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drivers/dma/iop-adma.c
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/* * offload engine driver for the Intel Xscale series of i/o processors * Copyright © 2006, Intel Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. * * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * * You should have received a copy of the GNU General Public License along with * this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. * */ /* * This driver supports the asynchrounous DMA copy and RAID engines available * on the Intel Xscale(R) family of I/O Processors (IOP 32x, 33x, 134x) */ #include <linux/init.h> #include <linux/module.h> |
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#include <linux/delay.h> #include <linux/dma-mapping.h> #include <linux/spinlock.h> #include <linux/interrupt.h> #include <linux/platform_device.h> #include <linux/memory.h> #include <linux/ioport.h> |
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#include <linux/raid/pq.h> |
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#include <mach/adma.h> |
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#define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common) #define to_iop_adma_device(dev) \ container_of(dev, struct iop_adma_device, common) #define tx_to_iop_adma_slot(tx) \ container_of(tx, struct iop_adma_desc_slot, async_tx) /** * iop_adma_free_slots - flags descriptor slots for reuse * @slot: Slot to free * Caller must hold &iop_chan->lock while calling this function */ static void iop_adma_free_slots(struct iop_adma_desc_slot *slot) { int stride = slot->slots_per_op; while (stride--) { slot->slots_per_op = 0; slot = list_entry(slot->slot_node.next, struct iop_adma_desc_slot, slot_node); } } |
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static void iop_desc_unmap(struct iop_adma_chan *iop_chan, struct iop_adma_desc_slot *desc) { struct dma_async_tx_descriptor *tx = &desc->async_tx; struct iop_adma_desc_slot *unmap = desc->group_head; struct device *dev = &iop_chan->device->pdev->dev; u32 len = unmap->unmap_len; enum dma_ctrl_flags flags = tx->flags; u32 src_cnt; dma_addr_t addr; dma_addr_t dest; src_cnt = unmap->unmap_src_cnt; dest = iop_desc_get_dest_addr(unmap, iop_chan); if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) { enum dma_data_direction dir; if (src_cnt > 1) /* is xor? */ dir = DMA_BIDIRECTIONAL; else dir = DMA_FROM_DEVICE; dma_unmap_page(dev, dest, len, dir); } if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { while (src_cnt--) { addr = iop_desc_get_src_addr(unmap, iop_chan, src_cnt); if (addr == dest) continue; dma_unmap_page(dev, addr, len, DMA_TO_DEVICE); } } desc->group_head = NULL; } static void iop_desc_unmap_pq(struct iop_adma_chan *iop_chan, struct iop_adma_desc_slot *desc) { struct dma_async_tx_descriptor *tx = &desc->async_tx; struct iop_adma_desc_slot *unmap = desc->group_head; struct device *dev = &iop_chan->device->pdev->dev; u32 len = unmap->unmap_len; enum dma_ctrl_flags flags = tx->flags; u32 src_cnt = unmap->unmap_src_cnt; dma_addr_t pdest = iop_desc_get_dest_addr(unmap, iop_chan); dma_addr_t qdest = iop_desc_get_qdest_addr(unmap, iop_chan); int i; if (tx->flags & DMA_PREP_CONTINUE) src_cnt -= 3; if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP) && !desc->pq_check_result) { dma_unmap_page(dev, pdest, len, DMA_BIDIRECTIONAL); dma_unmap_page(dev, qdest, len, DMA_BIDIRECTIONAL); } if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { dma_addr_t addr; for (i = 0; i < src_cnt; i++) { addr = iop_desc_get_src_addr(unmap, iop_chan, i); dma_unmap_page(dev, addr, len, DMA_TO_DEVICE); } if (desc->pq_check_result) { dma_unmap_page(dev, pdest, len, DMA_TO_DEVICE); dma_unmap_page(dev, qdest, len, DMA_TO_DEVICE); } } desc->group_head = NULL; } |
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static dma_cookie_t iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc, struct iop_adma_chan *iop_chan, dma_cookie_t cookie) { |
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struct dma_async_tx_descriptor *tx = &desc->async_tx; BUG_ON(tx->cookie < 0); if (tx->cookie > 0) { cookie = tx->cookie; tx->cookie = 0; |
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/* call the callback (must not sleep or submit new * operations to this channel) */ |
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if (tx->callback) tx->callback(tx->callback_param); |
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/* unmap dma addresses * (unmap_single vs unmap_page?) */ if (desc->group_head && desc->unmap_len) { |
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if (iop_desc_is_pq(desc)) iop_desc_unmap_pq(iop_chan, desc); else iop_desc_unmap(iop_chan, desc); |
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} } /* run dependent operations */ |
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dma_run_dependencies(tx); |
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return cookie; } static int iop_adma_clean_slot(struct iop_adma_desc_slot *desc, struct iop_adma_chan *iop_chan) { /* the client is allowed to attach dependent operations * until 'ack' is set */ |
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if (!async_tx_test_ack(&desc->async_tx)) |
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return 0; /* leave the last descriptor in the chain * so we can append to it */ if (desc->chain_node.next == &iop_chan->chain) return 1; dev_dbg(iop_chan->device->common.dev, "\tfree slot: %d slots_per_op: %d ", desc->idx, desc->slots_per_op); list_del(&desc->chain_node); iop_adma_free_slots(desc); return 0; } static void __iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan) { struct iop_adma_desc_slot *iter, *_iter, *grp_start = NULL; dma_cookie_t cookie = 0; u32 current_desc = iop_chan_get_current_descriptor(iop_chan); int busy = iop_chan_is_busy(iop_chan); int seen_current = 0, slot_cnt = 0, slots_per_op = 0; |
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dev_dbg(iop_chan->device->common.dev, "%s ", __func__); |
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/* free completed slots from the chain starting with * the oldest descriptor */ list_for_each_entry_safe(iter, _iter, &iop_chan->chain, chain_node) { pr_debug("\tcookie: %d slot: %d busy: %d " "this_desc: %#x next_desc: %#x ack: %d ", iter->async_tx.cookie, iter->idx, busy, iter->async_tx.phys, iop_desc_get_next_desc(iter), |
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async_tx_test_ack(&iter->async_tx)); |
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prefetch(_iter); prefetch(&_iter->async_tx); /* do not advance past the current descriptor loaded into the * hardware channel, subsequent descriptors are either in * process or have not been submitted */ if (seen_current) break; /* stop the search if we reach the current descriptor and the * channel is busy, or if it appears that the current descriptor * needs to be re-read (i.e. has been appended to) */ if (iter->async_tx.phys == current_desc) { BUG_ON(seen_current++); if (busy || iop_desc_get_next_desc(iter)) break; } /* detect the start of a group transaction */ if (!slot_cnt && !slots_per_op) { slot_cnt = iter->slot_cnt; slots_per_op = iter->slots_per_op; if (slot_cnt <= slots_per_op) { slot_cnt = 0; slots_per_op = 0; } } if (slot_cnt) { pr_debug("\tgroup++ "); if (!grp_start) grp_start = iter; slot_cnt -= slots_per_op; } /* all the members of a group are complete */ if (slots_per_op != 0 && slot_cnt == 0) { struct iop_adma_desc_slot *grp_iter, *_grp_iter; int end_of_chain = 0; pr_debug("\tgroup end "); /* collect the total results */ if (grp_start->xor_check_result) { u32 zero_sum_result = 0; slot_cnt = grp_start->slot_cnt; grp_iter = grp_start; list_for_each_entry_from(grp_iter, &iop_chan->chain, chain_node) { zero_sum_result |= iop_desc_get_zero_result(grp_iter); pr_debug("\titer%d result: %d ", grp_iter->idx, zero_sum_result); slot_cnt -= slots_per_op; if (slot_cnt == 0) break; } pr_debug("\tgrp_start->xor_check_result: %p ", grp_start->xor_check_result); *grp_start->xor_check_result = zero_sum_result; } /* clean up the group */ slot_cnt = grp_start->slot_cnt; grp_iter = grp_start; list_for_each_entry_safe_from(grp_iter, _grp_iter, &iop_chan->chain, chain_node) { cookie = iop_adma_run_tx_complete_actions( grp_iter, iop_chan, cookie); slot_cnt -= slots_per_op; end_of_chain = iop_adma_clean_slot(grp_iter, iop_chan); if (slot_cnt == 0 || end_of_chain) break; } /* the group should be complete at this point */ BUG_ON(slot_cnt); slots_per_op = 0; grp_start = NULL; if (end_of_chain) break; else continue; } else if (slots_per_op) /* wait for group completion */ continue; /* write back zero sum results (single descriptor case) */ if (iter->xor_check_result && iter->async_tx.cookie) *iter->xor_check_result = iop_desc_get_zero_result(iter); cookie = iop_adma_run_tx_complete_actions( iter, iop_chan, cookie); if (iop_adma_clean_slot(iter, iop_chan)) break; } |
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if (cookie > 0) { iop_chan->completed_cookie = cookie; pr_debug("\tcompleted cookie %d ", cookie); } } static void iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan) { spin_lock_bh(&iop_chan->lock); __iop_adma_slot_cleanup(iop_chan); spin_unlock_bh(&iop_chan->lock); } static void iop_adma_tasklet(unsigned long data) { |
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struct iop_adma_chan *iop_chan = (struct iop_adma_chan *) data; |
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/* lockdep will flag depedency submissions as potentially * recursive locking, this is not the case as a dependency * submission will never recurse a channels submit routine. * There are checks in async_tx.c to prevent this. */ spin_lock_nested(&iop_chan->lock, SINGLE_DEPTH_NESTING); |
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__iop_adma_slot_cleanup(iop_chan); spin_unlock(&iop_chan->lock); |
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} static struct iop_adma_desc_slot * iop_adma_alloc_slots(struct iop_adma_chan *iop_chan, int num_slots, int slots_per_op) { struct iop_adma_desc_slot *iter, *_iter, *alloc_start = NULL; |
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LIST_HEAD(chain); |
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int slots_found, retry = 0; /* start search from the last allocated descrtiptor * if a contiguous allocation can not be found start searching * from the beginning of the list */ retry: slots_found = 0; if (retry == 0) iter = iop_chan->last_used; else iter = list_entry(&iop_chan->all_slots, struct iop_adma_desc_slot, slot_node); list_for_each_entry_safe_continue( iter, _iter, &iop_chan->all_slots, slot_node) { prefetch(_iter); prefetch(&_iter->async_tx); if (iter->slots_per_op) { /* give up after finding the first busy slot * on the second pass through the list */ if (retry) break; slots_found = 0; continue; } /* start the allocation if the slot is correctly aligned */ if (!slots_found++) { if (iop_desc_is_aligned(iter, slots_per_op)) alloc_start = iter; else { slots_found = 0; continue; } } if (slots_found == num_slots) { struct iop_adma_desc_slot *alloc_tail = NULL; struct iop_adma_desc_slot *last_used = NULL; iter = alloc_start; while (num_slots) { int i; dev_dbg(iop_chan->device->common.dev, "allocated slot: %d " "(desc %p phys: %#x) slots_per_op %d ", iter->idx, iter->hw_desc, iter->async_tx.phys, slots_per_op); /* pre-ack all but the last descriptor */ if (num_slots != slots_per_op) |
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async_tx_ack(&iter->async_tx); |
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list_add_tail(&iter->chain_node, &chain); alloc_tail = iter; iter->async_tx.cookie = 0; iter->slot_cnt = num_slots; iter->xor_check_result = NULL; for (i = 0; i < slots_per_op; i++) { iter->slots_per_op = slots_per_op - i; last_used = iter; iter = list_entry(iter->slot_node.next, struct iop_adma_desc_slot, slot_node); } num_slots -= slots_per_op; } alloc_tail->group_head = alloc_start; alloc_tail->async_tx.cookie = -EBUSY; |
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list_splice(&chain, &alloc_tail->tx_list); |
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iop_chan->last_used = last_used; iop_desc_clear_next_desc(alloc_start); iop_desc_clear_next_desc(alloc_tail); return alloc_tail; } } if (!retry++) goto retry; |
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/* perform direct reclaim if the allocation fails */ __iop_adma_slot_cleanup(iop_chan); |
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return NULL; } static dma_cookie_t iop_desc_assign_cookie(struct iop_adma_chan *iop_chan, struct iop_adma_desc_slot *desc) { dma_cookie_t cookie = iop_chan->common.cookie; cookie++; if (cookie < 0) cookie = 1; iop_chan->common.cookie = desc->async_tx.cookie = cookie; return cookie; } static void iop_adma_check_threshold(struct iop_adma_chan *iop_chan) { dev_dbg(iop_chan->device->common.dev, "pending: %d ", iop_chan->pending); if (iop_chan->pending >= IOP_ADMA_THRESHOLD) { iop_chan->pending = 0; iop_chan_append(iop_chan); } } static dma_cookie_t iop_adma_tx_submit(struct dma_async_tx_descriptor *tx) { struct iop_adma_desc_slot *sw_desc = tx_to_iop_adma_slot(tx); struct iop_adma_chan *iop_chan = to_iop_adma_chan(tx->chan); struct iop_adma_desc_slot *grp_start, *old_chain_tail; int slot_cnt; int slots_per_op; dma_cookie_t cookie; |
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dma_addr_t next_dma; |
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grp_start = sw_desc->group_head; slot_cnt = grp_start->slot_cnt; slots_per_op = grp_start->slots_per_op; spin_lock_bh(&iop_chan->lock); cookie = iop_desc_assign_cookie(iop_chan, sw_desc); old_chain_tail = list_entry(iop_chan->chain.prev, struct iop_adma_desc_slot, chain_node); |
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list_splice_init(&sw_desc->tx_list, |
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&old_chain_tail->chain_node); /* fix up the hardware chain */ |
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next_dma = grp_start->async_tx.phys; iop_desc_set_next_desc(old_chain_tail, next_dma); BUG_ON(iop_desc_get_next_desc(old_chain_tail) != next_dma); /* flush */ |
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/* check for pre-chained descriptors */ |
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iop_paranoia(iop_desc_get_next_desc(sw_desc)); |
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/* increment the pending count by the number of slots * memcpy operations have a 1:1 (slot:operation) relation * other operations are heavier and will pop the threshold * more often. */ iop_chan->pending += slot_cnt; iop_adma_check_threshold(iop_chan); spin_unlock_bh(&iop_chan->lock); dev_dbg(iop_chan->device->common.dev, "%s cookie: %d slot: %d ", |
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__func__, sw_desc->async_tx.cookie, sw_desc->idx); |
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return cookie; } |
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static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan); static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan); |
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/** * iop_adma_alloc_chan_resources - returns the number of allocated descriptors * @chan - allocate descriptor resources for this channel * @client - current client requesting the channel be ready for requests * * Note: We keep the slots for 1 operation on iop_chan->chain at all times. To * avoid deadlock, via async_xor, num_descs_in_pool must at a minimum be * greater than 2x the number slots needed to satisfy a device->max_xor * request. * */ |
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static int iop_adma_alloc_chan_resources(struct dma_chan *chan) |
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{ char *hw_desc; int idx; struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); struct iop_adma_desc_slot *slot = NULL; int init = iop_chan->slots_allocated ? 0 : 1; struct iop_adma_platform_data *plat_data = iop_chan->device->pdev->dev.platform_data; int num_descs_in_pool = plat_data->pool_size/IOP_ADMA_SLOT_SIZE; /* Allocate descriptor slots */ do { idx = iop_chan->slots_allocated; if (idx == num_descs_in_pool) break; slot = kzalloc(sizeof(*slot), GFP_KERNEL); if (!slot) { printk(KERN_INFO "IOP ADMA Channel only initialized" " %d descriptor slots", idx); break; } hw_desc = (char *) iop_chan->device->dma_desc_pool_virt; slot->hw_desc = (void *) &hw_desc[idx * IOP_ADMA_SLOT_SIZE]; dma_async_tx_descriptor_init(&slot->async_tx, chan); slot->async_tx.tx_submit = iop_adma_tx_submit; |
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INIT_LIST_HEAD(&slot->tx_list); |
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INIT_LIST_HEAD(&slot->chain_node); INIT_LIST_HEAD(&slot->slot_node); |
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hw_desc = (char *) iop_chan->device->dma_desc_pool; slot->async_tx.phys = (dma_addr_t) &hw_desc[idx * IOP_ADMA_SLOT_SIZE]; slot->idx = idx; spin_lock_bh(&iop_chan->lock); iop_chan->slots_allocated++; list_add_tail(&slot->slot_node, &iop_chan->all_slots); spin_unlock_bh(&iop_chan->lock); } while (iop_chan->slots_allocated < num_descs_in_pool); if (idx && !iop_chan->last_used) iop_chan->last_used = list_entry(iop_chan->all_slots.next, struct iop_adma_desc_slot, slot_node); dev_dbg(iop_chan->device->common.dev, "allocated %d descriptor slots last_used: %p ", iop_chan->slots_allocated, iop_chan->last_used); /* initialize the channel and the chain with a null operation */ if (init) { if (dma_has_cap(DMA_MEMCPY, iop_chan->device->common.cap_mask)) iop_chan_start_null_memcpy(iop_chan); else if (dma_has_cap(DMA_XOR, iop_chan->device->common.cap_mask)) iop_chan_start_null_xor(iop_chan); else BUG(); } return (idx > 0) ? idx : -ENOMEM; } static struct dma_async_tx_descriptor * |
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iop_adma_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags) |
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{ struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); struct iop_adma_desc_slot *sw_desc, *grp_start; int slot_cnt, slots_per_op; |
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dev_dbg(iop_chan->device->common.dev, "%s ", __func__); |
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spin_lock_bh(&iop_chan->lock); slot_cnt = iop_chan_interrupt_slot_count(&slots_per_op, iop_chan); sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); if (sw_desc) { grp_start = sw_desc->group_head; iop_desc_init_interrupt(grp_start, iop_chan); grp_start->unmap_len = 0; |
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sw_desc->async_tx.flags = flags; |
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} spin_unlock_bh(&iop_chan->lock); return sw_desc ? &sw_desc->async_tx : NULL; } |
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static struct dma_async_tx_descriptor * |
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iop_adma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest, |
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dma_addr_t dma_src, size_t len, unsigned long flags) |
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{ struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); struct iop_adma_desc_slot *sw_desc, *grp_start; int slot_cnt, slots_per_op; if (unlikely(!len)) return NULL; BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT)); dev_dbg(iop_chan->device->common.dev, "%s len: %u ", |
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__func__, len); |
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spin_lock_bh(&iop_chan->lock); slot_cnt = iop_chan_memcpy_slot_count(len, &slots_per_op); sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); if (sw_desc) { grp_start = sw_desc->group_head; |
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iop_desc_init_memcpy(grp_start, flags); |
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iop_desc_set_byte_count(grp_start, iop_chan, len); |
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iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest); iop_desc_set_memcpy_src_addr(grp_start, dma_src); |
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sw_desc->unmap_src_cnt = 1; sw_desc->unmap_len = len; |
636bdeaa1 dmaengine: ack to... |
640 |
sw_desc->async_tx.flags = flags; |
c21109231 dmaengine: driver... |
641 642 643 644 645 646 647 |
} spin_unlock_bh(&iop_chan->lock); return sw_desc ? &sw_desc->async_tx : NULL; } static struct dma_async_tx_descriptor * |
0036731c8 async_tx: kill tx... |
648 |
iop_adma_prep_dma_memset(struct dma_chan *chan, dma_addr_t dma_dest, |
d4c56f97f async_tx: replace... |
649 |
int value, size_t len, unsigned long flags) |
c21109231 dmaengine: driver... |
650 651 652 653 654 655 656 657 658 659 660 |
{ struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); struct iop_adma_desc_slot *sw_desc, *grp_start; int slot_cnt, slots_per_op; if (unlikely(!len)) return NULL; BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT)); dev_dbg(iop_chan->device->common.dev, "%s len: %u ", |
3d9b525b6 iop-adma.c: repla... |
661 |
__func__, len); |
c21109231 dmaengine: driver... |
662 663 664 665 666 667 |
spin_lock_bh(&iop_chan->lock); slot_cnt = iop_chan_memset_slot_count(len, &slots_per_op); sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); if (sw_desc) { grp_start = sw_desc->group_head; |
d4c56f97f async_tx: replace... |
668 |
iop_desc_init_memset(grp_start, flags); |
c21109231 dmaengine: driver... |
669 670 |
iop_desc_set_byte_count(grp_start, iop_chan, len); iop_desc_set_block_fill_val(grp_start, value); |
0036731c8 async_tx: kill tx... |
671 |
iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest); |
c21109231 dmaengine: driver... |
672 673 |
sw_desc->unmap_src_cnt = 1; sw_desc->unmap_len = len; |
636bdeaa1 dmaengine: ack to... |
674 |
sw_desc->async_tx.flags = flags; |
c21109231 dmaengine: driver... |
675 676 677 678 679 |
} spin_unlock_bh(&iop_chan->lock); return sw_desc ? &sw_desc->async_tx : NULL; } |
c21109231 dmaengine: driver... |
680 |
static struct dma_async_tx_descriptor * |
0036731c8 async_tx: kill tx... |
681 682 |
iop_adma_prep_dma_xor(struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t *dma_src, unsigned int src_cnt, size_t len, |
d4c56f97f async_tx: replace... |
683 |
unsigned long flags) |
c21109231 dmaengine: driver... |
684 685 686 687 688 689 690 691 692 693 |
{ struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); struct iop_adma_desc_slot *sw_desc, *grp_start; int slot_cnt, slots_per_op; if (unlikely(!len)) return NULL; BUG_ON(unlikely(len > IOP_ADMA_XOR_MAX_BYTE_COUNT)); dev_dbg(iop_chan->device->common.dev, |
d4c56f97f async_tx: replace... |
694 695 |
"%s src_cnt: %d len: %u flags: %lx ", |
3d9b525b6 iop-adma.c: repla... |
696 |
__func__, src_cnt, len, flags); |
c21109231 dmaengine: driver... |
697 698 699 700 701 702 |
spin_lock_bh(&iop_chan->lock); slot_cnt = iop_chan_xor_slot_count(len, src_cnt, &slots_per_op); sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); if (sw_desc) { grp_start = sw_desc->group_head; |
d4c56f97f async_tx: replace... |
703 |
iop_desc_init_xor(grp_start, src_cnt, flags); |
c21109231 dmaengine: driver... |
704 |
iop_desc_set_byte_count(grp_start, iop_chan, len); |
0036731c8 async_tx: kill tx... |
705 |
iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest); |
c21109231 dmaengine: driver... |
706 707 |
sw_desc->unmap_src_cnt = src_cnt; sw_desc->unmap_len = len; |
636bdeaa1 dmaengine: ack to... |
708 |
sw_desc->async_tx.flags = flags; |
0036731c8 async_tx: kill tx... |
709 710 711 |
while (src_cnt--) iop_desc_set_xor_src_addr(grp_start, src_cnt, dma_src[src_cnt]); |
c21109231 dmaengine: driver... |
712 713 714 715 716 |
} spin_unlock_bh(&iop_chan->lock); return sw_desc ? &sw_desc->async_tx : NULL; } |
c21109231 dmaengine: driver... |
717 |
static struct dma_async_tx_descriptor * |
099f53cb5 async_tx: rename ... |
718 719 720 |
iop_adma_prep_dma_xor_val(struct dma_chan *chan, dma_addr_t *dma_src, unsigned int src_cnt, size_t len, u32 *result, unsigned long flags) |
c21109231 dmaengine: driver... |
721 722 723 724 725 726 727 728 729 730 |
{ struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); struct iop_adma_desc_slot *sw_desc, *grp_start; int slot_cnt, slots_per_op; if (unlikely(!len)) return NULL; dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u ", |
3d9b525b6 iop-adma.c: repla... |
731 |
__func__, src_cnt, len); |
c21109231 dmaengine: driver... |
732 733 734 735 736 737 |
spin_lock_bh(&iop_chan->lock); slot_cnt = iop_chan_zero_sum_slot_count(len, src_cnt, &slots_per_op); sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); if (sw_desc) { grp_start = sw_desc->group_head; |
d4c56f97f async_tx: replace... |
738 |
iop_desc_init_zero_sum(grp_start, src_cnt, flags); |
c21109231 dmaengine: driver... |
739 740 741 742 |
iop_desc_set_zero_sum_byte_count(grp_start, len); grp_start->xor_check_result = result; pr_debug("\t%s: grp_start->xor_check_result: %p ", |
3d9b525b6 iop-adma.c: repla... |
743 |
__func__, grp_start->xor_check_result); |
c21109231 dmaengine: driver... |
744 745 |
sw_desc->unmap_src_cnt = src_cnt; sw_desc->unmap_len = len; |
636bdeaa1 dmaengine: ack to... |
746 |
sw_desc->async_tx.flags = flags; |
0036731c8 async_tx: kill tx... |
747 748 749 |
while (src_cnt--) iop_desc_set_zero_sum_src_addr(grp_start, src_cnt, dma_src[src_cnt]); |
c21109231 dmaengine: driver... |
750 751 752 753 754 |
} spin_unlock_bh(&iop_chan->lock); return sw_desc ? &sw_desc->async_tx : NULL; } |
7bf649aee iop-adma: P+Q sup... |
755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 |
static struct dma_async_tx_descriptor * iop_adma_prep_dma_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, unsigned int src_cnt, const unsigned char *scf, size_t len, unsigned long flags) { struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); struct iop_adma_desc_slot *sw_desc, *g; int slot_cnt, slots_per_op; int continue_srcs; if (unlikely(!len)) return NULL; BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT); dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u flags: %lx ", __func__, src_cnt, len, flags); if (dmaf_p_disabled_continue(flags)) continue_srcs = 1+src_cnt; else if (dmaf_continue(flags)) continue_srcs = 3+src_cnt; else continue_srcs = 0+src_cnt; spin_lock_bh(&iop_chan->lock); slot_cnt = iop_chan_pq_slot_count(len, continue_srcs, &slots_per_op); sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); if (sw_desc) { int i; g = sw_desc->group_head; iop_desc_set_byte_count(g, iop_chan, len); /* even if P is disabled its destination address (bits * [3:0]) must match Q. It is ok if P points to an * invalid address, it won't be written. */ if (flags & DMA_PREP_PQ_DISABLE_P) dst[0] = dst[1] & 0x7; iop_desc_set_pq_addr(g, dst); sw_desc->unmap_src_cnt = src_cnt; sw_desc->unmap_len = len; sw_desc->async_tx.flags = flags; for (i = 0; i < src_cnt; i++) iop_desc_set_pq_src_addr(g, i, src[i], scf[i]); /* if we are continuing a previous operation factor in * the old p and q values, see the comment for dma_maxpq * in include/linux/dmaengine.h */ if (dmaf_p_disabled_continue(flags)) iop_desc_set_pq_src_addr(g, i++, dst[1], 1); else if (dmaf_continue(flags)) { iop_desc_set_pq_src_addr(g, i++, dst[0], 0); iop_desc_set_pq_src_addr(g, i++, dst[1], 1); iop_desc_set_pq_src_addr(g, i++, dst[1], 0); } iop_desc_init_pq(g, i, flags); } spin_unlock_bh(&iop_chan->lock); return sw_desc ? &sw_desc->async_tx : NULL; } static struct dma_async_tx_descriptor * iop_adma_prep_dma_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, unsigned int src_cnt, const unsigned char *scf, size_t len, enum sum_check_flags *pqres, unsigned long flags) { struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); struct iop_adma_desc_slot *sw_desc, *g; int slot_cnt, slots_per_op; if (unlikely(!len)) return NULL; BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT); dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u ", __func__, src_cnt, len); spin_lock_bh(&iop_chan->lock); slot_cnt = iop_chan_pq_zero_sum_slot_count(len, src_cnt + 2, &slots_per_op); sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); if (sw_desc) { /* for validate operations p and q are tagged onto the * end of the source list */ int pq_idx = src_cnt; g = sw_desc->group_head; iop_desc_init_pq_zero_sum(g, src_cnt+2, flags); iop_desc_set_pq_zero_sum_byte_count(g, len); g->pq_check_result = pqres; pr_debug("\t%s: g->pq_check_result: %p ", __func__, g->pq_check_result); sw_desc->unmap_src_cnt = src_cnt+2; sw_desc->unmap_len = len; sw_desc->async_tx.flags = flags; while (src_cnt--) iop_desc_set_pq_zero_sum_src_addr(g, src_cnt, src[src_cnt], scf[src_cnt]); iop_desc_set_pq_zero_sum_addr(g, pq_idx, src); } spin_unlock_bh(&iop_chan->lock); return sw_desc ? &sw_desc->async_tx : NULL; } |
c21109231 dmaengine: driver... |
869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 |
static void iop_adma_free_chan_resources(struct dma_chan *chan) { struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); struct iop_adma_desc_slot *iter, *_iter; int in_use_descs = 0; iop_adma_slot_cleanup(iop_chan); spin_lock_bh(&iop_chan->lock); list_for_each_entry_safe(iter, _iter, &iop_chan->chain, chain_node) { in_use_descs++; list_del(&iter->chain_node); } list_for_each_entry_safe_reverse( iter, _iter, &iop_chan->all_slots, slot_node) { list_del(&iter->slot_node); kfree(iter); iop_chan->slots_allocated--; } iop_chan->last_used = NULL; dev_dbg(iop_chan->device->common.dev, "%s slots_allocated %d ", |
3d9b525b6 iop-adma.c: repla... |
893 |
__func__, iop_chan->slots_allocated); |
c21109231 dmaengine: driver... |
894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 |
spin_unlock_bh(&iop_chan->lock); /* one is ok since we left it on there on purpose */ if (in_use_descs > 1) printk(KERN_ERR "IOP: Freeing %d in use descriptors! ", in_use_descs - 1); } /** * iop_adma_is_complete - poll the status of an ADMA transaction * @chan: ADMA channel handle * @cookie: ADMA transaction identifier */ static enum dma_status iop_adma_is_complete(struct dma_chan *chan, dma_cookie_t cookie, dma_cookie_t *done, dma_cookie_t *used) { struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); dma_cookie_t last_used; dma_cookie_t last_complete; enum dma_status ret; last_used = chan->cookie; last_complete = iop_chan->completed_cookie; if (done) *done = last_complete; if (used) *used = last_used; ret = dma_async_is_complete(cookie, last_complete, last_used); if (ret == DMA_SUCCESS) return ret; iop_adma_slot_cleanup(iop_chan); last_used = chan->cookie; last_complete = iop_chan->completed_cookie; if (done) *done = last_complete; if (used) *used = last_used; return dma_async_is_complete(cookie, last_complete, last_used); } static irqreturn_t iop_adma_eot_handler(int irq, void *data) { struct iop_adma_chan *chan = data; |
3d9b525b6 iop-adma.c: repla... |
946 947 |
dev_dbg(chan->device->common.dev, "%s ", __func__); |
c21109231 dmaengine: driver... |
948 949 950 951 952 953 954 955 956 957 958 |
tasklet_schedule(&chan->irq_tasklet); iop_adma_device_clear_eot_status(chan); return IRQ_HANDLED; } static irqreturn_t iop_adma_eoc_handler(int irq, void *data) { struct iop_adma_chan *chan = data; |
3d9b525b6 iop-adma.c: repla... |
959 960 |
dev_dbg(chan->device->common.dev, "%s ", __func__); |
c21109231 dmaengine: driver... |
961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 |
tasklet_schedule(&chan->irq_tasklet); iop_adma_device_clear_eoc_status(chan); return IRQ_HANDLED; } static irqreturn_t iop_adma_err_handler(int irq, void *data) { struct iop_adma_chan *chan = data; unsigned long status = iop_chan_get_status(chan); dev_printk(KERN_ERR, chan->device->common.dev, "error ( %s%s%s%s%s%s%s) ", iop_is_err_int_parity(status, chan) ? "int_parity " : "", iop_is_err_mcu_abort(status, chan) ? "mcu_abort " : "", iop_is_err_int_tabort(status, chan) ? "int_tabort " : "", iop_is_err_int_mabort(status, chan) ? "int_mabort " : "", iop_is_err_pci_tabort(status, chan) ? "pci_tabort " : "", iop_is_err_pci_mabort(status, chan) ? "pci_mabort " : "", iop_is_err_split_tx(status, chan) ? "split_tx " : ""); iop_adma_device_clear_err_status(chan); BUG(); return IRQ_HANDLED; } static void iop_adma_issue_pending(struct dma_chan *chan) { struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); if (iop_chan->pending) { iop_chan->pending = 0; iop_chan_append(iop_chan); } } /* * Perform a transaction to verify the HW works. */ #define IOP_ADMA_TEST_SIZE 2000 static int __devinit iop_adma_memcpy_self_test(struct iop_adma_device *device) { int i; void *src, *dest; dma_addr_t src_dma, dest_dma; struct dma_chan *dma_chan; dma_cookie_t cookie; struct dma_async_tx_descriptor *tx; int err = 0; struct iop_adma_chan *iop_chan; |
3d9b525b6 iop-adma.c: repla... |
1017 1018 |
dev_dbg(device->common.dev, "%s ", __func__); |
c21109231 dmaengine: driver... |
1019 |
|
eccf2144e iop-adma: fixup s... |
1020 |
src = kmalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL); |
c21109231 dmaengine: driver... |
1021 1022 |
if (!src) return -ENOMEM; |
eccf2144e iop-adma: fixup s... |
1023 |
dest = kzalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL); |
c21109231 dmaengine: driver... |
1024 1025 1026 1027 1028 1029 1030 1031 |
if (!dest) { kfree(src); return -ENOMEM; } /* Fill in src buffer */ for (i = 0; i < IOP_ADMA_TEST_SIZE; i++) ((u8 *) src)[i] = (u8)i; |
c21109231 dmaengine: driver... |
1032 1033 1034 1035 |
/* Start copy, using first DMA channel */ dma_chan = container_of(device->common.channels.next, struct dma_chan, device_node); |
aa1e6f1a3 dmaengine: kill s... |
1036 |
if (iop_adma_alloc_chan_resources(dma_chan) < 1) { |
c21109231 dmaengine: driver... |
1037 1038 1039 |
err = -ENODEV; goto out; } |
c21109231 dmaengine: driver... |
1040 1041 |
dest_dma = dma_map_single(dma_chan->device->dev, dest, IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE); |
c21109231 dmaengine: driver... |
1042 1043 |
src_dma = dma_map_single(dma_chan->device->dev, src, IOP_ADMA_TEST_SIZE, DMA_TO_DEVICE); |
0036731c8 async_tx: kill tx... |
1044 |
tx = iop_adma_prep_dma_memcpy(dma_chan, dest_dma, src_dma, |
636bdeaa1 dmaengine: ack to... |
1045 1046 |
IOP_ADMA_TEST_SIZE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
c21109231 dmaengine: driver... |
1047 1048 1049 |
cookie = iop_adma_tx_submit(tx); iop_adma_issue_pending(dma_chan); |
c21109231 dmaengine: driver... |
1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 |
msleep(1); if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { dev_printk(KERN_ERR, dma_chan->device->dev, "Self-test copy timed out, disabling "); err = -ENODEV; goto free_resources; } iop_chan = to_iop_adma_chan(dma_chan); dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma, IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE); if (memcmp(src, dest, IOP_ADMA_TEST_SIZE)) { dev_printk(KERN_ERR, dma_chan->device->dev, "Self-test copy failed compare, disabling "); err = -ENODEV; goto free_resources; } free_resources: iop_adma_free_chan_resources(dma_chan); out: kfree(src); kfree(dest); return err; } #define IOP_ADMA_NUM_SRC_TEST 4 /* must be <= 15 */ static int __devinit |
099f53cb5 async_tx: rename ... |
1082 |
iop_adma_xor_val_self_test(struct iop_adma_device *device) |
c21109231 dmaengine: driver... |
1083 1084 1085 1086 1087 |
{ int i, src_idx; struct page *dest; struct page *xor_srcs[IOP_ADMA_NUM_SRC_TEST]; struct page *zero_sum_srcs[IOP_ADMA_NUM_SRC_TEST + 1]; |
0036731c8 async_tx: kill tx... |
1088 |
dma_addr_t dma_srcs[IOP_ADMA_NUM_SRC_TEST + 1]; |
c21109231 dmaengine: driver... |
1089 1090 1091 1092 1093 1094 1095 1096 1097 |
dma_addr_t dma_addr, dest_dma; struct dma_async_tx_descriptor *tx; struct dma_chan *dma_chan; dma_cookie_t cookie; u8 cmp_byte = 0; u32 cmp_word; u32 zero_sum_result; int err = 0; struct iop_adma_chan *iop_chan; |
3d9b525b6 iop-adma.c: repla... |
1098 1099 |
dev_dbg(device->common.dev, "%s ", __func__); |
c21109231 dmaengine: driver... |
1100 1101 1102 |
for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) { xor_srcs[src_idx] = alloc_page(GFP_KERNEL); |
a09b09ae5 iop-adma, mv_xor:... |
1103 1104 |
if (!xor_srcs[src_idx]) { while (src_idx--) |
c21109231 dmaengine: driver... |
1105 |
__free_page(xor_srcs[src_idx]); |
a09b09ae5 iop-adma, mv_xor:... |
1106 1107 |
return -ENOMEM; } |
c21109231 dmaengine: driver... |
1108 1109 1110 |
} dest = alloc_page(GFP_KERNEL); |
a09b09ae5 iop-adma, mv_xor:... |
1111 1112 |
if (!dest) { while (src_idx--) |
c21109231 dmaengine: driver... |
1113 |
__free_page(xor_srcs[src_idx]); |
a09b09ae5 iop-adma, mv_xor:... |
1114 1115 |
return -ENOMEM; } |
c21109231 dmaengine: driver... |
1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 |
/* Fill in src buffers */ for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) { u8 *ptr = page_address(xor_srcs[src_idx]); for (i = 0; i < PAGE_SIZE; i++) ptr[i] = (1 << src_idx); } for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) cmp_byte ^= (u8) (1 << src_idx); cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | (cmp_byte << 8) | cmp_byte; memset(page_address(dest), 0, PAGE_SIZE); dma_chan = container_of(device->common.channels.next, struct dma_chan, device_node); |
aa1e6f1a3 dmaengine: kill s... |
1135 |
if (iop_adma_alloc_chan_resources(dma_chan) < 1) { |
c21109231 dmaengine: driver... |
1136 1137 1138 1139 1140 |
err = -ENODEV; goto out; } /* test xor */ |
c21109231 dmaengine: driver... |
1141 1142 |
dest_dma = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE); |
0036731c8 async_tx: kill tx... |
1143 1144 1145 1146 |
for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++) dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i], 0, PAGE_SIZE, DMA_TO_DEVICE); tx = iop_adma_prep_dma_xor(dma_chan, dest_dma, dma_srcs, |
636bdeaa1 dmaengine: ack to... |
1147 1148 |
IOP_ADMA_NUM_SRC_TEST, PAGE_SIZE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
c21109231 dmaengine: driver... |
1149 1150 1151 |
cookie = iop_adma_tx_submit(tx); iop_adma_issue_pending(dma_chan); |
c21109231 dmaengine: driver... |
1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 |
msleep(8); if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { dev_printk(KERN_ERR, dma_chan->device->dev, "Self-test xor timed out, disabling "); err = -ENODEV; goto free_resources; } iop_chan = to_iop_adma_chan(dma_chan); dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { u32 *ptr = page_address(dest); if (ptr[i] != cmp_word) { dev_printk(KERN_ERR, dma_chan->device->dev, "Self-test xor failed compare, disabling "); err = -ENODEV; goto free_resources; } } dma_sync_single_for_device(&iop_chan->device->pdev->dev, dest_dma, PAGE_SIZE, DMA_TO_DEVICE); /* skip zero sum if the capability is not present */ |
099f53cb5 async_tx: rename ... |
1180 |
if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask)) |
c21109231 dmaengine: driver... |
1181 1182 1183 1184 1185 1186 1187 1188 |
goto free_resources; /* zero sum the sources with the destintation page */ for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++) zero_sum_srcs[i] = xor_srcs[i]; zero_sum_srcs[i] = dest; zero_sum_result = 1; |
0036731c8 async_tx: kill tx... |
1189 1190 1191 1192 |
for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++) dma_srcs[i] = dma_map_page(dma_chan->device->dev, zero_sum_srcs[i], 0, PAGE_SIZE, DMA_TO_DEVICE); |
099f53cb5 async_tx: rename ... |
1193 1194 1195 1196 |
tx = iop_adma_prep_dma_xor_val(dma_chan, dma_srcs, IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE, &zero_sum_result, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
c21109231 dmaengine: driver... |
1197 1198 1199 |
cookie = iop_adma_tx_submit(tx); iop_adma_issue_pending(dma_chan); |
c21109231 dmaengine: driver... |
1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 |
msleep(8); if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { dev_printk(KERN_ERR, dma_chan->device->dev, "Self-test zero sum timed out, disabling "); err = -ENODEV; goto free_resources; } if (zero_sum_result != 0) { dev_printk(KERN_ERR, dma_chan->device->dev, "Self-test zero sum failed compare, disabling "); err = -ENODEV; goto free_resources; } /* test memset */ |
c21109231 dmaengine: driver... |
1219 1220 |
dma_addr = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE); |
636bdeaa1 dmaengine: ack to... |
1221 1222 |
tx = iop_adma_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
c21109231 dmaengine: driver... |
1223 1224 1225 |
cookie = iop_adma_tx_submit(tx); iop_adma_issue_pending(dma_chan); |
c21109231 dmaengine: driver... |
1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 |
msleep(8); if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { dev_printk(KERN_ERR, dma_chan->device->dev, "Self-test memset timed out, disabling "); err = -ENODEV; goto free_resources; } for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) { u32 *ptr = page_address(dest); if (ptr[i]) { dev_printk(KERN_ERR, dma_chan->device->dev, "Self-test memset failed compare, disabling "); err = -ENODEV; goto free_resources; } } /* test for non-zero parity sum */ zero_sum_result = 0; |
0036731c8 async_tx: kill tx... |
1249 1250 1251 1252 |
for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++) dma_srcs[i] = dma_map_page(dma_chan->device->dev, zero_sum_srcs[i], 0, PAGE_SIZE, DMA_TO_DEVICE); |
099f53cb5 async_tx: rename ... |
1253 1254 1255 1256 |
tx = iop_adma_prep_dma_xor_val(dma_chan, dma_srcs, IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE, &zero_sum_result, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
c21109231 dmaengine: driver... |
1257 1258 1259 |
cookie = iop_adma_tx_submit(tx); iop_adma_issue_pending(dma_chan); |
c21109231 dmaengine: driver... |
1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 |
msleep(8); if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { dev_printk(KERN_ERR, dma_chan->device->dev, "Self-test non-zero sum timed out, disabling "); err = -ENODEV; goto free_resources; } if (zero_sum_result != 1) { dev_printk(KERN_ERR, dma_chan->device->dev, "Self-test non-zero sum failed compare, disabling "); err = -ENODEV; goto free_resources; } free_resources: iop_adma_free_chan_resources(dma_chan); out: src_idx = IOP_ADMA_NUM_SRC_TEST; while (src_idx--) __free_page(xor_srcs[src_idx]); __free_page(dest); return err; } |
f6dbf6516 iop-adma: P+Q sel... |
1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 |
#ifdef CONFIG_MD_RAID6_PQ static int __devinit iop_adma_pq_zero_sum_self_test(struct iop_adma_device *device) { /* combined sources, software pq results, and extra hw pq results */ struct page *pq[IOP_ADMA_NUM_SRC_TEST+2+2]; /* ptr to the extra hw pq buffers defined above */ struct page **pq_hw = &pq[IOP_ADMA_NUM_SRC_TEST+2]; /* address conversion buffers (dma_map / page_address) */ void *pq_sw[IOP_ADMA_NUM_SRC_TEST+2]; dma_addr_t pq_src[IOP_ADMA_NUM_SRC_TEST]; dma_addr_t pq_dest[2]; int i; struct dma_async_tx_descriptor *tx; struct dma_chan *dma_chan; dma_cookie_t cookie; u32 zero_sum_result; int err = 0; struct device *dev; dev_dbg(device->common.dev, "%s ", __func__); for (i = 0; i < ARRAY_SIZE(pq); i++) { pq[i] = alloc_page(GFP_KERNEL); if (!pq[i]) { while (i--) __free_page(pq[i]); return -ENOMEM; } } /* Fill in src buffers */ for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++) { pq_sw[i] = page_address(pq[i]); memset(pq_sw[i], 0x11111111 * (1<<i), PAGE_SIZE); } pq_sw[i] = page_address(pq[i]); pq_sw[i+1] = page_address(pq[i+1]); dma_chan = container_of(device->common.channels.next, struct dma_chan, device_node); if (iop_adma_alloc_chan_resources(dma_chan) < 1) { err = -ENODEV; goto out; } dev = dma_chan->device->dev; /* initialize the dests */ memset(page_address(pq_hw[0]), 0 , PAGE_SIZE); memset(page_address(pq_hw[1]), 0 , PAGE_SIZE); /* test pq */ pq_dest[0] = dma_map_page(dev, pq_hw[0], 0, PAGE_SIZE, DMA_FROM_DEVICE); pq_dest[1] = dma_map_page(dev, pq_hw[1], 0, PAGE_SIZE, DMA_FROM_DEVICE); for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++) pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE, DMA_TO_DEVICE); tx = iop_adma_prep_dma_pq(dma_chan, pq_dest, pq_src, IOP_ADMA_NUM_SRC_TEST, (u8 *)raid6_gfexp, PAGE_SIZE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); cookie = iop_adma_tx_submit(tx); iop_adma_issue_pending(dma_chan); msleep(8); if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { dev_err(dev, "Self-test pq timed out, disabling "); err = -ENODEV; goto free_resources; } raid6_call.gen_syndrome(IOP_ADMA_NUM_SRC_TEST+2, PAGE_SIZE, pq_sw); if (memcmp(pq_sw[IOP_ADMA_NUM_SRC_TEST], page_address(pq_hw[0]), PAGE_SIZE) != 0) { dev_err(dev, "Self-test p failed compare, disabling "); err = -ENODEV; goto free_resources; } if (memcmp(pq_sw[IOP_ADMA_NUM_SRC_TEST+1], page_address(pq_hw[1]), PAGE_SIZE) != 0) { dev_err(dev, "Self-test q failed compare, disabling "); err = -ENODEV; goto free_resources; } /* test correct zero sum using the software generated pq values */ for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 2; i++) pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE, DMA_TO_DEVICE); zero_sum_result = ~0; tx = iop_adma_prep_dma_pq_val(dma_chan, &pq_src[IOP_ADMA_NUM_SRC_TEST], pq_src, IOP_ADMA_NUM_SRC_TEST, raid6_gfexp, PAGE_SIZE, &zero_sum_result, DMA_PREP_INTERRUPT|DMA_CTRL_ACK); cookie = iop_adma_tx_submit(tx); iop_adma_issue_pending(dma_chan); msleep(8); if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { dev_err(dev, "Self-test pq-zero-sum timed out, disabling "); err = -ENODEV; goto free_resources; } if (zero_sum_result != 0) { dev_err(dev, "Self-test pq-zero-sum failed to validate: %x ", zero_sum_result); err = -ENODEV; goto free_resources; } /* test incorrect zero sum */ i = IOP_ADMA_NUM_SRC_TEST; memset(pq_sw[i] + 100, 0, 100); memset(pq_sw[i+1] + 200, 0, 200); for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 2; i++) pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE, DMA_TO_DEVICE); zero_sum_result = 0; tx = iop_adma_prep_dma_pq_val(dma_chan, &pq_src[IOP_ADMA_NUM_SRC_TEST], pq_src, IOP_ADMA_NUM_SRC_TEST, raid6_gfexp, PAGE_SIZE, &zero_sum_result, DMA_PREP_INTERRUPT|DMA_CTRL_ACK); cookie = iop_adma_tx_submit(tx); iop_adma_issue_pending(dma_chan); msleep(8); if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { dev_err(dev, "Self-test !pq-zero-sum timed out, disabling "); err = -ENODEV; goto free_resources; } if (zero_sum_result != (SUM_CHECK_P_RESULT | SUM_CHECK_Q_RESULT)) { dev_err(dev, "Self-test !pq-zero-sum failed to validate: %x ", zero_sum_result); err = -ENODEV; goto free_resources; } free_resources: iop_adma_free_chan_resources(dma_chan); out: i = ARRAY_SIZE(pq); while (i--) __free_page(pq[i]); return err; } #endif |
c21109231 dmaengine: driver... |
1458 1459 1460 1461 1462 |
static int __devexit iop_adma_remove(struct platform_device *dev) { struct iop_adma_device *device = platform_get_drvdata(dev); struct dma_chan *chan, *_chan; struct iop_adma_chan *iop_chan; |
c21109231 dmaengine: driver... |
1463 1464 1465 |
struct iop_adma_platform_data *plat_data = dev->dev.platform_data; dma_async_device_unregister(&device->common); |
c21109231 dmaengine: driver... |
1466 1467 |
dma_free_coherent(&dev->dev, plat_data->pool_size, device->dma_desc_pool_virt, device->dma_desc_pool); |
c21109231 dmaengine: driver... |
1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 |
list_for_each_entry_safe(chan, _chan, &device->common.channels, device_node) { iop_chan = to_iop_adma_chan(chan); list_del(&chan->device_node); kfree(iop_chan); } kfree(device); return 0; } static int __devinit iop_adma_probe(struct platform_device *pdev) { struct resource *res; int ret = 0, i; struct iop_adma_device *adev; struct iop_adma_chan *iop_chan; struct dma_device *dma_dev; struct iop_adma_platform_data *plat_data = pdev->dev.platform_data; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) return -ENODEV; if (!devm_request_mem_region(&pdev->dev, res->start, |
2e032b62c iop-adma.c: use r... |
1493 |
resource_size(res), pdev->name)) |
c21109231 dmaengine: driver... |
1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 |
return -EBUSY; adev = kzalloc(sizeof(*adev), GFP_KERNEL); if (!adev) return -ENOMEM; dma_dev = &adev->common; /* allocate coherent memory for hardware descriptors * note: writecombine gives slightly better performance, but * requires that we explicitly flush the writes */ if ((adev->dma_desc_pool_virt = dma_alloc_writecombine(&pdev->dev, plat_data->pool_size, &adev->dma_desc_pool, GFP_KERNEL)) == NULL) { ret = -ENOMEM; goto err_free_adev; } dev_dbg(&pdev->dev, "%s: allocted descriptor pool virt %p phys %p ", |
3d9b525b6 iop-adma.c: repla... |
1515 |
__func__, adev->dma_desc_pool_virt, |
c21109231 dmaengine: driver... |
1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 |
(void *) adev->dma_desc_pool); adev->id = plat_data->hw_id; /* discover transaction capabilites from the platform data */ dma_dev->cap_mask = plat_data->cap_mask; adev->pdev = pdev; platform_set_drvdata(pdev, adev); INIT_LIST_HEAD(&dma_dev->channels); /* set base routines */ dma_dev->device_alloc_chan_resources = iop_adma_alloc_chan_resources; dma_dev->device_free_chan_resources = iop_adma_free_chan_resources; dma_dev->device_is_tx_complete = iop_adma_is_complete; dma_dev->device_issue_pending = iop_adma_issue_pending; |
c21109231 dmaengine: driver... |
1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 |
dma_dev->dev = &pdev->dev; /* set prep routines based on capability */ if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) dma_dev->device_prep_dma_memcpy = iop_adma_prep_dma_memcpy; if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) dma_dev->device_prep_dma_memset = iop_adma_prep_dma_memset; if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { dma_dev->max_xor = iop_adma_get_max_xor(); dma_dev->device_prep_dma_xor = iop_adma_prep_dma_xor; } |
099f53cb5 async_tx: rename ... |
1544 1545 1546 |
if (dma_has_cap(DMA_XOR_VAL, dma_dev->cap_mask)) dma_dev->device_prep_dma_xor_val = iop_adma_prep_dma_xor_val; |
7bf649aee iop-adma: P+Q sup... |
1547 1548 1549 1550 1551 1552 1553 |
if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) { dma_set_maxpq(dma_dev, iop_adma_get_max_pq(), 0); dma_dev->device_prep_dma_pq = iop_adma_prep_dma_pq; } if (dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask)) dma_dev->device_prep_dma_pq_val = iop_adma_prep_dma_pq_val; |
c21109231 dmaengine: driver... |
1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 |
if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask)) dma_dev->device_prep_dma_interrupt = iop_adma_prep_dma_interrupt; iop_chan = kzalloc(sizeof(*iop_chan), GFP_KERNEL); if (!iop_chan) { ret = -ENOMEM; goto err_free_dma; } iop_chan->device = adev; iop_chan->mmr_base = devm_ioremap(&pdev->dev, res->start, |
2e032b62c iop-adma.c: use r... |
1566 |
resource_size(res)); |
c21109231 dmaengine: driver... |
1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 |
if (!iop_chan->mmr_base) { ret = -ENOMEM; goto err_free_iop_chan; } tasklet_init(&iop_chan->irq_tasklet, iop_adma_tasklet, (unsigned long) iop_chan); /* clear errors before enabling interrupts */ iop_adma_device_clear_err_status(iop_chan); for (i = 0; i < 3; i++) { irq_handler_t handler[] = { iop_adma_eot_handler, iop_adma_eoc_handler, iop_adma_err_handler }; int irq = platform_get_irq(pdev, i); if (irq < 0) { ret = -ENXIO; goto err_free_iop_chan; } else { ret = devm_request_irq(&pdev->dev, irq, handler[i], 0, pdev->name, iop_chan); if (ret) goto err_free_iop_chan; } } spin_lock_init(&iop_chan->lock); |
c21109231 dmaengine: driver... |
1594 1595 |
INIT_LIST_HEAD(&iop_chan->chain); INIT_LIST_HEAD(&iop_chan->all_slots); |
c21109231 dmaengine: driver... |
1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 |
iop_chan->common.device = dma_dev; list_add_tail(&iop_chan->common.device_node, &dma_dev->channels); if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) { ret = iop_adma_memcpy_self_test(adev); dev_dbg(&pdev->dev, "memcpy self test returned %d ", ret); if (ret) goto err_free_iop_chan; } if (dma_has_cap(DMA_XOR, dma_dev->cap_mask) || |
f6dbf6516 iop-adma: P+Q sel... |
1608 |
dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) { |
099f53cb5 async_tx: rename ... |
1609 |
ret = iop_adma_xor_val_self_test(adev); |
c21109231 dmaengine: driver... |
1610 1611 1612 1613 1614 |
dev_dbg(&pdev->dev, "xor self test returned %d ", ret); if (ret) goto err_free_iop_chan; } |
f6dbf6516 iop-adma: P+Q sel... |
1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 |
if (dma_has_cap(DMA_PQ, dma_dev->cap_mask) && dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask)) { #ifdef CONFIG_MD_RAID6_PQ ret = iop_adma_pq_zero_sum_self_test(adev); dev_dbg(&pdev->dev, "pq self test returned %d ", ret); #else /* can not test raid6, so do not publish capability */ dma_cap_clear(DMA_PQ, dma_dev->cap_mask); dma_cap_clear(DMA_PQ_VAL, dma_dev->cap_mask); ret = 0; #endif if (ret) goto err_free_iop_chan; } |
c21109231 dmaengine: driver... |
1630 |
dev_printk(KERN_INFO, &pdev->dev, "Intel(R) IOP: " |
9308add6e dmaengine: cleanu... |
1631 1632 |
"( %s%s%s%s%s%s%s) ", |
b2f46fd8e async_tx: add sup... |
1633 |
dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "pq " : "", |
099f53cb5 async_tx: rename ... |
1634 |
dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask) ? "pq_val " : "", |
c21109231 dmaengine: driver... |
1635 |
dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "", |
099f53cb5 async_tx: rename ... |
1636 |
dma_has_cap(DMA_XOR_VAL, dma_dev->cap_mask) ? "xor_val " : "", |
c21109231 dmaengine: driver... |
1637 |
dma_has_cap(DMA_MEMSET, dma_dev->cap_mask) ? "fill " : "", |
c21109231 dmaengine: driver... |
1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 |
dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "", dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : ""); dma_async_device_register(dma_dev); goto out; err_free_iop_chan: kfree(iop_chan); err_free_dma: dma_free_coherent(&adev->pdev->dev, plat_data->pool_size, adev->dma_desc_pool_virt, adev->dma_desc_pool); err_free_adev: kfree(adev); out: return ret; } static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan) { struct iop_adma_desc_slot *sw_desc, *grp_start; dma_cookie_t cookie; int slot_cnt, slots_per_op; |
3d9b525b6 iop-adma.c: repla... |
1660 1661 |
dev_dbg(iop_chan->device->common.dev, "%s ", __func__); |
c21109231 dmaengine: driver... |
1662 1663 1664 1665 1666 1667 |
spin_lock_bh(&iop_chan->lock); slot_cnt = iop_chan_memcpy_slot_count(0, &slots_per_op); sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); if (sw_desc) { grp_start = sw_desc->group_head; |
308136d1a iop-adma: impleme... |
1668 |
list_splice_init(&sw_desc->tx_list, &iop_chan->chain); |
636bdeaa1 dmaengine: ack to... |
1669 |
async_tx_ack(&sw_desc->async_tx); |
c21109231 dmaengine: driver... |
1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 |
iop_desc_init_memcpy(grp_start, 0); iop_desc_set_byte_count(grp_start, iop_chan, 0); iop_desc_set_dest_addr(grp_start, iop_chan, 0); iop_desc_set_memcpy_src_addr(grp_start, 0); cookie = iop_chan->common.cookie; cookie++; if (cookie <= 1) cookie = 2; /* initialize the completed cookie to be less than * the most recently used cookie */ iop_chan->completed_cookie = cookie - 1; iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie; /* channel should not be busy */ BUG_ON(iop_chan_is_busy(iop_chan)); /* clear any prior error-status bits */ iop_adma_device_clear_err_status(iop_chan); /* disable operation */ iop_chan_disable(iop_chan); /* set the descriptor address */ iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys); /* 1/ don't add pre-chained descriptors * 2/ dummy read to flush next_desc write */ BUG_ON(iop_desc_get_next_desc(sw_desc)); /* run the descriptor */ iop_chan_enable(iop_chan); } else dev_printk(KERN_ERR, iop_chan->device->common.dev, "failed to allocate null descriptor "); spin_unlock_bh(&iop_chan->lock); } static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan) { struct iop_adma_desc_slot *sw_desc, *grp_start; dma_cookie_t cookie; int slot_cnt, slots_per_op; |
3d9b525b6 iop-adma.c: repla... |
1717 1718 |
dev_dbg(iop_chan->device->common.dev, "%s ", __func__); |
c21109231 dmaengine: driver... |
1719 1720 1721 1722 1723 1724 |
spin_lock_bh(&iop_chan->lock); slot_cnt = iop_chan_xor_slot_count(0, 2, &slots_per_op); sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); if (sw_desc) { grp_start = sw_desc->group_head; |
308136d1a iop-adma: impleme... |
1725 |
list_splice_init(&sw_desc->tx_list, &iop_chan->chain); |
636bdeaa1 dmaengine: ack to... |
1726 |
async_tx_ack(&sw_desc->async_tx); |
c21109231 dmaengine: driver... |
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iop_desc_init_null_xor(grp_start, 2, 0); iop_desc_set_byte_count(grp_start, iop_chan, 0); iop_desc_set_dest_addr(grp_start, iop_chan, 0); iop_desc_set_xor_src_addr(grp_start, 0, 0); iop_desc_set_xor_src_addr(grp_start, 1, 0); cookie = iop_chan->common.cookie; cookie++; if (cookie <= 1) cookie = 2; /* initialize the completed cookie to be less than * the most recently used cookie */ iop_chan->completed_cookie = cookie - 1; iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie; /* channel should not be busy */ BUG_ON(iop_chan_is_busy(iop_chan)); /* clear any prior error-status bits */ iop_adma_device_clear_err_status(iop_chan); /* disable operation */ iop_chan_disable(iop_chan); /* set the descriptor address */ iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys); /* 1/ don't add pre-chained descriptors * 2/ dummy read to flush next_desc write */ BUG_ON(iop_desc_get_next_desc(sw_desc)); /* run the descriptor */ iop_chan_enable(iop_chan); } else dev_printk(KERN_ERR, iop_chan->device->common.dev, "failed to allocate null descriptor "); spin_unlock_bh(&iop_chan->lock); } |
ebabe2762 iop-adma: fix pla... |
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MODULE_ALIAS("platform:iop-adma"); |
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static struct platform_driver iop_adma_driver = { .probe = iop_adma_probe, |
bdf602bd7 [ARM] fix lots of... |
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.remove = __devexit_p(iop_adma_remove), |
c21109231 dmaengine: driver... |
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.driver = { .owner = THIS_MODULE, .name = "iop-adma", }, }; static int __init iop_adma_init (void) { |
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return platform_driver_register(&iop_adma_driver); } static void __exit iop_adma_exit (void) { platform_driver_unregister(&iop_adma_driver); return; } |
af49d9248 Remove "unsafe" f... |
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module_exit(iop_adma_exit); |
c21109231 dmaengine: driver... |
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module_init(iop_adma_init); |
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MODULE_AUTHOR("Intel Corporation"); MODULE_DESCRIPTION("IOP ADMA Engine Driver"); MODULE_LICENSE("GPL"); |