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drivers/firewire/fw-ohci.c
70.9 KB
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/* * Driver for OHCI 1394 controllers |
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* |
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* Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software Foundation, * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
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#include <linux/compiler.h> |
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#include <linux/delay.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/gfp.h> |
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#include <linux/init.h> #include <linux/interrupt.h> #include <linux/kernel.h> |
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#include <linux/mm.h> |
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#include <linux/module.h> |
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#include <linux/moduleparam.h> |
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#include <linux/pci.h> |
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#include <linux/spinlock.h> |
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#include <asm/page.h> |
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#include <asm/system.h> |
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#ifdef CONFIG_PPC_PMAC #include <asm/pmac_feature.h> #endif |
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#include "fw-ohci.h" |
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#include "fw-transaction.h" |
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#define DESCRIPTOR_OUTPUT_MORE 0 #define DESCRIPTOR_OUTPUT_LAST (1 << 12) #define DESCRIPTOR_INPUT_MORE (2 << 12) #define DESCRIPTOR_INPUT_LAST (3 << 12) #define DESCRIPTOR_STATUS (1 << 11) #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) #define DESCRIPTOR_PING (1 << 7) #define DESCRIPTOR_YY (1 << 6) #define DESCRIPTOR_NO_IRQ (0 << 4) #define DESCRIPTOR_IRQ_ERROR (1 << 4) #define DESCRIPTOR_IRQ_ALWAYS (3 << 4) #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) #define DESCRIPTOR_WAIT (3 << 0) |
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struct descriptor { __le16 req_count; __le16 control; __le32 data_address; __le32 branch_address; __le16 res_count; __le16 transfer_status; } __attribute__((aligned(16))); |
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struct db_descriptor { __le16 first_size; __le16 control; __le16 second_req_count; __le16 first_req_count; __le32 branch_address; __le16 second_res_count; __le16 first_res_count; __le32 reserved0; __le32 first_buffer; __le32 second_buffer; __le32 reserved1; } __attribute__((aligned(16))); |
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#define CONTROL_SET(regs) (regs) #define CONTROL_CLEAR(regs) ((regs) + 4) #define COMMAND_PTR(regs) ((regs) + 12) #define CONTEXT_MATCH(regs) ((regs) + 16) |
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struct ar_buffer { |
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struct descriptor descriptor; |
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struct ar_buffer *next; __le32 data[0]; }; |
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struct ar_context { struct fw_ohci *ohci; struct ar_buffer *current_buffer; struct ar_buffer *last_buffer; void *pointer; |
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u32 regs; |
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struct tasklet_struct tasklet; }; |
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struct context; typedef int (*descriptor_callback_t)(struct context *ctx, struct descriptor *d, struct descriptor *last); |
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/* * A buffer that contains a block of DMA-able coherent memory used for * storing a portion of a DMA descriptor program. */ struct descriptor_buffer { struct list_head list; dma_addr_t buffer_bus; size_t buffer_size; size_t used; struct descriptor buffer[0]; }; |
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struct context { |
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struct fw_ohci *ohci; |
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u32 regs; |
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int total_allocation; |
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/* * List of page-sized buffers for storing DMA descriptors. * Head of list contains buffers in use and tail of list contains * free buffers. */ struct list_head buffer_list; /* * Pointer to a buffer inside buffer_list that contains the tail * end of the current DMA program. */ struct descriptor_buffer *buffer_tail; /* * The descriptor containing the branch address of the first * descriptor that has not yet been filled by the device. */ struct descriptor *last; /* * The last descriptor in the DMA program. It contains the branch * address that must be updated upon appending a new descriptor. */ struct descriptor *prev; |
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descriptor_callback_t callback; |
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struct tasklet_struct tasklet; |
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}; |
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#define IT_HEADER_SY(v) ((v) << 0) #define IT_HEADER_TCODE(v) ((v) << 4) #define IT_HEADER_CHANNEL(v) ((v) << 8) #define IT_HEADER_TAG(v) ((v) << 14) #define IT_HEADER_SPEED(v) ((v) << 16) #define IT_HEADER_DATA_LENGTH(v) ((v) << 16) |
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struct iso_context { struct fw_iso_context base; |
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struct context context; |
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int excess_bytes; |
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void *header; size_t header_length; |
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}; #define CONFIG_ROM_SIZE 1024 struct fw_ohci { struct fw_card card; __iomem char *registers; dma_addr_t self_id_bus; __le32 *self_id_cpu; struct tasklet_struct bus_reset_tasklet; |
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int node_id; |
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int generation; |
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int request_generation; /* for timestamping incoming requests */ |
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u32 bus_seconds; |
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bool use_dualbuffer; |
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bool old_uninorth; |
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bool bus_reset_packet_quirk; |
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/* * Spinlock for accessing fw_ohci data. Never call out of * this driver with this lock held. */ |
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spinlock_t lock; u32 self_id_buffer[512]; /* Config rom buffers */ __be32 *config_rom; dma_addr_t config_rom_bus; __be32 *next_config_rom; dma_addr_t next_config_rom_bus; u32 next_header; struct ar_context ar_request_ctx; struct ar_context ar_response_ctx; |
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struct context at_request_ctx; struct context at_response_ctx; |
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u32 it_context_mask; struct iso_context *it_context_list; u32 ir_context_mask; struct iso_context *ir_context_list; }; |
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static inline struct fw_ohci *fw_ohci(struct fw_card *card) |
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{ return container_of(card, struct fw_ohci, card); } |
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#define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 #define IR_CONTEXT_BUFFER_FILL 0x80000000 #define IR_CONTEXT_ISOCH_HEADER 0x40000000 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 |
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#define CONTEXT_RUN 0x8000 #define CONTEXT_WAKE 0x1000 #define CONTEXT_DEAD 0x0800 #define CONTEXT_ACTIVE 0x0400 #define OHCI1394_MAX_AT_REQ_RETRIES 0x2 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 #define FW_OHCI_MAJOR 240 #define OHCI1394_REGISTER_SIZE 0x800 #define OHCI_LOOP_COUNT 500 #define OHCI1394_PCI_HCI_Control 0x40 #define SELF_ID_BUF_SIZE 0x800 |
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#define OHCI_TCODE_PHY_PACKET 0x0e |
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#define OHCI_VERSION_1_1 0x010010 |
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static char ohci_driver_name[] = KBUILD_MODNAME; |
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#ifdef CONFIG_FIREWIRE_OHCI_DEBUG |
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#define OHCI_PARAM_DEBUG_AT_AR 1 |
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#define OHCI_PARAM_DEBUG_SELFIDS 2 |
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#define OHCI_PARAM_DEBUG_IRQS 4 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */ |
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static int param_debug; module_param_named(debug, param_debug, int, 0644); MODULE_PARM_DESC(debug, "Verbose logging (default = 0" |
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", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR) |
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", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS) ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS) ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS) |
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", or a combination, or all = -1)"); static void log_irqs(u32 evt) { |
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if (likely(!(param_debug & (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS)))) return; if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) && !(evt & OHCI1394_busReset)) |
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return; |
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fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s ", evt, evt & OHCI1394_selfIDComplete ? " selfID" : "", evt & OHCI1394_RQPkt ? " AR_req" : "", evt & OHCI1394_RSPkt ? " AR_resp" : "", evt & OHCI1394_reqTxComplete ? " AT_req" : "", evt & OHCI1394_respTxComplete ? " AT_resp" : "", evt & OHCI1394_isochRx ? " IR" : "", evt & OHCI1394_isochTx ? " IT" : "", evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", evt & OHCI1394_regAccessFail ? " regAccessFail" : "", evt & OHCI1394_busReset ? " busReset" : "", evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | OHCI1394_RSPkt | OHCI1394_reqTxComplete | OHCI1394_respTxComplete | OHCI1394_isochRx | OHCI1394_isochTx | OHCI1394_postedWriteErr | OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds | OHCI1394_regAccessFail | OHCI1394_busReset) |
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? " ?" : ""); } static const char *speed[] = { [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta", }; static const char *power[] = { [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W", [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W", }; static const char port[] = { '.', '-', 'p', 'c', }; static char _p(u32 *s, int shift) { return port[*s >> shift & 3]; } |
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static void log_selfids(int node_id, int generation, int self_id_count, u32 *s) |
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{ if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) return; |
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fw_notify("%d selfIDs, generation %d, local node ID %04x ", self_id_count, generation, node_id); |
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for (; self_id_count--; ++s) if ((*s & 1 << 23) == 0) |
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fw_notify("selfID 0: %08x, phy %d [%c%c%c] " "%s gc=%d %s %s%s%s ", *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2), speed[*s >> 14 & 3], *s >> 16 & 63, power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); |
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else |
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fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c] ", *s, *s >> 24 & 63, _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10), _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2)); |
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} static const char *evts[] = { [0x00] = "evt_no_status", [0x01] = "-reserved-", [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack", [0x04] = "evt_underrun", [0x05] = "evt_overrun", [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read", [0x08] = "evt_data_write", [0x09] = "evt_bus_reset", [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err", [0x0c] = "-reserved-", [0x0d] = "-reserved-", [0x0e] = "evt_unknown", [0x0f] = "evt_flushed", [0x10] = "-reserved-", [0x11] = "ack_complete", [0x12] = "ack_pending ", [0x13] = "-reserved-", [0x14] = "ack_busy_X", [0x15] = "ack_busy_A", [0x16] = "ack_busy_B", [0x17] = "-reserved-", [0x18] = "-reserved-", [0x19] = "-reserved-", [0x1a] = "-reserved-", [0x1b] = "ack_tardy", [0x1c] = "-reserved-", [0x1d] = "ack_data_error", [0x1e] = "ack_type_error", [0x1f] = "-reserved-", [0x20] = "pending/cancelled", }; static const char *tcodes[] = { [0x0] = "QW req", [0x1] = "BW req", [0x2] = "W resp", [0x3] = "-reserved-", [0x4] = "QR req", [0x5] = "BR req", [0x6] = "QR resp", [0x7] = "BR resp", [0x8] = "cycle start", [0x9] = "Lk req", [0xa] = "async stream packet", [0xb] = "Lk resp", [0xc] = "-reserved-", [0xd] = "-reserved-", [0xe] = "link internal", [0xf] = "-reserved-", }; static const char *phys[] = { [0x0] = "phy config packet", [0x1] = "link-on packet", [0x2] = "self-id packet", [0x3] = "-reserved-", }; static void log_ar_at_event(char dir, int speed, u32 *header, int evt) { int tcode = header[0] >> 4 & 0xf; char specific[12]; if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR))) return; if (unlikely(evt >= ARRAY_SIZE(evts))) evt = 0x1f; |
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if (evt == OHCI1394_evt_bus_reset) { |
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fw_notify("A%c evt_bus_reset, generation %d ", dir, (header[2] >> 16) & 0xff); |
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return; } |
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if (header[0] == ~header[1]) { |
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fw_notify("A%c %s, %s, %08x ", dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]); |
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return; } switch (tcode) { case 0x0: case 0x6: case 0x8: snprintf(specific, sizeof(specific), " = %08x", be32_to_cpu((__force __be32)header[3])); break; case 0x1: case 0x5: case 0x7: case 0x9: case 0xb: snprintf(specific, sizeof(specific), " %x,%x", header[3] >> 16, header[3] & 0xffff); break; default: specific[0] = '\0'; } switch (tcode) { case 0xe: case 0xa: |
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fw_notify("A%c %s, %s ", dir, evts[evt], tcodes[tcode]); |
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break; case 0x0: case 0x1: case 0x4: case 0x5: case 0x9: |
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fw_notify("A%c spd %x tl %02x, " "%04x -> %04x, %s, " "%s, %04x%08x%s ", dir, speed, header[0] >> 10 & 0x3f, header[1] >> 16, header[0] >> 16, evts[evt], tcodes[tcode], header[1] & 0xffff, header[2], specific); |
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break; default: |
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fw_notify("A%c spd %x tl %02x, " "%04x -> %04x, %s, " "%s%s ", dir, speed, header[0] >> 10 & 0x3f, header[1] >> 16, header[0] >> 16, evts[evt], tcodes[tcode], specific); |
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} } #else #define log_irqs(evt) |
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#define log_selfids(node_id, generation, self_id_count, sid) |
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#define log_ar_at_event(dir, speed, header, evt) #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */ |
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static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) |
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{ writel(data, ohci->registers + offset); } |
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static inline u32 reg_read(const struct fw_ohci *ohci, int offset) |
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{ return readl(ohci->registers + offset); } |
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static inline void flush_writes(const struct fw_ohci *ohci) |
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{ /* Do a dummy read to flush writes. */ reg_read(ohci, OHCI1394_Version); } static int ohci_update_phy_reg(struct fw_card *card, int addr, int clear_bits, int set_bits) { struct fw_ohci *ohci = fw_ohci(card); u32 val, old; reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); |
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flush_writes(ohci); |
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msleep(2); val = reg_read(ohci, OHCI1394_PhyControl); if ((val & OHCI1394_PhyControl_ReadDone) == 0) { fw_error("failed to set phy reg bits. "); return -EBUSY; } old = OHCI1394_PhyControl_ReadData(val); old = (old & ~clear_bits) | set_bits; reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Write(addr, old)); return 0; } |
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static int ar_context_add_page(struct ar_context *ctx) |
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{ |
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struct device *dev = ctx->ohci->card.device; struct ar_buffer *ab; |
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dma_addr_t uninitialized_var(ab_bus); |
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size_t offset; |
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ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC); |
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if (ab == NULL) return -ENOMEM; |
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memset(&ab->descriptor, 0, sizeof(ab->descriptor)); |
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ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | DESCRIPTOR_STATUS | DESCRIPTOR_BRANCH_ALWAYS); |
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offset = offsetof(struct ar_buffer, data); ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset); ab->descriptor.data_address = cpu_to_le32(ab_bus + offset); ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset); ab->descriptor.branch_address = 0; |
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ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1); |
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ctx->last_buffer->next = ab; ctx->last_buffer = ab; |
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reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); |
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flush_writes(ctx->ohci); |
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return 0; |
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} |
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#if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) #define cond_le32_to_cpu(v) \ (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v)) #else #define cond_le32_to_cpu(v) le32_to_cpu(v) #endif |
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static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) |
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{ |
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struct fw_ohci *ohci = ctx->ohci; |
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struct fw_packet p; u32 status, length, tcode; |
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int evt; |
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p.header[0] = cond_le32_to_cpu(buffer[0]); p.header[1] = cond_le32_to_cpu(buffer[1]); p.header[2] = cond_le32_to_cpu(buffer[2]); |
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tcode = (p.header[0] >> 4) & 0x0f; switch (tcode) { case TCODE_WRITE_QUADLET_REQUEST: case TCODE_READ_QUADLET_RESPONSE: |
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p.header[3] = (__force __u32) buffer[3]; |
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p.header_length = 16; |
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p.payload_length = 0; |
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break; |
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case TCODE_READ_BLOCK_REQUEST : |
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p.header[3] = cond_le32_to_cpu(buffer[3]); |
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|
511 512 513 514 515 |
p.header_length = 16; p.payload_length = 0; break; case TCODE_WRITE_BLOCK_REQUEST: |
2639a6fb2
|
516 517 518 |
case TCODE_READ_BLOCK_RESPONSE: case TCODE_LOCK_REQUEST: case TCODE_LOCK_RESPONSE: |
11bf20ad0
|
519 |
p.header[3] = cond_le32_to_cpu(buffer[3]); |
2639a6fb2
|
520 |
p.header_length = 16; |
32b46093a
|
521 |
p.payload_length = p.header[3] >> 16; |
2639a6fb2
|
522 523 524 525 |
break; case TCODE_WRITE_RESPONSE: case TCODE_READ_QUADLET_REQUEST: |
32b46093a
|
526 |
case OHCI_TCODE_PHY_PACKET: |
2639a6fb2
|
527 |
p.header_length = 12; |
32b46093a
|
528 |
p.payload_length = 0; |
2639a6fb2
|
529 |
break; |
ccff96294
|
530 531 532 533 534 |
default: /* FIXME: Stop context, discard everything, and restart? */ p.header_length = 0; p.payload_length = 0; |
2639a6fb2
|
535 |
} |
ed5689122
|
536 |
|
32b46093a
|
537 538 539 540 |
p.payload = (void *) buffer + p.header_length; /* FIXME: What to do about evt_* errors? */ length = (p.header_length + p.payload_length + 3) / 4; |
11bf20ad0
|
541 |
status = cond_le32_to_cpu(buffer[length]); |
43286568a
|
542 |
evt = (status >> 16) & 0x1f; |
32b46093a
|
543 |
|
43286568a
|
544 |
p.ack = evt - 16; |
32b46093a
|
545 546 547 |
p.speed = (status >> 21) & 0x7; p.timestamp = status & 0xffff; p.generation = ohci->request_generation; |
ed5689122
|
548 |
|
43286568a
|
549 |
log_ar_at_event('R', p.speed, p.header, evt); |
ad3c0fe8b
|
550 |
|
c781c06d1
|
551 552 |
/* * The OHCI bus reset handler synthesizes a phy packet with |
ed5689122
|
553 554 555 556 557 |
* the new generation number when a bus reset happens (see * section 8.4.2.3). This helps us determine when a request * was received and make sure we send the response in the same * generation. We only need this for requests; for responses * we use the unique tlabel for finding the matching |
c781c06d1
|
558 |
* request. |
d34316a4b
|
559 560 561 562 |
* * Alas some chips sometimes emit bus reset packets with a * wrong generation. We set the correct generation for these * at a slightly incorrect time (in bus_reset_tasklet). |
c781c06d1
|
563 |
*/ |
d34316a4b
|
564 565 566 567 |
if (evt == OHCI1394_evt_bus_reset) { if (!ohci->bus_reset_packet_quirk) ohci->request_generation = (p.header[2] >> 16) & 0xff; } else if (ctx == &ohci->ar_request_ctx) { |
2639a6fb2
|
568 |
fw_core_handle_request(&ohci->card, &p); |
d34316a4b
|
569 |
} else { |
2639a6fb2
|
570 |
fw_core_handle_response(&ohci->card, &p); |
d34316a4b
|
571 |
} |
ed5689122
|
572 |
|
32b46093a
|
573 574 |
return buffer + length + 1; } |
ed5689122
|
575 |
|
32b46093a
|
576 577 578 579 580 581 582 583 584 585 586 587 588 |
static void ar_context_tasklet(unsigned long data) { struct ar_context *ctx = (struct ar_context *)data; struct fw_ohci *ohci = ctx->ohci; struct ar_buffer *ab; struct descriptor *d; void *buffer, *end; ab = ctx->current_buffer; d = &ab->descriptor; if (d->res_count == 0) { size_t size, rest, offset; |
6b84236d3
|
589 590 |
dma_addr_t start_bus; void *start; |
32b46093a
|
591 |
|
c781c06d1
|
592 593 |
/* * This descriptor is finished and we may have a |
32b46093a
|
594 |
* packet split across this and the next buffer. We |
c781c06d1
|
595 596 |
* reuse the page for reassembling the split packet. */ |
32b46093a
|
597 598 |
offset = offsetof(struct ar_buffer, data); |
6b84236d3
|
599 600 |
start = buffer = ab; start_bus = le32_to_cpu(ab->descriptor.data_address) - offset; |
32b46093a
|
601 |
|
32b46093a
|
602 603 604 605 606 607 608 609 610 611 612 613 |
ab = ab->next; d = &ab->descriptor; size = buffer + PAGE_SIZE - ctx->pointer; rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count); memmove(buffer, ctx->pointer, size); memcpy(buffer + size, ab->data, rest); ctx->current_buffer = ab; ctx->pointer = (void *) ab->data + rest; end = buffer + size + rest; while (buffer < end) buffer = handle_ar_packet(ctx, buffer); |
bde1709aa
|
614 |
dma_free_coherent(ohci->card.device, PAGE_SIZE, |
6b84236d3
|
615 |
start, start_bus); |
32b46093a
|
616 617 618 619 620 621 622 623 624 |
ar_context_add_page(ctx); } else { buffer = ctx->pointer; ctx->pointer = end = (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count); while (buffer < end) buffer = handle_ar_packet(ctx, buffer); } |
ed5689122
|
625 626 627 |
} static int |
72e318e07
|
628 |
ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs) |
ed5689122
|
629 |
{ |
32b46093a
|
630 |
struct ar_buffer ab; |
ed5689122
|
631 |
|
72e318e07
|
632 633 634 |
ctx->regs = regs; ctx->ohci = ohci; ctx->last_buffer = &ab; |
ed5689122
|
635 |
tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); |
32b46093a
|
636 637 638 639 |
ar_context_add_page(ctx); ar_context_add_page(ctx); ctx->current_buffer = ab.next; ctx->pointer = ctx->current_buffer->data; |
2aef469a3
|
640 641 642 643 644 645 646 647 648 649 |
return 0; } static void ar_context_run(struct ar_context *ctx) { struct ar_buffer *ab = ctx->current_buffer; dma_addr_t ab_bus; size_t offset; offset = offsetof(struct ar_buffer, data); |
0a9972baa
|
650 |
ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset; |
2aef469a3
|
651 652 |
reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1); |
a77754a75
|
653 |
reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); |
32b46093a
|
654 |
flush_writes(ctx->ohci); |
ed5689122
|
655 |
} |
373b2edd8
|
656 |
|
a186b4a6b
|
657 658 659 660 661 662 663 664 665 666 667 668 669 670 |
static struct descriptor * find_branch_descriptor(struct descriptor *d, int z) { int b, key; b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2; key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8; /* figure out which descriptor the branch address goes in */ if (z == 2 && (b == 3 || key == 2)) return d; else return d + z - 1; } |
30200739e
|
671 672 673 |
static void context_tasklet(unsigned long data) { struct context *ctx = (struct context *) data; |
30200739e
|
674 675 676 |
struct descriptor *d, *last; u32 address; int z; |
fe5ca6343
|
677 |
struct descriptor_buffer *desc; |
30200739e
|
678 |
|
fe5ca6343
|
679 680 681 |
desc = list_entry(ctx->buffer_list.next, struct descriptor_buffer, list); last = ctx->last; |
30200739e
|
682 |
while (last->branch_address != 0) { |
fe5ca6343
|
683 |
struct descriptor_buffer *old_desc = desc; |
30200739e
|
684 685 |
address = le32_to_cpu(last->branch_address); z = address & 0xf; |
fe5ca6343
|
686 687 688 689 690 691 692 693 694 |
address &= ~0xf; /* If the branch address points to a buffer outside of the * current buffer, advance to the next buffer. */ if (address < desc->buffer_bus || address >= desc->buffer_bus + desc->used) desc = list_entry(desc->list.next, struct descriptor_buffer, list); d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d); |
a186b4a6b
|
695 |
last = find_branch_descriptor(d, z); |
30200739e
|
696 697 698 |
if (!ctx->callback(ctx, d, last)) break; |
fe5ca6343
|
699 700 701 702 703 704 705 706 707 708 |
if (old_desc != desc) { /* If we've advanced to the next buffer, move the * previous buffer to the free list. */ unsigned long flags; old_desc->used = 0; spin_lock_irqsave(&ctx->ohci->lock, flags); list_move_tail(&old_desc->list, &ctx->buffer_list); spin_unlock_irqrestore(&ctx->ohci->lock, flags); } ctx->last = last; |
30200739e
|
709 710 |
} } |
fe5ca6343
|
711 712 713 714 715 716 717 718 |
/* * Allocate a new buffer and add it to the list of free buffers for this * context. Must be called with ohci->lock held. */ static int context_add_buffer(struct context *ctx) { struct descriptor_buffer *desc; |
f5101d58a
|
719 |
dma_addr_t uninitialized_var(bus_addr); |
fe5ca6343
|
720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 |
int offset; /* * 16MB of descriptors should be far more than enough for any DMA * program. This will catch run-away userspace or DoS attacks. */ if (ctx->total_allocation >= 16*1024*1024) return -ENOMEM; desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, &bus_addr, GFP_ATOMIC); if (!desc) return -ENOMEM; offset = (void *)&desc->buffer - (void *)desc; desc->buffer_size = PAGE_SIZE - offset; desc->buffer_bus = bus_addr + offset; desc->used = 0; list_add_tail(&desc->list, &ctx->buffer_list); ctx->total_allocation += PAGE_SIZE; return 0; } |
30200739e
|
744 745 |
static int context_init(struct context *ctx, struct fw_ohci *ohci, |
fe5ca6343
|
746 |
u32 regs, descriptor_callback_t callback) |
30200739e
|
747 748 749 |
{ ctx->ohci = ohci; ctx->regs = regs; |
fe5ca6343
|
750 751 752 753 |
ctx->total_allocation = 0; INIT_LIST_HEAD(&ctx->buffer_list); if (context_add_buffer(ctx) < 0) |
30200739e
|
754 |
return -ENOMEM; |
fe5ca6343
|
755 756 |
ctx->buffer_tail = list_entry(ctx->buffer_list.next, struct descriptor_buffer, list); |
30200739e
|
757 758 |
tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); ctx->callback = callback; |
c781c06d1
|
759 760 |
/* * We put a dummy descriptor in the buffer that has a NULL |
30200739e
|
761 |
* branch address and looks like it's been sent. That way we |
fe5ca6343
|
762 |
* have a descriptor to append DMA programs to. |
c781c06d1
|
763 |
*/ |
fe5ca6343
|
764 765 766 767 768 769 |
memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer)); ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011); ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer); ctx->last = ctx->buffer_tail->buffer; ctx->prev = ctx->buffer_tail->buffer; |
30200739e
|
770 771 772 |
return 0; } |
9b32d5f30
|
773 |
static void |
30200739e
|
774 775 776 |
context_release(struct context *ctx) { struct fw_card *card = &ctx->ohci->card; |
fe5ca6343
|
777 |
struct descriptor_buffer *desc, *tmp; |
30200739e
|
778 |
|
fe5ca6343
|
779 780 781 782 |
list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list) dma_free_coherent(card->device, PAGE_SIZE, desc, desc->buffer_bus - ((void *)&desc->buffer - (void *)desc)); |
30200739e
|
783 |
} |
fe5ca6343
|
784 |
/* Must be called with ohci->lock held */ |
30200739e
|
785 786 787 |
static struct descriptor * context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus) { |
fe5ca6343
|
788 789 790 791 792 793 794 795 796 |
struct descriptor *d = NULL; struct descriptor_buffer *desc = ctx->buffer_tail; if (z * sizeof(*d) > desc->buffer_size) return NULL; if (z * sizeof(*d) > desc->buffer_size - desc->used) { /* No room for the descriptor in this buffer, so advance to the * next one. */ |
30200739e
|
797 |
|
fe5ca6343
|
798 799 800 801 802 803 804 805 806 807 |
if (desc->list.next == &ctx->buffer_list) { /* If there is no free buffer next in the list, * allocate one. */ if (context_add_buffer(ctx) < 0) return NULL; } desc = list_entry(desc->list.next, struct descriptor_buffer, list); ctx->buffer_tail = desc; } |
30200739e
|
808 |
|
fe5ca6343
|
809 |
d = desc->buffer + desc->used / sizeof(*d); |
2d826cc5c
|
810 |
memset(d, 0, z * sizeof(*d)); |
fe5ca6343
|
811 |
*d_bus = desc->buffer_bus + desc->used; |
30200739e
|
812 813 814 |
return d; } |
295e3feb9
|
815 |
static void context_run(struct context *ctx, u32 extra) |
30200739e
|
816 817 |
{ struct fw_ohci *ohci = ctx->ohci; |
a77754a75
|
818 |
reg_write(ohci, COMMAND_PTR(ctx->regs), |
fe5ca6343
|
819 |
le32_to_cpu(ctx->last->branch_address)); |
a77754a75
|
820 821 |
reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); |
30200739e
|
822 823 824 825 826 827 828 |
flush_writes(ohci); } static void context_append(struct context *ctx, struct descriptor *d, int z, int extra) { dma_addr_t d_bus; |
fe5ca6343
|
829 |
struct descriptor_buffer *desc = ctx->buffer_tail; |
30200739e
|
830 |
|
fe5ca6343
|
831 |
d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d); |
30200739e
|
832 |
|
fe5ca6343
|
833 834 835 |
desc->used += (z + extra) * sizeof(*d); ctx->prev->branch_address = cpu_to_le32(d_bus | z); ctx->prev = find_branch_descriptor(d, z); |
30200739e
|
836 |
|
a77754a75
|
837 |
reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); |
30200739e
|
838 839 840 841 842 843 |
flush_writes(ctx->ohci); } static void context_stop(struct context *ctx) { u32 reg; |
b82956685
|
844 |
int i; |
30200739e
|
845 |
|
a77754a75
|
846 |
reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); |
b82956685
|
847 |
flush_writes(ctx->ohci); |
30200739e
|
848 |
|
b82956685
|
849 |
for (i = 0; i < 10; i++) { |
a77754a75
|
850 |
reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs)); |
b82956685
|
851 852 853 854 855 |
if ((reg & CONTEXT_ACTIVE) == 0) break; fw_notify("context_stop: still active (0x%08x) ", reg); |
b980f5a22
|
856 |
mdelay(1); |
b82956685
|
857 |
} |
30200739e
|
858 |
} |
ed5689122
|
859 |
|
f319b6a02
|
860 861 862 |
struct driver_data { struct fw_packet *packet; }; |
ed5689122
|
863 |
|
c781c06d1
|
864 865 |
/* * This function apppends a packet to the DMA queue for transmission. |
f319b6a02
|
866 |
* Must always be called with the ochi->lock held to ensure proper |
c781c06d1
|
867 868 |
* generation handling and locking around packet queue manipulation. */ |
f319b6a02
|
869 870 |
static int at_context_queue_packet(struct context *ctx, struct fw_packet *packet) |
ed5689122
|
871 |
{ |
ed5689122
|
872 |
struct fw_ohci *ohci = ctx->ohci; |
4b6d51ec6
|
873 |
dma_addr_t d_bus, uninitialized_var(payload_bus); |
f319b6a02
|
874 875 876 |
struct driver_data *driver_data; struct descriptor *d, *last; __le32 *header; |
ed5689122
|
877 |
int z, tcode; |
f319b6a02
|
878 |
u32 reg; |
ed5689122
|
879 |
|
f319b6a02
|
880 881 882 883 |
d = context_get_descriptors(ctx, 4, &d_bus); if (d == NULL) { packet->ack = RCODE_SEND_ERROR; return -1; |
ed5689122
|
884 |
} |
a77754a75
|
885 |
d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); |
f319b6a02
|
886 |
d[0].res_count = cpu_to_le16(packet->timestamp); |
c781c06d1
|
887 888 |
/* * The DMA format for asyncronous link packets is different |
ed5689122
|
889 890 |
* from the IEEE1394 layout, so shift the fields around * accordingly. If header_length is 8, it's a PHY packet, to |
c781c06d1
|
891 892 |
* which we need to prepend an extra quadlet. */ |
f319b6a02
|
893 894 |
header = (__le32 *) &d[1]; |
ed5689122
|
895 |
if (packet->header_length > 8) { |
f319b6a02
|
896 897 898 899 900 |
header[0] = cpu_to_le32((packet->header[0] & 0xffff) | (packet->speed << 16)); header[1] = cpu_to_le32((packet->header[1] & 0xffff) | (packet->header[0] & 0xffff0000)); header[2] = cpu_to_le32(packet->header[2]); |
ed5689122
|
901 902 903 |
tcode = (packet->header[0] >> 4) & 0x0f; if (TCODE_IS_BLOCK_PACKET(tcode)) |
f319b6a02
|
904 |
header[3] = cpu_to_le32(packet->header[3]); |
ed5689122
|
905 |
else |
f319b6a02
|
906 907 908 |
header[3] = (__force __le32) packet->header[3]; d[0].req_count = cpu_to_le16(packet->header_length); |
ed5689122
|
909 |
} else { |
f319b6a02
|
910 911 912 913 914 |
header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) | (packet->speed << 16)); header[1] = cpu_to_le32(packet->header[0]); header[2] = cpu_to_le32(packet->header[1]); d[0].req_count = cpu_to_le16(12); |
ed5689122
|
915 |
} |
f319b6a02
|
916 917 |
driver_data = (struct driver_data *) &d[3]; driver_data->packet = packet; |
20d116731
|
918 |
packet->driver_data = driver_data; |
a186b4a6b
|
919 |
|
f319b6a02
|
920 921 922 923 |
if (packet->payload_length > 0) { payload_bus = dma_map_single(ohci->card.device, packet->payload, packet->payload_length, DMA_TO_DEVICE); |
8d8bb39b9
|
924 |
if (dma_mapping_error(ohci->card.device, payload_bus)) { |
f319b6a02
|
925 926 927 928 929 930 931 932 |
packet->ack = RCODE_SEND_ERROR; return -1; } d[2].req_count = cpu_to_le16(packet->payload_length); d[2].data_address = cpu_to_le32(payload_bus); last = &d[2]; z = 3; |
ed5689122
|
933 |
} else { |
f319b6a02
|
934 935 |
last = &d[0]; z = 2; |
ed5689122
|
936 |
} |
ed5689122
|
937 |
|
a77754a75
|
938 939 940 |
last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | DESCRIPTOR_IRQ_ALWAYS | DESCRIPTOR_BRANCH_ALWAYS); |
ed5689122
|
941 |
|
76f73ca1b
|
942 943 944 945 946 947 948 949 950 951 952 953 954 |
/* * If the controller and packet generations don't match, we need to * bail out and try again. If IntEvent.busReset is set, the AT context * is halted, so appending to the context and trying to run it is * futile. Most controllers do the right thing and just flush the AT * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind * up stalling out. So we just bail out in software and try again * later, and everyone is happy. * FIXME: Document how the locking works. */ if (ohci->generation != packet->generation || reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) { |
ab88ca488
|
955 956 957 |
if (packet->payload_length > 0) dma_unmap_single(ohci->card.device, payload_bus, packet->payload_length, DMA_TO_DEVICE); |
f319b6a02
|
958 959 960 961 962 |
packet->ack = RCODE_GENERATION; return -1; } context_append(ctx, d, z, 4 - z); |
ed5689122
|
963 |
|
f319b6a02
|
964 |
/* If the context isn't already running, start it up. */ |
a77754a75
|
965 |
reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs)); |
053b30808
|
966 |
if ((reg & CONTEXT_RUN) == 0) |
f319b6a02
|
967 968 969 |
context_run(ctx, 0); return 0; |
ed5689122
|
970 |
} |
f319b6a02
|
971 972 973 |
static int handle_at_packet(struct context *context, struct descriptor *d, struct descriptor *last) |
ed5689122
|
974 |
{ |
f319b6a02
|
975 |
struct driver_data *driver_data; |
ed5689122
|
976 |
struct fw_packet *packet; |
f319b6a02
|
977 978 |
struct fw_ohci *ohci = context->ohci; dma_addr_t payload_bus; |
ed5689122
|
979 |
int evt; |
f319b6a02
|
980 981 982 |
if (last->transfer_status == 0) /* This descriptor isn't done yet, stop iteration. */ return 0; |
ed5689122
|
983 |
|
f319b6a02
|
984 985 986 987 988 |
driver_data = (struct driver_data *) &d[3]; packet = driver_data->packet; if (packet == NULL) /* This packet was cancelled, just continue. */ return 1; |
730c32f58
|
989 |
|
f319b6a02
|
990 991 992 |
payload_bus = le32_to_cpu(last->data_address); if (payload_bus != 0) dma_unmap_single(ohci->card.device, payload_bus, |
ed5689122
|
993 |
packet->payload_length, DMA_TO_DEVICE); |
ed5689122
|
994 |
|
f319b6a02
|
995 996 |
evt = le16_to_cpu(last->transfer_status) & 0x1f; packet->timestamp = le16_to_cpu(last->res_count); |
ed5689122
|
997 |
|
ad3c0fe8b
|
998 |
log_ar_at_event('T', packet->speed, packet->header, evt); |
f319b6a02
|
999 1000 1001 1002 1003 |
switch (evt) { case OHCI1394_evt_timeout: /* Async response transmit timed out. */ packet->ack = RCODE_CANCELLED; break; |
ed5689122
|
1004 |
|
f319b6a02
|
1005 |
case OHCI1394_evt_flushed: |
c781c06d1
|
1006 1007 1008 1009 |
/* * The packet was flushed should give same error as * when we try to use a stale generation count. */ |
f319b6a02
|
1010 1011 |
packet->ack = RCODE_GENERATION; break; |
ed5689122
|
1012 |
|
f319b6a02
|
1013 |
case OHCI1394_evt_missing_ack: |
c781c06d1
|
1014 1015 1016 1017 |
/* * Using a valid (current) generation count, but the * node is not on the bus or not sending acks. */ |
f319b6a02
|
1018 1019 |
packet->ack = RCODE_NO_ACK; break; |
ed5689122
|
1020 |
|
f319b6a02
|
1021 1022 1023 1024 1025 1026 1027 1028 1029 |
case ACK_COMPLETE + 0x10: case ACK_PENDING + 0x10: case ACK_BUSY_X + 0x10: case ACK_BUSY_A + 0x10: case ACK_BUSY_B + 0x10: case ACK_DATA_ERROR + 0x10: case ACK_TYPE_ERROR + 0x10: packet->ack = evt - 0x10; break; |
ed5689122
|
1030 |
|
f319b6a02
|
1031 1032 1033 1034 |
default: packet->ack = RCODE_SEND_ERROR; break; } |
ed5689122
|
1035 |
|
f319b6a02
|
1036 |
packet->callback(packet, &ohci->card, packet->ack); |
ed5689122
|
1037 |
|
f319b6a02
|
1038 |
return 1; |
ed5689122
|
1039 |
} |
a77754a75
|
1040 1041 1042 1043 1044 |
#define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff) #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f) #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff) #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff) #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff) |
93c4cceb9
|
1045 1046 1047 1048 1049 1050 |
static void handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr) { struct fw_packet response; int tcode, length, i; |
a77754a75
|
1051 |
tcode = HEADER_GET_TCODE(packet->header[0]); |
93c4cceb9
|
1052 |
if (TCODE_IS_BLOCK_PACKET(tcode)) |
a77754a75
|
1053 |
length = HEADER_GET_DATA_LENGTH(packet->header[3]); |
93c4cceb9
|
1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 |
else length = 4; i = csr - CSR_CONFIG_ROM; if (i + length > CONFIG_ROM_SIZE) { fw_fill_response(&response, packet->header, RCODE_ADDRESS_ERROR, NULL, 0); } else if (!TCODE_IS_READ_REQUEST(tcode)) { fw_fill_response(&response, packet->header, RCODE_TYPE_ERROR, NULL, 0); } else { fw_fill_response(&response, packet->header, RCODE_COMPLETE, (void *) ohci->config_rom + i, length); } fw_core_handle_response(&ohci->card, &response); } static void handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr) { struct fw_packet response; int tcode, length, ext_tcode, sel; __be32 *payload, lock_old; u32 lock_arg, lock_data; |
a77754a75
|
1079 1080 |
tcode = HEADER_GET_TCODE(packet->header[0]); length = HEADER_GET_DATA_LENGTH(packet->header[3]); |
93c4cceb9
|
1081 |
payload = packet->payload; |
a77754a75
|
1082 |
ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]); |
93c4cceb9
|
1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 |
if (tcode == TCODE_LOCK_REQUEST && ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { lock_arg = be32_to_cpu(payload[0]); lock_data = be32_to_cpu(payload[1]); } else if (tcode == TCODE_READ_QUADLET_REQUEST) { lock_arg = 0; lock_data = 0; } else { fw_fill_response(&response, packet->header, RCODE_TYPE_ERROR, NULL, 0); goto out; } sel = (csr - CSR_BUS_MANAGER_ID) / 4; reg_write(ohci, OHCI1394_CSRData, lock_data); reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); reg_write(ohci, OHCI1394_CSRControl, sel); if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData)); else fw_notify("swap not done yet "); fw_fill_response(&response, packet->header, |
2d826cc5c
|
1109 |
RCODE_COMPLETE, &lock_old, sizeof(lock_old)); |
93c4cceb9
|
1110 1111 1112 1113 1114 |
out: fw_core_handle_response(&ohci->card, &response); } static void |
f319b6a02
|
1115 |
handle_local_request(struct context *ctx, struct fw_packet *packet) |
93c4cceb9
|
1116 1117 1118 |
{ u64 offset; u32 csr; |
473d28c73
|
1119 1120 1121 1122 |
if (ctx == &ctx->ohci->at_request_ctx) { packet->ack = ACK_PENDING; packet->callback(packet, &ctx->ohci->card, packet->ack); } |
93c4cceb9
|
1123 1124 1125 |
offset = ((unsigned long long) |
a77754a75
|
1126 |
HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) | |
93c4cceb9
|
1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 |
packet->header[2]; csr = offset - CSR_REGISTER_BASE; /* Handle config rom reads. */ if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) handle_local_rom(ctx->ohci, packet, csr); else switch (csr) { case CSR_BUS_MANAGER_ID: case CSR_BANDWIDTH_AVAILABLE: case CSR_CHANNELS_AVAILABLE_HI: case CSR_CHANNELS_AVAILABLE_LO: handle_local_lock(ctx->ohci, packet, csr); break; default: if (ctx == &ctx->ohci->at_request_ctx) fw_core_handle_request(&ctx->ohci->card, packet); else fw_core_handle_response(&ctx->ohci->card, packet); break; } |
473d28c73
|
1147 1148 1149 1150 1151 |
if (ctx == &ctx->ohci->at_response_ctx) { packet->ack = ACK_COMPLETE; packet->callback(packet, &ctx->ohci->card, packet->ack); } |
93c4cceb9
|
1152 |
} |
e636fe257
|
1153 |
|
ed5689122
|
1154 |
static void |
f319b6a02
|
1155 |
at_context_transmit(struct context *ctx, struct fw_packet *packet) |
ed5689122
|
1156 |
{ |
ed5689122
|
1157 |
unsigned long flags; |
f319b6a02
|
1158 |
int retval; |
ed5689122
|
1159 1160 |
spin_lock_irqsave(&ctx->ohci->lock, flags); |
a77754a75
|
1161 |
if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id && |
e636fe257
|
1162 |
ctx->ohci->generation == packet->generation) { |
93c4cceb9
|
1163 1164 1165 |
spin_unlock_irqrestore(&ctx->ohci->lock, flags); handle_local_request(ctx, packet); return; |
e636fe257
|
1166 |
} |
ed5689122
|
1167 |
|
f319b6a02
|
1168 |
retval = at_context_queue_packet(ctx, packet); |
ed5689122
|
1169 |
spin_unlock_irqrestore(&ctx->ohci->lock, flags); |
f319b6a02
|
1170 1171 |
if (retval < 0) packet->callback(packet, &ctx->ohci->card, packet->ack); |
a186b4a6b
|
1172 |
|
ed5689122
|
1173 1174 1175 1176 1177 |
} static void bus_reset_tasklet(unsigned long data) { struct fw_ohci *ohci = (struct fw_ohci *)data; |
e636fe257
|
1178 |
int self_id_count, i, j, reg; |
ed5689122
|
1179 1180 |
int generation, new_generation; unsigned long flags; |
4eaff7d63
|
1181 1182 |
void *free_rom = NULL; dma_addr_t free_rom_bus = 0; |
ed5689122
|
1183 1184 1185 |
reg = reg_read(ohci, OHCI1394_NodeID); if (!(reg & OHCI1394_NodeID_idValid)) { |
02ff8f8ee
|
1186 1187 |
fw_notify("node ID not valid, new bus reset in progress "); |
ed5689122
|
1188 1189 |
return; } |
02ff8f8ee
|
1190 1191 1192 1193 1194 1195 1196 |
if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { fw_notify("malconfigured bus "); return; } ohci->node_id = reg & (OHCI1394_NodeID_busNumber | OHCI1394_NodeID_nodeNumber); |
ed5689122
|
1197 |
|
c8a9a498e
|
1198 1199 1200 1201 1202 1203 |
reg = reg_read(ohci, OHCI1394_SelfIDCount); if (reg & OHCI1394_SelfIDCount_selfIDError) { fw_notify("inconsistent self IDs "); return; } |
c781c06d1
|
1204 1205 |
/* * The count in the SelfIDCount register is the number of |
ed5689122
|
1206 1207 |
* bytes in the self ID receive buffer. Since we also receive * the inverted quadlets and a header quadlet, we shift one |
c781c06d1
|
1208 1209 |
* bit extra to get the actual number of self IDs. */ |
c8a9a498e
|
1210 |
self_id_count = (reg >> 3) & 0x3ff; |
016bf3dfc
|
1211 1212 1213 1214 1215 |
if (self_id_count == 0) { fw_notify("inconsistent self IDs "); return; } |
11bf20ad0
|
1216 |
generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff; |
ee71c2f9e
|
1217 |
rmb(); |
ed5689122
|
1218 1219 |
for (i = 1, j = 0; j < self_id_count; i += 2, j++) { |
c8a9a498e
|
1220 1221 1222 1223 1224 |
if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) { fw_notify("inconsistent self IDs "); return; } |
11bf20ad0
|
1225 1226 |
ohci->self_id_buffer[j] = cond_le32_to_cpu(ohci->self_id_cpu[i]); |
ed5689122
|
1227 |
} |
ee71c2f9e
|
1228 |
rmb(); |
ed5689122
|
1229 |
|
c781c06d1
|
1230 1231 |
/* * Check the consistency of the self IDs we just read. The |
ed5689122
|
1232 1233 1234 1235 1236 1237 1238 1239 1240 |
* problem we face is that a new bus reset can start while we * read out the self IDs from the DMA buffer. If this happens, * the DMA buffer will be overwritten with new self IDs and we * will read out inconsistent data. The OHCI specification * (section 11.2) recommends a technique similar to * linux/seqlock.h, where we remember the generation of the * self IDs in the buffer before reading them out and compare * it to the current generation after reading them out. If * the two generations match we know we have a consistent set |
c781c06d1
|
1241 1242 |
* of self IDs. */ |
ed5689122
|
1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 |
new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; if (new_generation != generation) { fw_notify("recursive bus reset detected, " "discarding self ids "); return; } /* FIXME: Document how the locking works. */ spin_lock_irqsave(&ohci->lock, flags); ohci->generation = generation; |
f319b6a02
|
1256 1257 |
context_stop(&ohci->at_request_ctx); context_stop(&ohci->at_response_ctx); |
ed5689122
|
1258 |
reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); |
d34316a4b
|
1259 1260 |
if (ohci->bus_reset_packet_quirk) ohci->request_generation = generation; |
c781c06d1
|
1261 1262 |
/* * This next bit is unrelated to the AT context stuff but we |
ed5689122
|
1263 1264 1265 1266 |
* have to do it under the spinlock also. If a new config rom * was set up before this reset, the old one is now no longer * in use and we can free it. Update the config rom pointers * to point to the current config rom and clear the |
c781c06d1
|
1267 1268 |
* next_config_rom pointer so a new udpate can take place. */ |
ed5689122
|
1269 1270 |
if (ohci->next_config_rom != NULL) { |
0bd243c4d
|
1271 1272 1273 1274 |
if (ohci->next_config_rom != ohci->config_rom) { free_rom = ohci->config_rom; free_rom_bus = ohci->config_rom_bus; } |
ed5689122
|
1275 1276 1277 |
ohci->config_rom = ohci->next_config_rom; ohci->config_rom_bus = ohci->next_config_rom_bus; ohci->next_config_rom = NULL; |
c781c06d1
|
1278 1279 |
/* * Restore config_rom image and manually update |
ed5689122
|
1280 1281 |
* config_rom registers. Writing the header quadlet * will indicate that the config rom is ready, so we |
c781c06d1
|
1282 1283 |
* do that last. */ |
ed5689122
|
1284 1285 1286 1287 1288 |
reg_write(ohci, OHCI1394_BusOptions, be32_to_cpu(ohci->config_rom[2])); ohci->config_rom[0] = cpu_to_be32(ohci->next_header); reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header); } |
080de8c2c
|
1289 1290 1291 1292 |
#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0); reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0); #endif |
ed5689122
|
1293 |
spin_unlock_irqrestore(&ohci->lock, flags); |
4eaff7d63
|
1294 1295 1296 |
if (free_rom) dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, free_rom, free_rom_bus); |
08ddb2f4c
|
1297 1298 |
log_selfids(ohci->node_id, generation, self_id_count, ohci->self_id_buffer); |
ad3c0fe8b
|
1299 |
|
e636fe257
|
1300 |
fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, |
ed5689122
|
1301 1302 1303 1304 1305 1306 |
self_id_count, ohci->self_id_buffer); } static irqreturn_t irq_handler(int irq, void *data) { struct fw_ohci *ohci = data; |
d60d7f1d5
|
1307 |
u32 event, iso_event, cycle_time; |
ed5689122
|
1308 1309 1310 |
int i; event = reg_read(ohci, OHCI1394_IntEventClear); |
a515958d6
|
1311 |
if (!event || !~event) |
ed5689122
|
1312 |
return IRQ_NONE; |
a007bb857
|
1313 1314 |
/* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */ reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset); |
ad3c0fe8b
|
1315 |
log_irqs(event); |
ed5689122
|
1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 |
if (event & OHCI1394_selfIDComplete) tasklet_schedule(&ohci->bus_reset_tasklet); if (event & OHCI1394_RQPkt) tasklet_schedule(&ohci->ar_request_ctx.tasklet); if (event & OHCI1394_RSPkt) tasklet_schedule(&ohci->ar_response_ctx.tasklet); if (event & OHCI1394_reqTxComplete) tasklet_schedule(&ohci->at_request_ctx.tasklet); if (event & OHCI1394_respTxComplete) tasklet_schedule(&ohci->at_response_ctx.tasklet); |
c889475fb
|
1331 |
iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); |
ed5689122
|
1332 1333 1334 1335 |
reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); while (iso_event) { i = ffs(iso_event) - 1; |
30200739e
|
1336 |
tasklet_schedule(&ohci->ir_context_list[i].context.tasklet); |
ed5689122
|
1337 1338 |
iso_event &= ~(1 << i); } |
c889475fb
|
1339 |
iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); |
ed5689122
|
1340 1341 1342 1343 |
reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); while (iso_event) { i = ffs(iso_event) - 1; |
30200739e
|
1344 |
tasklet_schedule(&ohci->it_context_list[i].context.tasklet); |
ed5689122
|
1345 1346 |
iso_event &= ~(1 << i); } |
75f7832e3
|
1347 1348 1349 1350 |
if (unlikely(event & OHCI1394_regAccessFail)) fw_error("Register access failure - " "please notify linux1394-devel@lists.sf.net "); |
e524f616f
|
1351 1352 1353 |
if (unlikely(event & OHCI1394_postedWriteErr)) fw_error("PCI posted write error "); |
bb9f2206b
|
1354 1355 1356 1357 1358 1359 1360 |
if (unlikely(event & OHCI1394_cycleTooLong)) { if (printk_ratelimit()) fw_notify("isochronous cycle too long "); reg_write(ohci, OHCI1394_LinkControlSet, OHCI1394_LinkControl_cycleMaster); } |
d60d7f1d5
|
1361 1362 1363 1364 1365 |
if (event & OHCI1394_cycle64Seconds) { cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer); if ((cycle_time & 0x80000000) == 0) ohci->bus_seconds++; } |
ed5689122
|
1366 1367 |
return IRQ_HANDLED; } |
2aef469a3
|
1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 |
static int software_reset(struct fw_ohci *ohci) { int i; reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); for (i = 0; i < OHCI_LOOP_COUNT; i++) { if ((reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_softReset) == 0) return 0; msleep(1); } return -EBUSY; } |
ed5689122
|
1383 1384 1385 1386 |
static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length) { struct fw_ohci *ohci = fw_ohci(card); struct pci_dev *dev = to_pci_dev(card->device); |
022147242
|
1387 1388 |
u32 lps; int i; |
ed5689122
|
1389 |
|
2aef469a3
|
1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 |
if (software_reset(ohci)) { fw_error("Failed to reset ohci card. "); return -EBUSY; } /* * Now enable LPS, which we need in order to start accessing * most of the registers. In fact, on some cards (ALI M5251), * accessing registers in the SClk domain without LPS enabled * will lock up the machine. Wait 50msec to make sure we have |
022147242
|
1401 1402 |
* full link enabled. However, with some cards (well, at least * a JMicron PCIe card), we have to try again sometimes. |
2aef469a3
|
1403 1404 1405 1406 1407 |
*/ reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS | OHCI1394_HCControl_postedWriteEnable); flush_writes(ohci); |
022147242
|
1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 |
for (lps = 0, i = 0; !lps && i < 3; i++) { msleep(50); lps = reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS; } if (!lps) { fw_error("Failed to set Link Power Status "); return -EIO; } |
2aef469a3
|
1420 1421 1422 |
reg_write(ohci, OHCI1394_HCControlClear, OHCI1394_HCControl_noByteSwapData); |
affc9c24a
|
1423 |
reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); |
e896ec430
|
1424 1425 |
reg_write(ohci, OHCI1394_LinkControlClear, OHCI1394_LinkControl_rcvPhyPkt); |
2aef469a3
|
1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 |
reg_write(ohci, OHCI1394_LinkControlSet, OHCI1394_LinkControl_rcvSelfID | OHCI1394_LinkControl_cycleTimerEnable | OHCI1394_LinkControl_cycleMaster); reg_write(ohci, OHCI1394_ATRetries, OHCI1394_MAX_AT_REQ_RETRIES | (OHCI1394_MAX_AT_RESP_RETRIES << 4) | (OHCI1394_MAX_PHYS_RESP_RETRIES << 8)); ar_context_run(&ohci->ar_request_ctx); ar_context_run(&ohci->ar_response_ctx); |
2aef469a3
|
1438 1439 1440 1441 1442 1443 1444 1445 |
reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000); reg_write(ohci, OHCI1394_IntEventClear, ~0); reg_write(ohci, OHCI1394_IntMaskClear, ~0); reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_selfIDComplete | OHCI1394_RQPkt | OHCI1394_RSPkt | OHCI1394_reqTxComplete | OHCI1394_respTxComplete | OHCI1394_isochRx | OHCI1394_isochTx | |
bb9f2206b
|
1446 |
OHCI1394_postedWriteErr | OHCI1394_cycleTooLong | |
75f7832e3
|
1447 1448 |
OHCI1394_cycle64Seconds | OHCI1394_regAccessFail | OHCI1394_masterIntEnable); |
a007bb857
|
1449 1450 |
if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS) reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset); |
2aef469a3
|
1451 1452 1453 1454 1455 |
/* Activate link_on bit and contender bit in our self ID packets.*/ if (ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER) < 0) return -EIO; |
c781c06d1
|
1456 1457 |
/* * When the link is not yet enabled, the atomic config rom |
ed5689122
|
1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 |
* update mechanism described below in ohci_set_config_rom() * is not active. We have to update ConfigRomHeader and * BusOptions manually, and the write to ConfigROMmap takes * effect immediately. We tie this to the enabling of the * link, so we have a valid config rom before enabling - the * OHCI requires that ConfigROMhdr and BusOptions have valid * values before enabling. * * However, when the ConfigROMmap is written, some controllers * always read back quadlets 0 and 2 from the config rom to * the ConfigRomHeader and BusOptions registers on bus reset. * They shouldn't do that in this initial case where the link * isn't enabled. This means we have to use the same * workaround here, setting the bus header to 0 and then write * the right values in the bus reset tasklet. */ |
0bd243c4d
|
1474 1475 1476 1477 1478 1479 1480 |
if (config_rom) { ohci->next_config_rom = dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, &ohci->next_config_rom_bus, GFP_KERNEL); if (ohci->next_config_rom == NULL) return -ENOMEM; |
ed5689122
|
1481 |
|
0bd243c4d
|
1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 |
memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE); fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4); } else { /* * In the suspend case, config_rom is NULL, which * means that we just reuse the old config rom. */ ohci->next_config_rom = ohci->config_rom; ohci->next_config_rom_bus = ohci->config_rom_bus; } |
ed5689122
|
1492 |
|
0bd243c4d
|
1493 |
ohci->next_header = be32_to_cpu(ohci->next_config_rom[0]); |
ed5689122
|
1494 1495 |
ohci->next_config_rom[0] = 0; reg_write(ohci, OHCI1394_ConfigROMhdr, 0); |
0bd243c4d
|
1496 1497 |
reg_write(ohci, OHCI1394_BusOptions, be32_to_cpu(ohci->next_config_rom[2])); |
ed5689122
|
1498 1499 1500 1501 1502 |
reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); if (request_irq(dev->irq, irq_handler, |
65efffa8f
|
1503 |
IRQF_SHARED, ohci_driver_name, ohci)) { |
ed5689122
|
1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 |
fw_error("Failed to allocate shared interrupt %d. ", dev->irq); dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, ohci->config_rom, ohci->config_rom_bus); return -EIO; } reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_linkEnable | OHCI1394_HCControl_BIBimageValid); flush_writes(ohci); |
c781c06d1
|
1516 1517 1518 1519 |
/* * We are ready to go, initiate bus reset to finish the * initialization. */ |
ed5689122
|
1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 |
fw_core_initiate_bus_reset(&ohci->card, 1); return 0; } static int ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length) { struct fw_ohci *ohci; unsigned long flags; |
4eaff7d63
|
1531 |
int retval = -EBUSY; |
ed5689122
|
1532 |
__be32 *next_config_rom; |
f5101d58a
|
1533 |
dma_addr_t uninitialized_var(next_config_rom_bus); |
ed5689122
|
1534 1535 |
ohci = fw_ohci(card); |
c781c06d1
|
1536 1537 |
/* * When the OHCI controller is enabled, the config rom update |
ed5689122
|
1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 |
* mechanism is a bit tricky, but easy enough to use. See * section 5.5.6 in the OHCI specification. * * The OHCI controller caches the new config rom address in a * shadow register (ConfigROMmapNext) and needs a bus reset * for the changes to take place. When the bus reset is * detected, the controller loads the new values for the * ConfigRomHeader and BusOptions registers from the specified * config rom and loads ConfigROMmap from the ConfigROMmapNext * shadow register. All automatically and atomically. * * Now, there's a twist to this story. The automatic load of * ConfigRomHeader and BusOptions doesn't honor the * noByteSwapData bit, so with a be32 config rom, the * controller will load be32 values in to these registers * during the atomic update, even on litte endian * architectures. The workaround we use is to put a 0 in the * header quadlet; 0 is endian agnostic and means that the * config rom isn't ready yet. In the bus reset tasklet we * then set up the real values for the two registers. * * We use ohci->lock to avoid racing with the code that sets * ohci->next_config_rom to NULL (see bus_reset_tasklet). */ next_config_rom = dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, &next_config_rom_bus, GFP_KERNEL); if (next_config_rom == NULL) return -ENOMEM; spin_lock_irqsave(&ohci->lock, flags); if (ohci->next_config_rom == NULL) { ohci->next_config_rom = next_config_rom; ohci->next_config_rom_bus = next_config_rom_bus; memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE); fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4); ohci->next_header = config_rom[0]; ohci->next_config_rom[0] = 0; reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); |
4eaff7d63
|
1584 |
retval = 0; |
ed5689122
|
1585 1586 1587 |
} spin_unlock_irqrestore(&ohci->lock, flags); |
c781c06d1
|
1588 1589 |
/* * Now initiate a bus reset to have the changes take |
ed5689122
|
1590 1591 1592 |
* effect. We clean up the old config rom memory and DMA * mappings in the bus reset tasklet, since the OHCI * controller could need to access it before the bus reset |
c781c06d1
|
1593 1594 |
* takes effect. */ |
ed5689122
|
1595 1596 |
if (retval == 0) fw_core_initiate_bus_reset(&ohci->card, 1); |
4eaff7d63
|
1597 1598 1599 |
else dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, next_config_rom, next_config_rom_bus); |
ed5689122
|
1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 |
return retval; } static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) { struct fw_ohci *ohci = fw_ohci(card); at_context_transmit(&ohci->at_request_ctx, packet); } static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) { struct fw_ohci *ohci = fw_ohci(card); at_context_transmit(&ohci->at_response_ctx, packet); } |
730c32f58
|
1617 1618 1619 |
static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) { struct fw_ohci *ohci = fw_ohci(card); |
f319b6a02
|
1620 1621 1622 |
struct context *ctx = &ohci->at_request_ctx; struct driver_data *driver_data = packet->driver_data; int retval = -ENOENT; |
730c32f58
|
1623 |
|
f319b6a02
|
1624 |
tasklet_disable(&ctx->tasklet); |
730c32f58
|
1625 |
|
f319b6a02
|
1626 1627 |
if (packet->ack != 0) goto out; |
730c32f58
|
1628 |
|
ad3c0fe8b
|
1629 |
log_ar_at_event('T', packet->speed, packet->header, 0x20); |
f319b6a02
|
1630 1631 1632 1633 |
driver_data->packet = NULL; packet->ack = RCODE_CANCELLED; packet->callback(packet, &ohci->card, packet->ack); retval = 0; |
730c32f58
|
1634 |
|
f319b6a02
|
1635 1636 |
out: tasklet_enable(&ctx->tasklet); |
730c32f58
|
1637 |
|
f319b6a02
|
1638 |
return retval; |
730c32f58
|
1639 |
} |
ed5689122
|
1640 1641 1642 |
static int ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation) { |
080de8c2c
|
1643 1644 1645 |
#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA return 0; #else |
ed5689122
|
1646 1647 |
struct fw_ohci *ohci = fw_ohci(card); unsigned long flags; |
907293d78
|
1648 |
int n, retval = 0; |
ed5689122
|
1649 |
|
c781c06d1
|
1650 1651 1652 1653 |
/* * FIXME: Make sure this bitmask is cleared when we clear the busReset * interrupt bit. Clear physReqResourceAllBuses on bus reset. */ |
ed5689122
|
1654 1655 1656 1657 1658 1659 1660 |
spin_lock_irqsave(&ohci->lock, flags); if (ohci->generation != generation) { retval = -ESTALE; goto out; } |
c781c06d1
|
1661 1662 1663 1664 |
/* * Note, if the node ID contains a non-local bus ID, physical DMA is * enabled for _all_ nodes on remote buses. */ |
907293d78
|
1665 1666 1667 1668 1669 1670 |
n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; if (n < 32) reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); else reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); |
ed5689122
|
1671 |
flush_writes(ohci); |
ed5689122
|
1672 |
out: |
6cad95fe9
|
1673 |
spin_unlock_irqrestore(&ohci->lock, flags); |
ed5689122
|
1674 |
return retval; |
080de8c2c
|
1675 |
#endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */ |
ed5689122
|
1676 |
} |
373b2edd8
|
1677 |
|
d60d7f1d5
|
1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 |
static u64 ohci_get_bus_time(struct fw_card *card) { struct fw_ohci *ohci = fw_ohci(card); u32 cycle_time; u64 bus_time; cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer); bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time; return bus_time; } |
d2746dc19
|
1690 1691 1692 |
static int handle_ir_dualbuffer_packet(struct context *context, struct descriptor *d, struct descriptor *last) |
ed5689122
|
1693 |
{ |
295e3feb9
|
1694 1695 1696 |
struct iso_context *ctx = container_of(context, struct iso_context, context); struct db_descriptor *db = (struct db_descriptor *) d; |
c70dc788f
|
1697 |
__le32 *ir_header; |
9b32d5f30
|
1698 |
size_t header_length; |
c70dc788f
|
1699 1700 |
void *p, *end; int i; |
d2746dc19
|
1701 |
|
efbf390a2
|
1702 |
if (db->first_res_count != 0 && db->second_res_count != 0) { |
0642b6577
|
1703 1704 1705 1706 1707 1708 |
if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) { /* This descriptor isn't done yet, stop iteration. */ return 0; } ctx->excess_bytes -= le16_to_cpu(db->second_req_count); } |
295e3feb9
|
1709 |
|
c70dc788f
|
1710 1711 1712 1713 1714 1715 1716 |
header_length = le16_to_cpu(db->first_req_count) - le16_to_cpu(db->first_res_count); i = ctx->header_length; p = db + 1; end = p + header_length; while (p < end && i + ctx->base.header_size <= PAGE_SIZE) { |
c781c06d1
|
1717 1718 |
/* * The iso header is byteswapped to little endian by |
15536221d
|
1719 1720 1721 |
* the controller, but the remaining header quadlets * are big endian. We want to present all the headers * as big endian, so we have to swap the first |
c781c06d1
|
1722 1723 |
* quadlet. */ |
15536221d
|
1724 1725 |
*(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4)); memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4); |
c70dc788f
|
1726 |
i += ctx->base.header_size; |
0642b6577
|
1727 |
ctx->excess_bytes += |
efbf390a2
|
1728 |
(le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff; |
c70dc788f
|
1729 1730 |
p += ctx->base.header_size + 4; } |
c70dc788f
|
1731 |
ctx->header_length = i; |
9b32d5f30
|
1732 |
|
0642b6577
|
1733 1734 |
ctx->excess_bytes -= le16_to_cpu(db->second_req_count) - le16_to_cpu(db->second_res_count); |
a77754a75
|
1735 |
if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) { |
c70dc788f
|
1736 1737 1738 |
ir_header = (__le32 *) (db + 1); ctx->base.callback(&ctx->base, le32_to_cpu(ir_header[0]) & 0xffff, |
9b32d5f30
|
1739 |
ctx->header_length, ctx->header, |
295e3feb9
|
1740 |
ctx->base.callback_data); |
9b32d5f30
|
1741 1742 |
ctx->header_length = 0; } |
ed5689122
|
1743 |
|
295e3feb9
|
1744 |
return 1; |
ed5689122
|
1745 |
} |
a186b4a6b
|
1746 1747 1748 1749 1750 1751 |
static int handle_ir_packet_per_buffer(struct context *context, struct descriptor *d, struct descriptor *last) { struct iso_context *ctx = container_of(context, struct iso_context, context); |
bcee893c6
|
1752 |
struct descriptor *pd; |
a186b4a6b
|
1753 |
__le32 *ir_header; |
bcee893c6
|
1754 1755 |
void *p; int i; |
a186b4a6b
|
1756 |
|
bcee893c6
|
1757 1758 1759 1760 1761 |
for (pd = d; pd <= last; pd++) { if (pd->transfer_status) break; } if (pd > last) |
a186b4a6b
|
1762 1763 |
/* Descriptor(s) not done yet, stop iteration */ return 0; |
a186b4a6b
|
1764 |
i = ctx->header_length; |
bcee893c6
|
1765 |
p = last + 1; |
a186b4a6b
|
1766 |
|
bcee893c6
|
1767 1768 |
if (ctx->base.header_size > 0 && i + ctx->base.header_size <= PAGE_SIZE) { |
a186b4a6b
|
1769 1770 1771 1772 1773 1774 1775 1776 |
/* * The iso header is byteswapped to little endian by * the controller, but the remaining header quadlets * are big endian. We want to present all the headers * as big endian, so we have to swap the first quadlet. */ *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4)); memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4); |
bcee893c6
|
1777 |
ctx->header_length += ctx->base.header_size; |
a186b4a6b
|
1778 |
} |
bcee893c6
|
1779 1780 |
if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) { ir_header = (__le32 *) p; |
a186b4a6b
|
1781 1782 1783 1784 1785 1786 |
ctx->base.callback(&ctx->base, le32_to_cpu(ir_header[0]) & 0xffff, ctx->header_length, ctx->header, ctx->base.callback_data); ctx->header_length = 0; } |
a186b4a6b
|
1787 1788 |
return 1; } |
30200739e
|
1789 1790 1791 |
static int handle_it_packet(struct context *context, struct descriptor *d, struct descriptor *last) |
ed5689122
|
1792 |
{ |
30200739e
|
1793 1794 |
struct iso_context *ctx = container_of(context, struct iso_context, context); |
373b2edd8
|
1795 |
|
30200739e
|
1796 1797 1798 |
if (last->transfer_status == 0) /* This descriptor isn't done yet, stop iteration. */ return 0; |
a77754a75
|
1799 |
if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) |
9b32d5f30
|
1800 1801 |
ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count), 0, NULL, ctx->base.callback_data); |
30200739e
|
1802 1803 |
return 1; |
ed5689122
|
1804 |
} |
30200739e
|
1805 |
static struct fw_iso_context * |
eb0306eac
|
1806 |
ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size) |
ed5689122
|
1807 1808 1809 |
{ struct fw_ohci *ohci = fw_ohci(card); struct iso_context *ctx, *list; |
30200739e
|
1810 |
descriptor_callback_t callback; |
295e3feb9
|
1811 |
u32 *mask, regs; |
ed5689122
|
1812 |
unsigned long flags; |
9b32d5f30
|
1813 |
int index, retval = -ENOMEM; |
ed5689122
|
1814 1815 1816 1817 |
if (type == FW_ISO_CONTEXT_TRANSMIT) { mask = &ohci->it_context_mask; list = ohci->it_context_list; |
30200739e
|
1818 |
callback = handle_it_packet; |
ed5689122
|
1819 |
} else { |
373b2edd8
|
1820 1821 |
mask = &ohci->ir_context_mask; list = ohci->ir_context_list; |
95984f62c
|
1822 |
if (ohci->use_dualbuffer) |
a186b4a6b
|
1823 1824 1825 |
callback = handle_ir_dualbuffer_packet; else callback = handle_ir_packet_per_buffer; |
ed5689122
|
1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 |
} spin_lock_irqsave(&ohci->lock, flags); index = ffs(*mask) - 1; if (index >= 0) *mask &= ~(1 << index); spin_unlock_irqrestore(&ohci->lock, flags); if (index < 0) return ERR_PTR(-EBUSY); |
373b2edd8
|
1836 1837 1838 1839 |
if (type == FW_ISO_CONTEXT_TRANSMIT) regs = OHCI1394_IsoXmitContextBase(index); else regs = OHCI1394_IsoRcvContextBase(index); |
ed5689122
|
1840 |
ctx = &list[index]; |
2d826cc5c
|
1841 |
memset(ctx, 0, sizeof(*ctx)); |
9b32d5f30
|
1842 1843 1844 1845 |
ctx->header_length = 0; ctx->header = (void *) __get_free_page(GFP_KERNEL); if (ctx->header == NULL) goto out; |
fe5ca6343
|
1846 |
retval = context_init(&ctx->context, ohci, regs, callback); |
9b32d5f30
|
1847 1848 |
if (retval < 0) goto out_with_header; |
ed5689122
|
1849 1850 |
return &ctx->base; |
9b32d5f30
|
1851 1852 1853 1854 1855 1856 1857 1858 1859 |
out_with_header: free_page((unsigned long)ctx->header); out: spin_lock_irqsave(&ohci->lock, flags); *mask |= 1 << index; spin_unlock_irqrestore(&ohci->lock, flags); return ERR_PTR(retval); |
ed5689122
|
1860 |
} |
eb0306eac
|
1861 1862 |
static int ohci_start_iso(struct fw_iso_context *base, s32 cycle, u32 sync, u32 tags) |
ed5689122
|
1863 |
{ |
373b2edd8
|
1864 |
struct iso_context *ctx = container_of(base, struct iso_context, base); |
30200739e
|
1865 |
struct fw_ohci *ohci = ctx->context.ohci; |
8a2f7d932
|
1866 |
u32 control, match; |
ed5689122
|
1867 |
int index; |
295e3feb9
|
1868 1869 |
if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { index = ctx - ohci->it_context_list; |
8a2f7d932
|
1870 1871 1872 |
match = 0; if (cycle >= 0) match = IT_CONTEXT_CYCLE_MATCH_ENABLE | |
295e3feb9
|
1873 |
(cycle & 0x7fff) << 16; |
21efb3cfc
|
1874 |
|
295e3feb9
|
1875 1876 |
reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); |
8a2f7d932
|
1877 |
context_run(&ctx->context, match); |
295e3feb9
|
1878 1879 |
} else { index = ctx - ohci->ir_context_list; |
a186b4a6b
|
1880 |
control = IR_CONTEXT_ISOCH_HEADER; |
95984f62c
|
1881 |
if (ohci->use_dualbuffer) |
a186b4a6b
|
1882 |
control |= IR_CONTEXT_DUAL_BUFFER_MODE; |
8a2f7d932
|
1883 1884 1885 1886 1887 |
match = (tags << 28) | (sync << 8) | ctx->base.channel; if (cycle >= 0) { match |= (cycle & 0x07fff) << 12; control |= IR_CONTEXT_CYCLE_MATCH_ENABLE; } |
ed5689122
|
1888 |
|
295e3feb9
|
1889 1890 |
reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); |
a77754a75
|
1891 |
reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); |
8a2f7d932
|
1892 |
context_run(&ctx->context, control); |
295e3feb9
|
1893 |
} |
ed5689122
|
1894 1895 1896 |
return 0; } |
b82956685
|
1897 1898 1899 |
static int ohci_stop_iso(struct fw_iso_context *base) { struct fw_ohci *ohci = fw_ohci(base->card); |
373b2edd8
|
1900 |
struct iso_context *ctx = container_of(base, struct iso_context, base); |
b82956685
|
1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 |
int index; if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { index = ctx - ohci->it_context_list; reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); } else { index = ctx - ohci->ir_context_list; reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); } flush_writes(ohci); context_stop(&ctx->context); return 0; } |
ed5689122
|
1915 1916 1917 |
static void ohci_free_iso_context(struct fw_iso_context *base) { struct fw_ohci *ohci = fw_ohci(base->card); |
373b2edd8
|
1918 |
struct iso_context *ctx = container_of(base, struct iso_context, base); |
ed5689122
|
1919 1920 |
unsigned long flags; int index; |
b82956685
|
1921 1922 |
ohci_stop_iso(base); context_release(&ctx->context); |
9b32d5f30
|
1923 |
free_page((unsigned long)ctx->header); |
b82956685
|
1924 |
|
ed5689122
|
1925 1926 1927 1928 |
spin_lock_irqsave(&ohci->lock, flags); if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { index = ctx - ohci->it_context_list; |
ed5689122
|
1929 1930 1931 |
ohci->it_context_mask |= 1 << index; } else { index = ctx - ohci->ir_context_list; |
ed5689122
|
1932 1933 |
ohci->ir_context_mask |= 1 << index; } |
ed5689122
|
1934 1935 1936 1937 1938 |
spin_unlock_irqrestore(&ohci->lock, flags); } static int |
295e3feb9
|
1939 1940 1941 1942 |
ohci_queue_iso_transmit(struct fw_iso_context *base, struct fw_iso_packet *packet, struct fw_iso_buffer *buffer, unsigned long payload) |
ed5689122
|
1943 |
{ |
373b2edd8
|
1944 |
struct iso_context *ctx = container_of(base, struct iso_context, base); |
30200739e
|
1945 |
struct descriptor *d, *last, *pd; |
ed5689122
|
1946 1947 |
struct fw_iso_packet *p; __le32 *header; |
9aad81253
|
1948 |
dma_addr_t d_bus, page_bus; |
ed5689122
|
1949 1950 |
u32 z, header_z, payload_z, irq; u32 payload_index, payload_end_index, next_page_index; |
30200739e
|
1951 |
int page, end_page, i, length, offset; |
ed5689122
|
1952 |
|
c781c06d1
|
1953 1954 1955 1956 |
/* * FIXME: Cycle lost behavior should be configurable: lose * packet, retransmit or terminate.. */ |
ed5689122
|
1957 1958 |
p = packet; |
9aad81253
|
1959 |
payload_index = payload; |
ed5689122
|
1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 |
if (p->skip) z = 1; else z = 2; if (p->header_length > 0) z++; /* Determine the first page the payload isn't contained in. */ end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; if (p->payload_length > 0) payload_z = end_page - (payload_index >> PAGE_SHIFT); else payload_z = 0; z += payload_z; /* Get header size in number of descriptors. */ |
2d826cc5c
|
1978 |
header_z = DIV_ROUND_UP(p->header_length, sizeof(*d)); |
ed5689122
|
1979 |
|
30200739e
|
1980 1981 1982 |
d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); if (d == NULL) return -ENOMEM; |
ed5689122
|
1983 1984 |
if (!p->skip) { |
a77754a75
|
1985 |
d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); |
ed5689122
|
1986 1987 1988 |
d[0].req_count = cpu_to_le16(8); header = (__le32 *) &d[1]; |
a77754a75
|
1989 1990 1991 1992 1993 |
header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) | IT_HEADER_TAG(p->tag) | IT_HEADER_TCODE(TCODE_STREAM_DATA) | IT_HEADER_CHANNEL(ctx->base.channel) | IT_HEADER_SPEED(ctx->base.speed)); |
ed5689122
|
1994 |
header[1] = |
a77754a75
|
1995 |
cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length + |
ed5689122
|
1996 1997 1998 1999 2000 |
p->payload_length)); } if (p->header_length > 0) { d[2].req_count = cpu_to_le16(p->header_length); |
2d826cc5c
|
2001 |
d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d)); |
ed5689122
|
2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 |
memcpy(&d[z], p->header, p->header_length); } pd = d + z - payload_z; payload_end_index = payload_index + p->payload_length; for (i = 0; i < payload_z; i++) { page = payload_index >> PAGE_SHIFT; offset = payload_index & ~PAGE_MASK; next_page_index = (page + 1) << PAGE_SHIFT; length = min(next_page_index, payload_end_index) - payload_index; pd[i].req_count = cpu_to_le16(length); |
9aad81253
|
2014 2015 2016 |
page_bus = page_private(buffer->pages[page]); pd[i].data_address = cpu_to_le32(page_bus + offset); |
ed5689122
|
2017 2018 2019 |
payload_index += length; } |
ed5689122
|
2020 |
if (p->interrupt) |
a77754a75
|
2021 |
irq = DESCRIPTOR_IRQ_ALWAYS; |
ed5689122
|
2022 |
else |
a77754a75
|
2023 |
irq = DESCRIPTOR_NO_IRQ; |
ed5689122
|
2024 |
|
30200739e
|
2025 |
last = z == 2 ? d : d + z - 1; |
a77754a75
|
2026 2027 2028 |
last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | DESCRIPTOR_STATUS | DESCRIPTOR_BRANCH_ALWAYS | |
cbb59da71
|
2029 |
irq); |
ed5689122
|
2030 |
|
30200739e
|
2031 |
context_append(&ctx->context, d, z, header_z); |
ed5689122
|
2032 2033 2034 |
return 0; } |
373b2edd8
|
2035 |
|
98b6cbe83
|
2036 |
static int |
d2746dc19
|
2037 2038 2039 2040 |
ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base, struct fw_iso_packet *packet, struct fw_iso_buffer *buffer, unsigned long payload) |
295e3feb9
|
2041 2042 2043 2044 2045 2046 2047 |
{ struct iso_context *ctx = container_of(base, struct iso_context, base); struct db_descriptor *db = NULL; struct descriptor *d; struct fw_iso_packet *p; dma_addr_t d_bus, page_bus; u32 z, header_z, length, rest; |
c70dc788f
|
2048 |
int page, offset, packet_count, header_size; |
373b2edd8
|
2049 |
|
c781c06d1
|
2050 2051 2052 2053 |
/* * FIXME: Cycle lost behavior should be configurable: lose * packet, retransmit or terminate.. */ |
295e3feb9
|
2054 2055 2056 |
p = packet; z = 2; |
c781c06d1
|
2057 2058 2059 2060 |
/* * The OHCI controller puts the status word in the header * buffer too, so we need 4 extra bytes per packet. */ |
c70dc788f
|
2061 2062 |
packet_count = p->header_length / ctx->base.header_size; header_size = packet_count * (ctx->base.header_size + 4); |
295e3feb9
|
2063 |
/* Get header size in number of descriptors. */ |
2d826cc5c
|
2064 |
header_z = DIV_ROUND_UP(header_size, sizeof(*d)); |
295e3feb9
|
2065 2066 2067 |
page = payload >> PAGE_SHIFT; offset = payload & ~PAGE_MASK; rest = p->payload_length; |
295e3feb9
|
2068 2069 2070 2071 2072 2073 2074 2075 |
/* FIXME: make packet-per-buffer/dual-buffer a context option */ while (rest > 0) { d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); if (d == NULL) return -ENOMEM; db = (struct db_descriptor *) d; |
a77754a75
|
2076 2077 |
db->control = cpu_to_le16(DESCRIPTOR_STATUS | DESCRIPTOR_BRANCH_ALWAYS); |
c70dc788f
|
2078 |
db->first_size = cpu_to_le16(ctx->base.header_size + 4); |
0642b6577
|
2079 2080 2081 2082 2083 2084 |
if (p->skip && rest == p->payload_length) { db->control |= cpu_to_le16(DESCRIPTOR_WAIT); db->first_req_count = db->first_size; } else { db->first_req_count = cpu_to_le16(header_size); } |
1e1d196bf
|
2085 |
db->first_res_count = db->first_req_count; |
2d826cc5c
|
2086 |
db->first_buffer = cpu_to_le32(d_bus + sizeof(*db)); |
373b2edd8
|
2087 |
|
0642b6577
|
2088 2089 2090 |
if (p->skip && rest == p->payload_length) length = 4; else if (offset + rest < PAGE_SIZE) |
295e3feb9
|
2091 2092 2093 |
length = rest; else length = PAGE_SIZE - offset; |
1e1d196bf
|
2094 2095 |
db->second_req_count = cpu_to_le16(length); db->second_res_count = db->second_req_count; |
295e3feb9
|
2096 2097 |
page_bus = page_private(buffer->pages[page]); db->second_buffer = cpu_to_le32(page_bus + offset); |
cb2d2cdbc
|
2098 |
if (p->interrupt && length == rest) |
a77754a75
|
2099 |
db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); |
cb2d2cdbc
|
2100 |
|
295e3feb9
|
2101 2102 2103 |
context_append(&ctx->context, d, z, header_z); offset = (offset + length) & ~PAGE_MASK; rest -= length; |
0642b6577
|
2104 2105 |
if (offset == 0) page++; |
295e3feb9
|
2106 |
} |
d2746dc19
|
2107 2108 |
return 0; } |
21efb3cfc
|
2109 |
|
d2746dc19
|
2110 |
static int |
a186b4a6b
|
2111 2112 2113 2114 2115 2116 2117 |
ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base, struct fw_iso_packet *packet, struct fw_iso_buffer *buffer, unsigned long payload) { struct iso_context *ctx = container_of(base, struct iso_context, base); struct descriptor *d = NULL, *pd = NULL; |
bcee893c6
|
2118 |
struct fw_iso_packet *p = packet; |
a186b4a6b
|
2119 2120 |
dma_addr_t d_bus, page_bus; u32 z, header_z, rest; |
bcee893c6
|
2121 2122 |
int i, j, length; int page, offset, packet_count, header_size, payload_per_buffer; |
a186b4a6b
|
2123 2124 2125 2126 2127 2128 |
/* * The OHCI controller puts the status word in the * buffer too, so we need 4 extra bytes per packet. */ packet_count = p->header_length / ctx->base.header_size; |
bcee893c6
|
2129 |
header_size = ctx->base.header_size + 4; |
a186b4a6b
|
2130 2131 2132 2133 2134 |
/* Get header size in number of descriptors. */ header_z = DIV_ROUND_UP(header_size, sizeof(*d)); page = payload >> PAGE_SHIFT; offset = payload & ~PAGE_MASK; |
bcee893c6
|
2135 |
payload_per_buffer = p->payload_length / packet_count; |
a186b4a6b
|
2136 2137 2138 |
for (i = 0; i < packet_count; i++) { /* d points to the header descriptor */ |
bcee893c6
|
2139 |
z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1; |
a186b4a6b
|
2140 |
d = context_get_descriptors(&ctx->context, |
bcee893c6
|
2141 |
z + header_z, &d_bus); |
a186b4a6b
|
2142 2143 |
if (d == NULL) return -ENOMEM; |
bcee893c6
|
2144 2145 2146 2147 |
d->control = cpu_to_le16(DESCRIPTOR_STATUS | DESCRIPTOR_INPUT_MORE); if (p->skip && i == 0) d->control |= cpu_to_le16(DESCRIPTOR_WAIT); |
a186b4a6b
|
2148 2149 |
d->req_count = cpu_to_le16(header_size); d->res_count = d->req_count; |
bcee893c6
|
2150 |
d->transfer_status = 0; |
a186b4a6b
|
2151 |
d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d))); |
bcee893c6
|
2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 |
rest = payload_per_buffer; for (j = 1; j < z; j++) { pd = d + j; pd->control = cpu_to_le16(DESCRIPTOR_STATUS | DESCRIPTOR_INPUT_MORE); if (offset + rest < PAGE_SIZE) length = rest; else length = PAGE_SIZE - offset; pd->req_count = cpu_to_le16(length); pd->res_count = pd->req_count; pd->transfer_status = 0; page_bus = page_private(buffer->pages[page]); pd->data_address = cpu_to_le32(page_bus + offset); offset = (offset + length) & ~PAGE_MASK; rest -= length; if (offset == 0) page++; } |
a186b4a6b
|
2174 2175 2176 |
pd->control = cpu_to_le16(DESCRIPTOR_STATUS | DESCRIPTOR_INPUT_LAST | DESCRIPTOR_BRANCH_ALWAYS); |
bcee893c6
|
2177 |
if (p->interrupt && i == packet_count - 1) |
a186b4a6b
|
2178 |
pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); |
a186b4a6b
|
2179 2180 2181 2182 2183 2184 2185 |
context_append(&ctx->context, d, z, header_z); } return 0; } static int |
295e3feb9
|
2186 2187 2188 2189 2190 |
ohci_queue_iso(struct fw_iso_context *base, struct fw_iso_packet *packet, struct fw_iso_buffer *buffer, unsigned long payload) { |
e364cf4e0
|
2191 |
struct iso_context *ctx = container_of(base, struct iso_context, base); |
fe5ca6343
|
2192 2193 |
unsigned long flags; int retval; |
e364cf4e0
|
2194 |
|
fe5ca6343
|
2195 |
spin_lock_irqsave(&ctx->context.ohci->lock, flags); |
295e3feb9
|
2196 |
if (base->type == FW_ISO_CONTEXT_TRANSMIT) |
fe5ca6343
|
2197 |
retval = ohci_queue_iso_transmit(base, packet, buffer, payload); |
95984f62c
|
2198 |
else if (ctx->context.ohci->use_dualbuffer) |
fe5ca6343
|
2199 |
retval = ohci_queue_iso_receive_dualbuffer(base, packet, |
d2746dc19
|
2200 |
buffer, payload); |
e364cf4e0
|
2201 |
else |
fe5ca6343
|
2202 |
retval = ohci_queue_iso_receive_packet_per_buffer(base, packet, |
a186b4a6b
|
2203 2204 |
buffer, payload); |
fe5ca6343
|
2205 2206 2207 |
spin_unlock_irqrestore(&ctx->context.ohci->lock, flags); return retval; |
295e3feb9
|
2208 |
} |
21ebcd122
|
2209 |
static const struct fw_card_driver ohci_driver = { |
ed5689122
|
2210 2211 2212 2213 2214 |
.enable = ohci_enable, .update_phy_reg = ohci_update_phy_reg, .set_config_rom = ohci_set_config_rom, .send_request = ohci_send_request, .send_response = ohci_send_response, |
730c32f58
|
2215 |
.cancel_packet = ohci_cancel_packet, |
ed5689122
|
2216 |
.enable_phys_dma = ohci_enable_phys_dma, |
d60d7f1d5
|
2217 |
.get_bus_time = ohci_get_bus_time, |
ed5689122
|
2218 2219 2220 2221 |
.allocate_iso_context = ohci_allocate_iso_context, .free_iso_context = ohci_free_iso_context, .queue_iso = ohci_queue_iso, |
69cdb7268
|
2222 |
.start_iso = ohci_start_iso, |
b82956685
|
2223 |
.stop_iso = ohci_stop_iso, |
ed5689122
|
2224 |
}; |
ea8d006b9
|
2225 |
#ifdef CONFIG_PPC_PMAC |
2ed0f181f
|
2226 2227 |
static void ohci_pmac_on(struct pci_dev *dev) { |
ea8d006b9
|
2228 2229 2230 2231 2232 2233 2234 2235 |
if (machine_is(powermac)) { struct device_node *ofn = pci_device_to_OF_node(dev); if (ofn) { pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1); pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1); } } |
2ed0f181f
|
2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 |
} static void ohci_pmac_off(struct pci_dev *dev) { if (machine_is(powermac)) { struct device_node *ofn = pci_device_to_OF_node(dev); if (ofn) { pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0); pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0); } } } #else #define ohci_pmac_on(dev) #define ohci_pmac_off(dev) |
ea8d006b9
|
2252 |
#endif /* CONFIG_PPC_PMAC */ |
2ed0f181f
|
2253 2254 2255 2256 |
static int __devinit pci_probe(struct pci_dev *dev, const struct pci_device_id *ent) { struct fw_ohci *ohci; |
95984f62c
|
2257 |
u32 bus_options, max_receive, link_speed, version; |
2ed0f181f
|
2258 2259 2260 |
u64 guid; int err; size_t size; |
2d826cc5c
|
2261 |
ohci = kzalloc(sizeof(*ohci), GFP_KERNEL); |
ed5689122
|
2262 2263 2264 2265 2266 2267 2268 |
if (ohci == NULL) { fw_error("Could not malloc fw_ohci data. "); return -ENOMEM; } fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); |
130d5496e
|
2269 |
ohci_pmac_on(dev); |
d79406dd1
|
2270 2271 |
err = pci_enable_device(dev); if (err) { |
ed5689122
|
2272 2273 |
fw_error("Failed to enable OHCI hardware. "); |
bd7dee631
|
2274 |
goto fail_free; |
ed5689122
|
2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 |
} pci_set_master(dev); pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); pci_set_drvdata(dev, ohci); spin_lock_init(&ohci->lock); tasklet_init(&ohci->bus_reset_tasklet, bus_reset_tasklet, (unsigned long)ohci); |
d79406dd1
|
2285 2286 |
err = pci_request_region(dev, 0, ohci_driver_name); if (err) { |
ed5689122
|
2287 2288 |
fw_error("MMIO resource unavailable "); |
d79406dd1
|
2289 |
goto fail_disable; |
ed5689122
|
2290 2291 2292 2293 2294 2295 |
} ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE); if (ohci->registers == NULL) { fw_error("Failed to remap registers "); |
d79406dd1
|
2296 2297 |
err = -ENXIO; goto fail_iomem; |
ed5689122
|
2298 |
} |
95984f62c
|
2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 |
version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; ohci->use_dualbuffer = version >= OHCI_VERSION_1_1; /* x86-32 currently doesn't use highmem for dma_alloc_coherent */ #if !defined(CONFIG_X86_32) /* dual-buffer mode is broken with descriptor addresses above 2G */ if (dev->vendor == PCI_VENDOR_ID_TI && dev->device == PCI_DEVICE_ID_TI_TSB43AB22) ohci->use_dualbuffer = false; #endif #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE && dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW; #endif ohci->bus_reset_packet_quirk = dev->vendor == PCI_VENDOR_ID_TI; |
ed5689122
|
2315 2316 2317 2318 2319 |
ar_context_init(&ohci->ar_request_ctx, ohci, OHCI1394_AsReqRcvContextControlSet); ar_context_init(&ohci->ar_response_ctx, ohci, OHCI1394_AsRspRcvContextControlSet); |
fe5ca6343
|
2320 |
context_init(&ohci->at_request_ctx, ohci, |
f319b6a02
|
2321 |
OHCI1394_AsReqTrContextControlSet, handle_at_packet); |
ed5689122
|
2322 |
|
fe5ca6343
|
2323 |
context_init(&ohci->at_response_ctx, ohci, |
f319b6a02
|
2324 |
OHCI1394_AsRspTrContextControlSet, handle_at_packet); |
ed5689122
|
2325 |
|
ed5689122
|
2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 |
reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask); ohci->it_context_list = kzalloc(size, GFP_KERNEL); reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask); ohci->ir_context_list = kzalloc(size, GFP_KERNEL); if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) { fw_error("Out of memory for it/ir contexts. "); |
d79406dd1
|
2341 2342 |
err = -ENOMEM; goto fail_registers; |
ed5689122
|
2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 |
} /* self-id dma buffer allocation */ ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device, SELF_ID_BUF_SIZE, &ohci->self_id_bus, GFP_KERNEL); if (ohci->self_id_cpu == NULL) { fw_error("Out of memory for self ID buffer. "); |
d79406dd1
|
2353 2354 |
err = -ENOMEM; goto fail_registers; |
ed5689122
|
2355 |
} |
ed5689122
|
2356 2357 2358 2359 2360 |
bus_options = reg_read(ohci, OHCI1394_BusOptions); max_receive = (bus_options >> 12) & 0xf; link_speed = bus_options & 0x7; guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | reg_read(ohci, OHCI1394_GUIDLo); |
d79406dd1
|
2361 2362 2363 |
err = fw_card_add(&ohci->card, max_receive, link_speed, guid); if (err < 0) goto fail_self_id; |
ed5689122
|
2364 |
|
500be7251
|
2365 2366 |
fw_notify("Added fw-ohci device %s, OHCI version %x.%x ", |
95984f62c
|
2367 |
dev->dev.bus_id, version >> 16, version & 0xff); |
ed5689122
|
2368 |
return 0; |
d79406dd1
|
2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 |
fail_self_id: dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, ohci->self_id_cpu, ohci->self_id_bus); fail_registers: kfree(ohci->it_context_list); kfree(ohci->ir_context_list); pci_iounmap(dev, ohci->registers); fail_iomem: pci_release_region(dev, 0); fail_disable: pci_disable_device(dev); |
bd7dee631
|
2381 2382 |
fail_free: kfree(&ohci->card); |
130d5496e
|
2383 |
ohci_pmac_off(dev); |
d79406dd1
|
2384 2385 |
return err; |
ed5689122
|
2386 2387 2388 2389 2390 2391 2392 |
} static void pci_remove(struct pci_dev *dev) { struct fw_ohci *ohci; ohci = pci_get_drvdata(dev); |
e254a4b45
|
2393 2394 |
reg_write(ohci, OHCI1394_IntMaskClear, ~0); flush_writes(ohci); |
ed5689122
|
2395 |
fw_core_remove_card(&ohci->card); |
c781c06d1
|
2396 2397 2398 2399 |
/* * FIXME: Fail all pending packets here, now that the upper * layers can't queue any more. */ |
ed5689122
|
2400 2401 2402 |
software_reset(ohci); free_irq(dev->irq, ohci); |
d79406dd1
|
2403 2404 2405 2406 2407 2408 2409 |
dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, ohci->self_id_cpu, ohci->self_id_bus); kfree(ohci->it_context_list); kfree(ohci->ir_context_list); pci_iounmap(dev, ohci->registers); pci_release_region(dev, 0); pci_disable_device(dev); |
bd7dee631
|
2410 |
kfree(&ohci->card); |
2ed0f181f
|
2411 |
ohci_pmac_off(dev); |
ea8d006b9
|
2412 |
|
ed5689122
|
2413 2414 2415 |
fw_notify("Removed fw-ohci device. "); } |
2aef469a3
|
2416 |
#ifdef CONFIG_PM |
2ed0f181f
|
2417 |
static int pci_suspend(struct pci_dev *dev, pm_message_t state) |
2aef469a3
|
2418 |
{ |
2ed0f181f
|
2419 |
struct fw_ohci *ohci = pci_get_drvdata(dev); |
2aef469a3
|
2420 2421 2422 |
int err; software_reset(ohci); |
2ed0f181f
|
2423 2424 |
free_irq(dev->irq, ohci); err = pci_save_state(dev); |
2aef469a3
|
2425 |
if (err) { |
8a8cea273
|
2426 2427 |
fw_error("pci_save_state failed "); |
2aef469a3
|
2428 2429 |
return err; } |
2ed0f181f
|
2430 |
err = pci_set_power_state(dev, pci_choose_state(dev, state)); |
551114287
|
2431 2432 2433 |
if (err) fw_error("pci_set_power_state failed with %d ", err); |
2ed0f181f
|
2434 |
ohci_pmac_off(dev); |
ea8d006b9
|
2435 |
|
2aef469a3
|
2436 2437 |
return 0; } |
2ed0f181f
|
2438 |
static int pci_resume(struct pci_dev *dev) |
2aef469a3
|
2439 |
{ |
2ed0f181f
|
2440 |
struct fw_ohci *ohci = pci_get_drvdata(dev); |
2aef469a3
|
2441 |
int err; |
2ed0f181f
|
2442 2443 2444 2445 |
ohci_pmac_on(dev); pci_set_power_state(dev, PCI_D0); pci_restore_state(dev); err = pci_enable_device(dev); |
2aef469a3
|
2446 |
if (err) { |
8a8cea273
|
2447 2448 |
fw_error("pci_enable_device failed "); |
2aef469a3
|
2449 2450 |
return err; } |
0bd243c4d
|
2451 |
return ohci_enable(&ohci->card, NULL, 0); |
2aef469a3
|
2452 2453 |
} #endif |
ed5689122
|
2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 |
static struct pci_device_id pci_table[] = { { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, { } }; MODULE_DEVICE_TABLE(pci, pci_table); static struct pci_driver fw_ohci_pci_driver = { .name = ohci_driver_name, .id_table = pci_table, .probe = pci_probe, .remove = pci_remove, |
2aef469a3
|
2466 2467 2468 2469 |
#ifdef CONFIG_PM .resume = pci_resume, .suspend = pci_suspend, #endif |
ed5689122
|
2470 2471 2472 2473 2474 |
}; MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); MODULE_LICENSE("GPL"); |
1e4c7b0da
|
2475 2476 2477 2478 |
/* Provide a module alias so root-on-sbp2 initrds don't break. */ #ifndef CONFIG_IEEE1394_OHCI1394_MODULE MODULE_ALIAS("ohci1394"); #endif |
ed5689122
|
2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 |
static int __init fw_ohci_init(void) { return pci_register_driver(&fw_ohci_pci_driver); } static void __exit fw_ohci_cleanup(void) { pci_unregister_driver(&fw_ohci_pci_driver); } module_init(fw_ohci_init); module_exit(fw_ohci_cleanup); |