#ifndef MFD_TMIO_H
  #define MFD_TMIO_H

  #include <linux/fb.h>

  #include <linux/io.h>
  #include <linux/platform_device.h>

  #define tmio_ioread8(addr) readb(addr)
  #define tmio_ioread16(addr) readw(addr)
  #define tmio_ioread16_rep(r, b, l) readsw(r, b, l)
  #define tmio_ioread32(addr) \
  	(((u32) readw((addr))) | (((u32) readw((addr) + 2)) << 16))
  
  #define tmio_iowrite8(val, addr) writeb((val), (addr))
  #define tmio_iowrite16(val, addr) writew((val), (addr))
  #define tmio_iowrite16_rep(r, b, l) writesw(r, b, l)
  #define tmio_iowrite32(val, addr) \
  	do { \
  	writew((val),       (addr)); \
  	writew((val) >> 16, (addr) + 2); \
  	} while (0)

  #define CNF_CMD     0x04
  #define CNF_CTL_BASE   0x10
  #define CNF_INT_PIN  0x3d
  #define CNF_STOP_CLK_CTL 0x40
  #define CNF_GCLK_CTL 0x41
  #define CNF_SD_CLK_MODE 0x42
  #define CNF_PIN_STATUS 0x44
  #define CNF_PWR_CTL_1 0x48
  #define CNF_PWR_CTL_2 0x49
  #define CNF_PWR_CTL_3 0x4a
  #define CNF_CARD_DETECT_MODE 0x4c
  #define CNF_SD_SLOT 0x50
  #define CNF_EXT_GCLK_CTL_1 0xf0
  #define CNF_EXT_GCLK_CTL_2 0xf1
  #define CNF_EXT_GCLK_CTL_3 0xf9
  #define CNF_SD_LED_EN_1 0xfa
  #define CNF_SD_LED_EN_2 0xfe
  
  #define   SDCREN 0x2   /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/
  
  #define sd_config_write8(base, shift, reg, val) \
  	tmio_iowrite8((val), (base) + ((reg) << (shift)))
  #define sd_config_write16(base, shift, reg, val) \
  	tmio_iowrite16((val), (base) + ((reg) << (shift)))
  #define sd_config_write32(base, shift, reg, val) \
  	do { \
  		tmio_iowrite16((val), (base) + ((reg) << (shift)));   \
  		tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \
  	} while (0)

  /* tmio MMC platform flags */
  #define TMIO_MMC_WRPROTECT_DISABLE	(1 << 0)

  int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
  int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
  void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
  void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);

  struct tmio_mmc_dma {
  	void *chan_priv_tx;
  	void *chan_priv_rx;
  };

  /*

   * data for the MMC controller
   */
  struct tmio_mmc_data {

  	unsigned int			hclk;

  	unsigned long			capabilities;

  	unsigned long			flags;

  	u32				ocr_mask;	/* available voltages */

  	struct tmio_mmc_dma		*dma;

  	void (*set_pwr)(struct platform_device *host, int state);
  	void (*set_clk_div)(struct platform_device *host, int state);

  };
  
  /*

   * data for the NAND controller
   */
  struct tmio_nand_data {
  	struct nand_bbt_descr	*badblock_pattern;
  	struct mtd_partition	*partition;
  	unsigned int		num_partitions;
  };

  #define FBIO_TMIO_ACC_WRITE	0x7C639300
  #define FBIO_TMIO_ACC_SYNC	0x7C639301
  
  struct tmio_fb_data {
  	int			(*lcd_set_power)(struct platform_device *fb_dev,
  								bool on);
  	int			(*lcd_mode)(struct platform_device *fb_dev,
  					const struct fb_videomode *mode);
  	int			num_modes;
  	struct fb_videomode	*modes;
  
  	/* in mm: size of screen */
  	int			height;
  	int			width;
  };

  #endif