Doug / smarc-fsl-linux-kernel | Embedian Git Server

Commit 0082c16e3a6d87c7b156ccf21f5e6c448b102809

Authored by Linus Torvalds 2012-07-27 03:57:41 +0800

Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches

Merge tag 'spi-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/misc

Pull spi updates from Mark Brown:
 "Since Grant is even more specacularly busy than usual for the time
  being I've been collecting SPI patches for him for this release -
  probably things will revert back to Grant before the next release.

  There's nothing too exciting here, mostly it's simple driver specific
  stuff:

   - Add spi: to the modaliases of SPI devices to provide namespacing.
   - A driver for AD-FMCOMMS1-EBZ.
   - DT binding for Orion.
   - Fixes and cleanups for i.MX, PL0022, OMAP and bitbang drivers.

   There may be a few more fixes I've missed, people keep sending me new
   things."

* tag 'spi-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/misc:
  spi/orion: remove uneeded spi_info
  spi/bcm63xx: fix clock configuration selection
  spi/orion: add device tree binding
  spi/omap2: mark omap2_mcspi_master_setup as __devinit
  spi: omap2-mcspi: Fix the below warning
  spi: Add AD-FMCOMMS1-EBZ I2C-SPI bridge driver
  spi/imx: use gpio_is_valid to determine if a gpio is valid
  spi/imx: remove redundant config.speed_hz setting
  spi/gpio: start with CS non-active
  spi: tegra: use dmaengine based dma driver
  spi/pl022: cleanup pl022 header documentation
  spi/pl022: enable runtime PM
  spi/pl022: delete DB5500 support
  spi/pl022: disable port when unused
  spi: Add "spi:" prefix to modalias attribute of spi devices

Showing 13 changed files Inline Diff

Documentation/devicetree/bindings/spi/spi-orion.txt
drivers/spi/Kconfig
drivers/spi/Makefile
drivers/spi/spi-bcm63xx.c
drivers/spi/spi-gpio.c
drivers/spi/spi-imx.c
drivers/spi/spi-omap2-mcspi.c
drivers/spi/spi-orion.c
drivers/spi/spi-pl022.c
drivers/spi/spi-tegra.c
drivers/spi/spi-xcomm.c
drivers/spi/spi.c
include/linux/amba/pl022.h

Documentation/devicetree/bindings/spi/spi-orion.txt

Diff comments View file @ 0082c16

File was created	1	Marvell Orion SPI device
	2
	3	Required properties:
	4	- compatible : should be "marvell,orion-spi".
	5	- reg : offset and length of the register set for the device
	6	- cell-index : Which of multiple SPI controllers is this.
	7	Optional properties:
	8	- interrupts : Is currently not used.
	9
	10	Example:
	11	spi@10600 {
	12	compatible = "marvell,orion-spi";
	13	#address-cells = <1>;
	14	#size-cells = <0>;
	15	cell-index = <0>;
	16	reg = <0x10600 0x28>;
	17	interrupts = <23>;
	18	status = "disabled";
	19	};
	20

drivers/spi/Kconfig

Diff comments View file @ 0082c16

 #
 # SPI driver configuration
 #
 # NOTE:  the reason this doesn't show SPI slave support is mostly that
 # nobody's needed a slave side API yet.  The master-role API is not
 # fully appropriate there, so it'd need some thought to do well.
 #
 menuconfig SPI
 	bool "SPI support"
 	depends on HAS_IOMEM
 	help
 	  The "Serial Peripheral Interface" is a low level synchronous
 	  protocol.  Chips that support SPI can have data transfer rates
 	  up to several tens of Mbit/sec.  Chips are addressed with a
 	  controller and a chipselect.  Most SPI slaves don't support
 	  dynamic device discovery; some are even write-only or read-only.
 	  SPI is widely used by microcontrollers to talk with sensors,
 	  eeprom and flash memory, codecs and various other controller
 	  chips, analog to digital (and d-to-a) converters, and more.
 	  MMC and SD cards can be accessed using SPI protocol; and for
 	  DataFlash cards used in MMC sockets, SPI must always be used.
 	  SPI is one of a family of similar protocols using a four wire
 	  interface (select, clock, data in, data out) including Microwire
 	  (half duplex), SSP, SSI, and PSP.  This driver framework should
 	  work with most such devices and controllers.
 if SPI
 config SPI_DEBUG
 	boolean "Debug support for SPI drivers"
 	depends on DEBUG_KERNEL
 	help
 	  Say "yes" to enable debug messaging (like dev_dbg and pr_debug),
 	  sysfs, and debugfs support in SPI controller and protocol drivers.
 #
 # MASTER side ... talking to discrete SPI slave chips including microcontrollers
 #
 config SPI_MASTER
 #	boolean "SPI Master Support"
 	boolean
 	default SPI
 	help
 	  If your system has an master-capable SPI controller (which
 	  provides the clock and chipselect), you can enable that
 	  controller and the protocol drivers for the SPI slave chips
 	  that are connected.
 if SPI_MASTER
 comment "SPI Master Controller Drivers"
 config SPI_ALTERA
 	tristate "Altera SPI Controller"
 	select SPI_BITBANG
 	help
 	  This is the driver for the Altera SPI Controller.
 config SPI_ATH79
 	tristate "Atheros AR71XX/AR724X/AR913X SPI controller driver"
 	depends on ATH79 && GENERIC_GPIO
 	select SPI_BITBANG
 	help
 	  This enables support for the SPI controller present on the
 	  Atheros AR71XX/AR724X/AR913X SoCs.
 config SPI_ATMEL
 	tristate "Atmel SPI Controller"
 	depends on (ARCH_AT91 || AVR32)
 	help
 	  This selects a driver for the Atmel SPI Controller, present on
 	  many AT32 (AVR32) and AT91 (ARM) chips.
 config SPI_BFIN5XX
 	tristate "SPI controller driver for ADI Blackfin5xx"
 	depends on BLACKFIN
 	help
 	  This is the SPI controller master driver for Blackfin 5xx processor.
 config SPI_BFIN_SPORT
 	tristate "SPI bus via Blackfin SPORT"
 	depends on BLACKFIN
 	help
 	  Enable support for a SPI bus via the Blackfin SPORT peripheral.
 config SPI_AU1550
 	tristate "Au1550/Au1200/Au1300 SPI Controller"
 	depends on MIPS_ALCHEMY && EXPERIMENTAL
 	select SPI_BITBANG
 	help
 	  If you say yes to this option, support will be included for the
 	  PSC SPI controller found on Au1550, Au1200 and Au1300 series.
 config SPI_BCM63XX
 	tristate "Broadcom BCM63xx SPI controller"
 	depends on BCM63XX
 	help
           Enable support for the SPI controller on the Broadcom BCM63xx SoCs.
 config SPI_BITBANG
 	tristate "Utilities for Bitbanging SPI masters"
 	help
 	  With a few GPIO pins, your system can bitbang the SPI protocol.
 	  Select this to get SPI support through I/O pins (GPIO, parallel
 	  port, etc).  Or, some systems' SPI master controller drivers use
 	  this code to manage the per-word or per-transfer accesses to the
 	  hardware shift registers.
 	  This is library code, and is automatically selected by drivers that
 	  need it.  You only need to select this explicitly to support driver
 	  modules that aren't part of this kernel tree.
 config SPI_BUTTERFLY
 	tristate "Parallel port adapter for AVR Butterfly (DEVELOPMENT)"
 	depends on PARPORT
 	select SPI_BITBANG
 	help
 	  This uses a custom parallel port cable to connect to an AVR
 	  Butterfly <http://www.atmel.com/products/avr/butterfly>, an
 	  inexpensive battery powered microcontroller evaluation board.
 	  This same cable can be used to flash new firmware.
 config SPI_COLDFIRE_QSPI
 	tristate "Freescale Coldfire QSPI controller"
 	depends on (M520x || M523x || M5249 || M525x || M527x || M528x || M532x)
 	help
 	  This enables support for the Coldfire QSPI controller in master
 	  mode.
 config SPI_DAVINCI
 	tristate "Texas Instruments DaVinci/DA8x/OMAP-L/AM1x SoC SPI controller"
 	depends on ARCH_DAVINCI
 	select SPI_BITBANG
 	help
 	  SPI master controller for DaVinci/DA8x/OMAP-L/AM1x SPI modules.
 config SPI_EP93XX
 	tristate "Cirrus Logic EP93xx SPI controller"
 	depends on ARCH_EP93XX
 	help
 	  This enables using the Cirrus EP93xx SPI controller in master
 	  mode.
 config SPI_GPIO
 	tristate "GPIO-based bitbanging SPI Master"
 	depends on GENERIC_GPIO
 	select SPI_BITBANG
 	help
 	  This simple GPIO bitbanging SPI master uses the arch-neutral GPIO
 	  interface to manage MOSI, MISO, SCK, and chipselect signals.  SPI
 	  slaves connected to a bus using this driver are configured as usual,
 	  except that the spi_board_info.controller_data holds the GPIO number
 	  for the chipselect used by this controller driver.
 	  Note that this driver often won't achieve even 1 Mbit/sec speeds,
 	  making it unusually slow for SPI.  If your platform can inline
 	  GPIO operations, you should be able to leverage that for better
 	  speed with a custom version of this driver; see the source code.
 config SPI_IMX
 	tristate "Freescale i.MX SPI controllers"
 	depends on ARCH_MXC
 	select SPI_BITBANG
 	default m if IMX_HAVE_PLATFORM_SPI_IMX
 	help
 	  This enables using the Freescale i.MX SPI controllers in master
 	  mode.
 config SPI_LM70_LLP
 	tristate "Parallel port adapter for LM70 eval board (DEVELOPMENT)"
 	depends on PARPORT && EXPERIMENTAL
 	select SPI_BITBANG
 	help
 	  This driver supports the NS LM70 LLP Evaluation Board,
 	  which interfaces to an LM70 temperature sensor using
 	  a parallel port.
 config SPI_MPC52xx
 	tristate "Freescale MPC52xx SPI (non-PSC) controller support"
 	depends on PPC_MPC52xx
 	help
 	  This drivers supports the MPC52xx SPI controller in master SPI
 	  mode.
 config SPI_MPC52xx_PSC
 	tristate "Freescale MPC52xx PSC SPI controller"
 	depends on PPC_MPC52xx && EXPERIMENTAL
 	help
 	  This enables using the Freescale MPC52xx Programmable Serial
 	  Controller in master SPI mode.
 config SPI_MPC512x_PSC
 	tristate "Freescale MPC512x PSC SPI controller"
 	depends on PPC_MPC512x
 	help
 	  This enables using the Freescale MPC5121 Programmable Serial
 	  Controller in SPI master mode.
 config SPI_FSL_LIB
 	tristate
 	depends on FSL_SOC
 config SPI_FSL_SPI
 	bool "Freescale SPI controller"
 	depends on FSL_SOC
 	select SPI_FSL_LIB
 	help
 	  This enables using the Freescale SPI controllers in master mode.
 	  MPC83xx platform uses the controller in cpu mode or CPM/QE mode.
 	  MPC8569 uses the controller in QE mode, MPC8610 in cpu mode.
 config SPI_FSL_ESPI
 	bool "Freescale eSPI controller"
 	depends on FSL_SOC
 	select SPI_FSL_LIB
 	help
 	  This enables using the Freescale eSPI controllers in master mode.
 	  From MPC8536, 85xx platform uses the controller, and all P10xx,
 	  P20xx, P30xx,P40xx, P50xx uses this controller.
 config SPI_OC_TINY
 	tristate "OpenCores tiny SPI"
 	depends on GENERIC_GPIO
 	select SPI_BITBANG
 	help
 	  This is the driver for OpenCores tiny SPI master controller.
 config SPI_OMAP_UWIRE
 	tristate "OMAP1 MicroWire"
 	depends on ARCH_OMAP1
 	select SPI_BITBANG
 	help
 	  This hooks up to the MicroWire controller on OMAP1 chips.
 config SPI_OMAP24XX
 	tristate "McSPI driver for OMAP"
 	depends on ARCH_OMAP2PLUS
 	help
 	  SPI master controller for OMAP24XX and later Multichannel SPI
 	  (McSPI) modules.
 config SPI_OMAP_100K
 	tristate "OMAP SPI 100K"
 	depends on ARCH_OMAP850 || ARCH_OMAP730
 	help
 	  OMAP SPI 100K master controller for omap7xx boards.
 config SPI_ORION
 	tristate "Orion SPI master (EXPERIMENTAL)"
 	depends on PLAT_ORION && EXPERIMENTAL
 	help
 	  This enables using the SPI master controller on the Orion chips.
 config SPI_PL022
 	tristate "ARM AMBA PL022 SSP controller"
 	depends on ARM_AMBA
 	default y if MACH_U300
 	default y if ARCH_REALVIEW
 	default y if INTEGRATOR_IMPD1
 	default y if ARCH_VERSATILE
 	help
 	  This selects the ARM(R) AMBA(R) PrimeCell PL022 SSP
 	  controller. If you have an embedded system with an AMBA(R)
 	  bus and a PL022 controller, say Y or M here.
 config SPI_PPC4xx
 	tristate "PPC4xx SPI Controller"
 	depends on PPC32 && 4xx
 	select SPI_BITBANG
 	help
 	  This selects a driver for the PPC4xx SPI Controller.
 config SPI_PXA2XX
 	tristate "PXA2xx SSP SPI master"
 	depends on (ARCH_PXA || (X86_32 && PCI)) && EXPERIMENTAL
 	select PXA_SSP if ARCH_PXA
 	help
 	  This enables using a PXA2xx or Sodaville SSP port as a SPI master
 	  controller. The driver can be configured to use any SSP port and
 	  additional documentation can be found a Documentation/spi/pxa2xx.
 config SPI_PXA2XX_PCI
 	def_bool SPI_PXA2XX && X86_32 && PCI
 config SPI_RSPI
 	tristate "Renesas RSPI controller"
 	depends on SUPERH
 	help
 	  SPI driver for Renesas RSPI blocks.
 config SPI_S3C24XX
 	tristate "Samsung S3C24XX series SPI"
 	depends on ARCH_S3C24XX && EXPERIMENTAL
 	select SPI_BITBANG
 	help
 	  SPI driver for Samsung S3C24XX series ARM SoCs
 config SPI_S3C24XX_FIQ
 	bool "S3C24XX driver with FIQ pseudo-DMA"
 	depends on SPI_S3C24XX
 	select FIQ
 	help
 	  Enable FIQ support for the S3C24XX SPI driver to provide pseudo
 	  DMA by using the fast-interrupt request framework, This allows
 	  the driver to get DMA-like performance when there are either
 	  no free DMA channels, or when doing transfers that required both
 	  TX and RX data paths.
 config SPI_S3C64XX
 	tristate "Samsung S3C64XX series type SPI"
 	depends on (ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5P64X0 || ARCH_EXYNOS)
 	select S3C64XX_DMA if ARCH_S3C64XX
 	help
 	  SPI driver for Samsung S3C64XX and newer SoCs.
 config SPI_SH_MSIOF
 	tristate "SuperH MSIOF SPI controller"
 	depends on SUPERH && HAVE_CLK
 	select SPI_BITBANG
 	help
 	  SPI driver for SuperH MSIOF blocks.
 config SPI_SH
 	tristate "SuperH SPI controller"
 	depends on SUPERH
 	help
 	  SPI driver for SuperH SPI blocks.
 config SPI_SH_SCI
 	tristate "SuperH SCI SPI controller"
 	depends on SUPERH
 	select SPI_BITBANG
 	help
 	  SPI driver for SuperH SCI blocks.
 config SPI_SH_HSPI
 	tristate "SuperH HSPI controller"
 	depends on ARCH_SHMOBILE
 	help
 	  SPI driver for SuperH HSPI blocks.
 config SPI_SIRF
 	tristate "CSR SiRFprimaII SPI controller"
 	depends on ARCH_PRIMA2
 	select SPI_BITBANG
 	help
 	  SPI driver for CSR SiRFprimaII SoCs
 config SPI_STMP3XXX
 	tristate "Freescale STMP37xx/378x SPI/SSP controller"
 	depends on ARCH_STMP3XXX
 	help
 	  SPI driver for Freescale STMP37xx/378x SoC SSP interface
 config SPI_TEGRA
 	tristate "Nvidia Tegra SPI controller"
-	depends on ARCH_TEGRA && TEGRA_SYSTEM_DMA
+	depends on ARCH_TEGRA && (TEGRA_SYSTEM_DMA || TEGRA20_APB_DMA)
 	help
 	  SPI driver for NVidia Tegra SoCs
 config SPI_TI_SSP
 	tristate "TI Sequencer Serial Port - SPI Support"
 	depends on MFD_TI_SSP
 	help
 	  This selects an SPI master implementation using a TI sequencer
 	  serial port.
 config SPI_TOPCLIFF_PCH
 	tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) SPI"
 	depends on PCI
 	help
 	  SPI driver for the Topcliff PCH (Platform Controller Hub) SPI bus
 	  used in some x86 embedded processors.
 	  This driver also supports the ML7213/ML7223/ML7831, a companion chip
 	  for the Atom E6xx series and compatible with the Intel EG20T PCH.
 config SPI_TXX9
 	tristate "Toshiba TXx9 SPI controller"
 	depends on GENERIC_GPIO && CPU_TX49XX
 	help
 	  SPI driver for Toshiba TXx9 MIPS SoCs
+config SPI_XCOMM
+	tristate "Analog Devices AD-FMCOMMS1-EBZ SPI-I2C-bridge driver"
+	depends on I2C
+	help
+	  Support for the SPI-I2C bridge found on the Analog Devices
+	  AD-FMCOMMS1-EBZ board.
 config SPI_XILINX
 	tristate "Xilinx SPI controller common module"
 	depends on HAS_IOMEM && EXPERIMENTAL
 	select SPI_BITBANG
 	help
 	  This exposes the SPI controller IP from the Xilinx EDK.
 	  See the "OPB Serial Peripheral Interface (SPI) (v1.00e)"
 	  Product Specification document (DS464) for hardware details.
 	  Or for the DS570, see "XPS Serial Peripheral Interface (SPI) (v2.00b)"
 config SPI_NUC900
 	tristate "Nuvoton NUC900 series SPI"
 	depends on ARCH_W90X900 && EXPERIMENTAL
 	select SPI_BITBANG
 	help
 	  SPI driver for Nuvoton NUC900 series ARM SoCs
 #
 # Add new SPI master controllers in alphabetical order above this line
 #
 config SPI_DESIGNWARE
 	tristate "DesignWare SPI controller core support"
 	help
 	  general driver for SPI controller core from DesignWare
 config SPI_DW_PCI
 	tristate "PCI interface driver for DW SPI core"
 	depends on SPI_DESIGNWARE && PCI
 config SPI_DW_MID_DMA
 	bool "DMA support for DW SPI controller on Intel Moorestown platform"
 	depends on SPI_DW_PCI && INTEL_MID_DMAC
 config SPI_DW_MMIO
 	tristate "Memory-mapped io interface driver for DW SPI core"
 	depends on SPI_DESIGNWARE && HAVE_CLK
 #
 # There are lots of SPI device types, with sensors and memory
 # being probably the most widely used ones.
 #
 comment "SPI Protocol Masters"
 config SPI_SPIDEV
 	tristate "User mode SPI device driver support"
 	depends on EXPERIMENTAL
 	help
 	  This supports user mode SPI protocol drivers.
 	  Note that this application programming interface is EXPERIMENTAL
 	  and hence SUBJECT TO CHANGE WITHOUT NOTICE while it stabilizes.
 config SPI_TLE62X0
 	tristate "Infineon TLE62X0 (for power switching)"
 	depends on SYSFS
 	help
 	  SPI driver for Infineon TLE62X0 series line driver chips,
 	  such as the TLE6220, TLE6230 and TLE6240.  This provides a
 	  sysfs interface, with each line presented as a kind of GPIO
 	  exposing both switch control and diagnostic feedback.
 #
 # Add new SPI protocol masters in alphabetical order above this line
 #
 endif # SPI_MASTER
 # (slave support would go here)
 endif # SPI

drivers/spi/Makefile

Diff comments View file @ 0082c16

 #
 # Makefile for kernel SPI drivers.
 #
 ccflags-$(CONFIG_SPI_DEBUG) := -DDEBUG
 # small core, mostly translating board-specific
 # config declarations into driver model code
 obj-$(CONFIG_SPI_MASTER)		+= spi.o
 obj-$(CONFIG_SPI_SPIDEV)		+= spidev.o
 # SPI master controller drivers (bus)
 obj-$(CONFIG_SPI_ALTERA)		+= spi-altera.o
 obj-$(CONFIG_SPI_ATMEL)			+= spi-atmel.o
 obj-$(CONFIG_SPI_ATH79)			+= spi-ath79.o
 obj-$(CONFIG_SPI_AU1550)		+= spi-au1550.o
 obj-$(CONFIG_SPI_BCM63XX)		+= spi-bcm63xx.o
 obj-$(CONFIG_SPI_BFIN5XX)		+= spi-bfin5xx.o
 obj-$(CONFIG_SPI_BFIN_SPORT)		+= spi-bfin-sport.o
 obj-$(CONFIG_SPI_BITBANG)		+= spi-bitbang.o
 obj-$(CONFIG_SPI_BUTTERFLY)		+= spi-butterfly.o
 obj-$(CONFIG_SPI_COLDFIRE_QSPI)		+= spi-coldfire-qspi.o
 obj-$(CONFIG_SPI_DAVINCI)		+= spi-davinci.o
 obj-$(CONFIG_SPI_DESIGNWARE)		+= spi-dw.o
 obj-$(CONFIG_SPI_DW_MMIO)		+= spi-dw-mmio.o
 obj-$(CONFIG_SPI_DW_PCI)		+= spi-dw-midpci.o
 spi-dw-midpci-objs			:= spi-dw-pci.o spi-dw-mid.o
 obj-$(CONFIG_SPI_EP93XX)		+= spi-ep93xx.o
 obj-$(CONFIG_SPI_FSL_LIB)		+= spi-fsl-lib.o
 obj-$(CONFIG_SPI_FSL_ESPI)		+= spi-fsl-espi.o
 obj-$(CONFIG_SPI_FSL_SPI)		+= spi-fsl-spi.o
 obj-$(CONFIG_SPI_GPIO)			+= spi-gpio.o
 obj-$(CONFIG_SPI_IMX)			+= spi-imx.o
 obj-$(CONFIG_SPI_LM70_LLP)		+= spi-lm70llp.o
 obj-$(CONFIG_SPI_MPC512x_PSC)		+= spi-mpc512x-psc.o
 obj-$(CONFIG_SPI_MPC52xx_PSC)		+= spi-mpc52xx-psc.o
 obj-$(CONFIG_SPI_MPC52xx)		+= spi-mpc52xx.o
 obj-$(CONFIG_SPI_NUC900)		+= spi-nuc900.o
 obj-$(CONFIG_SPI_OC_TINY)		+= spi-oc-tiny.o
 obj-$(CONFIG_SPI_OMAP_UWIRE)		+= spi-omap-uwire.o
 obj-$(CONFIG_SPI_OMAP_100K)		+= spi-omap-100k.o
 obj-$(CONFIG_SPI_OMAP24XX)		+= spi-omap2-mcspi.o
 obj-$(CONFIG_SPI_ORION)			+= spi-orion.o
 obj-$(CONFIG_SPI_PL022)			+= spi-pl022.o
 obj-$(CONFIG_SPI_PPC4xx)		+= spi-ppc4xx.o
 obj-$(CONFIG_SPI_PXA2XX)		+= spi-pxa2xx.o
 obj-$(CONFIG_SPI_PXA2XX_PCI)		+= spi-pxa2xx-pci.o
 obj-$(CONFIG_SPI_RSPI)			+= spi-rspi.o
 obj-$(CONFIG_SPI_S3C24XX)		+= spi-s3c24xx-hw.o
 spi-s3c24xx-hw-y			:= spi-s3c24xx.o
 spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
 obj-$(CONFIG_SPI_S3C64XX)		+= spi-s3c64xx.o
 obj-$(CONFIG_SPI_SH)			+= spi-sh.o
 obj-$(CONFIG_SPI_SH_HSPI)		+= spi-sh-hspi.o
 obj-$(CONFIG_SPI_SH_MSIOF)		+= spi-sh-msiof.o
 obj-$(CONFIG_SPI_SH_SCI)		+= spi-sh-sci.o
 obj-$(CONFIG_SPI_SIRF)		+= spi-sirf.o
 obj-$(CONFIG_SPI_STMP3XXX)		+= spi-stmp.o
 obj-$(CONFIG_SPI_TEGRA)			+= spi-tegra.o
 obj-$(CONFIG_SPI_TI_SSP)		+= spi-ti-ssp.o
 obj-$(CONFIG_SPI_TLE62X0)		+= spi-tle62x0.o
 obj-$(CONFIG_SPI_TOPCLIFF_PCH)		+= spi-topcliff-pch.o
 obj-$(CONFIG_SPI_TXX9)			+= spi-txx9.o
+obj-$(CONFIG_SPI_XCOMM)		+= spi-xcomm.o
 obj-$(CONFIG_SPI_XILINX)		+= spi-xilinx.o

drivers/spi/spi-bcm63xx.c

Diff comments View file @ 0082c16

1	/*	1	/*
2	* Broadcom BCM63xx SPI controller support	2	* Broadcom BCM63xx SPI controller support
3	*	3	*
4	* Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>	4	* Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
5	* Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>	5	* Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
6	*	6	*
7	* This program is free software; you can redistribute it and/or	7	* This program is free software; you can redistribute it and/or
8	* modify it under the terms of the GNU General Public License	8	* modify it under the terms of the GNU General Public License
9	* as published by the Free Software Foundation; either version 2	9	* as published by the Free Software Foundation; either version 2
10	* of the License, or (at your option) any later version.	10	* of the License, or (at your option) any later version.
11	*	11	*
12	* This program is distributed in the hope that it will be useful,	12	* This program is distributed in the hope that it will be useful,
13	* but WITHOUT ANY WARRANTY; without even the implied warranty of	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15	* GNU General Public License for more details.	15	* GNU General Public License for more details.
16	*	16	*
17	* You should have received a copy of the GNU General Public License	17	* You should have received a copy of the GNU General Public License
18	* along with this program; if not, write to the	18	* along with this program; if not, write to the
19	* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,	19	* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
20	*/	20	*/
21		21
22	#include <linux/kernel.h>	22	#include <linux/kernel.h>
23	#include <linux/init.h>	23	#include <linux/init.h>
24	#include <linux/clk.h>	24	#include <linux/clk.h>
25	#include <linux/io.h>	25	#include <linux/io.h>
26	#include <linux/module.h>	26	#include <linux/module.h>
27	#include <linux/platform_device.h>	27	#include <linux/platform_device.h>
28	#include <linux/delay.h>	28	#include <linux/delay.h>
29	#include <linux/interrupt.h>	29	#include <linux/interrupt.h>
30	#include <linux/spi/spi.h>	30	#include <linux/spi/spi.h>
31	#include <linux/completion.h>	31	#include <linux/completion.h>
32	#include <linux/err.h>	32	#include <linux/err.h>
33	#include <linux/workqueue.h>	33	#include <linux/workqueue.h>
34	#include <linux/pm_runtime.h>	34	#include <linux/pm_runtime.h>
35		35
36	#include <bcm63xx_dev_spi.h>	36	#include <bcm63xx_dev_spi.h>
37		37
38	#define PFX KBUILD_MODNAME	38	#define PFX KBUILD_MODNAME
39	#define DRV_VER "0.1.2"	39	#define DRV_VER "0.1.2"
40		40
41	struct bcm63xx_spi {	41	struct bcm63xx_spi {
42	struct completion done;	42	struct completion done;
43		43
44	void __iomem *regs;	44	void __iomem *regs;
45	int irq;	45	int irq;
46		46
47	/* Platform data */	47	/* Platform data */
48	u32 speed_hz;	48	u32 speed_hz;
49	unsigned fifo_size;	49	unsigned fifo_size;
50		50
51	/* Data buffers */	51	/* Data buffers */
52	const unsigned char *tx_ptr;	52	const unsigned char *tx_ptr;
53	unsigned char *rx_ptr;	53	unsigned char *rx_ptr;
54		54
55	/* data iomem */	55	/* data iomem */
56	u8 __iomem *tx_io;	56	u8 __iomem *tx_io;
57	const u8 __iomem *rx_io;	57	const u8 __iomem *rx_io;
58		58
59	int remaining_bytes;	59	int remaining_bytes;
60		60
61	struct clk *clk;	61	struct clk *clk;
62	struct platform_device *pdev;	62	struct platform_device *pdev;
63	};	63	};
64		64
65	static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,	65	static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
66	unsigned int offset)	66	unsigned int offset)
67	{	67	{
68	return bcm_readb(bs->regs + bcm63xx_spireg(offset));	68	return bcm_readb(bs->regs + bcm63xx_spireg(offset));
69	}	69	}
70		70
71	static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,	71	static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
72	unsigned int offset)	72	unsigned int offset)
73	{	73	{
74	return bcm_readw(bs->regs + bcm63xx_spireg(offset));	74	return bcm_readw(bs->regs + bcm63xx_spireg(offset));
75	}	75	}
76		76
77	static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,	77	static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
78	u8 value, unsigned int offset)	78	u8 value, unsigned int offset)
79	{	79	{
80	bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));	80	bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
81	}	81	}
82		82
83	static inline void bcm_spi_writew(struct bcm63xx_spi *bs,	83	static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
84	u16 value, unsigned int offset)	84	u16 value, unsigned int offset)
85	{	85	{
86	bcm_writew(value, bs->regs + bcm63xx_spireg(offset));	86	bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
87	}	87	}
88		88
89	static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {	89	static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
90	{ 20000000, SPI_CLK_20MHZ },	90	{ 20000000, SPI_CLK_20MHZ },
91	{ 12500000, SPI_CLK_12_50MHZ },	91	{ 12500000, SPI_CLK_12_50MHZ },
92	{ 6250000, SPI_CLK_6_250MHZ },	92	{ 6250000, SPI_CLK_6_250MHZ },
93	{ 3125000, SPI_CLK_3_125MHZ },	93	{ 3125000, SPI_CLK_3_125MHZ },
94	{ 1563000, SPI_CLK_1_563MHZ },	94	{ 1563000, SPI_CLK_1_563MHZ },
95	{ 781000, SPI_CLK_0_781MHZ },	95	{ 781000, SPI_CLK_0_781MHZ },
96	{ 391000, SPI_CLK_0_391MHZ }	96	{ 391000, SPI_CLK_0_391MHZ }
97	};	97	};
98		98
99	static int bcm63xx_spi_check_transfer(struct spi_device *spi,	99	static int bcm63xx_spi_check_transfer(struct spi_device *spi,
100	struct spi_transfer *t)	100	struct spi_transfer *t)
101	{	101	{
102	u8 bits_per_word;	102	u8 bits_per_word;
103		103
104	bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;	104	bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
105	if (bits_per_word != 8) {	105	if (bits_per_word != 8) {
106	dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",	106	dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
107	__func__, bits_per_word);	107	__func__, bits_per_word);
108	return -EINVAL;	108	return -EINVAL;
109	}	109	}
110		110
111	if (spi->chip_select > spi->master->num_chipselect) {	111	if (spi->chip_select > spi->master->num_chipselect) {
112	dev_err(&spi->dev, "%s, unsupported slave %d\n",	112	dev_err(&spi->dev, "%s, unsupported slave %d\n",
113	__func__, spi->chip_select);	113	__func__, spi->chip_select);
114	return -EINVAL;	114	return -EINVAL;
115	}	115	}
116		116
117	return 0;	117	return 0;
118	}	118	}
119		119
120	static void bcm63xx_spi_setup_transfer(struct spi_device *spi,	120	static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
121	struct spi_transfer *t)	121	struct spi_transfer *t)
122	{	122	{
123	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);	123	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
124	u32 hz;	124	u32 hz;
125	u8 clk_cfg, reg;	125	u8 clk_cfg, reg;
126	int i;	126	int i;
127		127
128	hz = (t) ? t->speed_hz : spi->max_speed_hz;	128	hz = (t) ? t->speed_hz : spi->max_speed_hz;
129		129
130	/* Find the closest clock configuration */	130	/* Find the closest clock configuration */
131	for (i = 0; i < SPI_CLK_MASK; i++) {	131	for (i = 0; i < SPI_CLK_MASK; i++) {
132	if (hz <= bcm63xx_spi_freq_table[i][0]) {	132	if (hz >= bcm63xx_spi_freq_table[i][0]) {
133	clk_cfg = bcm63xx_spi_freq_table[i][1];	133	clk_cfg = bcm63xx_spi_freq_table[i][1];
134	break;	134	break;
135	}	135	}
136	}	136	}
137		137
138	/* No matching configuration found, default to lowest */	138	/* No matching configuration found, default to lowest */
139	if (i == SPI_CLK_MASK)	139	if (i == SPI_CLK_MASK)
140	clk_cfg = SPI_CLK_0_391MHZ;	140	clk_cfg = SPI_CLK_0_391MHZ;
141		141
142	/* clear existing clock configuration bits of the register */	142	/* clear existing clock configuration bits of the register */
143	reg = bcm_spi_readb(bs, SPI_CLK_CFG);	143	reg = bcm_spi_readb(bs, SPI_CLK_CFG);
144	reg &= ~SPI_CLK_MASK;	144	reg &= ~SPI_CLK_MASK;
145	reg \|= clk_cfg;	145	reg \|= clk_cfg;
146		146
147	bcm_spi_writeb(bs, reg, SPI_CLK_CFG);	147	bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
148	dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",	148	dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
149	clk_cfg, hz);	149	clk_cfg, hz);
150	}	150	}
151		151
152	/* the spi->mode bits understood by this driver: */	152	/* the spi->mode bits understood by this driver: */
153	#define MODEBITS (SPI_CPOL \| SPI_CPHA)	153	#define MODEBITS (SPI_CPOL \| SPI_CPHA)
154		154
155	static int bcm63xx_spi_setup(struct spi_device *spi)	155	static int bcm63xx_spi_setup(struct spi_device *spi)
156	{	156	{
157	struct bcm63xx_spi *bs;	157	struct bcm63xx_spi *bs;
158	int ret;	158	int ret;
159		159
160	bs = spi_master_get_devdata(spi->master);	160	bs = spi_master_get_devdata(spi->master);
161		161
162	if (!spi->bits_per_word)	162	if (!spi->bits_per_word)
163	spi->bits_per_word = 8;	163	spi->bits_per_word = 8;
164		164
165	if (spi->mode & ~MODEBITS) {	165	if (spi->mode & ~MODEBITS) {
166	dev_err(&spi->dev, "%s, unsupported mode bits %x\n",	166	dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
167	__func__, spi->mode & ~MODEBITS);	167	__func__, spi->mode & ~MODEBITS);
168	return -EINVAL;	168	return -EINVAL;
169	}	169	}
170		170
171	ret = bcm63xx_spi_check_transfer(spi, NULL);	171	ret = bcm63xx_spi_check_transfer(spi, NULL);
172	if (ret < 0) {	172	if (ret < 0) {
173	dev_err(&spi->dev, "setup: unsupported mode bits %x\n",	173	dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
174	spi->mode & ~MODEBITS);	174	spi->mode & ~MODEBITS);
175	return ret;	175	return ret;
176	}	176	}
177		177
178	dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",	178	dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
179	__func__, spi->mode & MODEBITS, spi->bits_per_word, 0);	179	__func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
180		180
181	return 0;	181	return 0;
182	}	182	}
183		183
184	/* Fill the TX FIFO with as many bytes as possible */	184	/* Fill the TX FIFO with as many bytes as possible */
185	static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)	185	static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)
186	{	186	{
187	u8 size;	187	u8 size;
188		188
189	/* Fill the Tx FIFO with as many bytes as possible */	189	/* Fill the Tx FIFO with as many bytes as possible */
190	size = bs->remaining_bytes < bs->fifo_size ? bs->remaining_bytes :	190	size = bs->remaining_bytes < bs->fifo_size ? bs->remaining_bytes :
191	bs->fifo_size;	191	bs->fifo_size;
192	memcpy_toio(bs->tx_io, bs->tx_ptr, size);	192	memcpy_toio(bs->tx_io, bs->tx_ptr, size);
193	bs->remaining_bytes -= size;	193	bs->remaining_bytes -= size;
194	}	194	}
195		195
196	static unsigned int bcm63xx_txrx_bufs(struct spi_device *spi,	196	static unsigned int bcm63xx_txrx_bufs(struct spi_device *spi,
197	struct spi_transfer *t)	197	struct spi_transfer *t)
198	{	198	{
199	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);	199	struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
200	u16 msg_ctl;	200	u16 msg_ctl;
201	u16 cmd;	201	u16 cmd;
202		202
203	/* Disable the CMD_DONE interrupt */	203	/* Disable the CMD_DONE interrupt */
204	bcm_spi_writeb(bs, 0, SPI_INT_MASK);	204	bcm_spi_writeb(bs, 0, SPI_INT_MASK);
205		205
206	dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",	206	dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
207	t->tx_buf, t->rx_buf, t->len);	207	t->tx_buf, t->rx_buf, t->len);
208		208
209	/* Transmitter is inhibited */	209	/* Transmitter is inhibited */
210	bs->tx_ptr = t->tx_buf;	210	bs->tx_ptr = t->tx_buf;
211	bs->rx_ptr = t->rx_buf;	211	bs->rx_ptr = t->rx_buf;
212		212
213	if (t->tx_buf) {	213	if (t->tx_buf) {
214	bs->remaining_bytes = t->len;	214	bs->remaining_bytes = t->len;
215	bcm63xx_spi_fill_tx_fifo(bs);	215	bcm63xx_spi_fill_tx_fifo(bs);
216	}	216	}
217		217
218	init_completion(&bs->done);	218	init_completion(&bs->done);
219		219
220	/* Fill in the Message control register */	220	/* Fill in the Message control register */
221	msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT);	221	msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT);
222		222
223	if (t->rx_buf && t->tx_buf)	223	if (t->rx_buf && t->tx_buf)
224	msg_ctl \|= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT);	224	msg_ctl \|= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT);
225	else if (t->rx_buf)	225	else if (t->rx_buf)
226	msg_ctl \|= (SPI_HD_R << SPI_MSG_TYPE_SHIFT);	226	msg_ctl \|= (SPI_HD_R << SPI_MSG_TYPE_SHIFT);
227	else if (t->tx_buf)	227	else if (t->tx_buf)
228	msg_ctl \|= (SPI_HD_W << SPI_MSG_TYPE_SHIFT);	228	msg_ctl \|= (SPI_HD_W << SPI_MSG_TYPE_SHIFT);
229		229
230	bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);	230	bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
231		231
232	/* Issue the transfer */	232	/* Issue the transfer */
233	cmd = SPI_CMD_START_IMMEDIATE;	233	cmd = SPI_CMD_START_IMMEDIATE;
234	cmd \|= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);	234	cmd \|= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
235	cmd \|= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);	235	cmd \|= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
236	bcm_spi_writew(bs, cmd, SPI_CMD);	236	bcm_spi_writew(bs, cmd, SPI_CMD);
237		237
238	/* Enable the CMD_DONE interrupt */	238	/* Enable the CMD_DONE interrupt */
239	bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);	239	bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
240		240
241	return t->len - bs->remaining_bytes;	241	return t->len - bs->remaining_bytes;
242	}	242	}
243		243
244	static int bcm63xx_spi_prepare_transfer(struct spi_master *master)	244	static int bcm63xx_spi_prepare_transfer(struct spi_master *master)
245	{	245	{
246	struct bcm63xx_spi *bs = spi_master_get_devdata(master);	246	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
247		247
248	pm_runtime_get_sync(&bs->pdev->dev);	248	pm_runtime_get_sync(&bs->pdev->dev);
249		249
250	return 0;	250	return 0;
251	}	251	}
252		252
253	static int bcm63xx_spi_unprepare_transfer(struct spi_master *master)	253	static int bcm63xx_spi_unprepare_transfer(struct spi_master *master)
254	{	254	{
255	struct bcm63xx_spi *bs = spi_master_get_devdata(master);	255	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
256		256
257	pm_runtime_put(&bs->pdev->dev);	257	pm_runtime_put(&bs->pdev->dev);
258		258
259	return 0;	259	return 0;
260	}	260	}
261		261
262	static int bcm63xx_spi_transfer_one(struct spi_master *master,	262	static int bcm63xx_spi_transfer_one(struct spi_master *master,
263	struct spi_message *m)	263	struct spi_message *m)
264	{	264	{
265	struct bcm63xx_spi *bs = spi_master_get_devdata(master);	265	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
266	struct spi_transfer *t;	266	struct spi_transfer *t;
267	struct spi_device *spi = m->spi;	267	struct spi_device *spi = m->spi;
268	int status = 0;	268	int status = 0;
269	unsigned int timeout = 0;	269	unsigned int timeout = 0;
270		270
271	list_for_each_entry(t, &m->transfers, transfer_list) {	271	list_for_each_entry(t, &m->transfers, transfer_list) {
272	unsigned int len = t->len;	272	unsigned int len = t->len;
273	u8 rx_tail;	273	u8 rx_tail;
274		274
275	status = bcm63xx_spi_check_transfer(spi, t);	275	status = bcm63xx_spi_check_transfer(spi, t);
276	if (status < 0)	276	if (status < 0)
277	goto exit;	277	goto exit;
278		278
279	/* configure adapter for a new transfer */	279	/* configure adapter for a new transfer */
280	bcm63xx_spi_setup_transfer(spi, t);	280	bcm63xx_spi_setup_transfer(spi, t);
281		281
282	while (len) {	282	while (len) {
283	/* send the data */	283	/* send the data */
284	len -= bcm63xx_txrx_bufs(spi, t);	284	len -= bcm63xx_txrx_bufs(spi, t);
285		285
286	timeout = wait_for_completion_timeout(&bs->done, HZ);	286	timeout = wait_for_completion_timeout(&bs->done, HZ);
287	if (!timeout) {	287	if (!timeout) {
288	status = -ETIMEDOUT;	288	status = -ETIMEDOUT;
289	goto exit;	289	goto exit;
290	}	290	}
291		291
292	/* read out all data */	292	/* read out all data */
293	rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);	293	rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
294		294
295	/* Read out all the data */	295	/* Read out all the data */
296	if (rx_tail)	296	if (rx_tail)
297	memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail);	297	memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail);
298	}	298	}
299		299
300	m->actual_length += t->len;	300	m->actual_length += t->len;
301	}	301	}
302	exit:	302	exit:
303	m->status = status;	303	m->status = status;
304	spi_finalize_current_message(master);	304	spi_finalize_current_message(master);
305		305
306	return 0;	306	return 0;
307	}	307	}
308		308
309	/* This driver supports single master mode only. Hence	309	/* This driver supports single master mode only. Hence
310	* CMD_DONE is the only interrupt we care about	310	* CMD_DONE is the only interrupt we care about
311	*/	311	*/
312	static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)	312	static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
313	{	313	{
314	struct spi_master master = (struct spi_master )dev_id;	314	struct spi_master master = (struct spi_master )dev_id;
315	struct bcm63xx_spi *bs = spi_master_get_devdata(master);	315	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
316	u8 intr;	316	u8 intr;
317		317
318	/* Read interupts and clear them immediately */	318	/* Read interupts and clear them immediately */
319	intr = bcm_spi_readb(bs, SPI_INT_STATUS);	319	intr = bcm_spi_readb(bs, SPI_INT_STATUS);
320	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);	320	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
321	bcm_spi_writeb(bs, 0, SPI_INT_MASK);	321	bcm_spi_writeb(bs, 0, SPI_INT_MASK);
322		322
323	/* A transfer completed */	323	/* A transfer completed */
324	if (intr & SPI_INTR_CMD_DONE)	324	if (intr & SPI_INTR_CMD_DONE)
325	complete(&bs->done);	325	complete(&bs->done);
326		326
327	return IRQ_HANDLED;	327	return IRQ_HANDLED;
328	}	328	}
329		329
330		330
331	static int __devinit bcm63xx_spi_probe(struct platform_device *pdev)	331	static int __devinit bcm63xx_spi_probe(struct platform_device *pdev)
332	{	332	{
333	struct resource *r;	333	struct resource *r;
334	struct device *dev = &pdev->dev;	334	struct device *dev = &pdev->dev;
335	struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;	335	struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
336	int irq;	336	int irq;
337	struct spi_master *master;	337	struct spi_master *master;
338	struct clk *clk;	338	struct clk *clk;
339	struct bcm63xx_spi *bs;	339	struct bcm63xx_spi *bs;
340	int ret;	340	int ret;
341		341
342	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);	342	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
343	if (!r) {	343	if (!r) {
344	dev_err(dev, "no iomem\n");	344	dev_err(dev, "no iomem\n");
345	ret = -ENXIO;	345	ret = -ENXIO;
346	goto out;	346	goto out;
347	}	347	}
348		348
349	irq = platform_get_irq(pdev, 0);	349	irq = platform_get_irq(pdev, 0);
350	if (irq < 0) {	350	if (irq < 0) {
351	dev_err(dev, "no irq\n");	351	dev_err(dev, "no irq\n");
352	ret = -ENXIO;	352	ret = -ENXIO;
353	goto out;	353	goto out;
354	}	354	}
355		355
356	clk = clk_get(dev, "spi");	356	clk = clk_get(dev, "spi");
357	if (IS_ERR(clk)) {	357	if (IS_ERR(clk)) {
358	dev_err(dev, "no clock for device\n");	358	dev_err(dev, "no clock for device\n");
359	ret = PTR_ERR(clk);	359	ret = PTR_ERR(clk);
360	goto out;	360	goto out;
361	}	361	}
362		362
363	master = spi_alloc_master(dev, sizeof(*bs));	363	master = spi_alloc_master(dev, sizeof(*bs));
364	if (!master) {	364	if (!master) {
365	dev_err(dev, "out of memory\n");	365	dev_err(dev, "out of memory\n");
366	ret = -ENOMEM;	366	ret = -ENOMEM;
367	goto out_clk;	367	goto out_clk;
368	}	368	}
369		369
370	bs = spi_master_get_devdata(master);	370	bs = spi_master_get_devdata(master);
371		371
372	platform_set_drvdata(pdev, master);	372	platform_set_drvdata(pdev, master);
373	bs->pdev = pdev;	373	bs->pdev = pdev;
374		374
375	if (!devm_request_mem_region(&pdev->dev, r->start,	375	if (!devm_request_mem_region(&pdev->dev, r->start,
376	resource_size(r), PFX)) {	376	resource_size(r), PFX)) {
377	dev_err(dev, "iomem request failed\n");	377	dev_err(dev, "iomem request failed\n");
378	ret = -ENXIO;	378	ret = -ENXIO;
379	goto out_err;	379	goto out_err;
380	}	380	}
381		381
382	bs->regs = devm_ioremap_nocache(&pdev->dev, r->start,	382	bs->regs = devm_ioremap_nocache(&pdev->dev, r->start,
383	resource_size(r));	383	resource_size(r));
384	if (!bs->regs) {	384	if (!bs->regs) {
385	dev_err(dev, "unable to ioremap regs\n");	385	dev_err(dev, "unable to ioremap regs\n");
386	ret = -ENOMEM;	386	ret = -ENOMEM;
387	goto out_err;	387	goto out_err;
388	}	388	}
389		389
390	bs->irq = irq;	390	bs->irq = irq;
391	bs->clk = clk;	391	bs->clk = clk;
392	bs->fifo_size = pdata->fifo_size;	392	bs->fifo_size = pdata->fifo_size;
393		393
394	ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,	394	ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
395	pdev->name, master);	395	pdev->name, master);
396	if (ret) {	396	if (ret) {
397	dev_err(dev, "unable to request irq\n");	397	dev_err(dev, "unable to request irq\n");
398	goto out_err;	398	goto out_err;
399	}	399	}
400		400
401	master->bus_num = pdata->bus_num;	401	master->bus_num = pdata->bus_num;
402	master->num_chipselect = pdata->num_chipselect;	402	master->num_chipselect = pdata->num_chipselect;
403	master->setup = bcm63xx_spi_setup;	403	master->setup = bcm63xx_spi_setup;
404	master->prepare_transfer_hardware = bcm63xx_spi_prepare_transfer;	404	master->prepare_transfer_hardware = bcm63xx_spi_prepare_transfer;
405	master->unprepare_transfer_hardware = bcm63xx_spi_unprepare_transfer;	405	master->unprepare_transfer_hardware = bcm63xx_spi_unprepare_transfer;
406	master->transfer_one_message = bcm63xx_spi_transfer_one;	406	master->transfer_one_message = bcm63xx_spi_transfer_one;
407	master->mode_bits = MODEBITS;	407	master->mode_bits = MODEBITS;
408	bs->speed_hz = pdata->speed_hz;	408	bs->speed_hz = pdata->speed_hz;
409	bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));	409	bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
410	bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));	410	bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
411		411
412	/* Initialize hardware */	412	/* Initialize hardware */
413	clk_enable(bs->clk);	413	clk_enable(bs->clk);
414	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);	414	bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
415		415
416	/* register and we are done */	416	/* register and we are done */
417	ret = spi_register_master(master);	417	ret = spi_register_master(master);
418	if (ret) {	418	if (ret) {
419	dev_err(dev, "spi register failed\n");	419	dev_err(dev, "spi register failed\n");
420	goto out_clk_disable;	420	goto out_clk_disable;
421	}	421	}
422		422
423	dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d) v%s\n",	423	dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d) v%s\n",
424	r->start, irq, bs->fifo_size, DRV_VER);	424	r->start, irq, bs->fifo_size, DRV_VER);
425		425
426	return 0;	426	return 0;
427		427
428	out_clk_disable:	428	out_clk_disable:
429	clk_disable(clk);	429	clk_disable(clk);
430	out_err:	430	out_err:
431	platform_set_drvdata(pdev, NULL);	431	platform_set_drvdata(pdev, NULL);
432	spi_master_put(master);	432	spi_master_put(master);
433	out_clk:	433	out_clk:
434	clk_put(clk);	434	clk_put(clk);
435	out:	435	out:
436	return ret;	436	return ret;
437	}	437	}
438		438
439	static int __devexit bcm63xx_spi_remove(struct platform_device *pdev)	439	static int __devexit bcm63xx_spi_remove(struct platform_device *pdev)
440	{	440	{
441	struct spi_master *master = platform_get_drvdata(pdev);	441	struct spi_master *master = platform_get_drvdata(pdev);
442	struct bcm63xx_spi *bs = spi_master_get_devdata(master);	442	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
443		443
444	spi_unregister_master(master);	444	spi_unregister_master(master);
445		445
446	/* reset spi block */	446	/* reset spi block */
447	bcm_spi_writeb(bs, 0, SPI_INT_MASK);	447	bcm_spi_writeb(bs, 0, SPI_INT_MASK);
448		448
449	/* HW shutdown */	449	/* HW shutdown */
450	clk_disable(bs->clk);	450	clk_disable(bs->clk);
451	clk_put(bs->clk);	451	clk_put(bs->clk);
452		452
453	platform_set_drvdata(pdev, 0);	453	platform_set_drvdata(pdev, 0);
454		454
455	return 0;	455	return 0;
456	}	456	}
457		457
458	#ifdef CONFIG_PM	458	#ifdef CONFIG_PM
459	static int bcm63xx_spi_suspend(struct device *dev)	459	static int bcm63xx_spi_suspend(struct device *dev)
460	{	460	{
461	struct spi_master *master =	461	struct spi_master *master =
462	platform_get_drvdata(to_platform_device(dev));	462	platform_get_drvdata(to_platform_device(dev));
463	struct bcm63xx_spi *bs = spi_master_get_devdata(master);	463	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
464		464
465	clk_disable(bs->clk);	465	clk_disable(bs->clk);
466		466
467	return 0;	467	return 0;
468	}	468	}
469		469
470	static int bcm63xx_spi_resume(struct device *dev)	470	static int bcm63xx_spi_resume(struct device *dev)
471	{	471	{
472	struct spi_master *master =	472	struct spi_master *master =
473	platform_get_drvdata(to_platform_device(dev));	473	platform_get_drvdata(to_platform_device(dev));
474	struct bcm63xx_spi *bs = spi_master_get_devdata(master);	474	struct bcm63xx_spi *bs = spi_master_get_devdata(master);
475		475
476	clk_enable(bs->clk);	476	clk_enable(bs->clk);
477		477
478	return 0;	478	return 0;
479	}	479	}
480		480
481	static const struct dev_pm_ops bcm63xx_spi_pm_ops = {	481	static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
482	.suspend = bcm63xx_spi_suspend,	482	.suspend = bcm63xx_spi_suspend,
483	.resume = bcm63xx_spi_resume,	483	.resume = bcm63xx_spi_resume,
484	};	484	};
485		485
486	#define BCM63XX_SPI_PM_OPS (&bcm63xx_spi_pm_ops)	486	#define BCM63XX_SPI_PM_OPS (&bcm63xx_spi_pm_ops)
487	#else	487	#else
488	#define BCM63XX_SPI_PM_OPS NULL	488	#define BCM63XX_SPI_PM_OPS NULL
489	#endif	489	#endif
490		490
491	static struct platform_driver bcm63xx_spi_driver = {	491	static struct platform_driver bcm63xx_spi_driver = {
492	.driver = {	492	.driver = {
493	.name = "bcm63xx-spi",	493	.name = "bcm63xx-spi",
494	.owner = THIS_MODULE,	494	.owner = THIS_MODULE,
495	.pm = BCM63XX_SPI_PM_OPS,	495	.pm = BCM63XX_SPI_PM_OPS,
496	},	496	},
497	.probe = bcm63xx_spi_probe,	497	.probe = bcm63xx_spi_probe,
498	.remove = __devexit_p(bcm63xx_spi_remove),	498	.remove = __devexit_p(bcm63xx_spi_remove),
499	};	499	};
500		500
501	module_platform_driver(bcm63xx_spi_driver);	501	module_platform_driver(bcm63xx_spi_driver);
502		502
503	MODULE_ALIAS("platform:bcm63xx_spi");	503	MODULE_ALIAS("platform:bcm63xx_spi");
504	MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");	504	MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
505	MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");	505	MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
506	MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");	506	MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
507	MODULE_LICENSE("GPL");	507	MODULE_LICENSE("GPL");
508		508

drivers/spi/spi-gpio.c

Diff comments View file @ 0082c16

 /*
  * SPI master driver using generic bitbanged GPIO
  *
  * Copyright (C) 2006,2008 David Brownell
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/spi_bitbang.h>
 #include <linux/spi/spi_gpio.h>
 /*
  * This bitbanging SPI master driver should help make systems usable
  * when a native hardware SPI engine is not available, perhaps because
  * its driver isn't yet working or because the I/O pins it requires
  * are used for other purposes.
  *
  * platform_device->driver_data ... points to spi_gpio
  *
  * spi->controller_state ... reserved for bitbang framework code
  * spi->controller_data ... holds chipselect GPIO
  *
  * spi->master->dev.driver_data ... points to spi_gpio->bitbang
  */
 struct spi_gpio {
 	struct spi_bitbang		bitbang;
 	struct spi_gpio_platform_data	pdata;
 	struct platform_device		*pdev;
 };
 /*----------------------------------------------------------------------*/
 /*
  * Because the overhead of going through four GPIO procedure calls
  * per transferred bit can make performance a problem, this code
  * is set up so that you can use it in either of two ways:
  *
  *   - The slow generic way:  set up platform_data to hold the GPIO
  *     numbers used for MISO/MOSI/SCK, and issue procedure calls for
  *     each of them.  This driver can handle several such busses.
  *
  *   - The quicker inlined way:  only helps with platform GPIO code
  *     that inlines operations for constant GPIOs.  This can give
  *     you tight (fast!) inner loops, but each such bus needs a
  *     new driver.  You'll define a new C file, with Makefile and
  *     Kconfig support; the C code can be a total of six lines:
  *
  *		#define DRIVER_NAME	"myboard_spi2"
  *		#define	SPI_MISO_GPIO	119
  *		#define	SPI_MOSI_GPIO	120
  *		#define	SPI_SCK_GPIO	121
  *		#define	SPI_N_CHIPSEL	4
  *		#include "spi-gpio.c"
  */
 #ifndef DRIVER_NAME
 #define DRIVER_NAME	"spi_gpio"
 #define GENERIC_BITBANG	/* vs tight inlines */
 /* all functions referencing these symbols must define pdata */
 #define SPI_MISO_GPIO	((pdata)->miso)
 #define SPI_MOSI_GPIO	((pdata)->mosi)
 #define SPI_SCK_GPIO	((pdata)->sck)
 #define SPI_N_CHIPSEL	((pdata)->num_chipselect)
 #endif
 /*----------------------------------------------------------------------*/
 static inline const struct spi_gpio_platform_data * __pure
 spi_to_pdata(const struct spi_device *spi)
 {
 	const struct spi_bitbang	*bang;
 	const struct spi_gpio		*spi_gpio;
 	bang = spi_master_get_devdata(spi->master);
 	spi_gpio = container_of(bang, struct spi_gpio, bitbang);
 	return &spi_gpio->pdata;
 }
 /* this is #defined to avoid unused-variable warnings when inlining */
 #define pdata		spi_to_pdata(spi)
 static inline void setsck(const struct spi_device *spi, int is_on)
 {
 	gpio_set_value(SPI_SCK_GPIO, is_on);
 }
 static inline void setmosi(const struct spi_device *spi, int is_on)
 {
 	gpio_set_value(SPI_MOSI_GPIO, is_on);
 }
 static inline int getmiso(const struct spi_device *spi)
 {
 	return !!gpio_get_value(SPI_MISO_GPIO);
 }
 #undef pdata
 /*
  * NOTE:  this clocks "as fast as we can".  It "should" be a function of the
  * requested device clock.  Software overhead means we usually have trouble
  * reaching even one Mbit/sec (except when we can inline bitops), so for now
  * we'll just assume we never need additional per-bit slowdowns.
  */
 #define spidelay(nsecs)	do {} while (0)
 #include "spi-bitbang-txrx.h"
 /*
  * These functions can leverage inline expansion of GPIO calls to shrink
  * costs for a txrx bit, often by factors of around ten (by instruction
  * count).  That is particularly visible for larger word sizes, but helps
  * even with default 8-bit words.
  *
  * REVISIT overheads calling these functions for each word also have
  * significant performance costs.  Having txrx_bufs() calls that inline
  * the txrx_word() logic would help performance, e.g. on larger blocks
  * used with flash storage or MMC/SD.  There should also be ways to make
  * GCC be less stupid about reloading registers inside the I/O loops,
  * even without inlined GPIO calls; __attribute__((hot)) on GCC 4.3?
  */
 static u32 spi_gpio_txrx_word_mode0(struct spi_device *spi,
 		unsigned nsecs, u32 word, u8 bits)
 {
 	return bitbang_txrx_be_cpha0(spi, nsecs, 0, 0, word, bits);
 }
 static u32 spi_gpio_txrx_word_mode1(struct spi_device *spi,
 		unsigned nsecs, u32 word, u8 bits)
 {
 	return bitbang_txrx_be_cpha1(spi, nsecs, 0, 0, word, bits);
 }
 static u32 spi_gpio_txrx_word_mode2(struct spi_device *spi,
 		unsigned nsecs, u32 word, u8 bits)
 {
 	return bitbang_txrx_be_cpha0(spi, nsecs, 1, 0, word, bits);
 }
 static u32 spi_gpio_txrx_word_mode3(struct spi_device *spi,
 		unsigned nsecs, u32 word, u8 bits)
 {
 	return bitbang_txrx_be_cpha1(spi, nsecs, 1, 0, word, bits);
 }
 /*
  * These functions do not call setmosi or getmiso if respective flag
  * (SPI_MASTER_NO_RX or SPI_MASTER_NO_TX) is set, so they are safe to
  * call when such pin is not present or defined in the controller.
  * A separate set of callbacks is defined to get highest possible
  * speed in the generic case (when both MISO and MOSI lines are
  * available), as optimiser will remove the checks when argument is
  * constant.
  */
 static u32 spi_gpio_spec_txrx_word_mode0(struct spi_device *spi,
 		unsigned nsecs, u32 word, u8 bits)
 {
 	unsigned flags = spi->master->flags;
 	return bitbang_txrx_be_cpha0(spi, nsecs, 0, flags, word, bits);
 }
 static u32 spi_gpio_spec_txrx_word_mode1(struct spi_device *spi,
 		unsigned nsecs, u32 word, u8 bits)
 {
 	unsigned flags = spi->master->flags;
 	return bitbang_txrx_be_cpha1(spi, nsecs, 0, flags, word, bits);
 }
 static u32 spi_gpio_spec_txrx_word_mode2(struct spi_device *spi,
 		unsigned nsecs, u32 word, u8 bits)
 {
 	unsigned flags = spi->master->flags;
 	return bitbang_txrx_be_cpha0(spi, nsecs, 1, flags, word, bits);
 }
 static u32 spi_gpio_spec_txrx_word_mode3(struct spi_device *spi,
 		unsigned nsecs, u32 word, u8 bits)
 {
 	unsigned flags = spi->master->flags;
 	return bitbang_txrx_be_cpha1(spi, nsecs, 1, flags, word, bits);
 }
 /*----------------------------------------------------------------------*/
 static void spi_gpio_chipselect(struct spi_device *spi, int is_active)
 {
 	unsigned long cs = (unsigned long) spi->controller_data;
 	/* set initial clock polarity */
 	if (is_active)
 		setsck(spi, spi->mode & SPI_CPOL);
 	if (cs != SPI_GPIO_NO_CHIPSELECT) {
 		/* SPI is normally active-low */
 		gpio_set_value(cs, (spi->mode & SPI_CS_HIGH) ? is_active : !is_active);
 	}
 }
 static int spi_gpio_setup(struct spi_device *spi)
 {
 	unsigned long	cs = (unsigned long) spi->controller_data;
 	int		status = 0;
 	if (spi->bits_per_word > 32)
 		return -EINVAL;
 	if (!spi->controller_state) {
 		if (cs != SPI_GPIO_NO_CHIPSELECT) {
 			status = gpio_request(cs, dev_name(&spi->dev));
 			if (status)
 				return status;
-			status = gpio_direction_output(cs, spi->mode & SPI_CS_HIGH);
+			status = gpio_direction_output(cs,
+					!(spi->mode & SPI_CS_HIGH));
 		}
 	}
 	if (!status)
 		status = spi_bitbang_setup(spi);
 	if (status) {
 		if (!spi->controller_state && cs != SPI_GPIO_NO_CHIPSELECT)
 			gpio_free(cs);
 	}
 	return status;
 }
 static void spi_gpio_cleanup(struct spi_device *spi)
 {
 	unsigned long	cs = (unsigned long) spi->controller_data;
 	if (cs != SPI_GPIO_NO_CHIPSELECT)
 		gpio_free(cs);
 	spi_bitbang_cleanup(spi);
 }
 static int __devinit spi_gpio_alloc(unsigned pin, const char *label, bool is_in)
 {
 	int value;
 	value = gpio_request(pin, label);
 	if (value == 0) {
 		if (is_in)
 			value = gpio_direction_input(pin);
 		else
 			value = gpio_direction_output(pin, 0);
 	}
 	return value;
 }
 static int __devinit
 spi_gpio_request(struct spi_gpio_platform_data *pdata, const char *label,
 	u16 *res_flags)
 {
 	int value;
 	/* NOTE:  SPI_*_GPIO symbols may reference "pdata" */
 	if (SPI_MOSI_GPIO != SPI_GPIO_NO_MOSI) {
 		value = spi_gpio_alloc(SPI_MOSI_GPIO, label, false);
 		if (value)
 			goto done;
 	} else {
 		/* HW configuration without MOSI pin */
 		*res_flags |= SPI_MASTER_NO_TX;
 	}
 	if (SPI_MISO_GPIO != SPI_GPIO_NO_MISO) {
 		value = spi_gpio_alloc(SPI_MISO_GPIO, label, true);
 		if (value)
 			goto free_mosi;
 	} else {
 		/* HW configuration without MISO pin */
 		*res_flags |= SPI_MASTER_NO_RX;
 	}
 	value = spi_gpio_alloc(SPI_SCK_GPIO, label, false);
 	if (value)
 		goto free_miso;
 	goto done;
 free_miso:
 	if (SPI_MISO_GPIO != SPI_GPIO_NO_MISO)
 		gpio_free(SPI_MISO_GPIO);
 free_mosi:
 	if (SPI_MOSI_GPIO != SPI_GPIO_NO_MOSI)
 		gpio_free(SPI_MOSI_GPIO);
 done:
 	return value;
 }
 static int __devinit spi_gpio_probe(struct platform_device *pdev)
 {
 	int				status;
 	struct spi_master		*master;
 	struct spi_gpio			*spi_gpio;
 	struct spi_gpio_platform_data	*pdata;
 	u16 master_flags = 0;
 	pdata = pdev->dev.platform_data;
 #ifdef GENERIC_BITBANG
 	if (!pdata || !pdata->num_chipselect)
 		return -ENODEV;
 #endif
 	status = spi_gpio_request(pdata, dev_name(&pdev->dev), &master_flags);
 	if (status < 0)
 		return status;
 	master = spi_alloc_master(&pdev->dev, sizeof *spi_gpio);
 	if (!master) {
 		status = -ENOMEM;
 		goto gpio_free;
 	}
 	spi_gpio = spi_master_get_devdata(master);
 	platform_set_drvdata(pdev, spi_gpio);
 	spi_gpio->pdev = pdev;
 	if (pdata)
 		spi_gpio->pdata = *pdata;
 	master->flags = master_flags;
 	master->bus_num = pdev->id;
 	master->num_chipselect = SPI_N_CHIPSEL;
 	master->setup = spi_gpio_setup;
 	master->cleanup = spi_gpio_cleanup;
 	spi_gpio->bitbang.master = spi_master_get(master);
 	spi_gpio->bitbang.chipselect = spi_gpio_chipselect;
 	if ((master_flags & (SPI_MASTER_NO_TX | SPI_MASTER_NO_RX)) == 0) {
 		spi_gpio->bitbang.txrx_word[SPI_MODE_0] = spi_gpio_txrx_word_mode0;
 		spi_gpio->bitbang.txrx_word[SPI_MODE_1] = spi_gpio_txrx_word_mode1;
 		spi_gpio->bitbang.txrx_word[SPI_MODE_2] = spi_gpio_txrx_word_mode2;
 		spi_gpio->bitbang.txrx_word[SPI_MODE_3] = spi_gpio_txrx_word_mode3;
 	} else {
 		spi_gpio->bitbang.txrx_word[SPI_MODE_0] = spi_gpio_spec_txrx_word_mode0;
 		spi_gpio->bitbang.txrx_word[SPI_MODE_1] = spi_gpio_spec_txrx_word_mode1;
 		spi_gpio->bitbang.txrx_word[SPI_MODE_2] = spi_gpio_spec_txrx_word_mode2;
 		spi_gpio->bitbang.txrx_word[SPI_MODE_3] = spi_gpio_spec_txrx_word_mode3;
 	}
 	spi_gpio->bitbang.setup_transfer = spi_bitbang_setup_transfer;
 	spi_gpio->bitbang.flags = SPI_CS_HIGH;
 	status = spi_bitbang_start(&spi_gpio->bitbang);
 	if (status < 0) {
 		spi_master_put(spi_gpio->bitbang.master);
 gpio_free:
 		if (SPI_MISO_GPIO != SPI_GPIO_NO_MISO)
 			gpio_free(SPI_MISO_GPIO);
 		if (SPI_MOSI_GPIO != SPI_GPIO_NO_MOSI)
 			gpio_free(SPI_MOSI_GPIO);
 		gpio_free(SPI_SCK_GPIO);
 		spi_master_put(master);
 	}
 	return status;
 }
 static int __devexit spi_gpio_remove(struct platform_device *pdev)
 {
 	struct spi_gpio			*spi_gpio;
 	struct spi_gpio_platform_data	*pdata;
 	int				status;
 	spi_gpio = platform_get_drvdata(pdev);
 	pdata = pdev->dev.platform_data;
 	/* stop() unregisters child devices too */
 	status = spi_bitbang_stop(&spi_gpio->bitbang);
 	spi_master_put(spi_gpio->bitbang.master);
 	platform_set_drvdata(pdev, NULL);
 	if (SPI_MISO_GPIO != SPI_GPIO_NO_MISO)
 		gpio_free(SPI_MISO_GPIO);
 	if (SPI_MOSI_GPIO != SPI_GPIO_NO_MOSI)
 		gpio_free(SPI_MOSI_GPIO);
 	gpio_free(SPI_SCK_GPIO);
 	return status;
 }
 MODULE_ALIAS("platform:" DRIVER_NAME);
 static struct platform_driver spi_gpio_driver = {
 	.driver.name	= DRIVER_NAME,
 	.driver.owner	= THIS_MODULE,
 	.probe		= spi_gpio_probe,
 	.remove		= __devexit_p(spi_gpio_remove),
 };
 module_platform_driver(spi_gpio_driver);
 MODULE_DESCRIPTION("SPI master driver using generic bitbanged GPIO ");
 MODULE_AUTHOR("David Brownell");
 MODULE_LICENSE("GPL");

drivers/spi/spi-imx.c

Diff comments View file @ 0082c16

 /*
  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  * Copyright (C) 2008 Juergen Beisert
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * as published by the Free Software Foundation; either version 2
  * of the License, or (at your option) any later version.
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the
  * Free Software Foundation
  * 51 Franklin Street, Fifth Floor
  * Boston, MA  02110-1301, USA.
  */
 #include <linux/clk.h>
 #include <linux/completion.h>
 #include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/spi_bitbang.h>
 #include <linux/types.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/of_gpio.h>
 #include <linux/pinctrl/consumer.h>
 #include <mach/spi.h>
 #define DRIVER_NAME "spi_imx"
 #define MXC_CSPIRXDATA		0x00
 #define MXC_CSPITXDATA		0x04
 #define MXC_CSPICTRL		0x08
 #define MXC_CSPIINT		0x0c
 #define MXC_RESET		0x1c
 /* generic defines to abstract from the different register layouts */
 #define MXC_INT_RR	(1 << 0) /* Receive data ready interrupt */
 #define MXC_INT_TE	(1 << 1) /* Transmit FIFO empty interrupt */
 struct spi_imx_config {
 	unsigned int speed_hz;
 	unsigned int bpw;
 	unsigned int mode;
 	u8 cs;
 };
 enum spi_imx_devtype {
 	IMX1_CSPI,
 	IMX21_CSPI,
 	IMX27_CSPI,
 	IMX31_CSPI,
 	IMX35_CSPI,	/* CSPI on all i.mx except above */
 	IMX51_ECSPI,	/* ECSPI on i.mx51 and later */
 };
 struct spi_imx_data;
 struct spi_imx_devtype_data {
 	void (*intctrl)(struct spi_imx_data *, int);
 	int (*config)(struct spi_imx_data *, struct spi_imx_config *);
 	void (*trigger)(struct spi_imx_data *);
 	int (*rx_available)(struct spi_imx_data *);
 	void (*reset)(struct spi_imx_data *);
 	enum spi_imx_devtype devtype;
 };
 struct spi_imx_data {
 	struct spi_bitbang bitbang;
 	struct completion xfer_done;
 	void __iomem *base;
 	int irq;
 	struct clk *clk_per;
 	struct clk *clk_ipg;
 	unsigned long spi_clk;
 	unsigned int count;
 	void (*tx)(struct spi_imx_data *);
 	void (*rx)(struct spi_imx_data *);
 	void *rx_buf;
 	const void *tx_buf;
 	unsigned int txfifo; /* number of words pushed in tx FIFO */
 	struct spi_imx_devtype_data *devtype_data;
 	int chipselect[0];
 };
 static inline int is_imx27_cspi(struct spi_imx_data *d)
 {
 	return d->devtype_data->devtype == IMX27_CSPI;
 }
 static inline int is_imx35_cspi(struct spi_imx_data *d)
 {
 	return d->devtype_data->devtype == IMX35_CSPI;
 }
 static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d)
 {
 	return (d->devtype_data->devtype == IMX51_ECSPI) ? 64 : 8;
 }
 #define MXC_SPI_BUF_RX(type)						\
 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx)		\
 {									\
 	unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);	\
 									\
 	if (spi_imx->rx_buf) {						\
 		*(type *)spi_imx->rx_buf = val;				\
 		spi_imx->rx_buf += sizeof(type);			\
 	}								\
 }
 #define MXC_SPI_BUF_TX(type)						\
 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx)		\
 {									\
 	type val = 0;							\
 									\
 	if (spi_imx->tx_buf) {						\
 		val = *(type *)spi_imx->tx_buf;				\
 		spi_imx->tx_buf += sizeof(type);			\
 	}								\
 									\
 	spi_imx->count -= sizeof(type);					\
 									\
 	writel(val, spi_imx->base + MXC_CSPITXDATA);			\
 }
 MXC_SPI_BUF_RX(u8)
 MXC_SPI_BUF_TX(u8)
 MXC_SPI_BUF_RX(u16)
 MXC_SPI_BUF_TX(u16)
 MXC_SPI_BUF_RX(u32)
 MXC_SPI_BUF_TX(u32)
 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
  * (which is currently not the case in this driver)
  */
 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
 	256, 384, 512, 768, 1024};
 /* MX21, MX27 */
 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
 		unsigned int fspi, unsigned int max)
 {
 	int i;
 	for (i = 2; i < max; i++)
 		if (fspi * mxc_clkdivs[i] >= fin)
 			return i;
 	return max;
 }
 /* MX1, MX31, MX35, MX51 CSPI */
 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
 		unsigned int fspi)
 {
 	int i, div = 4;
 	for (i = 0; i < 7; i++) {
 		if (fspi * div >= fin)
 			return i;
 		div <<= 1;
 	}
 	return 7;
 }
 #define MX51_ECSPI_CTRL		0x08
 #define MX51_ECSPI_CTRL_ENABLE		(1 <<  0)
 #define MX51_ECSPI_CTRL_XCH		(1 <<  2)
 #define MX51_ECSPI_CTRL_MODE_MASK	(0xf << 4)
 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET	8
 #define MX51_ECSPI_CTRL_PREDIV_OFFSET	12
 #define MX51_ECSPI_CTRL_CS(cs)		((cs) << 18)
 #define MX51_ECSPI_CTRL_BL_OFFSET	20
 #define MX51_ECSPI_CONFIG	0x0c
 #define MX51_ECSPI_CONFIG_SCLKPHA(cs)	(1 << ((cs) +  0))
 #define MX51_ECSPI_CONFIG_SCLKPOL(cs)	(1 << ((cs) +  4))
 #define MX51_ECSPI_CONFIG_SBBCTRL(cs)	(1 << ((cs) +  8))
 #define MX51_ECSPI_CONFIG_SSBPOL(cs)	(1 << ((cs) + 12))
 #define MX51_ECSPI_INT		0x10
 #define MX51_ECSPI_INT_TEEN		(1 <<  0)
 #define MX51_ECSPI_INT_RREN		(1 <<  3)
 #define MX51_ECSPI_STAT		0x18
 #define MX51_ECSPI_STAT_RR		(1 <<  3)
 /* MX51 eCSPI */
 static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi)
 {
 	/*
 	 * there are two 4-bit dividers, the pre-divider divides by
 	 * $pre, the post-divider by 2^$post
 	 */
 	unsigned int pre, post;
 	if (unlikely(fspi > fin))
 		return 0;
 	post = fls(fin) - fls(fspi);
 	if (fin > fspi << post)
 		post++;
 	/* now we have: (fin <= fspi << post) with post being minimal */
 	post = max(4U, post) - 4;
 	if (unlikely(post > 0xf)) {
 		pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
 				__func__, fspi, fin);
 		return 0xff;
 	}
 	pre = DIV_ROUND_UP(fin, fspi << post) - 1;
 	pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
 			__func__, fin, fspi, post, pre);
 	return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
 		(post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
 }
 static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
 {
 	unsigned val = 0;
 	if (enable & MXC_INT_TE)
 		val |= MX51_ECSPI_INT_TEEN;
 	if (enable & MXC_INT_RR)
 		val |= MX51_ECSPI_INT_RREN;
 	writel(val, spi_imx->base + MX51_ECSPI_INT);
 }
 static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
 {
 	u32 reg;
 	reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
 	reg |= MX51_ECSPI_CTRL_XCH;
 	writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
 }
 static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
 		struct spi_imx_config *config)
 {
 	u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0;
 	/*
 	 * The hardware seems to have a race condition when changing modes. The
 	 * current assumption is that the selection of the channel arrives
 	 * earlier in the hardware than the mode bits when they are written at
 	 * the same time.
 	 * So set master mode for all channels as we do not support slave mode.
 	 */
 	ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
 	/* set clock speed */
 	ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz);
 	/* set chip select to use */
 	ctrl |= MX51_ECSPI_CTRL_CS(config->cs);
 	ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
 	cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs);
 	if (config->mode & SPI_CPHA)
 		cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
 	if (config->mode & SPI_CPOL)
 		cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
 	if (config->mode & SPI_CS_HIGH)
 		cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
 	writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
 	writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
 	return 0;
 }
 static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
 {
 	return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
 }
 static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx)
 {
 	/* drain receive buffer */
 	while (mx51_ecspi_rx_available(spi_imx))
 		readl(spi_imx->base + MXC_CSPIRXDATA);
 }
 #define MX31_INTREG_TEEN	(1 << 0)
 #define MX31_INTREG_RREN	(1 << 3)
 #define MX31_CSPICTRL_ENABLE	(1 << 0)
 #define MX31_CSPICTRL_MASTER	(1 << 1)
 #define MX31_CSPICTRL_XCH	(1 << 2)
 #define MX31_CSPICTRL_POL	(1 << 4)
 #define MX31_CSPICTRL_PHA	(1 << 5)
 #define MX31_CSPICTRL_SSCTL	(1 << 6)
 #define MX31_CSPICTRL_SSPOL	(1 << 7)
 #define MX31_CSPICTRL_BC_SHIFT	8
 #define MX35_CSPICTRL_BL_SHIFT	20
 #define MX31_CSPICTRL_CS_SHIFT	24
 #define MX35_CSPICTRL_CS_SHIFT	12
 #define MX31_CSPICTRL_DR_SHIFT	16
 #define MX31_CSPISTATUS		0x14
 #define MX31_STATUS_RR		(1 << 3)
 /* These functions also work for the i.MX35, but be aware that
  * the i.MX35 has a slightly different register layout for bits
  * we do not use here.
  */
 static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
 {
 	unsigned int val = 0;
 	if (enable & MXC_INT_TE)
 		val |= MX31_INTREG_TEEN;
 	if (enable & MXC_INT_RR)
 		val |= MX31_INTREG_RREN;
 	writel(val, spi_imx->base + MXC_CSPIINT);
 }
 static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
 {
 	unsigned int reg;
 	reg = readl(spi_imx->base + MXC_CSPICTRL);
 	reg |= MX31_CSPICTRL_XCH;
 	writel(reg, spi_imx->base + MXC_CSPICTRL);
 }
 static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
 		struct spi_imx_config *config)
 {
 	unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
 	int cs = spi_imx->chipselect[config->cs];
 	reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
 		MX31_CSPICTRL_DR_SHIFT;
 	if (is_imx35_cspi(spi_imx)) {
 		reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
 		reg |= MX31_CSPICTRL_SSCTL;
 	} else {
 		reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
 	}
 	if (config->mode & SPI_CPHA)
 		reg |= MX31_CSPICTRL_PHA;
 	if (config->mode & SPI_CPOL)
 		reg |= MX31_CSPICTRL_POL;
 	if (config->mode & SPI_CS_HIGH)
 		reg |= MX31_CSPICTRL_SSPOL;
 	if (cs < 0)
 		reg |= (cs + 32) <<
 			(is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
 						  MX31_CSPICTRL_CS_SHIFT);
 	writel(reg, spi_imx->base + MXC_CSPICTRL);
 	return 0;
 }
 static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
 {
 	return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
 }
 static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx)
 {
 	/* drain receive buffer */
 	while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
 		readl(spi_imx->base + MXC_CSPIRXDATA);
 }
 #define MX21_INTREG_RR		(1 << 4)
 #define MX21_INTREG_TEEN	(1 << 9)
 #define MX21_INTREG_RREN	(1 << 13)
 #define MX21_CSPICTRL_POL	(1 << 5)
 #define MX21_CSPICTRL_PHA	(1 << 6)
 #define MX21_CSPICTRL_SSPOL	(1 << 8)
 #define MX21_CSPICTRL_XCH	(1 << 9)
 #define MX21_CSPICTRL_ENABLE	(1 << 10)
 #define MX21_CSPICTRL_MASTER	(1 << 11)
 #define MX21_CSPICTRL_DR_SHIFT	14
 #define MX21_CSPICTRL_CS_SHIFT	19
 static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
 {
 	unsigned int val = 0;
 	if (enable & MXC_INT_TE)
 		val |= MX21_INTREG_TEEN;
 	if (enable & MXC_INT_RR)
 		val |= MX21_INTREG_RREN;
 	writel(val, spi_imx->base + MXC_CSPIINT);
 }
 static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx)
 {
 	unsigned int reg;
 	reg = readl(spi_imx->base + MXC_CSPICTRL);
 	reg |= MX21_CSPICTRL_XCH;
 	writel(reg, spi_imx->base + MXC_CSPICTRL);
 }
 static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx,
 		struct spi_imx_config *config)
 {
 	unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
 	int cs = spi_imx->chipselect[config->cs];
 	unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
 	reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) <<
 		MX21_CSPICTRL_DR_SHIFT;
 	reg |= config->bpw - 1;
 	if (config->mode & SPI_CPHA)
 		reg |= MX21_CSPICTRL_PHA;
 	if (config->mode & SPI_CPOL)
 		reg |= MX21_CSPICTRL_POL;
 	if (config->mode & SPI_CS_HIGH)
 		reg |= MX21_CSPICTRL_SSPOL;
 	if (cs < 0)
 		reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT;
 	writel(reg, spi_imx->base + MXC_CSPICTRL);
 	return 0;
 }
 static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx)
 {
 	return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
 }
 static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx)
 {
 	writel(1, spi_imx->base + MXC_RESET);
 }
 #define MX1_INTREG_RR		(1 << 3)
 #define MX1_INTREG_TEEN		(1 << 8)
 #define MX1_INTREG_RREN		(1 << 11)
 #define MX1_CSPICTRL_POL	(1 << 4)
 #define MX1_CSPICTRL_PHA	(1 << 5)
 #define MX1_CSPICTRL_XCH	(1 << 8)
 #define MX1_CSPICTRL_ENABLE	(1 << 9)
 #define MX1_CSPICTRL_MASTER	(1 << 10)
 #define MX1_CSPICTRL_DR_SHIFT	13
 static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
 {
 	unsigned int val = 0;
 	if (enable & MXC_INT_TE)
 		val |= MX1_INTREG_TEEN;
 	if (enable & MXC_INT_RR)
 		val |= MX1_INTREG_RREN;
 	writel(val, spi_imx->base + MXC_CSPIINT);
 }
 static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
 {
 	unsigned int reg;
 	reg = readl(spi_imx->base + MXC_CSPICTRL);
 	reg |= MX1_CSPICTRL_XCH;
 	writel(reg, spi_imx->base + MXC_CSPICTRL);
 }
 static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
 		struct spi_imx_config *config)
 {
 	unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
 	reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
 		MX1_CSPICTRL_DR_SHIFT;
 	reg |= config->bpw - 1;
 	if (config->mode & SPI_CPHA)
 		reg |= MX1_CSPICTRL_PHA;
 	if (config->mode & SPI_CPOL)
 		reg |= MX1_CSPICTRL_POL;
 	writel(reg, spi_imx->base + MXC_CSPICTRL);
 	return 0;
 }
 static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
 {
 	return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
 }
 static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
 {
 	writel(1, spi_imx->base + MXC_RESET);
 }
 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
 	.intctrl = mx1_intctrl,
 	.config = mx1_config,
 	.trigger = mx1_trigger,
 	.rx_available = mx1_rx_available,
 	.reset = mx1_reset,
 	.devtype = IMX1_CSPI,
 };
 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
 	.intctrl = mx21_intctrl,
 	.config = mx21_config,
 	.trigger = mx21_trigger,
 	.rx_available = mx21_rx_available,
 	.reset = mx21_reset,
 	.devtype = IMX21_CSPI,
 };
 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
 	/* i.mx27 cspi shares the functions with i.mx21 one */
 	.intctrl = mx21_intctrl,
 	.config = mx21_config,
 	.trigger = mx21_trigger,
 	.rx_available = mx21_rx_available,
 	.reset = mx21_reset,
 	.devtype = IMX27_CSPI,
 };
 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
 	.intctrl = mx31_intctrl,
 	.config = mx31_config,
 	.trigger = mx31_trigger,
 	.rx_available = mx31_rx_available,
 	.reset = mx31_reset,
 	.devtype = IMX31_CSPI,
 };
 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
 	/* i.mx35 and later cspi shares the functions with i.mx31 one */
 	.intctrl = mx31_intctrl,
 	.config = mx31_config,
 	.trigger = mx31_trigger,
 	.rx_available = mx31_rx_available,
 	.reset = mx31_reset,
 	.devtype = IMX35_CSPI,
 };
 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
 	.intctrl = mx51_ecspi_intctrl,
 	.config = mx51_ecspi_config,
 	.trigger = mx51_ecspi_trigger,
 	.rx_available = mx51_ecspi_rx_available,
 	.reset = mx51_ecspi_reset,
 	.devtype = IMX51_ECSPI,
 };
 static struct platform_device_id spi_imx_devtype[] = {
 	{
 		.name = "imx1-cspi",
 		.driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
 	}, {
 		.name = "imx21-cspi",
 		.driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
 	}, {
 		.name = "imx27-cspi",
 		.driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
 	}, {
 		.name = "imx31-cspi",
 		.driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
 	}, {
 		.name = "imx35-cspi",
 		.driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
 	}, {
 		.name = "imx51-ecspi",
 		.driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
 	}, {
 		/* sentinel */
 	}
 };
 static const struct of_device_id spi_imx_dt_ids[] = {
 	{ .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
 	{ .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
 	{ .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
 	{ .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
 	{ .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
 	{ .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
 	{ /* sentinel */ }
 };
 static void spi_imx_chipselect(struct spi_device *spi, int is_active)
 {
 	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 	int gpio = spi_imx->chipselect[spi->chip_select];
 	int active = is_active != BITBANG_CS_INACTIVE;
 	int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
-	if (gpio < 0)
+	if (!gpio_is_valid(gpio))
 		return;
 	gpio_set_value(gpio, dev_is_lowactive ^ active);
 }
 static void spi_imx_push(struct spi_imx_data *spi_imx)
 {
 	while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) {
 		if (!spi_imx->count)
 			break;
 		spi_imx->tx(spi_imx);
 		spi_imx->txfifo++;
 	}
 	spi_imx->devtype_data->trigger(spi_imx);
 }
 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
 {
 	struct spi_imx_data *spi_imx = dev_id;
 	while (spi_imx->devtype_data->rx_available(spi_imx)) {
 		spi_imx->rx(spi_imx);
 		spi_imx->txfifo--;
 	}
 	if (spi_imx->count) {
 		spi_imx_push(spi_imx);
 		return IRQ_HANDLED;
 	}
 	if (spi_imx->txfifo) {
 		/* No data left to push, but still waiting for rx data,
 		 * enable receive data available interrupt.
 		 */
 		spi_imx->devtype_data->intctrl(
 				spi_imx, MXC_INT_RR);
 		return IRQ_HANDLED;
 	}
 	spi_imx->devtype_data->intctrl(spi_imx, 0);
 	complete(&spi_imx->xfer_done);
 	return IRQ_HANDLED;
 }
 static int spi_imx_setupxfer(struct spi_device *spi,
 				 struct spi_transfer *t)
 {
 	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 	struct spi_imx_config config;
 	config.bpw = t ? t->bits_per_word : spi->bits_per_word;
 	config.speed_hz  = t ? t->speed_hz : spi->max_speed_hz;
 	config.mode = spi->mode;
 	config.cs = spi->chip_select;
 	if (!config.speed_hz)
 		config.speed_hz = spi->max_speed_hz;
 	if (!config.bpw)
 		config.bpw = spi->bits_per_word;
-	if (!config.speed_hz)
-		config.speed_hz = spi->max_speed_hz;
 	/* Initialize the functions for transfer */
 	if (config.bpw <= 8) {
 		spi_imx->rx = spi_imx_buf_rx_u8;
 		spi_imx->tx = spi_imx_buf_tx_u8;
 	} else if (config.bpw <= 16) {
 		spi_imx->rx = spi_imx_buf_rx_u16;
 		spi_imx->tx = spi_imx_buf_tx_u16;
 	} else if (config.bpw <= 32) {
 		spi_imx->rx = spi_imx_buf_rx_u32;
 		spi_imx->tx = spi_imx_buf_tx_u32;
 	} else
 		BUG();
 	spi_imx->devtype_data->config(spi_imx, &config);
 	return 0;
 }
 static int spi_imx_transfer(struct spi_device *spi,
 				struct spi_transfer *transfer)
 {
 	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 	spi_imx->tx_buf = transfer->tx_buf;
 	spi_imx->rx_buf = transfer->rx_buf;
 	spi_imx->count = transfer->len;
 	spi_imx->txfifo = 0;
 	init_completion(&spi_imx->xfer_done);
 	spi_imx_push(spi_imx);
 	spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
 	wait_for_completion(&spi_imx->xfer_done);
 	return transfer->len;
 }
 static int spi_imx_setup(struct spi_device *spi)
 {
 	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 	int gpio = spi_imx->chipselect[spi->chip_select];
 	dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
 		 spi->mode, spi->bits_per_word, spi->max_speed_hz);
-	if (gpio >= 0)
+	if (gpio_is_valid(gpio))
 		gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
 	spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
 	return 0;
 }
 static void spi_imx_cleanup(struct spi_device *spi)
 {
 }
 static int __devinit spi_imx_probe(struct platform_device *pdev)
 {
 	struct device_node *np = pdev->dev.of_node;
 	const struct of_device_id *of_id =
 			of_match_device(spi_imx_dt_ids, &pdev->dev);
 	struct spi_imx_master *mxc_platform_info =
 			dev_get_platdata(&pdev->dev);
 	struct spi_master *master;
 	struct spi_imx_data *spi_imx;
 	struct resource *res;
 	struct pinctrl *pinctrl;
 	int i, ret, num_cs;
 	if (!np && !mxc_platform_info) {
 		dev_err(&pdev->dev, "can't get the platform data\n");
 		return -EINVAL;
 	}
 	ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs);
 	if (ret < 0) {
 		if (mxc_platform_info)
 			num_cs = mxc_platform_info->num_chipselect;
 		else
 			return ret;
 	}
 	master = spi_alloc_master(&pdev->dev,
 			sizeof(struct spi_imx_data) + sizeof(int) * num_cs);
 	if (!master)
 		return -ENOMEM;
 	platform_set_drvdata(pdev, master);
 	master->bus_num = pdev->id;
 	master->num_chipselect = num_cs;
 	spi_imx = spi_master_get_devdata(master);
 	spi_imx->bitbang.master = spi_master_get(master);
 	for (i = 0; i < master->num_chipselect; i++) {
 		int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
-		if (cs_gpio < 0 && mxc_platform_info)
+		if (!gpio_is_valid(cs_gpio) && mxc_platform_info)
 			cs_gpio = mxc_platform_info->chipselect[i];
 		spi_imx->chipselect[i] = cs_gpio;
-		if (cs_gpio < 0)
+		if (!gpio_is_valid(cs_gpio))
 			continue;
 		ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME);
 		if (ret) {
 			dev_err(&pdev->dev, "can't get cs gpios\n");
 			goto out_gpio_free;
 		}
 	}
 	spi_imx->bitbang.chipselect = spi_imx_chipselect;
 	spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
 	spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
 	spi_imx->bitbang.master->setup = spi_imx_setup;
 	spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
 	spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 	init_completion(&spi_imx->xfer_done);
 	spi_imx->devtype_data = of_id ? of_id->data :
 		(struct spi_imx_devtype_data *) pdev->id_entry->driver_data;
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res) {
 		dev_err(&pdev->dev, "can't get platform resource\n");
 		ret = -ENOMEM;
 		goto out_gpio_free;
 	}
 	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
 		dev_err(&pdev->dev, "request_mem_region failed\n");
 		ret = -EBUSY;
 		goto out_gpio_free;
 	}
 	spi_imx->base = ioremap(res->start, resource_size(res));
 	if (!spi_imx->base) {
 		ret = -EINVAL;
 		goto out_release_mem;
 	}
 	spi_imx->irq = platform_get_irq(pdev, 0);
 	if (spi_imx->irq < 0) {
 		ret = -EINVAL;
 		goto out_iounmap;
 	}
 	ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx);
 	if (ret) {
 		dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
 		goto out_iounmap;
 	}
 	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
 	if (IS_ERR(pinctrl)) {
 		ret = PTR_ERR(pinctrl);
 		goto out_free_irq;
 	}
 	spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
 	if (IS_ERR(spi_imx->clk_ipg)) {
 		ret = PTR_ERR(spi_imx->clk_ipg);
 		goto out_free_irq;
 	}
 	spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
 	if (IS_ERR(spi_imx->clk_per)) {
 		ret = PTR_ERR(spi_imx->clk_per);
 		goto out_free_irq;
 	}
 	clk_prepare_enable(spi_imx->clk_per);
 	clk_prepare_enable(spi_imx->clk_ipg);
 	spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
 	spi_imx->devtype_data->reset(spi_imx);
 	spi_imx->devtype_data->intctrl(spi_imx, 0);
 	master->dev.of_node = pdev->dev.of_node;
 	ret = spi_bitbang_start(&spi_imx->bitbang);
 	if (ret) {
 		dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
 		goto out_clk_put;
 	}
 	dev_info(&pdev->dev, "probed\n");
 	return ret;
 out_clk_put:
 	clk_disable_unprepare(spi_imx->clk_per);
 	clk_disable_unprepare(spi_imx->clk_ipg);
 out_free_irq:
 	free_irq(spi_imx->irq, spi_imx);
 out_iounmap:
 	iounmap(spi_imx->base);
 out_release_mem:
 	release_mem_region(res->start, resource_size(res));
 out_gpio_free:
 	while (--i >= 0) {
-		if (spi_imx->chipselect[i] >= 0)
+		if (gpio_is_valid(spi_imx->chipselect[i]))
 			gpio_free(spi_imx->chipselect[i]);
 	}
 	spi_master_put(master);
 	kfree(master);
 	platform_set_drvdata(pdev, NULL);
 	return ret;
 }
 static int __devexit spi_imx_remove(struct platform_device *pdev)
 {
 	struct spi_master *master = platform_get_drvdata(pdev);
 	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
 	int i;
 	spi_bitbang_stop(&spi_imx->bitbang);
 	writel(0, spi_imx->base + MXC_CSPICTRL);
 	clk_disable_unprepare(spi_imx->clk_per);
 	clk_disable_unprepare(spi_imx->clk_ipg);
 	free_irq(spi_imx->irq, spi_imx);
 	iounmap(spi_imx->base);
 	for (i = 0; i < master->num_chipselect; i++)
-		if (spi_imx->chipselect[i] >= 0)
+		if (gpio_is_valid(spi_imx->chipselect[i]))
 			gpio_free(spi_imx->chipselect[i]);
 	spi_master_put(master);
 	release_mem_region(res->start, resource_size(res));
 	platform_set_drvdata(pdev, NULL);
 	return 0;
 }
 static struct platform_driver spi_imx_driver = {
 	.driver = {
 		   .name = DRIVER_NAME,
 		   .owner = THIS_MODULE,
 		   .of_match_table = spi_imx_dt_ids,
 		   },
 	.id_table = spi_imx_devtype,
 	.probe = spi_imx_probe,
 	.remove = __devexit_p(spi_imx_remove),
 };
 module_platform_driver(spi_imx_driver);
 MODULE_DESCRIPTION("SPI Master Controller driver");
 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
 MODULE_LICENSE("GPL");

drivers/spi/spi-omap2-mcspi.c

Diff comments View file @ 0082c16

 /*
  * OMAP2 McSPI controller driver
  *
  * Copyright (C) 2005, 2006 Nokia Corporation
  * Author:	Samuel Ortiz <samuel.ortiz@nokia.com> and
  *		Juha Yrj�l� <juha.yrjola@nokia.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  *
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/module.h>
 #include <linux/device.h>
 #include <linux/delay.h>
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/slab.h>
 #include <linux/pm_runtime.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/spi/spi.h>
 #include <plat/dma.h>
 #include <plat/clock.h>
 #include <plat/mcspi.h>
 #define OMAP2_MCSPI_MAX_FREQ		48000000
 #define SPI_AUTOSUSPEND_TIMEOUT		2000
 #define OMAP2_MCSPI_REVISION		0x00
 #define OMAP2_MCSPI_SYSSTATUS		0x14
 #define OMAP2_MCSPI_IRQSTATUS		0x18
 #define OMAP2_MCSPI_IRQENABLE		0x1c
 #define OMAP2_MCSPI_WAKEUPENABLE	0x20
 #define OMAP2_MCSPI_SYST		0x24
 #define OMAP2_MCSPI_MODULCTRL		0x28
 /* per-channel banks, 0x14 bytes each, first is: */
 #define OMAP2_MCSPI_CHCONF0		0x2c
 #define OMAP2_MCSPI_CHSTAT0		0x30
 #define OMAP2_MCSPI_CHCTRL0		0x34
 #define OMAP2_MCSPI_TX0			0x38
 #define OMAP2_MCSPI_RX0			0x3c
 /* per-register bitmasks: */
 #define OMAP2_MCSPI_MODULCTRL_SINGLE	BIT(0)
 #define OMAP2_MCSPI_MODULCTRL_MS	BIT(2)
 #define OMAP2_MCSPI_MODULCTRL_STEST	BIT(3)
 #define OMAP2_MCSPI_CHCONF_PHA		BIT(0)
 #define OMAP2_MCSPI_CHCONF_POL		BIT(1)
 #define OMAP2_MCSPI_CHCONF_CLKD_MASK	(0x0f << 2)
 #define OMAP2_MCSPI_CHCONF_EPOL		BIT(6)
 #define OMAP2_MCSPI_CHCONF_WL_MASK	(0x1f << 7)
 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY	BIT(12)
 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY	BIT(13)
 #define OMAP2_MCSPI_CHCONF_TRM_MASK	(0x03 << 12)
 #define OMAP2_MCSPI_CHCONF_DMAW		BIT(14)
 #define OMAP2_MCSPI_CHCONF_DMAR		BIT(15)
 #define OMAP2_MCSPI_CHCONF_DPE0		BIT(16)
 #define OMAP2_MCSPI_CHCONF_DPE1		BIT(17)
 #define OMAP2_MCSPI_CHCONF_IS		BIT(18)
 #define OMAP2_MCSPI_CHCONF_TURBO	BIT(19)
 #define OMAP2_MCSPI_CHCONF_FORCE	BIT(20)
 #define OMAP2_MCSPI_CHSTAT_RXS		BIT(0)
 #define OMAP2_MCSPI_CHSTAT_TXS		BIT(1)
 #define OMAP2_MCSPI_CHSTAT_EOT		BIT(2)
 #define OMAP2_MCSPI_CHCTRL_EN		BIT(0)
 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN	BIT(0)
 /* We have 2 DMA channels per CS, one for RX and one for TX */
 struct omap2_mcspi_dma {
 	int dma_tx_channel;
 	int dma_rx_channel;
 	int dma_tx_sync_dev;
 	int dma_rx_sync_dev;
 	struct completion dma_tx_completion;
 	struct completion dma_rx_completion;
 };
 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
  * cache operations; better heuristics consider wordsize and bitrate.
  */
 #define DMA_MIN_BYTES			160
 /*
  * Used for context save and restore, structure members to be updated whenever
  * corresponding registers are modified.
  */
 struct omap2_mcspi_regs {
 	u32 modulctrl;
 	u32 wakeupenable;
 	struct list_head cs;
 };
 struct omap2_mcspi {
 	struct spi_master	*master;
 	/* Virtual base address of the controller */
 	void __iomem		*base;
 	unsigned long		phys;
 	/* SPI1 has 4 channels, while SPI2 has 2 */
 	struct omap2_mcspi_dma	*dma_channels;
 	struct device		*dev;
 	struct omap2_mcspi_regs ctx;
 };
 struct omap2_mcspi_cs {
 	void __iomem		*base;
 	unsigned long		phys;
 	int			word_len;
 	struct list_head	node;
 	/* Context save and restore shadow register */
 	u32			chconf0;
 };
 #define MOD_REG_BIT(val, mask, set) do { \
 	if (set) \
 		val |= mask; \
 	else \
 		val &= ~mask; \
 } while (0)
 static inline void mcspi_write_reg(struct spi_master *master,
 		int idx, u32 val)
 {
 	struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 	__raw_writel(val, mcspi->base + idx);
 }
 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
 {
 	struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 	return __raw_readl(mcspi->base + idx);
 }
 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
 		int idx, u32 val)
 {
 	struct omap2_mcspi_cs	*cs = spi->controller_state;
 	__raw_writel(val, cs->base +  idx);
 }
 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
 {
 	struct omap2_mcspi_cs	*cs = spi->controller_state;
 	return __raw_readl(cs->base + idx);
 }
 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
 {
 	struct omap2_mcspi_cs *cs = spi->controller_state;
 	return cs->chconf0;
 }
 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
 {
 	struct omap2_mcspi_cs *cs = spi->controller_state;
 	cs->chconf0 = val;
 	mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
 	mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 }
 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
 		int is_read, int enable)
 {
 	u32 l, rw;
 	l = mcspi_cached_chconf0(spi);
 	if (is_read) /* 1 is read, 0 write */
 		rw = OMAP2_MCSPI_CHCONF_DMAR;
 	else
 		rw = OMAP2_MCSPI_CHCONF_DMAW;
 	MOD_REG_BIT(l, rw, enable);
 	mcspi_write_chconf0(spi, l);
 }
 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
 {
 	u32 l;
 	l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
 	mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
 	/* Flash post-writes */
 	mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
 }
 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
 {
 	u32 l;
 	l = mcspi_cached_chconf0(spi);
 	MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
 	mcspi_write_chconf0(spi, l);
 }
 static void omap2_mcspi_set_master_mode(struct spi_master *master)
 {
 	struct omap2_mcspi	*mcspi = spi_master_get_devdata(master);
 	struct omap2_mcspi_regs	*ctx = &mcspi->ctx;
 	u32 l;
 	/*
 	 * Setup when switching from (reset default) slave mode
 	 * to single-channel master mode
 	 */
 	l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
 	MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
 	MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
 	MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
 	mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
 	ctx->modulctrl = l;
 }
 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
 {
 	struct spi_master	*spi_cntrl = mcspi->master;
 	struct omap2_mcspi_regs	*ctx = &mcspi->ctx;
 	struct omap2_mcspi_cs	*cs;
 	/* McSPI: context restore */
 	mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
 	mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
 	list_for_each_entry(cs, &ctx->cs, node)
 		__raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
 }
 static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
 {
 	pm_runtime_mark_last_busy(mcspi->dev);
 	pm_runtime_put_autosuspend(mcspi->dev);
 }
 static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
 {
 	return pm_runtime_get_sync(mcspi->dev);
 }
 static int omap2_prepare_transfer(struct spi_master *master)
 {
 	struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 	pm_runtime_get_sync(mcspi->dev);
 	return 0;
 }
 static int omap2_unprepare_transfer(struct spi_master *master)
 {
 	struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 	pm_runtime_mark_last_busy(mcspi->dev);
 	pm_runtime_put_autosuspend(mcspi->dev);
 	return 0;
 }
 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
 {
 	unsigned long timeout;
 	timeout = jiffies + msecs_to_jiffies(1000);
 	while (!(__raw_readl(reg) & bit)) {
 		if (time_after(jiffies, timeout))
 			return -1;
 		cpu_relax();
 	}
 	return 0;
 }
 static unsigned
 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
 {
 	struct omap2_mcspi	*mcspi;
 	struct omap2_mcspi_cs	*cs = spi->controller_state;
 	struct omap2_mcspi_dma  *mcspi_dma;
 	unsigned int		count, c;
 	unsigned long		base, tx_reg, rx_reg;
 	int			word_len, data_type, element_count;
 	int			elements = 0;
 	u32			l;
 	u8			* rx;
 	const u8		* tx;
 	void __iomem		*chstat_reg;
 	mcspi = spi_master_get_devdata(spi->master);
 	mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 	l = mcspi_cached_chconf0(spi);
 	chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
 	count = xfer->len;
 	c = count;
 	word_len = cs->word_len;
 	base = cs->phys;
 	tx_reg = base + OMAP2_MCSPI_TX0;
 	rx_reg = base + OMAP2_MCSPI_RX0;
 	rx = xfer->rx_buf;
 	tx = xfer->tx_buf;
 	if (word_len <= 8) {
 		data_type = OMAP_DMA_DATA_TYPE_S8;
 		element_count = count;
 	} else if (word_len <= 16) {
 		data_type = OMAP_DMA_DATA_TYPE_S16;
 		element_count = count >> 1;
 	} else /* word_len <= 32 */ {
 		data_type = OMAP_DMA_DATA_TYPE_S32;
 		element_count = count >> 2;
 	}
 	if (tx != NULL) {
 		omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel,
 				data_type, element_count, 1,
 				OMAP_DMA_SYNC_ELEMENT,
 				mcspi_dma->dma_tx_sync_dev, 0);
 		omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0,
 				OMAP_DMA_AMODE_CONSTANT,
 				tx_reg, 0, 0);
 		omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0,
 				OMAP_DMA_AMODE_POST_INC,
 				xfer->tx_dma, 0, 0);
 	}
 	if (rx != NULL) {
 		elements = element_count - 1;
 		if (l & OMAP2_MCSPI_CHCONF_TURBO)
 			elements--;
 		omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
 				data_type, elements, 1,
 				OMAP_DMA_SYNC_ELEMENT,
 				mcspi_dma->dma_rx_sync_dev, 1);
 		omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0,
 				OMAP_DMA_AMODE_CONSTANT,
 				rx_reg, 0, 0);
 		omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0,
 				OMAP_DMA_AMODE_POST_INC,
 				xfer->rx_dma, 0, 0);
 	}
 	if (tx != NULL) {
 		omap_start_dma(mcspi_dma->dma_tx_channel);
 		omap2_mcspi_set_dma_req(spi, 0, 1);
 	}
 	if (rx != NULL) {
 		omap_start_dma(mcspi_dma->dma_rx_channel);
 		omap2_mcspi_set_dma_req(spi, 1, 1);
 	}
 	if (tx != NULL) {
 		wait_for_completion(&mcspi_dma->dma_tx_completion);
-		dma_unmap_single(&spi->dev, xfer->tx_dma, count, DMA_TO_DEVICE);
+		dma_unmap_single(mcspi->dev, xfer->tx_dma, count,
+				 DMA_TO_DEVICE);
 		/* for TX_ONLY mode, be sure all words have shifted out */
 		if (rx == NULL) {
 			if (mcspi_wait_for_reg_bit(chstat_reg,
 						OMAP2_MCSPI_CHSTAT_TXS) < 0)
 				dev_err(&spi->dev, "TXS timed out\n");
 			else if (mcspi_wait_for_reg_bit(chstat_reg,
 						OMAP2_MCSPI_CHSTAT_EOT) < 0)
 				dev_err(&spi->dev, "EOT timed out\n");
 		}
 	}
 	if (rx != NULL) {
 		wait_for_completion(&mcspi_dma->dma_rx_completion);
-		dma_unmap_single(&spi->dev, xfer->rx_dma, count, DMA_FROM_DEVICE);
+		dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
+				 DMA_FROM_DEVICE);
 		omap2_mcspi_set_enable(spi, 0);
 		if (l & OMAP2_MCSPI_CHCONF_TURBO) {
 			if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
 				   & OMAP2_MCSPI_CHSTAT_RXS)) {
 				u32 w;
 				w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 				if (word_len <= 8)
 					((u8 *)xfer->rx_buf)[elements++] = w;
 				else if (word_len <= 16)
 					((u16 *)xfer->rx_buf)[elements++] = w;
 				else /* word_len <= 32 */
 					((u32 *)xfer->rx_buf)[elements++] = w;
 			} else {
 				dev_err(&spi->dev,
 					"DMA RX penultimate word empty");
 				count -= (word_len <= 8)  ? 2 :
 					(word_len <= 16) ? 4 :
 					/* word_len <= 32 */ 8;
 				omap2_mcspi_set_enable(spi, 1);
 				return count;
 			}
 		}
 		if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
 				& OMAP2_MCSPI_CHSTAT_RXS)) {
 			u32 w;
 			w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 			if (word_len <= 8)
 				((u8 *)xfer->rx_buf)[elements] = w;
 			else if (word_len <= 16)
 				((u16 *)xfer->rx_buf)[elements] = w;
 			else /* word_len <= 32 */
 				((u32 *)xfer->rx_buf)[elements] = w;
 		} else {
 			dev_err(&spi->dev, "DMA RX last word empty");
 			count -= (word_len <= 8)  ? 1 :
 				 (word_len <= 16) ? 2 :
 			       /* word_len <= 32 */ 4;
 		}
 		omap2_mcspi_set_enable(spi, 1);
 	}
 	return count;
 }
 static unsigned
 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 {
 	struct omap2_mcspi	*mcspi;
 	struct omap2_mcspi_cs	*cs = spi->controller_state;
 	unsigned int		count, c;
 	u32			l;
 	void __iomem		*base = cs->base;
 	void __iomem		*tx_reg;
 	void __iomem		*rx_reg;
 	void __iomem		*chstat_reg;
 	int			word_len;
 	mcspi = spi_master_get_devdata(spi->master);
 	count = xfer->len;
 	c = count;
 	word_len = cs->word_len;
 	l = mcspi_cached_chconf0(spi);
 	/* We store the pre-calculated register addresses on stack to speed
 	 * up the transfer loop. */
 	tx_reg		= base + OMAP2_MCSPI_TX0;
 	rx_reg		= base + OMAP2_MCSPI_RX0;
 	chstat_reg	= base + OMAP2_MCSPI_CHSTAT0;
 	if (c < (word_len>>3))
 		return 0;
 	if (word_len <= 8) {
 		u8		*rx;
 		const u8	*tx;
 		rx = xfer->rx_buf;
 		tx = xfer->tx_buf;
 		do {
 			c -= 1;
 			if (tx != NULL) {
 				if (mcspi_wait_for_reg_bit(chstat_reg,
 						OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 					dev_err(&spi->dev, "TXS timed out\n");
 					goto out;
 				}
 				dev_vdbg(&spi->dev, "write-%d %02x\n",
 						word_len, *tx);
 				__raw_writel(*tx++, tx_reg);
 			}
 			if (rx != NULL) {
 				if (mcspi_wait_for_reg_bit(chstat_reg,
 						OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 					dev_err(&spi->dev, "RXS timed out\n");
 					goto out;
 				}
 				if (c == 1 && tx == NULL &&
 				    (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 					omap2_mcspi_set_enable(spi, 0);
 					*rx++ = __raw_readl(rx_reg);
 					dev_vdbg(&spi->dev, "read-%d %02x\n",
 						    word_len, *(rx - 1));
 					if (mcspi_wait_for_reg_bit(chstat_reg,
 						OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 						dev_err(&spi->dev,
 							"RXS timed out\n");
 						goto out;
 					}
 					c = 0;
 				} else if (c == 0 && tx == NULL) {
 					omap2_mcspi_set_enable(spi, 0);
 				}
 				*rx++ = __raw_readl(rx_reg);
 				dev_vdbg(&spi->dev, "read-%d %02x\n",
 						word_len, *(rx - 1));
 			}
 		} while (c);
 	} else if (word_len <= 16) {
 		u16		*rx;
 		const u16	*tx;
 		rx = xfer->rx_buf;
 		tx = xfer->tx_buf;
 		do {
 			c -= 2;
 			if (tx != NULL) {
 				if (mcspi_wait_for_reg_bit(chstat_reg,
 						OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 					dev_err(&spi->dev, "TXS timed out\n");
 					goto out;
 				}
 				dev_vdbg(&spi->dev, "write-%d %04x\n",
 						word_len, *tx);
 				__raw_writel(*tx++, tx_reg);
 			}
 			if (rx != NULL) {
 				if (mcspi_wait_for_reg_bit(chstat_reg,
 						OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 					dev_err(&spi->dev, "RXS timed out\n");
 					goto out;
 				}
 				if (c == 2 && tx == NULL &&
 				    (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 					omap2_mcspi_set_enable(spi, 0);
 					*rx++ = __raw_readl(rx_reg);
 					dev_vdbg(&spi->dev, "read-%d %04x\n",
 						    word_len, *(rx - 1));
 					if (mcspi_wait_for_reg_bit(chstat_reg,
 						OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 						dev_err(&spi->dev,
 							"RXS timed out\n");
 						goto out;
 					}
 					c = 0;
 				} else if (c == 0 && tx == NULL) {
 					omap2_mcspi_set_enable(spi, 0);
 				}
 				*rx++ = __raw_readl(rx_reg);
 				dev_vdbg(&spi->dev, "read-%d %04x\n",
 						word_len, *(rx - 1));
 			}
 		} while (c >= 2);
 	} else if (word_len <= 32) {
 		u32		*rx;
 		const u32	*tx;
 		rx = xfer->rx_buf;
 		tx = xfer->tx_buf;
 		do {
 			c -= 4;
 			if (tx != NULL) {
 				if (mcspi_wait_for_reg_bit(chstat_reg,
 						OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 					dev_err(&spi->dev, "TXS timed out\n");
 					goto out;
 				}
 				dev_vdbg(&spi->dev, "write-%d %08x\n",
 						word_len, *tx);
 				__raw_writel(*tx++, tx_reg);
 			}
 			if (rx != NULL) {
 				if (mcspi_wait_for_reg_bit(chstat_reg,
 						OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 					dev_err(&spi->dev, "RXS timed out\n");
 					goto out;
 				}
 				if (c == 4 && tx == NULL &&
 				    (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 					omap2_mcspi_set_enable(spi, 0);
 					*rx++ = __raw_readl(rx_reg);
 					dev_vdbg(&spi->dev, "read-%d %08x\n",
 						    word_len, *(rx - 1));
 					if (mcspi_wait_for_reg_bit(chstat_reg,
 						OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 						dev_err(&spi->dev,
 							"RXS timed out\n");
 						goto out;
 					}
 					c = 0;
 				} else if (c == 0 && tx == NULL) {
 					omap2_mcspi_set_enable(spi, 0);
 				}
 				*rx++ = __raw_readl(rx_reg);
 				dev_vdbg(&spi->dev, "read-%d %08x\n",
 						word_len, *(rx - 1));
 			}
 		} while (c >= 4);
 	}
 	/* for TX_ONLY mode, be sure all words have shifted out */
 	if (xfer->rx_buf == NULL) {
 		if (mcspi_wait_for_reg_bit(chstat_reg,
 				OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 			dev_err(&spi->dev, "TXS timed out\n");
 		} else if (mcspi_wait_for_reg_bit(chstat_reg,
 				OMAP2_MCSPI_CHSTAT_EOT) < 0)
 			dev_err(&spi->dev, "EOT timed out\n");
 		/* disable chan to purge rx datas received in TX_ONLY transfer,
 		 * otherwise these rx datas will affect the direct following
 		 * RX_ONLY transfer.
 		 */
 		omap2_mcspi_set_enable(spi, 0);
 	}
 out:
 	omap2_mcspi_set_enable(spi, 1);
 	return count - c;
 }
 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
 {
 	u32 div;
 	for (div = 0; div < 15; div++)
 		if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
 			return div;
 	return 15;
 }
 /* called only when no transfer is active to this device */
 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
 		struct spi_transfer *t)
 {
 	struct omap2_mcspi_cs *cs = spi->controller_state;
 	struct omap2_mcspi *mcspi;
 	struct spi_master *spi_cntrl;
 	u32 l = 0, div = 0;
 	u8 word_len = spi->bits_per_word;
 	u32 speed_hz = spi->max_speed_hz;
 	mcspi = spi_master_get_devdata(spi->master);
 	spi_cntrl = mcspi->master;
 	if (t != NULL && t->bits_per_word)
 		word_len = t->bits_per_word;
 	cs->word_len = word_len;
 	if (t && t->speed_hz)
 		speed_hz = t->speed_hz;
 	speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
 	div = omap2_mcspi_calc_divisor(speed_hz);
 	l = mcspi_cached_chconf0(spi);
 	/* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
 	 * REVISIT: this controller could support SPI_3WIRE mode.
 	 */
 	l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
 	l |= OMAP2_MCSPI_CHCONF_DPE0;
 	/* wordlength */
 	l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
 	l |= (word_len - 1) << 7;
 	/* set chipselect polarity; manage with FORCE */
 	if (!(spi->mode & SPI_CS_HIGH))
 		l |= OMAP2_MCSPI_CHCONF_EPOL;	/* active-low; normal */
 	else
 		l &= ~OMAP2_MCSPI_CHCONF_EPOL;
 	/* set clock divisor */
 	l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
 	l |= div << 2;
 	/* set SPI mode 0..3 */
 	if (spi->mode & SPI_CPOL)
 		l |= OMAP2_MCSPI_CHCONF_POL;
 	else
 		l &= ~OMAP2_MCSPI_CHCONF_POL;
 	if (spi->mode & SPI_CPHA)
 		l |= OMAP2_MCSPI_CHCONF_PHA;
 	else
 		l &= ~OMAP2_MCSPI_CHCONF_PHA;
 	mcspi_write_chconf0(spi, l);
 	dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
 			OMAP2_MCSPI_MAX_FREQ >> div,
 			(spi->mode & SPI_CPHA) ? "trailing" : "leading",
 			(spi->mode & SPI_CPOL) ? "inverted" : "normal");
 	return 0;
 }
 static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data)
 {
 	struct spi_device	*spi = data;
 	struct omap2_mcspi	*mcspi;
 	struct omap2_mcspi_dma	*mcspi_dma;
 	mcspi = spi_master_get_devdata(spi->master);
 	mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
 	complete(&mcspi_dma->dma_rx_completion);
 	/* We must disable the DMA RX request */
 	omap2_mcspi_set_dma_req(spi, 1, 0);
 }
 static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
 {
 	struct spi_device	*spi = data;
 	struct omap2_mcspi	*mcspi;
 	struct omap2_mcspi_dma	*mcspi_dma;
 	mcspi = spi_master_get_devdata(spi->master);
 	mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
 	complete(&mcspi_dma->dma_tx_completion);
 	/* We must disable the DMA TX request */
 	omap2_mcspi_set_dma_req(spi, 0, 0);
 }
 static int omap2_mcspi_request_dma(struct spi_device *spi)
 {
 	struct spi_master	*master = spi->master;
 	struct omap2_mcspi	*mcspi;
 	struct omap2_mcspi_dma	*mcspi_dma;
 	mcspi = spi_master_get_devdata(master);
 	mcspi_dma = mcspi->dma_channels + spi->chip_select;
 	if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX",
 			omap2_mcspi_dma_rx_callback, spi,
 			&mcspi_dma->dma_rx_channel)) {
 		dev_err(&spi->dev, "no RX DMA channel for McSPI\n");
 		return -EAGAIN;
 	}
 	if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX",
 			omap2_mcspi_dma_tx_callback, spi,
 			&mcspi_dma->dma_tx_channel)) {
 		omap_free_dma(mcspi_dma->dma_rx_channel);
 		mcspi_dma->dma_rx_channel = -1;
 		dev_err(&spi->dev, "no TX DMA channel for McSPI\n");
 		return -EAGAIN;
 	}
 	init_completion(&mcspi_dma->dma_rx_completion);
 	init_completion(&mcspi_dma->dma_tx_completion);
 	return 0;
 }
 static int omap2_mcspi_setup(struct spi_device *spi)
 {
 	int			ret;
 	struct omap2_mcspi	*mcspi = spi_master_get_devdata(spi->master);
 	struct omap2_mcspi_regs	*ctx = &mcspi->ctx;
 	struct omap2_mcspi_dma	*mcspi_dma;
 	struct omap2_mcspi_cs	*cs = spi->controller_state;
 	if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
 		dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
 			spi->bits_per_word);
 		return -EINVAL;
 	}
 	mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 	if (!cs) {
 		cs = kzalloc(sizeof *cs, GFP_KERNEL);
 		if (!cs)
 			return -ENOMEM;
 		cs->base = mcspi->base + spi->chip_select * 0x14;
 		cs->phys = mcspi->phys + spi->chip_select * 0x14;
 		cs->chconf0 = 0;
 		spi->controller_state = cs;
 		/* Link this to context save list */
 		list_add_tail(&cs->node, &ctx->cs);
 	}
 	if (mcspi_dma->dma_rx_channel == -1
 			|| mcspi_dma->dma_tx_channel == -1) {
 		ret = omap2_mcspi_request_dma(spi);
 		if (ret < 0)
 			return ret;
 	}
 	ret = omap2_mcspi_enable_clocks(mcspi);
 	if (ret < 0)
 		return ret;
 	ret = omap2_mcspi_setup_transfer(spi, NULL);
 	omap2_mcspi_disable_clocks(mcspi);
 	return ret;
 }
 static void omap2_mcspi_cleanup(struct spi_device *spi)
 {
 	struct omap2_mcspi	*mcspi;
 	struct omap2_mcspi_dma	*mcspi_dma;
 	struct omap2_mcspi_cs	*cs;
 	mcspi = spi_master_get_devdata(spi->master);
 	if (spi->controller_state) {
 		/* Unlink controller state from context save list */
 		cs = spi->controller_state;
 		list_del(&cs->node);
 		kfree(cs);
 	}
 	if (spi->chip_select < spi->master->num_chipselect) {
 		mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 		if (mcspi_dma->dma_rx_channel != -1) {
 			omap_free_dma(mcspi_dma->dma_rx_channel);
 			mcspi_dma->dma_rx_channel = -1;
 		}
 		if (mcspi_dma->dma_tx_channel != -1) {
 			omap_free_dma(mcspi_dma->dma_tx_channel);
 			mcspi_dma->dma_tx_channel = -1;
 		}
 	}
 }
 static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
 {
 	/* We only enable one channel at a time -- the one whose message is
 	 * -- although this controller would gladly
 	 * arbitrate among multiple channels.  This corresponds to "single
 	 * channel" master mode.  As a side effect, we need to manage the
 	 * chipselect with the FORCE bit ... CS != channel enable.
 	 */
 	struct spi_device		*spi;
 	struct spi_transfer		*t = NULL;
 	int				cs_active = 0;
 	struct omap2_mcspi_cs		*cs;
 	struct omap2_mcspi_device_config *cd;
 	int				par_override = 0;
 	int				status = 0;
 	u32				chconf;
 	spi = m->spi;
 	cs = spi->controller_state;
 	cd = spi->controller_data;
 	omap2_mcspi_set_enable(spi, 1);
 	list_for_each_entry(t, &m->transfers, transfer_list) {
 		if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
 			status = -EINVAL;
 			break;
 		}
 		if (par_override || t->speed_hz || t->bits_per_word) {
 			par_override = 1;
 			status = omap2_mcspi_setup_transfer(spi, t);
 			if (status < 0)
 				break;
 			if (!t->speed_hz && !t->bits_per_word)
 				par_override = 0;
 		}
 		if (!cs_active) {
 			omap2_mcspi_force_cs(spi, 1);
 			cs_active = 1;
 		}
 		chconf = mcspi_cached_chconf0(spi);
 		chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
 		chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
 		if (t->tx_buf == NULL)
 			chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
 		else if (t->rx_buf == NULL)
 			chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
 		if (cd && cd->turbo_mode && t->tx_buf == NULL) {
 			/* Turbo mode is for more than one word */
 			if (t->len > ((cs->word_len + 7) >> 3))
 				chconf |= OMAP2_MCSPI_CHCONF_TURBO;
 		}
 		mcspi_write_chconf0(spi, chconf);
 		if (t->len) {
 			unsigned	count;
 			/* RX_ONLY mode needs dummy data in TX reg */
 			if (t->tx_buf == NULL)
 				__raw_writel(0, cs->base
 						+ OMAP2_MCSPI_TX0);
 			if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
 				count = omap2_mcspi_txrx_dma(spi, t);
 			else
 				count = omap2_mcspi_txrx_pio(spi, t);
 			m->actual_length += count;
 			if (count != t->len) {
 				status = -EIO;
 				break;
 			}
 		}
 		if (t->delay_usecs)
 			udelay(t->delay_usecs);
 		/* ignore the "leave it on after last xfer" hint */
 		if (t->cs_change) {
 			omap2_mcspi_force_cs(spi, 0);
 			cs_active = 0;
 		}
 	}
 	/* Restore defaults if they were overriden */
 	if (par_override) {
 		par_override = 0;
 		status = omap2_mcspi_setup_transfer(spi, NULL);
 	}
 	if (cs_active)
 		omap2_mcspi_force_cs(spi, 0);
 	omap2_mcspi_set_enable(spi, 0);
 	m->status = status;
 }
 static int omap2_mcspi_transfer_one_message(struct spi_master *master,
 						struct spi_message *m)
 {
 	struct omap2_mcspi	*mcspi;
 	struct spi_transfer	*t;
 	mcspi = spi_master_get_devdata(master);
 	m->actual_length = 0;
 	m->status = 0;
 	/* reject invalid messages and transfers */
 	if (list_empty(&m->transfers))
 		return -EINVAL;
 	list_for_each_entry(t, &m->transfers, transfer_list) {
 		const void	*tx_buf = t->tx_buf;
 		void		*rx_buf = t->rx_buf;
 		unsigned	len = t->len;
 		if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
 				|| (len && !(rx_buf || tx_buf))
 				|| (t->bits_per_word &&
 					(  t->bits_per_word < 4
 					|| t->bits_per_word > 32))) {
 			dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
 					t->speed_hz,
 					len,
 					tx_buf ? "tx" : "",
 					rx_buf ? "rx" : "",
 					t->bits_per_word);
 			return -EINVAL;
 		}
 		if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
 			dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n",
 				t->speed_hz,
 				OMAP2_MCSPI_MAX_FREQ >> 15);
 			return -EINVAL;
 		}
 		if (m->is_dma_mapped || len < DMA_MIN_BYTES)
 			continue;
 		if (tx_buf != NULL) {
 			t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
 					len, DMA_TO_DEVICE);
 			if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
 				dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
 						'T', len);
 				return -EINVAL;
 			}
 		}
 		if (rx_buf != NULL) {
 			t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
 					DMA_FROM_DEVICE);
 			if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
 				dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
 						'R', len);
 				if (tx_buf != NULL)
 					dma_unmap_single(mcspi->dev, t->tx_dma,
 							len, DMA_TO_DEVICE);
 				return -EINVAL;
 			}
 		}
 	}
 	omap2_mcspi_work(mcspi, m);
 	spi_finalize_current_message(master);
 	return 0;
 }
-static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
+static int __devinit omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
 {
 	struct spi_master	*master = mcspi->master;
 	struct omap2_mcspi_regs	*ctx = &mcspi->ctx;
 	int			ret = 0;
 	ret = omap2_mcspi_enable_clocks(mcspi);
 	if (ret < 0)
 		return ret;
 	mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
 				OMAP2_MCSPI_WAKEUPENABLE_WKEN);
 	ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
 	omap2_mcspi_set_master_mode(master);
 	omap2_mcspi_disable_clocks(mcspi);
 	return 0;
 }
 static int omap_mcspi_runtime_resume(struct device *dev)
 {
 	struct omap2_mcspi	*mcspi;
 	struct spi_master	*master;
 	master = dev_get_drvdata(dev);
 	mcspi = spi_master_get_devdata(master);
 	omap2_mcspi_restore_ctx(mcspi);
 	return 0;
 }
 static struct omap2_mcspi_platform_config omap2_pdata = {
 	.regs_offset = 0,
 };
 static struct omap2_mcspi_platform_config omap4_pdata = {
 	.regs_offset = OMAP4_MCSPI_REG_OFFSET,
 };
 static const struct of_device_id omap_mcspi_of_match[] = {
 	{
 		.compatible = "ti,omap2-mcspi",
 		.data = &omap2_pdata,
 	},
 	{
 		.compatible = "ti,omap4-mcspi",
 		.data = &omap4_pdata,
 	},
 	{ },
 };
 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
 static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
 {
 	struct spi_master	*master;
 	struct omap2_mcspi_platform_config *pdata;
 	struct omap2_mcspi	*mcspi;
 	struct resource		*r;
 	int			status = 0, i;
 	u32			regs_offset = 0;
 	static int		bus_num = 1;
 	struct device_node	*node = pdev->dev.of_node;
 	const struct of_device_id *match;
 	master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
 	if (master == NULL) {
 		dev_dbg(&pdev->dev, "master allocation failed\n");
 		return -ENOMEM;
 	}
 	/* the spi->mode bits understood by this driver: */
 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 	master->setup = omap2_mcspi_setup;
 	master->prepare_transfer_hardware = omap2_prepare_transfer;
 	master->unprepare_transfer_hardware = omap2_unprepare_transfer;
 	master->transfer_one_message = omap2_mcspi_transfer_one_message;
 	master->cleanup = omap2_mcspi_cleanup;
 	master->dev.of_node = node;
 	match = of_match_device(omap_mcspi_of_match, &pdev->dev);
 	if (match) {
 		u32 num_cs = 1; /* default number of chipselect */
 		pdata = match->data;
 		of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
 		master->num_chipselect = num_cs;
 		master->bus_num = bus_num++;
 	} else {
 		pdata = pdev->dev.platform_data;
 		master->num_chipselect = pdata->num_cs;
 		if (pdev->id != -1)
 			master->bus_num = pdev->id;
 	}
 	regs_offset = pdata->regs_offset;
 	dev_set_drvdata(&pdev->dev, master);
 	mcspi = spi_master_get_devdata(master);
 	mcspi->master = master;
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (r == NULL) {
 		status = -ENODEV;
 		goto free_master;
 	}
 	r->start += regs_offset;
 	r->end += regs_offset;
 	mcspi->phys = r->start;
 	mcspi->base = devm_request_and_ioremap(&pdev->dev, r);
 	if (!mcspi->base) {
 		dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
 		status = -ENOMEM;
 		goto free_master;
 	}
 	mcspi->dev = &pdev->dev;
 	INIT_LIST_HEAD(&mcspi->ctx.cs);
 	mcspi->dma_channels = kcalloc(master->num_chipselect,
 			sizeof(struct omap2_mcspi_dma),
 			GFP_KERNEL);
 	if (mcspi->dma_channels == NULL)
 		goto free_master;
 	for (i = 0; i < master->num_chipselect; i++) {
 		char dma_ch_name[14];
 		struct resource *dma_res;
 		sprintf(dma_ch_name, "rx%d", i);
 		dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
 							dma_ch_name);
 		if (!dma_res) {
 			dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
 			status = -ENODEV;
 			break;
 		}
 		mcspi->dma_channels[i].dma_rx_channel = -1;
 		mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
 		sprintf(dma_ch_name, "tx%d", i);
 		dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
 							dma_ch_name);
 		if (!dma_res) {
 			dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
 			status = -ENODEV;
 			break;
 		}
 		mcspi->dma_channels[i].dma_tx_channel = -1;
 		mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
 	}
 	if (status < 0)
 		goto dma_chnl_free;
 	pm_runtime_use_autosuspend(&pdev->dev);
 	pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
 	pm_runtime_enable(&pdev->dev);
 	if (status || omap2_mcspi_master_setup(mcspi) < 0)
 		goto disable_pm;
 	status = spi_register_master(master);
 	if (status < 0)
 		goto err_spi_register;
 	return status;
 err_spi_register:
 	spi_master_put(master);
 disable_pm:
 	pm_runtime_disable(&pdev->dev);
 dma_chnl_free:
 	kfree(mcspi->dma_channels);
 free_master:
 	kfree(master);
 	platform_set_drvdata(pdev, NULL);
 	return status;
 }
 static int __devexit omap2_mcspi_remove(struct platform_device *pdev)
 {
 	struct spi_master	*master;
 	struct omap2_mcspi	*mcspi;
 	struct omap2_mcspi_dma	*dma_channels;
 	master = dev_get_drvdata(&pdev->dev);
 	mcspi = spi_master_get_devdata(master);
 	dma_channels = mcspi->dma_channels;
 	omap2_mcspi_disable_clocks(mcspi);
 	pm_runtime_disable(&pdev->dev);
 	spi_unregister_master(master);
 	kfree(dma_channels);
 	platform_set_drvdata(pdev, NULL);
 	return 0;
 }
 /* work with hotplug and coldplug */
 MODULE_ALIAS("platform:omap2_mcspi");
 #ifdef	CONFIG_SUSPEND
 /*
  * When SPI wake up from off-mode, CS is in activate state. If it was in
  * unactive state when driver was suspend, then force it to unactive state at
  * wake up.
  */
 static int omap2_mcspi_resume(struct device *dev)
 {
 	struct spi_master	*master = dev_get_drvdata(dev);
 	struct omap2_mcspi	*mcspi = spi_master_get_devdata(master);
 	struct omap2_mcspi_regs	*ctx = &mcspi->ctx;
 	struct omap2_mcspi_cs	*cs;
 	omap2_mcspi_enable_clocks(mcspi);
 	list_for_each_entry(cs, &ctx->cs, node) {
 		if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
 			/*
 			 * We need to toggle CS state for OMAP take this
 			 * change in account.
 			 */
 			MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 1);
 			__raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
 			MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 0);
 			__raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
 		}
 	}
 	omap2_mcspi_disable_clocks(mcspi);
 	return 0;
 }
 #else
 #define	omap2_mcspi_resume	NULL
 #endif
 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
 	.resume = omap2_mcspi_resume,
 	.runtime_resume	= omap_mcspi_runtime_resume,
 };
 static struct platform_driver omap2_mcspi_driver = {
 	.driver = {
 		.name =		"omap2_mcspi",
 		.owner =	THIS_MODULE,
 		.pm =		&omap2_mcspi_pm_ops,
 		.of_match_table = omap_mcspi_of_match,
 	},
 	.probe =	omap2_mcspi_probe,
 	.remove =	__devexit_p(omap2_mcspi_remove),
 };
 module_platform_driver(omap2_mcspi_driver);
 MODULE_LICENSE("GPL");

drivers/spi/spi-orion.c

Diff comments View file @ 0082c16

 /*
  * Marvell Orion SPI controller driver
  *
  * Author: Shadi Ammouri <shadi@marvell.com>
  * Copyright (C) 2007-2008 Marvell Ltd.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/delay.h>
 #include <linux/platform_device.h>
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/spi/spi.h>
 #include <linux/module.h>
+#include <linux/of.h>
 #include <linux/clk.h>
 #include <asm/unaligned.h>
 #define DRIVER_NAME			"orion_spi"
 #define ORION_NUM_CHIPSELECTS		1 /* only one slave is supported*/
 #define ORION_SPI_WAIT_RDY_MAX_LOOP	2000 /* in usec */
 #define ORION_SPI_IF_CTRL_REG		0x00
 #define ORION_SPI_IF_CONFIG_REG		0x04
 #define ORION_SPI_DATA_OUT_REG		0x08
 #define ORION_SPI_DATA_IN_REG		0x0c
 #define ORION_SPI_INT_CAUSE_REG		0x10
 #define ORION_SPI_IF_8_16_BIT_MODE	(1 << 5)
 #define ORION_SPI_CLK_PRESCALE_MASK	0x1F
 struct orion_spi {
 	struct work_struct	work;
 	/* Lock access to transfer list.	*/
 	spinlock_t		lock;
 	struct list_head	msg_queue;
 	struct spi_master	*master;
 	void __iomem		*base;
 	unsigned int		max_speed;
 	unsigned int		min_speed;
-	struct orion_spi_info	*spi_info;
 	struct clk              *clk;
 };
 static struct workqueue_struct *orion_spi_wq;
 static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
 {
 	return orion_spi->base + reg;
 }
 static inline void
 orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
 {
 	void __iomem *reg_addr = spi_reg(orion_spi, reg);
 	u32 val;
 	val = readl(reg_addr);
 	val |= mask;
 	writel(val, reg_addr);
 }
 static inline void
 orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
 {
 	void __iomem *reg_addr = spi_reg(orion_spi, reg);
 	u32 val;
 	val = readl(reg_addr);
 	val &= ~mask;
 	writel(val, reg_addr);
 }
 static int orion_spi_set_transfer_size(struct orion_spi *orion_spi, int size)
 {
 	if (size == 16) {
 		orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
 				  ORION_SPI_IF_8_16_BIT_MODE);
 	} else if (size == 8) {
 		orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
 				  ORION_SPI_IF_8_16_BIT_MODE);
 	} else {
 		pr_debug("Bad bits per word value %d (only 8 or 16 are "
 			 "allowed).\n", size);
 		return -EINVAL;
 	}
 	return 0;
 }
 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
 {
 	u32 tclk_hz;
 	u32 rate;
 	u32 prescale;
 	u32 reg;
 	struct orion_spi *orion_spi;
 	orion_spi = spi_master_get_devdata(spi->master);
 	tclk_hz = clk_get_rate(orion_spi->clk);
 	/*
 	 * the supported rates are: 4,6,8...30
 	 * round up as we look for equal or less speed
 	 */
 	rate = DIV_ROUND_UP(tclk_hz, speed);
 	rate = roundup(rate, 2);
 	/* check if requested speed is too small */
 	if (rate > 30)
 		return -EINVAL;
 	if (rate < 4)
 		rate = 4;
 	/* Convert the rate to SPI clock divisor value.	*/
 	prescale = 0x10 + rate/2;
 	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
 	reg = ((reg & ~ORION_SPI_CLK_PRESCALE_MASK) | prescale);
 	writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
 	return 0;
 }
 /*
  * called only when no transfer is active on the bus
  */
 static int
 orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 {
 	struct orion_spi *orion_spi;
 	unsigned int speed = spi->max_speed_hz;
 	unsigned int bits_per_word = spi->bits_per_word;
 	int	rc;
 	orion_spi = spi_master_get_devdata(spi->master);
 	if ((t != NULL) && t->speed_hz)
 		speed = t->speed_hz;
 	if ((t != NULL) && t->bits_per_word)
 		bits_per_word = t->bits_per_word;
 	rc = orion_spi_baudrate_set(spi, speed);
 	if (rc)
 		return rc;
 	return orion_spi_set_transfer_size(orion_spi, bits_per_word);
 }
 static void orion_spi_set_cs(struct orion_spi *orion_spi, int enable)
 {
 	if (enable)
 		orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
 	else
 		orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
 }
 static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
 {
 	int i;
 	for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
 		if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
 			return 1;
 		else
 			udelay(1);
 	}
 	return -1;
 }
 static inline int
 orion_spi_write_read_8bit(struct spi_device *spi,
 			  const u8 **tx_buf, u8 **rx_buf)
 {
 	void __iomem *tx_reg, *rx_reg, *int_reg;
 	struct orion_spi *orion_spi;
 	orion_spi = spi_master_get_devdata(spi->master);
 	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
 	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
 	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
 	/* clear the interrupt cause register */
 	writel(0x0, int_reg);
 	if (tx_buf && *tx_buf)
 		writel(*(*tx_buf)++, tx_reg);
 	else
 		writel(0, tx_reg);
 	if (orion_spi_wait_till_ready(orion_spi) < 0) {
 		dev_err(&spi->dev, "TXS timed out\n");
 		return -1;
 	}
 	if (rx_buf && *rx_buf)
 		*(*rx_buf)++ = readl(rx_reg);
 	return 1;
 }
 static inline int
 orion_spi_write_read_16bit(struct spi_device *spi,
 			   const u16 **tx_buf, u16 **rx_buf)
 {
 	void __iomem *tx_reg, *rx_reg, *int_reg;
 	struct orion_spi *orion_spi;
 	orion_spi = spi_master_get_devdata(spi->master);
 	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
 	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
 	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
 	/* clear the interrupt cause register */
 	writel(0x0, int_reg);
 	if (tx_buf && *tx_buf)
 		writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
 	else
 		writel(0, tx_reg);
 	if (orion_spi_wait_till_ready(orion_spi) < 0) {
 		dev_err(&spi->dev, "TXS timed out\n");
 		return -1;
 	}
 	if (rx_buf && *rx_buf)
 		put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
 	return 1;
 }
 static unsigned int
 orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
 {
 	struct orion_spi *orion_spi;
 	unsigned int count;
 	int word_len;
 	orion_spi = spi_master_get_devdata(spi->master);
 	word_len = spi->bits_per_word;
 	count = xfer->len;
 	if (word_len == 8) {
 		const u8 *tx = xfer->tx_buf;
 		u8 *rx = xfer->rx_buf;
 		do {
 			if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
 				goto out;
 			count--;
 		} while (count);
 	} else if (word_len == 16) {
 		const u16 *tx = xfer->tx_buf;
 		u16 *rx = xfer->rx_buf;
 		do {
 			if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
 				goto out;
 			count -= 2;
 		} while (count);
 	}
 out:
 	return xfer->len - count;
 }
 static void orion_spi_work(struct work_struct *work)
 {
 	struct orion_spi *orion_spi =
 		container_of(work, struct orion_spi, work);
 	spin_lock_irq(&orion_spi->lock);
 	while (!list_empty(&orion_spi->msg_queue)) {
 		struct spi_message *m;
 		struct spi_device *spi;
 		struct spi_transfer *t = NULL;
 		int par_override = 0;
 		int status = 0;
 		int cs_active = 0;
 		m = container_of(orion_spi->msg_queue.next, struct spi_message,
 				 queue);
 		list_del_init(&m->queue);
 		spin_unlock_irq(&orion_spi->lock);
 		spi = m->spi;
 		/* Load defaults */
 		status = orion_spi_setup_transfer(spi, NULL);
 		if (status < 0)
 			goto msg_done;
 		list_for_each_entry(t, &m->transfers, transfer_list) {
 			if (par_override || t->speed_hz || t->bits_per_word) {
 				par_override = 1;
 				status = orion_spi_setup_transfer(spi, t);
 				if (status < 0)
 					break;
 				if (!t->speed_hz && !t->bits_per_word)
 					par_override = 0;
 			}
 			if (!cs_active) {
 				orion_spi_set_cs(orion_spi, 1);
 				cs_active = 1;
 			}
 			if (t->len)
 				m->actual_length +=
 					orion_spi_write_read(spi, t);
 			if (t->delay_usecs)
 				udelay(t->delay_usecs);
 			if (t->cs_change) {
 				orion_spi_set_cs(orion_spi, 0);
 				cs_active = 0;
 			}
 		}
 msg_done:
 		if (cs_active)
 			orion_spi_set_cs(orion_spi, 0);
 		m->status = status;
 		m->complete(m->context);
 		spin_lock_irq(&orion_spi->lock);
 	}
 	spin_unlock_irq(&orion_spi->lock);
 }
 static int __init orion_spi_reset(struct orion_spi *orion_spi)
 {
 	/* Verify that the CS is deasserted */
 	orion_spi_set_cs(orion_spi, 0);
 	return 0;
 }
 static int orion_spi_setup(struct spi_device *spi)
 {
 	struct orion_spi *orion_spi;
 	orion_spi = spi_master_get_devdata(spi->master);
 	if ((spi->max_speed_hz == 0)
 			|| (spi->max_speed_hz > orion_spi->max_speed))
 		spi->max_speed_hz = orion_spi->max_speed;
 	if (spi->max_speed_hz < orion_spi->min_speed) {
 		dev_err(&spi->dev, "setup: requested speed too low %d Hz\n",
 			spi->max_speed_hz);
 		return -EINVAL;
 	}
 	/*
 	 * baudrate & width will be set orion_spi_setup_transfer
 	 */
 	return 0;
 }
 static int orion_spi_transfer(struct spi_device *spi, struct spi_message *m)
 {
 	struct orion_spi *orion_spi;
 	struct spi_transfer *t = NULL;
 	unsigned long flags;
 	m->actual_length = 0;
 	m->status = 0;
 	/* reject invalid messages and transfers */
 	if (list_empty(&m->transfers) || !m->complete)
 		return -EINVAL;
 	orion_spi = spi_master_get_devdata(spi->master);
 	list_for_each_entry(t, &m->transfers, transfer_list) {
 		unsigned int bits_per_word = spi->bits_per_word;
 		if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
 			dev_err(&spi->dev,
 				"message rejected : "
 				"invalid transfer data buffers\n");
 			goto msg_rejected;
 		}
 		if (t->bits_per_word)
 			bits_per_word = t->bits_per_word;
 		if ((bits_per_word != 8) && (bits_per_word != 16)) {
 			dev_err(&spi->dev,
 				"message rejected : "
 				"invalid transfer bits_per_word (%d bits)\n",
 				bits_per_word);
 			goto msg_rejected;
 		}
 		/*make sure buffer length is even when working in 16 bit mode*/
 		if ((t->bits_per_word == 16) && (t->len & 1)) {
 			dev_err(&spi->dev,
 				"message rejected : "
 				"odd data length (%d) while in 16 bit mode\n",
 				t->len);
 			goto msg_rejected;
 		}
 		if (t->speed_hz && t->speed_hz < orion_spi->min_speed) {
 			dev_err(&spi->dev,
 				"message rejected : "
 				"device min speed (%d Hz) exceeds "
 				"required transfer speed (%d Hz)\n",
 				orion_spi->min_speed, t->speed_hz);
 			goto msg_rejected;
 		}
 	}
 	spin_lock_irqsave(&orion_spi->lock, flags);
 	list_add_tail(&m->queue, &orion_spi->msg_queue);
 	queue_work(orion_spi_wq, &orion_spi->work);
 	spin_unlock_irqrestore(&orion_spi->lock, flags);
 	return 0;
 msg_rejected:
 	/* Message rejected and not queued */
 	m->status = -EINVAL;
 	if (m->complete)
 		m->complete(m->context);
 	return -EINVAL;
 }
 static int __init orion_spi_probe(struct platform_device *pdev)
 {
 	struct spi_master *master;
 	struct orion_spi *spi;
 	struct resource *r;
-	struct orion_spi_info *spi_info;
 	unsigned long tclk_hz;
 	int status = 0;
+	const u32 *iprop;
+	int size;
-	spi_info = pdev->dev.platform_data;
 	master = spi_alloc_master(&pdev->dev, sizeof *spi);
 	if (master == NULL) {
 		dev_dbg(&pdev->dev, "master allocation failed\n");
 		return -ENOMEM;
 	}
 	if (pdev->id != -1)
 		master->bus_num = pdev->id;
+	if (pdev->dev.of_node) {
+		iprop = of_get_property(pdev->dev.of_node, "cell-index",
+					&size);
+		if (iprop && size == sizeof(*iprop))
+			master->bus_num = *iprop;
+	}
 	/* we support only mode 0, and no options */
 	master->mode_bits = 0;
 	master->setup = orion_spi_setup;
 	master->transfer = orion_spi_transfer;
 	master->num_chipselect = ORION_NUM_CHIPSELECTS;
 	dev_set_drvdata(&pdev->dev, master);
 	spi = spi_master_get_devdata(master);
 	spi->master = master;
-	spi->spi_info = spi_info;
 	spi->clk = clk_get(&pdev->dev, NULL);
 	if (IS_ERR(spi->clk)) {
 		status = PTR_ERR(spi->clk);
 		goto out;
 	}
 	clk_prepare(spi->clk);
 	clk_enable(spi->clk);
 	tclk_hz = clk_get_rate(spi->clk);
 	spi->max_speed = DIV_ROUND_UP(tclk_hz, 4);
 	spi->min_speed = DIV_ROUND_UP(tclk_hz, 30);
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (r == NULL) {
 		status = -ENODEV;
 		goto out_rel_clk;
 	}
 	if (!request_mem_region(r->start, resource_size(r),
 				dev_name(&pdev->dev))) {
 		status = -EBUSY;
 		goto out_rel_clk;
 	}
 	spi->base = ioremap(r->start, SZ_1K);
 	INIT_WORK(&spi->work, orion_spi_work);
 	spin_lock_init(&spi->lock);
 	INIT_LIST_HEAD(&spi->msg_queue);
 	if (orion_spi_reset(spi) < 0)
 		goto out_rel_mem;
+	master->dev.of_node = pdev->dev.of_node;
 	status = spi_register_master(master);
 	if (status < 0)
 		goto out_rel_mem;
 	return status;
 out_rel_mem:
 	release_mem_region(r->start, resource_size(r));
 out_rel_clk:
 	clk_disable_unprepare(spi->clk);
 	clk_put(spi->clk);
 out:
 	spi_master_put(master);
 	return status;
 }
 static int __exit orion_spi_remove(struct platform_device *pdev)
 {
 	struct spi_master *master;
 	struct orion_spi *spi;
 	struct resource *r;
 	master = dev_get_drvdata(&pdev->dev);
 	spi = spi_master_get_devdata(master);
 	cancel_work_sync(&spi->work);
 	clk_disable_unprepare(spi->clk);
 	clk_put(spi->clk);
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	release_mem_region(r->start, resource_size(r));
 	spi_unregister_master(master);
 	return 0;
 }
 MODULE_ALIAS("platform:" DRIVER_NAME);
+static const struct of_device_id orion_spi_of_match_table[] __devinitdata = {
+	{ .compatible = "marvell,orion-spi", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
 static struct platform_driver orion_spi_driver = {
 	.driver = {
 		.name	= DRIVER_NAME,
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(orion_spi_of_match_table),
 	},
 	.remove		= __exit_p(orion_spi_remove),
 };
 static int __init orion_spi_init(void)
 {
 	orion_spi_wq = create_singlethread_workqueue(
 				orion_spi_driver.driver.name);
 	if (orion_spi_wq == NULL)
 		return -ENOMEM;
 	return platform_driver_probe(&orion_spi_driver, orion_spi_probe);
 }
 module_init(orion_spi_init);
 static void __exit orion_spi_exit(void)
 {
 	flush_workqueue(orion_spi_wq);
 	platform_driver_unregister(&orion_spi_driver);
 	destroy_workqueue(orion_spi_wq);
 }
 module_exit(orion_spi_exit);

drivers/spi/spi-pl022.c

Diff comments View file @ 0082c16

 /*
  * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
  *
  * Copyright (C) 2008-2009 ST-Ericsson AB
  * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
  *
  * Author: Linus Walleij <linus.walleij@stericsson.com>
  *
  * Initial version inspired by:
  *	linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
  * Initial adoption to PL022 by:
  *      Sachin Verma <sachin.verma@st.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/device.h>
 #include <linux/ioport.h>
 #include <linux/errno.h>
 #include <linux/interrupt.h>
 #include <linux/spi/spi.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/pl022.h>
 #include <linux/io.h>
 #include <linux/slab.h>
 #include <linux/dmaengine.h>
 #include <linux/dma-mapping.h>
 #include <linux/scatterlist.h>
 #include <linux/pm_runtime.h>
 /*
  * This macro is used to define some register default values.
  * reg is masked with mask, the OR:ed with an (again masked)
  * val shifted sb steps to the left.
  */
 #define SSP_WRITE_BITS(reg, val, mask, sb) \
  ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
 /*
  * This macro is also used to define some default values.
  * It will just shift val by sb steps to the left and mask
  * the result with mask.
  */
 #define GEN_MASK_BITS(val, mask, sb) \
  (((val)<<(sb)) & (mask))
 #define DRIVE_TX		0
 #define DO_NOT_DRIVE_TX		1
 #define DO_NOT_QUEUE_DMA	0
 #define QUEUE_DMA		1
 #define RX_TRANSFER		1
 #define TX_TRANSFER		2
 /*
  * Macros to access SSP Registers with their offsets
  */
 #define SSP_CR0(r)	(r + 0x000)
 #define SSP_CR1(r)	(r + 0x004)
 #define SSP_DR(r)	(r + 0x008)
 #define SSP_SR(r)	(r + 0x00C)
 #define SSP_CPSR(r)	(r + 0x010)
 #define SSP_IMSC(r)	(r + 0x014)
 #define SSP_RIS(r)	(r + 0x018)
 #define SSP_MIS(r)	(r + 0x01C)
 #define SSP_ICR(r)	(r + 0x020)
 #define SSP_DMACR(r)	(r + 0x024)
 #define SSP_ITCR(r)	(r + 0x080)
 #define SSP_ITIP(r)	(r + 0x084)
 #define SSP_ITOP(r)	(r + 0x088)
 #define SSP_TDR(r)	(r + 0x08C)
 #define SSP_PID0(r)	(r + 0xFE0)
 #define SSP_PID1(r)	(r + 0xFE4)
 #define SSP_PID2(r)	(r + 0xFE8)
 #define SSP_PID3(r)	(r + 0xFEC)
 #define SSP_CID0(r)	(r + 0xFF0)
 #define SSP_CID1(r)	(r + 0xFF4)
 #define SSP_CID2(r)	(r + 0xFF8)
 #define SSP_CID3(r)	(r + 0xFFC)
 /*
  * SSP Control Register 0  - SSP_CR0
  */
 #define SSP_CR0_MASK_DSS	(0x0FUL << 0)
 #define SSP_CR0_MASK_FRF	(0x3UL << 4)
 #define SSP_CR0_MASK_SPO	(0x1UL << 6)
 #define SSP_CR0_MASK_SPH	(0x1UL << 7)
 #define SSP_CR0_MASK_SCR	(0xFFUL << 8)
 /*
  * The ST version of this block moves som bits
  * in SSP_CR0 and extends it to 32 bits
  */
 #define SSP_CR0_MASK_DSS_ST	(0x1FUL << 0)
 #define SSP_CR0_MASK_HALFDUP_ST	(0x1UL << 5)
 #define SSP_CR0_MASK_CSS_ST	(0x1FUL << 16)
 #define SSP_CR0_MASK_FRF_ST	(0x3UL << 21)
 /*
  * SSP Control Register 0  - SSP_CR1
  */
 #define SSP_CR1_MASK_LBM	(0x1UL << 0)
 #define SSP_CR1_MASK_SSE	(0x1UL << 1)
 #define SSP_CR1_MASK_MS		(0x1UL << 2)
 #define SSP_CR1_MASK_SOD	(0x1UL << 3)
 /*
  * The ST version of this block adds some bits
  * in SSP_CR1
  */
 #define SSP_CR1_MASK_RENDN_ST	(0x1UL << 4)
 #define SSP_CR1_MASK_TENDN_ST	(0x1UL << 5)
 #define SSP_CR1_MASK_MWAIT_ST	(0x1UL << 6)
 #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)
 #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)
 /* This one is only in the PL023 variant */
 #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
 /*
  * SSP Status Register - SSP_SR
  */
 #define SSP_SR_MASK_TFE		(0x1UL << 0) /* Transmit FIFO empty */
 #define SSP_SR_MASK_TNF		(0x1UL << 1) /* Transmit FIFO not full */
 #define SSP_SR_MASK_RNE		(0x1UL << 2) /* Receive FIFO not empty */
 #define SSP_SR_MASK_RFF		(0x1UL << 3) /* Receive FIFO full */
 #define SSP_SR_MASK_BSY		(0x1UL << 4) /* Busy Flag */
 /*
  * SSP Clock Prescale Register  - SSP_CPSR
  */
 #define SSP_CPSR_MASK_CPSDVSR	(0xFFUL << 0)
 /*
  * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
  */
 #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */
 #define SSP_IMSC_MASK_RTIM  (0x1UL << 1) /* Receive timeout Interrupt mask */
 #define SSP_IMSC_MASK_RXIM  (0x1UL << 2) /* Receive FIFO Interrupt mask */
 #define SSP_IMSC_MASK_TXIM  (0x1UL << 3) /* Transmit FIFO Interrupt mask */
 /*
  * SSP Raw Interrupt Status Register - SSP_RIS
  */
 /* Receive Overrun Raw Interrupt status */
 #define SSP_RIS_MASK_RORRIS		(0x1UL << 0)
 /* Receive Timeout Raw Interrupt status */
 #define SSP_RIS_MASK_RTRIS		(0x1UL << 1)
 /* Receive FIFO Raw Interrupt status */
 #define SSP_RIS_MASK_RXRIS		(0x1UL << 2)
 /* Transmit FIFO Raw Interrupt status */
 #define SSP_RIS_MASK_TXRIS		(0x1UL << 3)
 /*
  * SSP Masked Interrupt Status Register - SSP_MIS
  */
 /* Receive Overrun Masked Interrupt status */
 #define SSP_MIS_MASK_RORMIS		(0x1UL << 0)
 /* Receive Timeout Masked Interrupt status */
 #define SSP_MIS_MASK_RTMIS		(0x1UL << 1)
 /* Receive FIFO Masked Interrupt status */
 #define SSP_MIS_MASK_RXMIS		(0x1UL << 2)
 /* Transmit FIFO Masked Interrupt status */
 #define SSP_MIS_MASK_TXMIS		(0x1UL << 3)
 /*
  * SSP Interrupt Clear Register - SSP_ICR
  */
 /* Receive Overrun Raw Clear Interrupt bit */
 #define SSP_ICR_MASK_RORIC		(0x1UL << 0)
 /* Receive Timeout Clear Interrupt bit */
 #define SSP_ICR_MASK_RTIC		(0x1UL << 1)
 /*
  * SSP DMA Control Register - SSP_DMACR
  */
 /* Receive DMA Enable bit */
 #define SSP_DMACR_MASK_RXDMAE		(0x1UL << 0)
 /* Transmit DMA Enable bit */
 #define SSP_DMACR_MASK_TXDMAE		(0x1UL << 1)
 /*
  * SSP Integration Test control Register - SSP_ITCR
  */
 #define SSP_ITCR_MASK_ITEN		(0x1UL << 0)
 #define SSP_ITCR_MASK_TESTFIFO		(0x1UL << 1)
 /*
  * SSP Integration Test Input Register - SSP_ITIP
  */
 #define ITIP_MASK_SSPRXD		 (0x1UL << 0)
 #define ITIP_MASK_SSPFSSIN		 (0x1UL << 1)
 #define ITIP_MASK_SSPCLKIN		 (0x1UL << 2)
 #define ITIP_MASK_RXDMAC		 (0x1UL << 3)
 #define ITIP_MASK_TXDMAC		 (0x1UL << 4)
 #define ITIP_MASK_SSPTXDIN		 (0x1UL << 5)
 /*
  * SSP Integration Test output Register - SSP_ITOP
  */
 #define ITOP_MASK_SSPTXD		 (0x1UL << 0)
 #define ITOP_MASK_SSPFSSOUT		 (0x1UL << 1)
 #define ITOP_MASK_SSPCLKOUT		 (0x1UL << 2)
 #define ITOP_MASK_SSPOEn		 (0x1UL << 3)
 #define ITOP_MASK_SSPCTLOEn		 (0x1UL << 4)
 #define ITOP_MASK_RORINTR		 (0x1UL << 5)
 #define ITOP_MASK_RTINTR		 (0x1UL << 6)
 #define ITOP_MASK_RXINTR		 (0x1UL << 7)
 #define ITOP_MASK_TXINTR		 (0x1UL << 8)
 #define ITOP_MASK_INTR			 (0x1UL << 9)
 #define ITOP_MASK_RXDMABREQ		 (0x1UL << 10)
 #define ITOP_MASK_RXDMASREQ		 (0x1UL << 11)
 #define ITOP_MASK_TXDMABREQ		 (0x1UL << 12)
 #define ITOP_MASK_TXDMASREQ		 (0x1UL << 13)
 /*
  * SSP Test Data Register - SSP_TDR
  */
 #define TDR_MASK_TESTDATA		(0xFFFFFFFF)
 /*
  * Message State
  * we use the spi_message.state (void *) pointer to
  * hold a single state value, that's why all this
  * (void *) casting is done here.
  */
 #define STATE_START			((void *) 0)
 #define STATE_RUNNING			((void *) 1)
 #define STATE_DONE			((void *) 2)
 #define STATE_ERROR			((void *) -1)
 /*
  * SSP State - Whether Enabled or Disabled
  */
 #define SSP_DISABLED			(0)
 #define SSP_ENABLED			(1)
 /*
  * SSP DMA State - Whether DMA Enabled or Disabled
  */
 #define SSP_DMA_DISABLED		(0)
 #define SSP_DMA_ENABLED			(1)
 /*
  * SSP Clock Defaults
  */
 #define SSP_DEFAULT_CLKRATE 0x2
 #define SSP_DEFAULT_PRESCALE 0x40
 /*
  * SSP Clock Parameter ranges
  */
 #define CPSDVR_MIN 0x02
 #define CPSDVR_MAX 0xFE
 #define SCR_MIN 0x00
 #define SCR_MAX 0xFF
 /*
  * SSP Interrupt related Macros
  */
 #define DEFAULT_SSP_REG_IMSC  0x0UL
 #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC
 #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC)
 #define CLEAR_ALL_INTERRUPTS  0x3
 #define SPI_POLLING_TIMEOUT 1000
 /*
  * The type of reading going on on this chip
  */
 enum ssp_reading {
 	READING_NULL,
 	READING_U8,
 	READING_U16,
 	READING_U32
 };
 /**
  * The type of writing going on on this chip
  */
 enum ssp_writing {
 	WRITING_NULL,
 	WRITING_U8,
 	WRITING_U16,
 	WRITING_U32
 };
 /**
  * struct vendor_data - vendor-specific config parameters
  * for PL022 derivates
  * @fifodepth: depth of FIFOs (both)
  * @max_bpw: maximum number of bits per word
  * @unidir: supports unidirection transfers
  * @extended_cr: 32 bit wide control register 0 with extra
  * features and extra features in CR1 as found in the ST variants
  * @pl023: supports a subset of the ST extensions called "PL023"
  */
 struct vendor_data {
 	int fifodepth;
 	int max_bpw;
 	bool unidir;
 	bool extended_cr;
 	bool pl023;
 	bool loopback;
 };
 /**
  * struct pl022 - This is the private SSP driver data structure
  * @adev: AMBA device model hookup
  * @vendor: vendor data for the IP block
  * @phybase: the physical memory where the SSP device resides
  * @virtbase: the virtual memory where the SSP is mapped
  * @clk: outgoing clock "SPICLK" for the SPI bus
  * @master: SPI framework hookup
  * @master_info: controller-specific data from machine setup
  * @kworker: thread struct for message pump
  * @kworker_task: pointer to task for message pump kworker thread
  * @pump_messages: work struct for scheduling work to the message pump
  * @queue_lock: spinlock to syncronise access to message queue
  * @queue: message queue
  * @busy: message pump is busy
  * @running: message pump is running
  * @pump_transfers: Tasklet used in Interrupt Transfer mode
  * @cur_msg: Pointer to current spi_message being processed
  * @cur_transfer: Pointer to current spi_transfer
  * @cur_chip: pointer to current clients chip(assigned from controller_state)
  * @next_msg_cs_active: the next message in the queue has been examined
  *  and it was found that it uses the same chip select as the previous
  *  message, so we left it active after the previous transfer, and it's
  *  active already.
  * @tx: current position in TX buffer to be read
  * @tx_end: end position in TX buffer to be read
  * @rx: current position in RX buffer to be written
  * @rx_end: end position in RX buffer to be written
  * @read: the type of read currently going on
  * @write: the type of write currently going on
  * @exp_fifo_level: expected FIFO level
  * @dma_rx_channel: optional channel for RX DMA
  * @dma_tx_channel: optional channel for TX DMA
  * @sgt_rx: scattertable for the RX transfer
  * @sgt_tx: scattertable for the TX transfer
  * @dummypage: a dummy page used for driving data on the bus with DMA
  */
 struct pl022 {
 	struct amba_device		*adev;
 	struct vendor_data		*vendor;
 	resource_size_t			phybase;
 	void __iomem			*virtbase;
 	struct clk			*clk;
 	struct spi_master		*master;
 	struct pl022_ssp_controller	*master_info;
 	/* Message per-transfer pump */
 	struct tasklet_struct		pump_transfers;
 	struct spi_message		*cur_msg;
 	struct spi_transfer		*cur_transfer;
 	struct chip_data		*cur_chip;
 	bool				next_msg_cs_active;
 	void				*tx;
 	void				*tx_end;
 	void				*rx;
 	void				*rx_end;
 	enum ssp_reading		read;
 	enum ssp_writing		write;
 	u32				exp_fifo_level;
 	enum ssp_rx_level_trig		rx_lev_trig;
 	enum ssp_tx_level_trig		tx_lev_trig;
 	/* DMA settings */
 #ifdef CONFIG_DMA_ENGINE
 	struct dma_chan			*dma_rx_channel;
 	struct dma_chan			*dma_tx_channel;
 	struct sg_table			sgt_rx;
 	struct sg_table			sgt_tx;
 	char				*dummypage;
 	bool				dma_running;
 #endif
 };
 /**
  * struct chip_data - To maintain runtime state of SSP for each client chip
  * @cr0: Value of control register CR0 of SSP - on later ST variants this
  *       register is 32 bits wide rather than just 16
  * @cr1: Value of control register CR1 of SSP
  * @dmacr: Value of DMA control Register of SSP
  * @cpsr: Value of Clock prescale register
  * @n_bytes: how many bytes(power of 2) reqd for a given data width of client
  * @enable_dma: Whether to enable DMA or not
  * @read: function ptr to be used to read when doing xfer for this chip
  * @write: function ptr to be used to write when doing xfer for this chip
  * @cs_control: chip select callback provided by chip
  * @xfer_type: polling/interrupt/DMA
  *
  * Runtime state of the SSP controller, maintained per chip,
  * This would be set according to the current message that would be served
  */
 struct chip_data {
 	u32 cr0;
 	u16 cr1;
 	u16 dmacr;
 	u16 cpsr;
 	u8 n_bytes;
 	bool enable_dma;
 	enum ssp_reading read;
 	enum ssp_writing write;
 	void (*cs_control) (u32 command);
 	int xfer_type;
 };
 /**
  * null_cs_control - Dummy chip select function
  * @command: select/delect the chip
  *
  * If no chip select function is provided by client this is used as dummy
  * chip select
  */
 static void null_cs_control(u32 command)
 {
 	pr_debug("pl022: dummy chip select control, CS=0x%x\n", command);
 }
 /**
  * giveback - current spi_message is over, schedule next message and call
  * callback of this message. Assumes that caller already
  * set message->status; dma and pio irqs are blocked
  * @pl022: SSP driver private data structure
  */
 static void giveback(struct pl022 *pl022)
 {
 	struct spi_transfer *last_transfer;
 	pl022->next_msg_cs_active = false;
 	last_transfer = list_entry(pl022->cur_msg->transfers.prev,
 					struct spi_transfer,
 					transfer_list);
 	/* Delay if requested before any change in chip select */
 	if (last_transfer->delay_usecs)
 		/*
 		 * FIXME: This runs in interrupt context.
 		 * Is this really smart?
 		 */
 		udelay(last_transfer->delay_usecs);
 	if (!last_transfer->cs_change) {
 		struct spi_message *next_msg;
 		/*
 		 * cs_change was not set. We can keep the chip select
 		 * enabled if there is message in the queue and it is
 		 * for the same spi device.
 		 *
 		 * We cannot postpone this until pump_messages, because
 		 * after calling msg->complete (below) the driver that
 		 * sent the current message could be unloaded, which
 		 * could invalidate the cs_control() callback...
 		 */
 		/* get a pointer to the next message, if any */
 		next_msg = spi_get_next_queued_message(pl022->master);
 		/*
 		 * see if the next and current messages point
 		 * to the same spi device.
 		 */
 		if (next_msg && next_msg->spi != pl022->cur_msg->spi)
 			next_msg = NULL;
 		if (!next_msg || pl022->cur_msg->state == STATE_ERROR)
 			pl022->cur_chip->cs_control(SSP_CHIP_DESELECT);
 		else
 			pl022->next_msg_cs_active = true;
 	}
 	pl022->cur_msg = NULL;
 	pl022->cur_transfer = NULL;
 	pl022->cur_chip = NULL;
 	spi_finalize_current_message(pl022->master);
+	/* disable the SPI/SSP operation */
+	writew((readw(SSP_CR1(pl022->virtbase)) &
+		(~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
 }
 /**
  * flush - flush the FIFO to reach a clean state
  * @pl022: SSP driver private data structure
  */
 static int flush(struct pl022 *pl022)
 {
 	unsigned long limit = loops_per_jiffy << 1;
 	dev_dbg(&pl022->adev->dev, "flush\n");
 	do {
 		while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
 			readw(SSP_DR(pl022->virtbase));
 	} while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
 	pl022->exp_fifo_level = 0;
 	return limit;
 }
 /**
  * restore_state - Load configuration of current chip
  * @pl022: SSP driver private data structure
  */
 static void restore_state(struct pl022 *pl022)
 {
 	struct chip_data *chip = pl022->cur_chip;
 	if (pl022->vendor->extended_cr)
 		writel(chip->cr0, SSP_CR0(pl022->virtbase));
 	else
 		writew(chip->cr0, SSP_CR0(pl022->virtbase));
 	writew(chip->cr1, SSP_CR1(pl022->virtbase));
 	writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
 	writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
 	writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
 	writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
 }
 /*
  * Default SSP Register Values
  */
 #define DEFAULT_SSP_REG_CR0 ( \
 	GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0)	| \
 	GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \
 	GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
 	GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
 	GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
 )
 /* ST versions have slightly different bit layout */
 #define DEFAULT_SSP_REG_CR0_ST ( \
 	GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0)	| \
 	GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \
 	GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
 	GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
 	GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
 	GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16)	| \
 	GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \
 )
 /* The PL023 version is slightly different again */
 #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \
 	GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0)	| \
 	GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
 	GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
 	GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
 )
 #define DEFAULT_SSP_REG_CR1 ( \
 	GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
 	GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
 	GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
 	GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \
 )
 /* ST versions extend this register to use all 16 bits */
 #define DEFAULT_SSP_REG_CR1_ST ( \
 	DEFAULT_SSP_REG_CR1 | \
 	GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
 	GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
 	GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\
 	GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
 	GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \
 )
 /*
  * The PL023 variant has further differences: no loopback mode, no microwire
  * support, and a new clock feedback delay setting.
  */
 #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \
 	GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
 	GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
 	GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
 	GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
 	GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
 	GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
 	GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \
 	GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \
 )
 #define DEFAULT_SSP_REG_CPSR ( \
 	GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
 )
 #define DEFAULT_SSP_REG_DMACR (\
 	GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
 	GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
 )
 /**
  * load_ssp_default_config - Load default configuration for SSP
  * @pl022: SSP driver private data structure
  */
 static void load_ssp_default_config(struct pl022 *pl022)
 {
 	if (pl022->vendor->pl023) {
 		writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
 		writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
 	} else if (pl022->vendor->extended_cr) {
 		writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
 		writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
 	} else {
 		writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
 		writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
 	}
 	writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
 	writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
 	writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
 	writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
 }
 /**
  * This will write to TX and read from RX according to the parameters
  * set in pl022.
  */
 static void readwriter(struct pl022 *pl022)
 {
 	/*
 	 * The FIFO depth is different between primecell variants.
 	 * I believe filling in too much in the FIFO might cause
 	 * errons in 8bit wide transfers on ARM variants (just 8 words
 	 * FIFO, means only 8x8 = 64 bits in FIFO) at least.
 	 *
 	 * To prevent this issue, the TX FIFO is only filled to the
 	 * unused RX FIFO fill length, regardless of what the TX
 	 * FIFO status flag indicates.
 	 */
 	dev_dbg(&pl022->adev->dev,
 		"%s, rx: %p, rxend: %p, tx: %p, txend: %p\n",
 		__func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
 	/* Read as much as you can */
 	while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
 	       && (pl022->rx < pl022->rx_end)) {
 		switch (pl022->read) {
 		case READING_NULL:
 			readw(SSP_DR(pl022->virtbase));
 			break;
 		case READING_U8:
 			*(u8 *) (pl022->rx) =
 				readw(SSP_DR(pl022->virtbase)) & 0xFFU;
 			break;
 		case READING_U16:
 			*(u16 *) (pl022->rx) =
 				(u16) readw(SSP_DR(pl022->virtbase));
 			break;
 		case READING_U32:
 			*(u32 *) (pl022->rx) =
 				readl(SSP_DR(pl022->virtbase));
 			break;
 		}
 		pl022->rx += (pl022->cur_chip->n_bytes);
 		pl022->exp_fifo_level--;
 	}
 	/*
 	 * Write as much as possible up to the RX FIFO size
 	 */
 	while ((pl022->exp_fifo_level < pl022->vendor->fifodepth)
 	       && (pl022->tx < pl022->tx_end)) {
 		switch (pl022->write) {
 		case WRITING_NULL:
 			writew(0x0, SSP_DR(pl022->virtbase));
 			break;
 		case WRITING_U8:
 			writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
 			break;
 		case WRITING_U16:
 			writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
 			break;
 		case WRITING_U32:
 			writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
 			break;
 		}
 		pl022->tx += (pl022->cur_chip->n_bytes);
 		pl022->exp_fifo_level++;
 		/*
 		 * This inner reader takes care of things appearing in the RX
 		 * FIFO as we're transmitting. This will happen a lot since the
 		 * clock starts running when you put things into the TX FIFO,
 		 * and then things are continuously clocked into the RX FIFO.
 		 */
 		while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
 		       && (pl022->rx < pl022->rx_end)) {
 			switch (pl022->read) {
 			case READING_NULL:
 				readw(SSP_DR(pl022->virtbase));
 				break;
 			case READING_U8:
 				*(u8 *) (pl022->rx) =
 					readw(SSP_DR(pl022->virtbase)) & 0xFFU;
 				break;
 			case READING_U16:
 				*(u16 *) (pl022->rx) =
 					(u16) readw(SSP_DR(pl022->virtbase));
 				break;
 			case READING_U32:
 				*(u32 *) (pl022->rx) =
 					readl(SSP_DR(pl022->virtbase));
 				break;
 			}
 			pl022->rx += (pl022->cur_chip->n_bytes);
 			pl022->exp_fifo_level--;
 		}
 	}
 	/*
 	 * When we exit here the TX FIFO should be full and the RX FIFO
 	 * should be empty
 	 */
 }
 /**
  * next_transfer - Move to the Next transfer in the current spi message
  * @pl022: SSP driver private data structure
  *
  * This function moves though the linked list of spi transfers in the
  * current spi message and returns with the state of current spi
  * message i.e whether its last transfer is done(STATE_DONE) or
  * Next transfer is ready(STATE_RUNNING)
  */
 static void *next_transfer(struct pl022 *pl022)
 {
 	struct spi_message *msg = pl022->cur_msg;
 	struct spi_transfer *trans = pl022->cur_transfer;
 	/* Move to next transfer */
 	if (trans->transfer_list.next != &msg->transfers) {
 		pl022->cur_transfer =
 		    list_entry(trans->transfer_list.next,
 			       struct spi_transfer, transfer_list);
 		return STATE_RUNNING;
 	}
 	return STATE_DONE;
 }
 /*
  * This DMA functionality is only compiled in if we have
  * access to the generic DMA devices/DMA engine.
  */
 #ifdef CONFIG_DMA_ENGINE
 static void unmap_free_dma_scatter(struct pl022 *pl022)
 {
 	/* Unmap and free the SG tables */
 	dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl,
 		     pl022->sgt_tx.nents, DMA_TO_DEVICE);
 	dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl,
 		     pl022->sgt_rx.nents, DMA_FROM_DEVICE);
 	sg_free_table(&pl022->sgt_rx);
 	sg_free_table(&pl022->sgt_tx);
 }
 static void dma_callback(void *data)
 {
 	struct pl022 *pl022 = data;
 	struct spi_message *msg = pl022->cur_msg;
 	BUG_ON(!pl022->sgt_rx.sgl);
 #ifdef VERBOSE_DEBUG
 	/*
 	 * Optionally dump out buffers to inspect contents, this is
 	 * good if you want to convince yourself that the loopback
 	 * read/write contents are the same, when adopting to a new
 	 * DMA engine.
 	 */
 	{
 		struct scatterlist *sg;
 		unsigned int i;
 		dma_sync_sg_for_cpu(&pl022->adev->dev,
 				    pl022->sgt_rx.sgl,
 				    pl022->sgt_rx.nents,
 				    DMA_FROM_DEVICE);
 		for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) {
 			dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i);
 			print_hex_dump(KERN_ERR, "SPI RX: ",
 				       DUMP_PREFIX_OFFSET,
 				       16,
 				       1,
 				       sg_virt(sg),
 				       sg_dma_len(sg),
 				       1);
 		}
 		for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) {
 			dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i);
 			print_hex_dump(KERN_ERR, "SPI TX: ",
 				       DUMP_PREFIX_OFFSET,
 				       16,
 				       1,
 				       sg_virt(sg),
 				       sg_dma_len(sg),
 				       1);
 		}
 	}
 #endif
 	unmap_free_dma_scatter(pl022);
 	/* Update total bytes transferred */
 	msg->actual_length += pl022->cur_transfer->len;
 	if (pl022->cur_transfer->cs_change)
 		pl022->cur_chip->
 			cs_control(SSP_CHIP_DESELECT);
 	/* Move to next transfer */
 	msg->state = next_transfer(pl022);
 	tasklet_schedule(&pl022->pump_transfers);
 }
 static void setup_dma_scatter(struct pl022 *pl022,
 			      void *buffer,
 			      unsigned int length,
 			      struct sg_table *sgtab)
 {
 	struct scatterlist *sg;
 	int bytesleft = length;
 	void *bufp = buffer;
 	int mapbytes;
 	int i;
 	if (buffer) {
 		for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
 			/*
 			 * If there are less bytes left than what fits
 			 * in the current page (plus page alignment offset)
 			 * we just feed in this, else we stuff in as much
 			 * as we can.
 			 */
 			if (bytesleft < (PAGE_SIZE - offset_in_page(bufp)))
 				mapbytes = bytesleft;
 			else
 				mapbytes = PAGE_SIZE - offset_in_page(bufp);
 			sg_set_page(sg, virt_to_page(bufp),
 				    mapbytes, offset_in_page(bufp));
 			bufp += mapbytes;
 			bytesleft -= mapbytes;
 			dev_dbg(&pl022->adev->dev,
 				"set RX/TX target page @ %p, %d bytes, %d left\n",
 				bufp, mapbytes, bytesleft);
 		}
 	} else {
 		/* Map the dummy buffer on every page */
 		for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
 			if (bytesleft < PAGE_SIZE)
 				mapbytes = bytesleft;
 			else
 				mapbytes = PAGE_SIZE;
 			sg_set_page(sg, virt_to_page(pl022->dummypage),
 				    mapbytes, 0);
 			bytesleft -= mapbytes;
 			dev_dbg(&pl022->adev->dev,
 				"set RX/TX to dummy page %d bytes, %d left\n",
 				mapbytes, bytesleft);
 		}
 	}
 	BUG_ON(bytesleft);
 }
 /**
  * configure_dma - configures the channels for the next transfer
  * @pl022: SSP driver's private data structure
  */
 static int configure_dma(struct pl022 *pl022)
 {
 	struct dma_slave_config rx_conf = {
 		.src_addr = SSP_DR(pl022->phybase),
 		.direction = DMA_DEV_TO_MEM,
 		.device_fc = false,
 	};
 	struct dma_slave_config tx_conf = {
 		.dst_addr = SSP_DR(pl022->phybase),
 		.direction = DMA_MEM_TO_DEV,
 		.device_fc = false,
 	};
 	unsigned int pages;
 	int ret;
 	int rx_sglen, tx_sglen;
 	struct dma_chan *rxchan = pl022->dma_rx_channel;
 	struct dma_chan *txchan = pl022->dma_tx_channel;
 	struct dma_async_tx_descriptor *rxdesc;
 	struct dma_async_tx_descriptor *txdesc;
 	/* Check that the channels are available */
 	if (!rxchan || !txchan)
 		return -ENODEV;
 	/*
 	 * If supplied, the DMA burstsize should equal the FIFO trigger level.
 	 * Notice that the DMA engine uses one-to-one mapping. Since we can
 	 * not trigger on 2 elements this needs explicit mapping rather than
 	 * calculation.
 	 */
 	switch (pl022->rx_lev_trig) {
 	case SSP_RX_1_OR_MORE_ELEM:
 		rx_conf.src_maxburst = 1;
 		break;
 	case SSP_RX_4_OR_MORE_ELEM:
 		rx_conf.src_maxburst = 4;
 		break;
 	case SSP_RX_8_OR_MORE_ELEM:
 		rx_conf.src_maxburst = 8;
 		break;
 	case SSP_RX_16_OR_MORE_ELEM:
 		rx_conf.src_maxburst = 16;
 		break;
 	case SSP_RX_32_OR_MORE_ELEM:
 		rx_conf.src_maxburst = 32;
 		break;
 	default:
 		rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1;
 		break;
 	}
 	switch (pl022->tx_lev_trig) {
 	case SSP_TX_1_OR_MORE_EMPTY_LOC:
 		tx_conf.dst_maxburst = 1;
 		break;
 	case SSP_TX_4_OR_MORE_EMPTY_LOC:
 		tx_conf.dst_maxburst = 4;
 		break;
 	case SSP_TX_8_OR_MORE_EMPTY_LOC:
 		tx_conf.dst_maxburst = 8;
 		break;
 	case SSP_TX_16_OR_MORE_EMPTY_LOC:
 		tx_conf.dst_maxburst = 16;
 		break;
 	case SSP_TX_32_OR_MORE_EMPTY_LOC:
 		tx_conf.dst_maxburst = 32;
 		break;
 	default:
 		tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1;
 		break;
 	}
 	switch (pl022->read) {
 	case READING_NULL:
 		/* Use the same as for writing */
 		rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
 		break;
 	case READING_U8:
 		rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 		break;
 	case READING_U16:
 		rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 		break;
 	case READING_U32:
 		rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 		break;
 	}
 	switch (pl022->write) {
 	case WRITING_NULL:
 		/* Use the same as for reading */
 		tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
 		break;
 	case WRITING_U8:
 		tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 		break;
 	case WRITING_U16:
 		tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 		break;
 	case WRITING_U32:
 		tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 		break;
 	}
 	/* SPI pecularity: we need to read and write the same width */
 	if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
 		rx_conf.src_addr_width = tx_conf.dst_addr_width;
 	if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
 		tx_conf.dst_addr_width = rx_conf.src_addr_width;
 	BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width);
 	dmaengine_slave_config(rxchan, &rx_conf);
 	dmaengine_slave_config(txchan, &tx_conf);
 	/* Create sglists for the transfers */
 	pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE);
 	dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages);
 	ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC);
 	if (ret)
 		goto err_alloc_rx_sg;
 	ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC);
 	if (ret)
 		goto err_alloc_tx_sg;
 	/* Fill in the scatterlists for the RX+TX buffers */
 	setup_dma_scatter(pl022, pl022->rx,
 			  pl022->cur_transfer->len, &pl022->sgt_rx);
 	setup_dma_scatter(pl022, pl022->tx,
 			  pl022->cur_transfer->len, &pl022->sgt_tx);
 	/* Map DMA buffers */
 	rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
 			   pl022->sgt_rx.nents, DMA_FROM_DEVICE);
 	if (!rx_sglen)
 		goto err_rx_sgmap;
 	tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl,
 			   pl022->sgt_tx.nents, DMA_TO_DEVICE);
 	if (!tx_sglen)
 		goto err_tx_sgmap;
 	/* Send both scatterlists */
 	rxdesc = dmaengine_prep_slave_sg(rxchan,
 				      pl022->sgt_rx.sgl,
 				      rx_sglen,
 				      DMA_DEV_TO_MEM,
 				      DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 	if (!rxdesc)
 		goto err_rxdesc;
 	txdesc = dmaengine_prep_slave_sg(txchan,
 				      pl022->sgt_tx.sgl,
 				      tx_sglen,
 				      DMA_MEM_TO_DEV,
 				      DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 	if (!txdesc)
 		goto err_txdesc;
 	/* Put the callback on the RX transfer only, that should finish last */
 	rxdesc->callback = dma_callback;
 	rxdesc->callback_param = pl022;
 	/* Submit and fire RX and TX with TX last so we're ready to read! */
 	dmaengine_submit(rxdesc);
 	dmaengine_submit(txdesc);
 	dma_async_issue_pending(rxchan);
 	dma_async_issue_pending(txchan);
 	pl022->dma_running = true;
 	return 0;
 err_txdesc:
 	dmaengine_terminate_all(txchan);
 err_rxdesc:
 	dmaengine_terminate_all(rxchan);
 	dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl,
 		     pl022->sgt_tx.nents, DMA_TO_DEVICE);
 err_tx_sgmap:
 	dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
 		     pl022->sgt_tx.nents, DMA_FROM_DEVICE);
 err_rx_sgmap:
 	sg_free_table(&pl022->sgt_tx);
 err_alloc_tx_sg:
 	sg_free_table(&pl022->sgt_rx);
 err_alloc_rx_sg:
 	return -ENOMEM;
 }
 static int __devinit pl022_dma_probe(struct pl022 *pl022)
 {
 	dma_cap_mask_t mask;
 	/* Try to acquire a generic DMA engine slave channel */
 	dma_cap_zero(mask);
 	dma_cap_set(DMA_SLAVE, mask);
 	/*
 	 * We need both RX and TX channels to do DMA, else do none
 	 * of them.
 	 */
 	pl022->dma_rx_channel = dma_request_channel(mask,
 					    pl022->master_info->dma_filter,
 					    pl022->master_info->dma_rx_param);
 	if (!pl022->dma_rx_channel) {
 		dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n");
 		goto err_no_rxchan;
 	}
 	pl022->dma_tx_channel = dma_request_channel(mask,
 					    pl022->master_info->dma_filter,
 					    pl022->master_info->dma_tx_param);
 	if (!pl022->dma_tx_channel) {
 		dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n");
 		goto err_no_txchan;
 	}
 	pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
 	if (!pl022->dummypage) {
 		dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n");
 		goto err_no_dummypage;
 	}
 	dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
 		 dma_chan_name(pl022->dma_rx_channel),
 		 dma_chan_name(pl022->dma_tx_channel));
 	return 0;
 err_no_dummypage:
 	dma_release_channel(pl022->dma_tx_channel);
 err_no_txchan:
 	dma_release_channel(pl022->dma_rx_channel);
 	pl022->dma_rx_channel = NULL;
 err_no_rxchan:
 	dev_err(&pl022->adev->dev,
 			"Failed to work in dma mode, work without dma!\n");
 	return -ENODEV;
 }
 static void terminate_dma(struct pl022 *pl022)
 {
 	struct dma_chan *rxchan = pl022->dma_rx_channel;
 	struct dma_chan *txchan = pl022->dma_tx_channel;
 	dmaengine_terminate_all(rxchan);
 	dmaengine_terminate_all(txchan);
 	unmap_free_dma_scatter(pl022);
 	pl022->dma_running = false;
 }
 static void pl022_dma_remove(struct pl022 *pl022)
 {
 	if (pl022->dma_running)
 		terminate_dma(pl022);
 	if (pl022->dma_tx_channel)
 		dma_release_channel(pl022->dma_tx_channel);
 	if (pl022->dma_rx_channel)
 		dma_release_channel(pl022->dma_rx_channel);
 	kfree(pl022->dummypage);
 }
 #else
 static inline int configure_dma(struct pl022 *pl022)
 {
 	return -ENODEV;
 }
 static inline int pl022_dma_probe(struct pl022 *pl022)
 {
 	return 0;
 }
 static inline void pl022_dma_remove(struct pl022 *pl022)
 {
 }
 #endif
 /**
  * pl022_interrupt_handler - Interrupt handler for SSP controller
  *
  * This function handles interrupts generated for an interrupt based transfer.
  * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the
  * current message's state as STATE_ERROR and schedule the tasklet
  * pump_transfers which will do the postprocessing of the current message by
  * calling giveback(). Otherwise it reads data from RX FIFO till there is no
  * more data, and writes data in TX FIFO till it is not full. If we complete
  * the transfer we move to the next transfer and schedule the tasklet.
  */
 static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
 {
 	struct pl022 *pl022 = dev_id;
 	struct spi_message *msg = pl022->cur_msg;
 	u16 irq_status = 0;
 	u16 flag = 0;
 	if (unlikely(!msg)) {
 		dev_err(&pl022->adev->dev,
 			"bad message state in interrupt handler");
 		/* Never fail */
 		return IRQ_HANDLED;
 	}
 	/* Read the Interrupt Status Register */
 	irq_status = readw(SSP_MIS(pl022->virtbase));
 	if (unlikely(!irq_status))
 		return IRQ_NONE;
 	/*
 	 * This handles the FIFO interrupts, the timeout
 	 * interrupts are flatly ignored, they cannot be
 	 * trusted.
 	 */
 	if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) {
 		/*
 		 * Overrun interrupt - bail out since our Data has been
 		 * corrupted
 		 */
 		dev_err(&pl022->adev->dev, "FIFO overrun\n");
 		if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
 			dev_err(&pl022->adev->dev,
 				"RXFIFO is full\n");
 		if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF)
 			dev_err(&pl022->adev->dev,
 				"TXFIFO is full\n");
 		/*
 		 * Disable and clear interrupts, disable SSP,
 		 * mark message with bad status so it can be
 		 * retried.
 		 */
 		writew(DISABLE_ALL_INTERRUPTS,
 		       SSP_IMSC(pl022->virtbase));
 		writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
 		writew((readw(SSP_CR1(pl022->virtbase)) &
 			(~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
 		msg->state = STATE_ERROR;
 		/* Schedule message queue handler */
 		tasklet_schedule(&pl022->pump_transfers);
 		return IRQ_HANDLED;
 	}
 	readwriter(pl022);
 	if ((pl022->tx == pl022->tx_end) && (flag == 0)) {
 		flag = 1;
 		/* Disable Transmit interrupt, enable receive interrupt */
 		writew((readw(SSP_IMSC(pl022->virtbase)) &
 		       ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM,
 		       SSP_IMSC(pl022->virtbase));
 	}
 	/*
 	 * Since all transactions must write as much as shall be read,
 	 * we can conclude the entire transaction once RX is complete.
 	 * At this point, all TX will always be finished.
 	 */
 	if (pl022->rx >= pl022->rx_end) {
 		writew(DISABLE_ALL_INTERRUPTS,
 		       SSP_IMSC(pl022->virtbase));
 		writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
 		if (unlikely(pl022->rx > pl022->rx_end)) {
 			dev_warn(&pl022->adev->dev, "read %u surplus "
 				 "bytes (did you request an odd "
 				 "number of bytes on a 16bit bus?)\n",
 				 (u32) (pl022->rx - pl022->rx_end));
 		}
 		/* Update total bytes transferred */
 		msg->actual_length += pl022->cur_transfer->len;
 		if (pl022->cur_transfer->cs_change)
 			pl022->cur_chip->
 				cs_control(SSP_CHIP_DESELECT);
 		/* Move to next transfer */
 		msg->state = next_transfer(pl022);
 		tasklet_schedule(&pl022->pump_transfers);
 		return IRQ_HANDLED;
 	}
 	return IRQ_HANDLED;
 }
 /**
  * This sets up the pointers to memory for the next message to
  * send out on the SPI bus.
  */
 static int set_up_next_transfer(struct pl022 *pl022,
 				struct spi_transfer *transfer)
 {
 	int residue;
 	/* Sanity check the message for this bus width */
 	residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes;
 	if (unlikely(residue != 0)) {
 		dev_err(&pl022->adev->dev,
 			"message of %u bytes to transmit but the current "
 			"chip bus has a data width of %u bytes!\n",
 			pl022->cur_transfer->len,
 			pl022->cur_chip->n_bytes);
 		dev_err(&pl022->adev->dev, "skipping this message\n");
 		return -EIO;
 	}
 	pl022->tx = (void *)transfer->tx_buf;
 	pl022->tx_end = pl022->tx + pl022->cur_transfer->len;
 	pl022->rx = (void *)transfer->rx_buf;
 	pl022->rx_end = pl022->rx + pl022->cur_transfer->len;
 	pl022->write =
 	    pl022->tx ? pl022->cur_chip->write : WRITING_NULL;
 	pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL;
 	return 0;
 }
 /**
  * pump_transfers - Tasklet function which schedules next transfer
  * when running in interrupt or DMA transfer mode.
  * @data: SSP driver private data structure
  *
  */
 static void pump_transfers(unsigned long data)
 {
 	struct pl022 *pl022 = (struct pl022 *) data;
 	struct spi_message *message = NULL;
 	struct spi_transfer *transfer = NULL;
 	struct spi_transfer *previous = NULL;
 	/* Get current state information */
 	message = pl022->cur_msg;
 	transfer = pl022->cur_transfer;
 	/* Handle for abort */
 	if (message->state == STATE_ERROR) {
 		message->status = -EIO;
 		giveback(pl022);
 		return;
 	}
 	/* Handle end of message */
 	if (message->state == STATE_DONE) {
 		message->status = 0;
 		giveback(pl022);
 		return;
 	}
 	/* Delay if requested at end of transfer before CS change */
 	if (message->state == STATE_RUNNING) {
 		previous = list_entry(transfer->transfer_list.prev,
 					struct spi_transfer,
 					transfer_list);
 		if (previous->delay_usecs)
 			/*
 			 * FIXME: This runs in interrupt context.
 			 * Is this really smart?
 			 */
 			udelay(previous->delay_usecs);
 		/* Reselect chip select only if cs_change was requested */
 		if (previous->cs_change)
 			pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
 	} else {
 		/* STATE_START */
 		message->state = STATE_RUNNING;
 	}
 	if (set_up_next_transfer(pl022, transfer)) {
 		message->state = STATE_ERROR;
 		message->status = -EIO;
 		giveback(pl022);
 		return;
 	}
 	/* Flush the FIFOs and let's go! */
 	flush(pl022);
 	if (pl022->cur_chip->enable_dma) {
 		if (configure_dma(pl022)) {
 			dev_dbg(&pl022->adev->dev,
 				"configuration of DMA failed, fall back to interrupt mode\n");
 			goto err_config_dma;
 		}
 		return;
 	}
 err_config_dma:
 	/* enable all interrupts except RX */
 	writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase));
 }
 static void do_interrupt_dma_transfer(struct pl022 *pl022)
 {
 	/*
 	 * Default is to enable all interrupts except RX -
 	 * this will be enabled once TX is complete
 	 */
 	u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM;
 	/* Enable target chip, if not already active */
 	if (!pl022->next_msg_cs_active)
 		pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
 	if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
 		/* Error path */
 		pl022->cur_msg->state = STATE_ERROR;
 		pl022->cur_msg->status = -EIO;
 		giveback(pl022);
 		return;
 	}
 	/* If we're using DMA, set up DMA here */
 	if (pl022->cur_chip->enable_dma) {
 		/* Configure DMA transfer */
 		if (configure_dma(pl022)) {
 			dev_dbg(&pl022->adev->dev,
 				"configuration of DMA failed, fall back to interrupt mode\n");
 			goto err_config_dma;
 		}
 		/* Disable interrupts in DMA mode, IRQ from DMA controller */
 		irqflags = DISABLE_ALL_INTERRUPTS;
 	}
 err_config_dma:
 	/* Enable SSP, turn on interrupts */
 	writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
 	       SSP_CR1(pl022->virtbase));
 	writew(irqflags, SSP_IMSC(pl022->virtbase));
 }
 static void do_polling_transfer(struct pl022 *pl022)
 {
 	struct spi_message *message = NULL;
 	struct spi_transfer *transfer = NULL;
 	struct spi_transfer *previous = NULL;
 	struct chip_data *chip;
 	unsigned long time, timeout;
 	chip = pl022->cur_chip;
 	message = pl022->cur_msg;
 	while (message->state != STATE_DONE) {
 		/* Handle for abort */
 		if (message->state == STATE_ERROR)
 			break;
 		transfer = pl022->cur_transfer;
 		/* Delay if requested at end of transfer */
 		if (message->state == STATE_RUNNING) {
 			previous =
 			    list_entry(transfer->transfer_list.prev,
 				       struct spi_transfer, transfer_list);
 			if (previous->delay_usecs)
 				udelay(previous->delay_usecs);
 			if (previous->cs_change)
 				pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
 		} else {
 			/* STATE_START */
 			message->state = STATE_RUNNING;
 			if (!pl022->next_msg_cs_active)
 				pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
 		}
 		/* Configuration Changing Per Transfer */
 		if (set_up_next_transfer(pl022, transfer)) {
 			/* Error path */
 			message->state = STATE_ERROR;
 			break;
 		}
 		/* Flush FIFOs and enable SSP */
 		flush(pl022);
 		writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
 		       SSP_CR1(pl022->virtbase));
 		dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
 		timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT);
 		while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) {
 			time = jiffies;
 			readwriter(pl022);
 			if (time_after(time, timeout)) {
 				dev_warn(&pl022->adev->dev,
 				"%s: timeout!\n", __func__);
 				message->state = STATE_ERROR;
 				goto out;
 			}
 			cpu_relax();
 		}
 		/* Update total byte transferred */
 		message->actual_length += pl022->cur_transfer->len;
 		if (pl022->cur_transfer->cs_change)
 			pl022->cur_chip->cs_control(SSP_CHIP_DESELECT);
 		/* Move to next transfer */
 		message->state = next_transfer(pl022);
 	}
 out:
 	/* Handle end of message */
 	if (message->state == STATE_DONE)
 		message->status = 0;
 	else
 		message->status = -EIO;
 	giveback(pl022);
 	return;
 }
 static int pl022_transfer_one_message(struct spi_master *master,
 				      struct spi_message *msg)
 {
 	struct pl022 *pl022 = spi_master_get_devdata(master);
 	/* Initial message state */
 	pl022->cur_msg = msg;
 	msg->state = STATE_START;
 	pl022->cur_transfer = list_entry(msg->transfers.next,
 					 struct spi_transfer, transfer_list);
 	/* Setup the SPI using the per chip configuration */
 	pl022->cur_chip = spi_get_ctldata(msg->spi);
 	restore_state(pl022);
 	flush(pl022);
 	if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
 		do_polling_transfer(pl022);
 	else
 		do_interrupt_dma_transfer(pl022);
 	return 0;
 }
 static int pl022_prepare_transfer_hardware(struct spi_master *master)
 {
 	struct pl022 *pl022 = spi_master_get_devdata(master);
 	/*
 	 * Just make sure we have all we need to run the transfer by syncing
 	 * with the runtime PM framework.
 	 */
 	pm_runtime_get_sync(&pl022->adev->dev);
 	return 0;
 }
 static int pl022_unprepare_transfer_hardware(struct spi_master *master)
 {
 	struct pl022 *pl022 = spi_master_get_devdata(master);
 	/* nothing more to do - disable spi/ssp and power off */
 	writew((readw(SSP_CR1(pl022->virtbase)) &
 		(~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
 	if (pl022->master_info->autosuspend_delay > 0) {
 		pm_runtime_mark_last_busy(&pl022->adev->dev);
 		pm_runtime_put_autosuspend(&pl022->adev->dev);
 	} else {
 		pm_runtime_put(&pl022->adev->dev);
 	}
 	return 0;
 }
 static int verify_controller_parameters(struct pl022 *pl022,
 				struct pl022_config_chip const *chip_info)
 {
 	if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI)
 	    || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) {
 		dev_err(&pl022->adev->dev,
 			"interface is configured incorrectly\n");
 		return -EINVAL;
 	}
 	if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) &&
 	    (!pl022->vendor->unidir)) {
 		dev_err(&pl022->adev->dev,
 			"unidirectional mode not supported in this "
 			"hardware version\n");
 		return -EINVAL;
 	}
 	if ((chip_info->hierarchy != SSP_MASTER)
 	    && (chip_info->hierarchy != SSP_SLAVE)) {
 		dev_err(&pl022->adev->dev,
 			"hierarchy is configured incorrectly\n");
 		return -EINVAL;
 	}
 	if ((chip_info->com_mode != INTERRUPT_TRANSFER)
 	    && (chip_info->com_mode != DMA_TRANSFER)
 	    && (chip_info->com_mode != POLLING_TRANSFER)) {
 		dev_err(&pl022->adev->dev,
 			"Communication mode is configured incorrectly\n");
 		return -EINVAL;
 	}
 	switch (chip_info->rx_lev_trig) {
 	case SSP_RX_1_OR_MORE_ELEM:
 	case SSP_RX_4_OR_MORE_ELEM:
 	case SSP_RX_8_OR_MORE_ELEM:
 		/* These are always OK, all variants can handle this */
 		break;
 	case SSP_RX_16_OR_MORE_ELEM:
 		if (pl022->vendor->fifodepth < 16) {
 			dev_err(&pl022->adev->dev,
 			"RX FIFO Trigger Level is configured incorrectly\n");
 			return -EINVAL;
 		}
 		break;
 	case SSP_RX_32_OR_MORE_ELEM:
 		if (pl022->vendor->fifodepth < 32) {
 			dev_err(&pl022->adev->dev,
 			"RX FIFO Trigger Level is configured incorrectly\n");
 			return -EINVAL;
 		}
 		break;
 	default:
 		dev_err(&pl022->adev->dev,
 			"RX FIFO Trigger Level is configured incorrectly\n");
 		return -EINVAL;
 		break;
 	}
 	switch (chip_info->tx_lev_trig) {
 	case SSP_TX_1_OR_MORE_EMPTY_LOC:
 	case SSP_TX_4_OR_MORE_EMPTY_LOC:
 	case SSP_TX_8_OR_MORE_EMPTY_LOC:
 		/* These are always OK, all variants can handle this */
 		break;
 	case SSP_TX_16_OR_MORE_EMPTY_LOC:
 		if (pl022->vendor->fifodepth < 16) {
 			dev_err(&pl022->adev->dev,
 			"TX FIFO Trigger Level is configured incorrectly\n");
 			return -EINVAL;
 		}
 		break;
 	case SSP_TX_32_OR_MORE_EMPTY_LOC:
 		if (pl022->vendor->fifodepth < 32) {
 			dev_err(&pl022->adev->dev,
 			"TX FIFO Trigger Level is configured incorrectly\n");
 			return -EINVAL;
 		}
 		break;
 	default:
 		dev_err(&pl022->adev->dev,
 			"TX FIFO Trigger Level is configured incorrectly\n");
 		return -EINVAL;
 		break;
 	}
 	if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {
 		if ((chip_info->ctrl_len < SSP_BITS_4)
 		    || (chip_info->ctrl_len > SSP_BITS_32)) {
 			dev_err(&pl022->adev->dev,
 				"CTRL LEN is configured incorrectly\n");
 			return -EINVAL;
 		}
 		if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO)
 		    && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) {
 			dev_err(&pl022->adev->dev,
 				"Wait State is configured incorrectly\n");
 			return -EINVAL;
 		}
 		/* Half duplex is only available in the ST Micro version */
 		if (pl022->vendor->extended_cr) {
 			if ((chip_info->duplex !=
 			     SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
 			    && (chip_info->duplex !=
 				SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) {
 				dev_err(&pl022->adev->dev,
 					"Microwire duplex mode is configured incorrectly\n");
 				return -EINVAL;
 			}
 		} else {
 			if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
 				dev_err(&pl022->adev->dev,
 					"Microwire half duplex mode requested,"
 					" but this is only available in the"
 					" ST version of PL022\n");
 			return -EINVAL;
 		}
 	}
 	return 0;
 }
 static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
 {
 	return rate / (cpsdvsr * (1 + scr));
 }
 static int calculate_effective_freq(struct pl022 *pl022, int freq, struct
 				    ssp_clock_params * clk_freq)
 {
 	/* Lets calculate the frequency parameters */
 	u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN;
 	u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0,
 		best_scr = 0, tmp, found = 0;
 	rate = clk_get_rate(pl022->clk);
 	/* cpsdvscr = 2 & scr 0 */
 	max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN);
 	/* cpsdvsr = 254 & scr = 255 */
 	min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX);
 	if (freq > max_tclk)
 		dev_warn(&pl022->adev->dev,
 			"Max speed that can be programmed is %d Hz, you requested %d\n",
 			max_tclk, freq);
 	if (freq < min_tclk) {
 		dev_err(&pl022->adev->dev,
 			"Requested frequency: %d Hz is less than minimum possible %d Hz\n",
 			freq, min_tclk);
 		return -EINVAL;
 	}
 	/*
 	 * best_freq will give closest possible available rate (<= requested
 	 * freq) for all values of scr & cpsdvsr.
 	 */
 	while ((cpsdvsr <= CPSDVR_MAX) && !found) {
 		while (scr <= SCR_MAX) {
 			tmp = spi_rate(rate, cpsdvsr, scr);
 			if (tmp > freq) {
 				/* we need lower freq */
 				scr++;
 				continue;
 			}
 			/*
 			 * If found exact value, mark found and break.
 			 * If found more closer value, update and break.
 			 */
 			if (tmp > best_freq) {
 				best_freq = tmp;
 				best_cpsdvsr = cpsdvsr;
 				best_scr = scr;
 				if (tmp == freq)
 					found = 1;
 			}
 			/*
 			 * increased scr will give lower rates, which are not
 			 * required
 			 */
 			break;
 		}
 		cpsdvsr += 2;
 		scr = SCR_MIN;
 	}
 	WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n",
 			freq);
 	clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF);
 	clk_freq->scr = (u8) (best_scr & 0xFF);
 	dev_dbg(&pl022->adev->dev,
 		"SSP Target Frequency is: %u, Effective Frequency is %u\n",
 		freq, best_freq);
 	dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n",
 		clk_freq->cpsdvsr, clk_freq->scr);
 	return 0;
 }
 /*
  * A piece of default chip info unless the platform
  * supplies it.
  */
 static const struct pl022_config_chip pl022_default_chip_info = {
 	.com_mode = POLLING_TRANSFER,
 	.iface = SSP_INTERFACE_MOTOROLA_SPI,
 	.hierarchy = SSP_SLAVE,
 	.slave_tx_disable = DO_NOT_DRIVE_TX,
 	.rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
 	.tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
 	.ctrl_len = SSP_BITS_8,
 	.wait_state = SSP_MWIRE_WAIT_ZERO,
 	.duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
 	.cs_control = null_cs_control,
 };
 /**
  * pl022_setup - setup function registered to SPI master framework
  * @spi: spi device which is requesting setup
  *
  * This function is registered to the SPI framework for this SPI master
  * controller. If it is the first time when setup is called by this device,
  * this function will initialize the runtime state for this chip and save
  * the same in the device structure. Else it will update the runtime info
  * with the updated chip info. Nothing is really being written to the
  * controller hardware here, that is not done until the actual transfer
  * commence.
  */
 static int pl022_setup(struct spi_device *spi)
 {
 	struct pl022_config_chip const *chip_info;
 	struct chip_data *chip;
 	struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0};
 	int status = 0;
 	struct pl022 *pl022 = spi_master_get_devdata(spi->master);
 	unsigned int bits = spi->bits_per_word;
 	u32 tmp;
 	if (!spi->max_speed_hz)
 		return -EINVAL;
 	/* Get controller_state if one is supplied */
 	chip = spi_get_ctldata(spi);
 	if (chip == NULL) {
 		chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 		if (!chip) {
 			dev_err(&spi->dev,
 				"cannot allocate controller state\n");
 			return -ENOMEM;
 		}
 		dev_dbg(&spi->dev,
 			"allocated memory for controller's runtime state\n");
 	}
 	/* Get controller data if one is supplied */
 	chip_info = spi->controller_data;
 	if (chip_info == NULL) {
 		chip_info = &pl022_default_chip_info;
 		/* spi_board_info.controller_data not is supplied */
 		dev_dbg(&spi->dev,
 			"using default controller_data settings\n");
 	} else
 		dev_dbg(&spi->dev,
 			"using user supplied controller_data settings\n");
 	/*
 	 * We can override with custom divisors, else we use the board
 	 * frequency setting
 	 */
 	if ((0 == chip_info->clk_freq.cpsdvsr)
 	    && (0 == chip_info->clk_freq.scr)) {
 		status = calculate_effective_freq(pl022,
 						  spi->max_speed_hz,
 						  &clk_freq);
 		if (status < 0)
 			goto err_config_params;
 	} else {
 		memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq));
 		if ((clk_freq.cpsdvsr % 2) != 0)
 			clk_freq.cpsdvsr =
 				clk_freq.cpsdvsr - 1;
 	}
 	if ((clk_freq.cpsdvsr < CPSDVR_MIN)
 	    || (clk_freq.cpsdvsr > CPSDVR_MAX)) {
 		status = -EINVAL;
 		dev_err(&spi->dev,
 			"cpsdvsr is configured incorrectly\n");
 		goto err_config_params;
 	}
 	status = verify_controller_parameters(pl022, chip_info);
 	if (status) {
 		dev_err(&spi->dev, "controller data is incorrect");
 		goto err_config_params;
 	}
 	pl022->rx_lev_trig = chip_info->rx_lev_trig;
 	pl022->tx_lev_trig = chip_info->tx_lev_trig;
 	/* Now set controller state based on controller data */
 	chip->xfer_type = chip_info->com_mode;
 	if (!chip_info->cs_control) {
 		chip->cs_control = null_cs_control;
 		dev_warn(&spi->dev,
 			 "chip select function is NULL for this chip\n");
 	} else
 		chip->cs_control = chip_info->cs_control;
 	/* Check bits per word with vendor specific range */
 	if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) {
 		status = -ENOTSUPP;
 		dev_err(&spi->dev, "illegal data size for this controller!\n");
 		dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n",
 				pl022->vendor->max_bpw);
 		goto err_config_params;
 	} else if (bits <= 8) {
 		dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n");
 		chip->n_bytes = 1;
 		chip->read = READING_U8;
 		chip->write = WRITING_U8;
 	} else if (bits <= 16) {
 		dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n");
 		chip->n_bytes = 2;
 		chip->read = READING_U16;
 		chip->write = WRITING_U16;
 	} else {
 		dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n");
 		chip->n_bytes = 4;
 		chip->read = READING_U32;
 		chip->write = WRITING_U32;
 	}
 	/* Now Initialize all register settings required for this chip */
 	chip->cr0 = 0;
 	chip->cr1 = 0;
 	chip->dmacr = 0;
 	chip->cpsr = 0;
 	if ((chip_info->com_mode == DMA_TRANSFER)
 	    && ((pl022->master_info)->enable_dma)) {
 		chip->enable_dma = true;
 		dev_dbg(&spi->dev, "DMA mode set in controller state\n");
 		SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
 			       SSP_DMACR_MASK_RXDMAE, 0);
 		SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
 			       SSP_DMACR_MASK_TXDMAE, 1);
 	} else {
 		chip->enable_dma = false;
 		dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n");
 		SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
 			       SSP_DMACR_MASK_RXDMAE, 0);
 		SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
 			       SSP_DMACR_MASK_TXDMAE, 1);
 	}
 	chip->cpsr = clk_freq.cpsdvsr;
 	/* Special setup for the ST micro extended control registers */
 	if (pl022->vendor->extended_cr) {
 		u32 etx;
 		if (pl022->vendor->pl023) {
 			/* These bits are only in the PL023 */
 			SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
 				       SSP_CR1_MASK_FBCLKDEL_ST, 13);
 		} else {
 			/* These bits are in the PL022 but not PL023 */
 			SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
 				       SSP_CR0_MASK_HALFDUP_ST, 5);
 			SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
 				       SSP_CR0_MASK_CSS_ST, 16);
 			SSP_WRITE_BITS(chip->cr0, chip_info->iface,
 				       SSP_CR0_MASK_FRF_ST, 21);
 			SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
 				       SSP_CR1_MASK_MWAIT_ST, 6);
 		}
 		SSP_WRITE_BITS(chip->cr0, bits - 1,
 			       SSP_CR0_MASK_DSS_ST, 0);
 		if (spi->mode & SPI_LSB_FIRST) {
 			tmp = SSP_RX_LSB;
 			etx = SSP_TX_LSB;
 		} else {
 			tmp = SSP_RX_MSB;
 			etx = SSP_TX_MSB;
 		}
 		SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);
 		SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);
 		SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
 			       SSP_CR1_MASK_RXIFLSEL_ST, 7);
 		SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
 			       SSP_CR1_MASK_TXIFLSEL_ST, 10);
 	} else {
 		SSP_WRITE_BITS(chip->cr0, bits - 1,
 			       SSP_CR0_MASK_DSS, 0);
 		SSP_WRITE_BITS(chip->cr0, chip_info->iface,
 			       SSP_CR0_MASK_FRF, 4);
 	}
 	/* Stuff that is common for all versions */
 	if (spi->mode & SPI_CPOL)
 		tmp = SSP_CLK_POL_IDLE_HIGH;
 	else
 		tmp = SSP_CLK_POL_IDLE_LOW;
 	SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);
 	if (spi->mode & SPI_CPHA)
 		tmp = SSP_CLK_SECOND_EDGE;
 	else
 		tmp = SSP_CLK_FIRST_EDGE;
 	SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);
 	SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8);
 	/* Loopback is available on all versions except PL023 */
 	if (pl022->vendor->loopback) {
 		if (spi->mode & SPI_LOOP)
 			tmp = LOOPBACK_ENABLED;
 		else
 			tmp = LOOPBACK_DISABLED;
 		SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);
 	}
 	SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
 	SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
 	SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD,
 		3);
 	/* Save controller_state */
 	spi_set_ctldata(spi, chip);
 	return status;
  err_config_params:
 	spi_set_ctldata(spi, NULL);
 	kfree(chip);
 	return status;
 }
 /**
  * pl022_cleanup - cleanup function registered to SPI master framework
  * @spi: spi device which is requesting cleanup
  *
  * This function is registered to the SPI framework for this SPI master
  * controller. It will free the runtime state of chip.
  */
 static void pl022_cleanup(struct spi_device *spi)
 {
 	struct chip_data *chip = spi_get_ctldata(spi);
 	spi_set_ctldata(spi, NULL);
 	kfree(chip);
 }
 static int __devinit
 pl022_probe(struct amba_device *adev, const struct amba_id *id)
 {
 	struct device *dev = &adev->dev;
 	struct pl022_ssp_controller *platform_info = adev->dev.platform_data;
 	struct spi_master *master;
 	struct pl022 *pl022 = NULL;	/*Data for this driver */
 	int status = 0;
 	dev_info(&adev->dev,
 		 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid);
 	if (platform_info == NULL) {
 		dev_err(&adev->dev, "probe - no platform data supplied\n");
 		status = -ENODEV;
 		goto err_no_pdata;
 	}
 	/* Allocate master with space for data */
 	master = spi_alloc_master(dev, sizeof(struct pl022));
 	if (master == NULL) {
 		dev_err(&adev->dev, "probe - cannot alloc SPI master\n");
 		status = -ENOMEM;
 		goto err_no_master;
 	}
 	pl022 = spi_master_get_devdata(master);
 	pl022->master = master;
 	pl022->master_info = platform_info;
 	pl022->adev = adev;
 	pl022->vendor = id->data;
 	/*
 	 * Bus Number Which has been Assigned to this SSP controller
 	 * on this board
 	 */
 	master->bus_num = platform_info->bus_id;
 	master->num_chipselect = platform_info->num_chipselect;
 	master->cleanup = pl022_cleanup;
 	master->setup = pl022_setup;
 	master->prepare_transfer_hardware = pl022_prepare_transfer_hardware;
 	master->transfer_one_message = pl022_transfer_one_message;
 	master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware;
 	master->rt = platform_info->rt;
 	/*
 	 * Supports mode 0-3, loopback, and active low CS. Transfers are
 	 * always MS bit first on the original pl022.
 	 */
 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
 	if (pl022->vendor->extended_cr)
 		master->mode_bits |= SPI_LSB_FIRST;
 	dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num);
 	status = amba_request_regions(adev, NULL);
 	if (status)
 		goto err_no_ioregion;
 	pl022->phybase = adev->res.start;
 	pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res));
 	if (pl022->virtbase == NULL) {
 		status = -ENOMEM;
 		goto err_no_ioremap;
 	}
 	printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n",
 	       adev->res.start, pl022->virtbase);
+	pm_runtime_enable(dev);
+	pm_runtime_resume(dev);
 	pl022->clk = clk_get(&adev->dev, NULL);
 	if (IS_ERR(pl022->clk)) {
 		status = PTR_ERR(pl022->clk);
 		dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n");
 		goto err_no_clk;
 	}
 	status = clk_prepare(pl022->clk);
 	if (status) {
 		dev_err(&adev->dev, "could not prepare SSP/SPI bus clock\n");
 		goto  err_clk_prep;
 	}
 	status = clk_enable(pl022->clk);
 	if (status) {
 		dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n");
 		goto err_no_clk_en;
 	}
 	/* Initialize transfer pump */
 	tasklet_init(&pl022->pump_transfers, pump_transfers,
 		     (unsigned long)pl022);
 	/* Disable SSP */
 	writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
 	       SSP_CR1(pl022->virtbase));
 	load_ssp_default_config(pl022);
 	status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022",
 			     pl022);
 	if (status < 0) {
 		dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status);
 		goto err_no_irq;
 	}
 	/* Get DMA channels */
 	if (platform_info->enable_dma) {
 		status = pl022_dma_probe(pl022);
 		if (status != 0)
 			platform_info->enable_dma = 0;
 	}
 	/* Register with the SPI framework */
 	amba_set_drvdata(adev, pl022);
 	status = spi_register_master(master);
 	if (status != 0) {
 		dev_err(&adev->dev,
 			"probe - problem registering spi master\n");
 		goto err_spi_register;
 	}
 	dev_dbg(dev, "probe succeeded\n");
 	/* let runtime pm put suspend */
 	if (platform_info->autosuspend_delay > 0) {
 		dev_info(&adev->dev,
 			"will use autosuspend for runtime pm, delay %dms\n",
 			platform_info->autosuspend_delay);
 		pm_runtime_set_autosuspend_delay(dev,
 			platform_info->autosuspend_delay);
 		pm_runtime_use_autosuspend(dev);
 		pm_runtime_put_autosuspend(dev);
 	} else {
 		pm_runtime_put(dev);
 	}
 	return 0;
  err_spi_register:
 	if (platform_info->enable_dma)
 		pl022_dma_remove(pl022);
 	free_irq(adev->irq[0], pl022);
  err_no_irq:
 	clk_disable(pl022->clk);
  err_no_clk_en:
 	clk_unprepare(pl022->clk);
  err_clk_prep:
 	clk_put(pl022->clk);
  err_no_clk:
 	iounmap(pl022->virtbase);
  err_no_ioremap:
 	amba_release_regions(adev);
  err_no_ioregion:
 	spi_master_put(master);
  err_no_master:
  err_no_pdata:
 	return status;
 }
 static int __devexit
 pl022_remove(struct amba_device *adev)
 {
 	struct pl022 *pl022 = amba_get_drvdata(adev);
 	if (!pl022)
 		return 0;
 	/*
 	 * undo pm_runtime_put() in probe.  I assume that we're not
 	 * accessing the primecell here.
 	 */
 	pm_runtime_get_noresume(&adev->dev);
 	load_ssp_default_config(pl022);
 	if (pl022->master_info->enable_dma)
 		pl022_dma_remove(pl022);
 	free_irq(adev->irq[0], pl022);
 	clk_disable(pl022->clk);
 	clk_unprepare(pl022->clk);
 	clk_put(pl022->clk);
+	pm_runtime_disable(&adev->dev);
 	iounmap(pl022->virtbase);
 	amba_release_regions(adev);
 	tasklet_disable(&pl022->pump_transfers);
 	spi_unregister_master(pl022->master);
 	spi_master_put(pl022->master);
 	amba_set_drvdata(adev, NULL);
 	return 0;
 }
 #ifdef CONFIG_SUSPEND
 static int pl022_suspend(struct device *dev)
 {
 	struct pl022 *pl022 = dev_get_drvdata(dev);
 	int ret;
 	ret = spi_master_suspend(pl022->master);
 	if (ret) {
 		dev_warn(dev, "cannot suspend master\n");
 		return ret;
 	}
 	dev_dbg(dev, "suspended\n");
 	return 0;
 }
 static int pl022_resume(struct device *dev)
 {
 	struct pl022 *pl022 = dev_get_drvdata(dev);
 	int ret;
 	/* Start the queue running */
 	ret = spi_master_resume(pl022->master);
 	if (ret)
 		dev_err(dev, "problem starting queue (%d)\n", ret);
 	else
 		dev_dbg(dev, "resumed\n");
 	return ret;
 }
 #endif	/* CONFIG_PM */
 #ifdef CONFIG_PM_RUNTIME
 static int pl022_runtime_suspend(struct device *dev)
 {
 	struct pl022 *pl022 = dev_get_drvdata(dev);
 	clk_disable(pl022->clk);
 	return 0;
 }
 static int pl022_runtime_resume(struct device *dev)
 {
 	struct pl022 *pl022 = dev_get_drvdata(dev);
 	clk_enable(pl022->clk);
 	return 0;
 }
 #endif
 static const struct dev_pm_ops pl022_dev_pm_ops = {
 	SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume)
 	SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL)
 };
 static struct vendor_data vendor_arm = {
 	.fifodepth = 8,
 	.max_bpw = 16,
 	.unidir = false,
 	.extended_cr = false,
 	.pl023 = false,
 	.loopback = true,
 };
 static struct vendor_data vendor_st = {
 	.fifodepth = 32,
 	.max_bpw = 32,
 	.unidir = false,
 	.extended_cr = true,
 	.pl023 = false,
 	.loopback = true,
 };
 static struct vendor_data vendor_st_pl023 = {
 	.fifodepth = 32,
 	.max_bpw = 32,
 	.unidir = false,
 	.extended_cr = true,
 	.pl023 = true,
 	.loopback = false,
 };
-static struct vendor_data vendor_db5500_pl023 = {
-	.fifodepth = 32,
-	.max_bpw = 32,
-	.unidir = false,
-	.extended_cr = true,
-	.pl023 = true,
-	.loopback = true,
-};
 static struct amba_id pl022_ids[] = {
 	{
 		/*
 		 * ARM PL022 variant, this has a 16bit wide
 		 * and 8 locations deep TX/RX FIFO
 		 */
 		.id	= 0x00041022,
 		.mask	= 0x000fffff,
 		.data	= &vendor_arm,
 	},
 	{
 		/*
 		 * ST Micro derivative, this has 32bit wide
 		 * and 32 locations deep TX/RX FIFO
 		 */
 		.id	= 0x01080022,
 		.mask	= 0xffffffff,
 		.data	= &vendor_st,
 	},
 	{
 		/*
 		 * ST-Ericsson derivative "PL023" (this is not
 		 * an official ARM number), this is a PL022 SSP block
 		 * stripped to SPI mode only, it has 32bit wide
 		 * and 32 locations deep TX/RX FIFO but no extended
 		 * CR0/CR1 register
 		 */
 		.id	= 0x00080023,
 		.mask	= 0xffffffff,
 		.data	= &vendor_st_pl023,
-	},
-	{
-		.id	= 0x10080023,
-		.mask	= 0xffffffff,
-		.data	= &vendor_db5500_pl023,
 	},
 	{ 0, 0 },
 };
 MODULE_DEVICE_TABLE(amba, pl022_ids);
 static struct amba_driver pl022_driver = {
 	.drv = {
 		.name	= "ssp-pl022",
 		.pm	= &pl022_dev_pm_ops,
 	},
 	.id_table	= pl022_ids,
 	.probe		= pl022_probe,
 	.remove		= __devexit_p(pl022_remove),
 };
 static int __init pl022_init(void)
 {
 	return amba_driver_register(&pl022_driver);
 }
 subsys_initcall(pl022_init);
 static void __exit pl022_exit(void)

drivers/spi/spi-tegra.c

Diff comments View file @ 0082c16

1	/*	1	/*
2	* Driver for Nvidia TEGRA spi controller.	2	* Driver for Nvidia TEGRA spi controller.
3	*	3	*
4	* Copyright (C) 2010 Google, Inc.	4	* Copyright (C) 2010 Google, Inc.
5	*	5	*
6	* Author:	6	* Author:
7	* Erik Gilling <konkers@android.com>	7	* Erik Gilling <konkers@android.com>
8	*	8	*
9	* This software is licensed under the terms of the GNU General Public	9	* This software is licensed under the terms of the GNU General Public
10	* License version 2, as published by the Free Software Foundation, and	10	* License version 2, as published by the Free Software Foundation, and
11	* may be copied, distributed, and modified under those terms.	11	* may be copied, distributed, and modified under those terms.
12	*	12	*
13	* This program is distributed in the hope that it will be useful,	13	* This program is distributed in the hope that it will be useful,
14	* but WITHOUT ANY WARRANTY; without even the implied warranty of	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16	* GNU General Public License for more details.	16	* GNU General Public License for more details.
17	*	17	*
18	*/	18	*/
19		19
20	#include <linux/kernel.h>	20	#include <linux/kernel.h>
21	#include <linux/module.h>	21	#include <linux/module.h>
22	#include <linux/init.h>	22	#include <linux/init.h>
23	#include <linux/err.h>	23	#include <linux/err.h>
24	#include <linux/platform_device.h>	24	#include <linux/platform_device.h>
25	#include <linux/io.h>	25	#include <linux/io.h>
26	#include <linux/dma-mapping.h>	26	#include <linux/dma-mapping.h>
27	#include <linux/dmapool.h>	27	#include <linux/dmapool.h>
28	#include <linux/clk.h>	28	#include <linux/clk.h>
29	#include <linux/interrupt.h>	29	#include <linux/interrupt.h>
30	#include <linux/delay.h>	30	#include <linux/delay.h>
31		31
32	#include <linux/spi/spi.h>	32	#include <linux/spi/spi.h>
		33	#include <linux/dmaengine.h>
33		34
34	#include <mach/dma.h>	35	#include <mach/dma.h>
35		36
36	#define SLINK_COMMAND 0x000	37	#define SLINK_COMMAND 0x000
37	#define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0)	38	#define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0)
38	#define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5)	39	#define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5)
39	#define SLINK_BOTH_EN (1 << 10)	40	#define SLINK_BOTH_EN (1 << 10)
40	#define SLINK_CS_SW (1 << 11)	41	#define SLINK_CS_SW (1 << 11)
41	#define SLINK_CS_VALUE (1 << 12)	42	#define SLINK_CS_VALUE (1 << 12)
42	#define SLINK_CS_POLARITY (1 << 13)	43	#define SLINK_CS_POLARITY (1 << 13)
43	#define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16)	44	#define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16)
44	#define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16)	45	#define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16)
45	#define SLINK_IDLE_SDA_PULL_LOW (2 << 16)	46	#define SLINK_IDLE_SDA_PULL_LOW (2 << 16)
46	#define SLINK_IDLE_SDA_PULL_HIGH (3 << 16)	47	#define SLINK_IDLE_SDA_PULL_HIGH (3 << 16)
47	#define SLINK_IDLE_SDA_MASK (3 << 16)	48	#define SLINK_IDLE_SDA_MASK (3 << 16)
48	#define SLINK_CS_POLARITY1 (1 << 20)	49	#define SLINK_CS_POLARITY1 (1 << 20)
49	#define SLINK_CK_SDA (1 << 21)	50	#define SLINK_CK_SDA (1 << 21)
50	#define SLINK_CS_POLARITY2 (1 << 22)	51	#define SLINK_CS_POLARITY2 (1 << 22)
51	#define SLINK_CS_POLARITY3 (1 << 23)	52	#define SLINK_CS_POLARITY3 (1 << 23)
52	#define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24)	53	#define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24)
53	#define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24)	54	#define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24)
54	#define SLINK_IDLE_SCLK_PULL_LOW (2 << 24)	55	#define SLINK_IDLE_SCLK_PULL_LOW (2 << 24)
55	#define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24)	56	#define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24)
56	#define SLINK_IDLE_SCLK_MASK (3 << 24)	57	#define SLINK_IDLE_SCLK_MASK (3 << 24)
57	#define SLINK_M_S (1 << 28)	58	#define SLINK_M_S (1 << 28)
58	#define SLINK_WAIT (1 << 29)	59	#define SLINK_WAIT (1 << 29)
59	#define SLINK_GO (1 << 30)	60	#define SLINK_GO (1 << 30)
60	#define SLINK_ENB (1 << 31)	61	#define SLINK_ENB (1 << 31)
61		62
62	#define SLINK_COMMAND2 0x004	63	#define SLINK_COMMAND2 0x004
63	#define SLINK_LSBFE (1 << 0)	64	#define SLINK_LSBFE (1 << 0)
64	#define SLINK_SSOE (1 << 1)	65	#define SLINK_SSOE (1 << 1)
65	#define SLINK_SPIE (1 << 4)	66	#define SLINK_SPIE (1 << 4)
66	#define SLINK_BIDIROE (1 << 6)	67	#define SLINK_BIDIROE (1 << 6)
67	#define SLINK_MODFEN (1 << 7)	68	#define SLINK_MODFEN (1 << 7)
68	#define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8)	69	#define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8)
69	#define SLINK_CS_ACTIVE_BETWEEN (1 << 17)	70	#define SLINK_CS_ACTIVE_BETWEEN (1 << 17)
70	#define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18)	71	#define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18)
71	#define SLINK_SS_SETUP(x) (((x) & 0x3) << 20)	72	#define SLINK_SS_SETUP(x) (((x) & 0x3) << 20)
72	#define SLINK_FIFO_REFILLS_0 (0 << 22)	73	#define SLINK_FIFO_REFILLS_0 (0 << 22)
73	#define SLINK_FIFO_REFILLS_1 (1 << 22)	74	#define SLINK_FIFO_REFILLS_1 (1 << 22)
74	#define SLINK_FIFO_REFILLS_2 (2 << 22)	75	#define SLINK_FIFO_REFILLS_2 (2 << 22)
75	#define SLINK_FIFO_REFILLS_3 (3 << 22)	76	#define SLINK_FIFO_REFILLS_3 (3 << 22)
76	#define SLINK_FIFO_REFILLS_MASK (3 << 22)	77	#define SLINK_FIFO_REFILLS_MASK (3 << 22)
77	#define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26)	78	#define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26)
78	#define SLINK_SPC0 (1 << 29)	79	#define SLINK_SPC0 (1 << 29)
79	#define SLINK_TXEN (1 << 30)	80	#define SLINK_TXEN (1 << 30)
80	#define SLINK_RXEN (1 << 31)	81	#define SLINK_RXEN (1 << 31)
81		82
82	#define SLINK_STATUS 0x008	83	#define SLINK_STATUS 0x008
83	#define SLINK_COUNT(val) (((val) >> 0) & 0x1f)	84	#define SLINK_COUNT(val) (((val) >> 0) & 0x1f)
84	#define SLINK_WORD(val) (((val) >> 5) & 0x1f)	85	#define SLINK_WORD(val) (((val) >> 5) & 0x1f)
85	#define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff)	86	#define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff)
86	#define SLINK_MODF (1 << 16)	87	#define SLINK_MODF (1 << 16)
87	#define SLINK_RX_UNF (1 << 18)	88	#define SLINK_RX_UNF (1 << 18)
88	#define SLINK_TX_OVF (1 << 19)	89	#define SLINK_TX_OVF (1 << 19)
89	#define SLINK_TX_FULL (1 << 20)	90	#define SLINK_TX_FULL (1 << 20)
90	#define SLINK_TX_EMPTY (1 << 21)	91	#define SLINK_TX_EMPTY (1 << 21)
91	#define SLINK_RX_FULL (1 << 22)	92	#define SLINK_RX_FULL (1 << 22)
92	#define SLINK_RX_EMPTY (1 << 23)	93	#define SLINK_RX_EMPTY (1 << 23)
93	#define SLINK_TX_UNF (1 << 24)	94	#define SLINK_TX_UNF (1 << 24)
94	#define SLINK_RX_OVF (1 << 25)	95	#define SLINK_RX_OVF (1 << 25)
95	#define SLINK_TX_FLUSH (1 << 26)	96	#define SLINK_TX_FLUSH (1 << 26)
96	#define SLINK_RX_FLUSH (1 << 27)	97	#define SLINK_RX_FLUSH (1 << 27)
97	#define SLINK_SCLK (1 << 28)	98	#define SLINK_SCLK (1 << 28)
98	#define SLINK_ERR (1 << 29)	99	#define SLINK_ERR (1 << 29)
99	#define SLINK_RDY (1 << 30)	100	#define SLINK_RDY (1 << 30)
100	#define SLINK_BSY (1 << 31)	101	#define SLINK_BSY (1 << 31)
101		102
102	#define SLINK_MAS_DATA 0x010	103	#define SLINK_MAS_DATA 0x010
103	#define SLINK_SLAVE_DATA 0x014	104	#define SLINK_SLAVE_DATA 0x014
104		105
105	#define SLINK_DMA_CTL 0x018	106	#define SLINK_DMA_CTL 0x018
106	#define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0)	107	#define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0)
107	#define SLINK_TX_TRIG_1 (0 << 16)	108	#define SLINK_TX_TRIG_1 (0 << 16)
108	#define SLINK_TX_TRIG_4 (1 << 16)	109	#define SLINK_TX_TRIG_4 (1 << 16)
109	#define SLINK_TX_TRIG_8 (2 << 16)	110	#define SLINK_TX_TRIG_8 (2 << 16)
110	#define SLINK_TX_TRIG_16 (3 << 16)	111	#define SLINK_TX_TRIG_16 (3 << 16)
111	#define SLINK_TX_TRIG_MASK (3 << 16)	112	#define SLINK_TX_TRIG_MASK (3 << 16)
112	#define SLINK_RX_TRIG_1 (0 << 18)	113	#define SLINK_RX_TRIG_1 (0 << 18)
113	#define SLINK_RX_TRIG_4 (1 << 18)	114	#define SLINK_RX_TRIG_4 (1 << 18)
114	#define SLINK_RX_TRIG_8 (2 << 18)	115	#define SLINK_RX_TRIG_8 (2 << 18)
115	#define SLINK_RX_TRIG_16 (3 << 18)	116	#define SLINK_RX_TRIG_16 (3 << 18)
116	#define SLINK_RX_TRIG_MASK (3 << 18)	117	#define SLINK_RX_TRIG_MASK (3 << 18)
117	#define SLINK_PACKED (1 << 20)	118	#define SLINK_PACKED (1 << 20)
118	#define SLINK_PACK_SIZE_4 (0 << 21)	119	#define SLINK_PACK_SIZE_4 (0 << 21)
119	#define SLINK_PACK_SIZE_8 (1 << 21)	120	#define SLINK_PACK_SIZE_8 (1 << 21)
120	#define SLINK_PACK_SIZE_16 (2 << 21)	121	#define SLINK_PACK_SIZE_16 (2 << 21)
121	#define SLINK_PACK_SIZE_32 (3 << 21)	122	#define SLINK_PACK_SIZE_32 (3 << 21)
122	#define SLINK_PACK_SIZE_MASK (3 << 21)	123	#define SLINK_PACK_SIZE_MASK (3 << 21)
123	#define SLINK_IE_TXC (1 << 26)	124	#define SLINK_IE_TXC (1 << 26)
124	#define SLINK_IE_RXC (1 << 27)	125	#define SLINK_IE_RXC (1 << 27)
125	#define SLINK_DMA_EN (1 << 31)	126	#define SLINK_DMA_EN (1 << 31)
126		127
127	#define SLINK_STATUS2 0x01c	128	#define SLINK_STATUS2 0x01c
128	#define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0)	129	#define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0)
129	#define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f) >> 16)	130	#define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f) >> 16)
130		131
131	#define SLINK_TX_FIFO 0x100	132	#define SLINK_TX_FIFO 0x100
132	#define SLINK_RX_FIFO 0x180	133	#define SLINK_RX_FIFO 0x180
133		134
134	static const unsigned long spi_tegra_req_sels[] = {	135	static const unsigned long spi_tegra_req_sels[] = {
135	TEGRA_DMA_REQ_SEL_SL2B1,	136	TEGRA_DMA_REQ_SEL_SL2B1,
136	TEGRA_DMA_REQ_SEL_SL2B2,	137	TEGRA_DMA_REQ_SEL_SL2B2,
137	TEGRA_DMA_REQ_SEL_SL2B3,	138	TEGRA_DMA_REQ_SEL_SL2B3,
138	TEGRA_DMA_REQ_SEL_SL2B4,	139	TEGRA_DMA_REQ_SEL_SL2B4,
139	};	140	};
140		141
141	#define BB_LEN 32	142	#define BB_LEN 32
142		143
143	struct spi_tegra_data {	144	struct spi_tegra_data {
144	struct spi_master *master;	145	struct spi_master *master;
145	struct platform_device *pdev;	146	struct platform_device *pdev;
146	spinlock_t lock;	147	spinlock_t lock;
147		148
148	struct clk *clk;	149	struct clk *clk;
149	void __iomem *base;	150	void __iomem *base;
150	unsigned long phys;	151	unsigned long phys;
151		152
152	u32 cur_speed;	153	u32 cur_speed;
153		154
154	struct list_head queue;	155	struct list_head queue;
155	struct spi_transfer *cur;	156	struct spi_transfer *cur;
156	unsigned cur_pos;	157	unsigned cur_pos;
157	unsigned cur_len;	158	unsigned cur_len;
158	unsigned cur_bytes_per_word;	159	unsigned cur_bytes_per_word;
159		160
160	/* The tegra spi controller has a bug which causes the first word	161	/* The tegra spi controller has a bug which causes the first word
161	* in PIO transactions to be garbage. Since packed DMA transactions	162	* in PIO transactions to be garbage. Since packed DMA transactions
162	* require transfers to be 4 byte aligned we need a bounce buffer	163	* require transfers to be 4 byte aligned we need a bounce buffer
163	* for the generic case.	164	* for the generic case.
164	*/	165	*/
		166	int dma_req_len;
		167	#if defined(CONFIG_TEGRA_SYSTEM_DMA)
165	struct tegra_dma_req rx_dma_req;	168	struct tegra_dma_req rx_dma_req;
166	struct tegra_dma_channel *rx_dma;	169	struct tegra_dma_channel *rx_dma;
		170	#else
		171	struct dma_chan *rx_dma;
		172	struct dma_slave_config sconfig;
		173	struct dma_async_tx_descriptor *rx_dma_desc;
		174	dma_cookie_t rx_cookie;
		175	#endif
167	u32 *rx_bb;	176	u32 *rx_bb;
168	dma_addr_t rx_bb_phys;	177	dma_addr_t rx_bb_phys;
169	};	178	};
170		179
		180	#if !defined(CONFIG_TEGRA_SYSTEM_DMA)
		181	static void tegra_spi_rx_dma_complete(void *args);
		182	#endif
171		183
172	static inline unsigned long spi_tegra_readl(struct spi_tegra_data *tspi,	184	static inline unsigned long spi_tegra_readl(struct spi_tegra_data *tspi,
173	unsigned long reg)	185	unsigned long reg)
174	{	186	{
175	return readl(tspi->base + reg);	187	return readl(tspi->base + reg);
176	}	188	}
177		189
178	static inline void spi_tegra_writel(struct spi_tegra_data *tspi,	190	static inline void spi_tegra_writel(struct spi_tegra_data *tspi,
179	unsigned long val,	191	unsigned long val,
180	unsigned long reg)	192	unsigned long reg)
181	{	193	{
182	writel(val, tspi->base + reg);	194	writel(val, tspi->base + reg);
183	}	195	}
184		196
185	static void spi_tegra_go(struct spi_tegra_data *tspi)	197	static void spi_tegra_go(struct spi_tegra_data *tspi)
186	{	198	{
187	unsigned long val;	199	unsigned long val;
188		200
189	wmb();	201	wmb();
190		202
191	val = spi_tegra_readl(tspi, SLINK_DMA_CTL);	203	val = spi_tegra_readl(tspi, SLINK_DMA_CTL);
192	val &= ~SLINK_DMA_BLOCK_SIZE(~0) & ~SLINK_DMA_EN;	204	val &= ~SLINK_DMA_BLOCK_SIZE(~0) & ~SLINK_DMA_EN;
193	val \|= SLINK_DMA_BLOCK_SIZE(tspi->rx_dma_req.size / 4 - 1);	205	val \|= SLINK_DMA_BLOCK_SIZE(tspi->dma_req_len / 4 - 1);
194	spi_tegra_writel(tspi, val, SLINK_DMA_CTL);	206	spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
195		207	#if defined(CONFIG_TEGRA_SYSTEM_DMA)
		208	tspi->rx_dma_req.size = tspi->dma_req_len;
196	tegra_dma_enqueue_req(tspi->rx_dma, &tspi->rx_dma_req);	209	tegra_dma_enqueue_req(tspi->rx_dma, &tspi->rx_dma_req);
		210	#else
		211	tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma,
		212	tspi->rx_bb_phys, tspi->dma_req_len,
		213	DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
		214	if (!tspi->rx_dma_desc) {
		215	dev_err(&tspi->pdev->dev, "dmaengine slave prep failed\n");
		216	return;
		217	}
		218	tspi->rx_dma_desc->callback = tegra_spi_rx_dma_complete;
		219	tspi->rx_dma_desc->callback_param = tspi;
		220	tspi->rx_cookie = dmaengine_submit(tspi->rx_dma_desc);
		221	dma_async_issue_pending(tspi->rx_dma);
		222	#endif
197		223
198	val \|= SLINK_DMA_EN;	224	val \|= SLINK_DMA_EN;
199	spi_tegra_writel(tspi, val, SLINK_DMA_CTL);	225	spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
200	}	226	}
201		227
202	static unsigned spi_tegra_fill_tx_fifo(struct spi_tegra_data *tspi,	228	static unsigned spi_tegra_fill_tx_fifo(struct spi_tegra_data *tspi,
203	struct spi_transfer *t)	229	struct spi_transfer *t)
204	{	230	{
205	unsigned len = min(t->len - tspi->cur_pos, BB_LEN *	231	unsigned len = min(t->len - tspi->cur_pos, BB_LEN *
206	tspi->cur_bytes_per_word);	232	tspi->cur_bytes_per_word);
207	u8 tx_buf = (u8 )t->tx_buf + tspi->cur_pos;	233	u8 tx_buf = (u8 )t->tx_buf + tspi->cur_pos;
208	int i, j;	234	int i, j;
209	unsigned long val;	235	unsigned long val;
210		236
211	val = spi_tegra_readl(tspi, SLINK_COMMAND);	237	val = spi_tegra_readl(tspi, SLINK_COMMAND);
212	val &= ~SLINK_WORD_SIZE(~0);	238	val &= ~SLINK_WORD_SIZE(~0);
213	val \|= SLINK_WORD_SIZE(len / tspi->cur_bytes_per_word - 1);	239	val \|= SLINK_WORD_SIZE(len / tspi->cur_bytes_per_word - 1);
214	spi_tegra_writel(tspi, val, SLINK_COMMAND);	240	spi_tegra_writel(tspi, val, SLINK_COMMAND);
215		241
216	for (i = 0; i < len; i += tspi->cur_bytes_per_word) {	242	for (i = 0; i < len; i += tspi->cur_bytes_per_word) {
217	val = 0;	243	val = 0;
218	for (j = 0; j < tspi->cur_bytes_per_word; j++)	244	for (j = 0; j < tspi->cur_bytes_per_word; j++)
219	val \|= tx_buf[i + j] << j * 8;	245	val \|= tx_buf[i + j] << j * 8;
220		246
221	spi_tegra_writel(tspi, val, SLINK_TX_FIFO);	247	spi_tegra_writel(tspi, val, SLINK_TX_FIFO);
222	}	248	}
223		249
224	tspi->rx_dma_req.size = len / tspi->cur_bytes_per_word * 4;	250	tspi->dma_req_len = len / tspi->cur_bytes_per_word * 4;
225		251
226	return len;	252	return len;
227	}	253	}
228		254
229	static unsigned spi_tegra_drain_rx_fifo(struct spi_tegra_data *tspi,	255	static unsigned spi_tegra_drain_rx_fifo(struct spi_tegra_data *tspi,
230	struct spi_transfer *t)	256	struct spi_transfer *t)
231	{	257	{
232	unsigned len = tspi->cur_len;	258	unsigned len = tspi->cur_len;
233	u8 rx_buf = (u8 )t->rx_buf + tspi->cur_pos;	259	u8 rx_buf = (u8 )t->rx_buf + tspi->cur_pos;
234	int i, j;	260	int i, j;
235	unsigned long val;	261	unsigned long val;
236		262
237	for (i = 0; i < len; i += tspi->cur_bytes_per_word) {	263	for (i = 0; i < len; i += tspi->cur_bytes_per_word) {
238	val = tspi->rx_bb[i / tspi->cur_bytes_per_word];	264	val = tspi->rx_bb[i / tspi->cur_bytes_per_word];
239	for (j = 0; j < tspi->cur_bytes_per_word; j++)	265	for (j = 0; j < tspi->cur_bytes_per_word; j++)
240	rx_buf[i + j] = (val >> (j * 8)) & 0xff;	266	rx_buf[i + j] = (val >> (j * 8)) & 0xff;
241	}	267	}
242		268
243	return len;	269	return len;
244	}	270	}
245		271
246	static void spi_tegra_start_transfer(struct spi_device *spi,	272	static void spi_tegra_start_transfer(struct spi_device *spi,
247	struct spi_transfer *t)	273	struct spi_transfer *t)
248	{	274	{
249	struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);	275	struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
250	u32 speed;	276	u32 speed;
251	u8 bits_per_word;	277	u8 bits_per_word;
252	unsigned long val;	278	unsigned long val;
253		279
254	speed = t->speed_hz ? t->speed_hz : spi->max_speed_hz;	280	speed = t->speed_hz ? t->speed_hz : spi->max_speed_hz;
255	bits_per_word = t->bits_per_word ? t->bits_per_word :	281	bits_per_word = t->bits_per_word ? t->bits_per_word :
256	spi->bits_per_word;	282	spi->bits_per_word;
257		283
258	tspi->cur_bytes_per_word = (bits_per_word - 1) / 8 + 1;	284	tspi->cur_bytes_per_word = (bits_per_word - 1) / 8 + 1;
259		285
260	if (speed != tspi->cur_speed)	286	if (speed != tspi->cur_speed)
261	clk_set_rate(tspi->clk, speed);	287	clk_set_rate(tspi->clk, speed);
262		288
263	if (tspi->cur_speed == 0)	289	if (tspi->cur_speed == 0)
264	clk_prepare_enable(tspi->clk);	290	clk_prepare_enable(tspi->clk);
265		291
266	tspi->cur_speed = speed;	292	tspi->cur_speed = speed;
267		293
268	val = spi_tegra_readl(tspi, SLINK_COMMAND2);	294	val = spi_tegra_readl(tspi, SLINK_COMMAND2);
269	val &= ~SLINK_SS_EN_CS(~0) \| SLINK_RXEN \| SLINK_TXEN;	295	val &= ~SLINK_SS_EN_CS(~0) \| SLINK_RXEN \| SLINK_TXEN;
270	if (t->rx_buf)	296	if (t->rx_buf)
271	val \|= SLINK_RXEN;	297	val \|= SLINK_RXEN;
272	if (t->tx_buf)	298	if (t->tx_buf)
273	val \|= SLINK_TXEN;	299	val \|= SLINK_TXEN;
274	val \|= SLINK_SS_EN_CS(spi->chip_select);	300	val \|= SLINK_SS_EN_CS(spi->chip_select);
275	val \|= SLINK_SPIE;	301	val \|= SLINK_SPIE;
276	spi_tegra_writel(tspi, val, SLINK_COMMAND2);	302	spi_tegra_writel(tspi, val, SLINK_COMMAND2);
277		303
278	val = spi_tegra_readl(tspi, SLINK_COMMAND);	304	val = spi_tegra_readl(tspi, SLINK_COMMAND);
279	val &= ~SLINK_BIT_LENGTH(~0);	305	val &= ~SLINK_BIT_LENGTH(~0);
280	val \|= SLINK_BIT_LENGTH(bits_per_word - 1);	306	val \|= SLINK_BIT_LENGTH(bits_per_word - 1);
281		307
282	/* FIXME: should probably control CS manually so that we can be sure	308	/* FIXME: should probably control CS manually so that we can be sure
283	* it does not go low between transfer and to support delay_usecs	309	* it does not go low between transfer and to support delay_usecs
284	* correctly.	310	* correctly.
285	*/	311	*/
286	val &= ~SLINK_IDLE_SCLK_MASK & ~SLINK_CK_SDA & ~SLINK_CS_SW;	312	val &= ~SLINK_IDLE_SCLK_MASK & ~SLINK_CK_SDA & ~SLINK_CS_SW;
287		313
288	if (spi->mode & SPI_CPHA)	314	if (spi->mode & SPI_CPHA)
289	val \|= SLINK_CK_SDA;	315	val \|= SLINK_CK_SDA;
290		316
291	if (spi->mode & SPI_CPOL)	317	if (spi->mode & SPI_CPOL)
292	val \|= SLINK_IDLE_SCLK_DRIVE_HIGH;	318	val \|= SLINK_IDLE_SCLK_DRIVE_HIGH;
293	else	319	else
294	val \|= SLINK_IDLE_SCLK_DRIVE_LOW;	320	val \|= SLINK_IDLE_SCLK_DRIVE_LOW;
295		321
296	val \|= SLINK_M_S;	322	val \|= SLINK_M_S;
297		323
298	spi_tegra_writel(tspi, val, SLINK_COMMAND);	324	spi_tegra_writel(tspi, val, SLINK_COMMAND);
299		325
300	spi_tegra_writel(tspi, SLINK_RX_FLUSH \| SLINK_TX_FLUSH, SLINK_STATUS);	326	spi_tegra_writel(tspi, SLINK_RX_FLUSH \| SLINK_TX_FLUSH, SLINK_STATUS);
301		327
302	tspi->cur = t;	328	tspi->cur = t;
303	tspi->cur_pos = 0;	329	tspi->cur_pos = 0;
304	tspi->cur_len = spi_tegra_fill_tx_fifo(tspi, t);	330	tspi->cur_len = spi_tegra_fill_tx_fifo(tspi, t);
305		331
306	spi_tegra_go(tspi);	332	spi_tegra_go(tspi);
307	}	333	}
308		334
309	static void spi_tegra_start_message(struct spi_device *spi,	335	static void spi_tegra_start_message(struct spi_device *spi,
310	struct spi_message *m)	336	struct spi_message *m)
311	{	337	{
312	struct spi_transfer *t;	338	struct spi_transfer *t;
313		339
314	m->actual_length = 0;	340	m->actual_length = 0;
315	m->status = 0;	341	m->status = 0;
316		342
317	t = list_first_entry(&m->transfers, struct spi_transfer, transfer_list);	343	t = list_first_entry(&m->transfers, struct spi_transfer, transfer_list);
318	spi_tegra_start_transfer(spi, t);	344	spi_tegra_start_transfer(spi, t);
319	}	345	}
320		346
321	static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req)	347	static void handle_spi_rx_dma_complete(struct spi_tegra_data *tspi)
322	{	348	{
323	struct spi_tegra_data *tspi = req->dev;
324	unsigned long flags;	349	unsigned long flags;
325	struct spi_message *m;	350	struct spi_message *m;
326	struct spi_device *spi;	351	struct spi_device *spi;
327	int timeout = 0;	352	int timeout = 0;
328	unsigned long val;	353	unsigned long val;
329		354
330	/* the SPI controller may come back with both the BSY and RDY bits	355	/* the SPI controller may come back with both the BSY and RDY bits
331	* set. In this case we need to wait for the BSY bit to clear so	356	* set. In this case we need to wait for the BSY bit to clear so
332	* that we are sure the DMA is finished. 1000 reads was empirically	357	* that we are sure the DMA is finished. 1000 reads was empirically
333	* determined to be long enough.	358	* determined to be long enough.
334	*/	359	*/
335	while (timeout++ < 1000) {	360	while (timeout++ < 1000) {
336	if (!(spi_tegra_readl(tspi, SLINK_STATUS) & SLINK_BSY))	361	if (!(spi_tegra_readl(tspi, SLINK_STATUS) & SLINK_BSY))
337	break;	362	break;
338	}	363	}
339		364
340	spin_lock_irqsave(&tspi->lock, flags);	365	spin_lock_irqsave(&tspi->lock, flags);
341		366
342	val = spi_tegra_readl(tspi, SLINK_STATUS);	367	val = spi_tegra_readl(tspi, SLINK_STATUS);
343	val \|= SLINK_RDY;	368	val \|= SLINK_RDY;
344	spi_tegra_writel(tspi, val, SLINK_STATUS);	369	spi_tegra_writel(tspi, val, SLINK_STATUS);
345		370
346	m = list_first_entry(&tspi->queue, struct spi_message, queue);	371	m = list_first_entry(&tspi->queue, struct spi_message, queue);
347		372
348	if (timeout >= 1000)	373	if (timeout >= 1000)
349	m->status = -EIO;	374	m->status = -EIO;
350		375
351	spi = m->state;	376	spi = m->state;
352		377
353	tspi->cur_pos += spi_tegra_drain_rx_fifo(tspi, tspi->cur);	378	tspi->cur_pos += spi_tegra_drain_rx_fifo(tspi, tspi->cur);
354	m->actual_length += tspi->cur_pos;	379	m->actual_length += tspi->cur_pos;
355		380
356	if (tspi->cur_pos < tspi->cur->len) {	381	if (tspi->cur_pos < tspi->cur->len) {
357	tspi->cur_len = spi_tegra_fill_tx_fifo(tspi, tspi->cur);	382	tspi->cur_len = spi_tegra_fill_tx_fifo(tspi, tspi->cur);
358	spi_tegra_go(tspi);	383	spi_tegra_go(tspi);
359	} else if (!list_is_last(&tspi->cur->transfer_list,	384	} else if (!list_is_last(&tspi->cur->transfer_list,
360	&m->transfers)) {	385	&m->transfers)) {
361	tspi->cur = list_first_entry(&tspi->cur->transfer_list,	386	tspi->cur = list_first_entry(&tspi->cur->transfer_list,
362	struct spi_transfer,	387	struct spi_transfer,
363	transfer_list);	388	transfer_list);
364	spi_tegra_start_transfer(spi, tspi->cur);	389	spi_tegra_start_transfer(spi, tspi->cur);
365	} else {	390	} else {
366	list_del(&m->queue);	391	list_del(&m->queue);
367		392
368	m->complete(m->context);	393	m->complete(m->context);
369		394
370	if (!list_empty(&tspi->queue)) {	395	if (!list_empty(&tspi->queue)) {
371	m = list_first_entry(&tspi->queue, struct spi_message,	396	m = list_first_entry(&tspi->queue, struct spi_message,
372	queue);	397	queue);
373	spi = m->state;	398	spi = m->state;
374	spi_tegra_start_message(spi, m);	399	spi_tegra_start_message(spi, m);
375	} else {	400	} else {
376	clk_disable_unprepare(tspi->clk);	401	clk_disable_unprepare(tspi->clk);
377	tspi->cur_speed = 0;	402	tspi->cur_speed = 0;
378	}	403	}
379	}	404	}
380		405
381	spin_unlock_irqrestore(&tspi->lock, flags);	406	spin_unlock_irqrestore(&tspi->lock, flags);
382	}	407	}
		408	#if defined(CONFIG_TEGRA_SYSTEM_DMA)
		409	static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req)
		410	{
		411	struct spi_tegra_data *tspi = req->dev;
		412	handle_spi_rx_dma_complete(tspi);
		413	}
		414	#else
		415	static void tegra_spi_rx_dma_complete(void *args)
		416	{
		417	struct spi_tegra_data *tspi = args;
		418	handle_spi_rx_dma_complete(tspi);
		419	}
		420	#endif
383		421
384	static int spi_tegra_setup(struct spi_device *spi)	422	static int spi_tegra_setup(struct spi_device *spi)
385	{	423	{
386	struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);	424	struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
387	unsigned long cs_bit;	425	unsigned long cs_bit;
388	unsigned long val;	426	unsigned long val;
389	unsigned long flags;	427	unsigned long flags;
390		428
391	dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",	429	dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
392	spi->bits_per_word,	430	spi->bits_per_word,
393	spi->mode & SPI_CPOL ? "" : "~",	431	spi->mode & SPI_CPOL ? "" : "~",
394	spi->mode & SPI_CPHA ? "" : "~",	432	spi->mode & SPI_CPHA ? "" : "~",
395	spi->max_speed_hz);	433	spi->max_speed_hz);
396		434
397		435
398	switch (spi->chip_select) {	436	switch (spi->chip_select) {
399	case 0:	437	case 0:
400	cs_bit = SLINK_CS_POLARITY;	438	cs_bit = SLINK_CS_POLARITY;
401	break;	439	break;
402		440
403	case 1:	441	case 1:
404	cs_bit = SLINK_CS_POLARITY1;	442	cs_bit = SLINK_CS_POLARITY1;
405	break;	443	break;
406		444
407	case 2:	445	case 2:
408	cs_bit = SLINK_CS_POLARITY2;	446	cs_bit = SLINK_CS_POLARITY2;
409	break;	447	break;
410		448
411	case 4:	449	case 4:
412	cs_bit = SLINK_CS_POLARITY3;	450	cs_bit = SLINK_CS_POLARITY3;
413	break;	451	break;
414		452
415	default:	453	default:
416	return -EINVAL;	454	return -EINVAL;
417	}	455	}
418		456
419	spin_lock_irqsave(&tspi->lock, flags);	457	spin_lock_irqsave(&tspi->lock, flags);
420		458
421	val = spi_tegra_readl(tspi, SLINK_COMMAND);	459	val = spi_tegra_readl(tspi, SLINK_COMMAND);
422	if (spi->mode & SPI_CS_HIGH)	460	if (spi->mode & SPI_CS_HIGH)
423	val \|= cs_bit;	461	val \|= cs_bit;
424	else	462	else
425	val &= ~cs_bit;	463	val &= ~cs_bit;
426	spi_tegra_writel(tspi, val, SLINK_COMMAND);	464	spi_tegra_writel(tspi, val, SLINK_COMMAND);
427		465
428	spin_unlock_irqrestore(&tspi->lock, flags);	466	spin_unlock_irqrestore(&tspi->lock, flags);
429		467
430	return 0;	468	return 0;
431	}	469	}
432		470
433	static int spi_tegra_transfer(struct spi_device spi, struct spi_message m)	471	static int spi_tegra_transfer(struct spi_device spi, struct spi_message m)
434	{	472	{
435	struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);	473	struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
436	struct spi_transfer *t;	474	struct spi_transfer *t;
437	unsigned long flags;	475	unsigned long flags;
438	int was_empty;	476	int was_empty;
439		477
440	if (list_empty(&m->transfers) \|\| !m->complete)	478	if (list_empty(&m->transfers) \|\| !m->complete)
441	return -EINVAL;	479	return -EINVAL;
442		480
443	list_for_each_entry(t, &m->transfers, transfer_list) {	481	list_for_each_entry(t, &m->transfers, transfer_list) {
444	if (t->bits_per_word < 0 \|\| t->bits_per_word > 32)	482	if (t->bits_per_word < 0 \|\| t->bits_per_word > 32)
445	return -EINVAL;	483	return -EINVAL;
446		484
447	if (t->len == 0)	485	if (t->len == 0)
448	return -EINVAL;	486	return -EINVAL;
449		487
450	if (!t->rx_buf && !t->tx_buf)	488	if (!t->rx_buf && !t->tx_buf)
451	return -EINVAL;	489	return -EINVAL;
452	}	490	}
453		491
454	m->state = spi;	492	m->state = spi;
455		493
456	spin_lock_irqsave(&tspi->lock, flags);	494	spin_lock_irqsave(&tspi->lock, flags);
457	was_empty = list_empty(&tspi->queue);	495	was_empty = list_empty(&tspi->queue);
458	list_add_tail(&m->queue, &tspi->queue);	496	list_add_tail(&m->queue, &tspi->queue);
459		497
460	if (was_empty)	498	if (was_empty)
461	spi_tegra_start_message(spi, m);	499	spi_tegra_start_message(spi, m);
462		500
463	spin_unlock_irqrestore(&tspi->lock, flags);	501	spin_unlock_irqrestore(&tspi->lock, flags);
464		502
465	return 0;	503	return 0;
466	}	504	}
467		505
468	static int __devinit spi_tegra_probe(struct platform_device *pdev)	506	static int __devinit spi_tegra_probe(struct platform_device *pdev)
469	{	507	{
470	struct spi_master *master;	508	struct spi_master *master;
471	struct spi_tegra_data *tspi;	509	struct spi_tegra_data *tspi;
472	struct resource *r;	510	struct resource *r;
473	int ret;	511	int ret;
		512	#if !defined(CONFIG_TEGRA_SYSTEM_DMA)
		513	dma_cap_mask_t mask;
		514	#endif
474		515
475	master = spi_alloc_master(&pdev->dev, sizeof *tspi);	516	master = spi_alloc_master(&pdev->dev, sizeof *tspi);
476	if (master == NULL) {	517	if (master == NULL) {
477	dev_err(&pdev->dev, "master allocation failed\n");	518	dev_err(&pdev->dev, "master allocation failed\n");
478	return -ENOMEM;	519	return -ENOMEM;
479	}	520	}
480		521
481	/* the spi->mode bits understood by this driver: */	522	/* the spi->mode bits understood by this driver: */
482	master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH;	523	master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH;
483		524
484	master->bus_num = pdev->id;	525	master->bus_num = pdev->id;
485		526
486	master->setup = spi_tegra_setup;	527	master->setup = spi_tegra_setup;
487	master->transfer = spi_tegra_transfer;	528	master->transfer = spi_tegra_transfer;
488	master->num_chipselect = 4;	529	master->num_chipselect = 4;
489		530
490	dev_set_drvdata(&pdev->dev, master);	531	dev_set_drvdata(&pdev->dev, master);
491	tspi = spi_master_get_devdata(master);	532	tspi = spi_master_get_devdata(master);
492	tspi->master = master;	533	tspi->master = master;
493	tspi->pdev = pdev;	534	tspi->pdev = pdev;
494	spin_lock_init(&tspi->lock);	535	spin_lock_init(&tspi->lock);
495		536
496	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);	537	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
497	if (r == NULL) {	538	if (r == NULL) {
498	ret = -ENODEV;	539	ret = -ENODEV;
499	goto err0;	540	goto err0;
500	}	541	}
501		542
502	if (!request_mem_region(r->start, resource_size(r),	543	if (!request_mem_region(r->start, resource_size(r),
503	dev_name(&pdev->dev))) {	544	dev_name(&pdev->dev))) {
504	ret = -EBUSY;	545	ret = -EBUSY;
505	goto err0;	546	goto err0;
506	}	547	}
507		548
508	tspi->phys = r->start;	549	tspi->phys = r->start;
509	tspi->base = ioremap(r->start, resource_size(r));	550	tspi->base = ioremap(r->start, resource_size(r));
510	if (!tspi->base) {	551	if (!tspi->base) {
511	dev_err(&pdev->dev, "can't ioremap iomem\n");	552	dev_err(&pdev->dev, "can't ioremap iomem\n");
512	ret = -ENOMEM;	553	ret = -ENOMEM;
513	goto err1;	554	goto err1;
514	}	555	}
515		556
516	tspi->clk = clk_get(&pdev->dev, NULL);	557	tspi->clk = clk_get(&pdev->dev, NULL);
517	if (IS_ERR(tspi->clk)) {	558	if (IS_ERR(tspi->clk)) {
518	dev_err(&pdev->dev, "can not get clock\n");	559	dev_err(&pdev->dev, "can not get clock\n");
519	ret = PTR_ERR(tspi->clk);	560	ret = PTR_ERR(tspi->clk);
520	goto err2;	561	goto err2;
521	}	562	}
522		563
523	INIT_LIST_HEAD(&tspi->queue);	564	INIT_LIST_HEAD(&tspi->queue);
524		565
		566	#if defined(CONFIG_TEGRA_SYSTEM_DMA)
525	tspi->rx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT);	567	tspi->rx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT);
526	if (!tspi->rx_dma) {	568	if (!tspi->rx_dma) {
527	dev_err(&pdev->dev, "can not allocate rx dma channel\n");	569	dev_err(&pdev->dev, "can not allocate rx dma channel\n");
528	ret = -ENODEV;	570	ret = -ENODEV;
529	goto err3;	571	goto err3;
530	}	572	}
		573	#else
		574	dma_cap_zero(mask);
		575	dma_cap_set(DMA_SLAVE, mask);
		576	tspi->rx_dma = dma_request_channel(mask, NULL, NULL);
		577	if (!tspi->rx_dma) {
		578	dev_err(&pdev->dev, "can not allocate rx dma channel\n");
		579	ret = -ENODEV;
		580	goto err3;
		581	}
531		582
		583	#endif
		584
532	tspi->rx_bb = dma_alloc_coherent(&pdev->dev, sizeof(u32) * BB_LEN,	585	tspi->rx_bb = dma_alloc_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
533	&tspi->rx_bb_phys, GFP_KERNEL);	586	&tspi->rx_bb_phys, GFP_KERNEL);
534	if (!tspi->rx_bb) {	587	if (!tspi->rx_bb) {
535	dev_err(&pdev->dev, "can not allocate rx bounce buffer\n");	588	dev_err(&pdev->dev, "can not allocate rx bounce buffer\n");
536	ret = -ENOMEM;	589	ret = -ENOMEM;
537	goto err4;	590	goto err4;
538	}	591	}
539		592
		593	#if defined(CONFIG_TEGRA_SYSTEM_DMA)
540	tspi->rx_dma_req.complete = tegra_spi_rx_dma_complete;	594	tspi->rx_dma_req.complete = tegra_spi_rx_dma_complete;
541	tspi->rx_dma_req.to_memory = 1;	595	tspi->rx_dma_req.to_memory = 1;
542	tspi->rx_dma_req.dest_addr = tspi->rx_bb_phys;	596	tspi->rx_dma_req.dest_addr = tspi->rx_bb_phys;
543	tspi->rx_dma_req.dest_bus_width = 32;	597	tspi->rx_dma_req.dest_bus_width = 32;
544	tspi->rx_dma_req.source_addr = tspi->phys + SLINK_RX_FIFO;	598	tspi->rx_dma_req.source_addr = tspi->phys + SLINK_RX_FIFO;
545	tspi->rx_dma_req.source_bus_width = 32;	599	tspi->rx_dma_req.source_bus_width = 32;
546	tspi->rx_dma_req.source_wrap = 4;	600	tspi->rx_dma_req.source_wrap = 4;
547	tspi->rx_dma_req.req_sel = spi_tegra_req_sels[pdev->id];	601	tspi->rx_dma_req.req_sel = spi_tegra_req_sels[pdev->id];
548	tspi->rx_dma_req.dev = tspi;	602	tspi->rx_dma_req.dev = tspi;
		603	#else
		604	/* Dmaengine Dma slave config */
		605	tspi->sconfig.src_addr = tspi->phys + SLINK_RX_FIFO;
		606	tspi->sconfig.dst_addr = tspi->phys + SLINK_RX_FIFO;
		607	tspi->sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
		608	tspi->sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
		609	tspi->sconfig.slave_id = spi_tegra_req_sels[pdev->id];
		610	tspi->sconfig.src_maxburst = 1;
		611	tspi->sconfig.dst_maxburst = 1;
		612	ret = dmaengine_device_control(tspi->rx_dma,
		613	DMA_SLAVE_CONFIG, (unsigned long) &tspi->sconfig);
		614	if (ret < 0) {
		615	dev_err(&pdev->dev, "can not do slave configure for dma %d\n",
		616	ret);
		617	goto err4;
		618	}
		619	#endif
549		620
550	master->dev.of_node = pdev->dev.of_node;	621	master->dev.of_node = pdev->dev.of_node;
551	ret = spi_register_master(master);	622	ret = spi_register_master(master);
552		623
553	if (ret < 0)	624	if (ret < 0)
554	goto err5;	625	goto err5;
555		626
556	return ret;	627	return ret;
557		628
558	err5:	629	err5:
559	dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,	630	dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
560	tspi->rx_bb, tspi->rx_bb_phys);	631	tspi->rx_bb, tspi->rx_bb_phys);
561	err4:	632	err4:
		633	#if defined(CONFIG_TEGRA_SYSTEM_DMA)
562	tegra_dma_free_channel(tspi->rx_dma);	634	tegra_dma_free_channel(tspi->rx_dma);
		635	#else
		636	dma_release_channel(tspi->rx_dma);
		637	#endif
563	err3:	638	err3:
564	clk_put(tspi->clk);	639	clk_put(tspi->clk);
565	err2:	640	err2:
566	iounmap(tspi->base);	641	iounmap(tspi->base);
567	err1:	642	err1:
568	release_mem_region(r->start, resource_size(r));	643	release_mem_region(r->start, resource_size(r));
569	err0:	644	err0:
570	spi_master_put(master);	645	spi_master_put(master);
571	return ret;	646	return ret;
572	}	647	}
573		648
574	static int __devexit spi_tegra_remove(struct platform_device *pdev)	649	static int __devexit spi_tegra_remove(struct platform_device *pdev)
575	{	650	{
576	struct spi_master *master;	651	struct spi_master *master;
577	struct spi_tegra_data *tspi;	652	struct spi_tegra_data *tspi;
578	struct resource *r;	653	struct resource *r;
579		654
580	master = dev_get_drvdata(&pdev->dev);	655	master = dev_get_drvdata(&pdev->dev);
581	tspi = spi_master_get_devdata(master);	656	tspi = spi_master_get_devdata(master);
582		657
583	spi_unregister_master(master);	658	spi_unregister_master(master);
		659	#if defined(CONFIG_TEGRA_SYSTEM_DMA)
584	tegra_dma_free_channel(tspi->rx_dma);	660	tegra_dma_free_channel(tspi->rx_dma);
		661	#else
		662	dma_release_channel(tspi->rx_dma);
		663	#endif
585		664
586	dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,	665	dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
587	tspi->rx_bb, tspi->rx_bb_phys);	666	tspi->rx_bb, tspi->rx_bb_phys);
588		667
589	clk_put(tspi->clk);	668	clk_put(tspi->clk);
590	iounmap(tspi->base);	669	iounmap(tspi->base);
591		670
592	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);	671	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
593	release_mem_region(r->start, resource_size(r));	672	release_mem_region(r->start, resource_size(r));
594		673
595	return 0;	674	return 0;
596	}	675	}
597		676
598	MODULE_ALIAS("platform:spi_tegra");	677	MODULE_ALIAS("platform:spi_tegra");
599		678
600	#ifdef CONFIG_OF	679	#ifdef CONFIG_OF
601	static struct of_device_id spi_tegra_of_match_table[] __devinitdata = {	680	static struct of_device_id spi_tegra_of_match_table[] __devinitdata = {
602	{ .compatible = "nvidia,tegra20-spi", },	681	{ .compatible = "nvidia,tegra20-spi", },
603	{}	682	{}
604	};	683	};
605	MODULE_DEVICE_TABLE(of, spi_tegra_of_match_table);	684	MODULE_DEVICE_TABLE(of, spi_tegra_of_match_table);
606	#else /* CONFIG_OF */	685	#else /* CONFIG_OF */
607	#define spi_tegra_of_match_table NULL	686	#define spi_tegra_of_match_table NULL
608	#endif /* CONFIG_OF */	687	#endif /* CONFIG_OF */
609		688
610	static struct platform_driver spi_tegra_driver = {	689	static struct platform_driver spi_tegra_driver = {
611	.driver = {	690	.driver = {
612	.name = "spi_tegra",	691	.name = "spi_tegra",
613	.owner = THIS_MODULE,	692	.owner = THIS_MODULE,
614	.of_match_table = spi_tegra_of_match_table,	693	.of_match_table = spi_tegra_of_match_table,
615	},	694	},
616	.probe = spi_tegra_probe,	695	.probe = spi_tegra_probe,
617	.remove = __devexit_p(spi_tegra_remove),	696	.remove = __devexit_p(spi_tegra_remove),
618	};	697	};
619	module_platform_driver(spi_tegra_driver);	698	module_platform_driver(spi_tegra_driver);
620		699
621	MODULE_LICENSE("GPL");	700	MODULE_LICENSE("GPL");

drivers/spi/spi-xcomm.c

Diff comments View file @ 0082c16

File was created	1	/*
	2	* Analog Devices AD-FMCOMMS1-EBZ board I2C-SPI bridge driver
	3	*
	4	* Copyright 2012 Analog Devices Inc.
	5	* Author: Lars-Peter Clausen <lars@metafoo.de>
	6	*
	7	* Licensed under the GPL-2 or later.
	8	*/
	9
	10	#include <linux/kernel.h>
	11	#include <linux/init.h>
	12	#include <linux/module.h>
	13	#include <linux/delay.h>
	14	#include <linux/i2c.h>
	15	#include <linux/spi/spi.h>
	16	#include <asm/unaligned.h>
	17
	18	#define SPI_XCOMM_SETTINGS_LEN_OFFSET 10
	19	#define SPI_XCOMM_SETTINGS_3WIRE BIT(6)
	20	#define SPI_XCOMM_SETTINGS_CS_HIGH BIT(5)
	21	#define SPI_XCOMM_SETTINGS_SAMPLE_END BIT(4)
	22	#define SPI_XCOMM_SETTINGS_CPHA BIT(3)
	23	#define SPI_XCOMM_SETTINGS_CPOL BIT(2)
	24	#define SPI_XCOMM_SETTINGS_CLOCK_DIV_MASK 0x3
	25	#define SPI_XCOMM_SETTINGS_CLOCK_DIV_64 0x2
	26	#define SPI_XCOMM_SETTINGS_CLOCK_DIV_16 0x1
	27	#define SPI_XCOMM_SETTINGS_CLOCK_DIV_4 0x0
	28
	29	#define SPI_XCOMM_CMD_UPDATE_CONFIG 0x03
	30	#define SPI_XCOMM_CMD_WRITE 0x04
	31
	32	#define SPI_XCOMM_CLOCK 48000000
	33
	34	struct spi_xcomm {
	35	struct i2c_client *i2c;
	36
	37	uint16_t settings;
	38	uint16_t chipselect;
	39
	40	unsigned int current_speed;
	41
	42	uint8_t buf[63];
	43	};
	44
	45	static int spi_xcomm_sync_config(struct spi_xcomm *spi_xcomm, unsigned int len)
	46	{
	47	uint16_t settings;
	48	uint8_t *buf = spi_xcomm->buf;
	49
	50	settings = spi_xcomm->settings;
	51	settings \|= len << SPI_XCOMM_SETTINGS_LEN_OFFSET;
	52
	53	buf[0] = SPI_XCOMM_CMD_UPDATE_CONFIG;
	54	put_unaligned_be16(settings, &buf[1]);
	55	put_unaligned_be16(spi_xcomm->chipselect, &buf[3]);
	56
	57	return i2c_master_send(spi_xcomm->i2c, buf, 5);
	58	}
	59
	60	static void spi_xcomm_chipselect(struct spi_xcomm *spi_xcomm,
	61	struct spi_device *spi, int is_active)
	62	{
	63	unsigned long cs = spi->chip_select;
	64	uint16_t chipselect = spi_xcomm->chipselect;
	65
	66	if (is_active)
	67	chipselect \|= BIT(cs);
	68	else
	69	chipselect &= ~BIT(cs);
	70
	71	spi_xcomm->chipselect = chipselect;
	72	}
	73
	74	static int spi_xcomm_setup_transfer(struct spi_xcomm *spi_xcomm,
	75	struct spi_device spi, struct spi_transfer t, unsigned int *settings)
	76	{
	77	unsigned int speed;
	78
	79	if ((t->bits_per_word && t->bits_per_word != 8) \|\| t->len > 62)
	80	return -EINVAL;
	81
	82	speed = t->speed_hz ? t->speed_hz : spi->max_speed_hz;
	83
	84	if (speed != spi_xcomm->current_speed) {
	85	unsigned int divider = DIV_ROUND_UP(SPI_XCOMM_CLOCK, speed);
	86	if (divider >= 64)
	87	*settings \|= SPI_XCOMM_SETTINGS_CLOCK_DIV_64;
	88	else if (divider >= 16)
	89	*settings \|= SPI_XCOMM_SETTINGS_CLOCK_DIV_16;
	90	else
	91	*settings \|= SPI_XCOMM_SETTINGS_CLOCK_DIV_4;
	92
	93	spi_xcomm->current_speed = speed;
	94	}
	95
	96	if (spi->mode & SPI_CPOL)
	97	*settings \|= SPI_XCOMM_SETTINGS_CPOL;
	98	else
	99	*settings &= ~SPI_XCOMM_SETTINGS_CPOL;
	100
	101	if (spi->mode & SPI_CPHA)
	102	*settings &= ~SPI_XCOMM_SETTINGS_CPHA;
	103	else
	104	*settings \|= SPI_XCOMM_SETTINGS_CPHA;
	105
	106	if (spi->mode & SPI_3WIRE)
	107	*settings \|= SPI_XCOMM_SETTINGS_3WIRE;
	108	else
	109	*settings &= ~SPI_XCOMM_SETTINGS_3WIRE;
	110
	111	return 0;
	112	}
	113
	114	static int spi_xcomm_txrx_bufs(struct spi_xcomm *spi_xcomm,
	115	struct spi_device spi, struct spi_transfer t)
	116	{
	117	int ret;
	118
	119	if (t->tx_buf) {
	120	spi_xcomm->buf[0] = SPI_XCOMM_CMD_WRITE;
	121	memcpy(spi_xcomm->buf + 1, t->tx_buf, t->len);
	122
	123	ret = i2c_master_send(spi_xcomm->i2c, spi_xcomm->buf, t->len + 1);
	124	if (ret < 0)
	125	return ret;
	126	else if (ret != t->len + 1)
	127	return -EIO;
	128	} else if (t->rx_buf) {
	129	ret = i2c_master_recv(spi_xcomm->i2c, t->rx_buf, t->len);
	130	if (ret < 0)
	131	return ret;
	132	else if (ret != t->len)
	133	return -EIO;
	134	}
	135
	136	return t->len;
	137	}
	138
	139	static int spi_xcomm_transfer_one(struct spi_master *master,
	140	struct spi_message *msg)
	141	{
	142	struct spi_xcomm *spi_xcomm = spi_master_get_devdata(master);
	143	unsigned int settings = spi_xcomm->settings;
	144	struct spi_device *spi = msg->spi;
	145	unsigned cs_change = 0;
	146	struct spi_transfer *t;
	147	bool is_first = true;
	148	int status = 0;
	149	bool is_last;
	150
	151	is_first = true;
	152
	153	spi_xcomm_chipselect(spi_xcomm, spi, true);
	154
	155	list_for_each_entry(t, &msg->transfers, transfer_list) {
	156
	157	if (!t->tx_buf && !t->rx_buf && t->len) {
	158	status = -EINVAL;
	159	break;
	160	}
	161
	162	status = spi_xcomm_setup_transfer(spi_xcomm, spi, t, &settings);
	163	if (status < 0)
	164	break;
	165
	166	is_last = list_is_last(&t->transfer_list, &msg->transfers);
	167	cs_change = t->cs_change;
	168
	169	if (cs_change ^ is_last)
	170	settings \|= BIT(5);
	171	else
	172	settings &= ~BIT(5);
	173
	174	if (t->rx_buf) {
	175	spi_xcomm->settings = settings;
	176	status = spi_xcomm_sync_config(spi_xcomm, t->len);
	177	if (status < 0)
	178	break;
	179	} else if (settings != spi_xcomm->settings \|\| is_first) {
	180	spi_xcomm->settings = settings;
	181	status = spi_xcomm_sync_config(spi_xcomm, 0);
	182	if (status < 0)
	183	break;
	184	}
	185
	186	if (t->len) {
	187	status = spi_xcomm_txrx_bufs(spi_xcomm, spi, t);
	188
	189	if (status < 0)
	190	break;
	191
	192	if (status > 0)
	193	msg->actual_length += status;
	194	}
	195	status = 0;
	196
	197	if (t->delay_usecs)
	198	udelay(t->delay_usecs);
	199
	200	is_first = false;
	201	}
	202
	203	if (status != 0 \|\| !cs_change)
	204	spi_xcomm_chipselect(spi_xcomm, spi, false);
	205
	206	msg->status = status;
	207	spi_finalize_current_message(master);
	208
	209	return status;
	210	}
	211
	212	static int spi_xcomm_setup(struct spi_device *spi)
	213	{
	214	if (spi->bits_per_word != 8)
	215	return -EINVAL;
	216
	217	return 0;
	218	}
	219
	220	static int __devinit spi_xcomm_probe(struct i2c_client *i2c,
	221	const struct i2c_device_id *id)
	222	{
	223	struct spi_xcomm *spi_xcomm;
	224	struct spi_master *master;
	225	int ret;
	226
	227	master = spi_alloc_master(&i2c->dev, sizeof(*spi_xcomm));
	228	if (!master)
	229	return -ENOMEM;
	230
	231	spi_xcomm = spi_master_get_devdata(master);
	232	spi_xcomm->i2c = i2c;
	233
	234	master->num_chipselect = 16;
	235	master->mode_bits = SPI_CPHA \| SPI_CPOL \| SPI_3WIRE;
	236	master->flags = SPI_MASTER_HALF_DUPLEX;
	237	master->setup = spi_xcomm_setup;
	238	master->transfer_one_message = spi_xcomm_transfer_one;
	239	master->dev.of_node = i2c->dev.of_node;
	240	i2c_set_clientdata(i2c, master);
	241
	242	ret = spi_register_master(master);
	243	if (ret < 0)
	244	spi_master_put(master);
	245
	246	return ret;
	247	}
	248
	249	static int __devexit spi_xcomm_remove(struct i2c_client *i2c)
	250	{
	251	struct spi_master *master = i2c_get_clientdata(i2c);
	252
	253	spi_unregister_master(master);
	254
	255	return 0;
	256	}
	257
	258	static const struct i2c_device_id spi_xcomm_ids[] = {
	259	{ "spi-xcomm" },
	260	{ },
	261	};
	262
	263	static struct i2c_driver spi_xcomm_driver = {
	264	.driver = {
	265	.name = "spi-xcomm",
	266	.owner = THIS_MODULE,
	267	},
	268	.id_table = spi_xcomm_ids,
	269	.probe = spi_xcomm_probe,
	270	.remove = __devexit_p(spi_xcomm_remove),
	271	};
	272	module_i2c_driver(spi_xcomm_driver);
	273
	274	MODULE_LICENSE("GPL");
	275	MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
	276	MODULE_DESCRIPTION("Analog Devices AD-FMCOMMS1-EBZ board I2C-SPI bridge driver");
	277

drivers/spi/spi.c

Diff comments View file @ 0082c16

include/linux/amba/pl022.h

Diff comments View file @ 0082c16

 /*
  * include/linux/amba/pl022.h
  *
  * Copyright (C) 2008-2009 ST-Ericsson AB
  * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
  *
  * Author: Linus Walleij <linus.walleij@stericsson.com>
  *
  * Initial version inspired by:
  *	linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
  * Initial adoption to PL022 by:
  *      Sachin Verma <sachin.verma@st.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
 #ifndef _SSP_PL022_H
 #define _SSP_PL022_H
 #include <linux/types.h>
 /**
  * whether SSP is in loopback mode or not
  */
 enum ssp_loopback {
 	LOOPBACK_DISABLED,
 	LOOPBACK_ENABLED
 };
 /**
  * enum ssp_interface - interfaces allowed for this SSP Controller
  * @SSP_INTERFACE_MOTOROLA_SPI: Motorola Interface
  * @SSP_INTERFACE_TI_SYNC_SERIAL: Texas Instrument Synchronous Serial
  * interface
  * @SSP_INTERFACE_NATIONAL_MICROWIRE: National Semiconductor Microwire
  * interface
  * @SSP_INTERFACE_UNIDIRECTIONAL: Unidirectional interface (STn8810
  * &STn8815 only)
  */
 enum ssp_interface {
 	SSP_INTERFACE_MOTOROLA_SPI,
 	SSP_INTERFACE_TI_SYNC_SERIAL,
 	SSP_INTERFACE_NATIONAL_MICROWIRE,
 	SSP_INTERFACE_UNIDIRECTIONAL
 };
 /**
  * enum ssp_hierarchy - whether SSP is configured as Master or Slave
  */
 enum ssp_hierarchy {
 	SSP_MASTER,
 	SSP_SLAVE
 };
 /**
  * enum ssp_clock_params - clock parameters, to set SSP clock at a
  * desired freq
  */
 struct ssp_clock_params {
 	u8 cpsdvsr; /* value from 2 to 254 (even only!) */
 	u8 scr;	    /* value from 0 to 255 */
 };
 /**
  * enum ssp_rx_endian - endianess of Rx FIFO Data
  * this feature is only available in ST versionf of PL022
  */
 enum ssp_rx_endian {
 	SSP_RX_MSB,
 	SSP_RX_LSB
 };
 /**
  * enum ssp_tx_endian - endianess of Tx FIFO Data
  */
 enum ssp_tx_endian {
 	SSP_TX_MSB,
 	SSP_TX_LSB
 };
 /**
  * enum ssp_data_size - number of bits in one data element
  */
 enum ssp_data_size {
 	SSP_DATA_BITS_4 = 0x03, SSP_DATA_BITS_5, SSP_DATA_BITS_6,
 	SSP_DATA_BITS_7, SSP_DATA_BITS_8, SSP_DATA_BITS_9,
 	SSP_DATA_BITS_10, SSP_DATA_BITS_11, SSP_DATA_BITS_12,
 	SSP_DATA_BITS_13, SSP_DATA_BITS_14, SSP_DATA_BITS_15,
 	SSP_DATA_BITS_16, SSP_DATA_BITS_17, SSP_DATA_BITS_18,
 	SSP_DATA_BITS_19, SSP_DATA_BITS_20, SSP_DATA_BITS_21,
 	SSP_DATA_BITS_22, SSP_DATA_BITS_23, SSP_DATA_BITS_24,
 	SSP_DATA_BITS_25, SSP_DATA_BITS_26, SSP_DATA_BITS_27,
 	SSP_DATA_BITS_28, SSP_DATA_BITS_29, SSP_DATA_BITS_30,
 	SSP_DATA_BITS_31, SSP_DATA_BITS_32
 };
 /**
  * enum ssp_mode - SSP mode of operation (Communication modes)
  */
 enum ssp_mode {
 	INTERRUPT_TRANSFER,
 	POLLING_TRANSFER,
 	DMA_TRANSFER
 };
 /**
  * enum ssp_rx_level_trig - receive FIFO watermark level which triggers
  * IT: Interrupt fires when _N_ or more elements in RX FIFO.
  */
 enum ssp_rx_level_trig {
 	SSP_RX_1_OR_MORE_ELEM,
 	SSP_RX_4_OR_MORE_ELEM,
 	SSP_RX_8_OR_MORE_ELEM,
 	SSP_RX_16_OR_MORE_ELEM,
 	SSP_RX_32_OR_MORE_ELEM
 };
 /**
  * Transmit FIFO watermark level which triggers (IT Interrupt fires
  * when _N_ or more empty locations in TX FIFO)
  */
 enum ssp_tx_level_trig {
 	SSP_TX_1_OR_MORE_EMPTY_LOC,
 	SSP_TX_4_OR_MORE_EMPTY_LOC,
 	SSP_TX_8_OR_MORE_EMPTY_LOC,
 	SSP_TX_16_OR_MORE_EMPTY_LOC,
 	SSP_TX_32_OR_MORE_EMPTY_LOC
 };
 /**
  * enum SPI Clock Phase - clock phase (Motorola SPI interface only)
  * @SSP_CLK_FIRST_EDGE: Receive data on first edge transition (actual direction depends on polarity)
  * @SSP_CLK_SECOND_EDGE: Receive data on second edge transition (actual direction depends on polarity)
  */
 enum ssp_spi_clk_phase {
 	SSP_CLK_FIRST_EDGE,
 	SSP_CLK_SECOND_EDGE
 };
 /**
  * enum SPI Clock Polarity - clock polarity (Motorola SPI interface only)
  * @SSP_CLK_POL_IDLE_LOW: Low inactive level
  * @SSP_CLK_POL_IDLE_HIGH: High inactive level
  */
 enum ssp_spi_clk_pol {
 	SSP_CLK_POL_IDLE_LOW,
 	SSP_CLK_POL_IDLE_HIGH
 };
 /**
  * Microwire Conrol Lengths Command size in microwire format
  */
 enum ssp_microwire_ctrl_len {
 	SSP_BITS_4 = 0x03, SSP_BITS_5, SSP_BITS_6,
 	SSP_BITS_7, SSP_BITS_8, SSP_BITS_9,
 	SSP_BITS_10, SSP_BITS_11, SSP_BITS_12,
 	SSP_BITS_13, SSP_BITS_14, SSP_BITS_15,
 	SSP_BITS_16, SSP_BITS_17, SSP_BITS_18,
 	SSP_BITS_19, SSP_BITS_20, SSP_BITS_21,
 	SSP_BITS_22, SSP_BITS_23, SSP_BITS_24,
 	SSP_BITS_25, SSP_BITS_26, SSP_BITS_27,
 	SSP_BITS_28, SSP_BITS_29, SSP_BITS_30,
 	SSP_BITS_31, SSP_BITS_32
 };
 /**
  * enum Microwire Wait State
  * @SSP_MWIRE_WAIT_ZERO: No wait state inserted after last command bit
  * @SSP_MWIRE_WAIT_ONE: One wait state inserted after last command bit
  */
 enum ssp_microwire_wait_state {
 	SSP_MWIRE_WAIT_ZERO,
 	SSP_MWIRE_WAIT_ONE
 };
 /**
  * enum ssp_duplex - whether Full/Half Duplex on microwire, only
  * available in the ST Micro variant.
  * @SSP_MICROWIRE_CHANNEL_FULL_DUPLEX: SSPTXD becomes bi-directional,
  *     SSPRXD not used
  * @SSP_MICROWIRE_CHANNEL_HALF_DUPLEX: SSPTXD is an output, SSPRXD is
  *     an input.
  */
 enum ssp_duplex {
 	SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
 	SSP_MICROWIRE_CHANNEL_HALF_DUPLEX
 };
 /**
  * enum ssp_clkdelay - an optional clock delay on the feedback clock
  * only available in the ST Micro PL023 variant.
  * @SSP_FEEDBACK_CLK_DELAY_NONE: no delay, the data coming in from the
  * slave is sampled directly
  * @SSP_FEEDBACK_CLK_DELAY_1T: the incoming slave data is sampled with
  * a delay of T-dt
  * @SSP_FEEDBACK_CLK_DELAY_2T: dito with a delay if 2T-dt
  * @SSP_FEEDBACK_CLK_DELAY_3T: dito with a delay if 3T-dt
  * @SSP_FEEDBACK_CLK_DELAY_4T: dito with a delay if 4T-dt
  * @SSP_FEEDBACK_CLK_DELAY_5T: dito with a delay if 5T-dt
  * @SSP_FEEDBACK_CLK_DELAY_6T: dito with a delay if 6T-dt
  * @SSP_FEEDBACK_CLK_DELAY_7T: dito with a delay if 7T-dt
  */
 enum ssp_clkdelay {
 	SSP_FEEDBACK_CLK_DELAY_NONE,
 	SSP_FEEDBACK_CLK_DELAY_1T,
 	SSP_FEEDBACK_CLK_DELAY_2T,
 	SSP_FEEDBACK_CLK_DELAY_3T,
 	SSP_FEEDBACK_CLK_DELAY_4T,
 	SSP_FEEDBACK_CLK_DELAY_5T,
 	SSP_FEEDBACK_CLK_DELAY_6T,
 	SSP_FEEDBACK_CLK_DELAY_7T
 };
 /**
  * CHIP select/deselect commands
  */
 enum ssp_chip_select {
 	SSP_CHIP_SELECT,
 	SSP_CHIP_DESELECT
 };
 struct dma_chan;
 /**
  * struct pl022_ssp_master - device.platform_data for SPI controller devices.
+ * @bus_id: identifier for this bus
  * @num_chipselect: chipselects are used to distinguish individual
  *     SPI slaves, and are numbered from zero to num_chipselects - 1.
  *     each slave has a chipselect signal, but it's common that not
  *     every chipselect is connected to a slave.
  * @enable_dma: if true enables DMA driven transfers.
  * @dma_rx_param: parameter to locate an RX DMA channel.
  * @dma_tx_param: parameter to locate a TX DMA channel.
  * @autosuspend_delay: delay in ms following transfer completion before the
  *     runtime power management system suspends the device. A setting of 0
  *     indicates no delay and the device will be suspended immediately.
  * @rt: indicates the controller should run the message pump with realtime
  *     priority to minimise the transfer latency on the bus.
  */
 struct pl022_ssp_controller {
 	u16 bus_id;
 	u8 num_chipselect;
 	u8 enable_dma:1;
 	bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
 	void *dma_rx_param;
 	void *dma_tx_param;
 	int autosuspend_delay;
 	bool rt;
 };
 /**
  * struct ssp_config_chip - spi_board_info.controller_data for SPI
  * slave devices, copied to spi_device.controller_data.
  *
- * @lbm: used for test purpose to internally connect RX and TX
  * @iface: Interface type(Motorola, TI, Microwire, Universal)
  * @hierarchy: sets whether interface is master or slave
  * @slave_tx_disable: SSPTXD is disconnected (in slave mode only)
  * @clk_freq: Tune freq parameters of SSP(when in master mode)
- * @endian_rx: Endianess of Data in Rx FIFO
- * @endian_tx: Endianess of Data in Tx FIFO
- * @data_size: Width of data element(4 to 32 bits)
  * @com_mode: communication mode: polling, Interrupt or DMA
  * @rx_lev_trig: Rx FIFO watermark level (for IT & DMA mode)
  * @tx_lev_trig: Tx FIFO watermark level (for IT & DMA mode)
- * @clk_phase: Motorola SPI interface Clock phase
- * @clk_pol: Motorola SPI interface Clock polarity
  * @ctrl_len: Microwire interface: Control length
  * @wait_state: Microwire interface: Wait state
  * @duplex: Microwire interface: Full/Half duplex
  * @clkdelay: on the PL023 variant, the delay in feeback clock cycles
  * before sampling the incoming line
  * @cs_control: function pointer to board-specific function to
  * assert/deassert I/O port to control HW generation of devices chip-select.
- * @dma_xfer_type: Type of DMA xfer (Mem-to-periph or Periph-to-Periph)
- * @dma_config: DMA configuration for SSP controller and peripheral
  */
 struct pl022_config_chip {
 	enum ssp_interface iface;
 	enum ssp_hierarchy hierarchy;
 	bool slave_tx_disable;
 	struct ssp_clock_params clk_freq;
 	enum ssp_mode com_mode;
 	enum ssp_rx_level_trig rx_lev_trig;
 	enum ssp_tx_level_trig tx_lev_trig;
 	enum ssp_microwire_ctrl_len ctrl_len;
 	enum ssp_microwire_wait_state wait_state;
 	enum ssp_duplex duplex;
 	enum ssp_clkdelay clkdelay;
 	void (*cs_control) (u32 control);
 };
 #endif /* _SSP_PL022_H */