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Commit 01e9607815755f748eb8722c3c3d8f308b7b4470

Authored by Adrian Knoth
Committed by Takashi Iwai
1 parent 88fabbfcc6
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

ALSA: hdspm - Fix DS/QS output channel mappings on RME MADI/MADIface 

Caused by two typos, no output channel mappings were assigned for
MADI/MADIface at double/quad speed.

The channel mapping is indeed identical to the single speed mapping, the
cards will simply use the first N channels.

Signed-off-by: Florian Faber <faber@faberman.de>
Signed-off-by: Fredrik Lingvall <fredrik.lingvall@gmail.com>
Signed-off-by: Adrian Knoth <adi@drcomp.erfurt.thur.de>
Signed-off-by: Takashi Iwai <tiwai@suse.de>

Showing 1 changed file with 2 additions and 2 deletions Inline Diff

sound/pci/rme9652/hdspm.c
Diff comments   View file @ 01e9607
1 /* 1 /*
2 * ALSA driver for RME Hammerfall DSP MADI audio interface(s) 2 * ALSA driver for RME Hammerfall DSP MADI audio interface(s)
3 * 3 *
4 * Copyright (c) 2003 Winfried Ritsch (IEM) 4 * Copyright (c) 2003 Winfried Ritsch (IEM)
5 * code based on hdsp.c Paul Davis 5 * code based on hdsp.c Paul Davis
6 * Marcus Andersson 6 * Marcus Andersson
7 * Thomas Charbonnel 7 * Thomas Charbonnel
8 * Modified 2006-06-01 for AES32 support by Remy Bruno 8 * Modified 2006-06-01 for AES32 support by Remy Bruno
9 * <remy.bruno@trinnov.com> 9 * <remy.bruno@trinnov.com>
10 * 10 *
11 * Modified 2009-04-13 for proper metering by Florian Faber 11 * Modified 2009-04-13 for proper metering by Florian Faber
12 * <faber@faberman.de> 12 * <faber@faberman.de>
13 * 13 *
14 * Modified 2009-04-14 for native float support by Florian Faber 14 * Modified 2009-04-14 for native float support by Florian Faber
15 * <faber@faberman.de> 15 * <faber@faberman.de>
16 * 16 *
17 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber 17 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber
18 * <faber@faberman.de> 18 * <faber@faberman.de>
19 * 19 *
20 * Modified 2009-04-30 added hw serial number support by Florian Faber 20 * Modified 2009-04-30 added hw serial number support by Florian Faber
21 * 21 *
22 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth 22 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
23 * 23 *
24 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth 24 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
25 * 25 *
26 * This program is free software; you can redistribute it and/or modify 26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License as published by 27 * it under the terms of the GNU General Public License as published by
28 * the Free Software Foundation; either version 2 of the License, or 28 * the Free Software Foundation; either version 2 of the License, or
29 * (at your option) any later version. 29 * (at your option) any later version.
30 * 30 *
31 * This program is distributed in the hope that it will be useful, 31 * This program is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of 32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34 * GNU General Public License for more details. 34 * GNU General Public License for more details.
35 * 35 *
36 * You should have received a copy of the GNU General Public License 36 * You should have received a copy of the GNU General Public License
37 * along with this program; if not, write to the Free Software 37 * along with this program; if not, write to the Free Software
38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
39 * 39 *
40 */ 40 */
41 #include <linux/init.h> 41 #include <linux/init.h>
42 #include <linux/delay.h> 42 #include <linux/delay.h>
43 #include <linux/interrupt.h> 43 #include <linux/interrupt.h>
44 #include <linux/moduleparam.h> 44 #include <linux/moduleparam.h>
45 #include <linux/slab.h> 45 #include <linux/slab.h>
46 #include <linux/pci.h> 46 #include <linux/pci.h>
47 #include <linux/math64.h> 47 #include <linux/math64.h>
48 #include <asm/io.h> 48 #include <asm/io.h>
49 49
50 #include <sound/core.h> 50 #include <sound/core.h>
51 #include <sound/control.h> 51 #include <sound/control.h>
52 #include <sound/pcm.h> 52 #include <sound/pcm.h>
53 #include <sound/pcm_params.h> 53 #include <sound/pcm_params.h>
54 #include <sound/info.h> 54 #include <sound/info.h>
55 #include <sound/asoundef.h> 55 #include <sound/asoundef.h>
56 #include <sound/rawmidi.h> 56 #include <sound/rawmidi.h>
57 #include <sound/hwdep.h> 57 #include <sound/hwdep.h>
58 #include <sound/initval.h> 58 #include <sound/initval.h>
59 59
60 #include <sound/hdspm.h> 60 #include <sound/hdspm.h>
61 61
62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
64 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */ 64 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
65 65
66 module_param_array(index, int, NULL, 0444); 66 module_param_array(index, int, NULL, 0444);
67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface."); 67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
68 68
69 module_param_array(id, charp, NULL, 0444); 69 module_param_array(id, charp, NULL, 0444);
70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface."); 70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
71 71
72 module_param_array(enable, bool, NULL, 0444); 72 module_param_array(enable, bool, NULL, 0444);
73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards."); 73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
74 74
75 75
76 MODULE_AUTHOR 76 MODULE_AUTHOR
77 ( 77 (
78 "Winfried Ritsch <ritsch_AT_iem.at>, " 78 "Winfried Ritsch <ritsch_AT_iem.at>, "
79 "Paul Davis <paul@linuxaudiosystems.com>, " 79 "Paul Davis <paul@linuxaudiosystems.com>, "
80 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, " 80 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
81 "Remy Bruno <remy.bruno@trinnov.com>, " 81 "Remy Bruno <remy.bruno@trinnov.com>, "
82 "Florian Faber <faberman@linuxproaudio.org>, " 82 "Florian Faber <faberman@linuxproaudio.org>, "
83 "Adrian Knoth <adi@drcomp.erfurt.thur.de>" 83 "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
84 ); 84 );
85 MODULE_DESCRIPTION("RME HDSPM"); 85 MODULE_DESCRIPTION("RME HDSPM");
86 MODULE_LICENSE("GPL"); 86 MODULE_LICENSE("GPL");
87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}"); 87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
88 88
89 /* --- Write registers. --- 89 /* --- Write registers. ---
90 These are defined as byte-offsets from the iobase value. */ 90 These are defined as byte-offsets from the iobase value. */
91 91
92 #define HDSPM_WR_SETTINGS 0 92 #define HDSPM_WR_SETTINGS 0
93 #define HDSPM_outputBufferAddress 32 93 #define HDSPM_outputBufferAddress 32
94 #define HDSPM_inputBufferAddress 36 94 #define HDSPM_inputBufferAddress 36
95 #define HDSPM_controlRegister 64 95 #define HDSPM_controlRegister 64
96 #define HDSPM_interruptConfirmation 96 96 #define HDSPM_interruptConfirmation 96
97 #define HDSPM_control2Reg 256 /* not in specs ???????? */ 97 #define HDSPM_control2Reg 256 /* not in specs ???????? */
98 #define HDSPM_freqReg 256 /* for AES32 */ 98 #define HDSPM_freqReg 256 /* for AES32 */
99 #define HDSPM_midiDataOut0 352 /* just believe in old code */ 99 #define HDSPM_midiDataOut0 352 /* just believe in old code */
100 #define HDSPM_midiDataOut1 356 100 #define HDSPM_midiDataOut1 356
101 #define HDSPM_eeprom_wr 384 /* for AES32 */ 101 #define HDSPM_eeprom_wr 384 /* for AES32 */
102 102
103 /* DMA enable for 64 channels, only Bit 0 is relevant */ 103 /* DMA enable for 64 channels, only Bit 0 is relevant */
104 #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */ 104 #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */
105 #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */ 105 #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */
106 106
107 /* 16 page addresses for each of the 64 channels DMA buffer in and out 107 /* 16 page addresses for each of the 64 channels DMA buffer in and out
108 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */ 108 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
109 #define HDSPM_pageAddressBufferOut 8192 109 #define HDSPM_pageAddressBufferOut 8192
110 #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4) 110 #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4)
111 111
112 #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */ 112 #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */
113 113
114 #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */ 114 #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */
115 115
116 /* --- Read registers. --- 116 /* --- Read registers. ---
117 These are defined as byte-offsets from the iobase value */ 117 These are defined as byte-offsets from the iobase value */
118 #define HDSPM_statusRegister 0 118 #define HDSPM_statusRegister 0
119 /*#define HDSPM_statusRegister2 96 */ 119 /*#define HDSPM_statusRegister2 96 */
120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at 120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
121 * offset 192, for AES32 *and* MADI 121 * offset 192, for AES32 *and* MADI
122 * => need to check that offset 192 is working on MADI */ 122 * => need to check that offset 192 is working on MADI */
123 #define HDSPM_statusRegister2 192 123 #define HDSPM_statusRegister2 192
124 #define HDSPM_timecodeRegister 128 124 #define HDSPM_timecodeRegister 128
125 125
126 /* AIO, RayDAT */ 126 /* AIO, RayDAT */
127 #define HDSPM_RD_STATUS_0 0 127 #define HDSPM_RD_STATUS_0 0
128 #define HDSPM_RD_STATUS_1 64 128 #define HDSPM_RD_STATUS_1 64
129 #define HDSPM_RD_STATUS_2 128 129 #define HDSPM_RD_STATUS_2 128
130 #define HDSPM_RD_STATUS_3 192 130 #define HDSPM_RD_STATUS_3 192
131 131
132 #define HDSPM_RD_TCO 256 132 #define HDSPM_RD_TCO 256
133 #define HDSPM_RD_PLL_FREQ 512 133 #define HDSPM_RD_PLL_FREQ 512
134 #define HDSPM_WR_TCO 128 134 #define HDSPM_WR_TCO 128
135 135
136 #define HDSPM_TCO1_TCO_lock 0x00000001 136 #define HDSPM_TCO1_TCO_lock 0x00000001
137 #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002 137 #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002
138 #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004 138 #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004
139 #define HDSPM_TCO1_LTC_Input_valid 0x00000008 139 #define HDSPM_TCO1_LTC_Input_valid 0x00000008
140 #define HDSPM_TCO1_WCK_Input_valid 0x00000010 140 #define HDSPM_TCO1_WCK_Input_valid 0x00000010
141 #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020 141 #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020
142 #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040 142 #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040
143 143
144 #define HDSPM_TCO1_set_TC 0x00000100 144 #define HDSPM_TCO1_set_TC 0x00000100
145 #define HDSPM_TCO1_set_drop_frame_flag 0x00000200 145 #define HDSPM_TCO1_set_drop_frame_flag 0x00000200
146 #define HDSPM_TCO1_LTC_Format_LSB 0x00000400 146 #define HDSPM_TCO1_LTC_Format_LSB 0x00000400
147 #define HDSPM_TCO1_LTC_Format_MSB 0x00000800 147 #define HDSPM_TCO1_LTC_Format_MSB 0x00000800
148 148
149 #define HDSPM_TCO2_TC_run 0x00010000 149 #define HDSPM_TCO2_TC_run 0x00010000
150 #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000 150 #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000
151 #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000 151 #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000
152 #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000 152 #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000
153 #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000 153 #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000
154 #define HDSPM_TCO2_set_jam_sync 0x00200000 154 #define HDSPM_TCO2_set_jam_sync 0x00200000
155 #define HDSPM_TCO2_set_flywheel 0x00400000 155 #define HDSPM_TCO2_set_flywheel 0x00400000
156 156
157 #define HDSPM_TCO2_set_01_4 0x01000000 157 #define HDSPM_TCO2_set_01_4 0x01000000
158 #define HDSPM_TCO2_set_pull_down 0x02000000 158 #define HDSPM_TCO2_set_pull_down 0x02000000
159 #define HDSPM_TCO2_set_pull_up 0x04000000 159 #define HDSPM_TCO2_set_pull_up 0x04000000
160 #define HDSPM_TCO2_set_freq 0x08000000 160 #define HDSPM_TCO2_set_freq 0x08000000
161 #define HDSPM_TCO2_set_term_75R 0x10000000 161 #define HDSPM_TCO2_set_term_75R 0x10000000
162 #define HDSPM_TCO2_set_input_LSB 0x20000000 162 #define HDSPM_TCO2_set_input_LSB 0x20000000
163 #define HDSPM_TCO2_set_input_MSB 0x40000000 163 #define HDSPM_TCO2_set_input_MSB 0x40000000
164 #define HDSPM_TCO2_set_freq_from_app 0x80000000 164 #define HDSPM_TCO2_set_freq_from_app 0x80000000
165 165
166 166
167 #define HDSPM_midiDataOut0 352 167 #define HDSPM_midiDataOut0 352
168 #define HDSPM_midiDataOut1 356 168 #define HDSPM_midiDataOut1 356
169 #define HDSPM_midiDataOut2 368 169 #define HDSPM_midiDataOut2 368
170 170
171 #define HDSPM_midiDataIn0 360 171 #define HDSPM_midiDataIn0 360
172 #define HDSPM_midiDataIn1 364 172 #define HDSPM_midiDataIn1 364
173 #define HDSPM_midiDataIn2 372 173 #define HDSPM_midiDataIn2 372
174 #define HDSPM_midiDataIn3 376 174 #define HDSPM_midiDataIn3 376
175 175
176 /* status is data bytes in MIDI-FIFO (0-128) */ 176 /* status is data bytes in MIDI-FIFO (0-128) */
177 #define HDSPM_midiStatusOut0 384 177 #define HDSPM_midiStatusOut0 384
178 #define HDSPM_midiStatusOut1 388 178 #define HDSPM_midiStatusOut1 388
179 #define HDSPM_midiStatusOut2 400 179 #define HDSPM_midiStatusOut2 400
180 180
181 #define HDSPM_midiStatusIn0 392 181 #define HDSPM_midiStatusIn0 392
182 #define HDSPM_midiStatusIn1 396 182 #define HDSPM_midiStatusIn1 396
183 #define HDSPM_midiStatusIn2 404 183 #define HDSPM_midiStatusIn2 404
184 #define HDSPM_midiStatusIn3 408 184 #define HDSPM_midiStatusIn3 408
185 185
186 186
187 /* the meters are regular i/o-mapped registers, but offset 187 /* the meters are regular i/o-mapped registers, but offset
188 considerably from the rest. the peak registers are reset 188 considerably from the rest. the peak registers are reset
189 when read; the least-significant 4 bits are full-scale counters; 189 when read; the least-significant 4 bits are full-scale counters;
190 the actual peak value is in the most-significant 24 bits. 190 the actual peak value is in the most-significant 24 bits.
191 */ 191 */
192 192
193 #define HDSPM_MADI_INPUT_PEAK 4096 193 #define HDSPM_MADI_INPUT_PEAK 4096
194 #define HDSPM_MADI_PLAYBACK_PEAK 4352 194 #define HDSPM_MADI_PLAYBACK_PEAK 4352
195 #define HDSPM_MADI_OUTPUT_PEAK 4608 195 #define HDSPM_MADI_OUTPUT_PEAK 4608
196 196
197 #define HDSPM_MADI_INPUT_RMS_L 6144 197 #define HDSPM_MADI_INPUT_RMS_L 6144
198 #define HDSPM_MADI_PLAYBACK_RMS_L 6400 198 #define HDSPM_MADI_PLAYBACK_RMS_L 6400
199 #define HDSPM_MADI_OUTPUT_RMS_L 6656 199 #define HDSPM_MADI_OUTPUT_RMS_L 6656
200 200
201 #define HDSPM_MADI_INPUT_RMS_H 7168 201 #define HDSPM_MADI_INPUT_RMS_H 7168
202 #define HDSPM_MADI_PLAYBACK_RMS_H 7424 202 #define HDSPM_MADI_PLAYBACK_RMS_H 7424
203 #define HDSPM_MADI_OUTPUT_RMS_H 7680 203 #define HDSPM_MADI_OUTPUT_RMS_H 7680
204 204
205 /* --- Control Register bits --------- */ 205 /* --- Control Register bits --------- */
206 #define HDSPM_Start (1<<0) /* start engine */ 206 #define HDSPM_Start (1<<0) /* start engine */
207 207
208 #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */ 208 #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */
209 #define HDSPM_Latency1 (1<<2) /* where n is defined */ 209 #define HDSPM_Latency1 (1<<2) /* where n is defined */
210 #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */ 210 #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */
211 211
212 #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */ 212 #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */
213 #define HDSPM_c0Master 0x1 /* Master clock bit in settings 213 #define HDSPM_c0Master 0x1 /* Master clock bit in settings
214 register [RayDAT, AIO] */ 214 register [RayDAT, AIO] */
215 215
216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */ 216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
217 217
218 #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */ 218 #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
219 #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */ 219 #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */
220 #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ 220 #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
221 #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */ 221 #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */
222 222
223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */ 223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
224 #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1, 224 #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1,
225 56channelMODE=0 */ /* MADI ONLY*/ 225 56channelMODE=0 */ /* MADI ONLY*/
226 #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */ 226 #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */
227 227
228 #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode, 228 #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode,
229 0=off, 1=on */ /* MADI ONLY */ 229 0=off, 1=on */ /* MADI ONLY */
230 #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */ 230 #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
231 231
232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax 232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
233 * -- MADI ONLY 233 * -- MADI ONLY
234 */ 234 */
235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */ 235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
236 236
237 #define HDSPM_SyncRef2 (1<<13) 237 #define HDSPM_SyncRef2 (1<<13)
238 #define HDSPM_SyncRef3 (1<<25) 238 #define HDSPM_SyncRef3 (1<<25)
239 239
240 #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */ 240 #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */
241 #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use 241 #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use
242 AES additional bits in 242 AES additional bits in
243 lower 5 Audiodatabits ??? */ 243 lower 5 Audiodatabits ??? */
244 #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */ 244 #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */
245 #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */ 245 #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
246 246
247 #define HDSPM_Midi0InterruptEnable 0x0400000 247 #define HDSPM_Midi0InterruptEnable 0x0400000
248 #define HDSPM_Midi1InterruptEnable 0x0800000 248 #define HDSPM_Midi1InterruptEnable 0x0800000
249 #define HDSPM_Midi2InterruptEnable 0x0200000 249 #define HDSPM_Midi2InterruptEnable 0x0200000
250 #define HDSPM_Midi3InterruptEnable 0x4000000 250 #define HDSPM_Midi3InterruptEnable 0x4000000
251 251
252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */ 252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
253 #define HDSPe_FLOAT_FORMAT 0x2000000 253 #define HDSPe_FLOAT_FORMAT 0x2000000
254 254
255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */ 255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */ 256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
257 #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */ 257 #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */
258 258
259 #define HDSPM_wclk_sel (1<<30) 259 #define HDSPM_wclk_sel (1<<30)
260 260
261 /* --- bit helper defines */ 261 /* --- bit helper defines */
262 #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2) 262 #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
263 #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\ 263 #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\
264 HDSPM_DoubleSpeed|HDSPM_QuadSpeed) 264 HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
265 #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1) 265 #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1)
266 #define HDSPM_InputOptical 0 266 #define HDSPM_InputOptical 0
267 #define HDSPM_InputCoaxial (HDSPM_InputSelect0) 267 #define HDSPM_InputCoaxial (HDSPM_InputSelect0)
268 #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\ 268 #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\
269 HDSPM_SyncRef2|HDSPM_SyncRef3) 269 HDSPM_SyncRef2|HDSPM_SyncRef3)
270 270
271 #define HDSPM_c0_SyncRef0 0x2 271 #define HDSPM_c0_SyncRef0 0x2
272 #define HDSPM_c0_SyncRef1 0x4 272 #define HDSPM_c0_SyncRef1 0x4
273 #define HDSPM_c0_SyncRef2 0x8 273 #define HDSPM_c0_SyncRef2 0x8
274 #define HDSPM_c0_SyncRef3 0x10 274 #define HDSPM_c0_SyncRef3 0x10
275 #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\ 275 #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
276 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3) 276 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
277 277
278 #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */ 278 #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */
279 #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */ 279 #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */
280 #define HDSPM_SYNC_FROM_TCO 2 280 #define HDSPM_SYNC_FROM_TCO 2
281 #define HDSPM_SYNC_FROM_SYNC_IN 3 281 #define HDSPM_SYNC_FROM_SYNC_IN 3
282 282
283 #define HDSPM_Frequency32KHz HDSPM_Frequency0 283 #define HDSPM_Frequency32KHz HDSPM_Frequency0
284 #define HDSPM_Frequency44_1KHz HDSPM_Frequency1 284 #define HDSPM_Frequency44_1KHz HDSPM_Frequency1
285 #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0) 285 #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0)
286 #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0) 286 #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0)
287 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1) 287 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
288 #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\ 288 #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
289 HDSPM_Frequency0) 289 HDSPM_Frequency0)
290 #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0) 290 #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0)
291 #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1) 291 #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1)
292 #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\ 292 #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\
293 HDSPM_Frequency0) 293 HDSPM_Frequency0)
294 294
295 295
296 /* Synccheck Status */ 296 /* Synccheck Status */
297 #define HDSPM_SYNC_CHECK_NO_LOCK 0 297 #define HDSPM_SYNC_CHECK_NO_LOCK 0
298 #define HDSPM_SYNC_CHECK_LOCK 1 298 #define HDSPM_SYNC_CHECK_LOCK 1
299 #define HDSPM_SYNC_CHECK_SYNC 2 299 #define HDSPM_SYNC_CHECK_SYNC 2
300 300
301 /* AutoSync References - used by "autosync_ref" control switch */ 301 /* AutoSync References - used by "autosync_ref" control switch */
302 #define HDSPM_AUTOSYNC_FROM_WORD 0 302 #define HDSPM_AUTOSYNC_FROM_WORD 0
303 #define HDSPM_AUTOSYNC_FROM_MADI 1 303 #define HDSPM_AUTOSYNC_FROM_MADI 1
304 #define HDSPM_AUTOSYNC_FROM_TCO 2 304 #define HDSPM_AUTOSYNC_FROM_TCO 2
305 #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3 305 #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3
306 #define HDSPM_AUTOSYNC_FROM_NONE 4 306 #define HDSPM_AUTOSYNC_FROM_NONE 4
307 307
308 /* Possible sources of MADI input */ 308 /* Possible sources of MADI input */
309 #define HDSPM_OPTICAL 0 /* optical */ 309 #define HDSPM_OPTICAL 0 /* optical */
310 #define HDSPM_COAXIAL 1 /* BNC */ 310 #define HDSPM_COAXIAL 1 /* BNC */
311 311
312 #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask) 312 #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask)
313 #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1)) 313 #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1))
314 314
315 #define hdspm_encode_in(x) (((x)&0x3)<<14) 315 #define hdspm_encode_in(x) (((x)&0x3)<<14)
316 #define hdspm_decode_in(x) (((x)>>14)&0x3) 316 #define hdspm_decode_in(x) (((x)>>14)&0x3)
317 317
318 /* --- control2 register bits --- */ 318 /* --- control2 register bits --- */
319 #define HDSPM_TMS (1<<0) 319 #define HDSPM_TMS (1<<0)
320 #define HDSPM_TCK (1<<1) 320 #define HDSPM_TCK (1<<1)
321 #define HDSPM_TDI (1<<2) 321 #define HDSPM_TDI (1<<2)
322 #define HDSPM_JTAG (1<<3) 322 #define HDSPM_JTAG (1<<3)
323 #define HDSPM_PWDN (1<<4) 323 #define HDSPM_PWDN (1<<4)
324 #define HDSPM_PROGRAM (1<<5) 324 #define HDSPM_PROGRAM (1<<5)
325 #define HDSPM_CONFIG_MODE_0 (1<<6) 325 #define HDSPM_CONFIG_MODE_0 (1<<6)
326 #define HDSPM_CONFIG_MODE_1 (1<<7) 326 #define HDSPM_CONFIG_MODE_1 (1<<7)
327 /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/ 327 /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/
328 #define HDSPM_BIGENDIAN_MODE (1<<9) 328 #define HDSPM_BIGENDIAN_MODE (1<<9)
329 #define HDSPM_RD_MULTIPLE (1<<10) 329 #define HDSPM_RD_MULTIPLE (1<<10)
330 330
331 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and 331 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
332 that do not conflict with specific bits for AES32 seem to be valid also 332 that do not conflict with specific bits for AES32 seem to be valid also
333 for the AES32 333 for the AES32
334 */ 334 */
335 #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */ 335 #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */
336 #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */ 336 #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
337 #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1 337 #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1
338 * (like inp0) 338 * (like inp0)
339 */ 339 */
340 340
341 #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */ 341 #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */
342 #define HDSPM_madiSync (1<<18) /* MADI is in sync */ 342 #define HDSPM_madiSync (1<<18) /* MADI is in sync */
343 343
344 #define HDSPM_tcoLock 0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */ 344 #define HDSPM_tcoLock 0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */
345 #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status */ 345 #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status */
346 346
347 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */ 347 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */
348 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */ 348 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */
349 349
350 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ 350 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
351 /* since 64byte accurate, last 6 bits are not used */ 351 /* since 64byte accurate, last 6 bits are not used */
352 352
353 353
354 354
355 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */ 355 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
356 356
357 #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */ 357 #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */
358 #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */ 358 #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */
359 #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */ 359 #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */
360 #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */ 360 #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */
361 361
362 #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with 362 #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with
363 * Interrupt 363 * Interrupt
364 */ 364 */
365 #define HDSPM_tco_detect 0x08000000 365 #define HDSPM_tco_detect 0x08000000
366 #define HDSPM_tco_lock 0x20000000 366 #define HDSPM_tco_lock 0x20000000
367 367
368 #define HDSPM_s2_tco_detect 0x00000040 368 #define HDSPM_s2_tco_detect 0x00000040
369 #define HDSPM_s2_AEBO_D 0x00000080 369 #define HDSPM_s2_AEBO_D 0x00000080
370 #define HDSPM_s2_AEBI_D 0x00000100 370 #define HDSPM_s2_AEBI_D 0x00000100
371 371
372 372
373 #define HDSPM_midi0IRQPending 0x40000000 373 #define HDSPM_midi0IRQPending 0x40000000
374 #define HDSPM_midi1IRQPending 0x80000000 374 #define HDSPM_midi1IRQPending 0x80000000
375 #define HDSPM_midi2IRQPending 0x20000000 375 #define HDSPM_midi2IRQPending 0x20000000
376 #define HDSPM_midi2IRQPendingAES 0x00000020 376 #define HDSPM_midi2IRQPendingAES 0x00000020
377 #define HDSPM_midi3IRQPending 0x00200000 377 #define HDSPM_midi3IRQPending 0x00200000
378 378
379 /* --- status bit helpers */ 379 /* --- status bit helpers */
380 #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\ 380 #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\
381 HDSPM_madiFreq2|HDSPM_madiFreq3) 381 HDSPM_madiFreq2|HDSPM_madiFreq3)
382 #define HDSPM_madiFreq32 (HDSPM_madiFreq0) 382 #define HDSPM_madiFreq32 (HDSPM_madiFreq0)
383 #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1) 383 #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1)
384 #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1) 384 #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1)
385 #define HDSPM_madiFreq64 (HDSPM_madiFreq2) 385 #define HDSPM_madiFreq64 (HDSPM_madiFreq2)
386 #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2) 386 #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2)
387 #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2) 387 #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2)
388 #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2) 388 #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
389 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3) 389 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
390 #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0) 390 #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0)
391 391
392 /* Status2 Register bits */ /* MADI ONLY */ 392 /* Status2 Register bits */ /* MADI ONLY */
393 393
394 #define HDSPM_version0 (1<<0) /* not realy defined but I guess */ 394 #define HDSPM_version0 (1<<0) /* not realy defined but I guess */
395 #define HDSPM_version1 (1<<1) /* in former cards it was ??? */ 395 #define HDSPM_version1 (1<<1) /* in former cards it was ??? */
396 #define HDSPM_version2 (1<<2) 396 #define HDSPM_version2 (1<<2)
397 397
398 #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */ 398 #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */
399 #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */ 399 #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */
400 400
401 #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */ 401 #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */
402 #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */ 402 #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */
403 #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, */ 403 #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, */
404 /* missing Bit for 111=128, 1000=176.4, 1001=192 */ 404 /* missing Bit for 111=128, 1000=176.4, 1001=192 */
405 405
406 #define HDSPM_SyncRef0 0x10000 /* Sync Reference */ 406 #define HDSPM_SyncRef0 0x10000 /* Sync Reference */
407 #define HDSPM_SyncRef1 0x20000 407 #define HDSPM_SyncRef1 0x20000
408 408
409 #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */ 409 #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */
410 #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */ 410 #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */
411 #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */ 411 #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */
412 412
413 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync) 413 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
414 414
415 #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2) 415 #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
416 #define HDSPM_wcFreq32 (HDSPM_wc_freq0) 416 #define HDSPM_wcFreq32 (HDSPM_wc_freq0)
417 #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1) 417 #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1)
418 #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1) 418 #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1)
419 #define HDSPM_wcFreq64 (HDSPM_wc_freq2) 419 #define HDSPM_wcFreq64 (HDSPM_wc_freq2)
420 #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2) 420 #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2)
421 #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2) 421 #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2)
422 422
423 #define HDSPM_status1_F_0 0x0400000 423 #define HDSPM_status1_F_0 0x0400000
424 #define HDSPM_status1_F_1 0x0800000 424 #define HDSPM_status1_F_1 0x0800000
425 #define HDSPM_status1_F_2 0x1000000 425 #define HDSPM_status1_F_2 0x1000000
426 #define HDSPM_status1_F_3 0x2000000 426 #define HDSPM_status1_F_3 0x2000000
427 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3) 427 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
428 428
429 429
430 #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 430 #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
431 HDSPM_SelSyncRef2) 431 HDSPM_SelSyncRef2)
432 #define HDSPM_SelSyncRef_WORD 0 432 #define HDSPM_SelSyncRef_WORD 0
433 #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0) 433 #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0)
434 #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1) 434 #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1)
435 #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1) 435 #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
436 #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 436 #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
437 HDSPM_SelSyncRef2) 437 HDSPM_SelSyncRef2)
438 438
439 /* 439 /*
440 For AES32, bits for status, status2 and timecode are different 440 For AES32, bits for status, status2 and timecode are different
441 */ 441 */
442 /* status */ 442 /* status */
443 #define HDSPM_AES32_wcLock 0x0200000 443 #define HDSPM_AES32_wcLock 0x0200000
444 #define HDSPM_AES32_wcFreq_bit 22 444 #define HDSPM_AES32_wcFreq_bit 22
445 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function 445 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
446 HDSPM_bit2freq */ 446 HDSPM_bit2freq */
447 #define HDSPM_AES32_syncref_bit 16 447 #define HDSPM_AES32_syncref_bit 16
448 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */ 448 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
449 449
450 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0 450 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
451 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1 451 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
452 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2 452 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
453 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3 453 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
454 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4 454 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
455 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5 455 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
456 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6 456 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
457 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7 457 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
458 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8 458 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
459 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9 459 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9
460 460
461 /* status2 */ 461 /* status2 */
462 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */ 462 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
463 #define HDSPM_LockAES 0x80 463 #define HDSPM_LockAES 0x80
464 #define HDSPM_LockAES1 0x80 464 #define HDSPM_LockAES1 0x80
465 #define HDSPM_LockAES2 0x40 465 #define HDSPM_LockAES2 0x40
466 #define HDSPM_LockAES3 0x20 466 #define HDSPM_LockAES3 0x20
467 #define HDSPM_LockAES4 0x10 467 #define HDSPM_LockAES4 0x10
468 #define HDSPM_LockAES5 0x8 468 #define HDSPM_LockAES5 0x8
469 #define HDSPM_LockAES6 0x4 469 #define HDSPM_LockAES6 0x4
470 #define HDSPM_LockAES7 0x2 470 #define HDSPM_LockAES7 0x2
471 #define HDSPM_LockAES8 0x1 471 #define HDSPM_LockAES8 0x1
472 /* 472 /*
473 Timecode 473 Timecode
474 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on 474 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
475 AES i+1 475 AES i+1
476 bits 3210 476 bits 3210
477 0001 32kHz 477 0001 32kHz
478 0010 44.1kHz 478 0010 44.1kHz
479 0011 48kHz 479 0011 48kHz
480 0100 64kHz 480 0100 64kHz
481 0101 88.2kHz 481 0101 88.2kHz
482 0110 96kHz 482 0110 96kHz
483 0111 128kHz 483 0111 128kHz
484 1000 176.4kHz 484 1000 176.4kHz
485 1001 192kHz 485 1001 192kHz
486 NB: Timecode register doesn't seem to work on AES32 card revision 230 486 NB: Timecode register doesn't seem to work on AES32 card revision 230
487 */ 487 */
488 488
489 /* Mixer Values */ 489 /* Mixer Values */
490 #define UNITY_GAIN 32768 /* = 65536/2 */ 490 #define UNITY_GAIN 32768 /* = 65536/2 */
491 #define MINUS_INFINITY_GAIN 0 491 #define MINUS_INFINITY_GAIN 0
492 492
493 /* Number of channels for different Speed Modes */ 493 /* Number of channels for different Speed Modes */
494 #define MADI_SS_CHANNELS 64 494 #define MADI_SS_CHANNELS 64
495 #define MADI_DS_CHANNELS 32 495 #define MADI_DS_CHANNELS 32
496 #define MADI_QS_CHANNELS 16 496 #define MADI_QS_CHANNELS 16
497 497
498 #define RAYDAT_SS_CHANNELS 36 498 #define RAYDAT_SS_CHANNELS 36
499 #define RAYDAT_DS_CHANNELS 20 499 #define RAYDAT_DS_CHANNELS 20
500 #define RAYDAT_QS_CHANNELS 12 500 #define RAYDAT_QS_CHANNELS 12
501 501
502 #define AIO_IN_SS_CHANNELS 14 502 #define AIO_IN_SS_CHANNELS 14
503 #define AIO_IN_DS_CHANNELS 10 503 #define AIO_IN_DS_CHANNELS 10
504 #define AIO_IN_QS_CHANNELS 8 504 #define AIO_IN_QS_CHANNELS 8
505 #define AIO_OUT_SS_CHANNELS 16 505 #define AIO_OUT_SS_CHANNELS 16
506 #define AIO_OUT_DS_CHANNELS 12 506 #define AIO_OUT_DS_CHANNELS 12
507 #define AIO_OUT_QS_CHANNELS 10 507 #define AIO_OUT_QS_CHANNELS 10
508 508
509 /* the size of a substream (1 mono data stream) */ 509 /* the size of a substream (1 mono data stream) */
510 #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024) 510 #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024)
511 #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES) 511 #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
512 512
513 /* the size of the area we need to allocate for DMA transfers. the 513 /* the size of the area we need to allocate for DMA transfers. the
514 size is the same regardless of the number of channels, and 514 size is the same regardless of the number of channels, and
515 also the latency to use. 515 also the latency to use.
516 for one direction !!! 516 for one direction !!!
517 */ 517 */
518 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES) 518 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
519 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024) 519 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
520 520
521 /* revisions >= 230 indicate AES32 card */ 521 /* revisions >= 230 indicate AES32 card */
522 #define HDSPM_MADI_REV 210 522 #define HDSPM_MADI_REV 210
523 #define HDSPM_RAYDAT_REV 211 523 #define HDSPM_RAYDAT_REV 211
524 #define HDSPM_AIO_REV 212 524 #define HDSPM_AIO_REV 212
525 #define HDSPM_MADIFACE_REV 213 525 #define HDSPM_MADIFACE_REV 213
526 #define HDSPM_AES_REV 240 526 #define HDSPM_AES_REV 240
527 527
528 /* speed factor modes */ 528 /* speed factor modes */
529 #define HDSPM_SPEED_SINGLE 0 529 #define HDSPM_SPEED_SINGLE 0
530 #define HDSPM_SPEED_DOUBLE 1 530 #define HDSPM_SPEED_DOUBLE 1
531 #define HDSPM_SPEED_QUAD 2 531 #define HDSPM_SPEED_QUAD 2
532 532
533 /* names for speed modes */ 533 /* names for speed modes */
534 static char *hdspm_speed_names[] = { "single", "double", "quad" }; 534 static char *hdspm_speed_names[] = { "single", "double", "quad" };
535 535
536 static char *texts_autosync_aes_tco[] = { "Word Clock", 536 static char *texts_autosync_aes_tco[] = { "Word Clock",
537 "AES1", "AES2", "AES3", "AES4", 537 "AES1", "AES2", "AES3", "AES4",
538 "AES5", "AES6", "AES7", "AES8", 538 "AES5", "AES6", "AES7", "AES8",
539 "TCO" }; 539 "TCO" };
540 static char *texts_autosync_aes[] = { "Word Clock", 540 static char *texts_autosync_aes[] = { "Word Clock",
541 "AES1", "AES2", "AES3", "AES4", 541 "AES1", "AES2", "AES3", "AES4",
542 "AES5", "AES6", "AES7", "AES8" }; 542 "AES5", "AES6", "AES7", "AES8" };
543 static char *texts_autosync_madi_tco[] = { "Word Clock", 543 static char *texts_autosync_madi_tco[] = { "Word Clock",
544 "MADI", "TCO", "Sync In" }; 544 "MADI", "TCO", "Sync In" };
545 static char *texts_autosync_madi[] = { "Word Clock", 545 static char *texts_autosync_madi[] = { "Word Clock",
546 "MADI", "Sync In" }; 546 "MADI", "Sync In" };
547 547
548 static char *texts_autosync_raydat_tco[] = { 548 static char *texts_autosync_raydat_tco[] = {
549 "Word Clock", 549 "Word Clock",
550 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 550 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
551 "AES", "SPDIF", "TCO", "Sync In" 551 "AES", "SPDIF", "TCO", "Sync In"
552 }; 552 };
553 static char *texts_autosync_raydat[] = { 553 static char *texts_autosync_raydat[] = {
554 "Word Clock", 554 "Word Clock",
555 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 555 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
556 "AES", "SPDIF", "Sync In" 556 "AES", "SPDIF", "Sync In"
557 }; 557 };
558 static char *texts_autosync_aio_tco[] = { 558 static char *texts_autosync_aio_tco[] = {
559 "Word Clock", 559 "Word Clock",
560 "ADAT", "AES", "SPDIF", "TCO", "Sync In" 560 "ADAT", "AES", "SPDIF", "TCO", "Sync In"
561 }; 561 };
562 static char *texts_autosync_aio[] = { "Word Clock", 562 static char *texts_autosync_aio[] = { "Word Clock",
563 "ADAT", "AES", "SPDIF", "Sync In" }; 563 "ADAT", "AES", "SPDIF", "Sync In" };
564 564
565 static char *texts_freq[] = { 565 static char *texts_freq[] = {
566 "No Lock", 566 "No Lock",
567 "32 kHz", 567 "32 kHz",
568 "44.1 kHz", 568 "44.1 kHz",
569 "48 kHz", 569 "48 kHz",
570 "64 kHz", 570 "64 kHz",
571 "88.2 kHz", 571 "88.2 kHz",
572 "96 kHz", 572 "96 kHz",
573 "128 kHz", 573 "128 kHz",
574 "176.4 kHz", 574 "176.4 kHz",
575 "192 kHz" 575 "192 kHz"
576 }; 576 };
577 577
578 static char *texts_ports_madi[] = { 578 static char *texts_ports_madi[] = {
579 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6", 579 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
580 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12", 580 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
581 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18", 581 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
582 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24", 582 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
583 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30", 583 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
584 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36", 584 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
585 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42", 585 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
586 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48", 586 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
587 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54", 587 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
588 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60", 588 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
589 "MADI.61", "MADI.62", "MADI.63", "MADI.64", 589 "MADI.61", "MADI.62", "MADI.63", "MADI.64",
590 }; 590 };
591 591
592 592
593 static char *texts_ports_raydat_ss[] = { 593 static char *texts_ports_raydat_ss[] = {
594 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6", 594 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
595 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 595 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
596 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2", 596 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
597 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8", 597 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
598 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6", 598 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
599 "ADAT4.7", "ADAT4.8", 599 "ADAT4.7", "ADAT4.8",
600 "AES.L", "AES.R", 600 "AES.L", "AES.R",
601 "SPDIF.L", "SPDIF.R" 601 "SPDIF.L", "SPDIF.R"
602 }; 602 };
603 603
604 static char *texts_ports_raydat_ds[] = { 604 static char *texts_ports_raydat_ds[] = {
605 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", 605 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
606 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 606 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
607 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4", 607 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
608 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", 608 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
609 "AES.L", "AES.R", 609 "AES.L", "AES.R",
610 "SPDIF.L", "SPDIF.R" 610 "SPDIF.L", "SPDIF.R"
611 }; 611 };
612 612
613 static char *texts_ports_raydat_qs[] = { 613 static char *texts_ports_raydat_qs[] = {
614 "ADAT1.1", "ADAT1.2", 614 "ADAT1.1", "ADAT1.2",
615 "ADAT2.1", "ADAT2.2", 615 "ADAT2.1", "ADAT2.2",
616 "ADAT3.1", "ADAT3.2", 616 "ADAT3.1", "ADAT3.2",
617 "ADAT4.1", "ADAT4.2", 617 "ADAT4.1", "ADAT4.2",
618 "AES.L", "AES.R", 618 "AES.L", "AES.R",
619 "SPDIF.L", "SPDIF.R" 619 "SPDIF.L", "SPDIF.R"
620 }; 620 };
621 621
622 622
623 static char *texts_ports_aio_in_ss[] = { 623 static char *texts_ports_aio_in_ss[] = {
624 "Analogue.L", "Analogue.R", 624 "Analogue.L", "Analogue.R",
625 "AES.L", "AES.R", 625 "AES.L", "AES.R",
626 "SPDIF.L", "SPDIF.R", 626 "SPDIF.L", "SPDIF.R",
627 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 627 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
628 "ADAT.7", "ADAT.8" 628 "ADAT.7", "ADAT.8"
629 }; 629 };
630 630
631 static char *texts_ports_aio_out_ss[] = { 631 static char *texts_ports_aio_out_ss[] = {
632 "Analogue.L", "Analogue.R", 632 "Analogue.L", "Analogue.R",
633 "AES.L", "AES.R", 633 "AES.L", "AES.R",
634 "SPDIF.L", "SPDIF.R", 634 "SPDIF.L", "SPDIF.R",
635 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 635 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
636 "ADAT.7", "ADAT.8", 636 "ADAT.7", "ADAT.8",
637 "Phone.L", "Phone.R" 637 "Phone.L", "Phone.R"
638 }; 638 };
639 639
640 static char *texts_ports_aio_in_ds[] = { 640 static char *texts_ports_aio_in_ds[] = {
641 "Analogue.L", "Analogue.R", 641 "Analogue.L", "Analogue.R",
642 "AES.L", "AES.R", 642 "AES.L", "AES.R",
643 "SPDIF.L", "SPDIF.R", 643 "SPDIF.L", "SPDIF.R",
644 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4" 644 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
645 }; 645 };
646 646
647 static char *texts_ports_aio_out_ds[] = { 647 static char *texts_ports_aio_out_ds[] = {
648 "Analogue.L", "Analogue.R", 648 "Analogue.L", "Analogue.R",
649 "AES.L", "AES.R", 649 "AES.L", "AES.R",
650 "SPDIF.L", "SPDIF.R", 650 "SPDIF.L", "SPDIF.R",
651 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 651 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
652 "Phone.L", "Phone.R" 652 "Phone.L", "Phone.R"
653 }; 653 };
654 654
655 static char *texts_ports_aio_in_qs[] = { 655 static char *texts_ports_aio_in_qs[] = {
656 "Analogue.L", "Analogue.R", 656 "Analogue.L", "Analogue.R",
657 "AES.L", "AES.R", 657 "AES.L", "AES.R",
658 "SPDIF.L", "SPDIF.R", 658 "SPDIF.L", "SPDIF.R",
659 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4" 659 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
660 }; 660 };
661 661
662 static char *texts_ports_aio_out_qs[] = { 662 static char *texts_ports_aio_out_qs[] = {
663 "Analogue.L", "Analogue.R", 663 "Analogue.L", "Analogue.R",
664 "AES.L", "AES.R", 664 "AES.L", "AES.R",
665 "SPDIF.L", "SPDIF.R", 665 "SPDIF.L", "SPDIF.R",
666 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 666 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
667 "Phone.L", "Phone.R" 667 "Phone.L", "Phone.R"
668 }; 668 };
669 669
670 static char *texts_ports_aes32[] = { 670 static char *texts_ports_aes32[] = {
671 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7", 671 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
672 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14", 672 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
673 "AES.15", "AES.16" 673 "AES.15", "AES.16"
674 }; 674 };
675 675
676 /* These tables map the ALSA channels 1..N to the channels that we 676 /* These tables map the ALSA channels 1..N to the channels that we
677 need to use in order to find the relevant channel buffer. RME 677 need to use in order to find the relevant channel buffer. RME
678 refers to this kind of mapping as between "the ADAT channel and 678 refers to this kind of mapping as between "the ADAT channel and
679 the DMA channel." We index it using the logical audio channel, 679 the DMA channel." We index it using the logical audio channel,
680 and the value is the DMA channel (i.e. channel buffer number) 680 and the value is the DMA channel (i.e. channel buffer number)
681 where the data for that channel can be read/written from/to. 681 where the data for that channel can be read/written from/to.
682 */ 682 */
683 683
684 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = { 684 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
685 0, 1, 2, 3, 4, 5, 6, 7, 685 0, 1, 2, 3, 4, 5, 6, 7,
686 8, 9, 10, 11, 12, 13, 14, 15, 686 8, 9, 10, 11, 12, 13, 14, 15,
687 16, 17, 18, 19, 20, 21, 22, 23, 687 16, 17, 18, 19, 20, 21, 22, 23,
688 24, 25, 26, 27, 28, 29, 30, 31, 688 24, 25, 26, 27, 28, 29, 30, 31,
689 32, 33, 34, 35, 36, 37, 38, 39, 689 32, 33, 34, 35, 36, 37, 38, 39,
690 40, 41, 42, 43, 44, 45, 46, 47, 690 40, 41, 42, 43, 44, 45, 46, 47,
691 48, 49, 50, 51, 52, 53, 54, 55, 691 48, 49, 50, 51, 52, 53, 54, 55,
692 56, 57, 58, 59, 60, 61, 62, 63 692 56, 57, 58, 59, 60, 61, 62, 63
693 }; 693 };
694 694
695 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = { 695 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
696 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */ 696 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */
697 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */ 697 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
698 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */ 698 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
699 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */ 699 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
700 0, 1, /* AES */ 700 0, 1, /* AES */
701 2, 3, /* SPDIF */ 701 2, 3, /* SPDIF */
702 -1, -1, -1, -1, 702 -1, -1, -1, -1,
703 -1, -1, -1, -1, -1, -1, -1, -1, 703 -1, -1, -1, -1, -1, -1, -1, -1,
704 -1, -1, -1, -1, -1, -1, -1, -1, 704 -1, -1, -1, -1, -1, -1, -1, -1,
705 -1, -1, -1, -1, -1, -1, -1, -1, 705 -1, -1, -1, -1, -1, -1, -1, -1,
706 }; 706 };
707 707
708 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = { 708 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
709 4, 5, 6, 7, /* ADAT 1 */ 709 4, 5, 6, 7, /* ADAT 1 */
710 8, 9, 10, 11, /* ADAT 2 */ 710 8, 9, 10, 11, /* ADAT 2 */
711 12, 13, 14, 15, /* ADAT 3 */ 711 12, 13, 14, 15, /* ADAT 3 */
712 16, 17, 18, 19, /* ADAT 4 */ 712 16, 17, 18, 19, /* ADAT 4 */
713 0, 1, /* AES */ 713 0, 1, /* AES */
714 2, 3, /* SPDIF */ 714 2, 3, /* SPDIF */
715 -1, -1, -1, -1, 715 -1, -1, -1, -1,
716 -1, -1, -1, -1, -1, -1, -1, -1, 716 -1, -1, -1, -1, -1, -1, -1, -1,
717 -1, -1, -1, -1, -1, -1, -1, -1, 717 -1, -1, -1, -1, -1, -1, -1, -1,
718 -1, -1, -1, -1, -1, -1, -1, -1, 718 -1, -1, -1, -1, -1, -1, -1, -1,
719 -1, -1, -1, -1, -1, -1, -1, -1, 719 -1, -1, -1, -1, -1, -1, -1, -1,
720 -1, -1, -1, -1, -1, -1, -1, -1, 720 -1, -1, -1, -1, -1, -1, -1, -1,
721 }; 721 };
722 722
723 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = { 723 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
724 4, 5, /* ADAT 1 */ 724 4, 5, /* ADAT 1 */
725 6, 7, /* ADAT 2 */ 725 6, 7, /* ADAT 2 */
726 8, 9, /* ADAT 3 */ 726 8, 9, /* ADAT 3 */
727 10, 11, /* ADAT 4 */ 727 10, 11, /* ADAT 4 */
728 0, 1, /* AES */ 728 0, 1, /* AES */
729 2, 3, /* SPDIF */ 729 2, 3, /* SPDIF */
730 -1, -1, -1, -1, 730 -1, -1, -1, -1,
731 -1, -1, -1, -1, -1, -1, -1, -1, 731 -1, -1, -1, -1, -1, -1, -1, -1,
732 -1, -1, -1, -1, -1, -1, -1, -1, 732 -1, -1, -1, -1, -1, -1, -1, -1,
733 -1, -1, -1, -1, -1, -1, -1, -1, 733 -1, -1, -1, -1, -1, -1, -1, -1,
734 -1, -1, -1, -1, -1, -1, -1, -1, 734 -1, -1, -1, -1, -1, -1, -1, -1,
735 -1, -1, -1, -1, -1, -1, -1, -1, 735 -1, -1, -1, -1, -1, -1, -1, -1,
736 -1, -1, -1, -1, -1, -1, -1, -1, 736 -1, -1, -1, -1, -1, -1, -1, -1,
737 }; 737 };
738 738
739 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = { 739 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
740 0, 1, /* line in */ 740 0, 1, /* line in */
741 8, 9, /* aes in, */ 741 8, 9, /* aes in, */
742 10, 11, /* spdif in */ 742 10, 11, /* spdif in */
743 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */ 743 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
744 -1, -1, 744 -1, -1,
745 -1, -1, -1, -1, -1, -1, -1, -1, 745 -1, -1, -1, -1, -1, -1, -1, -1,
746 -1, -1, -1, -1, -1, -1, -1, -1, 746 -1, -1, -1, -1, -1, -1, -1, -1,
747 -1, -1, -1, -1, -1, -1, -1, -1, 747 -1, -1, -1, -1, -1, -1, -1, -1,
748 -1, -1, -1, -1, -1, -1, -1, -1, 748 -1, -1, -1, -1, -1, -1, -1, -1,
749 -1, -1, -1, -1, -1, -1, -1, -1, 749 -1, -1, -1, -1, -1, -1, -1, -1,
750 -1, -1, -1, -1, -1, -1, -1, -1, 750 -1, -1, -1, -1, -1, -1, -1, -1,
751 }; 751 };
752 752
753 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = { 753 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
754 0, 1, /* line out */ 754 0, 1, /* line out */
755 8, 9, /* aes out */ 755 8, 9, /* aes out */
756 10, 11, /* spdif out */ 756 10, 11, /* spdif out */
757 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */ 757 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
758 6, 7, /* phone out */ 758 6, 7, /* phone out */
759 -1, -1, -1, -1, -1, -1, -1, -1, 759 -1, -1, -1, -1, -1, -1, -1, -1,
760 -1, -1, -1, -1, -1, -1, -1, -1, 760 -1, -1, -1, -1, -1, -1, -1, -1,
761 -1, -1, -1, -1, -1, -1, -1, -1, 761 -1, -1, -1, -1, -1, -1, -1, -1,
762 -1, -1, -1, -1, -1, -1, -1, -1, 762 -1, -1, -1, -1, -1, -1, -1, -1,
763 -1, -1, -1, -1, -1, -1, -1, -1, 763 -1, -1, -1, -1, -1, -1, -1, -1,
764 -1, -1, -1, -1, -1, -1, -1, -1, 764 -1, -1, -1, -1, -1, -1, -1, -1,
765 }; 765 };
766 766
767 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = { 767 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
768 0, 1, /* line in */ 768 0, 1, /* line in */
769 8, 9, /* aes in */ 769 8, 9, /* aes in */
770 10, 11, /* spdif in */ 770 10, 11, /* spdif in */
771 12, 14, 16, 18, /* adat in */ 771 12, 14, 16, 18, /* adat in */
772 -1, -1, -1, -1, -1, -1, 772 -1, -1, -1, -1, -1, -1,
773 -1, -1, -1, -1, -1, -1, -1, -1, 773 -1, -1, -1, -1, -1, -1, -1, -1,
774 -1, -1, -1, -1, -1, -1, -1, -1, 774 -1, -1, -1, -1, -1, -1, -1, -1,
775 -1, -1, -1, -1, -1, -1, -1, -1, 775 -1, -1, -1, -1, -1, -1, -1, -1,
776 -1, -1, -1, -1, -1, -1, -1, -1, 776 -1, -1, -1, -1, -1, -1, -1, -1,
777 -1, -1, -1, -1, -1, -1, -1, -1, 777 -1, -1, -1, -1, -1, -1, -1, -1,
778 -1, -1, -1, -1, -1, -1, -1, -1 778 -1, -1, -1, -1, -1, -1, -1, -1
779 }; 779 };
780 780
781 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = { 781 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
782 0, 1, /* line out */ 782 0, 1, /* line out */
783 8, 9, /* aes out */ 783 8, 9, /* aes out */
784 10, 11, /* spdif out */ 784 10, 11, /* spdif out */
785 12, 14, 16, 18, /* adat out */ 785 12, 14, 16, 18, /* adat out */
786 6, 7, /* phone out */ 786 6, 7, /* phone out */
787 -1, -1, -1, -1, 787 -1, -1, -1, -1,
788 -1, -1, -1, -1, -1, -1, -1, -1, 788 -1, -1, -1, -1, -1, -1, -1, -1,
789 -1, -1, -1, -1, -1, -1, -1, -1, 789 -1, -1, -1, -1, -1, -1, -1, -1,
790 -1, -1, -1, -1, -1, -1, -1, -1, 790 -1, -1, -1, -1, -1, -1, -1, -1,
791 -1, -1, -1, -1, -1, -1, -1, -1, 791 -1, -1, -1, -1, -1, -1, -1, -1,
792 -1, -1, -1, -1, -1, -1, -1, -1, 792 -1, -1, -1, -1, -1, -1, -1, -1,
793 -1, -1, -1, -1, -1, -1, -1, -1 793 -1, -1, -1, -1, -1, -1, -1, -1
794 }; 794 };
795 795
796 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = { 796 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
797 0, 1, /* line in */ 797 0, 1, /* line in */
798 8, 9, /* aes in */ 798 8, 9, /* aes in */
799 10, 11, /* spdif in */ 799 10, 11, /* spdif in */
800 12, 16, /* adat in */ 800 12, 16, /* adat in */
801 -1, -1, -1, -1, -1, -1, -1, -1, 801 -1, -1, -1, -1, -1, -1, -1, -1,
802 -1, -1, -1, -1, -1, -1, -1, -1, 802 -1, -1, -1, -1, -1, -1, -1, -1,
803 -1, -1, -1, -1, -1, -1, -1, -1, 803 -1, -1, -1, -1, -1, -1, -1, -1,
804 -1, -1, -1, -1, -1, -1, -1, -1, 804 -1, -1, -1, -1, -1, -1, -1, -1,
805 -1, -1, -1, -1, -1, -1, -1, -1, 805 -1, -1, -1, -1, -1, -1, -1, -1,
806 -1, -1, -1, -1, -1, -1, -1, -1, 806 -1, -1, -1, -1, -1, -1, -1, -1,
807 -1, -1, -1, -1, -1, -1, -1, -1 807 -1, -1, -1, -1, -1, -1, -1, -1
808 }; 808 };
809 809
810 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = { 810 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
811 0, 1, /* line out */ 811 0, 1, /* line out */
812 8, 9, /* aes out */ 812 8, 9, /* aes out */
813 10, 11, /* spdif out */ 813 10, 11, /* spdif out */
814 12, 16, /* adat out */ 814 12, 16, /* adat out */
815 6, 7, /* phone out */ 815 6, 7, /* phone out */
816 -1, -1, -1, -1, -1, -1, 816 -1, -1, -1, -1, -1, -1,
817 -1, -1, -1, -1, -1, -1, -1, -1, 817 -1, -1, -1, -1, -1, -1, -1, -1,
818 -1, -1, -1, -1, -1, -1, -1, -1, 818 -1, -1, -1, -1, -1, -1, -1, -1,
819 -1, -1, -1, -1, -1, -1, -1, -1, 819 -1, -1, -1, -1, -1, -1, -1, -1,
820 -1, -1, -1, -1, -1, -1, -1, -1, 820 -1, -1, -1, -1, -1, -1, -1, -1,
821 -1, -1, -1, -1, -1, -1, -1, -1, 821 -1, -1, -1, -1, -1, -1, -1, -1,
822 -1, -1, -1, -1, -1, -1, -1, -1 822 -1, -1, -1, -1, -1, -1, -1, -1
823 }; 823 };
824 824
825 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = { 825 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
826 0, 1, 2, 3, 4, 5, 6, 7, 826 0, 1, 2, 3, 4, 5, 6, 7,
827 8, 9, 10, 11, 12, 13, 14, 15, 827 8, 9, 10, 11, 12, 13, 14, 15,
828 -1, -1, -1, -1, -1, -1, -1, -1, 828 -1, -1, -1, -1, -1, -1, -1, -1,
829 -1, -1, -1, -1, -1, -1, -1, -1, 829 -1, -1, -1, -1, -1, -1, -1, -1,
830 -1, -1, -1, -1, -1, -1, -1, -1, 830 -1, -1, -1, -1, -1, -1, -1, -1,
831 -1, -1, -1, -1, -1, -1, -1, -1, 831 -1, -1, -1, -1, -1, -1, -1, -1,
832 -1, -1, -1, -1, -1, -1, -1, -1, 832 -1, -1, -1, -1, -1, -1, -1, -1,
833 -1, -1, -1, -1, -1, -1, -1, -1 833 -1, -1, -1, -1, -1, -1, -1, -1
834 }; 834 };
835 835
836 struct hdspm_midi { 836 struct hdspm_midi {
837 struct hdspm *hdspm; 837 struct hdspm *hdspm;
838 int id; 838 int id;
839 struct snd_rawmidi *rmidi; 839 struct snd_rawmidi *rmidi;
840 struct snd_rawmidi_substream *input; 840 struct snd_rawmidi_substream *input;
841 struct snd_rawmidi_substream *output; 841 struct snd_rawmidi_substream *output;
842 char istimer; /* timer in use */ 842 char istimer; /* timer in use */
843 struct timer_list timer; 843 struct timer_list timer;
844 spinlock_t lock; 844 spinlock_t lock;
845 int pending; 845 int pending;
846 int dataIn; 846 int dataIn;
847 int statusIn; 847 int statusIn;
848 int dataOut; 848 int dataOut;
849 int statusOut; 849 int statusOut;
850 int ie; 850 int ie;
851 int irq; 851 int irq;
852 }; 852 };
853 853
854 struct hdspm_tco { 854 struct hdspm_tco {
855 int input; 855 int input;
856 int framerate; 856 int framerate;
857 int wordclock; 857 int wordclock;
858 int samplerate; 858 int samplerate;
859 int pull; 859 int pull;
860 int term; /* 0 = off, 1 = on */ 860 int term; /* 0 = off, 1 = on */
861 }; 861 };
862 862
863 struct hdspm { 863 struct hdspm {
864 spinlock_t lock; 864 spinlock_t lock;
865 /* only one playback and/or capture stream */ 865 /* only one playback and/or capture stream */
866 struct snd_pcm_substream *capture_substream; 866 struct snd_pcm_substream *capture_substream;
867 struct snd_pcm_substream *playback_substream; 867 struct snd_pcm_substream *playback_substream;
868 868
869 char *card_name; /* for procinfo */ 869 char *card_name; /* for procinfo */
870 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/ 870 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
871 871
872 uint8_t io_type; 872 uint8_t io_type;
873 873
874 int monitor_outs; /* set up monitoring outs init flag */ 874 int monitor_outs; /* set up monitoring outs init flag */
875 875
876 u32 control_register; /* cached value */ 876 u32 control_register; /* cached value */
877 u32 control2_register; /* cached value */ 877 u32 control2_register; /* cached value */
878 u32 settings_register; 878 u32 settings_register;
879 879
880 struct hdspm_midi midi[4]; 880 struct hdspm_midi midi[4];
881 struct tasklet_struct midi_tasklet; 881 struct tasklet_struct midi_tasklet;
882 882
883 size_t period_bytes; 883 size_t period_bytes;
884 unsigned char ss_in_channels; 884 unsigned char ss_in_channels;
885 unsigned char ds_in_channels; 885 unsigned char ds_in_channels;
886 unsigned char qs_in_channels; 886 unsigned char qs_in_channels;
887 unsigned char ss_out_channels; 887 unsigned char ss_out_channels;
888 unsigned char ds_out_channels; 888 unsigned char ds_out_channels;
889 unsigned char qs_out_channels; 889 unsigned char qs_out_channels;
890 890
891 unsigned char max_channels_in; 891 unsigned char max_channels_in;
892 unsigned char max_channels_out; 892 unsigned char max_channels_out;
893 893
894 char *channel_map_in; 894 char *channel_map_in;
895 char *channel_map_out; 895 char *channel_map_out;
896 896
897 char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs; 897 char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
898 char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs; 898 char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
899 899
900 char **port_names_in; 900 char **port_names_in;
901 char **port_names_out; 901 char **port_names_out;
902 902
903 char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs; 903 char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
904 char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs; 904 char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
905 905
906 unsigned char *playback_buffer; /* suitably aligned address */ 906 unsigned char *playback_buffer; /* suitably aligned address */
907 unsigned char *capture_buffer; /* suitably aligned address */ 907 unsigned char *capture_buffer; /* suitably aligned address */
908 908
909 pid_t capture_pid; /* process id which uses capture */ 909 pid_t capture_pid; /* process id which uses capture */
910 pid_t playback_pid; /* process id which uses capture */ 910 pid_t playback_pid; /* process id which uses capture */
911 int running; /* running status */ 911 int running; /* running status */
912 912
913 int last_external_sample_rate; /* samplerate mystic ... */ 913 int last_external_sample_rate; /* samplerate mystic ... */
914 int last_internal_sample_rate; 914 int last_internal_sample_rate;
915 int system_sample_rate; 915 int system_sample_rate;
916 916
917 int dev; /* Hardware vars... */ 917 int dev; /* Hardware vars... */
918 int irq; 918 int irq;
919 unsigned long port; 919 unsigned long port;
920 void __iomem *iobase; 920 void __iomem *iobase;
921 921
922 int irq_count; /* for debug */ 922 int irq_count; /* for debug */
923 int midiPorts; 923 int midiPorts;
924 924
925 struct snd_card *card; /* one card */ 925 struct snd_card *card; /* one card */
926 struct snd_pcm *pcm; /* has one pcm */ 926 struct snd_pcm *pcm; /* has one pcm */
927 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */ 927 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */
928 struct pci_dev *pci; /* and an pci info */ 928 struct pci_dev *pci; /* and an pci info */
929 929
930 /* Mixer vars */ 930 /* Mixer vars */
931 /* fast alsa mixer */ 931 /* fast alsa mixer */
932 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS]; 932 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
933 /* but input to much, so not used */ 933 /* but input to much, so not used */
934 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS]; 934 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
935 /* full mixer accessable over mixer ioctl or hwdep-device */ 935 /* full mixer accessable over mixer ioctl or hwdep-device */
936 struct hdspm_mixer *mixer; 936 struct hdspm_mixer *mixer;
937 937
938 struct hdspm_tco *tco; /* NULL if no TCO detected */ 938 struct hdspm_tco *tco; /* NULL if no TCO detected */
939 939
940 char **texts_autosync; 940 char **texts_autosync;
941 int texts_autosync_items; 941 int texts_autosync_items;
942 942
943 cycles_t last_interrupt; 943 cycles_t last_interrupt;
944 944
945 struct hdspm_peak_rms peak_rms; 945 struct hdspm_peak_rms peak_rms;
946 }; 946 };
947 947
948 948
949 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = { 949 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = {
950 { 950 {
951 .vendor = PCI_VENDOR_ID_XILINX, 951 .vendor = PCI_VENDOR_ID_XILINX,
952 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI, 952 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
953 .subvendor = PCI_ANY_ID, 953 .subvendor = PCI_ANY_ID,
954 .subdevice = PCI_ANY_ID, 954 .subdevice = PCI_ANY_ID,
955 .class = 0, 955 .class = 0,
956 .class_mask = 0, 956 .class_mask = 0,
957 .driver_data = 0}, 957 .driver_data = 0},
958 {0,} 958 {0,}
959 }; 959 };
960 960
961 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids); 961 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
962 962
963 /* prototypes */ 963 /* prototypes */
964 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card, 964 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
965 struct hdspm * hdspm); 965 struct hdspm * hdspm);
966 static int __devinit snd_hdspm_create_pcm(struct snd_card *card, 966 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
967 struct hdspm * hdspm); 967 struct hdspm * hdspm);
968 968
969 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm); 969 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
970 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm); 970 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
971 static int hdspm_autosync_ref(struct hdspm *hdspm); 971 static int hdspm_autosync_ref(struct hdspm *hdspm);
972 static int snd_hdspm_set_defaults(struct hdspm *hdspm); 972 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
973 static void hdspm_set_sgbuf(struct hdspm *hdspm, 973 static void hdspm_set_sgbuf(struct hdspm *hdspm,
974 struct snd_pcm_substream *substream, 974 struct snd_pcm_substream *substream,
975 unsigned int reg, int channels); 975 unsigned int reg, int channels);
976 976
977 static inline int HDSPM_bit2freq(int n) 977 static inline int HDSPM_bit2freq(int n)
978 { 978 {
979 static const int bit2freq_tab[] = { 979 static const int bit2freq_tab[] = {
980 0, 32000, 44100, 48000, 64000, 88200, 980 0, 32000, 44100, 48000, 64000, 88200,
981 96000, 128000, 176400, 192000 }; 981 96000, 128000, 176400, 192000 };
982 if (n < 1 || n > 9) 982 if (n < 1 || n > 9)
983 return 0; 983 return 0;
984 return bit2freq_tab[n]; 984 return bit2freq_tab[n];
985 } 985 }
986 986
987 /* Write/read to/from HDSPM with Adresses in Bytes 987 /* Write/read to/from HDSPM with Adresses in Bytes
988 not words but only 32Bit writes are allowed */ 988 not words but only 32Bit writes are allowed */
989 989
990 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg, 990 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
991 unsigned int val) 991 unsigned int val)
992 { 992 {
993 writel(val, hdspm->iobase + reg); 993 writel(val, hdspm->iobase + reg);
994 } 994 }
995 995
996 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg) 996 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
997 { 997 {
998 return readl(hdspm->iobase + reg); 998 return readl(hdspm->iobase + reg);
999 } 999 }
1000 1000
1001 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader 1001 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1002 mixer is write only on hardware so we have to cache him for read 1002 mixer is write only on hardware so we have to cache him for read
1003 each fader is a u32, but uses only the first 16 bit */ 1003 each fader is a u32, but uses only the first 16 bit */
1004 1004
1005 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan, 1005 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1006 unsigned int in) 1006 unsigned int in)
1007 { 1007 {
1008 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1008 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1009 return 0; 1009 return 0;
1010 1010
1011 return hdspm->mixer->ch[chan].in[in]; 1011 return hdspm->mixer->ch[chan].in[in];
1012 } 1012 }
1013 1013
1014 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan, 1014 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1015 unsigned int pb) 1015 unsigned int pb)
1016 { 1016 {
1017 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1017 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1018 return 0; 1018 return 0;
1019 return hdspm->mixer->ch[chan].pb[pb]; 1019 return hdspm->mixer->ch[chan].pb[pb];
1020 } 1020 }
1021 1021
1022 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan, 1022 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1023 unsigned int in, unsigned short data) 1023 unsigned int in, unsigned short data)
1024 { 1024 {
1025 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1025 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1026 return -1; 1026 return -1;
1027 1027
1028 hdspm_write(hdspm, 1028 hdspm_write(hdspm,
1029 HDSPM_MADI_mixerBase + 1029 HDSPM_MADI_mixerBase +
1030 ((in + 128 * chan) * sizeof(u32)), 1030 ((in + 128 * chan) * sizeof(u32)),
1031 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF)); 1031 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1032 return 0; 1032 return 0;
1033 } 1033 }
1034 1034
1035 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan, 1035 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1036 unsigned int pb, unsigned short data) 1036 unsigned int pb, unsigned short data)
1037 { 1037 {
1038 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1038 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1039 return -1; 1039 return -1;
1040 1040
1041 hdspm_write(hdspm, 1041 hdspm_write(hdspm,
1042 HDSPM_MADI_mixerBase + 1042 HDSPM_MADI_mixerBase +
1043 ((64 + pb + 128 * chan) * sizeof(u32)), 1043 ((64 + pb + 128 * chan) * sizeof(u32)),
1044 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF)); 1044 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1045 return 0; 1045 return 0;
1046 } 1046 }
1047 1047
1048 1048
1049 /* enable DMA for specific channels, now available for DSP-MADI */ 1049 /* enable DMA for specific channels, now available for DSP-MADI */
1050 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v) 1050 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1051 { 1051 {
1052 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v); 1052 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1053 } 1053 }
1054 1054
1055 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v) 1055 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1056 { 1056 {
1057 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v); 1057 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1058 } 1058 }
1059 1059
1060 /* check if same process is writing and reading */ 1060 /* check if same process is writing and reading */
1061 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm) 1061 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1062 { 1062 {
1063 unsigned long flags; 1063 unsigned long flags;
1064 int ret = 1; 1064 int ret = 1;
1065 1065
1066 spin_lock_irqsave(&hdspm->lock, flags); 1066 spin_lock_irqsave(&hdspm->lock, flags);
1067 if ((hdspm->playback_pid != hdspm->capture_pid) && 1067 if ((hdspm->playback_pid != hdspm->capture_pid) &&
1068 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) { 1068 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1069 ret = 0; 1069 ret = 0;
1070 } 1070 }
1071 spin_unlock_irqrestore(&hdspm->lock, flags); 1071 spin_unlock_irqrestore(&hdspm->lock, flags);
1072 return ret; 1072 return ret;
1073 } 1073 }
1074 1074
1075 /* check for external sample rate */ 1075 /* check for external sample rate */
1076 static int hdspm_external_sample_rate(struct hdspm *hdspm) 1076 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1077 { 1077 {
1078 unsigned int status, status2, timecode; 1078 unsigned int status, status2, timecode;
1079 int syncref, rate = 0, rate_bits; 1079 int syncref, rate = 0, rate_bits;
1080 1080
1081 switch (hdspm->io_type) { 1081 switch (hdspm->io_type) {
1082 case AES32: 1082 case AES32:
1083 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1083 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1084 status = hdspm_read(hdspm, HDSPM_statusRegister); 1084 status = hdspm_read(hdspm, HDSPM_statusRegister);
1085 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 1085 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
1086 1086
1087 syncref = hdspm_autosync_ref(hdspm); 1087 syncref = hdspm_autosync_ref(hdspm);
1088 1088
1089 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD && 1089 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD &&
1090 status & HDSPM_AES32_wcLock) 1090 status & HDSPM_AES32_wcLock)
1091 return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF); 1091 return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF);
1092 1092
1093 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 && 1093 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 &&
1094 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 && 1094 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 &&
1095 status2 & (HDSPM_LockAES >> 1095 status2 & (HDSPM_LockAES >>
1096 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1))) 1096 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)))
1097 return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF); 1097 return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF);
1098 return 0; 1098 return 0;
1099 break; 1099 break;
1100 1100
1101 case MADIface: 1101 case MADIface:
1102 status = hdspm_read(hdspm, HDSPM_statusRegister); 1102 status = hdspm_read(hdspm, HDSPM_statusRegister);
1103 1103
1104 if (!(status & HDSPM_madiLock)) { 1104 if (!(status & HDSPM_madiLock)) {
1105 rate = 0; /* no lock */ 1105 rate = 0; /* no lock */
1106 } else { 1106 } else {
1107 switch (status & (HDSPM_status1_freqMask)) { 1107 switch (status & (HDSPM_status1_freqMask)) {
1108 case HDSPM_status1_F_0*1: 1108 case HDSPM_status1_F_0*1:
1109 rate = 32000; break; 1109 rate = 32000; break;
1110 case HDSPM_status1_F_0*2: 1110 case HDSPM_status1_F_0*2:
1111 rate = 44100; break; 1111 rate = 44100; break;
1112 case HDSPM_status1_F_0*3: 1112 case HDSPM_status1_F_0*3:
1113 rate = 48000; break; 1113 rate = 48000; break;
1114 case HDSPM_status1_F_0*4: 1114 case HDSPM_status1_F_0*4:
1115 rate = 64000; break; 1115 rate = 64000; break;
1116 case HDSPM_status1_F_0*5: 1116 case HDSPM_status1_F_0*5:
1117 rate = 88200; break; 1117 rate = 88200; break;
1118 case HDSPM_status1_F_0*6: 1118 case HDSPM_status1_F_0*6:
1119 rate = 96000; break; 1119 rate = 96000; break;
1120 case HDSPM_status1_F_0*7: 1120 case HDSPM_status1_F_0*7:
1121 rate = 128000; break; 1121 rate = 128000; break;
1122 case HDSPM_status1_F_0*8: 1122 case HDSPM_status1_F_0*8:
1123 rate = 176400; break; 1123 rate = 176400; break;
1124 case HDSPM_status1_F_0*9: 1124 case HDSPM_status1_F_0*9:
1125 rate = 192000; break; 1125 rate = 192000; break;
1126 default: 1126 default:
1127 rate = 0; break; 1127 rate = 0; break;
1128 } 1128 }
1129 } 1129 }
1130 1130
1131 break; 1131 break;
1132 1132
1133 case MADI: 1133 case MADI:
1134 case AIO: 1134 case AIO:
1135 case RayDAT: 1135 case RayDAT:
1136 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1136 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1137 status = hdspm_read(hdspm, HDSPM_statusRegister); 1137 status = hdspm_read(hdspm, HDSPM_statusRegister);
1138 rate = 0; 1138 rate = 0;
1139 1139
1140 /* if wordclock has synced freq and wordclock is valid */ 1140 /* if wordclock has synced freq and wordclock is valid */
1141 if ((status2 & HDSPM_wcLock) != 0 && 1141 if ((status2 & HDSPM_wcLock) != 0 &&
1142 (status & HDSPM_SelSyncRef0) == 0) { 1142 (status & HDSPM_SelSyncRef0) == 0) {
1143 1143
1144 rate_bits = status2 & HDSPM_wcFreqMask; 1144 rate_bits = status2 & HDSPM_wcFreqMask;
1145 1145
1146 1146
1147 switch (rate_bits) { 1147 switch (rate_bits) {
1148 case HDSPM_wcFreq32: 1148 case HDSPM_wcFreq32:
1149 rate = 32000; 1149 rate = 32000;
1150 break; 1150 break;
1151 case HDSPM_wcFreq44_1: 1151 case HDSPM_wcFreq44_1:
1152 rate = 44100; 1152 rate = 44100;
1153 break; 1153 break;
1154 case HDSPM_wcFreq48: 1154 case HDSPM_wcFreq48:
1155 rate = 48000; 1155 rate = 48000;
1156 break; 1156 break;
1157 case HDSPM_wcFreq64: 1157 case HDSPM_wcFreq64:
1158 rate = 64000; 1158 rate = 64000;
1159 break; 1159 break;
1160 case HDSPM_wcFreq88_2: 1160 case HDSPM_wcFreq88_2:
1161 rate = 88200; 1161 rate = 88200;
1162 break; 1162 break;
1163 case HDSPM_wcFreq96: 1163 case HDSPM_wcFreq96:
1164 rate = 96000; 1164 rate = 96000;
1165 break; 1165 break;
1166 default: 1166 default:
1167 rate = 0; 1167 rate = 0;
1168 break; 1168 break;
1169 } 1169 }
1170 } 1170 }
1171 1171
1172 /* if rate detected and Syncref is Word than have it, 1172 /* if rate detected and Syncref is Word than have it,
1173 * word has priority to MADI 1173 * word has priority to MADI
1174 */ 1174 */
1175 if (rate != 0 && 1175 if (rate != 0 &&
1176 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD) 1176 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1177 return rate; 1177 return rate;
1178 1178
1179 /* maybe a madi input (which is taken if sel sync is madi) */ 1179 /* maybe a madi input (which is taken if sel sync is madi) */
1180 if (status & HDSPM_madiLock) { 1180 if (status & HDSPM_madiLock) {
1181 rate_bits = status & HDSPM_madiFreqMask; 1181 rate_bits = status & HDSPM_madiFreqMask;
1182 1182
1183 switch (rate_bits) { 1183 switch (rate_bits) {
1184 case HDSPM_madiFreq32: 1184 case HDSPM_madiFreq32:
1185 rate = 32000; 1185 rate = 32000;
1186 break; 1186 break;
1187 case HDSPM_madiFreq44_1: 1187 case HDSPM_madiFreq44_1:
1188 rate = 44100; 1188 rate = 44100;
1189 break; 1189 break;
1190 case HDSPM_madiFreq48: 1190 case HDSPM_madiFreq48:
1191 rate = 48000; 1191 rate = 48000;
1192 break; 1192 break;
1193 case HDSPM_madiFreq64: 1193 case HDSPM_madiFreq64:
1194 rate = 64000; 1194 rate = 64000;
1195 break; 1195 break;
1196 case HDSPM_madiFreq88_2: 1196 case HDSPM_madiFreq88_2:
1197 rate = 88200; 1197 rate = 88200;
1198 break; 1198 break;
1199 case HDSPM_madiFreq96: 1199 case HDSPM_madiFreq96:
1200 rate = 96000; 1200 rate = 96000;
1201 break; 1201 break;
1202 case HDSPM_madiFreq128: 1202 case HDSPM_madiFreq128:
1203 rate = 128000; 1203 rate = 128000;
1204 break; 1204 break;
1205 case HDSPM_madiFreq176_4: 1205 case HDSPM_madiFreq176_4:
1206 rate = 176400; 1206 rate = 176400;
1207 break; 1207 break;
1208 case HDSPM_madiFreq192: 1208 case HDSPM_madiFreq192:
1209 rate = 192000; 1209 rate = 192000;
1210 break; 1210 break;
1211 default: 1211 default:
1212 rate = 0; 1212 rate = 0;
1213 break; 1213 break;
1214 } 1214 }
1215 } 1215 }
1216 break; 1216 break;
1217 } 1217 }
1218 1218
1219 return rate; 1219 return rate;
1220 } 1220 }
1221 1221
1222 /* Latency function */ 1222 /* Latency function */
1223 static inline void hdspm_compute_period_size(struct hdspm *hdspm) 1223 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1224 { 1224 {
1225 hdspm->period_bytes = 1 << ((hdspm_decode_latency(hdspm->control_register) + 8)); 1225 hdspm->period_bytes = 1 << ((hdspm_decode_latency(hdspm->control_register) + 8));
1226 } 1226 }
1227 1227
1228 1228
1229 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm) 1229 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1230 { 1230 {
1231 int position; 1231 int position;
1232 1232
1233 position = hdspm_read(hdspm, HDSPM_statusRegister); 1233 position = hdspm_read(hdspm, HDSPM_statusRegister);
1234 1234
1235 switch (hdspm->io_type) { 1235 switch (hdspm->io_type) {
1236 case RayDAT: 1236 case RayDAT:
1237 case AIO: 1237 case AIO:
1238 position &= HDSPM_BufferPositionMask; 1238 position &= HDSPM_BufferPositionMask;
1239 position /= 4; /* Bytes per sample */ 1239 position /= 4; /* Bytes per sample */
1240 break; 1240 break;
1241 default: 1241 default:
1242 position = (position & HDSPM_BufferID) ? 1242 position = (position & HDSPM_BufferID) ?
1243 (hdspm->period_bytes / 4) : 0; 1243 (hdspm->period_bytes / 4) : 0;
1244 } 1244 }
1245 1245
1246 return position; 1246 return position;
1247 } 1247 }
1248 1248
1249 1249
1250 static inline void hdspm_start_audio(struct hdspm * s) 1250 static inline void hdspm_start_audio(struct hdspm * s)
1251 { 1251 {
1252 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start); 1252 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1253 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1253 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1254 } 1254 }
1255 1255
1256 static inline void hdspm_stop_audio(struct hdspm * s) 1256 static inline void hdspm_stop_audio(struct hdspm * s)
1257 { 1257 {
1258 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable); 1258 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1259 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1259 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1260 } 1260 }
1261 1261
1262 /* should I silence all or only opened ones ? doit all for first even is 4MB*/ 1262 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1263 static void hdspm_silence_playback(struct hdspm *hdspm) 1263 static void hdspm_silence_playback(struct hdspm *hdspm)
1264 { 1264 {
1265 int i; 1265 int i;
1266 int n = hdspm->period_bytes; 1266 int n = hdspm->period_bytes;
1267 void *buf = hdspm->playback_buffer; 1267 void *buf = hdspm->playback_buffer;
1268 1268
1269 if (buf == NULL) 1269 if (buf == NULL)
1270 return; 1270 return;
1271 1271
1272 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 1272 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1273 memset(buf, 0, n); 1273 memset(buf, 0, n);
1274 buf += HDSPM_CHANNEL_BUFFER_BYTES; 1274 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1275 } 1275 }
1276 } 1276 }
1277 1277
1278 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames) 1278 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1279 { 1279 {
1280 int n; 1280 int n;
1281 1281
1282 spin_lock_irq(&s->lock); 1282 spin_lock_irq(&s->lock);
1283 1283
1284 frames >>= 7; 1284 frames >>= 7;
1285 n = 0; 1285 n = 0;
1286 while (frames) { 1286 while (frames) {
1287 n++; 1287 n++;
1288 frames >>= 1; 1288 frames >>= 1;
1289 } 1289 }
1290 s->control_register &= ~HDSPM_LatencyMask; 1290 s->control_register &= ~HDSPM_LatencyMask;
1291 s->control_register |= hdspm_encode_latency(n); 1291 s->control_register |= hdspm_encode_latency(n);
1292 1292
1293 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1293 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1294 1294
1295 hdspm_compute_period_size(s); 1295 hdspm_compute_period_size(s);
1296 1296
1297 spin_unlock_irq(&s->lock); 1297 spin_unlock_irq(&s->lock);
1298 1298
1299 return 0; 1299 return 0;
1300 } 1300 }
1301 1301
1302 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period) 1302 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1303 { 1303 {
1304 u64 freq_const; 1304 u64 freq_const;
1305 1305
1306 if (period == 0) 1306 if (period == 0)
1307 return 0; 1307 return 0;
1308 1308
1309 switch (hdspm->io_type) { 1309 switch (hdspm->io_type) {
1310 case MADI: 1310 case MADI:
1311 case AES32: 1311 case AES32:
1312 freq_const = 110069313433624ULL; 1312 freq_const = 110069313433624ULL;
1313 break; 1313 break;
1314 case RayDAT: 1314 case RayDAT:
1315 case AIO: 1315 case AIO:
1316 freq_const = 104857600000000ULL; 1316 freq_const = 104857600000000ULL;
1317 break; 1317 break;
1318 case MADIface: 1318 case MADIface:
1319 freq_const = 131072000000000ULL; 1319 freq_const = 131072000000000ULL;
1320 } 1320 }
1321 1321
1322 return div_u64(freq_const, period); 1322 return div_u64(freq_const, period);
1323 } 1323 }
1324 1324
1325 1325
1326 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate) 1326 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1327 { 1327 {
1328 u64 n; 1328 u64 n;
1329 1329
1330 if (rate >= 112000) 1330 if (rate >= 112000)
1331 rate /= 4; 1331 rate /= 4;
1332 else if (rate >= 56000) 1332 else if (rate >= 56000)
1333 rate /= 2; 1333 rate /= 2;
1334 1334
1335 switch (hdspm->io_type) { 1335 switch (hdspm->io_type) {
1336 case MADIface: 1336 case MADIface:
1337 n = 131072000000000ULL; /* 125 MHz */ 1337 n = 131072000000000ULL; /* 125 MHz */
1338 break; 1338 break;
1339 case MADI: 1339 case MADI:
1340 case AES32: 1340 case AES32:
1341 n = 110069313433624ULL; /* 105 MHz */ 1341 n = 110069313433624ULL; /* 105 MHz */
1342 break; 1342 break;
1343 case RayDAT: 1343 case RayDAT:
1344 case AIO: 1344 case AIO:
1345 n = 104857600000000ULL; /* 100 MHz */ 1345 n = 104857600000000ULL; /* 100 MHz */
1346 break; 1346 break;
1347 } 1347 }
1348 1348
1349 n = div_u64(n, rate); 1349 n = div_u64(n, rate);
1350 /* n should be less than 2^32 for being written to FREQ register */ 1350 /* n should be less than 2^32 for being written to FREQ register */
1351 snd_BUG_ON(n >> 32); 1351 snd_BUG_ON(n >> 32);
1352 hdspm_write(hdspm, HDSPM_freqReg, (u32)n); 1352 hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1353 } 1353 }
1354 1354
1355 /* dummy set rate lets see what happens */ 1355 /* dummy set rate lets see what happens */
1356 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally) 1356 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1357 { 1357 {
1358 int current_rate; 1358 int current_rate;
1359 int rate_bits; 1359 int rate_bits;
1360 int not_set = 0; 1360 int not_set = 0;
1361 int current_speed, target_speed; 1361 int current_speed, target_speed;
1362 1362
1363 /* ASSUMPTION: hdspm->lock is either set, or there is no need for 1363 /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1364 it (e.g. during module initialization). 1364 it (e.g. during module initialization).
1365 */ 1365 */
1366 1366
1367 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) { 1367 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1368 1368
1369 /* SLAVE --- */ 1369 /* SLAVE --- */
1370 if (called_internally) { 1370 if (called_internally) {
1371 1371
1372 /* request from ctl or card initialization 1372 /* request from ctl or card initialization
1373 just make a warning an remember setting 1373 just make a warning an remember setting
1374 for future master mode switching */ 1374 for future master mode switching */
1375 1375
1376 snd_printk(KERN_WARNING "HDSPM: " 1376 snd_printk(KERN_WARNING "HDSPM: "
1377 "Warning: device is not running " 1377 "Warning: device is not running "
1378 "as a clock master.\n"); 1378 "as a clock master.\n");
1379 not_set = 1; 1379 not_set = 1;
1380 } else { 1380 } else {
1381 1381
1382 /* hw_param request while in AutoSync mode */ 1382 /* hw_param request while in AutoSync mode */
1383 int external_freq = 1383 int external_freq =
1384 hdspm_external_sample_rate(hdspm); 1384 hdspm_external_sample_rate(hdspm);
1385 1385
1386 if (hdspm_autosync_ref(hdspm) == 1386 if (hdspm_autosync_ref(hdspm) ==
1387 HDSPM_AUTOSYNC_FROM_NONE) { 1387 HDSPM_AUTOSYNC_FROM_NONE) {
1388 1388
1389 snd_printk(KERN_WARNING "HDSPM: " 1389 snd_printk(KERN_WARNING "HDSPM: "
1390 "Detected no Externel Sync \n"); 1390 "Detected no Externel Sync \n");
1391 not_set = 1; 1391 not_set = 1;
1392 1392
1393 } else if (rate != external_freq) { 1393 } else if (rate != external_freq) {
1394 1394
1395 snd_printk(KERN_WARNING "HDSPM: " 1395 snd_printk(KERN_WARNING "HDSPM: "
1396 "Warning: No AutoSync source for " 1396 "Warning: No AutoSync source for "
1397 "requested rate\n"); 1397 "requested rate\n");
1398 not_set = 1; 1398 not_set = 1;
1399 } 1399 }
1400 } 1400 }
1401 } 1401 }
1402 1402
1403 current_rate = hdspm->system_sample_rate; 1403 current_rate = hdspm->system_sample_rate;
1404 1404
1405 /* Changing between Singe, Double and Quad speed is not 1405 /* Changing between Singe, Double and Quad speed is not
1406 allowed if any substreams are open. This is because such a change 1406 allowed if any substreams are open. This is because such a change
1407 causes a shift in the location of the DMA buffers and a reduction 1407 causes a shift in the location of the DMA buffers and a reduction
1408 in the number of available buffers. 1408 in the number of available buffers.
1409 1409
1410 Note that a similar but essentially insoluble problem exists for 1410 Note that a similar but essentially insoluble problem exists for
1411 externally-driven rate changes. All we can do is to flag rate 1411 externally-driven rate changes. All we can do is to flag rate
1412 changes in the read/write routines. 1412 changes in the read/write routines.
1413 */ 1413 */
1414 1414
1415 if (current_rate <= 48000) 1415 if (current_rate <= 48000)
1416 current_speed = HDSPM_SPEED_SINGLE; 1416 current_speed = HDSPM_SPEED_SINGLE;
1417 else if (current_rate <= 96000) 1417 else if (current_rate <= 96000)
1418 current_speed = HDSPM_SPEED_DOUBLE; 1418 current_speed = HDSPM_SPEED_DOUBLE;
1419 else 1419 else
1420 current_speed = HDSPM_SPEED_QUAD; 1420 current_speed = HDSPM_SPEED_QUAD;
1421 1421
1422 if (rate <= 48000) 1422 if (rate <= 48000)
1423 target_speed = HDSPM_SPEED_SINGLE; 1423 target_speed = HDSPM_SPEED_SINGLE;
1424 else if (rate <= 96000) 1424 else if (rate <= 96000)
1425 target_speed = HDSPM_SPEED_DOUBLE; 1425 target_speed = HDSPM_SPEED_DOUBLE;
1426 else 1426 else
1427 target_speed = HDSPM_SPEED_QUAD; 1427 target_speed = HDSPM_SPEED_QUAD;
1428 1428
1429 switch (rate) { 1429 switch (rate) {
1430 case 32000: 1430 case 32000:
1431 rate_bits = HDSPM_Frequency32KHz; 1431 rate_bits = HDSPM_Frequency32KHz;
1432 break; 1432 break;
1433 case 44100: 1433 case 44100:
1434 rate_bits = HDSPM_Frequency44_1KHz; 1434 rate_bits = HDSPM_Frequency44_1KHz;
1435 break; 1435 break;
1436 case 48000: 1436 case 48000:
1437 rate_bits = HDSPM_Frequency48KHz; 1437 rate_bits = HDSPM_Frequency48KHz;
1438 break; 1438 break;
1439 case 64000: 1439 case 64000:
1440 rate_bits = HDSPM_Frequency64KHz; 1440 rate_bits = HDSPM_Frequency64KHz;
1441 break; 1441 break;
1442 case 88200: 1442 case 88200:
1443 rate_bits = HDSPM_Frequency88_2KHz; 1443 rate_bits = HDSPM_Frequency88_2KHz;
1444 break; 1444 break;
1445 case 96000: 1445 case 96000:
1446 rate_bits = HDSPM_Frequency96KHz; 1446 rate_bits = HDSPM_Frequency96KHz;
1447 break; 1447 break;
1448 case 128000: 1448 case 128000:
1449 rate_bits = HDSPM_Frequency128KHz; 1449 rate_bits = HDSPM_Frequency128KHz;
1450 break; 1450 break;
1451 case 176400: 1451 case 176400:
1452 rate_bits = HDSPM_Frequency176_4KHz; 1452 rate_bits = HDSPM_Frequency176_4KHz;
1453 break; 1453 break;
1454 case 192000: 1454 case 192000:
1455 rate_bits = HDSPM_Frequency192KHz; 1455 rate_bits = HDSPM_Frequency192KHz;
1456 break; 1456 break;
1457 default: 1457 default:
1458 return -EINVAL; 1458 return -EINVAL;
1459 } 1459 }
1460 1460
1461 if (current_speed != target_speed 1461 if (current_speed != target_speed
1462 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) { 1462 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1463 snd_printk 1463 snd_printk
1464 (KERN_ERR "HDSPM: " 1464 (KERN_ERR "HDSPM: "
1465 "cannot change from %s speed to %s speed mode " 1465 "cannot change from %s speed to %s speed mode "
1466 "(capture PID = %d, playback PID = %d)\n", 1466 "(capture PID = %d, playback PID = %d)\n",
1467 hdspm_speed_names[current_speed], 1467 hdspm_speed_names[current_speed],
1468 hdspm_speed_names[target_speed], 1468 hdspm_speed_names[target_speed],
1469 hdspm->capture_pid, hdspm->playback_pid); 1469 hdspm->capture_pid, hdspm->playback_pid);
1470 return -EBUSY; 1470 return -EBUSY;
1471 } 1471 }
1472 1472
1473 hdspm->control_register &= ~HDSPM_FrequencyMask; 1473 hdspm->control_register &= ~HDSPM_FrequencyMask;
1474 hdspm->control_register |= rate_bits; 1474 hdspm->control_register |= rate_bits;
1475 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1475 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1476 1476
1477 /* For AES32, need to set DDS value in FREQ register 1477 /* For AES32, need to set DDS value in FREQ register
1478 For MADI, also apparently */ 1478 For MADI, also apparently */
1479 hdspm_set_dds_value(hdspm, rate); 1479 hdspm_set_dds_value(hdspm, rate);
1480 1480
1481 if (AES32 == hdspm->io_type && rate != current_rate) 1481 if (AES32 == hdspm->io_type && rate != current_rate)
1482 hdspm_write(hdspm, HDSPM_eeprom_wr, 0); 1482 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1483 1483
1484 hdspm->system_sample_rate = rate; 1484 hdspm->system_sample_rate = rate;
1485 1485
1486 if (rate <= 48000) { 1486 if (rate <= 48000) {
1487 hdspm->channel_map_in = hdspm->channel_map_in_ss; 1487 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1488 hdspm->channel_map_out = hdspm->channel_map_out_ss; 1488 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1489 hdspm->max_channels_in = hdspm->ss_in_channels; 1489 hdspm->max_channels_in = hdspm->ss_in_channels;
1490 hdspm->max_channels_out = hdspm->ss_out_channels; 1490 hdspm->max_channels_out = hdspm->ss_out_channels;
1491 hdspm->port_names_in = hdspm->port_names_in_ss; 1491 hdspm->port_names_in = hdspm->port_names_in_ss;
1492 hdspm->port_names_out = hdspm->port_names_out_ss; 1492 hdspm->port_names_out = hdspm->port_names_out_ss;
1493 } else if (rate <= 96000) { 1493 } else if (rate <= 96000) {
1494 hdspm->channel_map_in = hdspm->channel_map_in_ds; 1494 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1495 hdspm->channel_map_out = hdspm->channel_map_out_ds; 1495 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1496 hdspm->max_channels_in = hdspm->ds_in_channels; 1496 hdspm->max_channels_in = hdspm->ds_in_channels;
1497 hdspm->max_channels_out = hdspm->ds_out_channels; 1497 hdspm->max_channels_out = hdspm->ds_out_channels;
1498 hdspm->port_names_in = hdspm->port_names_in_ds; 1498 hdspm->port_names_in = hdspm->port_names_in_ds;
1499 hdspm->port_names_out = hdspm->port_names_out_ds; 1499 hdspm->port_names_out = hdspm->port_names_out_ds;
1500 } else { 1500 } else {
1501 hdspm->channel_map_in = hdspm->channel_map_in_qs; 1501 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1502 hdspm->channel_map_out = hdspm->channel_map_out_qs; 1502 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1503 hdspm->max_channels_in = hdspm->qs_in_channels; 1503 hdspm->max_channels_in = hdspm->qs_in_channels;
1504 hdspm->max_channels_out = hdspm->qs_out_channels; 1504 hdspm->max_channels_out = hdspm->qs_out_channels;
1505 hdspm->port_names_in = hdspm->port_names_in_qs; 1505 hdspm->port_names_in = hdspm->port_names_in_qs;
1506 hdspm->port_names_out = hdspm->port_names_out_qs; 1506 hdspm->port_names_out = hdspm->port_names_out_qs;
1507 } 1507 }
1508 1508
1509 if (not_set != 0) 1509 if (not_set != 0)
1510 return -1; 1510 return -1;
1511 1511
1512 return 0; 1512 return 0;
1513 } 1513 }
1514 1514
1515 /* mainly for init to 0 on load */ 1515 /* mainly for init to 0 on load */
1516 static void all_in_all_mixer(struct hdspm * hdspm, int sgain) 1516 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1517 { 1517 {
1518 int i, j; 1518 int i, j;
1519 unsigned int gain; 1519 unsigned int gain;
1520 1520
1521 if (sgain > UNITY_GAIN) 1521 if (sgain > UNITY_GAIN)
1522 gain = UNITY_GAIN; 1522 gain = UNITY_GAIN;
1523 else if (sgain < 0) 1523 else if (sgain < 0)
1524 gain = 0; 1524 gain = 0;
1525 else 1525 else
1526 gain = sgain; 1526 gain = sgain;
1527 1527
1528 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++) 1528 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1529 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) { 1529 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1530 hdspm_write_in_gain(hdspm, i, j, gain); 1530 hdspm_write_in_gain(hdspm, i, j, gain);
1531 hdspm_write_pb_gain(hdspm, i, j, gain); 1531 hdspm_write_pb_gain(hdspm, i, j, gain);
1532 } 1532 }
1533 } 1533 }
1534 1534
1535 /*---------------------------------------------------------------------------- 1535 /*----------------------------------------------------------------------------
1536 MIDI 1536 MIDI
1537 ----------------------------------------------------------------------------*/ 1537 ----------------------------------------------------------------------------*/
1538 1538
1539 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm, 1539 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1540 int id) 1540 int id)
1541 { 1541 {
1542 /* the hardware already does the relevant bit-mask with 0xff */ 1542 /* the hardware already does the relevant bit-mask with 0xff */
1543 return hdspm_read(hdspm, hdspm->midi[id].dataIn); 1543 return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1544 } 1544 }
1545 1545
1546 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id, 1546 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1547 int val) 1547 int val)
1548 { 1548 {
1549 /* the hardware already does the relevant bit-mask with 0xff */ 1549 /* the hardware already does the relevant bit-mask with 0xff */
1550 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val); 1550 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1551 } 1551 }
1552 1552
1553 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id) 1553 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1554 { 1554 {
1555 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF; 1555 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1556 } 1556 }
1557 1557
1558 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id) 1558 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1559 { 1559 {
1560 int fifo_bytes_used; 1560 int fifo_bytes_used;
1561 1561
1562 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF; 1562 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1563 1563
1564 if (fifo_bytes_used < 128) 1564 if (fifo_bytes_used < 128)
1565 return 128 - fifo_bytes_used; 1565 return 128 - fifo_bytes_used;
1566 else 1566 else
1567 return 0; 1567 return 0;
1568 } 1568 }
1569 1569
1570 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id) 1570 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1571 { 1571 {
1572 while (snd_hdspm_midi_input_available (hdspm, id)) 1572 while (snd_hdspm_midi_input_available (hdspm, id))
1573 snd_hdspm_midi_read_byte (hdspm, id); 1573 snd_hdspm_midi_read_byte (hdspm, id);
1574 } 1574 }
1575 1575
1576 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi) 1576 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1577 { 1577 {
1578 unsigned long flags; 1578 unsigned long flags;
1579 int n_pending; 1579 int n_pending;
1580 int to_write; 1580 int to_write;
1581 int i; 1581 int i;
1582 unsigned char buf[128]; 1582 unsigned char buf[128];
1583 1583
1584 /* Output is not interrupt driven */ 1584 /* Output is not interrupt driven */
1585 1585
1586 spin_lock_irqsave (&hmidi->lock, flags); 1586 spin_lock_irqsave (&hmidi->lock, flags);
1587 if (hmidi->output && 1587 if (hmidi->output &&
1588 !snd_rawmidi_transmit_empty (hmidi->output)) { 1588 !snd_rawmidi_transmit_empty (hmidi->output)) {
1589 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm, 1589 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1590 hmidi->id); 1590 hmidi->id);
1591 if (n_pending > 0) { 1591 if (n_pending > 0) {
1592 if (n_pending > (int)sizeof (buf)) 1592 if (n_pending > (int)sizeof (buf))
1593 n_pending = sizeof (buf); 1593 n_pending = sizeof (buf);
1594 1594
1595 to_write = snd_rawmidi_transmit (hmidi->output, buf, 1595 to_write = snd_rawmidi_transmit (hmidi->output, buf,
1596 n_pending); 1596 n_pending);
1597 if (to_write > 0) { 1597 if (to_write > 0) {
1598 for (i = 0; i < to_write; ++i) 1598 for (i = 0; i < to_write; ++i)
1599 snd_hdspm_midi_write_byte (hmidi->hdspm, 1599 snd_hdspm_midi_write_byte (hmidi->hdspm,
1600 hmidi->id, 1600 hmidi->id,
1601 buf[i]); 1601 buf[i]);
1602 } 1602 }
1603 } 1603 }
1604 } 1604 }
1605 spin_unlock_irqrestore (&hmidi->lock, flags); 1605 spin_unlock_irqrestore (&hmidi->lock, flags);
1606 return 0; 1606 return 0;
1607 } 1607 }
1608 1608
1609 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi) 1609 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1610 { 1610 {
1611 unsigned char buf[128]; /* this buffer is designed to match the MIDI 1611 unsigned char buf[128]; /* this buffer is designed to match the MIDI
1612 * input FIFO size 1612 * input FIFO size
1613 */ 1613 */
1614 unsigned long flags; 1614 unsigned long flags;
1615 int n_pending; 1615 int n_pending;
1616 int i; 1616 int i;
1617 1617
1618 spin_lock_irqsave (&hmidi->lock, flags); 1618 spin_lock_irqsave (&hmidi->lock, flags);
1619 n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id); 1619 n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1620 if (n_pending > 0) { 1620 if (n_pending > 0) {
1621 if (hmidi->input) { 1621 if (hmidi->input) {
1622 if (n_pending > (int)sizeof (buf)) 1622 if (n_pending > (int)sizeof (buf))
1623 n_pending = sizeof (buf); 1623 n_pending = sizeof (buf);
1624 for (i = 0; i < n_pending; ++i) 1624 for (i = 0; i < n_pending; ++i)
1625 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm, 1625 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1626 hmidi->id); 1626 hmidi->id);
1627 if (n_pending) 1627 if (n_pending)
1628 snd_rawmidi_receive (hmidi->input, buf, 1628 snd_rawmidi_receive (hmidi->input, buf,
1629 n_pending); 1629 n_pending);
1630 } else { 1630 } else {
1631 /* flush the MIDI input FIFO */ 1631 /* flush the MIDI input FIFO */
1632 while (n_pending--) 1632 while (n_pending--)
1633 snd_hdspm_midi_read_byte (hmidi->hdspm, 1633 snd_hdspm_midi_read_byte (hmidi->hdspm,
1634 hmidi->id); 1634 hmidi->id);
1635 } 1635 }
1636 } 1636 }
1637 hmidi->pending = 0; 1637 hmidi->pending = 0;
1638 1638
1639 hmidi->hdspm->control_register |= hmidi->ie; 1639 hmidi->hdspm->control_register |= hmidi->ie;
1640 hdspm_write(hmidi->hdspm, HDSPM_controlRegister, 1640 hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1641 hmidi->hdspm->control_register); 1641 hmidi->hdspm->control_register);
1642 1642
1643 spin_unlock_irqrestore (&hmidi->lock, flags); 1643 spin_unlock_irqrestore (&hmidi->lock, flags);
1644 return snd_hdspm_midi_output_write (hmidi); 1644 return snd_hdspm_midi_output_write (hmidi);
1645 } 1645 }
1646 1646
1647 static void 1647 static void
1648 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 1648 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1649 { 1649 {
1650 struct hdspm *hdspm; 1650 struct hdspm *hdspm;
1651 struct hdspm_midi *hmidi; 1651 struct hdspm_midi *hmidi;
1652 unsigned long flags; 1652 unsigned long flags;
1653 1653
1654 hmidi = substream->rmidi->private_data; 1654 hmidi = substream->rmidi->private_data;
1655 hdspm = hmidi->hdspm; 1655 hdspm = hmidi->hdspm;
1656 1656
1657 spin_lock_irqsave (&hdspm->lock, flags); 1657 spin_lock_irqsave (&hdspm->lock, flags);
1658 if (up) { 1658 if (up) {
1659 if (!(hdspm->control_register & hmidi->ie)) { 1659 if (!(hdspm->control_register & hmidi->ie)) {
1660 snd_hdspm_flush_midi_input (hdspm, hmidi->id); 1660 snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1661 hdspm->control_register |= hmidi->ie; 1661 hdspm->control_register |= hmidi->ie;
1662 } 1662 }
1663 } else { 1663 } else {
1664 hdspm->control_register &= ~hmidi->ie; 1664 hdspm->control_register &= ~hmidi->ie;
1665 } 1665 }
1666 1666
1667 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1667 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1668 spin_unlock_irqrestore (&hdspm->lock, flags); 1668 spin_unlock_irqrestore (&hdspm->lock, flags);
1669 } 1669 }
1670 1670
1671 static void snd_hdspm_midi_output_timer(unsigned long data) 1671 static void snd_hdspm_midi_output_timer(unsigned long data)
1672 { 1672 {
1673 struct hdspm_midi *hmidi = (struct hdspm_midi *) data; 1673 struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1674 unsigned long flags; 1674 unsigned long flags;
1675 1675
1676 snd_hdspm_midi_output_write(hmidi); 1676 snd_hdspm_midi_output_write(hmidi);
1677 spin_lock_irqsave (&hmidi->lock, flags); 1677 spin_lock_irqsave (&hmidi->lock, flags);
1678 1678
1679 /* this does not bump hmidi->istimer, because the 1679 /* this does not bump hmidi->istimer, because the
1680 kernel automatically removed the timer when it 1680 kernel automatically removed the timer when it
1681 expired, and we are now adding it back, thus 1681 expired, and we are now adding it back, thus
1682 leaving istimer wherever it was set before. 1682 leaving istimer wherever it was set before.
1683 */ 1683 */
1684 1684
1685 if (hmidi->istimer) { 1685 if (hmidi->istimer) {
1686 hmidi->timer.expires = 1 + jiffies; 1686 hmidi->timer.expires = 1 + jiffies;
1687 add_timer(&hmidi->timer); 1687 add_timer(&hmidi->timer);
1688 } 1688 }
1689 1689
1690 spin_unlock_irqrestore (&hmidi->lock, flags); 1690 spin_unlock_irqrestore (&hmidi->lock, flags);
1691 } 1691 }
1692 1692
1693 static void 1693 static void
1694 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 1694 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1695 { 1695 {
1696 struct hdspm_midi *hmidi; 1696 struct hdspm_midi *hmidi;
1697 unsigned long flags; 1697 unsigned long flags;
1698 1698
1699 hmidi = substream->rmidi->private_data; 1699 hmidi = substream->rmidi->private_data;
1700 spin_lock_irqsave (&hmidi->lock, flags); 1700 spin_lock_irqsave (&hmidi->lock, flags);
1701 if (up) { 1701 if (up) {
1702 if (!hmidi->istimer) { 1702 if (!hmidi->istimer) {
1703 init_timer(&hmidi->timer); 1703 init_timer(&hmidi->timer);
1704 hmidi->timer.function = snd_hdspm_midi_output_timer; 1704 hmidi->timer.function = snd_hdspm_midi_output_timer;
1705 hmidi->timer.data = (unsigned long) hmidi; 1705 hmidi->timer.data = (unsigned long) hmidi;
1706 hmidi->timer.expires = 1 + jiffies; 1706 hmidi->timer.expires = 1 + jiffies;
1707 add_timer(&hmidi->timer); 1707 add_timer(&hmidi->timer);
1708 hmidi->istimer++; 1708 hmidi->istimer++;
1709 } 1709 }
1710 } else { 1710 } else {
1711 if (hmidi->istimer && --hmidi->istimer <= 0) 1711 if (hmidi->istimer && --hmidi->istimer <= 0)
1712 del_timer (&hmidi->timer); 1712 del_timer (&hmidi->timer);
1713 } 1713 }
1714 spin_unlock_irqrestore (&hmidi->lock, flags); 1714 spin_unlock_irqrestore (&hmidi->lock, flags);
1715 if (up) 1715 if (up)
1716 snd_hdspm_midi_output_write(hmidi); 1716 snd_hdspm_midi_output_write(hmidi);
1717 } 1717 }
1718 1718
1719 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream) 1719 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1720 { 1720 {
1721 struct hdspm_midi *hmidi; 1721 struct hdspm_midi *hmidi;
1722 1722
1723 hmidi = substream->rmidi->private_data; 1723 hmidi = substream->rmidi->private_data;
1724 spin_lock_irq (&hmidi->lock); 1724 spin_lock_irq (&hmidi->lock);
1725 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id); 1725 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1726 hmidi->input = substream; 1726 hmidi->input = substream;
1727 spin_unlock_irq (&hmidi->lock); 1727 spin_unlock_irq (&hmidi->lock);
1728 1728
1729 return 0; 1729 return 0;
1730 } 1730 }
1731 1731
1732 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream) 1732 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
1733 { 1733 {
1734 struct hdspm_midi *hmidi; 1734 struct hdspm_midi *hmidi;
1735 1735
1736 hmidi = substream->rmidi->private_data; 1736 hmidi = substream->rmidi->private_data;
1737 spin_lock_irq (&hmidi->lock); 1737 spin_lock_irq (&hmidi->lock);
1738 hmidi->output = substream; 1738 hmidi->output = substream;
1739 spin_unlock_irq (&hmidi->lock); 1739 spin_unlock_irq (&hmidi->lock);
1740 1740
1741 return 0; 1741 return 0;
1742 } 1742 }
1743 1743
1744 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream) 1744 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
1745 { 1745 {
1746 struct hdspm_midi *hmidi; 1746 struct hdspm_midi *hmidi;
1747 1747
1748 snd_hdspm_midi_input_trigger (substream, 0); 1748 snd_hdspm_midi_input_trigger (substream, 0);
1749 1749
1750 hmidi = substream->rmidi->private_data; 1750 hmidi = substream->rmidi->private_data;
1751 spin_lock_irq (&hmidi->lock); 1751 spin_lock_irq (&hmidi->lock);
1752 hmidi->input = NULL; 1752 hmidi->input = NULL;
1753 spin_unlock_irq (&hmidi->lock); 1753 spin_unlock_irq (&hmidi->lock);
1754 1754
1755 return 0; 1755 return 0;
1756 } 1756 }
1757 1757
1758 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream) 1758 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
1759 { 1759 {
1760 struct hdspm_midi *hmidi; 1760 struct hdspm_midi *hmidi;
1761 1761
1762 snd_hdspm_midi_output_trigger (substream, 0); 1762 snd_hdspm_midi_output_trigger (substream, 0);
1763 1763
1764 hmidi = substream->rmidi->private_data; 1764 hmidi = substream->rmidi->private_data;
1765 spin_lock_irq (&hmidi->lock); 1765 spin_lock_irq (&hmidi->lock);
1766 hmidi->output = NULL; 1766 hmidi->output = NULL;
1767 spin_unlock_irq (&hmidi->lock); 1767 spin_unlock_irq (&hmidi->lock);
1768 1768
1769 return 0; 1769 return 0;
1770 } 1770 }
1771 1771
1772 static struct snd_rawmidi_ops snd_hdspm_midi_output = 1772 static struct snd_rawmidi_ops snd_hdspm_midi_output =
1773 { 1773 {
1774 .open = snd_hdspm_midi_output_open, 1774 .open = snd_hdspm_midi_output_open,
1775 .close = snd_hdspm_midi_output_close, 1775 .close = snd_hdspm_midi_output_close,
1776 .trigger = snd_hdspm_midi_output_trigger, 1776 .trigger = snd_hdspm_midi_output_trigger,
1777 }; 1777 };
1778 1778
1779 static struct snd_rawmidi_ops snd_hdspm_midi_input = 1779 static struct snd_rawmidi_ops snd_hdspm_midi_input =
1780 { 1780 {
1781 .open = snd_hdspm_midi_input_open, 1781 .open = snd_hdspm_midi_input_open,
1782 .close = snd_hdspm_midi_input_close, 1782 .close = snd_hdspm_midi_input_close,
1783 .trigger = snd_hdspm_midi_input_trigger, 1783 .trigger = snd_hdspm_midi_input_trigger,
1784 }; 1784 };
1785 1785
1786 static int __devinit snd_hdspm_create_midi (struct snd_card *card, 1786 static int __devinit snd_hdspm_create_midi (struct snd_card *card,
1787 struct hdspm *hdspm, int id) 1787 struct hdspm *hdspm, int id)
1788 { 1788 {
1789 int err; 1789 int err;
1790 char buf[32]; 1790 char buf[32];
1791 1791
1792 hdspm->midi[id].id = id; 1792 hdspm->midi[id].id = id;
1793 hdspm->midi[id].hdspm = hdspm; 1793 hdspm->midi[id].hdspm = hdspm;
1794 spin_lock_init (&hdspm->midi[id].lock); 1794 spin_lock_init (&hdspm->midi[id].lock);
1795 1795
1796 if (0 == id) { 1796 if (0 == id) {
1797 if (MADIface == hdspm->io_type) { 1797 if (MADIface == hdspm->io_type) {
1798 /* MIDI-over-MADI on HDSPe MADIface */ 1798 /* MIDI-over-MADI on HDSPe MADIface */
1799 hdspm->midi[0].dataIn = HDSPM_midiDataIn2; 1799 hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
1800 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2; 1800 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
1801 hdspm->midi[0].dataOut = HDSPM_midiDataOut2; 1801 hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
1802 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2; 1802 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
1803 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable; 1803 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
1804 hdspm->midi[0].irq = HDSPM_midi2IRQPending; 1804 hdspm->midi[0].irq = HDSPM_midi2IRQPending;
1805 } else { 1805 } else {
1806 hdspm->midi[0].dataIn = HDSPM_midiDataIn0; 1806 hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
1807 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0; 1807 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
1808 hdspm->midi[0].dataOut = HDSPM_midiDataOut0; 1808 hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
1809 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0; 1809 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
1810 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable; 1810 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
1811 hdspm->midi[0].irq = HDSPM_midi0IRQPending; 1811 hdspm->midi[0].irq = HDSPM_midi0IRQPending;
1812 } 1812 }
1813 } else if (1 == id) { 1813 } else if (1 == id) {
1814 hdspm->midi[1].dataIn = HDSPM_midiDataIn1; 1814 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
1815 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1; 1815 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
1816 hdspm->midi[1].dataOut = HDSPM_midiDataOut1; 1816 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
1817 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1; 1817 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
1818 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable; 1818 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
1819 hdspm->midi[1].irq = HDSPM_midi1IRQPending; 1819 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
1820 } else if ((2 == id) && (MADI == hdspm->io_type)) { 1820 } else if ((2 == id) && (MADI == hdspm->io_type)) {
1821 /* MIDI-over-MADI on HDSPe MADI */ 1821 /* MIDI-over-MADI on HDSPe MADI */
1822 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 1822 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1823 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 1823 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1824 hdspm->midi[2].dataOut = HDSPM_midiDataOut2; 1824 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
1825 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2; 1825 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
1826 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 1826 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1827 hdspm->midi[2].irq = HDSPM_midi2IRQPending; 1827 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
1828 } else if (2 == id) { 1828 } else if (2 == id) {
1829 /* TCO MTC, read only */ 1829 /* TCO MTC, read only */
1830 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 1830 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1831 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 1831 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1832 hdspm->midi[2].dataOut = -1; 1832 hdspm->midi[2].dataOut = -1;
1833 hdspm->midi[2].statusOut = -1; 1833 hdspm->midi[2].statusOut = -1;
1834 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 1834 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1835 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES; 1835 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
1836 } else if (3 == id) { 1836 } else if (3 == id) {
1837 /* TCO MTC on HDSPe MADI */ 1837 /* TCO MTC on HDSPe MADI */
1838 hdspm->midi[3].dataIn = HDSPM_midiDataIn3; 1838 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
1839 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3; 1839 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
1840 hdspm->midi[3].dataOut = -1; 1840 hdspm->midi[3].dataOut = -1;
1841 hdspm->midi[3].statusOut = -1; 1841 hdspm->midi[3].statusOut = -1;
1842 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable; 1842 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
1843 hdspm->midi[3].irq = HDSPM_midi3IRQPending; 1843 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
1844 } 1844 }
1845 1845
1846 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) || 1846 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
1847 (MADIface == hdspm->io_type)))) { 1847 (MADIface == hdspm->io_type)))) {
1848 if ((id == 0) && (MADIface == hdspm->io_type)) { 1848 if ((id == 0) && (MADIface == hdspm->io_type)) {
1849 sprintf(buf, "%s MIDIoverMADI", card->shortname); 1849 sprintf(buf, "%s MIDIoverMADI", card->shortname);
1850 } else if ((id == 2) && (MADI == hdspm->io_type)) { 1850 } else if ((id == 2) && (MADI == hdspm->io_type)) {
1851 sprintf(buf, "%s MIDIoverMADI", card->shortname); 1851 sprintf(buf, "%s MIDIoverMADI", card->shortname);
1852 } else { 1852 } else {
1853 sprintf(buf, "%s MIDI %d", card->shortname, id+1); 1853 sprintf(buf, "%s MIDI %d", card->shortname, id+1);
1854 } 1854 }
1855 err = snd_rawmidi_new(card, buf, id, 1, 1, 1855 err = snd_rawmidi_new(card, buf, id, 1, 1,
1856 &hdspm->midi[id].rmidi); 1856 &hdspm->midi[id].rmidi);
1857 if (err < 0) 1857 if (err < 0)
1858 return err; 1858 return err;
1859 1859
1860 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d", 1860 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
1861 card->id, id+1); 1861 card->id, id+1);
1862 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 1862 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1863 1863
1864 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 1864 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1865 SNDRV_RAWMIDI_STREAM_OUTPUT, 1865 SNDRV_RAWMIDI_STREAM_OUTPUT,
1866 &snd_hdspm_midi_output); 1866 &snd_hdspm_midi_output);
1867 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 1867 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1868 SNDRV_RAWMIDI_STREAM_INPUT, 1868 SNDRV_RAWMIDI_STREAM_INPUT,
1869 &snd_hdspm_midi_input); 1869 &snd_hdspm_midi_input);
1870 1870
1871 hdspm->midi[id].rmidi->info_flags |= 1871 hdspm->midi[id].rmidi->info_flags |=
1872 SNDRV_RAWMIDI_INFO_OUTPUT | 1872 SNDRV_RAWMIDI_INFO_OUTPUT |
1873 SNDRV_RAWMIDI_INFO_INPUT | 1873 SNDRV_RAWMIDI_INFO_INPUT |
1874 SNDRV_RAWMIDI_INFO_DUPLEX; 1874 SNDRV_RAWMIDI_INFO_DUPLEX;
1875 } else { 1875 } else {
1876 /* TCO MTC, read only */ 1876 /* TCO MTC, read only */
1877 sprintf(buf, "%s MTC %d", card->shortname, id+1); 1877 sprintf(buf, "%s MTC %d", card->shortname, id+1);
1878 err = snd_rawmidi_new(card, buf, id, 1, 1, 1878 err = snd_rawmidi_new(card, buf, id, 1, 1,
1879 &hdspm->midi[id].rmidi); 1879 &hdspm->midi[id].rmidi);
1880 if (err < 0) 1880 if (err < 0)
1881 return err; 1881 return err;
1882 1882
1883 sprintf(hdspm->midi[id].rmidi->name, 1883 sprintf(hdspm->midi[id].rmidi->name,
1884 "%s MTC %d", card->id, id+1); 1884 "%s MTC %d", card->id, id+1);
1885 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 1885 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1886 1886
1887 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 1887 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1888 SNDRV_RAWMIDI_STREAM_INPUT, 1888 SNDRV_RAWMIDI_STREAM_INPUT,
1889 &snd_hdspm_midi_input); 1889 &snd_hdspm_midi_input);
1890 1890
1891 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT; 1891 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
1892 } 1892 }
1893 1893
1894 return 0; 1894 return 0;
1895 } 1895 }
1896 1896
1897 1897
1898 static void hdspm_midi_tasklet(unsigned long arg) 1898 static void hdspm_midi_tasklet(unsigned long arg)
1899 { 1899 {
1900 struct hdspm *hdspm = (struct hdspm *)arg; 1900 struct hdspm *hdspm = (struct hdspm *)arg;
1901 int i = 0; 1901 int i = 0;
1902 1902
1903 while (i < hdspm->midiPorts) { 1903 while (i < hdspm->midiPorts) {
1904 if (hdspm->midi[i].pending) 1904 if (hdspm->midi[i].pending)
1905 snd_hdspm_midi_input_read(&hdspm->midi[i]); 1905 snd_hdspm_midi_input_read(&hdspm->midi[i]);
1906 1906
1907 i++; 1907 i++;
1908 } 1908 }
1909 } 1909 }
1910 1910
1911 1911
1912 /*----------------------------------------------------------------------------- 1912 /*-----------------------------------------------------------------------------
1913 Status Interface 1913 Status Interface
1914 ----------------------------------------------------------------------------*/ 1914 ----------------------------------------------------------------------------*/
1915 1915
1916 /* get the system sample rate which is set */ 1916 /* get the system sample rate which is set */
1917 1917
1918 1918
1919 /** 1919 /**
1920 * Calculate the real sample rate from the 1920 * Calculate the real sample rate from the
1921 * current DDS value. 1921 * current DDS value.
1922 **/ 1922 **/
1923 static int hdspm_get_system_sample_rate(struct hdspm *hdspm) 1923 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
1924 { 1924 {
1925 unsigned int period, rate; 1925 unsigned int period, rate;
1926 1926
1927 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 1927 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
1928 rate = hdspm_calc_dds_value(hdspm, period); 1928 rate = hdspm_calc_dds_value(hdspm, period);
1929 1929
1930 return rate; 1930 return rate;
1931 } 1931 }
1932 1932
1933 1933
1934 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \ 1934 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
1935 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1935 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1936 .name = xname, \ 1936 .name = xname, \
1937 .index = xindex, \ 1937 .index = xindex, \
1938 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1938 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1939 .info = snd_hdspm_info_system_sample_rate, \ 1939 .info = snd_hdspm_info_system_sample_rate, \
1940 .get = snd_hdspm_get_system_sample_rate \ 1940 .get = snd_hdspm_get_system_sample_rate \
1941 } 1941 }
1942 1942
1943 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol, 1943 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
1944 struct snd_ctl_elem_info *uinfo) 1944 struct snd_ctl_elem_info *uinfo)
1945 { 1945 {
1946 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1946 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1947 uinfo->count = 1; 1947 uinfo->count = 1;
1948 uinfo->value.integer.min = 27000; 1948 uinfo->value.integer.min = 27000;
1949 uinfo->value.integer.max = 207000; 1949 uinfo->value.integer.max = 207000;
1950 uinfo->value.integer.step = 1; 1950 uinfo->value.integer.step = 1;
1951 return 0; 1951 return 0;
1952 } 1952 }
1953 1953
1954 1954
1955 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol, 1955 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
1956 struct snd_ctl_elem_value * 1956 struct snd_ctl_elem_value *
1957 ucontrol) 1957 ucontrol)
1958 { 1958 {
1959 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 1959 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1960 1960
1961 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm); 1961 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
1962 return 0; 1962 return 0;
1963 } 1963 }
1964 1964
1965 1965
1966 /** 1966 /**
1967 * Returns the WordClock sample rate class for the given card. 1967 * Returns the WordClock sample rate class for the given card.
1968 **/ 1968 **/
1969 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm) 1969 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
1970 { 1970 {
1971 int status; 1971 int status;
1972 1972
1973 switch (hdspm->io_type) { 1973 switch (hdspm->io_type) {
1974 case RayDAT: 1974 case RayDAT:
1975 case AIO: 1975 case AIO:
1976 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 1976 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
1977 return (status >> 16) & 0xF; 1977 return (status >> 16) & 0xF;
1978 break; 1978 break;
1979 default: 1979 default:
1980 break; 1980 break;
1981 } 1981 }
1982 1982
1983 1983
1984 return 0; 1984 return 0;
1985 } 1985 }
1986 1986
1987 1987
1988 /** 1988 /**
1989 * Returns the TCO sample rate class for the given card. 1989 * Returns the TCO sample rate class for the given card.
1990 **/ 1990 **/
1991 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm) 1991 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
1992 { 1992 {
1993 int status; 1993 int status;
1994 1994
1995 if (hdspm->tco) { 1995 if (hdspm->tco) {
1996 switch (hdspm->io_type) { 1996 switch (hdspm->io_type) {
1997 case RayDAT: 1997 case RayDAT:
1998 case AIO: 1998 case AIO:
1999 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 1999 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2000 return (status >> 20) & 0xF; 2000 return (status >> 20) & 0xF;
2001 break; 2001 break;
2002 default: 2002 default:
2003 break; 2003 break;
2004 } 2004 }
2005 } 2005 }
2006 2006
2007 return 0; 2007 return 0;
2008 } 2008 }
2009 2009
2010 2010
2011 /** 2011 /**
2012 * Returns the SYNC_IN sample rate class for the given card. 2012 * Returns the SYNC_IN sample rate class for the given card.
2013 **/ 2013 **/
2014 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm) 2014 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2015 { 2015 {
2016 int status; 2016 int status;
2017 2017
2018 if (hdspm->tco) { 2018 if (hdspm->tco) {
2019 switch (hdspm->io_type) { 2019 switch (hdspm->io_type) {
2020 case RayDAT: 2020 case RayDAT:
2021 case AIO: 2021 case AIO:
2022 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2022 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2023 return (status >> 12) & 0xF; 2023 return (status >> 12) & 0xF;
2024 break; 2024 break;
2025 default: 2025 default:
2026 break; 2026 break;
2027 } 2027 }
2028 } 2028 }
2029 2029
2030 return 0; 2030 return 0;
2031 } 2031 }
2032 2032
2033 2033
2034 /** 2034 /**
2035 * Returns the sample rate class for input source <idx> for 2035 * Returns the sample rate class for input source <idx> for
2036 * 'new style' cards like the AIO and RayDAT. 2036 * 'new style' cards like the AIO and RayDAT.
2037 **/ 2037 **/
2038 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx) 2038 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2039 { 2039 {
2040 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2040 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2041 2041
2042 return (status >> (idx*4)) & 0xF; 2042 return (status >> (idx*4)) & 0xF;
2043 } 2043 }
2044 2044
2045 2045
2046 2046
2047 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \ 2047 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2048 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2048 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2049 .name = xname, \ 2049 .name = xname, \
2050 .private_value = xindex, \ 2050 .private_value = xindex, \
2051 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2051 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2052 .info = snd_hdspm_info_autosync_sample_rate, \ 2052 .info = snd_hdspm_info_autosync_sample_rate, \
2053 .get = snd_hdspm_get_autosync_sample_rate \ 2053 .get = snd_hdspm_get_autosync_sample_rate \
2054 } 2054 }
2055 2055
2056 2056
2057 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2057 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2058 struct snd_ctl_elem_info *uinfo) 2058 struct snd_ctl_elem_info *uinfo)
2059 { 2059 {
2060 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2060 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2061 uinfo->count = 1; 2061 uinfo->count = 1;
2062 uinfo->value.enumerated.items = 10; 2062 uinfo->value.enumerated.items = 10;
2063 2063
2064 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2064 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2065 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2065 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2066 strcpy(uinfo->value.enumerated.name, 2066 strcpy(uinfo->value.enumerated.name,
2067 texts_freq[uinfo->value.enumerated.item]); 2067 texts_freq[uinfo->value.enumerated.item]);
2068 return 0; 2068 return 0;
2069 } 2069 }
2070 2070
2071 2071
2072 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2072 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2073 struct snd_ctl_elem_value * 2073 struct snd_ctl_elem_value *
2074 ucontrol) 2074 ucontrol)
2075 { 2075 {
2076 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2076 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2077 2077
2078 switch (hdspm->io_type) { 2078 switch (hdspm->io_type) {
2079 case RayDAT: 2079 case RayDAT:
2080 switch (kcontrol->private_value) { 2080 switch (kcontrol->private_value) {
2081 case 0: 2081 case 0:
2082 ucontrol->value.enumerated.item[0] = 2082 ucontrol->value.enumerated.item[0] =
2083 hdspm_get_wc_sample_rate(hdspm); 2083 hdspm_get_wc_sample_rate(hdspm);
2084 break; 2084 break;
2085 case 7: 2085 case 7:
2086 ucontrol->value.enumerated.item[0] = 2086 ucontrol->value.enumerated.item[0] =
2087 hdspm_get_tco_sample_rate(hdspm); 2087 hdspm_get_tco_sample_rate(hdspm);
2088 break; 2088 break;
2089 case 8: 2089 case 8:
2090 ucontrol->value.enumerated.item[0] = 2090 ucontrol->value.enumerated.item[0] =
2091 hdspm_get_sync_in_sample_rate(hdspm); 2091 hdspm_get_sync_in_sample_rate(hdspm);
2092 break; 2092 break;
2093 default: 2093 default:
2094 ucontrol->value.enumerated.item[0] = 2094 ucontrol->value.enumerated.item[0] =
2095 hdspm_get_s1_sample_rate(hdspm, 2095 hdspm_get_s1_sample_rate(hdspm,
2096 kcontrol->private_value-1); 2096 kcontrol->private_value-1);
2097 } 2097 }
2098 2098
2099 case AIO: 2099 case AIO:
2100 switch (kcontrol->private_value) { 2100 switch (kcontrol->private_value) {
2101 case 0: /* WC */ 2101 case 0: /* WC */
2102 ucontrol->value.enumerated.item[0] = 2102 ucontrol->value.enumerated.item[0] =
2103 hdspm_get_wc_sample_rate(hdspm); 2103 hdspm_get_wc_sample_rate(hdspm);
2104 break; 2104 break;
2105 case 4: /* TCO */ 2105 case 4: /* TCO */
2106 ucontrol->value.enumerated.item[0] = 2106 ucontrol->value.enumerated.item[0] =
2107 hdspm_get_tco_sample_rate(hdspm); 2107 hdspm_get_tco_sample_rate(hdspm);
2108 break; 2108 break;
2109 case 5: /* SYNC_IN */ 2109 case 5: /* SYNC_IN */
2110 ucontrol->value.enumerated.item[0] = 2110 ucontrol->value.enumerated.item[0] =
2111 hdspm_get_sync_in_sample_rate(hdspm); 2111 hdspm_get_sync_in_sample_rate(hdspm);
2112 break; 2112 break;
2113 default: 2113 default:
2114 ucontrol->value.enumerated.item[0] = 2114 ucontrol->value.enumerated.item[0] =
2115 hdspm_get_s1_sample_rate(hdspm, 2115 hdspm_get_s1_sample_rate(hdspm,
2116 ucontrol->id.index-1); 2116 ucontrol->id.index-1);
2117 } 2117 }
2118 default: 2118 default:
2119 break; 2119 break;
2120 } 2120 }
2121 2121
2122 return 0; 2122 return 0;
2123 } 2123 }
2124 2124
2125 2125
2126 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \ 2126 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2127 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2127 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2128 .name = xname, \ 2128 .name = xname, \
2129 .index = xindex, \ 2129 .index = xindex, \
2130 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2130 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2131 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2131 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2132 .info = snd_hdspm_info_system_clock_mode, \ 2132 .info = snd_hdspm_info_system_clock_mode, \
2133 .get = snd_hdspm_get_system_clock_mode, \ 2133 .get = snd_hdspm_get_system_clock_mode, \
2134 .put = snd_hdspm_put_system_clock_mode, \ 2134 .put = snd_hdspm_put_system_clock_mode, \
2135 } 2135 }
2136 2136
2137 2137
2138 /** 2138 /**
2139 * Returns the system clock mode for the given card. 2139 * Returns the system clock mode for the given card.
2140 * @returns 0 - master, 1 - slave 2140 * @returns 0 - master, 1 - slave
2141 **/ 2141 **/
2142 static int hdspm_system_clock_mode(struct hdspm *hdspm) 2142 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2143 { 2143 {
2144 switch (hdspm->io_type) { 2144 switch (hdspm->io_type) {
2145 case AIO: 2145 case AIO:
2146 case RayDAT: 2146 case RayDAT:
2147 if (hdspm->settings_register & HDSPM_c0Master) 2147 if (hdspm->settings_register & HDSPM_c0Master)
2148 return 0; 2148 return 0;
2149 break; 2149 break;
2150 2150
2151 default: 2151 default:
2152 if (hdspm->control_register & HDSPM_ClockModeMaster) 2152 if (hdspm->control_register & HDSPM_ClockModeMaster)
2153 return 0; 2153 return 0;
2154 } 2154 }
2155 2155
2156 return 1; 2156 return 1;
2157 } 2157 }
2158 2158
2159 2159
2160 /** 2160 /**
2161 * Sets the system clock mode. 2161 * Sets the system clock mode.
2162 * @param mode 0 - master, 1 - slave 2162 * @param mode 0 - master, 1 - slave
2163 **/ 2163 **/
2164 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode) 2164 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2165 { 2165 {
2166 switch (hdspm->io_type) { 2166 switch (hdspm->io_type) {
2167 case AIO: 2167 case AIO:
2168 case RayDAT: 2168 case RayDAT:
2169 if (0 == mode) 2169 if (0 == mode)
2170 hdspm->settings_register |= HDSPM_c0Master; 2170 hdspm->settings_register |= HDSPM_c0Master;
2171 else 2171 else
2172 hdspm->settings_register &= ~HDSPM_c0Master; 2172 hdspm->settings_register &= ~HDSPM_c0Master;
2173 2173
2174 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 2174 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2175 break; 2175 break;
2176 2176
2177 default: 2177 default:
2178 if (0 == mode) 2178 if (0 == mode)
2179 hdspm->control_register |= HDSPM_ClockModeMaster; 2179 hdspm->control_register |= HDSPM_ClockModeMaster;
2180 else 2180 else
2181 hdspm->control_register &= ~HDSPM_ClockModeMaster; 2181 hdspm->control_register &= ~HDSPM_ClockModeMaster;
2182 2182
2183 hdspm_write(hdspm, HDSPM_controlRegister, 2183 hdspm_write(hdspm, HDSPM_controlRegister,
2184 hdspm->control_register); 2184 hdspm->control_register);
2185 } 2185 }
2186 } 2186 }
2187 2187
2188 2188
2189 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol, 2189 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2190 struct snd_ctl_elem_info *uinfo) 2190 struct snd_ctl_elem_info *uinfo)
2191 { 2191 {
2192 static char *texts[] = { "Master", "AutoSync" }; 2192 static char *texts[] = { "Master", "AutoSync" };
2193 2193
2194 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2194 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2195 uinfo->count = 1; 2195 uinfo->count = 1;
2196 uinfo->value.enumerated.items = 2; 2196 uinfo->value.enumerated.items = 2;
2197 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2197 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2198 uinfo->value.enumerated.item = 2198 uinfo->value.enumerated.item =
2199 uinfo->value.enumerated.items - 1; 2199 uinfo->value.enumerated.items - 1;
2200 strcpy(uinfo->value.enumerated.name, 2200 strcpy(uinfo->value.enumerated.name,
2201 texts[uinfo->value.enumerated.item]); 2201 texts[uinfo->value.enumerated.item]);
2202 return 0; 2202 return 0;
2203 } 2203 }
2204 2204
2205 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol, 2205 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2206 struct snd_ctl_elem_value *ucontrol) 2206 struct snd_ctl_elem_value *ucontrol)
2207 { 2207 {
2208 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2208 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2209 2209
2210 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm); 2210 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2211 return 0; 2211 return 0;
2212 } 2212 }
2213 2213
2214 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol, 2214 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2215 struct snd_ctl_elem_value *ucontrol) 2215 struct snd_ctl_elem_value *ucontrol)
2216 { 2216 {
2217 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2217 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2218 int val; 2218 int val;
2219 2219
2220 if (!snd_hdspm_use_is_exclusive(hdspm)) 2220 if (!snd_hdspm_use_is_exclusive(hdspm))
2221 return -EBUSY; 2221 return -EBUSY;
2222 2222
2223 val = ucontrol->value.enumerated.item[0]; 2223 val = ucontrol->value.enumerated.item[0];
2224 if (val < 0) 2224 if (val < 0)
2225 val = 0; 2225 val = 0;
2226 else if (val > 1) 2226 else if (val > 1)
2227 val = 1; 2227 val = 1;
2228 2228
2229 hdspm_set_system_clock_mode(hdspm, val); 2229 hdspm_set_system_clock_mode(hdspm, val);
2230 2230
2231 return 0; 2231 return 0;
2232 } 2232 }
2233 2233
2234 2234
2235 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \ 2235 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2236 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2236 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2237 .name = xname, \ 2237 .name = xname, \
2238 .index = xindex, \ 2238 .index = xindex, \
2239 .info = snd_hdspm_info_clock_source, \ 2239 .info = snd_hdspm_info_clock_source, \
2240 .get = snd_hdspm_get_clock_source, \ 2240 .get = snd_hdspm_get_clock_source, \
2241 .put = snd_hdspm_put_clock_source \ 2241 .put = snd_hdspm_put_clock_source \
2242 } 2242 }
2243 2243
2244 2244
2245 static int hdspm_clock_source(struct hdspm * hdspm) 2245 static int hdspm_clock_source(struct hdspm * hdspm)
2246 { 2246 {
2247 switch (hdspm->system_sample_rate) { 2247 switch (hdspm->system_sample_rate) {
2248 case 32000: return 0; 2248 case 32000: return 0;
2249 case 44100: return 1; 2249 case 44100: return 1;
2250 case 48000: return 2; 2250 case 48000: return 2;
2251 case 64000: return 3; 2251 case 64000: return 3;
2252 case 88200: return 4; 2252 case 88200: return 4;
2253 case 96000: return 5; 2253 case 96000: return 5;
2254 case 128000: return 6; 2254 case 128000: return 6;
2255 case 176400: return 7; 2255 case 176400: return 7;
2256 case 192000: return 8; 2256 case 192000: return 8;
2257 } 2257 }
2258 2258
2259 return -1; 2259 return -1;
2260 } 2260 }
2261 2261
2262 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode) 2262 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2263 { 2263 {
2264 int rate; 2264 int rate;
2265 switch (mode) { 2265 switch (mode) {
2266 case 0: 2266 case 0:
2267 rate = 32000; break; 2267 rate = 32000; break;
2268 case 1: 2268 case 1:
2269 rate = 44100; break; 2269 rate = 44100; break;
2270 case 2: 2270 case 2:
2271 rate = 48000; break; 2271 rate = 48000; break;
2272 case 3: 2272 case 3:
2273 rate = 64000; break; 2273 rate = 64000; break;
2274 case 4: 2274 case 4:
2275 rate = 88200; break; 2275 rate = 88200; break;
2276 case 5: 2276 case 5:
2277 rate = 96000; break; 2277 rate = 96000; break;
2278 case 6: 2278 case 6:
2279 rate = 128000; break; 2279 rate = 128000; break;
2280 case 7: 2280 case 7:
2281 rate = 176400; break; 2281 rate = 176400; break;
2282 case 8: 2282 case 8:
2283 rate = 192000; break; 2283 rate = 192000; break;
2284 default: 2284 default:
2285 rate = 48000; 2285 rate = 48000;
2286 } 2286 }
2287 hdspm_set_rate(hdspm, rate, 1); 2287 hdspm_set_rate(hdspm, rate, 1);
2288 return 0; 2288 return 0;
2289 } 2289 }
2290 2290
2291 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol, 2291 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2292 struct snd_ctl_elem_info *uinfo) 2292 struct snd_ctl_elem_info *uinfo)
2293 { 2293 {
2294 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2294 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2295 uinfo->count = 1; 2295 uinfo->count = 1;
2296 uinfo->value.enumerated.items = 9; 2296 uinfo->value.enumerated.items = 9;
2297 2297
2298 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2298 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2299 uinfo->value.enumerated.item = 2299 uinfo->value.enumerated.item =
2300 uinfo->value.enumerated.items - 1; 2300 uinfo->value.enumerated.items - 1;
2301 2301
2302 strcpy(uinfo->value.enumerated.name, 2302 strcpy(uinfo->value.enumerated.name,
2303 texts_freq[uinfo->value.enumerated.item+1]); 2303 texts_freq[uinfo->value.enumerated.item+1]);
2304 2304
2305 return 0; 2305 return 0;
2306 } 2306 }
2307 2307
2308 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol, 2308 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2309 struct snd_ctl_elem_value *ucontrol) 2309 struct snd_ctl_elem_value *ucontrol)
2310 { 2310 {
2311 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2311 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2312 2312
2313 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm); 2313 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2314 return 0; 2314 return 0;
2315 } 2315 }
2316 2316
2317 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol, 2317 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2318 struct snd_ctl_elem_value *ucontrol) 2318 struct snd_ctl_elem_value *ucontrol)
2319 { 2319 {
2320 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2320 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2321 int change; 2321 int change;
2322 int val; 2322 int val;
2323 2323
2324 if (!snd_hdspm_use_is_exclusive(hdspm)) 2324 if (!snd_hdspm_use_is_exclusive(hdspm))
2325 return -EBUSY; 2325 return -EBUSY;
2326 val = ucontrol->value.enumerated.item[0]; 2326 val = ucontrol->value.enumerated.item[0];
2327 if (val < 0) 2327 if (val < 0)
2328 val = 0; 2328 val = 0;
2329 if (val > 9) 2329 if (val > 9)
2330 val = 9; 2330 val = 9;
2331 spin_lock_irq(&hdspm->lock); 2331 spin_lock_irq(&hdspm->lock);
2332 if (val != hdspm_clock_source(hdspm)) 2332 if (val != hdspm_clock_source(hdspm))
2333 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0; 2333 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2334 else 2334 else
2335 change = 0; 2335 change = 0;
2336 spin_unlock_irq(&hdspm->lock); 2336 spin_unlock_irq(&hdspm->lock);
2337 return change; 2337 return change;
2338 } 2338 }
2339 2339
2340 2340
2341 #define HDSPM_PREF_SYNC_REF(xname, xindex) \ 2341 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2342 {.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2342 {.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2343 .name = xname, \ 2343 .name = xname, \
2344 .index = xindex, \ 2344 .index = xindex, \
2345 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2345 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2346 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2346 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2347 .info = snd_hdspm_info_pref_sync_ref, \ 2347 .info = snd_hdspm_info_pref_sync_ref, \
2348 .get = snd_hdspm_get_pref_sync_ref, \ 2348 .get = snd_hdspm_get_pref_sync_ref, \
2349 .put = snd_hdspm_put_pref_sync_ref \ 2349 .put = snd_hdspm_put_pref_sync_ref \
2350 } 2350 }
2351 2351
2352 2352
2353 /** 2353 /**
2354 * Returns the current preferred sync reference setting. 2354 * Returns the current preferred sync reference setting.
2355 * The semantics of the return value are depending on the 2355 * The semantics of the return value are depending on the
2356 * card, please see the comments for clarification. 2356 * card, please see the comments for clarification.
2357 **/ 2357 **/
2358 static int hdspm_pref_sync_ref(struct hdspm * hdspm) 2358 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2359 { 2359 {
2360 switch (hdspm->io_type) { 2360 switch (hdspm->io_type) {
2361 case AES32: 2361 case AES32:
2362 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2362 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2363 case 0: return 0; /* WC */ 2363 case 0: return 0; /* WC */
2364 case HDSPM_SyncRef0: return 1; /* AES 1 */ 2364 case HDSPM_SyncRef0: return 1; /* AES 1 */
2365 case HDSPM_SyncRef1: return 2; /* AES 2 */ 2365 case HDSPM_SyncRef1: return 2; /* AES 2 */
2366 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */ 2366 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2367 case HDSPM_SyncRef2: return 4; /* AES 4 */ 2367 case HDSPM_SyncRef2: return 4; /* AES 4 */
2368 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */ 2368 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2369 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */ 2369 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2370 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0: 2370 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2371 return 7; /* AES 7 */ 2371 return 7; /* AES 7 */
2372 case HDSPM_SyncRef3: return 8; /* AES 8 */ 2372 case HDSPM_SyncRef3: return 8; /* AES 8 */
2373 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */ 2373 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2374 } 2374 }
2375 break; 2375 break;
2376 2376
2377 case MADI: 2377 case MADI:
2378 case MADIface: 2378 case MADIface:
2379 if (hdspm->tco) { 2379 if (hdspm->tco) {
2380 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2380 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2381 case 0: return 0; /* WC */ 2381 case 0: return 0; /* WC */
2382 case HDSPM_SyncRef0: return 1; /* MADI */ 2382 case HDSPM_SyncRef0: return 1; /* MADI */
2383 case HDSPM_SyncRef1: return 2; /* TCO */ 2383 case HDSPM_SyncRef1: return 2; /* TCO */
2384 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2384 case HDSPM_SyncRef1+HDSPM_SyncRef0:
2385 return 3; /* SYNC_IN */ 2385 return 3; /* SYNC_IN */
2386 } 2386 }
2387 } else { 2387 } else {
2388 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2388 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2389 case 0: return 0; /* WC */ 2389 case 0: return 0; /* WC */
2390 case HDSPM_SyncRef0: return 1; /* MADI */ 2390 case HDSPM_SyncRef0: return 1; /* MADI */
2391 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2391 case HDSPM_SyncRef1+HDSPM_SyncRef0:
2392 return 2; /* SYNC_IN */ 2392 return 2; /* SYNC_IN */
2393 } 2393 }
2394 } 2394 }
2395 break; 2395 break;
2396 2396
2397 case RayDAT: 2397 case RayDAT:
2398 if (hdspm->tco) { 2398 if (hdspm->tco) {
2399 switch ((hdspm->settings_register & 2399 switch ((hdspm->settings_register &
2400 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2400 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2401 case 0: return 0; /* WC */ 2401 case 0: return 0; /* WC */
2402 case 3: return 1; /* ADAT 1 */ 2402 case 3: return 1; /* ADAT 1 */
2403 case 4: return 2; /* ADAT 2 */ 2403 case 4: return 2; /* ADAT 2 */
2404 case 5: return 3; /* ADAT 3 */ 2404 case 5: return 3; /* ADAT 3 */
2405 case 6: return 4; /* ADAT 4 */ 2405 case 6: return 4; /* ADAT 4 */
2406 case 1: return 5; /* AES */ 2406 case 1: return 5; /* AES */
2407 case 2: return 6; /* SPDIF */ 2407 case 2: return 6; /* SPDIF */
2408 case 9: return 7; /* TCO */ 2408 case 9: return 7; /* TCO */
2409 case 10: return 8; /* SYNC_IN */ 2409 case 10: return 8; /* SYNC_IN */
2410 } 2410 }
2411 } else { 2411 } else {
2412 switch ((hdspm->settings_register & 2412 switch ((hdspm->settings_register &
2413 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2413 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2414 case 0: return 0; /* WC */ 2414 case 0: return 0; /* WC */
2415 case 3: return 1; /* ADAT 1 */ 2415 case 3: return 1; /* ADAT 1 */
2416 case 4: return 2; /* ADAT 2 */ 2416 case 4: return 2; /* ADAT 2 */
2417 case 5: return 3; /* ADAT 3 */ 2417 case 5: return 3; /* ADAT 3 */
2418 case 6: return 4; /* ADAT 4 */ 2418 case 6: return 4; /* ADAT 4 */
2419 case 1: return 5; /* AES */ 2419 case 1: return 5; /* AES */
2420 case 2: return 6; /* SPDIF */ 2420 case 2: return 6; /* SPDIF */
2421 case 10: return 7; /* SYNC_IN */ 2421 case 10: return 7; /* SYNC_IN */
2422 } 2422 }
2423 } 2423 }
2424 2424
2425 break; 2425 break;
2426 2426
2427 case AIO: 2427 case AIO:
2428 if (hdspm->tco) { 2428 if (hdspm->tco) {
2429 switch ((hdspm->settings_register & 2429 switch ((hdspm->settings_register &
2430 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2430 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2431 case 0: return 0; /* WC */ 2431 case 0: return 0; /* WC */
2432 case 3: return 1; /* ADAT */ 2432 case 3: return 1; /* ADAT */
2433 case 1: return 2; /* AES */ 2433 case 1: return 2; /* AES */
2434 case 2: return 3; /* SPDIF */ 2434 case 2: return 3; /* SPDIF */
2435 case 9: return 4; /* TCO */ 2435 case 9: return 4; /* TCO */
2436 case 10: return 5; /* SYNC_IN */ 2436 case 10: return 5; /* SYNC_IN */
2437 } 2437 }
2438 } else { 2438 } else {
2439 switch ((hdspm->settings_register & 2439 switch ((hdspm->settings_register &
2440 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2440 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2441 case 0: return 0; /* WC */ 2441 case 0: return 0; /* WC */
2442 case 3: return 1; /* ADAT */ 2442 case 3: return 1; /* ADAT */
2443 case 1: return 2; /* AES */ 2443 case 1: return 2; /* AES */
2444 case 2: return 3; /* SPDIF */ 2444 case 2: return 3; /* SPDIF */
2445 case 10: return 4; /* SYNC_IN */ 2445 case 10: return 4; /* SYNC_IN */
2446 } 2446 }
2447 } 2447 }
2448 2448
2449 break; 2449 break;
2450 } 2450 }
2451 2451
2452 return -1; 2452 return -1;
2453 } 2453 }
2454 2454
2455 2455
2456 /** 2456 /**
2457 * Set the preferred sync reference to <pref>. The semantics 2457 * Set the preferred sync reference to <pref>. The semantics
2458 * of <pref> are depending on the card type, see the comments 2458 * of <pref> are depending on the card type, see the comments
2459 * for clarification. 2459 * for clarification.
2460 **/ 2460 **/
2461 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref) 2461 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2462 { 2462 {
2463 int p = 0; 2463 int p = 0;
2464 2464
2465 switch (hdspm->io_type) { 2465 switch (hdspm->io_type) {
2466 case AES32: 2466 case AES32:
2467 hdspm->control_register &= ~HDSPM_SyncRefMask; 2467 hdspm->control_register &= ~HDSPM_SyncRefMask;
2468 switch (pref) { 2468 switch (pref) {
2469 case 0: /* WC */ 2469 case 0: /* WC */
2470 break; 2470 break;
2471 case 1: /* AES 1 */ 2471 case 1: /* AES 1 */
2472 hdspm->control_register |= HDSPM_SyncRef0; 2472 hdspm->control_register |= HDSPM_SyncRef0;
2473 break; 2473 break;
2474 case 2: /* AES 2 */ 2474 case 2: /* AES 2 */
2475 hdspm->control_register |= HDSPM_SyncRef1; 2475 hdspm->control_register |= HDSPM_SyncRef1;
2476 break; 2476 break;
2477 case 3: /* AES 3 */ 2477 case 3: /* AES 3 */
2478 hdspm->control_register |= 2478 hdspm->control_register |=
2479 HDSPM_SyncRef1+HDSPM_SyncRef0; 2479 HDSPM_SyncRef1+HDSPM_SyncRef0;
2480 break; 2480 break;
2481 case 4: /* AES 4 */ 2481 case 4: /* AES 4 */
2482 hdspm->control_register |= HDSPM_SyncRef2; 2482 hdspm->control_register |= HDSPM_SyncRef2;
2483 break; 2483 break;
2484 case 5: /* AES 5 */ 2484 case 5: /* AES 5 */
2485 hdspm->control_register |= 2485 hdspm->control_register |=
2486 HDSPM_SyncRef2+HDSPM_SyncRef0; 2486 HDSPM_SyncRef2+HDSPM_SyncRef0;
2487 break; 2487 break;
2488 case 6: /* AES 6 */ 2488 case 6: /* AES 6 */
2489 hdspm->control_register |= 2489 hdspm->control_register |=
2490 HDSPM_SyncRef2+HDSPM_SyncRef1; 2490 HDSPM_SyncRef2+HDSPM_SyncRef1;
2491 break; 2491 break;
2492 case 7: /* AES 7 */ 2492 case 7: /* AES 7 */
2493 hdspm->control_register |= 2493 hdspm->control_register |=
2494 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0; 2494 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2495 break; 2495 break;
2496 case 8: /* AES 8 */ 2496 case 8: /* AES 8 */
2497 hdspm->control_register |= HDSPM_SyncRef3; 2497 hdspm->control_register |= HDSPM_SyncRef3;
2498 break; 2498 break;
2499 case 9: /* TCO */ 2499 case 9: /* TCO */
2500 hdspm->control_register |= 2500 hdspm->control_register |=
2501 HDSPM_SyncRef3+HDSPM_SyncRef0; 2501 HDSPM_SyncRef3+HDSPM_SyncRef0;
2502 break; 2502 break;
2503 default: 2503 default:
2504 return -1; 2504 return -1;
2505 } 2505 }
2506 2506
2507 break; 2507 break;
2508 2508
2509 case MADI: 2509 case MADI:
2510 case MADIface: 2510 case MADIface:
2511 hdspm->control_register &= ~HDSPM_SyncRefMask; 2511 hdspm->control_register &= ~HDSPM_SyncRefMask;
2512 if (hdspm->tco) { 2512 if (hdspm->tco) {
2513 switch (pref) { 2513 switch (pref) {
2514 case 0: /* WC */ 2514 case 0: /* WC */
2515 break; 2515 break;
2516 case 1: /* MADI */ 2516 case 1: /* MADI */
2517 hdspm->control_register |= HDSPM_SyncRef0; 2517 hdspm->control_register |= HDSPM_SyncRef0;
2518 break; 2518 break;
2519 case 2: /* TCO */ 2519 case 2: /* TCO */
2520 hdspm->control_register |= HDSPM_SyncRef1; 2520 hdspm->control_register |= HDSPM_SyncRef1;
2521 break; 2521 break;
2522 case 3: /* SYNC_IN */ 2522 case 3: /* SYNC_IN */
2523 hdspm->control_register |= 2523 hdspm->control_register |=
2524 HDSPM_SyncRef0+HDSPM_SyncRef1; 2524 HDSPM_SyncRef0+HDSPM_SyncRef1;
2525 break; 2525 break;
2526 default: 2526 default:
2527 return -1; 2527 return -1;
2528 } 2528 }
2529 } else { 2529 } else {
2530 switch (pref) { 2530 switch (pref) {
2531 case 0: /* WC */ 2531 case 0: /* WC */
2532 break; 2532 break;
2533 case 1: /* MADI */ 2533 case 1: /* MADI */
2534 hdspm->control_register |= HDSPM_SyncRef0; 2534 hdspm->control_register |= HDSPM_SyncRef0;
2535 break; 2535 break;
2536 case 2: /* SYNC_IN */ 2536 case 2: /* SYNC_IN */
2537 hdspm->control_register |= 2537 hdspm->control_register |=
2538 HDSPM_SyncRef0+HDSPM_SyncRef1; 2538 HDSPM_SyncRef0+HDSPM_SyncRef1;
2539 break; 2539 break;
2540 default: 2540 default:
2541 return -1; 2541 return -1;
2542 } 2542 }
2543 } 2543 }
2544 2544
2545 break; 2545 break;
2546 2546
2547 case RayDAT: 2547 case RayDAT:
2548 if (hdspm->tco) { 2548 if (hdspm->tco) {
2549 switch (pref) { 2549 switch (pref) {
2550 case 0: p = 0; break; /* WC */ 2550 case 0: p = 0; break; /* WC */
2551 case 1: p = 3; break; /* ADAT 1 */ 2551 case 1: p = 3; break; /* ADAT 1 */
2552 case 2: p = 4; break; /* ADAT 2 */ 2552 case 2: p = 4; break; /* ADAT 2 */
2553 case 3: p = 5; break; /* ADAT 3 */ 2553 case 3: p = 5; break; /* ADAT 3 */
2554 case 4: p = 6; break; /* ADAT 4 */ 2554 case 4: p = 6; break; /* ADAT 4 */
2555 case 5: p = 1; break; /* AES */ 2555 case 5: p = 1; break; /* AES */
2556 case 6: p = 2; break; /* SPDIF */ 2556 case 6: p = 2; break; /* SPDIF */
2557 case 7: p = 9; break; /* TCO */ 2557 case 7: p = 9; break; /* TCO */
2558 case 8: p = 10; break; /* SYNC_IN */ 2558 case 8: p = 10; break; /* SYNC_IN */
2559 default: return -1; 2559 default: return -1;
2560 } 2560 }
2561 } else { 2561 } else {
2562 switch (pref) { 2562 switch (pref) {
2563 case 0: p = 0; break; /* WC */ 2563 case 0: p = 0; break; /* WC */
2564 case 1: p = 3; break; /* ADAT 1 */ 2564 case 1: p = 3; break; /* ADAT 1 */
2565 case 2: p = 4; break; /* ADAT 2 */ 2565 case 2: p = 4; break; /* ADAT 2 */
2566 case 3: p = 5; break; /* ADAT 3 */ 2566 case 3: p = 5; break; /* ADAT 3 */
2567 case 4: p = 6; break; /* ADAT 4 */ 2567 case 4: p = 6; break; /* ADAT 4 */
2568 case 5: p = 1; break; /* AES */ 2568 case 5: p = 1; break; /* AES */
2569 case 6: p = 2; break; /* SPDIF */ 2569 case 6: p = 2; break; /* SPDIF */
2570 case 7: p = 10; break; /* SYNC_IN */ 2570 case 7: p = 10; break; /* SYNC_IN */
2571 default: return -1; 2571 default: return -1;
2572 } 2572 }
2573 } 2573 }
2574 break; 2574 break;
2575 2575
2576 case AIO: 2576 case AIO:
2577 if (hdspm->tco) { 2577 if (hdspm->tco) {
2578 switch (pref) { 2578 switch (pref) {
2579 case 0: p = 0; break; /* WC */ 2579 case 0: p = 0; break; /* WC */
2580 case 1: p = 3; break; /* ADAT */ 2580 case 1: p = 3; break; /* ADAT */
2581 case 2: p = 1; break; /* AES */ 2581 case 2: p = 1; break; /* AES */
2582 case 3: p = 2; break; /* SPDIF */ 2582 case 3: p = 2; break; /* SPDIF */
2583 case 4: p = 9; break; /* TCO */ 2583 case 4: p = 9; break; /* TCO */
2584 case 5: p = 10; break; /* SYNC_IN */ 2584 case 5: p = 10; break; /* SYNC_IN */
2585 default: return -1; 2585 default: return -1;
2586 } 2586 }
2587 } else { 2587 } else {
2588 switch (pref) { 2588 switch (pref) {
2589 case 0: p = 0; break; /* WC */ 2589 case 0: p = 0; break; /* WC */
2590 case 1: p = 3; break; /* ADAT */ 2590 case 1: p = 3; break; /* ADAT */
2591 case 2: p = 1; break; /* AES */ 2591 case 2: p = 1; break; /* AES */
2592 case 3: p = 2; break; /* SPDIF */ 2592 case 3: p = 2; break; /* SPDIF */
2593 case 4: p = 10; break; /* SYNC_IN */ 2593 case 4: p = 10; break; /* SYNC_IN */
2594 default: return -1; 2594 default: return -1;
2595 } 2595 }
2596 } 2596 }
2597 break; 2597 break;
2598 } 2598 }
2599 2599
2600 switch (hdspm->io_type) { 2600 switch (hdspm->io_type) {
2601 case RayDAT: 2601 case RayDAT:
2602 case AIO: 2602 case AIO:
2603 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask; 2603 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2604 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p; 2604 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2605 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 2605 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2606 break; 2606 break;
2607 2607
2608 case MADI: 2608 case MADI:
2609 case MADIface: 2609 case MADIface:
2610 case AES32: 2610 case AES32:
2611 hdspm_write(hdspm, HDSPM_controlRegister, 2611 hdspm_write(hdspm, HDSPM_controlRegister,
2612 hdspm->control_register); 2612 hdspm->control_register);
2613 } 2613 }
2614 2614
2615 return 0; 2615 return 0;
2616 } 2616 }
2617 2617
2618 2618
2619 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol, 2619 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2620 struct snd_ctl_elem_info *uinfo) 2620 struct snd_ctl_elem_info *uinfo)
2621 { 2621 {
2622 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2622 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2623 2623
2624 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2624 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2625 uinfo->count = 1; 2625 uinfo->count = 1;
2626 uinfo->value.enumerated.items = hdspm->texts_autosync_items; 2626 uinfo->value.enumerated.items = hdspm->texts_autosync_items;
2627 2627
2628 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2628 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2629 uinfo->value.enumerated.item = 2629 uinfo->value.enumerated.item =
2630 uinfo->value.enumerated.items - 1; 2630 uinfo->value.enumerated.items - 1;
2631 2631
2632 strcpy(uinfo->value.enumerated.name, 2632 strcpy(uinfo->value.enumerated.name,
2633 hdspm->texts_autosync[uinfo->value.enumerated.item]); 2633 hdspm->texts_autosync[uinfo->value.enumerated.item]);
2634 2634
2635 return 0; 2635 return 0;
2636 } 2636 }
2637 2637
2638 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol, 2638 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2639 struct snd_ctl_elem_value *ucontrol) 2639 struct snd_ctl_elem_value *ucontrol)
2640 { 2640 {
2641 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2641 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2642 int psf = hdspm_pref_sync_ref(hdspm); 2642 int psf = hdspm_pref_sync_ref(hdspm);
2643 2643
2644 if (psf >= 0) { 2644 if (psf >= 0) {
2645 ucontrol->value.enumerated.item[0] = psf; 2645 ucontrol->value.enumerated.item[0] = psf;
2646 return 0; 2646 return 0;
2647 } 2647 }
2648 2648
2649 return -1; 2649 return -1;
2650 } 2650 }
2651 2651
2652 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol, 2652 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2653 struct snd_ctl_elem_value *ucontrol) 2653 struct snd_ctl_elem_value *ucontrol)
2654 { 2654 {
2655 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2655 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2656 int val, change = 0; 2656 int val, change = 0;
2657 2657
2658 if (!snd_hdspm_use_is_exclusive(hdspm)) 2658 if (!snd_hdspm_use_is_exclusive(hdspm))
2659 return -EBUSY; 2659 return -EBUSY;
2660 2660
2661 val = ucontrol->value.enumerated.item[0]; 2661 val = ucontrol->value.enumerated.item[0];
2662 2662
2663 if (val < 0) 2663 if (val < 0)
2664 val = 0; 2664 val = 0;
2665 else if (val >= hdspm->texts_autosync_items) 2665 else if (val >= hdspm->texts_autosync_items)
2666 val = hdspm->texts_autosync_items-1; 2666 val = hdspm->texts_autosync_items-1;
2667 2667
2668 spin_lock_irq(&hdspm->lock); 2668 spin_lock_irq(&hdspm->lock);
2669 if (val != hdspm_pref_sync_ref(hdspm)) 2669 if (val != hdspm_pref_sync_ref(hdspm))
2670 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0; 2670 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
2671 2671
2672 spin_unlock_irq(&hdspm->lock); 2672 spin_unlock_irq(&hdspm->lock);
2673 return change; 2673 return change;
2674 } 2674 }
2675 2675
2676 2676
2677 #define HDSPM_AUTOSYNC_REF(xname, xindex) \ 2677 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
2678 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2678 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2679 .name = xname, \ 2679 .name = xname, \
2680 .index = xindex, \ 2680 .index = xindex, \
2681 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2681 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2682 .info = snd_hdspm_info_autosync_ref, \ 2682 .info = snd_hdspm_info_autosync_ref, \
2683 .get = snd_hdspm_get_autosync_ref, \ 2683 .get = snd_hdspm_get_autosync_ref, \
2684 } 2684 }
2685 2685
2686 static int hdspm_autosync_ref(struct hdspm *hdspm) 2686 static int hdspm_autosync_ref(struct hdspm *hdspm)
2687 { 2687 {
2688 if (AES32 == hdspm->io_type) { 2688 if (AES32 == hdspm->io_type) {
2689 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister); 2689 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
2690 unsigned int syncref = 2690 unsigned int syncref =
2691 (status >> HDSPM_AES32_syncref_bit) & 0xF; 2691 (status >> HDSPM_AES32_syncref_bit) & 0xF;
2692 if (syncref == 0) 2692 if (syncref == 0)
2693 return HDSPM_AES32_AUTOSYNC_FROM_WORD; 2693 return HDSPM_AES32_AUTOSYNC_FROM_WORD;
2694 if (syncref <= 8) 2694 if (syncref <= 8)
2695 return syncref; 2695 return syncref;
2696 return HDSPM_AES32_AUTOSYNC_FROM_NONE; 2696 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
2697 } else if (MADI == hdspm->io_type) { 2697 } else if (MADI == hdspm->io_type) {
2698 /* This looks at the autosync selected sync reference */ 2698 /* This looks at the autosync selected sync reference */
2699 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 2699 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2700 2700
2701 switch (status2 & HDSPM_SelSyncRefMask) { 2701 switch (status2 & HDSPM_SelSyncRefMask) {
2702 case HDSPM_SelSyncRef_WORD: 2702 case HDSPM_SelSyncRef_WORD:
2703 return HDSPM_AUTOSYNC_FROM_WORD; 2703 return HDSPM_AUTOSYNC_FROM_WORD;
2704 case HDSPM_SelSyncRef_MADI: 2704 case HDSPM_SelSyncRef_MADI:
2705 return HDSPM_AUTOSYNC_FROM_MADI; 2705 return HDSPM_AUTOSYNC_FROM_MADI;
2706 case HDSPM_SelSyncRef_TCO: 2706 case HDSPM_SelSyncRef_TCO:
2707 return HDSPM_AUTOSYNC_FROM_TCO; 2707 return HDSPM_AUTOSYNC_FROM_TCO;
2708 case HDSPM_SelSyncRef_SyncIn: 2708 case HDSPM_SelSyncRef_SyncIn:
2709 return HDSPM_AUTOSYNC_FROM_SYNC_IN; 2709 return HDSPM_AUTOSYNC_FROM_SYNC_IN;
2710 case HDSPM_SelSyncRef_NVALID: 2710 case HDSPM_SelSyncRef_NVALID:
2711 return HDSPM_AUTOSYNC_FROM_NONE; 2711 return HDSPM_AUTOSYNC_FROM_NONE;
2712 default: 2712 default:
2713 return 0; 2713 return 0;
2714 } 2714 }
2715 2715
2716 } 2716 }
2717 return 0; 2717 return 0;
2718 } 2718 }
2719 2719
2720 2720
2721 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol, 2721 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
2722 struct snd_ctl_elem_info *uinfo) 2722 struct snd_ctl_elem_info *uinfo)
2723 { 2723 {
2724 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2724 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2725 2725
2726 if (AES32 == hdspm->io_type) { 2726 if (AES32 == hdspm->io_type) {
2727 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3", 2727 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3",
2728 "AES4", "AES5", "AES6", "AES7", "AES8", "None"}; 2728 "AES4", "AES5", "AES6", "AES7", "AES8", "None"};
2729 2729
2730 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2730 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2731 uinfo->count = 1; 2731 uinfo->count = 1;
2732 uinfo->value.enumerated.items = 10; 2732 uinfo->value.enumerated.items = 10;
2733 if (uinfo->value.enumerated.item >= 2733 if (uinfo->value.enumerated.item >=
2734 uinfo->value.enumerated.items) 2734 uinfo->value.enumerated.items)
2735 uinfo->value.enumerated.item = 2735 uinfo->value.enumerated.item =
2736 uinfo->value.enumerated.items - 1; 2736 uinfo->value.enumerated.items - 1;
2737 strcpy(uinfo->value.enumerated.name, 2737 strcpy(uinfo->value.enumerated.name,
2738 texts[uinfo->value.enumerated.item]); 2738 texts[uinfo->value.enumerated.item]);
2739 } else if (MADI == hdspm->io_type) { 2739 } else if (MADI == hdspm->io_type) {
2740 static char *texts[] = {"Word Clock", "MADI", "TCO", 2740 static char *texts[] = {"Word Clock", "MADI", "TCO",
2741 "Sync In", "None" }; 2741 "Sync In", "None" };
2742 2742
2743 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2743 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2744 uinfo->count = 1; 2744 uinfo->count = 1;
2745 uinfo->value.enumerated.items = 5; 2745 uinfo->value.enumerated.items = 5;
2746 if (uinfo->value.enumerated.item >= 2746 if (uinfo->value.enumerated.item >=
2747 uinfo->value.enumerated.items) 2747 uinfo->value.enumerated.items)
2748 uinfo->value.enumerated.item = 2748 uinfo->value.enumerated.item =
2749 uinfo->value.enumerated.items - 1; 2749 uinfo->value.enumerated.items - 1;
2750 strcpy(uinfo->value.enumerated.name, 2750 strcpy(uinfo->value.enumerated.name,
2751 texts[uinfo->value.enumerated.item]); 2751 texts[uinfo->value.enumerated.item]);
2752 } 2752 }
2753 return 0; 2753 return 0;
2754 } 2754 }
2755 2755
2756 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol, 2756 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
2757 struct snd_ctl_elem_value *ucontrol) 2757 struct snd_ctl_elem_value *ucontrol)
2758 { 2758 {
2759 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2759 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2760 2760
2761 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm); 2761 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
2762 return 0; 2762 return 0;
2763 } 2763 }
2764 2764
2765 2765
2766 #define HDSPM_LINE_OUT(xname, xindex) \ 2766 #define HDSPM_LINE_OUT(xname, xindex) \
2767 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2767 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2768 .name = xname, \ 2768 .name = xname, \
2769 .index = xindex, \ 2769 .index = xindex, \
2770 .info = snd_hdspm_info_line_out, \ 2770 .info = snd_hdspm_info_line_out, \
2771 .get = snd_hdspm_get_line_out, \ 2771 .get = snd_hdspm_get_line_out, \
2772 .put = snd_hdspm_put_line_out \ 2772 .put = snd_hdspm_put_line_out \
2773 } 2773 }
2774 2774
2775 static int hdspm_line_out(struct hdspm * hdspm) 2775 static int hdspm_line_out(struct hdspm * hdspm)
2776 { 2776 {
2777 return (hdspm->control_register & HDSPM_LineOut) ? 1 : 0; 2777 return (hdspm->control_register & HDSPM_LineOut) ? 1 : 0;
2778 } 2778 }
2779 2779
2780 2780
2781 static int hdspm_set_line_output(struct hdspm * hdspm, int out) 2781 static int hdspm_set_line_output(struct hdspm * hdspm, int out)
2782 { 2782 {
2783 if (out) 2783 if (out)
2784 hdspm->control_register |= HDSPM_LineOut; 2784 hdspm->control_register |= HDSPM_LineOut;
2785 else 2785 else
2786 hdspm->control_register &= ~HDSPM_LineOut; 2786 hdspm->control_register &= ~HDSPM_LineOut;
2787 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 2787 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2788 2788
2789 return 0; 2789 return 0;
2790 } 2790 }
2791 2791
2792 #define snd_hdspm_info_line_out snd_ctl_boolean_mono_info 2792 #define snd_hdspm_info_line_out snd_ctl_boolean_mono_info
2793 2793
2794 static int snd_hdspm_get_line_out(struct snd_kcontrol *kcontrol, 2794 static int snd_hdspm_get_line_out(struct snd_kcontrol *kcontrol,
2795 struct snd_ctl_elem_value *ucontrol) 2795 struct snd_ctl_elem_value *ucontrol)
2796 { 2796 {
2797 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2797 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2798 2798
2799 spin_lock_irq(&hdspm->lock); 2799 spin_lock_irq(&hdspm->lock);
2800 ucontrol->value.integer.value[0] = hdspm_line_out(hdspm); 2800 ucontrol->value.integer.value[0] = hdspm_line_out(hdspm);
2801 spin_unlock_irq(&hdspm->lock); 2801 spin_unlock_irq(&hdspm->lock);
2802 return 0; 2802 return 0;
2803 } 2803 }
2804 2804
2805 static int snd_hdspm_put_line_out(struct snd_kcontrol *kcontrol, 2805 static int snd_hdspm_put_line_out(struct snd_kcontrol *kcontrol,
2806 struct snd_ctl_elem_value *ucontrol) 2806 struct snd_ctl_elem_value *ucontrol)
2807 { 2807 {
2808 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2808 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2809 int change; 2809 int change;
2810 unsigned int val; 2810 unsigned int val;
2811 2811
2812 if (!snd_hdspm_use_is_exclusive(hdspm)) 2812 if (!snd_hdspm_use_is_exclusive(hdspm))
2813 return -EBUSY; 2813 return -EBUSY;
2814 val = ucontrol->value.integer.value[0] & 1; 2814 val = ucontrol->value.integer.value[0] & 1;
2815 spin_lock_irq(&hdspm->lock); 2815 spin_lock_irq(&hdspm->lock);
2816 change = (int) val != hdspm_line_out(hdspm); 2816 change = (int) val != hdspm_line_out(hdspm);
2817 hdspm_set_line_output(hdspm, val); 2817 hdspm_set_line_output(hdspm, val);
2818 spin_unlock_irq(&hdspm->lock); 2818 spin_unlock_irq(&hdspm->lock);
2819 return change; 2819 return change;
2820 } 2820 }
2821 2821
2822 2822
2823 #define HDSPM_TX_64(xname, xindex) \ 2823 #define HDSPM_TX_64(xname, xindex) \
2824 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2824 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2825 .name = xname, \ 2825 .name = xname, \
2826 .index = xindex, \ 2826 .index = xindex, \
2827 .info = snd_hdspm_info_tx_64, \ 2827 .info = snd_hdspm_info_tx_64, \
2828 .get = snd_hdspm_get_tx_64, \ 2828 .get = snd_hdspm_get_tx_64, \
2829 .put = snd_hdspm_put_tx_64 \ 2829 .put = snd_hdspm_put_tx_64 \
2830 } 2830 }
2831 2831
2832 static int hdspm_tx_64(struct hdspm * hdspm) 2832 static int hdspm_tx_64(struct hdspm * hdspm)
2833 { 2833 {
2834 return (hdspm->control_register & HDSPM_TX_64ch) ? 1 : 0; 2834 return (hdspm->control_register & HDSPM_TX_64ch) ? 1 : 0;
2835 } 2835 }
2836 2836
2837 static int hdspm_set_tx_64(struct hdspm * hdspm, int out) 2837 static int hdspm_set_tx_64(struct hdspm * hdspm, int out)
2838 { 2838 {
2839 if (out) 2839 if (out)
2840 hdspm->control_register |= HDSPM_TX_64ch; 2840 hdspm->control_register |= HDSPM_TX_64ch;
2841 else 2841 else
2842 hdspm->control_register &= ~HDSPM_TX_64ch; 2842 hdspm->control_register &= ~HDSPM_TX_64ch;
2843 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 2843 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2844 2844
2845 return 0; 2845 return 0;
2846 } 2846 }
2847 2847
2848 #define snd_hdspm_info_tx_64 snd_ctl_boolean_mono_info 2848 #define snd_hdspm_info_tx_64 snd_ctl_boolean_mono_info
2849 2849
2850 static int snd_hdspm_get_tx_64(struct snd_kcontrol *kcontrol, 2850 static int snd_hdspm_get_tx_64(struct snd_kcontrol *kcontrol,
2851 struct snd_ctl_elem_value *ucontrol) 2851 struct snd_ctl_elem_value *ucontrol)
2852 { 2852 {
2853 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2853 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2854 2854
2855 spin_lock_irq(&hdspm->lock); 2855 spin_lock_irq(&hdspm->lock);
2856 ucontrol->value.integer.value[0] = hdspm_tx_64(hdspm); 2856 ucontrol->value.integer.value[0] = hdspm_tx_64(hdspm);
2857 spin_unlock_irq(&hdspm->lock); 2857 spin_unlock_irq(&hdspm->lock);
2858 return 0; 2858 return 0;
2859 } 2859 }
2860 2860
2861 static int snd_hdspm_put_tx_64(struct snd_kcontrol *kcontrol, 2861 static int snd_hdspm_put_tx_64(struct snd_kcontrol *kcontrol,
2862 struct snd_ctl_elem_value *ucontrol) 2862 struct snd_ctl_elem_value *ucontrol)
2863 { 2863 {
2864 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2864 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2865 int change; 2865 int change;
2866 unsigned int val; 2866 unsigned int val;
2867 2867
2868 if (!snd_hdspm_use_is_exclusive(hdspm)) 2868 if (!snd_hdspm_use_is_exclusive(hdspm))
2869 return -EBUSY; 2869 return -EBUSY;
2870 val = ucontrol->value.integer.value[0] & 1; 2870 val = ucontrol->value.integer.value[0] & 1;
2871 spin_lock_irq(&hdspm->lock); 2871 spin_lock_irq(&hdspm->lock);
2872 change = (int) val != hdspm_tx_64(hdspm); 2872 change = (int) val != hdspm_tx_64(hdspm);
2873 hdspm_set_tx_64(hdspm, val); 2873 hdspm_set_tx_64(hdspm, val);
2874 spin_unlock_irq(&hdspm->lock); 2874 spin_unlock_irq(&hdspm->lock);
2875 return change; 2875 return change;
2876 } 2876 }
2877 2877
2878 2878
2879 #define HDSPM_C_TMS(xname, xindex) \ 2879 #define HDSPM_C_TMS(xname, xindex) \
2880 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2880 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2881 .name = xname, \ 2881 .name = xname, \
2882 .index = xindex, \ 2882 .index = xindex, \
2883 .info = snd_hdspm_info_c_tms, \ 2883 .info = snd_hdspm_info_c_tms, \
2884 .get = snd_hdspm_get_c_tms, \ 2884 .get = snd_hdspm_get_c_tms, \
2885 .put = snd_hdspm_put_c_tms \ 2885 .put = snd_hdspm_put_c_tms \
2886 } 2886 }
2887 2887
2888 static int hdspm_c_tms(struct hdspm * hdspm) 2888 static int hdspm_c_tms(struct hdspm * hdspm)
2889 { 2889 {
2890 return (hdspm->control_register & HDSPM_clr_tms) ? 1 : 0; 2890 return (hdspm->control_register & HDSPM_clr_tms) ? 1 : 0;
2891 } 2891 }
2892 2892
2893 static int hdspm_set_c_tms(struct hdspm * hdspm, int out) 2893 static int hdspm_set_c_tms(struct hdspm * hdspm, int out)
2894 { 2894 {
2895 if (out) 2895 if (out)
2896 hdspm->control_register |= HDSPM_clr_tms; 2896 hdspm->control_register |= HDSPM_clr_tms;
2897 else 2897 else
2898 hdspm->control_register &= ~HDSPM_clr_tms; 2898 hdspm->control_register &= ~HDSPM_clr_tms;
2899 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 2899 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2900 2900
2901 return 0; 2901 return 0;
2902 } 2902 }
2903 2903
2904 #define snd_hdspm_info_c_tms snd_ctl_boolean_mono_info 2904 #define snd_hdspm_info_c_tms snd_ctl_boolean_mono_info
2905 2905
2906 static int snd_hdspm_get_c_tms(struct snd_kcontrol *kcontrol, 2906 static int snd_hdspm_get_c_tms(struct snd_kcontrol *kcontrol,
2907 struct snd_ctl_elem_value *ucontrol) 2907 struct snd_ctl_elem_value *ucontrol)
2908 { 2908 {
2909 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2909 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2910 2910
2911 spin_lock_irq(&hdspm->lock); 2911 spin_lock_irq(&hdspm->lock);
2912 ucontrol->value.integer.value[0] = hdspm_c_tms(hdspm); 2912 ucontrol->value.integer.value[0] = hdspm_c_tms(hdspm);
2913 spin_unlock_irq(&hdspm->lock); 2913 spin_unlock_irq(&hdspm->lock);
2914 return 0; 2914 return 0;
2915 } 2915 }
2916 2916
2917 static int snd_hdspm_put_c_tms(struct snd_kcontrol *kcontrol, 2917 static int snd_hdspm_put_c_tms(struct snd_kcontrol *kcontrol,
2918 struct snd_ctl_elem_value *ucontrol) 2918 struct snd_ctl_elem_value *ucontrol)
2919 { 2919 {
2920 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2920 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2921 int change; 2921 int change;
2922 unsigned int val; 2922 unsigned int val;
2923 2923
2924 if (!snd_hdspm_use_is_exclusive(hdspm)) 2924 if (!snd_hdspm_use_is_exclusive(hdspm))
2925 return -EBUSY; 2925 return -EBUSY;
2926 val = ucontrol->value.integer.value[0] & 1; 2926 val = ucontrol->value.integer.value[0] & 1;
2927 spin_lock_irq(&hdspm->lock); 2927 spin_lock_irq(&hdspm->lock);
2928 change = (int) val != hdspm_c_tms(hdspm); 2928 change = (int) val != hdspm_c_tms(hdspm);
2929 hdspm_set_c_tms(hdspm, val); 2929 hdspm_set_c_tms(hdspm, val);
2930 spin_unlock_irq(&hdspm->lock); 2930 spin_unlock_irq(&hdspm->lock);
2931 return change; 2931 return change;
2932 } 2932 }
2933 2933
2934 2934
2935 #define HDSPM_SAFE_MODE(xname, xindex) \ 2935 #define HDSPM_SAFE_MODE(xname, xindex) \
2936 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2936 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2937 .name = xname, \ 2937 .name = xname, \
2938 .index = xindex, \ 2938 .index = xindex, \
2939 .info = snd_hdspm_info_safe_mode, \ 2939 .info = snd_hdspm_info_safe_mode, \
2940 .get = snd_hdspm_get_safe_mode, \ 2940 .get = snd_hdspm_get_safe_mode, \
2941 .put = snd_hdspm_put_safe_mode \ 2941 .put = snd_hdspm_put_safe_mode \
2942 } 2942 }
2943 2943
2944 static int hdspm_safe_mode(struct hdspm * hdspm) 2944 static int hdspm_safe_mode(struct hdspm * hdspm)
2945 { 2945 {
2946 return (hdspm->control_register & HDSPM_AutoInp) ? 1 : 0; 2946 return (hdspm->control_register & HDSPM_AutoInp) ? 1 : 0;
2947 } 2947 }
2948 2948
2949 static int hdspm_set_safe_mode(struct hdspm * hdspm, int out) 2949 static int hdspm_set_safe_mode(struct hdspm * hdspm, int out)
2950 { 2950 {
2951 if (out) 2951 if (out)
2952 hdspm->control_register |= HDSPM_AutoInp; 2952 hdspm->control_register |= HDSPM_AutoInp;
2953 else 2953 else
2954 hdspm->control_register &= ~HDSPM_AutoInp; 2954 hdspm->control_register &= ~HDSPM_AutoInp;
2955 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 2955 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2956 2956
2957 return 0; 2957 return 0;
2958 } 2958 }
2959 2959
2960 #define snd_hdspm_info_safe_mode snd_ctl_boolean_mono_info 2960 #define snd_hdspm_info_safe_mode snd_ctl_boolean_mono_info
2961 2961
2962 static int snd_hdspm_get_safe_mode(struct snd_kcontrol *kcontrol, 2962 static int snd_hdspm_get_safe_mode(struct snd_kcontrol *kcontrol,
2963 struct snd_ctl_elem_value *ucontrol) 2963 struct snd_ctl_elem_value *ucontrol)
2964 { 2964 {
2965 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2965 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2966 2966
2967 spin_lock_irq(&hdspm->lock); 2967 spin_lock_irq(&hdspm->lock);
2968 ucontrol->value.integer.value[0] = hdspm_safe_mode(hdspm); 2968 ucontrol->value.integer.value[0] = hdspm_safe_mode(hdspm);
2969 spin_unlock_irq(&hdspm->lock); 2969 spin_unlock_irq(&hdspm->lock);
2970 return 0; 2970 return 0;
2971 } 2971 }
2972 2972
2973 static int snd_hdspm_put_safe_mode(struct snd_kcontrol *kcontrol, 2973 static int snd_hdspm_put_safe_mode(struct snd_kcontrol *kcontrol,
2974 struct snd_ctl_elem_value *ucontrol) 2974 struct snd_ctl_elem_value *ucontrol)
2975 { 2975 {
2976 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2976 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2977 int change; 2977 int change;
2978 unsigned int val; 2978 unsigned int val;
2979 2979
2980 if (!snd_hdspm_use_is_exclusive(hdspm)) 2980 if (!snd_hdspm_use_is_exclusive(hdspm))
2981 return -EBUSY; 2981 return -EBUSY;
2982 val = ucontrol->value.integer.value[0] & 1; 2982 val = ucontrol->value.integer.value[0] & 1;
2983 spin_lock_irq(&hdspm->lock); 2983 spin_lock_irq(&hdspm->lock);
2984 change = (int) val != hdspm_safe_mode(hdspm); 2984 change = (int) val != hdspm_safe_mode(hdspm);
2985 hdspm_set_safe_mode(hdspm, val); 2985 hdspm_set_safe_mode(hdspm, val);
2986 spin_unlock_irq(&hdspm->lock); 2986 spin_unlock_irq(&hdspm->lock);
2987 return change; 2987 return change;
2988 } 2988 }
2989 2989
2990 2990
2991 #define HDSPM_EMPHASIS(xname, xindex) \ 2991 #define HDSPM_EMPHASIS(xname, xindex) \
2992 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2992 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2993 .name = xname, \ 2993 .name = xname, \
2994 .index = xindex, \ 2994 .index = xindex, \
2995 .info = snd_hdspm_info_emphasis, \ 2995 .info = snd_hdspm_info_emphasis, \
2996 .get = snd_hdspm_get_emphasis, \ 2996 .get = snd_hdspm_get_emphasis, \
2997 .put = snd_hdspm_put_emphasis \ 2997 .put = snd_hdspm_put_emphasis \
2998 } 2998 }
2999 2999
3000 static int hdspm_emphasis(struct hdspm * hdspm) 3000 static int hdspm_emphasis(struct hdspm * hdspm)
3001 { 3001 {
3002 return (hdspm->control_register & HDSPM_Emphasis) ? 1 : 0; 3002 return (hdspm->control_register & HDSPM_Emphasis) ? 1 : 0;
3003 } 3003 }
3004 3004
3005 static int hdspm_set_emphasis(struct hdspm * hdspm, int emp) 3005 static int hdspm_set_emphasis(struct hdspm * hdspm, int emp)
3006 { 3006 {
3007 if (emp) 3007 if (emp)
3008 hdspm->control_register |= HDSPM_Emphasis; 3008 hdspm->control_register |= HDSPM_Emphasis;
3009 else 3009 else
3010 hdspm->control_register &= ~HDSPM_Emphasis; 3010 hdspm->control_register &= ~HDSPM_Emphasis;
3011 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3011 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3012 3012
3013 return 0; 3013 return 0;
3014 } 3014 }
3015 3015
3016 #define snd_hdspm_info_emphasis snd_ctl_boolean_mono_info 3016 #define snd_hdspm_info_emphasis snd_ctl_boolean_mono_info
3017 3017
3018 static int snd_hdspm_get_emphasis(struct snd_kcontrol *kcontrol, 3018 static int snd_hdspm_get_emphasis(struct snd_kcontrol *kcontrol,
3019 struct snd_ctl_elem_value *ucontrol) 3019 struct snd_ctl_elem_value *ucontrol)
3020 { 3020 {
3021 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3021 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3022 3022
3023 spin_lock_irq(&hdspm->lock); 3023 spin_lock_irq(&hdspm->lock);
3024 ucontrol->value.enumerated.item[0] = hdspm_emphasis(hdspm); 3024 ucontrol->value.enumerated.item[0] = hdspm_emphasis(hdspm);
3025 spin_unlock_irq(&hdspm->lock); 3025 spin_unlock_irq(&hdspm->lock);
3026 return 0; 3026 return 0;
3027 } 3027 }
3028 3028
3029 static int snd_hdspm_put_emphasis(struct snd_kcontrol *kcontrol, 3029 static int snd_hdspm_put_emphasis(struct snd_kcontrol *kcontrol,
3030 struct snd_ctl_elem_value *ucontrol) 3030 struct snd_ctl_elem_value *ucontrol)
3031 { 3031 {
3032 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3032 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3033 int change; 3033 int change;
3034 unsigned int val; 3034 unsigned int val;
3035 3035
3036 if (!snd_hdspm_use_is_exclusive(hdspm)) 3036 if (!snd_hdspm_use_is_exclusive(hdspm))
3037 return -EBUSY; 3037 return -EBUSY;
3038 val = ucontrol->value.integer.value[0] & 1; 3038 val = ucontrol->value.integer.value[0] & 1;
3039 spin_lock_irq(&hdspm->lock); 3039 spin_lock_irq(&hdspm->lock);
3040 change = (int) val != hdspm_emphasis(hdspm); 3040 change = (int) val != hdspm_emphasis(hdspm);
3041 hdspm_set_emphasis(hdspm, val); 3041 hdspm_set_emphasis(hdspm, val);
3042 spin_unlock_irq(&hdspm->lock); 3042 spin_unlock_irq(&hdspm->lock);
3043 return change; 3043 return change;
3044 } 3044 }
3045 3045
3046 3046
3047 #define HDSPM_DOLBY(xname, xindex) \ 3047 #define HDSPM_DOLBY(xname, xindex) \
3048 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3048 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3049 .name = xname, \ 3049 .name = xname, \
3050 .index = xindex, \ 3050 .index = xindex, \
3051 .info = snd_hdspm_info_dolby, \ 3051 .info = snd_hdspm_info_dolby, \
3052 .get = snd_hdspm_get_dolby, \ 3052 .get = snd_hdspm_get_dolby, \
3053 .put = snd_hdspm_put_dolby \ 3053 .put = snd_hdspm_put_dolby \
3054 } 3054 }
3055 3055
3056 static int hdspm_dolby(struct hdspm * hdspm) 3056 static int hdspm_dolby(struct hdspm * hdspm)
3057 { 3057 {
3058 return (hdspm->control_register & HDSPM_Dolby) ? 1 : 0; 3058 return (hdspm->control_register & HDSPM_Dolby) ? 1 : 0;
3059 } 3059 }
3060 3060
3061 static int hdspm_set_dolby(struct hdspm * hdspm, int dol) 3061 static int hdspm_set_dolby(struct hdspm * hdspm, int dol)
3062 { 3062 {
3063 if (dol) 3063 if (dol)
3064 hdspm->control_register |= HDSPM_Dolby; 3064 hdspm->control_register |= HDSPM_Dolby;
3065 else 3065 else
3066 hdspm->control_register &= ~HDSPM_Dolby; 3066 hdspm->control_register &= ~HDSPM_Dolby;
3067 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3067 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3068 3068
3069 return 0; 3069 return 0;
3070 } 3070 }
3071 3071
3072 #define snd_hdspm_info_dolby snd_ctl_boolean_mono_info 3072 #define snd_hdspm_info_dolby snd_ctl_boolean_mono_info
3073 3073
3074 static int snd_hdspm_get_dolby(struct snd_kcontrol *kcontrol, 3074 static int snd_hdspm_get_dolby(struct snd_kcontrol *kcontrol,
3075 struct snd_ctl_elem_value *ucontrol) 3075 struct snd_ctl_elem_value *ucontrol)
3076 { 3076 {
3077 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3077 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3078 3078
3079 spin_lock_irq(&hdspm->lock); 3079 spin_lock_irq(&hdspm->lock);
3080 ucontrol->value.enumerated.item[0] = hdspm_dolby(hdspm); 3080 ucontrol->value.enumerated.item[0] = hdspm_dolby(hdspm);
3081 spin_unlock_irq(&hdspm->lock); 3081 spin_unlock_irq(&hdspm->lock);
3082 return 0; 3082 return 0;
3083 } 3083 }
3084 3084
3085 static int snd_hdspm_put_dolby(struct snd_kcontrol *kcontrol, 3085 static int snd_hdspm_put_dolby(struct snd_kcontrol *kcontrol,
3086 struct snd_ctl_elem_value *ucontrol) 3086 struct snd_ctl_elem_value *ucontrol)
3087 { 3087 {
3088 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3088 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3089 int change; 3089 int change;
3090 unsigned int val; 3090 unsigned int val;
3091 3091
3092 if (!snd_hdspm_use_is_exclusive(hdspm)) 3092 if (!snd_hdspm_use_is_exclusive(hdspm))
3093 return -EBUSY; 3093 return -EBUSY;
3094 val = ucontrol->value.integer.value[0] & 1; 3094 val = ucontrol->value.integer.value[0] & 1;
3095 spin_lock_irq(&hdspm->lock); 3095 spin_lock_irq(&hdspm->lock);
3096 change = (int) val != hdspm_dolby(hdspm); 3096 change = (int) val != hdspm_dolby(hdspm);
3097 hdspm_set_dolby(hdspm, val); 3097 hdspm_set_dolby(hdspm, val);
3098 spin_unlock_irq(&hdspm->lock); 3098 spin_unlock_irq(&hdspm->lock);
3099 return change; 3099 return change;
3100 } 3100 }
3101 3101
3102 3102
3103 #define HDSPM_PROFESSIONAL(xname, xindex) \ 3103 #define HDSPM_PROFESSIONAL(xname, xindex) \
3104 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3104 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3105 .name = xname, \ 3105 .name = xname, \
3106 .index = xindex, \ 3106 .index = xindex, \
3107 .info = snd_hdspm_info_professional, \ 3107 .info = snd_hdspm_info_professional, \
3108 .get = snd_hdspm_get_professional, \ 3108 .get = snd_hdspm_get_professional, \
3109 .put = snd_hdspm_put_professional \ 3109 .put = snd_hdspm_put_professional \
3110 } 3110 }
3111 3111
3112 static int hdspm_professional(struct hdspm * hdspm) 3112 static int hdspm_professional(struct hdspm * hdspm)
3113 { 3113 {
3114 return (hdspm->control_register & HDSPM_Professional) ? 1 : 0; 3114 return (hdspm->control_register & HDSPM_Professional) ? 1 : 0;
3115 } 3115 }
3116 3116
3117 static int hdspm_set_professional(struct hdspm * hdspm, int dol) 3117 static int hdspm_set_professional(struct hdspm * hdspm, int dol)
3118 { 3118 {
3119 if (dol) 3119 if (dol)
3120 hdspm->control_register |= HDSPM_Professional; 3120 hdspm->control_register |= HDSPM_Professional;
3121 else 3121 else
3122 hdspm->control_register &= ~HDSPM_Professional; 3122 hdspm->control_register &= ~HDSPM_Professional;
3123 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3123 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3124 3124
3125 return 0; 3125 return 0;
3126 } 3126 }
3127 3127
3128 #define snd_hdspm_info_professional snd_ctl_boolean_mono_info 3128 #define snd_hdspm_info_professional snd_ctl_boolean_mono_info
3129 3129
3130 static int snd_hdspm_get_professional(struct snd_kcontrol *kcontrol, 3130 static int snd_hdspm_get_professional(struct snd_kcontrol *kcontrol,
3131 struct snd_ctl_elem_value *ucontrol) 3131 struct snd_ctl_elem_value *ucontrol)
3132 { 3132 {
3133 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3133 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3134 3134
3135 spin_lock_irq(&hdspm->lock); 3135 spin_lock_irq(&hdspm->lock);
3136 ucontrol->value.enumerated.item[0] = hdspm_professional(hdspm); 3136 ucontrol->value.enumerated.item[0] = hdspm_professional(hdspm);
3137 spin_unlock_irq(&hdspm->lock); 3137 spin_unlock_irq(&hdspm->lock);
3138 return 0; 3138 return 0;
3139 } 3139 }
3140 3140
3141 static int snd_hdspm_put_professional(struct snd_kcontrol *kcontrol, 3141 static int snd_hdspm_put_professional(struct snd_kcontrol *kcontrol,
3142 struct snd_ctl_elem_value *ucontrol) 3142 struct snd_ctl_elem_value *ucontrol)
3143 { 3143 {
3144 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3144 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3145 int change; 3145 int change;
3146 unsigned int val; 3146 unsigned int val;
3147 3147
3148 if (!snd_hdspm_use_is_exclusive(hdspm)) 3148 if (!snd_hdspm_use_is_exclusive(hdspm))
3149 return -EBUSY; 3149 return -EBUSY;
3150 val = ucontrol->value.integer.value[0] & 1; 3150 val = ucontrol->value.integer.value[0] & 1;
3151 spin_lock_irq(&hdspm->lock); 3151 spin_lock_irq(&hdspm->lock);
3152 change = (int) val != hdspm_professional(hdspm); 3152 change = (int) val != hdspm_professional(hdspm);
3153 hdspm_set_professional(hdspm, val); 3153 hdspm_set_professional(hdspm, val);
3154 spin_unlock_irq(&hdspm->lock); 3154 spin_unlock_irq(&hdspm->lock);
3155 return change; 3155 return change;
3156 } 3156 }
3157 3157
3158 #define HDSPM_INPUT_SELECT(xname, xindex) \ 3158 #define HDSPM_INPUT_SELECT(xname, xindex) \
3159 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3159 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3160 .name = xname, \ 3160 .name = xname, \
3161 .index = xindex, \ 3161 .index = xindex, \
3162 .info = snd_hdspm_info_input_select, \ 3162 .info = snd_hdspm_info_input_select, \
3163 .get = snd_hdspm_get_input_select, \ 3163 .get = snd_hdspm_get_input_select, \
3164 .put = snd_hdspm_put_input_select \ 3164 .put = snd_hdspm_put_input_select \
3165 } 3165 }
3166 3166
3167 static int hdspm_input_select(struct hdspm * hdspm) 3167 static int hdspm_input_select(struct hdspm * hdspm)
3168 { 3168 {
3169 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0; 3169 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3170 } 3170 }
3171 3171
3172 static int hdspm_set_input_select(struct hdspm * hdspm, int out) 3172 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3173 { 3173 {
3174 if (out) 3174 if (out)
3175 hdspm->control_register |= HDSPM_InputSelect0; 3175 hdspm->control_register |= HDSPM_InputSelect0;
3176 else 3176 else
3177 hdspm->control_register &= ~HDSPM_InputSelect0; 3177 hdspm->control_register &= ~HDSPM_InputSelect0;
3178 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3178 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3179 3179
3180 return 0; 3180 return 0;
3181 } 3181 }
3182 3182
3183 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol, 3183 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3184 struct snd_ctl_elem_info *uinfo) 3184 struct snd_ctl_elem_info *uinfo)
3185 { 3185 {
3186 static char *texts[] = { "optical", "coaxial" }; 3186 static char *texts[] = { "optical", "coaxial" };
3187 3187
3188 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3188 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3189 uinfo->count = 1; 3189 uinfo->count = 1;
3190 uinfo->value.enumerated.items = 2; 3190 uinfo->value.enumerated.items = 2;
3191 3191
3192 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3192 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3193 uinfo->value.enumerated.item = 3193 uinfo->value.enumerated.item =
3194 uinfo->value.enumerated.items - 1; 3194 uinfo->value.enumerated.items - 1;
3195 strcpy(uinfo->value.enumerated.name, 3195 strcpy(uinfo->value.enumerated.name,
3196 texts[uinfo->value.enumerated.item]); 3196 texts[uinfo->value.enumerated.item]);
3197 3197
3198 return 0; 3198 return 0;
3199 } 3199 }
3200 3200
3201 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol, 3201 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3202 struct snd_ctl_elem_value *ucontrol) 3202 struct snd_ctl_elem_value *ucontrol)
3203 { 3203 {
3204 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3204 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3205 3205
3206 spin_lock_irq(&hdspm->lock); 3206 spin_lock_irq(&hdspm->lock);
3207 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm); 3207 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3208 spin_unlock_irq(&hdspm->lock); 3208 spin_unlock_irq(&hdspm->lock);
3209 return 0; 3209 return 0;
3210 } 3210 }
3211 3211
3212 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol, 3212 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3213 struct snd_ctl_elem_value *ucontrol) 3213 struct snd_ctl_elem_value *ucontrol)
3214 { 3214 {
3215 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3215 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3216 int change; 3216 int change;
3217 unsigned int val; 3217 unsigned int val;
3218 3218
3219 if (!snd_hdspm_use_is_exclusive(hdspm)) 3219 if (!snd_hdspm_use_is_exclusive(hdspm))
3220 return -EBUSY; 3220 return -EBUSY;
3221 val = ucontrol->value.integer.value[0] & 1; 3221 val = ucontrol->value.integer.value[0] & 1;
3222 spin_lock_irq(&hdspm->lock); 3222 spin_lock_irq(&hdspm->lock);
3223 change = (int) val != hdspm_input_select(hdspm); 3223 change = (int) val != hdspm_input_select(hdspm);
3224 hdspm_set_input_select(hdspm, val); 3224 hdspm_set_input_select(hdspm, val);
3225 spin_unlock_irq(&hdspm->lock); 3225 spin_unlock_irq(&hdspm->lock);
3226 return change; 3226 return change;
3227 } 3227 }
3228 3228
3229 3229
3230 #define HDSPM_DS_WIRE(xname, xindex) \ 3230 #define HDSPM_DS_WIRE(xname, xindex) \
3231 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3231 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3232 .name = xname, \ 3232 .name = xname, \
3233 .index = xindex, \ 3233 .index = xindex, \
3234 .info = snd_hdspm_info_ds_wire, \ 3234 .info = snd_hdspm_info_ds_wire, \
3235 .get = snd_hdspm_get_ds_wire, \ 3235 .get = snd_hdspm_get_ds_wire, \
3236 .put = snd_hdspm_put_ds_wire \ 3236 .put = snd_hdspm_put_ds_wire \
3237 } 3237 }
3238 3238
3239 static int hdspm_ds_wire(struct hdspm * hdspm) 3239 static int hdspm_ds_wire(struct hdspm * hdspm)
3240 { 3240 {
3241 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0; 3241 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3242 } 3242 }
3243 3243
3244 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds) 3244 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3245 { 3245 {
3246 if (ds) 3246 if (ds)
3247 hdspm->control_register |= HDSPM_DS_DoubleWire; 3247 hdspm->control_register |= HDSPM_DS_DoubleWire;
3248 else 3248 else
3249 hdspm->control_register &= ~HDSPM_DS_DoubleWire; 3249 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3250 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3250 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3251 3251
3252 return 0; 3252 return 0;
3253 } 3253 }
3254 3254
3255 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol, 3255 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3256 struct snd_ctl_elem_info *uinfo) 3256 struct snd_ctl_elem_info *uinfo)
3257 { 3257 {
3258 static char *texts[] = { "Single", "Double" }; 3258 static char *texts[] = { "Single", "Double" };
3259 3259
3260 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3260 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3261 uinfo->count = 1; 3261 uinfo->count = 1;
3262 uinfo->value.enumerated.items = 2; 3262 uinfo->value.enumerated.items = 2;
3263 3263
3264 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3264 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3265 uinfo->value.enumerated.item = 3265 uinfo->value.enumerated.item =
3266 uinfo->value.enumerated.items - 1; 3266 uinfo->value.enumerated.items - 1;
3267 strcpy(uinfo->value.enumerated.name, 3267 strcpy(uinfo->value.enumerated.name,
3268 texts[uinfo->value.enumerated.item]); 3268 texts[uinfo->value.enumerated.item]);
3269 3269
3270 return 0; 3270 return 0;
3271 } 3271 }
3272 3272
3273 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol, 3273 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3274 struct snd_ctl_elem_value *ucontrol) 3274 struct snd_ctl_elem_value *ucontrol)
3275 { 3275 {
3276 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3276 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3277 3277
3278 spin_lock_irq(&hdspm->lock); 3278 spin_lock_irq(&hdspm->lock);
3279 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm); 3279 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3280 spin_unlock_irq(&hdspm->lock); 3280 spin_unlock_irq(&hdspm->lock);
3281 return 0; 3281 return 0;
3282 } 3282 }
3283 3283
3284 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol, 3284 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3285 struct snd_ctl_elem_value *ucontrol) 3285 struct snd_ctl_elem_value *ucontrol)
3286 { 3286 {
3287 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3287 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3288 int change; 3288 int change;
3289 unsigned int val; 3289 unsigned int val;
3290 3290
3291 if (!snd_hdspm_use_is_exclusive(hdspm)) 3291 if (!snd_hdspm_use_is_exclusive(hdspm))
3292 return -EBUSY; 3292 return -EBUSY;
3293 val = ucontrol->value.integer.value[0] & 1; 3293 val = ucontrol->value.integer.value[0] & 1;
3294 spin_lock_irq(&hdspm->lock); 3294 spin_lock_irq(&hdspm->lock);
3295 change = (int) val != hdspm_ds_wire(hdspm); 3295 change = (int) val != hdspm_ds_wire(hdspm);
3296 hdspm_set_ds_wire(hdspm, val); 3296 hdspm_set_ds_wire(hdspm, val);
3297 spin_unlock_irq(&hdspm->lock); 3297 spin_unlock_irq(&hdspm->lock);
3298 return change; 3298 return change;
3299 } 3299 }
3300 3300
3301 3301
3302 #define HDSPM_QS_WIRE(xname, xindex) \ 3302 #define HDSPM_QS_WIRE(xname, xindex) \
3303 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3303 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3304 .name = xname, \ 3304 .name = xname, \
3305 .index = xindex, \ 3305 .index = xindex, \
3306 .info = snd_hdspm_info_qs_wire, \ 3306 .info = snd_hdspm_info_qs_wire, \
3307 .get = snd_hdspm_get_qs_wire, \ 3307 .get = snd_hdspm_get_qs_wire, \
3308 .put = snd_hdspm_put_qs_wire \ 3308 .put = snd_hdspm_put_qs_wire \
3309 } 3309 }
3310 3310
3311 static int hdspm_qs_wire(struct hdspm * hdspm) 3311 static int hdspm_qs_wire(struct hdspm * hdspm)
3312 { 3312 {
3313 if (hdspm->control_register & HDSPM_QS_DoubleWire) 3313 if (hdspm->control_register & HDSPM_QS_DoubleWire)
3314 return 1; 3314 return 1;
3315 if (hdspm->control_register & HDSPM_QS_QuadWire) 3315 if (hdspm->control_register & HDSPM_QS_QuadWire)
3316 return 2; 3316 return 2;
3317 return 0; 3317 return 0;
3318 } 3318 }
3319 3319
3320 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode) 3320 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3321 { 3321 {
3322 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire); 3322 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3323 switch (mode) { 3323 switch (mode) {
3324 case 0: 3324 case 0:
3325 break; 3325 break;
3326 case 1: 3326 case 1:
3327 hdspm->control_register |= HDSPM_QS_DoubleWire; 3327 hdspm->control_register |= HDSPM_QS_DoubleWire;
3328 break; 3328 break;
3329 case 2: 3329 case 2:
3330 hdspm->control_register |= HDSPM_QS_QuadWire; 3330 hdspm->control_register |= HDSPM_QS_QuadWire;
3331 break; 3331 break;
3332 } 3332 }
3333 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3333 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3334 3334
3335 return 0; 3335 return 0;
3336 } 3336 }
3337 3337
3338 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol, 3338 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3339 struct snd_ctl_elem_info *uinfo) 3339 struct snd_ctl_elem_info *uinfo)
3340 { 3340 {
3341 static char *texts[] = { "Single", "Double", "Quad" }; 3341 static char *texts[] = { "Single", "Double", "Quad" };
3342 3342
3343 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3343 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3344 uinfo->count = 1; 3344 uinfo->count = 1;
3345 uinfo->value.enumerated.items = 3; 3345 uinfo->value.enumerated.items = 3;
3346 3346
3347 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3347 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3348 uinfo->value.enumerated.item = 3348 uinfo->value.enumerated.item =
3349 uinfo->value.enumerated.items - 1; 3349 uinfo->value.enumerated.items - 1;
3350 strcpy(uinfo->value.enumerated.name, 3350 strcpy(uinfo->value.enumerated.name,
3351 texts[uinfo->value.enumerated.item]); 3351 texts[uinfo->value.enumerated.item]);
3352 3352
3353 return 0; 3353 return 0;
3354 } 3354 }
3355 3355
3356 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol, 3356 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3357 struct snd_ctl_elem_value *ucontrol) 3357 struct snd_ctl_elem_value *ucontrol)
3358 { 3358 {
3359 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3359 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3360 3360
3361 spin_lock_irq(&hdspm->lock); 3361 spin_lock_irq(&hdspm->lock);
3362 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm); 3362 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3363 spin_unlock_irq(&hdspm->lock); 3363 spin_unlock_irq(&hdspm->lock);
3364 return 0; 3364 return 0;
3365 } 3365 }
3366 3366
3367 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol, 3367 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3368 struct snd_ctl_elem_value *ucontrol) 3368 struct snd_ctl_elem_value *ucontrol)
3369 { 3369 {
3370 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3370 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3371 int change; 3371 int change;
3372 int val; 3372 int val;
3373 3373
3374 if (!snd_hdspm_use_is_exclusive(hdspm)) 3374 if (!snd_hdspm_use_is_exclusive(hdspm))
3375 return -EBUSY; 3375 return -EBUSY;
3376 val = ucontrol->value.integer.value[0]; 3376 val = ucontrol->value.integer.value[0];
3377 if (val < 0) 3377 if (val < 0)
3378 val = 0; 3378 val = 0;
3379 if (val > 2) 3379 if (val > 2)
3380 val = 2; 3380 val = 2;
3381 spin_lock_irq(&hdspm->lock); 3381 spin_lock_irq(&hdspm->lock);
3382 change = val != hdspm_qs_wire(hdspm); 3382 change = val != hdspm_qs_wire(hdspm);
3383 hdspm_set_qs_wire(hdspm, val); 3383 hdspm_set_qs_wire(hdspm, val);
3384 spin_unlock_irq(&hdspm->lock); 3384 spin_unlock_irq(&hdspm->lock);
3385 return change; 3385 return change;
3386 } 3386 }
3387 3387
3388 3388
3389 #define HDSPM_MIXER(xname, xindex) \ 3389 #define HDSPM_MIXER(xname, xindex) \
3390 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 3390 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3391 .name = xname, \ 3391 .name = xname, \
3392 .index = xindex, \ 3392 .index = xindex, \
3393 .device = 0, \ 3393 .device = 0, \
3394 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3394 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3395 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3395 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3396 .info = snd_hdspm_info_mixer, \ 3396 .info = snd_hdspm_info_mixer, \
3397 .get = snd_hdspm_get_mixer, \ 3397 .get = snd_hdspm_get_mixer, \
3398 .put = snd_hdspm_put_mixer \ 3398 .put = snd_hdspm_put_mixer \
3399 } 3399 }
3400 3400
3401 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol, 3401 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3402 struct snd_ctl_elem_info *uinfo) 3402 struct snd_ctl_elem_info *uinfo)
3403 { 3403 {
3404 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3404 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3405 uinfo->count = 3; 3405 uinfo->count = 3;
3406 uinfo->value.integer.min = 0; 3406 uinfo->value.integer.min = 0;
3407 uinfo->value.integer.max = 65535; 3407 uinfo->value.integer.max = 65535;
3408 uinfo->value.integer.step = 1; 3408 uinfo->value.integer.step = 1;
3409 return 0; 3409 return 0;
3410 } 3410 }
3411 3411
3412 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol, 3412 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3413 struct snd_ctl_elem_value *ucontrol) 3413 struct snd_ctl_elem_value *ucontrol)
3414 { 3414 {
3415 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3415 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3416 int source; 3416 int source;
3417 int destination; 3417 int destination;
3418 3418
3419 source = ucontrol->value.integer.value[0]; 3419 source = ucontrol->value.integer.value[0];
3420 if (source < 0) 3420 if (source < 0)
3421 source = 0; 3421 source = 0;
3422 else if (source >= 2 * HDSPM_MAX_CHANNELS) 3422 else if (source >= 2 * HDSPM_MAX_CHANNELS)
3423 source = 2 * HDSPM_MAX_CHANNELS - 1; 3423 source = 2 * HDSPM_MAX_CHANNELS - 1;
3424 3424
3425 destination = ucontrol->value.integer.value[1]; 3425 destination = ucontrol->value.integer.value[1];
3426 if (destination < 0) 3426 if (destination < 0)
3427 destination = 0; 3427 destination = 0;
3428 else if (destination >= HDSPM_MAX_CHANNELS) 3428 else if (destination >= HDSPM_MAX_CHANNELS)
3429 destination = HDSPM_MAX_CHANNELS - 1; 3429 destination = HDSPM_MAX_CHANNELS - 1;
3430 3430
3431 spin_lock_irq(&hdspm->lock); 3431 spin_lock_irq(&hdspm->lock);
3432 if (source >= HDSPM_MAX_CHANNELS) 3432 if (source >= HDSPM_MAX_CHANNELS)
3433 ucontrol->value.integer.value[2] = 3433 ucontrol->value.integer.value[2] =
3434 hdspm_read_pb_gain(hdspm, destination, 3434 hdspm_read_pb_gain(hdspm, destination,
3435 source - HDSPM_MAX_CHANNELS); 3435 source - HDSPM_MAX_CHANNELS);
3436 else 3436 else
3437 ucontrol->value.integer.value[2] = 3437 ucontrol->value.integer.value[2] =
3438 hdspm_read_in_gain(hdspm, destination, source); 3438 hdspm_read_in_gain(hdspm, destination, source);
3439 3439
3440 spin_unlock_irq(&hdspm->lock); 3440 spin_unlock_irq(&hdspm->lock);
3441 3441
3442 return 0; 3442 return 0;
3443 } 3443 }
3444 3444
3445 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol, 3445 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3446 struct snd_ctl_elem_value *ucontrol) 3446 struct snd_ctl_elem_value *ucontrol)
3447 { 3447 {
3448 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3448 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3449 int change; 3449 int change;
3450 int source; 3450 int source;
3451 int destination; 3451 int destination;
3452 int gain; 3452 int gain;
3453 3453
3454 if (!snd_hdspm_use_is_exclusive(hdspm)) 3454 if (!snd_hdspm_use_is_exclusive(hdspm))
3455 return -EBUSY; 3455 return -EBUSY;
3456 3456
3457 source = ucontrol->value.integer.value[0]; 3457 source = ucontrol->value.integer.value[0];
3458 destination = ucontrol->value.integer.value[1]; 3458 destination = ucontrol->value.integer.value[1];
3459 3459
3460 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS) 3460 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3461 return -1; 3461 return -1;
3462 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS) 3462 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3463 return -1; 3463 return -1;
3464 3464
3465 gain = ucontrol->value.integer.value[2]; 3465 gain = ucontrol->value.integer.value[2];
3466 3466
3467 spin_lock_irq(&hdspm->lock); 3467 spin_lock_irq(&hdspm->lock);
3468 3468
3469 if (source >= HDSPM_MAX_CHANNELS) 3469 if (source >= HDSPM_MAX_CHANNELS)
3470 change = gain != hdspm_read_pb_gain(hdspm, destination, 3470 change = gain != hdspm_read_pb_gain(hdspm, destination,
3471 source - 3471 source -
3472 HDSPM_MAX_CHANNELS); 3472 HDSPM_MAX_CHANNELS);
3473 else 3473 else
3474 change = gain != hdspm_read_in_gain(hdspm, destination, 3474 change = gain != hdspm_read_in_gain(hdspm, destination,
3475 source); 3475 source);
3476 3476
3477 if (change) { 3477 if (change) {
3478 if (source >= HDSPM_MAX_CHANNELS) 3478 if (source >= HDSPM_MAX_CHANNELS)
3479 hdspm_write_pb_gain(hdspm, destination, 3479 hdspm_write_pb_gain(hdspm, destination,
3480 source - HDSPM_MAX_CHANNELS, 3480 source - HDSPM_MAX_CHANNELS,
3481 gain); 3481 gain);
3482 else 3482 else
3483 hdspm_write_in_gain(hdspm, destination, source, 3483 hdspm_write_in_gain(hdspm, destination, source,
3484 gain); 3484 gain);
3485 } 3485 }
3486 spin_unlock_irq(&hdspm->lock); 3486 spin_unlock_irq(&hdspm->lock);
3487 3487
3488 return change; 3488 return change;
3489 } 3489 }
3490 3490
3491 /* The simple mixer control(s) provide gain control for the 3491 /* The simple mixer control(s) provide gain control for the
3492 basic 1:1 mappings of playback streams to output 3492 basic 1:1 mappings of playback streams to output
3493 streams. 3493 streams.
3494 */ 3494 */
3495 3495
3496 #define HDSPM_PLAYBACK_MIXER \ 3496 #define HDSPM_PLAYBACK_MIXER \
3497 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3497 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3498 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \ 3498 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3499 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3499 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3500 .info = snd_hdspm_info_playback_mixer, \ 3500 .info = snd_hdspm_info_playback_mixer, \
3501 .get = snd_hdspm_get_playback_mixer, \ 3501 .get = snd_hdspm_get_playback_mixer, \
3502 .put = snd_hdspm_put_playback_mixer \ 3502 .put = snd_hdspm_put_playback_mixer \
3503 } 3503 }
3504 3504
3505 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol, 3505 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3506 struct snd_ctl_elem_info *uinfo) 3506 struct snd_ctl_elem_info *uinfo)
3507 { 3507 {
3508 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3508 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3509 uinfo->count = 1; 3509 uinfo->count = 1;
3510 uinfo->value.integer.min = 0; 3510 uinfo->value.integer.min = 0;
3511 uinfo->value.integer.max = 64; 3511 uinfo->value.integer.max = 64;
3512 uinfo->value.integer.step = 1; 3512 uinfo->value.integer.step = 1;
3513 return 0; 3513 return 0;
3514 } 3514 }
3515 3515
3516 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol, 3516 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3517 struct snd_ctl_elem_value *ucontrol) 3517 struct snd_ctl_elem_value *ucontrol)
3518 { 3518 {
3519 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3519 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3520 int channel; 3520 int channel;
3521 3521
3522 channel = ucontrol->id.index - 1; 3522 channel = ucontrol->id.index - 1;
3523 3523
3524 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3524 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3525 return -EINVAL; 3525 return -EINVAL;
3526 3526
3527 spin_lock_irq(&hdspm->lock); 3527 spin_lock_irq(&hdspm->lock);
3528 ucontrol->value.integer.value[0] = 3528 ucontrol->value.integer.value[0] =
3529 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN; 3529 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3530 spin_unlock_irq(&hdspm->lock); 3530 spin_unlock_irq(&hdspm->lock);
3531 3531
3532 return 0; 3532 return 0;
3533 } 3533 }
3534 3534
3535 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol, 3535 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3536 struct snd_ctl_elem_value *ucontrol) 3536 struct snd_ctl_elem_value *ucontrol)
3537 { 3537 {
3538 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3538 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3539 int change; 3539 int change;
3540 int channel; 3540 int channel;
3541 int gain; 3541 int gain;
3542 3542
3543 if (!snd_hdspm_use_is_exclusive(hdspm)) 3543 if (!snd_hdspm_use_is_exclusive(hdspm))
3544 return -EBUSY; 3544 return -EBUSY;
3545 3545
3546 channel = ucontrol->id.index - 1; 3546 channel = ucontrol->id.index - 1;
3547 3547
3548 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3548 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3549 return -EINVAL; 3549 return -EINVAL;
3550 3550
3551 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64; 3551 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3552 3552
3553 spin_lock_irq(&hdspm->lock); 3553 spin_lock_irq(&hdspm->lock);
3554 change = 3554 change =
3555 gain != hdspm_read_pb_gain(hdspm, channel, 3555 gain != hdspm_read_pb_gain(hdspm, channel,
3556 channel); 3556 channel);
3557 if (change) 3557 if (change)
3558 hdspm_write_pb_gain(hdspm, channel, channel, 3558 hdspm_write_pb_gain(hdspm, channel, channel,
3559 gain); 3559 gain);
3560 spin_unlock_irq(&hdspm->lock); 3560 spin_unlock_irq(&hdspm->lock);
3561 return change; 3561 return change;
3562 } 3562 }
3563 3563
3564 #define HDSPM_SYNC_CHECK(xname, xindex) \ 3564 #define HDSPM_SYNC_CHECK(xname, xindex) \
3565 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3565 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3566 .name = xname, \ 3566 .name = xname, \
3567 .private_value = xindex, \ 3567 .private_value = xindex, \
3568 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3568 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3569 .info = snd_hdspm_info_sync_check, \ 3569 .info = snd_hdspm_info_sync_check, \
3570 .get = snd_hdspm_get_sync_check \ 3570 .get = snd_hdspm_get_sync_check \
3571 } 3571 }
3572 3572
3573 3573
3574 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol, 3574 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3575 struct snd_ctl_elem_info *uinfo) 3575 struct snd_ctl_elem_info *uinfo)
3576 { 3576 {
3577 static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" }; 3577 static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3578 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3578 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3579 uinfo->count = 1; 3579 uinfo->count = 1;
3580 uinfo->value.enumerated.items = 4; 3580 uinfo->value.enumerated.items = 4;
3581 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3581 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3582 uinfo->value.enumerated.item = 3582 uinfo->value.enumerated.item =
3583 uinfo->value.enumerated.items - 1; 3583 uinfo->value.enumerated.items - 1;
3584 strcpy(uinfo->value.enumerated.name, 3584 strcpy(uinfo->value.enumerated.name,
3585 texts[uinfo->value.enumerated.item]); 3585 texts[uinfo->value.enumerated.item]);
3586 return 0; 3586 return 0;
3587 } 3587 }
3588 3588
3589 static int hdspm_wc_sync_check(struct hdspm *hdspm) 3589 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3590 { 3590 {
3591 int status, status2; 3591 int status, status2;
3592 3592
3593 switch (hdspm->io_type) { 3593 switch (hdspm->io_type) {
3594 case AES32: 3594 case AES32:
3595 status = hdspm_read(hdspm, HDSPM_statusRegister); 3595 status = hdspm_read(hdspm, HDSPM_statusRegister);
3596 if (status & HDSPM_wcSync) 3596 if (status & HDSPM_wcSync)
3597 return 2; 3597 return 2;
3598 else if (status & HDSPM_wcLock) 3598 else if (status & HDSPM_wcLock)
3599 return 1; 3599 return 1;
3600 return 0; 3600 return 0;
3601 break; 3601 break;
3602 3602
3603 case MADI: 3603 case MADI:
3604 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3604 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3605 if (status2 & HDSPM_wcLock) { 3605 if (status2 & HDSPM_wcLock) {
3606 if (status2 & HDSPM_wcSync) 3606 if (status2 & HDSPM_wcSync)
3607 return 2; 3607 return 2;
3608 else 3608 else
3609 return 1; 3609 return 1;
3610 } 3610 }
3611 return 0; 3611 return 0;
3612 break; 3612 break;
3613 3613
3614 case RayDAT: 3614 case RayDAT:
3615 case AIO: 3615 case AIO:
3616 status = hdspm_read(hdspm, HDSPM_statusRegister); 3616 status = hdspm_read(hdspm, HDSPM_statusRegister);
3617 3617
3618 if (status & 0x2000000) 3618 if (status & 0x2000000)
3619 return 2; 3619 return 2;
3620 else if (status & 0x1000000) 3620 else if (status & 0x1000000)
3621 return 1; 3621 return 1;
3622 return 0; 3622 return 0;
3623 3623
3624 break; 3624 break;
3625 3625
3626 case MADIface: 3626 case MADIface:
3627 break; 3627 break;
3628 } 3628 }
3629 3629
3630 3630
3631 return 3; 3631 return 3;
3632 } 3632 }
3633 3633
3634 3634
3635 static int hdspm_madi_sync_check(struct hdspm *hdspm) 3635 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3636 { 3636 {
3637 int status = hdspm_read(hdspm, HDSPM_statusRegister); 3637 int status = hdspm_read(hdspm, HDSPM_statusRegister);
3638 if (status & HDSPM_madiLock) { 3638 if (status & HDSPM_madiLock) {
3639 if (status & HDSPM_madiSync) 3639 if (status & HDSPM_madiSync)
3640 return 2; 3640 return 2;
3641 else 3641 else
3642 return 1; 3642 return 1;
3643 } 3643 }
3644 return 0; 3644 return 0;
3645 } 3645 }
3646 3646
3647 3647
3648 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx) 3648 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3649 { 3649 {
3650 int status, lock, sync; 3650 int status, lock, sync;
3651 3651
3652 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 3652 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3653 3653
3654 lock = (status & (0x1<<idx)) ? 1 : 0; 3654 lock = (status & (0x1<<idx)) ? 1 : 0;
3655 sync = (status & (0x100<<idx)) ? 1 : 0; 3655 sync = (status & (0x100<<idx)) ? 1 : 0;
3656 3656
3657 if (lock && sync) 3657 if (lock && sync)
3658 return 2; 3658 return 2;
3659 else if (lock) 3659 else if (lock)
3660 return 1; 3660 return 1;
3661 return 0; 3661 return 0;
3662 } 3662 }
3663 3663
3664 3664
3665 static int hdspm_sync_in_sync_check(struct hdspm *hdspm) 3665 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3666 { 3666 {
3667 int status, lock = 0, sync = 0; 3667 int status, lock = 0, sync = 0;
3668 3668
3669 switch (hdspm->io_type) { 3669 switch (hdspm->io_type) {
3670 case RayDAT: 3670 case RayDAT:
3671 case AIO: 3671 case AIO:
3672 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3); 3672 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3673 lock = (status & 0x400) ? 1 : 0; 3673 lock = (status & 0x400) ? 1 : 0;
3674 sync = (status & 0x800) ? 1 : 0; 3674 sync = (status & 0x800) ? 1 : 0;
3675 break; 3675 break;
3676 3676
3677 case MADI: 3677 case MADI:
3678 case AES32: 3678 case AES32:
3679 status = hdspm_read(hdspm, HDSPM_statusRegister2); 3679 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3680 lock = (status & 0x400000) ? 1 : 0; 3680 lock = (status & 0x400000) ? 1 : 0;
3681 sync = (status & 0x800000) ? 1 : 0; 3681 sync = (status & 0x800000) ? 1 : 0;
3682 break; 3682 break;
3683 3683
3684 case MADIface: 3684 case MADIface:
3685 break; 3685 break;
3686 } 3686 }
3687 3687
3688 if (lock && sync) 3688 if (lock && sync)
3689 return 2; 3689 return 2;
3690 else if (lock) 3690 else if (lock)
3691 return 1; 3691 return 1;
3692 3692
3693 return 0; 3693 return 0;
3694 } 3694 }
3695 3695
3696 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx) 3696 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3697 { 3697 {
3698 int status2, lock, sync; 3698 int status2, lock, sync;
3699 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3699 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3700 3700
3701 lock = (status2 & (0x0080 >> idx)) ? 1 : 0; 3701 lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3702 sync = (status2 & (0x8000 >> idx)) ? 1 : 0; 3702 sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3703 3703
3704 if (sync) 3704 if (sync)
3705 return 2; 3705 return 2;
3706 else if (lock) 3706 else if (lock)
3707 return 1; 3707 return 1;
3708 return 0; 3708 return 0;
3709 } 3709 }
3710 3710
3711 3711
3712 static int hdspm_tco_sync_check(struct hdspm *hdspm) 3712 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3713 { 3713 {
3714 int status; 3714 int status;
3715 3715
3716 if (hdspm->tco) { 3716 if (hdspm->tco) {
3717 switch (hdspm->io_type) { 3717 switch (hdspm->io_type) {
3718 case MADI: 3718 case MADI:
3719 case AES32: 3719 case AES32:
3720 status = hdspm_read(hdspm, HDSPM_statusRegister); 3720 status = hdspm_read(hdspm, HDSPM_statusRegister);
3721 if (status & HDSPM_tcoLock) { 3721 if (status & HDSPM_tcoLock) {
3722 if (status & HDSPM_tcoSync) 3722 if (status & HDSPM_tcoSync)
3723 return 2; 3723 return 2;
3724 else 3724 else
3725 return 1; 3725 return 1;
3726 } 3726 }
3727 return 0; 3727 return 0;
3728 3728
3729 break; 3729 break;
3730 3730
3731 case RayDAT: 3731 case RayDAT:
3732 case AIO: 3732 case AIO:
3733 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 3733 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3734 3734
3735 if (status & 0x8000000) 3735 if (status & 0x8000000)
3736 return 2; /* Sync */ 3736 return 2; /* Sync */
3737 if (status & 0x4000000) 3737 if (status & 0x4000000)
3738 return 1; /* Lock */ 3738 return 1; /* Lock */
3739 return 0; /* No signal */ 3739 return 0; /* No signal */
3740 break; 3740 break;
3741 3741
3742 default: 3742 default:
3743 break; 3743 break;
3744 } 3744 }
3745 } 3745 }
3746 3746
3747 return 3; /* N/A */ 3747 return 3; /* N/A */
3748 } 3748 }
3749 3749
3750 3750
3751 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol, 3751 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
3752 struct snd_ctl_elem_value *ucontrol) 3752 struct snd_ctl_elem_value *ucontrol)
3753 { 3753 {
3754 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3754 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3755 int val = -1; 3755 int val = -1;
3756 3756
3757 switch (hdspm->io_type) { 3757 switch (hdspm->io_type) {
3758 case RayDAT: 3758 case RayDAT:
3759 switch (kcontrol->private_value) { 3759 switch (kcontrol->private_value) {
3760 case 0: /* WC */ 3760 case 0: /* WC */
3761 val = hdspm_wc_sync_check(hdspm); break; 3761 val = hdspm_wc_sync_check(hdspm); break;
3762 case 7: /* TCO */ 3762 case 7: /* TCO */
3763 val = hdspm_tco_sync_check(hdspm); break; 3763 val = hdspm_tco_sync_check(hdspm); break;
3764 case 8: /* SYNC IN */ 3764 case 8: /* SYNC IN */
3765 val = hdspm_sync_in_sync_check(hdspm); break; 3765 val = hdspm_sync_in_sync_check(hdspm); break;
3766 default: 3766 default:
3767 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1); 3767 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3768 } 3768 }
3769 3769
3770 case AIO: 3770 case AIO:
3771 switch (kcontrol->private_value) { 3771 switch (kcontrol->private_value) {
3772 case 0: /* WC */ 3772 case 0: /* WC */
3773 val = hdspm_wc_sync_check(hdspm); break; 3773 val = hdspm_wc_sync_check(hdspm); break;
3774 case 4: /* TCO */ 3774 case 4: /* TCO */
3775 val = hdspm_tco_sync_check(hdspm); break; 3775 val = hdspm_tco_sync_check(hdspm); break;
3776 case 5: /* SYNC IN */ 3776 case 5: /* SYNC IN */
3777 val = hdspm_sync_in_sync_check(hdspm); break; 3777 val = hdspm_sync_in_sync_check(hdspm); break;
3778 default: 3778 default:
3779 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1); 3779 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3780 } 3780 }
3781 3781
3782 case MADI: 3782 case MADI:
3783 switch (kcontrol->private_value) { 3783 switch (kcontrol->private_value) {
3784 case 0: /* WC */ 3784 case 0: /* WC */
3785 val = hdspm_wc_sync_check(hdspm); break; 3785 val = hdspm_wc_sync_check(hdspm); break;
3786 case 1: /* MADI */ 3786 case 1: /* MADI */
3787 val = hdspm_madi_sync_check(hdspm); break; 3787 val = hdspm_madi_sync_check(hdspm); break;
3788 case 2: /* TCO */ 3788 case 2: /* TCO */
3789 val = hdspm_tco_sync_check(hdspm); break; 3789 val = hdspm_tco_sync_check(hdspm); break;
3790 case 3: /* SYNC_IN */ 3790 case 3: /* SYNC_IN */
3791 val = hdspm_sync_in_sync_check(hdspm); break; 3791 val = hdspm_sync_in_sync_check(hdspm); break;
3792 } 3792 }
3793 3793
3794 case MADIface: 3794 case MADIface:
3795 val = hdspm_madi_sync_check(hdspm); /* MADI */ 3795 val = hdspm_madi_sync_check(hdspm); /* MADI */
3796 break; 3796 break;
3797 3797
3798 case AES32: 3798 case AES32:
3799 switch (kcontrol->private_value) { 3799 switch (kcontrol->private_value) {
3800 case 0: /* WC */ 3800 case 0: /* WC */
3801 val = hdspm_wc_sync_check(hdspm); break; 3801 val = hdspm_wc_sync_check(hdspm); break;
3802 case 9: /* TCO */ 3802 case 9: /* TCO */
3803 val = hdspm_tco_sync_check(hdspm); break; 3803 val = hdspm_tco_sync_check(hdspm); break;
3804 case 10 /* SYNC IN */: 3804 case 10 /* SYNC IN */:
3805 val = hdspm_sync_in_sync_check(hdspm); break; 3805 val = hdspm_sync_in_sync_check(hdspm); break;
3806 default: 3806 default:
3807 val = hdspm_aes_sync_check(hdspm, 3807 val = hdspm_aes_sync_check(hdspm,
3808 ucontrol->id.index-1); 3808 ucontrol->id.index-1);
3809 } 3809 }
3810 3810
3811 } 3811 }
3812 3812
3813 if (-1 == val) 3813 if (-1 == val)
3814 val = 3; 3814 val = 3;
3815 3815
3816 ucontrol->value.enumerated.item[0] = val; 3816 ucontrol->value.enumerated.item[0] = val;
3817 return 0; 3817 return 0;
3818 } 3818 }
3819 3819
3820 3820
3821 3821
3822 /** 3822 /**
3823 * TCO controls 3823 * TCO controls
3824 **/ 3824 **/
3825 static void hdspm_tco_write(struct hdspm *hdspm) 3825 static void hdspm_tco_write(struct hdspm *hdspm)
3826 { 3826 {
3827 unsigned int tc[4] = { 0, 0, 0, 0}; 3827 unsigned int tc[4] = { 0, 0, 0, 0};
3828 3828
3829 switch (hdspm->tco->input) { 3829 switch (hdspm->tco->input) {
3830 case 0: 3830 case 0:
3831 tc[2] |= HDSPM_TCO2_set_input_MSB; 3831 tc[2] |= HDSPM_TCO2_set_input_MSB;
3832 break; 3832 break;
3833 case 1: 3833 case 1:
3834 tc[2] |= HDSPM_TCO2_set_input_LSB; 3834 tc[2] |= HDSPM_TCO2_set_input_LSB;
3835 break; 3835 break;
3836 default: 3836 default:
3837 break; 3837 break;
3838 } 3838 }
3839 3839
3840 switch (hdspm->tco->framerate) { 3840 switch (hdspm->tco->framerate) {
3841 case 1: 3841 case 1:
3842 tc[1] |= HDSPM_TCO1_LTC_Format_LSB; 3842 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
3843 break; 3843 break;
3844 case 2: 3844 case 2:
3845 tc[1] |= HDSPM_TCO1_LTC_Format_MSB; 3845 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
3846 break; 3846 break;
3847 case 3: 3847 case 3:
3848 tc[1] |= HDSPM_TCO1_LTC_Format_MSB + 3848 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
3849 HDSPM_TCO1_set_drop_frame_flag; 3849 HDSPM_TCO1_set_drop_frame_flag;
3850 break; 3850 break;
3851 case 4: 3851 case 4:
3852 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 3852 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
3853 HDSPM_TCO1_LTC_Format_MSB; 3853 HDSPM_TCO1_LTC_Format_MSB;
3854 break; 3854 break;
3855 case 5: 3855 case 5:
3856 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 3856 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
3857 HDSPM_TCO1_LTC_Format_MSB + 3857 HDSPM_TCO1_LTC_Format_MSB +
3858 HDSPM_TCO1_set_drop_frame_flag; 3858 HDSPM_TCO1_set_drop_frame_flag;
3859 break; 3859 break;
3860 default: 3860 default:
3861 break; 3861 break;
3862 } 3862 }
3863 3863
3864 switch (hdspm->tco->wordclock) { 3864 switch (hdspm->tco->wordclock) {
3865 case 1: 3865 case 1:
3866 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB; 3866 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
3867 break; 3867 break;
3868 case 2: 3868 case 2:
3869 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB; 3869 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
3870 break; 3870 break;
3871 default: 3871 default:
3872 break; 3872 break;
3873 } 3873 }
3874 3874
3875 switch (hdspm->tco->samplerate) { 3875 switch (hdspm->tco->samplerate) {
3876 case 1: 3876 case 1:
3877 tc[2] |= HDSPM_TCO2_set_freq; 3877 tc[2] |= HDSPM_TCO2_set_freq;
3878 break; 3878 break;
3879 case 2: 3879 case 2:
3880 tc[2] |= HDSPM_TCO2_set_freq_from_app; 3880 tc[2] |= HDSPM_TCO2_set_freq_from_app;
3881 break; 3881 break;
3882 default: 3882 default:
3883 break; 3883 break;
3884 } 3884 }
3885 3885
3886 switch (hdspm->tco->pull) { 3886 switch (hdspm->tco->pull) {
3887 case 1: 3887 case 1:
3888 tc[2] |= HDSPM_TCO2_set_pull_up; 3888 tc[2] |= HDSPM_TCO2_set_pull_up;
3889 break; 3889 break;
3890 case 2: 3890 case 2:
3891 tc[2] |= HDSPM_TCO2_set_pull_down; 3891 tc[2] |= HDSPM_TCO2_set_pull_down;
3892 break; 3892 break;
3893 case 3: 3893 case 3:
3894 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4; 3894 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
3895 break; 3895 break;
3896 case 4: 3896 case 4:
3897 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4; 3897 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
3898 break; 3898 break;
3899 default: 3899 default:
3900 break; 3900 break;
3901 } 3901 }
3902 3902
3903 if (1 == hdspm->tco->term) { 3903 if (1 == hdspm->tco->term) {
3904 tc[2] |= HDSPM_TCO2_set_term_75R; 3904 tc[2] |= HDSPM_TCO2_set_term_75R;
3905 } 3905 }
3906 3906
3907 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]); 3907 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
3908 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]); 3908 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
3909 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]); 3909 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
3910 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]); 3910 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
3911 } 3911 }
3912 3912
3913 3913
3914 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \ 3914 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
3915 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3915 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3916 .name = xname, \ 3916 .name = xname, \
3917 .index = xindex, \ 3917 .index = xindex, \
3918 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 3918 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
3919 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3919 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3920 .info = snd_hdspm_info_tco_sample_rate, \ 3920 .info = snd_hdspm_info_tco_sample_rate, \
3921 .get = snd_hdspm_get_tco_sample_rate, \ 3921 .get = snd_hdspm_get_tco_sample_rate, \
3922 .put = snd_hdspm_put_tco_sample_rate \ 3922 .put = snd_hdspm_put_tco_sample_rate \
3923 } 3923 }
3924 3924
3925 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol, 3925 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
3926 struct snd_ctl_elem_info *uinfo) 3926 struct snd_ctl_elem_info *uinfo)
3927 { 3927 {
3928 static char *texts[] = { "44.1 kHz", "48 kHz" }; 3928 static char *texts[] = { "44.1 kHz", "48 kHz" };
3929 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3929 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3930 uinfo->count = 1; 3930 uinfo->count = 1;
3931 uinfo->value.enumerated.items = 2; 3931 uinfo->value.enumerated.items = 2;
3932 3932
3933 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3933 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3934 uinfo->value.enumerated.item = 3934 uinfo->value.enumerated.item =
3935 uinfo->value.enumerated.items - 1; 3935 uinfo->value.enumerated.items - 1;
3936 3936
3937 strcpy(uinfo->value.enumerated.name, 3937 strcpy(uinfo->value.enumerated.name,
3938 texts[uinfo->value.enumerated.item]); 3938 texts[uinfo->value.enumerated.item]);
3939 3939
3940 return 0; 3940 return 0;
3941 } 3941 }
3942 3942
3943 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol, 3943 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
3944 struct snd_ctl_elem_value *ucontrol) 3944 struct snd_ctl_elem_value *ucontrol)
3945 { 3945 {
3946 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3946 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3947 3947
3948 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate; 3948 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
3949 3949
3950 return 0; 3950 return 0;
3951 } 3951 }
3952 3952
3953 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol, 3953 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
3954 struct snd_ctl_elem_value *ucontrol) 3954 struct snd_ctl_elem_value *ucontrol)
3955 { 3955 {
3956 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3956 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3957 3957
3958 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) { 3958 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
3959 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0]; 3959 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
3960 3960
3961 hdspm_tco_write(hdspm); 3961 hdspm_tco_write(hdspm);
3962 3962
3963 return 1; 3963 return 1;
3964 } 3964 }
3965 3965
3966 return 0; 3966 return 0;
3967 } 3967 }
3968 3968
3969 3969
3970 #define HDSPM_TCO_PULL(xname, xindex) \ 3970 #define HDSPM_TCO_PULL(xname, xindex) \
3971 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3971 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3972 .name = xname, \ 3972 .name = xname, \
3973 .index = xindex, \ 3973 .index = xindex, \
3974 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 3974 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
3975 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3975 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3976 .info = snd_hdspm_info_tco_pull, \ 3976 .info = snd_hdspm_info_tco_pull, \
3977 .get = snd_hdspm_get_tco_pull, \ 3977 .get = snd_hdspm_get_tco_pull, \
3978 .put = snd_hdspm_put_tco_pull \ 3978 .put = snd_hdspm_put_tco_pull \
3979 } 3979 }
3980 3980
3981 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol, 3981 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
3982 struct snd_ctl_elem_info *uinfo) 3982 struct snd_ctl_elem_info *uinfo)
3983 { 3983 {
3984 static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" }; 3984 static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" };
3985 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3985 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3986 uinfo->count = 1; 3986 uinfo->count = 1;
3987 uinfo->value.enumerated.items = 5; 3987 uinfo->value.enumerated.items = 5;
3988 3988
3989 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3989 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3990 uinfo->value.enumerated.item = 3990 uinfo->value.enumerated.item =
3991 uinfo->value.enumerated.items - 1; 3991 uinfo->value.enumerated.items - 1;
3992 3992
3993 strcpy(uinfo->value.enumerated.name, 3993 strcpy(uinfo->value.enumerated.name,
3994 texts[uinfo->value.enumerated.item]); 3994 texts[uinfo->value.enumerated.item]);
3995 3995
3996 return 0; 3996 return 0;
3997 } 3997 }
3998 3998
3999 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol, 3999 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4000 struct snd_ctl_elem_value *ucontrol) 4000 struct snd_ctl_elem_value *ucontrol)
4001 { 4001 {
4002 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4002 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4003 4003
4004 ucontrol->value.enumerated.item[0] = hdspm->tco->pull; 4004 ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4005 4005
4006 return 0; 4006 return 0;
4007 } 4007 }
4008 4008
4009 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol, 4009 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4010 struct snd_ctl_elem_value *ucontrol) 4010 struct snd_ctl_elem_value *ucontrol)
4011 { 4011 {
4012 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4012 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4013 4013
4014 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) { 4014 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4015 hdspm->tco->pull = ucontrol->value.enumerated.item[0]; 4015 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4016 4016
4017 hdspm_tco_write(hdspm); 4017 hdspm_tco_write(hdspm);
4018 4018
4019 return 1; 4019 return 1;
4020 } 4020 }
4021 4021
4022 return 0; 4022 return 0;
4023 } 4023 }
4024 4024
4025 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \ 4025 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4026 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4026 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4027 .name = xname, \ 4027 .name = xname, \
4028 .index = xindex, \ 4028 .index = xindex, \
4029 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4029 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4030 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4030 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4031 .info = snd_hdspm_info_tco_wck_conversion, \ 4031 .info = snd_hdspm_info_tco_wck_conversion, \
4032 .get = snd_hdspm_get_tco_wck_conversion, \ 4032 .get = snd_hdspm_get_tco_wck_conversion, \
4033 .put = snd_hdspm_put_tco_wck_conversion \ 4033 .put = snd_hdspm_put_tco_wck_conversion \
4034 } 4034 }
4035 4035
4036 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4036 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4037 struct snd_ctl_elem_info *uinfo) 4037 struct snd_ctl_elem_info *uinfo)
4038 { 4038 {
4039 static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" }; 4039 static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4040 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 4040 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4041 uinfo->count = 1; 4041 uinfo->count = 1;
4042 uinfo->value.enumerated.items = 3; 4042 uinfo->value.enumerated.items = 3;
4043 4043
4044 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 4044 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4045 uinfo->value.enumerated.item = 4045 uinfo->value.enumerated.item =
4046 uinfo->value.enumerated.items - 1; 4046 uinfo->value.enumerated.items - 1;
4047 4047
4048 strcpy(uinfo->value.enumerated.name, 4048 strcpy(uinfo->value.enumerated.name,
4049 texts[uinfo->value.enumerated.item]); 4049 texts[uinfo->value.enumerated.item]);
4050 4050
4051 return 0; 4051 return 0;
4052 } 4052 }
4053 4053
4054 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4054 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4055 struct snd_ctl_elem_value *ucontrol) 4055 struct snd_ctl_elem_value *ucontrol)
4056 { 4056 {
4057 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4057 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4058 4058
4059 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock; 4059 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4060 4060
4061 return 0; 4061 return 0;
4062 } 4062 }
4063 4063
4064 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4064 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4065 struct snd_ctl_elem_value *ucontrol) 4065 struct snd_ctl_elem_value *ucontrol)
4066 { 4066 {
4067 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4067 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4068 4068
4069 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) { 4069 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4070 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0]; 4070 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4071 4071
4072 hdspm_tco_write(hdspm); 4072 hdspm_tco_write(hdspm);
4073 4073
4074 return 1; 4074 return 1;
4075 } 4075 }
4076 4076
4077 return 0; 4077 return 0;
4078 } 4078 }
4079 4079
4080 4080
4081 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \ 4081 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4082 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4082 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4083 .name = xname, \ 4083 .name = xname, \
4084 .index = xindex, \ 4084 .index = xindex, \
4085 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4085 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4086 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4086 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4087 .info = snd_hdspm_info_tco_frame_rate, \ 4087 .info = snd_hdspm_info_tco_frame_rate, \
4088 .get = snd_hdspm_get_tco_frame_rate, \ 4088 .get = snd_hdspm_get_tco_frame_rate, \
4089 .put = snd_hdspm_put_tco_frame_rate \ 4089 .put = snd_hdspm_put_tco_frame_rate \
4090 } 4090 }
4091 4091
4092 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol, 4092 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4093 struct snd_ctl_elem_info *uinfo) 4093 struct snd_ctl_elem_info *uinfo)
4094 { 4094 {
4095 static char *texts[] = { "24 fps", "25 fps", "29.97fps", 4095 static char *texts[] = { "24 fps", "25 fps", "29.97fps",
4096 "29.97 dfps", "30 fps", "30 dfps" }; 4096 "29.97 dfps", "30 fps", "30 dfps" };
4097 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 4097 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4098 uinfo->count = 1; 4098 uinfo->count = 1;
4099 uinfo->value.enumerated.items = 6; 4099 uinfo->value.enumerated.items = 6;
4100 4100
4101 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 4101 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4102 uinfo->value.enumerated.item = 4102 uinfo->value.enumerated.item =
4103 uinfo->value.enumerated.items - 1; 4103 uinfo->value.enumerated.items - 1;
4104 4104
4105 strcpy(uinfo->value.enumerated.name, 4105 strcpy(uinfo->value.enumerated.name,
4106 texts[uinfo->value.enumerated.item]); 4106 texts[uinfo->value.enumerated.item]);
4107 4107
4108 return 0; 4108 return 0;
4109 } 4109 }
4110 4110
4111 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol, 4111 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4112 struct snd_ctl_elem_value *ucontrol) 4112 struct snd_ctl_elem_value *ucontrol)
4113 { 4113 {
4114 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4114 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4115 4115
4116 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate; 4116 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4117 4117
4118 return 0; 4118 return 0;
4119 } 4119 }
4120 4120
4121 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol, 4121 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4122 struct snd_ctl_elem_value *ucontrol) 4122 struct snd_ctl_elem_value *ucontrol)
4123 { 4123 {
4124 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4124 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4125 4125
4126 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) { 4126 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4127 hdspm->tco->framerate = ucontrol->value.enumerated.item[0]; 4127 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4128 4128
4129 hdspm_tco_write(hdspm); 4129 hdspm_tco_write(hdspm);
4130 4130
4131 return 1; 4131 return 1;
4132 } 4132 }
4133 4133
4134 return 0; 4134 return 0;
4135 } 4135 }
4136 4136
4137 4137
4138 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \ 4138 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4139 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4139 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4140 .name = xname, \ 4140 .name = xname, \
4141 .index = xindex, \ 4141 .index = xindex, \
4142 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4142 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4143 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4143 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4144 .info = snd_hdspm_info_tco_sync_source, \ 4144 .info = snd_hdspm_info_tco_sync_source, \
4145 .get = snd_hdspm_get_tco_sync_source, \ 4145 .get = snd_hdspm_get_tco_sync_source, \
4146 .put = snd_hdspm_put_tco_sync_source \ 4146 .put = snd_hdspm_put_tco_sync_source \
4147 } 4147 }
4148 4148
4149 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol, 4149 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4150 struct snd_ctl_elem_info *uinfo) 4150 struct snd_ctl_elem_info *uinfo)
4151 { 4151 {
4152 static char *texts[] = { "LTC", "Video", "WCK" }; 4152 static char *texts[] = { "LTC", "Video", "WCK" };
4153 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 4153 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4154 uinfo->count = 1; 4154 uinfo->count = 1;
4155 uinfo->value.enumerated.items = 3; 4155 uinfo->value.enumerated.items = 3;
4156 4156
4157 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 4157 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4158 uinfo->value.enumerated.item = 4158 uinfo->value.enumerated.item =
4159 uinfo->value.enumerated.items - 1; 4159 uinfo->value.enumerated.items - 1;
4160 4160
4161 strcpy(uinfo->value.enumerated.name, 4161 strcpy(uinfo->value.enumerated.name,
4162 texts[uinfo->value.enumerated.item]); 4162 texts[uinfo->value.enumerated.item]);
4163 4163
4164 return 0; 4164 return 0;
4165 } 4165 }
4166 4166
4167 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol, 4167 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4168 struct snd_ctl_elem_value *ucontrol) 4168 struct snd_ctl_elem_value *ucontrol)
4169 { 4169 {
4170 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4170 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4171 4171
4172 ucontrol->value.enumerated.item[0] = hdspm->tco->input; 4172 ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4173 4173
4174 return 0; 4174 return 0;
4175 } 4175 }
4176 4176
4177 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol, 4177 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4178 struct snd_ctl_elem_value *ucontrol) 4178 struct snd_ctl_elem_value *ucontrol)
4179 { 4179 {
4180 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4180 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4181 4181
4182 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) { 4182 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4183 hdspm->tco->input = ucontrol->value.enumerated.item[0]; 4183 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4184 4184
4185 hdspm_tco_write(hdspm); 4185 hdspm_tco_write(hdspm);
4186 4186
4187 return 1; 4187 return 1;
4188 } 4188 }
4189 4189
4190 return 0; 4190 return 0;
4191 } 4191 }
4192 4192
4193 4193
4194 #define HDSPM_TCO_WORD_TERM(xname, xindex) \ 4194 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4195 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4195 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4196 .name = xname, \ 4196 .name = xname, \
4197 .index = xindex, \ 4197 .index = xindex, \
4198 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4198 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4199 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4199 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4200 .info = snd_hdspm_info_tco_word_term, \ 4200 .info = snd_hdspm_info_tco_word_term, \
4201 .get = snd_hdspm_get_tco_word_term, \ 4201 .get = snd_hdspm_get_tco_word_term, \
4202 .put = snd_hdspm_put_tco_word_term \ 4202 .put = snd_hdspm_put_tco_word_term \
4203 } 4203 }
4204 4204
4205 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol, 4205 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4206 struct snd_ctl_elem_info *uinfo) 4206 struct snd_ctl_elem_info *uinfo)
4207 { 4207 {
4208 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 4208 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4209 uinfo->count = 1; 4209 uinfo->count = 1;
4210 uinfo->value.integer.min = 0; 4210 uinfo->value.integer.min = 0;
4211 uinfo->value.integer.max = 1; 4211 uinfo->value.integer.max = 1;
4212 4212
4213 return 0; 4213 return 0;
4214 } 4214 }
4215 4215
4216 4216
4217 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol, 4217 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4218 struct snd_ctl_elem_value *ucontrol) 4218 struct snd_ctl_elem_value *ucontrol)
4219 { 4219 {
4220 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4220 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4221 4221
4222 ucontrol->value.enumerated.item[0] = hdspm->tco->term; 4222 ucontrol->value.enumerated.item[0] = hdspm->tco->term;
4223 4223
4224 return 0; 4224 return 0;
4225 } 4225 }
4226 4226
4227 4227
4228 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol, 4228 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4229 struct snd_ctl_elem_value *ucontrol) 4229 struct snd_ctl_elem_value *ucontrol)
4230 { 4230 {
4231 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4231 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4232 4232
4233 if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) { 4233 if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) {
4234 hdspm->tco->term = ucontrol->value.enumerated.item[0]; 4234 hdspm->tco->term = ucontrol->value.enumerated.item[0];
4235 4235
4236 hdspm_tco_write(hdspm); 4236 hdspm_tco_write(hdspm);
4237 4237
4238 return 1; 4238 return 1;
4239 } 4239 }
4240 4240
4241 return 0; 4241 return 0;
4242 } 4242 }
4243 4243
4244 4244
4245 4245
4246 4246
4247 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = { 4247 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4248 HDSPM_MIXER("Mixer", 0), 4248 HDSPM_MIXER("Mixer", 0),
4249 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4249 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4250 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4250 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4251 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4251 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4252 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4252 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4253 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4253 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4254 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4254 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4255 HDSPM_SYNC_CHECK("MADI SyncCheck", 1), 4255 HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4256 HDSPM_SYNC_CHECK("TCO SyncCHeck", 2), 4256 HDSPM_SYNC_CHECK("TCO SyncCHeck", 2),
4257 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3), 4257 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4258 HDSPM_LINE_OUT("Line Out", 0), 4258 HDSPM_LINE_OUT("Line Out", 0),
4259 HDSPM_TX_64("TX 64 channels mode", 0), 4259 HDSPM_TX_64("TX 64 channels mode", 0),
4260 HDSPM_C_TMS("Clear Track Marker", 0), 4260 HDSPM_C_TMS("Clear Track Marker", 0),
4261 HDSPM_SAFE_MODE("Safe Mode", 0), 4261 HDSPM_SAFE_MODE("Safe Mode", 0),
4262 HDSPM_INPUT_SELECT("Input Select", 0) 4262 HDSPM_INPUT_SELECT("Input Select", 0)
4263 }; 4263 };
4264 4264
4265 4265
4266 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = { 4266 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4267 HDSPM_MIXER("Mixer", 0), 4267 HDSPM_MIXER("Mixer", 0),
4268 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4268 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4269 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4269 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4270 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4270 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4271 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4271 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4272 HDSPM_SYNC_CHECK("MADI SyncCheck", 0), 4272 HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4273 HDSPM_TX_64("TX 64 channels mode", 0), 4273 HDSPM_TX_64("TX 64 channels mode", 0),
4274 HDSPM_C_TMS("Clear Track Marker", 0), 4274 HDSPM_C_TMS("Clear Track Marker", 0),
4275 HDSPM_SAFE_MODE("Safe Mode", 0), 4275 HDSPM_SAFE_MODE("Safe Mode", 0),
4276 HDSPM_INPUT_SELECT("Input Select", 0), 4276 HDSPM_INPUT_SELECT("Input Select", 0),
4277 }; 4277 };
4278 4278
4279 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = { 4279 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4280 HDSPM_MIXER("Mixer", 0), 4280 HDSPM_MIXER("Mixer", 0),
4281 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4281 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4282 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4282 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4283 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4283 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4284 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4284 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4285 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4285 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4286 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4286 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4287 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4287 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4288 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4288 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4289 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4289 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4290 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3), 4290 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4291 HDSPM_SYNC_CHECK("TCO SyncCheck", 4), 4291 HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4292 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5), 4292 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4293 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4293 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4294 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4294 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4295 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4295 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4296 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3), 4296 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4297 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4), 4297 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4298 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5) 4298 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5)
4299 4299
4300 /* 4300 /*
4301 HDSPM_INPUT_SELECT("Input Select", 0), 4301 HDSPM_INPUT_SELECT("Input Select", 0),
4302 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0), 4302 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4303 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0); 4303 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4304 HDSPM_SPDIF_IN("SPDIF In", 0); 4304 HDSPM_SPDIF_IN("SPDIF In", 0);
4305 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0); 4305 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4306 HDSPM_INPUT_LEVEL("Input Level", 0); 4306 HDSPM_INPUT_LEVEL("Input Level", 0);
4307 HDSPM_OUTPUT_LEVEL("Output Level", 0); 4307 HDSPM_OUTPUT_LEVEL("Output Level", 0);
4308 HDSPM_PHONES("Phones", 0); 4308 HDSPM_PHONES("Phones", 0);
4309 */ 4309 */
4310 }; 4310 };
4311 4311
4312 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = { 4312 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4313 HDSPM_MIXER("Mixer", 0), 4313 HDSPM_MIXER("Mixer", 0),
4314 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4314 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4315 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0), 4315 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4316 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0), 4316 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4317 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4317 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4318 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4318 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4319 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4319 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4320 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4320 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4321 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3), 4321 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4322 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4), 4322 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4323 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5), 4323 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4324 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6), 4324 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4325 HDSPM_SYNC_CHECK("TCO SyncCheck", 7), 4325 HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4326 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8), 4326 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4327 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4327 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4328 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4328 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4329 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4329 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4330 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3), 4330 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4331 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4), 4331 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4332 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5), 4332 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4333 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6), 4333 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4334 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7), 4334 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4335 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8) 4335 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8)
4336 }; 4336 };
4337 4337
4338 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = { 4338 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4339 HDSPM_MIXER("Mixer", 0), 4339 HDSPM_MIXER("Mixer", 0),
4340 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4340 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4341 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4341 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4342 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4342 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4343 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4343 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4344 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4344 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4345 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4345 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4346 HDSPM_SYNC_CHECK("WC Sync Check", 0), 4346 HDSPM_SYNC_CHECK("WC Sync Check", 0),
4347 HDSPM_SYNC_CHECK("AES1 Sync Check", 1), 4347 HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4348 HDSPM_SYNC_CHECK("AES2 Sync Check", 2), 4348 HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4349 HDSPM_SYNC_CHECK("AES3 Sync Check", 3), 4349 HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4350 HDSPM_SYNC_CHECK("AES4 Sync Check", 4), 4350 HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4351 HDSPM_SYNC_CHECK("AES5 Sync Check", 5), 4351 HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4352 HDSPM_SYNC_CHECK("AES6 Sync Check", 6), 4352 HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4353 HDSPM_SYNC_CHECK("AES7 Sync Check", 7), 4353 HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4354 HDSPM_SYNC_CHECK("AES8 Sync Check", 8), 4354 HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4355 HDSPM_SYNC_CHECK("TCO Sync Check", 9), 4355 HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4356 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10), 4356 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4357 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4357 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4358 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1), 4358 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4359 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2), 4359 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4360 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3), 4360 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4361 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4), 4361 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4362 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5), 4362 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4363 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6), 4363 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4364 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7), 4364 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4365 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8), 4365 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4366 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9), 4366 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4367 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10), 4367 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4368 HDSPM_LINE_OUT("Line Out", 0), 4368 HDSPM_LINE_OUT("Line Out", 0),
4369 HDSPM_EMPHASIS("Emphasis", 0), 4369 HDSPM_EMPHASIS("Emphasis", 0),
4370 HDSPM_DOLBY("Non Audio", 0), 4370 HDSPM_DOLBY("Non Audio", 0),
4371 HDSPM_PROFESSIONAL("Professional", 0), 4371 HDSPM_PROFESSIONAL("Professional", 0),
4372 HDSPM_C_TMS("Clear Track Marker", 0), 4372 HDSPM_C_TMS("Clear Track Marker", 0),
4373 HDSPM_DS_WIRE("Double Speed Wire Mode", 0), 4373 HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4374 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0), 4374 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4375 }; 4375 };
4376 4376
4377 4377
4378 4378
4379 /* Control elements for the optional TCO module */ 4379 /* Control elements for the optional TCO module */
4380 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = { 4380 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4381 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0), 4381 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4382 HDSPM_TCO_PULL("TCO Pull", 0), 4382 HDSPM_TCO_PULL("TCO Pull", 0),
4383 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0), 4383 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4384 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0), 4384 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4385 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0), 4385 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4386 HDSPM_TCO_WORD_TERM("TCO Word Term", 0) 4386 HDSPM_TCO_WORD_TERM("TCO Word Term", 0)
4387 }; 4387 };
4388 4388
4389 4389
4390 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER; 4390 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4391 4391
4392 4392
4393 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm) 4393 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4394 { 4394 {
4395 int i; 4395 int i;
4396 4396
4397 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) { 4397 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4398 if (hdspm->system_sample_rate > 48000) { 4398 if (hdspm->system_sample_rate > 48000) {
4399 hdspm->playback_mixer_ctls[i]->vd[0].access = 4399 hdspm->playback_mixer_ctls[i]->vd[0].access =
4400 SNDRV_CTL_ELEM_ACCESS_INACTIVE | 4400 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4401 SNDRV_CTL_ELEM_ACCESS_READ | 4401 SNDRV_CTL_ELEM_ACCESS_READ |
4402 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4402 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4403 } else { 4403 } else {
4404 hdspm->playback_mixer_ctls[i]->vd[0].access = 4404 hdspm->playback_mixer_ctls[i]->vd[0].access =
4405 SNDRV_CTL_ELEM_ACCESS_READWRITE | 4405 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4406 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4406 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4407 } 4407 }
4408 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE | 4408 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4409 SNDRV_CTL_EVENT_MASK_INFO, 4409 SNDRV_CTL_EVENT_MASK_INFO,
4410 &hdspm->playback_mixer_ctls[i]->id); 4410 &hdspm->playback_mixer_ctls[i]->id);
4411 } 4411 }
4412 4412
4413 return 0; 4413 return 0;
4414 } 4414 }
4415 4415
4416 4416
4417 static int snd_hdspm_create_controls(struct snd_card *card, 4417 static int snd_hdspm_create_controls(struct snd_card *card,
4418 struct hdspm *hdspm) 4418 struct hdspm *hdspm)
4419 { 4419 {
4420 unsigned int idx, limit; 4420 unsigned int idx, limit;
4421 int err; 4421 int err;
4422 struct snd_kcontrol *kctl; 4422 struct snd_kcontrol *kctl;
4423 struct snd_kcontrol_new *list = NULL; 4423 struct snd_kcontrol_new *list = NULL;
4424 4424
4425 switch (hdspm->io_type) { 4425 switch (hdspm->io_type) {
4426 case MADI: 4426 case MADI:
4427 list = snd_hdspm_controls_madi; 4427 list = snd_hdspm_controls_madi;
4428 limit = ARRAY_SIZE(snd_hdspm_controls_madi); 4428 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4429 break; 4429 break;
4430 case MADIface: 4430 case MADIface:
4431 list = snd_hdspm_controls_madiface; 4431 list = snd_hdspm_controls_madiface;
4432 limit = ARRAY_SIZE(snd_hdspm_controls_madiface); 4432 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4433 break; 4433 break;
4434 case AIO: 4434 case AIO:
4435 list = snd_hdspm_controls_aio; 4435 list = snd_hdspm_controls_aio;
4436 limit = ARRAY_SIZE(snd_hdspm_controls_aio); 4436 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4437 break; 4437 break;
4438 case RayDAT: 4438 case RayDAT:
4439 list = snd_hdspm_controls_raydat; 4439 list = snd_hdspm_controls_raydat;
4440 limit = ARRAY_SIZE(snd_hdspm_controls_raydat); 4440 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4441 break; 4441 break;
4442 case AES32: 4442 case AES32:
4443 list = snd_hdspm_controls_aes32; 4443 list = snd_hdspm_controls_aes32;
4444 limit = ARRAY_SIZE(snd_hdspm_controls_aes32); 4444 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4445 break; 4445 break;
4446 } 4446 }
4447 4447
4448 if (NULL != list) { 4448 if (NULL != list) {
4449 for (idx = 0; idx < limit; idx++) { 4449 for (idx = 0; idx < limit; idx++) {
4450 err = snd_ctl_add(card, 4450 err = snd_ctl_add(card,
4451 snd_ctl_new1(&list[idx], hdspm)); 4451 snd_ctl_new1(&list[idx], hdspm));
4452 if (err < 0) 4452 if (err < 0)
4453 return err; 4453 return err;
4454 } 4454 }
4455 } 4455 }
4456 4456
4457 4457
4458 /* create simple 1:1 playback mixer controls */ 4458 /* create simple 1:1 playback mixer controls */
4459 snd_hdspm_playback_mixer.name = "Chn"; 4459 snd_hdspm_playback_mixer.name = "Chn";
4460 if (hdspm->system_sample_rate >= 128000) { 4460 if (hdspm->system_sample_rate >= 128000) {
4461 limit = hdspm->qs_out_channels; 4461 limit = hdspm->qs_out_channels;
4462 } else if (hdspm->system_sample_rate >= 64000) { 4462 } else if (hdspm->system_sample_rate >= 64000) {
4463 limit = hdspm->ds_out_channels; 4463 limit = hdspm->ds_out_channels;
4464 } else { 4464 } else {
4465 limit = hdspm->ss_out_channels; 4465 limit = hdspm->ss_out_channels;
4466 } 4466 }
4467 for (idx = 0; idx < limit; ++idx) { 4467 for (idx = 0; idx < limit; ++idx) {
4468 snd_hdspm_playback_mixer.index = idx + 1; 4468 snd_hdspm_playback_mixer.index = idx + 1;
4469 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm); 4469 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4470 err = snd_ctl_add(card, kctl); 4470 err = snd_ctl_add(card, kctl);
4471 if (err < 0) 4471 if (err < 0)
4472 return err; 4472 return err;
4473 hdspm->playback_mixer_ctls[idx] = kctl; 4473 hdspm->playback_mixer_ctls[idx] = kctl;
4474 } 4474 }
4475 4475
4476 4476
4477 if (hdspm->tco) { 4477 if (hdspm->tco) {
4478 /* add tco control elements */ 4478 /* add tco control elements */
4479 list = snd_hdspm_controls_tco; 4479 list = snd_hdspm_controls_tco;
4480 limit = ARRAY_SIZE(snd_hdspm_controls_tco); 4480 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4481 for (idx = 0; idx < limit; idx++) { 4481 for (idx = 0; idx < limit; idx++) {
4482 err = snd_ctl_add(card, 4482 err = snd_ctl_add(card,
4483 snd_ctl_new1(&list[idx], hdspm)); 4483 snd_ctl_new1(&list[idx], hdspm));
4484 if (err < 0) 4484 if (err < 0)
4485 return err; 4485 return err;
4486 } 4486 }
4487 } 4487 }
4488 4488
4489 return 0; 4489 return 0;
4490 } 4490 }
4491 4491
4492 /*------------------------------------------------------------ 4492 /*------------------------------------------------------------
4493 /proc interface 4493 /proc interface
4494 ------------------------------------------------------------*/ 4494 ------------------------------------------------------------*/
4495 4495
4496 static void 4496 static void
4497 snd_hdspm_proc_read_madi(struct snd_info_entry * entry, 4497 snd_hdspm_proc_read_madi(struct snd_info_entry * entry,
4498 struct snd_info_buffer *buffer) 4498 struct snd_info_buffer *buffer)
4499 { 4499 {
4500 struct hdspm *hdspm = entry->private_data; 4500 struct hdspm *hdspm = entry->private_data;
4501 unsigned int status, status2, control, freq; 4501 unsigned int status, status2, control, freq;
4502 4502
4503 char *pref_sync_ref; 4503 char *pref_sync_ref;
4504 char *autosync_ref; 4504 char *autosync_ref;
4505 char *system_clock_mode; 4505 char *system_clock_mode;
4506 char *insel; 4506 char *insel;
4507 int x, x2; 4507 int x, x2;
4508 4508
4509 /* TCO stuff */ 4509 /* TCO stuff */
4510 int a, ltc, frames, seconds, minutes, hours; 4510 int a, ltc, frames, seconds, minutes, hours;
4511 unsigned int period; 4511 unsigned int period;
4512 u64 freq_const = 0; 4512 u64 freq_const = 0;
4513 u32 rate; 4513 u32 rate;
4514 4514
4515 status = hdspm_read(hdspm, HDSPM_statusRegister); 4515 status = hdspm_read(hdspm, HDSPM_statusRegister);
4516 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 4516 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4517 control = hdspm->control_register; 4517 control = hdspm->control_register;
4518 freq = hdspm_read(hdspm, HDSPM_timecodeRegister); 4518 freq = hdspm_read(hdspm, HDSPM_timecodeRegister);
4519 4519
4520 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n", 4520 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4521 hdspm->card_name, hdspm->card->number + 1, 4521 hdspm->card_name, hdspm->card->number + 1,
4522 hdspm->firmware_rev, 4522 hdspm->firmware_rev,
4523 (status2 & HDSPM_version0) | 4523 (status2 & HDSPM_version0) |
4524 (status2 & HDSPM_version1) | (status2 & 4524 (status2 & HDSPM_version1) | (status2 &
4525 HDSPM_version2)); 4525 HDSPM_version2));
4526 4526
4527 snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n", 4527 snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4528 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF, 4528 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4529 (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF); 4529 (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF);
4530 4530
4531 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 4531 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4532 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 4532 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4533 4533
4534 snd_iprintf(buffer, "--- System ---\n"); 4534 snd_iprintf(buffer, "--- System ---\n");
4535 4535
4536 snd_iprintf(buffer, 4536 snd_iprintf(buffer,
4537 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 4537 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4538 status & HDSPM_audioIRQPending, 4538 status & HDSPM_audioIRQPending,
4539 (status & HDSPM_midi0IRQPending) ? 1 : 0, 4539 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4540 (status & HDSPM_midi1IRQPending) ? 1 : 0, 4540 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4541 hdspm->irq_count); 4541 hdspm->irq_count);
4542 snd_iprintf(buffer, 4542 snd_iprintf(buffer,
4543 "HW pointer: id = %d, rawptr = %d (%d->%d) " 4543 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4544 "estimated= %ld (bytes)\n", 4544 "estimated= %ld (bytes)\n",
4545 ((status & HDSPM_BufferID) ? 1 : 0), 4545 ((status & HDSPM_BufferID) ? 1 : 0),
4546 (status & HDSPM_BufferPositionMask), 4546 (status & HDSPM_BufferPositionMask),
4547 (status & HDSPM_BufferPositionMask) % 4547 (status & HDSPM_BufferPositionMask) %
4548 (2 * (int)hdspm->period_bytes), 4548 (2 * (int)hdspm->period_bytes),
4549 ((status & HDSPM_BufferPositionMask) - 64) % 4549 ((status & HDSPM_BufferPositionMask) - 64) %
4550 (2 * (int)hdspm->period_bytes), 4550 (2 * (int)hdspm->period_bytes),
4551 (long) hdspm_hw_pointer(hdspm) * 4); 4551 (long) hdspm_hw_pointer(hdspm) * 4);
4552 4552
4553 snd_iprintf(buffer, 4553 snd_iprintf(buffer,
4554 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 4554 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4555 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 4555 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4556 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 4556 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4557 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 4557 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4558 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 4558 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4559 snd_iprintf(buffer, 4559 snd_iprintf(buffer,
4560 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 4560 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4561 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 4561 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4562 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 4562 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4563 snd_iprintf(buffer, 4563 snd_iprintf(buffer,
4564 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 4564 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4565 "status2=0x%x\n", 4565 "status2=0x%x\n",
4566 hdspm->control_register, hdspm->control2_register, 4566 hdspm->control_register, hdspm->control2_register,
4567 status, status2); 4567 status, status2);
4568 if (status & HDSPM_tco_detect) { 4568 if (status & HDSPM_tco_detect) {
4569 snd_iprintf(buffer, "TCO module detected.\n"); 4569 snd_iprintf(buffer, "TCO module detected.\n");
4570 a = hdspm_read(hdspm, HDSPM_RD_TCO+4); 4570 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4571 if (a & HDSPM_TCO1_LTC_Input_valid) { 4571 if (a & HDSPM_TCO1_LTC_Input_valid) {
4572 snd_iprintf(buffer, " LTC valid, "); 4572 snd_iprintf(buffer, " LTC valid, ");
4573 switch (a & (HDSPM_TCO1_LTC_Format_LSB | 4573 switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4574 HDSPM_TCO1_LTC_Format_MSB)) { 4574 HDSPM_TCO1_LTC_Format_MSB)) {
4575 case 0: 4575 case 0:
4576 snd_iprintf(buffer, "24 fps, "); 4576 snd_iprintf(buffer, "24 fps, ");
4577 break; 4577 break;
4578 case HDSPM_TCO1_LTC_Format_LSB: 4578 case HDSPM_TCO1_LTC_Format_LSB:
4579 snd_iprintf(buffer, "25 fps, "); 4579 snd_iprintf(buffer, "25 fps, ");
4580 break; 4580 break;
4581 case HDSPM_TCO1_LTC_Format_MSB: 4581 case HDSPM_TCO1_LTC_Format_MSB:
4582 snd_iprintf(buffer, "29.97 fps, "); 4582 snd_iprintf(buffer, "29.97 fps, ");
4583 break; 4583 break;
4584 default: 4584 default:
4585 snd_iprintf(buffer, "30 fps, "); 4585 snd_iprintf(buffer, "30 fps, ");
4586 break; 4586 break;
4587 } 4587 }
4588 if (a & HDSPM_TCO1_set_drop_frame_flag) { 4588 if (a & HDSPM_TCO1_set_drop_frame_flag) {
4589 snd_iprintf(buffer, "drop frame\n"); 4589 snd_iprintf(buffer, "drop frame\n");
4590 } else { 4590 } else {
4591 snd_iprintf(buffer, "full frame\n"); 4591 snd_iprintf(buffer, "full frame\n");
4592 } 4592 }
4593 } else { 4593 } else {
4594 snd_iprintf(buffer, " no LTC\n"); 4594 snd_iprintf(buffer, " no LTC\n");
4595 } 4595 }
4596 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) { 4596 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4597 snd_iprintf(buffer, " Video: NTSC\n"); 4597 snd_iprintf(buffer, " Video: NTSC\n");
4598 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) { 4598 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4599 snd_iprintf(buffer, " Video: PAL\n"); 4599 snd_iprintf(buffer, " Video: PAL\n");
4600 } else { 4600 } else {
4601 snd_iprintf(buffer, " No video\n"); 4601 snd_iprintf(buffer, " No video\n");
4602 } 4602 }
4603 if (a & HDSPM_TCO1_TCO_lock) { 4603 if (a & HDSPM_TCO1_TCO_lock) {
4604 snd_iprintf(buffer, " Sync: lock\n"); 4604 snd_iprintf(buffer, " Sync: lock\n");
4605 } else { 4605 } else {
4606 snd_iprintf(buffer, " Sync: no lock\n"); 4606 snd_iprintf(buffer, " Sync: no lock\n");
4607 } 4607 }
4608 4608
4609 switch (hdspm->io_type) { 4609 switch (hdspm->io_type) {
4610 case MADI: 4610 case MADI:
4611 case AES32: 4611 case AES32:
4612 freq_const = 110069313433624ULL; 4612 freq_const = 110069313433624ULL;
4613 break; 4613 break;
4614 case RayDAT: 4614 case RayDAT:
4615 case AIO: 4615 case AIO:
4616 freq_const = 104857600000000ULL; 4616 freq_const = 104857600000000ULL;
4617 break; 4617 break;
4618 case MADIface: 4618 case MADIface:
4619 break; /* no TCO possible */ 4619 break; /* no TCO possible */
4620 } 4620 }
4621 4621
4622 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 4622 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4623 snd_iprintf(buffer, " period: %u\n", period); 4623 snd_iprintf(buffer, " period: %u\n", period);
4624 4624
4625 4625
4626 /* rate = freq_const/period; */ 4626 /* rate = freq_const/period; */
4627 rate = div_u64(freq_const, period); 4627 rate = div_u64(freq_const, period);
4628 4628
4629 if (control & HDSPM_QuadSpeed) { 4629 if (control & HDSPM_QuadSpeed) {
4630 rate *= 4; 4630 rate *= 4;
4631 } else if (control & HDSPM_DoubleSpeed) { 4631 } else if (control & HDSPM_DoubleSpeed) {
4632 rate *= 2; 4632 rate *= 2;
4633 } 4633 }
4634 4634
4635 snd_iprintf(buffer, " Frequency: %u Hz\n", 4635 snd_iprintf(buffer, " Frequency: %u Hz\n",
4636 (unsigned int) rate); 4636 (unsigned int) rate);
4637 4637
4638 ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 4638 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4639 frames = ltc & 0xF; 4639 frames = ltc & 0xF;
4640 ltc >>= 4; 4640 ltc >>= 4;
4641 frames += (ltc & 0x3) * 10; 4641 frames += (ltc & 0x3) * 10;
4642 ltc >>= 4; 4642 ltc >>= 4;
4643 seconds = ltc & 0xF; 4643 seconds = ltc & 0xF;
4644 ltc >>= 4; 4644 ltc >>= 4;
4645 seconds += (ltc & 0x7) * 10; 4645 seconds += (ltc & 0x7) * 10;
4646 ltc >>= 4; 4646 ltc >>= 4;
4647 minutes = ltc & 0xF; 4647 minutes = ltc & 0xF;
4648 ltc >>= 4; 4648 ltc >>= 4;
4649 minutes += (ltc & 0x7) * 10; 4649 minutes += (ltc & 0x7) * 10;
4650 ltc >>= 4; 4650 ltc >>= 4;
4651 hours = ltc & 0xF; 4651 hours = ltc & 0xF;
4652 ltc >>= 4; 4652 ltc >>= 4;
4653 hours += (ltc & 0x3) * 10; 4653 hours += (ltc & 0x3) * 10;
4654 snd_iprintf(buffer, 4654 snd_iprintf(buffer,
4655 " LTC In: %02d:%02d:%02d:%02d\n", 4655 " LTC In: %02d:%02d:%02d:%02d\n",
4656 hours, minutes, seconds, frames); 4656 hours, minutes, seconds, frames);
4657 4657
4658 } else { 4658 } else {
4659 snd_iprintf(buffer, "No TCO module detected.\n"); 4659 snd_iprintf(buffer, "No TCO module detected.\n");
4660 } 4660 }
4661 4661
4662 snd_iprintf(buffer, "--- Settings ---\n"); 4662 snd_iprintf(buffer, "--- Settings ---\n");
4663 4663
4664 x = 1 << (6 + hdspm_decode_latency(hdspm->control_register & 4664 x = 1 << (6 + hdspm_decode_latency(hdspm->control_register &
4665 HDSPM_LatencyMask)); 4665 HDSPM_LatencyMask));
4666 4666
4667 snd_iprintf(buffer, 4667 snd_iprintf(buffer,
4668 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 4668 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4669 x, (unsigned long) hdspm->period_bytes); 4669 x, (unsigned long) hdspm->period_bytes);
4670 4670
4671 snd_iprintf(buffer, "Line out: %s\n", 4671 snd_iprintf(buffer, "Line out: %s\n",
4672 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off"); 4672 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4673 4673
4674 switch (hdspm->control_register & HDSPM_InputMask) { 4674 switch (hdspm->control_register & HDSPM_InputMask) {
4675 case HDSPM_InputOptical: 4675 case HDSPM_InputOptical:
4676 insel = "Optical"; 4676 insel = "Optical";
4677 break; 4677 break;
4678 case HDSPM_InputCoaxial: 4678 case HDSPM_InputCoaxial:
4679 insel = "Coaxial"; 4679 insel = "Coaxial";
4680 break; 4680 break;
4681 default: 4681 default:
4682 insel = "Unkown"; 4682 insel = "Unkown";
4683 } 4683 }
4684 4684
4685 snd_iprintf(buffer, 4685 snd_iprintf(buffer,
4686 "ClearTrackMarker = %s, Transmit in %s Channel Mode, " 4686 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4687 "Auto Input %s\n", 4687 "Auto Input %s\n",
4688 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off", 4688 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4689 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56", 4689 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4690 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off"); 4690 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4691 4691
4692 4692
4693 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) 4693 if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4694 system_clock_mode = "AutoSync"; 4694 system_clock_mode = "AutoSync";
4695 else 4695 else
4696 system_clock_mode = "Master"; 4696 system_clock_mode = "Master";
4697 snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode); 4697 snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4698 4698
4699 switch (hdspm_pref_sync_ref(hdspm)) { 4699 switch (hdspm_pref_sync_ref(hdspm)) {
4700 case HDSPM_SYNC_FROM_WORD: 4700 case HDSPM_SYNC_FROM_WORD:
4701 pref_sync_ref = "Word Clock"; 4701 pref_sync_ref = "Word Clock";
4702 break; 4702 break;
4703 case HDSPM_SYNC_FROM_MADI: 4703 case HDSPM_SYNC_FROM_MADI:
4704 pref_sync_ref = "MADI Sync"; 4704 pref_sync_ref = "MADI Sync";
4705 break; 4705 break;
4706 case HDSPM_SYNC_FROM_TCO: 4706 case HDSPM_SYNC_FROM_TCO:
4707 pref_sync_ref = "TCO"; 4707 pref_sync_ref = "TCO";
4708 break; 4708 break;
4709 case HDSPM_SYNC_FROM_SYNC_IN: 4709 case HDSPM_SYNC_FROM_SYNC_IN:
4710 pref_sync_ref = "Sync In"; 4710 pref_sync_ref = "Sync In";
4711 break; 4711 break;
4712 default: 4712 default:
4713 pref_sync_ref = "XXXX Clock"; 4713 pref_sync_ref = "XXXX Clock";
4714 break; 4714 break;
4715 } 4715 }
4716 snd_iprintf(buffer, "Preferred Sync Reference: %s\n", 4716 snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4717 pref_sync_ref); 4717 pref_sync_ref);
4718 4718
4719 snd_iprintf(buffer, "System Clock Frequency: %d\n", 4719 snd_iprintf(buffer, "System Clock Frequency: %d\n",
4720 hdspm->system_sample_rate); 4720 hdspm->system_sample_rate);
4721 4721
4722 4722
4723 snd_iprintf(buffer, "--- Status:\n"); 4723 snd_iprintf(buffer, "--- Status:\n");
4724 4724
4725 x = status & HDSPM_madiSync; 4725 x = status & HDSPM_madiSync;
4726 x2 = status2 & HDSPM_wcSync; 4726 x2 = status2 & HDSPM_wcSync;
4727 4727
4728 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n", 4728 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
4729 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") : 4729 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4730 "NoLock", 4730 "NoLock",
4731 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") : 4731 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4732 "NoLock"); 4732 "NoLock");
4733 4733
4734 switch (hdspm_autosync_ref(hdspm)) { 4734 switch (hdspm_autosync_ref(hdspm)) {
4735 case HDSPM_AUTOSYNC_FROM_SYNC_IN: 4735 case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4736 autosync_ref = "Sync In"; 4736 autosync_ref = "Sync In";
4737 break; 4737 break;
4738 case HDSPM_AUTOSYNC_FROM_TCO: 4738 case HDSPM_AUTOSYNC_FROM_TCO:
4739 autosync_ref = "TCO"; 4739 autosync_ref = "TCO";
4740 break; 4740 break;
4741 case HDSPM_AUTOSYNC_FROM_WORD: 4741 case HDSPM_AUTOSYNC_FROM_WORD:
4742 autosync_ref = "Word Clock"; 4742 autosync_ref = "Word Clock";
4743 break; 4743 break;
4744 case HDSPM_AUTOSYNC_FROM_MADI: 4744 case HDSPM_AUTOSYNC_FROM_MADI:
4745 autosync_ref = "MADI Sync"; 4745 autosync_ref = "MADI Sync";
4746 break; 4746 break;
4747 case HDSPM_AUTOSYNC_FROM_NONE: 4747 case HDSPM_AUTOSYNC_FROM_NONE:
4748 autosync_ref = "Input not valid"; 4748 autosync_ref = "Input not valid";
4749 break; 4749 break;
4750 default: 4750 default:
4751 autosync_ref = "---"; 4751 autosync_ref = "---";
4752 break; 4752 break;
4753 } 4753 }
4754 snd_iprintf(buffer, 4754 snd_iprintf(buffer,
4755 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n", 4755 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
4756 autosync_ref, hdspm_external_sample_rate(hdspm), 4756 autosync_ref, hdspm_external_sample_rate(hdspm),
4757 (status & HDSPM_madiFreqMask) >> 22, 4757 (status & HDSPM_madiFreqMask) >> 22,
4758 (status2 & HDSPM_wcFreqMask) >> 5); 4758 (status2 & HDSPM_wcFreqMask) >> 5);
4759 4759
4760 snd_iprintf(buffer, "Input: %s, Mode=%s\n", 4760 snd_iprintf(buffer, "Input: %s, Mode=%s\n",
4761 (status & HDSPM_AB_int) ? "Coax" : "Optical", 4761 (status & HDSPM_AB_int) ? "Coax" : "Optical",
4762 (status & HDSPM_RX_64ch) ? "64 channels" : 4762 (status & HDSPM_RX_64ch) ? "64 channels" :
4763 "56 channels"); 4763 "56 channels");
4764 4764
4765 snd_iprintf(buffer, "\n"); 4765 snd_iprintf(buffer, "\n");
4766 } 4766 }
4767 4767
4768 static void 4768 static void
4769 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry, 4769 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
4770 struct snd_info_buffer *buffer) 4770 struct snd_info_buffer *buffer)
4771 { 4771 {
4772 struct hdspm *hdspm = entry->private_data; 4772 struct hdspm *hdspm = entry->private_data;
4773 unsigned int status; 4773 unsigned int status;
4774 unsigned int status2; 4774 unsigned int status2;
4775 unsigned int timecode; 4775 unsigned int timecode;
4776 int pref_syncref; 4776 int pref_syncref;
4777 char *autosync_ref; 4777 char *autosync_ref;
4778 int x; 4778 int x;
4779 4779
4780 status = hdspm_read(hdspm, HDSPM_statusRegister); 4780 status = hdspm_read(hdspm, HDSPM_statusRegister);
4781 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 4781 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4782 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 4782 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
4783 4783
4784 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n", 4784 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
4785 hdspm->card_name, hdspm->card->number + 1, 4785 hdspm->card_name, hdspm->card->number + 1,
4786 hdspm->firmware_rev); 4786 hdspm->firmware_rev);
4787 4787
4788 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 4788 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4789 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 4789 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4790 4790
4791 snd_iprintf(buffer, "--- System ---\n"); 4791 snd_iprintf(buffer, "--- System ---\n");
4792 4792
4793 snd_iprintf(buffer, 4793 snd_iprintf(buffer,
4794 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 4794 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4795 status & HDSPM_audioIRQPending, 4795 status & HDSPM_audioIRQPending,
4796 (status & HDSPM_midi0IRQPending) ? 1 : 0, 4796 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4797 (status & HDSPM_midi1IRQPending) ? 1 : 0, 4797 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4798 hdspm->irq_count); 4798 hdspm->irq_count);
4799 snd_iprintf(buffer, 4799 snd_iprintf(buffer,
4800 "HW pointer: id = %d, rawptr = %d (%d->%d) " 4800 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4801 "estimated= %ld (bytes)\n", 4801 "estimated= %ld (bytes)\n",
4802 ((status & HDSPM_BufferID) ? 1 : 0), 4802 ((status & HDSPM_BufferID) ? 1 : 0),
4803 (status & HDSPM_BufferPositionMask), 4803 (status & HDSPM_BufferPositionMask),
4804 (status & HDSPM_BufferPositionMask) % 4804 (status & HDSPM_BufferPositionMask) %
4805 (2 * (int)hdspm->period_bytes), 4805 (2 * (int)hdspm->period_bytes),
4806 ((status & HDSPM_BufferPositionMask) - 64) % 4806 ((status & HDSPM_BufferPositionMask) - 64) %
4807 (2 * (int)hdspm->period_bytes), 4807 (2 * (int)hdspm->period_bytes),
4808 (long) hdspm_hw_pointer(hdspm) * 4); 4808 (long) hdspm_hw_pointer(hdspm) * 4);
4809 4809
4810 snd_iprintf(buffer, 4810 snd_iprintf(buffer,
4811 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 4811 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4812 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 4812 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4813 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 4813 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4814 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 4814 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4815 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 4815 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4816 snd_iprintf(buffer, 4816 snd_iprintf(buffer,
4817 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 4817 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4818 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 4818 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4819 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 4819 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4820 snd_iprintf(buffer, 4820 snd_iprintf(buffer,
4821 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 4821 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4822 "status2=0x%x\n", 4822 "status2=0x%x\n",
4823 hdspm->control_register, hdspm->control2_register, 4823 hdspm->control_register, hdspm->control2_register,
4824 status, status2); 4824 status, status2);
4825 4825
4826 snd_iprintf(buffer, "--- Settings ---\n"); 4826 snd_iprintf(buffer, "--- Settings ---\n");
4827 4827
4828 x = 1 << (6 + hdspm_decode_latency(hdspm->control_register & 4828 x = 1 << (6 + hdspm_decode_latency(hdspm->control_register &
4829 HDSPM_LatencyMask)); 4829 HDSPM_LatencyMask));
4830 4830
4831 snd_iprintf(buffer, 4831 snd_iprintf(buffer,
4832 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 4832 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4833 x, (unsigned long) hdspm->period_bytes); 4833 x, (unsigned long) hdspm->period_bytes);
4834 4834
4835 snd_iprintf(buffer, "Line out: %s\n", 4835 snd_iprintf(buffer, "Line out: %s\n",
4836 (hdspm-> 4836 (hdspm->
4837 control_register & HDSPM_LineOut) ? "on " : "off"); 4837 control_register & HDSPM_LineOut) ? "on " : "off");
4838 4838
4839 snd_iprintf(buffer, 4839 snd_iprintf(buffer,
4840 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n", 4840 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
4841 (hdspm-> 4841 (hdspm->
4842 control_register & HDSPM_clr_tms) ? "on" : "off", 4842 control_register & HDSPM_clr_tms) ? "on" : "off",
4843 (hdspm-> 4843 (hdspm->
4844 control_register & HDSPM_Emphasis) ? "on" : "off", 4844 control_register & HDSPM_Emphasis) ? "on" : "off",
4845 (hdspm-> 4845 (hdspm->
4846 control_register & HDSPM_Dolby) ? "on" : "off"); 4846 control_register & HDSPM_Dolby) ? "on" : "off");
4847 4847
4848 4848
4849 pref_syncref = hdspm_pref_sync_ref(hdspm); 4849 pref_syncref = hdspm_pref_sync_ref(hdspm);
4850 if (pref_syncref == 0) 4850 if (pref_syncref == 0)
4851 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n"); 4851 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
4852 else 4852 else
4853 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n", 4853 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
4854 pref_syncref); 4854 pref_syncref);
4855 4855
4856 snd_iprintf(buffer, "System Clock Frequency: %d\n", 4856 snd_iprintf(buffer, "System Clock Frequency: %d\n",
4857 hdspm->system_sample_rate); 4857 hdspm->system_sample_rate);
4858 4858
4859 snd_iprintf(buffer, "Double speed: %s\n", 4859 snd_iprintf(buffer, "Double speed: %s\n",
4860 hdspm->control_register & HDSPM_DS_DoubleWire? 4860 hdspm->control_register & HDSPM_DS_DoubleWire?
4861 "Double wire" : "Single wire"); 4861 "Double wire" : "Single wire");
4862 snd_iprintf(buffer, "Quad speed: %s\n", 4862 snd_iprintf(buffer, "Quad speed: %s\n",
4863 hdspm->control_register & HDSPM_QS_DoubleWire? 4863 hdspm->control_register & HDSPM_QS_DoubleWire?
4864 "Double wire" : 4864 "Double wire" :
4865 hdspm->control_register & HDSPM_QS_QuadWire? 4865 hdspm->control_register & HDSPM_QS_QuadWire?
4866 "Quad wire" : "Single wire"); 4866 "Quad wire" : "Single wire");
4867 4867
4868 snd_iprintf(buffer, "--- Status:\n"); 4868 snd_iprintf(buffer, "--- Status:\n");
4869 4869
4870 snd_iprintf(buffer, "Word: %s Frequency: %d\n", 4870 snd_iprintf(buffer, "Word: %s Frequency: %d\n",
4871 (status & HDSPM_AES32_wcLock) ? "Sync " : "No Lock", 4871 (status & HDSPM_AES32_wcLock) ? "Sync " : "No Lock",
4872 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF)); 4872 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
4873 4873
4874 for (x = 0; x < 8; x++) { 4874 for (x = 0; x < 8; x++) {
4875 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n", 4875 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n",
4876 x+1, 4876 x+1,
4877 (status2 & (HDSPM_LockAES >> x)) ? 4877 (status2 & (HDSPM_LockAES >> x)) ?
4878 "Sync " : "No Lock", 4878 "Sync " : "No Lock",
4879 HDSPM_bit2freq((timecode >> (4*x)) & 0xF)); 4879 HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
4880 } 4880 }
4881 4881
4882 switch (hdspm_autosync_ref(hdspm)) { 4882 switch (hdspm_autosync_ref(hdspm)) {
4883 case HDSPM_AES32_AUTOSYNC_FROM_NONE: 4883 case HDSPM_AES32_AUTOSYNC_FROM_NONE:
4884 autosync_ref = "None"; break; 4884 autosync_ref = "None"; break;
4885 case HDSPM_AES32_AUTOSYNC_FROM_WORD: 4885 case HDSPM_AES32_AUTOSYNC_FROM_WORD:
4886 autosync_ref = "Word Clock"; break; 4886 autosync_ref = "Word Clock"; break;
4887 case HDSPM_AES32_AUTOSYNC_FROM_AES1: 4887 case HDSPM_AES32_AUTOSYNC_FROM_AES1:
4888 autosync_ref = "AES1"; break; 4888 autosync_ref = "AES1"; break;
4889 case HDSPM_AES32_AUTOSYNC_FROM_AES2: 4889 case HDSPM_AES32_AUTOSYNC_FROM_AES2:
4890 autosync_ref = "AES2"; break; 4890 autosync_ref = "AES2"; break;
4891 case HDSPM_AES32_AUTOSYNC_FROM_AES3: 4891 case HDSPM_AES32_AUTOSYNC_FROM_AES3:
4892 autosync_ref = "AES3"; break; 4892 autosync_ref = "AES3"; break;
4893 case HDSPM_AES32_AUTOSYNC_FROM_AES4: 4893 case HDSPM_AES32_AUTOSYNC_FROM_AES4:
4894 autosync_ref = "AES4"; break; 4894 autosync_ref = "AES4"; break;
4895 case HDSPM_AES32_AUTOSYNC_FROM_AES5: 4895 case HDSPM_AES32_AUTOSYNC_FROM_AES5:
4896 autosync_ref = "AES5"; break; 4896 autosync_ref = "AES5"; break;
4897 case HDSPM_AES32_AUTOSYNC_FROM_AES6: 4897 case HDSPM_AES32_AUTOSYNC_FROM_AES6:
4898 autosync_ref = "AES6"; break; 4898 autosync_ref = "AES6"; break;
4899 case HDSPM_AES32_AUTOSYNC_FROM_AES7: 4899 case HDSPM_AES32_AUTOSYNC_FROM_AES7:
4900 autosync_ref = "AES7"; break; 4900 autosync_ref = "AES7"; break;
4901 case HDSPM_AES32_AUTOSYNC_FROM_AES8: 4901 case HDSPM_AES32_AUTOSYNC_FROM_AES8:
4902 autosync_ref = "AES8"; break; 4902 autosync_ref = "AES8"; break;
4903 default: 4903 default:
4904 autosync_ref = "---"; break; 4904 autosync_ref = "---"; break;
4905 } 4905 }
4906 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref); 4906 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
4907 4907
4908 snd_iprintf(buffer, "\n"); 4908 snd_iprintf(buffer, "\n");
4909 } 4909 }
4910 4910
4911 static void 4911 static void
4912 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry, 4912 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
4913 struct snd_info_buffer *buffer) 4913 struct snd_info_buffer *buffer)
4914 { 4914 {
4915 struct hdspm *hdspm = entry->private_data; 4915 struct hdspm *hdspm = entry->private_data;
4916 unsigned int status1, status2, status3, control, i; 4916 unsigned int status1, status2, status3, control, i;
4917 unsigned int lock, sync; 4917 unsigned int lock, sync;
4918 4918
4919 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */ 4919 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
4920 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */ 4920 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
4921 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */ 4921 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
4922 4922
4923 control = hdspm->control_register; 4923 control = hdspm->control_register;
4924 4924
4925 snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1); 4925 snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
4926 snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2); 4926 snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
4927 snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3); 4927 snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
4928 4928
4929 4929
4930 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n"); 4930 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
4931 4931
4932 snd_iprintf(buffer, "Clock mode : %s\n", 4932 snd_iprintf(buffer, "Clock mode : %s\n",
4933 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave"); 4933 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
4934 snd_iprintf(buffer, "System frequency: %d Hz\n", 4934 snd_iprintf(buffer, "System frequency: %d Hz\n",
4935 hdspm_get_system_sample_rate(hdspm)); 4935 hdspm_get_system_sample_rate(hdspm));
4936 4936
4937 snd_iprintf(buffer, "\n*** INPUT STATUS\n\n"); 4937 snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
4938 4938
4939 lock = 0x1; 4939 lock = 0x1;
4940 sync = 0x100; 4940 sync = 0x100;
4941 4941
4942 for (i = 0; i < 8; i++) { 4942 for (i = 0; i < 8; i++) {
4943 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n", 4943 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
4944 i, 4944 i,
4945 (status1 & lock) ? 1 : 0, 4945 (status1 & lock) ? 1 : 0,
4946 (status1 & sync) ? 1 : 0, 4946 (status1 & sync) ? 1 : 0,
4947 texts_freq[(status2 >> (i * 4)) & 0xF]); 4947 texts_freq[(status2 >> (i * 4)) & 0xF]);
4948 4948
4949 lock = lock<<1; 4949 lock = lock<<1;
4950 sync = sync<<1; 4950 sync = sync<<1;
4951 } 4951 }
4952 4952
4953 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n", 4953 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
4954 (status1 & 0x1000000) ? 1 : 0, 4954 (status1 & 0x1000000) ? 1 : 0,
4955 (status1 & 0x2000000) ? 1 : 0, 4955 (status1 & 0x2000000) ? 1 : 0,
4956 texts_freq[(status1 >> 16) & 0xF]); 4956 texts_freq[(status1 >> 16) & 0xF]);
4957 4957
4958 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n", 4958 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
4959 (status1 & 0x4000000) ? 1 : 0, 4959 (status1 & 0x4000000) ? 1 : 0,
4960 (status1 & 0x8000000) ? 1 : 0, 4960 (status1 & 0x8000000) ? 1 : 0,
4961 texts_freq[(status1 >> 20) & 0xF]); 4961 texts_freq[(status1 >> 20) & 0xF]);
4962 4962
4963 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n", 4963 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
4964 (status3 & 0x400) ? 1 : 0, 4964 (status3 & 0x400) ? 1 : 0,
4965 (status3 & 0x800) ? 1 : 0, 4965 (status3 & 0x800) ? 1 : 0,
4966 texts_freq[(status2 >> 12) & 0xF]); 4966 texts_freq[(status2 >> 12) & 0xF]);
4967 4967
4968 } 4968 }
4969 4969
4970 #ifdef CONFIG_SND_DEBUG 4970 #ifdef CONFIG_SND_DEBUG
4971 static void 4971 static void
4972 snd_hdspm_proc_read_debug(struct snd_info_entry *entry, 4972 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
4973 struct snd_info_buffer *buffer) 4973 struct snd_info_buffer *buffer)
4974 { 4974 {
4975 struct hdspm *hdspm = entry->private_data; 4975 struct hdspm *hdspm = entry->private_data;
4976 4976
4977 int j,i; 4977 int j,i;
4978 4978
4979 for (i = 0; i < 256 /* 1024*64 */; i += j) { 4979 for (i = 0; i < 256 /* 1024*64 */; i += j) {
4980 snd_iprintf(buffer, "0x%08X: ", i); 4980 snd_iprintf(buffer, "0x%08X: ", i);
4981 for (j = 0; j < 16; j += 4) 4981 for (j = 0; j < 16; j += 4)
4982 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j)); 4982 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
4983 snd_iprintf(buffer, "\n"); 4983 snd_iprintf(buffer, "\n");
4984 } 4984 }
4985 } 4985 }
4986 #endif 4986 #endif
4987 4987
4988 4988
4989 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry, 4989 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
4990 struct snd_info_buffer *buffer) 4990 struct snd_info_buffer *buffer)
4991 { 4991 {
4992 struct hdspm *hdspm = entry->private_data; 4992 struct hdspm *hdspm = entry->private_data;
4993 int i; 4993 int i;
4994 4994
4995 snd_iprintf(buffer, "# generated by hdspm\n"); 4995 snd_iprintf(buffer, "# generated by hdspm\n");
4996 4996
4997 for (i = 0; i < hdspm->max_channels_in; i++) { 4997 for (i = 0; i < hdspm->max_channels_in; i++) {
4998 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]); 4998 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
4999 } 4999 }
5000 } 5000 }
5001 5001
5002 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry, 5002 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5003 struct snd_info_buffer *buffer) 5003 struct snd_info_buffer *buffer)
5004 { 5004 {
5005 struct hdspm *hdspm = entry->private_data; 5005 struct hdspm *hdspm = entry->private_data;
5006 int i; 5006 int i;
5007 5007
5008 snd_iprintf(buffer, "# generated by hdspm\n"); 5008 snd_iprintf(buffer, "# generated by hdspm\n");
5009 5009
5010 for (i = 0; i < hdspm->max_channels_out; i++) { 5010 for (i = 0; i < hdspm->max_channels_out; i++) {
5011 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]); 5011 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5012 } 5012 }
5013 } 5013 }
5014 5014
5015 5015
5016 static void __devinit snd_hdspm_proc_init(struct hdspm *hdspm) 5016 static void __devinit snd_hdspm_proc_init(struct hdspm *hdspm)
5017 { 5017 {
5018 struct snd_info_entry *entry; 5018 struct snd_info_entry *entry;
5019 5019
5020 if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) { 5020 if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5021 switch (hdspm->io_type) { 5021 switch (hdspm->io_type) {
5022 case AES32: 5022 case AES32:
5023 snd_info_set_text_ops(entry, hdspm, 5023 snd_info_set_text_ops(entry, hdspm,
5024 snd_hdspm_proc_read_aes32); 5024 snd_hdspm_proc_read_aes32);
5025 break; 5025 break;
5026 case MADI: 5026 case MADI:
5027 snd_info_set_text_ops(entry, hdspm, 5027 snd_info_set_text_ops(entry, hdspm,
5028 snd_hdspm_proc_read_madi); 5028 snd_hdspm_proc_read_madi);
5029 break; 5029 break;
5030 case MADIface: 5030 case MADIface:
5031 /* snd_info_set_text_ops(entry, hdspm, 5031 /* snd_info_set_text_ops(entry, hdspm,
5032 snd_hdspm_proc_read_madiface); */ 5032 snd_hdspm_proc_read_madiface); */
5033 break; 5033 break;
5034 case RayDAT: 5034 case RayDAT:
5035 snd_info_set_text_ops(entry, hdspm, 5035 snd_info_set_text_ops(entry, hdspm,
5036 snd_hdspm_proc_read_raydat); 5036 snd_hdspm_proc_read_raydat);
5037 break; 5037 break;
5038 case AIO: 5038 case AIO:
5039 break; 5039 break;
5040 } 5040 }
5041 } 5041 }
5042 5042
5043 if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) { 5043 if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5044 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in); 5044 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5045 } 5045 }
5046 5046
5047 if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) { 5047 if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5048 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out); 5048 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5049 } 5049 }
5050 5050
5051 #ifdef CONFIG_SND_DEBUG 5051 #ifdef CONFIG_SND_DEBUG
5052 /* debug file to read all hdspm registers */ 5052 /* debug file to read all hdspm registers */
5053 if (!snd_card_proc_new(hdspm->card, "debug", &entry)) 5053 if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5054 snd_info_set_text_ops(entry, hdspm, 5054 snd_info_set_text_ops(entry, hdspm,
5055 snd_hdspm_proc_read_debug); 5055 snd_hdspm_proc_read_debug);
5056 #endif 5056 #endif
5057 } 5057 }
5058 5058
5059 /*------------------------------------------------------------ 5059 /*------------------------------------------------------------
5060 hdspm intitialize 5060 hdspm intitialize
5061 ------------------------------------------------------------*/ 5061 ------------------------------------------------------------*/
5062 5062
5063 static int snd_hdspm_set_defaults(struct hdspm * hdspm) 5063 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5064 { 5064 {
5065 /* ASSUMPTION: hdspm->lock is either held, or there is no need to 5065 /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5066 hold it (e.g. during module initialization). 5066 hold it (e.g. during module initialization).
5067 */ 5067 */
5068 5068
5069 /* set defaults: */ 5069 /* set defaults: */
5070 5070
5071 hdspm->settings_register = 0; 5071 hdspm->settings_register = 0;
5072 5072
5073 switch (hdspm->io_type) { 5073 switch (hdspm->io_type) {
5074 case MADI: 5074 case MADI:
5075 case MADIface: 5075 case MADIface:
5076 hdspm->control_register = 5076 hdspm->control_register =
5077 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 5077 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5078 break; 5078 break;
5079 5079
5080 case RayDAT: 5080 case RayDAT:
5081 case AIO: 5081 case AIO:
5082 hdspm->settings_register = 0x1 + 0x1000; 5082 hdspm->settings_register = 0x1 + 0x1000;
5083 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0, 5083 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5084 * line_out */ 5084 * line_out */
5085 hdspm->control_register = 5085 hdspm->control_register =
5086 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 5086 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5087 break; 5087 break;
5088 5088
5089 case AES32: 5089 case AES32:
5090 hdspm->control_register = 5090 hdspm->control_register =
5091 HDSPM_ClockModeMaster | /* Master Cloack Mode on */ 5091 HDSPM_ClockModeMaster | /* Master Cloack Mode on */
5092 hdspm_encode_latency(7) | /* latency max=8192samples */ 5092 hdspm_encode_latency(7) | /* latency max=8192samples */
5093 HDSPM_SyncRef0 | /* AES1 is syncclock */ 5093 HDSPM_SyncRef0 | /* AES1 is syncclock */
5094 HDSPM_LineOut | /* Analog output in */ 5094 HDSPM_LineOut | /* Analog output in */
5095 HDSPM_Professional; /* Professional mode */ 5095 HDSPM_Professional; /* Professional mode */
5096 break; 5096 break;
5097 } 5097 }
5098 5098
5099 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 5099 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5100 5100
5101 if (AES32 == hdspm->io_type) { 5101 if (AES32 == hdspm->io_type) {
5102 /* No control2 register for AES32 */ 5102 /* No control2 register for AES32 */
5103 #ifdef SNDRV_BIG_ENDIAN 5103 #ifdef SNDRV_BIG_ENDIAN
5104 hdspm->control2_register = HDSPM_BIGENDIAN_MODE; 5104 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5105 #else 5105 #else
5106 hdspm->control2_register = 0; 5106 hdspm->control2_register = 0;
5107 #endif 5107 #endif
5108 5108
5109 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register); 5109 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5110 } 5110 }
5111 hdspm_compute_period_size(hdspm); 5111 hdspm_compute_period_size(hdspm);
5112 5112
5113 /* silence everything */ 5113 /* silence everything */
5114 5114
5115 all_in_all_mixer(hdspm, 0 * UNITY_GAIN); 5115 all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5116 5116
5117 if (hdspm->io_type == AIO || hdspm->io_type == RayDAT) { 5117 if (hdspm->io_type == AIO || hdspm->io_type == RayDAT) {
5118 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 5118 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5119 } 5119 }
5120 5120
5121 /* set a default rate so that the channel map is set up. */ 5121 /* set a default rate so that the channel map is set up. */
5122 hdspm_set_rate(hdspm, 48000, 1); 5122 hdspm_set_rate(hdspm, 48000, 1);
5123 5123
5124 return 0; 5124 return 0;
5125 } 5125 }
5126 5126
5127 5127
5128 /*------------------------------------------------------------ 5128 /*------------------------------------------------------------
5129 interrupt 5129 interrupt
5130 ------------------------------------------------------------*/ 5130 ------------------------------------------------------------*/
5131 5131
5132 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id) 5132 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5133 { 5133 {
5134 struct hdspm *hdspm = (struct hdspm *) dev_id; 5134 struct hdspm *hdspm = (struct hdspm *) dev_id;
5135 unsigned int status; 5135 unsigned int status;
5136 int i, audio, midi, schedule = 0; 5136 int i, audio, midi, schedule = 0;
5137 /* cycles_t now; */ 5137 /* cycles_t now; */
5138 5138
5139 status = hdspm_read(hdspm, HDSPM_statusRegister); 5139 status = hdspm_read(hdspm, HDSPM_statusRegister);
5140 5140
5141 audio = status & HDSPM_audioIRQPending; 5141 audio = status & HDSPM_audioIRQPending;
5142 midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending | 5142 midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5143 HDSPM_midi2IRQPending | HDSPM_midi3IRQPending); 5143 HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5144 5144
5145 /* now = get_cycles(); */ 5145 /* now = get_cycles(); */
5146 /** 5146 /**
5147 * LAT_2..LAT_0 period counter (win) counter (mac) 5147 * LAT_2..LAT_0 period counter (win) counter (mac)
5148 * 6 4096 ~256053425 ~514672358 5148 * 6 4096 ~256053425 ~514672358
5149 * 5 2048 ~128024983 ~257373821 5149 * 5 2048 ~128024983 ~257373821
5150 * 4 1024 ~64023706 ~128718089 5150 * 4 1024 ~64023706 ~128718089
5151 * 3 512 ~32005945 ~64385999 5151 * 3 512 ~32005945 ~64385999
5152 * 2 256 ~16003039 ~32260176 5152 * 2 256 ~16003039 ~32260176
5153 * 1 128 ~7998738 ~16194507 5153 * 1 128 ~7998738 ~16194507
5154 * 0 64 ~3998231 ~8191558 5154 * 0 64 ~3998231 ~8191558
5155 **/ 5155 **/
5156 /* 5156 /*
5157 snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n", 5157 snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n",
5158 now-hdspm->last_interrupt, status & 0xFFC0); 5158 now-hdspm->last_interrupt, status & 0xFFC0);
5159 hdspm->last_interrupt = now; 5159 hdspm->last_interrupt = now;
5160 */ 5160 */
5161 5161
5162 if (!audio && !midi) 5162 if (!audio && !midi)
5163 return IRQ_NONE; 5163 return IRQ_NONE;
5164 5164
5165 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0); 5165 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5166 hdspm->irq_count++; 5166 hdspm->irq_count++;
5167 5167
5168 5168
5169 if (audio) { 5169 if (audio) {
5170 if (hdspm->capture_substream) 5170 if (hdspm->capture_substream)
5171 snd_pcm_period_elapsed(hdspm->capture_substream); 5171 snd_pcm_period_elapsed(hdspm->capture_substream);
5172 5172
5173 if (hdspm->playback_substream) 5173 if (hdspm->playback_substream)
5174 snd_pcm_period_elapsed(hdspm->playback_substream); 5174 snd_pcm_period_elapsed(hdspm->playback_substream);
5175 } 5175 }
5176 5176
5177 if (midi) { 5177 if (midi) {
5178 i = 0; 5178 i = 0;
5179 while (i < hdspm->midiPorts) { 5179 while (i < hdspm->midiPorts) {
5180 if ((hdspm_read(hdspm, 5180 if ((hdspm_read(hdspm,
5181 hdspm->midi[i].statusIn) & 0xff) && 5181 hdspm->midi[i].statusIn) & 0xff) &&
5182 (status & hdspm->midi[i].irq)) { 5182 (status & hdspm->midi[i].irq)) {
5183 /* we disable interrupts for this input until 5183 /* we disable interrupts for this input until
5184 * processing is done 5184 * processing is done
5185 */ 5185 */
5186 hdspm->control_register &= ~hdspm->midi[i].ie; 5186 hdspm->control_register &= ~hdspm->midi[i].ie;
5187 hdspm_write(hdspm, HDSPM_controlRegister, 5187 hdspm_write(hdspm, HDSPM_controlRegister,
5188 hdspm->control_register); 5188 hdspm->control_register);
5189 hdspm->midi[i].pending = 1; 5189 hdspm->midi[i].pending = 1;
5190 schedule = 1; 5190 schedule = 1;
5191 } 5191 }
5192 5192
5193 i++; 5193 i++;
5194 } 5194 }
5195 5195
5196 if (schedule) 5196 if (schedule)
5197 tasklet_hi_schedule(&hdspm->midi_tasklet); 5197 tasklet_hi_schedule(&hdspm->midi_tasklet);
5198 } 5198 }
5199 5199
5200 return IRQ_HANDLED; 5200 return IRQ_HANDLED;
5201 } 5201 }
5202 5202
5203 /*------------------------------------------------------------ 5203 /*------------------------------------------------------------
5204 pcm interface 5204 pcm interface
5205 ------------------------------------------------------------*/ 5205 ------------------------------------------------------------*/
5206 5206
5207 5207
5208 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream 5208 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5209 *substream) 5209 *substream)
5210 { 5210 {
5211 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5211 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5212 return hdspm_hw_pointer(hdspm); 5212 return hdspm_hw_pointer(hdspm);
5213 } 5213 }
5214 5214
5215 5215
5216 static int snd_hdspm_reset(struct snd_pcm_substream *substream) 5216 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5217 { 5217 {
5218 struct snd_pcm_runtime *runtime = substream->runtime; 5218 struct snd_pcm_runtime *runtime = substream->runtime;
5219 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5219 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5220 struct snd_pcm_substream *other; 5220 struct snd_pcm_substream *other;
5221 5221
5222 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5222 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5223 other = hdspm->capture_substream; 5223 other = hdspm->capture_substream;
5224 else 5224 else
5225 other = hdspm->playback_substream; 5225 other = hdspm->playback_substream;
5226 5226
5227 if (hdspm->running) 5227 if (hdspm->running)
5228 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm); 5228 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5229 else 5229 else
5230 runtime->status->hw_ptr = 0; 5230 runtime->status->hw_ptr = 0;
5231 if (other) { 5231 if (other) {
5232 struct snd_pcm_substream *s; 5232 struct snd_pcm_substream *s;
5233 struct snd_pcm_runtime *oruntime = other->runtime; 5233 struct snd_pcm_runtime *oruntime = other->runtime;
5234 snd_pcm_group_for_each_entry(s, substream) { 5234 snd_pcm_group_for_each_entry(s, substream) {
5235 if (s == other) { 5235 if (s == other) {
5236 oruntime->status->hw_ptr = 5236 oruntime->status->hw_ptr =
5237 runtime->status->hw_ptr; 5237 runtime->status->hw_ptr;
5238 break; 5238 break;
5239 } 5239 }
5240 } 5240 }
5241 } 5241 }
5242 return 0; 5242 return 0;
5243 } 5243 }
5244 5244
5245 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream, 5245 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5246 struct snd_pcm_hw_params *params) 5246 struct snd_pcm_hw_params *params)
5247 { 5247 {
5248 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5248 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5249 int err; 5249 int err;
5250 int i; 5250 int i;
5251 pid_t this_pid; 5251 pid_t this_pid;
5252 pid_t other_pid; 5252 pid_t other_pid;
5253 5253
5254 spin_lock_irq(&hdspm->lock); 5254 spin_lock_irq(&hdspm->lock);
5255 5255
5256 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5256 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5257 this_pid = hdspm->playback_pid; 5257 this_pid = hdspm->playback_pid;
5258 other_pid = hdspm->capture_pid; 5258 other_pid = hdspm->capture_pid;
5259 } else { 5259 } else {
5260 this_pid = hdspm->capture_pid; 5260 this_pid = hdspm->capture_pid;
5261 other_pid = hdspm->playback_pid; 5261 other_pid = hdspm->playback_pid;
5262 } 5262 }
5263 5263
5264 if (other_pid > 0 && this_pid != other_pid) { 5264 if (other_pid > 0 && this_pid != other_pid) {
5265 5265
5266 /* The other stream is open, and not by the same 5266 /* The other stream is open, and not by the same
5267 task as this one. Make sure that the parameters 5267 task as this one. Make sure that the parameters
5268 that matter are the same. 5268 that matter are the same.
5269 */ 5269 */
5270 5270
5271 if (params_rate(params) != hdspm->system_sample_rate) { 5271 if (params_rate(params) != hdspm->system_sample_rate) {
5272 spin_unlock_irq(&hdspm->lock); 5272 spin_unlock_irq(&hdspm->lock);
5273 _snd_pcm_hw_param_setempty(params, 5273 _snd_pcm_hw_param_setempty(params,
5274 SNDRV_PCM_HW_PARAM_RATE); 5274 SNDRV_PCM_HW_PARAM_RATE);
5275 return -EBUSY; 5275 return -EBUSY;
5276 } 5276 }
5277 5277
5278 if (params_period_size(params) != hdspm->period_bytes / 4) { 5278 if (params_period_size(params) != hdspm->period_bytes / 4) {
5279 spin_unlock_irq(&hdspm->lock); 5279 spin_unlock_irq(&hdspm->lock);
5280 _snd_pcm_hw_param_setempty(params, 5280 _snd_pcm_hw_param_setempty(params,
5281 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5281 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5282 return -EBUSY; 5282 return -EBUSY;
5283 } 5283 }
5284 5284
5285 } 5285 }
5286 /* We're fine. */ 5286 /* We're fine. */
5287 spin_unlock_irq(&hdspm->lock); 5287 spin_unlock_irq(&hdspm->lock);
5288 5288
5289 /* how to make sure that the rate matches an externally-set one ? */ 5289 /* how to make sure that the rate matches an externally-set one ? */
5290 5290
5291 spin_lock_irq(&hdspm->lock); 5291 spin_lock_irq(&hdspm->lock);
5292 err = hdspm_set_rate(hdspm, params_rate(params), 0); 5292 err = hdspm_set_rate(hdspm, params_rate(params), 0);
5293 if (err < 0) { 5293 if (err < 0) {
5294 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err); 5294 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err);
5295 spin_unlock_irq(&hdspm->lock); 5295 spin_unlock_irq(&hdspm->lock);
5296 _snd_pcm_hw_param_setempty(params, 5296 _snd_pcm_hw_param_setempty(params,
5297 SNDRV_PCM_HW_PARAM_RATE); 5297 SNDRV_PCM_HW_PARAM_RATE);
5298 return err; 5298 return err;
5299 } 5299 }
5300 spin_unlock_irq(&hdspm->lock); 5300 spin_unlock_irq(&hdspm->lock);
5301 5301
5302 err = hdspm_set_interrupt_interval(hdspm, 5302 err = hdspm_set_interrupt_interval(hdspm,
5303 params_period_size(params)); 5303 params_period_size(params));
5304 if (err < 0) { 5304 if (err < 0) {
5305 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err); 5305 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err);
5306 _snd_pcm_hw_param_setempty(params, 5306 _snd_pcm_hw_param_setempty(params,
5307 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5307 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5308 return err; 5308 return err;
5309 } 5309 }
5310 5310
5311 /* Memory allocation, takashi's method, dont know if we should 5311 /* Memory allocation, takashi's method, dont know if we should
5312 * spinlock 5312 * spinlock
5313 */ 5313 */
5314 /* malloc all buffer even if not enabled to get sure */ 5314 /* malloc all buffer even if not enabled to get sure */
5315 /* Update for MADI rev 204: we need to allocate for all channels, 5315 /* Update for MADI rev 204: we need to allocate for all channels,
5316 * otherwise it doesn't work at 96kHz */ 5316 * otherwise it doesn't work at 96kHz */
5317 5317
5318 err = 5318 err =
5319 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES); 5319 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5320 if (err < 0) { 5320 if (err < 0) {
5321 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err); 5321 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err);
5322 return err; 5322 return err;
5323 } 5323 }
5324 5324
5325 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5325 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5326 5326
5327 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut, 5327 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
5328 params_channels(params)); 5328 params_channels(params));
5329 5329
5330 for (i = 0; i < params_channels(params); ++i) 5330 for (i = 0; i < params_channels(params); ++i)
5331 snd_hdspm_enable_out(hdspm, i, 1); 5331 snd_hdspm_enable_out(hdspm, i, 1);
5332 5332
5333 hdspm->playback_buffer = 5333 hdspm->playback_buffer =
5334 (unsigned char *) substream->runtime->dma_area; 5334 (unsigned char *) substream->runtime->dma_area;
5335 snd_printdd("Allocated sample buffer for playback at %p\n", 5335 snd_printdd("Allocated sample buffer for playback at %p\n",
5336 hdspm->playback_buffer); 5336 hdspm->playback_buffer);
5337 } else { 5337 } else {
5338 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn, 5338 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
5339 params_channels(params)); 5339 params_channels(params));
5340 5340
5341 for (i = 0; i < params_channels(params); ++i) 5341 for (i = 0; i < params_channels(params); ++i)
5342 snd_hdspm_enable_in(hdspm, i, 1); 5342 snd_hdspm_enable_in(hdspm, i, 1);
5343 5343
5344 hdspm->capture_buffer = 5344 hdspm->capture_buffer =
5345 (unsigned char *) substream->runtime->dma_area; 5345 (unsigned char *) substream->runtime->dma_area;
5346 snd_printdd("Allocated sample buffer for capture at %p\n", 5346 snd_printdd("Allocated sample buffer for capture at %p\n",
5347 hdspm->capture_buffer); 5347 hdspm->capture_buffer);
5348 } 5348 }
5349 5349
5350 /* 5350 /*
5351 snd_printdd("Allocated sample buffer for %s at 0x%08X\n", 5351 snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
5352 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 5352 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5353 "playback" : "capture", 5353 "playback" : "capture",
5354 snd_pcm_sgbuf_get_addr(substream, 0)); 5354 snd_pcm_sgbuf_get_addr(substream, 0));
5355 */ 5355 */
5356 /* 5356 /*
5357 snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n", 5357 snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5358 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 5358 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5359 "playback" : "capture", 5359 "playback" : "capture",
5360 params_rate(params), params_channels(params), 5360 params_rate(params), params_channels(params),
5361 params_buffer_size(params)); 5361 params_buffer_size(params));
5362 */ 5362 */
5363 5363
5364 5364
5365 /* Switch to native float format if requested */ 5365 /* Switch to native float format if requested */
5366 if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) { 5366 if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5367 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT)) 5367 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5368 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n"); 5368 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n");
5369 5369
5370 hdspm->control_register |= HDSPe_FLOAT_FORMAT; 5370 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5371 } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) { 5371 } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5372 if (hdspm->control_register & HDSPe_FLOAT_FORMAT) 5372 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5373 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n"); 5373 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n");
5374 5374
5375 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT; 5375 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5376 } 5376 }
5377 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 5377 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5378 5378
5379 return 0; 5379 return 0;
5380 } 5380 }
5381 5381
5382 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream) 5382 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5383 { 5383 {
5384 int i; 5384 int i;
5385 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5385 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5386 5386
5387 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5387 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5388 5388
5389 /* params_channels(params) should be enough, 5389 /* params_channels(params) should be enough,
5390 but to get sure in case of error */ 5390 but to get sure in case of error */
5391 for (i = 0; i < hdspm->max_channels_out; ++i) 5391 for (i = 0; i < hdspm->max_channels_out; ++i)
5392 snd_hdspm_enable_out(hdspm, i, 0); 5392 snd_hdspm_enable_out(hdspm, i, 0);
5393 5393
5394 hdspm->playback_buffer = NULL; 5394 hdspm->playback_buffer = NULL;
5395 } else { 5395 } else {
5396 for (i = 0; i < hdspm->max_channels_in; ++i) 5396 for (i = 0; i < hdspm->max_channels_in; ++i)
5397 snd_hdspm_enable_in(hdspm, i, 0); 5397 snd_hdspm_enable_in(hdspm, i, 0);
5398 5398
5399 hdspm->capture_buffer = NULL; 5399 hdspm->capture_buffer = NULL;
5400 5400
5401 } 5401 }
5402 5402
5403 snd_pcm_lib_free_pages(substream); 5403 snd_pcm_lib_free_pages(substream);
5404 5404
5405 return 0; 5405 return 0;
5406 } 5406 }
5407 5407
5408 5408
5409 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream, 5409 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5410 struct snd_pcm_channel_info *info) 5410 struct snd_pcm_channel_info *info)
5411 { 5411 {
5412 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5412 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5413 5413
5414 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5414 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5415 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) { 5415 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
5416 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel); 5416 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel);
5417 return -EINVAL; 5417 return -EINVAL;
5418 } 5418 }
5419 5419
5420 if (hdspm->channel_map_out[info->channel] < 0) { 5420 if (hdspm->channel_map_out[info->channel] < 0) {
5421 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel); 5421 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel);
5422 return -EINVAL; 5422 return -EINVAL;
5423 } 5423 }
5424 5424
5425 info->offset = hdspm->channel_map_out[info->channel] * 5425 info->offset = hdspm->channel_map_out[info->channel] *
5426 HDSPM_CHANNEL_BUFFER_BYTES; 5426 HDSPM_CHANNEL_BUFFER_BYTES;
5427 } else { 5427 } else {
5428 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) { 5428 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
5429 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel); 5429 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel);
5430 return -EINVAL; 5430 return -EINVAL;
5431 } 5431 }
5432 5432
5433 if (hdspm->channel_map_in[info->channel] < 0) { 5433 if (hdspm->channel_map_in[info->channel] < 0) {
5434 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel); 5434 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel);
5435 return -EINVAL; 5435 return -EINVAL;
5436 } 5436 }
5437 5437
5438 info->offset = hdspm->channel_map_in[info->channel] * 5438 info->offset = hdspm->channel_map_in[info->channel] *
5439 HDSPM_CHANNEL_BUFFER_BYTES; 5439 HDSPM_CHANNEL_BUFFER_BYTES;
5440 } 5440 }
5441 5441
5442 info->first = 0; 5442 info->first = 0;
5443 info->step = 32; 5443 info->step = 32;
5444 return 0; 5444 return 0;
5445 } 5445 }
5446 5446
5447 5447
5448 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream, 5448 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5449 unsigned int cmd, void *arg) 5449 unsigned int cmd, void *arg)
5450 { 5450 {
5451 switch (cmd) { 5451 switch (cmd) {
5452 case SNDRV_PCM_IOCTL1_RESET: 5452 case SNDRV_PCM_IOCTL1_RESET:
5453 return snd_hdspm_reset(substream); 5453 return snd_hdspm_reset(substream);
5454 5454
5455 case SNDRV_PCM_IOCTL1_CHANNEL_INFO: 5455 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5456 { 5456 {
5457 struct snd_pcm_channel_info *info = arg; 5457 struct snd_pcm_channel_info *info = arg;
5458 return snd_hdspm_channel_info(substream, info); 5458 return snd_hdspm_channel_info(substream, info);
5459 } 5459 }
5460 default: 5460 default:
5461 break; 5461 break;
5462 } 5462 }
5463 5463
5464 return snd_pcm_lib_ioctl(substream, cmd, arg); 5464 return snd_pcm_lib_ioctl(substream, cmd, arg);
5465 } 5465 }
5466 5466
5467 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd) 5467 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5468 { 5468 {
5469 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5469 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5470 struct snd_pcm_substream *other; 5470 struct snd_pcm_substream *other;
5471 int running; 5471 int running;
5472 5472
5473 spin_lock(&hdspm->lock); 5473 spin_lock(&hdspm->lock);
5474 running = hdspm->running; 5474 running = hdspm->running;
5475 switch (cmd) { 5475 switch (cmd) {
5476 case SNDRV_PCM_TRIGGER_START: 5476 case SNDRV_PCM_TRIGGER_START:
5477 running |= 1 << substream->stream; 5477 running |= 1 << substream->stream;
5478 break; 5478 break;
5479 case SNDRV_PCM_TRIGGER_STOP: 5479 case SNDRV_PCM_TRIGGER_STOP:
5480 running &= ~(1 << substream->stream); 5480 running &= ~(1 << substream->stream);
5481 break; 5481 break;
5482 default: 5482 default:
5483 snd_BUG(); 5483 snd_BUG();
5484 spin_unlock(&hdspm->lock); 5484 spin_unlock(&hdspm->lock);
5485 return -EINVAL; 5485 return -EINVAL;
5486 } 5486 }
5487 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5487 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5488 other = hdspm->capture_substream; 5488 other = hdspm->capture_substream;
5489 else 5489 else
5490 other = hdspm->playback_substream; 5490 other = hdspm->playback_substream;
5491 5491
5492 if (other) { 5492 if (other) {
5493 struct snd_pcm_substream *s; 5493 struct snd_pcm_substream *s;
5494 snd_pcm_group_for_each_entry(s, substream) { 5494 snd_pcm_group_for_each_entry(s, substream) {
5495 if (s == other) { 5495 if (s == other) {
5496 snd_pcm_trigger_done(s, substream); 5496 snd_pcm_trigger_done(s, substream);
5497 if (cmd == SNDRV_PCM_TRIGGER_START) 5497 if (cmd == SNDRV_PCM_TRIGGER_START)
5498 running |= 1 << s->stream; 5498 running |= 1 << s->stream;
5499 else 5499 else
5500 running &= ~(1 << s->stream); 5500 running &= ~(1 << s->stream);
5501 goto _ok; 5501 goto _ok;
5502 } 5502 }
5503 } 5503 }
5504 if (cmd == SNDRV_PCM_TRIGGER_START) { 5504 if (cmd == SNDRV_PCM_TRIGGER_START) {
5505 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) 5505 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5506 && substream->stream == 5506 && substream->stream ==
5507 SNDRV_PCM_STREAM_CAPTURE) 5507 SNDRV_PCM_STREAM_CAPTURE)
5508 hdspm_silence_playback(hdspm); 5508 hdspm_silence_playback(hdspm);
5509 } else { 5509 } else {
5510 if (running && 5510 if (running &&
5511 substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5511 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5512 hdspm_silence_playback(hdspm); 5512 hdspm_silence_playback(hdspm);
5513 } 5513 }
5514 } else { 5514 } else {
5515 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 5515 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5516 hdspm_silence_playback(hdspm); 5516 hdspm_silence_playback(hdspm);
5517 } 5517 }
5518 _ok: 5518 _ok:
5519 snd_pcm_trigger_done(substream, substream); 5519 snd_pcm_trigger_done(substream, substream);
5520 if (!hdspm->running && running) 5520 if (!hdspm->running && running)
5521 hdspm_start_audio(hdspm); 5521 hdspm_start_audio(hdspm);
5522 else if (hdspm->running && !running) 5522 else if (hdspm->running && !running)
5523 hdspm_stop_audio(hdspm); 5523 hdspm_stop_audio(hdspm);
5524 hdspm->running = running; 5524 hdspm->running = running;
5525 spin_unlock(&hdspm->lock); 5525 spin_unlock(&hdspm->lock);
5526 5526
5527 return 0; 5527 return 0;
5528 } 5528 }
5529 5529
5530 static int snd_hdspm_prepare(struct snd_pcm_substream *substream) 5530 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5531 { 5531 {
5532 return 0; 5532 return 0;
5533 } 5533 }
5534 5534
5535 static unsigned int period_sizes_old[] = { 5535 static unsigned int period_sizes_old[] = {
5536 64, 128, 256, 512, 1024, 2048, 4096 5536 64, 128, 256, 512, 1024, 2048, 4096
5537 }; 5537 };
5538 5538
5539 static unsigned int period_sizes_new[] = { 5539 static unsigned int period_sizes_new[] = {
5540 32, 64, 128, 256, 512, 1024, 2048, 4096 5540 32, 64, 128, 256, 512, 1024, 2048, 4096
5541 }; 5541 };
5542 5542
5543 /* RayDAT and AIO always have a buffer of 16384 samples per channel */ 5543 /* RayDAT and AIO always have a buffer of 16384 samples per channel */
5544 static unsigned int raydat_aio_buffer_sizes[] = { 5544 static unsigned int raydat_aio_buffer_sizes[] = {
5545 16384 5545 16384
5546 }; 5546 };
5547 5547
5548 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = { 5548 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5549 .info = (SNDRV_PCM_INFO_MMAP | 5549 .info = (SNDRV_PCM_INFO_MMAP |
5550 SNDRV_PCM_INFO_MMAP_VALID | 5550 SNDRV_PCM_INFO_MMAP_VALID |
5551 SNDRV_PCM_INFO_NONINTERLEAVED | 5551 SNDRV_PCM_INFO_NONINTERLEAVED |
5552 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE), 5552 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5553 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5553 .formats = SNDRV_PCM_FMTBIT_S32_LE,
5554 .rates = (SNDRV_PCM_RATE_32000 | 5554 .rates = (SNDRV_PCM_RATE_32000 |
5555 SNDRV_PCM_RATE_44100 | 5555 SNDRV_PCM_RATE_44100 |
5556 SNDRV_PCM_RATE_48000 | 5556 SNDRV_PCM_RATE_48000 |
5557 SNDRV_PCM_RATE_64000 | 5557 SNDRV_PCM_RATE_64000 |
5558 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5558 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5559 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ), 5559 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5560 .rate_min = 32000, 5560 .rate_min = 32000,
5561 .rate_max = 192000, 5561 .rate_max = 192000,
5562 .channels_min = 1, 5562 .channels_min = 1,
5563 .channels_max = HDSPM_MAX_CHANNELS, 5563 .channels_max = HDSPM_MAX_CHANNELS,
5564 .buffer_bytes_max = 5564 .buffer_bytes_max =
5565 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5565 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5566 .period_bytes_min = (64 * 4), 5566 .period_bytes_min = (64 * 4),
5567 .period_bytes_max = (4096 * 4) * HDSPM_MAX_CHANNELS, 5567 .period_bytes_max = (4096 * 4) * HDSPM_MAX_CHANNELS,
5568 .periods_min = 2, 5568 .periods_min = 2,
5569 .periods_max = 512, 5569 .periods_max = 512,
5570 .fifo_size = 0 5570 .fifo_size = 0
5571 }; 5571 };
5572 5572
5573 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = { 5573 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5574 .info = (SNDRV_PCM_INFO_MMAP | 5574 .info = (SNDRV_PCM_INFO_MMAP |
5575 SNDRV_PCM_INFO_MMAP_VALID | 5575 SNDRV_PCM_INFO_MMAP_VALID |
5576 SNDRV_PCM_INFO_NONINTERLEAVED | 5576 SNDRV_PCM_INFO_NONINTERLEAVED |
5577 SNDRV_PCM_INFO_SYNC_START), 5577 SNDRV_PCM_INFO_SYNC_START),
5578 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5578 .formats = SNDRV_PCM_FMTBIT_S32_LE,
5579 .rates = (SNDRV_PCM_RATE_32000 | 5579 .rates = (SNDRV_PCM_RATE_32000 |
5580 SNDRV_PCM_RATE_44100 | 5580 SNDRV_PCM_RATE_44100 |
5581 SNDRV_PCM_RATE_48000 | 5581 SNDRV_PCM_RATE_48000 |
5582 SNDRV_PCM_RATE_64000 | 5582 SNDRV_PCM_RATE_64000 |
5583 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5583 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5584 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000), 5584 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5585 .rate_min = 32000, 5585 .rate_min = 32000,
5586 .rate_max = 192000, 5586 .rate_max = 192000,
5587 .channels_min = 1, 5587 .channels_min = 1,
5588 .channels_max = HDSPM_MAX_CHANNELS, 5588 .channels_max = HDSPM_MAX_CHANNELS,
5589 .buffer_bytes_max = 5589 .buffer_bytes_max =
5590 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5590 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5591 .period_bytes_min = (64 * 4), 5591 .period_bytes_min = (64 * 4),
5592 .period_bytes_max = (4096 * 4) * HDSPM_MAX_CHANNELS, 5592 .period_bytes_max = (4096 * 4) * HDSPM_MAX_CHANNELS,
5593 .periods_min = 2, 5593 .periods_min = 2,
5594 .periods_max = 512, 5594 .periods_max = 512,
5595 .fifo_size = 0 5595 .fifo_size = 0
5596 }; 5596 };
5597 5597
5598 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes_old = { 5598 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes_old = {
5599 .count = ARRAY_SIZE(period_sizes_old), 5599 .count = ARRAY_SIZE(period_sizes_old),
5600 .list = period_sizes_old, 5600 .list = period_sizes_old,
5601 .mask = 0 5601 .mask = 0
5602 }; 5602 };
5603 5603
5604 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes_new = { 5604 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes_new = {
5605 .count = ARRAY_SIZE(period_sizes_new), 5605 .count = ARRAY_SIZE(period_sizes_new),
5606 .list = period_sizes_new, 5606 .list = period_sizes_new,
5607 .mask = 0 5607 .mask = 0
5608 }; 5608 };
5609 5609
5610 static struct snd_pcm_hw_constraint_list hw_constraints_raydat_io_buffer = { 5610 static struct snd_pcm_hw_constraint_list hw_constraints_raydat_io_buffer = {
5611 .count = ARRAY_SIZE(raydat_aio_buffer_sizes), 5611 .count = ARRAY_SIZE(raydat_aio_buffer_sizes),
5612 .list = raydat_aio_buffer_sizes, 5612 .list = raydat_aio_buffer_sizes,
5613 .mask = 0 5613 .mask = 0
5614 }; 5614 };
5615 5615
5616 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params, 5616 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5617 struct snd_pcm_hw_rule *rule) 5617 struct snd_pcm_hw_rule *rule)
5618 { 5618 {
5619 struct hdspm *hdspm = rule->private; 5619 struct hdspm *hdspm = rule->private;
5620 struct snd_interval *c = 5620 struct snd_interval *c =
5621 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5621 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5622 struct snd_interval *r = 5622 struct snd_interval *r =
5623 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5623 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5624 5624
5625 if (r->min > 96000 && r->max <= 192000) { 5625 if (r->min > 96000 && r->max <= 192000) {
5626 struct snd_interval t = { 5626 struct snd_interval t = {
5627 .min = hdspm->qs_in_channels, 5627 .min = hdspm->qs_in_channels,
5628 .max = hdspm->qs_in_channels, 5628 .max = hdspm->qs_in_channels,
5629 .integer = 1, 5629 .integer = 1,
5630 }; 5630 };
5631 return snd_interval_refine(c, &t); 5631 return snd_interval_refine(c, &t);
5632 } else if (r->min > 48000 && r->max <= 96000) { 5632 } else if (r->min > 48000 && r->max <= 96000) {
5633 struct snd_interval t = { 5633 struct snd_interval t = {
5634 .min = hdspm->ds_in_channels, 5634 .min = hdspm->ds_in_channels,
5635 .max = hdspm->ds_in_channels, 5635 .max = hdspm->ds_in_channels,
5636 .integer = 1, 5636 .integer = 1,
5637 }; 5637 };
5638 return snd_interval_refine(c, &t); 5638 return snd_interval_refine(c, &t);
5639 } else if (r->max < 64000) { 5639 } else if (r->max < 64000) {
5640 struct snd_interval t = { 5640 struct snd_interval t = {
5641 .min = hdspm->ss_in_channels, 5641 .min = hdspm->ss_in_channels,
5642 .max = hdspm->ss_in_channels, 5642 .max = hdspm->ss_in_channels,
5643 .integer = 1, 5643 .integer = 1,
5644 }; 5644 };
5645 return snd_interval_refine(c, &t); 5645 return snd_interval_refine(c, &t);
5646 } 5646 }
5647 5647
5648 return 0; 5648 return 0;
5649 } 5649 }
5650 5650
5651 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params, 5651 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5652 struct snd_pcm_hw_rule * rule) 5652 struct snd_pcm_hw_rule * rule)
5653 { 5653 {
5654 struct hdspm *hdspm = rule->private; 5654 struct hdspm *hdspm = rule->private;
5655 struct snd_interval *c = 5655 struct snd_interval *c =
5656 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5656 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5657 struct snd_interval *r = 5657 struct snd_interval *r =
5658 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5658 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5659 5659
5660 if (r->min > 96000 && r->max <= 192000) { 5660 if (r->min > 96000 && r->max <= 192000) {
5661 struct snd_interval t = { 5661 struct snd_interval t = {
5662 .min = hdspm->qs_out_channels, 5662 .min = hdspm->qs_out_channels,
5663 .max = hdspm->qs_out_channels, 5663 .max = hdspm->qs_out_channels,
5664 .integer = 1, 5664 .integer = 1,
5665 }; 5665 };
5666 return snd_interval_refine(c, &t); 5666 return snd_interval_refine(c, &t);
5667 } else if (r->min > 48000 && r->max <= 96000) { 5667 } else if (r->min > 48000 && r->max <= 96000) {
5668 struct snd_interval t = { 5668 struct snd_interval t = {
5669 .min = hdspm->ds_out_channels, 5669 .min = hdspm->ds_out_channels,
5670 .max = hdspm->ds_out_channels, 5670 .max = hdspm->ds_out_channels,
5671 .integer = 1, 5671 .integer = 1,
5672 }; 5672 };
5673 return snd_interval_refine(c, &t); 5673 return snd_interval_refine(c, &t);
5674 } else if (r->max < 64000) { 5674 } else if (r->max < 64000) {
5675 struct snd_interval t = { 5675 struct snd_interval t = {
5676 .min = hdspm->ss_out_channels, 5676 .min = hdspm->ss_out_channels,
5677 .max = hdspm->ss_out_channels, 5677 .max = hdspm->ss_out_channels,
5678 .integer = 1, 5678 .integer = 1,
5679 }; 5679 };
5680 return snd_interval_refine(c, &t); 5680 return snd_interval_refine(c, &t);
5681 } else { 5681 } else {
5682 } 5682 }
5683 return 0; 5683 return 0;
5684 } 5684 }
5685 5685
5686 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params, 5686 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5687 struct snd_pcm_hw_rule * rule) 5687 struct snd_pcm_hw_rule * rule)
5688 { 5688 {
5689 struct hdspm *hdspm = rule->private; 5689 struct hdspm *hdspm = rule->private;
5690 struct snd_interval *c = 5690 struct snd_interval *c =
5691 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5691 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5692 struct snd_interval *r = 5692 struct snd_interval *r =
5693 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5693 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5694 5694
5695 if (c->min >= hdspm->ss_in_channels) { 5695 if (c->min >= hdspm->ss_in_channels) {
5696 struct snd_interval t = { 5696 struct snd_interval t = {
5697 .min = 32000, 5697 .min = 32000,
5698 .max = 48000, 5698 .max = 48000,
5699 .integer = 1, 5699 .integer = 1,
5700 }; 5700 };
5701 return snd_interval_refine(r, &t); 5701 return snd_interval_refine(r, &t);
5702 } else if (c->max <= hdspm->qs_in_channels) { 5702 } else if (c->max <= hdspm->qs_in_channels) {
5703 struct snd_interval t = { 5703 struct snd_interval t = {
5704 .min = 128000, 5704 .min = 128000,
5705 .max = 192000, 5705 .max = 192000,
5706 .integer = 1, 5706 .integer = 1,
5707 }; 5707 };
5708 return snd_interval_refine(r, &t); 5708 return snd_interval_refine(r, &t);
5709 } else if (c->max <= hdspm->ds_in_channels) { 5709 } else if (c->max <= hdspm->ds_in_channels) {
5710 struct snd_interval t = { 5710 struct snd_interval t = {
5711 .min = 64000, 5711 .min = 64000,
5712 .max = 96000, 5712 .max = 96000,
5713 .integer = 1, 5713 .integer = 1,
5714 }; 5714 };
5715 return snd_interval_refine(r, &t); 5715 return snd_interval_refine(r, &t);
5716 } 5716 }
5717 5717
5718 return 0; 5718 return 0;
5719 } 5719 }
5720 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params, 5720 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5721 struct snd_pcm_hw_rule *rule) 5721 struct snd_pcm_hw_rule *rule)
5722 { 5722 {
5723 struct hdspm *hdspm = rule->private; 5723 struct hdspm *hdspm = rule->private;
5724 struct snd_interval *c = 5724 struct snd_interval *c =
5725 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5725 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5726 struct snd_interval *r = 5726 struct snd_interval *r =
5727 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5727 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5728 5728
5729 if (c->min >= hdspm->ss_out_channels) { 5729 if (c->min >= hdspm->ss_out_channels) {
5730 struct snd_interval t = { 5730 struct snd_interval t = {
5731 .min = 32000, 5731 .min = 32000,
5732 .max = 48000, 5732 .max = 48000,
5733 .integer = 1, 5733 .integer = 1,
5734 }; 5734 };
5735 return snd_interval_refine(r, &t); 5735 return snd_interval_refine(r, &t);
5736 } else if (c->max <= hdspm->qs_out_channels) { 5736 } else if (c->max <= hdspm->qs_out_channels) {
5737 struct snd_interval t = { 5737 struct snd_interval t = {
5738 .min = 128000, 5738 .min = 128000,
5739 .max = 192000, 5739 .max = 192000,
5740 .integer = 1, 5740 .integer = 1,
5741 }; 5741 };
5742 return snd_interval_refine(r, &t); 5742 return snd_interval_refine(r, &t);
5743 } else if (c->max <= hdspm->ds_out_channels) { 5743 } else if (c->max <= hdspm->ds_out_channels) {
5744 struct snd_interval t = { 5744 struct snd_interval t = {
5745 .min = 64000, 5745 .min = 64000,
5746 .max = 96000, 5746 .max = 96000,
5747 .integer = 1, 5747 .integer = 1,
5748 }; 5748 };
5749 return snd_interval_refine(r, &t); 5749 return snd_interval_refine(r, &t);
5750 } 5750 }
5751 5751
5752 return 0; 5752 return 0;
5753 } 5753 }
5754 5754
5755 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params, 5755 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
5756 struct snd_pcm_hw_rule *rule) 5756 struct snd_pcm_hw_rule *rule)
5757 { 5757 {
5758 unsigned int list[3]; 5758 unsigned int list[3];
5759 struct hdspm *hdspm = rule->private; 5759 struct hdspm *hdspm = rule->private;
5760 struct snd_interval *c = hw_param_interval(params, 5760 struct snd_interval *c = hw_param_interval(params,
5761 SNDRV_PCM_HW_PARAM_CHANNELS); 5761 SNDRV_PCM_HW_PARAM_CHANNELS);
5762 5762
5763 list[0] = hdspm->qs_in_channels; 5763 list[0] = hdspm->qs_in_channels;
5764 list[1] = hdspm->ds_in_channels; 5764 list[1] = hdspm->ds_in_channels;
5765 list[2] = hdspm->ss_in_channels; 5765 list[2] = hdspm->ss_in_channels;
5766 return snd_interval_list(c, 3, list, 0); 5766 return snd_interval_list(c, 3, list, 0);
5767 } 5767 }
5768 5768
5769 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params, 5769 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
5770 struct snd_pcm_hw_rule *rule) 5770 struct snd_pcm_hw_rule *rule)
5771 { 5771 {
5772 unsigned int list[3]; 5772 unsigned int list[3];
5773 struct hdspm *hdspm = rule->private; 5773 struct hdspm *hdspm = rule->private;
5774 struct snd_interval *c = hw_param_interval(params, 5774 struct snd_interval *c = hw_param_interval(params,
5775 SNDRV_PCM_HW_PARAM_CHANNELS); 5775 SNDRV_PCM_HW_PARAM_CHANNELS);
5776 5776
5777 list[0] = hdspm->qs_out_channels; 5777 list[0] = hdspm->qs_out_channels;
5778 list[1] = hdspm->ds_out_channels; 5778 list[1] = hdspm->ds_out_channels;
5779 list[2] = hdspm->ss_out_channels; 5779 list[2] = hdspm->ss_out_channels;
5780 return snd_interval_list(c, 3, list, 0); 5780 return snd_interval_list(c, 3, list, 0);
5781 } 5781 }
5782 5782
5783 5783
5784 static unsigned int hdspm_aes32_sample_rates[] = { 5784 static unsigned int hdspm_aes32_sample_rates[] = {
5785 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 5785 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
5786 }; 5786 };
5787 5787
5788 static struct snd_pcm_hw_constraint_list 5788 static struct snd_pcm_hw_constraint_list
5789 hdspm_hw_constraints_aes32_sample_rates = { 5789 hdspm_hw_constraints_aes32_sample_rates = {
5790 .count = ARRAY_SIZE(hdspm_aes32_sample_rates), 5790 .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
5791 .list = hdspm_aes32_sample_rates, 5791 .list = hdspm_aes32_sample_rates,
5792 .mask = 0 5792 .mask = 0
5793 }; 5793 };
5794 5794
5795 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream) 5795 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
5796 { 5796 {
5797 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5797 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5798 struct snd_pcm_runtime *runtime = substream->runtime; 5798 struct snd_pcm_runtime *runtime = substream->runtime;
5799 5799
5800 spin_lock_irq(&hdspm->lock); 5800 spin_lock_irq(&hdspm->lock);
5801 5801
5802 snd_pcm_set_sync(substream); 5802 snd_pcm_set_sync(substream);
5803 5803
5804 5804
5805 runtime->hw = snd_hdspm_playback_subinfo; 5805 runtime->hw = snd_hdspm_playback_subinfo;
5806 5806
5807 if (hdspm->capture_substream == NULL) 5807 if (hdspm->capture_substream == NULL)
5808 hdspm_stop_audio(hdspm); 5808 hdspm_stop_audio(hdspm);
5809 5809
5810 hdspm->playback_pid = current->pid; 5810 hdspm->playback_pid = current->pid;
5811 hdspm->playback_substream = substream; 5811 hdspm->playback_substream = substream;
5812 5812
5813 spin_unlock_irq(&hdspm->lock); 5813 spin_unlock_irq(&hdspm->lock);
5814 5814
5815 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 5815 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
5816 5816
5817 switch (hdspm->io_type) { 5817 switch (hdspm->io_type) {
5818 case AIO: 5818 case AIO:
5819 case RayDAT: 5819 case RayDAT:
5820 snd_pcm_hw_constraint_list(runtime, 0, 5820 snd_pcm_hw_constraint_list(runtime, 0,
5821 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5821 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5822 &hw_constraints_period_sizes_new); 5822 &hw_constraints_period_sizes_new);
5823 snd_pcm_hw_constraint_list(runtime, 0, 5823 snd_pcm_hw_constraint_list(runtime, 0,
5824 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 5824 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
5825 &hw_constraints_raydat_io_buffer); 5825 &hw_constraints_raydat_io_buffer);
5826 5826
5827 break; 5827 break;
5828 5828
5829 default: 5829 default:
5830 snd_pcm_hw_constraint_list(runtime, 0, 5830 snd_pcm_hw_constraint_list(runtime, 0,
5831 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5831 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5832 &hw_constraints_period_sizes_old); 5832 &hw_constraints_period_sizes_old);
5833 } 5833 }
5834 5834
5835 if (AES32 == hdspm->io_type) { 5835 if (AES32 == hdspm->io_type) {
5836 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5836 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5837 &hdspm_hw_constraints_aes32_sample_rates); 5837 &hdspm_hw_constraints_aes32_sample_rates);
5838 } else { 5838 } else {
5839 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5839 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5840 snd_hdspm_hw_rule_rate_out_channels, hdspm, 5840 snd_hdspm_hw_rule_rate_out_channels, hdspm,
5841 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5841 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5842 } 5842 }
5843 5843
5844 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5844 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5845 snd_hdspm_hw_rule_out_channels, hdspm, 5845 snd_hdspm_hw_rule_out_channels, hdspm,
5846 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5846 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5847 5847
5848 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5848 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5849 snd_hdspm_hw_rule_out_channels_rate, hdspm, 5849 snd_hdspm_hw_rule_out_channels_rate, hdspm,
5850 SNDRV_PCM_HW_PARAM_RATE, -1); 5850 SNDRV_PCM_HW_PARAM_RATE, -1);
5851 5851
5852 return 0; 5852 return 0;
5853 } 5853 }
5854 5854
5855 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream) 5855 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream)
5856 { 5856 {
5857 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5857 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5858 5858
5859 spin_lock_irq(&hdspm->lock); 5859 spin_lock_irq(&hdspm->lock);
5860 5860
5861 hdspm->playback_pid = -1; 5861 hdspm->playback_pid = -1;
5862 hdspm->playback_substream = NULL; 5862 hdspm->playback_substream = NULL;
5863 5863
5864 spin_unlock_irq(&hdspm->lock); 5864 spin_unlock_irq(&hdspm->lock);
5865 5865
5866 return 0; 5866 return 0;
5867 } 5867 }
5868 5868
5869 5869
5870 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream) 5870 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream)
5871 { 5871 {
5872 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5872 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5873 struct snd_pcm_runtime *runtime = substream->runtime; 5873 struct snd_pcm_runtime *runtime = substream->runtime;
5874 5874
5875 spin_lock_irq(&hdspm->lock); 5875 spin_lock_irq(&hdspm->lock);
5876 snd_pcm_set_sync(substream); 5876 snd_pcm_set_sync(substream);
5877 runtime->hw = snd_hdspm_capture_subinfo; 5877 runtime->hw = snd_hdspm_capture_subinfo;
5878 5878
5879 if (hdspm->playback_substream == NULL) 5879 if (hdspm->playback_substream == NULL)
5880 hdspm_stop_audio(hdspm); 5880 hdspm_stop_audio(hdspm);
5881 5881
5882 hdspm->capture_pid = current->pid; 5882 hdspm->capture_pid = current->pid;
5883 hdspm->capture_substream = substream; 5883 hdspm->capture_substream = substream;
5884 5884
5885 spin_unlock_irq(&hdspm->lock); 5885 spin_unlock_irq(&hdspm->lock);
5886 5886
5887 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 5887 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
5888 switch (hdspm->io_type) { 5888 switch (hdspm->io_type) {
5889 case AIO: 5889 case AIO:
5890 case RayDAT: 5890 case RayDAT:
5891 snd_pcm_hw_constraint_list(runtime, 0, 5891 snd_pcm_hw_constraint_list(runtime, 0,
5892 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5892 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5893 &hw_constraints_period_sizes_new); 5893 &hw_constraints_period_sizes_new);
5894 snd_pcm_hw_constraint_list(runtime, 0, 5894 snd_pcm_hw_constraint_list(runtime, 0,
5895 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 5895 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
5896 &hw_constraints_raydat_io_buffer); 5896 &hw_constraints_raydat_io_buffer);
5897 break; 5897 break;
5898 5898
5899 default: 5899 default:
5900 snd_pcm_hw_constraint_list(runtime, 0, 5900 snd_pcm_hw_constraint_list(runtime, 0,
5901 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5901 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5902 &hw_constraints_period_sizes_old); 5902 &hw_constraints_period_sizes_old);
5903 } 5903 }
5904 5904
5905 if (AES32 == hdspm->io_type) { 5905 if (AES32 == hdspm->io_type) {
5906 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5906 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5907 &hdspm_hw_constraints_aes32_sample_rates); 5907 &hdspm_hw_constraints_aes32_sample_rates);
5908 } else { 5908 } else {
5909 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5909 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5910 snd_hdspm_hw_rule_rate_in_channels, hdspm, 5910 snd_hdspm_hw_rule_rate_in_channels, hdspm,
5911 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5911 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5912 } 5912 }
5913 5913
5914 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5914 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5915 snd_hdspm_hw_rule_in_channels, hdspm, 5915 snd_hdspm_hw_rule_in_channels, hdspm,
5916 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5916 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5917 5917
5918 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5918 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5919 snd_hdspm_hw_rule_in_channels_rate, hdspm, 5919 snd_hdspm_hw_rule_in_channels_rate, hdspm,
5920 SNDRV_PCM_HW_PARAM_RATE, -1); 5920 SNDRV_PCM_HW_PARAM_RATE, -1);
5921 5921
5922 return 0; 5922 return 0;
5923 } 5923 }
5924 5924
5925 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream) 5925 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream)
5926 { 5926 {
5927 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5927 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5928 5928
5929 spin_lock_irq(&hdspm->lock); 5929 spin_lock_irq(&hdspm->lock);
5930 5930
5931 hdspm->capture_pid = -1; 5931 hdspm->capture_pid = -1;
5932 hdspm->capture_substream = NULL; 5932 hdspm->capture_substream = NULL;
5933 5933
5934 spin_unlock_irq(&hdspm->lock); 5934 spin_unlock_irq(&hdspm->lock);
5935 return 0; 5935 return 0;
5936 } 5936 }
5937 5937
5938 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file) 5938 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
5939 { 5939 {
5940 /* we have nothing to initialize but the call is required */ 5940 /* we have nothing to initialize but the call is required */
5941 return 0; 5941 return 0;
5942 } 5942 }
5943 5943
5944 static inline int copy_u32_le(void __user *dest, void __iomem *src) 5944 static inline int copy_u32_le(void __user *dest, void __iomem *src)
5945 { 5945 {
5946 u32 val = readl(src); 5946 u32 val = readl(src);
5947 return copy_to_user(dest, &val, 4); 5947 return copy_to_user(dest, &val, 4);
5948 } 5948 }
5949 5949
5950 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, 5950 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
5951 unsigned int cmd, unsigned long __user arg) 5951 unsigned int cmd, unsigned long __user arg)
5952 { 5952 {
5953 void __user *argp = (void __user *)arg; 5953 void __user *argp = (void __user *)arg;
5954 struct hdspm *hdspm = hw->private_data; 5954 struct hdspm *hdspm = hw->private_data;
5955 struct hdspm_mixer_ioctl mixer; 5955 struct hdspm_mixer_ioctl mixer;
5956 struct hdspm_config info; 5956 struct hdspm_config info;
5957 struct hdspm_status status; 5957 struct hdspm_status status;
5958 struct hdspm_version hdspm_version; 5958 struct hdspm_version hdspm_version;
5959 struct hdspm_peak_rms *levels; 5959 struct hdspm_peak_rms *levels;
5960 struct hdspm_ltc ltc; 5960 struct hdspm_ltc ltc;
5961 unsigned int statusregister; 5961 unsigned int statusregister;
5962 long unsigned int s; 5962 long unsigned int s;
5963 int i = 0; 5963 int i = 0;
5964 5964
5965 switch (cmd) { 5965 switch (cmd) {
5966 5966
5967 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS: 5967 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
5968 levels = &hdspm->peak_rms; 5968 levels = &hdspm->peak_rms;
5969 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 5969 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
5970 levels->input_peaks[i] = 5970 levels->input_peaks[i] =
5971 readl(hdspm->iobase + 5971 readl(hdspm->iobase +
5972 HDSPM_MADI_INPUT_PEAK + i*4); 5972 HDSPM_MADI_INPUT_PEAK + i*4);
5973 levels->playback_peaks[i] = 5973 levels->playback_peaks[i] =
5974 readl(hdspm->iobase + 5974 readl(hdspm->iobase +
5975 HDSPM_MADI_PLAYBACK_PEAK + i*4); 5975 HDSPM_MADI_PLAYBACK_PEAK + i*4);
5976 levels->output_peaks[i] = 5976 levels->output_peaks[i] =
5977 readl(hdspm->iobase + 5977 readl(hdspm->iobase +
5978 HDSPM_MADI_OUTPUT_PEAK + i*4); 5978 HDSPM_MADI_OUTPUT_PEAK + i*4);
5979 5979
5980 levels->input_rms[i] = 5980 levels->input_rms[i] =
5981 ((uint64_t) readl(hdspm->iobase + 5981 ((uint64_t) readl(hdspm->iobase +
5982 HDSPM_MADI_INPUT_RMS_H + i*4) << 32) | 5982 HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
5983 (uint64_t) readl(hdspm->iobase + 5983 (uint64_t) readl(hdspm->iobase +
5984 HDSPM_MADI_INPUT_RMS_L + i*4); 5984 HDSPM_MADI_INPUT_RMS_L + i*4);
5985 levels->playback_rms[i] = 5985 levels->playback_rms[i] =
5986 ((uint64_t)readl(hdspm->iobase + 5986 ((uint64_t)readl(hdspm->iobase +
5987 HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) | 5987 HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
5988 (uint64_t)readl(hdspm->iobase + 5988 (uint64_t)readl(hdspm->iobase +
5989 HDSPM_MADI_PLAYBACK_RMS_L + i*4); 5989 HDSPM_MADI_PLAYBACK_RMS_L + i*4);
5990 levels->output_rms[i] = 5990 levels->output_rms[i] =
5991 ((uint64_t)readl(hdspm->iobase + 5991 ((uint64_t)readl(hdspm->iobase +
5992 HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) | 5992 HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
5993 (uint64_t)readl(hdspm->iobase + 5993 (uint64_t)readl(hdspm->iobase +
5994 HDSPM_MADI_OUTPUT_RMS_L + i*4); 5994 HDSPM_MADI_OUTPUT_RMS_L + i*4);
5995 } 5995 }
5996 5996
5997 if (hdspm->system_sample_rate > 96000) { 5997 if (hdspm->system_sample_rate > 96000) {
5998 levels->speed = qs; 5998 levels->speed = qs;
5999 } else if (hdspm->system_sample_rate > 48000) { 5999 } else if (hdspm->system_sample_rate > 48000) {
6000 levels->speed = ds; 6000 levels->speed = ds;
6001 } else { 6001 } else {
6002 levels->speed = ss; 6002 levels->speed = ss;
6003 } 6003 }
6004 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 6004 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
6005 6005
6006 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms)); 6006 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms));
6007 if (0 != s) { 6007 if (0 != s) {
6008 /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu 6008 /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu
6009 [Levels]\n", sizeof(struct hdspm_peak_rms), s); 6009 [Levels]\n", sizeof(struct hdspm_peak_rms), s);
6010 */ 6010 */
6011 return -EFAULT; 6011 return -EFAULT;
6012 } 6012 }
6013 break; 6013 break;
6014 6014
6015 case SNDRV_HDSPM_IOCTL_GET_LTC: 6015 case SNDRV_HDSPM_IOCTL_GET_LTC:
6016 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 6016 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
6017 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 6017 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
6018 if (i & HDSPM_TCO1_LTC_Input_valid) { 6018 if (i & HDSPM_TCO1_LTC_Input_valid) {
6019 switch (i & (HDSPM_TCO1_LTC_Format_LSB | 6019 switch (i & (HDSPM_TCO1_LTC_Format_LSB |
6020 HDSPM_TCO1_LTC_Format_MSB)) { 6020 HDSPM_TCO1_LTC_Format_MSB)) {
6021 case 0: 6021 case 0:
6022 ltc.format = fps_24; 6022 ltc.format = fps_24;
6023 break; 6023 break;
6024 case HDSPM_TCO1_LTC_Format_LSB: 6024 case HDSPM_TCO1_LTC_Format_LSB:
6025 ltc.format = fps_25; 6025 ltc.format = fps_25;
6026 break; 6026 break;
6027 case HDSPM_TCO1_LTC_Format_MSB: 6027 case HDSPM_TCO1_LTC_Format_MSB:
6028 ltc.format = fps_2997; 6028 ltc.format = fps_2997;
6029 break; 6029 break;
6030 default: 6030 default:
6031 ltc.format = 30; 6031 ltc.format = 30;
6032 break; 6032 break;
6033 } 6033 }
6034 if (i & HDSPM_TCO1_set_drop_frame_flag) { 6034 if (i & HDSPM_TCO1_set_drop_frame_flag) {
6035 ltc.frame = drop_frame; 6035 ltc.frame = drop_frame;
6036 } else { 6036 } else {
6037 ltc.frame = full_frame; 6037 ltc.frame = full_frame;
6038 } 6038 }
6039 } else { 6039 } else {
6040 ltc.format = format_invalid; 6040 ltc.format = format_invalid;
6041 ltc.frame = frame_invalid; 6041 ltc.frame = frame_invalid;
6042 } 6042 }
6043 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) { 6043 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
6044 ltc.input_format = ntsc; 6044 ltc.input_format = ntsc;
6045 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) { 6045 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
6046 ltc.input_format = pal; 6046 ltc.input_format = pal;
6047 } else { 6047 } else {
6048 ltc.input_format = no_video; 6048 ltc.input_format = no_video;
6049 } 6049 }
6050 6050
6051 s = copy_to_user(argp, &ltc, sizeof(struct hdspm_ltc)); 6051 s = copy_to_user(argp, &ltc, sizeof(struct hdspm_ltc));
6052 if (0 != s) { 6052 if (0 != s) {
6053 /* 6053 /*
6054 snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */ 6054 snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6055 return -EFAULT; 6055 return -EFAULT;
6056 } 6056 }
6057 6057
6058 break; 6058 break;
6059 6059
6060 case SNDRV_HDSPM_IOCTL_GET_CONFIG: 6060 case SNDRV_HDSPM_IOCTL_GET_CONFIG:
6061 6061
6062 spin_lock_irq(&hdspm->lock); 6062 spin_lock_irq(&hdspm->lock);
6063 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm); 6063 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
6064 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm); 6064 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
6065 6065
6066 info.system_sample_rate = hdspm->system_sample_rate; 6066 info.system_sample_rate = hdspm->system_sample_rate;
6067 info.autosync_sample_rate = 6067 info.autosync_sample_rate =
6068 hdspm_external_sample_rate(hdspm); 6068 hdspm_external_sample_rate(hdspm);
6069 info.system_clock_mode = hdspm_system_clock_mode(hdspm); 6069 info.system_clock_mode = hdspm_system_clock_mode(hdspm);
6070 info.clock_source = hdspm_clock_source(hdspm); 6070 info.clock_source = hdspm_clock_source(hdspm);
6071 info.autosync_ref = hdspm_autosync_ref(hdspm); 6071 info.autosync_ref = hdspm_autosync_ref(hdspm);
6072 info.line_out = hdspm_line_out(hdspm); 6072 info.line_out = hdspm_line_out(hdspm);
6073 info.passthru = 0; 6073 info.passthru = 0;
6074 spin_unlock_irq(&hdspm->lock); 6074 spin_unlock_irq(&hdspm->lock);
6075 if (copy_to_user((void __user *) arg, &info, sizeof(info))) 6075 if (copy_to_user((void __user *) arg, &info, sizeof(info)))
6076 return -EFAULT; 6076 return -EFAULT;
6077 break; 6077 break;
6078 6078
6079 case SNDRV_HDSPM_IOCTL_GET_STATUS: 6079 case SNDRV_HDSPM_IOCTL_GET_STATUS:
6080 status.card_type = hdspm->io_type; 6080 status.card_type = hdspm->io_type;
6081 6081
6082 status.autosync_source = hdspm_autosync_ref(hdspm); 6082 status.autosync_source = hdspm_autosync_ref(hdspm);
6083 6083
6084 status.card_clock = 110069313433624ULL; 6084 status.card_clock = 110069313433624ULL;
6085 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 6085 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
6086 6086
6087 switch (hdspm->io_type) { 6087 switch (hdspm->io_type) {
6088 case MADI: 6088 case MADI:
6089 case MADIface: 6089 case MADIface:
6090 status.card_specific.madi.sync_wc = 6090 status.card_specific.madi.sync_wc =
6091 hdspm_wc_sync_check(hdspm); 6091 hdspm_wc_sync_check(hdspm);
6092 status.card_specific.madi.sync_madi = 6092 status.card_specific.madi.sync_madi =
6093 hdspm_madi_sync_check(hdspm); 6093 hdspm_madi_sync_check(hdspm);
6094 status.card_specific.madi.sync_tco = 6094 status.card_specific.madi.sync_tco =
6095 hdspm_tco_sync_check(hdspm); 6095 hdspm_tco_sync_check(hdspm);
6096 status.card_specific.madi.sync_in = 6096 status.card_specific.madi.sync_in =
6097 hdspm_sync_in_sync_check(hdspm); 6097 hdspm_sync_in_sync_check(hdspm);
6098 6098
6099 statusregister = 6099 statusregister =
6100 hdspm_read(hdspm, HDSPM_statusRegister); 6100 hdspm_read(hdspm, HDSPM_statusRegister);
6101 status.card_specific.madi.madi_input = 6101 status.card_specific.madi.madi_input =
6102 (statusregister & HDSPM_AB_int) ? 1 : 0; 6102 (statusregister & HDSPM_AB_int) ? 1 : 0;
6103 status.card_specific.madi.channel_format = 6103 status.card_specific.madi.channel_format =
6104 (statusregister & HDSPM_TX_64ch) ? 1 : 0; 6104 (statusregister & HDSPM_TX_64ch) ? 1 : 0;
6105 /* TODO: Mac driver sets it when f_s>48kHz */ 6105 /* TODO: Mac driver sets it when f_s>48kHz */
6106 status.card_specific.madi.frame_format = 0; 6106 status.card_specific.madi.frame_format = 0;
6107 6107
6108 default: 6108 default:
6109 break; 6109 break;
6110 } 6110 }
6111 6111
6112 if (copy_to_user((void __user *) arg, &status, sizeof(status))) 6112 if (copy_to_user((void __user *) arg, &status, sizeof(status)))
6113 return -EFAULT; 6113 return -EFAULT;
6114 6114
6115 6115
6116 break; 6116 break;
6117 6117
6118 case SNDRV_HDSPM_IOCTL_GET_VERSION: 6118 case SNDRV_HDSPM_IOCTL_GET_VERSION:
6119 hdspm_version.card_type = hdspm->io_type; 6119 hdspm_version.card_type = hdspm->io_type;
6120 strncpy(hdspm_version.cardname, hdspm->card_name, 6120 strncpy(hdspm_version.cardname, hdspm->card_name,
6121 sizeof(hdspm_version.cardname)); 6121 sizeof(hdspm_version.cardname));
6122 hdspm_version.serial = (hdspm_read(hdspm, 6122 hdspm_version.serial = (hdspm_read(hdspm,
6123 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF; 6123 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
6124 hdspm_version.firmware_rev = hdspm->firmware_rev; 6124 hdspm_version.firmware_rev = hdspm->firmware_rev;
6125 hdspm_version.addons = 0; 6125 hdspm_version.addons = 0;
6126 if (hdspm->tco) 6126 if (hdspm->tco)
6127 hdspm_version.addons |= HDSPM_ADDON_TCO; 6127 hdspm_version.addons |= HDSPM_ADDON_TCO;
6128 6128
6129 if (copy_to_user((void __user *) arg, &hdspm_version, 6129 if (copy_to_user((void __user *) arg, &hdspm_version,
6130 sizeof(hdspm_version))) 6130 sizeof(hdspm_version)))
6131 return -EFAULT; 6131 return -EFAULT;
6132 break; 6132 break;
6133 6133
6134 case SNDRV_HDSPM_IOCTL_GET_MIXER: 6134 case SNDRV_HDSPM_IOCTL_GET_MIXER:
6135 if (copy_from_user(&mixer, (void __user *)arg, sizeof(mixer))) 6135 if (copy_from_user(&mixer, (void __user *)arg, sizeof(mixer)))
6136 return -EFAULT; 6136 return -EFAULT;
6137 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer, 6137 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
6138 sizeof(struct hdspm_mixer))) 6138 sizeof(struct hdspm_mixer)))
6139 return -EFAULT; 6139 return -EFAULT;
6140 break; 6140 break;
6141 6141
6142 default: 6142 default:
6143 return -EINVAL; 6143 return -EINVAL;
6144 } 6144 }
6145 return 0; 6145 return 0;
6146 } 6146 }
6147 6147
6148 static struct snd_pcm_ops snd_hdspm_playback_ops = { 6148 static struct snd_pcm_ops snd_hdspm_playback_ops = {
6149 .open = snd_hdspm_playback_open, 6149 .open = snd_hdspm_playback_open,
6150 .close = snd_hdspm_playback_release, 6150 .close = snd_hdspm_playback_release,
6151 .ioctl = snd_hdspm_ioctl, 6151 .ioctl = snd_hdspm_ioctl,
6152 .hw_params = snd_hdspm_hw_params, 6152 .hw_params = snd_hdspm_hw_params,
6153 .hw_free = snd_hdspm_hw_free, 6153 .hw_free = snd_hdspm_hw_free,
6154 .prepare = snd_hdspm_prepare, 6154 .prepare = snd_hdspm_prepare,
6155 .trigger = snd_hdspm_trigger, 6155 .trigger = snd_hdspm_trigger,
6156 .pointer = snd_hdspm_hw_pointer, 6156 .pointer = snd_hdspm_hw_pointer,
6157 .page = snd_pcm_sgbuf_ops_page, 6157 .page = snd_pcm_sgbuf_ops_page,
6158 }; 6158 };
6159 6159
6160 static struct snd_pcm_ops snd_hdspm_capture_ops = { 6160 static struct snd_pcm_ops snd_hdspm_capture_ops = {
6161 .open = snd_hdspm_capture_open, 6161 .open = snd_hdspm_capture_open,
6162 .close = snd_hdspm_capture_release, 6162 .close = snd_hdspm_capture_release,
6163 .ioctl = snd_hdspm_ioctl, 6163 .ioctl = snd_hdspm_ioctl,
6164 .hw_params = snd_hdspm_hw_params, 6164 .hw_params = snd_hdspm_hw_params,
6165 .hw_free = snd_hdspm_hw_free, 6165 .hw_free = snd_hdspm_hw_free,
6166 .prepare = snd_hdspm_prepare, 6166 .prepare = snd_hdspm_prepare,
6167 .trigger = snd_hdspm_trigger, 6167 .trigger = snd_hdspm_trigger,
6168 .pointer = snd_hdspm_hw_pointer, 6168 .pointer = snd_hdspm_hw_pointer,
6169 .page = snd_pcm_sgbuf_ops_page, 6169 .page = snd_pcm_sgbuf_ops_page,
6170 }; 6170 };
6171 6171
6172 static int __devinit snd_hdspm_create_hwdep(struct snd_card *card, 6172 static int __devinit snd_hdspm_create_hwdep(struct snd_card *card,
6173 struct hdspm * hdspm) 6173 struct hdspm * hdspm)
6174 { 6174 {
6175 struct snd_hwdep *hw; 6175 struct snd_hwdep *hw;
6176 int err; 6176 int err;
6177 6177
6178 err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw); 6178 err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
6179 if (err < 0) 6179 if (err < 0)
6180 return err; 6180 return err;
6181 6181
6182 hdspm->hwdep = hw; 6182 hdspm->hwdep = hw;
6183 hw->private_data = hdspm; 6183 hw->private_data = hdspm;
6184 strcpy(hw->name, "HDSPM hwdep interface"); 6184 strcpy(hw->name, "HDSPM hwdep interface");
6185 6185
6186 hw->ops.open = snd_hdspm_hwdep_dummy_op; 6186 hw->ops.open = snd_hdspm_hwdep_dummy_op;
6187 hw->ops.ioctl = snd_hdspm_hwdep_ioctl; 6187 hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
6188 hw->ops.release = snd_hdspm_hwdep_dummy_op; 6188 hw->ops.release = snd_hdspm_hwdep_dummy_op;
6189 6189
6190 return 0; 6190 return 0;
6191 } 6191 }
6192 6192
6193 6193
6194 /*------------------------------------------------------------ 6194 /*------------------------------------------------------------
6195 memory interface 6195 memory interface
6196 ------------------------------------------------------------*/ 6196 ------------------------------------------------------------*/
6197 static int __devinit snd_hdspm_preallocate_memory(struct hdspm *hdspm) 6197 static int __devinit snd_hdspm_preallocate_memory(struct hdspm *hdspm)
6198 { 6198 {
6199 int err; 6199 int err;
6200 struct snd_pcm *pcm; 6200 struct snd_pcm *pcm;
6201 size_t wanted; 6201 size_t wanted;
6202 6202
6203 pcm = hdspm->pcm; 6203 pcm = hdspm->pcm;
6204 6204
6205 wanted = HDSPM_DMA_AREA_BYTES; 6205 wanted = HDSPM_DMA_AREA_BYTES;
6206 6206
6207 err = 6207 err =
6208 snd_pcm_lib_preallocate_pages_for_all(pcm, 6208 snd_pcm_lib_preallocate_pages_for_all(pcm,
6209 SNDRV_DMA_TYPE_DEV_SG, 6209 SNDRV_DMA_TYPE_DEV_SG,
6210 snd_dma_pci_data(hdspm->pci), 6210 snd_dma_pci_data(hdspm->pci),
6211 wanted, 6211 wanted,
6212 wanted); 6212 wanted);
6213 if (err < 0) { 6213 if (err < 0) {
6214 snd_printdd("Could not preallocate %zd Bytes\n", wanted); 6214 snd_printdd("Could not preallocate %zd Bytes\n", wanted);
6215 6215
6216 return err; 6216 return err;
6217 } else 6217 } else
6218 snd_printdd(" Preallocated %zd Bytes\n", wanted); 6218 snd_printdd(" Preallocated %zd Bytes\n", wanted);
6219 6219
6220 return 0; 6220 return 0;
6221 } 6221 }
6222 6222
6223 6223
6224 static void hdspm_set_sgbuf(struct hdspm *hdspm, 6224 static void hdspm_set_sgbuf(struct hdspm *hdspm,
6225 struct snd_pcm_substream *substream, 6225 struct snd_pcm_substream *substream,
6226 unsigned int reg, int channels) 6226 unsigned int reg, int channels)
6227 { 6227 {
6228 int i; 6228 int i;
6229 6229
6230 /* continuous memory segment */ 6230 /* continuous memory segment */
6231 for (i = 0; i < (channels * 16); i++) 6231 for (i = 0; i < (channels * 16); i++)
6232 hdspm_write(hdspm, reg + 4 * i, 6232 hdspm_write(hdspm, reg + 4 * i,
6233 snd_pcm_sgbuf_get_addr(substream, 4096 * i)); 6233 snd_pcm_sgbuf_get_addr(substream, 4096 * i));
6234 } 6234 }
6235 6235
6236 6236
6237 /* ------------- ALSA Devices ---------------------------- */ 6237 /* ------------- ALSA Devices ---------------------------- */
6238 static int __devinit snd_hdspm_create_pcm(struct snd_card *card, 6238 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
6239 struct hdspm *hdspm) 6239 struct hdspm *hdspm)
6240 { 6240 {
6241 struct snd_pcm *pcm; 6241 struct snd_pcm *pcm;
6242 int err; 6242 int err;
6243 6243
6244 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm); 6244 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6245 if (err < 0) 6245 if (err < 0)
6246 return err; 6246 return err;
6247 6247
6248 hdspm->pcm = pcm; 6248 hdspm->pcm = pcm;
6249 pcm->private_data = hdspm; 6249 pcm->private_data = hdspm;
6250 strcpy(pcm->name, hdspm->card_name); 6250 strcpy(pcm->name, hdspm->card_name);
6251 6251
6252 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, 6252 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
6253 &snd_hdspm_playback_ops); 6253 &snd_hdspm_playback_ops);
6254 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, 6254 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
6255 &snd_hdspm_capture_ops); 6255 &snd_hdspm_capture_ops);
6256 6256
6257 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 6257 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
6258 6258
6259 err = snd_hdspm_preallocate_memory(hdspm); 6259 err = snd_hdspm_preallocate_memory(hdspm);
6260 if (err < 0) 6260 if (err < 0)
6261 return err; 6261 return err;
6262 6262
6263 return 0; 6263 return 0;
6264 } 6264 }
6265 6265
6266 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm) 6266 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
6267 { 6267 {
6268 snd_hdspm_flush_midi_input(hdspm, 0); 6268 snd_hdspm_flush_midi_input(hdspm, 0);
6269 snd_hdspm_flush_midi_input(hdspm, 1); 6269 snd_hdspm_flush_midi_input(hdspm, 1);
6270 } 6270 }
6271 6271
6272 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card, 6272 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
6273 struct hdspm * hdspm) 6273 struct hdspm * hdspm)
6274 { 6274 {
6275 int err, i; 6275 int err, i;
6276 6276
6277 snd_printdd("Create card...\n"); 6277 snd_printdd("Create card...\n");
6278 err = snd_hdspm_create_pcm(card, hdspm); 6278 err = snd_hdspm_create_pcm(card, hdspm);
6279 if (err < 0) 6279 if (err < 0)
6280 return err; 6280 return err;
6281 6281
6282 i = 0; 6282 i = 0;
6283 while (i < hdspm->midiPorts) { 6283 while (i < hdspm->midiPorts) {
6284 err = snd_hdspm_create_midi(card, hdspm, i); 6284 err = snd_hdspm_create_midi(card, hdspm, i);
6285 if (err < 0) { 6285 if (err < 0) {
6286 return err; 6286 return err;
6287 } 6287 }
6288 i++; 6288 i++;
6289 } 6289 }
6290 6290
6291 err = snd_hdspm_create_controls(card, hdspm); 6291 err = snd_hdspm_create_controls(card, hdspm);
6292 if (err < 0) 6292 if (err < 0)
6293 return err; 6293 return err;
6294 6294
6295 err = snd_hdspm_create_hwdep(card, hdspm); 6295 err = snd_hdspm_create_hwdep(card, hdspm);
6296 if (err < 0) 6296 if (err < 0)
6297 return err; 6297 return err;
6298 6298
6299 snd_printdd("proc init...\n"); 6299 snd_printdd("proc init...\n");
6300 snd_hdspm_proc_init(hdspm); 6300 snd_hdspm_proc_init(hdspm);
6301 6301
6302 hdspm->system_sample_rate = -1; 6302 hdspm->system_sample_rate = -1;
6303 hdspm->last_external_sample_rate = -1; 6303 hdspm->last_external_sample_rate = -1;
6304 hdspm->last_internal_sample_rate = -1; 6304 hdspm->last_internal_sample_rate = -1;
6305 hdspm->playback_pid = -1; 6305 hdspm->playback_pid = -1;
6306 hdspm->capture_pid = -1; 6306 hdspm->capture_pid = -1;
6307 hdspm->capture_substream = NULL; 6307 hdspm->capture_substream = NULL;
6308 hdspm->playback_substream = NULL; 6308 hdspm->playback_substream = NULL;
6309 6309
6310 snd_printdd("Set defaults...\n"); 6310 snd_printdd("Set defaults...\n");
6311 err = snd_hdspm_set_defaults(hdspm); 6311 err = snd_hdspm_set_defaults(hdspm);
6312 if (err < 0) 6312 if (err < 0)
6313 return err; 6313 return err;
6314 6314
6315 snd_printdd("Update mixer controls...\n"); 6315 snd_printdd("Update mixer controls...\n");
6316 hdspm_update_simple_mixer_controls(hdspm); 6316 hdspm_update_simple_mixer_controls(hdspm);
6317 6317
6318 snd_printdd("Initializeing complete ???\n"); 6318 snd_printdd("Initializeing complete ???\n");
6319 6319
6320 err = snd_card_register(card); 6320 err = snd_card_register(card);
6321 if (err < 0) { 6321 if (err < 0) {
6322 snd_printk(KERN_ERR "HDSPM: error registering card\n"); 6322 snd_printk(KERN_ERR "HDSPM: error registering card\n");
6323 return err; 6323 return err;
6324 } 6324 }
6325 6325
6326 snd_printdd("... yes now\n"); 6326 snd_printdd("... yes now\n");
6327 6327
6328 return 0; 6328 return 0;
6329 } 6329 }
6330 6330
6331 static int __devinit snd_hdspm_create(struct snd_card *card, 6331 static int __devinit snd_hdspm_create(struct snd_card *card,
6332 struct hdspm *hdspm) { 6332 struct hdspm *hdspm) {
6333 6333
6334 struct pci_dev *pci = hdspm->pci; 6334 struct pci_dev *pci = hdspm->pci;
6335 int err; 6335 int err;
6336 unsigned long io_extent; 6336 unsigned long io_extent;
6337 6337
6338 hdspm->irq = -1; 6338 hdspm->irq = -1;
6339 hdspm->card = card; 6339 hdspm->card = card;
6340 6340
6341 spin_lock_init(&hdspm->lock); 6341 spin_lock_init(&hdspm->lock);
6342 6342
6343 pci_read_config_word(hdspm->pci, 6343 pci_read_config_word(hdspm->pci,
6344 PCI_CLASS_REVISION, &hdspm->firmware_rev); 6344 PCI_CLASS_REVISION, &hdspm->firmware_rev);
6345 6345
6346 strcpy(card->mixername, "Xilinx FPGA"); 6346 strcpy(card->mixername, "Xilinx FPGA");
6347 strcpy(card->driver, "HDSPM"); 6347 strcpy(card->driver, "HDSPM");
6348 6348
6349 switch (hdspm->firmware_rev) { 6349 switch (hdspm->firmware_rev) {
6350 case HDSPM_MADI_REV: 6350 case HDSPM_MADI_REV:
6351 hdspm->io_type = MADI; 6351 hdspm->io_type = MADI;
6352 hdspm->card_name = "RME MADI"; 6352 hdspm->card_name = "RME MADI";
6353 hdspm->midiPorts = 3; 6353 hdspm->midiPorts = 3;
6354 break; 6354 break;
6355 case HDSPM_RAYDAT_REV: 6355 case HDSPM_RAYDAT_REV:
6356 hdspm->io_type = RayDAT; 6356 hdspm->io_type = RayDAT;
6357 hdspm->card_name = "RME RayDAT"; 6357 hdspm->card_name = "RME RayDAT";
6358 hdspm->midiPorts = 2; 6358 hdspm->midiPorts = 2;
6359 break; 6359 break;
6360 case HDSPM_AIO_REV: 6360 case HDSPM_AIO_REV:
6361 hdspm->io_type = AIO; 6361 hdspm->io_type = AIO;
6362 hdspm->card_name = "RME AIO"; 6362 hdspm->card_name = "RME AIO";
6363 hdspm->midiPorts = 1; 6363 hdspm->midiPorts = 1;
6364 break; 6364 break;
6365 case HDSPM_MADIFACE_REV: 6365 case HDSPM_MADIFACE_REV:
6366 hdspm->io_type = MADIface; 6366 hdspm->io_type = MADIface;
6367 hdspm->card_name = "RME MADIface"; 6367 hdspm->card_name = "RME MADIface";
6368 hdspm->midiPorts = 1; 6368 hdspm->midiPorts = 1;
6369 break; 6369 break;
6370 case HDSPM_AES_REV: 6370 case HDSPM_AES_REV:
6371 hdspm->io_type = AES32; 6371 hdspm->io_type = AES32;
6372 hdspm->card_name = "RME AES32"; 6372 hdspm->card_name = "RME AES32";
6373 hdspm->midiPorts = 2; 6373 hdspm->midiPorts = 2;
6374 break; 6374 break;
6375 } 6375 }
6376 6376
6377 err = pci_enable_device(pci); 6377 err = pci_enable_device(pci);
6378 if (err < 0) 6378 if (err < 0)
6379 return err; 6379 return err;
6380 6380
6381 pci_set_master(hdspm->pci); 6381 pci_set_master(hdspm->pci);
6382 6382
6383 err = pci_request_regions(pci, "hdspm"); 6383 err = pci_request_regions(pci, "hdspm");
6384 if (err < 0) 6384 if (err < 0)
6385 return err; 6385 return err;
6386 6386
6387 hdspm->port = pci_resource_start(pci, 0); 6387 hdspm->port = pci_resource_start(pci, 0);
6388 io_extent = pci_resource_len(pci, 0); 6388 io_extent = pci_resource_len(pci, 0);
6389 6389
6390 snd_printdd("grabbed memory region 0x%lx-0x%lx\n", 6390 snd_printdd("grabbed memory region 0x%lx-0x%lx\n",
6391 hdspm->port, hdspm->port + io_extent - 1); 6391 hdspm->port, hdspm->port + io_extent - 1);
6392 6392
6393 hdspm->iobase = ioremap_nocache(hdspm->port, io_extent); 6393 hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
6394 if (!hdspm->iobase) { 6394 if (!hdspm->iobase) {
6395 snd_printk(KERN_ERR "HDSPM: " 6395 snd_printk(KERN_ERR "HDSPM: "
6396 "unable to remap region 0x%lx-0x%lx\n", 6396 "unable to remap region 0x%lx-0x%lx\n",
6397 hdspm->port, hdspm->port + io_extent - 1); 6397 hdspm->port, hdspm->port + io_extent - 1);
6398 return -EBUSY; 6398 return -EBUSY;
6399 } 6399 }
6400 snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n", 6400 snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n",
6401 (unsigned long)hdspm->iobase, hdspm->port, 6401 (unsigned long)hdspm->iobase, hdspm->port,
6402 hdspm->port + io_extent - 1); 6402 hdspm->port + io_extent - 1);
6403 6403
6404 if (request_irq(pci->irq, snd_hdspm_interrupt, 6404 if (request_irq(pci->irq, snd_hdspm_interrupt,
6405 IRQF_SHARED, "hdspm", hdspm)) { 6405 IRQF_SHARED, "hdspm", hdspm)) {
6406 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq); 6406 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq);
6407 return -EBUSY; 6407 return -EBUSY;
6408 } 6408 }
6409 6409
6410 snd_printdd("use IRQ %d\n", pci->irq); 6410 snd_printdd("use IRQ %d\n", pci->irq);
6411 6411
6412 hdspm->irq = pci->irq; 6412 hdspm->irq = pci->irq;
6413 6413
6414 snd_printdd("kmalloc Mixer memory of %zd Bytes\n", 6414 snd_printdd("kmalloc Mixer memory of %zd Bytes\n",
6415 sizeof(struct hdspm_mixer)); 6415 sizeof(struct hdspm_mixer));
6416 hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL); 6416 hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL);
6417 if (!hdspm->mixer) { 6417 if (!hdspm->mixer) {
6418 snd_printk(KERN_ERR "HDSPM: " 6418 snd_printk(KERN_ERR "HDSPM: "
6419 "unable to kmalloc Mixer memory of %d Bytes\n", 6419 "unable to kmalloc Mixer memory of %d Bytes\n",
6420 (int)sizeof(struct hdspm_mixer)); 6420 (int)sizeof(struct hdspm_mixer));
6421 return err; 6421 return err;
6422 } 6422 }
6423 6423
6424 hdspm->port_names_in = NULL; 6424 hdspm->port_names_in = NULL;
6425 hdspm->port_names_out = NULL; 6425 hdspm->port_names_out = NULL;
6426 6426
6427 switch (hdspm->io_type) { 6427 switch (hdspm->io_type) {
6428 case AES32: 6428 case AES32:
6429 hdspm->ss_in_channels = hdspm->ss_out_channels = 16; 6429 hdspm->ss_in_channels = hdspm->ss_out_channels = 16;
6430 hdspm->ds_in_channels = hdspm->ds_out_channels = 16; 6430 hdspm->ds_in_channels = hdspm->ds_out_channels = 16;
6431 hdspm->qs_in_channels = hdspm->qs_out_channels = 16; 6431 hdspm->qs_in_channels = hdspm->qs_out_channels = 16;
6432 6432
6433 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6433 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6434 channel_map_aes32; 6434 channel_map_aes32;
6435 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6435 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6436 channel_map_aes32; 6436 channel_map_aes32;
6437 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6437 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6438 channel_map_aes32; 6438 channel_map_aes32;
6439 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6439 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6440 texts_ports_aes32; 6440 texts_ports_aes32;
6441 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6441 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6442 texts_ports_aes32; 6442 texts_ports_aes32;
6443 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6443 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6444 texts_ports_aes32; 6444 texts_ports_aes32;
6445 6445
6446 hdspm->max_channels_out = hdspm->max_channels_in = 16; 6446 hdspm->max_channels_out = hdspm->max_channels_in = 16;
6447 hdspm->port_names_in = hdspm->port_names_out = 6447 hdspm->port_names_in = hdspm->port_names_out =
6448 texts_ports_aes32; 6448 texts_ports_aes32;
6449 hdspm->channel_map_in = hdspm->channel_map_out = 6449 hdspm->channel_map_in = hdspm->channel_map_out =
6450 channel_map_aes32; 6450 channel_map_aes32;
6451 6451
6452 break; 6452 break;
6453 6453
6454 case MADI: 6454 case MADI:
6455 case MADIface: 6455 case MADIface:
6456 hdspm->ss_in_channels = hdspm->ss_out_channels = 6456 hdspm->ss_in_channels = hdspm->ss_out_channels =
6457 MADI_SS_CHANNELS; 6457 MADI_SS_CHANNELS;
6458 hdspm->ds_in_channels = hdspm->ds_out_channels = 6458 hdspm->ds_in_channels = hdspm->ds_out_channels =
6459 MADI_DS_CHANNELS; 6459 MADI_DS_CHANNELS;
6460 hdspm->qs_in_channels = hdspm->qs_out_channels = 6460 hdspm->qs_in_channels = hdspm->qs_out_channels =
6461 MADI_QS_CHANNELS; 6461 MADI_QS_CHANNELS;
6462 6462
6463 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6463 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6464 channel_map_unity_ss; 6464 channel_map_unity_ss;
6465 hdspm->channel_map_in_ds = hdspm->channel_map_out_ss = 6465 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6466 channel_map_unity_ss; 6466 channel_map_unity_ss;
6467 hdspm->channel_map_in_qs = hdspm->channel_map_out_ss = 6467 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6468 channel_map_unity_ss; 6468 channel_map_unity_ss;
6469 6469
6470 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6470 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6471 texts_ports_madi; 6471 texts_ports_madi;
6472 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6472 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6473 texts_ports_madi; 6473 texts_ports_madi;
6474 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6474 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6475 texts_ports_madi; 6475 texts_ports_madi;
6476 break; 6476 break;
6477 6477
6478 case AIO: 6478 case AIO:
6479 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) { 6479 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
6480 snd_printk(KERN_INFO "HDSPM: AEB input board found, but not supported\n"); 6480 snd_printk(KERN_INFO "HDSPM: AEB input board found, but not supported\n");
6481 } 6481 }
6482 6482
6483 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS; 6483 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6484 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS; 6484 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6485 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS; 6485 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6486 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS; 6486 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6487 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS; 6487 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6488 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS; 6488 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6489 6489
6490 hdspm->channel_map_out_ss = channel_map_aio_out_ss; 6490 hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6491 hdspm->channel_map_out_ds = channel_map_aio_out_ds; 6491 hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6492 hdspm->channel_map_out_qs = channel_map_aio_out_qs; 6492 hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6493 6493
6494 hdspm->channel_map_in_ss = channel_map_aio_in_ss; 6494 hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6495 hdspm->channel_map_in_ds = channel_map_aio_in_ds; 6495 hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6496 hdspm->channel_map_in_qs = channel_map_aio_in_qs; 6496 hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6497 6497
6498 hdspm->port_names_in_ss = texts_ports_aio_in_ss; 6498 hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6499 hdspm->port_names_out_ss = texts_ports_aio_out_ss; 6499 hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6500 hdspm->port_names_in_ds = texts_ports_aio_in_ds; 6500 hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6501 hdspm->port_names_out_ds = texts_ports_aio_out_ds; 6501 hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6502 hdspm->port_names_in_qs = texts_ports_aio_in_qs; 6502 hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6503 hdspm->port_names_out_qs = texts_ports_aio_out_qs; 6503 hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6504 6504
6505 break; 6505 break;
6506 6506
6507 case RayDAT: 6507 case RayDAT:
6508 hdspm->ss_in_channels = hdspm->ss_out_channels = 6508 hdspm->ss_in_channels = hdspm->ss_out_channels =
6509 RAYDAT_SS_CHANNELS; 6509 RAYDAT_SS_CHANNELS;
6510 hdspm->ds_in_channels = hdspm->ds_out_channels = 6510 hdspm->ds_in_channels = hdspm->ds_out_channels =
6511 RAYDAT_DS_CHANNELS; 6511 RAYDAT_DS_CHANNELS;
6512 hdspm->qs_in_channels = hdspm->qs_out_channels = 6512 hdspm->qs_in_channels = hdspm->qs_out_channels =
6513 RAYDAT_QS_CHANNELS; 6513 RAYDAT_QS_CHANNELS;
6514 6514
6515 hdspm->max_channels_in = RAYDAT_SS_CHANNELS; 6515 hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6516 hdspm->max_channels_out = RAYDAT_SS_CHANNELS; 6516 hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6517 6517
6518 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6518 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6519 channel_map_raydat_ss; 6519 channel_map_raydat_ss;
6520 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6520 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6521 channel_map_raydat_ds; 6521 channel_map_raydat_ds;
6522 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6522 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6523 channel_map_raydat_qs; 6523 channel_map_raydat_qs;
6524 hdspm->channel_map_in = hdspm->channel_map_out = 6524 hdspm->channel_map_in = hdspm->channel_map_out =
6525 channel_map_raydat_ss; 6525 channel_map_raydat_ss;
6526 6526
6527 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6527 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6528 texts_ports_raydat_ss; 6528 texts_ports_raydat_ss;
6529 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6529 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6530 texts_ports_raydat_ds; 6530 texts_ports_raydat_ds;
6531 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6531 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6532 texts_ports_raydat_qs; 6532 texts_ports_raydat_qs;
6533 6533
6534 6534
6535 break; 6535 break;
6536 6536
6537 } 6537 }
6538 6538
6539 /* TCO detection */ 6539 /* TCO detection */
6540 switch (hdspm->io_type) { 6540 switch (hdspm->io_type) {
6541 case AIO: 6541 case AIO:
6542 case RayDAT: 6542 case RayDAT:
6543 if (hdspm_read(hdspm, HDSPM_statusRegister2) & 6543 if (hdspm_read(hdspm, HDSPM_statusRegister2) &
6544 HDSPM_s2_tco_detect) { 6544 HDSPM_s2_tco_detect) {
6545 hdspm->midiPorts++; 6545 hdspm->midiPorts++;
6546 hdspm->tco = kzalloc(sizeof(struct hdspm_tco), 6546 hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6547 GFP_KERNEL); 6547 GFP_KERNEL);
6548 if (NULL != hdspm->tco) { 6548 if (NULL != hdspm->tco) {
6549 hdspm_tco_write(hdspm); 6549 hdspm_tco_write(hdspm);
6550 } 6550 }
6551 snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n"); 6551 snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n");
6552 } else { 6552 } else {
6553 hdspm->tco = NULL; 6553 hdspm->tco = NULL;
6554 } 6554 }
6555 break; 6555 break;
6556 6556
6557 case MADI: 6557 case MADI:
6558 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) { 6558 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
6559 hdspm->midiPorts++; 6559 hdspm->midiPorts++;
6560 hdspm->tco = kzalloc(sizeof(struct hdspm_tco), 6560 hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6561 GFP_KERNEL); 6561 GFP_KERNEL);
6562 if (NULL != hdspm->tco) { 6562 if (NULL != hdspm->tco) {
6563 hdspm_tco_write(hdspm); 6563 hdspm_tco_write(hdspm);
6564 } 6564 }
6565 snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n"); 6565 snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n");
6566 } else { 6566 } else {
6567 hdspm->tco = NULL; 6567 hdspm->tco = NULL;
6568 } 6568 }
6569 break; 6569 break;
6570 6570
6571 default: 6571 default:
6572 hdspm->tco = NULL; 6572 hdspm->tco = NULL;
6573 } 6573 }
6574 6574
6575 /* texts */ 6575 /* texts */
6576 switch (hdspm->io_type) { 6576 switch (hdspm->io_type) {
6577 case AES32: 6577 case AES32:
6578 if (hdspm->tco) { 6578 if (hdspm->tco) {
6579 hdspm->texts_autosync = texts_autosync_aes_tco; 6579 hdspm->texts_autosync = texts_autosync_aes_tco;
6580 hdspm->texts_autosync_items = 10; 6580 hdspm->texts_autosync_items = 10;
6581 } else { 6581 } else {
6582 hdspm->texts_autosync = texts_autosync_aes; 6582 hdspm->texts_autosync = texts_autosync_aes;
6583 hdspm->texts_autosync_items = 9; 6583 hdspm->texts_autosync_items = 9;
6584 } 6584 }
6585 break; 6585 break;
6586 6586
6587 case MADI: 6587 case MADI:
6588 if (hdspm->tco) { 6588 if (hdspm->tco) {
6589 hdspm->texts_autosync = texts_autosync_madi_tco; 6589 hdspm->texts_autosync = texts_autosync_madi_tco;
6590 hdspm->texts_autosync_items = 4; 6590 hdspm->texts_autosync_items = 4;
6591 } else { 6591 } else {
6592 hdspm->texts_autosync = texts_autosync_madi; 6592 hdspm->texts_autosync = texts_autosync_madi;
6593 hdspm->texts_autosync_items = 3; 6593 hdspm->texts_autosync_items = 3;
6594 } 6594 }
6595 break; 6595 break;
6596 6596
6597 case MADIface: 6597 case MADIface:
6598 6598
6599 break; 6599 break;
6600 6600
6601 case RayDAT: 6601 case RayDAT:
6602 if (hdspm->tco) { 6602 if (hdspm->tco) {
6603 hdspm->texts_autosync = texts_autosync_raydat_tco; 6603 hdspm->texts_autosync = texts_autosync_raydat_tco;
6604 hdspm->texts_autosync_items = 9; 6604 hdspm->texts_autosync_items = 9;
6605 } else { 6605 } else {
6606 hdspm->texts_autosync = texts_autosync_raydat; 6606 hdspm->texts_autosync = texts_autosync_raydat;
6607 hdspm->texts_autosync_items = 8; 6607 hdspm->texts_autosync_items = 8;
6608 } 6608 }
6609 break; 6609 break;
6610 6610
6611 case AIO: 6611 case AIO:
6612 if (hdspm->tco) { 6612 if (hdspm->tco) {
6613 hdspm->texts_autosync = texts_autosync_aio_tco; 6613 hdspm->texts_autosync = texts_autosync_aio_tco;
6614 hdspm->texts_autosync_items = 6; 6614 hdspm->texts_autosync_items = 6;
6615 } else { 6615 } else {
6616 hdspm->texts_autosync = texts_autosync_aio; 6616 hdspm->texts_autosync = texts_autosync_aio;
6617 hdspm->texts_autosync_items = 5; 6617 hdspm->texts_autosync_items = 5;
6618 } 6618 }
6619 break; 6619 break;
6620 6620
6621 } 6621 }
6622 6622
6623 tasklet_init(&hdspm->midi_tasklet, 6623 tasklet_init(&hdspm->midi_tasklet,
6624 hdspm_midi_tasklet, (unsigned long) hdspm); 6624 hdspm_midi_tasklet, (unsigned long) hdspm);
6625 6625
6626 snd_printdd("create alsa devices.\n"); 6626 snd_printdd("create alsa devices.\n");
6627 err = snd_hdspm_create_alsa_devices(card, hdspm); 6627 err = snd_hdspm_create_alsa_devices(card, hdspm);
6628 if (err < 0) 6628 if (err < 0)
6629 return err; 6629 return err;
6630 6630
6631 snd_hdspm_initialize_midi_flush(hdspm); 6631 snd_hdspm_initialize_midi_flush(hdspm);
6632 6632
6633 return 0; 6633 return 0;
6634 } 6634 }
6635 6635
6636 6636
6637 static int snd_hdspm_free(struct hdspm * hdspm) 6637 static int snd_hdspm_free(struct hdspm * hdspm)
6638 { 6638 {
6639 6639
6640 if (hdspm->port) { 6640 if (hdspm->port) {
6641 6641
6642 /* stop th audio, and cancel all interrupts */ 6642 /* stop th audio, and cancel all interrupts */
6643 hdspm->control_register &= 6643 hdspm->control_register &=
6644 ~(HDSPM_Start | HDSPM_AudioInterruptEnable | 6644 ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
6645 HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable | 6645 HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
6646 HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable); 6646 HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
6647 hdspm_write(hdspm, HDSPM_controlRegister, 6647 hdspm_write(hdspm, HDSPM_controlRegister,
6648 hdspm->control_register); 6648 hdspm->control_register);
6649 } 6649 }
6650 6650
6651 if (hdspm->irq >= 0) 6651 if (hdspm->irq >= 0)
6652 free_irq(hdspm->irq, (void *) hdspm); 6652 free_irq(hdspm->irq, (void *) hdspm);
6653 6653
6654 kfree(hdspm->mixer); 6654 kfree(hdspm->mixer);
6655 6655
6656 if (hdspm->iobase) 6656 if (hdspm->iobase)
6657 iounmap(hdspm->iobase); 6657 iounmap(hdspm->iobase);
6658 6658
6659 if (hdspm->port) 6659 if (hdspm->port)
6660 pci_release_regions(hdspm->pci); 6660 pci_release_regions(hdspm->pci);
6661 6661
6662 pci_disable_device(hdspm->pci); 6662 pci_disable_device(hdspm->pci);
6663 return 0; 6663 return 0;
6664 } 6664 }
6665 6665
6666 6666
6667 static void snd_hdspm_card_free(struct snd_card *card) 6667 static void snd_hdspm_card_free(struct snd_card *card)
6668 { 6668 {
6669 struct hdspm *hdspm = card->private_data; 6669 struct hdspm *hdspm = card->private_data;
6670 6670
6671 if (hdspm) 6671 if (hdspm)
6672 snd_hdspm_free(hdspm); 6672 snd_hdspm_free(hdspm);
6673 } 6673 }
6674 6674
6675 6675
6676 static int __devinit snd_hdspm_probe(struct pci_dev *pci, 6676 static int __devinit snd_hdspm_probe(struct pci_dev *pci,
6677 const struct pci_device_id *pci_id) 6677 const struct pci_device_id *pci_id)
6678 { 6678 {
6679 static int dev; 6679 static int dev;
6680 struct hdspm *hdspm; 6680 struct hdspm *hdspm;
6681 struct snd_card *card; 6681 struct snd_card *card;
6682 int err; 6682 int err;
6683 6683
6684 if (dev >= SNDRV_CARDS) 6684 if (dev >= SNDRV_CARDS)
6685 return -ENODEV; 6685 return -ENODEV;
6686 if (!enable[dev]) { 6686 if (!enable[dev]) {
6687 dev++; 6687 dev++;
6688 return -ENOENT; 6688 return -ENOENT;
6689 } 6689 }
6690 6690
6691 err = snd_card_create(index[dev], id[dev], 6691 err = snd_card_create(index[dev], id[dev],
6692 THIS_MODULE, sizeof(struct hdspm), &card); 6692 THIS_MODULE, sizeof(struct hdspm), &card);
6693 if (err < 0) 6693 if (err < 0)
6694 return err; 6694 return err;
6695 6695
6696 hdspm = card->private_data; 6696 hdspm = card->private_data;
6697 card->private_free = snd_hdspm_card_free; 6697 card->private_free = snd_hdspm_card_free;
6698 hdspm->dev = dev; 6698 hdspm->dev = dev;
6699 hdspm->pci = pci; 6699 hdspm->pci = pci;
6700 6700
6701 snd_card_set_dev(card, &pci->dev); 6701 snd_card_set_dev(card, &pci->dev);
6702 6702
6703 err = snd_hdspm_create(card, hdspm); 6703 err = snd_hdspm_create(card, hdspm);
6704 if (err < 0) { 6704 if (err < 0) {
6705 snd_card_free(card); 6705 snd_card_free(card);
6706 return err; 6706 return err;
6707 } 6707 }
6708 6708
6709 if (hdspm->io_type != MADIface) { 6709 if (hdspm->io_type != MADIface) {
6710 sprintf(card->shortname, "%s_%x", 6710 sprintf(card->shortname, "%s_%x",
6711 hdspm->card_name, 6711 hdspm->card_name,
6712 (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF); 6712 (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF);
6713 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d", 6713 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d",
6714 hdspm->card_name, 6714 hdspm->card_name,
6715 (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF, 6715 (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF,
6716 hdspm->port, hdspm->irq); 6716 hdspm->port, hdspm->irq);
6717 } else { 6717 } else {
6718 sprintf(card->shortname, "%s", hdspm->card_name); 6718 sprintf(card->shortname, "%s", hdspm->card_name);
6719 sprintf(card->longname, "%s at 0x%lx, irq %d", 6719 sprintf(card->longname, "%s at 0x%lx, irq %d",
6720 hdspm->card_name, hdspm->port, hdspm->irq); 6720 hdspm->card_name, hdspm->port, hdspm->irq);
6721 } 6721 }
6722 6722
6723 err = snd_card_register(card); 6723 err = snd_card_register(card);
6724 if (err < 0) { 6724 if (err < 0) {
6725 snd_card_free(card); 6725 snd_card_free(card);
6726 return err; 6726 return err;
6727 } 6727 }
6728 6728
6729 pci_set_drvdata(pci, card); 6729 pci_set_drvdata(pci, card);
6730 6730
6731 dev++; 6731 dev++;
6732 return 0; 6732 return 0;
6733 } 6733 }
6734 6734
6735 static void __devexit snd_hdspm_remove(struct pci_dev *pci) 6735 static void __devexit snd_hdspm_remove(struct pci_dev *pci)
6736 { 6736 {
6737 snd_card_free(pci_get_drvdata(pci)); 6737 snd_card_free(pci_get_drvdata(pci));
6738 pci_set_drvdata(pci, NULL); 6738 pci_set_drvdata(pci, NULL);
6739 } 6739 }
6740 6740
6741 static struct pci_driver driver = { 6741 static struct pci_driver driver = {
6742 .name = "RME Hammerfall DSP MADI", 6742 .name = "RME Hammerfall DSP MADI",
6743 .id_table = snd_hdspm_ids, 6743 .id_table = snd_hdspm_ids,
6744 .probe = snd_hdspm_probe, 6744 .probe = snd_hdspm_probe,
6745 .remove = __devexit_p(snd_hdspm_remove), 6745 .remove = __devexit_p(snd_hdspm_remove),
6746 }; 6746 };
6747 6747
6748 6748
6749 static int __init alsa_card_hdspm_init(void) 6749 static int __init alsa_card_hdspm_init(void)
6750 { 6750 {
6751 return pci_register_driver(&driver); 6751 return pci_register_driver(&driver);
6752 } 6752 }
6753 6753
6754 static void __exit alsa_card_hdspm_exit(void) 6754 static void __exit alsa_card_hdspm_exit(void)
6755 { 6755 {
6756 pci_unregister_driver(&driver); 6756 pci_unregister_driver(&driver);
6757 } 6757 }
6758 6758
6759 module_init(alsa_card_hdspm_init) 6759 module_init(alsa_card_hdspm_init)
6760 module_exit(alsa_card_hdspm_exit) 6760 module_exit(alsa_card_hdspm_exit)
6761 6761