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Commit 022416967a814aa1b3a9476a842c0947a1a9d784

Authored by David Howells
Committed by Linus Torvalds
1 parent 69de7fc037
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

[PATCH] LOG2: Make powerpc's __ilog2_u64() take a 64-bit argument 

Make powerpc's __ilog2_u64() take a 64-bit argument.

Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

Showing 1 changed file with 1 additions and 1 deletions Inline Diff

include/asm-powerpc/bitops.h
Diff comments   View file @ 0224169
1 /* 1 /*
2 * PowerPC atomic bit operations. 2 * PowerPC atomic bit operations.
3 * 3 *
4 * Merged version by David Gibson <david@gibson.dropbear.id.au>. 4 * Merged version by David Gibson <david@gibson.dropbear.id.au>.
5 * Based on ppc64 versions by: Dave Engebretsen, Todd Inglett, Don 5 * Based on ppc64 versions by: Dave Engebretsen, Todd Inglett, Don
6 * Reed, Pat McCarthy, Peter Bergner, Anton Blanchard. They 6 * Reed, Pat McCarthy, Peter Bergner, Anton Blanchard. They
7 * originally took it from the ppc32 code. 7 * originally took it from the ppc32 code.
8 * 8 *
9 * Within a word, bits are numbered LSB first. Lot's of places make 9 * Within a word, bits are numbered LSB first. Lot's of places make
10 * this assumption by directly testing bits with (val & (1<<nr)). 10 * this assumption by directly testing bits with (val & (1<<nr)).
11 * This can cause confusion for large (> 1 word) bitmaps on a 11 * This can cause confusion for large (> 1 word) bitmaps on a
12 * big-endian system because, unlike little endian, the number of each 12 * big-endian system because, unlike little endian, the number of each
13 * bit depends on the word size. 13 * bit depends on the word size.
14 * 14 *
15 * The bitop functions are defined to work on unsigned longs, so for a 15 * The bitop functions are defined to work on unsigned longs, so for a
16 * ppc64 system the bits end up numbered: 16 * ppc64 system the bits end up numbered:
17 * |63..............0|127............64|191...........128|255...........196| 17 * |63..............0|127............64|191...........128|255...........196|
18 * and on ppc32: 18 * and on ppc32:
19 * |31.....0|63....31|95....64|127...96|159..128|191..160|223..192|255..224| 19 * |31.....0|63....31|95....64|127...96|159..128|191..160|223..192|255..224|
20 * 20 *
21 * There are a few little-endian macros used mostly for filesystem 21 * There are a few little-endian macros used mostly for filesystem
22 * bitmaps, these work on similar bit arrays layouts, but 22 * bitmaps, these work on similar bit arrays layouts, but
23 * byte-oriented: 23 * byte-oriented:
24 * |7...0|15...8|23...16|31...24|39...32|47...40|55...48|63...56| 24 * |7...0|15...8|23...16|31...24|39...32|47...40|55...48|63...56|
25 * 25 *
26 * The main difference is that bit 3-5 (64b) or 3-4 (32b) in the bit 26 * The main difference is that bit 3-5 (64b) or 3-4 (32b) in the bit
27 * number field needs to be reversed compared to the big-endian bit 27 * number field needs to be reversed compared to the big-endian bit
28 * fields. This can be achieved by XOR with 0x38 (64b) or 0x18 (32b). 28 * fields. This can be achieved by XOR with 0x38 (64b) or 0x18 (32b).
29 * 29 *
30 * This program is free software; you can redistribute it and/or 30 * This program is free software; you can redistribute it and/or
31 * modify it under the terms of the GNU General Public License 31 * modify it under the terms of the GNU General Public License
32 * as published by the Free Software Foundation; either version 32 * as published by the Free Software Foundation; either version
33 * 2 of the License, or (at your option) any later version. 33 * 2 of the License, or (at your option) any later version.
34 */ 34 */
35 35
36 #ifndef _ASM_POWERPC_BITOPS_H 36 #ifndef _ASM_POWERPC_BITOPS_H
37 #define _ASM_POWERPC_BITOPS_H 37 #define _ASM_POWERPC_BITOPS_H
38 38
39 #ifdef __KERNEL__ 39 #ifdef __KERNEL__
40 40
41 #include <linux/compiler.h> 41 #include <linux/compiler.h>
42 #include <asm/atomic.h> 42 #include <asm/atomic.h>
43 #include <asm/asm-compat.h> 43 #include <asm/asm-compat.h>
44 #include <asm/synch.h> 44 #include <asm/synch.h>
45 45
46 /* 46 /*
47 * clear_bit doesn't imply a memory barrier 47 * clear_bit doesn't imply a memory barrier
48 */ 48 */
49 #define smp_mb__before_clear_bit() smp_mb() 49 #define smp_mb__before_clear_bit() smp_mb()
50 #define smp_mb__after_clear_bit() smp_mb() 50 #define smp_mb__after_clear_bit() smp_mb()
51 51
52 #define BITOP_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) 52 #define BITOP_MASK(nr) (1UL << ((nr) % BITS_PER_LONG))
53 #define BITOP_WORD(nr) ((nr) / BITS_PER_LONG) 53 #define BITOP_WORD(nr) ((nr) / BITS_PER_LONG)
54 #define BITOP_LE_SWIZZLE ((BITS_PER_LONG-1) & ~0x7) 54 #define BITOP_LE_SWIZZLE ((BITS_PER_LONG-1) & ~0x7)
55 55
56 static __inline__ void set_bit(int nr, volatile unsigned long *addr) 56 static __inline__ void set_bit(int nr, volatile unsigned long *addr)
57 { 57 {
58 unsigned long old; 58 unsigned long old;
59 unsigned long mask = BITOP_MASK(nr); 59 unsigned long mask = BITOP_MASK(nr);
60 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr); 60 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
61 61
62 __asm__ __volatile__( 62 __asm__ __volatile__(
63 "1:" PPC_LLARX "%0,0,%3 # set_bit\n" 63 "1:" PPC_LLARX "%0,0,%3 # set_bit\n"
64 "or %0,%0,%2\n" 64 "or %0,%0,%2\n"
65 PPC405_ERR77(0,%3) 65 PPC405_ERR77(0,%3)
66 PPC_STLCX "%0,0,%3\n" 66 PPC_STLCX "%0,0,%3\n"
67 "bne- 1b" 67 "bne- 1b"
68 : "=&r" (old), "+m" (*p) 68 : "=&r" (old), "+m" (*p)
69 : "r" (mask), "r" (p) 69 : "r" (mask), "r" (p)
70 : "cc" ); 70 : "cc" );
71 } 71 }
72 72
73 static __inline__ void clear_bit(int nr, volatile unsigned long *addr) 73 static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
74 { 74 {
75 unsigned long old; 75 unsigned long old;
76 unsigned long mask = BITOP_MASK(nr); 76 unsigned long mask = BITOP_MASK(nr);
77 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr); 77 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
78 78
79 __asm__ __volatile__( 79 __asm__ __volatile__(
80 "1:" PPC_LLARX "%0,0,%3 # clear_bit\n" 80 "1:" PPC_LLARX "%0,0,%3 # clear_bit\n"
81 "andc %0,%0,%2\n" 81 "andc %0,%0,%2\n"
82 PPC405_ERR77(0,%3) 82 PPC405_ERR77(0,%3)
83 PPC_STLCX "%0,0,%3\n" 83 PPC_STLCX "%0,0,%3\n"
84 "bne- 1b" 84 "bne- 1b"
85 : "=&r" (old), "+m" (*p) 85 : "=&r" (old), "+m" (*p)
86 : "r" (mask), "r" (p) 86 : "r" (mask), "r" (p)
87 : "cc" ); 87 : "cc" );
88 } 88 }
89 89
90 static __inline__ void change_bit(int nr, volatile unsigned long *addr) 90 static __inline__ void change_bit(int nr, volatile unsigned long *addr)
91 { 91 {
92 unsigned long old; 92 unsigned long old;
93 unsigned long mask = BITOP_MASK(nr); 93 unsigned long mask = BITOP_MASK(nr);
94 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr); 94 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
95 95
96 __asm__ __volatile__( 96 __asm__ __volatile__(
97 "1:" PPC_LLARX "%0,0,%3 # change_bit\n" 97 "1:" PPC_LLARX "%0,0,%3 # change_bit\n"
98 "xor %0,%0,%2\n" 98 "xor %0,%0,%2\n"
99 PPC405_ERR77(0,%3) 99 PPC405_ERR77(0,%3)
100 PPC_STLCX "%0,0,%3\n" 100 PPC_STLCX "%0,0,%3\n"
101 "bne- 1b" 101 "bne- 1b"
102 : "=&r" (old), "+m" (*p) 102 : "=&r" (old), "+m" (*p)
103 : "r" (mask), "r" (p) 103 : "r" (mask), "r" (p)
104 : "cc" ); 104 : "cc" );
105 } 105 }
106 106
107 static __inline__ int test_and_set_bit(unsigned long nr, 107 static __inline__ int test_and_set_bit(unsigned long nr,
108 volatile unsigned long *addr) 108 volatile unsigned long *addr)
109 { 109 {
110 unsigned long old, t; 110 unsigned long old, t;
111 unsigned long mask = BITOP_MASK(nr); 111 unsigned long mask = BITOP_MASK(nr);
112 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr); 112 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
113 113
114 __asm__ __volatile__( 114 __asm__ __volatile__(
115 LWSYNC_ON_SMP 115 LWSYNC_ON_SMP
116 "1:" PPC_LLARX "%0,0,%3 # test_and_set_bit\n" 116 "1:" PPC_LLARX "%0,0,%3 # test_and_set_bit\n"
117 "or %1,%0,%2 \n" 117 "or %1,%0,%2 \n"
118 PPC405_ERR77(0,%3) 118 PPC405_ERR77(0,%3)
119 PPC_STLCX "%1,0,%3 \n" 119 PPC_STLCX "%1,0,%3 \n"
120 "bne- 1b" 120 "bne- 1b"
121 ISYNC_ON_SMP 121 ISYNC_ON_SMP
122 : "=&r" (old), "=&r" (t) 122 : "=&r" (old), "=&r" (t)
123 : "r" (mask), "r" (p) 123 : "r" (mask), "r" (p)
124 : "cc", "memory"); 124 : "cc", "memory");
125 125
126 return (old & mask) != 0; 126 return (old & mask) != 0;
127 } 127 }
128 128
129 static __inline__ int test_and_clear_bit(unsigned long nr, 129 static __inline__ int test_and_clear_bit(unsigned long nr,
130 volatile unsigned long *addr) 130 volatile unsigned long *addr)
131 { 131 {
132 unsigned long old, t; 132 unsigned long old, t;
133 unsigned long mask = BITOP_MASK(nr); 133 unsigned long mask = BITOP_MASK(nr);
134 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr); 134 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
135 135
136 __asm__ __volatile__( 136 __asm__ __volatile__(
137 LWSYNC_ON_SMP 137 LWSYNC_ON_SMP
138 "1:" PPC_LLARX "%0,0,%3 # test_and_clear_bit\n" 138 "1:" PPC_LLARX "%0,0,%3 # test_and_clear_bit\n"
139 "andc %1,%0,%2 \n" 139 "andc %1,%0,%2 \n"
140 PPC405_ERR77(0,%3) 140 PPC405_ERR77(0,%3)
141 PPC_STLCX "%1,0,%3 \n" 141 PPC_STLCX "%1,0,%3 \n"
142 "bne- 1b" 142 "bne- 1b"
143 ISYNC_ON_SMP 143 ISYNC_ON_SMP
144 : "=&r" (old), "=&r" (t) 144 : "=&r" (old), "=&r" (t)
145 : "r" (mask), "r" (p) 145 : "r" (mask), "r" (p)
146 : "cc", "memory"); 146 : "cc", "memory");
147 147
148 return (old & mask) != 0; 148 return (old & mask) != 0;
149 } 149 }
150 150
151 static __inline__ int test_and_change_bit(unsigned long nr, 151 static __inline__ int test_and_change_bit(unsigned long nr,
152 volatile unsigned long *addr) 152 volatile unsigned long *addr)
153 { 153 {
154 unsigned long old, t; 154 unsigned long old, t;
155 unsigned long mask = BITOP_MASK(nr); 155 unsigned long mask = BITOP_MASK(nr);
156 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr); 156 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
157 157
158 __asm__ __volatile__( 158 __asm__ __volatile__(
159 LWSYNC_ON_SMP 159 LWSYNC_ON_SMP
160 "1:" PPC_LLARX "%0,0,%3 # test_and_change_bit\n" 160 "1:" PPC_LLARX "%0,0,%3 # test_and_change_bit\n"
161 "xor %1,%0,%2 \n" 161 "xor %1,%0,%2 \n"
162 PPC405_ERR77(0,%3) 162 PPC405_ERR77(0,%3)
163 PPC_STLCX "%1,0,%3 \n" 163 PPC_STLCX "%1,0,%3 \n"
164 "bne- 1b" 164 "bne- 1b"
165 ISYNC_ON_SMP 165 ISYNC_ON_SMP
166 : "=&r" (old), "=&r" (t) 166 : "=&r" (old), "=&r" (t)
167 : "r" (mask), "r" (p) 167 : "r" (mask), "r" (p)
168 : "cc", "memory"); 168 : "cc", "memory");
169 169
170 return (old & mask) != 0; 170 return (old & mask) != 0;
171 } 171 }
172 172
173 static __inline__ void set_bits(unsigned long mask, unsigned long *addr) 173 static __inline__ void set_bits(unsigned long mask, unsigned long *addr)
174 { 174 {
175 unsigned long old; 175 unsigned long old;
176 176
177 __asm__ __volatile__( 177 __asm__ __volatile__(
178 "1:" PPC_LLARX "%0,0,%3 # set_bits\n" 178 "1:" PPC_LLARX "%0,0,%3 # set_bits\n"
179 "or %0,%0,%2\n" 179 "or %0,%0,%2\n"
180 PPC_STLCX "%0,0,%3\n" 180 PPC_STLCX "%0,0,%3\n"
181 "bne- 1b" 181 "bne- 1b"
182 : "=&r" (old), "+m" (*addr) 182 : "=&r" (old), "+m" (*addr)
183 : "r" (mask), "r" (addr) 183 : "r" (mask), "r" (addr)
184 : "cc"); 184 : "cc");
185 } 185 }
186 186
187 #include <asm-generic/bitops/non-atomic.h> 187 #include <asm-generic/bitops/non-atomic.h>
188 188
189 /* 189 /*
190 * Return the zero-based bit position (LE, not IBM bit numbering) of 190 * Return the zero-based bit position (LE, not IBM bit numbering) of
191 * the most significant 1-bit in a double word. 191 * the most significant 1-bit in a double word.
192 */ 192 */
193 static __inline__ __attribute__((const)) 193 static __inline__ __attribute__((const))
194 int __ilog2(unsigned long x) 194 int __ilog2(unsigned long x)
195 { 195 {
196 int lz; 196 int lz;
197 197
198 asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (x)); 198 asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (x));
199 return BITS_PER_LONG - 1 - lz; 199 return BITS_PER_LONG - 1 - lz;
200 } 200 }
201 201
202 static inline __attribute__((const)) 202 static inline __attribute__((const))
203 int __ilog2_u32(u32 n) 203 int __ilog2_u32(u32 n)
204 { 204 {
205 int bit; 205 int bit;
206 asm ("cntlzw %0,%1" : "=r" (bit) : "r" (n)); 206 asm ("cntlzw %0,%1" : "=r" (bit) : "r" (n));
207 return 31 - bit; 207 return 31 - bit;
208 } 208 }
209 209
210 #ifdef __powerpc64__ 210 #ifdef __powerpc64__
211 static inline __attribute__((const)) 211 static inline __attribute__((const))
212 int __ilog2_u64(u32 n) 212 int __ilog2_u64(u64 n)
213 { 213 {
214 int bit; 214 int bit;
215 asm ("cntlzd %0,%1" : "=r" (bit) : "r" (n)); 215 asm ("cntlzd %0,%1" : "=r" (bit) : "r" (n));
216 return 63 - bit; 216 return 63 - bit;
217 } 217 }
218 #endif 218 #endif
219 219
220 /* 220 /*
221 * Determines the bit position of the least significant 0 bit in the 221 * Determines the bit position of the least significant 0 bit in the
222 * specified double word. The returned bit position will be 222 * specified double word. The returned bit position will be
223 * zero-based, starting from the right side (63/31 - 0). 223 * zero-based, starting from the right side (63/31 - 0).
224 */ 224 */
225 static __inline__ unsigned long ffz(unsigned long x) 225 static __inline__ unsigned long ffz(unsigned long x)
226 { 226 {
227 /* no zero exists anywhere in the 8 byte area. */ 227 /* no zero exists anywhere in the 8 byte area. */
228 if ((x = ~x) == 0) 228 if ((x = ~x) == 0)
229 return BITS_PER_LONG; 229 return BITS_PER_LONG;
230 230
231 /* 231 /*
232 * Calculate the bit position of the least signficant '1' bit in x 232 * Calculate the bit position of the least signficant '1' bit in x
233 * (since x has been changed this will actually be the least signficant 233 * (since x has been changed this will actually be the least signficant
234 * '0' bit in * the original x). Note: (x & -x) gives us a mask that 234 * '0' bit in * the original x). Note: (x & -x) gives us a mask that
235 * is the least significant * (RIGHT-most) 1-bit of the value in x. 235 * is the least significant * (RIGHT-most) 1-bit of the value in x.
236 */ 236 */
237 return __ilog2(x & -x); 237 return __ilog2(x & -x);
238 } 238 }
239 239
240 static __inline__ int __ffs(unsigned long x) 240 static __inline__ int __ffs(unsigned long x)
241 { 241 {
242 return __ilog2(x & -x); 242 return __ilog2(x & -x);
243 } 243 }
244 244
245 /* 245 /*
246 * ffs: find first bit set. This is defined the same way as 246 * ffs: find first bit set. This is defined the same way as
247 * the libc and compiler builtin ffs routines, therefore 247 * the libc and compiler builtin ffs routines, therefore
248 * differs in spirit from the above ffz (man ffs). 248 * differs in spirit from the above ffz (man ffs).
249 */ 249 */
250 static __inline__ int ffs(int x) 250 static __inline__ int ffs(int x)
251 { 251 {
252 unsigned long i = (unsigned long)x; 252 unsigned long i = (unsigned long)x;
253 return __ilog2(i & -i) + 1; 253 return __ilog2(i & -i) + 1;
254 } 254 }
255 255
256 /* 256 /*
257 * fls: find last (most-significant) bit set. 257 * fls: find last (most-significant) bit set.
258 * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. 258 * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
259 */ 259 */
260 static __inline__ int fls(unsigned int x) 260 static __inline__ int fls(unsigned int x)
261 { 261 {
262 int lz; 262 int lz;
263 263
264 asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x)); 264 asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
265 return 32 - lz; 265 return 32 - lz;
266 } 266 }
267 #include <asm-generic/bitops/fls64.h> 267 #include <asm-generic/bitops/fls64.h>
268 268
269 #include <asm-generic/bitops/hweight.h> 269 #include <asm-generic/bitops/hweight.h>
270 270
271 #define find_first_zero_bit(addr, size) find_next_zero_bit((addr), (size), 0) 271 #define find_first_zero_bit(addr, size) find_next_zero_bit((addr), (size), 0)
272 unsigned long find_next_zero_bit(const unsigned long *addr, 272 unsigned long find_next_zero_bit(const unsigned long *addr,
273 unsigned long size, unsigned long offset); 273 unsigned long size, unsigned long offset);
274 /** 274 /**
275 * find_first_bit - find the first set bit in a memory region 275 * find_first_bit - find the first set bit in a memory region
276 * @addr: The address to start the search at 276 * @addr: The address to start the search at
277 * @size: The maximum size to search 277 * @size: The maximum size to search
278 * 278 *
279 * Returns the bit-number of the first set bit, not the number of the byte 279 * Returns the bit-number of the first set bit, not the number of the byte
280 * containing a bit. 280 * containing a bit.
281 */ 281 */
282 #define find_first_bit(addr, size) find_next_bit((addr), (size), 0) 282 #define find_first_bit(addr, size) find_next_bit((addr), (size), 0)
283 unsigned long find_next_bit(const unsigned long *addr, 283 unsigned long find_next_bit(const unsigned long *addr,
284 unsigned long size, unsigned long offset); 284 unsigned long size, unsigned long offset);
285 285
286 /* Little-endian versions */ 286 /* Little-endian versions */
287 287
288 static __inline__ int test_le_bit(unsigned long nr, 288 static __inline__ int test_le_bit(unsigned long nr,
289 __const__ unsigned long *addr) 289 __const__ unsigned long *addr)
290 { 290 {
291 __const__ unsigned char *tmp = (__const__ unsigned char *) addr; 291 __const__ unsigned char *tmp = (__const__ unsigned char *) addr;
292 return (tmp[nr >> 3] >> (nr & 7)) & 1; 292 return (tmp[nr >> 3] >> (nr & 7)) & 1;
293 } 293 }
294 294
295 #define __set_le_bit(nr, addr) \ 295 #define __set_le_bit(nr, addr) \
296 __set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr)) 296 __set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
297 #define __clear_le_bit(nr, addr) \ 297 #define __clear_le_bit(nr, addr) \
298 __clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr)) 298 __clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
299 299
300 #define test_and_set_le_bit(nr, addr) \ 300 #define test_and_set_le_bit(nr, addr) \
301 test_and_set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr)) 301 test_and_set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
302 #define test_and_clear_le_bit(nr, addr) \ 302 #define test_and_clear_le_bit(nr, addr) \
303 test_and_clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr)) 303 test_and_clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
304 304
305 #define __test_and_set_le_bit(nr, addr) \ 305 #define __test_and_set_le_bit(nr, addr) \
306 __test_and_set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr)) 306 __test_and_set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
307 #define __test_and_clear_le_bit(nr, addr) \ 307 #define __test_and_clear_le_bit(nr, addr) \
308 __test_and_clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr)) 308 __test_and_clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
309 309
310 #define find_first_zero_le_bit(addr, size) generic_find_next_zero_le_bit((addr), (size), 0) 310 #define find_first_zero_le_bit(addr, size) generic_find_next_zero_le_bit((addr), (size), 0)
311 unsigned long generic_find_next_zero_le_bit(const unsigned long *addr, 311 unsigned long generic_find_next_zero_le_bit(const unsigned long *addr,
312 unsigned long size, unsigned long offset); 312 unsigned long size, unsigned long offset);
313 313
314 /* Bitmap functions for the ext2 filesystem */ 314 /* Bitmap functions for the ext2 filesystem */
315 315
316 #define ext2_set_bit(nr,addr) \ 316 #define ext2_set_bit(nr,addr) \
317 __test_and_set_le_bit((nr), (unsigned long*)addr) 317 __test_and_set_le_bit((nr), (unsigned long*)addr)
318 #define ext2_clear_bit(nr, addr) \ 318 #define ext2_clear_bit(nr, addr) \
319 __test_and_clear_le_bit((nr), (unsigned long*)addr) 319 __test_and_clear_le_bit((nr), (unsigned long*)addr)
320 320
321 #define ext2_set_bit_atomic(lock, nr, addr) \ 321 #define ext2_set_bit_atomic(lock, nr, addr) \
322 test_and_set_le_bit((nr), (unsigned long*)addr) 322 test_and_set_le_bit((nr), (unsigned long*)addr)
323 #define ext2_clear_bit_atomic(lock, nr, addr) \ 323 #define ext2_clear_bit_atomic(lock, nr, addr) \
324 test_and_clear_le_bit((nr), (unsigned long*)addr) 324 test_and_clear_le_bit((nr), (unsigned long*)addr)
325 325
326 #define ext2_test_bit(nr, addr) test_le_bit((nr),(unsigned long*)addr) 326 #define ext2_test_bit(nr, addr) test_le_bit((nr),(unsigned long*)addr)
327 327
328 #define ext2_find_first_zero_bit(addr, size) \ 328 #define ext2_find_first_zero_bit(addr, size) \
329 find_first_zero_le_bit((unsigned long*)addr, size) 329 find_first_zero_le_bit((unsigned long*)addr, size)
330 #define ext2_find_next_zero_bit(addr, size, off) \ 330 #define ext2_find_next_zero_bit(addr, size, off) \
331 generic_find_next_zero_le_bit((unsigned long*)addr, size, off) 331 generic_find_next_zero_le_bit((unsigned long*)addr, size, off)
332 332
333 /* Bitmap functions for the minix filesystem. */ 333 /* Bitmap functions for the minix filesystem. */
334 334
335 #define minix_test_and_set_bit(nr,addr) \ 335 #define minix_test_and_set_bit(nr,addr) \
336 __test_and_set_le_bit(nr, (unsigned long *)addr) 336 __test_and_set_le_bit(nr, (unsigned long *)addr)
337 #define minix_set_bit(nr,addr) \ 337 #define minix_set_bit(nr,addr) \
338 __set_le_bit(nr, (unsigned long *)addr) 338 __set_le_bit(nr, (unsigned long *)addr)
339 #define minix_test_and_clear_bit(nr,addr) \ 339 #define minix_test_and_clear_bit(nr,addr) \
340 __test_and_clear_le_bit(nr, (unsigned long *)addr) 340 __test_and_clear_le_bit(nr, (unsigned long *)addr)
341 #define minix_test_bit(nr,addr) \ 341 #define minix_test_bit(nr,addr) \
342 test_le_bit(nr, (unsigned long *)addr) 342 test_le_bit(nr, (unsigned long *)addr)
343 343
344 #define minix_find_first_zero_bit(addr,size) \ 344 #define minix_find_first_zero_bit(addr,size) \
345 find_first_zero_le_bit((unsigned long *)addr, size) 345 find_first_zero_le_bit((unsigned long *)addr, size)
346 346
347 #include <asm-generic/bitops/sched.h> 347 #include <asm-generic/bitops/sched.h>
348 348
349 #endif /* __KERNEL__ */ 349 #endif /* __KERNEL__ */
350 350
351 #endif /* _ASM_POWERPC_BITOPS_H */ 351 #endif /* _ASM_POWERPC_BITOPS_H */
352 352