Doug / smarc-fsl-linux-kernel

Download as
Browse Code ยป

Commit 02d8bf8dc6b09cb810599c64d47da3bdf4f85882

Authored by Laxman Dewangan
Committed by Wolfram Sang
1 parent 9dce4bcaaa
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

i2c: tegra: use of_match_ptr() for match_table initialization 

In place of defining match_table for non-DT based as NULL,
use of_match_ptr() for initialzing the of_match_table.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>

Showing 1 changed file with 1 additions and 3 deletions Inline Diff

drivers/i2c/busses/i2c-tegra.c
Diff comments   View file @ 02d8bf8
1 /* 1 /*
2 * drivers/i2c/busses/i2c-tegra.c 2 * drivers/i2c/busses/i2c-tegra.c
3 * 3 *
4 * Copyright (C) 2010 Google, Inc. 4 * Copyright (C) 2010 Google, Inc.
5 * Author: Colin Cross <ccross@android.com> 5 * Author: Colin Cross <ccross@android.com>
6 * 6 *
7 * This software is licensed under the terms of the GNU General Public 7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and 8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms. 9 * may be copied, distributed, and modified under those terms.
10 * 10 *
11 * This program is distributed in the hope that it will be useful, 11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 * 15 *
16 */ 16 */
17 17
18 #include <linux/kernel.h> 18 #include <linux/kernel.h>
19 #include <linux/init.h> 19 #include <linux/init.h>
20 #include <linux/platform_device.h> 20 #include <linux/platform_device.h>
21 #include <linux/clk.h> 21 #include <linux/clk.h>
22 #include <linux/err.h> 22 #include <linux/err.h>
23 #include <linux/i2c.h> 23 #include <linux/i2c.h>
24 #include <linux/io.h> 24 #include <linux/io.h>
25 #include <linux/interrupt.h> 25 #include <linux/interrupt.h>
26 #include <linux/delay.h> 26 #include <linux/delay.h>
27 #include <linux/slab.h> 27 #include <linux/slab.h>
28 #include <linux/i2c-tegra.h> 28 #include <linux/i2c-tegra.h>
29 #include <linux/of_i2c.h> 29 #include <linux/of_i2c.h>
30 #include <linux/module.h> 30 #include <linux/module.h>
31 31
32 #include <asm/unaligned.h> 32 #include <asm/unaligned.h>
33 33
34 #include <mach/clk.h> 34 #include <mach/clk.h>
35 35
36 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000)) 36 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
37 #define BYTES_PER_FIFO_WORD 4 37 #define BYTES_PER_FIFO_WORD 4
38 38
39 #define I2C_CNFG 0x000 39 #define I2C_CNFG 0x000
40 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12 40 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12
41 #define I2C_CNFG_PACKET_MODE_EN (1<<10) 41 #define I2C_CNFG_PACKET_MODE_EN (1<<10)
42 #define I2C_CNFG_NEW_MASTER_FSM (1<<11) 42 #define I2C_CNFG_NEW_MASTER_FSM (1<<11)
43 #define I2C_STATUS 0x01C 43 #define I2C_STATUS 0x01C
44 #define I2C_SL_CNFG 0x020 44 #define I2C_SL_CNFG 0x020
45 #define I2C_SL_CNFG_NACK (1<<1) 45 #define I2C_SL_CNFG_NACK (1<<1)
46 #define I2C_SL_CNFG_NEWSL (1<<2) 46 #define I2C_SL_CNFG_NEWSL (1<<2)
47 #define I2C_SL_ADDR1 0x02c 47 #define I2C_SL_ADDR1 0x02c
48 #define I2C_SL_ADDR2 0x030 48 #define I2C_SL_ADDR2 0x030
49 #define I2C_TX_FIFO 0x050 49 #define I2C_TX_FIFO 0x050
50 #define I2C_RX_FIFO 0x054 50 #define I2C_RX_FIFO 0x054
51 #define I2C_PACKET_TRANSFER_STATUS 0x058 51 #define I2C_PACKET_TRANSFER_STATUS 0x058
52 #define I2C_FIFO_CONTROL 0x05c 52 #define I2C_FIFO_CONTROL 0x05c
53 #define I2C_FIFO_CONTROL_TX_FLUSH (1<<1) 53 #define I2C_FIFO_CONTROL_TX_FLUSH (1<<1)
54 #define I2C_FIFO_CONTROL_RX_FLUSH (1<<0) 54 #define I2C_FIFO_CONTROL_RX_FLUSH (1<<0)
55 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5 55 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5
56 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2 56 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2
57 #define I2C_FIFO_STATUS 0x060 57 #define I2C_FIFO_STATUS 0x060
58 #define I2C_FIFO_STATUS_TX_MASK 0xF0 58 #define I2C_FIFO_STATUS_TX_MASK 0xF0
59 #define I2C_FIFO_STATUS_TX_SHIFT 4 59 #define I2C_FIFO_STATUS_TX_SHIFT 4
60 #define I2C_FIFO_STATUS_RX_MASK 0x0F 60 #define I2C_FIFO_STATUS_RX_MASK 0x0F
61 #define I2C_FIFO_STATUS_RX_SHIFT 0 61 #define I2C_FIFO_STATUS_RX_SHIFT 0
62 #define I2C_INT_MASK 0x064 62 #define I2C_INT_MASK 0x064
63 #define I2C_INT_STATUS 0x068 63 #define I2C_INT_STATUS 0x068
64 #define I2C_INT_PACKET_XFER_COMPLETE (1<<7) 64 #define I2C_INT_PACKET_XFER_COMPLETE (1<<7)
65 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE (1<<6) 65 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE (1<<6)
66 #define I2C_INT_TX_FIFO_OVERFLOW (1<<5) 66 #define I2C_INT_TX_FIFO_OVERFLOW (1<<5)
67 #define I2C_INT_RX_FIFO_UNDERFLOW (1<<4) 67 #define I2C_INT_RX_FIFO_UNDERFLOW (1<<4)
68 #define I2C_INT_NO_ACK (1<<3) 68 #define I2C_INT_NO_ACK (1<<3)
69 #define I2C_INT_ARBITRATION_LOST (1<<2) 69 #define I2C_INT_ARBITRATION_LOST (1<<2)
70 #define I2C_INT_TX_FIFO_DATA_REQ (1<<1) 70 #define I2C_INT_TX_FIFO_DATA_REQ (1<<1)
71 #define I2C_INT_RX_FIFO_DATA_REQ (1<<0) 71 #define I2C_INT_RX_FIFO_DATA_REQ (1<<0)
72 #define I2C_CLK_DIVISOR 0x06c 72 #define I2C_CLK_DIVISOR 0x06c
73 73
74 #define DVC_CTRL_REG1 0x000 74 #define DVC_CTRL_REG1 0x000
75 #define DVC_CTRL_REG1_INTR_EN (1<<10) 75 #define DVC_CTRL_REG1_INTR_EN (1<<10)
76 #define DVC_CTRL_REG2 0x004 76 #define DVC_CTRL_REG2 0x004
77 #define DVC_CTRL_REG3 0x008 77 #define DVC_CTRL_REG3 0x008
78 #define DVC_CTRL_REG3_SW_PROG (1<<26) 78 #define DVC_CTRL_REG3_SW_PROG (1<<26)
79 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN (1<<30) 79 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN (1<<30)
80 #define DVC_STATUS 0x00c 80 #define DVC_STATUS 0x00c
81 #define DVC_STATUS_I2C_DONE_INTR (1<<30) 81 #define DVC_STATUS_I2C_DONE_INTR (1<<30)
82 82
83 #define I2C_ERR_NONE 0x00 83 #define I2C_ERR_NONE 0x00
84 #define I2C_ERR_NO_ACK 0x01 84 #define I2C_ERR_NO_ACK 0x01
85 #define I2C_ERR_ARBITRATION_LOST 0x02 85 #define I2C_ERR_ARBITRATION_LOST 0x02
86 #define I2C_ERR_UNKNOWN_INTERRUPT 0x04 86 #define I2C_ERR_UNKNOWN_INTERRUPT 0x04
87 87
88 #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28 88 #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28
89 #define PACKET_HEADER0_PACKET_ID_SHIFT 16 89 #define PACKET_HEADER0_PACKET_ID_SHIFT 16
90 #define PACKET_HEADER0_CONT_ID_SHIFT 12 90 #define PACKET_HEADER0_CONT_ID_SHIFT 12
91 #define PACKET_HEADER0_PROTOCOL_I2C (1<<4) 91 #define PACKET_HEADER0_PROTOCOL_I2C (1<<4)
92 92
93 #define I2C_HEADER_HIGHSPEED_MODE (1<<22) 93 #define I2C_HEADER_HIGHSPEED_MODE (1<<22)
94 #define I2C_HEADER_CONT_ON_NAK (1<<21) 94 #define I2C_HEADER_CONT_ON_NAK (1<<21)
95 #define I2C_HEADER_SEND_START_BYTE (1<<20) 95 #define I2C_HEADER_SEND_START_BYTE (1<<20)
96 #define I2C_HEADER_READ (1<<19) 96 #define I2C_HEADER_READ (1<<19)
97 #define I2C_HEADER_10BIT_ADDR (1<<18) 97 #define I2C_HEADER_10BIT_ADDR (1<<18)
98 #define I2C_HEADER_IE_ENABLE (1<<17) 98 #define I2C_HEADER_IE_ENABLE (1<<17)
99 #define I2C_HEADER_REPEAT_START (1<<16) 99 #define I2C_HEADER_REPEAT_START (1<<16)
100 #define I2C_HEADER_CONTINUE_XFER (1<<15) 100 #define I2C_HEADER_CONTINUE_XFER (1<<15)
101 #define I2C_HEADER_MASTER_ADDR_SHIFT 12 101 #define I2C_HEADER_MASTER_ADDR_SHIFT 12
102 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 102 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1
103 /* 103 /*
104 * msg_end_type: The bus control which need to be send at end of transfer. 104 * msg_end_type: The bus control which need to be send at end of transfer.
105 * @MSG_END_STOP: Send stop pulse at end of transfer. 105 * @MSG_END_STOP: Send stop pulse at end of transfer.
106 * @MSG_END_REPEAT_START: Send repeat start at end of transfer. 106 * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
107 * @MSG_END_CONTINUE: The following on message is coming and so do not send 107 * @MSG_END_CONTINUE: The following on message is coming and so do not send
108 * stop or repeat start. 108 * stop or repeat start.
109 */ 109 */
110 enum msg_end_type { 110 enum msg_end_type {
111 MSG_END_STOP, 111 MSG_END_STOP,
112 MSG_END_REPEAT_START, 112 MSG_END_REPEAT_START,
113 MSG_END_CONTINUE, 113 MSG_END_CONTINUE,
114 }; 114 };
115 115
116 /** 116 /**
117 * struct tegra_i2c_dev - per device i2c context 117 * struct tegra_i2c_dev - per device i2c context
118 * @dev: device reference for power management 118 * @dev: device reference for power management
119 * @adapter: core i2c layer adapter information 119 * @adapter: core i2c layer adapter information
120 * @clk: clock reference for i2c controller 120 * @clk: clock reference for i2c controller
121 * @i2c_clk: clock reference for i2c bus 121 * @i2c_clk: clock reference for i2c bus
122 * @base: ioremapped registers cookie 122 * @base: ioremapped registers cookie
123 * @cont_id: i2c controller id, used for for packet header 123 * @cont_id: i2c controller id, used for for packet header
124 * @irq: irq number of transfer complete interrupt 124 * @irq: irq number of transfer complete interrupt
125 * @is_dvc: identifies the DVC i2c controller, has a different register layout 125 * @is_dvc: identifies the DVC i2c controller, has a different register layout
126 * @msg_complete: transfer completion notifier 126 * @msg_complete: transfer completion notifier
127 * @msg_err: error code for completed message 127 * @msg_err: error code for completed message
128 * @msg_buf: pointer to current message data 128 * @msg_buf: pointer to current message data
129 * @msg_buf_remaining: size of unsent data in the message buffer 129 * @msg_buf_remaining: size of unsent data in the message buffer
130 * @msg_read: identifies read transfers 130 * @msg_read: identifies read transfers
131 * @bus_clk_rate: current i2c bus clock rate 131 * @bus_clk_rate: current i2c bus clock rate
132 * @is_suspended: prevents i2c controller accesses after suspend is called 132 * @is_suspended: prevents i2c controller accesses after suspend is called
133 */ 133 */
134 struct tegra_i2c_dev { 134 struct tegra_i2c_dev {
135 struct device *dev; 135 struct device *dev;
136 struct i2c_adapter adapter; 136 struct i2c_adapter adapter;
137 struct clk *clk; 137 struct clk *clk;
138 struct clk *i2c_clk; 138 struct clk *i2c_clk;
139 void __iomem *base; 139 void __iomem *base;
140 int cont_id; 140 int cont_id;
141 int irq; 141 int irq;
142 bool irq_disabled; 142 bool irq_disabled;
143 int is_dvc; 143 int is_dvc;
144 struct completion msg_complete; 144 struct completion msg_complete;
145 int msg_err; 145 int msg_err;
146 u8 *msg_buf; 146 u8 *msg_buf;
147 size_t msg_buf_remaining; 147 size_t msg_buf_remaining;
148 int msg_read; 148 int msg_read;
149 unsigned long bus_clk_rate; 149 unsigned long bus_clk_rate;
150 bool is_suspended; 150 bool is_suspended;
151 }; 151 };
152 152
153 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg) 153 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
154 { 154 {
155 writel(val, i2c_dev->base + reg); 155 writel(val, i2c_dev->base + reg);
156 } 156 }
157 157
158 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) 158 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
159 { 159 {
160 return readl(i2c_dev->base + reg); 160 return readl(i2c_dev->base + reg);
161 } 161 }
162 162
163 /* 163 /*
164 * i2c_writel and i2c_readl will offset the register if necessary to talk 164 * i2c_writel and i2c_readl will offset the register if necessary to talk
165 * to the I2C block inside the DVC block 165 * to the I2C block inside the DVC block
166 */ 166 */
167 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, 167 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
168 unsigned long reg) 168 unsigned long reg)
169 { 169 {
170 if (i2c_dev->is_dvc) 170 if (i2c_dev->is_dvc)
171 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40; 171 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
172 return reg; 172 return reg;
173 } 173 }
174 174
175 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, 175 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
176 unsigned long reg) 176 unsigned long reg)
177 { 177 {
178 writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 178 writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
179 179
180 /* Read back register to make sure that register writes completed */ 180 /* Read back register to make sure that register writes completed */
181 if (reg != I2C_TX_FIFO) 181 if (reg != I2C_TX_FIFO)
182 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 182 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
183 } 183 }
184 184
185 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) 185 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
186 { 186 {
187 return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 187 return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
188 } 188 }
189 189
190 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, 190 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
191 unsigned long reg, int len) 191 unsigned long reg, int len)
192 { 192 {
193 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 193 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
194 } 194 }
195 195
196 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, 196 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
197 unsigned long reg, int len) 197 unsigned long reg, int len)
198 { 198 {
199 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 199 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
200 } 200 }
201 201
202 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 202 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
203 { 203 {
204 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK); 204 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
205 int_mask &= ~mask; 205 int_mask &= ~mask;
206 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 206 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
207 } 207 }
208 208
209 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 209 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
210 { 210 {
211 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK); 211 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
212 int_mask |= mask; 212 int_mask |= mask;
213 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 213 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
214 } 214 }
215 215
216 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) 216 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
217 { 217 {
218 unsigned long timeout = jiffies + HZ; 218 unsigned long timeout = jiffies + HZ;
219 u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL); 219 u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
220 val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH; 220 val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
221 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL); 221 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
222 222
223 while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) & 223 while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
224 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) { 224 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
225 if (time_after(jiffies, timeout)) { 225 if (time_after(jiffies, timeout)) {
226 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n"); 226 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
227 return -ETIMEDOUT; 227 return -ETIMEDOUT;
228 } 228 }
229 msleep(1); 229 msleep(1);
230 } 230 }
231 return 0; 231 return 0;
232 } 232 }
233 233
234 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev) 234 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
235 { 235 {
236 u32 val; 236 u32 val;
237 int rx_fifo_avail; 237 int rx_fifo_avail;
238 u8 *buf = i2c_dev->msg_buf; 238 u8 *buf = i2c_dev->msg_buf;
239 size_t buf_remaining = i2c_dev->msg_buf_remaining; 239 size_t buf_remaining = i2c_dev->msg_buf_remaining;
240 int words_to_transfer; 240 int words_to_transfer;
241 241
242 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 242 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
243 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >> 243 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
244 I2C_FIFO_STATUS_RX_SHIFT; 244 I2C_FIFO_STATUS_RX_SHIFT;
245 245
246 /* Rounds down to not include partial word at the end of buf */ 246 /* Rounds down to not include partial word at the end of buf */
247 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 247 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
248 if (words_to_transfer > rx_fifo_avail) 248 if (words_to_transfer > rx_fifo_avail)
249 words_to_transfer = rx_fifo_avail; 249 words_to_transfer = rx_fifo_avail;
250 250
251 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer); 251 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
252 252
253 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 253 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
254 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 254 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
255 rx_fifo_avail -= words_to_transfer; 255 rx_fifo_avail -= words_to_transfer;
256 256
257 /* 257 /*
258 * If there is a partial word at the end of buf, handle it manually to 258 * If there is a partial word at the end of buf, handle it manually to
259 * prevent overwriting past the end of buf 259 * prevent overwriting past the end of buf
260 */ 260 */
261 if (rx_fifo_avail > 0 && buf_remaining > 0) { 261 if (rx_fifo_avail > 0 && buf_remaining > 0) {
262 BUG_ON(buf_remaining > 3); 262 BUG_ON(buf_remaining > 3);
263 val = i2c_readl(i2c_dev, I2C_RX_FIFO); 263 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
264 memcpy(buf, &val, buf_remaining); 264 memcpy(buf, &val, buf_remaining);
265 buf_remaining = 0; 265 buf_remaining = 0;
266 rx_fifo_avail--; 266 rx_fifo_avail--;
267 } 267 }
268 268
269 BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0); 269 BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
270 i2c_dev->msg_buf_remaining = buf_remaining; 270 i2c_dev->msg_buf_remaining = buf_remaining;
271 i2c_dev->msg_buf = buf; 271 i2c_dev->msg_buf = buf;
272 return 0; 272 return 0;
273 } 273 }
274 274
275 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev) 275 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
276 { 276 {
277 u32 val; 277 u32 val;
278 int tx_fifo_avail; 278 int tx_fifo_avail;
279 u8 *buf = i2c_dev->msg_buf; 279 u8 *buf = i2c_dev->msg_buf;
280 size_t buf_remaining = i2c_dev->msg_buf_remaining; 280 size_t buf_remaining = i2c_dev->msg_buf_remaining;
281 int words_to_transfer; 281 int words_to_transfer;
282 282
283 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 283 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
284 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >> 284 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
285 I2C_FIFO_STATUS_TX_SHIFT; 285 I2C_FIFO_STATUS_TX_SHIFT;
286 286
287 /* Rounds down to not include partial word at the end of buf */ 287 /* Rounds down to not include partial word at the end of buf */
288 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 288 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
289 289
290 /* It's very common to have < 4 bytes, so optimize that case. */ 290 /* It's very common to have < 4 bytes, so optimize that case. */
291 if (words_to_transfer) { 291 if (words_to_transfer) {
292 if (words_to_transfer > tx_fifo_avail) 292 if (words_to_transfer > tx_fifo_avail)
293 words_to_transfer = tx_fifo_avail; 293 words_to_transfer = tx_fifo_avail;
294 294
295 /* 295 /*
296 * Update state before writing to FIFO. If this casues us 296 * Update state before writing to FIFO. If this casues us
297 * to finish writing all bytes (AKA buf_remaining goes to 0) we 297 * to finish writing all bytes (AKA buf_remaining goes to 0) we
298 * have a potential for an interrupt (PACKET_XFER_COMPLETE is 298 * have a potential for an interrupt (PACKET_XFER_COMPLETE is
299 * not maskable). We need to make sure that the isr sees 299 * not maskable). We need to make sure that the isr sees
300 * buf_remaining as 0 and doesn't call us back re-entrantly. 300 * buf_remaining as 0 and doesn't call us back re-entrantly.
301 */ 301 */
302 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 302 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
303 tx_fifo_avail -= words_to_transfer; 303 tx_fifo_avail -= words_to_transfer;
304 i2c_dev->msg_buf_remaining = buf_remaining; 304 i2c_dev->msg_buf_remaining = buf_remaining;
305 i2c_dev->msg_buf = buf + 305 i2c_dev->msg_buf = buf +
306 words_to_transfer * BYTES_PER_FIFO_WORD; 306 words_to_transfer * BYTES_PER_FIFO_WORD;
307 barrier(); 307 barrier();
308 308
309 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); 309 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
310 310
311 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 311 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
312 } 312 }
313 313
314 /* 314 /*
315 * If there is a partial word at the end of buf, handle it manually to 315 * If there is a partial word at the end of buf, handle it manually to
316 * prevent reading past the end of buf, which could cross a page 316 * prevent reading past the end of buf, which could cross a page
317 * boundary and fault. 317 * boundary and fault.
318 */ 318 */
319 if (tx_fifo_avail > 0 && buf_remaining > 0) { 319 if (tx_fifo_avail > 0 && buf_remaining > 0) {
320 BUG_ON(buf_remaining > 3); 320 BUG_ON(buf_remaining > 3);
321 memcpy(&val, buf, buf_remaining); 321 memcpy(&val, buf, buf_remaining);
322 322
323 /* Again update before writing to FIFO to make sure isr sees. */ 323 /* Again update before writing to FIFO to make sure isr sees. */
324 i2c_dev->msg_buf_remaining = 0; 324 i2c_dev->msg_buf_remaining = 0;
325 i2c_dev->msg_buf = NULL; 325 i2c_dev->msg_buf = NULL;
326 barrier(); 326 barrier();
327 327
328 i2c_writel(i2c_dev, val, I2C_TX_FIFO); 328 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
329 } 329 }
330 330
331 return 0; 331 return 0;
332 } 332 }
333 333
334 /* 334 /*
335 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller) 335 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
336 * block. This block is identical to the rest of the I2C blocks, except that 336 * block. This block is identical to the rest of the I2C blocks, except that
337 * it only supports master mode, it has registers moved around, and it needs 337 * it only supports master mode, it has registers moved around, and it needs
338 * some extra init to get it into I2C mode. The register moves are handled 338 * some extra init to get it into I2C mode. The register moves are handled
339 * by i2c_readl and i2c_writel 339 * by i2c_readl and i2c_writel
340 */ 340 */
341 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev) 341 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
342 { 342 {
343 u32 val = 0; 343 u32 val = 0;
344 val = dvc_readl(i2c_dev, DVC_CTRL_REG3); 344 val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
345 val |= DVC_CTRL_REG3_SW_PROG; 345 val |= DVC_CTRL_REG3_SW_PROG;
346 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN; 346 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
347 dvc_writel(i2c_dev, val, DVC_CTRL_REG3); 347 dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
348 348
349 val = dvc_readl(i2c_dev, DVC_CTRL_REG1); 349 val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
350 val |= DVC_CTRL_REG1_INTR_EN; 350 val |= DVC_CTRL_REG1_INTR_EN;
351 dvc_writel(i2c_dev, val, DVC_CTRL_REG1); 351 dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
352 } 352 }
353 353
354 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) 354 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
355 { 355 {
356 u32 val; 356 u32 val;
357 int err = 0; 357 int err = 0;
358 358
359 clk_enable(i2c_dev->clk); 359 clk_enable(i2c_dev->clk);
360 360
361 tegra_periph_reset_assert(i2c_dev->clk); 361 tegra_periph_reset_assert(i2c_dev->clk);
362 udelay(2); 362 udelay(2);
363 tegra_periph_reset_deassert(i2c_dev->clk); 363 tegra_periph_reset_deassert(i2c_dev->clk);
364 364
365 if (i2c_dev->is_dvc) 365 if (i2c_dev->is_dvc)
366 tegra_dvc_init(i2c_dev); 366 tegra_dvc_init(i2c_dev);
367 367
368 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | 368 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
369 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT); 369 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
370 i2c_writel(i2c_dev, val, I2C_CNFG); 370 i2c_writel(i2c_dev, val, I2C_CNFG);
371 i2c_writel(i2c_dev, 0, I2C_INT_MASK); 371 i2c_writel(i2c_dev, 0, I2C_INT_MASK);
372 clk_set_rate(i2c_dev->clk, i2c_dev->bus_clk_rate * 8); 372 clk_set_rate(i2c_dev->clk, i2c_dev->bus_clk_rate * 8);
373 373
374 if (!i2c_dev->is_dvc) { 374 if (!i2c_dev->is_dvc) {
375 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG); 375 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
376 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL; 376 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
377 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG); 377 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
378 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1); 378 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
379 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2); 379 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
380 380
381 } 381 }
382 382
383 val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT | 383 val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
384 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT; 384 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
385 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL); 385 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
386 386
387 if (tegra_i2c_flush_fifos(i2c_dev)) 387 if (tegra_i2c_flush_fifos(i2c_dev))
388 err = -ETIMEDOUT; 388 err = -ETIMEDOUT;
389 389
390 clk_disable(i2c_dev->clk); 390 clk_disable(i2c_dev->clk);
391 391
392 if (i2c_dev->irq_disabled) { 392 if (i2c_dev->irq_disabled) {
393 i2c_dev->irq_disabled = 0; 393 i2c_dev->irq_disabled = 0;
394 enable_irq(i2c_dev->irq); 394 enable_irq(i2c_dev->irq);
395 } 395 }
396 396
397 return err; 397 return err;
398 } 398 }
399 399
400 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) 400 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
401 { 401 {
402 u32 status; 402 u32 status;
403 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 403 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
404 struct tegra_i2c_dev *i2c_dev = dev_id; 404 struct tegra_i2c_dev *i2c_dev = dev_id;
405 405
406 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 406 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
407 407
408 if (status == 0) { 408 if (status == 0) {
409 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n", 409 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
410 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), 410 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
411 i2c_readl(i2c_dev, I2C_STATUS), 411 i2c_readl(i2c_dev, I2C_STATUS),
412 i2c_readl(i2c_dev, I2C_CNFG)); 412 i2c_readl(i2c_dev, I2C_CNFG));
413 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 413 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
414 414
415 if (!i2c_dev->irq_disabled) { 415 if (!i2c_dev->irq_disabled) {
416 disable_irq_nosync(i2c_dev->irq); 416 disable_irq_nosync(i2c_dev->irq);
417 i2c_dev->irq_disabled = 1; 417 i2c_dev->irq_disabled = 1;
418 } 418 }
419 goto err; 419 goto err;
420 } 420 }
421 421
422 if (unlikely(status & status_err)) { 422 if (unlikely(status & status_err)) {
423 if (status & I2C_INT_NO_ACK) 423 if (status & I2C_INT_NO_ACK)
424 i2c_dev->msg_err |= I2C_ERR_NO_ACK; 424 i2c_dev->msg_err |= I2C_ERR_NO_ACK;
425 if (status & I2C_INT_ARBITRATION_LOST) 425 if (status & I2C_INT_ARBITRATION_LOST)
426 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; 426 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
427 goto err; 427 goto err;
428 } 428 }
429 429
430 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { 430 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
431 if (i2c_dev->msg_buf_remaining) 431 if (i2c_dev->msg_buf_remaining)
432 tegra_i2c_empty_rx_fifo(i2c_dev); 432 tegra_i2c_empty_rx_fifo(i2c_dev);
433 else 433 else
434 BUG(); 434 BUG();
435 } 435 }
436 436
437 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { 437 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
438 if (i2c_dev->msg_buf_remaining) 438 if (i2c_dev->msg_buf_remaining)
439 tegra_i2c_fill_tx_fifo(i2c_dev); 439 tegra_i2c_fill_tx_fifo(i2c_dev);
440 else 440 else
441 tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ); 441 tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
442 } 442 }
443 443
444 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 444 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
445 if (i2c_dev->is_dvc) 445 if (i2c_dev->is_dvc)
446 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 446 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
447 447
448 if (status & I2C_INT_PACKET_XFER_COMPLETE) { 448 if (status & I2C_INT_PACKET_XFER_COMPLETE) {
449 BUG_ON(i2c_dev->msg_buf_remaining); 449 BUG_ON(i2c_dev->msg_buf_remaining);
450 complete(&i2c_dev->msg_complete); 450 complete(&i2c_dev->msg_complete);
451 } 451 }
452 return IRQ_HANDLED; 452 return IRQ_HANDLED;
453 err: 453 err:
454 /* An error occurred, mask all interrupts */ 454 /* An error occurred, mask all interrupts */
455 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST | 455 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
456 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ | 456 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
457 I2C_INT_RX_FIFO_DATA_REQ); 457 I2C_INT_RX_FIFO_DATA_REQ);
458 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 458 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
459 if (i2c_dev->is_dvc) 459 if (i2c_dev->is_dvc)
460 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 460 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
461 461
462 complete(&i2c_dev->msg_complete); 462 complete(&i2c_dev->msg_complete);
463 return IRQ_HANDLED; 463 return IRQ_HANDLED;
464 } 464 }
465 465
466 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, 466 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
467 struct i2c_msg *msg, enum msg_end_type end_state) 467 struct i2c_msg *msg, enum msg_end_type end_state)
468 { 468 {
469 u32 packet_header; 469 u32 packet_header;
470 u32 int_mask; 470 u32 int_mask;
471 int ret; 471 int ret;
472 472
473 tegra_i2c_flush_fifos(i2c_dev); 473 tegra_i2c_flush_fifos(i2c_dev);
474 474
475 if (msg->len == 0) 475 if (msg->len == 0)
476 return -EINVAL; 476 return -EINVAL;
477 477
478 i2c_dev->msg_buf = msg->buf; 478 i2c_dev->msg_buf = msg->buf;
479 i2c_dev->msg_buf_remaining = msg->len; 479 i2c_dev->msg_buf_remaining = msg->len;
480 i2c_dev->msg_err = I2C_ERR_NONE; 480 i2c_dev->msg_err = I2C_ERR_NONE;
481 i2c_dev->msg_read = (msg->flags & I2C_M_RD); 481 i2c_dev->msg_read = (msg->flags & I2C_M_RD);
482 INIT_COMPLETION(i2c_dev->msg_complete); 482 INIT_COMPLETION(i2c_dev->msg_complete);
483 483
484 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) | 484 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
485 PACKET_HEADER0_PROTOCOL_I2C | 485 PACKET_HEADER0_PROTOCOL_I2C |
486 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) | 486 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
487 (1 << PACKET_HEADER0_PACKET_ID_SHIFT); 487 (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
488 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 488 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
489 489
490 packet_header = msg->len - 1; 490 packet_header = msg->len - 1;
491 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 491 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
492 492
493 packet_header = I2C_HEADER_IE_ENABLE; 493 packet_header = I2C_HEADER_IE_ENABLE;
494 if (end_state == MSG_END_CONTINUE) 494 if (end_state == MSG_END_CONTINUE)
495 packet_header |= I2C_HEADER_CONTINUE_XFER; 495 packet_header |= I2C_HEADER_CONTINUE_XFER;
496 else if (end_state == MSG_END_REPEAT_START) 496 else if (end_state == MSG_END_REPEAT_START)
497 packet_header |= I2C_HEADER_REPEAT_START; 497 packet_header |= I2C_HEADER_REPEAT_START;
498 if (msg->flags & I2C_M_TEN) { 498 if (msg->flags & I2C_M_TEN) {
499 packet_header |= msg->addr; 499 packet_header |= msg->addr;
500 packet_header |= I2C_HEADER_10BIT_ADDR; 500 packet_header |= I2C_HEADER_10BIT_ADDR;
501 } else { 501 } else {
502 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT; 502 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
503 } 503 }
504 if (msg->flags & I2C_M_IGNORE_NAK) 504 if (msg->flags & I2C_M_IGNORE_NAK)
505 packet_header |= I2C_HEADER_CONT_ON_NAK; 505 packet_header |= I2C_HEADER_CONT_ON_NAK;
506 if (msg->flags & I2C_M_RD) 506 if (msg->flags & I2C_M_RD)
507 packet_header |= I2C_HEADER_READ; 507 packet_header |= I2C_HEADER_READ;
508 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 508 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
509 509
510 if (!(msg->flags & I2C_M_RD)) 510 if (!(msg->flags & I2C_M_RD))
511 tegra_i2c_fill_tx_fifo(i2c_dev); 511 tegra_i2c_fill_tx_fifo(i2c_dev);
512 512
513 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 513 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
514 if (msg->flags & I2C_M_RD) 514 if (msg->flags & I2C_M_RD)
515 int_mask |= I2C_INT_RX_FIFO_DATA_REQ; 515 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
516 else if (i2c_dev->msg_buf_remaining) 516 else if (i2c_dev->msg_buf_remaining)
517 int_mask |= I2C_INT_TX_FIFO_DATA_REQ; 517 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
518 tegra_i2c_unmask_irq(i2c_dev, int_mask); 518 tegra_i2c_unmask_irq(i2c_dev, int_mask);
519 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n", 519 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
520 i2c_readl(i2c_dev, I2C_INT_MASK)); 520 i2c_readl(i2c_dev, I2C_INT_MASK));
521 521
522 ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT); 522 ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT);
523 tegra_i2c_mask_irq(i2c_dev, int_mask); 523 tegra_i2c_mask_irq(i2c_dev, int_mask);
524 524
525 if (WARN_ON(ret == 0)) { 525 if (WARN_ON(ret == 0)) {
526 dev_err(i2c_dev->dev, "i2c transfer timed out\n"); 526 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
527 527
528 tegra_i2c_init(i2c_dev); 528 tegra_i2c_init(i2c_dev);
529 return -ETIMEDOUT; 529 return -ETIMEDOUT;
530 } 530 }
531 531
532 dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n", 532 dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n",
533 ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err); 533 ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
534 534
535 if (likely(i2c_dev->msg_err == I2C_ERR_NONE)) 535 if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
536 return 0; 536 return 0;
537 537
538 /* 538 /*
539 * NACK interrupt is generated before the I2C controller generates the 539 * NACK interrupt is generated before the I2C controller generates the
540 * STOP condition on the bus. So wait for 2 clock periods before resetting 540 * STOP condition on the bus. So wait for 2 clock periods before resetting
541 * the controller so that STOP condition has been delivered properly. 541 * the controller so that STOP condition has been delivered properly.
542 */ 542 */
543 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) 543 if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
544 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate)); 544 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
545 545
546 tegra_i2c_init(i2c_dev); 546 tegra_i2c_init(i2c_dev);
547 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { 547 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
548 if (msg->flags & I2C_M_IGNORE_NAK) 548 if (msg->flags & I2C_M_IGNORE_NAK)
549 return 0; 549 return 0;
550 return -EREMOTEIO; 550 return -EREMOTEIO;
551 } 551 }
552 552
553 return -EIO; 553 return -EIO;
554 } 554 }
555 555
556 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], 556 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
557 int num) 557 int num)
558 { 558 {
559 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 559 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
560 int i; 560 int i;
561 int ret = 0; 561 int ret = 0;
562 562
563 if (i2c_dev->is_suspended) 563 if (i2c_dev->is_suspended)
564 return -EBUSY; 564 return -EBUSY;
565 565
566 clk_enable(i2c_dev->clk); 566 clk_enable(i2c_dev->clk);
567 for (i = 0; i < num; i++) { 567 for (i = 0; i < num; i++) {
568 enum msg_end_type end_type = MSG_END_STOP; 568 enum msg_end_type end_type = MSG_END_STOP;
569 if (i < (num - 1)) { 569 if (i < (num - 1)) {
570 if (msgs[i + 1].flags & I2C_M_NOSTART) 570 if (msgs[i + 1].flags & I2C_M_NOSTART)
571 end_type = MSG_END_CONTINUE; 571 end_type = MSG_END_CONTINUE;
572 else 572 else
573 end_type = MSG_END_REPEAT_START; 573 end_type = MSG_END_REPEAT_START;
574 } 574 }
575 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type); 575 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
576 if (ret) 576 if (ret)
577 break; 577 break;
578 } 578 }
579 clk_disable(i2c_dev->clk); 579 clk_disable(i2c_dev->clk);
580 return ret ?: i; 580 return ret ?: i;
581 } 581 }
582 582
583 static u32 tegra_i2c_func(struct i2c_adapter *adap) 583 static u32 tegra_i2c_func(struct i2c_adapter *adap)
584 { 584 {
585 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR | 585 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
586 I2C_FUNC_PROTOCOL_MANGLING | I2C_FUNC_NOSTART; 586 I2C_FUNC_PROTOCOL_MANGLING | I2C_FUNC_NOSTART;
587 } 587 }
588 588
589 static const struct i2c_algorithm tegra_i2c_algo = { 589 static const struct i2c_algorithm tegra_i2c_algo = {
590 .master_xfer = tegra_i2c_xfer, 590 .master_xfer = tegra_i2c_xfer,
591 .functionality = tegra_i2c_func, 591 .functionality = tegra_i2c_func,
592 }; 592 };
593 593
594 static int __devinit tegra_i2c_probe(struct platform_device *pdev) 594 static int __devinit tegra_i2c_probe(struct platform_device *pdev)
595 { 595 {
596 struct tegra_i2c_dev *i2c_dev; 596 struct tegra_i2c_dev *i2c_dev;
597 struct tegra_i2c_platform_data *pdata = pdev->dev.platform_data; 597 struct tegra_i2c_platform_data *pdata = pdev->dev.platform_data;
598 struct resource *res; 598 struct resource *res;
599 struct clk *clk; 599 struct clk *clk;
600 struct clk *i2c_clk; 600 struct clk *i2c_clk;
601 const unsigned int *prop; 601 const unsigned int *prop;
602 void __iomem *base; 602 void __iomem *base;
603 int irq; 603 int irq;
604 int ret = 0; 604 int ret = 0;
605 605
606 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 606 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
607 if (!res) { 607 if (!res) {
608 dev_err(&pdev->dev, "no mem resource\n"); 608 dev_err(&pdev->dev, "no mem resource\n");
609 return -EINVAL; 609 return -EINVAL;
610 } 610 }
611 611
612 base = devm_request_and_ioremap(&pdev->dev, res); 612 base = devm_request_and_ioremap(&pdev->dev, res);
613 if (!base) { 613 if (!base) {
614 dev_err(&pdev->dev, "Cannot request/ioremap I2C registers\n"); 614 dev_err(&pdev->dev, "Cannot request/ioremap I2C registers\n");
615 return -EADDRNOTAVAIL; 615 return -EADDRNOTAVAIL;
616 } 616 }
617 617
618 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 618 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
619 if (!res) { 619 if (!res) {
620 dev_err(&pdev->dev, "no irq resource\n"); 620 dev_err(&pdev->dev, "no irq resource\n");
621 return -EINVAL; 621 return -EINVAL;
622 } 622 }
623 irq = res->start; 623 irq = res->start;
624 624
625 clk = devm_clk_get(&pdev->dev, NULL); 625 clk = devm_clk_get(&pdev->dev, NULL);
626 if (IS_ERR(clk)) { 626 if (IS_ERR(clk)) {
627 dev_err(&pdev->dev, "missing controller clock"); 627 dev_err(&pdev->dev, "missing controller clock");
628 return PTR_ERR(clk); 628 return PTR_ERR(clk);
629 } 629 }
630 630
631 i2c_clk = devm_clk_get(&pdev->dev, "i2c"); 631 i2c_clk = devm_clk_get(&pdev->dev, "i2c");
632 if (IS_ERR(i2c_clk)) { 632 if (IS_ERR(i2c_clk)) {
633 dev_err(&pdev->dev, "missing bus clock"); 633 dev_err(&pdev->dev, "missing bus clock");
634 return PTR_ERR(i2c_clk); 634 return PTR_ERR(i2c_clk);
635 } 635 }
636 636
637 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 637 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
638 if (!i2c_dev) { 638 if (!i2c_dev) {
639 dev_err(&pdev->dev, "Could not allocate struct tegra_i2c_dev"); 639 dev_err(&pdev->dev, "Could not allocate struct tegra_i2c_dev");
640 return -ENOMEM; 640 return -ENOMEM;
641 } 641 }
642 642
643 i2c_dev->base = base; 643 i2c_dev->base = base;
644 i2c_dev->clk = clk; 644 i2c_dev->clk = clk;
645 i2c_dev->i2c_clk = i2c_clk; 645 i2c_dev->i2c_clk = i2c_clk;
646 i2c_dev->adapter.algo = &tegra_i2c_algo; 646 i2c_dev->adapter.algo = &tegra_i2c_algo;
647 i2c_dev->irq = irq; 647 i2c_dev->irq = irq;
648 i2c_dev->cont_id = pdev->id; 648 i2c_dev->cont_id = pdev->id;
649 i2c_dev->dev = &pdev->dev; 649 i2c_dev->dev = &pdev->dev;
650 650
651 i2c_dev->bus_clk_rate = 100000; /* default clock rate */ 651 i2c_dev->bus_clk_rate = 100000; /* default clock rate */
652 if (pdata) { 652 if (pdata) {
653 i2c_dev->bus_clk_rate = pdata->bus_clk_rate; 653 i2c_dev->bus_clk_rate = pdata->bus_clk_rate;
654 654
655 } else if (i2c_dev->dev->of_node) { /* if there is a device tree node ... */ 655 } else if (i2c_dev->dev->of_node) { /* if there is a device tree node ... */
656 prop = of_get_property(i2c_dev->dev->of_node, 656 prop = of_get_property(i2c_dev->dev->of_node,
657 "clock-frequency", NULL); 657 "clock-frequency", NULL);
658 if (prop) 658 if (prop)
659 i2c_dev->bus_clk_rate = be32_to_cpup(prop); 659 i2c_dev->bus_clk_rate = be32_to_cpup(prop);
660 } 660 }
661 661
662 if (pdev->dev.of_node) 662 if (pdev->dev.of_node)
663 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node, 663 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
664 "nvidia,tegra20-i2c-dvc"); 664 "nvidia,tegra20-i2c-dvc");
665 else if (pdev->id == 3) 665 else if (pdev->id == 3)
666 i2c_dev->is_dvc = 1; 666 i2c_dev->is_dvc = 1;
667 init_completion(&i2c_dev->msg_complete); 667 init_completion(&i2c_dev->msg_complete);
668 668
669 platform_set_drvdata(pdev, i2c_dev); 669 platform_set_drvdata(pdev, i2c_dev);
670 670
671 ret = tegra_i2c_init(i2c_dev); 671 ret = tegra_i2c_init(i2c_dev);
672 if (ret) { 672 if (ret) {
673 dev_err(&pdev->dev, "Failed to initialize i2c controller"); 673 dev_err(&pdev->dev, "Failed to initialize i2c controller");
674 return ret; 674 return ret;
675 } 675 }
676 676
677 ret = devm_request_irq(&pdev->dev, i2c_dev->irq, 677 ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
678 tegra_i2c_isr, 0, pdev->name, i2c_dev); 678 tegra_i2c_isr, 0, pdev->name, i2c_dev);
679 if (ret) { 679 if (ret) {
680 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq); 680 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
681 return ret; 681 return ret;
682 } 682 }
683 683
684 clk_enable(i2c_dev->i2c_clk); 684 clk_enable(i2c_dev->i2c_clk);
685 685
686 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); 686 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
687 i2c_dev->adapter.owner = THIS_MODULE; 687 i2c_dev->adapter.owner = THIS_MODULE;
688 i2c_dev->adapter.class = I2C_CLASS_HWMON; 688 i2c_dev->adapter.class = I2C_CLASS_HWMON;
689 strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter", 689 strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
690 sizeof(i2c_dev->adapter.name)); 690 sizeof(i2c_dev->adapter.name));
691 i2c_dev->adapter.algo = &tegra_i2c_algo; 691 i2c_dev->adapter.algo = &tegra_i2c_algo;
692 i2c_dev->adapter.dev.parent = &pdev->dev; 692 i2c_dev->adapter.dev.parent = &pdev->dev;
693 i2c_dev->adapter.nr = pdev->id; 693 i2c_dev->adapter.nr = pdev->id;
694 i2c_dev->adapter.dev.of_node = pdev->dev.of_node; 694 i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
695 695
696 ret = i2c_add_numbered_adapter(&i2c_dev->adapter); 696 ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
697 if (ret) { 697 if (ret) {
698 dev_err(&pdev->dev, "Failed to add I2C adapter\n"); 698 dev_err(&pdev->dev, "Failed to add I2C adapter\n");
699 clk_disable_unprepare(i2c_dev->i2c_clk); 699 clk_disable_unprepare(i2c_dev->i2c_clk);
700 return ret; 700 return ret;
701 } 701 }
702 702
703 of_i2c_register_devices(&i2c_dev->adapter); 703 of_i2c_register_devices(&i2c_dev->adapter);
704 704
705 return 0; 705 return 0;
706 } 706 }
707 707
708 static int __devexit tegra_i2c_remove(struct platform_device *pdev) 708 static int __devexit tegra_i2c_remove(struct platform_device *pdev)
709 { 709 {
710 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 710 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
711 i2c_del_adapter(&i2c_dev->adapter); 711 i2c_del_adapter(&i2c_dev->adapter);
712 return 0; 712 return 0;
713 } 713 }
714 714
715 #ifdef CONFIG_PM 715 #ifdef CONFIG_PM
716 static int tegra_i2c_suspend(struct platform_device *pdev, pm_message_t state) 716 static int tegra_i2c_suspend(struct platform_device *pdev, pm_message_t state)
717 { 717 {
718 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 718 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
719 719
720 i2c_lock_adapter(&i2c_dev->adapter); 720 i2c_lock_adapter(&i2c_dev->adapter);
721 i2c_dev->is_suspended = true; 721 i2c_dev->is_suspended = true;
722 i2c_unlock_adapter(&i2c_dev->adapter); 722 i2c_unlock_adapter(&i2c_dev->adapter);
723 723
724 return 0; 724 return 0;
725 } 725 }
726 726
727 static int tegra_i2c_resume(struct platform_device *pdev) 727 static int tegra_i2c_resume(struct platform_device *pdev)
728 { 728 {
729 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 729 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
730 int ret; 730 int ret;
731 731
732 i2c_lock_adapter(&i2c_dev->adapter); 732 i2c_lock_adapter(&i2c_dev->adapter);
733 733
734 ret = tegra_i2c_init(i2c_dev); 734 ret = tegra_i2c_init(i2c_dev);
735 735
736 if (ret) { 736 if (ret) {
737 i2c_unlock_adapter(&i2c_dev->adapter); 737 i2c_unlock_adapter(&i2c_dev->adapter);
738 return ret; 738 return ret;
739 } 739 }
740 740
741 i2c_dev->is_suspended = false; 741 i2c_dev->is_suspended = false;
742 742
743 i2c_unlock_adapter(&i2c_dev->adapter); 743 i2c_unlock_adapter(&i2c_dev->adapter);
744 744
745 return 0; 745 return 0;
746 } 746 }
747 #endif 747 #endif
748 748
749 #if defined(CONFIG_OF) 749 #if defined(CONFIG_OF)
750 /* Match table for of_platform binding */ 750 /* Match table for of_platform binding */
751 static const struct of_device_id tegra_i2c_of_match[] __devinitconst = { 751 static const struct of_device_id tegra_i2c_of_match[] __devinitconst = {
752 { .compatible = "nvidia,tegra20-i2c", }, 752 { .compatible = "nvidia,tegra20-i2c", },
753 { .compatible = "nvidia,tegra20-i2c-dvc", }, 753 { .compatible = "nvidia,tegra20-i2c-dvc", },
754 {}, 754 {},
755 }; 755 };
756 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match); 756 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
757 #else
758 #define tegra_i2c_of_match NULL
759 #endif 757 #endif
760 758
761 static struct platform_driver tegra_i2c_driver = { 759 static struct platform_driver tegra_i2c_driver = {
762 .probe = tegra_i2c_probe, 760 .probe = tegra_i2c_probe,
763 .remove = __devexit_p(tegra_i2c_remove), 761 .remove = __devexit_p(tegra_i2c_remove),
764 #ifdef CONFIG_PM 762 #ifdef CONFIG_PM
765 .suspend = tegra_i2c_suspend, 763 .suspend = tegra_i2c_suspend,
766 .resume = tegra_i2c_resume, 764 .resume = tegra_i2c_resume,
767 #endif 765 #endif
768 .driver = { 766 .driver = {
769 .name = "tegra-i2c", 767 .name = "tegra-i2c",
770 .owner = THIS_MODULE, 768 .owner = THIS_MODULE,
771 .of_match_table = tegra_i2c_of_match, 769 .of_match_table = of_match_ptr(tegra_i2c_of_match),
772 }, 770 },
773 }; 771 };
774 772
775 static int __init tegra_i2c_init_driver(void) 773 static int __init tegra_i2c_init_driver(void)
776 { 774 {
777 return platform_driver_register(&tegra_i2c_driver); 775 return platform_driver_register(&tegra_i2c_driver);
778 } 776 }
779 777
780 static void __exit tegra_i2c_exit_driver(void) 778 static void __exit tegra_i2c_exit_driver(void)
781 { 779 {
782 platform_driver_unregister(&tegra_i2c_driver); 780 platform_driver_unregister(&tegra_i2c_driver);
783 } 781 }
784 782
785 subsys_initcall(tegra_i2c_init_driver); 783 subsys_initcall(tegra_i2c_init_driver);
786 module_exit(tegra_i2c_exit_driver); 784 module_exit(tegra_i2c_exit_driver);
787 785
788 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver"); 786 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
789 MODULE_AUTHOR("Colin Cross"); 787 MODULE_AUTHOR("Colin Cross");
790 MODULE_LICENSE("GPL v2"); 788 MODULE_LICENSE("GPL v2");
791 789