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Commit 037f4e6b6be47dcfb3f4e78e5c6abe7da92da1dd

Authored by Hans Verkuil
Committed by Mauro Carvalho Chehab
1 parent 8a09a4cc9b
Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch imx_3.14.28_1.0.0_ga

[media] ml86v7667: fix compile warning: 'ret' set but not used 

media_build/v4l/ml86v7667.c: In function 'ml86v7667_s_ctrl':
media_build/v4l/ml86v7667.c:120:6: warning: variable 'ret' set but not used [-Wunused-but-set-variable]
  int ret;
      ^
And indeed, ret is set but not used. Let's actually return the error
code.

Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>

Showing 1 changed file with 2 additions and 2 deletions Inline Diff

drivers/media/i2c/ml86v7667.c
Diff comments   View file @ 037f4e6
1 /* 1 /*
2 * OKI Semiconductor ML86V7667 video decoder driver 2 * OKI Semiconductor ML86V7667 video decoder driver
3 * 3 *
4 * Author: Vladimir Barinov <source@cogentembedded.com> 4 * Author: Vladimir Barinov <source@cogentembedded.com>
5 * Copyright (C) 2013 Cogent Embedded, Inc. 5 * Copyright (C) 2013 Cogent Embedded, Inc.
6 * Copyright (C) 2013 Renesas Solutions Corp. 6 * Copyright (C) 2013 Renesas Solutions Corp.
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify it 8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the 9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your 10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version. 11 * option) any later version.
12 */ 12 */
13 13
14 #include <linux/init.h> 14 #include <linux/init.h>
15 #include <linux/module.h> 15 #include <linux/module.h>
16 #include <linux/i2c.h> 16 #include <linux/i2c.h>
17 #include <linux/slab.h> 17 #include <linux/slab.h>
18 #include <linux/videodev2.h> 18 #include <linux/videodev2.h>
19 #include <media/v4l2-subdev.h> 19 #include <media/v4l2-subdev.h>
20 #include <media/v4l2-device.h> 20 #include <media/v4l2-device.h>
21 #include <media/v4l2-ioctl.h> 21 #include <media/v4l2-ioctl.h>
22 #include <media/v4l2-ctrls.h> 22 #include <media/v4l2-ctrls.h>
23 23
24 #define DRV_NAME "ml86v7667" 24 #define DRV_NAME "ml86v7667"
25 25
26 /* Subaddresses */ 26 /* Subaddresses */
27 #define MRA_REG 0x00 /* Mode Register A */ 27 #define MRA_REG 0x00 /* Mode Register A */
28 #define MRC_REG 0x02 /* Mode Register C */ 28 #define MRC_REG 0x02 /* Mode Register C */
29 #define LUMC_REG 0x0C /* Luminance Control */ 29 #define LUMC_REG 0x0C /* Luminance Control */
30 #define CLC_REG 0x10 /* Contrast level control */ 30 #define CLC_REG 0x10 /* Contrast level control */
31 #define SSEPL_REG 0x11 /* Sync separation level */ 31 #define SSEPL_REG 0x11 /* Sync separation level */
32 #define CHRCA_REG 0x12 /* Chrominance Control A */ 32 #define CHRCA_REG 0x12 /* Chrominance Control A */
33 #define ACCC_REG 0x14 /* ACC Loop filter & Chrominance control */ 33 #define ACCC_REG 0x14 /* ACC Loop filter & Chrominance control */
34 #define ACCRC_REG 0x15 /* ACC Reference level control */ 34 #define ACCRC_REG 0x15 /* ACC Reference level control */
35 #define HUE_REG 0x16 /* Hue control */ 35 #define HUE_REG 0x16 /* Hue control */
36 #define ADC2_REG 0x1F /* ADC Register 2 */ 36 #define ADC2_REG 0x1F /* ADC Register 2 */
37 #define PLLR1_REG 0x20 /* PLL Register 1 */ 37 #define PLLR1_REG 0x20 /* PLL Register 1 */
38 #define STATUS_REG 0x2C /* STATUS Register */ 38 #define STATUS_REG 0x2C /* STATUS Register */
39 39
40 /* Mode Register A register bits */ 40 /* Mode Register A register bits */
41 #define MRA_OUTPUT_MODE_MASK (3 << 6) 41 #define MRA_OUTPUT_MODE_MASK (3 << 6)
42 #define MRA_ITUR_BT601 (1 << 6) 42 #define MRA_ITUR_BT601 (1 << 6)
43 #define MRA_ITUR_BT656 (0 << 6) 43 #define MRA_ITUR_BT656 (0 << 6)
44 #define MRA_INPUT_MODE_MASK (7 << 3) 44 #define MRA_INPUT_MODE_MASK (7 << 3)
45 #define MRA_PAL_BT601 (4 << 3) 45 #define MRA_PAL_BT601 (4 << 3)
46 #define MRA_NTSC_BT601 (0 << 3) 46 #define MRA_NTSC_BT601 (0 << 3)
47 #define MRA_REGISTER_MODE (1 << 0) 47 #define MRA_REGISTER_MODE (1 << 0)
48 48
49 /* Mode Register C register bits */ 49 /* Mode Register C register bits */
50 #define MRC_AUTOSELECT (1 << 7) 50 #define MRC_AUTOSELECT (1 << 7)
51 51
52 /* Luminance Control register bits */ 52 /* Luminance Control register bits */
53 #define LUMC_ONOFF_SHIFT 7 53 #define LUMC_ONOFF_SHIFT 7
54 #define LUMC_ONOFF_MASK (1 << 7) 54 #define LUMC_ONOFF_MASK (1 << 7)
55 55
56 /* Contrast level control register bits */ 56 /* Contrast level control register bits */
57 #define CLC_CONTRAST_ONOFF (1 << 7) 57 #define CLC_CONTRAST_ONOFF (1 << 7)
58 #define CLC_CONTRAST_MASK 0x0F 58 #define CLC_CONTRAST_MASK 0x0F
59 59
60 /* Sync separation level register bits */ 60 /* Sync separation level register bits */
61 #define SSEPL_LUMINANCE_ONOFF (1 << 7) 61 #define SSEPL_LUMINANCE_ONOFF (1 << 7)
62 #define SSEPL_LUMINANCE_MASK 0x7F 62 #define SSEPL_LUMINANCE_MASK 0x7F
63 63
64 /* Chrominance Control A register bits */ 64 /* Chrominance Control A register bits */
65 #define CHRCA_MODE_SHIFT 6 65 #define CHRCA_MODE_SHIFT 6
66 #define CHRCA_MODE_MASK (1 << 6) 66 #define CHRCA_MODE_MASK (1 << 6)
67 67
68 /* ACC Loop filter & Chrominance control register bits */ 68 /* ACC Loop filter & Chrominance control register bits */
69 #define ACCC_CHROMA_CR_SHIFT 3 69 #define ACCC_CHROMA_CR_SHIFT 3
70 #define ACCC_CHROMA_CR_MASK (7 << 3) 70 #define ACCC_CHROMA_CR_MASK (7 << 3)
71 #define ACCC_CHROMA_CB_SHIFT 0 71 #define ACCC_CHROMA_CB_SHIFT 0
72 #define ACCC_CHROMA_CB_MASK (7 << 0) 72 #define ACCC_CHROMA_CB_MASK (7 << 0)
73 73
74 /* ACC Reference level control register bits */ 74 /* ACC Reference level control register bits */
75 #define ACCRC_CHROMA_MASK 0xfc 75 #define ACCRC_CHROMA_MASK 0xfc
76 #define ACCRC_CHROMA_SHIFT 2 76 #define ACCRC_CHROMA_SHIFT 2
77 77
78 /* ADC Register 2 register bits */ 78 /* ADC Register 2 register bits */
79 #define ADC2_CLAMP_VOLTAGE_MASK (7 << 1) 79 #define ADC2_CLAMP_VOLTAGE_MASK (7 << 1)
80 #define ADC2_CLAMP_VOLTAGE(n) ((n & 7) << 1) 80 #define ADC2_CLAMP_VOLTAGE(n) ((n & 7) << 1)
81 81
82 /* PLL Register 1 register bits */ 82 /* PLL Register 1 register bits */
83 #define PLLR1_FIXED_CLOCK (1 << 7) 83 #define PLLR1_FIXED_CLOCK (1 << 7)
84 84
85 /* STATUS Register register bits */ 85 /* STATUS Register register bits */
86 #define STATUS_HLOCK_DETECT (1 << 3) 86 #define STATUS_HLOCK_DETECT (1 << 3)
87 #define STATUS_NTSCPAL (1 << 2) 87 #define STATUS_NTSCPAL (1 << 2)
88 88
89 struct ml86v7667_priv { 89 struct ml86v7667_priv {
90 struct v4l2_subdev sd; 90 struct v4l2_subdev sd;
91 struct v4l2_ctrl_handler hdl; 91 struct v4l2_ctrl_handler hdl;
92 v4l2_std_id std; 92 v4l2_std_id std;
93 }; 93 };
94 94
95 static inline struct ml86v7667_priv *to_ml86v7667(struct v4l2_subdev *subdev) 95 static inline struct ml86v7667_priv *to_ml86v7667(struct v4l2_subdev *subdev)
96 { 96 {
97 return container_of(subdev, struct ml86v7667_priv, sd); 97 return container_of(subdev, struct ml86v7667_priv, sd);
98 } 98 }
99 99
100 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) 100 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
101 { 101 {
102 return &container_of(ctrl->handler, struct ml86v7667_priv, hdl)->sd; 102 return &container_of(ctrl->handler, struct ml86v7667_priv, hdl)->sd;
103 } 103 }
104 104
105 static int ml86v7667_mask_set(struct i2c_client *client, const u8 reg, 105 static int ml86v7667_mask_set(struct i2c_client *client, const u8 reg,
106 const u8 mask, const u8 data) 106 const u8 mask, const u8 data)
107 { 107 {
108 int val = i2c_smbus_read_byte_data(client, reg); 108 int val = i2c_smbus_read_byte_data(client, reg);
109 if (val < 0) 109 if (val < 0)
110 return val; 110 return val;
111 111
112 val = (val & ~mask) | (data & mask); 112 val = (val & ~mask) | (data & mask);
113 return i2c_smbus_write_byte_data(client, reg, val); 113 return i2c_smbus_write_byte_data(client, reg, val);
114 } 114 }
115 115
116 static int ml86v7667_s_ctrl(struct v4l2_ctrl *ctrl) 116 static int ml86v7667_s_ctrl(struct v4l2_ctrl *ctrl)
117 { 117 {
118 struct v4l2_subdev *sd = to_sd(ctrl); 118 struct v4l2_subdev *sd = to_sd(ctrl);
119 struct i2c_client *client = v4l2_get_subdevdata(sd); 119 struct i2c_client *client = v4l2_get_subdevdata(sd);
120 int ret; 120 int ret = -EINVAL;
121 121
122 switch (ctrl->id) { 122 switch (ctrl->id) {
123 case V4L2_CID_BRIGHTNESS: 123 case V4L2_CID_BRIGHTNESS:
124 ret = ml86v7667_mask_set(client, SSEPL_REG, 124 ret = ml86v7667_mask_set(client, SSEPL_REG,
125 SSEPL_LUMINANCE_MASK, ctrl->val); 125 SSEPL_LUMINANCE_MASK, ctrl->val);
126 break; 126 break;
127 case V4L2_CID_CONTRAST: 127 case V4L2_CID_CONTRAST:
128 ret = ml86v7667_mask_set(client, CLC_REG, 128 ret = ml86v7667_mask_set(client, CLC_REG,
129 CLC_CONTRAST_MASK, ctrl->val); 129 CLC_CONTRAST_MASK, ctrl->val);
130 break; 130 break;
131 case V4L2_CID_CHROMA_GAIN: 131 case V4L2_CID_CHROMA_GAIN:
132 ret = ml86v7667_mask_set(client, ACCRC_REG, ACCRC_CHROMA_MASK, 132 ret = ml86v7667_mask_set(client, ACCRC_REG, ACCRC_CHROMA_MASK,
133 ctrl->val << ACCRC_CHROMA_SHIFT); 133 ctrl->val << ACCRC_CHROMA_SHIFT);
134 break; 134 break;
135 case V4L2_CID_HUE: 135 case V4L2_CID_HUE:
136 ret = ml86v7667_mask_set(client, HUE_REG, ~0, ctrl->val); 136 ret = ml86v7667_mask_set(client, HUE_REG, ~0, ctrl->val);
137 break; 137 break;
138 case V4L2_CID_RED_BALANCE: 138 case V4L2_CID_RED_BALANCE:
139 ret = ml86v7667_mask_set(client, ACCC_REG, 139 ret = ml86v7667_mask_set(client, ACCC_REG,
140 ACCC_CHROMA_CR_MASK, 140 ACCC_CHROMA_CR_MASK,
141 ctrl->val << ACCC_CHROMA_CR_SHIFT); 141 ctrl->val << ACCC_CHROMA_CR_SHIFT);
142 break; 142 break;
143 case V4L2_CID_BLUE_BALANCE: 143 case V4L2_CID_BLUE_BALANCE:
144 ret = ml86v7667_mask_set(client, ACCC_REG, 144 ret = ml86v7667_mask_set(client, ACCC_REG,
145 ACCC_CHROMA_CB_MASK, 145 ACCC_CHROMA_CB_MASK,
146 ctrl->val << ACCC_CHROMA_CB_SHIFT); 146 ctrl->val << ACCC_CHROMA_CB_SHIFT);
147 break; 147 break;
148 case V4L2_CID_SHARPNESS: 148 case V4L2_CID_SHARPNESS:
149 ret = ml86v7667_mask_set(client, LUMC_REG, 149 ret = ml86v7667_mask_set(client, LUMC_REG,
150 LUMC_ONOFF_MASK, 150 LUMC_ONOFF_MASK,
151 ctrl->val << LUMC_ONOFF_SHIFT); 151 ctrl->val << LUMC_ONOFF_SHIFT);
152 break; 152 break;
153 case V4L2_CID_COLOR_KILLER: 153 case V4L2_CID_COLOR_KILLER:
154 ret = ml86v7667_mask_set(client, CHRCA_REG, 154 ret = ml86v7667_mask_set(client, CHRCA_REG,
155 CHRCA_MODE_MASK, 155 CHRCA_MODE_MASK,
156 ctrl->val << CHRCA_MODE_SHIFT); 156 ctrl->val << CHRCA_MODE_SHIFT);
157 break; 157 break;
158 } 158 }
159 159
160 return 0; 160 return ret;
161 } 161 }
162 162
163 static int ml86v7667_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) 163 static int ml86v7667_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
164 { 164 {
165 struct i2c_client *client = v4l2_get_subdevdata(sd); 165 struct i2c_client *client = v4l2_get_subdevdata(sd);
166 int status; 166 int status;
167 167
168 status = i2c_smbus_read_byte_data(client, STATUS_REG); 168 status = i2c_smbus_read_byte_data(client, STATUS_REG);
169 if (status < 0) 169 if (status < 0)
170 return status; 170 return status;
171 171
172 if (status & STATUS_HLOCK_DETECT) 172 if (status & STATUS_HLOCK_DETECT)
173 *std &= status & STATUS_NTSCPAL ? V4L2_STD_625_50 : V4L2_STD_525_60; 173 *std &= status & STATUS_NTSCPAL ? V4L2_STD_625_50 : V4L2_STD_525_60;
174 else 174 else
175 *std = V4L2_STD_UNKNOWN; 175 *std = V4L2_STD_UNKNOWN;
176 176
177 return 0; 177 return 0;
178 } 178 }
179 179
180 static int ml86v7667_g_input_status(struct v4l2_subdev *sd, u32 *status) 180 static int ml86v7667_g_input_status(struct v4l2_subdev *sd, u32 *status)
181 { 181 {
182 struct i2c_client *client = v4l2_get_subdevdata(sd); 182 struct i2c_client *client = v4l2_get_subdevdata(sd);
183 int status_reg; 183 int status_reg;
184 184
185 status_reg = i2c_smbus_read_byte_data(client, STATUS_REG); 185 status_reg = i2c_smbus_read_byte_data(client, STATUS_REG);
186 if (status_reg < 0) 186 if (status_reg < 0)
187 return status_reg; 187 return status_reg;
188 188
189 *status = status_reg & STATUS_HLOCK_DETECT ? 0 : V4L2_IN_ST_NO_SIGNAL; 189 *status = status_reg & STATUS_HLOCK_DETECT ? 0 : V4L2_IN_ST_NO_SIGNAL;
190 190
191 return 0; 191 return 0;
192 } 192 }
193 193
194 static int ml86v7667_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index, 194 static int ml86v7667_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
195 enum v4l2_mbus_pixelcode *code) 195 enum v4l2_mbus_pixelcode *code)
196 { 196 {
197 if (index > 0) 197 if (index > 0)
198 return -EINVAL; 198 return -EINVAL;
199 199
200 *code = V4L2_MBUS_FMT_YUYV8_2X8; 200 *code = V4L2_MBUS_FMT_YUYV8_2X8;
201 201
202 return 0; 202 return 0;
203 } 203 }
204 204
205 static int ml86v7667_mbus_fmt(struct v4l2_subdev *sd, 205 static int ml86v7667_mbus_fmt(struct v4l2_subdev *sd,
206 struct v4l2_mbus_framefmt *fmt) 206 struct v4l2_mbus_framefmt *fmt)
207 { 207 {
208 struct ml86v7667_priv *priv = to_ml86v7667(sd); 208 struct ml86v7667_priv *priv = to_ml86v7667(sd);
209 209
210 fmt->code = V4L2_MBUS_FMT_YUYV8_2X8; 210 fmt->code = V4L2_MBUS_FMT_YUYV8_2X8;
211 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M; 211 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
212 /* The top field is always transferred first by the chip */ 212 /* The top field is always transferred first by the chip */
213 fmt->field = V4L2_FIELD_INTERLACED_TB; 213 fmt->field = V4L2_FIELD_INTERLACED_TB;
214 fmt->width = 720; 214 fmt->width = 720;
215 fmt->height = priv->std & V4L2_STD_525_60 ? 480 : 576; 215 fmt->height = priv->std & V4L2_STD_525_60 ? 480 : 576;
216 216
217 return 0; 217 return 0;
218 } 218 }
219 219
220 static int ml86v7667_g_mbus_config(struct v4l2_subdev *sd, 220 static int ml86v7667_g_mbus_config(struct v4l2_subdev *sd,
221 struct v4l2_mbus_config *cfg) 221 struct v4l2_mbus_config *cfg)
222 { 222 {
223 cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING | 223 cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING |
224 V4L2_MBUS_DATA_ACTIVE_HIGH; 224 V4L2_MBUS_DATA_ACTIVE_HIGH;
225 cfg->type = V4L2_MBUS_BT656; 225 cfg->type = V4L2_MBUS_BT656;
226 226
227 return 0; 227 return 0;
228 } 228 }
229 229
230 static int ml86v7667_s_std(struct v4l2_subdev *sd, v4l2_std_id std) 230 static int ml86v7667_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
231 { 231 {
232 struct ml86v7667_priv *priv = to_ml86v7667(sd); 232 struct ml86v7667_priv *priv = to_ml86v7667(sd);
233 struct i2c_client *client = v4l2_get_subdevdata(&priv->sd); 233 struct i2c_client *client = v4l2_get_subdevdata(&priv->sd);
234 int ret; 234 int ret;
235 u8 mode; 235 u8 mode;
236 236
237 /* PAL/NTSC ITU-R BT.601 input mode */ 237 /* PAL/NTSC ITU-R BT.601 input mode */
238 mode = std & V4L2_STD_525_60 ? MRA_NTSC_BT601 : MRA_PAL_BT601; 238 mode = std & V4L2_STD_525_60 ? MRA_NTSC_BT601 : MRA_PAL_BT601;
239 ret = ml86v7667_mask_set(client, MRA_REG, MRA_INPUT_MODE_MASK, mode); 239 ret = ml86v7667_mask_set(client, MRA_REG, MRA_INPUT_MODE_MASK, mode);
240 if (ret < 0) 240 if (ret < 0)
241 return ret; 241 return ret;
242 242
243 priv->std = std; 243 priv->std = std;
244 244
245 return 0; 245 return 0;
246 } 246 }
247 247
248 #ifdef CONFIG_VIDEO_ADV_DEBUG 248 #ifdef CONFIG_VIDEO_ADV_DEBUG
249 static int ml86v7667_g_register(struct v4l2_subdev *sd, 249 static int ml86v7667_g_register(struct v4l2_subdev *sd,
250 struct v4l2_dbg_register *reg) 250 struct v4l2_dbg_register *reg)
251 { 251 {
252 struct i2c_client *client = v4l2_get_subdevdata(sd); 252 struct i2c_client *client = v4l2_get_subdevdata(sd);
253 int ret; 253 int ret;
254 254
255 ret = i2c_smbus_read_byte_data(client, (u8)reg->reg); 255 ret = i2c_smbus_read_byte_data(client, (u8)reg->reg);
256 if (ret < 0) 256 if (ret < 0)
257 return ret; 257 return ret;
258 258
259 reg->val = ret; 259 reg->val = ret;
260 reg->size = sizeof(u8); 260 reg->size = sizeof(u8);
261 261
262 return 0; 262 return 0;
263 } 263 }
264 264
265 static int ml86v7667_s_register(struct v4l2_subdev *sd, 265 static int ml86v7667_s_register(struct v4l2_subdev *sd,
266 const struct v4l2_dbg_register *reg) 266 const struct v4l2_dbg_register *reg)
267 { 267 {
268 struct i2c_client *client = v4l2_get_subdevdata(sd); 268 struct i2c_client *client = v4l2_get_subdevdata(sd);
269 269
270 return i2c_smbus_write_byte_data(client, (u8)reg->reg, (u8)reg->val); 270 return i2c_smbus_write_byte_data(client, (u8)reg->reg, (u8)reg->val);
271 } 271 }
272 #endif 272 #endif
273 273
274 static const struct v4l2_ctrl_ops ml86v7667_ctrl_ops = { 274 static const struct v4l2_ctrl_ops ml86v7667_ctrl_ops = {
275 .s_ctrl = ml86v7667_s_ctrl, 275 .s_ctrl = ml86v7667_s_ctrl,
276 }; 276 };
277 277
278 static struct v4l2_subdev_video_ops ml86v7667_subdev_video_ops = { 278 static struct v4l2_subdev_video_ops ml86v7667_subdev_video_ops = {
279 .querystd = ml86v7667_querystd, 279 .querystd = ml86v7667_querystd,
280 .g_input_status = ml86v7667_g_input_status, 280 .g_input_status = ml86v7667_g_input_status,
281 .enum_mbus_fmt = ml86v7667_enum_mbus_fmt, 281 .enum_mbus_fmt = ml86v7667_enum_mbus_fmt,
282 .try_mbus_fmt = ml86v7667_mbus_fmt, 282 .try_mbus_fmt = ml86v7667_mbus_fmt,
283 .g_mbus_fmt = ml86v7667_mbus_fmt, 283 .g_mbus_fmt = ml86v7667_mbus_fmt,
284 .s_mbus_fmt = ml86v7667_mbus_fmt, 284 .s_mbus_fmt = ml86v7667_mbus_fmt,
285 .g_mbus_config = ml86v7667_g_mbus_config, 285 .g_mbus_config = ml86v7667_g_mbus_config,
286 }; 286 };
287 287
288 static struct v4l2_subdev_core_ops ml86v7667_subdev_core_ops = { 288 static struct v4l2_subdev_core_ops ml86v7667_subdev_core_ops = {
289 .s_std = ml86v7667_s_std, 289 .s_std = ml86v7667_s_std,
290 #ifdef CONFIG_VIDEO_ADV_DEBUG 290 #ifdef CONFIG_VIDEO_ADV_DEBUG
291 .g_register = ml86v7667_g_register, 291 .g_register = ml86v7667_g_register,
292 .s_register = ml86v7667_s_register, 292 .s_register = ml86v7667_s_register,
293 #endif 293 #endif
294 }; 294 };
295 295
296 static struct v4l2_subdev_ops ml86v7667_subdev_ops = { 296 static struct v4l2_subdev_ops ml86v7667_subdev_ops = {
297 .core = &ml86v7667_subdev_core_ops, 297 .core = &ml86v7667_subdev_core_ops,
298 .video = &ml86v7667_subdev_video_ops, 298 .video = &ml86v7667_subdev_video_ops,
299 }; 299 };
300 300
301 static int ml86v7667_init(struct ml86v7667_priv *priv) 301 static int ml86v7667_init(struct ml86v7667_priv *priv)
302 { 302 {
303 struct i2c_client *client = v4l2_get_subdevdata(&priv->sd); 303 struct i2c_client *client = v4l2_get_subdevdata(&priv->sd);
304 int val; 304 int val;
305 int ret; 305 int ret;
306 306
307 /* BT.656-4 output mode, register mode */ 307 /* BT.656-4 output mode, register mode */
308 ret = ml86v7667_mask_set(client, MRA_REG, 308 ret = ml86v7667_mask_set(client, MRA_REG,
309 MRA_OUTPUT_MODE_MASK | MRA_REGISTER_MODE, 309 MRA_OUTPUT_MODE_MASK | MRA_REGISTER_MODE,
310 MRA_ITUR_BT656 | MRA_REGISTER_MODE); 310 MRA_ITUR_BT656 | MRA_REGISTER_MODE);
311 311
312 /* PLL circuit fixed clock, 32MHz */ 312 /* PLL circuit fixed clock, 32MHz */
313 ret |= ml86v7667_mask_set(client, PLLR1_REG, PLLR1_FIXED_CLOCK, 313 ret |= ml86v7667_mask_set(client, PLLR1_REG, PLLR1_FIXED_CLOCK,
314 PLLR1_FIXED_CLOCK); 314 PLLR1_FIXED_CLOCK);
315 315
316 /* ADC2 clamping voltage maximum */ 316 /* ADC2 clamping voltage maximum */
317 ret |= ml86v7667_mask_set(client, ADC2_REG, ADC2_CLAMP_VOLTAGE_MASK, 317 ret |= ml86v7667_mask_set(client, ADC2_REG, ADC2_CLAMP_VOLTAGE_MASK,
318 ADC2_CLAMP_VOLTAGE(7)); 318 ADC2_CLAMP_VOLTAGE(7));
319 319
320 /* enable luminance function */ 320 /* enable luminance function */
321 ret |= ml86v7667_mask_set(client, SSEPL_REG, SSEPL_LUMINANCE_ONOFF, 321 ret |= ml86v7667_mask_set(client, SSEPL_REG, SSEPL_LUMINANCE_ONOFF,
322 SSEPL_LUMINANCE_ONOFF); 322 SSEPL_LUMINANCE_ONOFF);
323 323
324 /* enable contrast function */ 324 /* enable contrast function */
325 ret |= ml86v7667_mask_set(client, CLC_REG, CLC_CONTRAST_ONOFF, 0); 325 ret |= ml86v7667_mask_set(client, CLC_REG, CLC_CONTRAST_ONOFF, 0);
326 326
327 /* 327 /*
328 * PAL/NTSC autodetection is enabled after reset, 328 * PAL/NTSC autodetection is enabled after reset,
329 * set the autodetected std in manual std mode and 329 * set the autodetected std in manual std mode and
330 * disable autodetection 330 * disable autodetection
331 */ 331 */
332 val = i2c_smbus_read_byte_data(client, STATUS_REG); 332 val = i2c_smbus_read_byte_data(client, STATUS_REG);
333 if (val < 0) 333 if (val < 0)
334 return val; 334 return val;
335 335
336 priv->std = val & STATUS_NTSCPAL ? V4L2_STD_625_50 : V4L2_STD_525_60; 336 priv->std = val & STATUS_NTSCPAL ? V4L2_STD_625_50 : V4L2_STD_525_60;
337 ret |= ml86v7667_mask_set(client, MRC_REG, MRC_AUTOSELECT, 0); 337 ret |= ml86v7667_mask_set(client, MRC_REG, MRC_AUTOSELECT, 0);
338 338
339 val = priv->std & V4L2_STD_525_60 ? MRA_NTSC_BT601 : MRA_PAL_BT601; 339 val = priv->std & V4L2_STD_525_60 ? MRA_NTSC_BT601 : MRA_PAL_BT601;
340 ret |= ml86v7667_mask_set(client, MRA_REG, MRA_INPUT_MODE_MASK, val); 340 ret |= ml86v7667_mask_set(client, MRA_REG, MRA_INPUT_MODE_MASK, val);
341 341
342 return ret; 342 return ret;
343 } 343 }
344 344
345 static int ml86v7667_probe(struct i2c_client *client, 345 static int ml86v7667_probe(struct i2c_client *client,
346 const struct i2c_device_id *did) 346 const struct i2c_device_id *did)
347 { 347 {
348 struct ml86v7667_priv *priv; 348 struct ml86v7667_priv *priv;
349 int ret; 349 int ret;
350 350
351 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 351 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
352 return -EIO; 352 return -EIO;
353 353
354 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL); 354 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
355 if (!priv) 355 if (!priv)
356 return -ENOMEM; 356 return -ENOMEM;
357 357
358 v4l2_i2c_subdev_init(&priv->sd, client, &ml86v7667_subdev_ops); 358 v4l2_i2c_subdev_init(&priv->sd, client, &ml86v7667_subdev_ops);
359 359
360 v4l2_ctrl_handler_init(&priv->hdl, 8); 360 v4l2_ctrl_handler_init(&priv->hdl, 8);
361 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops, 361 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
362 V4L2_CID_BRIGHTNESS, -64, 63, 1, 0); 362 V4L2_CID_BRIGHTNESS, -64, 63, 1, 0);
363 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops, 363 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
364 V4L2_CID_CONTRAST, -8, 7, 1, 0); 364 V4L2_CID_CONTRAST, -8, 7, 1, 0);
365 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops, 365 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
366 V4L2_CID_CHROMA_GAIN, -32, 31, 1, 0); 366 V4L2_CID_CHROMA_GAIN, -32, 31, 1, 0);
367 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops, 367 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
368 V4L2_CID_HUE, -128, 127, 1, 0); 368 V4L2_CID_HUE, -128, 127, 1, 0);
369 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops, 369 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
370 V4L2_CID_RED_BALANCE, -4, 3, 1, 0); 370 V4L2_CID_RED_BALANCE, -4, 3, 1, 0);
371 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops, 371 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
372 V4L2_CID_BLUE_BALANCE, -4, 3, 1, 0); 372 V4L2_CID_BLUE_BALANCE, -4, 3, 1, 0);
373 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops, 373 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
374 V4L2_CID_SHARPNESS, 0, 1, 1, 0); 374 V4L2_CID_SHARPNESS, 0, 1, 1, 0);
375 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops, 375 v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
376 V4L2_CID_COLOR_KILLER, 0, 1, 1, 0); 376 V4L2_CID_COLOR_KILLER, 0, 1, 1, 0);
377 priv->sd.ctrl_handler = &priv->hdl; 377 priv->sd.ctrl_handler = &priv->hdl;
378 378
379 ret = priv->hdl.error; 379 ret = priv->hdl.error;
380 if (ret) 380 if (ret)
381 goto cleanup; 381 goto cleanup;
382 382
383 v4l2_ctrl_handler_setup(&priv->hdl); 383 v4l2_ctrl_handler_setup(&priv->hdl);
384 384
385 ret = ml86v7667_init(priv); 385 ret = ml86v7667_init(priv);
386 if (ret) 386 if (ret)
387 goto cleanup; 387 goto cleanup;
388 388
389 v4l_info(client, "chip found @ 0x%02x (%s)\n", 389 v4l_info(client, "chip found @ 0x%02x (%s)\n",
390 client->addr, client->adapter->name); 390 client->addr, client->adapter->name);
391 return 0; 391 return 0;
392 392
393 cleanup: 393 cleanup:
394 v4l2_ctrl_handler_free(&priv->hdl); 394 v4l2_ctrl_handler_free(&priv->hdl);
395 v4l2_device_unregister_subdev(&priv->sd); 395 v4l2_device_unregister_subdev(&priv->sd);
396 v4l_err(client, "failed to probe @ 0x%02x (%s)\n", 396 v4l_err(client, "failed to probe @ 0x%02x (%s)\n",
397 client->addr, client->adapter->name); 397 client->addr, client->adapter->name);
398 return ret; 398 return ret;
399 } 399 }
400 400
401 static int ml86v7667_remove(struct i2c_client *client) 401 static int ml86v7667_remove(struct i2c_client *client)
402 { 402 {
403 struct v4l2_subdev *sd = i2c_get_clientdata(client); 403 struct v4l2_subdev *sd = i2c_get_clientdata(client);
404 struct ml86v7667_priv *priv = to_ml86v7667(sd); 404 struct ml86v7667_priv *priv = to_ml86v7667(sd);
405 405
406 v4l2_ctrl_handler_free(&priv->hdl); 406 v4l2_ctrl_handler_free(&priv->hdl);
407 v4l2_device_unregister_subdev(&priv->sd); 407 v4l2_device_unregister_subdev(&priv->sd);
408 408
409 return 0; 409 return 0;
410 } 410 }
411 411
412 static const struct i2c_device_id ml86v7667_id[] = { 412 static const struct i2c_device_id ml86v7667_id[] = {
413 {DRV_NAME, 0}, 413 {DRV_NAME, 0},
414 {}, 414 {},
415 }; 415 };
416 MODULE_DEVICE_TABLE(i2c, ml86v7667_id); 416 MODULE_DEVICE_TABLE(i2c, ml86v7667_id);
417 417
418 static struct i2c_driver ml86v7667_i2c_driver = { 418 static struct i2c_driver ml86v7667_i2c_driver = {
419 .driver = { 419 .driver = {
420 .name = DRV_NAME, 420 .name = DRV_NAME,
421 .owner = THIS_MODULE, 421 .owner = THIS_MODULE,
422 }, 422 },
423 .probe = ml86v7667_probe, 423 .probe = ml86v7667_probe,
424 .remove = ml86v7667_remove, 424 .remove = ml86v7667_remove,
425 .id_table = ml86v7667_id, 425 .id_table = ml86v7667_id,
426 }; 426 };
427 427
428 module_i2c_driver(ml86v7667_i2c_driver); 428 module_i2c_driver(ml86v7667_i2c_driver);
429 429
430 MODULE_DESCRIPTION("OKI Semiconductor ML86V7667 video decoder driver"); 430 MODULE_DESCRIPTION("OKI Semiconductor ML86V7667 video decoder driver");
431 MODULE_AUTHOR("Vladimir Barinov"); 431 MODULE_AUTHOR("Vladimir Barinov");
432 MODULE_LICENSE("GPL"); 432 MODULE_LICENSE("GPL");
433 433