Doug / smarc-fsl-linux-kernel

Download as
Browse Code ยป

Commit 04d86d6fc0477f217d60667adfc26f1f56264cc9

Authored by Peter Schwenke
Committed by Jeff Garzik
1 parent e9f3340673
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

ata_piix: add more toshiba laptops to broken suspend list 

Add more toshiba laptops to broken suspend list.  This is from OSDL
bugzilla bug 7780.

tj: re-formatted patch and added description and SOB.

Signed-off-by: Peter Schwenke <peter@bluetoad.com.au>
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>

Showing 1 changed file with 28 additions and 0 deletions Inline Diff

drivers/ata/ata_piix.c
Diff comments   View file @ 04d86d6
1 /* 1 /*
2 * ata_piix.c - Intel PATA/SATA controllers 2 * ata_piix.c - Intel PATA/SATA controllers
3 * 3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org 5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails. 6 * on emails.
7 * 7 *
8 * 8 *
9 * Copyright 2003-2005 Red Hat Inc 9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik 10 * Copyright 2003-2005 Jeff Garzik
11 * 11 *
12 * 12 *
13 * Copyright header from piix.c: 13 * Copyright header from piix.c:
14 * 14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer 15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> 16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> 17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 * 18 *
19 * 19 *
20 * This program is free software; you can redistribute it and/or modify 20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by 21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option) 22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version. 23 * any later version.
24 * 24 *
25 * This program is distributed in the hope that it will be useful, 25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of 26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details. 28 * GNU General Public License for more details.
29 * 29 *
30 * You should have received a copy of the GNU General Public License 30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to 31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 * 33 *
34 * 34 *
35 * libata documentation is available via 'make {ps|pdf}docs', 35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.* 36 * as Documentation/DocBook/libata.*
37 * 37 *
38 * Hardware documentation available at http://developer.intel.com/ 38 * Hardware documentation available at http://developer.intel.com/
39 * 39 *
40 * Documentation 40 * Documentation
41 * Publically available from Intel web site. Errata documentation 41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this 42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to 43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find. 44 * PIIX4. Older device documentation is now a bit tricky to find.
45 * 45 *
46 * The chipsets all follow very much the same design. The orginal Triton 46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this 47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then 48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This 49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those 50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix 51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers. 52 * for the early chip drivers.
53 * 53 *
54 * Errata of note: 54 * Errata of note:
55 * 55 *
56 * Unfixable 56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw 57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw 58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel 59 * by Intel
60 * 60 *
61 * Things we must deal with 61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA 62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover) 63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10 64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers 65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer 66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15 67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right 68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21 69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle 70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED] 71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary 72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned 73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 * 75 *
76 * Should have been BIOS fixed: 76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX 77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX 78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX 79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load 80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23) 81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode 82 * ICH3 errata #18 - Don't use native mode
83 */ 83 */
84 84
85 #include <linux/kernel.h> 85 #include <linux/kernel.h>
86 #include <linux/module.h> 86 #include <linux/module.h>
87 #include <linux/pci.h> 87 #include <linux/pci.h>
88 #include <linux/init.h> 88 #include <linux/init.h>
89 #include <linux/blkdev.h> 89 #include <linux/blkdev.h>
90 #include <linux/delay.h> 90 #include <linux/delay.h>
91 #include <linux/device.h> 91 #include <linux/device.h>
92 #include <scsi/scsi_host.h> 92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h> 93 #include <linux/libata.h>
94 #include <linux/dmi.h> 94 #include <linux/dmi.h>
95 95
96 #define DRV_NAME "ata_piix" 96 #define DRV_NAME "ata_piix"
97 #define DRV_VERSION "2.12" 97 #define DRV_VERSION "2.12"
98 98
99 enum { 99 enum {
100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ 100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
101 ICH5_PMR = 0x90, /* port mapping register */ 101 ICH5_PMR = 0x90, /* port mapping register */
102 ICH5_PCS = 0x92, /* port control and status */ 102 ICH5_PCS = 0x92, /* port control and status */
103 PIIX_SCC = 0x0A, /* sub-class code register */ 103 PIIX_SCC = 0x0A, /* sub-class code register */
104 104
105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */ 105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */ 106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ 107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
108 108
109 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS, 109 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
110 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR, 110 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
111 111
112 /* combined mode. if set, PATA is channel 0. 112 /* combined mode. if set, PATA is channel 0.
113 * if clear, PATA is channel 1. 113 * if clear, PATA is channel 1.
114 */ 114 */
115 PIIX_PORT_ENABLED = (1 << 0), 115 PIIX_PORT_ENABLED = (1 << 0),
116 PIIX_PORT_PRESENT = (1 << 4), 116 PIIX_PORT_PRESENT = (1 << 4),
117 117
118 PIIX_80C_PRI = (1 << 5) | (1 << 4), 118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6), 119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
120 120
121 /* controller IDs */ 121 /* controller IDs */
122 piix_pata_mwdma = 0, /* PIIX3 MWDMA only */ 122 piix_pata_mwdma = 0, /* PIIX3 MWDMA only */
123 piix_pata_33, /* PIIX4 at 33Mhz */ 123 piix_pata_33, /* PIIX4 at 33Mhz */
124 ich_pata_33, /* ICH up to UDMA 33 only */ 124 ich_pata_33, /* ICH up to UDMA 33 only */
125 ich_pata_66, /* ICH up to 66 Mhz */ 125 ich_pata_66, /* ICH up to 66 Mhz */
126 ich_pata_100, /* ICH up to UDMA 100 */ 126 ich_pata_100, /* ICH up to UDMA 100 */
127 ich5_sata, 127 ich5_sata,
128 ich6_sata, 128 ich6_sata,
129 ich6_sata_ahci, 129 ich6_sata_ahci,
130 ich6m_sata_ahci, 130 ich6m_sata_ahci,
131 ich8_sata_ahci, 131 ich8_sata_ahci,
132 ich8_2port_sata, 132 ich8_2port_sata,
133 ich8m_apple_sata_ahci, /* locks up on second port enable */ 133 ich8m_apple_sata_ahci, /* locks up on second port enable */
134 tolapai_sata_ahci, 134 tolapai_sata_ahci,
135 135
136 /* constants for mapping table */ 136 /* constants for mapping table */
137 P0 = 0, /* port 0 */ 137 P0 = 0, /* port 0 */
138 P1 = 1, /* port 1 */ 138 P1 = 1, /* port 1 */
139 P2 = 2, /* port 2 */ 139 P2 = 2, /* port 2 */
140 P3 = 3, /* port 3 */ 140 P3 = 3, /* port 3 */
141 IDE = -1, /* IDE */ 141 IDE = -1, /* IDE */
142 NA = -2, /* not avaliable */ 142 NA = -2, /* not avaliable */
143 RV = -3, /* reserved */ 143 RV = -3, /* reserved */
144 144
145 PIIX_AHCI_DEVICE = 6, 145 PIIX_AHCI_DEVICE = 6,
146 146
147 /* host->flags bits */ 147 /* host->flags bits */
148 PIIX_HOST_BROKEN_SUSPEND = (1 << 24), 148 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
149 }; 149 };
150 150
151 struct piix_map_db { 151 struct piix_map_db {
152 const u32 mask; 152 const u32 mask;
153 const u16 port_enable; 153 const u16 port_enable;
154 const int map[][4]; 154 const int map[][4];
155 }; 155 };
156 156
157 struct piix_host_priv { 157 struct piix_host_priv {
158 const int *map; 158 const int *map;
159 }; 159 };
160 160
161 static int piix_init_one(struct pci_dev *pdev, 161 static int piix_init_one(struct pci_dev *pdev,
162 const struct pci_device_id *ent); 162 const struct pci_device_id *ent);
163 static void piix_pata_error_handler(struct ata_port *ap); 163 static void piix_pata_error_handler(struct ata_port *ap);
164 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev); 164 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
165 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev); 165 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
166 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev); 166 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
167 static int ich_pata_cable_detect(struct ata_port *ap); 167 static int ich_pata_cable_detect(struct ata_port *ap);
168 #ifdef CONFIG_PM 168 #ifdef CONFIG_PM
169 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); 169 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
170 static int piix_pci_device_resume(struct pci_dev *pdev); 170 static int piix_pci_device_resume(struct pci_dev *pdev);
171 #endif 171 #endif
172 172
173 static unsigned int in_module_init = 1; 173 static unsigned int in_module_init = 1;
174 174
175 static const struct pci_device_id piix_pci_tbl[] = { 175 static const struct pci_device_id piix_pci_tbl[] = {
176 /* Intel PIIX3 for the 430HX etc */ 176 /* Intel PIIX3 for the 430HX etc */
177 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma }, 177 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
178 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ 178 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
179 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ 179 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
180 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 180 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
181 /* Intel PIIX4 */ 181 /* Intel PIIX4 */
182 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 182 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
183 /* Intel PIIX4 */ 183 /* Intel PIIX4 */
184 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 184 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
185 /* Intel PIIX */ 185 /* Intel PIIX */
186 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 186 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
187 /* Intel ICH (i810, i815, i840) UDMA 66*/ 187 /* Intel ICH (i810, i815, i840) UDMA 66*/
188 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 }, 188 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
189 /* Intel ICH0 : UDMA 33*/ 189 /* Intel ICH0 : UDMA 33*/
190 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 }, 190 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
191 /* Intel ICH2M */ 191 /* Intel ICH2M */
192 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 192 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
193 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */ 193 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
194 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 194 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
195 /* Intel ICH3M */ 195 /* Intel ICH3M */
196 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 196 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
197 /* Intel ICH3 (E7500/1) UDMA 100 */ 197 /* Intel ICH3 (E7500/1) UDMA 100 */
198 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 198 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
199 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */ 199 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
200 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 200 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 201 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
202 /* Intel ICH5 */ 202 /* Intel ICH5 */
203 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 203 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
204 /* C-ICH (i810E2) */ 204 /* C-ICH (i810E2) */
205 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 205 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
206 /* ESB (855GME/875P + 6300ESB) UDMA 100 */ 206 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
207 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 207 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
208 /* ICH6 (and 6) (i915) UDMA 100 */ 208 /* ICH6 (and 6) (i915) UDMA 100 */
209 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 209 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
210 /* ICH7/7-R (i945, i975) UDMA 100*/ 210 /* ICH7/7-R (i945, i975) UDMA 100*/
211 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 211 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
212 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 212 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
213 /* ICH8 Mobile PATA Controller */ 213 /* ICH8 Mobile PATA Controller */
214 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 214 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
215 215
216 /* NOTE: The following PCI ids must be kept in sync with the 216 /* NOTE: The following PCI ids must be kept in sync with the
217 * list in drivers/pci/quirks.c. 217 * list in drivers/pci/quirks.c.
218 */ 218 */
219 219
220 /* 82801EB (ICH5) */ 220 /* 82801EB (ICH5) */
221 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 221 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
222 /* 82801EB (ICH5) */ 222 /* 82801EB (ICH5) */
223 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 223 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
224 /* 6300ESB (ICH5 variant with broken PCS present bits) */ 224 /* 6300ESB (ICH5 variant with broken PCS present bits) */
225 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 225 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
226 /* 6300ESB pretending RAID */ 226 /* 6300ESB pretending RAID */
227 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 227 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
228 /* 82801FB/FW (ICH6/ICH6W) */ 228 /* 82801FB/FW (ICH6/ICH6W) */
229 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 229 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
230 /* 82801FR/FRW (ICH6R/ICH6RW) */ 230 /* 82801FR/FRW (ICH6R/ICH6RW) */
231 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 231 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
232 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */ 232 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
233 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, 233 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
234 /* 82801GB/GR/GH (ICH7, identical to ICH6) */ 234 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
235 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 235 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
236 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ 236 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
237 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, 237 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
238 /* Enterprise Southbridge 2 (631xESB/632xESB) */ 238 /* Enterprise Southbridge 2 (631xESB/632xESB) */
239 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 239 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
240 /* SATA Controller 1 IDE (ICH8) */ 240 /* SATA Controller 1 IDE (ICH8) */
241 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 241 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
242 /* SATA Controller 2 IDE (ICH8) */ 242 /* SATA Controller 2 IDE (ICH8) */
243 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 243 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
244 /* Mobile SATA Controller IDE (ICH8M) */ 244 /* Mobile SATA Controller IDE (ICH8M) */
245 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 245 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
246 /* Mobile SATA Controller IDE (ICH8M), Apple */ 246 /* Mobile SATA Controller IDE (ICH8M), Apple */
247 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata_ahci }, 247 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata_ahci },
248 /* SATA Controller IDE (ICH9) */ 248 /* SATA Controller IDE (ICH9) */
249 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 249 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
250 /* SATA Controller IDE (ICH9) */ 250 /* SATA Controller IDE (ICH9) */
251 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 251 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
252 /* SATA Controller IDE (ICH9) */ 252 /* SATA Controller IDE (ICH9) */
253 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 253 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
254 /* SATA Controller IDE (ICH9M) */ 254 /* SATA Controller IDE (ICH9M) */
255 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 255 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
256 /* SATA Controller IDE (ICH9M) */ 256 /* SATA Controller IDE (ICH9M) */
257 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 257 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
258 /* SATA Controller IDE (ICH9M) */ 258 /* SATA Controller IDE (ICH9M) */
259 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 259 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
260 /* SATA Controller IDE (Tolapai) */ 260 /* SATA Controller IDE (Tolapai) */
261 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci }, 261 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci },
262 262
263 { } /* terminate list */ 263 { } /* terminate list */
264 }; 264 };
265 265
266 static struct pci_driver piix_pci_driver = { 266 static struct pci_driver piix_pci_driver = {
267 .name = DRV_NAME, 267 .name = DRV_NAME,
268 .id_table = piix_pci_tbl, 268 .id_table = piix_pci_tbl,
269 .probe = piix_init_one, 269 .probe = piix_init_one,
270 .remove = ata_pci_remove_one, 270 .remove = ata_pci_remove_one,
271 #ifdef CONFIG_PM 271 #ifdef CONFIG_PM
272 .suspend = piix_pci_device_suspend, 272 .suspend = piix_pci_device_suspend,
273 .resume = piix_pci_device_resume, 273 .resume = piix_pci_device_resume,
274 #endif 274 #endif
275 }; 275 };
276 276
277 static struct scsi_host_template piix_sht = { 277 static struct scsi_host_template piix_sht = {
278 .module = THIS_MODULE, 278 .module = THIS_MODULE,
279 .name = DRV_NAME, 279 .name = DRV_NAME,
280 .ioctl = ata_scsi_ioctl, 280 .ioctl = ata_scsi_ioctl,
281 .queuecommand = ata_scsi_queuecmd, 281 .queuecommand = ata_scsi_queuecmd,
282 .can_queue = ATA_DEF_QUEUE, 282 .can_queue = ATA_DEF_QUEUE,
283 .this_id = ATA_SHT_THIS_ID, 283 .this_id = ATA_SHT_THIS_ID,
284 .sg_tablesize = LIBATA_MAX_PRD, 284 .sg_tablesize = LIBATA_MAX_PRD,
285 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 285 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
286 .emulated = ATA_SHT_EMULATED, 286 .emulated = ATA_SHT_EMULATED,
287 .use_clustering = ATA_SHT_USE_CLUSTERING, 287 .use_clustering = ATA_SHT_USE_CLUSTERING,
288 .proc_name = DRV_NAME, 288 .proc_name = DRV_NAME,
289 .dma_boundary = ATA_DMA_BOUNDARY, 289 .dma_boundary = ATA_DMA_BOUNDARY,
290 .slave_configure = ata_scsi_slave_config, 290 .slave_configure = ata_scsi_slave_config,
291 .slave_destroy = ata_scsi_slave_destroy, 291 .slave_destroy = ata_scsi_slave_destroy,
292 .bios_param = ata_std_bios_param, 292 .bios_param = ata_std_bios_param,
293 }; 293 };
294 294
295 static const struct ata_port_operations piix_pata_ops = { 295 static const struct ata_port_operations piix_pata_ops = {
296 .set_piomode = piix_set_piomode, 296 .set_piomode = piix_set_piomode,
297 .set_dmamode = piix_set_dmamode, 297 .set_dmamode = piix_set_dmamode,
298 .mode_filter = ata_pci_default_filter, 298 .mode_filter = ata_pci_default_filter,
299 299
300 .tf_load = ata_tf_load, 300 .tf_load = ata_tf_load,
301 .tf_read = ata_tf_read, 301 .tf_read = ata_tf_read,
302 .check_status = ata_check_status, 302 .check_status = ata_check_status,
303 .exec_command = ata_exec_command, 303 .exec_command = ata_exec_command,
304 .dev_select = ata_std_dev_select, 304 .dev_select = ata_std_dev_select,
305 305
306 .bmdma_setup = ata_bmdma_setup, 306 .bmdma_setup = ata_bmdma_setup,
307 .bmdma_start = ata_bmdma_start, 307 .bmdma_start = ata_bmdma_start,
308 .bmdma_stop = ata_bmdma_stop, 308 .bmdma_stop = ata_bmdma_stop,
309 .bmdma_status = ata_bmdma_status, 309 .bmdma_status = ata_bmdma_status,
310 .qc_prep = ata_qc_prep, 310 .qc_prep = ata_qc_prep,
311 .qc_issue = ata_qc_issue_prot, 311 .qc_issue = ata_qc_issue_prot,
312 .data_xfer = ata_data_xfer, 312 .data_xfer = ata_data_xfer,
313 313
314 .freeze = ata_bmdma_freeze, 314 .freeze = ata_bmdma_freeze,
315 .thaw = ata_bmdma_thaw, 315 .thaw = ata_bmdma_thaw,
316 .error_handler = piix_pata_error_handler, 316 .error_handler = piix_pata_error_handler,
317 .post_internal_cmd = ata_bmdma_post_internal_cmd, 317 .post_internal_cmd = ata_bmdma_post_internal_cmd,
318 .cable_detect = ata_cable_40wire, 318 .cable_detect = ata_cable_40wire,
319 319
320 .irq_handler = ata_interrupt, 320 .irq_handler = ata_interrupt,
321 .irq_clear = ata_bmdma_irq_clear, 321 .irq_clear = ata_bmdma_irq_clear,
322 .irq_on = ata_irq_on, 322 .irq_on = ata_irq_on,
323 323
324 .port_start = ata_port_start, 324 .port_start = ata_port_start,
325 }; 325 };
326 326
327 static const struct ata_port_operations ich_pata_ops = { 327 static const struct ata_port_operations ich_pata_ops = {
328 .set_piomode = piix_set_piomode, 328 .set_piomode = piix_set_piomode,
329 .set_dmamode = ich_set_dmamode, 329 .set_dmamode = ich_set_dmamode,
330 .mode_filter = ata_pci_default_filter, 330 .mode_filter = ata_pci_default_filter,
331 331
332 .tf_load = ata_tf_load, 332 .tf_load = ata_tf_load,
333 .tf_read = ata_tf_read, 333 .tf_read = ata_tf_read,
334 .check_status = ata_check_status, 334 .check_status = ata_check_status,
335 .exec_command = ata_exec_command, 335 .exec_command = ata_exec_command,
336 .dev_select = ata_std_dev_select, 336 .dev_select = ata_std_dev_select,
337 337
338 .bmdma_setup = ata_bmdma_setup, 338 .bmdma_setup = ata_bmdma_setup,
339 .bmdma_start = ata_bmdma_start, 339 .bmdma_start = ata_bmdma_start,
340 .bmdma_stop = ata_bmdma_stop, 340 .bmdma_stop = ata_bmdma_stop,
341 .bmdma_status = ata_bmdma_status, 341 .bmdma_status = ata_bmdma_status,
342 .qc_prep = ata_qc_prep, 342 .qc_prep = ata_qc_prep,
343 .qc_issue = ata_qc_issue_prot, 343 .qc_issue = ata_qc_issue_prot,
344 .data_xfer = ata_data_xfer, 344 .data_xfer = ata_data_xfer,
345 345
346 .freeze = ata_bmdma_freeze, 346 .freeze = ata_bmdma_freeze,
347 .thaw = ata_bmdma_thaw, 347 .thaw = ata_bmdma_thaw,
348 .error_handler = piix_pata_error_handler, 348 .error_handler = piix_pata_error_handler,
349 .post_internal_cmd = ata_bmdma_post_internal_cmd, 349 .post_internal_cmd = ata_bmdma_post_internal_cmd,
350 .cable_detect = ich_pata_cable_detect, 350 .cable_detect = ich_pata_cable_detect,
351 351
352 .irq_handler = ata_interrupt, 352 .irq_handler = ata_interrupt,
353 .irq_clear = ata_bmdma_irq_clear, 353 .irq_clear = ata_bmdma_irq_clear,
354 .irq_on = ata_irq_on, 354 .irq_on = ata_irq_on,
355 355
356 .port_start = ata_port_start, 356 .port_start = ata_port_start,
357 }; 357 };
358 358
359 static const struct ata_port_operations piix_sata_ops = { 359 static const struct ata_port_operations piix_sata_ops = {
360 .tf_load = ata_tf_load, 360 .tf_load = ata_tf_load,
361 .tf_read = ata_tf_read, 361 .tf_read = ata_tf_read,
362 .check_status = ata_check_status, 362 .check_status = ata_check_status,
363 .exec_command = ata_exec_command, 363 .exec_command = ata_exec_command,
364 .dev_select = ata_std_dev_select, 364 .dev_select = ata_std_dev_select,
365 365
366 .bmdma_setup = ata_bmdma_setup, 366 .bmdma_setup = ata_bmdma_setup,
367 .bmdma_start = ata_bmdma_start, 367 .bmdma_start = ata_bmdma_start,
368 .bmdma_stop = ata_bmdma_stop, 368 .bmdma_stop = ata_bmdma_stop,
369 .bmdma_status = ata_bmdma_status, 369 .bmdma_status = ata_bmdma_status,
370 .qc_prep = ata_qc_prep, 370 .qc_prep = ata_qc_prep,
371 .qc_issue = ata_qc_issue_prot, 371 .qc_issue = ata_qc_issue_prot,
372 .data_xfer = ata_data_xfer, 372 .data_xfer = ata_data_xfer,
373 373
374 .freeze = ata_bmdma_freeze, 374 .freeze = ata_bmdma_freeze,
375 .thaw = ata_bmdma_thaw, 375 .thaw = ata_bmdma_thaw,
376 .error_handler = ata_bmdma_error_handler, 376 .error_handler = ata_bmdma_error_handler,
377 .post_internal_cmd = ata_bmdma_post_internal_cmd, 377 .post_internal_cmd = ata_bmdma_post_internal_cmd,
378 378
379 .irq_handler = ata_interrupt, 379 .irq_handler = ata_interrupt,
380 .irq_clear = ata_bmdma_irq_clear, 380 .irq_clear = ata_bmdma_irq_clear,
381 .irq_on = ata_irq_on, 381 .irq_on = ata_irq_on,
382 382
383 .port_start = ata_port_start, 383 .port_start = ata_port_start,
384 }; 384 };
385 385
386 static const struct piix_map_db ich5_map_db = { 386 static const struct piix_map_db ich5_map_db = {
387 .mask = 0x7, 387 .mask = 0x7,
388 .port_enable = 0x3, 388 .port_enable = 0x3,
389 .map = { 389 .map = {
390 /* PM PS SM SS MAP */ 390 /* PM PS SM SS MAP */
391 { P0, NA, P1, NA }, /* 000b */ 391 { P0, NA, P1, NA }, /* 000b */
392 { P1, NA, P0, NA }, /* 001b */ 392 { P1, NA, P0, NA }, /* 001b */
393 { RV, RV, RV, RV }, 393 { RV, RV, RV, RV },
394 { RV, RV, RV, RV }, 394 { RV, RV, RV, RV },
395 { P0, P1, IDE, IDE }, /* 100b */ 395 { P0, P1, IDE, IDE }, /* 100b */
396 { P1, P0, IDE, IDE }, /* 101b */ 396 { P1, P0, IDE, IDE }, /* 101b */
397 { IDE, IDE, P0, P1 }, /* 110b */ 397 { IDE, IDE, P0, P1 }, /* 110b */
398 { IDE, IDE, P1, P0 }, /* 111b */ 398 { IDE, IDE, P1, P0 }, /* 111b */
399 }, 399 },
400 }; 400 };
401 401
402 static const struct piix_map_db ich6_map_db = { 402 static const struct piix_map_db ich6_map_db = {
403 .mask = 0x3, 403 .mask = 0x3,
404 .port_enable = 0xf, 404 .port_enable = 0xf,
405 .map = { 405 .map = {
406 /* PM PS SM SS MAP */ 406 /* PM PS SM SS MAP */
407 { P0, P2, P1, P3 }, /* 00b */ 407 { P0, P2, P1, P3 }, /* 00b */
408 { IDE, IDE, P1, P3 }, /* 01b */ 408 { IDE, IDE, P1, P3 }, /* 01b */
409 { P0, P2, IDE, IDE }, /* 10b */ 409 { P0, P2, IDE, IDE }, /* 10b */
410 { RV, RV, RV, RV }, 410 { RV, RV, RV, RV },
411 }, 411 },
412 }; 412 };
413 413
414 static const struct piix_map_db ich6m_map_db = { 414 static const struct piix_map_db ich6m_map_db = {
415 .mask = 0x3, 415 .mask = 0x3,
416 .port_enable = 0x5, 416 .port_enable = 0x5,
417 417
418 /* Map 01b isn't specified in the doc but some notebooks use 418 /* Map 01b isn't specified in the doc but some notebooks use
419 * it anyway. MAP 01b have been spotted on both ICH6M and 419 * it anyway. MAP 01b have been spotted on both ICH6M and
420 * ICH7M. 420 * ICH7M.
421 */ 421 */
422 .map = { 422 .map = {
423 /* PM PS SM SS MAP */ 423 /* PM PS SM SS MAP */
424 { P0, P2, NA, NA }, /* 00b */ 424 { P0, P2, NA, NA }, /* 00b */
425 { IDE, IDE, P1, P3 }, /* 01b */ 425 { IDE, IDE, P1, P3 }, /* 01b */
426 { P0, P2, IDE, IDE }, /* 10b */ 426 { P0, P2, IDE, IDE }, /* 10b */
427 { RV, RV, RV, RV }, 427 { RV, RV, RV, RV },
428 }, 428 },
429 }; 429 };
430 430
431 static const struct piix_map_db ich8_map_db = { 431 static const struct piix_map_db ich8_map_db = {
432 .mask = 0x3, 432 .mask = 0x3,
433 .port_enable = 0xf, 433 .port_enable = 0xf,
434 .map = { 434 .map = {
435 /* PM PS SM SS MAP */ 435 /* PM PS SM SS MAP */
436 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ 436 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
437 { RV, RV, RV, RV }, 437 { RV, RV, RV, RV },
438 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */ 438 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
439 { RV, RV, RV, RV }, 439 { RV, RV, RV, RV },
440 }, 440 },
441 }; 441 };
442 442
443 static const struct piix_map_db ich8_2port_map_db = { 443 static const struct piix_map_db ich8_2port_map_db = {
444 .mask = 0x3, 444 .mask = 0x3,
445 .port_enable = 0x3, 445 .port_enable = 0x3,
446 .map = { 446 .map = {
447 /* PM PS SM SS MAP */ 447 /* PM PS SM SS MAP */
448 { P0, NA, P1, NA }, /* 00b */ 448 { P0, NA, P1, NA }, /* 00b */
449 { RV, RV, RV, RV }, /* 01b */ 449 { RV, RV, RV, RV }, /* 01b */
450 { RV, RV, RV, RV }, /* 10b */ 450 { RV, RV, RV, RV }, /* 10b */
451 { RV, RV, RV, RV }, 451 { RV, RV, RV, RV },
452 }, 452 },
453 }; 453 };
454 454
455 static const struct piix_map_db ich8m_apple_map_db = { 455 static const struct piix_map_db ich8m_apple_map_db = {
456 .mask = 0x3, 456 .mask = 0x3,
457 .port_enable = 0x1, 457 .port_enable = 0x1,
458 .map = { 458 .map = {
459 /* PM PS SM SS MAP */ 459 /* PM PS SM SS MAP */
460 { P0, NA, NA, NA }, /* 00b */ 460 { P0, NA, NA, NA }, /* 00b */
461 { RV, RV, RV, RV }, 461 { RV, RV, RV, RV },
462 { P0, P2, IDE, IDE }, /* 10b */ 462 { P0, P2, IDE, IDE }, /* 10b */
463 { RV, RV, RV, RV }, 463 { RV, RV, RV, RV },
464 }, 464 },
465 }; 465 };
466 466
467 static const struct piix_map_db tolapai_map_db = { 467 static const struct piix_map_db tolapai_map_db = {
468 .mask = 0x3, 468 .mask = 0x3,
469 .port_enable = 0x3, 469 .port_enable = 0x3,
470 .map = { 470 .map = {
471 /* PM PS SM SS MAP */ 471 /* PM PS SM SS MAP */
472 { P0, NA, P1, NA }, /* 00b */ 472 { P0, NA, P1, NA }, /* 00b */
473 { RV, RV, RV, RV }, /* 01b */ 473 { RV, RV, RV, RV }, /* 01b */
474 { RV, RV, RV, RV }, /* 10b */ 474 { RV, RV, RV, RV }, /* 10b */
475 { RV, RV, RV, RV }, 475 { RV, RV, RV, RV },
476 }, 476 },
477 }; 477 };
478 478
479 static const struct piix_map_db *piix_map_db_table[] = { 479 static const struct piix_map_db *piix_map_db_table[] = {
480 [ich5_sata] = &ich5_map_db, 480 [ich5_sata] = &ich5_map_db,
481 [ich6_sata] = &ich6_map_db, 481 [ich6_sata] = &ich6_map_db,
482 [ich6_sata_ahci] = &ich6_map_db, 482 [ich6_sata_ahci] = &ich6_map_db,
483 [ich6m_sata_ahci] = &ich6m_map_db, 483 [ich6m_sata_ahci] = &ich6m_map_db,
484 [ich8_sata_ahci] = &ich8_map_db, 484 [ich8_sata_ahci] = &ich8_map_db,
485 [ich8_2port_sata] = &ich8_2port_map_db, 485 [ich8_2port_sata] = &ich8_2port_map_db,
486 [ich8m_apple_sata_ahci] = &ich8m_apple_map_db, 486 [ich8m_apple_sata_ahci] = &ich8m_apple_map_db,
487 [tolapai_sata_ahci] = &tolapai_map_db, 487 [tolapai_sata_ahci] = &tolapai_map_db,
488 }; 488 };
489 489
490 static struct ata_port_info piix_port_info[] = { 490 static struct ata_port_info piix_port_info[] = {
491 [piix_pata_mwdma] = /* PIIX3 MWDMA only */ 491 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
492 { 492 {
493 .sht = &piix_sht, 493 .sht = &piix_sht,
494 .flags = PIIX_PATA_FLAGS, 494 .flags = PIIX_PATA_FLAGS,
495 .pio_mask = 0x1f, /* pio0-4 */ 495 .pio_mask = 0x1f, /* pio0-4 */
496 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 496 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
497 .port_ops = &piix_pata_ops, 497 .port_ops = &piix_pata_ops,
498 }, 498 },
499 499
500 [piix_pata_33] = /* PIIX4 at 33MHz */ 500 [piix_pata_33] = /* PIIX4 at 33MHz */
501 { 501 {
502 .sht = &piix_sht, 502 .sht = &piix_sht,
503 .flags = PIIX_PATA_FLAGS, 503 .flags = PIIX_PATA_FLAGS,
504 .pio_mask = 0x1f, /* pio0-4 */ 504 .pio_mask = 0x1f, /* pio0-4 */
505 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 505 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
506 .udma_mask = ATA_UDMA_MASK_40C, 506 .udma_mask = ATA_UDMA_MASK_40C,
507 .port_ops = &piix_pata_ops, 507 .port_ops = &piix_pata_ops,
508 }, 508 },
509 509
510 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/ 510 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
511 { 511 {
512 .sht = &piix_sht, 512 .sht = &piix_sht,
513 .flags = PIIX_PATA_FLAGS, 513 .flags = PIIX_PATA_FLAGS,
514 .pio_mask = 0x1f, /* pio 0-4 */ 514 .pio_mask = 0x1f, /* pio 0-4 */
515 .mwdma_mask = 0x06, /* Check: maybe 0x07 */ 515 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
516 .udma_mask = ATA_UDMA2, /* UDMA33 */ 516 .udma_mask = ATA_UDMA2, /* UDMA33 */
517 .port_ops = &ich_pata_ops, 517 .port_ops = &ich_pata_ops,
518 }, 518 },
519 519
520 [ich_pata_66] = /* ICH controllers up to 66MHz */ 520 [ich_pata_66] = /* ICH controllers up to 66MHz */
521 { 521 {
522 .sht = &piix_sht, 522 .sht = &piix_sht,
523 .flags = PIIX_PATA_FLAGS, 523 .flags = PIIX_PATA_FLAGS,
524 .pio_mask = 0x1f, /* pio 0-4 */ 524 .pio_mask = 0x1f, /* pio 0-4 */
525 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */ 525 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
526 .udma_mask = ATA_UDMA4, 526 .udma_mask = ATA_UDMA4,
527 .port_ops = &ich_pata_ops, 527 .port_ops = &ich_pata_ops,
528 }, 528 },
529 529
530 [ich_pata_100] = 530 [ich_pata_100] =
531 { 531 {
532 .sht = &piix_sht, 532 .sht = &piix_sht,
533 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, 533 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
534 .pio_mask = 0x1f, /* pio0-4 */ 534 .pio_mask = 0x1f, /* pio0-4 */
535 .mwdma_mask = 0x06, /* mwdma1-2 */ 535 .mwdma_mask = 0x06, /* mwdma1-2 */
536 .udma_mask = ATA_UDMA5, /* udma0-5 */ 536 .udma_mask = ATA_UDMA5, /* udma0-5 */
537 .port_ops = &ich_pata_ops, 537 .port_ops = &ich_pata_ops,
538 }, 538 },
539 539
540 [ich5_sata] = 540 [ich5_sata] =
541 { 541 {
542 .sht = &piix_sht, 542 .sht = &piix_sht,
543 .flags = PIIX_SATA_FLAGS, 543 .flags = PIIX_SATA_FLAGS,
544 .pio_mask = 0x1f, /* pio0-4 */ 544 .pio_mask = 0x1f, /* pio0-4 */
545 .mwdma_mask = 0x07, /* mwdma0-2 */ 545 .mwdma_mask = 0x07, /* mwdma0-2 */
546 .udma_mask = ATA_UDMA6, 546 .udma_mask = ATA_UDMA6,
547 .port_ops = &piix_sata_ops, 547 .port_ops = &piix_sata_ops,
548 }, 548 },
549 549
550 [ich6_sata] = 550 [ich6_sata] =
551 { 551 {
552 .sht = &piix_sht, 552 .sht = &piix_sht,
553 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR, 553 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR,
554 .pio_mask = 0x1f, /* pio0-4 */ 554 .pio_mask = 0x1f, /* pio0-4 */
555 .mwdma_mask = 0x07, /* mwdma0-2 */ 555 .mwdma_mask = 0x07, /* mwdma0-2 */
556 .udma_mask = ATA_UDMA6, 556 .udma_mask = ATA_UDMA6,
557 .port_ops = &piix_sata_ops, 557 .port_ops = &piix_sata_ops,
558 }, 558 },
559 559
560 [ich6_sata_ahci] = 560 [ich6_sata_ahci] =
561 { 561 {
562 .sht = &piix_sht, 562 .sht = &piix_sht,
563 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | 563 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
564 PIIX_FLAG_AHCI, 564 PIIX_FLAG_AHCI,
565 .pio_mask = 0x1f, /* pio0-4 */ 565 .pio_mask = 0x1f, /* pio0-4 */
566 .mwdma_mask = 0x07, /* mwdma0-2 */ 566 .mwdma_mask = 0x07, /* mwdma0-2 */
567 .udma_mask = ATA_UDMA6, 567 .udma_mask = ATA_UDMA6,
568 .port_ops = &piix_sata_ops, 568 .port_ops = &piix_sata_ops,
569 }, 569 },
570 570
571 [ich6m_sata_ahci] = 571 [ich6m_sata_ahci] =
572 { 572 {
573 .sht = &piix_sht, 573 .sht = &piix_sht,
574 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | 574 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
575 PIIX_FLAG_AHCI, 575 PIIX_FLAG_AHCI,
576 .pio_mask = 0x1f, /* pio0-4 */ 576 .pio_mask = 0x1f, /* pio0-4 */
577 .mwdma_mask = 0x07, /* mwdma0-2 */ 577 .mwdma_mask = 0x07, /* mwdma0-2 */
578 .udma_mask = ATA_UDMA6, 578 .udma_mask = ATA_UDMA6,
579 .port_ops = &piix_sata_ops, 579 .port_ops = &piix_sata_ops,
580 }, 580 },
581 581
582 [ich8_sata_ahci] = 582 [ich8_sata_ahci] =
583 { 583 {
584 .sht = &piix_sht, 584 .sht = &piix_sht,
585 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | 585 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
586 PIIX_FLAG_AHCI, 586 PIIX_FLAG_AHCI,
587 .pio_mask = 0x1f, /* pio0-4 */ 587 .pio_mask = 0x1f, /* pio0-4 */
588 .mwdma_mask = 0x07, /* mwdma0-2 */ 588 .mwdma_mask = 0x07, /* mwdma0-2 */
589 .udma_mask = ATA_UDMA6, 589 .udma_mask = ATA_UDMA6,
590 .port_ops = &piix_sata_ops, 590 .port_ops = &piix_sata_ops,
591 }, 591 },
592 592
593 [ich8_2port_sata] = 593 [ich8_2port_sata] =
594 { 594 {
595 .sht = &piix_sht, 595 .sht = &piix_sht,
596 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | 596 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
597 PIIX_FLAG_AHCI, 597 PIIX_FLAG_AHCI,
598 .pio_mask = 0x1f, /* pio0-4 */ 598 .pio_mask = 0x1f, /* pio0-4 */
599 .mwdma_mask = 0x07, /* mwdma0-2 */ 599 .mwdma_mask = 0x07, /* mwdma0-2 */
600 .udma_mask = ATA_UDMA6, 600 .udma_mask = ATA_UDMA6,
601 .port_ops = &piix_sata_ops, 601 .port_ops = &piix_sata_ops,
602 }, 602 },
603 603
604 [tolapai_sata_ahci] = 604 [tolapai_sata_ahci] =
605 { 605 {
606 .sht = &piix_sht, 606 .sht = &piix_sht,
607 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | 607 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
608 PIIX_FLAG_AHCI, 608 PIIX_FLAG_AHCI,
609 .pio_mask = 0x1f, /* pio0-4 */ 609 .pio_mask = 0x1f, /* pio0-4 */
610 .mwdma_mask = 0x07, /* mwdma0-2 */ 610 .mwdma_mask = 0x07, /* mwdma0-2 */
611 .udma_mask = ATA_UDMA6, 611 .udma_mask = ATA_UDMA6,
612 .port_ops = &piix_sata_ops, 612 .port_ops = &piix_sata_ops,
613 }, 613 },
614 614
615 [ich8m_apple_sata_ahci] = 615 [ich8m_apple_sata_ahci] =
616 { 616 {
617 .sht = &piix_sht, 617 .sht = &piix_sht,
618 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | 618 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
619 PIIX_FLAG_AHCI, 619 PIIX_FLAG_AHCI,
620 .pio_mask = 0x1f, /* pio0-4 */ 620 .pio_mask = 0x1f, /* pio0-4 */
621 .mwdma_mask = 0x07, /* mwdma0-2 */ 621 .mwdma_mask = 0x07, /* mwdma0-2 */
622 .udma_mask = ATA_UDMA6, 622 .udma_mask = ATA_UDMA6,
623 .port_ops = &piix_sata_ops, 623 .port_ops = &piix_sata_ops,
624 }, 624 },
625 625
626 }; 626 };
627 627
628 static struct pci_bits piix_enable_bits[] = { 628 static struct pci_bits piix_enable_bits[] = {
629 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ 629 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
630 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ 630 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
631 }; 631 };
632 632
633 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); 633 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
634 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); 634 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
635 MODULE_LICENSE("GPL"); 635 MODULE_LICENSE("GPL");
636 MODULE_DEVICE_TABLE(pci, piix_pci_tbl); 636 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
637 MODULE_VERSION(DRV_VERSION); 637 MODULE_VERSION(DRV_VERSION);
638 638
639 struct ich_laptop { 639 struct ich_laptop {
640 u16 device; 640 u16 device;
641 u16 subvendor; 641 u16 subvendor;
642 u16 subdevice; 642 u16 subdevice;
643 }; 643 };
644 644
645 /* 645 /*
646 * List of laptops that use short cables rather than 80 wire 646 * List of laptops that use short cables rather than 80 wire
647 */ 647 */
648 648
649 static const struct ich_laptop ich_laptop[] = { 649 static const struct ich_laptop ich_laptop[] = {
650 /* devid, subvendor, subdev */ 650 /* devid, subvendor, subdev */
651 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ 651 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
652 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */ 652 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
653 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */ 653 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
654 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ 654 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
655 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */ 655 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
656 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */ 656 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
657 /* end marker */ 657 /* end marker */
658 { 0, } 658 { 0, }
659 }; 659 };
660 660
661 /** 661 /**
662 * ich_pata_cable_detect - Probe host controller cable detect info 662 * ich_pata_cable_detect - Probe host controller cable detect info
663 * @ap: Port for which cable detect info is desired 663 * @ap: Port for which cable detect info is desired
664 * 664 *
665 * Read 80c cable indicator from ATA PCI device's PCI config 665 * Read 80c cable indicator from ATA PCI device's PCI config
666 * register. This register is normally set by firmware (BIOS). 666 * register. This register is normally set by firmware (BIOS).
667 * 667 *
668 * LOCKING: 668 * LOCKING:
669 * None (inherited from caller). 669 * None (inherited from caller).
670 */ 670 */
671 671
672 static int ich_pata_cable_detect(struct ata_port *ap) 672 static int ich_pata_cable_detect(struct ata_port *ap)
673 { 673 {
674 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 674 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
675 const struct ich_laptop *lap = &ich_laptop[0]; 675 const struct ich_laptop *lap = &ich_laptop[0];
676 u8 tmp, mask; 676 u8 tmp, mask;
677 677
678 /* Check for specials - Acer Aspire 5602WLMi */ 678 /* Check for specials - Acer Aspire 5602WLMi */
679 while (lap->device) { 679 while (lap->device) {
680 if (lap->device == pdev->device && 680 if (lap->device == pdev->device &&
681 lap->subvendor == pdev->subsystem_vendor && 681 lap->subvendor == pdev->subsystem_vendor &&
682 lap->subdevice == pdev->subsystem_device) 682 lap->subdevice == pdev->subsystem_device)
683 return ATA_CBL_PATA40_SHORT; 683 return ATA_CBL_PATA40_SHORT;
684 684
685 lap++; 685 lap++;
686 } 686 }
687 687
688 /* check BIOS cable detect results */ 688 /* check BIOS cable detect results */
689 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; 689 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
690 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp); 690 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
691 if ((tmp & mask) == 0) 691 if ((tmp & mask) == 0)
692 return ATA_CBL_PATA40; 692 return ATA_CBL_PATA40;
693 return ATA_CBL_PATA80; 693 return ATA_CBL_PATA80;
694 } 694 }
695 695
696 /** 696 /**
697 * piix_pata_prereset - prereset for PATA host controller 697 * piix_pata_prereset - prereset for PATA host controller
698 * @link: Target link 698 * @link: Target link
699 * @deadline: deadline jiffies for the operation 699 * @deadline: deadline jiffies for the operation
700 * 700 *
701 * LOCKING: 701 * LOCKING:
702 * None (inherited from caller). 702 * None (inherited from caller).
703 */ 703 */
704 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline) 704 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
705 { 705 {
706 struct ata_port *ap = link->ap; 706 struct ata_port *ap = link->ap;
707 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 707 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
708 708
709 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) 709 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
710 return -ENOENT; 710 return -ENOENT;
711 return ata_std_prereset(link, deadline); 711 return ata_std_prereset(link, deadline);
712 } 712 }
713 713
714 static void piix_pata_error_handler(struct ata_port *ap) 714 static void piix_pata_error_handler(struct ata_port *ap)
715 { 715 {
716 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL, 716 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
717 ata_std_postreset); 717 ata_std_postreset);
718 } 718 }
719 719
720 /** 720 /**
721 * piix_set_piomode - Initialize host controller PATA PIO timings 721 * piix_set_piomode - Initialize host controller PATA PIO timings
722 * @ap: Port whose timings we are configuring 722 * @ap: Port whose timings we are configuring
723 * @adev: um 723 * @adev: um
724 * 724 *
725 * Set PIO mode for device, in host controller PCI config space. 725 * Set PIO mode for device, in host controller PCI config space.
726 * 726 *
727 * LOCKING: 727 * LOCKING:
728 * None (inherited from caller). 728 * None (inherited from caller).
729 */ 729 */
730 730
731 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev) 731 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
732 { 732 {
733 unsigned int pio = adev->pio_mode - XFER_PIO_0; 733 unsigned int pio = adev->pio_mode - XFER_PIO_0;
734 struct pci_dev *dev = to_pci_dev(ap->host->dev); 734 struct pci_dev *dev = to_pci_dev(ap->host->dev);
735 unsigned int is_slave = (adev->devno != 0); 735 unsigned int is_slave = (adev->devno != 0);
736 unsigned int master_port= ap->port_no ? 0x42 : 0x40; 736 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
737 unsigned int slave_port = 0x44; 737 unsigned int slave_port = 0x44;
738 u16 master_data; 738 u16 master_data;
739 u8 slave_data; 739 u8 slave_data;
740 u8 udma_enable; 740 u8 udma_enable;
741 int control = 0; 741 int control = 0;
742 742
743 /* 743 /*
744 * See Intel Document 298600-004 for the timing programing rules 744 * See Intel Document 298600-004 for the timing programing rules
745 * for ICH controllers. 745 * for ICH controllers.
746 */ 746 */
747 747
748 static const /* ISP RTC */ 748 static const /* ISP RTC */
749 u8 timings[][2] = { { 0, 0 }, 749 u8 timings[][2] = { { 0, 0 },
750 { 0, 0 }, 750 { 0, 0 },
751 { 1, 0 }, 751 { 1, 0 },
752 { 2, 1 }, 752 { 2, 1 },
753 { 2, 3 }, }; 753 { 2, 3 }, };
754 754
755 if (pio >= 2) 755 if (pio >= 2)
756 control |= 1; /* TIME1 enable */ 756 control |= 1; /* TIME1 enable */
757 if (ata_pio_need_iordy(adev)) 757 if (ata_pio_need_iordy(adev))
758 control |= 2; /* IE enable */ 758 control |= 2; /* IE enable */
759 759
760 /* Intel specifies that the PPE functionality is for disk only */ 760 /* Intel specifies that the PPE functionality is for disk only */
761 if (adev->class == ATA_DEV_ATA) 761 if (adev->class == ATA_DEV_ATA)
762 control |= 4; /* PPE enable */ 762 control |= 4; /* PPE enable */
763 763
764 /* PIO configuration clears DTE unconditionally. It will be 764 /* PIO configuration clears DTE unconditionally. It will be
765 * programmed in set_dmamode which is guaranteed to be called 765 * programmed in set_dmamode which is guaranteed to be called
766 * after set_piomode if any DMA mode is available. 766 * after set_piomode if any DMA mode is available.
767 */ 767 */
768 pci_read_config_word(dev, master_port, &master_data); 768 pci_read_config_word(dev, master_port, &master_data);
769 if (is_slave) { 769 if (is_slave) {
770 /* clear TIME1|IE1|PPE1|DTE1 */ 770 /* clear TIME1|IE1|PPE1|DTE1 */
771 master_data &= 0xff0f; 771 master_data &= 0xff0f;
772 /* Enable SITRE (seperate slave timing register) */ 772 /* Enable SITRE (seperate slave timing register) */
773 master_data |= 0x4000; 773 master_data |= 0x4000;
774 /* enable PPE1, IE1 and TIME1 as needed */ 774 /* enable PPE1, IE1 and TIME1 as needed */
775 master_data |= (control << 4); 775 master_data |= (control << 4);
776 pci_read_config_byte(dev, slave_port, &slave_data); 776 pci_read_config_byte(dev, slave_port, &slave_data);
777 slave_data &= (ap->port_no ? 0x0f : 0xf0); 777 slave_data &= (ap->port_no ? 0x0f : 0xf0);
778 /* Load the timing nibble for this slave */ 778 /* Load the timing nibble for this slave */
779 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) 779 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
780 << (ap->port_no ? 4 : 0); 780 << (ap->port_no ? 4 : 0);
781 } else { 781 } else {
782 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */ 782 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
783 master_data &= 0xccf0; 783 master_data &= 0xccf0;
784 /* Enable PPE, IE and TIME as appropriate */ 784 /* Enable PPE, IE and TIME as appropriate */
785 master_data |= control; 785 master_data |= control;
786 /* load ISP and RCT */ 786 /* load ISP and RCT */
787 master_data |= 787 master_data |=
788 (timings[pio][0] << 12) | 788 (timings[pio][0] << 12) |
789 (timings[pio][1] << 8); 789 (timings[pio][1] << 8);
790 } 790 }
791 pci_write_config_word(dev, master_port, master_data); 791 pci_write_config_word(dev, master_port, master_data);
792 if (is_slave) 792 if (is_slave)
793 pci_write_config_byte(dev, slave_port, slave_data); 793 pci_write_config_byte(dev, slave_port, slave_data);
794 794
795 /* Ensure the UDMA bit is off - it will be turned back on if 795 /* Ensure the UDMA bit is off - it will be turned back on if
796 UDMA is selected */ 796 UDMA is selected */
797 797
798 if (ap->udma_mask) { 798 if (ap->udma_mask) {
799 pci_read_config_byte(dev, 0x48, &udma_enable); 799 pci_read_config_byte(dev, 0x48, &udma_enable);
800 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); 800 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
801 pci_write_config_byte(dev, 0x48, udma_enable); 801 pci_write_config_byte(dev, 0x48, udma_enable);
802 } 802 }
803 } 803 }
804 804
805 /** 805 /**
806 * do_pata_set_dmamode - Initialize host controller PATA PIO timings 806 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
807 * @ap: Port whose timings we are configuring 807 * @ap: Port whose timings we are configuring
808 * @adev: Drive in question 808 * @adev: Drive in question
809 * @udma: udma mode, 0 - 6 809 * @udma: udma mode, 0 - 6
810 * @isich: set if the chip is an ICH device 810 * @isich: set if the chip is an ICH device
811 * 811 *
812 * Set UDMA mode for device, in host controller PCI config space. 812 * Set UDMA mode for device, in host controller PCI config space.
813 * 813 *
814 * LOCKING: 814 * LOCKING:
815 * None (inherited from caller). 815 * None (inherited from caller).
816 */ 816 */
817 817
818 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich) 818 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
819 { 819 {
820 struct pci_dev *dev = to_pci_dev(ap->host->dev); 820 struct pci_dev *dev = to_pci_dev(ap->host->dev);
821 u8 master_port = ap->port_no ? 0x42 : 0x40; 821 u8 master_port = ap->port_no ? 0x42 : 0x40;
822 u16 master_data; 822 u16 master_data;
823 u8 speed = adev->dma_mode; 823 u8 speed = adev->dma_mode;
824 int devid = adev->devno + 2 * ap->port_no; 824 int devid = adev->devno + 2 * ap->port_no;
825 u8 udma_enable = 0; 825 u8 udma_enable = 0;
826 826
827 static const /* ISP RTC */ 827 static const /* ISP RTC */
828 u8 timings[][2] = { { 0, 0 }, 828 u8 timings[][2] = { { 0, 0 },
829 { 0, 0 }, 829 { 0, 0 },
830 { 1, 0 }, 830 { 1, 0 },
831 { 2, 1 }, 831 { 2, 1 },
832 { 2, 3 }, }; 832 { 2, 3 }, };
833 833
834 pci_read_config_word(dev, master_port, &master_data); 834 pci_read_config_word(dev, master_port, &master_data);
835 if (ap->udma_mask) 835 if (ap->udma_mask)
836 pci_read_config_byte(dev, 0x48, &udma_enable); 836 pci_read_config_byte(dev, 0x48, &udma_enable);
837 837
838 if (speed >= XFER_UDMA_0) { 838 if (speed >= XFER_UDMA_0) {
839 unsigned int udma = adev->dma_mode - XFER_UDMA_0; 839 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
840 u16 udma_timing; 840 u16 udma_timing;
841 u16 ideconf; 841 u16 ideconf;
842 int u_clock, u_speed; 842 int u_clock, u_speed;
843 843
844 /* 844 /*
845 * UDMA is handled by a combination of clock switching and 845 * UDMA is handled by a combination of clock switching and
846 * selection of dividers 846 * selection of dividers
847 * 847 *
848 * Handy rule: Odd modes are UDMATIMx 01, even are 02 848 * Handy rule: Odd modes are UDMATIMx 01, even are 02
849 * except UDMA0 which is 00 849 * except UDMA0 which is 00
850 */ 850 */
851 u_speed = min(2 - (udma & 1), udma); 851 u_speed = min(2 - (udma & 1), udma);
852 if (udma == 5) 852 if (udma == 5)
853 u_clock = 0x1000; /* 100Mhz */ 853 u_clock = 0x1000; /* 100Mhz */
854 else if (udma > 2) 854 else if (udma > 2)
855 u_clock = 1; /* 66Mhz */ 855 u_clock = 1; /* 66Mhz */
856 else 856 else
857 u_clock = 0; /* 33Mhz */ 857 u_clock = 0; /* 33Mhz */
858 858
859 udma_enable |= (1 << devid); 859 udma_enable |= (1 << devid);
860 860
861 /* Load the CT/RP selection */ 861 /* Load the CT/RP selection */
862 pci_read_config_word(dev, 0x4A, &udma_timing); 862 pci_read_config_word(dev, 0x4A, &udma_timing);
863 udma_timing &= ~(3 << (4 * devid)); 863 udma_timing &= ~(3 << (4 * devid));
864 udma_timing |= u_speed << (4 * devid); 864 udma_timing |= u_speed << (4 * devid);
865 pci_write_config_word(dev, 0x4A, udma_timing); 865 pci_write_config_word(dev, 0x4A, udma_timing);
866 866
867 if (isich) { 867 if (isich) {
868 /* Select a 33/66/100Mhz clock */ 868 /* Select a 33/66/100Mhz clock */
869 pci_read_config_word(dev, 0x54, &ideconf); 869 pci_read_config_word(dev, 0x54, &ideconf);
870 ideconf &= ~(0x1001 << devid); 870 ideconf &= ~(0x1001 << devid);
871 ideconf |= u_clock << devid; 871 ideconf |= u_clock << devid;
872 /* For ICH or later we should set bit 10 for better 872 /* For ICH or later we should set bit 10 for better
873 performance (WR_PingPong_En) */ 873 performance (WR_PingPong_En) */
874 pci_write_config_word(dev, 0x54, ideconf); 874 pci_write_config_word(dev, 0x54, ideconf);
875 } 875 }
876 } else { 876 } else {
877 /* 877 /*
878 * MWDMA is driven by the PIO timings. We must also enable 878 * MWDMA is driven by the PIO timings. We must also enable
879 * IORDY unconditionally along with TIME1. PPE has already 879 * IORDY unconditionally along with TIME1. PPE has already
880 * been set when the PIO timing was set. 880 * been set when the PIO timing was set.
881 */ 881 */
882 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; 882 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
883 unsigned int control; 883 unsigned int control;
884 u8 slave_data; 884 u8 slave_data;
885 const unsigned int needed_pio[3] = { 885 const unsigned int needed_pio[3] = {
886 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 886 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
887 }; 887 };
888 int pio = needed_pio[mwdma] - XFER_PIO_0; 888 int pio = needed_pio[mwdma] - XFER_PIO_0;
889 889
890 control = 3; /* IORDY|TIME1 */ 890 control = 3; /* IORDY|TIME1 */
891 891
892 /* If the drive MWDMA is faster than it can do PIO then 892 /* If the drive MWDMA is faster than it can do PIO then
893 we must force PIO into PIO0 */ 893 we must force PIO into PIO0 */
894 894
895 if (adev->pio_mode < needed_pio[mwdma]) 895 if (adev->pio_mode < needed_pio[mwdma])
896 /* Enable DMA timing only */ 896 /* Enable DMA timing only */
897 control |= 8; /* PIO cycles in PIO0 */ 897 control |= 8; /* PIO cycles in PIO0 */
898 898
899 if (adev->devno) { /* Slave */ 899 if (adev->devno) { /* Slave */
900 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ 900 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
901 master_data |= control << 4; 901 master_data |= control << 4;
902 pci_read_config_byte(dev, 0x44, &slave_data); 902 pci_read_config_byte(dev, 0x44, &slave_data);
903 slave_data &= (ap->port_no ? 0x0f : 0xf0); 903 slave_data &= (ap->port_no ? 0x0f : 0xf0);
904 /* Load the matching timing */ 904 /* Load the matching timing */
905 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); 905 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
906 pci_write_config_byte(dev, 0x44, slave_data); 906 pci_write_config_byte(dev, 0x44, slave_data);
907 } else { /* Master */ 907 } else { /* Master */
908 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY 908 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
909 and master timing bits */ 909 and master timing bits */
910 master_data |= control; 910 master_data |= control;
911 master_data |= 911 master_data |=
912 (timings[pio][0] << 12) | 912 (timings[pio][0] << 12) |
913 (timings[pio][1] << 8); 913 (timings[pio][1] << 8);
914 } 914 }
915 915
916 if (ap->udma_mask) { 916 if (ap->udma_mask) {
917 udma_enable &= ~(1 << devid); 917 udma_enable &= ~(1 << devid);
918 pci_write_config_word(dev, master_port, master_data); 918 pci_write_config_word(dev, master_port, master_data);
919 } 919 }
920 } 920 }
921 /* Don't scribble on 0x48 if the controller does not support UDMA */ 921 /* Don't scribble on 0x48 if the controller does not support UDMA */
922 if (ap->udma_mask) 922 if (ap->udma_mask)
923 pci_write_config_byte(dev, 0x48, udma_enable); 923 pci_write_config_byte(dev, 0x48, udma_enable);
924 } 924 }
925 925
926 /** 926 /**
927 * piix_set_dmamode - Initialize host controller PATA DMA timings 927 * piix_set_dmamode - Initialize host controller PATA DMA timings
928 * @ap: Port whose timings we are configuring 928 * @ap: Port whose timings we are configuring
929 * @adev: um 929 * @adev: um
930 * 930 *
931 * Set MW/UDMA mode for device, in host controller PCI config space. 931 * Set MW/UDMA mode for device, in host controller PCI config space.
932 * 932 *
933 * LOCKING: 933 * LOCKING:
934 * None (inherited from caller). 934 * None (inherited from caller).
935 */ 935 */
936 936
937 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev) 937 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
938 { 938 {
939 do_pata_set_dmamode(ap, adev, 0); 939 do_pata_set_dmamode(ap, adev, 0);
940 } 940 }
941 941
942 /** 942 /**
943 * ich_set_dmamode - Initialize host controller PATA DMA timings 943 * ich_set_dmamode - Initialize host controller PATA DMA timings
944 * @ap: Port whose timings we are configuring 944 * @ap: Port whose timings we are configuring
945 * @adev: um 945 * @adev: um
946 * 946 *
947 * Set MW/UDMA mode for device, in host controller PCI config space. 947 * Set MW/UDMA mode for device, in host controller PCI config space.
948 * 948 *
949 * LOCKING: 949 * LOCKING:
950 * None (inherited from caller). 950 * None (inherited from caller).
951 */ 951 */
952 952
953 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev) 953 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
954 { 954 {
955 do_pata_set_dmamode(ap, adev, 1); 955 do_pata_set_dmamode(ap, adev, 1);
956 } 956 }
957 957
958 #ifdef CONFIG_PM 958 #ifdef CONFIG_PM
959 static int piix_broken_suspend(void) 959 static int piix_broken_suspend(void)
960 { 960 {
961 static const struct dmi_system_id sysids[] = { 961 static const struct dmi_system_id sysids[] = {
962 { 962 {
963 .ident = "TECRA M3", 963 .ident = "TECRA M3",
964 .matches = { 964 .matches = {
965 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 965 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
966 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"), 966 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
967 }, 967 },
968 }, 968 },
969 { 969 {
970 .ident = "TECRA M3",
971 .matches = {
972 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
973 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
974 },
975 },
976 {
970 .ident = "TECRA M5", 977 .ident = "TECRA M5",
971 .matches = { 978 .matches = {
972 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 979 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
973 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"), 980 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
974 }, 981 },
975 }, 982 },
976 { 983 {
977 .ident = "TECRA M7", 984 .ident = "TECRA M7",
978 .matches = { 985 .matches = {
979 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 986 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
980 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"), 987 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
981 }, 988 },
982 }, 989 },
983 { 990 {
991 .ident = "TECRA A8",
992 .matches = {
993 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
994 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
995 },
996 },
997 {
998 .ident = "Satellite R25",
999 .matches = {
1000 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1001 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1002 },
1003 },
1004 {
984 .ident = "Satellite U200", 1005 .ident = "Satellite U200",
985 .matches = { 1006 .matches = {
986 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1007 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
987 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"), 1008 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1009 },
1010 },
1011 {
1012 .ident = "Satellite U200",
1013 .matches = {
1014 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1015 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
988 }, 1016 },
989 }, 1017 },
990 { 1018 {
991 .ident = "Satellite Pro U200", 1019 .ident = "Satellite Pro U200",
992 .matches = { 1020 .matches = {
993 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1021 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
994 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"), 1022 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
995 }, 1023 },
996 }, 1024 },
997 { 1025 {
998 .ident = "Satellite U205", 1026 .ident = "Satellite U205",
999 .matches = { 1027 .matches = {
1000 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1028 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1001 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"), 1029 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1002 }, 1030 },
1003 }, 1031 },
1004 { 1032 {
1005 .ident = "SATELLITE U205", 1033 .ident = "SATELLITE U205",
1006 .matches = { 1034 .matches = {
1007 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1035 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1008 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"), 1036 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1009 }, 1037 },
1010 }, 1038 },
1011 { 1039 {
1012 .ident = "Portege M500", 1040 .ident = "Portege M500",
1013 .matches = { 1041 .matches = {
1014 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1042 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1015 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"), 1043 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1016 }, 1044 },
1017 }, 1045 },
1018 1046
1019 { } /* terminate list */ 1047 { } /* terminate list */
1020 }; 1048 };
1021 static const char *oemstrs[] = { 1049 static const char *oemstrs[] = {
1022 "Tecra M3,", 1050 "Tecra M3,",
1023 }; 1051 };
1024 int i; 1052 int i;
1025 1053
1026 if (dmi_check_system(sysids)) 1054 if (dmi_check_system(sysids))
1027 return 1; 1055 return 1;
1028 1056
1029 for (i = 0; i < ARRAY_SIZE(oemstrs); i++) 1057 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1030 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL)) 1058 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1031 return 1; 1059 return 1;
1032 1060
1033 return 0; 1061 return 0;
1034 } 1062 }
1035 1063
1036 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) 1064 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1037 { 1065 {
1038 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1066 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1039 unsigned long flags; 1067 unsigned long flags;
1040 int rc = 0; 1068 int rc = 0;
1041 1069
1042 rc = ata_host_suspend(host, mesg); 1070 rc = ata_host_suspend(host, mesg);
1043 if (rc) 1071 if (rc)
1044 return rc; 1072 return rc;
1045 1073
1046 /* Some braindamaged ACPI suspend implementations expect the 1074 /* Some braindamaged ACPI suspend implementations expect the
1047 * controller to be awake on entry; otherwise, it burns cpu 1075 * controller to be awake on entry; otherwise, it burns cpu
1048 * cycles and power trying to do something to the sleeping 1076 * cycles and power trying to do something to the sleeping
1049 * beauty. 1077 * beauty.
1050 */ 1078 */
1051 if (piix_broken_suspend() && mesg.event == PM_EVENT_SUSPEND) { 1079 if (piix_broken_suspend() && mesg.event == PM_EVENT_SUSPEND) {
1052 pci_save_state(pdev); 1080 pci_save_state(pdev);
1053 1081
1054 /* mark its power state as "unknown", since we don't 1082 /* mark its power state as "unknown", since we don't
1055 * know if e.g. the BIOS will change its device state 1083 * know if e.g. the BIOS will change its device state
1056 * when we suspend. 1084 * when we suspend.
1057 */ 1085 */
1058 if (pdev->current_state == PCI_D0) 1086 if (pdev->current_state == PCI_D0)
1059 pdev->current_state = PCI_UNKNOWN; 1087 pdev->current_state = PCI_UNKNOWN;
1060 1088
1061 /* tell resume that it's waking up from broken suspend */ 1089 /* tell resume that it's waking up from broken suspend */
1062 spin_lock_irqsave(&host->lock, flags); 1090 spin_lock_irqsave(&host->lock, flags);
1063 host->flags |= PIIX_HOST_BROKEN_SUSPEND; 1091 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1064 spin_unlock_irqrestore(&host->lock, flags); 1092 spin_unlock_irqrestore(&host->lock, flags);
1065 } else 1093 } else
1066 ata_pci_device_do_suspend(pdev, mesg); 1094 ata_pci_device_do_suspend(pdev, mesg);
1067 1095
1068 return 0; 1096 return 0;
1069 } 1097 }
1070 1098
1071 static int piix_pci_device_resume(struct pci_dev *pdev) 1099 static int piix_pci_device_resume(struct pci_dev *pdev)
1072 { 1100 {
1073 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1101 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1074 unsigned long flags; 1102 unsigned long flags;
1075 int rc; 1103 int rc;
1076 1104
1077 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) { 1105 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1078 spin_lock_irqsave(&host->lock, flags); 1106 spin_lock_irqsave(&host->lock, flags);
1079 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND; 1107 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1080 spin_unlock_irqrestore(&host->lock, flags); 1108 spin_unlock_irqrestore(&host->lock, flags);
1081 1109
1082 pci_set_power_state(pdev, PCI_D0); 1110 pci_set_power_state(pdev, PCI_D0);
1083 pci_restore_state(pdev); 1111 pci_restore_state(pdev);
1084 1112
1085 /* PCI device wasn't disabled during suspend. Use 1113 /* PCI device wasn't disabled during suspend. Use
1086 * pci_reenable_device() to avoid affecting the enable 1114 * pci_reenable_device() to avoid affecting the enable
1087 * count. 1115 * count.
1088 */ 1116 */
1089 rc = pci_reenable_device(pdev); 1117 rc = pci_reenable_device(pdev);
1090 if (rc) 1118 if (rc)
1091 dev_printk(KERN_ERR, &pdev->dev, "failed to enable " 1119 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1092 "device after resume (%d)\n", rc); 1120 "device after resume (%d)\n", rc);
1093 } else 1121 } else
1094 rc = ata_pci_device_do_resume(pdev); 1122 rc = ata_pci_device_do_resume(pdev);
1095 1123
1096 if (rc == 0) 1124 if (rc == 0)
1097 ata_host_resume(host); 1125 ata_host_resume(host);
1098 1126
1099 return rc; 1127 return rc;
1100 } 1128 }
1101 #endif 1129 #endif
1102 1130
1103 #define AHCI_PCI_BAR 5 1131 #define AHCI_PCI_BAR 5
1104 #define AHCI_GLOBAL_CTL 0x04 1132 #define AHCI_GLOBAL_CTL 0x04
1105 #define AHCI_ENABLE (1 << 31) 1133 #define AHCI_ENABLE (1 << 31)
1106 static int piix_disable_ahci(struct pci_dev *pdev) 1134 static int piix_disable_ahci(struct pci_dev *pdev)
1107 { 1135 {
1108 void __iomem *mmio; 1136 void __iomem *mmio;
1109 u32 tmp; 1137 u32 tmp;
1110 int rc = 0; 1138 int rc = 0;
1111 1139
1112 /* BUG: pci_enable_device has not yet been called. This 1140 /* BUG: pci_enable_device has not yet been called. This
1113 * works because this device is usually set up by BIOS. 1141 * works because this device is usually set up by BIOS.
1114 */ 1142 */
1115 1143
1116 if (!pci_resource_start(pdev, AHCI_PCI_BAR) || 1144 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1117 !pci_resource_len(pdev, AHCI_PCI_BAR)) 1145 !pci_resource_len(pdev, AHCI_PCI_BAR))
1118 return 0; 1146 return 0;
1119 1147
1120 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); 1148 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1121 if (!mmio) 1149 if (!mmio)
1122 return -ENOMEM; 1150 return -ENOMEM;
1123 1151
1124 tmp = ioread32(mmio + AHCI_GLOBAL_CTL); 1152 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1125 if (tmp & AHCI_ENABLE) { 1153 if (tmp & AHCI_ENABLE) {
1126 tmp &= ~AHCI_ENABLE; 1154 tmp &= ~AHCI_ENABLE;
1127 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL); 1155 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1128 1156
1129 tmp = ioread32(mmio + AHCI_GLOBAL_CTL); 1157 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1130 if (tmp & AHCI_ENABLE) 1158 if (tmp & AHCI_ENABLE)
1131 rc = -EIO; 1159 rc = -EIO;
1132 } 1160 }
1133 1161
1134 pci_iounmap(pdev, mmio); 1162 pci_iounmap(pdev, mmio);
1135 return rc; 1163 return rc;
1136 } 1164 }
1137 1165
1138 /** 1166 /**
1139 * piix_check_450nx_errata - Check for problem 450NX setup 1167 * piix_check_450nx_errata - Check for problem 450NX setup
1140 * @ata_dev: the PCI device to check 1168 * @ata_dev: the PCI device to check
1141 * 1169 *
1142 * Check for the present of 450NX errata #19 and errata #25. If 1170 * Check for the present of 450NX errata #19 and errata #25. If
1143 * they are found return an error code so we can turn off DMA 1171 * they are found return an error code so we can turn off DMA
1144 */ 1172 */
1145 1173
1146 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev) 1174 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1147 { 1175 {
1148 struct pci_dev *pdev = NULL; 1176 struct pci_dev *pdev = NULL;
1149 u16 cfg; 1177 u16 cfg;
1150 int no_piix_dma = 0; 1178 int no_piix_dma = 0;
1151 1179
1152 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) { 1180 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1153 /* Look for 450NX PXB. Check for problem configurations 1181 /* Look for 450NX PXB. Check for problem configurations
1154 A PCI quirk checks bit 6 already */ 1182 A PCI quirk checks bit 6 already */
1155 pci_read_config_word(pdev, 0x41, &cfg); 1183 pci_read_config_word(pdev, 0x41, &cfg);
1156 /* Only on the original revision: IDE DMA can hang */ 1184 /* Only on the original revision: IDE DMA can hang */
1157 if (pdev->revision == 0x00) 1185 if (pdev->revision == 0x00)
1158 no_piix_dma = 1; 1186 no_piix_dma = 1;
1159 /* On all revisions below 5 PXB bus lock must be disabled for IDE */ 1187 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1160 else if (cfg & (1<<14) && pdev->revision < 5) 1188 else if (cfg & (1<<14) && pdev->revision < 5)
1161 no_piix_dma = 2; 1189 no_piix_dma = 2;
1162 } 1190 }
1163 if (no_piix_dma) 1191 if (no_piix_dma)
1164 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n"); 1192 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
1165 if (no_piix_dma == 2) 1193 if (no_piix_dma == 2)
1166 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n"); 1194 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1167 return no_piix_dma; 1195 return no_piix_dma;
1168 } 1196 }
1169 1197
1170 static void __devinit piix_init_pcs(struct pci_dev *pdev, 1198 static void __devinit piix_init_pcs(struct pci_dev *pdev,
1171 struct ata_port_info *pinfo, 1199 struct ata_port_info *pinfo,
1172 const struct piix_map_db *map_db) 1200 const struct piix_map_db *map_db)
1173 { 1201 {
1174 u16 pcs, new_pcs; 1202 u16 pcs, new_pcs;
1175 1203
1176 pci_read_config_word(pdev, ICH5_PCS, &pcs); 1204 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1177 1205
1178 new_pcs = pcs | map_db->port_enable; 1206 new_pcs = pcs | map_db->port_enable;
1179 1207
1180 if (new_pcs != pcs) { 1208 if (new_pcs != pcs) {
1181 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs); 1209 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1182 pci_write_config_word(pdev, ICH5_PCS, new_pcs); 1210 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1183 msleep(150); 1211 msleep(150);
1184 } 1212 }
1185 } 1213 }
1186 1214
1187 static void __devinit piix_init_sata_map(struct pci_dev *pdev, 1215 static void __devinit piix_init_sata_map(struct pci_dev *pdev,
1188 struct ata_port_info *pinfo, 1216 struct ata_port_info *pinfo,
1189 const struct piix_map_db *map_db) 1217 const struct piix_map_db *map_db)
1190 { 1218 {
1191 struct piix_host_priv *hpriv = pinfo[0].private_data; 1219 struct piix_host_priv *hpriv = pinfo[0].private_data;
1192 const int *map; 1220 const int *map;
1193 int i, invalid_map = 0; 1221 int i, invalid_map = 0;
1194 u8 map_value; 1222 u8 map_value;
1195 1223
1196 pci_read_config_byte(pdev, ICH5_PMR, &map_value); 1224 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1197 1225
1198 map = map_db->map[map_value & map_db->mask]; 1226 map = map_db->map[map_value & map_db->mask];
1199 1227
1200 dev_printk(KERN_INFO, &pdev->dev, "MAP ["); 1228 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1201 for (i = 0; i < 4; i++) { 1229 for (i = 0; i < 4; i++) {
1202 switch (map[i]) { 1230 switch (map[i]) {
1203 case RV: 1231 case RV:
1204 invalid_map = 1; 1232 invalid_map = 1;
1205 printk(" XX"); 1233 printk(" XX");
1206 break; 1234 break;
1207 1235
1208 case NA: 1236 case NA:
1209 printk(" --"); 1237 printk(" --");
1210 break; 1238 break;
1211 1239
1212 case IDE: 1240 case IDE:
1213 WARN_ON((i & 1) || map[i + 1] != IDE); 1241 WARN_ON((i & 1) || map[i + 1] != IDE);
1214 pinfo[i / 2] = piix_port_info[ich_pata_100]; 1242 pinfo[i / 2] = piix_port_info[ich_pata_100];
1215 pinfo[i / 2].private_data = hpriv; 1243 pinfo[i / 2].private_data = hpriv;
1216 i++; 1244 i++;
1217 printk(" IDE IDE"); 1245 printk(" IDE IDE");
1218 break; 1246 break;
1219 1247
1220 default: 1248 default:
1221 printk(" P%d", map[i]); 1249 printk(" P%d", map[i]);
1222 if (i & 1) 1250 if (i & 1)
1223 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS; 1251 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1224 break; 1252 break;
1225 } 1253 }
1226 } 1254 }
1227 printk(" ]\n"); 1255 printk(" ]\n");
1228 1256
1229 if (invalid_map) 1257 if (invalid_map)
1230 dev_printk(KERN_ERR, &pdev->dev, 1258 dev_printk(KERN_ERR, &pdev->dev,
1231 "invalid MAP value %u\n", map_value); 1259 "invalid MAP value %u\n", map_value);
1232 1260
1233 hpriv->map = map; 1261 hpriv->map = map;
1234 } 1262 }
1235 1263
1236 static void piix_iocfg_bit18_quirk(struct pci_dev *pdev) 1264 static void piix_iocfg_bit18_quirk(struct pci_dev *pdev)
1237 { 1265 {
1238 static const struct dmi_system_id sysids[] = { 1266 static const struct dmi_system_id sysids[] = {
1239 { 1267 {
1240 /* Clevo M570U sets IOCFG bit 18 if the cdrom 1268 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1241 * isn't used to boot the system which 1269 * isn't used to boot the system which
1242 * disables the channel. 1270 * disables the channel.
1243 */ 1271 */
1244 .ident = "M570U", 1272 .ident = "M570U",
1245 .matches = { 1273 .matches = {
1246 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."), 1274 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1247 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"), 1275 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1248 }, 1276 },
1249 }, 1277 },
1250 1278
1251 { } /* terminate list */ 1279 { } /* terminate list */
1252 }; 1280 };
1253 u32 iocfg; 1281 u32 iocfg;
1254 1282
1255 if (!dmi_check_system(sysids)) 1283 if (!dmi_check_system(sysids))
1256 return; 1284 return;
1257 1285
1258 /* The datasheet says that bit 18 is NOOP but certain systems 1286 /* The datasheet says that bit 18 is NOOP but certain systems
1259 * seem to use it to disable a channel. Clear the bit on the 1287 * seem to use it to disable a channel. Clear the bit on the
1260 * affected systems. 1288 * affected systems.
1261 */ 1289 */
1262 pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg); 1290 pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg);
1263 if (iocfg & (1 << 18)) { 1291 if (iocfg & (1 << 18)) {
1264 dev_printk(KERN_INFO, &pdev->dev, 1292 dev_printk(KERN_INFO, &pdev->dev,
1265 "applying IOCFG bit18 quirk\n"); 1293 "applying IOCFG bit18 quirk\n");
1266 iocfg &= ~(1 << 18); 1294 iocfg &= ~(1 << 18);
1267 pci_write_config_dword(pdev, PIIX_IOCFG, iocfg); 1295 pci_write_config_dword(pdev, PIIX_IOCFG, iocfg);
1268 } 1296 }
1269 } 1297 }
1270 1298
1271 /** 1299 /**
1272 * piix_init_one - Register PIIX ATA PCI device with kernel services 1300 * piix_init_one - Register PIIX ATA PCI device with kernel services
1273 * @pdev: PCI device to register 1301 * @pdev: PCI device to register
1274 * @ent: Entry in piix_pci_tbl matching with @pdev 1302 * @ent: Entry in piix_pci_tbl matching with @pdev
1275 * 1303 *
1276 * Called from kernel PCI layer. We probe for combined mode (sigh), 1304 * Called from kernel PCI layer. We probe for combined mode (sigh),
1277 * and then hand over control to libata, for it to do the rest. 1305 * and then hand over control to libata, for it to do the rest.
1278 * 1306 *
1279 * LOCKING: 1307 * LOCKING:
1280 * Inherited from PCI layer (may sleep). 1308 * Inherited from PCI layer (may sleep).
1281 * 1309 *
1282 * RETURNS: 1310 * RETURNS:
1283 * Zero on success, or -ERRNO value. 1311 * Zero on success, or -ERRNO value.
1284 */ 1312 */
1285 1313
1286 static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1314 static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1287 { 1315 {
1288 static int printed_version; 1316 static int printed_version;
1289 struct device *dev = &pdev->dev; 1317 struct device *dev = &pdev->dev;
1290 struct ata_port_info port_info[2]; 1318 struct ata_port_info port_info[2];
1291 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] }; 1319 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1292 struct piix_host_priv *hpriv; 1320 struct piix_host_priv *hpriv;
1293 unsigned long port_flags; 1321 unsigned long port_flags;
1294 1322
1295 if (!printed_version++) 1323 if (!printed_version++)
1296 dev_printk(KERN_DEBUG, &pdev->dev, 1324 dev_printk(KERN_DEBUG, &pdev->dev,
1297 "version " DRV_VERSION "\n"); 1325 "version " DRV_VERSION "\n");
1298 1326
1299 /* no hotplugging support (FIXME) */ 1327 /* no hotplugging support (FIXME) */
1300 if (!in_module_init) 1328 if (!in_module_init)
1301 return -ENODEV; 1329 return -ENODEV;
1302 1330
1303 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1331 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1304 if (!hpriv) 1332 if (!hpriv)
1305 return -ENOMEM; 1333 return -ENOMEM;
1306 1334
1307 port_info[0] = piix_port_info[ent->driver_data]; 1335 port_info[0] = piix_port_info[ent->driver_data];
1308 port_info[1] = piix_port_info[ent->driver_data]; 1336 port_info[1] = piix_port_info[ent->driver_data];
1309 port_info[0].private_data = hpriv; 1337 port_info[0].private_data = hpriv;
1310 port_info[1].private_data = hpriv; 1338 port_info[1].private_data = hpriv;
1311 1339
1312 port_flags = port_info[0].flags; 1340 port_flags = port_info[0].flags;
1313 1341
1314 if (port_flags & PIIX_FLAG_AHCI) { 1342 if (port_flags & PIIX_FLAG_AHCI) {
1315 u8 tmp; 1343 u8 tmp;
1316 pci_read_config_byte(pdev, PIIX_SCC, &tmp); 1344 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1317 if (tmp == PIIX_AHCI_DEVICE) { 1345 if (tmp == PIIX_AHCI_DEVICE) {
1318 int rc = piix_disable_ahci(pdev); 1346 int rc = piix_disable_ahci(pdev);
1319 if (rc) 1347 if (rc)
1320 return rc; 1348 return rc;
1321 } 1349 }
1322 } 1350 }
1323 1351
1324 /* Initialize SATA map */ 1352 /* Initialize SATA map */
1325 if (port_flags & ATA_FLAG_SATA) { 1353 if (port_flags & ATA_FLAG_SATA) {
1326 piix_init_sata_map(pdev, port_info, 1354 piix_init_sata_map(pdev, port_info,
1327 piix_map_db_table[ent->driver_data]); 1355 piix_map_db_table[ent->driver_data]);
1328 piix_init_pcs(pdev, port_info, 1356 piix_init_pcs(pdev, port_info,
1329 piix_map_db_table[ent->driver_data]); 1357 piix_map_db_table[ent->driver_data]);
1330 } 1358 }
1331 1359
1332 /* apply IOCFG bit18 quirk */ 1360 /* apply IOCFG bit18 quirk */
1333 piix_iocfg_bit18_quirk(pdev); 1361 piix_iocfg_bit18_quirk(pdev);
1334 1362
1335 /* On ICH5, some BIOSen disable the interrupt using the 1363 /* On ICH5, some BIOSen disable the interrupt using the
1336 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. 1364 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1337 * On ICH6, this bit has the same effect, but only when 1365 * On ICH6, this bit has the same effect, but only when
1338 * MSI is disabled (and it is disabled, as we don't use 1366 * MSI is disabled (and it is disabled, as we don't use
1339 * message-signalled interrupts currently). 1367 * message-signalled interrupts currently).
1340 */ 1368 */
1341 if (port_flags & PIIX_FLAG_CHECKINTR) 1369 if (port_flags & PIIX_FLAG_CHECKINTR)
1342 pci_intx(pdev, 1); 1370 pci_intx(pdev, 1);
1343 1371
1344 if (piix_check_450nx_errata(pdev)) { 1372 if (piix_check_450nx_errata(pdev)) {
1345 /* This writes into the master table but it does not 1373 /* This writes into the master table but it does not
1346 really matter for this errata as we will apply it to 1374 really matter for this errata as we will apply it to
1347 all the PIIX devices on the board */ 1375 all the PIIX devices on the board */
1348 port_info[0].mwdma_mask = 0; 1376 port_info[0].mwdma_mask = 0;
1349 port_info[0].udma_mask = 0; 1377 port_info[0].udma_mask = 0;
1350 port_info[1].mwdma_mask = 0; 1378 port_info[1].mwdma_mask = 0;
1351 port_info[1].udma_mask = 0; 1379 port_info[1].udma_mask = 0;
1352 } 1380 }
1353 return ata_pci_init_one(pdev, ppi); 1381 return ata_pci_init_one(pdev, ppi);
1354 } 1382 }
1355 1383
1356 static int __init piix_init(void) 1384 static int __init piix_init(void)
1357 { 1385 {
1358 int rc; 1386 int rc;
1359 1387
1360 DPRINTK("pci_register_driver\n"); 1388 DPRINTK("pci_register_driver\n");
1361 rc = pci_register_driver(&piix_pci_driver); 1389 rc = pci_register_driver(&piix_pci_driver);
1362 if (rc) 1390 if (rc)
1363 return rc; 1391 return rc;
1364 1392
1365 in_module_init = 0; 1393 in_module_init = 0;
1366 1394
1367 DPRINTK("done\n"); 1395 DPRINTK("done\n");
1368 return 0; 1396 return 0;
1369 } 1397 }
1370 1398
1371 static void __exit piix_exit(void) 1399 static void __exit piix_exit(void)
1372 { 1400 {
1373 pci_unregister_driver(&piix_pci_driver); 1401 pci_unregister_driver(&piix_pci_driver);
1374 } 1402 }
1375 1403
1376 module_init(piix_init); 1404 module_init(piix_init);
1377 module_exit(piix_exit); 1405 module_exit(piix_exit);
1378 1406