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Commit 04d8a9db89f00dee78d792d094dc573784ead643

Authored by Julia Lawall
Committed by Matt Turner
1 parent a8a8a669ea
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

arch/alpha/kernel/sys_ruffian.c: Use DIV_ROUND_CLOSEST 

The kernel.h macro DIV_ROUND_CLOSEST performs the computation (x + d/2)/d
but is perhaps more readable.

The semantic patch that makes this change is as follows:
(http://www.emn.fr/x-info/coccinelle/)

// <smpl>
@haskernel@
@@

@depends on haskernel@
expression x,__divisor;
@@

- (((x) + ((__divisor) / 2)) / (__divisor))
+ DIV_ROUND_CLOSEST(x,__divisor)
// </smpl>

Signed-off-by: Julia Lawall <julia@diku.dk>
Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
Cc: Richard Henderson <rth@twiddle.net>
Signed-off-by: Matt Turner <mattst88@gmail.com>

Showing 1 changed file with 1 additions and 1 deletions Inline Diff

arch/alpha/kernel/sys_ruffian.c
Diff comments   View file @ 04d8a9d
1 /* 1 /*
2 * linux/arch/alpha/kernel/sys_ruffian.c 2 * linux/arch/alpha/kernel/sys_ruffian.c
3 * 3 *
4 * Copyright (C) 1995 David A Rusling 4 * Copyright (C) 1995 David A Rusling
5 * Copyright (C) 1996 Jay A Estabrook 5 * Copyright (C) 1996 Jay A Estabrook
6 * Copyright (C) 1998, 1999, 2000 Richard Henderson 6 * Copyright (C) 1998, 1999, 2000 Richard Henderson
7 * 7 *
8 * Code supporting the RUFFIAN. 8 * Code supporting the RUFFIAN.
9 */ 9 */
10 10
11 #include <linux/kernel.h> 11 #include <linux/kernel.h>
12 #include <linux/types.h> 12 #include <linux/types.h>
13 #include <linux/mm.h> 13 #include <linux/mm.h>
14 #include <linux/sched.h> 14 #include <linux/sched.h>
15 #include <linux/pci.h> 15 #include <linux/pci.h>
16 #include <linux/ioport.h> 16 #include <linux/ioport.h>
17 #include <linux/timex.h> 17 #include <linux/timex.h>
18 #include <linux/init.h> 18 #include <linux/init.h>
19 19
20 #include <asm/ptrace.h> 20 #include <asm/ptrace.h>
21 #include <asm/system.h> 21 #include <asm/system.h>
22 #include <asm/dma.h> 22 #include <asm/dma.h>
23 #include <asm/irq.h> 23 #include <asm/irq.h>
24 #include <asm/mmu_context.h> 24 #include <asm/mmu_context.h>
25 #include <asm/io.h> 25 #include <asm/io.h>
26 #include <asm/pgtable.h> 26 #include <asm/pgtable.h>
27 #include <asm/core_cia.h> 27 #include <asm/core_cia.h>
28 #include <asm/tlbflush.h> 28 #include <asm/tlbflush.h>
29 #include <asm/8253pit.h> 29 #include <asm/8253pit.h>
30 30
31 #include "proto.h" 31 #include "proto.h"
32 #include "irq_impl.h" 32 #include "irq_impl.h"
33 #include "pci_impl.h" 33 #include "pci_impl.h"
34 #include "machvec_impl.h" 34 #include "machvec_impl.h"
35 35
36 36
37 static void __init 37 static void __init
38 ruffian_init_irq(void) 38 ruffian_init_irq(void)
39 { 39 {
40 /* Invert 6&7 for i82371 */ 40 /* Invert 6&7 for i82371 */
41 *(vulp)PYXIS_INT_HILO = 0x000000c0UL; mb(); 41 *(vulp)PYXIS_INT_HILO = 0x000000c0UL; mb();
42 *(vulp)PYXIS_INT_CNFG = 0x00002064UL; mb(); /* all clear */ 42 *(vulp)PYXIS_INT_CNFG = 0x00002064UL; mb(); /* all clear */
43 43
44 outb(0x11,0xA0); 44 outb(0x11,0xA0);
45 outb(0x08,0xA1); 45 outb(0x08,0xA1);
46 outb(0x02,0xA1); 46 outb(0x02,0xA1);
47 outb(0x01,0xA1); 47 outb(0x01,0xA1);
48 outb(0xFF,0xA1); 48 outb(0xFF,0xA1);
49 49
50 outb(0x11,0x20); 50 outb(0x11,0x20);
51 outb(0x00,0x21); 51 outb(0x00,0x21);
52 outb(0x04,0x21); 52 outb(0x04,0x21);
53 outb(0x01,0x21); 53 outb(0x01,0x21);
54 outb(0xFF,0x21); 54 outb(0xFF,0x21);
55 55
56 /* Finish writing the 82C59A PIC Operation Control Words */ 56 /* Finish writing the 82C59A PIC Operation Control Words */
57 outb(0x20,0xA0); 57 outb(0x20,0xA0);
58 outb(0x20,0x20); 58 outb(0x20,0x20);
59 59
60 init_i8259a_irqs(); 60 init_i8259a_irqs();
61 61
62 /* Not interested in the bogus interrupts (0,3,6), 62 /* Not interested in the bogus interrupts (0,3,6),
63 NMI (1), HALT (2), flash (5), or 21142 (8). */ 63 NMI (1), HALT (2), flash (5), or 21142 (8). */
64 init_pyxis_irqs(0x16f0000); 64 init_pyxis_irqs(0x16f0000);
65 65
66 common_init_isa_dma(); 66 common_init_isa_dma();
67 } 67 }
68 68
69 #define RUFFIAN_LATCH ((PIT_TICK_RATE + HZ / 2) / HZ) 69 #define RUFFIAN_LATCH DIV_ROUND_CLOSEST(PIT_TICK_RATE, HZ)
70 70
71 static void __init 71 static void __init
72 ruffian_init_rtc(void) 72 ruffian_init_rtc(void)
73 { 73 {
74 /* Ruffian does not have the RTC connected to the CPU timer 74 /* Ruffian does not have the RTC connected to the CPU timer
75 interrupt. Instead, it uses the PIT connected to IRQ 0. */ 75 interrupt. Instead, it uses the PIT connected to IRQ 0. */
76 76
77 /* Setup interval timer. */ 77 /* Setup interval timer. */
78 outb(0x34, 0x43); /* binary, mode 2, LSB/MSB, ch 0 */ 78 outb(0x34, 0x43); /* binary, mode 2, LSB/MSB, ch 0 */
79 outb(RUFFIAN_LATCH & 0xff, 0x40); /* LSB */ 79 outb(RUFFIAN_LATCH & 0xff, 0x40); /* LSB */
80 outb(RUFFIAN_LATCH >> 8, 0x40); /* MSB */ 80 outb(RUFFIAN_LATCH >> 8, 0x40); /* MSB */
81 81
82 outb(0xb6, 0x43); /* pit counter 2: speaker */ 82 outb(0xb6, 0x43); /* pit counter 2: speaker */
83 outb(0x31, 0x42); 83 outb(0x31, 0x42);
84 outb(0x13, 0x42); 84 outb(0x13, 0x42);
85 85
86 setup_irq(0, &timer_irqaction); 86 setup_irq(0, &timer_irqaction);
87 } 87 }
88 88
89 static void 89 static void
90 ruffian_kill_arch (int mode) 90 ruffian_kill_arch (int mode)
91 { 91 {
92 cia_kill_arch(mode); 92 cia_kill_arch(mode);
93 #if 0 93 #if 0
94 /* This only causes re-entry to ARCSBIOS */ 94 /* This only causes re-entry to ARCSBIOS */
95 /* Perhaps this works for other PYXIS as well? */ 95 /* Perhaps this works for other PYXIS as well? */
96 *(vuip) PYXIS_RESET = 0x0000dead; 96 *(vuip) PYXIS_RESET = 0x0000dead;
97 mb(); 97 mb();
98 #endif 98 #endif
99 } 99 }
100 100
101 /* 101 /*
102 * Interrupt routing: 102 * Interrupt routing:
103 * 103 *
104 * Primary bus 104 * Primary bus
105 * IdSel INTA INTB INTC INTD 105 * IdSel INTA INTB INTC INTD
106 * 21052 13 - - - - 106 * 21052 13 - - - -
107 * SIO 14 23 - - - 107 * SIO 14 23 - - -
108 * 21143 15 44 - - - 108 * 21143 15 44 - - -
109 * Slot 0 17 43 42 41 40 109 * Slot 0 17 43 42 41 40
110 * 110 *
111 * Secondary bus 111 * Secondary bus
112 * IdSel INTA INTB INTC INTD 112 * IdSel INTA INTB INTC INTD
113 * Slot 0 8 (18) 19 18 17 16 113 * Slot 0 8 (18) 19 18 17 16
114 * Slot 1 9 (19) 31 30 29 28 114 * Slot 1 9 (19) 31 30 29 28
115 * Slot 2 10 (20) 27 26 25 24 115 * Slot 2 10 (20) 27 26 25 24
116 * Slot 3 11 (21) 39 38 37 36 116 * Slot 3 11 (21) 39 38 37 36
117 * Slot 4 12 (22) 35 34 33 32 117 * Slot 4 12 (22) 35 34 33 32
118 * 53c875 13 (23) 20 - - - 118 * 53c875 13 (23) 20 - - -
119 * 119 *
120 */ 120 */
121 121
122 static int __init 122 static int __init
123 ruffian_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 123 ruffian_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
124 { 124 {
125 static char irq_tab[11][5] __initdata = { 125 static char irq_tab[11][5] __initdata = {
126 /*INT INTA INTB INTC INTD */ 126 /*INT INTA INTB INTC INTD */
127 {-1, -1, -1, -1, -1}, /* IdSel 13, 21052 */ 127 {-1, -1, -1, -1, -1}, /* IdSel 13, 21052 */
128 {-1, -1, -1, -1, -1}, /* IdSel 14, SIO */ 128 {-1, -1, -1, -1, -1}, /* IdSel 14, SIO */
129 {44, 44, 44, 44, 44}, /* IdSel 15, 21143 */ 129 {44, 44, 44, 44, 44}, /* IdSel 15, 21143 */
130 {-1, -1, -1, -1, -1}, /* IdSel 16, none */ 130 {-1, -1, -1, -1, -1}, /* IdSel 16, none */
131 {43, 43, 42, 41, 40}, /* IdSel 17, 64-bit slot */ 131 {43, 43, 42, 41, 40}, /* IdSel 17, 64-bit slot */
132 /* the next 6 are actually on PCI bus 1, across the bridge */ 132 /* the next 6 are actually on PCI bus 1, across the bridge */
133 {19, 19, 18, 17, 16}, /* IdSel 8, slot 0 */ 133 {19, 19, 18, 17, 16}, /* IdSel 8, slot 0 */
134 {31, 31, 30, 29, 28}, /* IdSel 9, slot 1 */ 134 {31, 31, 30, 29, 28}, /* IdSel 9, slot 1 */
135 {27, 27, 26, 25, 24}, /* IdSel 10, slot 2 */ 135 {27, 27, 26, 25, 24}, /* IdSel 10, slot 2 */
136 {39, 39, 38, 37, 36}, /* IdSel 11, slot 3 */ 136 {39, 39, 38, 37, 36}, /* IdSel 11, slot 3 */
137 {35, 35, 34, 33, 32}, /* IdSel 12, slot 4 */ 137 {35, 35, 34, 33, 32}, /* IdSel 12, slot 4 */
138 {20, 20, 20, 20, 20}, /* IdSel 13, 53c875 */ 138 {20, 20, 20, 20, 20}, /* IdSel 13, 53c875 */
139 }; 139 };
140 const long min_idsel = 13, max_idsel = 23, irqs_per_slot = 5; 140 const long min_idsel = 13, max_idsel = 23, irqs_per_slot = 5;
141 return COMMON_TABLE_LOOKUP; 141 return COMMON_TABLE_LOOKUP;
142 } 142 }
143 143
144 static u8 __init 144 static u8 __init
145 ruffian_swizzle(struct pci_dev *dev, u8 *pinp) 145 ruffian_swizzle(struct pci_dev *dev, u8 *pinp)
146 { 146 {
147 int slot, pin = *pinp; 147 int slot, pin = *pinp;
148 148
149 if (dev->bus->number == 0) { 149 if (dev->bus->number == 0) {
150 slot = PCI_SLOT(dev->devfn); 150 slot = PCI_SLOT(dev->devfn);
151 } 151 }
152 /* Check for the built-in bridge. */ 152 /* Check for the built-in bridge. */
153 else if (PCI_SLOT(dev->bus->self->devfn) == 13) { 153 else if (PCI_SLOT(dev->bus->self->devfn) == 13) {
154 slot = PCI_SLOT(dev->devfn) + 10; 154 slot = PCI_SLOT(dev->devfn) + 10;
155 } 155 }
156 else 156 else
157 { 157 {
158 /* Must be a card-based bridge. */ 158 /* Must be a card-based bridge. */
159 do { 159 do {
160 if (PCI_SLOT(dev->bus->self->devfn) == 13) { 160 if (PCI_SLOT(dev->bus->self->devfn) == 13) {
161 slot = PCI_SLOT(dev->devfn) + 10; 161 slot = PCI_SLOT(dev->devfn) + 10;
162 break; 162 break;
163 } 163 }
164 pin = pci_swizzle_interrupt_pin(dev, pin); 164 pin = pci_swizzle_interrupt_pin(dev, pin);
165 165
166 /* Move up the chain of bridges. */ 166 /* Move up the chain of bridges. */
167 dev = dev->bus->self; 167 dev = dev->bus->self;
168 /* Slot of the next bridge. */ 168 /* Slot of the next bridge. */
169 slot = PCI_SLOT(dev->devfn); 169 slot = PCI_SLOT(dev->devfn);
170 } while (dev->bus->self); 170 } while (dev->bus->self);
171 } 171 }
172 *pinp = pin; 172 *pinp = pin;
173 return slot; 173 return slot;
174 } 174 }
175 175
176 #ifdef BUILDING_FOR_MILO 176 #ifdef BUILDING_FOR_MILO
177 /* 177 /*
178 * The DeskStation Ruffian motherboard firmware does not place 178 * The DeskStation Ruffian motherboard firmware does not place
179 * the memory size in the PALimpure area. Therefore, we use 179 * the memory size in the PALimpure area. Therefore, we use
180 * the Bank Configuration Registers in PYXIS to obtain the size. 180 * the Bank Configuration Registers in PYXIS to obtain the size.
181 */ 181 */
182 static unsigned long __init 182 static unsigned long __init
183 ruffian_get_bank_size(unsigned long offset) 183 ruffian_get_bank_size(unsigned long offset)
184 { 184 {
185 unsigned long bank_addr, bank, ret = 0; 185 unsigned long bank_addr, bank, ret = 0;
186 186
187 /* Valid offsets are: 0x800, 0x840 and 0x880 187 /* Valid offsets are: 0x800, 0x840 and 0x880
188 since Ruffian only uses three banks. */ 188 since Ruffian only uses three banks. */
189 bank_addr = (unsigned long)PYXIS_MCR + offset; 189 bank_addr = (unsigned long)PYXIS_MCR + offset;
190 bank = *(vulp)bank_addr; 190 bank = *(vulp)bank_addr;
191 191
192 /* Check BANK_ENABLE */ 192 /* Check BANK_ENABLE */
193 if (bank & 0x01) { 193 if (bank & 0x01) {
194 static unsigned long size[] __initdata = { 194 static unsigned long size[] __initdata = {
195 0x40000000UL, /* 0x00, 1G */ 195 0x40000000UL, /* 0x00, 1G */
196 0x20000000UL, /* 0x02, 512M */ 196 0x20000000UL, /* 0x02, 512M */
197 0x10000000UL, /* 0x04, 256M */ 197 0x10000000UL, /* 0x04, 256M */
198 0x08000000UL, /* 0x06, 128M */ 198 0x08000000UL, /* 0x06, 128M */
199 0x04000000UL, /* 0x08, 64M */ 199 0x04000000UL, /* 0x08, 64M */
200 0x02000000UL, /* 0x0a, 32M */ 200 0x02000000UL, /* 0x0a, 32M */
201 0x01000000UL, /* 0x0c, 16M */ 201 0x01000000UL, /* 0x0c, 16M */
202 0x00800000UL, /* 0x0e, 8M */ 202 0x00800000UL, /* 0x0e, 8M */
203 0x80000000UL, /* 0x10, 2G */ 203 0x80000000UL, /* 0x10, 2G */
204 }; 204 };
205 205
206 bank = (bank & 0x1e) >> 1; 206 bank = (bank & 0x1e) >> 1;
207 if (bank < ARRAY_SIZE(size)) 207 if (bank < ARRAY_SIZE(size))
208 ret = size[bank]; 208 ret = size[bank];
209 } 209 }
210 210
211 return ret; 211 return ret;
212 } 212 }
213 #endif /* BUILDING_FOR_MILO */ 213 #endif /* BUILDING_FOR_MILO */
214 214
215 /* 215 /*
216 * The System Vector 216 * The System Vector
217 */ 217 */
218 218
219 struct alpha_machine_vector ruffian_mv __initmv = { 219 struct alpha_machine_vector ruffian_mv __initmv = {
220 .vector_name = "Ruffian", 220 .vector_name = "Ruffian",
221 DO_EV5_MMU, 221 DO_EV5_MMU,
222 DO_DEFAULT_RTC, 222 DO_DEFAULT_RTC,
223 DO_PYXIS_IO, 223 DO_PYXIS_IO,
224 .machine_check = cia_machine_check, 224 .machine_check = cia_machine_check,
225 .max_isa_dma_address = ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS, 225 .max_isa_dma_address = ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS,
226 .min_io_address = DEFAULT_IO_BASE, 226 .min_io_address = DEFAULT_IO_BASE,
227 .min_mem_address = DEFAULT_MEM_BASE, 227 .min_mem_address = DEFAULT_MEM_BASE,
228 .pci_dac_offset = PYXIS_DAC_OFFSET, 228 .pci_dac_offset = PYXIS_DAC_OFFSET,
229 229
230 .nr_irqs = 48, 230 .nr_irqs = 48,
231 .device_interrupt = pyxis_device_interrupt, 231 .device_interrupt = pyxis_device_interrupt,
232 232
233 .init_arch = pyxis_init_arch, 233 .init_arch = pyxis_init_arch,
234 .init_irq = ruffian_init_irq, 234 .init_irq = ruffian_init_irq,
235 .init_rtc = ruffian_init_rtc, 235 .init_rtc = ruffian_init_rtc,
236 .init_pci = cia_init_pci, 236 .init_pci = cia_init_pci,
237 .kill_arch = ruffian_kill_arch, 237 .kill_arch = ruffian_kill_arch,
238 .pci_map_irq = ruffian_map_irq, 238 .pci_map_irq = ruffian_map_irq,
239 .pci_swizzle = ruffian_swizzle, 239 .pci_swizzle = ruffian_swizzle,
240 }; 240 };
241 ALIAS_MV(ruffian) 241 ALIAS_MV(ruffian)
242 242