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Commit 080909503664641432cc8adf2ee2084775fd992a

Authored by Linus Torvalds 2012-09-06 10:41:58 +0800

Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches

Merge tag 'mmc-fixes-for-3.6-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc

Pull MMC fixes from Chris Ball:
 - a firmware bug on several Samsung MoviNAND eMMC models causes
   permanent corruption on the device when secure erase and secure trim
   requests are made, so we disable those requests on these eMMC devices.
 - atmel-mci: fix a hang with some SD cards by waiting for not-busy flag.
 - dw_mmc: low-power mode breaks SDIO interrupts; fix PIO error handling;
   fix handling of error interrupts.
 - mxs-mmc: fix deadlocks; fix compile error due to dma.h arch change.
 - omap: fix broken PIO mode causing memory corruption.
 - sdhci-esdhc: fix card detection.

* tag 'mmc-fixes-for-3.6-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc:
  mmc: omap: fix broken PIO mode
  mmc: card: Skip secure erase on MoviNAND; causes unrecoverable corruption.
  mmc: dw_mmc: Disable low power mode if SDIO interrupts are used
  mmc: dw_mmc: fix error handling in PIO mode
  mmc: dw_mmc: correct mishandling error interrupt
  mmc: dw_mmc: amend using error interrupt status
  mmc: atmel-mci: not busy flag has also to be used for read operations
  mmc: sdhci-esdhc: break out early if clock is 0
  mmc: mxs-mmc: fix deadlock caused by recursion loop
  mmc: mxs-mmc: fix deadlock in SDIO IRQ case
  mmc: bfin_sdh: fix dma_desc_array build error

Showing 8 changed files Inline Diff

drivers/mmc/card/block.c
drivers/mmc/host/atmel-mci.c
drivers/mmc/host/bfin_sdh.c
drivers/mmc/host/dw_mmc.c
drivers/mmc/host/mxs-mmc.c
drivers/mmc/host/omap.c
drivers/mmc/host/sdhci-esdhc.h
include/linux/mmc/card.h

drivers/mmc/card/block.c

Diff comments View file @ 0809095

 /*
  * Block driver for media (i.e., flash cards)
  *
  * Copyright 2002 Hewlett-Packard Company
  * Copyright 2005-2008 Pierre Ossman
  *
  * Use consistent with the GNU GPL is permitted,
  * provided that this copyright notice is
  * preserved in its entirety in all copies and derived works.
  *
  * HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
  * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
  * FITNESS FOR ANY PARTICULAR PURPOSE.
  *
  * Many thanks to Alessandro Rubini and Jonathan Corbet!
  *
  * Author:  Andrew Christian
  *          28 May 2002
  */
 #include <linux/moduleparam.h>
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/fs.h>
 #include <linux/slab.h>
 #include <linux/errno.h>
 #include <linux/hdreg.h>
 #include <linux/kdev_t.h>
 #include <linux/blkdev.h>
 #include <linux/mutex.h>
 #include <linux/scatterlist.h>
 #include <linux/string_helpers.h>
 #include <linux/delay.h>
 #include <linux/capability.h>
 #include <linux/compat.h>
 #include <linux/mmc/ioctl.h>
 #include <linux/mmc/card.h>
 #include <linux/mmc/host.h>
 #include <linux/mmc/mmc.h>
 #include <linux/mmc/sd.h>
 #include <asm/uaccess.h>
 #include "queue.h"
 MODULE_ALIAS("mmc:block");
 #ifdef MODULE_PARAM_PREFIX
 #undef MODULE_PARAM_PREFIX
 #endif
 #define MODULE_PARAM_PREFIX "mmcblk."
 #define INAND_CMD38_ARG_EXT_CSD  113
 #define INAND_CMD38_ARG_ERASE    0x00
 #define INAND_CMD38_ARG_TRIM     0x01
 #define INAND_CMD38_ARG_SECERASE 0x80
 #define INAND_CMD38_ARG_SECTRIM1 0x81
 #define INAND_CMD38_ARG_SECTRIM2 0x88
 static DEFINE_MUTEX(block_mutex);
 /*
  * The defaults come from config options but can be overriden by module
  * or bootarg options.
  */
 static int perdev_minors = CONFIG_MMC_BLOCK_MINORS;
 /*
  * We've only got one major, so number of mmcblk devices is
  * limited to 256 / number of minors per device.
  */
 static int max_devices;
 /* 256 minors, so at most 256 separate devices */
 static DECLARE_BITMAP(dev_use, 256);
 static DECLARE_BITMAP(name_use, 256);
 /*
  * There is one mmc_blk_data per slot.
  */
 struct mmc_blk_data {
 	spinlock_t	lock;
 	struct gendisk	*disk;
 	struct mmc_queue queue;
 	struct list_head part;
 	unsigned int	flags;
 #define MMC_BLK_CMD23	(1 << 0)	/* Can do SET_BLOCK_COUNT for multiblock */
 #define MMC_BLK_REL_WR	(1 << 1)	/* MMC Reliable write support */
 	unsigned int	usage;
 	unsigned int	read_only;
 	unsigned int	part_type;
 	unsigned int	name_idx;
 	unsigned int	reset_done;
 #define MMC_BLK_READ		BIT(0)
 #define MMC_BLK_WRITE		BIT(1)
 #define MMC_BLK_DISCARD		BIT(2)
 #define MMC_BLK_SECDISCARD	BIT(3)
 	/*
 	 * Only set in main mmc_blk_data associated
 	 * with mmc_card with mmc_set_drvdata, and keeps
 	 * track of the current selected device partition.
 	 */
 	unsigned int	part_curr;
 	struct device_attribute force_ro;
 	struct device_attribute power_ro_lock;
 	int	area_type;
 };
 static DEFINE_MUTEX(open_lock);
 enum mmc_blk_status {
 	MMC_BLK_SUCCESS = 0,
 	MMC_BLK_PARTIAL,
 	MMC_BLK_CMD_ERR,
 	MMC_BLK_RETRY,
 	MMC_BLK_ABORT,
 	MMC_BLK_DATA_ERR,
 	MMC_BLK_ECC_ERR,
 	MMC_BLK_NOMEDIUM,
 };
 module_param(perdev_minors, int, 0444);
 MODULE_PARM_DESC(perdev_minors, "Minors numbers to allocate per device");
 static struct mmc_blk_data *mmc_blk_get(struct gendisk *disk)
 {
 	struct mmc_blk_data *md;
 	mutex_lock(&open_lock);
 	md = disk->private_data;
 	if (md && md->usage == 0)
 		md = NULL;
 	if (md)
 		md->usage++;
 	mutex_unlock(&open_lock);
 	return md;
 }
 static inline int mmc_get_devidx(struct gendisk *disk)
 {
 	int devmaj = MAJOR(disk_devt(disk));
 	int devidx = MINOR(disk_devt(disk)) / perdev_minors;
 	if (!devmaj)
 		devidx = disk->first_minor / perdev_minors;
 	return devidx;
 }
 static void mmc_blk_put(struct mmc_blk_data *md)
 {
 	mutex_lock(&open_lock);
 	md->usage--;
 	if (md->usage == 0) {
 		int devidx = mmc_get_devidx(md->disk);
 		blk_cleanup_queue(md->queue.queue);
 		__clear_bit(devidx, dev_use);
 		put_disk(md->disk);
 		kfree(md);
 	}
 	mutex_unlock(&open_lock);
 }
 static ssize_t power_ro_lock_show(struct device *dev,
 		struct device_attribute *attr, char *buf)
 {
 	int ret;
 	struct mmc_blk_data *md = mmc_blk_get(dev_to_disk(dev));
 	struct mmc_card *card = md->queue.card;
 	int locked = 0;
 	if (card->ext_csd.boot_ro_lock & EXT_CSD_BOOT_WP_B_PERM_WP_EN)
 		locked = 2;
 	else if (card->ext_csd.boot_ro_lock & EXT_CSD_BOOT_WP_B_PWR_WP_EN)
 		locked = 1;
 	ret = snprintf(buf, PAGE_SIZE, "%d\n", locked);
 	return ret;
 }
 static ssize_t power_ro_lock_store(struct device *dev,
 		struct device_attribute *attr, const char *buf, size_t count)
 {
 	int ret;
 	struct mmc_blk_data *md, *part_md;
 	struct mmc_card *card;
 	unsigned long set;
 	if (kstrtoul(buf, 0, &set))
 		return -EINVAL;
 	if (set != 1)
 		return count;
 	md = mmc_blk_get(dev_to_disk(dev));
 	card = md->queue.card;
 	mmc_claim_host(card->host);
 	ret = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_WP,
 				card->ext_csd.boot_ro_lock |
 				EXT_CSD_BOOT_WP_B_PWR_WP_EN,
 				card->ext_csd.part_time);
 	if (ret)
 		pr_err("%s: Locking boot partition ro until next power on failed: %d\n", md->disk->disk_name, ret);
 	else
 		card->ext_csd.boot_ro_lock |= EXT_CSD_BOOT_WP_B_PWR_WP_EN;
 	mmc_release_host(card->host);
 	if (!ret) {
 		pr_info("%s: Locking boot partition ro until next power on\n",
 			md->disk->disk_name);
 		set_disk_ro(md->disk, 1);
 		list_for_each_entry(part_md, &md->part, part)
 			if (part_md->area_type == MMC_BLK_DATA_AREA_BOOT) {
 				pr_info("%s: Locking boot partition ro until next power on\n", part_md->disk->disk_name);
 				set_disk_ro(part_md->disk, 1);
 			}
 	}
 	mmc_blk_put(md);
 	return count;
 }
 static ssize_t force_ro_show(struct device *dev, struct device_attribute *attr,
 			     char *buf)
 {
 	int ret;
 	struct mmc_blk_data *md = mmc_blk_get(dev_to_disk(dev));
 	ret = snprintf(buf, PAGE_SIZE, "%d",
 		       get_disk_ro(dev_to_disk(dev)) ^
 		       md->read_only);
 	mmc_blk_put(md);
 	return ret;
 }
 static ssize_t force_ro_store(struct device *dev, struct device_attribute *attr,
 			      const char *buf, size_t count)
 {
 	int ret;
 	char *end;
 	struct mmc_blk_data *md = mmc_blk_get(dev_to_disk(dev));
 	unsigned long set = simple_strtoul(buf, &end, 0);
 	if (end == buf) {
 		ret = -EINVAL;
 		goto out;
 	}
 	set_disk_ro(dev_to_disk(dev), set || md->read_only);
 	ret = count;
 out:
 	mmc_blk_put(md);
 	return ret;
 }
 static int mmc_blk_open(struct block_device *bdev, fmode_t mode)
 {
 	struct mmc_blk_data *md = mmc_blk_get(bdev->bd_disk);
 	int ret = -ENXIO;
 	mutex_lock(&block_mutex);
 	if (md) {
 		if (md->usage == 2)
 			check_disk_change(bdev);
 		ret = 0;
 		if ((mode & FMODE_WRITE) && md->read_only) {
 			mmc_blk_put(md);
 			ret = -EROFS;
 		}
 	}
 	mutex_unlock(&block_mutex);
 	return ret;
 }
 static int mmc_blk_release(struct gendisk *disk, fmode_t mode)
 {
 	struct mmc_blk_data *md = disk->private_data;
 	mutex_lock(&block_mutex);
 	mmc_blk_put(md);
 	mutex_unlock(&block_mutex);
 	return 0;
 }
 static int
 mmc_blk_getgeo(struct block_device *bdev, struct hd_geometry *geo)
 {
 	geo->cylinders = get_capacity(bdev->bd_disk) / (4 * 16);
 	geo->heads = 4;
 	geo->sectors = 16;
 	return 0;
 }
 struct mmc_blk_ioc_data {
 	struct mmc_ioc_cmd ic;
 	unsigned char *buf;
 	u64 buf_bytes;
 };
 static struct mmc_blk_ioc_data *mmc_blk_ioctl_copy_from_user(
 	struct mmc_ioc_cmd __user *user)
 {
 	struct mmc_blk_ioc_data *idata;
 	int err;
 	idata = kzalloc(sizeof(*idata), GFP_KERNEL);
 	if (!idata) {
 		err = -ENOMEM;
 		goto out;
 	}
 	if (copy_from_user(&idata->ic, user, sizeof(idata->ic))) {
 		err = -EFAULT;
 		goto idata_err;
 	}
 	idata->buf_bytes = (u64) idata->ic.blksz * idata->ic.blocks;
 	if (idata->buf_bytes > MMC_IOC_MAX_BYTES) {
 		err = -EOVERFLOW;
 		goto idata_err;
 	}
 	if (!idata->buf_bytes)
 		return idata;
 	idata->buf = kzalloc(idata->buf_bytes, GFP_KERNEL);
 	if (!idata->buf) {
 		err = -ENOMEM;
 		goto idata_err;
 	}
 	if (copy_from_user(idata->buf, (void __user *)(unsigned long)
 					idata->ic.data_ptr, idata->buf_bytes)) {
 		err = -EFAULT;
 		goto copy_err;
 	}
 	return idata;
 copy_err:
 	kfree(idata->buf);
 idata_err:
 	kfree(idata);
 out:
 	return ERR_PTR(err);
 }
 static int mmc_blk_ioctl_cmd(struct block_device *bdev,
 	struct mmc_ioc_cmd __user *ic_ptr)
 {
 	struct mmc_blk_ioc_data *idata;
 	struct mmc_blk_data *md;
 	struct mmc_card *card;
 	struct mmc_command cmd = {0};
 	struct mmc_data data = {0};
 	struct mmc_request mrq = {NULL};
 	struct scatterlist sg;
 	int err;
 	/*
 	 * The caller must have CAP_SYS_RAWIO, and must be calling this on the
 	 * whole block device, not on a partition.  This prevents overspray
 	 * between sibling partitions.
 	 */
 	if ((!capable(CAP_SYS_RAWIO)) || (bdev != bdev->bd_contains))
 		return -EPERM;
 	idata = mmc_blk_ioctl_copy_from_user(ic_ptr);
 	if (IS_ERR(idata))
 		return PTR_ERR(idata);
 	md = mmc_blk_get(bdev->bd_disk);
 	if (!md) {
 		err = -EINVAL;
 		goto cmd_err;
 	}
 	card = md->queue.card;
 	if (IS_ERR(card)) {
 		err = PTR_ERR(card);
 		goto cmd_done;
 	}
 	cmd.opcode = idata->ic.opcode;
 	cmd.arg = idata->ic.arg;
 	cmd.flags = idata->ic.flags;
 	if (idata->buf_bytes) {
 		data.sg = &sg;
 		data.sg_len = 1;
 		data.blksz = idata->ic.blksz;
 		data.blocks = idata->ic.blocks;
 		sg_init_one(data.sg, idata->buf, idata->buf_bytes);
 		if (idata->ic.write_flag)
 			data.flags = MMC_DATA_WRITE;
 		else
 			data.flags = MMC_DATA_READ;
 		/* data.flags must already be set before doing this. */
 		mmc_set_data_timeout(&data, card);
 		/* Allow overriding the timeout_ns for empirical tuning. */
 		if (idata->ic.data_timeout_ns)
 			data.timeout_ns = idata->ic.data_timeout_ns;
 		if ((cmd.flags & MMC_RSP_R1B) == MMC_RSP_R1B) {
 			/*
 			 * Pretend this is a data transfer and rely on the
 			 * host driver to compute timeout.  When all host
 			 * drivers support cmd.cmd_timeout for R1B, this
 			 * can be changed to:
 			 *
 			 *     mrq.data = NULL;
 			 *     cmd.cmd_timeout = idata->ic.cmd_timeout_ms;
 			 */
 			data.timeout_ns = idata->ic.cmd_timeout_ms * 1000000;
 		}
 		mrq.data = &data;
 	}
 	mrq.cmd = &cmd;
 	mmc_claim_host(card->host);
 	if (idata->ic.is_acmd) {
 		err = mmc_app_cmd(card->host, card);
 		if (err)
 			goto cmd_rel_host;
 	}
 	mmc_wait_for_req(card->host, &mrq);
 	if (cmd.error) {
 		dev_err(mmc_dev(card->host), "%s: cmd error %d\n",
 						__func__, cmd.error);
 		err = cmd.error;
 		goto cmd_rel_host;
 	}
 	if (data.error) {
 		dev_err(mmc_dev(card->host), "%s: data error %d\n",
 						__func__, data.error);
 		err = data.error;
 		goto cmd_rel_host;
 	}
 	/*
 	 * According to the SD specs, some commands require a delay after
 	 * issuing the command.
 	 */
 	if (idata->ic.postsleep_min_us)
 		usleep_range(idata->ic.postsleep_min_us, idata->ic.postsleep_max_us);
 	if (copy_to_user(&(ic_ptr->response), cmd.resp, sizeof(cmd.resp))) {
 		err = -EFAULT;
 		goto cmd_rel_host;
 	}
 	if (!idata->ic.write_flag) {
 		if (copy_to_user((void __user *)(unsigned long) idata->ic.data_ptr,
 						idata->buf, idata->buf_bytes)) {
 			err = -EFAULT;
 			goto cmd_rel_host;
 		}
 	}
 cmd_rel_host:
 	mmc_release_host(card->host);
 cmd_done:
 	mmc_blk_put(md);
 cmd_err:
 	kfree(idata->buf);
 	kfree(idata);
 	return err;
 }
 static int mmc_blk_ioctl(struct block_device *bdev, fmode_t mode,
 	unsigned int cmd, unsigned long arg)
 {
 	int ret = -EINVAL;
 	if (cmd == MMC_IOC_CMD)
 		ret = mmc_blk_ioctl_cmd(bdev, (struct mmc_ioc_cmd __user *)arg);
 	return ret;
 }
 #ifdef CONFIG_COMPAT
 static int mmc_blk_compat_ioctl(struct block_device *bdev, fmode_t mode,
 	unsigned int cmd, unsigned long arg)
 {
 	return mmc_blk_ioctl(bdev, mode, cmd, (unsigned long) compat_ptr(arg));
 }
 #endif
 static const struct block_device_operations mmc_bdops = {
 	.open			= mmc_blk_open,
 	.release		= mmc_blk_release,
 	.getgeo			= mmc_blk_getgeo,
 	.owner			= THIS_MODULE,
 	.ioctl			= mmc_blk_ioctl,
 #ifdef CONFIG_COMPAT
 	.compat_ioctl		= mmc_blk_compat_ioctl,
 #endif
 };
 static inline int mmc_blk_part_switch(struct mmc_card *card,
 				      struct mmc_blk_data *md)
 {
 	int ret;
 	struct mmc_blk_data *main_md = mmc_get_drvdata(card);
 	if (main_md->part_curr == md->part_type)
 		return 0;
 	if (mmc_card_mmc(card)) {
 		u8 part_config = card->ext_csd.part_config;
 		part_config &= ~EXT_CSD_PART_CONFIG_ACC_MASK;
 		part_config |= md->part_type;
 		ret = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
 				 EXT_CSD_PART_CONFIG, part_config,
 				 card->ext_csd.part_time);
 		if (ret)
 			return ret;
 		card->ext_csd.part_config = part_config;
 	}
 	main_md->part_curr = md->part_type;
 	return 0;
 }
 static u32 mmc_sd_num_wr_blocks(struct mmc_card *card)
 {
 	int err;
 	u32 result;
 	__be32 *blocks;
 	struct mmc_request mrq = {NULL};
 	struct mmc_command cmd = {0};
 	struct mmc_data data = {0};
 	struct scatterlist sg;
 	cmd.opcode = MMC_APP_CMD;
 	cmd.arg = card->rca << 16;
 	cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC;
 	err = mmc_wait_for_cmd(card->host, &cmd, 0);
 	if (err)
 		return (u32)-1;
 	if (!mmc_host_is_spi(card->host) && !(cmd.resp[0] & R1_APP_CMD))
 		return (u32)-1;
 	memset(&cmd, 0, sizeof(struct mmc_command));
 	cmd.opcode = SD_APP_SEND_NUM_WR_BLKS;
 	cmd.arg = 0;
 	cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_ADTC;
 	data.blksz = 4;
 	data.blocks = 1;
 	data.flags = MMC_DATA_READ;
 	data.sg = &sg;
 	data.sg_len = 1;
 	mmc_set_data_timeout(&data, card);
 	mrq.cmd = &cmd;
 	mrq.data = &data;
 	blocks = kmalloc(4, GFP_KERNEL);
 	if (!blocks)
 		return (u32)-1;
 	sg_init_one(&sg, blocks, 4);
 	mmc_wait_for_req(card->host, &mrq);
 	result = ntohl(*blocks);
 	kfree(blocks);
 	if (cmd.error || data.error)
 		result = (u32)-1;
 	return result;
 }
 static int send_stop(struct mmc_card *card, u32 *status)
 {
 	struct mmc_command cmd = {0};
 	int err;
 	cmd.opcode = MMC_STOP_TRANSMISSION;
 	cmd.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC;
 	err = mmc_wait_for_cmd(card->host, &cmd, 5);
 	if (err == 0)
 		*status = cmd.resp[0];
 	return err;
 }
 static int get_card_status(struct mmc_card *card, u32 *status, int retries)
 {
 	struct mmc_command cmd = {0};
 	int err;
 	cmd.opcode = MMC_SEND_STATUS;
 	if (!mmc_host_is_spi(card->host))
 		cmd.arg = card->rca << 16;
 	cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC;
 	err = mmc_wait_for_cmd(card->host, &cmd, retries);
 	if (err == 0)
 		*status = cmd.resp[0];
 	return err;
 }
 #define ERR_NOMEDIUM	3
 #define ERR_RETRY	2
 #define ERR_ABORT	1
 #define ERR_CONTINUE	0
 static int mmc_blk_cmd_error(struct request *req, const char *name, int error,
 	bool status_valid, u32 status)
 {
 	switch (error) {
 	case -EILSEQ:
 		/* response crc error, retry the r/w cmd */
 		pr_err("%s: %s sending %s command, card status %#x\n",
 			req->rq_disk->disk_name, "response CRC error",
 			name, status);
 		return ERR_RETRY;
 	case -ETIMEDOUT:
 		pr_err("%s: %s sending %s command, card status %#x\n",
 			req->rq_disk->disk_name, "timed out", name, status);
 		/* If the status cmd initially failed, retry the r/w cmd */
 		if (!status_valid)
 			return ERR_RETRY;
 		/*
 		 * If it was a r/w cmd crc error, or illegal command
 		 * (eg, issued in wrong state) then retry - we should
 		 * have corrected the state problem above.
 		 */
 		if (status & (R1_COM_CRC_ERROR | R1_ILLEGAL_COMMAND))
 			return ERR_RETRY;
 		/* Otherwise abort the command */
 		return ERR_ABORT;
 	default:
 		/* We don't understand the error code the driver gave us */
 		pr_err("%s: unknown error %d sending read/write command, card status %#x\n",
 		       req->rq_disk->disk_name, error, status);
 		return ERR_ABORT;
 	}
 }
 /*
  * Initial r/w and stop cmd error recovery.
  * We don't know whether the card received the r/w cmd or not, so try to
  * restore things back to a sane state.  Essentially, we do this as follows:
  * - Obtain card status.  If the first attempt to obtain card status fails,
  *   the status word will reflect the failed status cmd, not the failed
  *   r/w cmd.  If we fail to obtain card status, it suggests we can no
  *   longer communicate with the card.
  * - Check the card state.  If the card received the cmd but there was a
  *   transient problem with the response, it might still be in a data transfer
  *   mode.  Try to send it a stop command.  If this fails, we can't recover.
  * - If the r/w cmd failed due to a response CRC error, it was probably
  *   transient, so retry the cmd.
  * - If the r/w cmd timed out, but we didn't get the r/w cmd status, retry.
  * - If the r/w cmd timed out, and the r/w cmd failed due to CRC error or
  *   illegal cmd, retry.
  * Otherwise we don't understand what happened, so abort.
  */
 static int mmc_blk_cmd_recovery(struct mmc_card *card, struct request *req,
 	struct mmc_blk_request *brq, int *ecc_err)
 {
 	bool prev_cmd_status_valid = true;
 	u32 status, stop_status = 0;
 	int err, retry;
 	if (mmc_card_removed(card))
 		return ERR_NOMEDIUM;
 	/*
 	 * Try to get card status which indicates both the card state
 	 * and why there was no response.  If the first attempt fails,
 	 * we can't be sure the returned status is for the r/w command.
 	 */
 	for (retry = 2; retry >= 0; retry--) {
 		err = get_card_status(card, &status, 0);
 		if (!err)
 			break;
 		prev_cmd_status_valid = false;
 		pr_err("%s: error %d sending status command, %sing\n",
 		       req->rq_disk->disk_name, err, retry ? "retry" : "abort");
 	}
 	/* We couldn't get a response from the card.  Give up. */
 	if (err) {
 		/* Check if the card is removed */
 		if (mmc_detect_card_removed(card->host))
 			return ERR_NOMEDIUM;
 		return ERR_ABORT;
 	}
 	/* Flag ECC errors */
 	if ((status & R1_CARD_ECC_FAILED) ||
 	    (brq->stop.resp[0] & R1_CARD_ECC_FAILED) ||
 	    (brq->cmd.resp[0] & R1_CARD_ECC_FAILED))
 		*ecc_err = 1;
 	/*
 	 * Check the current card state.  If it is in some data transfer
 	 * mode, tell it to stop (and hopefully transition back to TRAN.)
 	 */
 	if (R1_CURRENT_STATE(status) == R1_STATE_DATA ||
 	    R1_CURRENT_STATE(status) == R1_STATE_RCV) {
 		err = send_stop(card, &stop_status);
 		if (err)
 			pr_err("%s: error %d sending stop command\n",
 			       req->rq_disk->disk_name, err);
 		/*
 		 * If the stop cmd also timed out, the card is probably
 		 * not present, so abort.  Other errors are bad news too.
 		 */
 		if (err)
 			return ERR_ABORT;
 		if (stop_status & R1_CARD_ECC_FAILED)
 			*ecc_err = 1;
 	}
 	/* Check for set block count errors */
 	if (brq->sbc.error)
 		return mmc_blk_cmd_error(req, "SET_BLOCK_COUNT", brq->sbc.error,
 				prev_cmd_status_valid, status);
 	/* Check for r/w command errors */
 	if (brq->cmd.error)
 		return mmc_blk_cmd_error(req, "r/w cmd", brq->cmd.error,
 				prev_cmd_status_valid, status);
 	/* Data errors */
 	if (!brq->stop.error)
 		return ERR_CONTINUE;
 	/* Now for stop errors.  These aren't fatal to the transfer. */
 	pr_err("%s: error %d sending stop command, original cmd response %#x, card status %#x\n",
 	       req->rq_disk->disk_name, brq->stop.error,
 	       brq->cmd.resp[0], status);
 	/*
 	 * Subsitute in our own stop status as this will give the error
 	 * state which happened during the execution of the r/w command.
 	 */
 	if (stop_status) {
 		brq->stop.resp[0] = stop_status;
 		brq->stop.error = 0;
 	}
 	return ERR_CONTINUE;
 }
 static int mmc_blk_reset(struct mmc_blk_data *md, struct mmc_host *host,
 			 int type)
 {
 	int err;
 	if (md->reset_done & type)
 		return -EEXIST;
 	md->reset_done |= type;
 	err = mmc_hw_reset(host);
 	/* Ensure we switch back to the correct partition */
 	if (err != -EOPNOTSUPP) {
 		struct mmc_blk_data *main_md = mmc_get_drvdata(host->card);
 		int part_err;
 		main_md->part_curr = main_md->part_type;
 		part_err = mmc_blk_part_switch(host->card, md);
 		if (part_err) {
 			/*
 			 * We have failed to get back into the correct
 			 * partition, so we need to abort the whole request.
 			 */
 			return -ENODEV;
 		}
 	}
 	return err;
 }
 static inline void mmc_blk_reset_success(struct mmc_blk_data *md, int type)
 {
 	md->reset_done &= ~type;
 }
 static int mmc_blk_issue_discard_rq(struct mmc_queue *mq, struct request *req)
 {
 	struct mmc_blk_data *md = mq->data;
 	struct mmc_card *card = md->queue.card;
 	unsigned int from, nr, arg;
 	int err = 0, type = MMC_BLK_DISCARD;
 	if (!mmc_can_erase(card)) {
 		err = -EOPNOTSUPP;
 		goto out;
 	}
 	from = blk_rq_pos(req);
 	nr = blk_rq_sectors(req);
 	if (mmc_can_discard(card))
 		arg = MMC_DISCARD_ARG;
 	else if (mmc_can_trim(card))
 		arg = MMC_TRIM_ARG;
 	else
 		arg = MMC_ERASE_ARG;
 retry:
 	if (card->quirks & MMC_QUIRK_INAND_CMD38) {
 		err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
 				 INAND_CMD38_ARG_EXT_CSD,
 				 arg == MMC_TRIM_ARG ?
 				 INAND_CMD38_ARG_TRIM :
 				 INAND_CMD38_ARG_ERASE,
 				 0);
 		if (err)
 			goto out;
 	}
 	err = mmc_erase(card, from, nr, arg);
 out:
 	if (err == -EIO && !mmc_blk_reset(md, card->host, type))
 		goto retry;
 	if (!err)
 		mmc_blk_reset_success(md, type);
 	blk_end_request(req, err, blk_rq_bytes(req));
 	return err ? 0 : 1;
 }
 static int mmc_blk_issue_secdiscard_rq(struct mmc_queue *mq,
 				       struct request *req)
 {
 	struct mmc_blk_data *md = mq->data;
 	struct mmc_card *card = md->queue.card;
 	unsigned int from, nr, arg, trim_arg, erase_arg;
 	int err = 0, type = MMC_BLK_SECDISCARD;
 	if (!(mmc_can_secure_erase_trim(card) || mmc_can_sanitize(card))) {
 		err = -EOPNOTSUPP;
 		goto out;
 	}
 	from = blk_rq_pos(req);
 	nr = blk_rq_sectors(req);
 	/* The sanitize operation is supported at v4.5 only */
 	if (mmc_can_sanitize(card)) {
 		erase_arg = MMC_ERASE_ARG;
 		trim_arg = MMC_TRIM_ARG;
 	} else {
 		erase_arg = MMC_SECURE_ERASE_ARG;
 		trim_arg = MMC_SECURE_TRIM1_ARG;
 	}
 	if (mmc_erase_group_aligned(card, from, nr))
 		arg = erase_arg;
 	else if (mmc_can_trim(card))
 		arg = trim_arg;
 	else {
 		err = -EINVAL;
 		goto out;
 	}
 retry:
 	if (card->quirks & MMC_QUIRK_INAND_CMD38) {
 		err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
 				 INAND_CMD38_ARG_EXT_CSD,
 				 arg == MMC_SECURE_TRIM1_ARG ?
 				 INAND_CMD38_ARG_SECTRIM1 :
 				 INAND_CMD38_ARG_SECERASE,
 				 0);
 		if (err)
 			goto out_retry;
 	}
 	err = mmc_erase(card, from, nr, arg);
 	if (err == -EIO)
 		goto out_retry;
 	if (err)
 		goto out;
 	if (arg == MMC_SECURE_TRIM1_ARG) {
 		if (card->quirks & MMC_QUIRK_INAND_CMD38) {
 			err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
 					 INAND_CMD38_ARG_EXT_CSD,
 					 INAND_CMD38_ARG_SECTRIM2,
 					 0);
 			if (err)
 				goto out_retry;
 		}
 		err = mmc_erase(card, from, nr, MMC_SECURE_TRIM2_ARG);
 		if (err == -EIO)
 			goto out_retry;
 		if (err)
 			goto out;
 	}
 	if (mmc_can_sanitize(card))
 		err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
 				 EXT_CSD_SANITIZE_START, 1, 0);
 out_retry:
 	if (err && !mmc_blk_reset(md, card->host, type))
 		goto retry;
 	if (!err)
 		mmc_blk_reset_success(md, type);
 out:
 	blk_end_request(req, err, blk_rq_bytes(req));
 	return err ? 0 : 1;
 }
 static int mmc_blk_issue_flush(struct mmc_queue *mq, struct request *req)
 {
 	struct mmc_blk_data *md = mq->data;
 	struct mmc_card *card = md->queue.card;
 	int ret = 0;
 	ret = mmc_flush_cache(card);
 	if (ret)
 		ret = -EIO;
 	blk_end_request_all(req, ret);
 	return ret ? 0 : 1;
 }
 /*
  * Reformat current write as a reliable write, supporting
  * both legacy and the enhanced reliable write MMC cards.
  * In each transfer we'll handle only as much as a single
  * reliable write can handle, thus finish the request in
  * partial completions.
  */
 static inline void mmc_apply_rel_rw(struct mmc_blk_request *brq,
 				    struct mmc_card *card,
 				    struct request *req)
 {
 	if (!(card->ext_csd.rel_param & EXT_CSD_WR_REL_PARAM_EN)) {
 		/* Legacy mode imposes restrictions on transfers. */
 		if (!IS_ALIGNED(brq->cmd.arg, card->ext_csd.rel_sectors))
 			brq->data.blocks = 1;
 		if (brq->data.blocks > card->ext_csd.rel_sectors)
 			brq->data.blocks = card->ext_csd.rel_sectors;
 		else if (brq->data.blocks < card->ext_csd.rel_sectors)
 			brq->data.blocks = 1;
 	}
 }
 #define CMD_ERRORS							\
 	(R1_OUT_OF_RANGE |	/* Command argument out of range */	\
 	 R1_ADDRESS_ERROR |	/* Misaligned address */		\
 	 R1_BLOCK_LEN_ERROR |	/* Transferred block length incorrect */\
 	 R1_WP_VIOLATION |	/* Tried to write to protected block */	\
 	 R1_CC_ERROR |		/* Card controller error */		\
 	 R1_ERROR)		/* General/unknown error */
 static int mmc_blk_err_check(struct mmc_card *card,
 			     struct mmc_async_req *areq)
 {
 	struct mmc_queue_req *mq_mrq = container_of(areq, struct mmc_queue_req,
 						    mmc_active);
 	struct mmc_blk_request *brq = &mq_mrq->brq;
 	struct request *req = mq_mrq->req;
 	int ecc_err = 0;
 	/*
 	 * sbc.error indicates a problem with the set block count
 	 * command.  No data will have been transferred.
 	 *
 	 * cmd.error indicates a problem with the r/w command.  No
 	 * data will have been transferred.
 	 *
 	 * stop.error indicates a problem with the stop command.  Data
 	 * may have been transferred, or may still be transferring.
 	 */
 	if (brq->sbc.error || brq->cmd.error || brq->stop.error ||
 	    brq->data.error) {
 		switch (mmc_blk_cmd_recovery(card, req, brq, &ecc_err)) {
 		case ERR_RETRY:
 			return MMC_BLK_RETRY;
 		case ERR_ABORT:
 			return MMC_BLK_ABORT;
 		case ERR_NOMEDIUM:
 			return MMC_BLK_NOMEDIUM;
 		case ERR_CONTINUE:
 			break;
 		}
 	}
 	/*
 	 * Check for errors relating to the execution of the
 	 * initial command - such as address errors.  No data
 	 * has been transferred.
 	 */
 	if (brq->cmd.resp[0] & CMD_ERRORS) {
 		pr_err("%s: r/w command failed, status = %#x\n",
 		       req->rq_disk->disk_name, brq->cmd.resp[0]);
 		return MMC_BLK_ABORT;
 	}
 	/*
 	 * Everything else is either success, or a data error of some
 	 * kind.  If it was a write, we may have transitioned to
 	 * program mode, which we have to wait for it to complete.
 	 */
 	if (!mmc_host_is_spi(card->host) && rq_data_dir(req) != READ) {
 		u32 status;
 		do {
 			int err = get_card_status(card, &status, 5);
 			if (err) {
 				pr_err("%s: error %d requesting status\n",
 				       req->rq_disk->disk_name, err);
 				return MMC_BLK_CMD_ERR;
 			}
 			/*
 			 * Some cards mishandle the status bits,
 			 * so make sure to check both the busy
 			 * indication and the card state.
 			 */
 		} while (!(status & R1_READY_FOR_DATA) ||
 			 (R1_CURRENT_STATE(status) == R1_STATE_PRG));
 	}
 	if (brq->data.error) {
 		pr_err("%s: error %d transferring data, sector %u, nr %u, cmd response %#x, card status %#x\n",
 		       req->rq_disk->disk_name, brq->data.error,
 		       (unsigned)blk_rq_pos(req),
 		       (unsigned)blk_rq_sectors(req),
 		       brq->cmd.resp[0], brq->stop.resp[0]);
 		if (rq_data_dir(req) == READ) {
 			if (ecc_err)
 				return MMC_BLK_ECC_ERR;
 			return MMC_BLK_DATA_ERR;
 		} else {
 			return MMC_BLK_CMD_ERR;
 		}
 	}
 	if (!brq->data.bytes_xfered)
 		return MMC_BLK_RETRY;
 	if (blk_rq_bytes(req) != brq->data.bytes_xfered)
 		return MMC_BLK_PARTIAL;
 	return MMC_BLK_SUCCESS;
 }
 static void mmc_blk_rw_rq_prep(struct mmc_queue_req *mqrq,
 			       struct mmc_card *card,
 			       int disable_multi,
 			       struct mmc_queue *mq)
 {
 	u32 readcmd, writecmd;
 	struct mmc_blk_request *brq = &mqrq->brq;
 	struct request *req = mqrq->req;
 	struct mmc_blk_data *md = mq->data;
 	bool do_data_tag;
 	/*
 	 * Reliable writes are used to implement Forced Unit Access and
 	 * REQ_META accesses, and are supported only on MMCs.
 	 *
 	 * XXX: this really needs a good explanation of why REQ_META
 	 * is treated special.
 	 */
 	bool do_rel_wr = ((req->cmd_flags & REQ_FUA) ||
 			  (req->cmd_flags & REQ_META)) &&
 		(rq_data_dir(req) == WRITE) &&
 		(md->flags & MMC_BLK_REL_WR);
 	memset(brq, 0, sizeof(struct mmc_blk_request));
 	brq->mrq.cmd = &brq->cmd;
 	brq->mrq.data = &brq->data;
 	brq->cmd.arg = blk_rq_pos(req);
 	if (!mmc_card_blockaddr(card))
 		brq->cmd.arg <<= 9;
 	brq->cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_ADTC;
 	brq->data.blksz = 512;
 	brq->stop.opcode = MMC_STOP_TRANSMISSION;
 	brq->stop.arg = 0;
 	brq->stop.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC;
 	brq->data.blocks = blk_rq_sectors(req);
 	/*
 	 * The block layer doesn't support all sector count
 	 * restrictions, so we need to be prepared for too big
 	 * requests.
 	 */
 	if (brq->data.blocks > card->host->max_blk_count)
 		brq->data.blocks = card->host->max_blk_count;
 	if (brq->data.blocks > 1) {
 		/*
 		 * After a read error, we redo the request one sector
 		 * at a time in order to accurately determine which
 		 * sectors can be read successfully.
 		 */
 		if (disable_multi)
 			brq->data.blocks = 1;
 		/* Some controllers can't do multiblock reads due to hw bugs */
 		if (card->host->caps2 & MMC_CAP2_NO_MULTI_READ &&
 		    rq_data_dir(req) == READ)
 			brq->data.blocks = 1;
 	}
 	if (brq->data.blocks > 1 || do_rel_wr) {
 		/* SPI multiblock writes terminate using a special
 		 * token, not a STOP_TRANSMISSION request.
 		 */
 		if (!mmc_host_is_spi(card->host) ||
 		    rq_data_dir(req) == READ)
 			brq->mrq.stop = &brq->stop;
 		readcmd = MMC_READ_MULTIPLE_BLOCK;
 		writecmd = MMC_WRITE_MULTIPLE_BLOCK;
 	} else {
 		brq->mrq.stop = NULL;
 		readcmd = MMC_READ_SINGLE_BLOCK;
 		writecmd = MMC_WRITE_BLOCK;
 	}
 	if (rq_data_dir(req) == READ) {
 		brq->cmd.opcode = readcmd;
 		brq->data.flags |= MMC_DATA_READ;
 	} else {
 		brq->cmd.opcode = writecmd;
 		brq->data.flags |= MMC_DATA_WRITE;
 	}
 	if (do_rel_wr)
 		mmc_apply_rel_rw(brq, card, req);
 	/*
 	 * Data tag is used only during writing meta data to speed
 	 * up write and any subsequent read of this meta data
 	 */
 	do_data_tag = (card->ext_csd.data_tag_unit_size) &&
 		(req->cmd_flags & REQ_META) &&
 		(rq_data_dir(req) == WRITE) &&
 		((brq->data.blocks * brq->data.blksz) >=
 		 card->ext_csd.data_tag_unit_size);
 	/*
 	 * Pre-defined multi-block transfers are preferable to
 	 * open ended-ones (and necessary for reliable writes).
 	 * However, it is not sufficient to just send CMD23,
 	 * and avoid the final CMD12, as on an error condition
 	 * CMD12 (stop) needs to be sent anyway. This, coupled
 	 * with Auto-CMD23 enhancements provided by some
 	 * hosts, means that the complexity of dealing
 	 * with this is best left to the host. If CMD23 is
 	 * supported by card and host, we'll fill sbc in and let
 	 * the host deal with handling it correctly. This means
 	 * that for hosts that don't expose MMC_CAP_CMD23, no
 	 * change of behavior will be observed.
 	 *
 	 * N.B: Some MMC cards experience perf degradation.
 	 * We'll avoid using CMD23-bounded multiblock writes for
 	 * these, while retaining features like reliable writes.
 	 */
 	if ((md->flags & MMC_BLK_CMD23) && mmc_op_multi(brq->cmd.opcode) &&
 	    (do_rel_wr || !(card->quirks & MMC_QUIRK_BLK_NO_CMD23) ||
 	     do_data_tag)) {
 		brq->sbc.opcode = MMC_SET_BLOCK_COUNT;
 		brq->sbc.arg = brq->data.blocks |
 			(do_rel_wr ? (1 << 31) : 0) |
 			(do_data_tag ? (1 << 29) : 0);
 		brq->sbc.flags = MMC_RSP_R1 | MMC_CMD_AC;
 		brq->mrq.sbc = &brq->sbc;
 	}
 	mmc_set_data_timeout(&brq->data, card);
 	brq->data.sg = mqrq->sg;
 	brq->data.sg_len = mmc_queue_map_sg(mq, mqrq);
 	/*
 	 * Adjust the sg list so it is the same size as the
 	 * request.
 	 */
 	if (brq->data.blocks != blk_rq_sectors(req)) {
 		int i, data_size = brq->data.blocks << 9;
 		struct scatterlist *sg;
 		for_each_sg(brq->data.sg, sg, brq->data.sg_len, i) {
 			data_size -= sg->length;
 			if (data_size <= 0) {
 				sg->length += data_size;
 				i++;
 				break;
 			}
 		}
 		brq->data.sg_len = i;
 	}
 	mqrq->mmc_active.mrq = &brq->mrq;
 	mqrq->mmc_active.err_check = mmc_blk_err_check;
 	mmc_queue_bounce_pre(mqrq);
 }
 static int mmc_blk_cmd_err(struct mmc_blk_data *md, struct mmc_card *card,
 			   struct mmc_blk_request *brq, struct request *req,
 			   int ret)
 {
 	/*
 	 * If this is an SD card and we're writing, we can first
 	 * mark the known good sectors as ok.
 	 *
 	 * If the card is not SD, we can still ok written sectors
 	 * as reported by the controller (which might be less than
 	 * the real number of written sectors, but never more).
 	 */
 	if (mmc_card_sd(card)) {
 		u32 blocks;
 		blocks = mmc_sd_num_wr_blocks(card);
 		if (blocks != (u32)-1) {
 			ret = blk_end_request(req, 0, blocks << 9);
 		}
 	} else {
 		ret = blk_end_request(req, 0, brq->data.bytes_xfered);
 	}
 	return ret;
 }
 static int mmc_blk_issue_rw_rq(struct mmc_queue *mq, struct request *rqc)
 {
 	struct mmc_blk_data *md = mq->data;
 	struct mmc_card *card = md->queue.card;
 	struct mmc_blk_request *brq = &mq->mqrq_cur->brq;
 	int ret = 1, disable_multi = 0, retry = 0, type;
 	enum mmc_blk_status status;
 	struct mmc_queue_req *mq_rq;
 	struct request *req = rqc;
 	struct mmc_async_req *areq;
 	if (!rqc && !mq->mqrq_prev->req)
 		return 0;
 	do {
 		if (rqc) {
 			/*
 			 * When 4KB native sector is enabled, only 8 blocks
 			 * multiple read or write is allowed
 			 */
 			if ((brq->data.blocks & 0x07) &&
 			    (card->ext_csd.data_sector_size == 4096)) {
 				pr_err("%s: Transfer size is not 4KB sector size aligned\n",
 					req->rq_disk->disk_name);
 				goto cmd_abort;
 			}
 			mmc_blk_rw_rq_prep(mq->mqrq_cur, card, 0, mq);
 			areq = &mq->mqrq_cur->mmc_active;
 		} else
 			areq = NULL;
 		areq = mmc_start_req(card->host, areq, (int *) &status);
 		if (!areq)
 			return 0;
 		mq_rq = container_of(areq, struct mmc_queue_req, mmc_active);
 		brq = &mq_rq->brq;
 		req = mq_rq->req;
 		type = rq_data_dir(req) == READ ? MMC_BLK_READ : MMC_BLK_WRITE;
 		mmc_queue_bounce_post(mq_rq);
 		switch (status) {
 		case MMC_BLK_SUCCESS:
 		case MMC_BLK_PARTIAL:
 			/*
 			 * A block was successfully transferred.
 			 */
 			mmc_blk_reset_success(md, type);
 			ret = blk_end_request(req, 0,
 						brq->data.bytes_xfered);
 			/*
 			 * If the blk_end_request function returns non-zero even
 			 * though all data has been transferred and no errors
 			 * were returned by the host controller, it's a bug.
 			 */
 			if (status == MMC_BLK_SUCCESS && ret) {
 				pr_err("%s BUG rq_tot %d d_xfer %d\n",
 				       __func__, blk_rq_bytes(req),
 				       brq->data.bytes_xfered);
 				rqc = NULL;
 				goto cmd_abort;
 			}
 			break;
 		case MMC_BLK_CMD_ERR:
 			ret = mmc_blk_cmd_err(md, card, brq, req, ret);
 			if (!mmc_blk_reset(md, card->host, type))
 				break;
 			goto cmd_abort;
 		case MMC_BLK_RETRY:
 			if (retry++ < 5)
 				break;
 			/* Fall through */
 		case MMC_BLK_ABORT:
 			if (!mmc_blk_reset(md, card->host, type))
 				break;
 			goto cmd_abort;
 		case MMC_BLK_DATA_ERR: {
 			int err;
 			err = mmc_blk_reset(md, card->host, type);
 			if (!err)
 				break;
 			if (err == -ENODEV)
 				goto cmd_abort;
 			/* Fall through */
 		}
 		case MMC_BLK_ECC_ERR:
 			if (brq->data.blocks > 1) {
 				/* Redo read one sector at a time */
 				pr_warning("%s: retrying using single block read\n",
 					   req->rq_disk->disk_name);
 				disable_multi = 1;
 				break;
 			}
 			/*
 			 * After an error, we redo I/O one sector at a
 			 * time, so we only reach here after trying to
 			 * read a single sector.
 			 */
 			ret = blk_end_request(req, -EIO,
 						brq->data.blksz);
 			if (!ret)
 				goto start_new_req;
 			break;
 		case MMC_BLK_NOMEDIUM:
 			goto cmd_abort;
 		}
 		if (ret) {
 			/*
 			 * In case of a incomplete request
 			 * prepare it again and resend.
 			 */
 			mmc_blk_rw_rq_prep(mq_rq, card, disable_multi, mq);
 			mmc_start_req(card->host, &mq_rq->mmc_active, NULL);
 		}
 	} while (ret);
 	return 1;
  cmd_abort:
 	if (mmc_card_removed(card))
 		req->cmd_flags |= REQ_QUIET;
 	while (ret)
 		ret = blk_end_request(req, -EIO, blk_rq_cur_bytes(req));
  start_new_req:
 	if (rqc) {
 		mmc_blk_rw_rq_prep(mq->mqrq_cur, card, 0, mq);
 		mmc_start_req(card->host, &mq->mqrq_cur->mmc_active, NULL);
 	}
 	return 0;
 }
 static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
 {
 	int ret;
 	struct mmc_blk_data *md = mq->data;
 	struct mmc_card *card = md->queue.card;
 	if (req && !mq->mqrq_prev->req)
 		/* claim host only for the first request */
 		mmc_claim_host(card->host);
 	ret = mmc_blk_part_switch(card, md);
 	if (ret) {
 		if (req) {
 			blk_end_request_all(req, -EIO);
 		}
 		ret = 0;
 		goto out;
 	}
 	if (req && req->cmd_flags & REQ_DISCARD) {
 		/* complete ongoing async transfer before issuing discard */
 		if (card->host->areq)
 			mmc_blk_issue_rw_rq(mq, NULL);
-		if (req->cmd_flags & REQ_SECURE)
+		if (req->cmd_flags & REQ_SECURE &&
+			!(card->quirks & MMC_QUIRK_SEC_ERASE_TRIM_BROKEN))
 			ret = mmc_blk_issue_secdiscard_rq(mq, req);
 		else
 			ret = mmc_blk_issue_discard_rq(mq, req);
 	} else if (req && req->cmd_flags & REQ_FLUSH) {
 		/* complete ongoing async transfer before issuing flush */
 		if (card->host->areq)
 			mmc_blk_issue_rw_rq(mq, NULL);
 		ret = mmc_blk_issue_flush(mq, req);
 	} else {
 		ret = mmc_blk_issue_rw_rq(mq, req);
 	}
 out:
 	if (!req)
 		/* release host only when there are no more requests */
 		mmc_release_host(card->host);
 	return ret;
 }
 static inline int mmc_blk_readonly(struct mmc_card *card)
 {
 	return mmc_card_readonly(card) ||
 	       !(card->csd.cmdclass & CCC_BLOCK_WRITE);
 }
 static struct mmc_blk_data *mmc_blk_alloc_req(struct mmc_card *card,
 					      struct device *parent,
 					      sector_t size,
 					      bool default_ro,
 					      const char *subname,
 					      int area_type)
 {
 	struct mmc_blk_data *md;
 	int devidx, ret;
 	devidx = find_first_zero_bit(dev_use, max_devices);
 	if (devidx >= max_devices)
 		return ERR_PTR(-ENOSPC);
 	__set_bit(devidx, dev_use);
 	md = kzalloc(sizeof(struct mmc_blk_data), GFP_KERNEL);
 	if (!md) {
 		ret = -ENOMEM;
 		goto out;
 	}
 	/*
 	 * !subname implies we are creating main mmc_blk_data that will be
 	 * associated with mmc_card with mmc_set_drvdata. Due to device
 	 * partitions, devidx will not coincide with a per-physical card
 	 * index anymore so we keep track of a name index.
 	 */
 	if (!subname) {
 		md->name_idx = find_first_zero_bit(name_use, max_devices);
 		__set_bit(md->name_idx, name_use);
 	} else
 		md->name_idx = ((struct mmc_blk_data *)
 				dev_to_disk(parent)->private_data)->name_idx;
 	md->area_type = area_type;
 	/*
 	 * Set the read-only status based on the supported commands
 	 * and the write protect switch.
 	 */
 	md->read_only = mmc_blk_readonly(card);
 	md->disk = alloc_disk(perdev_minors);
 	if (md->disk == NULL) {
 		ret = -ENOMEM;
 		goto err_kfree;
 	}
 	spin_lock_init(&md->lock);
 	INIT_LIST_HEAD(&md->part);
 	md->usage = 1;
 	ret = mmc_init_queue(&md->queue, card, &md->lock, subname);
 	if (ret)
 		goto err_putdisk;
 	md->queue.issue_fn = mmc_blk_issue_rq;
 	md->queue.data = md;
 	md->disk->major	= MMC_BLOCK_MAJOR;
 	md->disk->first_minor = devidx * perdev_minors;
 	md->disk->fops = &mmc_bdops;
 	md->disk->private_data = md;
 	md->disk->queue = md->queue.queue;
 	md->disk->driverfs_dev = parent;
 	set_disk_ro(md->disk, md->read_only || default_ro);
 	/*
 	 * As discussed on lkml, GENHD_FL_REMOVABLE should:
 	 *
 	 * - be set for removable media with permanent block devices
 	 * - be unset for removable block devices with permanent media
 	 *
 	 * Since MMC block devices clearly fall under the second
 	 * case, we do not set GENHD_FL_REMOVABLE.  Userspace
 	 * should use the block device creation/destruction hotplug
 	 * messages to tell when the card is present.
 	 */
 	snprintf(md->disk->disk_name, sizeof(md->disk->disk_name),
 		 "mmcblk%d%s", md->name_idx, subname ? subname : "");
 	if (mmc_card_mmc(card))
 		blk_queue_logical_block_size(md->queue.queue,
 					     card->ext_csd.data_sector_size);
 	else
 		blk_queue_logical_block_size(md->queue.queue, 512);
 	set_capacity(md->disk, size);
 	if (mmc_host_cmd23(card->host)) {
 		if (mmc_card_mmc(card) ||
 		    (mmc_card_sd(card) &&
 		     card->scr.cmds & SD_SCR_CMD23_SUPPORT))
 			md->flags |= MMC_BLK_CMD23;
 	}
 	if (mmc_card_mmc(card) &&
 	    md->flags & MMC_BLK_CMD23 &&
 	    ((card->ext_csd.rel_param & EXT_CSD_WR_REL_PARAM_EN) ||
 	     card->ext_csd.rel_sectors)) {
 		md->flags |= MMC_BLK_REL_WR;
 		blk_queue_flush(md->queue.queue, REQ_FLUSH | REQ_FUA);
 	}
 	return md;
  err_putdisk:
 	put_disk(md->disk);
  err_kfree:
 	kfree(md);
  out:
 	return ERR_PTR(ret);
 }
 static struct mmc_blk_data *mmc_blk_alloc(struct mmc_card *card)
 {
 	sector_t size;
 	struct mmc_blk_data *md;
 	if (!mmc_card_sd(card) && mmc_card_blockaddr(card)) {
 		/*
 		 * The EXT_CSD sector count is in number or 512 byte
 		 * sectors.
 		 */
 		size = card->ext_csd.sectors;
 	} else {
 		/*
 		 * The CSD capacity field is in units of read_blkbits.
 		 * set_capacity takes units of 512 bytes.
 		 */
 		size = card->csd.capacity << (card->csd.read_blkbits - 9);
 	}
 	md = mmc_blk_alloc_req(card, &card->dev, size, false, NULL,
 					MMC_BLK_DATA_AREA_MAIN);
 	return md;
 }
 static int mmc_blk_alloc_part(struct mmc_card *card,
 			      struct mmc_blk_data *md,
 			      unsigned int part_type,
 			      sector_t size,
 			      bool default_ro,
 			      const char *subname,
 			      int area_type)
 {
 	char cap_str[10];
 	struct mmc_blk_data *part_md;
 	part_md = mmc_blk_alloc_req(card, disk_to_dev(md->disk), size, default_ro,
 				    subname, area_type);
 	if (IS_ERR(part_md))
 		return PTR_ERR(part_md);
 	part_md->part_type = part_type;
 	list_add(&part_md->part, &md->part);
 	string_get_size((u64)get_capacity(part_md->disk) << 9, STRING_UNITS_2,
 			cap_str, sizeof(cap_str));
 	pr_info("%s: %s %s partition %u %s\n",
 	       part_md->disk->disk_name, mmc_card_id(card),
 	       mmc_card_name(card), part_md->part_type, cap_str);
 	return 0;
 }
 /* MMC Physical partitions consist of two boot partitions and
  * up to four general purpose partitions.
  * For each partition enabled in EXT_CSD a block device will be allocatedi
  * to provide access to the partition.
  */
 static int mmc_blk_alloc_parts(struct mmc_card *card, struct mmc_blk_data *md)
 {
 	int idx, ret = 0;
 	if (!mmc_card_mmc(card))
 		return 0;
 	for (idx = 0; idx < card->nr_parts; idx++) {
 		if (card->part[idx].size) {
 			ret = mmc_blk_alloc_part(card, md,
 				card->part[idx].part_cfg,
 				card->part[idx].size >> 9,
 				card->part[idx].force_ro,
 				card->part[idx].name,
 				card->part[idx].area_type);
 			if (ret)
 				return ret;
 		}
 	}
 	return ret;
 }
 static void mmc_blk_remove_req(struct mmc_blk_data *md)
 {
 	struct mmc_card *card;
 	if (md) {
 		card = md->queue.card;
 		if (md->disk->flags & GENHD_FL_UP) {
 			device_remove_file(disk_to_dev(md->disk), &md->force_ro);
 			if ((md->area_type & MMC_BLK_DATA_AREA_BOOT) &&
 					card->ext_csd.boot_ro_lockable)
 				device_remove_file(disk_to_dev(md->disk),
 					&md->power_ro_lock);
 			/* Stop new requests from getting into the queue */
 			del_gendisk(md->disk);
 		}
 		/* Then flush out any already in there */
 		mmc_cleanup_queue(&md->queue);
 		mmc_blk_put(md);
 	}
 }
 static void mmc_blk_remove_parts(struct mmc_card *card,
 				 struct mmc_blk_data *md)
 {
 	struct list_head *pos, *q;
 	struct mmc_blk_data *part_md;
 	__clear_bit(md->name_idx, name_use);
 	list_for_each_safe(pos, q, &md->part) {
 		part_md = list_entry(pos, struct mmc_blk_data, part);
 		list_del(pos);
 		mmc_blk_remove_req(part_md);
 	}
 }
 static int mmc_add_disk(struct mmc_blk_data *md)
 {
 	int ret;
 	struct mmc_card *card = md->queue.card;
 	add_disk(md->disk);
 	md->force_ro.show = force_ro_show;
 	md->force_ro.store = force_ro_store;
 	sysfs_attr_init(&md->force_ro.attr);
 	md->force_ro.attr.name = "force_ro";
 	md->force_ro.attr.mode = S_IRUGO | S_IWUSR;
 	ret = device_create_file(disk_to_dev(md->disk), &md->force_ro);
 	if (ret)
 		goto force_ro_fail;
 	if ((md->area_type & MMC_BLK_DATA_AREA_BOOT) &&
 	     card->ext_csd.boot_ro_lockable) {
 		umode_t mode;
 		if (card->ext_csd.boot_ro_lock & EXT_CSD_BOOT_WP_B_PWR_WP_DIS)
 			mode = S_IRUGO;
 		else
 			mode = S_IRUGO | S_IWUSR;
 		md->power_ro_lock.show = power_ro_lock_show;
 		md->power_ro_lock.store = power_ro_lock_store;
 		sysfs_attr_init(&md->power_ro_lock.attr);
 		md->power_ro_lock.attr.mode = mode;
 		md->power_ro_lock.attr.name =
 					"ro_lock_until_next_power_on";
 		ret = device_create_file(disk_to_dev(md->disk),
 				&md->power_ro_lock);
 		if (ret)
 			goto power_ro_lock_fail;
 	}
 	return ret;
 power_ro_lock_fail:
 	device_remove_file(disk_to_dev(md->disk), &md->force_ro);
 force_ro_fail:
 	del_gendisk(md->disk);
 	return ret;
 }
 #define CID_MANFID_SANDISK	0x2
 #define CID_MANFID_TOSHIBA	0x11
 #define CID_MANFID_MICRON	0x13
+#define CID_MANFID_SAMSUNG	0x15
 static const struct mmc_fixup blk_fixups[] =
 {
 	MMC_FIXUP("SEM02G", CID_MANFID_SANDISK, 0x100, add_quirk,
 		  MMC_QUIRK_INAND_CMD38),
 	MMC_FIXUP("SEM04G", CID_MANFID_SANDISK, 0x100, add_quirk,
 		  MMC_QUIRK_INAND_CMD38),
 	MMC_FIXUP("SEM08G", CID_MANFID_SANDISK, 0x100, add_quirk,
 		  MMC_QUIRK_INAND_CMD38),
 	MMC_FIXUP("SEM16G", CID_MANFID_SANDISK, 0x100, add_quirk,
 		  MMC_QUIRK_INAND_CMD38),
 	MMC_FIXUP("SEM32G", CID_MANFID_SANDISK, 0x100, add_quirk,
 		  MMC_QUIRK_INAND_CMD38),
 	/*
 	 * Some MMC cards experience performance degradation with CMD23
 	 * instead of CMD12-bounded multiblock transfers. For now we'll
 	 * black list what's bad...
 	 * - Certain Toshiba cards.
 	 *
 	 * N.B. This doesn't affect SD cards.
 	 */
 	MMC_FIXUP("MMC08G", CID_MANFID_TOSHIBA, CID_OEMID_ANY, add_quirk_mmc,
 		  MMC_QUIRK_BLK_NO_CMD23),
 	MMC_FIXUP("MMC16G", CID_MANFID_TOSHIBA, CID_OEMID_ANY, add_quirk_mmc,
 		  MMC_QUIRK_BLK_NO_CMD23),
 	MMC_FIXUP("MMC32G", CID_MANFID_TOSHIBA, CID_OEMID_ANY, add_quirk_mmc,
 		  MMC_QUIRK_BLK_NO_CMD23),
 	/*
 	 * Some Micron MMC cards needs longer data read timeout than
 	 * indicated in CSD.
 	 */
 	MMC_FIXUP(CID_NAME_ANY, CID_MANFID_MICRON, 0x200, add_quirk_mmc,
 		  MMC_QUIRK_LONG_READ_TIME),
+	/*
+	 * On these Samsung MoviNAND parts, performing secure erase or
+	 * secure trim can result in unrecoverable corruption due to a
+	 * firmware bug.
+	 */
+	MMC_FIXUP("M8G2FA", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc,
+		  MMC_QUIRK_SEC_ERASE_TRIM_BROKEN),
+	MMC_FIXUP("MAG4FA", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc,
+		  MMC_QUIRK_SEC_ERASE_TRIM_BROKEN),
+	MMC_FIXUP("MBG8FA", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc,
+		  MMC_QUIRK_SEC_ERASE_TRIM_BROKEN),
+	MMC_FIXUP("MCGAFA", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc,
+		  MMC_QUIRK_SEC_ERASE_TRIM_BROKEN),
+	MMC_FIXUP("VAL00M", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc,
+		  MMC_QUIRK_SEC_ERASE_TRIM_BROKEN),
+	MMC_FIXUP("VYL00M", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc,
+		  MMC_QUIRK_SEC_ERASE_TRIM_BROKEN),
+	MMC_FIXUP("KYL00M", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc,
+		  MMC_QUIRK_SEC_ERASE_TRIM_BROKEN),
+	MMC_FIXUP("VZL00M", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc,
+		  MMC_QUIRK_SEC_ERASE_TRIM_BROKEN),
 	END_FIXUP
 };
 static int mmc_blk_probe(struct mmc_card *card)
 {
 	struct mmc_blk_data *md, *part_md;
 	char cap_str[10];
 	/*
 	 * Check that the card supports the command class(es) we need.
 	 */
 	if (!(card->csd.cmdclass & CCC_BLOCK_READ))
 		return -ENODEV;
 	md = mmc_blk_alloc(card);
 	if (IS_ERR(md))
 		return PTR_ERR(md);
 	string_get_size((u64)get_capacity(md->disk) << 9, STRING_UNITS_2,
 			cap_str, sizeof(cap_str));
 	pr_info("%s: %s %s %s %s\n",
 		md->disk->disk_name, mmc_card_id(card), mmc_card_name(card),
 		cap_str, md->read_only ? "(ro)" : "");
 	if (mmc_blk_alloc_parts(card, md))
 		goto out;
 	mmc_set_drvdata(card, md);
 	mmc_fixup_device(card, blk_fixups);
 	if (mmc_add_disk(md))
 		goto out;
 	list_for_each_entry(part_md, &md->part, part) {
 		if (mmc_add_disk(part_md))
 			goto out;
 	}
 	return 0;
  out:
 	mmc_blk_remove_parts(card, md);
 	mmc_blk_remove_req(md);
 	return 0;
 }
 static void mmc_blk_remove(struct mmc_card *card)
 {
 	struct mmc_blk_data *md = mmc_get_drvdata(card);
 	mmc_blk_remove_parts(card, md);
 	mmc_claim_host(card->host);
 	mmc_blk_part_switch(card, md);
 	mmc_release_host(card->host);
 	mmc_blk_remove_req(md);
 	mmc_set_drvdata(card, NULL);
 }
 #ifdef CONFIG_PM
 static int mmc_blk_suspend(struct mmc_card *card)
 {
 	struct mmc_blk_data *part_md;
 	struct mmc_blk_data *md = mmc_get_drvdata(card);
 	if (md) {
 		mmc_queue_suspend(&md->queue);
 		list_for_each_entry(part_md, &md->part, part) {
 			mmc_queue_suspend(&part_md->queue);
 		}
 	}
 	return 0;
 }
 static int mmc_blk_resume(struct mmc_card *card)
 {
 	struct mmc_blk_data *part_md;
 	struct mmc_blk_data *md = mmc_get_drvdata(card);
 	if (md) {
 		/*
 		 * Resume involves the card going into idle state,
 		 * so current partition is always the main one.
 		 */
 		md->part_curr = md->part_type;
 		mmc_queue_resume(&md->queue);
 		list_for_each_entry(part_md, &md->part, part) {
 			mmc_queue_resume(&part_md->queue);
 		}
 	}
 	return 0;
 }
 #else
 #define	mmc_blk_suspend	NULL
 #define mmc_blk_resume	NULL
 #endif
 static struct mmc_driver mmc_driver = {
 	.drv		= {
 		.name	= "mmcblk",
 	},
 	.probe		= mmc_blk_probe,
 	.remove		= mmc_blk_remove,
 	.suspend	= mmc_blk_suspend,
 	.resume		= mmc_blk_resume,
 };
 static int __init mmc_blk_init(void)
 {
 	int res;
 	if (perdev_minors != CONFIG_MMC_BLOCK_MINORS)
 		pr_info("mmcblk: using %d minors per device\n", perdev_minors);
 	max_devices = 256 / perdev_minors;
 	res = register_blkdev(MMC_BLOCK_MAJOR, "mmc");
 	if (res)
 		goto out;
 	res = mmc_register_driver(&mmc_driver);
 	if (res)
 		goto out2;
 	return 0;
  out2:
 	unregister_blkdev(MMC_BLOCK_MAJOR, "mmc");
  out:
 	return res;
 }
 static void __exit mmc_blk_exit(void)
 {
 	mmc_unregister_driver(&mmc_driver);
 	unregister_blkdev(MMC_BLOCK_MAJOR, "mmc");
 }
 module_init(mmc_blk_init);
 module_exit(mmc_blk_exit);
 MODULE_LICENSE("GPL");
 MODULE_DESCRIPTION("Multimedia Card (MMC) block device driver");

drivers/mmc/host/atmel-mci.c

Diff comments View file @ 0809095

 /*
  * Atmel MultiMedia Card Interface driver
  *
  * Copyright (C) 2004-2008 Atmel Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #include <linux/blkdev.h>
 #include <linux/clk.h>
 #include <linux/debugfs.h>
 #include <linux/device.h>
 #include <linux/dmaengine.h>
 #include <linux/dma-mapping.h>
 #include <linux/err.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/scatterlist.h>
 #include <linux/seq_file.h>
 #include <linux/slab.h>
 #include <linux/stat.h>
 #include <linux/types.h>
 #include <linux/mmc/host.h>
 #include <linux/mmc/sdio.h>
 #include <mach/atmel-mci.h>
 #include <linux/atmel-mci.h>
 #include <linux/atmel_pdc.h>
 #include <asm/io.h>
 #include <asm/unaligned.h>
 #include <mach/cpu.h>
 #include <mach/board.h>
 #include "atmel-mci-regs.h"
 #define ATMCI_DATA_ERROR_FLAGS	(ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
 #define ATMCI_DMA_THRESHOLD	16
 enum {
 	EVENT_CMD_RDY = 0,
 	EVENT_XFER_COMPLETE,
 	EVENT_NOTBUSY,
 	EVENT_DATA_ERROR,
 };
 enum atmel_mci_state {
 	STATE_IDLE = 0,
 	STATE_SENDING_CMD,
 	STATE_DATA_XFER,
 	STATE_WAITING_NOTBUSY,
 	STATE_SENDING_STOP,
 	STATE_END_REQUEST,
 };
 enum atmci_xfer_dir {
 	XFER_RECEIVE = 0,
 	XFER_TRANSMIT,
 };
 enum atmci_pdc_buf {
 	PDC_FIRST_BUF = 0,
 	PDC_SECOND_BUF,
 };
 struct atmel_mci_caps {
 	bool    has_dma;
 	bool    has_pdc;
 	bool    has_cfg_reg;
 	bool    has_cstor_reg;
 	bool    has_highspeed;
 	bool    has_rwproof;
 	bool	has_odd_clk_div;
 	bool	has_bad_data_ordering;
 	bool	need_reset_after_xfer;
 	bool	need_blksz_mul_4;
+	bool	need_notbusy_for_read_ops;
 };
 struct atmel_mci_dma {
 	struct dma_chan			*chan;
 	struct dma_async_tx_descriptor	*data_desc;
 };
 /**
  * struct atmel_mci - MMC controller state shared between all slots
  * @lock: Spinlock protecting the queue and associated data.
  * @regs: Pointer to MMIO registers.
  * @sg: Scatterlist entry currently being processed by PIO or PDC code.
  * @pio_offset: Offset into the current scatterlist entry.
  * @buffer: Buffer used if we don't have the r/w proof capability. We
  *      don't have the time to switch pdc buffers so we have to use only
  *      one buffer for the full transaction.
  * @buf_size: size of the buffer.
  * @phys_buf_addr: buffer address needed for pdc.
  * @cur_slot: The slot which is currently using the controller.
  * @mrq: The request currently being processed on @cur_slot,
  *	or NULL if the controller is idle.
  * @cmd: The command currently being sent to the card, or NULL.
  * @data: The data currently being transferred, or NULL if no data
  *	transfer is in progress.
  * @data_size: just data->blocks * data->blksz.
  * @dma: DMA client state.
  * @data_chan: DMA channel being used for the current data transfer.
  * @cmd_status: Snapshot of SR taken upon completion of the current
  *	command. Only valid when EVENT_CMD_COMPLETE is pending.
  * @data_status: Snapshot of SR taken upon completion of the current
  *	data transfer. Only valid when EVENT_DATA_COMPLETE or
  *	EVENT_DATA_ERROR is pending.
  * @stop_cmdr: Value to be loaded into CMDR when the stop command is
  *	to be sent.
  * @tasklet: Tasklet running the request state machine.
  * @pending_events: Bitmask of events flagged by the interrupt handler
  *	to be processed by the tasklet.
  * @completed_events: Bitmask of events which the state machine has
  *	processed.
  * @state: Tasklet state.
  * @queue: List of slots waiting for access to the controller.
  * @need_clock_update: Update the clock rate before the next request.
  * @need_reset: Reset controller before next request.
  * @timer: Timer to balance the data timeout error flag which cannot rise.
  * @mode_reg: Value of the MR register.
  * @cfg_reg: Value of the CFG register.
  * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
  *	rate and timeout calculations.
  * @mapbase: Physical address of the MMIO registers.
  * @mck: The peripheral bus clock hooked up to the MMC controller.
  * @pdev: Platform device associated with the MMC controller.
  * @slot: Slots sharing this MMC controller.
  * @caps: MCI capabilities depending on MCI version.
  * @prepare_data: function to setup MCI before data transfer which
  * depends on MCI capabilities.
  * @submit_data: function to start data transfer which depends on MCI
  * capabilities.
  * @stop_transfer: function to stop data transfer which depends on MCI
  * capabilities.
  *
  * Locking
  * =======
  *
  * @lock is a softirq-safe spinlock protecting @queue as well as
  * @cur_slot, @mrq and @state. These must always be updated
  * at the same time while holding @lock.
  *
  * @lock also protects mode_reg and need_clock_update since these are
  * used to synchronize mode register updates with the queue
  * processing.
  *
  * The @mrq field of struct atmel_mci_slot is also protected by @lock,
  * and must always be written at the same time as the slot is added to
  * @queue.
  *
  * @pending_events and @completed_events are accessed using atomic bit
  * operations, so they don't need any locking.
  *
  * None of the fields touched by the interrupt handler need any
  * locking. However, ordering is important: Before EVENT_DATA_ERROR or
  * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
  * interrupts must be disabled and @data_status updated with a
  * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
  * CMDRDY interrupt must be disabled and @cmd_status updated with a
  * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
  * bytes_xfered field of @data must be written. This is ensured by
  * using barriers.
  */
 struct atmel_mci {
 	spinlock_t		lock;
 	void __iomem		*regs;
 	struct scatterlist	*sg;
 	unsigned int		pio_offset;
 	unsigned int		*buffer;
 	unsigned int		buf_size;
 	dma_addr_t		buf_phys_addr;
 	struct atmel_mci_slot	*cur_slot;
 	struct mmc_request	*mrq;
 	struct mmc_command	*cmd;
 	struct mmc_data		*data;
 	unsigned int		data_size;
 	struct atmel_mci_dma	dma;
 	struct dma_chan		*data_chan;
 	struct dma_slave_config	dma_conf;
 	u32			cmd_status;
 	u32			data_status;
 	u32			stop_cmdr;
 	struct tasklet_struct	tasklet;
 	unsigned long		pending_events;
 	unsigned long		completed_events;
 	enum atmel_mci_state	state;
 	struct list_head	queue;
 	bool			need_clock_update;
 	bool			need_reset;
 	struct timer_list	timer;
 	u32			mode_reg;
 	u32			cfg_reg;
 	unsigned long		bus_hz;
 	unsigned long		mapbase;
 	struct clk		*mck;
 	struct platform_device	*pdev;
 	struct atmel_mci_slot	*slot[ATMCI_MAX_NR_SLOTS];
 	struct atmel_mci_caps   caps;
 	u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
 	void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
 	void (*stop_transfer)(struct atmel_mci *host);
 };
 /**
  * struct atmel_mci_slot - MMC slot state
  * @mmc: The mmc_host representing this slot.
  * @host: The MMC controller this slot is using.
  * @sdc_reg: Value of SDCR to be written before using this slot.
  * @sdio_irq: SDIO irq mask for this slot.
  * @mrq: mmc_request currently being processed or waiting to be
  *	processed, or NULL when the slot is idle.
  * @queue_node: List node for placing this node in the @queue list of
  *	&struct atmel_mci.
  * @clock: Clock rate configured by set_ios(). Protected by host->lock.
  * @flags: Random state bits associated with the slot.
  * @detect_pin: GPIO pin used for card detection, or negative if not
  *	available.
  * @wp_pin: GPIO pin used for card write protect sending, or negative
  *	if not available.
  * @detect_is_active_high: The state of the detect pin when it is active.
  * @detect_timer: Timer used for debouncing @detect_pin interrupts.
  */
 struct atmel_mci_slot {
 	struct mmc_host		*mmc;
 	struct atmel_mci	*host;
 	u32			sdc_reg;
 	u32			sdio_irq;
 	struct mmc_request	*mrq;
 	struct list_head	queue_node;
 	unsigned int		clock;
 	unsigned long		flags;
 #define ATMCI_CARD_PRESENT	0
 #define ATMCI_CARD_NEED_INIT	1
 #define ATMCI_SHUTDOWN		2
 #define ATMCI_SUSPENDED		3
 	int			detect_pin;
 	int			wp_pin;
 	bool			detect_is_active_high;
 	struct timer_list	detect_timer;
 };
 #define atmci_test_and_clear_pending(host, event)		\
 	test_and_clear_bit(event, &host->pending_events)
 #define atmci_set_completed(host, event)			\
 	set_bit(event, &host->completed_events)
 #define atmci_set_pending(host, event)				\
 	set_bit(event, &host->pending_events)
 /*
  * The debugfs stuff below is mostly optimized away when
  * CONFIG_DEBUG_FS is not set.
  */
 static int atmci_req_show(struct seq_file *s, void *v)
 {
 	struct atmel_mci_slot	*slot = s->private;
 	struct mmc_request	*mrq;
 	struct mmc_command	*cmd;
 	struct mmc_command	*stop;
 	struct mmc_data		*data;
 	/* Make sure we get a consistent snapshot */
 	spin_lock_bh(&slot->host->lock);
 	mrq = slot->mrq;
 	if (mrq) {
 		cmd = mrq->cmd;
 		data = mrq->data;
 		stop = mrq->stop;
 		if (cmd)
 			seq_printf(s,
 				"CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 				cmd->opcode, cmd->arg, cmd->flags,
 				cmd->resp[0], cmd->resp[1], cmd->resp[2],
 				cmd->resp[3], cmd->error);
 		if (data)
 			seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 				data->bytes_xfered, data->blocks,
 				data->blksz, data->flags, data->error);
 		if (stop)
 			seq_printf(s,
 				"CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 				stop->opcode, stop->arg, stop->flags,
 				stop->resp[0], stop->resp[1], stop->resp[2],
 				stop->resp[3], stop->error);
 	}
 	spin_unlock_bh(&slot->host->lock);
 	return 0;
 }
 static int atmci_req_open(struct inode *inode, struct file *file)
 {
 	return single_open(file, atmci_req_show, inode->i_private);
 }
 static const struct file_operations atmci_req_fops = {
 	.owner		= THIS_MODULE,
 	.open		= atmci_req_open,
 	.read		= seq_read,
 	.llseek		= seq_lseek,
 	.release	= single_release,
 };
 static void atmci_show_status_reg(struct seq_file *s,
 		const char *regname, u32 value)
 {
 	static const char	*sr_bit[] = {
 		[0]	= "CMDRDY",
 		[1]	= "RXRDY",
 		[2]	= "TXRDY",
 		[3]	= "BLKE",
 		[4]	= "DTIP",
 		[5]	= "NOTBUSY",
 		[6]	= "ENDRX",
 		[7]	= "ENDTX",
 		[8]	= "SDIOIRQA",
 		[9]	= "SDIOIRQB",
 		[12]	= "SDIOWAIT",
 		[14]	= "RXBUFF",
 		[15]	= "TXBUFE",
 		[16]	= "RINDE",
 		[17]	= "RDIRE",
 		[18]	= "RCRCE",
 		[19]	= "RENDE",
 		[20]	= "RTOE",
 		[21]	= "DCRCE",
 		[22]	= "DTOE",
 		[23]	= "CSTOE",
 		[24]	= "BLKOVRE",
 		[25]	= "DMADONE",
 		[26]	= "FIFOEMPTY",
 		[27]	= "XFRDONE",
 		[30]	= "OVRE",
 		[31]	= "UNRE",
 	};
 	unsigned int		i;
 	seq_printf(s, "%s:\t0x%08x", regname, value);
 	for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
 		if (value & (1 << i)) {
 			if (sr_bit[i])
 				seq_printf(s, " %s", sr_bit[i]);
 			else
 				seq_puts(s, " UNKNOWN");
 		}
 	}
 	seq_putc(s, '\n');
 }
 static int atmci_regs_show(struct seq_file *s, void *v)
 {
 	struct atmel_mci	*host = s->private;
 	u32			*buf;
 	buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
 	if (!buf)
 		return -ENOMEM;
 	/*
 	 * Grab a more or less consistent snapshot. Note that we're
 	 * not disabling interrupts, so IMR and SR may not be
 	 * consistent.
 	 */
 	spin_lock_bh(&host->lock);
 	clk_enable(host->mck);
 	memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
 	clk_disable(host->mck);
 	spin_unlock_bh(&host->lock);
 	seq_printf(s, "MR:\t0x%08x%s%s ",
 			buf[ATMCI_MR / 4],
 			buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
 			buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "");
 	if (host->caps.has_odd_clk_div)
 		seq_printf(s, "{CLKDIV,CLKODD}=%u\n",
 				((buf[ATMCI_MR / 4] & 0xff) << 1)
 				| ((buf[ATMCI_MR / 4] >> 16) & 1));
 	else
 		seq_printf(s, "CLKDIV=%u\n",
 				(buf[ATMCI_MR / 4] & 0xff));
 	seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
 	seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
 	seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
 	seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
 			buf[ATMCI_BLKR / 4],
 			buf[ATMCI_BLKR / 4] & 0xffff,
 			(buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
 	if (host->caps.has_cstor_reg)
 		seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
 	/* Don't read RSPR and RDR; it will consume the data there */
 	atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
 	atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
 	if (host->caps.has_dma) {
 		u32 val;
 		val = buf[ATMCI_DMA / 4];
 		seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
 				val, val & 3,
 				((val >> 4) & 3) ?
 					1 << (((val >> 4) & 3) + 1) : 1,
 				val & ATMCI_DMAEN ? " DMAEN" : "");
 	}
 	if (host->caps.has_cfg_reg) {
 		u32 val;
 		val = buf[ATMCI_CFG / 4];
 		seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
 				val,
 				val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
 				val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
 				val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
 				val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
 	}
 	kfree(buf);
 	return 0;
 }
 static int atmci_regs_open(struct inode *inode, struct file *file)
 {
 	return single_open(file, atmci_regs_show, inode->i_private);
 }
 static const struct file_operations atmci_regs_fops = {
 	.owner		= THIS_MODULE,
 	.open		= atmci_regs_open,
 	.read		= seq_read,
 	.llseek		= seq_lseek,
 	.release	= single_release,
 };
 static void atmci_init_debugfs(struct atmel_mci_slot *slot)
 {
 	struct mmc_host		*mmc = slot->mmc;
 	struct atmel_mci	*host = slot->host;
 	struct dentry		*root;
 	struct dentry		*node;
 	root = mmc->debugfs_root;
 	if (!root)
 		return;
 	node = debugfs_create_file("regs", S_IRUSR, root, host,
 			&atmci_regs_fops);
 	if (IS_ERR(node))
 		return;
 	if (!node)
 		goto err;
 	node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
 	if (!node)
 		goto err;
 	node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 	if (!node)
 		goto err;
 	node = debugfs_create_x32("pending_events", S_IRUSR, root,
 				     (u32 *)&host->pending_events);
 	if (!node)
 		goto err;
 	node = debugfs_create_x32("completed_events", S_IRUSR, root,
 				     (u32 *)&host->completed_events);
 	if (!node)
 		goto err;
 	return;
 err:
 	dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 }
 static inline unsigned int atmci_get_version(struct atmel_mci *host)
 {
 	return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
 }
 static void atmci_timeout_timer(unsigned long data)
 {
 	struct atmel_mci *host;
 	host = (struct atmel_mci *)data;
 	dev_dbg(&host->pdev->dev, "software timeout\n");
 	if (host->mrq->cmd->data) {
 		host->mrq->cmd->data->error = -ETIMEDOUT;
 		host->data = NULL;
 	} else {
 		host->mrq->cmd->error = -ETIMEDOUT;
 		host->cmd = NULL;
 	}
 	host->need_reset = 1;
 	host->state = STATE_END_REQUEST;
 	smp_wmb();
 	tasklet_schedule(&host->tasklet);
 }
 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
 					unsigned int ns)
 {
 	/*
 	 * It is easier here to use us instead of ns for the timeout,
 	 * it prevents from overflows during calculation.
 	 */
 	unsigned int us = DIV_ROUND_UP(ns, 1000);
 	/* Maximum clock frequency is host->bus_hz/2 */
 	return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
 }
 static void atmci_set_timeout(struct atmel_mci *host,
 		struct atmel_mci_slot *slot, struct mmc_data *data)
 {
 	static unsigned	dtomul_to_shift[] = {
 		0, 4, 7, 8, 10, 12, 16, 20
 	};
 	unsigned	timeout;
 	unsigned	dtocyc;
 	unsigned	dtomul;
 	timeout = atmci_ns_to_clocks(host, data->timeout_ns)
 		+ data->timeout_clks;
 	for (dtomul = 0; dtomul < 8; dtomul++) {
 		unsigned shift = dtomul_to_shift[dtomul];
 		dtocyc = (timeout + (1 << shift) - 1) >> shift;
 		if (dtocyc < 15)
 			break;
 	}
 	if (dtomul >= 8) {
 		dtomul = 7;
 		dtocyc = 15;
 	}
 	dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
 			dtocyc << dtomul_to_shift[dtomul]);
 	atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
 }
 /*
  * Return mask with command flags to be enabled for this command.
  */
 static u32 atmci_prepare_command(struct mmc_host *mmc,
 				 struct mmc_command *cmd)
 {
 	struct mmc_data	*data;
 	u32		cmdr;
 	cmd->error = -EINPROGRESS;
 	cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
 	if (cmd->flags & MMC_RSP_PRESENT) {
 		if (cmd->flags & MMC_RSP_136)
 			cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
 		else
 			cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
 	}
 	/*
 	 * This should really be MAXLAT_5 for CMD2 and ACMD41, but
 	 * it's too difficult to determine whether this is an ACMD or
 	 * not. Better make it 64.
 	 */
 	cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
 	if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
 		cmdr |= ATMCI_CMDR_OPDCMD;
 	data = cmd->data;
 	if (data) {
 		cmdr |= ATMCI_CMDR_START_XFER;
 		if (cmd->opcode == SD_IO_RW_EXTENDED) {
 			cmdr |= ATMCI_CMDR_SDIO_BLOCK;
 		} else {
 			if (data->flags & MMC_DATA_STREAM)
 				cmdr |= ATMCI_CMDR_STREAM;
 			else if (data->blocks > 1)
 				cmdr |= ATMCI_CMDR_MULTI_BLOCK;
 			else
 				cmdr |= ATMCI_CMDR_BLOCK;
 		}
 		if (data->flags & MMC_DATA_READ)
 			cmdr |= ATMCI_CMDR_TRDIR_READ;
 	}
 	return cmdr;
 }
 static void atmci_send_command(struct atmel_mci *host,
 		struct mmc_command *cmd, u32 cmd_flags)
 {
 	WARN_ON(host->cmd);
 	host->cmd = cmd;
 	dev_vdbg(&host->pdev->dev,
 			"start command: ARGR=0x%08x CMDR=0x%08x\n",
 			cmd->arg, cmd_flags);
 	atmci_writel(host, ATMCI_ARGR, cmd->arg);
 	atmci_writel(host, ATMCI_CMDR, cmd_flags);
 }
 static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
 {
 	dev_dbg(&host->pdev->dev, "send stop command\n");
 	atmci_send_command(host, data->stop, host->stop_cmdr);
 	atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
 }
 /*
  * Configure given PDC buffer taking care of alignement issues.
  * Update host->data_size and host->sg.
  */
 static void atmci_pdc_set_single_buf(struct atmel_mci *host,
 	enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
 {
 	u32 pointer_reg, counter_reg;
 	unsigned int buf_size;
 	if (dir == XFER_RECEIVE) {
 		pointer_reg = ATMEL_PDC_RPR;
 		counter_reg = ATMEL_PDC_RCR;
 	} else {
 		pointer_reg = ATMEL_PDC_TPR;
 		counter_reg = ATMEL_PDC_TCR;
 	}
 	if (buf_nb == PDC_SECOND_BUF) {
 		pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
 		counter_reg += ATMEL_PDC_SCND_BUF_OFF;
 	}
 	if (!host->caps.has_rwproof) {
 		buf_size = host->buf_size;
 		atmci_writel(host, pointer_reg, host->buf_phys_addr);
 	} else {
 		buf_size = sg_dma_len(host->sg);
 		atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
 	}
 	if (host->data_size <= buf_size) {
 		if (host->data_size & 0x3) {
 			/* If size is different from modulo 4, transfer bytes */
 			atmci_writel(host, counter_reg, host->data_size);
 			atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
 		} else {
 			/* Else transfer 32-bits words */
 			atmci_writel(host, counter_reg, host->data_size / 4);
 		}
 		host->data_size = 0;
 	} else {
 		/* We assume the size of a page is 32-bits aligned */
 		atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
 		host->data_size -= sg_dma_len(host->sg);
 		if (host->data_size)
 			host->sg = sg_next(host->sg);
 	}
 }
 /*
  * Configure PDC buffer according to the data size ie configuring one or two
  * buffers. Don't use this function if you want to configure only the second
  * buffer. In this case, use atmci_pdc_set_single_buf.
  */
 static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
 {
 	atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
 	if (host->data_size)
 		atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
 }
 /*
  * Unmap sg lists, called when transfer is finished.
  */
 static void atmci_pdc_cleanup(struct atmel_mci *host)
 {
 	struct mmc_data         *data = host->data;
 	if (data)
 		dma_unmap_sg(&host->pdev->dev,
 				data->sg, data->sg_len,
 				((data->flags & MMC_DATA_WRITE)
 				 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
 }
 /*
  * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
  * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
  * interrupt needed for both transfer directions.
  */
 static void atmci_pdc_complete(struct atmel_mci *host)
 {
 	int transfer_size = host->data->blocks * host->data->blksz;
 	int i;
 	atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
 	if ((!host->caps.has_rwproof)
 	    && (host->data->flags & MMC_DATA_READ)) {
 		if (host->caps.has_bad_data_ordering)
 			for (i = 0; i < transfer_size; i++)
 				host->buffer[i] = swab32(host->buffer[i]);
 		sg_copy_from_buffer(host->data->sg, host->data->sg_len,
 		                    host->buffer, transfer_size);
 	}
 	atmci_pdc_cleanup(host);
 	/*
 	 * If the card was removed, data will be NULL. No point trying
 	 * to send the stop command or waiting for NBUSY in this case.
 	 */
 	if (host->data) {
 		dev_dbg(&host->pdev->dev,
 		        "(%s) set pending xfer complete\n", __func__);
 		atmci_set_pending(host, EVENT_XFER_COMPLETE);
 		tasklet_schedule(&host->tasklet);
 	}
 }
 static void atmci_dma_cleanup(struct atmel_mci *host)
 {
 	struct mmc_data                 *data = host->data;
 	if (data)
 		dma_unmap_sg(host->dma.chan->device->dev,
 				data->sg, data->sg_len,
 				((data->flags & MMC_DATA_WRITE)
 				 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
 }
 /*
  * This function is called by the DMA driver from tasklet context.
  */
 static void atmci_dma_complete(void *arg)
 {
 	struct atmel_mci	*host = arg;
 	struct mmc_data		*data = host->data;
 	dev_vdbg(&host->pdev->dev, "DMA complete\n");
 	if (host->caps.has_dma)
 		/* Disable DMA hardware handshaking on MCI */
 		atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
 	atmci_dma_cleanup(host);
 	/*
 	 * If the card was removed, data will be NULL. No point trying
 	 * to send the stop command or waiting for NBUSY in this case.
 	 */
 	if (data) {
 		dev_dbg(&host->pdev->dev,
 		        "(%s) set pending xfer complete\n", __func__);
 		atmci_set_pending(host, EVENT_XFER_COMPLETE);
 		tasklet_schedule(&host->tasklet);
 		/*
 		 * Regardless of what the documentation says, we have
 		 * to wait for NOTBUSY even after block read
 		 * operations.
 		 *
 		 * When the DMA transfer is complete, the controller
 		 * may still be reading the CRC from the card, i.e.
 		 * the data transfer is still in progress and we
 		 * haven't seen all the potential error bits yet.
 		 *
 		 * The interrupt handler will schedule a different
 		 * tasklet to finish things up when the data transfer
 		 * is completely done.
 		 *
 		 * We may not complete the mmc request here anyway
 		 * because the mmc layer may call back and cause us to
 		 * violate the "don't submit new operations from the
 		 * completion callback" rule of the dma engine
 		 * framework.
 		 */
 		atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
 	}
 }
 /*
  * Returns a mask of interrupt flags to be enabled after the whole
  * request has been prepared.
  */
 static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
 {
 	u32 iflags;
 	data->error = -EINPROGRESS;
 	host->sg = data->sg;
 	host->data = data;
 	host->data_chan = NULL;
 	iflags = ATMCI_DATA_ERROR_FLAGS;
 	/*
 	 * Errata: MMC data write operation with less than 12
 	 * bytes is impossible.
 	 *
 	 * Errata: MCI Transmit Data Register (TDR) FIFO
 	 * corruption when length is not multiple of 4.
 	 */
 	if (data->blocks * data->blksz < 12
 			|| (data->blocks * data->blksz) & 3)
 		host->need_reset = true;
 	host->pio_offset = 0;
 	if (data->flags & MMC_DATA_READ)
 		iflags |= ATMCI_RXRDY;
 	else
 		iflags |= ATMCI_TXRDY;
 	return iflags;
 }
 /*
  * Set interrupt flags and set block length into the MCI mode register even
  * if this value is also accessible in the MCI block register. It seems to be
  * necessary before the High Speed MCI version. It also map sg and configure
  * PDC registers.
  */
 static u32
 atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
 {
 	u32 iflags, tmp;
 	unsigned int sg_len;
 	enum dma_data_direction dir;
 	int i;
 	data->error = -EINPROGRESS;
 	host->data = data;
 	host->sg = data->sg;
 	iflags = ATMCI_DATA_ERROR_FLAGS;
 	/* Enable pdc mode */
 	atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
 	if (data->flags & MMC_DATA_READ) {
 		dir = DMA_FROM_DEVICE;
 		iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
 	} else {
 		dir = DMA_TO_DEVICE;
 		iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE;
 	}
 	/* Set BLKLEN */
 	tmp = atmci_readl(host, ATMCI_MR);
 	tmp &= 0x0000ffff;
 	tmp |= ATMCI_BLKLEN(data->blksz);
 	atmci_writel(host, ATMCI_MR, tmp);
 	/* Configure PDC */
 	host->data_size = data->blocks * data->blksz;
 	sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir);
 	if ((!host->caps.has_rwproof)
 	    && (host->data->flags & MMC_DATA_WRITE)) {
 		sg_copy_to_buffer(host->data->sg, host->data->sg_len,
 		                  host->buffer, host->data_size);
 		if (host->caps.has_bad_data_ordering)
 			for (i = 0; i < host->data_size; i++)
 				host->buffer[i] = swab32(host->buffer[i]);
 	}
 	if (host->data_size)
 		atmci_pdc_set_both_buf(host,
 			((dir == DMA_FROM_DEVICE) ? XFER_RECEIVE : XFER_TRANSMIT));
 	return iflags;
 }
 static u32
 atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
 {
 	struct dma_chan			*chan;
 	struct dma_async_tx_descriptor	*desc;
 	struct scatterlist		*sg;
 	unsigned int			i;
 	enum dma_data_direction		direction;
 	enum dma_transfer_direction	slave_dirn;
 	unsigned int			sglen;
 	u32				maxburst;
 	u32 iflags;
 	data->error = -EINPROGRESS;
 	WARN_ON(host->data);
 	host->sg = NULL;
 	host->data = data;
 	iflags = ATMCI_DATA_ERROR_FLAGS;
 	/*
 	 * We don't do DMA on "complex" transfers, i.e. with
 	 * non-word-aligned buffers or lengths. Also, we don't bother
 	 * with all the DMA setup overhead for short transfers.
 	 */
 	if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
 		return atmci_prepare_data(host, data);
 	if (data->blksz & 3)
 		return atmci_prepare_data(host, data);
 	for_each_sg(data->sg, sg, data->sg_len, i) {
 		if (sg->offset & 3 || sg->length & 3)
 			return atmci_prepare_data(host, data);
 	}
 	/* If we don't have a channel, we can't do DMA */
 	chan = host->dma.chan;
 	if (chan)
 		host->data_chan = chan;
 	if (!chan)
 		return -ENODEV;
 	if (data->flags & MMC_DATA_READ) {
 		direction = DMA_FROM_DEVICE;
 		host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
 		maxburst = atmci_convert_chksize(host->dma_conf.src_maxburst);
 	} else {
 		direction = DMA_TO_DEVICE;
 		host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
 		maxburst = atmci_convert_chksize(host->dma_conf.dst_maxburst);
 	}
 	atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) | ATMCI_DMAEN);
 	sglen = dma_map_sg(chan->device->dev, data->sg,
 			data->sg_len, direction);
 	dmaengine_slave_config(chan, &host->dma_conf);
 	desc = dmaengine_prep_slave_sg(chan,
 			data->sg, sglen, slave_dirn,
 			DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 	if (!desc)
 		goto unmap_exit;
 	host->dma.data_desc = desc;
 	desc->callback = atmci_dma_complete;
 	desc->callback_param = host;
 	return iflags;
 unmap_exit:
 	dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, direction);
 	return -ENOMEM;
 }
 static void
 atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
 {
 	return;
 }
 /*
  * Start PDC according to transfer direction.
  */
 static void
 atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
 {
 	if (data->flags & MMC_DATA_READ)
 		atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
 	else
 		atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
 }
 static void
 atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
 {
 	struct dma_chan			*chan = host->data_chan;
 	struct dma_async_tx_descriptor	*desc = host->dma.data_desc;
 	if (chan) {
 		dmaengine_submit(desc);
 		dma_async_issue_pending(chan);
 	}
 }
 static void atmci_stop_transfer(struct atmel_mci *host)
 {
 	dev_dbg(&host->pdev->dev,
 	        "(%s) set pending xfer complete\n", __func__);
 	atmci_set_pending(host, EVENT_XFER_COMPLETE);
 	atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
 }
 /*
  * Stop data transfer because error(s) occured.
  */
 static void atmci_stop_transfer_pdc(struct atmel_mci *host)
 {
 	atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
 }
 static void atmci_stop_transfer_dma(struct atmel_mci *host)
 {
 	struct dma_chan *chan = host->data_chan;
 	if (chan) {
 		dmaengine_terminate_all(chan);
 		atmci_dma_cleanup(host);
 	} else {
 		/* Data transfer was stopped by the interrupt handler */
 		dev_dbg(&host->pdev->dev,
 		        "(%s) set pending xfer complete\n", __func__);
 		atmci_set_pending(host, EVENT_XFER_COMPLETE);
 		atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
 	}
 }
 /*
  * Start a request: prepare data if needed, prepare the command and activate
  * interrupts.
  */
 static void atmci_start_request(struct atmel_mci *host,
 		struct atmel_mci_slot *slot)
 {
 	struct mmc_request	*mrq;
 	struct mmc_command	*cmd;
 	struct mmc_data		*data;
 	u32			iflags;
 	u32			cmdflags;
 	mrq = slot->mrq;
 	host->cur_slot = slot;
 	host->mrq = mrq;
 	host->pending_events = 0;
 	host->completed_events = 0;
 	host->cmd_status = 0;
 	host->data_status = 0;
 	dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode);
 	if (host->need_reset || host->caps.need_reset_after_xfer) {
 		iflags = atmci_readl(host, ATMCI_IMR);
 		iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
 		atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
 		atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
 		atmci_writel(host, ATMCI_MR, host->mode_reg);
 		if (host->caps.has_cfg_reg)
 			atmci_writel(host, ATMCI_CFG, host->cfg_reg);
 		atmci_writel(host, ATMCI_IER, iflags);
 		host->need_reset = false;
 	}
 	atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
 	iflags = atmci_readl(host, ATMCI_IMR);
 	if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
 		dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
 				iflags);
 	if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
 		/* Send init sequence (74 clock cycles) */
 		atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
 		while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
 			cpu_relax();
 	}
 	iflags = 0;
 	data = mrq->data;
 	if (data) {
 		atmci_set_timeout(host, slot, data);
 		/* Must set block count/size before sending command */
 		atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
 				| ATMCI_BLKLEN(data->blksz));
 		dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
 			ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
 		iflags |= host->prepare_data(host, data);
 	}
 	iflags |= ATMCI_CMDRDY;
 	cmd = mrq->cmd;
 	cmdflags = atmci_prepare_command(slot->mmc, cmd);
 	atmci_send_command(host, cmd, cmdflags);
 	if (data)
 		host->submit_data(host, data);
 	if (mrq->stop) {
 		host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
 		host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
 		if (!(data->flags & MMC_DATA_WRITE))
 			host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
 		if (data->flags & MMC_DATA_STREAM)
 			host->stop_cmdr |= ATMCI_CMDR_STREAM;
 		else
 			host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
 	}
 	/*
 	 * We could have enabled interrupts earlier, but I suspect
 	 * that would open up a nice can of interesting race
 	 * conditions (e.g. command and data complete, but stop not
 	 * prepared yet.)
 	 */
 	atmci_writel(host, ATMCI_IER, iflags);
 	mod_timer(&host->timer, jiffies +  msecs_to_jiffies(2000));
 }
 static void atmci_queue_request(struct atmel_mci *host,
 		struct atmel_mci_slot *slot, struct mmc_request *mrq)
 {
 	dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
 			host->state);
 	spin_lock_bh(&host->lock);
 	slot->mrq = mrq;
 	if (host->state == STATE_IDLE) {
 		host->state = STATE_SENDING_CMD;
 		atmci_start_request(host, slot);
 	} else {
 		dev_dbg(&host->pdev->dev, "queue request\n");
 		list_add_tail(&slot->queue_node, &host->queue);
 	}
 	spin_unlock_bh(&host->lock);
 }
 static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 {
 	struct atmel_mci_slot	*slot = mmc_priv(mmc);
 	struct atmel_mci	*host = slot->host;
 	struct mmc_data		*data;
 	WARN_ON(slot->mrq);
 	dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode);
 	/*
 	 * We may "know" the card is gone even though there's still an
 	 * electrical connection. If so, we really need to communicate
 	 * this to the MMC core since there won't be any more
 	 * interrupts as the card is completely removed. Otherwise,
 	 * the MMC core might believe the card is still there even
 	 * though the card was just removed very slowly.
 	 */
 	if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
 		mrq->cmd->error = -ENOMEDIUM;
 		mmc_request_done(mmc, mrq);
 		return;
 	}
 	/* We don't support multiple blocks of weird lengths. */
 	data = mrq->data;
 	if (data && data->blocks > 1 && data->blksz & 3) {
 		mrq->cmd->error = -EINVAL;
 		mmc_request_done(mmc, mrq);
 	}
 	atmci_queue_request(host, slot, mrq);
 }
 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 {
 	struct atmel_mci_slot	*slot = mmc_priv(mmc);
 	struct atmel_mci	*host = slot->host;
 	unsigned int		i;
 	slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
 	switch (ios->bus_width) {
 	case MMC_BUS_WIDTH_1:
 		slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
 		break;
 	case MMC_BUS_WIDTH_4:
 		slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
 		break;
 	}
 	if (ios->clock) {
 		unsigned int clock_min = ~0U;
 		u32 clkdiv;
 		spin_lock_bh(&host->lock);
 		if (!host->mode_reg) {
 			clk_enable(host->mck);
 			atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
 			atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
 			if (host->caps.has_cfg_reg)
 				atmci_writel(host, ATMCI_CFG, host->cfg_reg);
 		}
 		/*
 		 * Use mirror of ios->clock to prevent race with mmc
 		 * core ios update when finding the minimum.
 		 */
 		slot->clock = ios->clock;
 		for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
 			if (host->slot[i] && host->slot[i]->clock
 					&& host->slot[i]->clock < clock_min)
 				clock_min = host->slot[i]->clock;
 		}
 		/* Calculate clock divider */
 		if (host->caps.has_odd_clk_div) {
 			clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
 			if (clkdiv > 511) {
 				dev_warn(&mmc->class_dev,
 				         "clock %u too slow; using %lu\n",
 				         clock_min, host->bus_hz / (511 + 2));
 				clkdiv = 511;
 			}
 			host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
 			                 | ATMCI_MR_CLKODD(clkdiv & 1);
 		} else {
 			clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
 			if (clkdiv > 255) {
 				dev_warn(&mmc->class_dev,
 				         "clock %u too slow; using %lu\n",
 				         clock_min, host->bus_hz / (2 * 256));
 				clkdiv = 255;
 			}
 			host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
 		}
 		/*
 		 * WRPROOF and RDPROOF prevent overruns/underruns by
 		 * stopping the clock when the FIFO is full/empty.
 		 * This state is not expected to last for long.
 		 */
 		if (host->caps.has_rwproof)
 			host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
 		if (host->caps.has_cfg_reg) {
 			/* setup High Speed mode in relation with card capacity */
 			if (ios->timing == MMC_TIMING_SD_HS)
 				host->cfg_reg |= ATMCI_CFG_HSMODE;
 			else
 				host->cfg_reg &= ~ATMCI_CFG_HSMODE;
 		}
 		if (list_empty(&host->queue)) {
 			atmci_writel(host, ATMCI_MR, host->mode_reg);
 			if (host->caps.has_cfg_reg)
 				atmci_writel(host, ATMCI_CFG, host->cfg_reg);
 		} else {
 			host->need_clock_update = true;
 		}
 		spin_unlock_bh(&host->lock);
 	} else {
 		bool any_slot_active = false;
 		spin_lock_bh(&host->lock);
 		slot->clock = 0;
 		for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
 			if (host->slot[i] && host->slot[i]->clock) {
 				any_slot_active = true;
 				break;
 			}
 		}
 		if (!any_slot_active) {
 			atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
 			if (host->mode_reg) {
 				atmci_readl(host, ATMCI_MR);
 				clk_disable(host->mck);
 			}
 			host->mode_reg = 0;
 		}
 		spin_unlock_bh(&host->lock);
 	}
 	switch (ios->power_mode) {
 	case MMC_POWER_UP:
 		set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
 		break;
 	default:
 		/*
 		 * TODO: None of the currently available AVR32-based
 		 * boards allow MMC power to be turned off. Implement
 		 * power control when this can be tested properly.
 		 *
 		 * We also need to hook this into the clock management
 		 * somehow so that newly inserted cards aren't
 		 * subjected to a fast clock before we have a chance
 		 * to figure out what the maximum rate is. Currently,
 		 * there's no way to avoid this, and there never will
 		 * be for boards that don't support power control.
 		 */
 		break;
 	}
 }
 static int atmci_get_ro(struct mmc_host *mmc)
 {
 	int			read_only = -ENOSYS;
 	struct atmel_mci_slot	*slot = mmc_priv(mmc);
 	if (gpio_is_valid(slot->wp_pin)) {
 		read_only = gpio_get_value(slot->wp_pin);
 		dev_dbg(&mmc->class_dev, "card is %s\n",
 				read_only ? "read-only" : "read-write");
 	}
 	return read_only;
 }
 static int atmci_get_cd(struct mmc_host *mmc)
 {
 	int			present = -ENOSYS;
 	struct atmel_mci_slot	*slot = mmc_priv(mmc);
 	if (gpio_is_valid(slot->detect_pin)) {
 		present = !(gpio_get_value(slot->detect_pin) ^
 			    slot->detect_is_active_high);
 		dev_dbg(&mmc->class_dev, "card is %spresent\n",
 				present ? "" : "not ");
 	}
 	return present;
 }
 static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
 {
 	struct atmel_mci_slot	*slot = mmc_priv(mmc);
 	struct atmel_mci	*host = slot->host;
 	if (enable)
 		atmci_writel(host, ATMCI_IER, slot->sdio_irq);
 	else
 		atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
 }
 static const struct mmc_host_ops atmci_ops = {
 	.request	= atmci_request,
 	.set_ios	= atmci_set_ios,
 	.get_ro		= atmci_get_ro,
 	.get_cd		= atmci_get_cd,
 	.enable_sdio_irq = atmci_enable_sdio_irq,
 };
 /* Called with host->lock held */
 static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
 	__releases(&host->lock)
 	__acquires(&host->lock)
 {
 	struct atmel_mci_slot	*slot = NULL;
 	struct mmc_host		*prev_mmc = host->cur_slot->mmc;
 	WARN_ON(host->cmd || host->data);
 	/*
 	 * Update the MMC clock rate if necessary. This may be
 	 * necessary if set_ios() is called when a different slot is
 	 * busy transferring data.
 	 */
 	if (host->need_clock_update) {
 		atmci_writel(host, ATMCI_MR, host->mode_reg);
 		if (host->caps.has_cfg_reg)
 			atmci_writel(host, ATMCI_CFG, host->cfg_reg);
 	}
 	host->cur_slot->mrq = NULL;
 	host->mrq = NULL;
 	if (!list_empty(&host->queue)) {
 		slot = list_entry(host->queue.next,
 				struct atmel_mci_slot, queue_node);
 		list_del(&slot->queue_node);
 		dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
 				mmc_hostname(slot->mmc));
 		host->state = STATE_SENDING_CMD;
 		atmci_start_request(host, slot);
 	} else {
 		dev_vdbg(&host->pdev->dev, "list empty\n");
 		host->state = STATE_IDLE;
 	}
 	del_timer(&host->timer);
 	spin_unlock(&host->lock);
 	mmc_request_done(prev_mmc, mrq);
 	spin_lock(&host->lock);
 }
 static void atmci_command_complete(struct atmel_mci *host,
 			struct mmc_command *cmd)
 {
 	u32		status = host->cmd_status;
 	/* Read the response from the card (up to 16 bytes) */
 	cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
 	cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
 	cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
 	cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
 	if (status & ATMCI_RTOE)
 		cmd->error = -ETIMEDOUT;
 	else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
 		cmd->error = -EILSEQ;
 	else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
 		cmd->error = -EIO;
 	else if (host->mrq->data && (host->mrq->data->blksz & 3)) {
 		if (host->caps.need_blksz_mul_4) {
 			cmd->error = -EINVAL;
 			host->need_reset = 1;
 		}
 	} else
 		cmd->error = 0;
 }
 static void atmci_detect_change(unsigned long data)
 {
 	struct atmel_mci_slot	*slot = (struct atmel_mci_slot *)data;
 	bool			present;
 	bool			present_old;
 	/*
 	 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
 	 * freeing the interrupt. We must not re-enable the interrupt
 	 * if it has been freed, and if we're shutting down, it
 	 * doesn't really matter whether the card is present or not.
 	 */
 	smp_rmb();
 	if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
 		return;
 	enable_irq(gpio_to_irq(slot->detect_pin));
 	present = !(gpio_get_value(slot->detect_pin) ^
 		    slot->detect_is_active_high);
 	present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
 	dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
 			present, present_old);
 	if (present != present_old) {
 		struct atmel_mci	*host = slot->host;
 		struct mmc_request	*mrq;
 		dev_dbg(&slot->mmc->class_dev, "card %s\n",
 			present ? "inserted" : "removed");
 		spin_lock(&host->lock);
 		if (!present)
 			clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
 		else
 			set_bit(ATMCI_CARD_PRESENT, &slot->flags);
 		/* Clean up queue if present */
 		mrq = slot->mrq;
 		if (mrq) {
 			if (mrq == host->mrq) {
 				/*
 				 * Reset controller to terminate any ongoing
 				 * commands or data transfers.
 				 */
 				atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
 				atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
 				atmci_writel(host, ATMCI_MR, host->mode_reg);
 				if (host->caps.has_cfg_reg)
 					atmci_writel(host, ATMCI_CFG, host->cfg_reg);
 				host->data = NULL;
 				host->cmd = NULL;
 				switch (host->state) {
 				case STATE_IDLE:
 					break;
 				case STATE_SENDING_CMD:
 					mrq->cmd->error = -ENOMEDIUM;
 					if (mrq->data)
 						host->stop_transfer(host);
 					break;
 				case STATE_DATA_XFER:
 					mrq->data->error = -ENOMEDIUM;
 					host->stop_transfer(host);
 					break;
 				case STATE_WAITING_NOTBUSY:
 					mrq->data->error = -ENOMEDIUM;
 					break;
 				case STATE_SENDING_STOP:
 					mrq->stop->error = -ENOMEDIUM;
 					break;
 				case STATE_END_REQUEST:
 					break;
 				}
 				atmci_request_end(host, mrq);
 			} else {
 				list_del(&slot->queue_node);
 				mrq->cmd->error = -ENOMEDIUM;
 				if (mrq->data)
 					mrq->data->error = -ENOMEDIUM;
 				if (mrq->stop)
 					mrq->stop->error = -ENOMEDIUM;
 				spin_unlock(&host->lock);
 				mmc_request_done(slot->mmc, mrq);
 				spin_lock(&host->lock);
 			}
 		}
 		spin_unlock(&host->lock);
 		mmc_detect_change(slot->mmc, 0);
 	}
 }
 static void atmci_tasklet_func(unsigned long priv)
 {
 	struct atmel_mci	*host = (struct atmel_mci *)priv;
 	struct mmc_request	*mrq = host->mrq;
 	struct mmc_data		*data = host->data;
 	enum atmel_mci_state	state = host->state;
 	enum atmel_mci_state	prev_state;
 	u32			status;
 	spin_lock(&host->lock);
 	state = host->state;
 	dev_vdbg(&host->pdev->dev,
 		"tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
 		state, host->pending_events, host->completed_events,
 		atmci_readl(host, ATMCI_IMR));
 	do {
 		prev_state = state;
 		dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state);
 		switch (state) {
 		case STATE_IDLE:
 			break;
 		case STATE_SENDING_CMD:
 			/*
 			 * Command has been sent, we are waiting for command
 			 * ready. Then we have three next states possible:
 			 * END_REQUEST by default, WAITING_NOTBUSY if it's a
 			 * command needing it or DATA_XFER if there is data.
 			 */
 			dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
 			if (!atmci_test_and_clear_pending(host,
 						EVENT_CMD_RDY))
 				break;
 			dev_dbg(&host->pdev->dev, "set completed cmd ready\n");
 			host->cmd = NULL;
 			atmci_set_completed(host, EVENT_CMD_RDY);
 			atmci_command_complete(host, mrq->cmd);
 			if (mrq->data) {
 				dev_dbg(&host->pdev->dev,
 				        "command with data transfer");
 				/*
 				 * If there is a command error don't start
 				 * data transfer.
 				 */
 				if (mrq->cmd->error) {
 					host->stop_transfer(host);
 					host->data = NULL;
 					atmci_writel(host, ATMCI_IDR,
 					             ATMCI_TXRDY | ATMCI_RXRDY
 					             | ATMCI_DATA_ERROR_FLAGS);
 					state = STATE_END_REQUEST;
 				} else
 					state = STATE_DATA_XFER;
 			} else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) {
 				dev_dbg(&host->pdev->dev,
 				        "command response need waiting notbusy");
 				atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
 				state = STATE_WAITING_NOTBUSY;
 			} else
 				state = STATE_END_REQUEST;
 			break;
 		case STATE_DATA_XFER:
 			if (atmci_test_and_clear_pending(host,
 						EVENT_DATA_ERROR)) {
 				dev_dbg(&host->pdev->dev, "set completed data error\n");
 				atmci_set_completed(host, EVENT_DATA_ERROR);
 				state = STATE_END_REQUEST;
 				break;
 			}
 			/*
 			 * A data transfer is in progress. The event expected
 			 * to move to the next state depends of data transfer
 			 * type (PDC or DMA). Once transfer done we can move
 			 * to the next step which is WAITING_NOTBUSY in write
 			 * case and directly SENDING_STOP in read case.
 			 */
 			dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n");
 			if (!atmci_test_and_clear_pending(host,
 						EVENT_XFER_COMPLETE))
 				break;
 			dev_dbg(&host->pdev->dev,
 			        "(%s) set completed xfer complete\n",
 				__func__);
 			atmci_set_completed(host, EVENT_XFER_COMPLETE);
-			if (host->data->flags & MMC_DATA_WRITE) {
+			if (host->caps.need_notbusy_for_read_ops ||
+			   (host->data->flags & MMC_DATA_WRITE)) {
 				atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
 				state = STATE_WAITING_NOTBUSY;
 			} else if (host->mrq->stop) {
 				atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
 				atmci_send_stop_cmd(host, data);
 				state = STATE_SENDING_STOP;
 			} else {
 				host->data = NULL;
 				data->bytes_xfered = data->blocks * data->blksz;
 				data->error = 0;
 				state = STATE_END_REQUEST;
 			}
 			break;
 		case STATE_WAITING_NOTBUSY:
 			/*
 			 * We can be in the state for two reasons: a command
 			 * requiring waiting not busy signal (stop command
 			 * included) or a write operation. In the latest case,
 			 * we need to send a stop command.
 			 */
 			dev_dbg(&host->pdev->dev, "FSM: not busy?\n");
 			if (!atmci_test_and_clear_pending(host,
 						EVENT_NOTBUSY))
 				break;
 			dev_dbg(&host->pdev->dev, "set completed not busy\n");
 			atmci_set_completed(host, EVENT_NOTBUSY);
 			if (host->data) {
 				/*
 				 * For some commands such as CMD53, even if
 				 * there is data transfer, there is no stop
 				 * command to send.
 				 */
 				if (host->mrq->stop) {
 					atmci_writel(host, ATMCI_IER,
 					             ATMCI_CMDRDY);
 					atmci_send_stop_cmd(host, data);
 					state = STATE_SENDING_STOP;
 				} else {
 					host->data = NULL;
 					data->bytes_xfered = data->blocks
 					                     * data->blksz;
 					data->error = 0;
 					state = STATE_END_REQUEST;
 				}
 			} else
 				state = STATE_END_REQUEST;
 			break;
 		case STATE_SENDING_STOP:
 			/*
 			 * In this state, it is important to set host->data to
 			 * NULL (which is tested in the waiting notbusy state)
 			 * in order to go to the end request state instead of
 			 * sending stop again.
 			 */
 			dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
 			if (!atmci_test_and_clear_pending(host,
 						EVENT_CMD_RDY))
 				break;
 			dev_dbg(&host->pdev->dev, "FSM: cmd ready\n");
 			host->cmd = NULL;
 			data->bytes_xfered = data->blocks * data->blksz;
 			data->error = 0;
 			atmci_command_complete(host, mrq->stop);
 			if (mrq->stop->error) {
 				host->stop_transfer(host);
 				atmci_writel(host, ATMCI_IDR,
 				             ATMCI_TXRDY | ATMCI_RXRDY
 				             | ATMCI_DATA_ERROR_FLAGS);
 				state = STATE_END_REQUEST;
 			} else {
 				atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
 				state = STATE_WAITING_NOTBUSY;
 			}
 			host->data = NULL;
 			break;
 		case STATE_END_REQUEST:
 			atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY
 			                   | ATMCI_DATA_ERROR_FLAGS);
 			status = host->data_status;
 			if (unlikely(status)) {
 				host->stop_transfer(host);
 				host->data = NULL;
 				if (status & ATMCI_DTOE) {
 					data->error = -ETIMEDOUT;
 				} else if (status & ATMCI_DCRCE) {
 					data->error = -EILSEQ;
 				} else {
 					data->error = -EIO;
 				}
 			}
 			atmci_request_end(host, host->mrq);
 			state = STATE_IDLE;
 			break;
 		}
 	} while (state != prev_state);
 	host->state = state;
 	spin_unlock(&host->lock);
 }
 static void atmci_read_data_pio(struct atmel_mci *host)
 {
 	struct scatterlist	*sg = host->sg;
 	void			*buf = sg_virt(sg);
 	unsigned int		offset = host->pio_offset;
 	struct mmc_data		*data = host->data;
 	u32			value;
 	u32			status;
 	unsigned int		nbytes = 0;
 	do {
 		value = atmci_readl(host, ATMCI_RDR);
 		if (likely(offset + 4 <= sg->length)) {
 			put_unaligned(value, (u32 *)(buf + offset));
 			offset += 4;
 			nbytes += 4;
 			if (offset == sg->length) {
 				flush_dcache_page(sg_page(sg));
 				host->sg = sg = sg_next(sg);
 				if (!sg)
 					goto done;
 				offset = 0;
 				buf = sg_virt(sg);
 			}
 		} else {
 			unsigned int remaining = sg->length - offset;
 			memcpy(buf + offset, &value, remaining);
 			nbytes += remaining;
 			flush_dcache_page(sg_page(sg));
 			host->sg = sg = sg_next(sg);
 			if (!sg)
 				goto done;
 			offset = 4 - remaining;
 			buf = sg_virt(sg);
 			memcpy(buf, (u8 *)&value + remaining, offset);
 			nbytes += offset;
 		}
 		status = atmci_readl(host, ATMCI_SR);
 		if (status & ATMCI_DATA_ERROR_FLAGS) {
 			atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
 						| ATMCI_DATA_ERROR_FLAGS));
 			host->data_status = status;
 			data->bytes_xfered += nbytes;
 			return;
 		}
 	} while (status & ATMCI_RXRDY);
 	host->pio_offset = offset;
 	data->bytes_xfered += nbytes;
 	return;
 done:
 	atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
 	atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
 	data->bytes_xfered += nbytes;
 	smp_wmb();
 	atmci_set_pending(host, EVENT_XFER_COMPLETE);
 }
 static void atmci_write_data_pio(struct atmel_mci *host)
 {
 	struct scatterlist	*sg = host->sg;
 	void			*buf = sg_virt(sg);
 	unsigned int		offset = host->pio_offset;
 	struct mmc_data		*data = host->data;
 	u32			value;
 	u32			status;
 	unsigned int		nbytes = 0;
 	do {
 		if (likely(offset + 4 <= sg->length)) {
 			value = get_unaligned((u32 *)(buf + offset));
 			atmci_writel(host, ATMCI_TDR, value);
 			offset += 4;
 			nbytes += 4;
 			if (offset == sg->length) {
 				host->sg = sg = sg_next(sg);
 				if (!sg)
 					goto done;
 				offset = 0;
 				buf = sg_virt(sg);
 			}
 		} else {
 			unsigned int remaining = sg->length - offset;
 			value = 0;
 			memcpy(&value, buf + offset, remaining);
 			nbytes += remaining;
 			host->sg = sg = sg_next(sg);
 			if (!sg) {
 				atmci_writel(host, ATMCI_TDR, value);
 				goto done;
 			}
 			offset = 4 - remaining;
 			buf = sg_virt(sg);
 			memcpy((u8 *)&value + remaining, buf, offset);
 			atmci_writel(host, ATMCI_TDR, value);
 			nbytes += offset;
 		}
 		status = atmci_readl(host, ATMCI_SR);
 		if (status & ATMCI_DATA_ERROR_FLAGS) {
 			atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
 						| ATMCI_DATA_ERROR_FLAGS));
 			host->data_status = status;
 			data->bytes_xfered += nbytes;
 			return;
 		}
 	} while (status & ATMCI_TXRDY);
 	host->pio_offset = offset;
 	data->bytes_xfered += nbytes;
 	return;
 done:
 	atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
 	atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
 	data->bytes_xfered += nbytes;
 	smp_wmb();
 	atmci_set_pending(host, EVENT_XFER_COMPLETE);
 }
 static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
 {
 	int	i;
 	for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
 		struct atmel_mci_slot *slot = host->slot[i];
 		if (slot && (status & slot->sdio_irq)) {
 			mmc_signal_sdio_irq(slot->mmc);
 		}
 	}
 }
 static irqreturn_t atmci_interrupt(int irq, void *dev_id)
 {
 	struct atmel_mci	*host = dev_id;
 	u32			status, mask, pending;
 	unsigned int		pass_count = 0;
 	do {
 		status = atmci_readl(host, ATMCI_SR);
 		mask = atmci_readl(host, ATMCI_IMR);
 		pending = status & mask;
 		if (!pending)
 			break;
 		if (pending & ATMCI_DATA_ERROR_FLAGS) {
 			dev_dbg(&host->pdev->dev, "IRQ: data error\n");
 			atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
 					| ATMCI_RXRDY | ATMCI_TXRDY
 					| ATMCI_ENDRX | ATMCI_ENDTX
 					| ATMCI_RXBUFF | ATMCI_TXBUFE);
 			host->data_status = status;
 			dev_dbg(&host->pdev->dev, "set pending data error\n");
 			smp_wmb();
 			atmci_set_pending(host, EVENT_DATA_ERROR);
 			tasklet_schedule(&host->tasklet);
 		}
 		if (pending & ATMCI_TXBUFE) {
 			dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n");
 			atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
 			atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
 			/*
 			 * We can receive this interruption before having configured
 			 * the second pdc buffer, so we need to reconfigure first and
 			 * second buffers again
 			 */
 			if (host->data_size) {
 				atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
 				atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
 				atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
 			} else {
 				atmci_pdc_complete(host);
 			}
 		} else if (pending & ATMCI_ENDTX) {
 			dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n");
 			atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
 			if (host->data_size) {
 				atmci_pdc_set_single_buf(host,
 						XFER_TRANSMIT, PDC_SECOND_BUF);
 				atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
 			}
 		}
 		if (pending & ATMCI_RXBUFF) {
 			dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n");
 			atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
 			atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
 			/*
 			 * We can receive this interruption before having configured
 			 * the second pdc buffer, so we need to reconfigure first and
 			 * second buffers again
 			 */
 			if (host->data_size) {
 				atmci_pdc_set_both_buf(host, XFER_RECEIVE);
 				atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
 				atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
 			} else {
 				atmci_pdc_complete(host);
 			}
 		} else if (pending & ATMCI_ENDRX) {
 			dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n");
 			atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
 			if (host->data_size) {
 				atmci_pdc_set_single_buf(host,
 						XFER_RECEIVE, PDC_SECOND_BUF);
 				atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
 			}
 		}
 		/*
 		 * First mci IPs, so mainly the ones having pdc, have some
 		 * issues with the notbusy signal. You can't get it after
 		 * data transmission if you have not sent a stop command.
 		 * The appropriate workaround is to use the BLKE signal.
 		 */
 		if (pending & ATMCI_BLKE) {
 			dev_dbg(&host->pdev->dev, "IRQ: blke\n");
 			atmci_writel(host, ATMCI_IDR, ATMCI_BLKE);
 			smp_wmb();
 			dev_dbg(&host->pdev->dev, "set pending notbusy\n");
 			atmci_set_pending(host, EVENT_NOTBUSY);
 			tasklet_schedule(&host->tasklet);
 		}
 		if (pending & ATMCI_NOTBUSY) {
 			dev_dbg(&host->pdev->dev, "IRQ: not_busy\n");
 			atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY);
 			smp_wmb();
 			dev_dbg(&host->pdev->dev, "set pending notbusy\n");
 			atmci_set_pending(host, EVENT_NOTBUSY);
 			tasklet_schedule(&host->tasklet);
 		}
 		if (pending & ATMCI_RXRDY)
 			atmci_read_data_pio(host);
 		if (pending & ATMCI_TXRDY)
 			atmci_write_data_pio(host);
 		if (pending & ATMCI_CMDRDY) {
 			dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n");
 			atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
 			host->cmd_status = status;
 			smp_wmb();
 			dev_dbg(&host->pdev->dev, "set pending cmd rdy\n");
 			atmci_set_pending(host, EVENT_CMD_RDY);
 			tasklet_schedule(&host->tasklet);
 		}
 		if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
 			atmci_sdio_interrupt(host, status);
 	} while (pass_count++ < 5);
 	return pass_count ? IRQ_HANDLED : IRQ_NONE;
 }
 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
 {
 	struct atmel_mci_slot	*slot = dev_id;
 	/*
 	 * Disable interrupts until the pin has stabilized and check
 	 * the state then. Use mod_timer() since we may be in the
 	 * middle of the timer routine when this interrupt triggers.
 	 */
 	disable_irq_nosync(irq);
 	mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
 	return IRQ_HANDLED;
 }
 static int __init atmci_init_slot(struct atmel_mci *host,
 		struct mci_slot_pdata *slot_data, unsigned int id,
 		u32 sdc_reg, u32 sdio_irq)
 {
 	struct mmc_host			*mmc;
 	struct atmel_mci_slot		*slot;
 	mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
 	if (!mmc)
 		return -ENOMEM;
 	slot = mmc_priv(mmc);
 	slot->mmc = mmc;
 	slot->host = host;
 	slot->detect_pin = slot_data->detect_pin;
 	slot->wp_pin = slot_data->wp_pin;
 	slot->detect_is_active_high = slot_data->detect_is_active_high;
 	slot->sdc_reg = sdc_reg;
 	slot->sdio_irq = sdio_irq;
 	mmc->ops = &atmci_ops;
 	mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
 	mmc->f_max = host->bus_hz / 2;
 	mmc->ocr_avail	= MMC_VDD_32_33 | MMC_VDD_33_34;
 	if (sdio_irq)
 		mmc->caps |= MMC_CAP_SDIO_IRQ;
 	if (host->caps.has_highspeed)
 		mmc->caps |= MMC_CAP_SD_HIGHSPEED;
 	/*
 	 * Without the read/write proof capability, it is strongly suggested to
 	 * use only one bit for data to prevent fifo underruns and overruns
 	 * which will corrupt data.
 	 */
 	if ((slot_data->bus_width >= 4) && host->caps.has_rwproof)
 		mmc->caps |= MMC_CAP_4_BIT_DATA;
 	if (atmci_get_version(host) < 0x200) {
 		mmc->max_segs = 256;
 		mmc->max_blk_size = 4095;
 		mmc->max_blk_count = 256;
 		mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
 		mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs;
 	} else {
 		mmc->max_segs = 64;
 		mmc->max_req_size = 32768 * 512;
 		mmc->max_blk_size = 32768;
 		mmc->max_blk_count = 512;
 	}
 	/* Assume card is present initially */
 	set_bit(ATMCI_CARD_PRESENT, &slot->flags);
 	if (gpio_is_valid(slot->detect_pin)) {
 		if (gpio_request(slot->detect_pin, "mmc_detect")) {
 			dev_dbg(&mmc->class_dev, "no detect pin available\n");
 			slot->detect_pin = -EBUSY;
 		} else if (gpio_get_value(slot->detect_pin) ^
 				slot->detect_is_active_high) {
 			clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
 		}
 	}
 	if (!gpio_is_valid(slot->detect_pin))
 		mmc->caps |= MMC_CAP_NEEDS_POLL;
 	if (gpio_is_valid(slot->wp_pin)) {
 		if (gpio_request(slot->wp_pin, "mmc_wp")) {
 			dev_dbg(&mmc->class_dev, "no WP pin available\n");
 			slot->wp_pin = -EBUSY;
 		}
 	}
 	host->slot[id] = slot;
 	mmc_add_host(mmc);
 	if (gpio_is_valid(slot->detect_pin)) {
 		int ret;
 		setup_timer(&slot->detect_timer, atmci_detect_change,
 				(unsigned long)slot);
 		ret = request_irq(gpio_to_irq(slot->detect_pin),
 				atmci_detect_interrupt,
 				IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
 				"mmc-detect", slot);
 		if (ret) {
 			dev_dbg(&mmc->class_dev,
 				"could not request IRQ %d for detect pin\n",
 				gpio_to_irq(slot->detect_pin));
 			gpio_free(slot->detect_pin);
 			slot->detect_pin = -EBUSY;
 		}
 	}
 	atmci_init_debugfs(slot);
 	return 0;
 }
 static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot,
 		unsigned int id)
 {
 	/* Debugfs stuff is cleaned up by mmc core */
 	set_bit(ATMCI_SHUTDOWN, &slot->flags);
 	smp_wmb();
 	mmc_remove_host(slot->mmc);
 	if (gpio_is_valid(slot->detect_pin)) {
 		int pin = slot->detect_pin;
 		free_irq(gpio_to_irq(pin), slot);
 		del_timer_sync(&slot->detect_timer);
 		gpio_free(pin);
 	}
 	if (gpio_is_valid(slot->wp_pin))
 		gpio_free(slot->wp_pin);
 	slot->host->slot[id] = NULL;
 	mmc_free_host(slot->mmc);
 }
 static bool atmci_filter(struct dma_chan *chan, void *slave)
 {
 	struct mci_dma_data	*sl = slave;
 	if (sl && find_slave_dev(sl) == chan->device->dev) {
 		chan->private = slave_data_ptr(sl);
 		return true;
 	} else {
 		return false;
 	}
 }
 static bool atmci_configure_dma(struct atmel_mci *host)
 {
 	struct mci_platform_data	*pdata;
 	if (host == NULL)
 		return false;
 	pdata = host->pdev->dev.platform_data;
 	if (pdata && find_slave_dev(pdata->dma_slave)) {
 		dma_cap_mask_t mask;
 		/* Try to grab a DMA channel */
 		dma_cap_zero(mask);
 		dma_cap_set(DMA_SLAVE, mask);
 		host->dma.chan =
 			dma_request_channel(mask, atmci_filter, pdata->dma_slave);
 	}
 	if (!host->dma.chan) {
 		dev_warn(&host->pdev->dev, "no DMA channel available\n");
 		return false;
 	} else {
 		dev_info(&host->pdev->dev,
 					"using %s for DMA transfers\n",
 					dma_chan_name(host->dma.chan));
 		host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
 		host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 		host->dma_conf.src_maxburst = 1;
 		host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
 		host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 		host->dma_conf.dst_maxburst = 1;
 		host->dma_conf.device_fc = false;
 		return true;
 	}
 }
 /*
  * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
  * HSMCI provides DMA support and a new config register but no more supports
  * PDC.
  */
 static void __init atmci_get_cap(struct atmel_mci *host)
 {
 	unsigned int version;
 	version = atmci_get_version(host);
 	dev_info(&host->pdev->dev,
 			"version: 0x%x\n", version);
 	host->caps.has_dma = 0;
 	host->caps.has_pdc = 1;
 	host->caps.has_cfg_reg = 0;
 	host->caps.has_cstor_reg = 0;
 	host->caps.has_highspeed = 0;
 	host->caps.has_rwproof = 0;
 	host->caps.has_odd_clk_div = 0;
 	host->caps.has_bad_data_ordering = 1;
 	host->caps.need_reset_after_xfer = 1;
 	host->caps.need_blksz_mul_4 = 1;
+	host->caps.need_notbusy_for_read_ops = 0;
 	/* keep only major version number */
 	switch (version & 0xf00) {
 	case 0x500:
 		host->caps.has_odd_clk_div = 1;
 	case 0x400:
 	case 0x300:
 #ifdef CONFIG_AT_HDMAC
 		host->caps.has_dma = 1;
 #else
 		dev_info(&host->pdev->dev,
 			"has dma capability but dma engine is not selected, then use pio\n");
 #endif
 		host->caps.has_pdc = 0;
 		host->caps.has_cfg_reg = 1;
 		host->caps.has_cstor_reg = 1;
 		host->caps.has_highspeed = 1;
 	case 0x200:
 		host->caps.has_rwproof = 1;
 		host->caps.need_blksz_mul_4 = 0;
+		host->caps.need_notbusy_for_read_ops = 1;
 	case 0x100:
 		host->caps.has_bad_data_ordering = 0;
 		host->caps.need_reset_after_xfer = 0;
 	case 0x0:
 		break;
 	default:
 		host->caps.has_pdc = 0;
 		dev_warn(&host->pdev->dev,
 				"Unmanaged mci version, set minimum capabilities\n");
 		break;
 	}
 }
 static int __init atmci_probe(struct platform_device *pdev)
 {
 	struct mci_platform_data	*pdata;
 	struct atmel_mci		*host;
 	struct resource			*regs;
 	unsigned int			nr_slots;
 	int				irq;
 	int				ret;
 	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!regs)
 		return -ENXIO;
 	pdata = pdev->dev.platform_data;
 	if (!pdata)
 		return -ENXIO;
 	irq = platform_get_irq(pdev, 0);
 	if (irq < 0)
 		return irq;
 	host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL);
 	if (!host)
 		return -ENOMEM;
 	host->pdev = pdev;
 	spin_lock_init(&host->lock);
 	INIT_LIST_HEAD(&host->queue);
 	host->mck = clk_get(&pdev->dev, "mci_clk");
 	if (IS_ERR(host->mck)) {
 		ret = PTR_ERR(host->mck);
 		goto err_clk_get;
 	}
 	ret = -ENOMEM;
 	host->regs = ioremap(regs->start, resource_size(regs));
 	if (!host->regs)
 		goto err_ioremap;
 	clk_enable(host->mck);
 	atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
 	host->bus_hz = clk_get_rate(host->mck);
 	clk_disable(host->mck);
 	host->mapbase = regs->start;
 	tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
 	ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
 	if (ret)
 		goto err_request_irq;
 	/* Get MCI capabilities and set operations according to it */
 	atmci_get_cap(host);
 	if (host->caps.has_dma && atmci_configure_dma(host)) {
 		host->prepare_data = &atmci_prepare_data_dma;
 		host->submit_data = &atmci_submit_data_dma;
 		host->stop_transfer = &atmci_stop_transfer_dma;
 	} else if (host->caps.has_pdc) {
 		dev_info(&pdev->dev, "using PDC\n");
 		host->prepare_data = &atmci_prepare_data_pdc;
 		host->submit_data = &atmci_submit_data_pdc;
 		host->stop_transfer = &atmci_stop_transfer_pdc;
 	} else {
 		dev_info(&pdev->dev, "using PIO\n");
 		host->prepare_data = &atmci_prepare_data;
 		host->submit_data = &atmci_submit_data;
 		host->stop_transfer = &atmci_stop_transfer;
 	}
 	platform_set_drvdata(pdev, host);
 	setup_timer(&host->timer, atmci_timeout_timer, (unsigned long)host);
 	/* We need at least one slot to succeed */
 	nr_slots = 0;
 	ret = -ENODEV;
 	if (pdata->slot[0].bus_width) {
 		ret = atmci_init_slot(host, &pdata->slot[0],
 				0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
 		if (!ret) {
 			nr_slots++;
 			host->buf_size = host->slot[0]->mmc->max_req_size;
 		}
 	}
 	if (pdata->slot[1].bus_width) {
 		ret = atmci_init_slot(host, &pdata->slot[1],
 				1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
 		if (!ret) {
 			nr_slots++;
 			if (host->slot[1]->mmc->max_req_size > host->buf_size)
 				host->buf_size =
 					host->slot[1]->mmc->max_req_size;
 		}
 	}
 	if (!nr_slots) {
 		dev_err(&pdev->dev, "init failed: no slot defined\n");
 		goto err_init_slot;
 	}
 	if (!host->caps.has_rwproof) {
 		host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size,
 		                                  &host->buf_phys_addr,
 						  GFP_KERNEL);
 		if (!host->buffer) {
 			ret = -ENOMEM;
 			dev_err(&pdev->dev, "buffer allocation failed\n");
 			goto err_init_slot;
 		}
 	}
 	dev_info(&pdev->dev,
 			"Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
 			host->mapbase, irq, nr_slots);
 	return 0;
 err_init_slot:
 	if (host->dma.chan)
 		dma_release_channel(host->dma.chan);
 	free_irq(irq, host);
 err_request_irq:
 	iounmap(host->regs);
 err_ioremap:
 	clk_put(host->mck);
 err_clk_get:
 	kfree(host);
 	return ret;
 }
 static int __exit atmci_remove(struct platform_device *pdev)
 {
 	struct atmel_mci	*host = platform_get_drvdata(pdev);
 	unsigned int		i;
 	platform_set_drvdata(pdev, NULL);
 	if (host->buffer)
 		dma_free_coherent(&pdev->dev, host->buf_size,
 		                  host->buffer, host->buf_phys_addr);
 	for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
 		if (host->slot[i])
 			atmci_cleanup_slot(host->slot[i], i);
 	}
 	clk_enable(host->mck);
 	atmci_writel(host, ATMCI_IDR, ~0UL);
 	atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
 	atmci_readl(host, ATMCI_SR);
 	clk_disable(host->mck);
 #ifdef CONFIG_MMC_ATMELMCI_DMA
 	if (host->dma.chan)
 		dma_release_channel(host->dma.chan);
 #endif
 	free_irq(platform_get_irq(pdev, 0), host);
 	iounmap(host->regs);
 	clk_put(host->mck);
 	kfree(host);
 	return 0;
 }
 #ifdef CONFIG_PM
 static int atmci_suspend(struct device *dev)
 {
 	struct atmel_mci *host = dev_get_drvdata(dev);
 	int i;
 	 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
 		struct atmel_mci_slot *slot = host->slot[i];
 		int ret;
 		if (!slot)
 			continue;
 		ret = mmc_suspend_host(slot->mmc);
 		if (ret < 0) {
 			while (--i >= 0) {
 				slot = host->slot[i];
 				if (slot
 				&& test_bit(ATMCI_SUSPENDED, &slot->flags)) {
 					mmc_resume_host(host->slot[i]->mmc);
 					clear_bit(ATMCI_SUSPENDED, &slot->flags);
 				}
 			}
 			return ret;
 		} else {
 			set_bit(ATMCI_SUSPENDED, &slot->flags);
 		}
 	}
 	return 0;
 }
 static int atmci_resume(struct device *dev)
 {
 	struct atmel_mci *host = dev_get_drvdata(dev);
 	int i;
 	int ret = 0;
 	for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
 		struct atmel_mci_slot *slot = host->slot[i];
 		int err;
 		slot = host->slot[i];
 		if (!slot)
 			continue;
 		if (!test_bit(ATMCI_SUSPENDED, &slot->flags))
 			continue;
 		err = mmc_resume_host(slot->mmc);
 		if (err < 0)
 			ret = err;
 		else
 			clear_bit(ATMCI_SUSPENDED, &slot->flags);
 	}
 	return ret;
 }
 static SIMPLE_DEV_PM_OPS(atmci_pm, atmci_suspend, atmci_resume);
 #define ATMCI_PM_OPS	(&atmci_pm)
 #else
 #define ATMCI_PM_OPS	NULL
 #endif
 static struct platform_driver atmci_driver = {
 	.remove		= __exit_p(atmci_remove),
 	.driver		= {
 		.name		= "atmel_mci",
 		.pm		= ATMCI_PM_OPS,
 	},
 };
 static int __init atmci_init(void)
 {
 	return platform_driver_probe(&atmci_driver, atmci_probe);
 }
 static void __exit atmci_exit(void)
 {
 	platform_driver_unregister(&atmci_driver);
 }
 late_initcall(atmci_init); /* try to load after dma driver when built-in */
 module_exit(atmci_exit);
 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
 MODULE_LICENSE("GPL v2");

drivers/mmc/host/bfin_sdh.c

Diff comments View file @ 0809095

 /*
  * bfin_sdh.c - Analog Devices Blackfin SDH Controller
  *
  * Copyright (C) 2007-2009 Analog Device Inc.
  *
  * Licensed under the GPL-2 or later.
  */
 #define DRIVER_NAME	"bfin-sdh"
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/ioport.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/interrupt.h>
 #include <linux/dma-mapping.h>
 #include <linux/mmc/host.h>
 #include <linux/proc_fs.h>
 #include <linux/gfp.h>
 #include <asm/cacheflush.h>
 #include <asm/dma.h>
 #include <asm/portmux.h>
 #include <asm/bfin_sdh.h>
 #if defined(CONFIG_BF51x)
 #define bfin_read_SDH_PWR_CTL		bfin_read_RSI_PWR_CTL
 #define bfin_write_SDH_PWR_CTL		bfin_write_RSI_PWR_CTL
 #define bfin_read_SDH_CLK_CTL		bfin_read_RSI_CLK_CTL
 #define bfin_write_SDH_CLK_CTL		bfin_write_RSI_CLK_CTL
 #define bfin_write_SDH_ARGUMENT		bfin_write_RSI_ARGUMENT
 #define bfin_write_SDH_COMMAND		bfin_write_RSI_COMMAND
 #define bfin_write_SDH_DATA_TIMER	bfin_write_RSI_DATA_TIMER
 #define bfin_read_SDH_RESPONSE0		bfin_read_RSI_RESPONSE0
 #define bfin_read_SDH_RESPONSE1		bfin_read_RSI_RESPONSE1
 #define bfin_read_SDH_RESPONSE2		bfin_read_RSI_RESPONSE2
 #define bfin_read_SDH_RESPONSE3		bfin_read_RSI_RESPONSE3
 #define bfin_write_SDH_DATA_LGTH	bfin_write_RSI_DATA_LGTH
 #define bfin_read_SDH_DATA_CTL		bfin_read_RSI_DATA_CTL
 #define bfin_write_SDH_DATA_CTL		bfin_write_RSI_DATA_CTL
 #define bfin_read_SDH_DATA_CNT		bfin_read_RSI_DATA_CNT
 #define bfin_write_SDH_STATUS_CLR	bfin_write_RSI_STATUS_CLR
 #define bfin_read_SDH_E_STATUS		bfin_read_RSI_E_STATUS
 #define bfin_write_SDH_E_STATUS		bfin_write_RSI_E_STATUS
 #define bfin_read_SDH_STATUS		bfin_read_RSI_STATUS
 #define bfin_write_SDH_MASK0		bfin_write_RSI_MASK0
 #define bfin_read_SDH_CFG		bfin_read_RSI_CFG
 #define bfin_write_SDH_CFG		bfin_write_RSI_CFG
 #endif
-struct dma_desc_array {
-	unsigned long	start_addr;
-	unsigned short	cfg;
-	unsigned short	x_count;
-	short		x_modify;
-} __packed;
 struct sdh_host {
 	struct mmc_host		*mmc;
 	spinlock_t		lock;
 	struct resource		*res;
 	void __iomem		*base;
 	int			irq;
 	int			stat_irq;
 	int			dma_ch;
 	int			dma_dir;
 	struct dma_desc_array	*sg_cpu;
 	dma_addr_t		sg_dma;
 	int			dma_len;
 	unsigned int		imask;
 	unsigned int		power_mode;
 	unsigned int		clk_div;
 	struct mmc_request	*mrq;
 	struct mmc_command	*cmd;
 	struct mmc_data		*data;
 };
 static struct bfin_sd_host *get_sdh_data(struct platform_device *pdev)
 {
 	return pdev->dev.platform_data;
 }
 static void sdh_stop_clock(struct sdh_host *host)
 {
 	bfin_write_SDH_CLK_CTL(bfin_read_SDH_CLK_CTL() & ~CLK_E);
 	SSYNC();
 }
 static void sdh_enable_stat_irq(struct sdh_host *host, unsigned int mask)
 {
 	unsigned long flags;
 	spin_lock_irqsave(&host->lock, flags);
 	host->imask |= mask;
 	bfin_write_SDH_MASK0(mask);
 	SSYNC();
 	spin_unlock_irqrestore(&host->lock, flags);
 }
 static void sdh_disable_stat_irq(struct sdh_host *host, unsigned int mask)
 {
 	unsigned long flags;
 	spin_lock_irqsave(&host->lock, flags);
 	host->imask &= ~mask;
 	bfin_write_SDH_MASK0(host->imask);
 	SSYNC();
 	spin_unlock_irqrestore(&host->lock, flags);
 }
 static int sdh_setup_data(struct sdh_host *host, struct mmc_data *data)
 {
 	unsigned int length;
 	unsigned int data_ctl;
 	unsigned int dma_cfg;
 	unsigned int cycle_ns, timeout;
 	dev_dbg(mmc_dev(host->mmc), "%s enter flags: 0x%x\n", __func__, data->flags);
 	host->data = data;
 	data_ctl = 0;
 	dma_cfg = 0;
 	length = data->blksz * data->blocks;
 	bfin_write_SDH_DATA_LGTH(length);
 	if (data->flags & MMC_DATA_STREAM)
 		data_ctl |= DTX_MODE;
 	if (data->flags & MMC_DATA_READ)
 		data_ctl |= DTX_DIR;
 	/* Only supports power-of-2 block size */
 	if (data->blksz & (data->blksz - 1))
 		return -EINVAL;
 	data_ctl |= ((ffs(data->blksz) - 1) << 4);
 	bfin_write_SDH_DATA_CTL(data_ctl);
 	/* the time of a host clock period in ns */
 	cycle_ns = 1000000000 / (get_sclk() / (2 * (host->clk_div + 1)));
 	timeout = data->timeout_ns / cycle_ns;
 	timeout += data->timeout_clks;
 	bfin_write_SDH_DATA_TIMER(timeout);
 	SSYNC();
 	if (data->flags & MMC_DATA_READ) {
 		host->dma_dir = DMA_FROM_DEVICE;
 		dma_cfg |= WNR;
 	} else
 		host->dma_dir = DMA_TO_DEVICE;
 	sdh_enable_stat_irq(host, (DAT_CRC_FAIL | DAT_TIME_OUT | DAT_END));
 	host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma_dir);
 #if defined(CONFIG_BF54x)
 	dma_cfg |= DMAFLOW_ARRAY | NDSIZE_5 | RESTART | WDSIZE_32 | DMAEN;
 	{
 		struct scatterlist *sg;
 		int i;
 		for_each_sg(data->sg, sg, host->dma_len, i) {
 			host->sg_cpu[i].start_addr = sg_dma_address(sg);
 			host->sg_cpu[i].cfg = dma_cfg;
 			host->sg_cpu[i].x_count = sg_dma_len(sg) / 4;
 			host->sg_cpu[i].x_modify = 4;
 			dev_dbg(mmc_dev(host->mmc), "%d: start_addr:0x%lx, "
 				"cfg:0x%x, x_count:0x%x, x_modify:0x%x\n",
 				i, host->sg_cpu[i].start_addr,
 				host->sg_cpu[i].cfg, host->sg_cpu[i].x_count,
 				host->sg_cpu[i].x_modify);
 		}
 	}
 	flush_dcache_range((unsigned int)host->sg_cpu,
 		(unsigned int)host->sg_cpu +
 			host->dma_len * sizeof(struct dma_desc_array));
 	/* Set the last descriptor to stop mode */
 	host->sg_cpu[host->dma_len - 1].cfg &= ~(DMAFLOW | NDSIZE);
 	host->sg_cpu[host->dma_len - 1].cfg |= DI_EN;
 	set_dma_curr_desc_addr(host->dma_ch, (unsigned long *)host->sg_dma);
 	set_dma_x_count(host->dma_ch, 0);
 	set_dma_x_modify(host->dma_ch, 0);
 	set_dma_config(host->dma_ch, dma_cfg);
 #elif defined(CONFIG_BF51x)
 	/* RSI DMA doesn't work in array mode */
 	dma_cfg |= WDSIZE_32 | DMAEN;
 	set_dma_start_addr(host->dma_ch, sg_dma_address(&data->sg[0]));
 	set_dma_x_count(host->dma_ch, length / 4);
 	set_dma_x_modify(host->dma_ch, 4);
 	set_dma_config(host->dma_ch, dma_cfg);
 #endif
 	bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
 	SSYNC();
 	dev_dbg(mmc_dev(host->mmc), "%s exit\n", __func__);
 	return 0;
 }
 static void sdh_start_cmd(struct sdh_host *host, struct mmc_command *cmd)
 {
 	unsigned int sdh_cmd;
 	unsigned int stat_mask;
 	dev_dbg(mmc_dev(host->mmc), "%s enter cmd: 0x%p\n", __func__, cmd);
 	WARN_ON(host->cmd != NULL);
 	host->cmd = cmd;
 	sdh_cmd = 0;
 	stat_mask = 0;
 	sdh_cmd |= cmd->opcode;
 	if (cmd->flags & MMC_RSP_PRESENT) {
 		sdh_cmd |= CMD_RSP;
 		stat_mask |= CMD_RESP_END;
 	} else {
 		stat_mask |= CMD_SENT;
 	}
 	if (cmd->flags & MMC_RSP_136)
 		sdh_cmd |= CMD_L_RSP;
 	stat_mask |= CMD_CRC_FAIL | CMD_TIME_OUT;
 	sdh_enable_stat_irq(host, stat_mask);
 	bfin_write_SDH_ARGUMENT(cmd->arg);
 	bfin_write_SDH_COMMAND(sdh_cmd | CMD_E);
 	bfin_write_SDH_CLK_CTL(bfin_read_SDH_CLK_CTL() | CLK_E);
 	SSYNC();
 }
 static void sdh_finish_request(struct sdh_host *host, struct mmc_request *mrq)
 {
 	dev_dbg(mmc_dev(host->mmc), "%s enter\n", __func__);
 	host->mrq = NULL;
 	host->cmd = NULL;
 	host->data = NULL;
 	mmc_request_done(host->mmc, mrq);
 }
 static int sdh_cmd_done(struct sdh_host *host, unsigned int stat)
 {
 	struct mmc_command *cmd = host->cmd;
 	int ret = 0;
 	dev_dbg(mmc_dev(host->mmc), "%s enter cmd: %p\n", __func__, cmd);
 	if (!cmd)
 		return 0;
 	host->cmd = NULL;
 	if (cmd->flags & MMC_RSP_PRESENT) {
 		cmd->resp[0] = bfin_read_SDH_RESPONSE0();
 		if (cmd->flags & MMC_RSP_136) {
 			cmd->resp[1] = bfin_read_SDH_RESPONSE1();
 			cmd->resp[2] = bfin_read_SDH_RESPONSE2();
 			cmd->resp[3] = bfin_read_SDH_RESPONSE3();
 		}
 	}
 	if (stat & CMD_TIME_OUT)
 		cmd->error = -ETIMEDOUT;
 	else if (stat & CMD_CRC_FAIL && cmd->flags & MMC_RSP_CRC)
 		cmd->error = -EILSEQ;
 	sdh_disable_stat_irq(host, (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT | CMD_CRC_FAIL));
 	if (host->data && !cmd->error) {
 		if (host->data->flags & MMC_DATA_WRITE) {
 			ret = sdh_setup_data(host, host->data);
 			if (ret)
 				return 0;
 		}
 		sdh_enable_stat_irq(host, DAT_END | RX_OVERRUN | TX_UNDERRUN | DAT_TIME_OUT);
 	} else
 		sdh_finish_request(host, host->mrq);
 	return 1;
 }
 static int sdh_data_done(struct sdh_host *host, unsigned int stat)
 {
 	struct mmc_data *data = host->data;
 	dev_dbg(mmc_dev(host->mmc), "%s enter stat: 0x%x\n", __func__, stat);
 	if (!data)
 		return 0;
 	disable_dma(host->dma_ch);
 	dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 		     host->dma_dir);
 	if (stat & DAT_TIME_OUT)
 		data->error = -ETIMEDOUT;
 	else if (stat & DAT_CRC_FAIL)
 		data->error = -EILSEQ;
 	else if (stat & (RX_OVERRUN | TX_UNDERRUN))
 		data->error = -EIO;
 	if (!data->error)
 		data->bytes_xfered = data->blocks * data->blksz;
 	else
 		data->bytes_xfered = 0;
 	sdh_disable_stat_irq(host, DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN | TX_UNDERRUN);
 	bfin_write_SDH_STATUS_CLR(DAT_END_STAT | DAT_TIMEOUT_STAT | \
 			DAT_CRC_FAIL_STAT | DAT_BLK_END_STAT | RX_OVERRUN | TX_UNDERRUN);
 	bfin_write_SDH_DATA_CTL(0);
 	SSYNC();
 	host->data = NULL;
 	if (host->mrq->stop) {
 		sdh_stop_clock(host);
 		sdh_start_cmd(host, host->mrq->stop);
 	} else {
 		sdh_finish_request(host, host->mrq);
 	}
 	return 1;
 }
 static void sdh_request(struct mmc_host *mmc, struct mmc_request *mrq)
 {
 	struct sdh_host *host = mmc_priv(mmc);
 	int ret = 0;
 	dev_dbg(mmc_dev(host->mmc), "%s enter, mrp:%p, cmd:%p\n", __func__, mrq, mrq->cmd);
 	WARN_ON(host->mrq != NULL);
 	host->mrq = mrq;
 	host->data = mrq->data;
 	if (mrq->data && mrq->data->flags & MMC_DATA_READ) {
 		ret = sdh_setup_data(host, mrq->data);
 		if (ret)
 			return;
 	}
 	sdh_start_cmd(host, mrq->cmd);
 }
 static void sdh_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 {
 	struct sdh_host *host;
 	unsigned long flags;
 	u16 clk_ctl = 0;
 	u16 pwr_ctl = 0;
 	u16 cfg;
 	host = mmc_priv(mmc);
 	spin_lock_irqsave(&host->lock, flags);
 	if (ios->clock) {
 		unsigned long  sys_clk, ios_clk;
 		unsigned char clk_div;
 		ios_clk = 2 * ios->clock;
 		sys_clk = get_sclk();
 		clk_div = sys_clk / ios_clk;
 		if (sys_clk % ios_clk == 0)
 			clk_div -= 1;
 		clk_div = min_t(unsigned char, clk_div, 0xFF);
 		clk_ctl |= clk_div;
 		clk_ctl |= CLK_E;
 		host->clk_div = clk_div;
 	} else
 		sdh_stop_clock(host);
 	if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 #ifdef CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND
 		pwr_ctl |= ROD_CTL;
 #else
 		pwr_ctl |= SD_CMD_OD | ROD_CTL;
 #endif
 	if (ios->bus_width == MMC_BUS_WIDTH_4) {
 		cfg = bfin_read_SDH_CFG();
 		cfg &= ~PD_SDDAT3;
 		cfg |= PUP_SDDAT3;
 		/* Enable 4 bit SDIO */
 		cfg |= (SD4E | MWE);
 		bfin_write_SDH_CFG(cfg);
 		clk_ctl |= WIDE_BUS;
 	} else {
 		cfg = bfin_read_SDH_CFG();
 		cfg |= MWE;
 		bfin_write_SDH_CFG(cfg);
 	}
 	bfin_write_SDH_CLK_CTL(clk_ctl);
 	host->power_mode = ios->power_mode;
 	if (ios->power_mode == MMC_POWER_ON)
 		pwr_ctl |= PWR_ON;
 	bfin_write_SDH_PWR_CTL(pwr_ctl);
 	SSYNC();
 	spin_unlock_irqrestore(&host->lock, flags);
 	dev_dbg(mmc_dev(host->mmc), "SDH: clk_div = 0x%x actual clock:%ld expected clock:%d\n",
 		host->clk_div,
 		host->clk_div ? get_sclk() / (2 * (host->clk_div + 1)) : 0,
 		ios->clock);
 }
 static const struct mmc_host_ops sdh_ops = {
 	.request	= sdh_request,
 	.set_ios	= sdh_set_ios,
 };
 static irqreturn_t sdh_dma_irq(int irq, void *devid)
 {
 	struct sdh_host *host = devid;
 	dev_dbg(mmc_dev(host->mmc), "%s enter, irq_stat: 0x%04x\n", __func__,
 		get_dma_curr_irqstat(host->dma_ch));
 	clear_dma_irqstat(host->dma_ch);
 	SSYNC();
 	return IRQ_HANDLED;
 }
 static irqreturn_t sdh_stat_irq(int irq, void *devid)
 {
 	struct sdh_host *host = devid;
 	unsigned int status;
 	int handled = 0;
 	dev_dbg(mmc_dev(host->mmc), "%s enter\n", __func__);
 	status = bfin_read_SDH_E_STATUS();
 	if (status & SD_CARD_DET) {
 		mmc_detect_change(host->mmc, 0);
 		bfin_write_SDH_E_STATUS(SD_CARD_DET);
 	}
 	status = bfin_read_SDH_STATUS();
 	if (status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT | CMD_CRC_FAIL)) {
 		handled |= sdh_cmd_done(host, status);
 		bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT | \
 				CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);
 		SSYNC();
 	}
 	status = bfin_read_SDH_STATUS();
 	if (status & (DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN | TX_UNDERRUN))
 		handled |= sdh_data_done(host, status);
 	dev_dbg(mmc_dev(host->mmc), "%s exit\n\n", __func__);
 	return IRQ_RETVAL(handled);
 }
 static int __devinit sdh_probe(struct platform_device *pdev)
 {
 	struct mmc_host *mmc;
 	struct sdh_host *host;
 	struct bfin_sd_host *drv_data = get_sdh_data(pdev);
 	int ret;
 	if (!drv_data) {
 		dev_err(&pdev->dev, "missing platform driver data\n");
 		ret = -EINVAL;
 		goto out;
 	}
 	mmc = mmc_alloc_host(sizeof(struct sdh_host), &pdev->dev);
 	if (!mmc) {
 		ret = -ENOMEM;
 		goto out;
 	}
 	mmc->ops = &sdh_ops;
 	mmc->max_segs = 32;
 	mmc->max_seg_size = 1 << 16;
 	mmc->max_blk_size = 1 << 11;
 	mmc->max_blk_count = 1 << 11;
 	mmc->max_req_size = PAGE_SIZE;
 	mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
 	mmc->f_max = get_sclk();
 	mmc->f_min = mmc->f_max >> 9;
 	mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_NEEDS_POLL;
 	host = mmc_priv(mmc);
 	host->mmc = mmc;
 	spin_lock_init(&host->lock);
 	host->irq = drv_data->irq_int0;
 	host->dma_ch = drv_data->dma_chan;
 	ret = request_dma(host->dma_ch, DRIVER_NAME "DMA");
 	if (ret) {
 		dev_err(&pdev->dev, "unable to request DMA channel\n");
 		goto out1;
 	}
 	ret = set_dma_callback(host->dma_ch, sdh_dma_irq, host);
 	if (ret) {
 		dev_err(&pdev->dev, "unable to request DMA irq\n");
 		goto out2;
 	}
 	host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
 	if (host->sg_cpu == NULL) {
 		ret = -ENOMEM;
 		goto out2;
 	}
 	platform_set_drvdata(pdev, mmc);
 	mmc_add_host(mmc);
 	ret = request_irq(host->irq, sdh_stat_irq, 0, "SDH Status IRQ", host);
 	if (ret) {
 		dev_err(&pdev->dev, "unable to request status irq\n");
 		goto out3;
 	}
 	ret = peripheral_request_list(drv_data->pin_req, DRIVER_NAME);
 	if (ret) {
 		dev_err(&pdev->dev, "unable to request peripheral pins\n");
 		goto out4;
 	}
 #if defined(CONFIG_BF54x)
 	/* Secure Digital Host shares DMA with Nand controller */
 	bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
 #endif
 	bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
 	SSYNC();
 	/* Disable card inserting detection pin. set MMC_CAP_NEES_POLL, and
 	 * mmc stack will do the detection.
 	 */
 	bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | (PUP_SDDAT | PUP_SDDAT3));
 	SSYNC();
 	return 0;
 out4:
 	free_irq(host->irq, host);
 out3:
 	mmc_remove_host(mmc);
 	dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
 out2:
 	free_dma(host->dma_ch);
 out1:
 	mmc_free_host(mmc);
  out:
 	return ret;
 }
 static int __devexit sdh_remove(struct platform_device *pdev)
 {
 	struct mmc_host *mmc = platform_get_drvdata(pdev);
 	platform_set_drvdata(pdev, NULL);
 	if (mmc) {
 		struct sdh_host *host = mmc_priv(mmc);
 		mmc_remove_host(mmc);
 		sdh_stop_clock(host);
 		free_irq(host->irq, host);
 		free_dma(host->dma_ch);
 		dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
 		mmc_free_host(mmc);
 	}
 	return 0;
 }
 #ifdef CONFIG_PM
 static int sdh_suspend(struct platform_device *dev, pm_message_t state)
 {
 	struct mmc_host *mmc = platform_get_drvdata(dev);
 	struct bfin_sd_host *drv_data = get_sdh_data(dev);
 	int ret = 0;
 	if (mmc)
 		ret = mmc_suspend_host(mmc);
 	bfin_write_SDH_PWR_CTL(bfin_read_SDH_PWR_CTL() & ~PWR_ON);
 	peripheral_free_list(drv_data->pin_req);
 	return ret;
 }
 static int sdh_resume(struct platform_device *dev)
 {
 	struct mmc_host *mmc = platform_get_drvdata(dev);
 	struct bfin_sd_host *drv_data = get_sdh_data(dev);
 	int ret = 0;
 	ret = peripheral_request_list(drv_data->pin_req, DRIVER_NAME);
 	if (ret) {
 		dev_err(&dev->dev, "unable to request peripheral pins\n");
 		return ret;
 	}
 	bfin_write_SDH_PWR_CTL(bfin_read_SDH_PWR_CTL() | PWR_ON);
 #if defined(CONFIG_BF54x)
 	/* Secure Digital Host shares DMA with Nand controller */
 	bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
 #endif
 	bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
 	SSYNC();
 	bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | (PUP_SDDAT | PUP_SDDAT3));
 	SSYNC();
 	if (mmc)
 		ret = mmc_resume_host(mmc);
 	return ret;
 }
 #else
 # define sdh_suspend NULL
 # define sdh_resume  NULL
 #endif
 static struct platform_driver sdh_driver = {
 	.probe   = sdh_probe,
 	.remove  = __devexit_p(sdh_remove),
 	.suspend = sdh_suspend,
 	.resume  = sdh_resume,
 	.driver  = {
 		.name = DRIVER_NAME,
 	},
 };
 module_platform_driver(sdh_driver);
 MODULE_DESCRIPTION("Blackfin Secure Digital Host Driver");
 MODULE_AUTHOR("Cliff Cai, Roy Huang");
 MODULE_LICENSE("GPL");

drivers/mmc/host/dw_mmc.c

Diff comments View file @ 0809095

 /*
  * Synopsys DesignWare Multimedia Card Interface driver
  *  (Based on NXP driver for lpc 31xx)
  *
  * Copyright (C) 2009 NXP Semiconductors
  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  */
 #include <linux/blkdev.h>
 #include <linux/clk.h>
 #include <linux/debugfs.h>
 #include <linux/device.h>
 #include <linux/dma-mapping.h>
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/seq_file.h>
 #include <linux/slab.h>
 #include <linux/stat.h>
 #include <linux/delay.h>
 #include <linux/irq.h>
 #include <linux/mmc/host.h>
 #include <linux/mmc/mmc.h>
 #include <linux/mmc/dw_mmc.h>
 #include <linux/bitops.h>
 #include <linux/regulator/consumer.h>
 #include <linux/workqueue.h>
 #include "dw_mmc.h"
 /* Common flag combinations */
 #define DW_MCI_DATA_ERROR_FLAGS	(SDMMC_INT_DTO | SDMMC_INT_DCRC | \
 				 SDMMC_INT_HTO | SDMMC_INT_SBE  | \
 				 SDMMC_INT_EBE)
 #define DW_MCI_CMD_ERROR_FLAGS	(SDMMC_INT_RTO | SDMMC_INT_RCRC | \
 				 SDMMC_INT_RESP_ERR)
 #define DW_MCI_ERROR_FLAGS	(DW_MCI_DATA_ERROR_FLAGS | \
 				 DW_MCI_CMD_ERROR_FLAGS  | SDMMC_INT_HLE)
 #define DW_MCI_SEND_STATUS	1
 #define DW_MCI_RECV_STATUS	2
 #define DW_MCI_DMA_THRESHOLD	16
 #ifdef CONFIG_MMC_DW_IDMAC
 struct idmac_desc {
 	u32		des0;	/* Control Descriptor */
 #define IDMAC_DES0_DIC	BIT(1)
 #define IDMAC_DES0_LD	BIT(2)
 #define IDMAC_DES0_FD	BIT(3)
 #define IDMAC_DES0_CH	BIT(4)
 #define IDMAC_DES0_ER	BIT(5)
 #define IDMAC_DES0_CES	BIT(30)
 #define IDMAC_DES0_OWN	BIT(31)
 	u32		des1;	/* Buffer sizes */
 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
 	((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
 	u32		des2;	/* buffer 1 physical address */
 	u32		des3;	/* buffer 2 physical address */
 };
 #endif /* CONFIG_MMC_DW_IDMAC */
 /**
  * struct dw_mci_slot - MMC slot state
  * @mmc: The mmc_host representing this slot.
  * @host: The MMC controller this slot is using.
  * @ctype: Card type for this slot.
  * @mrq: mmc_request currently being processed or waiting to be
  *	processed, or NULL when the slot is idle.
  * @queue_node: List node for placing this node in the @queue list of
  *	&struct dw_mci.
  * @clock: Clock rate configured by set_ios(). Protected by host->lock.
  * @flags: Random state bits associated with the slot.
  * @id: Number of this slot.
  * @last_detect_state: Most recently observed card detect state.
  */
 struct dw_mci_slot {
 	struct mmc_host		*mmc;
 	struct dw_mci		*host;
 	u32			ctype;
 	struct mmc_request	*mrq;
 	struct list_head	queue_node;
 	unsigned int		clock;
 	unsigned long		flags;
 #define DW_MMC_CARD_PRESENT	0
 #define DW_MMC_CARD_NEED_INIT	1
 	int			id;
 	int			last_detect_state;
 };
 #if defined(CONFIG_DEBUG_FS)
 static int dw_mci_req_show(struct seq_file *s, void *v)
 {
 	struct dw_mci_slot *slot = s->private;
 	struct mmc_request *mrq;
 	struct mmc_command *cmd;
 	struct mmc_command *stop;
 	struct mmc_data	*data;
 	/* Make sure we get a consistent snapshot */
 	spin_lock_bh(&slot->host->lock);
 	mrq = slot->mrq;
 	if (mrq) {
 		cmd = mrq->cmd;
 		data = mrq->data;
 		stop = mrq->stop;
 		if (cmd)
 			seq_printf(s,
 				   "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 				   cmd->opcode, cmd->arg, cmd->flags,
 				   cmd->resp[0], cmd->resp[1], cmd->resp[2],
 				   cmd->resp[2], cmd->error);
 		if (data)
 			seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 				   data->bytes_xfered, data->blocks,
 				   data->blksz, data->flags, data->error);
 		if (stop)
 			seq_printf(s,
 				   "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 				   stop->opcode, stop->arg, stop->flags,
 				   stop->resp[0], stop->resp[1], stop->resp[2],
 				   stop->resp[2], stop->error);
 	}
 	spin_unlock_bh(&slot->host->lock);
 	return 0;
 }
 static int dw_mci_req_open(struct inode *inode, struct file *file)
 {
 	return single_open(file, dw_mci_req_show, inode->i_private);
 }
 static const struct file_operations dw_mci_req_fops = {
 	.owner		= THIS_MODULE,
 	.open		= dw_mci_req_open,
 	.read		= seq_read,
 	.llseek		= seq_lseek,
 	.release	= single_release,
 };
 static int dw_mci_regs_show(struct seq_file *s, void *v)
 {
 	seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
 	seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
 	seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
 	seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
 	seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
 	seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
 	return 0;
 }
 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 {
 	return single_open(file, dw_mci_regs_show, inode->i_private);
 }
 static const struct file_operations dw_mci_regs_fops = {
 	.owner		= THIS_MODULE,
 	.open		= dw_mci_regs_open,
 	.read		= seq_read,
 	.llseek		= seq_lseek,
 	.release	= single_release,
 };
 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 {
 	struct mmc_host	*mmc = slot->mmc;
 	struct dw_mci *host = slot->host;
 	struct dentry *root;
 	struct dentry *node;
 	root = mmc->debugfs_root;
 	if (!root)
 		return;
 	node = debugfs_create_file("regs", S_IRUSR, root, host,
 				   &dw_mci_regs_fops);
 	if (!node)
 		goto err;
 	node = debugfs_create_file("req", S_IRUSR, root, slot,
 				   &dw_mci_req_fops);
 	if (!node)
 		goto err;
 	node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 	if (!node)
 		goto err;
 	node = debugfs_create_x32("pending_events", S_IRUSR, root,
 				  (u32 *)&host->pending_events);
 	if (!node)
 		goto err;
 	node = debugfs_create_x32("completed_events", S_IRUSR, root,
 				  (u32 *)&host->completed_events);
 	if (!node)
 		goto err;
 	return;
 err:
 	dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 }
 #endif /* defined(CONFIG_DEBUG_FS) */
 static void dw_mci_set_timeout(struct dw_mci *host)
 {
 	/* timeout (maximum) */
 	mci_writel(host, TMOUT, 0xffffffff);
 }
 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 {
 	struct mmc_data	*data;
 	u32 cmdr;
 	cmd->error = -EINPROGRESS;
 	cmdr = cmd->opcode;
 	if (cmdr == MMC_STOP_TRANSMISSION)
 		cmdr |= SDMMC_CMD_STOP;
 	else
 		cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 	if (cmd->flags & MMC_RSP_PRESENT) {
 		/* We expect a response, so set this bit */
 		cmdr |= SDMMC_CMD_RESP_EXP;
 		if (cmd->flags & MMC_RSP_136)
 			cmdr |= SDMMC_CMD_RESP_LONG;
 	}
 	if (cmd->flags & MMC_RSP_CRC)
 		cmdr |= SDMMC_CMD_RESP_CRC;
 	data = cmd->data;
 	if (data) {
 		cmdr |= SDMMC_CMD_DAT_EXP;
 		if (data->flags & MMC_DATA_STREAM)
 			cmdr |= SDMMC_CMD_STRM_MODE;
 		if (data->flags & MMC_DATA_WRITE)
 			cmdr |= SDMMC_CMD_DAT_WR;
 	}
 	return cmdr;
 }
 static void dw_mci_start_command(struct dw_mci *host,
 				 struct mmc_command *cmd, u32 cmd_flags)
 {
 	host->cmd = cmd;
 	dev_vdbg(&host->dev,
 		 "start command: ARGR=0x%08x CMDR=0x%08x\n",
 		 cmd->arg, cmd_flags);
 	mci_writel(host, CMDARG, cmd->arg);
 	wmb();
 	mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 }
 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
 {
 	dw_mci_start_command(host, data->stop, host->stop_cmdr);
 }
 /* DMA interface functions */
 static void dw_mci_stop_dma(struct dw_mci *host)
 {
 	if (host->using_dma) {
 		host->dma_ops->stop(host);
 		host->dma_ops->cleanup(host);
 	} else {
 		/* Data transfer was stopped by the interrupt handler */
 		set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 	}
 }
 static int dw_mci_get_dma_dir(struct mmc_data *data)
 {
 	if (data->flags & MMC_DATA_WRITE)
 		return DMA_TO_DEVICE;
 	else
 		return DMA_FROM_DEVICE;
 }
 #ifdef CONFIG_MMC_DW_IDMAC
 static void dw_mci_dma_cleanup(struct dw_mci *host)
 {
 	struct mmc_data *data = host->data;
 	if (data)
 		if (!data->host_cookie)
 			dma_unmap_sg(&host->dev,
 				     data->sg,
 				     data->sg_len,
 				     dw_mci_get_dma_dir(data));
 }
 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 {
 	u32 temp;
 	/* Disable and reset the IDMAC interface */
 	temp = mci_readl(host, CTRL);
 	temp &= ~SDMMC_CTRL_USE_IDMAC;
 	temp |= SDMMC_CTRL_DMA_RESET;
 	mci_writel(host, CTRL, temp);
 	/* Stop the IDMAC running */
 	temp = mci_readl(host, BMOD);
 	temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 	mci_writel(host, BMOD, temp);
 }
 static void dw_mci_idmac_complete_dma(struct dw_mci *host)
 {
 	struct mmc_data *data = host->data;
 	dev_vdbg(&host->dev, "DMA complete\n");
 	host->dma_ops->cleanup(host);
 	/*
 	 * If the card was removed, data will be NULL. No point in trying to
 	 * send the stop command or waiting for NBUSY in this case.
 	 */
 	if (data) {
 		set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 		tasklet_schedule(&host->tasklet);
 	}
 }
 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
 				    unsigned int sg_len)
 {
 	int i;
 	struct idmac_desc *desc = host->sg_cpu;
 	for (i = 0; i < sg_len; i++, desc++) {
 		unsigned int length = sg_dma_len(&data->sg[i]);
 		u32 mem_addr = sg_dma_address(&data->sg[i]);
 		/* Set the OWN bit and disable interrupts for this descriptor */
 		desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
 		/* Buffer length */
 		IDMAC_SET_BUFFER1_SIZE(desc, length);
 		/* Physical address to DMA to/from */
 		desc->des2 = mem_addr;
 	}
 	/* Set first descriptor */
 	desc = host->sg_cpu;
 	desc->des0 |= IDMAC_DES0_FD;
 	/* Set last descriptor */
 	desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
 	desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 	desc->des0 |= IDMAC_DES0_LD;
 	wmb();
 }
 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 {
 	u32 temp;
 	dw_mci_translate_sglist(host, host->data, sg_len);
 	/* Select IDMAC interface */
 	temp = mci_readl(host, CTRL);
 	temp |= SDMMC_CTRL_USE_IDMAC;
 	mci_writel(host, CTRL, temp);
 	wmb();
 	/* Enable the IDMAC */
 	temp = mci_readl(host, BMOD);
 	temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 	mci_writel(host, BMOD, temp);
 	/* Start it running */
 	mci_writel(host, PLDMND, 1);
 }
 static int dw_mci_idmac_init(struct dw_mci *host)
 {
 	struct idmac_desc *p;
 	int i, dma_support;
 	/* Number of descriptors in the ring buffer */
 	host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
 	/* Check if Hardware Configuration Register has support for DMA */
 	dma_support = (mci_readl(host, HCON) >> 16) & 0x3;
 	if (!dma_support || dma_support > 2) {
 		dev_err(&host->dev,
 			"Host Controller does not support IDMA Tx.\n");
 		host->dma_ops = NULL;
 		return -ENODEV;
 	}
 	dev_info(&host->dev, "Using internal DMA controller.\n");
 	/* Forward link the descriptor list */
 	for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
 		p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
 	/* Set the last descriptor as the end-of-ring descriptor */
 	p->des3 = host->sg_dma;
 	p->des0 = IDMAC_DES0_ER;
 	mci_writel(host, BMOD, SDMMC_IDMAC_SWRESET);
 	/* Mask out interrupts - get Tx & Rx complete only */
 	mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
 		   SDMMC_IDMAC_INT_TI);
 	/* Set the descriptor base address */
 	mci_writel(host, DBADDR, host->sg_dma);
 	return 0;
 }
 static struct dw_mci_dma_ops dw_mci_idmac_ops = {
 	.init = dw_mci_idmac_init,
 	.start = dw_mci_idmac_start_dma,
 	.stop = dw_mci_idmac_stop_dma,
 	.complete = dw_mci_idmac_complete_dma,
 	.cleanup = dw_mci_dma_cleanup,
 };
 #endif /* CONFIG_MMC_DW_IDMAC */
 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 				   struct mmc_data *data,
 				   bool next)
 {
 	struct scatterlist *sg;
 	unsigned int i, sg_len;
 	if (!next && data->host_cookie)
 		return data->host_cookie;
 	/*
 	 * We don't do DMA on "complex" transfers, i.e. with
 	 * non-word-aligned buffers or lengths. Also, we don't bother
 	 * with all the DMA setup overhead for short transfers.
 	 */
 	if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 		return -EINVAL;
 	if (data->blksz & 3)
 		return -EINVAL;
 	for_each_sg(data->sg, sg, data->sg_len, i) {
 		if (sg->offset & 3 || sg->length & 3)
 			return -EINVAL;
 	}
 	sg_len = dma_map_sg(&host->dev,
 			    data->sg,
 			    data->sg_len,
 			    dw_mci_get_dma_dir(data));
 	if (sg_len == 0)
 		return -EINVAL;
 	if (next)
 		data->host_cookie = sg_len;
 	return sg_len;
 }
 static void dw_mci_pre_req(struct mmc_host *mmc,
 			   struct mmc_request *mrq,
 			   bool is_first_req)
 {
 	struct dw_mci_slot *slot = mmc_priv(mmc);
 	struct mmc_data *data = mrq->data;
 	if (!slot->host->use_dma || !data)
 		return;
 	if (data->host_cookie) {
 		data->host_cookie = 0;
 		return;
 	}
 	if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
 		data->host_cookie = 0;
 }
 static void dw_mci_post_req(struct mmc_host *mmc,
 			    struct mmc_request *mrq,
 			    int err)
 {
 	struct dw_mci_slot *slot = mmc_priv(mmc);
 	struct mmc_data *data = mrq->data;
 	if (!slot->host->use_dma || !data)
 		return;
 	if (data->host_cookie)
 		dma_unmap_sg(&slot->host->dev,
 			     data->sg,
 			     data->sg_len,
 			     dw_mci_get_dma_dir(data));
 	data->host_cookie = 0;
 }
 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
 {
 	int sg_len;
 	u32 temp;
 	host->using_dma = 0;
 	/* If we don't have a channel, we can't do DMA */
 	if (!host->use_dma)
 		return -ENODEV;
 	sg_len = dw_mci_pre_dma_transfer(host, data, 0);
 	if (sg_len < 0) {
 		host->dma_ops->stop(host);
 		return sg_len;
 	}
 	host->using_dma = 1;
 	dev_vdbg(&host->dev,
 		 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
 		 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
 		 sg_len);
 	/* Enable the DMA interface */
 	temp = mci_readl(host, CTRL);
 	temp |= SDMMC_CTRL_DMA_ENABLE;
 	mci_writel(host, CTRL, temp);
 	/* Disable RX/TX IRQs, let DMA handle it */
 	temp = mci_readl(host, INTMASK);
 	temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
 	mci_writel(host, INTMASK, temp);
 	host->dma_ops->start(host, sg_len);
 	return 0;
 }
 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
 {
 	u32 temp;
 	data->error = -EINPROGRESS;
 	WARN_ON(host->data);
 	host->sg = NULL;
 	host->data = data;
 	if (data->flags & MMC_DATA_READ)
 		host->dir_status = DW_MCI_RECV_STATUS;
 	else
 		host->dir_status = DW_MCI_SEND_STATUS;
 	if (dw_mci_submit_data_dma(host, data)) {
 		int flags = SG_MITER_ATOMIC;
 		if (host->data->flags & MMC_DATA_READ)
 			flags |= SG_MITER_TO_SG;
 		else
 			flags |= SG_MITER_FROM_SG;
 		sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 		host->sg = data->sg;
 		host->part_buf_start = 0;
 		host->part_buf_count = 0;
 		mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
 		temp = mci_readl(host, INTMASK);
 		temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
 		mci_writel(host, INTMASK, temp);
 		temp = mci_readl(host, CTRL);
 		temp &= ~SDMMC_CTRL_DMA_ENABLE;
 		mci_writel(host, CTRL, temp);
 	}
 }
 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
 {
 	struct dw_mci *host = slot->host;
 	unsigned long timeout = jiffies + msecs_to_jiffies(500);
 	unsigned int cmd_status = 0;
 	mci_writel(host, CMDARG, arg);
 	wmb();
 	mci_writel(host, CMD, SDMMC_CMD_START | cmd);
 	while (time_before(jiffies, timeout)) {
 		cmd_status = mci_readl(host, CMD);
 		if (!(cmd_status & SDMMC_CMD_START))
 			return;
 	}
 	dev_err(&slot->mmc->class_dev,
 		"Timeout sending command (cmd %#x arg %#x status %#x)\n",
 		cmd, arg, cmd_status);
 }
 static void dw_mci_setup_bus(struct dw_mci_slot *slot)
 {
 	struct dw_mci *host = slot->host;
 	u32 div;
+	u32 clk_en_a;
 	if (slot->clock != host->current_speed) {
 		div = host->bus_hz / slot->clock;
 		if (host->bus_hz % slot->clock && host->bus_hz > slot->clock)
 			/*
 			 * move the + 1 after the divide to prevent
 			 * over-clocking the card.
 			 */
 			div += 1;
 		div = (host->bus_hz != slot->clock) ? DIV_ROUND_UP(div, 2) : 0;
 		dev_info(&slot->mmc->class_dev,
 			 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
 			 " div = %d)\n", slot->id, host->bus_hz, slot->clock,
 			 div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div);
 		/* disable clock */
 		mci_writel(host, CLKENA, 0);
 		mci_writel(host, CLKSRC, 0);
 		/* inform CIU */
 		mci_send_cmd(slot,
 			     SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 		/* set clock to desired speed */
 		mci_writel(host, CLKDIV, div);
 		/* inform CIU */
 		mci_send_cmd(slot,
 			     SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
-		/* enable clock */
+		/* enable clock; only low power if no SDIO */
-		mci_writel(host, CLKENA, ((SDMMC_CLKEN_ENABLE |
+		clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
-			   SDMMC_CLKEN_LOW_PWR) << slot->id));
+		if (!(mci_readl(host, INTMASK) & SDMMC_INT_SDIO(slot->id)))
+			clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
+		mci_writel(host, CLKENA, clk_en_a);
 		/* inform CIU */
 		mci_send_cmd(slot,
 			     SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 		host->current_speed = slot->clock;
 	}
 	/* Set the current slot bus width */
 	mci_writel(host, CTYPE, (slot->ctype << slot->id));
 }
 static void __dw_mci_start_request(struct dw_mci *host,
 				   struct dw_mci_slot *slot,
 				   struct mmc_command *cmd)
 {
 	struct mmc_request *mrq;
 	struct mmc_data	*data;
 	u32 cmdflags;
 	mrq = slot->mrq;
 	if (host->pdata->select_slot)
 		host->pdata->select_slot(slot->id);
 	/* Slot specific timing and width adjustment */
 	dw_mci_setup_bus(slot);
 	host->cur_slot = slot;
 	host->mrq = mrq;
 	host->pending_events = 0;
 	host->completed_events = 0;
 	host->data_status = 0;
 	data = cmd->data;
 	if (data) {
 		dw_mci_set_timeout(host);
 		mci_writel(host, BYTCNT, data->blksz*data->blocks);
 		mci_writel(host, BLKSIZ, data->blksz);
 	}
 	cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
 	/* this is the first command, send the initialization clock */
 	if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
 		cmdflags |= SDMMC_CMD_INIT;
 	if (data) {
 		dw_mci_submit_data(host, data);
 		wmb();
 	}
 	dw_mci_start_command(host, cmd, cmdflags);
 	if (mrq->stop)
 		host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
 }
 static void dw_mci_start_request(struct dw_mci *host,
 				 struct dw_mci_slot *slot)
 {
 	struct mmc_request *mrq = slot->mrq;
 	struct mmc_command *cmd;
 	cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
 	__dw_mci_start_request(host, slot, cmd);
 }
 /* must be called with host->lock held */
 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
 				 struct mmc_request *mrq)
 {
 	dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
 		 host->state);
 	slot->mrq = mrq;
 	if (host->state == STATE_IDLE) {
 		host->state = STATE_SENDING_CMD;
 		dw_mci_start_request(host, slot);
 	} else {
 		list_add_tail(&slot->queue_node, &host->queue);
 	}
 }
 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 {
 	struct dw_mci_slot *slot = mmc_priv(mmc);
 	struct dw_mci *host = slot->host;
 	WARN_ON(slot->mrq);
 	/*
 	 * The check for card presence and queueing of the request must be
 	 * atomic, otherwise the card could be removed in between and the
 	 * request wouldn't fail until another card was inserted.
 	 */
 	spin_lock_bh(&host->lock);
 	if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
 		spin_unlock_bh(&host->lock);
 		mrq->cmd->error = -ENOMEDIUM;
 		mmc_request_done(mmc, mrq);
 		return;
 	}
 	dw_mci_queue_request(host, slot, mrq);
 	spin_unlock_bh(&host->lock);
 }
 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 {
 	struct dw_mci_slot *slot = mmc_priv(mmc);
 	u32 regs;
 	/* set default 1 bit mode */
 	slot->ctype = SDMMC_CTYPE_1BIT;
 	switch (ios->bus_width) {
 	case MMC_BUS_WIDTH_1:
 		slot->ctype = SDMMC_CTYPE_1BIT;
 		break;
 	case MMC_BUS_WIDTH_4:
 		slot->ctype = SDMMC_CTYPE_4BIT;
 		break;
 	case MMC_BUS_WIDTH_8:
 		slot->ctype = SDMMC_CTYPE_8BIT;
 		break;
 	}
 	regs = mci_readl(slot->host, UHS_REG);
 	/* DDR mode set */
 	if (ios->timing == MMC_TIMING_UHS_DDR50)
 		regs |= (0x1 << slot->id) << 16;
 	else
 		regs &= ~(0x1 << slot->id) << 16;
 	mci_writel(slot->host, UHS_REG, regs);
 	if (ios->clock) {
 		/*
 		 * Use mirror of ios->clock to prevent race with mmc
 		 * core ios update when finding the minimum.
 		 */
 		slot->clock = ios->clock;
 	}
 	switch (ios->power_mode) {
 	case MMC_POWER_UP:
 		set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
 		break;
 	default:
 		break;
 	}
 }
 static int dw_mci_get_ro(struct mmc_host *mmc)
 {
 	int read_only;
 	struct dw_mci_slot *slot = mmc_priv(mmc);
 	struct dw_mci_board *brd = slot->host->pdata;
 	/* Use platform get_ro function, else try on board write protect */
 	if (brd->get_ro)
 		read_only = brd->get_ro(slot->id);
 	else
 		read_only =
 			mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
 	dev_dbg(&mmc->class_dev, "card is %s\n",
 		read_only ? "read-only" : "read-write");
 	return read_only;
 }
 static int dw_mci_get_cd(struct mmc_host *mmc)
 {
 	int present;
 	struct dw_mci_slot *slot = mmc_priv(mmc);
 	struct dw_mci_board *brd = slot->host->pdata;
 	/* Use platform get_cd function, else try onboard card detect */
 	if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
 		present = 1;
 	else if (brd->get_cd)
 		present = !brd->get_cd(slot->id);
 	else
 		present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
 			== 0 ? 1 : 0;
 	if (present)
 		dev_dbg(&mmc->class_dev, "card is present\n");
 	else
 		dev_dbg(&mmc->class_dev, "card is not present\n");
 	return present;
 }
+/*
+ * Disable lower power mode.
+ *
+ * Low power mode will stop the card clock when idle.  According to the
+ * description of the CLKENA register we should disable low power mode
+ * for SDIO cards if we need SDIO interrupts to work.
+ *
+ * This function is fast if low power mode is already disabled.
+ */
+static void dw_mci_disable_low_power(struct dw_mci_slot *slot)
+{
+	struct dw_mci *host = slot->host;
+	u32 clk_en_a;
+	const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
+	clk_en_a = mci_readl(host, CLKENA);
+	if (clk_en_a & clken_low_pwr) {
+		mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr);
+		mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
+			     SDMMC_CMD_PRV_DAT_WAIT, 0);
+	}
+}
 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
 {
 	struct dw_mci_slot *slot = mmc_priv(mmc);
 	struct dw_mci *host = slot->host;
 	u32 int_mask;
 	/* Enable/disable Slot Specific SDIO interrupt */
 	int_mask = mci_readl(host, INTMASK);
 	if (enb) {
+		/*
+		 * Turn off low power mode if it was enabled.  This is a bit of
+		 * a heavy operation and we disable / enable IRQs a lot, so
+		 * we'll leave low power mode disabled and it will get
+		 * re-enabled again in dw_mci_setup_bus().
+		 */
+		dw_mci_disable_low_power(slot);
 		mci_writel(host, INTMASK,
 			   (int_mask | SDMMC_INT_SDIO(slot->id)));
 	} else {
 		mci_writel(host, INTMASK,
 			   (int_mask & ~SDMMC_INT_SDIO(slot->id)));
 	}
 }
 static const struct mmc_host_ops dw_mci_ops = {
 	.request		= dw_mci_request,
 	.pre_req		= dw_mci_pre_req,
 	.post_req		= dw_mci_post_req,
 	.set_ios		= dw_mci_set_ios,
 	.get_ro			= dw_mci_get_ro,
 	.get_cd			= dw_mci_get_cd,
 	.enable_sdio_irq	= dw_mci_enable_sdio_irq,
 };
 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
 	__releases(&host->lock)
 	__acquires(&host->lock)
 {
 	struct dw_mci_slot *slot;
 	struct mmc_host	*prev_mmc = host->cur_slot->mmc;
 	WARN_ON(host->cmd || host->data);
 	host->cur_slot->mrq = NULL;
 	host->mrq = NULL;
 	if (!list_empty(&host->queue)) {
 		slot = list_entry(host->queue.next,
 				  struct dw_mci_slot, queue_node);
 		list_del(&slot->queue_node);
 		dev_vdbg(&host->dev, "list not empty: %s is next\n",
 			 mmc_hostname(slot->mmc));
 		host->state = STATE_SENDING_CMD;
 		dw_mci_start_request(host, slot);
 	} else {
 		dev_vdbg(&host->dev, "list empty\n");
 		host->state = STATE_IDLE;
 	}
 	spin_unlock(&host->lock);
 	mmc_request_done(prev_mmc, mrq);
 	spin_lock(&host->lock);
 }
 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
 {
 	u32 status = host->cmd_status;
 	host->cmd_status = 0;
 	/* Read the response from the card (up to 16 bytes) */
 	if (cmd->flags & MMC_RSP_PRESENT) {
 		if (cmd->flags & MMC_RSP_136) {
 			cmd->resp[3] = mci_readl(host, RESP0);
 			cmd->resp[2] = mci_readl(host, RESP1);
 			cmd->resp[1] = mci_readl(host, RESP2);
 			cmd->resp[0] = mci_readl(host, RESP3);
 		} else {
 			cmd->resp[0] = mci_readl(host, RESP0);
 			cmd->resp[1] = 0;
 			cmd->resp[2] = 0;
 			cmd->resp[3] = 0;
 		}
 	}
 	if (status & SDMMC_INT_RTO)
 		cmd->error = -ETIMEDOUT;
 	else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
 		cmd->error = -EILSEQ;
 	else if (status & SDMMC_INT_RESP_ERR)
 		cmd->error = -EIO;
 	else
 		cmd->error = 0;
 	if (cmd->error) {
 		/* newer ip versions need a delay between retries */
 		if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
 			mdelay(20);
 		if (cmd->data) {
 			dw_mci_stop_dma(host);
 			host->data = NULL;
 		}
 	}
 }
 static void dw_mci_tasklet_func(unsigned long priv)
 {
 	struct dw_mci *host = (struct dw_mci *)priv;
 	struct mmc_data	*data;
 	struct mmc_command *cmd;
 	enum dw_mci_state state;
 	enum dw_mci_state prev_state;
 	u32 status, ctrl;
 	spin_lock(&host->lock);
 	state = host->state;
 	data = host->data;
 	do {
 		prev_state = state;
 		switch (state) {
 		case STATE_IDLE:
 			break;
 		case STATE_SENDING_CMD:
 			if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
 						&host->pending_events))
 				break;
 			cmd = host->cmd;
 			host->cmd = NULL;
 			set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
 			dw_mci_command_complete(host, cmd);
 			if (cmd == host->mrq->sbc && !cmd->error) {
 				prev_state = state = STATE_SENDING_CMD;
 				__dw_mci_start_request(host, host->cur_slot,
 						       host->mrq->cmd);
 				goto unlock;
 			}
 			if (!host->mrq->data || cmd->error) {
 				dw_mci_request_end(host, host->mrq);
 				goto unlock;
 			}
 			prev_state = state = STATE_SENDING_DATA;
 			/* fall through */
 		case STATE_SENDING_DATA:
 			if (test_and_clear_bit(EVENT_DATA_ERROR,
 					       &host->pending_events)) {
 				dw_mci_stop_dma(host);
 				if (data->stop)
 					send_stop_cmd(host, data);
 				state = STATE_DATA_ERROR;
 				break;
 			}
 			if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
 						&host->pending_events))
 				break;
 			set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
 			prev_state = state = STATE_DATA_BUSY;
 			/* fall through */
 		case STATE_DATA_BUSY:
 			if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
 						&host->pending_events))
 				break;
 			host->data = NULL;
 			set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
 			status = host->data_status;
 			if (status & DW_MCI_DATA_ERROR_FLAGS) {
 				if (status & SDMMC_INT_DTO) {
 					data->error = -ETIMEDOUT;
 				} else if (status & SDMMC_INT_DCRC) {
 					data->error = -EILSEQ;
 				} else if (status & SDMMC_INT_EBE &&
 					   host->dir_status ==
 							DW_MCI_SEND_STATUS) {
 					/*
 					 * No data CRC status was returned.
 					 * The number of bytes transferred will
 					 * be exaggerated in PIO mode.
 					 */
 					data->bytes_xfered = 0;
 					data->error = -ETIMEDOUT;
 				} else {
 					dev_err(&host->dev,
 						"data FIFO error "
 						"(status=%08x)\n",
 						status);
 					data->error = -EIO;
 				}
 				/*
 				 * After an error, there may be data lingering
 				 * in the FIFO, so reset it - doing so
 				 * generates a block interrupt, hence setting
 				 * the scatter-gather pointer to NULL.
 				 */
 				sg_miter_stop(&host->sg_miter);
 				host->sg = NULL;
 				ctrl = mci_readl(host, CTRL);
 				ctrl |= SDMMC_CTRL_FIFO_RESET;
 				mci_writel(host, CTRL, ctrl);
 			} else {
 				data->bytes_xfered = data->blocks * data->blksz;
 				data->error = 0;
 			}
 			if (!data->stop) {
 				dw_mci_request_end(host, host->mrq);
 				goto unlock;
 			}
 			if (host->mrq->sbc && !data->error) {
 				data->stop->error = 0;
 				dw_mci_request_end(host, host->mrq);
 				goto unlock;
 			}
 			prev_state = state = STATE_SENDING_STOP;
 			if (!data->error)
 				send_stop_cmd(host, data);
 			/* fall through */
 		case STATE_SENDING_STOP:
 			if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
 						&host->pending_events))
 				break;
 			host->cmd = NULL;
 			dw_mci_command_complete(host, host->mrq->stop);
 			dw_mci_request_end(host, host->mrq);
 			goto unlock;
 		case STATE_DATA_ERROR:
 			if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
 						&host->pending_events))
 				break;
 			state = STATE_DATA_BUSY;
 			break;
 		}
 	} while (state != prev_state);
 	host->state = state;
 unlock:
 	spin_unlock(&host->lock);
 }
 /* push final bytes to part_buf, only use during push */
 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
 {
 	memcpy((void *)&host->part_buf, buf, cnt);
 	host->part_buf_count = cnt;
 }
 /* append bytes to part_buf, only use during push */
 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
 {
 	cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
 	memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
 	host->part_buf_count += cnt;
 	return cnt;
 }
 /* pull first bytes from part_buf, only use during pull */
 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
 {
 	cnt = min(cnt, (int)host->part_buf_count);
 	if (cnt) {
 		memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
 		       cnt);
 		host->part_buf_count -= cnt;
 		host->part_buf_start += cnt;
 	}
 	return cnt;
 }
 /* pull final bytes from the part_buf, assuming it's just been filled */
 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
 {
 	memcpy(buf, &host->part_buf, cnt);
 	host->part_buf_start = cnt;
 	host->part_buf_count = (1 << host->data_shift) - cnt;
 }
 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
 {
 	/* try and push anything in the part_buf */
 	if (unlikely(host->part_buf_count)) {
 		int len = dw_mci_push_part_bytes(host, buf, cnt);
 		buf += len;
 		cnt -= len;
 		if (!sg_next(host->sg) || host->part_buf_count == 2) {
 			mci_writew(host, DATA(host->data_offset),
 					host->part_buf16);
 			host->part_buf_count = 0;
 		}
 	}
 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
 	if (unlikely((unsigned long)buf & 0x1)) {
 		while (cnt >= 2) {
 			u16 aligned_buf[64];
 			int len = min(cnt & -2, (int)sizeof(aligned_buf));
 			int items = len >> 1;
 			int i;
 			/* memcpy from input buffer into aligned buffer */
 			memcpy(aligned_buf, buf, len);
 			buf += len;
 			cnt -= len;
 			/* push data from aligned buffer into fifo */
 			for (i = 0; i < items; ++i)
 				mci_writew(host, DATA(host->data_offset),
 						aligned_buf[i]);
 		}
 	} else
 #endif
 	{
 		u16 *pdata = buf;
 		for (; cnt >= 2; cnt -= 2)
 			mci_writew(host, DATA(host->data_offset), *pdata++);
 		buf = pdata;
 	}
 	/* put anything remaining in the part_buf */
 	if (cnt) {
 		dw_mci_set_part_bytes(host, buf, cnt);
 		if (!sg_next(host->sg))
 			mci_writew(host, DATA(host->data_offset),
 					host->part_buf16);
 	}
 }
 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
 {
 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
 	if (unlikely((unsigned long)buf & 0x1)) {
 		while (cnt >= 2) {
 			/* pull data from fifo into aligned buffer */
 			u16 aligned_buf[64];
 			int len = min(cnt & -2, (int)sizeof(aligned_buf));
 			int items = len >> 1;
 			int i;
 			for (i = 0; i < items; ++i)
 				aligned_buf[i] = mci_readw(host,
 						DATA(host->data_offset));
 			/* memcpy from aligned buffer into output buffer */
 			memcpy(buf, aligned_buf, len);
 			buf += len;
 			cnt -= len;
 		}
 	} else
 #endif
 	{
 		u16 *pdata = buf;
 		for (; cnt >= 2; cnt -= 2)
 			*pdata++ = mci_readw(host, DATA(host->data_offset));
 		buf = pdata;
 	}
 	if (cnt) {
 		host->part_buf16 = mci_readw(host, DATA(host->data_offset));
 		dw_mci_pull_final_bytes(host, buf, cnt);
 	}
 }
 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
 {
 	/* try and push anything in the part_buf */
 	if (unlikely(host->part_buf_count)) {
 		int len = dw_mci_push_part_bytes(host, buf, cnt);
 		buf += len;
 		cnt -= len;
 		if (!sg_next(host->sg) || host->part_buf_count == 4) {
 			mci_writel(host, DATA(host->data_offset),
 					host->part_buf32);
 			host->part_buf_count = 0;
 		}
 	}
 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
 	if (unlikely((unsigned long)buf & 0x3)) {
 		while (cnt >= 4) {
 			u32 aligned_buf[32];
 			int len = min(cnt & -4, (int)sizeof(aligned_buf));
 			int items = len >> 2;
 			int i;
 			/* memcpy from input buffer into aligned buffer */
 			memcpy(aligned_buf, buf, len);
 			buf += len;
 			cnt -= len;
 			/* push data from aligned buffer into fifo */
 			for (i = 0; i < items; ++i)
 				mci_writel(host, DATA(host->data_offset),
 						aligned_buf[i]);
 		}
 	} else
 #endif
 	{
 		u32 *pdata = buf;
 		for (; cnt >= 4; cnt -= 4)
 			mci_writel(host, DATA(host->data_offset), *pdata++);
 		buf = pdata;
 	}
 	/* put anything remaining in the part_buf */
 	if (cnt) {
 		dw_mci_set_part_bytes(host, buf, cnt);
 		if (!sg_next(host->sg))
 			mci_writel(host, DATA(host->data_offset),
 						host->part_buf32);
 	}
 }
 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
 {
 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
 	if (unlikely((unsigned long)buf & 0x3)) {
 		while (cnt >= 4) {
 			/* pull data from fifo into aligned buffer */
 			u32 aligned_buf[32];
 			int len = min(cnt & -4, (int)sizeof(aligned_buf));
 			int items = len >> 2;
 			int i;
 			for (i = 0; i < items; ++i)
 				aligned_buf[i] = mci_readl(host,
 						DATA(host->data_offset));
 			/* memcpy from aligned buffer into output buffer */
 			memcpy(buf, aligned_buf, len);
 			buf += len;
 			cnt -= len;
 		}
 	} else
 #endif
 	{
 		u32 *pdata = buf;
 		for (; cnt >= 4; cnt -= 4)
 			*pdata++ = mci_readl(host, DATA(host->data_offset));
 		buf = pdata;
 	}
 	if (cnt) {
 		host->part_buf32 = mci_readl(host, DATA(host->data_offset));
 		dw_mci_pull_final_bytes(host, buf, cnt);
 	}
 }
 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
 {
 	/* try and push anything in the part_buf */
 	if (unlikely(host->part_buf_count)) {
 		int len = dw_mci_push_part_bytes(host, buf, cnt);
 		buf += len;
 		cnt -= len;
 		if (!sg_next(host->sg) || host->part_buf_count == 8) {
 			mci_writew(host, DATA(host->data_offset),
 					host->part_buf);
 			host->part_buf_count = 0;
 		}
 	}
 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
 	if (unlikely((unsigned long)buf & 0x7)) {
 		while (cnt >= 8) {
 			u64 aligned_buf[16];
 			int len = min(cnt & -8, (int)sizeof(aligned_buf));
 			int items = len >> 3;
 			int i;
 			/* memcpy from input buffer into aligned buffer */
 			memcpy(aligned_buf, buf, len);
 			buf += len;
 			cnt -= len;
 			/* push data from aligned buffer into fifo */
 			for (i = 0; i < items; ++i)
 				mci_writeq(host, DATA(host->data_offset),
 						aligned_buf[i]);
 		}
 	} else
 #endif
 	{
 		u64 *pdata = buf;
 		for (; cnt >= 8; cnt -= 8)
 			mci_writeq(host, DATA(host->data_offset), *pdata++);
 		buf = pdata;
 	}
 	/* put anything remaining in the part_buf */
 	if (cnt) {
 		dw_mci_set_part_bytes(host, buf, cnt);
 		if (!sg_next(host->sg))
 			mci_writeq(host, DATA(host->data_offset),
 					host->part_buf);
 	}
 }
 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
 {
 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
 	if (unlikely((unsigned long)buf & 0x7)) {
 		while (cnt >= 8) {
 			/* pull data from fifo into aligned buffer */
 			u64 aligned_buf[16];
 			int len = min(cnt & -8, (int)sizeof(aligned_buf));
 			int items = len >> 3;
 			int i;
 			for (i = 0; i < items; ++i)
 				aligned_buf[i] = mci_readq(host,
 						DATA(host->data_offset));
 			/* memcpy from aligned buffer into output buffer */
 			memcpy(buf, aligned_buf, len);
 			buf += len;
 			cnt -= len;
 		}
 	} else
 #endif
 	{
 		u64 *pdata = buf;
 		for (; cnt >= 8; cnt -= 8)
 			*pdata++ = mci_readq(host, DATA(host->data_offset));
 		buf = pdata;
 	}
 	if (cnt) {
 		host->part_buf = mci_readq(host, DATA(host->data_offset));
 		dw_mci_pull_final_bytes(host, buf, cnt);
 	}
 }
 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
 {
 	int len;
 	/* get remaining partial bytes */
 	len = dw_mci_pull_part_bytes(host, buf, cnt);
 	if (unlikely(len == cnt))
 		return;
 	buf += len;
 	cnt -= len;
 	/* get the rest of the data */
 	host->pull_data(host, buf, cnt);
 }
 static void dw_mci_read_data_pio(struct dw_mci *host)
 {
 	struct sg_mapping_iter *sg_miter = &host->sg_miter;
 	void *buf;
 	unsigned int offset;
 	struct mmc_data	*data = host->data;
 	int shift = host->data_shift;
 	u32 status;
 	unsigned int nbytes = 0, len;
 	unsigned int remain, fcnt;
 	do {
 		if (!sg_miter_next(sg_miter))
 			goto done;
 		host->sg = sg_miter->__sg;
 		buf = sg_miter->addr;
 		remain = sg_miter->length;
 		offset = 0;
 		do {
 			fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
 					<< shift) + host->part_buf_count;
 			len = min(remain, fcnt);
 			if (!len)
 				break;
 			dw_mci_pull_data(host, (void *)(buf + offset), len);
 			offset += len;
 			nbytes += len;
 			remain -= len;
 		} while (remain);
-		sg_miter->consumed = offset;
+		sg_miter->consumed = offset;
 		status = mci_readl(host, MINTSTS);
 		mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
-		if (status & DW_MCI_DATA_ERROR_FLAGS) {
-			host->data_status = status;
-			data->bytes_xfered += nbytes;
-			sg_miter_stop(sg_miter);
-			host->sg = NULL;
-			smp_wmb();
-			set_bit(EVENT_DATA_ERROR, &host->pending_events);
-			tasklet_schedule(&host->tasklet);
-			return;
-		}
 	} while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/
 	data->bytes_xfered += nbytes;
 	if (!remain) {
 		if (!sg_miter_next(sg_miter))
 			goto done;
 		sg_miter->consumed = 0;
 	}
 	sg_miter_stop(sg_miter);
 	return;
 done:
 	data->bytes_xfered += nbytes;
 	sg_miter_stop(sg_miter);
 	host->sg = NULL;
 	smp_wmb();
 	set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 }
 static void dw_mci_write_data_pio(struct dw_mci *host)
 {
 	struct sg_mapping_iter *sg_miter = &host->sg_miter;
 	void *buf;
 	unsigned int offset;
 	struct mmc_data	*data = host->data;
 	int shift = host->data_shift;
 	u32 status;
 	unsigned int nbytes = 0, len;
 	unsigned int fifo_depth = host->fifo_depth;
 	unsigned int remain, fcnt;
 	do {
 		if (!sg_miter_next(sg_miter))
 			goto done;
 		host->sg = sg_miter->__sg;
 		buf = sg_miter->addr;
 		remain = sg_miter->length;
 		offset = 0;
 		do {
 			fcnt = ((fifo_depth -
 				 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
 					<< shift) - host->part_buf_count;
 			len = min(remain, fcnt);
 			if (!len)
 				break;
 			host->push_data(host, (void *)(buf + offset), len);
 			offset += len;
 			nbytes += len;
 			remain -= len;
 		} while (remain);
-		sg_miter->consumed = offset;
+		sg_miter->consumed = offset;
 		status = mci_readl(host, MINTSTS);
 		mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
-		if (status & DW_MCI_DATA_ERROR_FLAGS) {
-			host->data_status = status;
-			data->bytes_xfered += nbytes;
-			sg_miter_stop(sg_miter);
-			host->sg = NULL;
-			smp_wmb();
-			set_bit(EVENT_DATA_ERROR, &host->pending_events);
-			tasklet_schedule(&host->tasklet);
-			return;
-		}
 	} while (status & SDMMC_INT_TXDR); /* if TXDR write again */
 	data->bytes_xfered += nbytes;
 	if (!remain) {
 		if (!sg_miter_next(sg_miter))
 			goto done;
 		sg_miter->consumed = 0;
 	}
 	sg_miter_stop(sg_miter);
 	return;
 done:
 	data->bytes_xfered += nbytes;
 	sg_miter_stop(sg_miter);
 	host->sg = NULL;
 	smp_wmb();
 	set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 }
 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
 {
 	if (!host->cmd_status)
 		host->cmd_status = status;
 	smp_wmb();
 	set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
 	tasklet_schedule(&host->tasklet);
 }
 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
 {
 	struct dw_mci *host = dev_id;
-	u32 status, pending;
+	u32 pending;
 	unsigned int pass_count = 0;
 	int i;
 	do {
-		status = mci_readl(host, RINTSTS);
 		pending = mci_readl(host, MINTSTS); /* read-only mask reg */
 		/*
 		 * DTO fix - version 2.10a and below, and only if internal DMA
 		 * is configured.
 		 */
 		if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
 			if (!pending &&
 			    ((mci_readl(host, STATUS) >> 17) & 0x1fff))
 				pending |= SDMMC_INT_DATA_OVER;
 		}
 		if (!pending)
 			break;
 		if (pending & DW_MCI_CMD_ERROR_FLAGS) {
 			mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
-			host->cmd_status = status;
+			host->cmd_status = pending;
 			smp_wmb();
 			set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
 		}
 		if (pending & DW_MCI_DATA_ERROR_FLAGS) {
 			/* if there is an error report DATA_ERROR */
 			mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
-			host->data_status = status;
+			host->data_status = pending;
 			smp_wmb();
 			set_bit(EVENT_DATA_ERROR, &host->pending_events);
-			if (!(pending & (SDMMC_INT_DTO | SDMMC_INT_DCRC |
+			tasklet_schedule(&host->tasklet);
-					 SDMMC_INT_SBE | SDMMC_INT_EBE)))
-				tasklet_schedule(&host->tasklet);
 		}
 		if (pending & SDMMC_INT_DATA_OVER) {
 			mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
 			if (!host->data_status)
-				host->data_status = status;
+				host->data_status = pending;
 			smp_wmb();
 			if (host->dir_status == DW_MCI_RECV_STATUS) {
 				if (host->sg != NULL)
 					dw_mci_read_data_pio(host);
 			}
 			set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
 			tasklet_schedule(&host->tasklet);
 		}
 		if (pending & SDMMC_INT_RXDR) {
 			mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
 			if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
 				dw_mci_read_data_pio(host);
 		}
 		if (pending & SDMMC_INT_TXDR) {
 			mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
 			if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
 				dw_mci_write_data_pio(host);
 		}
 		if (pending & SDMMC_INT_CMD_DONE) {
 			mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
-			dw_mci_cmd_interrupt(host, status);
+			dw_mci_cmd_interrupt(host, pending);
 		}
 		if (pending & SDMMC_INT_CD) {
 			mci_writel(host, RINTSTS, SDMMC_INT_CD);
 			queue_work(host->card_workqueue, &host->card_work);
 		}
 		/* Handle SDIO Interrupts */
 		for (i = 0; i < host->num_slots; i++) {
 			struct dw_mci_slot *slot = host->slot[i];
 			if (pending & SDMMC_INT_SDIO(i)) {
 				mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i));
 				mmc_signal_sdio_irq(slot->mmc);
 			}
 		}
 	} while (pass_count++ < 5);
 #ifdef CONFIG_MMC_DW_IDMAC
 	/* Handle DMA interrupts */
 	pending = mci_readl(host, IDSTS);
 	if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
 		mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
 		mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
 		host->dma_ops->complete(host);
 	}
 #endif
 	return IRQ_HANDLED;
 }
 static void dw_mci_work_routine_card(struct work_struct *work)
 {
 	struct dw_mci *host = container_of(work, struct dw_mci, card_work);
 	int i;
 	for (i = 0; i < host->num_slots; i++) {
 		struct dw_mci_slot *slot = host->slot[i];
 		struct mmc_host *mmc = slot->mmc;
 		struct mmc_request *mrq;
 		int present;
 		u32 ctrl;
 		present = dw_mci_get_cd(mmc);
 		while (present != slot->last_detect_state) {
 			dev_dbg(&slot->mmc->class_dev, "card %s\n",
 				present ? "inserted" : "removed");
 			/* Power up slot (before spin_lock, may sleep) */
 			if (present != 0 && host->pdata->setpower)
 				host->pdata->setpower(slot->id, mmc->ocr_avail);
 			spin_lock_bh(&host->lock);
 			/* Card change detected */
 			slot->last_detect_state = present;
 			/* Mark card as present if applicable */
 			if (present != 0)
 				set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
 			/* Clean up queue if present */
 			mrq = slot->mrq;
 			if (mrq) {
 				if (mrq == host->mrq) {
 					host->data = NULL;
 					host->cmd = NULL;
 					switch (host->state) {
 					case STATE_IDLE:
 						break;
 					case STATE_SENDING_CMD:
 						mrq->cmd->error = -ENOMEDIUM;
 						if (!mrq->data)
 							break;
 						/* fall through */
 					case STATE_SENDING_DATA:
 						mrq->data->error = -ENOMEDIUM;
 						dw_mci_stop_dma(host);
 						break;
 					case STATE_DATA_BUSY:
 					case STATE_DATA_ERROR:
 						if (mrq->data->error == -EINPROGRESS)
 							mrq->data->error = -ENOMEDIUM;
 						if (!mrq->stop)
 							break;
 						/* fall through */
 					case STATE_SENDING_STOP:
 						mrq->stop->error = -ENOMEDIUM;
 						break;
 					}
 					dw_mci_request_end(host, mrq);
 				} else {
 					list_del(&slot->queue_node);
 					mrq->cmd->error = -ENOMEDIUM;
 					if (mrq->data)
 						mrq->data->error = -ENOMEDIUM;
 					if (mrq->stop)
 						mrq->stop->error = -ENOMEDIUM;
 					spin_unlock(&host->lock);
 					mmc_request_done(slot->mmc, mrq);
 					spin_lock(&host->lock);
 				}
 			}
 			/* Power down slot */
 			if (present == 0) {
 				clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
 				/*
 				 * Clear down the FIFO - doing so generates a
 				 * block interrupt, hence setting the
 				 * scatter-gather pointer to NULL.
 				 */
 				sg_miter_stop(&host->sg_miter);
 				host->sg = NULL;
 				ctrl = mci_readl(host, CTRL);
 				ctrl |= SDMMC_CTRL_FIFO_RESET;
 				mci_writel(host, CTRL, ctrl);
 #ifdef CONFIG_MMC_DW_IDMAC
 				ctrl = mci_readl(host, BMOD);
 				/* Software reset of DMA */
 				ctrl |= SDMMC_IDMAC_SWRESET;
 				mci_writel(host, BMOD, ctrl);
 #endif
 			}
 			spin_unlock_bh(&host->lock);
 			/* Power down slot (after spin_unlock, may sleep) */
 			if (present == 0 && host->pdata->setpower)
 				host->pdata->setpower(slot->id, 0);
 			present = dw_mci_get_cd(mmc);
 		}
 		mmc_detect_change(slot->mmc,
 			msecs_to_jiffies(host->pdata->detect_delay_ms));
 	}
 }
 static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)
 {
 	struct mmc_host *mmc;
 	struct dw_mci_slot *slot;
 	mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), &host->dev);
 	if (!mmc)
 		return -ENOMEM;
 	slot = mmc_priv(mmc);
 	slot->id = id;
 	slot->mmc = mmc;
 	slot->host = host;
 	mmc->ops = &dw_mci_ops;
 	mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
 	mmc->f_max = host->bus_hz;
 	if (host->pdata->get_ocr)
 		mmc->ocr_avail = host->pdata->get_ocr(id);
 	else
 		mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
 	/*
 	 * Start with slot power disabled, it will be enabled when a card
 	 * is detected.
 	 */
 	if (host->pdata->setpower)
 		host->pdata->setpower(id, 0);
 	if (host->pdata->caps)
 		mmc->caps = host->pdata->caps;
 	if (host->pdata->caps2)
 		mmc->caps2 = host->pdata->caps2;
 	if (host->pdata->get_bus_wd)
 		if (host->pdata->get_bus_wd(slot->id) >= 4)
 			mmc->caps |= MMC_CAP_4_BIT_DATA;
 	if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED)
 		mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
 	if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
 		mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
 	else
 		mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
 	if (host->pdata->blk_settings) {
 		mmc->max_segs = host->pdata->blk_settings->max_segs;
 		mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
 		mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
 		mmc->max_req_size = host->pdata->blk_settings->max_req_size;
 		mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
 	} else {
 		/* Useful defaults if platform data is unset. */
 #ifdef CONFIG_MMC_DW_IDMAC
 		mmc->max_segs = host->ring_size;
 		mmc->max_blk_size = 65536;
 		mmc->max_blk_count = host->ring_size;
 		mmc->max_seg_size = 0x1000;
 		mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
 #else
 		mmc->max_segs = 64;
 		mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
 		mmc->max_blk_count = 512;
 		mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
 		mmc->max_seg_size = mmc->max_req_size;
 #endif /* CONFIG_MMC_DW_IDMAC */
 	}
 	host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
 	if (IS_ERR(host->vmmc)) {
 		pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
 		host->vmmc = NULL;
 	} else
 		regulator_enable(host->vmmc);
 	if (dw_mci_get_cd(mmc))
 		set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
 	else
 		clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
 	host->slot[id] = slot;
 	mmc_add_host(mmc);
 #if defined(CONFIG_DEBUG_FS)
 	dw_mci_init_debugfs(slot);
 #endif
 	/* Card initially undetected */
 	slot->last_detect_state = 0;
 	/*
 	 * Card may have been plugged in prior to boot so we
 	 * need to run the detect tasklet
 	 */
 	queue_work(host->card_workqueue, &host->card_work);
 	return 0;
 }
 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
 {
 	/* Shutdown detect IRQ */
 	if (slot->host->pdata->exit)
 		slot->host->pdata->exit(id);
 	/* Debugfs stuff is cleaned up by mmc core */
 	mmc_remove_host(slot->mmc);
 	slot->host->slot[id] = NULL;
 	mmc_free_host(slot->mmc);
 }
 static void dw_mci_init_dma(struct dw_mci *host)
 {
 	/* Alloc memory for sg translation */
 	host->sg_cpu = dma_alloc_coherent(&host->dev, PAGE_SIZE,
 					  &host->sg_dma, GFP_KERNEL);
 	if (!host->sg_cpu) {
 		dev_err(&host->dev, "%s: could not alloc DMA memory\n",
 			__func__);
 		goto no_dma;
 	}
 	/* Determine which DMA interface to use */
 #ifdef CONFIG_MMC_DW_IDMAC
 	host->dma_ops = &dw_mci_idmac_ops;
 #endif
 	if (!host->dma_ops)
 		goto no_dma;
 	if (host->dma_ops->init && host->dma_ops->start &&
 	    host->dma_ops->stop && host->dma_ops->cleanup) {
 		if (host->dma_ops->init(host)) {
 			dev_err(&host->dev, "%s: Unable to initialize "
 				"DMA Controller.\n", __func__);
 			goto no_dma;
 		}
 	} else {
 		dev_err(&host->dev, "DMA initialization not found.\n");
 		goto no_dma;
 	}
 	host->use_dma = 1;
 	return;
 no_dma:
 	dev_info(&host->dev, "Using PIO mode.\n");
 	host->use_dma = 0;
 	return;
 }
 static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
 {
 	unsigned long timeout = jiffies + msecs_to_jiffies(500);
 	unsigned int ctrl;
 	mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
 				SDMMC_CTRL_DMA_RESET));
 	/* wait till resets clear */
 	do {
 		ctrl = mci_readl(host, CTRL);
 		if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
 			      SDMMC_CTRL_DMA_RESET)))
 			return true;
 	} while (time_before(jiffies, timeout));
 	dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
 	return false;
 }
 int dw_mci_probe(struct dw_mci *host)
 {
 	int width, i, ret = 0;
 	u32 fifo_size;
 	if (!host->pdata || !host->pdata->init) {
 		dev_err(&host->dev,
 			"Platform data must supply init function\n");
 		return -ENODEV;
 	}
 	if (!host->pdata->select_slot && host->pdata->num_slots > 1) {
 		dev_err(&host->dev,
 			"Platform data must supply select_slot function\n");
 		return -ENODEV;
 	}
 	if (!host->pdata->bus_hz) {
 		dev_err(&host->dev,
 			"Platform data must supply bus speed\n");
 		return -ENODEV;
 	}
 	host->bus_hz = host->pdata->bus_hz;
 	host->quirks = host->pdata->quirks;
 	spin_lock_init(&host->lock);
 	INIT_LIST_HEAD(&host->queue);
 	/*
 	 * Get the host data width - this assumes that HCON has been set with
 	 * the correct values.
 	 */
 	i = (mci_readl(host, HCON) >> 7) & 0x7;
 	if (!i) {
 		host->push_data = dw_mci_push_data16;
 		host->pull_data = dw_mci_pull_data16;
 		width = 16;
 		host->data_shift = 1;
 	} else if (i == 2) {
 		host->push_data = dw_mci_push_data64;
 		host->pull_data = dw_mci_pull_data64;
 		width = 64;
 		host->data_shift = 3;
 	} else {
 		/* Check for a reserved value, and warn if it is */
 		WARN((i != 1),
 		     "HCON reports a reserved host data width!\n"
 		     "Defaulting to 32-bit access.\n");
 		host->push_data = dw_mci_push_data32;
 		host->pull_data = dw_mci_pull_data32;
 		width = 32;
 		host->data_shift = 2;
 	}
 	/* Reset all blocks */
 	if (!mci_wait_reset(&host->dev, host))
 		return -ENODEV;
 	host->dma_ops = host->pdata->dma_ops;
 	dw_mci_init_dma(host);
 	/* Clear the interrupts for the host controller */
 	mci_writel(host, RINTSTS, 0xFFFFFFFF);
 	mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
 	/* Put in max timeout */
 	mci_writel(host, TMOUT, 0xFFFFFFFF);
 	/*
 	 * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
 	 *                          Tx Mark = fifo_size / 2 DMA Size = 8
 	 */
 	if (!host->pdata->fifo_depth) {
 		/*
 		 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
 		 * have been overwritten by the bootloader, just like we're
 		 * about to do, so if you know the value for your hardware, you
 		 * should put it in the platform data.
 		 */
 		fifo_size = mci_readl(host, FIFOTH);
 		fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
 	} else {
 		fifo_size = host->pdata->fifo_depth;
 	}
 	host->fifo_depth = fifo_size;
 	host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) |
 			((fifo_size/2) << 0));
 	mci_writel(host, FIFOTH, host->fifoth_val);
 	/* disable clock to CIU */
 	mci_writel(host, CLKENA, 0);
 	mci_writel(host, CLKSRC, 0);
 	tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
 	host->card_workqueue = alloc_workqueue("dw-mci-card",
 			WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
 	if (!host->card_workqueue)
 		goto err_dmaunmap;
 	INIT_WORK(&host->card_work, dw_mci_work_routine_card);
 	ret = request_irq(host->irq, dw_mci_interrupt, host->irq_flags, "dw-mci", host);
 	if (ret)
 		goto err_workqueue;
 	if (host->pdata->num_slots)
 		host->num_slots = host->pdata->num_slots;
 	else
 		host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
 	/* We need at least one slot to succeed */
 	for (i = 0; i < host->num_slots; i++) {
 		ret = dw_mci_init_slot(host, i);
 		if (ret) {
 			ret = -ENODEV;
 			goto err_init_slot;
 		}
 	}
 	/*
 	 * In 2.40a spec, Data offset is changed.
 	 * Need to check the version-id and set data-offset for DATA register.
 	 */
 	host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
 	dev_info(&host->dev, "Version ID is %04x\n", host->verid);
 	if (host->verid < DW_MMC_240A)
 		host->data_offset = DATA_OFFSET;
 	else
 		host->data_offset = DATA_240A_OFFSET;
 	/*
 	 * Enable interrupts for command done, data over, data empty, card det,
 	 * receive ready and error such as transmit, receive timeout, crc error
 	 */
 	mci_writel(host, RINTSTS, 0xFFFFFFFF);
 	mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
 		   SDMMC_INT_TXDR | SDMMC_INT_RXDR |
 		   DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
 	mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
 	dev_info(&host->dev, "DW MMC controller at irq %d, "
 		 "%d bit host data width, "
 		 "%u deep fifo\n",
 		 host->irq, width, fifo_size);
 	if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
 		dev_info(&host->dev, "Internal DMAC interrupt fix enabled.\n");
 	return 0;
 err_init_slot:
 	/* De-init any initialized slots */
 	while (i > 0) {
 		if (host->slot[i])
 			dw_mci_cleanup_slot(host->slot[i], i);
 		i--;
 	}
 	free_irq(host->irq, host);
 err_workqueue:
 	destroy_workqueue(host->card_workqueue);
 err_dmaunmap:
 	if (host->use_dma && host->dma_ops->exit)
 		host->dma_ops->exit(host);
 	dma_free_coherent(&host->dev, PAGE_SIZE,
 			  host->sg_cpu, host->sg_dma);
 	if (host->vmmc) {
 		regulator_disable(host->vmmc);
 		regulator_put(host->vmmc);
 	}
 	return ret;
 }
 EXPORT_SYMBOL(dw_mci_probe);
 void dw_mci_remove(struct dw_mci *host)
 {
 	int i;
 	mci_writel(host, RINTSTS, 0xFFFFFFFF);
 	mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
 	for (i = 0; i < host->num_slots; i++) {
 		dev_dbg(&host->dev, "remove slot %d\n", i);
 		if (host->slot[i])
 			dw_mci_cleanup_slot(host->slot[i], i);
 	}
 	/* disable clock to CIU */
 	mci_writel(host, CLKENA, 0);
 	mci_writel(host, CLKSRC, 0);
 	free_irq(host->irq, host);
 	destroy_workqueue(host->card_workqueue);
 	dma_free_coherent(&host->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
 	if (host->use_dma && host->dma_ops->exit)
 		host->dma_ops->exit(host);
 	if (host->vmmc) {
 		regulator_disable(host->vmmc);
 		regulator_put(host->vmmc);
 	}
 }
 EXPORT_SYMBOL(dw_mci_remove);
 #ifdef CONFIG_PM_SLEEP
 /*
  * TODO: we should probably disable the clock to the card in the suspend path.
  */
 int dw_mci_suspend(struct dw_mci *host)
 {
 	int i, ret = 0;
 	for (i = 0; i < host->num_slots; i++) {
 		struct dw_mci_slot *slot = host->slot[i];
 		if (!slot)
 			continue;
 		ret = mmc_suspend_host(slot->mmc);
 		if (ret < 0) {
 			while (--i >= 0) {
 				slot = host->slot[i];
 				if (slot)
 					mmc_resume_host(host->slot[i]->mmc);
 			}
 			return ret;
 		}
 	}
 	if (host->vmmc)
 		regulator_disable(host->vmmc);
 	return 0;
 }
 EXPORT_SYMBOL(dw_mci_suspend);
 int dw_mci_resume(struct dw_mci *host)
 {
 	int i, ret;
 	if (host->vmmc)
 		regulator_enable(host->vmmc);
 	if (!mci_wait_reset(&host->dev, host)) {
 		ret = -ENODEV;
 		return ret;
 	}
 	if (host->use_dma && host->dma_ops->init)
 		host->dma_ops->init(host);
 	/* Restore the old value at FIFOTH register */
 	mci_writel(host, FIFOTH, host->fifoth_val);
 	mci_writel(host, RINTSTS, 0xFFFFFFFF);
 	mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
 		   SDMMC_INT_TXDR | SDMMC_INT_RXDR |
 		   DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
 	mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
 	for (i = 0; i < host->num_slots; i++) {

drivers/mmc/host/mxs-mmc.c

Diff comments View file @ 0809095

 /*
  * Portions copyright (C) 2003 Russell King, PXA MMCI Driver
  * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
  *
  * Copyright 2008 Embedded Alley Solutions, Inc.
  * Copyright 2009-2011 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License along
  * with this program; if not, write to the Free Software Foundation, Inc.,
  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/ioport.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/of_gpio.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/interrupt.h>
 #include <linux/dma-mapping.h>
 #include <linux/dmaengine.h>
 #include <linux/highmem.h>
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/completion.h>
 #include <linux/mmc/host.h>
 #include <linux/mmc/mmc.h>
 #include <linux/mmc/sdio.h>
 #include <linux/gpio.h>
 #include <linux/regulator/consumer.h>
 #include <linux/module.h>
 #include <linux/fsl/mxs-dma.h>
 #include <linux/pinctrl/consumer.h>
 #include <linux/stmp_device.h>
 #include <linux/mmc/mxs-mmc.h>
 #define DRIVER_NAME	"mxs-mmc"
 /* card detect polling timeout */
 #define MXS_MMC_DETECT_TIMEOUT			(HZ/2)
 #define ssp_is_old(host)	((host)->devid == IMX23_MMC)
 /* SSP registers */
 #define HW_SSP_CTRL0				0x000
 #define  BM_SSP_CTRL0_RUN			(1 << 29)
 #define  BM_SSP_CTRL0_SDIO_IRQ_CHECK		(1 << 28)
 #define  BM_SSP_CTRL0_IGNORE_CRC		(1 << 26)
 #define  BM_SSP_CTRL0_READ			(1 << 25)
 #define  BM_SSP_CTRL0_DATA_XFER			(1 << 24)
 #define  BP_SSP_CTRL0_BUS_WIDTH			(22)
 #define  BM_SSP_CTRL0_BUS_WIDTH			(0x3 << 22)
 #define  BM_SSP_CTRL0_WAIT_FOR_IRQ		(1 << 21)
 #define  BM_SSP_CTRL0_LONG_RESP			(1 << 19)
 #define  BM_SSP_CTRL0_GET_RESP			(1 << 17)
 #define  BM_SSP_CTRL0_ENABLE			(1 << 16)
 #define  BP_SSP_CTRL0_XFER_COUNT		(0)
 #define  BM_SSP_CTRL0_XFER_COUNT		(0xffff)
 #define HW_SSP_CMD0				0x010
 #define  BM_SSP_CMD0_DBL_DATA_RATE_EN		(1 << 25)
 #define  BM_SSP_CMD0_SLOW_CLKING_EN		(1 << 22)
 #define  BM_SSP_CMD0_CONT_CLKING_EN		(1 << 21)
 #define  BM_SSP_CMD0_APPEND_8CYC		(1 << 20)
 #define  BP_SSP_CMD0_BLOCK_SIZE			(16)
 #define  BM_SSP_CMD0_BLOCK_SIZE			(0xf << 16)
 #define  BP_SSP_CMD0_BLOCK_COUNT		(8)
 #define  BM_SSP_CMD0_BLOCK_COUNT		(0xff << 8)
 #define  BP_SSP_CMD0_CMD			(0)
 #define  BM_SSP_CMD0_CMD			(0xff)
 #define HW_SSP_CMD1				0x020
 #define HW_SSP_XFER_SIZE			0x030
 #define HW_SSP_BLOCK_SIZE			0x040
 #define  BP_SSP_BLOCK_SIZE_BLOCK_COUNT		(4)
 #define  BM_SSP_BLOCK_SIZE_BLOCK_COUNT		(0xffffff << 4)
 #define  BP_SSP_BLOCK_SIZE_BLOCK_SIZE		(0)
 #define  BM_SSP_BLOCK_SIZE_BLOCK_SIZE		(0xf)
 #define HW_SSP_TIMING(h)			(ssp_is_old(h) ? 0x050 : 0x070)
 #define  BP_SSP_TIMING_TIMEOUT			(16)
 #define  BM_SSP_TIMING_TIMEOUT			(0xffff << 16)
 #define  BP_SSP_TIMING_CLOCK_DIVIDE		(8)
 #define  BM_SSP_TIMING_CLOCK_DIVIDE		(0xff << 8)
 #define  BP_SSP_TIMING_CLOCK_RATE		(0)
 #define  BM_SSP_TIMING_CLOCK_RATE		(0xff)
 #define HW_SSP_CTRL1(h)				(ssp_is_old(h) ? 0x060 : 0x080)
 #define  BM_SSP_CTRL1_SDIO_IRQ			(1 << 31)
 #define  BM_SSP_CTRL1_SDIO_IRQ_EN		(1 << 30)
 #define  BM_SSP_CTRL1_RESP_ERR_IRQ		(1 << 29)
 #define  BM_SSP_CTRL1_RESP_ERR_IRQ_EN		(1 << 28)
 #define  BM_SSP_CTRL1_RESP_TIMEOUT_IRQ		(1 << 27)
 #define  BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN	(1 << 26)
 #define  BM_SSP_CTRL1_DATA_TIMEOUT_IRQ		(1 << 25)
 #define  BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN	(1 << 24)
 #define  BM_SSP_CTRL1_DATA_CRC_IRQ		(1 << 23)
 #define  BM_SSP_CTRL1_DATA_CRC_IRQ_EN		(1 << 22)
 #define  BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ		(1 << 21)
 #define  BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN	(1 << 20)
 #define  BM_SSP_CTRL1_RECV_TIMEOUT_IRQ		(1 << 17)
 #define  BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN	(1 << 16)
 #define  BM_SSP_CTRL1_FIFO_OVERRUN_IRQ		(1 << 15)
 #define  BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN	(1 << 14)
 #define  BM_SSP_CTRL1_DMA_ENABLE		(1 << 13)
 #define  BM_SSP_CTRL1_POLARITY			(1 << 9)
 #define  BP_SSP_CTRL1_WORD_LENGTH		(4)
 #define  BM_SSP_CTRL1_WORD_LENGTH		(0xf << 4)
 #define  BP_SSP_CTRL1_SSP_MODE			(0)
 #define  BM_SSP_CTRL1_SSP_MODE			(0xf)
 #define HW_SSP_SDRESP0(h)			(ssp_is_old(h) ? 0x080 : 0x0a0)
 #define HW_SSP_SDRESP1(h)			(ssp_is_old(h) ? 0x090 : 0x0b0)
 #define HW_SSP_SDRESP2(h)			(ssp_is_old(h) ? 0x0a0 : 0x0c0)
 #define HW_SSP_SDRESP3(h)			(ssp_is_old(h) ? 0x0b0 : 0x0d0)
 #define HW_SSP_STATUS(h)			(ssp_is_old(h) ? 0x0c0 : 0x100)
 #define  BM_SSP_STATUS_CARD_DETECT		(1 << 28)
 #define  BM_SSP_STATUS_SDIO_IRQ			(1 << 17)
 #define BF_SSP(value, field)	(((value) << BP_SSP_##field) & BM_SSP_##field)
 #define MXS_MMC_IRQ_BITS	(BM_SSP_CTRL1_SDIO_IRQ		| \
 				 BM_SSP_CTRL1_RESP_ERR_IRQ	| \
 				 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ	| \
 				 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ	| \
 				 BM_SSP_CTRL1_DATA_CRC_IRQ	| \
 				 BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ	| \
 				 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ  | \
 				 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)
 #define SSP_PIO_NUM	3
 enum mxs_mmc_id {
 	IMX23_MMC,
 	IMX28_MMC,
 };
 struct mxs_mmc_host {
 	struct mmc_host			*mmc;
 	struct mmc_request		*mrq;
 	struct mmc_command		*cmd;
 	struct mmc_data			*data;
 	void __iomem			*base;
 	int				dma_channel;
 	struct clk			*clk;
 	unsigned int			clk_rate;
 	struct dma_chan         	*dmach;
 	struct mxs_dma_data		dma_data;
 	unsigned int			dma_dir;
 	enum dma_transfer_direction	slave_dirn;
 	u32				ssp_pio_words[SSP_PIO_NUM];
 	enum mxs_mmc_id			devid;
 	unsigned char			bus_width;
 	spinlock_t			lock;
 	int				sdio_irq_en;
 	int				wp_gpio;
 	bool				wp_inverted;
 };
 static int mxs_mmc_get_ro(struct mmc_host *mmc)
 {
 	struct mxs_mmc_host *host = mmc_priv(mmc);
 	int ret;
 	if (!gpio_is_valid(host->wp_gpio))
 		return -EINVAL;
 	ret = gpio_get_value(host->wp_gpio);
 	if (host->wp_inverted)
 		ret = !ret;
 	return ret;
 }
 static int mxs_mmc_get_cd(struct mmc_host *mmc)
 {
 	struct mxs_mmc_host *host = mmc_priv(mmc);
 	return !(readl(host->base + HW_SSP_STATUS(host)) &
 		 BM_SSP_STATUS_CARD_DETECT);
 }
 static void mxs_mmc_reset(struct mxs_mmc_host *host)
 {
 	u32 ctrl0, ctrl1;
 	stmp_reset_block(host->base);
 	ctrl0 = BM_SSP_CTRL0_IGNORE_CRC;
 	ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) |
 		BF_SSP(0x7, CTRL1_WORD_LENGTH) |
 		BM_SSP_CTRL1_DMA_ENABLE |
 		BM_SSP_CTRL1_POLARITY |
 		BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
 		BM_SSP_CTRL1_DATA_CRC_IRQ_EN |
 		BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
 		BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
 		BM_SSP_CTRL1_RESP_ERR_IRQ_EN;
 	writel(BF_SSP(0xffff, TIMING_TIMEOUT) |
 	       BF_SSP(2, TIMING_CLOCK_DIVIDE) |
 	       BF_SSP(0, TIMING_CLOCK_RATE),
 	       host->base + HW_SSP_TIMING(host));
 	if (host->sdio_irq_en) {
 		ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
 		ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN;
 	}
 	writel(ctrl0, host->base + HW_SSP_CTRL0);
 	writel(ctrl1, host->base + HW_SSP_CTRL1(host));
 }
 static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
 			      struct mmc_command *cmd);
 static void mxs_mmc_request_done(struct mxs_mmc_host *host)
 {
 	struct mmc_command *cmd = host->cmd;
 	struct mmc_data *data = host->data;
 	struct mmc_request *mrq = host->mrq;
 	if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
 		if (mmc_resp_type(cmd) & MMC_RSP_136) {
 			cmd->resp[3] = readl(host->base + HW_SSP_SDRESP0(host));
 			cmd->resp[2] = readl(host->base + HW_SSP_SDRESP1(host));
 			cmd->resp[1] = readl(host->base + HW_SSP_SDRESP2(host));
 			cmd->resp[0] = readl(host->base + HW_SSP_SDRESP3(host));
 		} else {
 			cmd->resp[0] = readl(host->base + HW_SSP_SDRESP0(host));
 		}
 	}
 	if (data) {
 		dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 			     data->sg_len, host->dma_dir);
 		/*
 		 * If there was an error on any block, we mark all
 		 * data blocks as being in error.
 		 */
 		if (!data->error)
 			data->bytes_xfered = data->blocks * data->blksz;
 		else
 			data->bytes_xfered = 0;
 		host->data = NULL;
 		if (mrq->stop) {
 			mxs_mmc_start_cmd(host, mrq->stop);
 			return;
 		}
 	}
 	host->mrq = NULL;
 	mmc_request_done(host->mmc, mrq);
 }
 static void mxs_mmc_dma_irq_callback(void *param)
 {
 	struct mxs_mmc_host *host = param;
 	mxs_mmc_request_done(host);
 }
 static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id)
 {
 	struct mxs_mmc_host *host = dev_id;
 	struct mmc_command *cmd = host->cmd;
 	struct mmc_data *data = host->data;
 	u32 stat;
 	spin_lock(&host->lock);
 	stat = readl(host->base + HW_SSP_CTRL1(host));
 	writel(stat & MXS_MMC_IRQ_BITS,
 	       host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_CLR);
+	spin_unlock(&host->lock);
 	if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN))
 		mmc_signal_sdio_irq(host->mmc);
-	spin_unlock(&host->lock);
 	if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ)
 		cmd->error = -ETIMEDOUT;
 	else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ)
 		cmd->error = -EIO;
 	if (data) {
 		if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ |
 			    BM_SSP_CTRL1_RECV_TIMEOUT_IRQ))
 			data->error = -ETIMEDOUT;
 		else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ)
 			data->error = -EILSEQ;
 		else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ |
 				 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ))
 			data->error = -EIO;
 	}
 	return IRQ_HANDLED;
 }
 static struct dma_async_tx_descriptor *mxs_mmc_prep_dma(
 	struct mxs_mmc_host *host, unsigned long flags)
 {
 	struct dma_async_tx_descriptor *desc;
 	struct mmc_data *data = host->data;
 	struct scatterlist * sgl;
 	unsigned int sg_len;
 	if (data) {
 		/* data */
 		dma_map_sg(mmc_dev(host->mmc), data->sg,
 			   data->sg_len, host->dma_dir);
 		sgl = data->sg;
 		sg_len = data->sg_len;
 	} else {
 		/* pio */
 		sgl = (struct scatterlist *) host->ssp_pio_words;
 		sg_len = SSP_PIO_NUM;
 	}
 	desc = dmaengine_prep_slave_sg(host->dmach,
 				sgl, sg_len, host->slave_dirn, flags);
 	if (desc) {
 		desc->callback = mxs_mmc_dma_irq_callback;
 		desc->callback_param = host;
 	} else {
 		if (data)
 			dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 				     data->sg_len, host->dma_dir);
 	}
 	return desc;
 }
 static void mxs_mmc_bc(struct mxs_mmc_host *host)
 {
 	struct mmc_command *cmd = host->cmd;
 	struct dma_async_tx_descriptor *desc;
 	u32 ctrl0, cmd0, cmd1;
 	ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC;
 	cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC;
 	cmd1 = cmd->arg;
 	if (host->sdio_irq_en) {
 		ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
 		cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
 	}
 	host->ssp_pio_words[0] = ctrl0;
 	host->ssp_pio_words[1] = cmd0;
 	host->ssp_pio_words[2] = cmd1;
 	host->dma_dir = DMA_NONE;
 	host->slave_dirn = DMA_TRANS_NONE;
 	desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK);
 	if (!desc)
 		goto out;
 	dmaengine_submit(desc);
 	dma_async_issue_pending(host->dmach);
 	return;
 out:
 	dev_warn(mmc_dev(host->mmc),
 		 "%s: failed to prep dma\n", __func__);
 }
 static void mxs_mmc_ac(struct mxs_mmc_host *host)
 {
 	struct mmc_command *cmd = host->cmd;
 	struct dma_async_tx_descriptor *desc;
 	u32 ignore_crc, get_resp, long_resp;
 	u32 ctrl0, cmd0, cmd1;
 	ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
 			0 : BM_SSP_CTRL0_IGNORE_CRC;
 	get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
 			BM_SSP_CTRL0_GET_RESP : 0;
 	long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
 			BM_SSP_CTRL0_LONG_RESP : 0;
 	ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp;
 	cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
 	cmd1 = cmd->arg;
 	if (host->sdio_irq_en) {
 		ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
 		cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
 	}
 	host->ssp_pio_words[0] = ctrl0;
 	host->ssp_pio_words[1] = cmd0;
 	host->ssp_pio_words[2] = cmd1;
 	host->dma_dir = DMA_NONE;
 	host->slave_dirn = DMA_TRANS_NONE;
 	desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK);
 	if (!desc)
 		goto out;
 	dmaengine_submit(desc);
 	dma_async_issue_pending(host->dmach);
 	return;
 out:
 	dev_warn(mmc_dev(host->mmc),
 		 "%s: failed to prep dma\n", __func__);
 }
 static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns)
 {
 	const unsigned int ssp_timeout_mul = 4096;
 	/*
 	 * Calculate ticks in ms since ns are large numbers
 	 * and might overflow
 	 */
 	const unsigned int clock_per_ms = clock_rate / 1000;
 	const unsigned int ms = ns / 1000;
 	const unsigned int ticks = ms * clock_per_ms;
 	const unsigned int ssp_ticks = ticks / ssp_timeout_mul;
 	WARN_ON(ssp_ticks == 0);
 	return ssp_ticks;
 }
 static void mxs_mmc_adtc(struct mxs_mmc_host *host)
 {
 	struct mmc_command *cmd = host->cmd;
 	struct mmc_data *data = cmd->data;
 	struct dma_async_tx_descriptor *desc;
 	struct scatterlist *sgl = data->sg, *sg;
 	unsigned int sg_len = data->sg_len;
 	int i;
 	unsigned short dma_data_dir, timeout;
 	enum dma_transfer_direction slave_dirn;
 	unsigned int data_size = 0, log2_blksz;
 	unsigned int blocks = data->blocks;
 	u32 ignore_crc, get_resp, long_resp, read;
 	u32 ctrl0, cmd0, cmd1, val;
 	ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
 			0 : BM_SSP_CTRL0_IGNORE_CRC;
 	get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
 			BM_SSP_CTRL0_GET_RESP : 0;
 	long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
 			BM_SSP_CTRL0_LONG_RESP : 0;
 	if (data->flags & MMC_DATA_WRITE) {
 		dma_data_dir = DMA_TO_DEVICE;
 		slave_dirn = DMA_MEM_TO_DEV;
 		read = 0;
 	} else {
 		dma_data_dir = DMA_FROM_DEVICE;
 		slave_dirn = DMA_DEV_TO_MEM;
 		read = BM_SSP_CTRL0_READ;
 	}
 	ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) |
 		ignore_crc | get_resp | long_resp |
 		BM_SSP_CTRL0_DATA_XFER | read |
 		BM_SSP_CTRL0_WAIT_FOR_IRQ |
 		BM_SSP_CTRL0_ENABLE;
 	cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
 	/* get logarithm to base 2 of block size for setting register */
 	log2_blksz = ilog2(data->blksz);
 	/*
 	 * take special care of the case that data size from data->sg
 	 * is not equal to blocks x blksz
 	 */
 	for_each_sg(sgl, sg, sg_len, i)
 		data_size += sg->length;
 	if (data_size != data->blocks * data->blksz)
 		blocks = 1;
 	/* xfer count, block size and count need to be set differently */
 	if (ssp_is_old(host)) {
 		ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT);
 		cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) |
 			BF_SSP(blocks - 1, CMD0_BLOCK_COUNT);
 	} else {
 		writel(data_size, host->base + HW_SSP_XFER_SIZE);
 		writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) |
 		       BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT),
 		       host->base + HW_SSP_BLOCK_SIZE);
 	}
 	if ((cmd->opcode == MMC_STOP_TRANSMISSION) ||
 	    (cmd->opcode == SD_IO_RW_EXTENDED))
 		cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
 	cmd1 = cmd->arg;
 	if (host->sdio_irq_en) {
 		ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
 		cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
 	}
 	/* set the timeout count */
 	timeout = mxs_ns_to_ssp_ticks(host->clk_rate, data->timeout_ns);
 	val = readl(host->base + HW_SSP_TIMING(host));
 	val &= ~(BM_SSP_TIMING_TIMEOUT);
 	val |= BF_SSP(timeout, TIMING_TIMEOUT);
 	writel(val, host->base + HW_SSP_TIMING(host));
 	/* pio */
 	host->ssp_pio_words[0] = ctrl0;
 	host->ssp_pio_words[1] = cmd0;
 	host->ssp_pio_words[2] = cmd1;
 	host->dma_dir = DMA_NONE;
 	host->slave_dirn = DMA_TRANS_NONE;
 	desc = mxs_mmc_prep_dma(host, 0);
 	if (!desc)
 		goto out;
 	/* append data sg */
 	WARN_ON(host->data != NULL);
 	host->data = data;
 	host->dma_dir = dma_data_dir;
 	host->slave_dirn = slave_dirn;
 	desc = mxs_mmc_prep_dma(host, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 	if (!desc)
 		goto out;
 	dmaengine_submit(desc);
 	dma_async_issue_pending(host->dmach);
 	return;
 out:
 	dev_warn(mmc_dev(host->mmc),
 		 "%s: failed to prep dma\n", __func__);
 }
 static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
 			      struct mmc_command *cmd)
 {
 	host->cmd = cmd;
 	switch (mmc_cmd_type(cmd)) {
 	case MMC_CMD_BC:
 		mxs_mmc_bc(host);
 		break;
 	case MMC_CMD_BCR:
 		mxs_mmc_ac(host);
 		break;
 	case MMC_CMD_AC:
 		mxs_mmc_ac(host);
 		break;
 	case MMC_CMD_ADTC:
 		mxs_mmc_adtc(host);
 		break;
 	default:
 		dev_warn(mmc_dev(host->mmc),
 			 "%s: unknown MMC command\n", __func__);
 		break;
 	}
 }
 static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
 {
 	struct mxs_mmc_host *host = mmc_priv(mmc);
 	WARN_ON(host->mrq != NULL);
 	host->mrq = mrq;
 	mxs_mmc_start_cmd(host, mrq->cmd);
 }
 static void mxs_mmc_set_clk_rate(struct mxs_mmc_host *host, unsigned int rate)
 {
 	unsigned int ssp_clk, ssp_sck;
 	u32 clock_divide, clock_rate;
 	u32 val;
 	ssp_clk = clk_get_rate(host->clk);
 	for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) {
 		clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide);
 		clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0;
 		if (clock_rate <= 255)
 			break;
 	}
 	if (clock_divide > 254) {
 		dev_err(mmc_dev(host->mmc),
 			"%s: cannot set clock to %d\n", __func__, rate);
 		return;
 	}
 	ssp_sck = ssp_clk / clock_divide / (1 + clock_rate);
 	val = readl(host->base + HW_SSP_TIMING(host));
 	val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE);
 	val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE);
 	val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE);
 	writel(val, host->base + HW_SSP_TIMING(host));
 	host->clk_rate = ssp_sck;
 	dev_dbg(mmc_dev(host->mmc),
 		"%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n",
 		__func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate);
 }
 static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 {
 	struct mxs_mmc_host *host = mmc_priv(mmc);
 	if (ios->bus_width == MMC_BUS_WIDTH_8)
 		host->bus_width = 2;
 	else if (ios->bus_width == MMC_BUS_WIDTH_4)
 		host->bus_width = 1;
 	else
 		host->bus_width = 0;
 	if (ios->clock)
 		mxs_mmc_set_clk_rate(host, ios->clock);
 }
 static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
 {
 	struct mxs_mmc_host *host = mmc_priv(mmc);
 	unsigned long flags;
 	spin_lock_irqsave(&host->lock, flags);
 	host->sdio_irq_en = enable;
 	if (enable) {
 		writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
 		       host->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 		writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
 		       host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_SET);
-		if (readl(host->base + HW_SSP_STATUS(host)) &
-				BM_SSP_STATUS_SDIO_IRQ)
-			mmc_signal_sdio_irq(host->mmc);
 	} else {
 		writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
 		       host->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
 		writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
 		       host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_CLR);
 	}
 	spin_unlock_irqrestore(&host->lock, flags);
+	if (enable && readl(host->base + HW_SSP_STATUS(host)) &
+			BM_SSP_STATUS_SDIO_IRQ)
+		mmc_signal_sdio_irq(host->mmc);
 }
 static const struct mmc_host_ops mxs_mmc_ops = {
 	.request = mxs_mmc_request,
 	.get_ro = mxs_mmc_get_ro,
 	.get_cd = mxs_mmc_get_cd,
 	.set_ios = mxs_mmc_set_ios,
 	.enable_sdio_irq = mxs_mmc_enable_sdio_irq,
 };
 static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param)
 {
 	struct mxs_mmc_host *host = param;
 	if (!mxs_dma_is_apbh(chan))
 		return false;
 	if (chan->chan_id != host->dma_channel)
 		return false;
 	chan->private = &host->dma_data;
 	return true;
 }
 static struct platform_device_id mxs_mmc_ids[] = {
 	{
 		.name = "imx23-mmc",
 		.driver_data = IMX23_MMC,
 	}, {
 		.name = "imx28-mmc",
 		.driver_data = IMX28_MMC,
 	}, {
 		/* sentinel */
 	}
 };
 MODULE_DEVICE_TABLE(platform, mxs_mmc_ids);
 static const struct of_device_id mxs_mmc_dt_ids[] = {
 	{ .compatible = "fsl,imx23-mmc", .data = (void *) IMX23_MMC, },
 	{ .compatible = "fsl,imx28-mmc", .data = (void *) IMX28_MMC, },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, mxs_mmc_dt_ids);
 static int mxs_mmc_probe(struct platform_device *pdev)
 {
 	const struct of_device_id *of_id =
 			of_match_device(mxs_mmc_dt_ids, &pdev->dev);
 	struct device_node *np = pdev->dev.of_node;
 	struct mxs_mmc_host *host;
 	struct mmc_host *mmc;
 	struct resource *iores, *dmares;
 	struct mxs_mmc_platform_data *pdata;
 	struct pinctrl *pinctrl;
 	int ret = 0, irq_err, irq_dma;
 	dma_cap_mask_t mask;
 	struct regulator *reg_vmmc;
 	enum of_gpio_flags flags;
 	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
 	irq_err = platform_get_irq(pdev, 0);
 	irq_dma = platform_get_irq(pdev, 1);
 	if (!iores || irq_err < 0 || irq_dma < 0)
 		return -EINVAL;
 	mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev);
 	if (!mmc)
 		return -ENOMEM;
 	host = mmc_priv(mmc);
 	host->base = devm_request_and_ioremap(&pdev->dev, iores);
 	if (!host->base) {
 		ret = -EADDRNOTAVAIL;
 		goto out_mmc_free;
 	}
 	if (np) {
 		host->devid = (enum mxs_mmc_id) of_id->data;
 		/*
 		 * TODO: This is a temporary solution and should be changed
 		 * to use generic DMA binding later when the helpers get in.
 		 */
 		ret = of_property_read_u32(np, "fsl,ssp-dma-channel",
 					   &host->dma_channel);
 		if (ret) {
 			dev_err(mmc_dev(host->mmc),
 				"failed to get dma channel\n");
 			goto out_mmc_free;
 		}
 	} else {
 		host->devid = pdev->id_entry->driver_data;
 		host->dma_channel = dmares->start;
 	}
 	host->mmc = mmc;
 	host->sdio_irq_en = 0;
 	reg_vmmc = devm_regulator_get(&pdev->dev, "vmmc");
 	if (!IS_ERR(reg_vmmc)) {
 		ret = regulator_enable(reg_vmmc);
 		if (ret) {
 			dev_err(&pdev->dev,
 				"Failed to enable vmmc regulator: %d\n", ret);
 			goto out_mmc_free;
 		}
 	}
 	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
 	if (IS_ERR(pinctrl)) {
 		ret = PTR_ERR(pinctrl);
 		goto out_mmc_free;
 	}
 	host->clk = clk_get(&pdev->dev, NULL);
 	if (IS_ERR(host->clk)) {
 		ret = PTR_ERR(host->clk);
 		goto out_mmc_free;
 	}
 	clk_prepare_enable(host->clk);
 	mxs_mmc_reset(host);
 	dma_cap_zero(mask);
 	dma_cap_set(DMA_SLAVE, mask);
 	host->dma_data.chan_irq = irq_dma;
 	host->dmach = dma_request_channel(mask, mxs_mmc_dma_filter, host);
 	if (!host->dmach) {
 		dev_err(mmc_dev(host->mmc),
 			"%s: failed to request dma\n", __func__);
 		goto out_clk_put;
 	}
 	/* set mmc core parameters */
 	mmc->ops = &mxs_mmc_ops;
 	mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
 		    MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL;
 	pdata =	mmc_dev(host->mmc)->platform_data;
 	if (!pdata) {
 		u32 bus_width = 0;
 		of_property_read_u32(np, "bus-width", &bus_width);
 		if (bus_width == 4)
 			mmc->caps |= MMC_CAP_4_BIT_DATA;
 		else if (bus_width == 8)
 			mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
 		host->wp_gpio = of_get_named_gpio_flags(np, "wp-gpios", 0,
 							&flags);
 		if (flags & OF_GPIO_ACTIVE_LOW)
 			host->wp_inverted = 1;
 	} else {
 		if (pdata->flags & SLOTF_8_BIT_CAPABLE)
 			mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
 		if (pdata->flags & SLOTF_4_BIT_CAPABLE)
 			mmc->caps |= MMC_CAP_4_BIT_DATA;
 		host->wp_gpio = pdata->wp_gpio;
 	}
 	mmc->f_min = 400000;
 	mmc->f_max = 288000000;
 	mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
 	mmc->max_segs = 52;
 	mmc->max_blk_size = 1 << 0xf;
 	mmc->max_blk_count = (ssp_is_old(host)) ? 0xff : 0xffffff;
 	mmc->max_req_size = (ssp_is_old(host)) ? 0xffff : 0xffffffff;
 	mmc->max_seg_size = dma_get_max_seg_size(host->dmach->device->dev);
 	platform_set_drvdata(pdev, mmc);
 	ret = devm_request_irq(&pdev->dev, irq_err, mxs_mmc_irq_handler, 0,
 			       DRIVER_NAME, host);
 	if (ret)
 		goto out_free_dma;
 	spin_lock_init(&host->lock);
 	ret = mmc_add_host(mmc);
 	if (ret)
 		goto out_free_dma;
 	dev_info(mmc_dev(host->mmc), "initialized\n");
 	return 0;
 out_free_dma:
 	if (host->dmach)
 		dma_release_channel(host->dmach);
 out_clk_put:
 	clk_disable_unprepare(host->clk);
 	clk_put(host->clk);
 out_mmc_free:
 	mmc_free_host(mmc);
 	return ret;
 }
 static int mxs_mmc_remove(struct platform_device *pdev)
 {
 	struct mmc_host *mmc = platform_get_drvdata(pdev);
 	struct mxs_mmc_host *host = mmc_priv(mmc);
 	mmc_remove_host(mmc);
 	platform_set_drvdata(pdev, NULL);
 	if (host->dmach)
 		dma_release_channel(host->dmach);
 	clk_disable_unprepare(host->clk);
 	clk_put(host->clk);
 	mmc_free_host(mmc);
 	return 0;
 }
 #ifdef CONFIG_PM
 static int mxs_mmc_suspend(struct device *dev)
 {
 	struct mmc_host *mmc = dev_get_drvdata(dev);
 	struct mxs_mmc_host *host = mmc_priv(mmc);
 	int ret = 0;
 	ret = mmc_suspend_host(mmc);
 	clk_disable_unprepare(host->clk);
 	return ret;
 }
 static int mxs_mmc_resume(struct device *dev)
 {
 	struct mmc_host *mmc = dev_get_drvdata(dev);
 	struct mxs_mmc_host *host = mmc_priv(mmc);
 	int ret = 0;
 	clk_prepare_enable(host->clk);
 	ret = mmc_resume_host(mmc);
 	return ret;
 }
 static const struct dev_pm_ops mxs_mmc_pm_ops = {
 	.suspend	= mxs_mmc_suspend,
 	.resume		= mxs_mmc_resume,
 };
 #endif
 static struct platform_driver mxs_mmc_driver = {
 	.probe		= mxs_mmc_probe,
 	.remove		= mxs_mmc_remove,
 	.id_table	= mxs_mmc_ids,
 	.driver		= {
 		.name	= DRIVER_NAME,
 		.owner	= THIS_MODULE,
 #ifdef CONFIG_PM
 		.pm	= &mxs_mmc_pm_ops,
 #endif
 		.of_match_table = mxs_mmc_dt_ids,
 	},
 };

drivers/mmc/host/omap.c

Diff comments View file @ 0809095

 /*
  *  linux/drivers/mmc/host/omap.c
  *
  *  Copyright (C) 2004 Nokia Corporation
  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
  *  Other hacks (DMA, SD, etc) by David Brownell
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #include <linux/module.h>
 #include <linux/moduleparam.h>
 #include <linux/init.h>
 #include <linux/ioport.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/dmaengine.h>
 #include <linux/dma-mapping.h>
 #include <linux/delay.h>
 #include <linux/spinlock.h>
 #include <linux/timer.h>
 #include <linux/omap-dma.h>
 #include <linux/mmc/host.h>
 #include <linux/mmc/card.h>
 #include <linux/clk.h>
 #include <linux/scatterlist.h>
 #include <linux/i2c/tps65010.h>
 #include <linux/slab.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <plat/board.h>
 #include <plat/mmc.h>
 #include <asm/gpio.h>
 #include <plat/dma.h>
 #include <plat/mux.h>
 #include <plat/fpga.h>
 #define	OMAP_MMC_REG_CMD	0x00
 #define	OMAP_MMC_REG_ARGL	0x01
 #define	OMAP_MMC_REG_ARGH	0x02
 #define	OMAP_MMC_REG_CON	0x03
 #define	OMAP_MMC_REG_STAT	0x04
 #define	OMAP_MMC_REG_IE		0x05
 #define	OMAP_MMC_REG_CTO	0x06
 #define	OMAP_MMC_REG_DTO	0x07
 #define	OMAP_MMC_REG_DATA	0x08
 #define	OMAP_MMC_REG_BLEN	0x09
 #define	OMAP_MMC_REG_NBLK	0x0a
 #define	OMAP_MMC_REG_BUF	0x0b
 #define	OMAP_MMC_REG_SDIO	0x0d
 #define	OMAP_MMC_REG_REV	0x0f
 #define	OMAP_MMC_REG_RSP0	0x10
 #define	OMAP_MMC_REG_RSP1	0x11
 #define	OMAP_MMC_REG_RSP2	0x12
 #define	OMAP_MMC_REG_RSP3	0x13
 #define	OMAP_MMC_REG_RSP4	0x14
 #define	OMAP_MMC_REG_RSP5	0x15
 #define	OMAP_MMC_REG_RSP6	0x16
 #define	OMAP_MMC_REG_RSP7	0x17
 #define	OMAP_MMC_REG_IOSR	0x18
 #define	OMAP_MMC_REG_SYSC	0x19
 #define	OMAP_MMC_REG_SYSS	0x1a
 #define	OMAP_MMC_STAT_CARD_ERR		(1 << 14)
 #define	OMAP_MMC_STAT_CARD_IRQ		(1 << 13)
 #define	OMAP_MMC_STAT_OCR_BUSY		(1 << 12)
 #define	OMAP_MMC_STAT_A_EMPTY		(1 << 11)
 #define	OMAP_MMC_STAT_A_FULL		(1 << 10)
 #define	OMAP_MMC_STAT_CMD_CRC		(1 <<  8)
 #define	OMAP_MMC_STAT_CMD_TOUT		(1 <<  7)
 #define	OMAP_MMC_STAT_DATA_CRC		(1 <<  6)
 #define	OMAP_MMC_STAT_DATA_TOUT		(1 <<  5)
 #define	OMAP_MMC_STAT_END_BUSY		(1 <<  4)
 #define	OMAP_MMC_STAT_END_OF_DATA	(1 <<  3)
 #define	OMAP_MMC_STAT_CARD_BUSY		(1 <<  2)
 #define	OMAP_MMC_STAT_END_OF_CMD	(1 <<  0)
 #define OMAP_MMC_REG(host, reg)		(OMAP_MMC_REG_##reg << (host)->reg_shift)
 #define OMAP_MMC_READ(host, reg)	__raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
 #define OMAP_MMC_WRITE(host, reg, val)	__raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
 /*
  * Command types
  */
 #define OMAP_MMC_CMDTYPE_BC	0
 #define OMAP_MMC_CMDTYPE_BCR	1
 #define OMAP_MMC_CMDTYPE_AC	2
 #define OMAP_MMC_CMDTYPE_ADTC	3
 #define DRIVER_NAME "mmci-omap"
 /* Specifies how often in millisecs to poll for card status changes
  * when the cover switch is open */
 #define OMAP_MMC_COVER_POLL_DELAY	500
 struct mmc_omap_host;
 struct mmc_omap_slot {
 	int			id;
 	unsigned int		vdd;
 	u16			saved_con;
 	u16			bus_mode;
 	unsigned int		fclk_freq;
 	unsigned		powered:1;
 	struct tasklet_struct	cover_tasklet;
 	struct timer_list       cover_timer;
 	unsigned		cover_open;
 	struct mmc_request      *mrq;
 	struct mmc_omap_host    *host;
 	struct mmc_host		*mmc;
 	struct omap_mmc_slot_data *pdata;
 };
 struct mmc_omap_host {
 	int			initialized;
 	int			suspended;
 	struct mmc_request *	mrq;
 	struct mmc_command *	cmd;
 	struct mmc_data *	data;
 	struct mmc_host *	mmc;
 	struct device *		dev;
 	unsigned char		id; /* 16xx chips have 2 MMC blocks */
 	struct clk *		iclk;
 	struct clk *		fclk;
 	struct dma_chan		*dma_rx;
 	u32			dma_rx_burst;
 	struct dma_chan		*dma_tx;
 	u32			dma_tx_burst;
 	struct resource		*mem_res;
 	void __iomem		*virt_base;
 	unsigned int		phys_base;
 	int			irq;
 	unsigned char		bus_mode;
 	unsigned char		hw_bus_mode;
 	unsigned int		reg_shift;
 	struct work_struct	cmd_abort_work;
 	unsigned		abort:1;
 	struct timer_list	cmd_abort_timer;
 	struct work_struct      slot_release_work;
 	struct mmc_omap_slot    *next_slot;
 	struct work_struct      send_stop_work;
 	struct mmc_data		*stop_data;
 	unsigned int		sg_len;
 	int			sg_idx;
 	u16 *			buffer;
 	u32			buffer_bytes_left;
 	u32			total_bytes_left;
 	unsigned		use_dma:1;
 	unsigned		brs_received:1, dma_done:1;
 	unsigned		dma_in_use:1;
 	spinlock_t		dma_lock;
 	struct mmc_omap_slot    *slots[OMAP_MMC_MAX_SLOTS];
 	struct mmc_omap_slot    *current_slot;
 	spinlock_t              slot_lock;
 	wait_queue_head_t       slot_wq;
 	int                     nr_slots;
 	struct timer_list       clk_timer;
 	spinlock_t		clk_lock;     /* for changing enabled state */
 	unsigned int            fclk_enabled:1;
 	struct workqueue_struct *mmc_omap_wq;
 	struct omap_mmc_platform_data *pdata;
 };
 static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
 {
 	unsigned long tick_ns;
 	if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
 		tick_ns = (1000000000 + slot->fclk_freq - 1) / slot->fclk_freq;
 		ndelay(8 * tick_ns);
 	}
 }
 static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
 {
 	unsigned long flags;
 	spin_lock_irqsave(&host->clk_lock, flags);
 	if (host->fclk_enabled != enable) {
 		host->fclk_enabled = enable;
 		if (enable)
 			clk_enable(host->fclk);
 		else
 			clk_disable(host->fclk);
 	}
 	spin_unlock_irqrestore(&host->clk_lock, flags);
 }
 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
 {
 	struct mmc_omap_host *host = slot->host;
 	unsigned long flags;
 	if (claimed)
 		goto no_claim;
 	spin_lock_irqsave(&host->slot_lock, flags);
 	while (host->mmc != NULL) {
 		spin_unlock_irqrestore(&host->slot_lock, flags);
 		wait_event(host->slot_wq, host->mmc == NULL);
 		spin_lock_irqsave(&host->slot_lock, flags);
 	}
 	host->mmc = slot->mmc;
 	spin_unlock_irqrestore(&host->slot_lock, flags);
 no_claim:
 	del_timer(&host->clk_timer);
 	if (host->current_slot != slot || !claimed)
 		mmc_omap_fclk_offdelay(host->current_slot);
 	if (host->current_slot != slot) {
 		OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
 		if (host->pdata->switch_slot != NULL)
 			host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
 		host->current_slot = slot;
 	}
 	if (claimed) {
 		mmc_omap_fclk_enable(host, 1);
 		/* Doing the dummy read here seems to work around some bug
 		 * at least in OMAP24xx silicon where the command would not
 		 * start after writing the CMD register. Sigh. */
 		OMAP_MMC_READ(host, CON);
 		OMAP_MMC_WRITE(host, CON, slot->saved_con);
 	} else
 		mmc_omap_fclk_enable(host, 0);
 }
 static void mmc_omap_start_request(struct mmc_omap_host *host,
 				   struct mmc_request *req);
 static void mmc_omap_slot_release_work(struct work_struct *work)
 {
 	struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 						  slot_release_work);
 	struct mmc_omap_slot *next_slot = host->next_slot;
 	struct mmc_request *rq;
 	host->next_slot = NULL;
 	mmc_omap_select_slot(next_slot, 1);
 	rq = next_slot->mrq;
 	next_slot->mrq = NULL;
 	mmc_omap_start_request(host, rq);
 }
 static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
 {
 	struct mmc_omap_host *host = slot->host;
 	unsigned long flags;
 	int i;
 	BUG_ON(slot == NULL || host->mmc == NULL);
 	if (clk_enabled)
 		/* Keeps clock running for at least 8 cycles on valid freq */
 		mod_timer(&host->clk_timer, jiffies  + HZ/10);
 	else {
 		del_timer(&host->clk_timer);
 		mmc_omap_fclk_offdelay(slot);
 		mmc_omap_fclk_enable(host, 0);
 	}
 	spin_lock_irqsave(&host->slot_lock, flags);
 	/* Check for any pending requests */
 	for (i = 0; i < host->nr_slots; i++) {
 		struct mmc_omap_slot *new_slot;
 		if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
 			continue;
 		BUG_ON(host->next_slot != NULL);
 		new_slot = host->slots[i];
 		/* The current slot should not have a request in queue */
 		BUG_ON(new_slot == host->current_slot);
 		host->next_slot = new_slot;
 		host->mmc = new_slot->mmc;
 		spin_unlock_irqrestore(&host->slot_lock, flags);
 		queue_work(host->mmc_omap_wq, &host->slot_release_work);
 		return;
 	}
 	host->mmc = NULL;
 	wake_up(&host->slot_wq);
 	spin_unlock_irqrestore(&host->slot_lock, flags);
 }
 static inline
 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
 {
 	if (slot->pdata->get_cover_state)
 		return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
 						    slot->id);
 	return 0;
 }
 static ssize_t
 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 			   char *buf)
 {
 	struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 	struct mmc_omap_slot *slot = mmc_priv(mmc);
 	return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
 		       "closed");
 }
 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 static ssize_t
 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 			char *buf)
 {
 	struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 	struct mmc_omap_slot *slot = mmc_priv(mmc);
 	return sprintf(buf, "%s\n", slot->pdata->name);
 }
 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 static void
 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 {
 	u32 cmdreg;
 	u32 resptype;
 	u32 cmdtype;
 	host->cmd = cmd;
 	resptype = 0;
 	cmdtype = 0;
 	/* Our hardware needs to know exact type */
 	switch (mmc_resp_type(cmd)) {
 	case MMC_RSP_NONE:
 		break;
 	case MMC_RSP_R1:
 	case MMC_RSP_R1B:
 		/* resp 1, 1b, 6, 7 */
 		resptype = 1;
 		break;
 	case MMC_RSP_R2:
 		resptype = 2;
 		break;
 	case MMC_RSP_R3:
 		resptype = 3;
 		break;
 	default:
 		dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
 		break;
 	}
 	if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 		cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 	} else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 		cmdtype = OMAP_MMC_CMDTYPE_BC;
 	} else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 		cmdtype = OMAP_MMC_CMDTYPE_BCR;
 	} else {
 		cmdtype = OMAP_MMC_CMDTYPE_AC;
 	}
 	cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 	if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
 		cmdreg |= 1 << 6;
 	if (cmd->flags & MMC_RSP_BUSY)
 		cmdreg |= 1 << 11;
 	if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 		cmdreg |= 1 << 15;
 	mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
 	OMAP_MMC_WRITE(host, CTO, 200);
 	OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 	OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 	OMAP_MMC_WRITE(host, IE,
 		       OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 		       OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 		       OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 		       OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 		       OMAP_MMC_STAT_END_OF_DATA);
 	OMAP_MMC_WRITE(host, CMD, cmdreg);
 }
 static void
 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
 		     int abort)
 {
 	enum dma_data_direction dma_data_dir;
 	struct device *dev = mmc_dev(host->mmc);
 	struct dma_chan *c;
 	if (data->flags & MMC_DATA_WRITE) {
 		dma_data_dir = DMA_TO_DEVICE;
 		c = host->dma_tx;
 	} else {
 		dma_data_dir = DMA_FROM_DEVICE;
 		c = host->dma_rx;
 	}
 	if (c) {
 		if (data->error) {
 			dmaengine_terminate_all(c);
 			/* Claim nothing transferred on error... */
 			data->bytes_xfered = 0;
 		}
 		dev = c->device->dev;
 	}
 	dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir);
 }
 static void mmc_omap_send_stop_work(struct work_struct *work)
 {
 	struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 						  send_stop_work);
 	struct mmc_omap_slot *slot = host->current_slot;
 	struct mmc_data *data = host->stop_data;
 	unsigned long tick_ns;
 	tick_ns = (1000000000 + slot->fclk_freq - 1)/slot->fclk_freq;
 	ndelay(8*tick_ns);
 	mmc_omap_start_command(host, data->stop);
 }
 static void
 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 {
 	if (host->dma_in_use)
 		mmc_omap_release_dma(host, data, data->error);
 	host->data = NULL;
 	host->sg_len = 0;
 	/* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 	 * dozens of requests until the card finishes writing data.
 	 * It'd be cheaper to just wait till an EOFB interrupt arrives...
 	 */
 	if (!data->stop) {
 		struct mmc_host *mmc;
 		host->mrq = NULL;
 		mmc = host->mmc;
 		mmc_omap_release_slot(host->current_slot, 1);
 		mmc_request_done(mmc, data->mrq);
 		return;
 	}
 	host->stop_data = data;
 	queue_work(host->mmc_omap_wq, &host->send_stop_work);
 }
 static void
 mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
 {
 	struct mmc_omap_slot *slot = host->current_slot;
 	unsigned int restarts, passes, timeout;
 	u16 stat = 0;
 	/* Sending abort takes 80 clocks. Have some extra and round up */
 	timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq;
 	restarts = 0;
 	while (restarts < maxloops) {
 		OMAP_MMC_WRITE(host, STAT, 0xFFFF);
 		OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
 		passes = 0;
 		while (passes < timeout) {
 			stat = OMAP_MMC_READ(host, STAT);
 			if (stat & OMAP_MMC_STAT_END_OF_CMD)
 				goto out;
 			udelay(1);
 			passes++;
 		}
 		restarts++;
 	}
 out:
 	OMAP_MMC_WRITE(host, STAT, stat);
 }
 static void
 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
 {
 	if (host->dma_in_use)
 		mmc_omap_release_dma(host, data, 1);
 	host->data = NULL;
 	host->sg_len = 0;
 	mmc_omap_send_abort(host, 10000);
 }
 static void
 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 {
 	unsigned long flags;
 	int done;
 	if (!host->dma_in_use) {
 		mmc_omap_xfer_done(host, data);
 		return;
 	}
 	done = 0;
 	spin_lock_irqsave(&host->dma_lock, flags);
 	if (host->dma_done)
 		done = 1;
 	else
 		host->brs_received = 1;
 	spin_unlock_irqrestore(&host->dma_lock, flags);
 	if (done)
 		mmc_omap_xfer_done(host, data);
 }
 static void
 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 {
 	unsigned long flags;
 	int done;
 	done = 0;
 	spin_lock_irqsave(&host->dma_lock, flags);
 	if (host->brs_received)
 		done = 1;
 	else
 		host->dma_done = 1;
 	spin_unlock_irqrestore(&host->dma_lock, flags);
 	if (done)
 		mmc_omap_xfer_done(host, data);
 }
 static void
 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 {
 	host->cmd = NULL;
 	del_timer(&host->cmd_abort_timer);
 	if (cmd->flags & MMC_RSP_PRESENT) {
 		if (cmd->flags & MMC_RSP_136) {
 			/* response type 2 */
 			cmd->resp[3] =
 				OMAP_MMC_READ(host, RSP0) |
 				(OMAP_MMC_READ(host, RSP1) << 16);
 			cmd->resp[2] =
 				OMAP_MMC_READ(host, RSP2) |
 				(OMAP_MMC_READ(host, RSP3) << 16);
 			cmd->resp[1] =
 				OMAP_MMC_READ(host, RSP4) |
 				(OMAP_MMC_READ(host, RSP5) << 16);
 			cmd->resp[0] =
 				OMAP_MMC_READ(host, RSP6) |
 				(OMAP_MMC_READ(host, RSP7) << 16);
 		} else {
 			/* response types 1, 1b, 3, 4, 5, 6 */
 			cmd->resp[0] =
 				OMAP_MMC_READ(host, RSP6) |
 				(OMAP_MMC_READ(host, RSP7) << 16);
 		}
 	}
 	if (host->data == NULL || cmd->error) {
 		struct mmc_host *mmc;
 		if (host->data != NULL)
 			mmc_omap_abort_xfer(host, host->data);
 		host->mrq = NULL;
 		mmc = host->mmc;
 		mmc_omap_release_slot(host->current_slot, 1);
 		mmc_request_done(mmc, cmd->mrq);
 	}
 }
 /*
  * Abort stuck command. Can occur when card is removed while it is being
  * read.
  */
 static void mmc_omap_abort_command(struct work_struct *work)
 {
 	struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 						  cmd_abort_work);
 	BUG_ON(!host->cmd);
 	dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
 		host->cmd->opcode);
 	if (host->cmd->error == 0)
 		host->cmd->error = -ETIMEDOUT;
 	if (host->data == NULL) {
 		struct mmc_command *cmd;
 		struct mmc_host    *mmc;
 		cmd = host->cmd;
 		host->cmd = NULL;
 		mmc_omap_send_abort(host, 10000);
 		host->mrq = NULL;
 		mmc = host->mmc;
 		mmc_omap_release_slot(host->current_slot, 1);
 		mmc_request_done(mmc, cmd->mrq);
 	} else
 		mmc_omap_cmd_done(host, host->cmd);
 	host->abort = 0;
 	enable_irq(host->irq);
 }
 static void
 mmc_omap_cmd_timer(unsigned long data)
 {
 	struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 	unsigned long flags;
 	spin_lock_irqsave(&host->slot_lock, flags);
 	if (host->cmd != NULL && !host->abort) {
 		OMAP_MMC_WRITE(host, IE, 0);
 		disable_irq(host->irq);
 		host->abort = 1;
 		queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
 	}
 	spin_unlock_irqrestore(&host->slot_lock, flags);
 }
 /* PIO only */
 static void
 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 {
 	struct scatterlist *sg;
 	sg = host->data->sg + host->sg_idx;
 	host->buffer_bytes_left = sg->length;
 	host->buffer = sg_virt(sg);
 	if (host->buffer_bytes_left > host->total_bytes_left)
 		host->buffer_bytes_left = host->total_bytes_left;
 }
 static void
 mmc_omap_clk_timer(unsigned long data)
 {
 	struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 	mmc_omap_fclk_enable(host, 0);
 }
 /* PIO only */
 static void
 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 {
-	int n;
+	int n, nwords;
 	if (host->buffer_bytes_left == 0) {
 		host->sg_idx++;
 		BUG_ON(host->sg_idx == host->sg_len);
 		mmc_omap_sg_to_buf(host);
 	}
 	n = 64;
 	if (n > host->buffer_bytes_left)
 		n = host->buffer_bytes_left;
+	nwords = n / 2;
+	nwords += n & 1; /* handle odd number of bytes to transfer */
 	host->buffer_bytes_left -= n;
 	host->total_bytes_left -= n;
 	host->data->bytes_xfered += n;
 	if (write) {
-		__raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA), host->buffer, n);
+		__raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),
+			      host->buffer, nwords);
 	} else {
-		__raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA), host->buffer, n);
+		__raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),
+			     host->buffer, nwords);
 	}
+	host->buffer += nwords;
 }
 static inline void mmc_omap_report_irq(u16 status)
 {
 	static const char *mmc_omap_status_bits[] = {
 		"EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 		"CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 	};
 	int i, c = 0;
 	for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 		if (status & (1 << i)) {
 			if (c)
 				printk(" ");
 			printk("%s", mmc_omap_status_bits[i]);
 			c++;
 		}
 }
 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 {
 	struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 	u16 status;
 	int end_command;
 	int end_transfer;
 	int transfer_error, cmd_error;
 	if (host->cmd == NULL && host->data == NULL) {
 		status = OMAP_MMC_READ(host, STAT);
 		dev_info(mmc_dev(host->slots[0]->mmc),
 			 "Spurious IRQ 0x%04x\n", status);
 		if (status != 0) {
 			OMAP_MMC_WRITE(host, STAT, status);
 			OMAP_MMC_WRITE(host, IE, 0);
 		}
 		return IRQ_HANDLED;
 	}
 	end_command = 0;
 	end_transfer = 0;
 	transfer_error = 0;
 	cmd_error = 0;
 	while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 		int cmd;
 		OMAP_MMC_WRITE(host, STAT, status);
 		if (host->cmd != NULL)
 			cmd = host->cmd->opcode;
 		else
 			cmd = -1;
 #ifdef CONFIG_MMC_DEBUG
 		dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 			status, cmd);
 		mmc_omap_report_irq(status);
 		printk("\n");
 #endif
 		if (host->total_bytes_left) {
 			if ((status & OMAP_MMC_STAT_A_FULL) ||
 			    (status & OMAP_MMC_STAT_END_OF_DATA))
 				mmc_omap_xfer_data(host, 0);
 			if (status & OMAP_MMC_STAT_A_EMPTY)
 				mmc_omap_xfer_data(host, 1);
 		}
 		if (status & OMAP_MMC_STAT_END_OF_DATA)
 			end_transfer = 1;
 		if (status & OMAP_MMC_STAT_DATA_TOUT) {
 			dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
 				cmd);
 			if (host->data) {
 				host->data->error = -ETIMEDOUT;
 				transfer_error = 1;
 			}
 		}
 		if (status & OMAP_MMC_STAT_DATA_CRC) {
 			if (host->data) {
 				host->data->error = -EILSEQ;
 				dev_dbg(mmc_dev(host->mmc),
 					 "data CRC error, bytes left %d\n",
 					host->total_bytes_left);
 				transfer_error = 1;
 			} else {
 				dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 			}
 		}
 		if (status & OMAP_MMC_STAT_CMD_TOUT) {
 			/* Timeouts are routine with some commands */
 			if (host->cmd) {
 				struct mmc_omap_slot *slot =
 					host->current_slot;
 				if (slot == NULL ||
 				    !mmc_omap_cover_is_open(slot))
 					dev_err(mmc_dev(host->mmc),
 						"command timeout (CMD%d)\n",
 						cmd);
 				host->cmd->error = -ETIMEDOUT;
 				end_command = 1;
 				cmd_error = 1;
 			}
 		}
 		if (status & OMAP_MMC_STAT_CMD_CRC) {
 			if (host->cmd) {
 				dev_err(mmc_dev(host->mmc),
 					"command CRC error (CMD%d, arg 0x%08x)\n",
 					cmd, host->cmd->arg);
 				host->cmd->error = -EILSEQ;
 				end_command = 1;
 				cmd_error = 1;
 			} else
 				dev_err(mmc_dev(host->mmc),
 					"command CRC error without cmd?\n");
 		}
 		if (status & OMAP_MMC_STAT_CARD_ERR) {
 			dev_dbg(mmc_dev(host->mmc),
 				"ignoring card status error (CMD%d)\n",
 				cmd);
 			end_command = 1;
 		}
 		/*
 		 * NOTE: On 1610 the END_OF_CMD may come too early when
 		 * starting a write
 		 */
 		if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 		    (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 			end_command = 1;
 		}
 	}
 	if (cmd_error && host->data) {
 		del_timer(&host->cmd_abort_timer);
 		host->abort = 1;
 		OMAP_MMC_WRITE(host, IE, 0);
 		disable_irq_nosync(host->irq);
 		queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
 		return IRQ_HANDLED;
 	}
 	if (end_command && host->cmd)
 		mmc_omap_cmd_done(host, host->cmd);
 	if (host->data != NULL) {
 		if (transfer_error)
 			mmc_omap_xfer_done(host, host->data);
 		else if (end_transfer)
 			mmc_omap_end_of_data(host, host->data);
 	}
 	return IRQ_HANDLED;
 }
 void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
 {
 	int cover_open;
 	struct mmc_omap_host *host = dev_get_drvdata(dev);
 	struct mmc_omap_slot *slot = host->slots[num];
 	BUG_ON(num >= host->nr_slots);
 	/* Other subsystems can call in here before we're initialised. */
 	if (host->nr_slots == 0 || !host->slots[num])
 		return;
 	cover_open = mmc_omap_cover_is_open(slot);
 	if (cover_open != slot->cover_open) {
 		slot->cover_open = cover_open;
 		sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
 	}
 	tasklet_hi_schedule(&slot->cover_tasklet);
 }
 static void mmc_omap_cover_timer(unsigned long arg)
 {
 	struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
 	tasklet_schedule(&slot->cover_tasklet);
 }
 static void mmc_omap_cover_handler(unsigned long param)
 {
 	struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
 	int cover_open = mmc_omap_cover_is_open(slot);
 	mmc_detect_change(slot->mmc, 0);
 	if (!cover_open)
 		return;
 	/*
 	 * If no card is inserted, we postpone polling until
 	 * the cover has been closed.
 	 */
 	if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card))
 		return;
 	mod_timer(&slot->cover_timer,
 		  jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
 }
 static void mmc_omap_dma_callback(void *priv)
 {
 	struct mmc_omap_host *host = priv;
 	struct mmc_data *data = host->data;
 	/* If we got to the end of DMA, assume everything went well */
 	data->bytes_xfered += data->blocks * data->blksz;
 	mmc_omap_dma_done(host, data);
 }
 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 {
 	u16 reg;
 	reg = OMAP_MMC_READ(host, SDIO);
 	reg &= ~(1 << 5);
 	OMAP_MMC_WRITE(host, SDIO, reg);
 	/* Set maximum timeout */
 	OMAP_MMC_WRITE(host, CTO, 0xff);
 }
 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 {
 	unsigned int timeout, cycle_ns;
 	u16 reg;
 	cycle_ns = 1000000000 / host->current_slot->fclk_freq;
 	timeout = req->data->timeout_ns / cycle_ns;
 	timeout += req->data->timeout_clks;
 	/* Check if we need to use timeout multiplier register */
 	reg = OMAP_MMC_READ(host, SDIO);
 	if (timeout > 0xffff) {
 		reg |= (1 << 5);
 		timeout /= 1024;
 	} else
 		reg &= ~(1 << 5);
 	OMAP_MMC_WRITE(host, SDIO, reg);
 	OMAP_MMC_WRITE(host, DTO, timeout);
 }
 static void
 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 {
 	struct mmc_data *data = req->data;
 	int i, use_dma, block_size;
 	unsigned sg_len;
 	host->data = data;
 	if (data == NULL) {
 		OMAP_MMC_WRITE(host, BLEN, 0);
 		OMAP_MMC_WRITE(host, NBLK, 0);
 		OMAP_MMC_WRITE(host, BUF, 0);
 		host->dma_in_use = 0;
 		set_cmd_timeout(host, req);
 		return;
 	}
 	block_size = data->blksz;
 	OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
 	OMAP_MMC_WRITE(host, BLEN, block_size - 1);
 	set_data_timeout(host, req);
 	/* cope with calling layer confusion; it issues "single
 	 * block" writes using multi-block scatterlists.
 	 */
 	sg_len = (data->blocks == 1) ? 1 : data->sg_len;
 	/* Only do DMA for entire blocks */
 	use_dma = host->use_dma;
 	if (use_dma) {
 		for (i = 0; i < sg_len; i++) {
 			if ((data->sg[i].length % block_size) != 0) {
 				use_dma = 0;
 				break;
 			}
 		}
 	}
 	host->sg_idx = 0;
 	if (use_dma) {
 		enum dma_data_direction dma_data_dir;
 		struct dma_async_tx_descriptor *tx;
 		struct dma_chan *c;
 		u32 burst, *bp;
 		u16 buf;
 		/*
 		 * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx
 		 * and 24xx. Use 16 or 32 word frames when the
 		 * blocksize is at least that large. Blocksize is
 		 * usually 512 bytes; but not for some SD reads.
 		 */
 		burst = cpu_is_omap15xx() ? 32 : 64;
 		if (burst > data->blksz)
 			burst = data->blksz;
 		burst >>= 1;
 		if (data->flags & MMC_DATA_WRITE) {
 			c = host->dma_tx;
 			bp = &host->dma_tx_burst;
 			buf = 0x0f80 | (burst - 1) << 0;
 			dma_data_dir = DMA_TO_DEVICE;
 		} else {
 			c = host->dma_rx;
 			bp = &host->dma_rx_burst;
 			buf = 0x800f | (burst - 1) << 8;
 			dma_data_dir = DMA_FROM_DEVICE;
 		}
 		if (!c)
 			goto use_pio;
 		/* Only reconfigure if we have a different burst size */
 		if (*bp != burst) {
 			struct dma_slave_config cfg;
 			cfg.src_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
 			cfg.dst_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
 			cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 			cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 			cfg.src_maxburst = burst;
 			cfg.dst_maxburst = burst;
 			if (dmaengine_slave_config(c, &cfg))
 				goto use_pio;
 			*bp = burst;
 		}
 		host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len,
 					  dma_data_dir);
 		if (host->sg_len == 0)
 			goto use_pio;
 		tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len,
 			data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
 			DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 		if (!tx)
 			goto use_pio;
 		OMAP_MMC_WRITE(host, BUF, buf);
 		tx->callback = mmc_omap_dma_callback;
 		tx->callback_param = host;
 		dmaengine_submit(tx);
 		host->brs_received = 0;
 		host->dma_done = 0;
 		host->dma_in_use = 1;
 		return;
 	}
  use_pio:
 	/* Revert to PIO? */
 	OMAP_MMC_WRITE(host, BUF, 0x1f1f);
 	host->total_bytes_left = data->blocks * block_size;
 	host->sg_len = sg_len;
 	mmc_omap_sg_to_buf(host);
 	host->dma_in_use = 0;
 }
 static void mmc_omap_start_request(struct mmc_omap_host *host,
 				   struct mmc_request *req)
 {
 	BUG_ON(host->mrq != NULL);
 	host->mrq = req;
 	/* only touch fifo AFTER the controller readies it */
 	mmc_omap_prepare_data(host, req);
 	mmc_omap_start_command(host, req->cmd);
 	if (host->dma_in_use) {
 		struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ?
 				host->dma_tx : host->dma_rx;
 		dma_async_issue_pending(c);
 	}
 }
 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
 {
 	struct mmc_omap_slot *slot = mmc_priv(mmc);
 	struct mmc_omap_host *host = slot->host;
 	unsigned long flags;
 	spin_lock_irqsave(&host->slot_lock, flags);
 	if (host->mmc != NULL) {
 		BUG_ON(slot->mrq != NULL);
 		slot->mrq = req;
 		spin_unlock_irqrestore(&host->slot_lock, flags);
 		return;
 	} else
 		host->mmc = mmc;
 	spin_unlock_irqrestore(&host->slot_lock, flags);
 	mmc_omap_select_slot(slot, 1);
 	mmc_omap_start_request(host, req);
 }
 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
 				int vdd)
 {
 	struct mmc_omap_host *host;
 	host = slot->host;
 	if (slot->pdata->set_power != NULL)
 		slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
 					vdd);
 	if (cpu_is_omap24xx()) {
 		u16 w;
 		if (power_on) {
 			w = OMAP_MMC_READ(host, CON);
 			OMAP_MMC_WRITE(host, CON, w | (1 << 11));
 		} else {
 			w = OMAP_MMC_READ(host, CON);
 			OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
 		}
 	}
 }
 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
 {
 	struct mmc_omap_slot *slot = mmc_priv(mmc);
 	struct mmc_omap_host *host = slot->host;
 	int func_clk_rate = clk_get_rate(host->fclk);
 	int dsor;
 	if (ios->clock == 0)
 		return 0;
 	dsor = func_clk_rate / ios->clock;
 	if (dsor < 1)
 		dsor = 1;
 	if (func_clk_rate / dsor > ios->clock)
 		dsor++;
 	if (dsor > 250)
 		dsor = 250;
 	slot->fclk_freq = func_clk_rate / dsor;
 	if (ios->bus_width == MMC_BUS_WIDTH_4)
 		dsor |= 1 << 15;
 	return dsor;
 }
 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 {
 	struct mmc_omap_slot *slot = mmc_priv(mmc);
 	struct mmc_omap_host *host = slot->host;
 	int i, dsor;
 	int clk_enabled;
 	mmc_omap_select_slot(slot, 0);
 	dsor = mmc_omap_calc_divisor(mmc, ios);
 	if (ios->vdd != slot->vdd)
 		slot->vdd = ios->vdd;
 	clk_enabled = 0;
 	switch (ios->power_mode) {
 	case MMC_POWER_OFF:
 		mmc_omap_set_power(slot, 0, ios->vdd);
 		break;
 	case MMC_POWER_UP:
 		/* Cannot touch dsor yet, just power up MMC */
 		mmc_omap_set_power(slot, 1, ios->vdd);
 		goto exit;
 	case MMC_POWER_ON:
 		mmc_omap_fclk_enable(host, 1);
 		clk_enabled = 1;
 		dsor |= 1 << 11;
 		break;
 	}
 	if (slot->bus_mode != ios->bus_mode) {
 		if (slot->pdata->set_bus_mode != NULL)
 			slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
 						  ios->bus_mode);
 		slot->bus_mode = ios->bus_mode;
 	}
 	/* On insanely high arm_per frequencies something sometimes
 	 * goes somehow out of sync, and the POW bit is not being set,
 	 * which results in the while loop below getting stuck.
 	 * Writing to the CON register twice seems to do the trick. */
 	for (i = 0; i < 2; i++)
 		OMAP_MMC_WRITE(host, CON, dsor);
 	slot->saved_con = dsor;
 	if (ios->power_mode == MMC_POWER_ON) {
 		/* worst case at 400kHz, 80 cycles makes 200 microsecs */
 		int usecs = 250;
 		/* Send clock cycles, poll completion */
 		OMAP_MMC_WRITE(host, IE, 0);
 		OMAP_MMC_WRITE(host, STAT, 0xffff);
 		OMAP_MMC_WRITE(host, CMD, 1 << 7);
 		while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
 			udelay(1);
 			usecs--;
 		}
 		OMAP_MMC_WRITE(host, STAT, 1);
 	}
 exit:
 	mmc_omap_release_slot(slot, clk_enabled);
 }
 static const struct mmc_host_ops mmc_omap_ops = {
 	.request	= mmc_omap_request,
 	.set_ios	= mmc_omap_set_ios,
 };
 static int __devinit mmc_omap_new_slot(struct mmc_omap_host *host, int id)
 {
 	struct mmc_omap_slot *slot = NULL;
 	struct mmc_host *mmc;
 	int r;
 	mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
 	if (mmc == NULL)
 		return -ENOMEM;
 	slot = mmc_priv(mmc);
 	slot->host = host;
 	slot->mmc = mmc;
 	slot->id = id;
 	slot->pdata = &host->pdata->slots[id];
 	host->slots[id] = slot;
 	mmc->caps = 0;
 	if (host->pdata->slots[id].wires >= 4)
 		mmc->caps |= MMC_CAP_4_BIT_DATA;
 	mmc->ops = &mmc_omap_ops;
 	mmc->f_min = 400000;
 	if (cpu_class_is_omap2())
 		mmc->f_max = 48000000;
 	else
 		mmc->f_max = 24000000;
 	if (host->pdata->max_freq)
 		mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
 	mmc->ocr_avail = slot->pdata->ocr_mask;
 	/* Use scatterlist DMA to reduce per-transfer costs.
 	 * NOTE max_seg_size assumption that small blocks aren't
 	 * normally used (except e.g. for reading SD registers).
 	 */
 	mmc->max_segs = 32;
 	mmc->max_blk_size = 2048;	/* BLEN is 11 bits (+1) */
 	mmc->max_blk_count = 2048;	/* NBLK is 11 bits (+1) */
 	mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
 	mmc->max_seg_size = mmc->max_req_size;
 	r = mmc_add_host(mmc);
 	if (r < 0)
 		goto err_remove_host;
 	if (slot->pdata->name != NULL) {
 		r = device_create_file(&mmc->class_dev,
 					&dev_attr_slot_name);
 		if (r < 0)
 			goto err_remove_host;
 	}
 	if (slot->pdata->get_cover_state != NULL) {
 		r = device_create_file(&mmc->class_dev,
 					&dev_attr_cover_switch);
 		if (r < 0)
 			goto err_remove_slot_name;
 		setup_timer(&slot->cover_timer, mmc_omap_cover_timer,
 			    (unsigned long)slot);
 		tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
 			     (unsigned long)slot);
 		tasklet_schedule(&slot->cover_tasklet);
 	}
 	return 0;
 err_remove_slot_name:
 	if (slot->pdata->name != NULL)
 		device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
 err_remove_host:
 	mmc_remove_host(mmc);
 	mmc_free_host(mmc);
 	return r;
 }
 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
 {
 	struct mmc_host *mmc = slot->mmc;
 	if (slot->pdata->name != NULL)
 		device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
 	if (slot->pdata->get_cover_state != NULL)
 		device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
 	tasklet_kill(&slot->cover_tasklet);
 	del_timer_sync(&slot->cover_timer);
 	flush_workqueue(slot->host->mmc_omap_wq);
 	mmc_remove_host(mmc);
 	mmc_free_host(mmc);
 }
 static int __devinit mmc_omap_probe(struct platform_device *pdev)
 {
 	struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
 	struct mmc_omap_host *host = NULL;
 	struct resource *res;
 	dma_cap_mask_t mask;
 	unsigned sig;
 	int i, ret = 0;
 	int irq;
 	if (pdata == NULL) {
 		dev_err(&pdev->dev, "platform data missing\n");
 		return -ENXIO;
 	}
 	if (pdata->nr_slots == 0) {
 		dev_err(&pdev->dev, "no slots\n");
 		return -ENXIO;
 	}
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	irq = platform_get_irq(pdev, 0);
 	if (res == NULL || irq < 0)
 		return -ENXIO;
 	res = request_mem_region(res->start, resource_size(res),
 				 pdev->name);
 	if (res == NULL)
 		return -EBUSY;
 	host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
 	if (host == NULL) {
 		ret = -ENOMEM;
 		goto err_free_mem_region;
 	}
 	INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
 	INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
 	INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
 	setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer,
 		    (unsigned long) host);
 	spin_lock_init(&host->clk_lock);
 	setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host);
 	spin_lock_init(&host->dma_lock);
 	spin_lock_init(&host->slot_lock);
 	init_waitqueue_head(&host->slot_wq);
 	host->pdata = pdata;
 	host->dev = &pdev->dev;
 	platform_set_drvdata(pdev, host);
 	host->id = pdev->id;
 	host->mem_res = res;
 	host->irq = irq;
 	host->use_dma = 1;
 	host->irq = irq;
 	host->phys_base = host->mem_res->start;
 	host->virt_base = ioremap(res->start, resource_size(res));
 	if (!host->virt_base)
 		goto err_ioremap;
 	host->iclk = clk_get(&pdev->dev, "ick");
 	if (IS_ERR(host->iclk)) {
 		ret = PTR_ERR(host->iclk);
 		goto err_free_mmc_host;
 	}
 	clk_enable(host->iclk);
 	host->fclk = clk_get(&pdev->dev, "fck");
 	if (IS_ERR(host->fclk)) {
 		ret = PTR_ERR(host->fclk);
 		goto err_free_iclk;
 	}
 	dma_cap_zero(mask);
 	dma_cap_set(DMA_SLAVE, mask);
 	host->dma_tx_burst = -1;
 	host->dma_rx_burst = -1;
 	if (cpu_is_omap24xx())
 		sig = host->id == 0 ? OMAP24XX_DMA_MMC1_TX : OMAP24XX_DMA_MMC2_TX;
 	else
 		sig = host->id == 0 ? OMAP_DMA_MMC_TX : OMAP_DMA_MMC2_TX;
 	host->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
 #if 0
 	if (!host->dma_tx) {
 		dev_err(host->dev, "unable to obtain TX DMA engine channel %u\n",
 			sig);
 		goto err_dma;
 	}
 #else
 	if (!host->dma_tx)
 		dev_warn(host->dev, "unable to obtain TX DMA engine channel %u\n",
 			sig);
 #endif
 	if (cpu_is_omap24xx())
 		sig = host->id == 0 ? OMAP24XX_DMA_MMC1_RX : OMAP24XX_DMA_MMC2_RX;
 	else
 		sig = host->id == 0 ? OMAP_DMA_MMC_RX : OMAP_DMA_MMC2_RX;
 	host->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
 #if 0
 	if (!host->dma_rx) {
 		dev_err(host->dev, "unable to obtain RX DMA engine channel %u\n",
 			sig);
 		goto err_dma;
 	}
 #else
 	if (!host->dma_rx)
 		dev_warn(host->dev, "unable to obtain RX DMA engine channel %u\n",
 			sig);
 #endif
 	ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
 	if (ret)
 		goto err_free_dma;
 	if (pdata->init != NULL) {
 		ret = pdata->init(&pdev->dev);
 		if (ret < 0)
 			goto err_free_irq;
 	}
 	host->nr_slots = pdata->nr_slots;
 	host->reg_shift = (cpu_is_omap7xx() ? 1 : 2);
 	host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);
 	if (!host->mmc_omap_wq)
 		goto err_plat_cleanup;
 	for (i = 0; i < pdata->nr_slots; i++) {
 		ret = mmc_omap_new_slot(host, i);
 		if (ret < 0) {
 			while (--i >= 0)
 				mmc_omap_remove_slot(host->slots[i]);
 			goto err_destroy_wq;
 		}
 	}
 	return 0;
 err_destroy_wq:
 	destroy_workqueue(host->mmc_omap_wq);
 err_plat_cleanup:
 	if (pdata->cleanup)
 		pdata->cleanup(&pdev->dev);
 err_free_irq:
 	free_irq(host->irq, host);
 err_free_dma:
 	if (host->dma_tx)
 		dma_release_channel(host->dma_tx);
 	if (host->dma_rx)
 		dma_release_channel(host->dma_rx);
 	clk_put(host->fclk);
 err_free_iclk:
 	clk_disable(host->iclk);
 	clk_put(host->iclk);
 err_free_mmc_host:
 	iounmap(host->virt_base);
 err_ioremap:
 	kfree(host);
 err_free_mem_region:
 	release_mem_region(res->start, resource_size(res));
 	return ret;
 }
 static int __devexit mmc_omap_remove(struct platform_device *pdev)
 {
 	struct mmc_omap_host *host = platform_get_drvdata(pdev);
 	int i;
 	platform_set_drvdata(pdev, NULL);
 	BUG_ON(host == NULL);
 	for (i = 0; i < host->nr_slots; i++)
 		mmc_omap_remove_slot(host->slots[i]);
 	if (host->pdata->cleanup)
 		host->pdata->cleanup(&pdev->dev);
 	mmc_omap_fclk_enable(host, 0);
 	free_irq(host->irq, host);
 	clk_put(host->fclk);
 	clk_disable(host->iclk);
 	clk_put(host->iclk);
 	if (host->dma_tx)
 		dma_release_channel(host->dma_tx);
 	if (host->dma_rx)
 		dma_release_channel(host->dma_rx);
 	iounmap(host->virt_base);
 	release_mem_region(pdev->resource[0].start,
 			   pdev->resource[0].end - pdev->resource[0].start + 1);
 	destroy_workqueue(host->mmc_omap_wq);
 	kfree(host);
 	return 0;
 }
 #ifdef CONFIG_PM
 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
 {
 	int i, ret = 0;
 	struct mmc_omap_host *host = platform_get_drvdata(pdev);
 	if (host == NULL || host->suspended)
 		return 0;
 	for (i = 0; i < host->nr_slots; i++) {
 		struct mmc_omap_slot *slot;
 		slot = host->slots[i];
 		ret = mmc_suspend_host(slot->mmc);
 		if (ret < 0) {
 			while (--i >= 0) {
 				slot = host->slots[i];
 				mmc_resume_host(slot->mmc);
 			}
 			return ret;
 		}
 	}
 	host->suspended = 1;
 	return 0;
 }
 static int mmc_omap_resume(struct platform_device *pdev)
 {
 	int i, ret = 0;
 	struct mmc_omap_host *host = platform_get_drvdata(pdev);
 	if (host == NULL || !host->suspended)
 		return 0;
 	for (i = 0; i < host->nr_slots; i++) {
 		struct mmc_omap_slot *slot;
 		slot = host->slots[i];
 		ret = mmc_resume_host(slot->mmc);
 		if (ret < 0)
 			return ret;
 		host->suspended = 0;
 	}
 	return 0;
 }
 #else
 #define mmc_omap_suspend	NULL
 #define mmc_omap_resume		NULL
 #endif
 static struct platform_driver mmc_omap_driver = {
 	.probe		= mmc_omap_probe,
 	.remove		= __devexit_p(mmc_omap_remove),
 	.suspend	= mmc_omap_suspend,
 	.resume		= mmc_omap_resume,
 	.driver		= {
 		.name	= DRIVER_NAME,
 		.owner	= THIS_MODULE,
 	},
 };
 module_platform_driver(mmc_omap_driver);
 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
 MODULE_LICENSE("GPL");
 MODULE_ALIAS("platform:" DRIVER_NAME);
 MODULE_AUTHOR("Juha Yrjölä");

drivers/mmc/host/sdhci-esdhc.h

Diff comments View file @ 0809095

 /*
  * Freescale eSDHC controller driver generics for OF and pltfm.
  *
  * Copyright (c) 2007 Freescale Semiconductor, Inc.
  * Copyright (c) 2009 MontaVista Software, Inc.
  * Copyright (c) 2010 Pengutronix e.K.
  *   Author: Wolfram Sang <w.sang@pengutronix.de>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License.
  */
 #ifndef _DRIVERS_MMC_SDHCI_ESDHC_H
 #define _DRIVERS_MMC_SDHCI_ESDHC_H
 /*
  * Ops and quirks for the Freescale eSDHC controller.
  */
 #define ESDHC_DEFAULT_QUIRKS	(SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \
 				SDHCI_QUIRK_NO_BUSY_IRQ | \
 				SDHCI_QUIRK_NONSTANDARD_CLOCK | \
 				SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
 				SDHCI_QUIRK_PIO_NEEDS_DELAY | \
 				SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 #define ESDHC_SYSTEM_CONTROL	0x2c
 #define ESDHC_CLOCK_MASK	0x0000fff0
 #define ESDHC_PREDIV_SHIFT	8
 #define ESDHC_DIVIDER_SHIFT	4
 #define ESDHC_CLOCK_PEREN	0x00000004
 #define ESDHC_CLOCK_HCKEN	0x00000002
 #define ESDHC_CLOCK_IPGEN	0x00000001
 /* pltfm-specific */
 #define ESDHC_HOST_CONTROL_LE	0x20
 /* OF-specific */
 #define ESDHC_DMA_SYSCTL	0x40c
 #define ESDHC_DMA_SNOOP		0x00000040
 #define ESDHC_HOST_CONTROL_RES	0x05
 static inline void esdhc_set_clock(struct sdhci_host *host, unsigned int clock)
 {
 	int pre_div = 2;
 	int div = 1;
 	u32 temp;
+	if (clock == 0)
+		goto out;
 	temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 	temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 		| ESDHC_CLOCK_MASK);
 	sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
-	if (clock == 0)
-		goto out;
 	while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
 		pre_div *= 2;
 	while (host->max_clk / pre_div / div > clock && div < 16)
 		div++;
 	dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
 		clock, host->max_clk / pre_div / div);
 	pre_div >>= 1;
 	div--;
 	temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 	temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 		| (div << ESDHC_DIVIDER_SHIFT)
 		| (pre_div << ESDHC_PREDIV_SHIFT));
 	sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 	mdelay(1);
 out:
 	host->clock = clock;
 }

include/linux/mmc/card.h

Diff comments View file @ 0809095

 /*
  *  linux/include/linux/mmc/card.h
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  *
  *  Card driver specific definitions.
  */
 #ifndef LINUX_MMC_CARD_H
 #define LINUX_MMC_CARD_H
 #include <linux/device.h>
 #include <linux/mmc/core.h>
 #include <linux/mod_devicetable.h>
 struct mmc_cid {
 	unsigned int		manfid;
 	char			prod_name[8];
 	unsigned int		serial;
 	unsigned short		oemid;
 	unsigned short		year;
 	unsigned char		hwrev;
 	unsigned char		fwrev;
 	unsigned char		month;
 };
 struct mmc_csd {
 	unsigned char		structure;
 	unsigned char		mmca_vsn;
 	unsigned short		cmdclass;
 	unsigned short		tacc_clks;
 	unsigned int		tacc_ns;
 	unsigned int		c_size;
 	unsigned int		r2w_factor;
 	unsigned int		max_dtr;
 	unsigned int		erase_size;		/* In sectors */
 	unsigned int		read_blkbits;
 	unsigned int		write_blkbits;
 	unsigned int		capacity;
 	unsigned int		read_partial:1,
 				read_misalign:1,
 				write_partial:1,
 				write_misalign:1;
 };
 struct mmc_ext_csd {
 	u8			rev;
 	u8			erase_group_def;
 	u8			sec_feature_support;
 	u8			rel_sectors;
 	u8			rel_param;
 	u8			part_config;
 	u8			cache_ctrl;
 	u8			rst_n_function;
 	unsigned int		part_time;		/* Units: ms */
 	unsigned int		sa_timeout;		/* Units: 100ns */
 	unsigned int		generic_cmd6_time;	/* Units: 10ms */
 	unsigned int            power_off_longtime;     /* Units: ms */
 	unsigned int		hs_max_dtr;
 #define MMC_HIGH_26_MAX_DTR	26000000
 #define MMC_HIGH_52_MAX_DTR	52000000
 #define MMC_HIGH_DDR_MAX_DTR	52000000
 #define MMC_HS200_MAX_DTR	200000000
 	unsigned int		sectors;
 	unsigned int		card_type;
 	unsigned int		hc_erase_size;		/* In sectors */
 	unsigned int		hc_erase_timeout;	/* In milliseconds */
 	unsigned int		sec_trim_mult;	/* Secure trim multiplier  */
 	unsigned int		sec_erase_mult;	/* Secure erase multiplier */
 	unsigned int		trim_timeout;		/* In milliseconds */
 	bool			enhanced_area_en;	/* enable bit */
 	unsigned long long	enhanced_area_offset;	/* Units: Byte */
 	unsigned int		enhanced_area_size;	/* Units: KB */
 	unsigned int		cache_size;		/* Units: KB */
 	bool			hpi_en;			/* HPI enablebit */
 	bool			hpi;			/* HPI support bit */
 	unsigned int		hpi_cmd;		/* cmd used as HPI */
 	unsigned int            data_sector_size;       /* 512 bytes or 4KB */
 	unsigned int            data_tag_unit_size;     /* DATA TAG UNIT size */
 	unsigned int		boot_ro_lock;		/* ro lock support */
 	bool			boot_ro_lockable;
 	u8			raw_partition_support;	/* 160 */
 	u8			raw_erased_mem_count;	/* 181 */
 	u8			raw_ext_csd_structure;	/* 194 */
 	u8			raw_card_type;		/* 196 */
 	u8			out_of_int_time;	/* 198 */
 	u8			raw_s_a_timeout;		/* 217 */
 	u8			raw_hc_erase_gap_size;	/* 221 */
 	u8			raw_erase_timeout_mult;	/* 223 */
 	u8			raw_hc_erase_grp_size;	/* 224 */
 	u8			raw_sec_trim_mult;	/* 229 */
 	u8			raw_sec_erase_mult;	/* 230 */
 	u8			raw_sec_feature_support;/* 231 */
 	u8			raw_trim_mult;		/* 232 */
 	u8			raw_sectors[4];		/* 212 - 4 bytes */
 	unsigned int            feature_support;
 #define MMC_DISCARD_FEATURE	BIT(0)                  /* CMD38 feature */
 };
 struct sd_scr {
 	unsigned char		sda_vsn;
 	unsigned char		sda_spec3;
 	unsigned char		bus_widths;
 #define SD_SCR_BUS_WIDTH_1	(1<<0)
 #define SD_SCR_BUS_WIDTH_4	(1<<2)
 	unsigned char		cmds;
 #define SD_SCR_CMD20_SUPPORT   (1<<0)
 #define SD_SCR_CMD23_SUPPORT   (1<<1)
 };
 struct sd_ssr {
 	unsigned int		au;			/* In sectors */
 	unsigned int		erase_timeout;		/* In milliseconds */
 	unsigned int		erase_offset;		/* In milliseconds */
 };
 struct sd_switch_caps {
 	unsigned int		hs_max_dtr;
 	unsigned int		uhs_max_dtr;
 #define HIGH_SPEED_MAX_DTR	50000000
 #define UHS_SDR104_MAX_DTR	208000000
 #define UHS_SDR50_MAX_DTR	100000000
 #define UHS_DDR50_MAX_DTR	50000000
 #define UHS_SDR25_MAX_DTR	UHS_DDR50_MAX_DTR
 #define UHS_SDR12_MAX_DTR	25000000
 	unsigned int		sd3_bus_mode;
 #define UHS_SDR12_BUS_SPEED	0
 #define HIGH_SPEED_BUS_SPEED	1
 #define UHS_SDR25_BUS_SPEED	1
 #define UHS_SDR50_BUS_SPEED	2
 #define UHS_SDR104_BUS_SPEED	3
 #define UHS_DDR50_BUS_SPEED	4
 #define SD_MODE_HIGH_SPEED	(1 << HIGH_SPEED_BUS_SPEED)
 #define SD_MODE_UHS_SDR12	(1 << UHS_SDR12_BUS_SPEED)
 #define SD_MODE_UHS_SDR25	(1 << UHS_SDR25_BUS_SPEED)
 #define SD_MODE_UHS_SDR50	(1 << UHS_SDR50_BUS_SPEED)
 #define SD_MODE_UHS_SDR104	(1 << UHS_SDR104_BUS_SPEED)
 #define SD_MODE_UHS_DDR50	(1 << UHS_DDR50_BUS_SPEED)
 	unsigned int		sd3_drv_type;
 #define SD_DRIVER_TYPE_B	0x01
 #define SD_DRIVER_TYPE_A	0x02
 #define SD_DRIVER_TYPE_C	0x04
 #define SD_DRIVER_TYPE_D	0x08
 	unsigned int		sd3_curr_limit;
 #define SD_SET_CURRENT_LIMIT_200	0
 #define SD_SET_CURRENT_LIMIT_400	1
 #define SD_SET_CURRENT_LIMIT_600	2
 #define SD_SET_CURRENT_LIMIT_800	3
 #define SD_SET_CURRENT_NO_CHANGE	(-1)
 #define SD_MAX_CURRENT_200	(1 << SD_SET_CURRENT_LIMIT_200)
 #define SD_MAX_CURRENT_400	(1 << SD_SET_CURRENT_LIMIT_400)
 #define SD_MAX_CURRENT_600	(1 << SD_SET_CURRENT_LIMIT_600)
 #define SD_MAX_CURRENT_800	(1 << SD_SET_CURRENT_LIMIT_800)
 };
 struct sdio_cccr {
 	unsigned int		sdio_vsn;
 	unsigned int		sd_vsn;
 	unsigned int		multi_block:1,
 				low_speed:1,
 				wide_bus:1,
 				high_power:1,
 				high_speed:1,
 				disable_cd:1;
 };
 struct sdio_cis {
 	unsigned short		vendor;
 	unsigned short		device;
 	unsigned short		blksize;
 	unsigned int		max_dtr;
 };
 struct mmc_host;
 struct sdio_func;
 struct sdio_func_tuple;
 #define SDIO_MAX_FUNCS		7
 /* The number of MMC physical partitions.  These consist of:
  * boot partitions (2), general purpose partitions (4) in MMC v4.4.
  */
 #define MMC_NUM_BOOT_PARTITION	2
 #define MMC_NUM_GP_PARTITION	4
 #define MMC_NUM_PHY_PARTITION	6
 #define MAX_MMC_PART_NAME_LEN	20
 /*
  * MMC Physical partitions
  */
 struct mmc_part {
 	unsigned int	size;	/* partition size (in bytes) */
 	unsigned int	part_cfg;	/* partition type */
 	char	name[MAX_MMC_PART_NAME_LEN];
 	bool	force_ro;	/* to make boot parts RO by default */
 	unsigned int	area_type;
 #define MMC_BLK_DATA_AREA_MAIN	(1<<0)
 #define MMC_BLK_DATA_AREA_BOOT	(1<<1)
 #define MMC_BLK_DATA_AREA_GP	(1<<2)
 };
 /*
  * MMC device
  */
 struct mmc_card {
 	struct mmc_host		*host;		/* the host this device belongs to */
 	struct device		dev;		/* the device */
 	unsigned int		rca;		/* relative card address of device */
 	unsigned int		type;		/* card type */
 #define MMC_TYPE_MMC		0		/* MMC card */
 #define MMC_TYPE_SD		1		/* SD card */
 #define MMC_TYPE_SDIO		2		/* SDIO card */
 #define MMC_TYPE_SD_COMBO	3		/* SD combo (IO+mem) card */
 	unsigned int		state;		/* (our) card state */
 #define MMC_STATE_PRESENT	(1<<0)		/* present in sysfs */
 #define MMC_STATE_READONLY	(1<<1)		/* card is read-only */
 #define MMC_STATE_HIGHSPEED	(1<<2)		/* card is in high speed mode */
 #define MMC_STATE_BLOCKADDR	(1<<3)		/* card uses block-addressing */
 #define MMC_STATE_HIGHSPEED_DDR (1<<4)		/* card is in high speed mode */
 #define MMC_STATE_ULTRAHIGHSPEED (1<<5)		/* card is in ultra high speed mode */
 #define MMC_CARD_SDXC		(1<<6)		/* card is SDXC */
 #define MMC_CARD_REMOVED	(1<<7)		/* card has been removed */
 #define MMC_STATE_HIGHSPEED_200	(1<<8)		/* card is in HS200 mode */
 #define MMC_STATE_SLEEP		(1<<9)		/* card is in sleep state */
 	unsigned int		quirks; 	/* card quirks */
 #define MMC_QUIRK_LENIENT_FN0	(1<<0)		/* allow SDIO FN0 writes outside of the VS CCCR range */
 #define MMC_QUIRK_BLKSZ_FOR_BYTE_MODE (1<<1)	/* use func->cur_blksize */
 						/* for byte mode */
 #define MMC_QUIRK_NONSTD_SDIO	(1<<2)		/* non-standard SDIO card attached */
 						/* (missing CIA registers) */
 #define MMC_QUIRK_BROKEN_CLK_GATING (1<<3)	/* clock gating the sdio bus will make card fail */
 #define MMC_QUIRK_NONSTD_FUNC_IF (1<<4)		/* SDIO card has nonstd function interfaces */
 #define MMC_QUIRK_DISABLE_CD	(1<<5)		/* disconnect CD/DAT[3] resistor */
 #define MMC_QUIRK_INAND_CMD38	(1<<6)		/* iNAND devices have broken CMD38 */
 #define MMC_QUIRK_BLK_NO_CMD23	(1<<7)		/* Avoid CMD23 for regular multiblock */
 #define MMC_QUIRK_BROKEN_BYTE_MODE_512 (1<<8)	/* Avoid sending 512 bytes in */
 #define MMC_QUIRK_LONG_READ_TIME (1<<9)		/* Data read time > CSD says */
+#define MMC_QUIRK_SEC_ERASE_TRIM_BROKEN (1<<10)	/* Skip secure for erase/trim */
 						/* byte mode */
 	unsigned int    poweroff_notify_state;	/* eMMC4.5 notify feature */
 #define MMC_NO_POWER_NOTIFICATION	0
 #define MMC_POWERED_ON			1
 #define MMC_POWEROFF_SHORT		2
 #define MMC_POWEROFF_LONG		3
 	unsigned int		erase_size;	/* erase size in sectors */
  	unsigned int		erase_shift;	/* if erase unit is power 2 */
  	unsigned int		pref_erase;	/* in sectors */
  	u8			erased_byte;	/* value of erased bytes */
 	u32			raw_cid[4];	/* raw card CID */
 	u32			raw_csd[4];	/* raw card CSD */
 	u32			raw_scr[2];	/* raw card SCR */
 	struct mmc_cid		cid;		/* card identification */
 	struct mmc_csd		csd;		/* card specific */
 	struct mmc_ext_csd	ext_csd;	/* mmc v4 extended card specific */
 	struct sd_scr		scr;		/* extra SD information */
 	struct sd_ssr		ssr;		/* yet more SD information */
 	struct sd_switch_caps	sw_caps;	/* switch (CMD6) caps */
 	unsigned int		sdio_funcs;	/* number of SDIO functions */
 	struct sdio_cccr	cccr;		/* common card info */
 	struct sdio_cis		cis;		/* common tuple info */
 	struct sdio_func	*sdio_func[SDIO_MAX_FUNCS]; /* SDIO functions (devices) */
 	struct sdio_func	*sdio_single_irq; /* SDIO function when only one IRQ active */
 	unsigned		num_info;	/* number of info strings */
 	const char		**info;		/* info strings */
 	struct sdio_func_tuple	*tuples;	/* unknown common tuples */
 	unsigned int		sd_bus_speed;	/* Bus Speed Mode set for the card */
 	struct dentry		*debugfs_root;
 	struct mmc_part	part[MMC_NUM_PHY_PARTITION]; /* physical partitions */
 	unsigned int    nr_parts;
 };
 /*
  * This function fill contents in mmc_part.
  */
 static inline void mmc_part_add(struct mmc_card *card, unsigned int size,
 			unsigned int part_cfg, char *name, int idx, bool ro,
 			int area_type)
 {
 	card->part[card->nr_parts].size = size;
 	card->part[card->nr_parts].part_cfg = part_cfg;
 	sprintf(card->part[card->nr_parts].name, name, idx);
 	card->part[card->nr_parts].force_ro = ro;
 	card->part[card->nr_parts].area_type = area_type;
 	card->nr_parts++;
 }
 /*
  *  The world is not perfect and supplies us with broken mmc/sdio devices.
  *  For at least some of these bugs we need a work-around.
  */
 struct mmc_fixup {
 	/* CID-specific fields. */
 	const char *name;
 	/* Valid revision range */
 	u64 rev_start, rev_end;
 	unsigned int manfid;
 	unsigned short oemid;
 	/* SDIO-specfic fields. You can use SDIO_ANY_ID here of course */
 	u16 cis_vendor, cis_device;
 	void (*vendor_fixup)(struct mmc_card *card, int data);
 	int data;
 };
 #define CID_MANFID_ANY (-1u)
 #define CID_OEMID_ANY ((unsigned short) -1)
 #define CID_NAME_ANY (NULL)
 #define END_FIXUP { 0 }
 #define _FIXUP_EXT(_name, _manfid, _oemid, _rev_start, _rev_end,	\
 		   _cis_vendor, _cis_device,				\
 		   _fixup, _data)					\
 	{						   \
 		.name = (_name),			   \
 		.manfid = (_manfid),			   \
 		.oemid = (_oemid),			   \
 		.rev_start = (_rev_start),		   \
 		.rev_end = (_rev_end),			   \
 		.cis_vendor = (_cis_vendor),		   \
 		.cis_device = (_cis_device),		   \
 		.vendor_fixup = (_fixup),		   \
 		.data = (_data),			   \
 	 }
 #define MMC_FIXUP_REV(_name, _manfid, _oemid, _rev_start, _rev_end,	\
 		      _fixup, _data)					\
 	_FIXUP_EXT(_name, _manfid,					\
 		   _oemid, _rev_start, _rev_end,			\
 		   SDIO_ANY_ID, SDIO_ANY_ID,				\
 		   _fixup, _data)					\
 #define MMC_FIXUP(_name, _manfid, _oemid, _fixup, _data) \
 	MMC_FIXUP_REV(_name, _manfid, _oemid, 0, -1ull, _fixup, _data)
 #define SDIO_FIXUP(_vendor, _device, _fixup, _data)			\
 	_FIXUP_EXT(CID_NAME_ANY, CID_MANFID_ANY,			\
 		    CID_OEMID_ANY, 0, -1ull,				\
 		   _vendor, _device,					\
 		   _fixup, _data)					\
 #define cid_rev(hwrev, fwrev, year, month)	\
 	(((u64) hwrev) << 40 |                  \
 	 ((u64) fwrev) << 32 |                  \
 	 ((u64) year) << 16 |                   \
 	 ((u64) month))
 #define cid_rev_card(card)		  \
 	cid_rev(card->cid.hwrev,	  \
 		    card->cid.fwrev,      \
 		    card->cid.year,	  \
 		    card->cid.month)
 /*
  * Unconditionally quirk add/remove.
  */
 static inline void __maybe_unused add_quirk(struct mmc_card *card, int data)
 {
 	card->quirks |= data;
 }
 static inline void __maybe_unused remove_quirk(struct mmc_card *card, int data)
 {
 	card->quirks &= ~data;
 }
 #define mmc_card_mmc(c)		((c)->type == MMC_TYPE_MMC)
 #define mmc_card_sd(c)		((c)->type == MMC_TYPE_SD)
 #define mmc_card_sdio(c)	((c)->type == MMC_TYPE_SDIO)
 #define mmc_card_present(c)	((c)->state & MMC_STATE_PRESENT)
 #define mmc_card_readonly(c)	((c)->state & MMC_STATE_READONLY)
 #define mmc_card_highspeed(c)	((c)->state & MMC_STATE_HIGHSPEED)
 #define mmc_card_hs200(c)	((c)->state & MMC_STATE_HIGHSPEED_200)
 #define mmc_card_blockaddr(c)	((c)->state & MMC_STATE_BLOCKADDR)
 #define mmc_card_ddr_mode(c)	((c)->state & MMC_STATE_HIGHSPEED_DDR)
 #define mmc_card_uhs(c)		((c)->state & MMC_STATE_ULTRAHIGHSPEED)
 #define mmc_sd_card_uhs(c)	((c)->state & MMC_STATE_ULTRAHIGHSPEED)
 #define mmc_card_ext_capacity(c) ((c)->state & MMC_CARD_SDXC)
 #define mmc_card_removed(c)	((c) && ((c)->state & MMC_CARD_REMOVED))
 #define mmc_card_is_sleep(c)	((c)->state & MMC_STATE_SLEEP)
 #define mmc_card_set_present(c)	((c)->state |= MMC_STATE_PRESENT)
 #define mmc_card_set_readonly(c) ((c)->state |= MMC_STATE_READONLY)
 #define mmc_card_set_highspeed(c) ((c)->state |= MMC_STATE_HIGHSPEED)
 #define mmc_card_set_hs200(c)	((c)->state |= MMC_STATE_HIGHSPEED_200)
 #define mmc_card_set_blockaddr(c) ((c)->state |= MMC_STATE_BLOCKADDR)
 #define mmc_card_set_ddr_mode(c) ((c)->state |= MMC_STATE_HIGHSPEED_DDR)
 #define mmc_card_set_uhs(c) ((c)->state |= MMC_STATE_ULTRAHIGHSPEED)
 #define mmc_sd_card_set_uhs(c) ((c)->state |= MMC_STATE_ULTRAHIGHSPEED)
 #define mmc_card_set_ext_capacity(c) ((c)->state |= MMC_CARD_SDXC)
 #define mmc_card_set_removed(c) ((c)->state |= MMC_CARD_REMOVED)
 #define mmc_card_set_sleep(c)	((c)->state |= MMC_STATE_SLEEP)
 #define mmc_card_clr_sleep(c)	((c)->state &= ~MMC_STATE_SLEEP)
 /*
  * Quirk add/remove for MMC products.
  */
 static inline void __maybe_unused add_quirk_mmc(struct mmc_card *card, int data)
 {
 	if (mmc_card_mmc(card))
 		card->quirks |= data;
 }
 static inline void __maybe_unused remove_quirk_mmc(struct mmc_card *card,
 						   int data)
 {
 	if (mmc_card_mmc(card))
 		card->quirks &= ~data;
 }
 /*
  * Quirk add/remove for SD products.
  */
 static inline void __maybe_unused add_quirk_sd(struct mmc_card *card, int data)
 {
 	if (mmc_card_sd(card))
 		card->quirks |= data;
 }
 static inline void __maybe_unused remove_quirk_sd(struct mmc_card *card,
 						   int data)
 {
 	if (mmc_card_sd(card))
 		card->quirks &= ~data;
 }
 static inline int mmc_card_lenient_fn0(const struct mmc_card *c)
 {
 	return c->quirks & MMC_QUIRK_LENIENT_FN0;
 }
 static inline int mmc_blksz_for_byte_mode(const struct mmc_card *c)
 {
 	return c->quirks & MMC_QUIRK_BLKSZ_FOR_BYTE_MODE;
 }
 static inline int mmc_card_disable_cd(const struct mmc_card *c)
 {
 	return c->quirks & MMC_QUIRK_DISABLE_CD;
 }
 static inline int mmc_card_nonstd_func_interface(const struct mmc_card *c)
 {
 	return c->quirks & MMC_QUIRK_NONSTD_FUNC_IF;
 }
 static inline int mmc_card_broken_byte_mode_512(const struct mmc_card *c)
 {
 	return c->quirks & MMC_QUIRK_BROKEN_BYTE_MODE_512;
 }
 static inline int mmc_card_long_read_time(const struct mmc_card *c)
 {
 	return c->quirks & MMC_QUIRK_LONG_READ_TIME;
 }
 #define mmc_card_name(c)	((c)->cid.prod_name)
 #define mmc_card_id(c)		(dev_name(&(c)->dev))
 #define mmc_dev_to_card(d)	container_of(d, struct mmc_card, dev)
 #define mmc_list_to_card(l)	container_of(l, struct mmc_card, node)
 #define mmc_get_drvdata(c)	dev_get_drvdata(&(c)->dev)
 #define mmc_set_drvdata(c,d)	dev_set_drvdata(&(c)->dev, d)
 /*
  * MMC device driver (e.g., Flash card, I/O card...)
  */
 struct mmc_driver {
 	struct device_driver drv;
 	int (*probe)(struct mmc_card *);
 	void (*remove)(struct mmc_card *);
 	int (*suspend)(struct mmc_card *);
 	int (*resume)(struct mmc_card *);
 };
 extern int mmc_register_driver(struct mmc_driver *);
 extern void mmc_unregister_driver(struct mmc_driver *);
 extern void mmc_fixup_device(struct mmc_card *card,
 			     const struct mmc_fixup *table);
 #endif /* LINUX_MMC_CARD_H */