Doug / smarc-fsl-linux-kernel | Embedian Git Server

Commit 0a03726ca982129b1e054f0e8c34ca7eea348acd

Authored by Linus Torvalds 2012-03-30 02:24:43 +0800

Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Pull the intel i915 hibernation memory corruption fix from Dave Airlie:
 "I tracked down the misc memory corruption after i915 hibernate to the
  blinking fbcon cursor, and realised the i915 driver wasn't doing the
  fbdev suspend/resume calls at all.  nouveau and radeon have done these
  calls for a long time.

  This has been fairly well tested and is definitely the main culprit in
  hibernate not working."

Yay.

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
  drm/i915: suspend fbdev device around suspend/hibernate

Showing 3 changed files Inline Diff

drivers/gpu/drm/i915/i915_drv.c
drivers/gpu/drm/i915/intel_drv.h
drivers/gpu/drm/i915/intel_fb.c

drivers/gpu/drm/i915/i915_drv.c

Diff comments View file @ 0a03726

 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
  */
 /*
  *
  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the
  * "Software"), to deal in the Software without restriction, including
  * without limitation the rights to use, copy, modify, merge, publish,
  * distribute, sub license, and/or sell copies of the Software, and to
  * permit persons to whom the Software is furnished to do so, subject to
  * the following conditions:
  *
  * The above copyright notice and this permission notice (including the
  * next paragraph) shall be included in all copies or substantial portions
  * of the Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
  */
 #include <linux/device.h>
 #include "drmP.h"
 #include "drm.h"
 #include "i915_drm.h"
 #include "i915_drv.h"
 #include "intel_drv.h"
 #include <linux/console.h>
 #include <linux/module.h>
 #include "drm_crtc_helper.h"
 static int i915_modeset __read_mostly = -1;
 module_param_named(modeset, i915_modeset, int, 0400);
 MODULE_PARM_DESC(modeset,
 		"Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
 		"1=on, -1=force vga console preference [default])");
 unsigned int i915_fbpercrtc __always_unused = 0;
 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
 int i915_panel_ignore_lid __read_mostly = 0;
 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
 MODULE_PARM_DESC(panel_ignore_lid,
 		"Override lid status (0=autodetect [default], 1=lid open, "
 		"-1=lid closed)");
 unsigned int i915_powersave __read_mostly = 1;
 module_param_named(powersave, i915_powersave, int, 0600);
 MODULE_PARM_DESC(powersave,
 		"Enable powersavings, fbc, downclocking, etc. (default: true)");
 int i915_semaphores __read_mostly = -1;
 module_param_named(semaphores, i915_semaphores, int, 0600);
 MODULE_PARM_DESC(semaphores,
 		"Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
 int i915_enable_rc6 __read_mostly = -1;
 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
 MODULE_PARM_DESC(i915_enable_rc6,
 		"Enable power-saving render C-state 6 (default: -1 (use per-chip default)");
 int i915_enable_fbc __read_mostly = -1;
 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
 MODULE_PARM_DESC(i915_enable_fbc,
 		"Enable frame buffer compression for power savings "
 		"(default: -1 (use per-chip default))");
 unsigned int i915_lvds_downclock __read_mostly = 0;
 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
 MODULE_PARM_DESC(lvds_downclock,
 		"Use panel (LVDS/eDP) downclocking for power savings "
 		"(default: false)");
 int i915_panel_use_ssc __read_mostly = -1;
 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
 MODULE_PARM_DESC(lvds_use_ssc,
 		"Use Spread Spectrum Clock with panels [LVDS/eDP] "
 		"(default: auto from VBT)");
 int i915_vbt_sdvo_panel_type __read_mostly = -1;
 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
 MODULE_PARM_DESC(vbt_sdvo_panel_type,
 		"Override selection of SDVO panel mode in the VBT "
 		"(default: auto)");
 static bool i915_try_reset __read_mostly = true;
 module_param_named(reset, i915_try_reset, bool, 0600);
 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 bool i915_enable_hangcheck __read_mostly = true;
 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 MODULE_PARM_DESC(enable_hangcheck,
 		"Periodically check GPU activity for detecting hangs. "
 		"WARNING: Disabling this can cause system wide hangs. "
 		"(default: true)");
 bool i915_enable_ppgtt __read_mostly = 1;
 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, bool, 0600);
 MODULE_PARM_DESC(i915_enable_ppgtt,
 		"Enable PPGTT (default: true)");
 static struct drm_driver driver;
 extern int intel_agp_enabled;
 #define INTEL_VGA_DEVICE(id, info) {		\
 	.class = PCI_BASE_CLASS_DISPLAY << 16,	\
 	.class_mask = 0xff0000,			\
 	.vendor = 0x8086,			\
 	.device = id,				\
 	.subvendor = PCI_ANY_ID,		\
 	.subdevice = PCI_ANY_ID,		\
 	.driver_data = (unsigned long) info }
 static const struct intel_device_info intel_i830_info = {
 	.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
 	.has_overlay = 1, .overlay_needs_physical = 1,
 };
 static const struct intel_device_info intel_845g_info = {
 	.gen = 2,
 	.has_overlay = 1, .overlay_needs_physical = 1,
 };
 static const struct intel_device_info intel_i85x_info = {
 	.gen = 2, .is_i85x = 1, .is_mobile = 1,
 	.cursor_needs_physical = 1,
 	.has_overlay = 1, .overlay_needs_physical = 1,
 };
 static const struct intel_device_info intel_i865g_info = {
 	.gen = 2,
 	.has_overlay = 1, .overlay_needs_physical = 1,
 };
 static const struct intel_device_info intel_i915g_info = {
 	.gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
 	.has_overlay = 1, .overlay_needs_physical = 1,
 };
 static const struct intel_device_info intel_i915gm_info = {
 	.gen = 3, .is_mobile = 1,
 	.cursor_needs_physical = 1,
 	.has_overlay = 1, .overlay_needs_physical = 1,
 	.supports_tv = 1,
 };
 static const struct intel_device_info intel_i945g_info = {
 	.gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
 	.has_overlay = 1, .overlay_needs_physical = 1,
 };
 static const struct intel_device_info intel_i945gm_info = {
 	.gen = 3, .is_i945gm = 1, .is_mobile = 1,
 	.has_hotplug = 1, .cursor_needs_physical = 1,
 	.has_overlay = 1, .overlay_needs_physical = 1,
 	.supports_tv = 1,
 };
 static const struct intel_device_info intel_i965g_info = {
 	.gen = 4, .is_broadwater = 1,
 	.has_hotplug = 1,
 	.has_overlay = 1,
 };
 static const struct intel_device_info intel_i965gm_info = {
 	.gen = 4, .is_crestline = 1,
 	.is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 	.has_overlay = 1,
 	.supports_tv = 1,
 };
 static const struct intel_device_info intel_g33_info = {
 	.gen = 3, .is_g33 = 1,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.has_overlay = 1,
 };
 static const struct intel_device_info intel_g45_info = {
 	.gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 	.has_pipe_cxsr = 1, .has_hotplug = 1,
 	.has_bsd_ring = 1,
 };
 static const struct intel_device_info intel_gm45_info = {
 	.gen = 4, .is_g4x = 1,
 	.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 	.has_pipe_cxsr = 1, .has_hotplug = 1,
 	.supports_tv = 1,
 	.has_bsd_ring = 1,
 };
 static const struct intel_device_info intel_pineview_info = {
 	.gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.has_overlay = 1,
 };
 static const struct intel_device_info intel_ironlake_d_info = {
 	.gen = 5,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.has_bsd_ring = 1,
 };
 static const struct intel_device_info intel_ironlake_m_info = {
 	.gen = 5, .is_mobile = 1,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.has_fbc = 1,
 	.has_bsd_ring = 1,
 };
 static const struct intel_device_info intel_sandybridge_d_info = {
 	.gen = 6,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.has_bsd_ring = 1,
 	.has_blt_ring = 1,
 	.has_llc = 1,
 };
 static const struct intel_device_info intel_sandybridge_m_info = {
 	.gen = 6, .is_mobile = 1,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.has_fbc = 1,
 	.has_bsd_ring = 1,
 	.has_blt_ring = 1,
 	.has_llc = 1,
 };
 static const struct intel_device_info intel_ivybridge_d_info = {
 	.is_ivybridge = 1, .gen = 7,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.has_bsd_ring = 1,
 	.has_blt_ring = 1,
 	.has_llc = 1,
 };
 static const struct intel_device_info intel_ivybridge_m_info = {
 	.is_ivybridge = 1, .gen = 7, .is_mobile = 1,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.has_fbc = 0,	/* FBC is not enabled on Ivybridge mobile yet */
 	.has_bsd_ring = 1,
 	.has_blt_ring = 1,
 	.has_llc = 1,
 };
 static const struct pci_device_id pciidlist[] = {		/* aka */
 	INTEL_VGA_DEVICE(0x3577, &intel_i830_info),		/* I830_M */
 	INTEL_VGA_DEVICE(0x2562, &intel_845g_info),		/* 845_G */
 	INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),		/* I855_GM */
 	INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 	INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),		/* I865_G */
 	INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),		/* I915_G */
 	INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),		/* E7221_G */
 	INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),		/* I915_GM */
 	INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),		/* I945_G */
 	INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),		/* I945_GM */
 	INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),		/* I945_GME */
 	INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),		/* I946_GZ */
 	INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),		/* G35_G */
 	INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),		/* I965_Q */
 	INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),		/* I965_G */
 	INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),		/* Q35_G */
 	INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),		/* G33_G */
 	INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),		/* Q33_G */
 	INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),		/* I965_GM */
 	INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),		/* I965_GME */
 	INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),		/* GM45_G */
 	INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),		/* IGD_E_G */
 	INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),		/* Q45_G */
 	INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),		/* G45_G */
 	INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),		/* G41_G */
 	INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),		/* B43_G */
 	INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),		/* B43_G.1 */
 	INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 	INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 	INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 	INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 	INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 	INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 	INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 	INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 	INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 	INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 	INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 	INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 	INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 	INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 	INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 	INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 	{0, 0, 0}
 };
 #if defined(CONFIG_DRM_I915_KMS)
 MODULE_DEVICE_TABLE(pci, pciidlist);
 #endif
 #define INTEL_PCH_DEVICE_ID_MASK	0xff00
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE	0x3b00
 #define INTEL_PCH_CPT_DEVICE_ID_TYPE	0x1c00
 #define INTEL_PCH_PPT_DEVICE_ID_TYPE	0x1e00
 void intel_detect_pch(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct pci_dev *pch;
 	/*
 	 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 	 * make graphics device passthrough work easy for VMM, that only
 	 * need to expose ISA bridge to let driver know the real hardware
 	 * underneath. This is a requirement from virtualization team.
 	 */
 	pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 	if (pch) {
 		if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 			int id;
 			id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 			if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_IBX;
 				DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 			} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_CPT;
 				DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 			} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 				/* PantherPoint is CPT compatible */
 				dev_priv->pch_type = PCH_CPT;
 				DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 			}
 		}
 		pci_dev_put(pch);
 	}
 }
 void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 {
 	int count;
 	count = 0;
 	while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
 		udelay(10);
 	I915_WRITE_NOTRACE(FORCEWAKE, 1);
 	POSTING_READ(FORCEWAKE);
 	count = 0;
 	while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
 		udelay(10);
 }
 void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
 {
 	int count;
 	count = 0;
 	while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
 		udelay(10);
 	I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1);
 	POSTING_READ(FORCEWAKE_MT);
 	count = 0;
 	while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
 		udelay(10);
 }
 /*
  * Generally this is called implicitly by the register read function. However,
  * if some sequence requires the GT to not power down then this function should
  * be called at the beginning of the sequence followed by a call to
  * gen6_gt_force_wake_put() at the end of the sequence.
  */
 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 {
 	unsigned long irqflags;
 	spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 	if (dev_priv->forcewake_count++ == 0)
 		dev_priv->display.force_wake_get(dev_priv);
 	spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 }
 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 {
 	u32 gtfifodbg;
 	gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
 	if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
 	     "MMIO read or write has been dropped %x\n", gtfifodbg))
 		I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
 }
 void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 {
 	I915_WRITE_NOTRACE(FORCEWAKE, 0);
 	/* The below doubles as a POSTING_READ */
 	gen6_gt_check_fifodbg(dev_priv);
 }
 void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
 {
 	I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0);
 	/* The below doubles as a POSTING_READ */
 	gen6_gt_check_fifodbg(dev_priv);
 }
 /*
  * see gen6_gt_force_wake_get()
  */
 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 {
 	unsigned long irqflags;
 	spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 	if (--dev_priv->forcewake_count == 0)
 		dev_priv->display.force_wake_put(dev_priv);
 	spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 }
 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 {
 	int ret = 0;
 	if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 		int loop = 500;
 		u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 		while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 			udelay(10);
 			fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 		}
 		if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 			++ret;
 		dev_priv->gt_fifo_count = fifo;
 	}
 	dev_priv->gt_fifo_count--;
 	return ret;
 }
 static int i915_drm_freeze(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	drm_kms_helper_poll_disable(dev);
 	pci_save_state(dev->pdev);
 	/* If KMS is active, we do the leavevt stuff here */
 	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 		int error = i915_gem_idle(dev);
 		if (error) {
 			dev_err(&dev->pdev->dev,
 				"GEM idle failed, resume might fail\n");
 			return error;
 		}
 		drm_irq_uninstall(dev);
 	}
 	i915_save_state(dev);
 	intel_opregion_fini(dev);
 	/* Modeset on resume, not lid events */
 	dev_priv->modeset_on_lid = 0;
+	console_lock();
+	intel_fbdev_set_suspend(dev, 1);
+	console_unlock();
 	return 0;
 }
 int i915_suspend(struct drm_device *dev, pm_message_t state)
 {
 	int error;
 	if (!dev || !dev->dev_private) {
 		DRM_ERROR("dev: %p\n", dev);
 		DRM_ERROR("DRM not initialized, aborting suspend.\n");
 		return -ENODEV;
 	}
 	if (state.event == PM_EVENT_PRETHAW)
 		return 0;
 	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 		return 0;
 	error = i915_drm_freeze(dev);
 	if (error)
 		return error;
 	if (state.event == PM_EVENT_SUSPEND) {
 		/* Shut down the device */
 		pci_disable_device(dev->pdev);
 		pci_set_power_state(dev->pdev, PCI_D3hot);
 	}
 	return 0;
 }
 static int i915_drm_thaw(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int error = 0;
 	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 		mutex_lock(&dev->struct_mutex);
 		i915_gem_restore_gtt_mappings(dev);
 		mutex_unlock(&dev->struct_mutex);
 	}
 	i915_restore_state(dev);
 	intel_opregion_setup(dev);
 	/* KMS EnterVT equivalent */
 	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 		mutex_lock(&dev->struct_mutex);
 		dev_priv->mm.suspended = 0;
 		error = i915_gem_init_hw(dev);
 		mutex_unlock(&dev->struct_mutex);
 		if (HAS_PCH_SPLIT(dev))
 			ironlake_init_pch_refclk(dev);
 		drm_mode_config_reset(dev);
 		drm_irq_install(dev);
 		/* Resume the modeset for every activated CRTC */
 		drm_helper_resume_force_mode(dev);
 		if (IS_IRONLAKE_M(dev))
 			ironlake_enable_rc6(dev);
 	}
 	intel_opregion_init(dev);
 	dev_priv->modeset_on_lid = 0;
+	console_lock();
+	intel_fbdev_set_suspend(dev, 0);
+	console_unlock();
 	return error;
 }
 int i915_resume(struct drm_device *dev)
 {
 	int ret;
 	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 		return 0;
 	if (pci_enable_device(dev->pdev))
 		return -EIO;
 	pci_set_master(dev->pdev);
 	ret = i915_drm_thaw(dev);
 	if (ret)
 		return ret;
 	drm_kms_helper_poll_enable(dev);
 	return 0;
 }
 static int i8xx_do_reset(struct drm_device *dev, u8 flags)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (IS_I85X(dev))
 		return -ENODEV;
 	I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 	POSTING_READ(D_STATE);
 	if (IS_I830(dev) || IS_845G(dev)) {
 		I915_WRITE(DEBUG_RESET_I830,
 			   DEBUG_RESET_DISPLAY |
 			   DEBUG_RESET_RENDER |
 			   DEBUG_RESET_FULL);
 		POSTING_READ(DEBUG_RESET_I830);
 		msleep(1);
 		I915_WRITE(DEBUG_RESET_I830, 0);
 		POSTING_READ(DEBUG_RESET_I830);
 	}
 	msleep(1);
 	I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 	POSTING_READ(D_STATE);
 	return 0;
 }
 static int i965_reset_complete(struct drm_device *dev)
 {
 	u8 gdrst;
 	pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 	return gdrst & 0x1;
 }
 static int i965_do_reset(struct drm_device *dev, u8 flags)
 {
 	u8 gdrst;
 	/*
 	 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 	 * well as the reset bit (GR/bit 0).  Setting the GR bit
 	 * triggers the reset; when done, the hardware will clear it.
 	 */
 	pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 	pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
 	return wait_for(i965_reset_complete(dev), 500);
 }
 static int ironlake_do_reset(struct drm_device *dev, u8 flags)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
 	return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 }
 static int gen6_do_reset(struct drm_device *dev, u8 flags)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int	ret;
 	unsigned long irqflags;
 	/* Hold gt_lock across reset to prevent any register access
 	 * with forcewake not set correctly
 	 */
 	spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 	/* Reset the chip */
 	/* GEN6_GDRST is not in the gt power well, no need to check
 	 * for fifo space for the write or forcewake the chip for
 	 * the read
 	 */
 	I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
 	/* Spin waiting for the device to ack the reset request */
 	ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 	/* If reset with a user forcewake, try to restore, otherwise turn it off */
 	if (dev_priv->forcewake_count)
 		dev_priv->display.force_wake_get(dev_priv);
 	else
 		dev_priv->display.force_wake_put(dev_priv);
 	/* Restore fifo count */
 	dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 	spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 	return ret;
 }
 /**
  * i915_reset - reset chip after a hang
  * @dev: drm device to reset
  * @flags: reset domains
  *
  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
  * reset or otherwise an error code.
  *
  * Procedure is fairly simple:
  *   - reset the chip using the reset reg
  *   - re-init context state
  *   - re-init hardware status page
  *   - re-init ring buffer
  *   - re-init interrupt state
  *   - re-init display
  */
 int i915_reset(struct drm_device *dev, u8 flags)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	/*
 	 * We really should only reset the display subsystem if we actually
 	 * need to
 	 */
 	bool need_display = true;
 	int ret;
 	if (!i915_try_reset)
 		return 0;
 	if (!mutex_trylock(&dev->struct_mutex))
 		return -EBUSY;
 	i915_gem_reset(dev);
 	ret = -ENODEV;
 	if (get_seconds() - dev_priv->last_gpu_reset < 5) {
 		DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 	} else switch (INTEL_INFO(dev)->gen) {
 	case 7:
 	case 6:
 		ret = gen6_do_reset(dev, flags);
 		break;
 	case 5:
 		ret = ironlake_do_reset(dev, flags);
 		break;
 	case 4:
 		ret = i965_do_reset(dev, flags);
 		break;
 	case 2:
 		ret = i8xx_do_reset(dev, flags);
 		break;
 	}
 	dev_priv->last_gpu_reset = get_seconds();
 	if (ret) {
 		DRM_ERROR("Failed to reset chip.\n");
 		mutex_unlock(&dev->struct_mutex);
 		return ret;
 	}
 	/* Ok, now get things going again... */
 	/*
 	 * Everything depends on having the GTT running, so we need to start
 	 * there.  Fortunately we don't need to do this unless we reset the
 	 * chip at a PCI level.
 	 *
 	 * Next we need to restore the context, but we don't use those
 	 * yet either...
 	 *
 	 * Ring buffer needs to be re-initialized in the KMS case, or if X
 	 * was running at the time of the reset (i.e. we weren't VT
 	 * switched away).
 	 */
 	if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 			!dev_priv->mm.suspended) {
 		dev_priv->mm.suspended = 0;
 		i915_gem_init_swizzling(dev);
 		dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
 		if (HAS_BSD(dev))
 		    dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
 		if (HAS_BLT(dev))
 		    dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
 		i915_gem_init_ppgtt(dev);
 		mutex_unlock(&dev->struct_mutex);
 		drm_irq_uninstall(dev);
 		drm_mode_config_reset(dev);
 		drm_irq_install(dev);
 		mutex_lock(&dev->struct_mutex);
 	}
 	mutex_unlock(&dev->struct_mutex);
 	/*
 	 * Perform a full modeset as on later generations, e.g. Ironlake, we may
 	 * need to retrain the display link and cannot just restore the register
 	 * values.
 	 */
 	if (need_display) {
 		mutex_lock(&dev->mode_config.mutex);
 		drm_helper_resume_force_mode(dev);
 		mutex_unlock(&dev->mode_config.mutex);
 	}
 	return 0;
 }
 static int __devinit
 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 {
 	/* Only bind to function 0 of the device. Early generations
 	 * used function 1 as a placeholder for multi-head. This causes
 	 * us confusion instead, especially on the systems where both
 	 * functions have the same PCI-ID!
 	 */
 	if (PCI_FUNC(pdev->devfn))
 		return -ENODEV;
 	return drm_get_pci_dev(pdev, ent, &driver);
 }
 static void
 i915_pci_remove(struct pci_dev *pdev)
 {
 	struct drm_device *dev = pci_get_drvdata(pdev);
 	drm_put_dev(dev);
 }
 static int i915_pm_suspend(struct device *dev)
 {
 	struct pci_dev *pdev = to_pci_dev(dev);
 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
 	int error;
 	if (!drm_dev || !drm_dev->dev_private) {
 		dev_err(dev, "DRM not initialized, aborting suspend.\n");
 		return -ENODEV;
 	}
 	if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 		return 0;
 	error = i915_drm_freeze(drm_dev);
 	if (error)
 		return error;
 	pci_disable_device(pdev);
 	pci_set_power_state(pdev, PCI_D3hot);
 	return 0;
 }
 static int i915_pm_resume(struct device *dev)
 {
 	struct pci_dev *pdev = to_pci_dev(dev);
 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
 	return i915_resume(drm_dev);
 }
 static int i915_pm_freeze(struct device *dev)
 {
 	struct pci_dev *pdev = to_pci_dev(dev);
 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
 	if (!drm_dev || !drm_dev->dev_private) {
 		dev_err(dev, "DRM not initialized, aborting suspend.\n");
 		return -ENODEV;
 	}
 	return i915_drm_freeze(drm_dev);
 }
 static int i915_pm_thaw(struct device *dev)
 {
 	struct pci_dev *pdev = to_pci_dev(dev);
 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
 	return i915_drm_thaw(drm_dev);
 }
 static int i915_pm_poweroff(struct device *dev)
 {
 	struct pci_dev *pdev = to_pci_dev(dev);
 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
 	return i915_drm_freeze(drm_dev);
 }
 static const struct dev_pm_ops i915_pm_ops = {
 	.suspend = i915_pm_suspend,
 	.resume = i915_pm_resume,
 	.freeze = i915_pm_freeze,
 	.thaw = i915_pm_thaw,
 	.poweroff = i915_pm_poweroff,
 	.restore = i915_pm_resume,
 };
 static struct vm_operations_struct i915_gem_vm_ops = {
 	.fault = i915_gem_fault,
 	.open = drm_gem_vm_open,
 	.close = drm_gem_vm_close,
 };
 static const struct file_operations i915_driver_fops = {
 	.owner = THIS_MODULE,
 	.open = drm_open,
 	.release = drm_release,
 	.unlocked_ioctl = drm_ioctl,
 	.mmap = drm_gem_mmap,
 	.poll = drm_poll,
 	.fasync = drm_fasync,
 	.read = drm_read,
 #ifdef CONFIG_COMPAT
 	.compat_ioctl = i915_compat_ioctl,
 #endif
 	.llseek = noop_llseek,
 };
 static struct drm_driver driver = {
 	/* Don't use MTRRs here; the Xserver or userspace app should
 	 * deal with them for Intel hardware.
 	 */
 	.driver_features =
 	    DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
 	    DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
 	.load = i915_driver_load,
 	.unload = i915_driver_unload,
 	.open = i915_driver_open,
 	.lastclose = i915_driver_lastclose,
 	.preclose = i915_driver_preclose,
 	.postclose = i915_driver_postclose,
 	/* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 	.suspend = i915_suspend,
 	.resume = i915_resume,
 	.device_is_agp = i915_driver_device_is_agp,
 	.reclaim_buffers = drm_core_reclaim_buffers,
 	.master_create = i915_master_create,
 	.master_destroy = i915_master_destroy,
 #if defined(CONFIG_DEBUG_FS)
 	.debugfs_init = i915_debugfs_init,
 	.debugfs_cleanup = i915_debugfs_cleanup,
 #endif
 	.gem_init_object = i915_gem_init_object,
 	.gem_free_object = i915_gem_free_object,
 	.gem_vm_ops = &i915_gem_vm_ops,
 	.dumb_create = i915_gem_dumb_create,
 	.dumb_map_offset = i915_gem_mmap_gtt,
 	.dumb_destroy = i915_gem_dumb_destroy,
 	.ioctls = i915_ioctls,
 	.fops = &i915_driver_fops,
 	.name = DRIVER_NAME,
 	.desc = DRIVER_DESC,
 	.date = DRIVER_DATE,
 	.major = DRIVER_MAJOR,
 	.minor = DRIVER_MINOR,
 	.patchlevel = DRIVER_PATCHLEVEL,
 };
 static struct pci_driver i915_pci_driver = {
 	.name = DRIVER_NAME,
 	.id_table = pciidlist,
 	.probe = i915_pci_probe,
 	.remove = i915_pci_remove,
 	.driver.pm = &i915_pm_ops,
 };
 static int __init i915_init(void)
 {
 	if (!intel_agp_enabled) {
 		DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 		return -ENODEV;
 	}
 	driver.num_ioctls = i915_max_ioctl;
 	/*
 	 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
 	 * explicitly disabled with the module pararmeter.
 	 *
 	 * Otherwise, just follow the parameter (defaulting to off).
 	 *
 	 * Allow optional vga_text_mode_force boot option to override
 	 * the default behavior.
 	 */
 #if defined(CONFIG_DRM_I915_KMS)
 	if (i915_modeset != 0)
 		driver.driver_features |= DRIVER_MODESET;
 #endif
 	if (i915_modeset == 1)
 		driver.driver_features |= DRIVER_MODESET;
 #ifdef CONFIG_VGA_CONSOLE
 	if (vgacon_text_force() && i915_modeset == -1)
 		driver.driver_features &= ~DRIVER_MODESET;
 #endif
 	if (!(driver.driver_features & DRIVER_MODESET))
 		driver.get_vblank_timestamp = NULL;
 	return drm_pci_init(&driver, &i915_pci_driver);
 }
 static void __exit i915_exit(void)
 {
 	drm_pci_exit(&driver, &i915_pci_driver);
 }
 module_init(i915_init);
 module_exit(i915_exit);
 MODULE_AUTHOR(DRIVER_AUTHOR);
 MODULE_DESCRIPTION(DRIVER_DESC);
 MODULE_LICENSE("GPL and additional rights");
 #define __i915_read(x, y) \
 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
 	u##x val = 0; \
 	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 		unsigned long irqflags; \
 		spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
 		if (dev_priv->forcewake_count == 0) \
 			dev_priv->display.force_wake_get(dev_priv); \
 		val = read##y(dev_priv->regs + reg); \
 		if (dev_priv->forcewake_count == 0) \
 			dev_priv->display.force_wake_put(dev_priv); \
 		spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
 	} else { \
 		val = read##y(dev_priv->regs + reg); \
 	} \
 	trace_i915_reg_rw(false, reg, val, sizeof(val)); \
 	return val; \
 }
 __i915_read(8, b)
 __i915_read(16, w)
 __i915_read(32, l)
 __i915_read(64, q)
 #undef __i915_read
 #define __i915_write(x, y) \
 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
 	u32 __fifo_ret = 0; \
 	trace_i915_reg_rw(true, reg, val, sizeof(val)); \
 	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 		__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
 	} \
 	write##y(val, dev_priv->regs + reg); \
 	if (unlikely(__fifo_ret)) { \
 		gen6_gt_check_fifodbg(dev_priv); \
 	} \
 }
 __i915_write(8, b)
 __i915_write(16, w)
 __i915_write(32, l)
 __i915_write(64, q)
 #undef __i915_write

drivers/gpu/drm/i915/intel_drv.h

Diff comments View file @ 0a03726

1	/*	1	/*
2	* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>	2	* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3	* Copyright (c) 2007-2008 Intel Corporation	3	* Copyright (c) 2007-2008 Intel Corporation
4	* Jesse Barnes <jesse.barnes@intel.com>	4	* Jesse Barnes <jesse.barnes@intel.com>
5	*	5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a	6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),	7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation	8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the	10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:	11	* Software is furnished to do so, subject to the following conditions:
12	*	12	*
13	* The above copyright notice and this permission notice (including the next	13	* The above copyright notice and this permission notice (including the next
14	* paragraph) shall be included in all copies or substantial portions of the	14	* paragraph) shall be included in all copies or substantial portions of the
15	* Software.	15	* Software.
16	*	16	*
17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS	22	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23	* IN THE SOFTWARE.	23	* IN THE SOFTWARE.
24	*/	24	*/
25	#ifndef __INTEL_DRV_H__	25	#ifndef __INTEL_DRV_H__
26	#define __INTEL_DRV_H__	26	#define __INTEL_DRV_H__
27		27
28	#include <linux/i2c.h>	28	#include <linux/i2c.h>
29	#include "i915_drm.h"	29	#include "i915_drm.h"
30	#include "i915_drv.h"	30	#include "i915_drv.h"
31	#include "drm_crtc.h"	31	#include "drm_crtc.h"
32	#include "drm_crtc_helper.h"	32	#include "drm_crtc_helper.h"
33	#include "drm_fb_helper.h"	33	#include "drm_fb_helper.h"
34		34
35	#define _wait_for(COND, MS, W) ({ \	35	#define _wait_for(COND, MS, W) ({ \
36	unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \	36	unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
37	int ret__ = 0; \	37	int ret__ = 0; \
38	while (!(COND)) { \	38	while (!(COND)) { \
39	if (time_after(jiffies, timeout__)) { \	39	if (time_after(jiffies, timeout__)) { \
40	ret__ = -ETIMEDOUT; \	40	ret__ = -ETIMEDOUT; \
41	break; \	41	break; \
42	} \	42	} \
43	if (W && drm_can_sleep()) msleep(W); \	43	if (W && drm_can_sleep()) msleep(W); \
44	} \	44	} \
45	ret__; \	45	ret__; \
46	})	46	})
47		47
48	#define wait_for(COND, MS) _wait_for(COND, MS, 1)	48	#define wait_for(COND, MS) _wait_for(COND, MS, 1)
49	#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)	49	#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
50		50
51	#define KHz(x) (1000*x)	51	#define KHz(x) (1000*x)
52	#define MHz(x) KHz(1000*x)	52	#define MHz(x) KHz(1000*x)
53		53
54	/*	54	/*
55	* Display related stuff	55	* Display related stuff
56	*/	56	*/
57		57
58	/* store information about an Ixxx DVO */	58	/* store information about an Ixxx DVO */
59	/* The i830->i865 use multiple DVOs with multiple i2cs */	59	/* The i830->i865 use multiple DVOs with multiple i2cs */
60	/* the i915, i945 have a single sDVO i2c bus - which is different */	60	/* the i915, i945 have a single sDVO i2c bus - which is different */
61	#define MAX_OUTPUTS 6	61	#define MAX_OUTPUTS 6
62	/* maximum connectors per crtcs in the mode set */	62	/* maximum connectors per crtcs in the mode set */
63	#define INTELFB_CONN_LIMIT 4	63	#define INTELFB_CONN_LIMIT 4
64		64
65	#define INTEL_I2C_BUS_DVO 1	65	#define INTEL_I2C_BUS_DVO 1
66	#define INTEL_I2C_BUS_SDVO 2	66	#define INTEL_I2C_BUS_SDVO 2
67		67
68	/* these are outputs from the chip - integrated only	68	/* these are outputs from the chip - integrated only
69	external chips are via DVO or SDVO output */	69	external chips are via DVO or SDVO output */
70	#define INTEL_OUTPUT_UNUSED 0	70	#define INTEL_OUTPUT_UNUSED 0
71	#define INTEL_OUTPUT_ANALOG 1	71	#define INTEL_OUTPUT_ANALOG 1
72	#define INTEL_OUTPUT_DVO 2	72	#define INTEL_OUTPUT_DVO 2
73	#define INTEL_OUTPUT_SDVO 3	73	#define INTEL_OUTPUT_SDVO 3
74	#define INTEL_OUTPUT_LVDS 4	74	#define INTEL_OUTPUT_LVDS 4
75	#define INTEL_OUTPUT_TVOUT 5	75	#define INTEL_OUTPUT_TVOUT 5
76	#define INTEL_OUTPUT_HDMI 6	76	#define INTEL_OUTPUT_HDMI 6
77	#define INTEL_OUTPUT_DISPLAYPORT 7	77	#define INTEL_OUTPUT_DISPLAYPORT 7
78	#define INTEL_OUTPUT_EDP 8	78	#define INTEL_OUTPUT_EDP 8
79		79
80	/* Intel Pipe Clone Bit */	80	/* Intel Pipe Clone Bit */
81	#define INTEL_HDMIB_CLONE_BIT 1	81	#define INTEL_HDMIB_CLONE_BIT 1
82	#define INTEL_HDMIC_CLONE_BIT 2	82	#define INTEL_HDMIC_CLONE_BIT 2
83	#define INTEL_HDMID_CLONE_BIT 3	83	#define INTEL_HDMID_CLONE_BIT 3
84	#define INTEL_HDMIE_CLONE_BIT 4	84	#define INTEL_HDMIE_CLONE_BIT 4
85	#define INTEL_HDMIF_CLONE_BIT 5	85	#define INTEL_HDMIF_CLONE_BIT 5
86	#define INTEL_SDVO_NON_TV_CLONE_BIT 6	86	#define INTEL_SDVO_NON_TV_CLONE_BIT 6
87	#define INTEL_SDVO_TV_CLONE_BIT 7	87	#define INTEL_SDVO_TV_CLONE_BIT 7
88	#define INTEL_SDVO_LVDS_CLONE_BIT 8	88	#define INTEL_SDVO_LVDS_CLONE_BIT 8
89	#define INTEL_ANALOG_CLONE_BIT 9	89	#define INTEL_ANALOG_CLONE_BIT 9
90	#define INTEL_TV_CLONE_BIT 10	90	#define INTEL_TV_CLONE_BIT 10
91	#define INTEL_DP_B_CLONE_BIT 11	91	#define INTEL_DP_B_CLONE_BIT 11
92	#define INTEL_DP_C_CLONE_BIT 12	92	#define INTEL_DP_C_CLONE_BIT 12
93	#define INTEL_DP_D_CLONE_BIT 13	93	#define INTEL_DP_D_CLONE_BIT 13
94	#define INTEL_LVDS_CLONE_BIT 14	94	#define INTEL_LVDS_CLONE_BIT 14
95	#define INTEL_DVO_TMDS_CLONE_BIT 15	95	#define INTEL_DVO_TMDS_CLONE_BIT 15
96	#define INTEL_DVO_LVDS_CLONE_BIT 16	96	#define INTEL_DVO_LVDS_CLONE_BIT 16
97	#define INTEL_EDP_CLONE_BIT 17	97	#define INTEL_EDP_CLONE_BIT 17
98		98
99	#define INTEL_DVO_CHIP_NONE 0	99	#define INTEL_DVO_CHIP_NONE 0
100	#define INTEL_DVO_CHIP_LVDS 1	100	#define INTEL_DVO_CHIP_LVDS 1
101	#define INTEL_DVO_CHIP_TMDS 2	101	#define INTEL_DVO_CHIP_TMDS 2
102	#define INTEL_DVO_CHIP_TVOUT 4	102	#define INTEL_DVO_CHIP_TVOUT 4
103		103
104	/* drm_display_mode->private_flags */	104	/* drm_display_mode->private_flags */
105	#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)	105	#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
106	#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)	106	#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
107	#define INTEL_MODE_DP_FORCE_6BPC (0x10)	107	#define INTEL_MODE_DP_FORCE_6BPC (0x10)
108		108
109	static inline void	109	static inline void
110	intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,	110	intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
111	int multiplier)	111	int multiplier)
112	{	112	{
113	mode->clock *= multiplier;	113	mode->clock *= multiplier;
114	mode->private_flags \|= multiplier;	114	mode->private_flags \|= multiplier;
115	}	115	}
116		116
117	static inline int	117	static inline int
118	intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)	118	intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
119	{	119	{
120	return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;	120	return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
121	}	121	}
122		122
123	struct intel_framebuffer {	123	struct intel_framebuffer {
124	struct drm_framebuffer base;	124	struct drm_framebuffer base;
125	struct drm_i915_gem_object *obj;	125	struct drm_i915_gem_object *obj;
126	};	126	};
127		127
128	struct intel_fbdev {	128	struct intel_fbdev {
129	struct drm_fb_helper helper;	129	struct drm_fb_helper helper;
130	struct intel_framebuffer ifb;	130	struct intel_framebuffer ifb;
131	struct list_head fbdev_list;	131	struct list_head fbdev_list;
132	struct drm_display_mode *our_mode;	132	struct drm_display_mode *our_mode;
133	};	133	};
134		134
135	struct intel_encoder {	135	struct intel_encoder {
136	struct drm_encoder base;	136	struct drm_encoder base;
137	int type;	137	int type;
138	bool needs_tv_clock;	138	bool needs_tv_clock;
139	void (hot_plug)(struct intel_encoder );	139	void (hot_plug)(struct intel_encoder );
140	int crtc_mask;	140	int crtc_mask;
141	int clone_mask;	141	int clone_mask;
142	};	142	};
143		143
144	struct intel_connector {	144	struct intel_connector {
145	struct drm_connector base;	145	struct drm_connector base;
146	struct intel_encoder *encoder;	146	struct intel_encoder *encoder;
147	};	147	};
148		148
149	struct intel_crtc {	149	struct intel_crtc {
150	struct drm_crtc base;	150	struct drm_crtc base;
151	enum pipe pipe;	151	enum pipe pipe;
152	enum plane plane;	152	enum plane plane;
153	u8 lut_r[256], lut_g[256], lut_b[256];	153	u8 lut_r[256], lut_g[256], lut_b[256];
154	int dpms_mode;	154	int dpms_mode;
155	bool active; /* is the crtc on? independent of the dpms mode */	155	bool active; /* is the crtc on? independent of the dpms mode */
156	bool busy; /* is scanout buffer being updated frequently? */	156	bool busy; /* is scanout buffer being updated frequently? */
157	struct timer_list idle_timer;	157	struct timer_list idle_timer;
158	bool lowfreq_avail;	158	bool lowfreq_avail;
159	struct intel_overlay *overlay;	159	struct intel_overlay *overlay;
160	struct intel_unpin_work *unpin_work;	160	struct intel_unpin_work *unpin_work;
161	int fdi_lanes;	161	int fdi_lanes;
162		162
163	struct drm_i915_gem_object *cursor_bo;	163	struct drm_i915_gem_object *cursor_bo;
164	uint32_t cursor_addr;	164	uint32_t cursor_addr;
165	int16_t cursor_x, cursor_y;	165	int16_t cursor_x, cursor_y;
166	int16_t cursor_width, cursor_height;	166	int16_t cursor_width, cursor_height;
167	bool cursor_visible;	167	bool cursor_visible;
168	unsigned int bpp;	168	unsigned int bpp;
169		169
170	bool no_pll; /* tertiary pipe for IVB */	170	bool no_pll; /* tertiary pipe for IVB */
171	bool use_pll_a;	171	bool use_pll_a;
172	};	172	};
173		173
174	struct intel_plane {	174	struct intel_plane {
175	struct drm_plane base;	175	struct drm_plane base;
176	enum pipe pipe;	176	enum pipe pipe;
177	struct drm_i915_gem_object *obj;	177	struct drm_i915_gem_object *obj;
178	bool primary_disabled;	178	bool primary_disabled;
179	int max_downscale;	179	int max_downscale;
180	u32 lut_r[1024], lut_g[1024], lut_b[1024];	180	u32 lut_r[1024], lut_g[1024], lut_b[1024];
181	void (update_plane)(struct drm_plane plane,	181	void (update_plane)(struct drm_plane plane,
182	struct drm_framebuffer *fb,	182	struct drm_framebuffer *fb,
183	struct drm_i915_gem_object *obj,	183	struct drm_i915_gem_object *obj,
184	int crtc_x, int crtc_y,	184	int crtc_x, int crtc_y,
185	unsigned int crtc_w, unsigned int crtc_h,	185	unsigned int crtc_w, unsigned int crtc_h,
186	uint32_t x, uint32_t y,	186	uint32_t x, uint32_t y,
187	uint32_t src_w, uint32_t src_h);	187	uint32_t src_w, uint32_t src_h);
188	void (disable_plane)(struct drm_plane plane);	188	void (disable_plane)(struct drm_plane plane);
189	int (update_colorkey)(struct drm_plane plane,	189	int (update_colorkey)(struct drm_plane plane,
190	struct drm_intel_sprite_colorkey *key);	190	struct drm_intel_sprite_colorkey *key);
191	void (get_colorkey)(struct drm_plane plane,	191	void (get_colorkey)(struct drm_plane plane,
192	struct drm_intel_sprite_colorkey *key);	192	struct drm_intel_sprite_colorkey *key);
193	};	193	};
194		194
195	#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)	195	#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
196	#define to_intel_connector(x) container_of(x, struct intel_connector, base)	196	#define to_intel_connector(x) container_of(x, struct intel_connector, base)
197	#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)	197	#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
198	#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)	198	#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
199	#define to_intel_plane(x) container_of(x, struct intel_plane, base)	199	#define to_intel_plane(x) container_of(x, struct intel_plane, base)
200		200
201	#define DIP_HEADER_SIZE 5	201	#define DIP_HEADER_SIZE 5
202		202
203	#define DIP_TYPE_AVI 0x82	203	#define DIP_TYPE_AVI 0x82
204	#define DIP_VERSION_AVI 0x2	204	#define DIP_VERSION_AVI 0x2
205	#define DIP_LEN_AVI 13	205	#define DIP_LEN_AVI 13
206		206
207	#define DIP_TYPE_SPD 0x83	207	#define DIP_TYPE_SPD 0x83
208	#define DIP_VERSION_SPD 0x1	208	#define DIP_VERSION_SPD 0x1
209	#define DIP_LEN_SPD 25	209	#define DIP_LEN_SPD 25
210	#define DIP_SPD_UNKNOWN 0	210	#define DIP_SPD_UNKNOWN 0
211	#define DIP_SPD_DSTB 0x1	211	#define DIP_SPD_DSTB 0x1
212	#define DIP_SPD_DVDP 0x2	212	#define DIP_SPD_DVDP 0x2
213	#define DIP_SPD_DVHS 0x3	213	#define DIP_SPD_DVHS 0x3
214	#define DIP_SPD_HDDVR 0x4	214	#define DIP_SPD_HDDVR 0x4
215	#define DIP_SPD_DVC 0x5	215	#define DIP_SPD_DVC 0x5
216	#define DIP_SPD_DSC 0x6	216	#define DIP_SPD_DSC 0x6
217	#define DIP_SPD_VCD 0x7	217	#define DIP_SPD_VCD 0x7
218	#define DIP_SPD_GAME 0x8	218	#define DIP_SPD_GAME 0x8
219	#define DIP_SPD_PC 0x9	219	#define DIP_SPD_PC 0x9
220	#define DIP_SPD_BD 0xa	220	#define DIP_SPD_BD 0xa
221	#define DIP_SPD_SCD 0xb	221	#define DIP_SPD_SCD 0xb
222		222
223	struct dip_infoframe {	223	struct dip_infoframe {
224	uint8_t type; /* HB0 */	224	uint8_t type; /* HB0 */
225	uint8_t ver; /* HB1 */	225	uint8_t ver; /* HB1 */
226	uint8_t len; /* HB2 - body len, not including checksum */	226	uint8_t len; /* HB2 - body len, not including checksum */
227	uint8_t ecc; /* Header ECC */	227	uint8_t ecc; /* Header ECC */
228	uint8_t checksum; /* PB0 */	228	uint8_t checksum; /* PB0 */
229	union {	229	union {
230	struct {	230	struct {
231	/* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */	231	/* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
232	uint8_t Y_A_B_S;	232	uint8_t Y_A_B_S;
233	/* PB2 - C 7:6, M 5:4, R 3:0 */	233	/* PB2 - C 7:6, M 5:4, R 3:0 */
234	uint8_t C_M_R;	234	uint8_t C_M_R;
235	/* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */	235	/* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
236	uint8_t ITC_EC_Q_SC;	236	uint8_t ITC_EC_Q_SC;
237	/* PB4 - VIC 6:0 */	237	/* PB4 - VIC 6:0 */
238	uint8_t VIC;	238	uint8_t VIC;
239	/* PB5 - PR 3:0 */	239	/* PB5 - PR 3:0 */
240	uint8_t PR;	240	uint8_t PR;
241	/* PB6 to PB13 */	241	/* PB6 to PB13 */
242	uint16_t top_bar_end;	242	uint16_t top_bar_end;
243	uint16_t bottom_bar_start;	243	uint16_t bottom_bar_start;
244	uint16_t left_bar_end;	244	uint16_t left_bar_end;
245	uint16_t right_bar_start;	245	uint16_t right_bar_start;
246	} avi;	246	} avi;
247	struct {	247	struct {
248	uint8_t vn[8];	248	uint8_t vn[8];
249	uint8_t pd[16];	249	uint8_t pd[16];
250	uint8_t sdi;	250	uint8_t sdi;
251	} spd;	251	} spd;
252	uint8_t payload[27];	252	uint8_t payload[27];
253	} __attribute__ ((packed)) body;	253	} __attribute__ ((packed)) body;
254	} __attribute__((packed));	254	} __attribute__((packed));
255		255
256	static inline struct drm_crtc *	256	static inline struct drm_crtc *
257	intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)	257	intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
258	{	258	{
259	struct drm_i915_private *dev_priv = dev->dev_private;	259	struct drm_i915_private *dev_priv = dev->dev_private;
260	return dev_priv->pipe_to_crtc_mapping[pipe];	260	return dev_priv->pipe_to_crtc_mapping[pipe];
261	}	261	}
262		262
263	static inline struct drm_crtc *	263	static inline struct drm_crtc *
264	intel_get_crtc_for_plane(struct drm_device *dev, int plane)	264	intel_get_crtc_for_plane(struct drm_device *dev, int plane)
265	{	265	{
266	struct drm_i915_private *dev_priv = dev->dev_private;	266	struct drm_i915_private *dev_priv = dev->dev_private;
267	return dev_priv->plane_to_crtc_mapping[plane];	267	return dev_priv->plane_to_crtc_mapping[plane];
268	}	268	}
269		269
270	struct intel_unpin_work {	270	struct intel_unpin_work {
271	struct work_struct work;	271	struct work_struct work;
272	struct drm_device *dev;	272	struct drm_device *dev;
273	struct drm_i915_gem_object *old_fb_obj;	273	struct drm_i915_gem_object *old_fb_obj;
274	struct drm_i915_gem_object *pending_flip_obj;	274	struct drm_i915_gem_object *pending_flip_obj;
275	struct drm_pending_vblank_event *event;	275	struct drm_pending_vblank_event *event;
276	int pending;	276	int pending;
277	bool enable_stall_check;	277	bool enable_stall_check;
278	};	278	};
279		279
280	struct intel_fbc_work {	280	struct intel_fbc_work {
281	struct delayed_work work;	281	struct delayed_work work;
282	struct drm_crtc *crtc;	282	struct drm_crtc *crtc;
283	struct drm_framebuffer *fb;	283	struct drm_framebuffer *fb;
284	int interval;	284	int interval;
285	};	285	};
286		286
287	int intel_ddc_get_modes(struct drm_connector c, struct i2c_adapter adapter);	287	int intel_ddc_get_modes(struct drm_connector c, struct i2c_adapter adapter);
288	extern bool intel_ddc_probe(struct intel_encoder *intel_encoder, int ddc_bus);	288	extern bool intel_ddc_probe(struct intel_encoder *intel_encoder, int ddc_bus);
289		289
290	extern void intel_attach_force_audio_property(struct drm_connector *connector);	290	extern void intel_attach_force_audio_property(struct drm_connector *connector);
291	extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);	291	extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
292		292
293	extern void intel_crt_init(struct drm_device *dev);	293	extern void intel_crt_init(struct drm_device *dev);
294	extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg);	294	extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg);
295	void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);	295	void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
296	extern bool intel_sdvo_init(struct drm_device *dev, int output_device);	296	extern bool intel_sdvo_init(struct drm_device *dev, int output_device);
297	extern void intel_dvo_init(struct drm_device *dev);	297	extern void intel_dvo_init(struct drm_device *dev);
298	extern void intel_tv_init(struct drm_device *dev);	298	extern void intel_tv_init(struct drm_device *dev);
299	extern void intel_mark_busy(struct drm_device *dev,	299	extern void intel_mark_busy(struct drm_device *dev,
300	struct drm_i915_gem_object *obj);	300	struct drm_i915_gem_object *obj);
301	extern bool intel_lvds_init(struct drm_device *dev);	301	extern bool intel_lvds_init(struct drm_device *dev);
302	extern void intel_dp_init(struct drm_device *dev, int dp_reg);	302	extern void intel_dp_init(struct drm_device *dev, int dp_reg);
303	void	303	void
304	intel_dp_set_m_n(struct drm_crtc crtc, struct drm_display_mode mode,	304	intel_dp_set_m_n(struct drm_crtc crtc, struct drm_display_mode mode,
305	struct drm_display_mode *adjusted_mode);	305	struct drm_display_mode *adjusted_mode);
306	extern bool intel_dpd_is_edp(struct drm_device *dev);	306	extern bool intel_dpd_is_edp(struct drm_device *dev);
307	extern void intel_edp_link_config(struct intel_encoder , int , int *);	307	extern void intel_edp_link_config(struct intel_encoder , int , int *);
308	extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);	308	extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
309	extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);	309	extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
310		310
311	/* intel_panel.c */	311	/* intel_panel.c */
312	extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,	312	extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
313	struct drm_display_mode *adjusted_mode);	313	struct drm_display_mode *adjusted_mode);
314	extern void intel_pch_panel_fitting(struct drm_device *dev,	314	extern void intel_pch_panel_fitting(struct drm_device *dev,
315	int fitting_mode,	315	int fitting_mode,
316	struct drm_display_mode *mode,	316	struct drm_display_mode *mode,
317	struct drm_display_mode *adjusted_mode);	317	struct drm_display_mode *adjusted_mode);
318	extern u32 intel_panel_get_max_backlight(struct drm_device *dev);	318	extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
319	extern u32 intel_panel_get_backlight(struct drm_device *dev);	319	extern u32 intel_panel_get_backlight(struct drm_device *dev);
320	extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);	320	extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
321	extern int intel_panel_setup_backlight(struct drm_device *dev);	321	extern int intel_panel_setup_backlight(struct drm_device *dev);
322	extern void intel_panel_enable_backlight(struct drm_device *dev);	322	extern void intel_panel_enable_backlight(struct drm_device *dev);
323	extern void intel_panel_disable_backlight(struct drm_device *dev);	323	extern void intel_panel_disable_backlight(struct drm_device *dev);
324	extern void intel_panel_destroy_backlight(struct drm_device *dev);	324	extern void intel_panel_destroy_backlight(struct drm_device *dev);
325	extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);	325	extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
326		326
327	extern void intel_crtc_load_lut(struct drm_crtc *crtc);	327	extern void intel_crtc_load_lut(struct drm_crtc *crtc);
328	extern void intel_encoder_prepare(struct drm_encoder *encoder);	328	extern void intel_encoder_prepare(struct drm_encoder *encoder);
329	extern void intel_encoder_commit(struct drm_encoder *encoder);	329	extern void intel_encoder_commit(struct drm_encoder *encoder);
330	extern void intel_encoder_destroy(struct drm_encoder *encoder);	330	extern void intel_encoder_destroy(struct drm_encoder *encoder);
331		331
332	static inline struct intel_encoder intel_attached_encoder(struct drm_connector connector)	332	static inline struct intel_encoder intel_attached_encoder(struct drm_connector connector)
333	{	333	{
334	return to_intel_connector(connector)->encoder;	334	return to_intel_connector(connector)->encoder;
335	}	335	}
336		336
337	extern void intel_connector_attach_encoder(struct intel_connector *connector,	337	extern void intel_connector_attach_encoder(struct intel_connector *connector,
338	struct intel_encoder *encoder);	338	struct intel_encoder *encoder);
339	extern struct drm_encoder intel_best_encoder(struct drm_connector connector);	339	extern struct drm_encoder intel_best_encoder(struct drm_connector connector);
340		340
341	extern struct drm_display_mode intel_crtc_mode_get(struct drm_device dev,	341	extern struct drm_display_mode intel_crtc_mode_get(struct drm_device dev,
342	struct drm_crtc *crtc);	342	struct drm_crtc *crtc);
343	int intel_get_pipe_from_crtc_id(struct drm_device dev, void data,	343	int intel_get_pipe_from_crtc_id(struct drm_device dev, void data,
344	struct drm_file *file_priv);	344	struct drm_file *file_priv);
345	extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);	345	extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
346	extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);	346	extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
347		347
348	struct intel_load_detect_pipe {	348	struct intel_load_detect_pipe {
349	struct drm_framebuffer *release_fb;	349	struct drm_framebuffer *release_fb;
350	bool load_detect_temp;	350	bool load_detect_temp;
351	int dpms_mode;	351	int dpms_mode;
352	};	352	};
353	extern bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,	353	extern bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
354	struct drm_connector *connector,	354	struct drm_connector *connector,
355	struct drm_display_mode *mode,	355	struct drm_display_mode *mode,
356	struct intel_load_detect_pipe *old);	356	struct intel_load_detect_pipe *old);
357	extern void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,	357	extern void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
358	struct drm_connector *connector,	358	struct drm_connector *connector,
359	struct intel_load_detect_pipe *old);	359	struct intel_load_detect_pipe *old);
360		360
361	extern void intelfb_restore(void);	361	extern void intelfb_restore(void);
362	extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,	362	extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
363	u16 blue, int regno);	363	u16 blue, int regno);
364	extern void intel_crtc_fb_gamma_get(struct drm_crtc crtc, u16 red, u16 *green,	364	extern void intel_crtc_fb_gamma_get(struct drm_crtc crtc, u16 red, u16 *green,
365	u16 *blue, int regno);	365	u16 *blue, int regno);
366	extern void intel_enable_clock_gating(struct drm_device *dev);	366	extern void intel_enable_clock_gating(struct drm_device *dev);
367	extern void ironlake_enable_drps(struct drm_device *dev);	367	extern void ironlake_enable_drps(struct drm_device *dev);
368	extern void ironlake_disable_drps(struct drm_device *dev);	368	extern void ironlake_disable_drps(struct drm_device *dev);
369	extern void gen6_enable_rps(struct drm_i915_private *dev_priv);	369	extern void gen6_enable_rps(struct drm_i915_private *dev_priv);
370	extern void gen6_update_ring_freq(struct drm_i915_private *dev_priv);	370	extern void gen6_update_ring_freq(struct drm_i915_private *dev_priv);
371	extern void gen6_disable_rps(struct drm_device *dev);	371	extern void gen6_disable_rps(struct drm_device *dev);
372	extern void intel_init_emon(struct drm_device *dev);	372	extern void intel_init_emon(struct drm_device *dev);
373		373
374	extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,	374	extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
375	struct drm_i915_gem_object *obj,	375	struct drm_i915_gem_object *obj,
376	struct intel_ring_buffer *pipelined);	376	struct intel_ring_buffer *pipelined);
377	extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);	377	extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
378		378
379	extern int intel_framebuffer_init(struct drm_device *dev,	379	extern int intel_framebuffer_init(struct drm_device *dev,
380	struct intel_framebuffer *ifb,	380	struct intel_framebuffer *ifb,
381	struct drm_mode_fb_cmd2 *mode_cmd,	381	struct drm_mode_fb_cmd2 *mode_cmd,
382	struct drm_i915_gem_object *obj);	382	struct drm_i915_gem_object *obj);
383	extern int intel_fbdev_init(struct drm_device *dev);	383	extern int intel_fbdev_init(struct drm_device *dev);
384	extern void intel_fbdev_fini(struct drm_device *dev);	384	extern void intel_fbdev_fini(struct drm_device *dev);
385		385	extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
386	extern void intel_prepare_page_flip(struct drm_device *dev, int plane);	386	extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
387	extern void intel_finish_page_flip(struct drm_device *dev, int pipe);	387	extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
388	extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);	388	extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
389		389
390	extern void intel_setup_overlay(struct drm_device *dev);	390	extern void intel_setup_overlay(struct drm_device *dev);
391	extern void intel_cleanup_overlay(struct drm_device *dev);	391	extern void intel_cleanup_overlay(struct drm_device *dev);
392	extern int intel_overlay_switch_off(struct intel_overlay *overlay);	392	extern int intel_overlay_switch_off(struct intel_overlay *overlay);
393	extern int intel_overlay_put_image(struct drm_device dev, void data,	393	extern int intel_overlay_put_image(struct drm_device dev, void data,
394	struct drm_file *file_priv);	394	struct drm_file *file_priv);
395	extern int intel_overlay_attrs(struct drm_device dev, void data,	395	extern int intel_overlay_attrs(struct drm_device dev, void data,
396	struct drm_file *file_priv);	396	struct drm_file *file_priv);
397		397
398	extern void intel_fb_output_poll_changed(struct drm_device *dev);	398	extern void intel_fb_output_poll_changed(struct drm_device *dev);
399	extern void intel_fb_restore_mode(struct drm_device *dev);	399	extern void intel_fb_restore_mode(struct drm_device *dev);
400		400
401	extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,	401	extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
402	bool state);	402	bool state);
403	#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)	403	#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
404	#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)	404	#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
405		405
406	extern void intel_init_clock_gating(struct drm_device *dev);	406	extern void intel_init_clock_gating(struct drm_device *dev);
407	extern void intel_write_eld(struct drm_encoder *encoder,	407	extern void intel_write_eld(struct drm_encoder *encoder,
408	struct drm_display_mode *mode);	408	struct drm_display_mode *mode);
409	extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);	409	extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
410		410
411	/* For use by IVB LP watermark workaround in intel_sprite.c */	411	/* For use by IVB LP watermark workaround in intel_sprite.c */
412	extern void sandybridge_update_wm(struct drm_device *dev);	412	extern void sandybridge_update_wm(struct drm_device *dev);
413	extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,	413	extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
414	uint32_t sprite_width,	414	uint32_t sprite_width,
415	int pixel_size);	415	int pixel_size);
416		416
417	extern int intel_sprite_set_colorkey(struct drm_device dev, void data,	417	extern int intel_sprite_set_colorkey(struct drm_device dev, void data,
418	struct drm_file *file_priv);	418	struct drm_file *file_priv);
419	extern int intel_sprite_get_colorkey(struct drm_device dev, void data,	419	extern int intel_sprite_get_colorkey(struct drm_device dev, void data,
420	struct drm_file *file_priv);	420	struct drm_file *file_priv);
421		421
422	#endif /* __INTEL_DRV_H__ */	422	#endif /* __INTEL_DRV_H__ */
423		423

drivers/gpu/drm/i915/intel_fb.c

Diff comments View file @ 0a03726

 /*
  * Copyright © 2007 David Airlie
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice (including the next
  * paragraph) shall be included in all copies or substantial portions of the
  * Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  *
  * Authors:
  *     David Airlie
  */
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/string.h>
 #include <linux/mm.h>
 #include <linux/tty.h>
 #include <linux/sysrq.h>
 #include <linux/delay.h>
 #include <linux/fb.h>
 #include <linux/init.h>
 #include <linux/vga_switcheroo.h>
 #include "drmP.h"
 #include "drm.h"
 #include "drm_crtc.h"
 #include "drm_fb_helper.h"
 #include "intel_drv.h"
 #include "i915_drm.h"
 #include "i915_drv.h"
 static struct fb_ops intelfb_ops = {
 	.owner = THIS_MODULE,
 	.fb_check_var = drm_fb_helper_check_var,
 	.fb_set_par = drm_fb_helper_set_par,
 	.fb_fillrect = cfb_fillrect,
 	.fb_copyarea = cfb_copyarea,
 	.fb_imageblit = cfb_imageblit,
 	.fb_pan_display = drm_fb_helper_pan_display,
 	.fb_blank = drm_fb_helper_blank,
 	.fb_setcmap = drm_fb_helper_setcmap,
 	.fb_debug_enter = drm_fb_helper_debug_enter,
 	.fb_debug_leave = drm_fb_helper_debug_leave,
 };
 static int intelfb_create(struct intel_fbdev *ifbdev,
 			  struct drm_fb_helper_surface_size *sizes)
 {
 	struct drm_device *dev = ifbdev->helper.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct fb_info *info;
 	struct drm_framebuffer *fb;
 	struct drm_mode_fb_cmd2 mode_cmd;
 	struct drm_i915_gem_object *obj;
 	struct device *device = &dev->pdev->dev;
 	int size, ret;
 	/* we don't do packed 24bpp */
 	if (sizes->surface_bpp == 24)
 		sizes->surface_bpp = 32;
 	mode_cmd.width = sizes->surface_width;
 	mode_cmd.height = sizes->surface_height;
 	mode_cmd.pitches[0] = ALIGN(mode_cmd.width * ((sizes->surface_bpp + 7) /
 						      8), 64);
 	mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
 							  sizes->surface_depth);
 	size = mode_cmd.pitches[0] * mode_cmd.height;
 	size = ALIGN(size, PAGE_SIZE);
 	obj = i915_gem_alloc_object(dev, size);
 	if (!obj) {
 		DRM_ERROR("failed to allocate framebuffer\n");
 		ret = -ENOMEM;
 		goto out;
 	}
 	mutex_lock(&dev->struct_mutex);
 	/* Flush everything out, we'll be doing GTT only from now on */
 	ret = intel_pin_and_fence_fb_obj(dev, obj, false);
 	if (ret) {
 		DRM_ERROR("failed to pin fb: %d\n", ret);
 		goto out_unref;
 	}
 	info = framebuffer_alloc(0, device);
 	if (!info) {
 		ret = -ENOMEM;
 		goto out_unpin;
 	}
 	info->par = ifbdev;
 	ret = intel_framebuffer_init(dev, &ifbdev->ifb, &mode_cmd, obj);
 	if (ret)
 		goto out_unpin;
 	fb = &ifbdev->ifb.base;
 	ifbdev->helper.fb = fb;
 	ifbdev->helper.fbdev = info;
 	strcpy(info->fix.id, "inteldrmfb");
 	info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT;
 	info->fbops = &intelfb_ops;
 	ret = fb_alloc_cmap(&info->cmap, 256, 0);
 	if (ret) {
 		ret = -ENOMEM;
 		goto out_unpin;
 	}
 	/* setup aperture base/size for vesafb takeover */
 	info->apertures = alloc_apertures(1);
 	if (!info->apertures) {
 		ret = -ENOMEM;
 		goto out_unpin;
 	}
 	info->apertures->ranges[0].base = dev->mode_config.fb_base;
 	info->apertures->ranges[0].size =
 		dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
 	info->fix.smem_start = dev->mode_config.fb_base + obj->gtt_offset;
 	info->fix.smem_len = size;
 	info->screen_base = ioremap_wc(dev->agp->base + obj->gtt_offset, size);
 	if (!info->screen_base) {
 		ret = -ENOSPC;
 		goto out_unpin;
 	}
 	info->screen_size = size;
 //	memset(info->screen_base, 0, size);
 	drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth);
 	drm_fb_helper_fill_var(info, &ifbdev->helper, sizes->fb_width, sizes->fb_height);
 	/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
 	DRM_DEBUG_KMS("allocated %dx%d fb: 0x%08x, bo %p\n",
 		      fb->width, fb->height,
 		      obj->gtt_offset, obj);
 	mutex_unlock(&dev->struct_mutex);
 	vga_switcheroo_client_fb_set(dev->pdev, info);
 	return 0;
 out_unpin:
 	i915_gem_object_unpin(obj);
 out_unref:
 	drm_gem_object_unreference(&obj->base);
 	mutex_unlock(&dev->struct_mutex);
 out:
 	return ret;
 }
 static int intel_fb_find_or_create_single(struct drm_fb_helper *helper,
 					  struct drm_fb_helper_surface_size *sizes)
 {
 	struct intel_fbdev *ifbdev = (struct intel_fbdev *)helper;
 	int new_fb = 0;
 	int ret;
 	if (!helper->fb) {
 		ret = intelfb_create(ifbdev, sizes);
 		if (ret)
 			return ret;
 		new_fb = 1;
 	}
 	return new_fb;
 }
 static struct drm_fb_helper_funcs intel_fb_helper_funcs = {
 	.gamma_set = intel_crtc_fb_gamma_set,
 	.gamma_get = intel_crtc_fb_gamma_get,
 	.fb_probe = intel_fb_find_or_create_single,
 };
 static void intel_fbdev_destroy(struct drm_device *dev,
 				struct intel_fbdev *ifbdev)
 {
 	struct fb_info *info;
 	struct intel_framebuffer *ifb = &ifbdev->ifb;
 	if (ifbdev->helper.fbdev) {
 		info = ifbdev->helper.fbdev;
 		unregister_framebuffer(info);
 		iounmap(info->screen_base);
 		if (info->cmap.len)
 			fb_dealloc_cmap(&info->cmap);
 		framebuffer_release(info);
 	}
 	drm_fb_helper_fini(&ifbdev->helper);
 	drm_framebuffer_cleanup(&ifb->base);
 	if (ifb->obj) {
 		drm_gem_object_unreference_unlocked(&ifb->obj->base);
 		ifb->obj = NULL;
 	}
 }
 int intel_fbdev_init(struct drm_device *dev)
 {
 	struct intel_fbdev *ifbdev;
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	int ret;
 	ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL);
 	if (!ifbdev)
 		return -ENOMEM;
 	dev_priv->fbdev = ifbdev;
 	ifbdev->helper.funcs = &intel_fb_helper_funcs;
 	ret = drm_fb_helper_init(dev, &ifbdev->helper,
 				 dev_priv->num_pipe,
 				 INTELFB_CONN_LIMIT);
 	if (ret) {
 		kfree(ifbdev);
 		return ret;
 	}
 	drm_fb_helper_single_add_all_connectors(&ifbdev->helper);
 	drm_fb_helper_initial_config(&ifbdev->helper, 32);
 	return 0;
 }
 void intel_fbdev_fini(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	if (!dev_priv->fbdev)
 		return;
 	intel_fbdev_destroy(dev, dev_priv->fbdev);
 	kfree(dev_priv->fbdev);
 	dev_priv->fbdev = NULL;
 }
+void intel_fbdev_set_suspend(struct drm_device *dev, int state)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	if (!dev_priv->fbdev)
+		return;
+	fb_set_suspend(dev_priv->fbdev->helper.fbdev, state);
+}
 MODULE_LICENSE("GPL and additional rights");
 void intel_fb_output_poll_changed(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	drm_fb_helper_hotplug_event(&dev_priv->fbdev->helper);
 }
 void intel_fb_restore_mode(struct drm_device *dev)
 {
 	int ret;
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct drm_mode_config *config = &dev->mode_config;
 	struct drm_plane *plane;
 	ret = drm_fb_helper_restore_fbdev_mode(&dev_priv->fbdev->helper);
 	if (ret)
 		DRM_DEBUG("failed to restore crtc mode\n");
 	/* Be sure to shut off any planes that may be active */
 	list_for_each_entry(plane, &config->plane_list, head)
 		plane->funcs->disable_plane(plane);
 }