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Commit 0a2c986557b964453f8deeaf56f6d88bf3e65e92

Authored by Linus Torvalds
2 parents 2d0f2400a4 780dc9ba4e
Exists in master and in 6 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator 

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator:
  regulator: TPS65910: Fix VDD1/2 voltage selector count

Showing 2 changed files Inline Diff

drivers/regulator/tps65910-regulator.c
Diff comments   View file @ 0a2c986
1 /* 1 /*
2 * tps65910.c -- TI tps65910 2 * tps65910.c -- TI tps65910
3 * 3 *
4 * Copyright 2010 Texas Instruments Inc. 4 * Copyright 2010 Texas Instruments Inc.
5 * 5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk> 6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk> 7 * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify it 9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the 10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your 11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version. 12 * option) any later version.
13 * 13 *
14 */ 14 */
15 15
16 #include <linux/kernel.h> 16 #include <linux/kernel.h>
17 #include <linux/module.h> 17 #include <linux/module.h>
18 #include <linux/init.h> 18 #include <linux/init.h>
19 #include <linux/err.h> 19 #include <linux/err.h>
20 #include <linux/platform_device.h> 20 #include <linux/platform_device.h>
21 #include <linux/regulator/driver.h> 21 #include <linux/regulator/driver.h>
22 #include <linux/regulator/machine.h> 22 #include <linux/regulator/machine.h>
23 #include <linux/delay.h> 23 #include <linux/delay.h>
24 #include <linux/slab.h> 24 #include <linux/slab.h>
25 #include <linux/gpio.h> 25 #include <linux/gpio.h>
26 #include <linux/mfd/tps65910.h> 26 #include <linux/mfd/tps65910.h>
27 27
28 #define TPS65910_REG_VRTC 0 28 #define TPS65910_REG_VRTC 0
29 #define TPS65910_REG_VIO 1 29 #define TPS65910_REG_VIO 1
30 #define TPS65910_REG_VDD1 2 30 #define TPS65910_REG_VDD1 2
31 #define TPS65910_REG_VDD2 3 31 #define TPS65910_REG_VDD2 3
32 #define TPS65910_REG_VDD3 4 32 #define TPS65910_REG_VDD3 4
33 #define TPS65910_REG_VDIG1 5 33 #define TPS65910_REG_VDIG1 5
34 #define TPS65910_REG_VDIG2 6 34 #define TPS65910_REG_VDIG2 6
35 #define TPS65910_REG_VPLL 7 35 #define TPS65910_REG_VPLL 7
36 #define TPS65910_REG_VDAC 8 36 #define TPS65910_REG_VDAC 8
37 #define TPS65910_REG_VAUX1 9 37 #define TPS65910_REG_VAUX1 9
38 #define TPS65910_REG_VAUX2 10 38 #define TPS65910_REG_VAUX2 10
39 #define TPS65910_REG_VAUX33 11 39 #define TPS65910_REG_VAUX33 11
40 #define TPS65910_REG_VMMC 12 40 #define TPS65910_REG_VMMC 12
41 41
42 #define TPS65911_REG_VDDCTRL 4 42 #define TPS65911_REG_VDDCTRL 4
43 #define TPS65911_REG_LDO1 5 43 #define TPS65911_REG_LDO1 5
44 #define TPS65911_REG_LDO2 6 44 #define TPS65911_REG_LDO2 6
45 #define TPS65911_REG_LDO3 7 45 #define TPS65911_REG_LDO3 7
46 #define TPS65911_REG_LDO4 8 46 #define TPS65911_REG_LDO4 8
47 #define TPS65911_REG_LDO5 9 47 #define TPS65911_REG_LDO5 9
48 #define TPS65911_REG_LDO6 10 48 #define TPS65911_REG_LDO6 10
49 #define TPS65911_REG_LDO7 11 49 #define TPS65911_REG_LDO7 11
50 #define TPS65911_REG_LDO8 12 50 #define TPS65911_REG_LDO8 12
51 51
52 #define TPS65910_SUPPLY_STATE_ENABLED 0x1 52 #define TPS65910_SUPPLY_STATE_ENABLED 0x1
53 53
54 /* supported VIO voltages in milivolts */ 54 /* supported VIO voltages in milivolts */
55 static const u16 VIO_VSEL_table[] = { 55 static const u16 VIO_VSEL_table[] = {
56 1500, 1800, 2500, 3300, 56 1500, 1800, 2500, 3300,
57 }; 57 };
58 58
59 /* VSEL tables for TPS65910 specific LDOs and dcdc's */ 59 /* VSEL tables for TPS65910 specific LDOs and dcdc's */
60 60
61 /* supported VDD3 voltages in milivolts */ 61 /* supported VDD3 voltages in milivolts */
62 static const u16 VDD3_VSEL_table[] = { 62 static const u16 VDD3_VSEL_table[] = {
63 5000, 63 5000,
64 }; 64 };
65 65
66 /* supported VDIG1 voltages in milivolts */ 66 /* supported VDIG1 voltages in milivolts */
67 static const u16 VDIG1_VSEL_table[] = { 67 static const u16 VDIG1_VSEL_table[] = {
68 1200, 1500, 1800, 2700, 68 1200, 1500, 1800, 2700,
69 }; 69 };
70 70
71 /* supported VDIG2 voltages in milivolts */ 71 /* supported VDIG2 voltages in milivolts */
72 static const u16 VDIG2_VSEL_table[] = { 72 static const u16 VDIG2_VSEL_table[] = {
73 1000, 1100, 1200, 1800, 73 1000, 1100, 1200, 1800,
74 }; 74 };
75 75
76 /* supported VPLL voltages in milivolts */ 76 /* supported VPLL voltages in milivolts */
77 static const u16 VPLL_VSEL_table[] = { 77 static const u16 VPLL_VSEL_table[] = {
78 1000, 1100, 1800, 2500, 78 1000, 1100, 1800, 2500,
79 }; 79 };
80 80
81 /* supported VDAC voltages in milivolts */ 81 /* supported VDAC voltages in milivolts */
82 static const u16 VDAC_VSEL_table[] = { 82 static const u16 VDAC_VSEL_table[] = {
83 1800, 2600, 2800, 2850, 83 1800, 2600, 2800, 2850,
84 }; 84 };
85 85
86 /* supported VAUX1 voltages in milivolts */ 86 /* supported VAUX1 voltages in milivolts */
87 static const u16 VAUX1_VSEL_table[] = { 87 static const u16 VAUX1_VSEL_table[] = {
88 1800, 2500, 2800, 2850, 88 1800, 2500, 2800, 2850,
89 }; 89 };
90 90
91 /* supported VAUX2 voltages in milivolts */ 91 /* supported VAUX2 voltages in milivolts */
92 static const u16 VAUX2_VSEL_table[] = { 92 static const u16 VAUX2_VSEL_table[] = {
93 1800, 2800, 2900, 3300, 93 1800, 2800, 2900, 3300,
94 }; 94 };
95 95
96 /* supported VAUX33 voltages in milivolts */ 96 /* supported VAUX33 voltages in milivolts */
97 static const u16 VAUX33_VSEL_table[] = { 97 static const u16 VAUX33_VSEL_table[] = {
98 1800, 2000, 2800, 3300, 98 1800, 2000, 2800, 3300,
99 }; 99 };
100 100
101 /* supported VMMC voltages in milivolts */ 101 /* supported VMMC voltages in milivolts */
102 static const u16 VMMC_VSEL_table[] = { 102 static const u16 VMMC_VSEL_table[] = {
103 1800, 2800, 3000, 3300, 103 1800, 2800, 3000, 3300,
104 }; 104 };
105 105
106 struct tps_info { 106 struct tps_info {
107 const char *name; 107 const char *name;
108 unsigned min_uV; 108 unsigned min_uV;
109 unsigned max_uV; 109 unsigned max_uV;
110 u8 table_len; 110 u8 table_len;
111 const u16 *table; 111 const u16 *table;
112 }; 112 };
113 113
114 static struct tps_info tps65910_regs[] = { 114 static struct tps_info tps65910_regs[] = {
115 { 115 {
116 .name = "VRTC", 116 .name = "VRTC",
117 }, 117 },
118 { 118 {
119 .name = "VIO", 119 .name = "VIO",
120 .min_uV = 1500000, 120 .min_uV = 1500000,
121 .max_uV = 3300000, 121 .max_uV = 3300000,
122 .table_len = ARRAY_SIZE(VIO_VSEL_table), 122 .table_len = ARRAY_SIZE(VIO_VSEL_table),
123 .table = VIO_VSEL_table, 123 .table = VIO_VSEL_table,
124 }, 124 },
125 { 125 {
126 .name = "VDD1", 126 .name = "VDD1",
127 .min_uV = 600000, 127 .min_uV = 600000,
128 .max_uV = 4500000, 128 .max_uV = 4500000,
129 }, 129 },
130 { 130 {
131 .name = "VDD2", 131 .name = "VDD2",
132 .min_uV = 600000, 132 .min_uV = 600000,
133 .max_uV = 4500000, 133 .max_uV = 4500000,
134 }, 134 },
135 { 135 {
136 .name = "VDD3", 136 .name = "VDD3",
137 .min_uV = 5000000, 137 .min_uV = 5000000,
138 .max_uV = 5000000, 138 .max_uV = 5000000,
139 .table_len = ARRAY_SIZE(VDD3_VSEL_table), 139 .table_len = ARRAY_SIZE(VDD3_VSEL_table),
140 .table = VDD3_VSEL_table, 140 .table = VDD3_VSEL_table,
141 }, 141 },
142 { 142 {
143 .name = "VDIG1", 143 .name = "VDIG1",
144 .min_uV = 1200000, 144 .min_uV = 1200000,
145 .max_uV = 2700000, 145 .max_uV = 2700000,
146 .table_len = ARRAY_SIZE(VDIG1_VSEL_table), 146 .table_len = ARRAY_SIZE(VDIG1_VSEL_table),
147 .table = VDIG1_VSEL_table, 147 .table = VDIG1_VSEL_table,
148 }, 148 },
149 { 149 {
150 .name = "VDIG2", 150 .name = "VDIG2",
151 .min_uV = 1000000, 151 .min_uV = 1000000,
152 .max_uV = 1800000, 152 .max_uV = 1800000,
153 .table_len = ARRAY_SIZE(VDIG2_VSEL_table), 153 .table_len = ARRAY_SIZE(VDIG2_VSEL_table),
154 .table = VDIG2_VSEL_table, 154 .table = VDIG2_VSEL_table,
155 }, 155 },
156 { 156 {
157 .name = "VPLL", 157 .name = "VPLL",
158 .min_uV = 1000000, 158 .min_uV = 1000000,
159 .max_uV = 2500000, 159 .max_uV = 2500000,
160 .table_len = ARRAY_SIZE(VPLL_VSEL_table), 160 .table_len = ARRAY_SIZE(VPLL_VSEL_table),
161 .table = VPLL_VSEL_table, 161 .table = VPLL_VSEL_table,
162 }, 162 },
163 { 163 {
164 .name = "VDAC", 164 .name = "VDAC",
165 .min_uV = 1800000, 165 .min_uV = 1800000,
166 .max_uV = 2850000, 166 .max_uV = 2850000,
167 .table_len = ARRAY_SIZE(VDAC_VSEL_table), 167 .table_len = ARRAY_SIZE(VDAC_VSEL_table),
168 .table = VDAC_VSEL_table, 168 .table = VDAC_VSEL_table,
169 }, 169 },
170 { 170 {
171 .name = "VAUX1", 171 .name = "VAUX1",
172 .min_uV = 1800000, 172 .min_uV = 1800000,
173 .max_uV = 2850000, 173 .max_uV = 2850000,
174 .table_len = ARRAY_SIZE(VAUX1_VSEL_table), 174 .table_len = ARRAY_SIZE(VAUX1_VSEL_table),
175 .table = VAUX1_VSEL_table, 175 .table = VAUX1_VSEL_table,
176 }, 176 },
177 { 177 {
178 .name = "VAUX2", 178 .name = "VAUX2",
179 .min_uV = 1800000, 179 .min_uV = 1800000,
180 .max_uV = 3300000, 180 .max_uV = 3300000,
181 .table_len = ARRAY_SIZE(VAUX2_VSEL_table), 181 .table_len = ARRAY_SIZE(VAUX2_VSEL_table),
182 .table = VAUX2_VSEL_table, 182 .table = VAUX2_VSEL_table,
183 }, 183 },
184 { 184 {
185 .name = "VAUX33", 185 .name = "VAUX33",
186 .min_uV = 1800000, 186 .min_uV = 1800000,
187 .max_uV = 3300000, 187 .max_uV = 3300000,
188 .table_len = ARRAY_SIZE(VAUX33_VSEL_table), 188 .table_len = ARRAY_SIZE(VAUX33_VSEL_table),
189 .table = VAUX33_VSEL_table, 189 .table = VAUX33_VSEL_table,
190 }, 190 },
191 { 191 {
192 .name = "VMMC", 192 .name = "VMMC",
193 .min_uV = 1800000, 193 .min_uV = 1800000,
194 .max_uV = 3300000, 194 .max_uV = 3300000,
195 .table_len = ARRAY_SIZE(VMMC_VSEL_table), 195 .table_len = ARRAY_SIZE(VMMC_VSEL_table),
196 .table = VMMC_VSEL_table, 196 .table = VMMC_VSEL_table,
197 }, 197 },
198 }; 198 };
199 199
200 static struct tps_info tps65911_regs[] = { 200 static struct tps_info tps65911_regs[] = {
201 { 201 {
202 .name = "VIO", 202 .name = "VIO",
203 .min_uV = 1500000, 203 .min_uV = 1500000,
204 .max_uV = 3300000, 204 .max_uV = 3300000,
205 .table_len = ARRAY_SIZE(VIO_VSEL_table), 205 .table_len = ARRAY_SIZE(VIO_VSEL_table),
206 .table = VIO_VSEL_table, 206 .table = VIO_VSEL_table,
207 }, 207 },
208 { 208 {
209 .name = "VDD1", 209 .name = "VDD1",
210 .min_uV = 600000, 210 .min_uV = 600000,
211 .max_uV = 4500000, 211 .max_uV = 4500000,
212 }, 212 },
213 { 213 {
214 .name = "VDD2", 214 .name = "VDD2",
215 .min_uV = 600000, 215 .min_uV = 600000,
216 .max_uV = 4500000, 216 .max_uV = 4500000,
217 }, 217 },
218 { 218 {
219 .name = "VDDCTRL", 219 .name = "VDDCTRL",
220 .min_uV = 600000, 220 .min_uV = 600000,
221 .max_uV = 1400000, 221 .max_uV = 1400000,
222 }, 222 },
223 { 223 {
224 .name = "LDO1", 224 .name = "LDO1",
225 .min_uV = 1000000, 225 .min_uV = 1000000,
226 .max_uV = 3300000, 226 .max_uV = 3300000,
227 }, 227 },
228 { 228 {
229 .name = "LDO2", 229 .name = "LDO2",
230 .min_uV = 1000000, 230 .min_uV = 1000000,
231 .max_uV = 3300000, 231 .max_uV = 3300000,
232 }, 232 },
233 { 233 {
234 .name = "LDO3", 234 .name = "LDO3",
235 .min_uV = 1000000, 235 .min_uV = 1000000,
236 .max_uV = 3300000, 236 .max_uV = 3300000,
237 }, 237 },
238 { 238 {
239 .name = "LDO4", 239 .name = "LDO4",
240 .min_uV = 1000000, 240 .min_uV = 1000000,
241 .max_uV = 3300000, 241 .max_uV = 3300000,
242 }, 242 },
243 { 243 {
244 .name = "LDO5", 244 .name = "LDO5",
245 .min_uV = 1000000, 245 .min_uV = 1000000,
246 .max_uV = 3300000, 246 .max_uV = 3300000,
247 }, 247 },
248 { 248 {
249 .name = "LDO6", 249 .name = "LDO6",
250 .min_uV = 1000000, 250 .min_uV = 1000000,
251 .max_uV = 3300000, 251 .max_uV = 3300000,
252 }, 252 },
253 { 253 {
254 .name = "LDO7", 254 .name = "LDO7",
255 .min_uV = 1000000, 255 .min_uV = 1000000,
256 .max_uV = 3300000, 256 .max_uV = 3300000,
257 }, 257 },
258 { 258 {
259 .name = "LDO8", 259 .name = "LDO8",
260 .min_uV = 1000000, 260 .min_uV = 1000000,
261 .max_uV = 3300000, 261 .max_uV = 3300000,
262 }, 262 },
263 }; 263 };
264 264
265 struct tps65910_reg { 265 struct tps65910_reg {
266 struct regulator_desc *desc; 266 struct regulator_desc *desc;
267 struct tps65910 *mfd; 267 struct tps65910 *mfd;
268 struct regulator_dev **rdev; 268 struct regulator_dev **rdev;
269 struct tps_info **info; 269 struct tps_info **info;
270 struct mutex mutex; 270 struct mutex mutex;
271 int num_regulators; 271 int num_regulators;
272 int mode; 272 int mode;
273 int (*get_ctrl_reg)(int); 273 int (*get_ctrl_reg)(int);
274 }; 274 };
275 275
276 static inline int tps65910_read(struct tps65910_reg *pmic, u8 reg) 276 static inline int tps65910_read(struct tps65910_reg *pmic, u8 reg)
277 { 277 {
278 u8 val; 278 u8 val;
279 int err; 279 int err;
280 280
281 err = pmic->mfd->read(pmic->mfd, reg, 1, &val); 281 err = pmic->mfd->read(pmic->mfd, reg, 1, &val);
282 if (err) 282 if (err)
283 return err; 283 return err;
284 284
285 return val; 285 return val;
286 } 286 }
287 287
288 static inline int tps65910_write(struct tps65910_reg *pmic, u8 reg, u8 val) 288 static inline int tps65910_write(struct tps65910_reg *pmic, u8 reg, u8 val)
289 { 289 {
290 return pmic->mfd->write(pmic->mfd, reg, 1, &val); 290 return pmic->mfd->write(pmic->mfd, reg, 1, &val);
291 } 291 }
292 292
293 static int tps65910_modify_bits(struct tps65910_reg *pmic, u8 reg, 293 static int tps65910_modify_bits(struct tps65910_reg *pmic, u8 reg,
294 u8 set_mask, u8 clear_mask) 294 u8 set_mask, u8 clear_mask)
295 { 295 {
296 int err, data; 296 int err, data;
297 297
298 mutex_lock(&pmic->mutex); 298 mutex_lock(&pmic->mutex);
299 299
300 data = tps65910_read(pmic, reg); 300 data = tps65910_read(pmic, reg);
301 if (data < 0) { 301 if (data < 0) {
302 dev_err(pmic->mfd->dev, "Read from reg 0x%x failed\n", reg); 302 dev_err(pmic->mfd->dev, "Read from reg 0x%x failed\n", reg);
303 err = data; 303 err = data;
304 goto out; 304 goto out;
305 } 305 }
306 306
307 data &= ~clear_mask; 307 data &= ~clear_mask;
308 data |= set_mask; 308 data |= set_mask;
309 err = tps65910_write(pmic, reg, data); 309 err = tps65910_write(pmic, reg, data);
310 if (err) 310 if (err)
311 dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg); 311 dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg);
312 312
313 out: 313 out:
314 mutex_unlock(&pmic->mutex); 314 mutex_unlock(&pmic->mutex);
315 return err; 315 return err;
316 } 316 }
317 317
318 static int tps65910_reg_read(struct tps65910_reg *pmic, u8 reg) 318 static int tps65910_reg_read(struct tps65910_reg *pmic, u8 reg)
319 { 319 {
320 int data; 320 int data;
321 321
322 mutex_lock(&pmic->mutex); 322 mutex_lock(&pmic->mutex);
323 323
324 data = tps65910_read(pmic, reg); 324 data = tps65910_read(pmic, reg);
325 if (data < 0) 325 if (data < 0)
326 dev_err(pmic->mfd->dev, "Read from reg 0x%x failed\n", reg); 326 dev_err(pmic->mfd->dev, "Read from reg 0x%x failed\n", reg);
327 327
328 mutex_unlock(&pmic->mutex); 328 mutex_unlock(&pmic->mutex);
329 return data; 329 return data;
330 } 330 }
331 331
332 static int tps65910_reg_write(struct tps65910_reg *pmic, u8 reg, u8 val) 332 static int tps65910_reg_write(struct tps65910_reg *pmic, u8 reg, u8 val)
333 { 333 {
334 int err; 334 int err;
335 335
336 mutex_lock(&pmic->mutex); 336 mutex_lock(&pmic->mutex);
337 337
338 err = tps65910_write(pmic, reg, val); 338 err = tps65910_write(pmic, reg, val);
339 if (err < 0) 339 if (err < 0)
340 dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg); 340 dev_err(pmic->mfd->dev, "Write for reg 0x%x failed\n", reg);
341 341
342 mutex_unlock(&pmic->mutex); 342 mutex_unlock(&pmic->mutex);
343 return err; 343 return err;
344 } 344 }
345 345
346 static int tps65910_get_ctrl_register(int id) 346 static int tps65910_get_ctrl_register(int id)
347 { 347 {
348 switch (id) { 348 switch (id) {
349 case TPS65910_REG_VRTC: 349 case TPS65910_REG_VRTC:
350 return TPS65910_VRTC; 350 return TPS65910_VRTC;
351 case TPS65910_REG_VIO: 351 case TPS65910_REG_VIO:
352 return TPS65910_VIO; 352 return TPS65910_VIO;
353 case TPS65910_REG_VDD1: 353 case TPS65910_REG_VDD1:
354 return TPS65910_VDD1; 354 return TPS65910_VDD1;
355 case TPS65910_REG_VDD2: 355 case TPS65910_REG_VDD2:
356 return TPS65910_VDD2; 356 return TPS65910_VDD2;
357 case TPS65910_REG_VDD3: 357 case TPS65910_REG_VDD3:
358 return TPS65910_VDD3; 358 return TPS65910_VDD3;
359 case TPS65910_REG_VDIG1: 359 case TPS65910_REG_VDIG1:
360 return TPS65910_VDIG1; 360 return TPS65910_VDIG1;
361 case TPS65910_REG_VDIG2: 361 case TPS65910_REG_VDIG2:
362 return TPS65910_VDIG2; 362 return TPS65910_VDIG2;
363 case TPS65910_REG_VPLL: 363 case TPS65910_REG_VPLL:
364 return TPS65910_VPLL; 364 return TPS65910_VPLL;
365 case TPS65910_REG_VDAC: 365 case TPS65910_REG_VDAC:
366 return TPS65910_VDAC; 366 return TPS65910_VDAC;
367 case TPS65910_REG_VAUX1: 367 case TPS65910_REG_VAUX1:
368 return TPS65910_VAUX1; 368 return TPS65910_VAUX1;
369 case TPS65910_REG_VAUX2: 369 case TPS65910_REG_VAUX2:
370 return TPS65910_VAUX2; 370 return TPS65910_VAUX2;
371 case TPS65910_REG_VAUX33: 371 case TPS65910_REG_VAUX33:
372 return TPS65910_VAUX33; 372 return TPS65910_VAUX33;
373 case TPS65910_REG_VMMC: 373 case TPS65910_REG_VMMC:
374 return TPS65910_VMMC; 374 return TPS65910_VMMC;
375 default: 375 default:
376 return -EINVAL; 376 return -EINVAL;
377 } 377 }
378 } 378 }
379 379
380 static int tps65911_get_ctrl_register(int id) 380 static int tps65911_get_ctrl_register(int id)
381 { 381 {
382 switch (id) { 382 switch (id) {
383 case TPS65910_REG_VRTC: 383 case TPS65910_REG_VRTC:
384 return TPS65910_VRTC; 384 return TPS65910_VRTC;
385 case TPS65910_REG_VIO: 385 case TPS65910_REG_VIO:
386 return TPS65910_VIO; 386 return TPS65910_VIO;
387 case TPS65910_REG_VDD1: 387 case TPS65910_REG_VDD1:
388 return TPS65910_VDD1; 388 return TPS65910_VDD1;
389 case TPS65910_REG_VDD2: 389 case TPS65910_REG_VDD2:
390 return TPS65910_VDD2; 390 return TPS65910_VDD2;
391 case TPS65911_REG_VDDCTRL: 391 case TPS65911_REG_VDDCTRL:
392 return TPS65911_VDDCTRL; 392 return TPS65911_VDDCTRL;
393 case TPS65911_REG_LDO1: 393 case TPS65911_REG_LDO1:
394 return TPS65911_LDO1; 394 return TPS65911_LDO1;
395 case TPS65911_REG_LDO2: 395 case TPS65911_REG_LDO2:
396 return TPS65911_LDO2; 396 return TPS65911_LDO2;
397 case TPS65911_REG_LDO3: 397 case TPS65911_REG_LDO3:
398 return TPS65911_LDO3; 398 return TPS65911_LDO3;
399 case TPS65911_REG_LDO4: 399 case TPS65911_REG_LDO4:
400 return TPS65911_LDO4; 400 return TPS65911_LDO4;
401 case TPS65911_REG_LDO5: 401 case TPS65911_REG_LDO5:
402 return TPS65911_LDO5; 402 return TPS65911_LDO5;
403 case TPS65911_REG_LDO6: 403 case TPS65911_REG_LDO6:
404 return TPS65911_LDO6; 404 return TPS65911_LDO6;
405 case TPS65911_REG_LDO7: 405 case TPS65911_REG_LDO7:
406 return TPS65911_LDO7; 406 return TPS65911_LDO7;
407 case TPS65911_REG_LDO8: 407 case TPS65911_REG_LDO8:
408 return TPS65911_LDO8; 408 return TPS65911_LDO8;
409 default: 409 default:
410 return -EINVAL; 410 return -EINVAL;
411 } 411 }
412 } 412 }
413 413
414 static int tps65910_is_enabled(struct regulator_dev *dev) 414 static int tps65910_is_enabled(struct regulator_dev *dev)
415 { 415 {
416 struct tps65910_reg *pmic = rdev_get_drvdata(dev); 416 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
417 int reg, value, id = rdev_get_id(dev); 417 int reg, value, id = rdev_get_id(dev);
418 418
419 reg = pmic->get_ctrl_reg(id); 419 reg = pmic->get_ctrl_reg(id);
420 if (reg < 0) 420 if (reg < 0)
421 return reg; 421 return reg;
422 422
423 value = tps65910_reg_read(pmic, reg); 423 value = tps65910_reg_read(pmic, reg);
424 if (value < 0) 424 if (value < 0)
425 return value; 425 return value;
426 426
427 return value & TPS65910_SUPPLY_STATE_ENABLED; 427 return value & TPS65910_SUPPLY_STATE_ENABLED;
428 } 428 }
429 429
430 static int tps65910_enable(struct regulator_dev *dev) 430 static int tps65910_enable(struct regulator_dev *dev)
431 { 431 {
432 struct tps65910_reg *pmic = rdev_get_drvdata(dev); 432 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
433 struct tps65910 *mfd = pmic->mfd; 433 struct tps65910 *mfd = pmic->mfd;
434 int reg, id = rdev_get_id(dev); 434 int reg, id = rdev_get_id(dev);
435 435
436 reg = pmic->get_ctrl_reg(id); 436 reg = pmic->get_ctrl_reg(id);
437 if (reg < 0) 437 if (reg < 0)
438 return reg; 438 return reg;
439 439
440 return tps65910_set_bits(mfd, reg, TPS65910_SUPPLY_STATE_ENABLED); 440 return tps65910_set_bits(mfd, reg, TPS65910_SUPPLY_STATE_ENABLED);
441 } 441 }
442 442
443 static int tps65910_disable(struct regulator_dev *dev) 443 static int tps65910_disable(struct regulator_dev *dev)
444 { 444 {
445 struct tps65910_reg *pmic = rdev_get_drvdata(dev); 445 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
446 struct tps65910 *mfd = pmic->mfd; 446 struct tps65910 *mfd = pmic->mfd;
447 int reg, id = rdev_get_id(dev); 447 int reg, id = rdev_get_id(dev);
448 448
449 reg = pmic->get_ctrl_reg(id); 449 reg = pmic->get_ctrl_reg(id);
450 if (reg < 0) 450 if (reg < 0)
451 return reg; 451 return reg;
452 452
453 return tps65910_clear_bits(mfd, reg, TPS65910_SUPPLY_STATE_ENABLED); 453 return tps65910_clear_bits(mfd, reg, TPS65910_SUPPLY_STATE_ENABLED);
454 } 454 }
455 455
456 456
457 static int tps65910_set_mode(struct regulator_dev *dev, unsigned int mode) 457 static int tps65910_set_mode(struct regulator_dev *dev, unsigned int mode)
458 { 458 {
459 struct tps65910_reg *pmic = rdev_get_drvdata(dev); 459 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
460 struct tps65910 *mfd = pmic->mfd; 460 struct tps65910 *mfd = pmic->mfd;
461 int reg, value, id = rdev_get_id(dev); 461 int reg, value, id = rdev_get_id(dev);
462 462
463 reg = pmic->get_ctrl_reg(id); 463 reg = pmic->get_ctrl_reg(id);
464 if (reg < 0) 464 if (reg < 0)
465 return reg; 465 return reg;
466 466
467 switch (mode) { 467 switch (mode) {
468 case REGULATOR_MODE_NORMAL: 468 case REGULATOR_MODE_NORMAL:
469 return tps65910_modify_bits(pmic, reg, LDO_ST_ON_BIT, 469 return tps65910_modify_bits(pmic, reg, LDO_ST_ON_BIT,
470 LDO_ST_MODE_BIT); 470 LDO_ST_MODE_BIT);
471 case REGULATOR_MODE_IDLE: 471 case REGULATOR_MODE_IDLE:
472 value = LDO_ST_ON_BIT | LDO_ST_MODE_BIT; 472 value = LDO_ST_ON_BIT | LDO_ST_MODE_BIT;
473 return tps65910_set_bits(mfd, reg, value); 473 return tps65910_set_bits(mfd, reg, value);
474 case REGULATOR_MODE_STANDBY: 474 case REGULATOR_MODE_STANDBY:
475 return tps65910_clear_bits(mfd, reg, LDO_ST_ON_BIT); 475 return tps65910_clear_bits(mfd, reg, LDO_ST_ON_BIT);
476 } 476 }
477 477
478 return -EINVAL; 478 return -EINVAL;
479 } 479 }
480 480
481 static unsigned int tps65910_get_mode(struct regulator_dev *dev) 481 static unsigned int tps65910_get_mode(struct regulator_dev *dev)
482 { 482 {
483 struct tps65910_reg *pmic = rdev_get_drvdata(dev); 483 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
484 int reg, value, id = rdev_get_id(dev); 484 int reg, value, id = rdev_get_id(dev);
485 485
486 reg = pmic->get_ctrl_reg(id); 486 reg = pmic->get_ctrl_reg(id);
487 if (reg < 0) 487 if (reg < 0)
488 return reg; 488 return reg;
489 489
490 value = tps65910_reg_read(pmic, reg); 490 value = tps65910_reg_read(pmic, reg);
491 if (value < 0) 491 if (value < 0)
492 return value; 492 return value;
493 493
494 if (value & LDO_ST_ON_BIT) 494 if (value & LDO_ST_ON_BIT)
495 return REGULATOR_MODE_STANDBY; 495 return REGULATOR_MODE_STANDBY;
496 else if (value & LDO_ST_MODE_BIT) 496 else if (value & LDO_ST_MODE_BIT)
497 return REGULATOR_MODE_IDLE; 497 return REGULATOR_MODE_IDLE;
498 else 498 else
499 return REGULATOR_MODE_NORMAL; 499 return REGULATOR_MODE_NORMAL;
500 } 500 }
501 501
502 static int tps65910_get_voltage_dcdc(struct regulator_dev *dev) 502 static int tps65910_get_voltage_dcdc(struct regulator_dev *dev)
503 { 503 {
504 struct tps65910_reg *pmic = rdev_get_drvdata(dev); 504 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
505 int id = rdev_get_id(dev), voltage = 0; 505 int id = rdev_get_id(dev), voltage = 0;
506 int opvsel = 0, srvsel = 0, vselmax = 0, mult = 0, sr = 0; 506 int opvsel = 0, srvsel = 0, vselmax = 0, mult = 0, sr = 0;
507 507
508 switch (id) { 508 switch (id) {
509 case TPS65910_REG_VDD1: 509 case TPS65910_REG_VDD1:
510 opvsel = tps65910_reg_read(pmic, TPS65910_VDD1_OP); 510 opvsel = tps65910_reg_read(pmic, TPS65910_VDD1_OP);
511 mult = tps65910_reg_read(pmic, TPS65910_VDD1); 511 mult = tps65910_reg_read(pmic, TPS65910_VDD1);
512 mult = (mult & VDD1_VGAIN_SEL_MASK) >> VDD1_VGAIN_SEL_SHIFT; 512 mult = (mult & VDD1_VGAIN_SEL_MASK) >> VDD1_VGAIN_SEL_SHIFT;
513 srvsel = tps65910_reg_read(pmic, TPS65910_VDD1_SR); 513 srvsel = tps65910_reg_read(pmic, TPS65910_VDD1_SR);
514 sr = opvsel & VDD1_OP_CMD_MASK; 514 sr = opvsel & VDD1_OP_CMD_MASK;
515 opvsel &= VDD1_OP_SEL_MASK; 515 opvsel &= VDD1_OP_SEL_MASK;
516 srvsel &= VDD1_SR_SEL_MASK; 516 srvsel &= VDD1_SR_SEL_MASK;
517 vselmax = 75; 517 vselmax = 75;
518 break; 518 break;
519 case TPS65910_REG_VDD2: 519 case TPS65910_REG_VDD2:
520 opvsel = tps65910_reg_read(pmic, TPS65910_VDD2_OP); 520 opvsel = tps65910_reg_read(pmic, TPS65910_VDD2_OP);
521 mult = tps65910_reg_read(pmic, TPS65910_VDD2); 521 mult = tps65910_reg_read(pmic, TPS65910_VDD2);
522 mult = (mult & VDD2_VGAIN_SEL_MASK) >> VDD2_VGAIN_SEL_SHIFT; 522 mult = (mult & VDD2_VGAIN_SEL_MASK) >> VDD2_VGAIN_SEL_SHIFT;
523 srvsel = tps65910_reg_read(pmic, TPS65910_VDD2_SR); 523 srvsel = tps65910_reg_read(pmic, TPS65910_VDD2_SR);
524 sr = opvsel & VDD2_OP_CMD_MASK; 524 sr = opvsel & VDD2_OP_CMD_MASK;
525 opvsel &= VDD2_OP_SEL_MASK; 525 opvsel &= VDD2_OP_SEL_MASK;
526 srvsel &= VDD2_SR_SEL_MASK; 526 srvsel &= VDD2_SR_SEL_MASK;
527 vselmax = 75; 527 vselmax = 75;
528 break; 528 break;
529 case TPS65911_REG_VDDCTRL: 529 case TPS65911_REG_VDDCTRL:
530 opvsel = tps65910_reg_read(pmic, TPS65911_VDDCTRL_OP); 530 opvsel = tps65910_reg_read(pmic, TPS65911_VDDCTRL_OP);
531 srvsel = tps65910_reg_read(pmic, TPS65911_VDDCTRL_SR); 531 srvsel = tps65910_reg_read(pmic, TPS65911_VDDCTRL_SR);
532 sr = opvsel & VDDCTRL_OP_CMD_MASK; 532 sr = opvsel & VDDCTRL_OP_CMD_MASK;
533 opvsel &= VDDCTRL_OP_SEL_MASK; 533 opvsel &= VDDCTRL_OP_SEL_MASK;
534 srvsel &= VDDCTRL_SR_SEL_MASK; 534 srvsel &= VDDCTRL_SR_SEL_MASK;
535 vselmax = 64; 535 vselmax = 64;
536 break; 536 break;
537 } 537 }
538 538
539 /* multiplier 0 == 1 but 2,3 normal */ 539 /* multiplier 0 == 1 but 2,3 normal */
540 if (!mult) 540 if (!mult)
541 mult=1; 541 mult=1;
542 542
543 if (sr) { 543 if (sr) {
544 /* normalise to valid range */ 544 /* normalise to valid range */
545 if (srvsel < 3) 545 if (srvsel < 3)
546 srvsel = 3; 546 srvsel = 3;
547 if (srvsel > vselmax) 547 if (srvsel > vselmax)
548 srvsel = vselmax; 548 srvsel = vselmax;
549 srvsel -= 3; 549 srvsel -= 3;
550 550
551 voltage = (srvsel * VDD1_2_OFFSET + VDD1_2_MIN_VOLT) * 100; 551 voltage = (srvsel * VDD1_2_OFFSET + VDD1_2_MIN_VOLT) * 100;
552 } else { 552 } else {
553 553
554 /* normalise to valid range*/ 554 /* normalise to valid range*/
555 if (opvsel < 3) 555 if (opvsel < 3)
556 opvsel = 3; 556 opvsel = 3;
557 if (opvsel > vselmax) 557 if (opvsel > vselmax)
558 opvsel = vselmax; 558 opvsel = vselmax;
559 opvsel -= 3; 559 opvsel -= 3;
560 560
561 voltage = (opvsel * VDD1_2_OFFSET + VDD1_2_MIN_VOLT) * 100; 561 voltage = (opvsel * VDD1_2_OFFSET + VDD1_2_MIN_VOLT) * 100;
562 } 562 }
563 563
564 voltage *= mult; 564 voltage *= mult;
565 565
566 return voltage; 566 return voltage;
567 } 567 }
568 568
569 static int tps65910_get_voltage(struct regulator_dev *dev) 569 static int tps65910_get_voltage(struct regulator_dev *dev)
570 { 570 {
571 struct tps65910_reg *pmic = rdev_get_drvdata(dev); 571 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
572 int reg, value, id = rdev_get_id(dev), voltage = 0; 572 int reg, value, id = rdev_get_id(dev), voltage = 0;
573 573
574 reg = pmic->get_ctrl_reg(id); 574 reg = pmic->get_ctrl_reg(id);
575 if (reg < 0) 575 if (reg < 0)
576 return reg; 576 return reg;
577 577
578 value = tps65910_reg_read(pmic, reg); 578 value = tps65910_reg_read(pmic, reg);
579 if (value < 0) 579 if (value < 0)
580 return value; 580 return value;
581 581
582 switch (id) { 582 switch (id) {
583 case TPS65910_REG_VIO: 583 case TPS65910_REG_VIO:
584 case TPS65910_REG_VDIG1: 584 case TPS65910_REG_VDIG1:
585 case TPS65910_REG_VDIG2: 585 case TPS65910_REG_VDIG2:
586 case TPS65910_REG_VPLL: 586 case TPS65910_REG_VPLL:
587 case TPS65910_REG_VDAC: 587 case TPS65910_REG_VDAC:
588 case TPS65910_REG_VAUX1: 588 case TPS65910_REG_VAUX1:
589 case TPS65910_REG_VAUX2: 589 case TPS65910_REG_VAUX2:
590 case TPS65910_REG_VAUX33: 590 case TPS65910_REG_VAUX33:
591 case TPS65910_REG_VMMC: 591 case TPS65910_REG_VMMC:
592 value &= LDO_SEL_MASK; 592 value &= LDO_SEL_MASK;
593 value >>= LDO_SEL_SHIFT; 593 value >>= LDO_SEL_SHIFT;
594 break; 594 break;
595 default: 595 default:
596 return -EINVAL; 596 return -EINVAL;
597 } 597 }
598 598
599 voltage = pmic->info[id]->table[value] * 1000; 599 voltage = pmic->info[id]->table[value] * 1000;
600 600
601 return voltage; 601 return voltage;
602 } 602 }
603 603
604 static int tps65910_get_voltage_vdd3(struct regulator_dev *dev) 604 static int tps65910_get_voltage_vdd3(struct regulator_dev *dev)
605 { 605 {
606 return 5 * 1000 * 1000; 606 return 5 * 1000 * 1000;
607 } 607 }
608 608
609 static int tps65911_get_voltage(struct regulator_dev *dev) 609 static int tps65911_get_voltage(struct regulator_dev *dev)
610 { 610 {
611 struct tps65910_reg *pmic = rdev_get_drvdata(dev); 611 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
612 int step_mv, id = rdev_get_id(dev); 612 int step_mv, id = rdev_get_id(dev);
613 u8 value, reg; 613 u8 value, reg;
614 614
615 reg = pmic->get_ctrl_reg(id); 615 reg = pmic->get_ctrl_reg(id);
616 616
617 value = tps65910_reg_read(pmic, reg); 617 value = tps65910_reg_read(pmic, reg);
618 618
619 switch (id) { 619 switch (id) {
620 case TPS65911_REG_LDO1: 620 case TPS65911_REG_LDO1:
621 case TPS65911_REG_LDO2: 621 case TPS65911_REG_LDO2:
622 case TPS65911_REG_LDO4: 622 case TPS65911_REG_LDO4:
623 value &= LDO1_SEL_MASK; 623 value &= LDO1_SEL_MASK;
624 value >>= LDO_SEL_SHIFT; 624 value >>= LDO_SEL_SHIFT;
625 /* The first 5 values of the selector correspond to 1V */ 625 /* The first 5 values of the selector correspond to 1V */
626 if (value < 5) 626 if (value < 5)
627 value = 0; 627 value = 0;
628 else 628 else
629 value -= 4; 629 value -= 4;
630 630
631 step_mv = 50; 631 step_mv = 50;
632 break; 632 break;
633 case TPS65911_REG_LDO3: 633 case TPS65911_REG_LDO3:
634 case TPS65911_REG_LDO5: 634 case TPS65911_REG_LDO5:
635 case TPS65911_REG_LDO6: 635 case TPS65911_REG_LDO6:
636 case TPS65911_REG_LDO7: 636 case TPS65911_REG_LDO7:
637 case TPS65911_REG_LDO8: 637 case TPS65911_REG_LDO8:
638 value &= LDO3_SEL_MASK; 638 value &= LDO3_SEL_MASK;
639 value >>= LDO_SEL_SHIFT; 639 value >>= LDO_SEL_SHIFT;
640 /* The first 3 values of the selector correspond to 1V */ 640 /* The first 3 values of the selector correspond to 1V */
641 if (value < 3) 641 if (value < 3)
642 value = 0; 642 value = 0;
643 else 643 else
644 value -= 2; 644 value -= 2;
645 645
646 step_mv = 100; 646 step_mv = 100;
647 break; 647 break;
648 case TPS65910_REG_VIO: 648 case TPS65910_REG_VIO:
649 return pmic->info[id]->table[value] * 1000; 649 return pmic->info[id]->table[value] * 1000;
650 break; 650 break;
651 default: 651 default:
652 return -EINVAL; 652 return -EINVAL;
653 } 653 }
654 654
655 return (LDO_MIN_VOLT + value * step_mv) * 1000; 655 return (LDO_MIN_VOLT + value * step_mv) * 1000;
656 } 656 }
657 657
658 static int tps65910_set_voltage_dcdc(struct regulator_dev *dev, 658 static int tps65910_set_voltage_dcdc(struct regulator_dev *dev,
659 unsigned selector) 659 unsigned selector)
660 { 660 {
661 struct tps65910_reg *pmic = rdev_get_drvdata(dev); 661 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
662 int id = rdev_get_id(dev), vsel; 662 int id = rdev_get_id(dev), vsel;
663 int dcdc_mult = 0; 663 int dcdc_mult = 0;
664 664
665 switch (id) { 665 switch (id) {
666 case TPS65910_REG_VDD1: 666 case TPS65910_REG_VDD1:
667 dcdc_mult = (selector / VDD1_2_NUM_VOLTS) + 1; 667 dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
668 if (dcdc_mult == 1) 668 if (dcdc_mult == 1)
669 dcdc_mult--; 669 dcdc_mult--;
670 vsel = (selector % VDD1_2_NUM_VOLTS) + 3; 670 vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3;
671 671
672 tps65910_modify_bits(pmic, TPS65910_VDD1, 672 tps65910_modify_bits(pmic, TPS65910_VDD1,
673 (dcdc_mult << VDD1_VGAIN_SEL_SHIFT), 673 (dcdc_mult << VDD1_VGAIN_SEL_SHIFT),
674 VDD1_VGAIN_SEL_MASK); 674 VDD1_VGAIN_SEL_MASK);
675 tps65910_reg_write(pmic, TPS65910_VDD1_OP, vsel); 675 tps65910_reg_write(pmic, TPS65910_VDD1_OP, vsel);
676 break; 676 break;
677 case TPS65910_REG_VDD2: 677 case TPS65910_REG_VDD2:
678 dcdc_mult = (selector / VDD1_2_NUM_VOLTS) + 1; 678 dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
679 if (dcdc_mult == 1) 679 if (dcdc_mult == 1)
680 dcdc_mult--; 680 dcdc_mult--;
681 vsel = (selector % VDD1_2_NUM_VOLTS) + 3; 681 vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3;
682 682
683 tps65910_modify_bits(pmic, TPS65910_VDD2, 683 tps65910_modify_bits(pmic, TPS65910_VDD2,
684 (dcdc_mult << VDD2_VGAIN_SEL_SHIFT), 684 (dcdc_mult << VDD2_VGAIN_SEL_SHIFT),
685 VDD1_VGAIN_SEL_MASK); 685 VDD1_VGAIN_SEL_MASK);
686 tps65910_reg_write(pmic, TPS65910_VDD2_OP, vsel); 686 tps65910_reg_write(pmic, TPS65910_VDD2_OP, vsel);
687 break; 687 break;
688 case TPS65911_REG_VDDCTRL: 688 case TPS65911_REG_VDDCTRL:
689 vsel = selector; 689 vsel = selector;
690 tps65910_reg_write(pmic, TPS65911_VDDCTRL_OP, vsel); 690 tps65910_reg_write(pmic, TPS65911_VDDCTRL_OP, vsel);
691 } 691 }
692 692
693 return 0; 693 return 0;
694 } 694 }
695 695
696 static int tps65910_set_voltage(struct regulator_dev *dev, unsigned selector) 696 static int tps65910_set_voltage(struct regulator_dev *dev, unsigned selector)
697 { 697 {
698 struct tps65910_reg *pmic = rdev_get_drvdata(dev); 698 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
699 int reg, id = rdev_get_id(dev); 699 int reg, id = rdev_get_id(dev);
700 700
701 reg = pmic->get_ctrl_reg(id); 701 reg = pmic->get_ctrl_reg(id);
702 if (reg < 0) 702 if (reg < 0)
703 return reg; 703 return reg;
704 704
705 switch (id) { 705 switch (id) {
706 case TPS65910_REG_VIO: 706 case TPS65910_REG_VIO:
707 case TPS65910_REG_VDIG1: 707 case TPS65910_REG_VDIG1:
708 case TPS65910_REG_VDIG2: 708 case TPS65910_REG_VDIG2:
709 case TPS65910_REG_VPLL: 709 case TPS65910_REG_VPLL:
710 case TPS65910_REG_VDAC: 710 case TPS65910_REG_VDAC:
711 case TPS65910_REG_VAUX1: 711 case TPS65910_REG_VAUX1:
712 case TPS65910_REG_VAUX2: 712 case TPS65910_REG_VAUX2:
713 case TPS65910_REG_VAUX33: 713 case TPS65910_REG_VAUX33:
714 case TPS65910_REG_VMMC: 714 case TPS65910_REG_VMMC:
715 return tps65910_modify_bits(pmic, reg, 715 return tps65910_modify_bits(pmic, reg,
716 (selector << LDO_SEL_SHIFT), LDO_SEL_MASK); 716 (selector << LDO_SEL_SHIFT), LDO_SEL_MASK);
717 } 717 }
718 718
719 return -EINVAL; 719 return -EINVAL;
720 } 720 }
721 721
722 static int tps65911_set_voltage(struct regulator_dev *dev, unsigned selector) 722 static int tps65911_set_voltage(struct regulator_dev *dev, unsigned selector)
723 { 723 {
724 struct tps65910_reg *pmic = rdev_get_drvdata(dev); 724 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
725 int reg, id = rdev_get_id(dev); 725 int reg, id = rdev_get_id(dev);
726 726
727 reg = pmic->get_ctrl_reg(id); 727 reg = pmic->get_ctrl_reg(id);
728 if (reg < 0) 728 if (reg < 0)
729 return reg; 729 return reg;
730 730
731 switch (id) { 731 switch (id) {
732 case TPS65911_REG_LDO1: 732 case TPS65911_REG_LDO1:
733 case TPS65911_REG_LDO2: 733 case TPS65911_REG_LDO2:
734 case TPS65911_REG_LDO4: 734 case TPS65911_REG_LDO4:
735 return tps65910_modify_bits(pmic, reg, 735 return tps65910_modify_bits(pmic, reg,
736 (selector << LDO_SEL_SHIFT), LDO1_SEL_MASK); 736 (selector << LDO_SEL_SHIFT), LDO1_SEL_MASK);
737 case TPS65911_REG_LDO3: 737 case TPS65911_REG_LDO3:
738 case TPS65911_REG_LDO5: 738 case TPS65911_REG_LDO5:
739 case TPS65911_REG_LDO6: 739 case TPS65911_REG_LDO6:
740 case TPS65911_REG_LDO7: 740 case TPS65911_REG_LDO7:
741 case TPS65911_REG_LDO8: 741 case TPS65911_REG_LDO8:
742 case TPS65910_REG_VIO: 742 case TPS65910_REG_VIO:
743 return tps65910_modify_bits(pmic, reg, 743 return tps65910_modify_bits(pmic, reg,
744 (selector << LDO_SEL_SHIFT), LDO3_SEL_MASK); 744 (selector << LDO_SEL_SHIFT), LDO3_SEL_MASK);
745 } 745 }
746 746
747 return -EINVAL; 747 return -EINVAL;
748 } 748 }
749 749
750 750
751 static int tps65910_list_voltage_dcdc(struct regulator_dev *dev, 751 static int tps65910_list_voltage_dcdc(struct regulator_dev *dev,
752 unsigned selector) 752 unsigned selector)
753 { 753 {
754 int volt, mult = 1, id = rdev_get_id(dev); 754 int volt, mult = 1, id = rdev_get_id(dev);
755 755
756 switch (id) { 756 switch (id) {
757 case TPS65910_REG_VDD1: 757 case TPS65910_REG_VDD1:
758 case TPS65910_REG_VDD2: 758 case TPS65910_REG_VDD2:
759 mult = (selector / VDD1_2_NUM_VOLTS) + 1; 759 mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
760 volt = VDD1_2_MIN_VOLT + 760 volt = VDD1_2_MIN_VOLT +
761 (selector % VDD1_2_NUM_VOLTS) * VDD1_2_OFFSET; 761 (selector % VDD1_2_NUM_VOLT_FINE) * VDD1_2_OFFSET;
762 break; 762 break;
763 case TPS65911_REG_VDDCTRL: 763 case TPS65911_REG_VDDCTRL:
764 volt = VDDCTRL_MIN_VOLT + (selector * VDDCTRL_OFFSET); 764 volt = VDDCTRL_MIN_VOLT + (selector * VDDCTRL_OFFSET);
765 break; 765 break;
766 default: 766 default:
767 BUG(); 767 BUG();
768 return -EINVAL; 768 return -EINVAL;
769 } 769 }
770 770
771 return volt * 100 * mult; 771 return volt * 100 * mult;
772 } 772 }
773 773
774 static int tps65910_list_voltage(struct regulator_dev *dev, 774 static int tps65910_list_voltage(struct regulator_dev *dev,
775 unsigned selector) 775 unsigned selector)
776 { 776 {
777 struct tps65910_reg *pmic = rdev_get_drvdata(dev); 777 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
778 int id = rdev_get_id(dev), voltage; 778 int id = rdev_get_id(dev), voltage;
779 779
780 if (id < TPS65910_REG_VIO || id > TPS65910_REG_VMMC) 780 if (id < TPS65910_REG_VIO || id > TPS65910_REG_VMMC)
781 return -EINVAL; 781 return -EINVAL;
782 782
783 if (selector >= pmic->info[id]->table_len) 783 if (selector >= pmic->info[id]->table_len)
784 return -EINVAL; 784 return -EINVAL;
785 else 785 else
786 voltage = pmic->info[id]->table[selector] * 1000; 786 voltage = pmic->info[id]->table[selector] * 1000;
787 787
788 return voltage; 788 return voltage;
789 } 789 }
790 790
791 static int tps65911_list_voltage(struct regulator_dev *dev, unsigned selector) 791 static int tps65911_list_voltage(struct regulator_dev *dev, unsigned selector)
792 { 792 {
793 struct tps65910_reg *pmic = rdev_get_drvdata(dev); 793 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
794 int step_mv = 0, id = rdev_get_id(dev); 794 int step_mv = 0, id = rdev_get_id(dev);
795 795
796 switch(id) { 796 switch(id) {
797 case TPS65911_REG_LDO1: 797 case TPS65911_REG_LDO1:
798 case TPS65911_REG_LDO2: 798 case TPS65911_REG_LDO2:
799 case TPS65911_REG_LDO4: 799 case TPS65911_REG_LDO4:
800 /* The first 5 values of the selector correspond to 1V */ 800 /* The first 5 values of the selector correspond to 1V */
801 if (selector < 5) 801 if (selector < 5)
802 selector = 0; 802 selector = 0;
803 else 803 else
804 selector -= 4; 804 selector -= 4;
805 805
806 step_mv = 50; 806 step_mv = 50;
807 break; 807 break;
808 case TPS65911_REG_LDO3: 808 case TPS65911_REG_LDO3:
809 case TPS65911_REG_LDO5: 809 case TPS65911_REG_LDO5:
810 case TPS65911_REG_LDO6: 810 case TPS65911_REG_LDO6:
811 case TPS65911_REG_LDO7: 811 case TPS65911_REG_LDO7:
812 case TPS65911_REG_LDO8: 812 case TPS65911_REG_LDO8:
813 /* The first 3 values of the selector correspond to 1V */ 813 /* The first 3 values of the selector correspond to 1V */
814 if (selector < 3) 814 if (selector < 3)
815 selector = 0; 815 selector = 0;
816 else 816 else
817 selector -= 2; 817 selector -= 2;
818 818
819 step_mv = 100; 819 step_mv = 100;
820 break; 820 break;
821 case TPS65910_REG_VIO: 821 case TPS65910_REG_VIO:
822 return pmic->info[id]->table[selector] * 1000; 822 return pmic->info[id]->table[selector] * 1000;
823 default: 823 default:
824 return -EINVAL; 824 return -EINVAL;
825 } 825 }
826 826
827 return (LDO_MIN_VOLT + selector * step_mv) * 1000; 827 return (LDO_MIN_VOLT + selector * step_mv) * 1000;
828 } 828 }
829 829
830 /* Regulator ops (except VRTC) */ 830 /* Regulator ops (except VRTC) */
831 static struct regulator_ops tps65910_ops_dcdc = { 831 static struct regulator_ops tps65910_ops_dcdc = {
832 .is_enabled = tps65910_is_enabled, 832 .is_enabled = tps65910_is_enabled,
833 .enable = tps65910_enable, 833 .enable = tps65910_enable,
834 .disable = tps65910_disable, 834 .disable = tps65910_disable,
835 .set_mode = tps65910_set_mode, 835 .set_mode = tps65910_set_mode,
836 .get_mode = tps65910_get_mode, 836 .get_mode = tps65910_get_mode,
837 .get_voltage = tps65910_get_voltage_dcdc, 837 .get_voltage = tps65910_get_voltage_dcdc,
838 .set_voltage_sel = tps65910_set_voltage_dcdc, 838 .set_voltage_sel = tps65910_set_voltage_dcdc,
839 .list_voltage = tps65910_list_voltage_dcdc, 839 .list_voltage = tps65910_list_voltage_dcdc,
840 }; 840 };
841 841
842 static struct regulator_ops tps65910_ops_vdd3 = { 842 static struct regulator_ops tps65910_ops_vdd3 = {
843 .is_enabled = tps65910_is_enabled, 843 .is_enabled = tps65910_is_enabled,
844 .enable = tps65910_enable, 844 .enable = tps65910_enable,
845 .disable = tps65910_disable, 845 .disable = tps65910_disable,
846 .set_mode = tps65910_set_mode, 846 .set_mode = tps65910_set_mode,
847 .get_mode = tps65910_get_mode, 847 .get_mode = tps65910_get_mode,
848 .get_voltage = tps65910_get_voltage_vdd3, 848 .get_voltage = tps65910_get_voltage_vdd3,
849 .list_voltage = tps65910_list_voltage, 849 .list_voltage = tps65910_list_voltage,
850 }; 850 };
851 851
852 static struct regulator_ops tps65910_ops = { 852 static struct regulator_ops tps65910_ops = {
853 .is_enabled = tps65910_is_enabled, 853 .is_enabled = tps65910_is_enabled,
854 .enable = tps65910_enable, 854 .enable = tps65910_enable,
855 .disable = tps65910_disable, 855 .disable = tps65910_disable,
856 .set_mode = tps65910_set_mode, 856 .set_mode = tps65910_set_mode,
857 .get_mode = tps65910_get_mode, 857 .get_mode = tps65910_get_mode,
858 .get_voltage = tps65910_get_voltage, 858 .get_voltage = tps65910_get_voltage,
859 .set_voltage_sel = tps65910_set_voltage, 859 .set_voltage_sel = tps65910_set_voltage,
860 .list_voltage = tps65910_list_voltage, 860 .list_voltage = tps65910_list_voltage,
861 }; 861 };
862 862
863 static struct regulator_ops tps65911_ops = { 863 static struct regulator_ops tps65911_ops = {
864 .is_enabled = tps65910_is_enabled, 864 .is_enabled = tps65910_is_enabled,
865 .enable = tps65910_enable, 865 .enable = tps65910_enable,
866 .disable = tps65910_disable, 866 .disable = tps65910_disable,
867 .set_mode = tps65910_set_mode, 867 .set_mode = tps65910_set_mode,
868 .get_mode = tps65910_get_mode, 868 .get_mode = tps65910_get_mode,
869 .get_voltage = tps65911_get_voltage, 869 .get_voltage = tps65911_get_voltage,
870 .set_voltage_sel = tps65911_set_voltage, 870 .set_voltage_sel = tps65911_set_voltage,
871 .list_voltage = tps65911_list_voltage, 871 .list_voltage = tps65911_list_voltage,
872 }; 872 };
873 873
874 static __devinit int tps65910_probe(struct platform_device *pdev) 874 static __devinit int tps65910_probe(struct platform_device *pdev)
875 { 875 {
876 struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent); 876 struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent);
877 struct tps_info *info; 877 struct tps_info *info;
878 struct regulator_init_data *reg_data; 878 struct regulator_init_data *reg_data;
879 struct regulator_dev *rdev; 879 struct regulator_dev *rdev;
880 struct tps65910_reg *pmic; 880 struct tps65910_reg *pmic;
881 struct tps65910_board *pmic_plat_data; 881 struct tps65910_board *pmic_plat_data;
882 int i, err; 882 int i, err;
883 883
884 pmic_plat_data = dev_get_platdata(tps65910->dev); 884 pmic_plat_data = dev_get_platdata(tps65910->dev);
885 if (!pmic_plat_data) 885 if (!pmic_plat_data)
886 return -EINVAL; 886 return -EINVAL;
887 887
888 reg_data = pmic_plat_data->tps65910_pmic_init_data; 888 reg_data = pmic_plat_data->tps65910_pmic_init_data;
889 889
890 pmic = kzalloc(sizeof(*pmic), GFP_KERNEL); 890 pmic = kzalloc(sizeof(*pmic), GFP_KERNEL);
891 if (!pmic) 891 if (!pmic)
892 return -ENOMEM; 892 return -ENOMEM;
893 893
894 mutex_init(&pmic->mutex); 894 mutex_init(&pmic->mutex);
895 pmic->mfd = tps65910; 895 pmic->mfd = tps65910;
896 platform_set_drvdata(pdev, pmic); 896 platform_set_drvdata(pdev, pmic);
897 897
898 /* Give control of all register to control port */ 898 /* Give control of all register to control port */
899 tps65910_set_bits(pmic->mfd, TPS65910_DEVCTRL, 899 tps65910_set_bits(pmic->mfd, TPS65910_DEVCTRL,
900 DEVCTRL_SR_CTL_I2C_SEL_MASK); 900 DEVCTRL_SR_CTL_I2C_SEL_MASK);
901 901
902 switch(tps65910_chip_id(tps65910)) { 902 switch(tps65910_chip_id(tps65910)) {
903 case TPS65910: 903 case TPS65910:
904 pmic->get_ctrl_reg = &tps65910_get_ctrl_register; 904 pmic->get_ctrl_reg = &tps65910_get_ctrl_register;
905 pmic->num_regulators = ARRAY_SIZE(tps65910_regs); 905 pmic->num_regulators = ARRAY_SIZE(tps65910_regs);
906 info = tps65910_regs; 906 info = tps65910_regs;
907 break; 907 break;
908 case TPS65911: 908 case TPS65911:
909 pmic->get_ctrl_reg = &tps65911_get_ctrl_register; 909 pmic->get_ctrl_reg = &tps65911_get_ctrl_register;
910 pmic->num_regulators = ARRAY_SIZE(tps65911_regs); 910 pmic->num_regulators = ARRAY_SIZE(tps65911_regs);
911 info = tps65911_regs; 911 info = tps65911_regs;
912 break; 912 break;
913 default: 913 default:
914 pr_err("Invalid tps chip version\n"); 914 pr_err("Invalid tps chip version\n");
915 kfree(pmic); 915 kfree(pmic);
916 return -ENODEV; 916 return -ENODEV;
917 } 917 }
918 918
919 pmic->desc = kcalloc(pmic->num_regulators, 919 pmic->desc = kcalloc(pmic->num_regulators,
920 sizeof(struct regulator_desc), GFP_KERNEL); 920 sizeof(struct regulator_desc), GFP_KERNEL);
921 if (!pmic->desc) { 921 if (!pmic->desc) {
922 err = -ENOMEM; 922 err = -ENOMEM;
923 goto err_free_pmic; 923 goto err_free_pmic;
924 } 924 }
925 925
926 pmic->info = kcalloc(pmic->num_regulators, 926 pmic->info = kcalloc(pmic->num_regulators,
927 sizeof(struct tps_info *), GFP_KERNEL); 927 sizeof(struct tps_info *), GFP_KERNEL);
928 if (!pmic->info) { 928 if (!pmic->info) {
929 err = -ENOMEM; 929 err = -ENOMEM;
930 goto err_free_desc; 930 goto err_free_desc;
931 } 931 }
932 932
933 pmic->rdev = kcalloc(pmic->num_regulators, 933 pmic->rdev = kcalloc(pmic->num_regulators,
934 sizeof(struct regulator_dev *), GFP_KERNEL); 934 sizeof(struct regulator_dev *), GFP_KERNEL);
935 if (!pmic->rdev) { 935 if (!pmic->rdev) {
936 err = -ENOMEM; 936 err = -ENOMEM;
937 goto err_free_info; 937 goto err_free_info;
938 } 938 }
939 939
940 for (i = 0; i < pmic->num_regulators; i++, info++, reg_data++) { 940 for (i = 0; i < pmic->num_regulators; i++, info++, reg_data++) {
941 /* Register the regulators */ 941 /* Register the regulators */
942 pmic->info[i] = info; 942 pmic->info[i] = info;
943 943
944 pmic->desc[i].name = info->name; 944 pmic->desc[i].name = info->name;
945 pmic->desc[i].id = i; 945 pmic->desc[i].id = i;
946 pmic->desc[i].n_voltages = info->table_len; 946 pmic->desc[i].n_voltages = info->table_len;
947 947
948 if (i == TPS65910_REG_VDD1 || i == TPS65910_REG_VDD2) { 948 if (i == TPS65910_REG_VDD1 || i == TPS65910_REG_VDD2) {
949 pmic->desc[i].ops = &tps65910_ops_dcdc; 949 pmic->desc[i].ops = &tps65910_ops_dcdc;
950 pmic->desc[i].n_voltages = VDD1_2_NUM_VOLT_FINE *
951 VDD1_2_NUM_VOLT_COARSE;
950 } else if (i == TPS65910_REG_VDD3) { 952 } else if (i == TPS65910_REG_VDD3) {
951 if (tps65910_chip_id(tps65910) == TPS65910) 953 if (tps65910_chip_id(tps65910) == TPS65910)
952 pmic->desc[i].ops = &tps65910_ops_vdd3; 954 pmic->desc[i].ops = &tps65910_ops_vdd3;
953 else 955 else
954 pmic->desc[i].ops = &tps65910_ops_dcdc; 956 pmic->desc[i].ops = &tps65910_ops_dcdc;
955 } else { 957 } else {
956 if (tps65910_chip_id(tps65910) == TPS65910) 958 if (tps65910_chip_id(tps65910) == TPS65910)
957 pmic->desc[i].ops = &tps65910_ops; 959 pmic->desc[i].ops = &tps65910_ops;
958 else 960 else
959 pmic->desc[i].ops = &tps65911_ops; 961 pmic->desc[i].ops = &tps65911_ops;
960 } 962 }
961 963
962 pmic->desc[i].type = REGULATOR_VOLTAGE; 964 pmic->desc[i].type = REGULATOR_VOLTAGE;
963 pmic->desc[i].owner = THIS_MODULE; 965 pmic->desc[i].owner = THIS_MODULE;
964 966
965 rdev = regulator_register(&pmic->desc[i], 967 rdev = regulator_register(&pmic->desc[i],
966 tps65910->dev, reg_data, pmic); 968 tps65910->dev, reg_data, pmic);
967 if (IS_ERR(rdev)) { 969 if (IS_ERR(rdev)) {
968 dev_err(tps65910->dev, 970 dev_err(tps65910->dev,
969 "failed to register %s regulator\n", 971 "failed to register %s regulator\n",
970 pdev->name); 972 pdev->name);
971 err = PTR_ERR(rdev); 973 err = PTR_ERR(rdev);
972 goto err_unregister_regulator; 974 goto err_unregister_regulator;
973 } 975 }
974 976
975 /* Save regulator for cleanup */ 977 /* Save regulator for cleanup */
976 pmic->rdev[i] = rdev; 978 pmic->rdev[i] = rdev;
977 } 979 }
978 return 0; 980 return 0;
979 981
980 err_unregister_regulator: 982 err_unregister_regulator:
981 while (--i >= 0) 983 while (--i >= 0)
982 regulator_unregister(pmic->rdev[i]); 984 regulator_unregister(pmic->rdev[i]);
983 kfree(pmic->rdev); 985 kfree(pmic->rdev);
984 err_free_info: 986 err_free_info:
985 kfree(pmic->info); 987 kfree(pmic->info);
986 err_free_desc: 988 err_free_desc:
987 kfree(pmic->desc); 989 kfree(pmic->desc);
988 err_free_pmic: 990 err_free_pmic:
989 kfree(pmic); 991 kfree(pmic);
990 return err; 992 return err;
991 } 993 }
992 994
993 static int __devexit tps65910_remove(struct platform_device *pdev) 995 static int __devexit tps65910_remove(struct platform_device *pdev)
994 { 996 {
995 struct tps65910_reg *pmic = platform_get_drvdata(pdev); 997 struct tps65910_reg *pmic = platform_get_drvdata(pdev);
996 int i; 998 int i;
997 999
998 for (i = 0; i < pmic->num_regulators; i++) 1000 for (i = 0; i < pmic->num_regulators; i++)
999 regulator_unregister(pmic->rdev[i]); 1001 regulator_unregister(pmic->rdev[i]);
1000 1002
1001 kfree(pmic->rdev); 1003 kfree(pmic->rdev);
1002 kfree(pmic->info); 1004 kfree(pmic->info);
1003 kfree(pmic->desc); 1005 kfree(pmic->desc);
1004 kfree(pmic); 1006 kfree(pmic);
1005 return 0; 1007 return 0;
1006 } 1008 }
1007 1009
1008 static struct platform_driver tps65910_driver = { 1010 static struct platform_driver tps65910_driver = {
1009 .driver = { 1011 .driver = {
1010 .name = "tps65910-pmic", 1012 .name = "tps65910-pmic",
1011 .owner = THIS_MODULE, 1013 .owner = THIS_MODULE,
1012 }, 1014 },
1013 .probe = tps65910_probe, 1015 .probe = tps65910_probe,
1014 .remove = __devexit_p(tps65910_remove), 1016 .remove = __devexit_p(tps65910_remove),
1015 }; 1017 };
1016 1018
1017 static int __init tps65910_init(void) 1019 static int __init tps65910_init(void)
1018 { 1020 {
1019 return platform_driver_register(&tps65910_driver); 1021 return platform_driver_register(&tps65910_driver);
1020 } 1022 }
1021 subsys_initcall(tps65910_init); 1023 subsys_initcall(tps65910_init);
1022 1024
1023 static void __exit tps65910_cleanup(void) 1025 static void __exit tps65910_cleanup(void)
1024 { 1026 {
1025 platform_driver_unregister(&tps65910_driver); 1027 platform_driver_unregister(&tps65910_driver);
1026 } 1028 }
1027 module_exit(tps65910_cleanup); 1029 module_exit(tps65910_cleanup);
1028 1030
1029 MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>"); 1031 MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
1030 MODULE_DESCRIPTION("TPS6507x voltage regulator driver"); 1032 MODULE_DESCRIPTION("TPS6507x voltage regulator driver");
1031 MODULE_LICENSE("GPL v2"); 1033 MODULE_LICENSE("GPL v2");
1032 MODULE_ALIAS("platform:tps65910-pmic"); 1034 MODULE_ALIAS("platform:tps65910-pmic");
1033 1035
include/linux/mfd/tps65910.h
Diff comments   View file @ 0a2c986
1 /* 1 /*
2 * tps65910.h -- TI TPS6591x 2 * tps65910.h -- TI TPS6591x
3 * 3 *
4 * Copyright 2010-2011 Texas Instruments Inc. 4 * Copyright 2010-2011 Texas Instruments Inc.
5 * 5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk> 6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk> 7 * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
8 * Author: Arnaud Deconinck <a-deconinck@ti.com> 8 * Author: Arnaud Deconinck <a-deconinck@ti.com>
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify it 10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the 11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your 12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version. 13 * option) any later version.
14 * 14 *
15 */ 15 */
16 16
17 #ifndef __LINUX_MFD_TPS65910_H 17 #ifndef __LINUX_MFD_TPS65910_H
18 #define __LINUX_MFD_TPS65910_H 18 #define __LINUX_MFD_TPS65910_H
19 19
20 /* TPS chip id list */ 20 /* TPS chip id list */
21 #define TPS65910 0 21 #define TPS65910 0
22 #define TPS65911 1 22 #define TPS65911 1
23 23
24 /* TPS regulator type list */ 24 /* TPS regulator type list */
25 #define REGULATOR_LDO 0 25 #define REGULATOR_LDO 0
26 #define REGULATOR_DCDC 1 26 #define REGULATOR_DCDC 1
27 27
28 /* 28 /*
29 * List of registers for component TPS65910 29 * List of registers for component TPS65910
30 * 30 *
31 */ 31 */
32 32
33 #define TPS65910_SECONDS 0x0 33 #define TPS65910_SECONDS 0x0
34 #define TPS65910_MINUTES 0x1 34 #define TPS65910_MINUTES 0x1
35 #define TPS65910_HOURS 0x2 35 #define TPS65910_HOURS 0x2
36 #define TPS65910_DAYS 0x3 36 #define TPS65910_DAYS 0x3
37 #define TPS65910_MONTHS 0x4 37 #define TPS65910_MONTHS 0x4
38 #define TPS65910_YEARS 0x5 38 #define TPS65910_YEARS 0x5
39 #define TPS65910_WEEKS 0x6 39 #define TPS65910_WEEKS 0x6
40 #define TPS65910_ALARM_SECONDS 0x8 40 #define TPS65910_ALARM_SECONDS 0x8
41 #define TPS65910_ALARM_MINUTES 0x9 41 #define TPS65910_ALARM_MINUTES 0x9
42 #define TPS65910_ALARM_HOURS 0xA 42 #define TPS65910_ALARM_HOURS 0xA
43 #define TPS65910_ALARM_DAYS 0xB 43 #define TPS65910_ALARM_DAYS 0xB
44 #define TPS65910_ALARM_MONTHS 0xC 44 #define TPS65910_ALARM_MONTHS 0xC
45 #define TPS65910_ALARM_YEARS 0xD 45 #define TPS65910_ALARM_YEARS 0xD
46 #define TPS65910_RTC_CTRL 0x10 46 #define TPS65910_RTC_CTRL 0x10
47 #define TPS65910_RTC_STATUS 0x11 47 #define TPS65910_RTC_STATUS 0x11
48 #define TPS65910_RTC_INTERRUPTS 0x12 48 #define TPS65910_RTC_INTERRUPTS 0x12
49 #define TPS65910_RTC_COMP_LSB 0x13 49 #define TPS65910_RTC_COMP_LSB 0x13
50 #define TPS65910_RTC_COMP_MSB 0x14 50 #define TPS65910_RTC_COMP_MSB 0x14
51 #define TPS65910_RTC_RES_PROG 0x15 51 #define TPS65910_RTC_RES_PROG 0x15
52 #define TPS65910_RTC_RESET_STATUS 0x16 52 #define TPS65910_RTC_RESET_STATUS 0x16
53 #define TPS65910_BCK1 0x17 53 #define TPS65910_BCK1 0x17
54 #define TPS65910_BCK2 0x18 54 #define TPS65910_BCK2 0x18
55 #define TPS65910_BCK3 0x19 55 #define TPS65910_BCK3 0x19
56 #define TPS65910_BCK4 0x1A 56 #define TPS65910_BCK4 0x1A
57 #define TPS65910_BCK5 0x1B 57 #define TPS65910_BCK5 0x1B
58 #define TPS65910_PUADEN 0x1C 58 #define TPS65910_PUADEN 0x1C
59 #define TPS65910_REF 0x1D 59 #define TPS65910_REF 0x1D
60 #define TPS65910_VRTC 0x1E 60 #define TPS65910_VRTC 0x1E
61 #define TPS65910_VIO 0x20 61 #define TPS65910_VIO 0x20
62 #define TPS65910_VDD1 0x21 62 #define TPS65910_VDD1 0x21
63 #define TPS65910_VDD1_OP 0x22 63 #define TPS65910_VDD1_OP 0x22
64 #define TPS65910_VDD1_SR 0x23 64 #define TPS65910_VDD1_SR 0x23
65 #define TPS65910_VDD2 0x24 65 #define TPS65910_VDD2 0x24
66 #define TPS65910_VDD2_OP 0x25 66 #define TPS65910_VDD2_OP 0x25
67 #define TPS65910_VDD2_SR 0x26 67 #define TPS65910_VDD2_SR 0x26
68 #define TPS65910_VDD3 0x27 68 #define TPS65910_VDD3 0x27
69 #define TPS65910_VDIG1 0x30 69 #define TPS65910_VDIG1 0x30
70 #define TPS65910_VDIG2 0x31 70 #define TPS65910_VDIG2 0x31
71 #define TPS65910_VAUX1 0x32 71 #define TPS65910_VAUX1 0x32
72 #define TPS65910_VAUX2 0x33 72 #define TPS65910_VAUX2 0x33
73 #define TPS65910_VAUX33 0x34 73 #define TPS65910_VAUX33 0x34
74 #define TPS65910_VMMC 0x35 74 #define TPS65910_VMMC 0x35
75 #define TPS65910_VPLL 0x36 75 #define TPS65910_VPLL 0x36
76 #define TPS65910_VDAC 0x37 76 #define TPS65910_VDAC 0x37
77 #define TPS65910_THERM 0x38 77 #define TPS65910_THERM 0x38
78 #define TPS65910_BBCH 0x39 78 #define TPS65910_BBCH 0x39
79 #define TPS65910_DCDCCTRL 0x3E 79 #define TPS65910_DCDCCTRL 0x3E
80 #define TPS65910_DEVCTRL 0x3F 80 #define TPS65910_DEVCTRL 0x3F
81 #define TPS65910_DEVCTRL2 0x40 81 #define TPS65910_DEVCTRL2 0x40
82 #define TPS65910_SLEEP_KEEP_LDO_ON 0x41 82 #define TPS65910_SLEEP_KEEP_LDO_ON 0x41
83 #define TPS65910_SLEEP_KEEP_RES_ON 0x42 83 #define TPS65910_SLEEP_KEEP_RES_ON 0x42
84 #define TPS65910_SLEEP_SET_LDO_OFF 0x43 84 #define TPS65910_SLEEP_SET_LDO_OFF 0x43
85 #define TPS65910_SLEEP_SET_RES_OFF 0x44 85 #define TPS65910_SLEEP_SET_RES_OFF 0x44
86 #define TPS65910_EN1_LDO_ASS 0x45 86 #define TPS65910_EN1_LDO_ASS 0x45
87 #define TPS65910_EN1_SMPS_ASS 0x46 87 #define TPS65910_EN1_SMPS_ASS 0x46
88 #define TPS65910_EN2_LDO_ASS 0x47 88 #define TPS65910_EN2_LDO_ASS 0x47
89 #define TPS65910_EN2_SMPS_ASS 0x48 89 #define TPS65910_EN2_SMPS_ASS 0x48
90 #define TPS65910_EN3_LDO_ASS 0x49 90 #define TPS65910_EN3_LDO_ASS 0x49
91 #define TPS65910_SPARE 0x4A 91 #define TPS65910_SPARE 0x4A
92 #define TPS65910_INT_STS 0x50 92 #define TPS65910_INT_STS 0x50
93 #define TPS65910_INT_MSK 0x51 93 #define TPS65910_INT_MSK 0x51
94 #define TPS65910_INT_STS2 0x52 94 #define TPS65910_INT_STS2 0x52
95 #define TPS65910_INT_MSK2 0x53 95 #define TPS65910_INT_MSK2 0x53
96 #define TPS65910_INT_STS3 0x54 96 #define TPS65910_INT_STS3 0x54
97 #define TPS65910_INT_MSK3 0x55 97 #define TPS65910_INT_MSK3 0x55
98 #define TPS65910_GPIO0 0x60 98 #define TPS65910_GPIO0 0x60
99 #define TPS65910_GPIO1 0x61 99 #define TPS65910_GPIO1 0x61
100 #define TPS65910_GPIO2 0x62 100 #define TPS65910_GPIO2 0x62
101 #define TPS65910_GPIO3 0x63 101 #define TPS65910_GPIO3 0x63
102 #define TPS65910_GPIO4 0x64 102 #define TPS65910_GPIO4 0x64
103 #define TPS65910_GPIO5 0x65 103 #define TPS65910_GPIO5 0x65
104 #define TPS65910_GPIO6 0x66 104 #define TPS65910_GPIO6 0x66
105 #define TPS65910_GPIO7 0x67 105 #define TPS65910_GPIO7 0x67
106 #define TPS65910_GPIO8 0x68 106 #define TPS65910_GPIO8 0x68
107 #define TPS65910_JTAGVERNUM 0x80 107 #define TPS65910_JTAGVERNUM 0x80
108 #define TPS65910_MAX_REGISTER 0x80 108 #define TPS65910_MAX_REGISTER 0x80
109 109
110 /* 110 /*
111 * List of registers specific to TPS65911 111 * List of registers specific to TPS65911
112 */ 112 */
113 #define TPS65911_VDDCTRL 0x27 113 #define TPS65911_VDDCTRL 0x27
114 #define TPS65911_VDDCTRL_OP 0x28 114 #define TPS65911_VDDCTRL_OP 0x28
115 #define TPS65911_VDDCTRL_SR 0x29 115 #define TPS65911_VDDCTRL_SR 0x29
116 #define TPS65911_LDO1 0x30 116 #define TPS65911_LDO1 0x30
117 #define TPS65911_LDO2 0x31 117 #define TPS65911_LDO2 0x31
118 #define TPS65911_LDO5 0x32 118 #define TPS65911_LDO5 0x32
119 #define TPS65911_LDO8 0x33 119 #define TPS65911_LDO8 0x33
120 #define TPS65911_LDO7 0x34 120 #define TPS65911_LDO7 0x34
121 #define TPS65911_LDO6 0x35 121 #define TPS65911_LDO6 0x35
122 #define TPS65911_LDO4 0x36 122 #define TPS65911_LDO4 0x36
123 #define TPS65911_LDO3 0x37 123 #define TPS65911_LDO3 0x37
124 #define TPS65911_VMBCH 0x6A 124 #define TPS65911_VMBCH 0x6A
125 #define TPS65911_VMBCH2 0x6B 125 #define TPS65911_VMBCH2 0x6B
126 126
127 /* 127 /*
128 * List of register bitfields for component TPS65910 128 * List of register bitfields for component TPS65910
129 * 129 *
130 */ 130 */
131 131
132 132
133 /*Register BCK1 (0x80) register.RegisterDescription */ 133 /*Register BCK1 (0x80) register.RegisterDescription */
134 #define BCK1_BCKUP_MASK 0xFF 134 #define BCK1_BCKUP_MASK 0xFF
135 #define BCK1_BCKUP_SHIFT 0 135 #define BCK1_BCKUP_SHIFT 0
136 136
137 137
138 /*Register BCK2 (0x80) register.RegisterDescription */ 138 /*Register BCK2 (0x80) register.RegisterDescription */
139 #define BCK2_BCKUP_MASK 0xFF 139 #define BCK2_BCKUP_MASK 0xFF
140 #define BCK2_BCKUP_SHIFT 0 140 #define BCK2_BCKUP_SHIFT 0
141 141
142 142
143 /*Register BCK3 (0x80) register.RegisterDescription */ 143 /*Register BCK3 (0x80) register.RegisterDescription */
144 #define BCK3_BCKUP_MASK 0xFF 144 #define BCK3_BCKUP_MASK 0xFF
145 #define BCK3_BCKUP_SHIFT 0 145 #define BCK3_BCKUP_SHIFT 0
146 146
147 147
148 /*Register BCK4 (0x80) register.RegisterDescription */ 148 /*Register BCK4 (0x80) register.RegisterDescription */
149 #define BCK4_BCKUP_MASK 0xFF 149 #define BCK4_BCKUP_MASK 0xFF
150 #define BCK4_BCKUP_SHIFT 0 150 #define BCK4_BCKUP_SHIFT 0
151 151
152 152
153 /*Register BCK5 (0x80) register.RegisterDescription */ 153 /*Register BCK5 (0x80) register.RegisterDescription */
154 #define BCK5_BCKUP_MASK 0xFF 154 #define BCK5_BCKUP_MASK 0xFF
155 #define BCK5_BCKUP_SHIFT 0 155 #define BCK5_BCKUP_SHIFT 0
156 156
157 157
158 /*Register PUADEN (0x80) register.RegisterDescription */ 158 /*Register PUADEN (0x80) register.RegisterDescription */
159 #define PUADEN_EN3P_MASK 0x80 159 #define PUADEN_EN3P_MASK 0x80
160 #define PUADEN_EN3P_SHIFT 7 160 #define PUADEN_EN3P_SHIFT 7
161 #define PUADEN_I2CCTLP_MASK 0x40 161 #define PUADEN_I2CCTLP_MASK 0x40
162 #define PUADEN_I2CCTLP_SHIFT 6 162 #define PUADEN_I2CCTLP_SHIFT 6
163 #define PUADEN_I2CSRP_MASK 0x20 163 #define PUADEN_I2CSRP_MASK 0x20
164 #define PUADEN_I2CSRP_SHIFT 5 164 #define PUADEN_I2CSRP_SHIFT 5
165 #define PUADEN_PWRONP_MASK 0x10 165 #define PUADEN_PWRONP_MASK 0x10
166 #define PUADEN_PWRONP_SHIFT 4 166 #define PUADEN_PWRONP_SHIFT 4
167 #define PUADEN_SLEEPP_MASK 0x08 167 #define PUADEN_SLEEPP_MASK 0x08
168 #define PUADEN_SLEEPP_SHIFT 3 168 #define PUADEN_SLEEPP_SHIFT 3
169 #define PUADEN_PWRHOLDP_MASK 0x04 169 #define PUADEN_PWRHOLDP_MASK 0x04
170 #define PUADEN_PWRHOLDP_SHIFT 2 170 #define PUADEN_PWRHOLDP_SHIFT 2
171 #define PUADEN_BOOT1P_MASK 0x02 171 #define PUADEN_BOOT1P_MASK 0x02
172 #define PUADEN_BOOT1P_SHIFT 1 172 #define PUADEN_BOOT1P_SHIFT 1
173 #define PUADEN_BOOT0P_MASK 0x01 173 #define PUADEN_BOOT0P_MASK 0x01
174 #define PUADEN_BOOT0P_SHIFT 0 174 #define PUADEN_BOOT0P_SHIFT 0
175 175
176 176
177 /*Register REF (0x80) register.RegisterDescription */ 177 /*Register REF (0x80) register.RegisterDescription */
178 #define REF_VMBCH_SEL_MASK 0x0C 178 #define REF_VMBCH_SEL_MASK 0x0C
179 #define REF_VMBCH_SEL_SHIFT 2 179 #define REF_VMBCH_SEL_SHIFT 2
180 #define REF_ST_MASK 0x03 180 #define REF_ST_MASK 0x03
181 #define REF_ST_SHIFT 0 181 #define REF_ST_SHIFT 0
182 182
183 183
184 /*Register VRTC (0x80) register.RegisterDescription */ 184 /*Register VRTC (0x80) register.RegisterDescription */
185 #define VRTC_VRTC_OFFMASK_MASK 0x08 185 #define VRTC_VRTC_OFFMASK_MASK 0x08
186 #define VRTC_VRTC_OFFMASK_SHIFT 3 186 #define VRTC_VRTC_OFFMASK_SHIFT 3
187 #define VRTC_ST_MASK 0x03 187 #define VRTC_ST_MASK 0x03
188 #define VRTC_ST_SHIFT 0 188 #define VRTC_ST_SHIFT 0
189 189
190 190
191 /*Register VIO (0x80) register.RegisterDescription */ 191 /*Register VIO (0x80) register.RegisterDescription */
192 #define VIO_ILMAX_MASK 0xC0 192 #define VIO_ILMAX_MASK 0xC0
193 #define VIO_ILMAX_SHIFT 6 193 #define VIO_ILMAX_SHIFT 6
194 #define VIO_SEL_MASK 0x0C 194 #define VIO_SEL_MASK 0x0C
195 #define VIO_SEL_SHIFT 2 195 #define VIO_SEL_SHIFT 2
196 #define VIO_ST_MASK 0x03 196 #define VIO_ST_MASK 0x03
197 #define VIO_ST_SHIFT 0 197 #define VIO_ST_SHIFT 0
198 198
199 199
200 /*Register VDD1 (0x80) register.RegisterDescription */ 200 /*Register VDD1 (0x80) register.RegisterDescription */
201 #define VDD1_VGAIN_SEL_MASK 0xC0 201 #define VDD1_VGAIN_SEL_MASK 0xC0
202 #define VDD1_VGAIN_SEL_SHIFT 6 202 #define VDD1_VGAIN_SEL_SHIFT 6
203 #define VDD1_ILMAX_MASK 0x20 203 #define VDD1_ILMAX_MASK 0x20
204 #define VDD1_ILMAX_SHIFT 5 204 #define VDD1_ILMAX_SHIFT 5
205 #define VDD1_TSTEP_MASK 0x1C 205 #define VDD1_TSTEP_MASK 0x1C
206 #define VDD1_TSTEP_SHIFT 2 206 #define VDD1_TSTEP_SHIFT 2
207 #define VDD1_ST_MASK 0x03 207 #define VDD1_ST_MASK 0x03
208 #define VDD1_ST_SHIFT 0 208 #define VDD1_ST_SHIFT 0
209 209
210 210
211 /*Register VDD1_OP (0x80) register.RegisterDescription */ 211 /*Register VDD1_OP (0x80) register.RegisterDescription */
212 #define VDD1_OP_CMD_MASK 0x80 212 #define VDD1_OP_CMD_MASK 0x80
213 #define VDD1_OP_CMD_SHIFT 7 213 #define VDD1_OP_CMD_SHIFT 7
214 #define VDD1_OP_SEL_MASK 0x7F 214 #define VDD1_OP_SEL_MASK 0x7F
215 #define VDD1_OP_SEL_SHIFT 0 215 #define VDD1_OP_SEL_SHIFT 0
216 216
217 217
218 /*Register VDD1_SR (0x80) register.RegisterDescription */ 218 /*Register VDD1_SR (0x80) register.RegisterDescription */
219 #define VDD1_SR_SEL_MASK 0x7F 219 #define VDD1_SR_SEL_MASK 0x7F
220 #define VDD1_SR_SEL_SHIFT 0 220 #define VDD1_SR_SEL_SHIFT 0
221 221
222 222
223 /*Register VDD2 (0x80) register.RegisterDescription */ 223 /*Register VDD2 (0x80) register.RegisterDescription */
224 #define VDD2_VGAIN_SEL_MASK 0xC0 224 #define VDD2_VGAIN_SEL_MASK 0xC0
225 #define VDD2_VGAIN_SEL_SHIFT 6 225 #define VDD2_VGAIN_SEL_SHIFT 6
226 #define VDD2_ILMAX_MASK 0x20 226 #define VDD2_ILMAX_MASK 0x20
227 #define VDD2_ILMAX_SHIFT 5 227 #define VDD2_ILMAX_SHIFT 5
228 #define VDD2_TSTEP_MASK 0x1C 228 #define VDD2_TSTEP_MASK 0x1C
229 #define VDD2_TSTEP_SHIFT 2 229 #define VDD2_TSTEP_SHIFT 2
230 #define VDD2_ST_MASK 0x03 230 #define VDD2_ST_MASK 0x03
231 #define VDD2_ST_SHIFT 0 231 #define VDD2_ST_SHIFT 0
232 232
233 233
234 /*Register VDD2_OP (0x80) register.RegisterDescription */ 234 /*Register VDD2_OP (0x80) register.RegisterDescription */
235 #define VDD2_OP_CMD_MASK 0x80 235 #define VDD2_OP_CMD_MASK 0x80
236 #define VDD2_OP_CMD_SHIFT 7 236 #define VDD2_OP_CMD_SHIFT 7
237 #define VDD2_OP_SEL_MASK 0x7F 237 #define VDD2_OP_SEL_MASK 0x7F
238 #define VDD2_OP_SEL_SHIFT 0 238 #define VDD2_OP_SEL_SHIFT 0
239 239
240 /*Register VDD2_SR (0x80) register.RegisterDescription */ 240 /*Register VDD2_SR (0x80) register.RegisterDescription */
241 #define VDD2_SR_SEL_MASK 0x7F 241 #define VDD2_SR_SEL_MASK 0x7F
242 #define VDD2_SR_SEL_SHIFT 0 242 #define VDD2_SR_SEL_SHIFT 0
243 243
244 244
245 /*Registers VDD1, VDD2 voltage values definitions */ 245 /*Registers VDD1, VDD2 voltage values definitions */
246 #define VDD1_2_NUM_VOLTS 73 246 #define VDD1_2_NUM_VOLT_FINE 73
247 #define VDD1_2_NUM_VOLT_COARSE 3
247 #define VDD1_2_MIN_VOLT 6000 248 #define VDD1_2_MIN_VOLT 6000
248 #define VDD1_2_OFFSET 125 249 #define VDD1_2_OFFSET 125
249 250
250 251
251 /*Register VDD3 (0x80) register.RegisterDescription */ 252 /*Register VDD3 (0x80) register.RegisterDescription */
252 #define VDD3_CKINEN_MASK 0x04 253 #define VDD3_CKINEN_MASK 0x04
253 #define VDD3_CKINEN_SHIFT 2 254 #define VDD3_CKINEN_SHIFT 2
254 #define VDD3_ST_MASK 0x03 255 #define VDD3_ST_MASK 0x03
255 #define VDD3_ST_SHIFT 0 256 #define VDD3_ST_SHIFT 0
256 #define VDDCTRL_MIN_VOLT 6000 257 #define VDDCTRL_MIN_VOLT 6000
257 #define VDDCTRL_OFFSET 125 258 #define VDDCTRL_OFFSET 125
258 259
259 /*Registers VDIG (0x80) to VDAC register.RegisterDescription */ 260 /*Registers VDIG (0x80) to VDAC register.RegisterDescription */
260 #define LDO_SEL_MASK 0x0C 261 #define LDO_SEL_MASK 0x0C
261 #define LDO_SEL_SHIFT 2 262 #define LDO_SEL_SHIFT 2
262 #define LDO_ST_MASK 0x03 263 #define LDO_ST_MASK 0x03
263 #define LDO_ST_SHIFT 0 264 #define LDO_ST_SHIFT 0
264 #define LDO_ST_ON_BIT 0x01 265 #define LDO_ST_ON_BIT 0x01
265 #define LDO_ST_MODE_BIT 0x02 266 #define LDO_ST_MODE_BIT 0x02
266 267
267 268
268 /* Registers LDO1 to LDO8 in tps65910 */ 269 /* Registers LDO1 to LDO8 in tps65910 */
269 #define LDO1_SEL_MASK 0xFC 270 #define LDO1_SEL_MASK 0xFC
270 #define LDO3_SEL_MASK 0x7C 271 #define LDO3_SEL_MASK 0x7C
271 #define LDO_MIN_VOLT 1000 272 #define LDO_MIN_VOLT 1000
272 #define LDO_MAX_VOLT 3300 273 #define LDO_MAX_VOLT 3300
273 274
274 275
275 /*Register VDIG1 (0x80) register.RegisterDescription */ 276 /*Register VDIG1 (0x80) register.RegisterDescription */
276 #define VDIG1_SEL_MASK 0x0C 277 #define VDIG1_SEL_MASK 0x0C
277 #define VDIG1_SEL_SHIFT 2 278 #define VDIG1_SEL_SHIFT 2
278 #define VDIG1_ST_MASK 0x03 279 #define VDIG1_ST_MASK 0x03
279 #define VDIG1_ST_SHIFT 0 280 #define VDIG1_ST_SHIFT 0
280 281
281 282
282 /*Register VDIG2 (0x80) register.RegisterDescription */ 283 /*Register VDIG2 (0x80) register.RegisterDescription */
283 #define VDIG2_SEL_MASK 0x0C 284 #define VDIG2_SEL_MASK 0x0C
284 #define VDIG2_SEL_SHIFT 2 285 #define VDIG2_SEL_SHIFT 2
285 #define VDIG2_ST_MASK 0x03 286 #define VDIG2_ST_MASK 0x03
286 #define VDIG2_ST_SHIFT 0 287 #define VDIG2_ST_SHIFT 0
287 288
288 289
289 /*Register VAUX1 (0x80) register.RegisterDescription */ 290 /*Register VAUX1 (0x80) register.RegisterDescription */
290 #define VAUX1_SEL_MASK 0x0C 291 #define VAUX1_SEL_MASK 0x0C
291 #define VAUX1_SEL_SHIFT 2 292 #define VAUX1_SEL_SHIFT 2
292 #define VAUX1_ST_MASK 0x03 293 #define VAUX1_ST_MASK 0x03
293 #define VAUX1_ST_SHIFT 0 294 #define VAUX1_ST_SHIFT 0
294 295
295 296
296 /*Register VAUX2 (0x80) register.RegisterDescription */ 297 /*Register VAUX2 (0x80) register.RegisterDescription */
297 #define VAUX2_SEL_MASK 0x0C 298 #define VAUX2_SEL_MASK 0x0C
298 #define VAUX2_SEL_SHIFT 2 299 #define VAUX2_SEL_SHIFT 2
299 #define VAUX2_ST_MASK 0x03 300 #define VAUX2_ST_MASK 0x03
300 #define VAUX2_ST_SHIFT 0 301 #define VAUX2_ST_SHIFT 0
301 302
302 303
303 /*Register VAUX33 (0x80) register.RegisterDescription */ 304 /*Register VAUX33 (0x80) register.RegisterDescription */
304 #define VAUX33_SEL_MASK 0x0C 305 #define VAUX33_SEL_MASK 0x0C
305 #define VAUX33_SEL_SHIFT 2 306 #define VAUX33_SEL_SHIFT 2
306 #define VAUX33_ST_MASK 0x03 307 #define VAUX33_ST_MASK 0x03
307 #define VAUX33_ST_SHIFT 0 308 #define VAUX33_ST_SHIFT 0
308 309
309 310
310 /*Register VMMC (0x80) register.RegisterDescription */ 311 /*Register VMMC (0x80) register.RegisterDescription */
311 #define VMMC_SEL_MASK 0x0C 312 #define VMMC_SEL_MASK 0x0C
312 #define VMMC_SEL_SHIFT 2 313 #define VMMC_SEL_SHIFT 2
313 #define VMMC_ST_MASK 0x03 314 #define VMMC_ST_MASK 0x03
314 #define VMMC_ST_SHIFT 0 315 #define VMMC_ST_SHIFT 0
315 316
316 317
317 /*Register VPLL (0x80) register.RegisterDescription */ 318 /*Register VPLL (0x80) register.RegisterDescription */
318 #define VPLL_SEL_MASK 0x0C 319 #define VPLL_SEL_MASK 0x0C
319 #define VPLL_SEL_SHIFT 2 320 #define VPLL_SEL_SHIFT 2
320 #define VPLL_ST_MASK 0x03 321 #define VPLL_ST_MASK 0x03
321 #define VPLL_ST_SHIFT 0 322 #define VPLL_ST_SHIFT 0
322 323
323 324
324 /*Register VDAC (0x80) register.RegisterDescription */ 325 /*Register VDAC (0x80) register.RegisterDescription */
325 #define VDAC_SEL_MASK 0x0C 326 #define VDAC_SEL_MASK 0x0C
326 #define VDAC_SEL_SHIFT 2 327 #define VDAC_SEL_SHIFT 2
327 #define VDAC_ST_MASK 0x03 328 #define VDAC_ST_MASK 0x03
328 #define VDAC_ST_SHIFT 0 329 #define VDAC_ST_SHIFT 0
329 330
330 331
331 /*Register THERM (0x80) register.RegisterDescription */ 332 /*Register THERM (0x80) register.RegisterDescription */
332 #define THERM_THERM_HD_MASK 0x20 333 #define THERM_THERM_HD_MASK 0x20
333 #define THERM_THERM_HD_SHIFT 5 334 #define THERM_THERM_HD_SHIFT 5
334 #define THERM_THERM_TS_MASK 0x10 335 #define THERM_THERM_TS_MASK 0x10
335 #define THERM_THERM_TS_SHIFT 4 336 #define THERM_THERM_TS_SHIFT 4
336 #define THERM_THERM_HDSEL_MASK 0x0C 337 #define THERM_THERM_HDSEL_MASK 0x0C
337 #define THERM_THERM_HDSEL_SHIFT 2 338 #define THERM_THERM_HDSEL_SHIFT 2
338 #define THERM_RSVD1_MASK 0x02 339 #define THERM_RSVD1_MASK 0x02
339 #define THERM_RSVD1_SHIFT 1 340 #define THERM_RSVD1_SHIFT 1
340 #define THERM_THERM_STATE_MASK 0x01 341 #define THERM_THERM_STATE_MASK 0x01
341 #define THERM_THERM_STATE_SHIFT 0 342 #define THERM_THERM_STATE_SHIFT 0
342 343
343 344
344 /*Register BBCH (0x80) register.RegisterDescription */ 345 /*Register BBCH (0x80) register.RegisterDescription */
345 #define BBCH_BBSEL_MASK 0x06 346 #define BBCH_BBSEL_MASK 0x06
346 #define BBCH_BBSEL_SHIFT 1 347 #define BBCH_BBSEL_SHIFT 1
347 #define BBCH_BBCHEN_MASK 0x01 348 #define BBCH_BBCHEN_MASK 0x01
348 #define BBCH_BBCHEN_SHIFT 0 349 #define BBCH_BBCHEN_SHIFT 0
349 350
350 351
351 /*Register DCDCCTRL (0x80) register.RegisterDescription */ 352 /*Register DCDCCTRL (0x80) register.RegisterDescription */
352 #define DCDCCTRL_VDD2_PSKIP_MASK 0x20 353 #define DCDCCTRL_VDD2_PSKIP_MASK 0x20
353 #define DCDCCTRL_VDD2_PSKIP_SHIFT 5 354 #define DCDCCTRL_VDD2_PSKIP_SHIFT 5
354 #define DCDCCTRL_VDD1_PSKIP_MASK 0x10 355 #define DCDCCTRL_VDD1_PSKIP_MASK 0x10
355 #define DCDCCTRL_VDD1_PSKIP_SHIFT 4 356 #define DCDCCTRL_VDD1_PSKIP_SHIFT 4
356 #define DCDCCTRL_VIO_PSKIP_MASK 0x08 357 #define DCDCCTRL_VIO_PSKIP_MASK 0x08
357 #define DCDCCTRL_VIO_PSKIP_SHIFT 3 358 #define DCDCCTRL_VIO_PSKIP_SHIFT 3
358 #define DCDCCTRL_DCDCCKEXT_MASK 0x04 359 #define DCDCCTRL_DCDCCKEXT_MASK 0x04
359 #define DCDCCTRL_DCDCCKEXT_SHIFT 2 360 #define DCDCCTRL_DCDCCKEXT_SHIFT 2
360 #define DCDCCTRL_DCDCCKSYNC_MASK 0x03 361 #define DCDCCTRL_DCDCCKSYNC_MASK 0x03
361 #define DCDCCTRL_DCDCCKSYNC_SHIFT 0 362 #define DCDCCTRL_DCDCCKSYNC_SHIFT 0
362 363
363 364
364 /*Register DEVCTRL (0x80) register.RegisterDescription */ 365 /*Register DEVCTRL (0x80) register.RegisterDescription */
365 #define DEVCTRL_RTC_PWDN_MASK 0x40 366 #define DEVCTRL_RTC_PWDN_MASK 0x40
366 #define DEVCTRL_RTC_PWDN_SHIFT 6 367 #define DEVCTRL_RTC_PWDN_SHIFT 6
367 #define DEVCTRL_CK32K_CTRL_MASK 0x20 368 #define DEVCTRL_CK32K_CTRL_MASK 0x20
368 #define DEVCTRL_CK32K_CTRL_SHIFT 5 369 #define DEVCTRL_CK32K_CTRL_SHIFT 5
369 #define DEVCTRL_SR_CTL_I2C_SEL_MASK 0x10 370 #define DEVCTRL_SR_CTL_I2C_SEL_MASK 0x10
370 #define DEVCTRL_SR_CTL_I2C_SEL_SHIFT 4 371 #define DEVCTRL_SR_CTL_I2C_SEL_SHIFT 4
371 #define DEVCTRL_DEV_OFF_RST_MASK 0x08 372 #define DEVCTRL_DEV_OFF_RST_MASK 0x08
372 #define DEVCTRL_DEV_OFF_RST_SHIFT 3 373 #define DEVCTRL_DEV_OFF_RST_SHIFT 3
373 #define DEVCTRL_DEV_ON_MASK 0x04 374 #define DEVCTRL_DEV_ON_MASK 0x04
374 #define DEVCTRL_DEV_ON_SHIFT 2 375 #define DEVCTRL_DEV_ON_SHIFT 2
375 #define DEVCTRL_DEV_SLP_MASK 0x02 376 #define DEVCTRL_DEV_SLP_MASK 0x02
376 #define DEVCTRL_DEV_SLP_SHIFT 1 377 #define DEVCTRL_DEV_SLP_SHIFT 1
377 #define DEVCTRL_DEV_OFF_MASK 0x01 378 #define DEVCTRL_DEV_OFF_MASK 0x01
378 #define DEVCTRL_DEV_OFF_SHIFT 0 379 #define DEVCTRL_DEV_OFF_SHIFT 0
379 380
380 381
381 /*Register DEVCTRL2 (0x80) register.RegisterDescription */ 382 /*Register DEVCTRL2 (0x80) register.RegisterDescription */
382 #define DEVCTRL2_TSLOT_LENGTH_MASK 0x30 383 #define DEVCTRL2_TSLOT_LENGTH_MASK 0x30
383 #define DEVCTRL2_TSLOT_LENGTH_SHIFT 4 384 #define DEVCTRL2_TSLOT_LENGTH_SHIFT 4
384 #define DEVCTRL2_SLEEPSIG_POL_MASK 0x08 385 #define DEVCTRL2_SLEEPSIG_POL_MASK 0x08
385 #define DEVCTRL2_SLEEPSIG_POL_SHIFT 3 386 #define DEVCTRL2_SLEEPSIG_POL_SHIFT 3
386 #define DEVCTRL2_PWON_LP_OFF_MASK 0x04 387 #define DEVCTRL2_PWON_LP_OFF_MASK 0x04
387 #define DEVCTRL2_PWON_LP_OFF_SHIFT 2 388 #define DEVCTRL2_PWON_LP_OFF_SHIFT 2
388 #define DEVCTRL2_PWON_LP_RST_MASK 0x02 389 #define DEVCTRL2_PWON_LP_RST_MASK 0x02
389 #define DEVCTRL2_PWON_LP_RST_SHIFT 1 390 #define DEVCTRL2_PWON_LP_RST_SHIFT 1
390 #define DEVCTRL2_IT_POL_MASK 0x01 391 #define DEVCTRL2_IT_POL_MASK 0x01
391 #define DEVCTRL2_IT_POL_SHIFT 0 392 #define DEVCTRL2_IT_POL_SHIFT 0
392 393
393 394
394 /*Register SLEEP_KEEP_LDO_ON (0x80) register.RegisterDescription */ 395 /*Register SLEEP_KEEP_LDO_ON (0x80) register.RegisterDescription */
395 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK 0x80 396 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK 0x80
396 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT 7 397 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT 7
397 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK 0x40 398 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK 0x40
398 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_SHIFT 6 399 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_SHIFT 6
399 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK 0x20 400 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK 0x20
400 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_SHIFT 5 401 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_SHIFT 5
401 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK 0x10 402 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK 0x10
402 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_SHIFT 4 403 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_SHIFT 4
403 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK 0x08 404 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK 0x08
404 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_SHIFT 3 405 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_SHIFT 3
405 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK 0x04 406 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK 0x04
406 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_SHIFT 2 407 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_SHIFT 2
407 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK 0x02 408 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK 0x02
408 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_SHIFT 1 409 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_SHIFT 1
409 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK 0x01 410 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK 0x01
410 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT 0 411 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT 0
411 412
412 413
413 /*Register SLEEP_KEEP_RES_ON (0x80) register.RegisterDescription */ 414 /*Register SLEEP_KEEP_RES_ON (0x80) register.RegisterDescription */
414 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK 0x80 415 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK 0x80
415 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT 7 416 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT 7
416 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK 0x40 417 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK 0x40
417 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_SHIFT 6 418 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_SHIFT 6
418 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK 0x20 419 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK 0x20
419 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_SHIFT 5 420 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_SHIFT 5
420 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK 0x10 421 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK 0x10
421 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_SHIFT 4 422 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_SHIFT 4
422 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK 0x08 423 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK 0x08
423 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_SHIFT 3 424 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_SHIFT 3
424 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK 0x04 425 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK 0x04
425 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_SHIFT 2 426 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_SHIFT 2
426 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK 0x02 427 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK 0x02
427 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_SHIFT 1 428 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_SHIFT 1
428 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK 0x01 429 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK 0x01
429 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT 0 430 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT 0
430 431
431 432
432 /*Register SLEEP_SET_LDO_OFF (0x80) register.RegisterDescription */ 433 /*Register SLEEP_SET_LDO_OFF (0x80) register.RegisterDescription */
433 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK 0x80 434 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK 0x80
434 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT 7 435 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT 7
435 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK 0x40 436 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK 0x40
436 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_SHIFT 6 437 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_SHIFT 6
437 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK 0x20 438 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK 0x20
438 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_SHIFT 5 439 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_SHIFT 5
439 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK 0x10 440 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK 0x10
440 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_SHIFT 4 441 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_SHIFT 4
441 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK 0x08 442 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK 0x08
442 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_SHIFT 3 443 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_SHIFT 3
443 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK 0x04 444 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK 0x04
444 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_SHIFT 2 445 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_SHIFT 2
445 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK 0x02 446 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK 0x02
446 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_SHIFT 1 447 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_SHIFT 1
447 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK 0x01 448 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK 0x01
448 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT 0 449 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT 0
449 450
450 451
451 /*Register SLEEP_SET_RES_OFF (0x80) register.RegisterDescription */ 452 /*Register SLEEP_SET_RES_OFF (0x80) register.RegisterDescription */
452 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK 0x80 453 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK 0x80
453 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT 7 454 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT 7
454 #define SLEEP_SET_RES_OFF_RSVD_MASK 0x60 455 #define SLEEP_SET_RES_OFF_RSVD_MASK 0x60
455 #define SLEEP_SET_RES_OFF_RSVD_SHIFT 5 456 #define SLEEP_SET_RES_OFF_RSVD_SHIFT 5
456 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK 0x10 457 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK 0x10
457 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_SHIFT 4 458 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_SHIFT 4
458 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK 0x08 459 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK 0x08
459 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_SHIFT 3 460 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_SHIFT 3
460 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK 0x04 461 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK 0x04
461 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_SHIFT 2 462 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_SHIFT 2
462 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK 0x02 463 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK 0x02
463 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_SHIFT 1 464 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_SHIFT 1
464 #define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK 0x01 465 #define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK 0x01
465 #define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT 0 466 #define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT 0
466 467
467 468
468 /*Register EN1_LDO_ASS (0x80) register.RegisterDescription */ 469 /*Register EN1_LDO_ASS (0x80) register.RegisterDescription */
469 #define EN1_LDO_ASS_VDAC_EN1_MASK 0x80 470 #define EN1_LDO_ASS_VDAC_EN1_MASK 0x80
470 #define EN1_LDO_ASS_VDAC_EN1_SHIFT 7 471 #define EN1_LDO_ASS_VDAC_EN1_SHIFT 7
471 #define EN1_LDO_ASS_VPLL_EN1_MASK 0x40 472 #define EN1_LDO_ASS_VPLL_EN1_MASK 0x40
472 #define EN1_LDO_ASS_VPLL_EN1_SHIFT 6 473 #define EN1_LDO_ASS_VPLL_EN1_SHIFT 6
473 #define EN1_LDO_ASS_VAUX33_EN1_MASK 0x20 474 #define EN1_LDO_ASS_VAUX33_EN1_MASK 0x20
474 #define EN1_LDO_ASS_VAUX33_EN1_SHIFT 5 475 #define EN1_LDO_ASS_VAUX33_EN1_SHIFT 5
475 #define EN1_LDO_ASS_VAUX2_EN1_MASK 0x10 476 #define EN1_LDO_ASS_VAUX2_EN1_MASK 0x10
476 #define EN1_LDO_ASS_VAUX2_EN1_SHIFT 4 477 #define EN1_LDO_ASS_VAUX2_EN1_SHIFT 4
477 #define EN1_LDO_ASS_VAUX1_EN1_MASK 0x08 478 #define EN1_LDO_ASS_VAUX1_EN1_MASK 0x08
478 #define EN1_LDO_ASS_VAUX1_EN1_SHIFT 3 479 #define EN1_LDO_ASS_VAUX1_EN1_SHIFT 3
479 #define EN1_LDO_ASS_VDIG2_EN1_MASK 0x04 480 #define EN1_LDO_ASS_VDIG2_EN1_MASK 0x04
480 #define EN1_LDO_ASS_VDIG2_EN1_SHIFT 2 481 #define EN1_LDO_ASS_VDIG2_EN1_SHIFT 2
481 #define EN1_LDO_ASS_VDIG1_EN1_MASK 0x02 482 #define EN1_LDO_ASS_VDIG1_EN1_MASK 0x02
482 #define EN1_LDO_ASS_VDIG1_EN1_SHIFT 1 483 #define EN1_LDO_ASS_VDIG1_EN1_SHIFT 1
483 #define EN1_LDO_ASS_VMMC_EN1_MASK 0x01 484 #define EN1_LDO_ASS_VMMC_EN1_MASK 0x01
484 #define EN1_LDO_ASS_VMMC_EN1_SHIFT 0 485 #define EN1_LDO_ASS_VMMC_EN1_SHIFT 0
485 486
486 487
487 /*Register EN1_SMPS_ASS (0x80) register.RegisterDescription */ 488 /*Register EN1_SMPS_ASS (0x80) register.RegisterDescription */
488 #define EN1_SMPS_ASS_RSVD_MASK 0xE0 489 #define EN1_SMPS_ASS_RSVD_MASK 0xE0
489 #define EN1_SMPS_ASS_RSVD_SHIFT 5 490 #define EN1_SMPS_ASS_RSVD_SHIFT 5
490 #define EN1_SMPS_ASS_SPARE_EN1_MASK 0x10 491 #define EN1_SMPS_ASS_SPARE_EN1_MASK 0x10
491 #define EN1_SMPS_ASS_SPARE_EN1_SHIFT 4 492 #define EN1_SMPS_ASS_SPARE_EN1_SHIFT 4
492 #define EN1_SMPS_ASS_VDD3_EN1_MASK 0x08 493 #define EN1_SMPS_ASS_VDD3_EN1_MASK 0x08
493 #define EN1_SMPS_ASS_VDD3_EN1_SHIFT 3 494 #define EN1_SMPS_ASS_VDD3_EN1_SHIFT 3
494 #define EN1_SMPS_ASS_VDD2_EN1_MASK 0x04 495 #define EN1_SMPS_ASS_VDD2_EN1_MASK 0x04
495 #define EN1_SMPS_ASS_VDD2_EN1_SHIFT 2 496 #define EN1_SMPS_ASS_VDD2_EN1_SHIFT 2
496 #define EN1_SMPS_ASS_VDD1_EN1_MASK 0x02 497 #define EN1_SMPS_ASS_VDD1_EN1_MASK 0x02
497 #define EN1_SMPS_ASS_VDD1_EN1_SHIFT 1 498 #define EN1_SMPS_ASS_VDD1_EN1_SHIFT 1
498 #define EN1_SMPS_ASS_VIO_EN1_MASK 0x01 499 #define EN1_SMPS_ASS_VIO_EN1_MASK 0x01
499 #define EN1_SMPS_ASS_VIO_EN1_SHIFT 0 500 #define EN1_SMPS_ASS_VIO_EN1_SHIFT 0
500 501
501 502
502 /*Register EN2_LDO_ASS (0x80) register.RegisterDescription */ 503 /*Register EN2_LDO_ASS (0x80) register.RegisterDescription */
503 #define EN2_LDO_ASS_VDAC_EN2_MASK 0x80 504 #define EN2_LDO_ASS_VDAC_EN2_MASK 0x80
504 #define EN2_LDO_ASS_VDAC_EN2_SHIFT 7 505 #define EN2_LDO_ASS_VDAC_EN2_SHIFT 7
505 #define EN2_LDO_ASS_VPLL_EN2_MASK 0x40 506 #define EN2_LDO_ASS_VPLL_EN2_MASK 0x40
506 #define EN2_LDO_ASS_VPLL_EN2_SHIFT 6 507 #define EN2_LDO_ASS_VPLL_EN2_SHIFT 6
507 #define EN2_LDO_ASS_VAUX33_EN2_MASK 0x20 508 #define EN2_LDO_ASS_VAUX33_EN2_MASK 0x20
508 #define EN2_LDO_ASS_VAUX33_EN2_SHIFT 5 509 #define EN2_LDO_ASS_VAUX33_EN2_SHIFT 5
509 #define EN2_LDO_ASS_VAUX2_EN2_MASK 0x10 510 #define EN2_LDO_ASS_VAUX2_EN2_MASK 0x10
510 #define EN2_LDO_ASS_VAUX2_EN2_SHIFT 4 511 #define EN2_LDO_ASS_VAUX2_EN2_SHIFT 4
511 #define EN2_LDO_ASS_VAUX1_EN2_MASK 0x08 512 #define EN2_LDO_ASS_VAUX1_EN2_MASK 0x08
512 #define EN2_LDO_ASS_VAUX1_EN2_SHIFT 3 513 #define EN2_LDO_ASS_VAUX1_EN2_SHIFT 3
513 #define EN2_LDO_ASS_VDIG2_EN2_MASK 0x04 514 #define EN2_LDO_ASS_VDIG2_EN2_MASK 0x04
514 #define EN2_LDO_ASS_VDIG2_EN2_SHIFT 2 515 #define EN2_LDO_ASS_VDIG2_EN2_SHIFT 2
515 #define EN2_LDO_ASS_VDIG1_EN2_MASK 0x02 516 #define EN2_LDO_ASS_VDIG1_EN2_MASK 0x02
516 #define EN2_LDO_ASS_VDIG1_EN2_SHIFT 1 517 #define EN2_LDO_ASS_VDIG1_EN2_SHIFT 1
517 #define EN2_LDO_ASS_VMMC_EN2_MASK 0x01 518 #define EN2_LDO_ASS_VMMC_EN2_MASK 0x01
518 #define EN2_LDO_ASS_VMMC_EN2_SHIFT 0 519 #define EN2_LDO_ASS_VMMC_EN2_SHIFT 0
519 520
520 521
521 /*Register EN2_SMPS_ASS (0x80) register.RegisterDescription */ 522 /*Register EN2_SMPS_ASS (0x80) register.RegisterDescription */
522 #define EN2_SMPS_ASS_RSVD_MASK 0xE0 523 #define EN2_SMPS_ASS_RSVD_MASK 0xE0
523 #define EN2_SMPS_ASS_RSVD_SHIFT 5 524 #define EN2_SMPS_ASS_RSVD_SHIFT 5
524 #define EN2_SMPS_ASS_SPARE_EN2_MASK 0x10 525 #define EN2_SMPS_ASS_SPARE_EN2_MASK 0x10
525 #define EN2_SMPS_ASS_SPARE_EN2_SHIFT 4 526 #define EN2_SMPS_ASS_SPARE_EN2_SHIFT 4
526 #define EN2_SMPS_ASS_VDD3_EN2_MASK 0x08 527 #define EN2_SMPS_ASS_VDD3_EN2_MASK 0x08
527 #define EN2_SMPS_ASS_VDD3_EN2_SHIFT 3 528 #define EN2_SMPS_ASS_VDD3_EN2_SHIFT 3
528 #define EN2_SMPS_ASS_VDD2_EN2_MASK 0x04 529 #define EN2_SMPS_ASS_VDD2_EN2_MASK 0x04
529 #define EN2_SMPS_ASS_VDD2_EN2_SHIFT 2 530 #define EN2_SMPS_ASS_VDD2_EN2_SHIFT 2
530 #define EN2_SMPS_ASS_VDD1_EN2_MASK 0x02 531 #define EN2_SMPS_ASS_VDD1_EN2_MASK 0x02
531 #define EN2_SMPS_ASS_VDD1_EN2_SHIFT 1 532 #define EN2_SMPS_ASS_VDD1_EN2_SHIFT 1
532 #define EN2_SMPS_ASS_VIO_EN2_MASK 0x01 533 #define EN2_SMPS_ASS_VIO_EN2_MASK 0x01
533 #define EN2_SMPS_ASS_VIO_EN2_SHIFT 0 534 #define EN2_SMPS_ASS_VIO_EN2_SHIFT 0
534 535
535 536
536 /*Register EN3_LDO_ASS (0x80) register.RegisterDescription */ 537 /*Register EN3_LDO_ASS (0x80) register.RegisterDescription */
537 #define EN3_LDO_ASS_VDAC_EN3_MASK 0x80 538 #define EN3_LDO_ASS_VDAC_EN3_MASK 0x80
538 #define EN3_LDO_ASS_VDAC_EN3_SHIFT 7 539 #define EN3_LDO_ASS_VDAC_EN3_SHIFT 7
539 #define EN3_LDO_ASS_VPLL_EN3_MASK 0x40 540 #define EN3_LDO_ASS_VPLL_EN3_MASK 0x40
540 #define EN3_LDO_ASS_VPLL_EN3_SHIFT 6 541 #define EN3_LDO_ASS_VPLL_EN3_SHIFT 6
541 #define EN3_LDO_ASS_VAUX33_EN3_MASK 0x20 542 #define EN3_LDO_ASS_VAUX33_EN3_MASK 0x20
542 #define EN3_LDO_ASS_VAUX33_EN3_SHIFT 5 543 #define EN3_LDO_ASS_VAUX33_EN3_SHIFT 5
543 #define EN3_LDO_ASS_VAUX2_EN3_MASK 0x10 544 #define EN3_LDO_ASS_VAUX2_EN3_MASK 0x10
544 #define EN3_LDO_ASS_VAUX2_EN3_SHIFT 4 545 #define EN3_LDO_ASS_VAUX2_EN3_SHIFT 4
545 #define EN3_LDO_ASS_VAUX1_EN3_MASK 0x08 546 #define EN3_LDO_ASS_VAUX1_EN3_MASK 0x08
546 #define EN3_LDO_ASS_VAUX1_EN3_SHIFT 3 547 #define EN3_LDO_ASS_VAUX1_EN3_SHIFT 3
547 #define EN3_LDO_ASS_VDIG2_EN3_MASK 0x04 548 #define EN3_LDO_ASS_VDIG2_EN3_MASK 0x04
548 #define EN3_LDO_ASS_VDIG2_EN3_SHIFT 2 549 #define EN3_LDO_ASS_VDIG2_EN3_SHIFT 2
549 #define EN3_LDO_ASS_VDIG1_EN3_MASK 0x02 550 #define EN3_LDO_ASS_VDIG1_EN3_MASK 0x02
550 #define EN3_LDO_ASS_VDIG1_EN3_SHIFT 1 551 #define EN3_LDO_ASS_VDIG1_EN3_SHIFT 1
551 #define EN3_LDO_ASS_VMMC_EN3_MASK 0x01 552 #define EN3_LDO_ASS_VMMC_EN3_MASK 0x01
552 #define EN3_LDO_ASS_VMMC_EN3_SHIFT 0 553 #define EN3_LDO_ASS_VMMC_EN3_SHIFT 0
553 554
554 555
555 /*Register SPARE (0x80) register.RegisterDescription */ 556 /*Register SPARE (0x80) register.RegisterDescription */
556 #define SPARE_SPARE_MASK 0xFF 557 #define SPARE_SPARE_MASK 0xFF
557 #define SPARE_SPARE_SHIFT 0 558 #define SPARE_SPARE_SHIFT 0
558 559
559 560
560 /*Register INT_STS (0x80) register.RegisterDescription */ 561 /*Register INT_STS (0x80) register.RegisterDescription */
561 #define INT_STS_RTC_PERIOD_IT_MASK 0x80 562 #define INT_STS_RTC_PERIOD_IT_MASK 0x80
562 #define INT_STS_RTC_PERIOD_IT_SHIFT 7 563 #define INT_STS_RTC_PERIOD_IT_SHIFT 7
563 #define INT_STS_RTC_ALARM_IT_MASK 0x40 564 #define INT_STS_RTC_ALARM_IT_MASK 0x40
564 #define INT_STS_RTC_ALARM_IT_SHIFT 6 565 #define INT_STS_RTC_ALARM_IT_SHIFT 6
565 #define INT_STS_HOTDIE_IT_MASK 0x20 566 #define INT_STS_HOTDIE_IT_MASK 0x20
566 #define INT_STS_HOTDIE_IT_SHIFT 5 567 #define INT_STS_HOTDIE_IT_SHIFT 5
567 #define INT_STS_PWRHOLD_IT_MASK 0x10 568 #define INT_STS_PWRHOLD_IT_MASK 0x10
568 #define INT_STS_PWRHOLD_IT_SHIFT 4 569 #define INT_STS_PWRHOLD_IT_SHIFT 4
569 #define INT_STS_PWRON_LP_IT_MASK 0x08 570 #define INT_STS_PWRON_LP_IT_MASK 0x08
570 #define INT_STS_PWRON_LP_IT_SHIFT 3 571 #define INT_STS_PWRON_LP_IT_SHIFT 3
571 #define INT_STS_PWRON_IT_MASK 0x04 572 #define INT_STS_PWRON_IT_MASK 0x04
572 #define INT_STS_PWRON_IT_SHIFT 2 573 #define INT_STS_PWRON_IT_SHIFT 2
573 #define INT_STS_VMBHI_IT_MASK 0x02 574 #define INT_STS_VMBHI_IT_MASK 0x02
574 #define INT_STS_VMBHI_IT_SHIFT 1 575 #define INT_STS_VMBHI_IT_SHIFT 1
575 #define INT_STS_VMBDCH_IT_MASK 0x01 576 #define INT_STS_VMBDCH_IT_MASK 0x01
576 #define INT_STS_VMBDCH_IT_SHIFT 0 577 #define INT_STS_VMBDCH_IT_SHIFT 0
577 578
578 579
579 /*Register INT_MSK (0x80) register.RegisterDescription */ 580 /*Register INT_MSK (0x80) register.RegisterDescription */
580 #define INT_MSK_RTC_PERIOD_IT_MSK_MASK 0x80 581 #define INT_MSK_RTC_PERIOD_IT_MSK_MASK 0x80
581 #define INT_MSK_RTC_PERIOD_IT_MSK_SHIFT 7 582 #define INT_MSK_RTC_PERIOD_IT_MSK_SHIFT 7
582 #define INT_MSK_RTC_ALARM_IT_MSK_MASK 0x40 583 #define INT_MSK_RTC_ALARM_IT_MSK_MASK 0x40
583 #define INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6 584 #define INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6
584 #define INT_MSK_HOTDIE_IT_MSK_MASK 0x20 585 #define INT_MSK_HOTDIE_IT_MSK_MASK 0x20
585 #define INT_MSK_HOTDIE_IT_MSK_SHIFT 5 586 #define INT_MSK_HOTDIE_IT_MSK_SHIFT 5
586 #define INT_MSK_PWRHOLD_IT_MSK_MASK 0x10 587 #define INT_MSK_PWRHOLD_IT_MSK_MASK 0x10
587 #define INT_MSK_PWRHOLD_IT_MSK_SHIFT 4 588 #define INT_MSK_PWRHOLD_IT_MSK_SHIFT 4
588 #define INT_MSK_PWRON_LP_IT_MSK_MASK 0x08 589 #define INT_MSK_PWRON_LP_IT_MSK_MASK 0x08
589 #define INT_MSK_PWRON_LP_IT_MSK_SHIFT 3 590 #define INT_MSK_PWRON_LP_IT_MSK_SHIFT 3
590 #define INT_MSK_PWRON_IT_MSK_MASK 0x04 591 #define INT_MSK_PWRON_IT_MSK_MASK 0x04
591 #define INT_MSK_PWRON_IT_MSK_SHIFT 2 592 #define INT_MSK_PWRON_IT_MSK_SHIFT 2
592 #define INT_MSK_VMBHI_IT_MSK_MASK 0x02 593 #define INT_MSK_VMBHI_IT_MSK_MASK 0x02
593 #define INT_MSK_VMBHI_IT_MSK_SHIFT 1 594 #define INT_MSK_VMBHI_IT_MSK_SHIFT 1
594 #define INT_MSK_VMBDCH_IT_MSK_MASK 0x01 595 #define INT_MSK_VMBDCH_IT_MSK_MASK 0x01
595 #define INT_MSK_VMBDCH_IT_MSK_SHIFT 0 596 #define INT_MSK_VMBDCH_IT_MSK_SHIFT 0
596 597
597 598
598 /*Register INT_STS2 (0x80) register.RegisterDescription */ 599 /*Register INT_STS2 (0x80) register.RegisterDescription */
599 #define INT_STS2_GPIO3_F_IT_MASK 0x80 600 #define INT_STS2_GPIO3_F_IT_MASK 0x80
600 #define INT_STS2_GPIO3_F_IT_SHIFT 7 601 #define INT_STS2_GPIO3_F_IT_SHIFT 7
601 #define INT_STS2_GPIO3_R_IT_MASK 0x40 602 #define INT_STS2_GPIO3_R_IT_MASK 0x40
602 #define INT_STS2_GPIO3_R_IT_SHIFT 6 603 #define INT_STS2_GPIO3_R_IT_SHIFT 6
603 #define INT_STS2_GPIO2_F_IT_MASK 0x20 604 #define INT_STS2_GPIO2_F_IT_MASK 0x20
604 #define INT_STS2_GPIO2_F_IT_SHIFT 5 605 #define INT_STS2_GPIO2_F_IT_SHIFT 5
605 #define INT_STS2_GPIO2_R_IT_MASK 0x10 606 #define INT_STS2_GPIO2_R_IT_MASK 0x10
606 #define INT_STS2_GPIO2_R_IT_SHIFT 4 607 #define INT_STS2_GPIO2_R_IT_SHIFT 4
607 #define INT_STS2_GPIO1_F_IT_MASK 0x08 608 #define INT_STS2_GPIO1_F_IT_MASK 0x08
608 #define INT_STS2_GPIO1_F_IT_SHIFT 3 609 #define INT_STS2_GPIO1_F_IT_SHIFT 3
609 #define INT_STS2_GPIO1_R_IT_MASK 0x04 610 #define INT_STS2_GPIO1_R_IT_MASK 0x04
610 #define INT_STS2_GPIO1_R_IT_SHIFT 2 611 #define INT_STS2_GPIO1_R_IT_SHIFT 2
611 #define INT_STS2_GPIO0_F_IT_MASK 0x02 612 #define INT_STS2_GPIO0_F_IT_MASK 0x02
612 #define INT_STS2_GPIO0_F_IT_SHIFT 1 613 #define INT_STS2_GPIO0_F_IT_SHIFT 1
613 #define INT_STS2_GPIO0_R_IT_MASK 0x01 614 #define INT_STS2_GPIO0_R_IT_MASK 0x01
614 #define INT_STS2_GPIO0_R_IT_SHIFT 0 615 #define INT_STS2_GPIO0_R_IT_SHIFT 0
615 616
616 617
617 /*Register INT_MSK2 (0x80) register.RegisterDescription */ 618 /*Register INT_MSK2 (0x80) register.RegisterDescription */
618 #define INT_MSK2_GPIO3_F_IT_MSK_MASK 0x80 619 #define INT_MSK2_GPIO3_F_IT_MSK_MASK 0x80
619 #define INT_MSK2_GPIO3_F_IT_MSK_SHIFT 7 620 #define INT_MSK2_GPIO3_F_IT_MSK_SHIFT 7
620 #define INT_MSK2_GPIO3_R_IT_MSK_MASK 0x40 621 #define INT_MSK2_GPIO3_R_IT_MSK_MASK 0x40
621 #define INT_MSK2_GPIO3_R_IT_MSK_SHIFT 6 622 #define INT_MSK2_GPIO3_R_IT_MSK_SHIFT 6
622 #define INT_MSK2_GPIO2_F_IT_MSK_MASK 0x20 623 #define INT_MSK2_GPIO2_F_IT_MSK_MASK 0x20
623 #define INT_MSK2_GPIO2_F_IT_MSK_SHIFT 5 624 #define INT_MSK2_GPIO2_F_IT_MSK_SHIFT 5
624 #define INT_MSK2_GPIO2_R_IT_MSK_MASK 0x10 625 #define INT_MSK2_GPIO2_R_IT_MSK_MASK 0x10
625 #define INT_MSK2_GPIO2_R_IT_MSK_SHIFT 4 626 #define INT_MSK2_GPIO2_R_IT_MSK_SHIFT 4
626 #define INT_MSK2_GPIO1_F_IT_MSK_MASK 0x08 627 #define INT_MSK2_GPIO1_F_IT_MSK_MASK 0x08
627 #define INT_MSK2_GPIO1_F_IT_MSK_SHIFT 3 628 #define INT_MSK2_GPIO1_F_IT_MSK_SHIFT 3
628 #define INT_MSK2_GPIO1_R_IT_MSK_MASK 0x04 629 #define INT_MSK2_GPIO1_R_IT_MSK_MASK 0x04
629 #define INT_MSK2_GPIO1_R_IT_MSK_SHIFT 2 630 #define INT_MSK2_GPIO1_R_IT_MSK_SHIFT 2
630 #define INT_MSK2_GPIO0_F_IT_MSK_MASK 0x02 631 #define INT_MSK2_GPIO0_F_IT_MSK_MASK 0x02
631 #define INT_MSK2_GPIO0_F_IT_MSK_SHIFT 1 632 #define INT_MSK2_GPIO0_F_IT_MSK_SHIFT 1
632 #define INT_MSK2_GPIO0_R_IT_MSK_MASK 0x01 633 #define INT_MSK2_GPIO0_R_IT_MSK_MASK 0x01
633 #define INT_MSK2_GPIO0_R_IT_MSK_SHIFT 0 634 #define INT_MSK2_GPIO0_R_IT_MSK_SHIFT 0
634 635
635 636
636 /*Register INT_STS3 (0x80) register.RegisterDescription */ 637 /*Register INT_STS3 (0x80) register.RegisterDescription */
637 #define INT_STS3_GPIO5_F_IT_MASK 0x08 638 #define INT_STS3_GPIO5_F_IT_MASK 0x08
638 #define INT_STS3_GPIO5_F_IT_SHIFT 3 639 #define INT_STS3_GPIO5_F_IT_SHIFT 3
639 #define INT_STS3_GPIO5_R_IT_MASK 0x04 640 #define INT_STS3_GPIO5_R_IT_MASK 0x04
640 #define INT_STS3_GPIO5_R_IT_SHIFT 2 641 #define INT_STS3_GPIO5_R_IT_SHIFT 2
641 #define INT_STS3_GPIO4_F_IT_MASK 0x02 642 #define INT_STS3_GPIO4_F_IT_MASK 0x02
642 #define INT_STS3_GPIO4_F_IT_SHIFT 1 643 #define INT_STS3_GPIO4_F_IT_SHIFT 1
643 #define INT_STS3_GPIO4_R_IT_MASK 0x01 644 #define INT_STS3_GPIO4_R_IT_MASK 0x01
644 #define INT_STS3_GPIO4_R_IT_SHIFT 0 645 #define INT_STS3_GPIO4_R_IT_SHIFT 0
645 646
646 647
647 /*Register INT_MSK3 (0x80) register.RegisterDescription */ 648 /*Register INT_MSK3 (0x80) register.RegisterDescription */
648 #define INT_MSK3_GPIO5_F_IT_MSK_MASK 0x08 649 #define INT_MSK3_GPIO5_F_IT_MSK_MASK 0x08
649 #define INT_MSK3_GPIO5_F_IT_MSK_SHIFT 3 650 #define INT_MSK3_GPIO5_F_IT_MSK_SHIFT 3
650 #define INT_MSK3_GPIO5_R_IT_MSK_MASK 0x04 651 #define INT_MSK3_GPIO5_R_IT_MSK_MASK 0x04
651 #define INT_MSK3_GPIO5_R_IT_MSK_SHIFT 2 652 #define INT_MSK3_GPIO5_R_IT_MSK_SHIFT 2
652 #define INT_MSK3_GPIO4_F_IT_MSK_MASK 0x02 653 #define INT_MSK3_GPIO4_F_IT_MSK_MASK 0x02
653 #define INT_MSK3_GPIO4_F_IT_MSK_SHIFT 1 654 #define INT_MSK3_GPIO4_F_IT_MSK_SHIFT 1
654 #define INT_MSK3_GPIO4_R_IT_MSK_MASK 0x01 655 #define INT_MSK3_GPIO4_R_IT_MSK_MASK 0x01
655 #define INT_MSK3_GPIO4_R_IT_MSK_SHIFT 0 656 #define INT_MSK3_GPIO4_R_IT_MSK_SHIFT 0
656 657
657 658
658 /*Register GPIO (0x80) register.RegisterDescription */ 659 /*Register GPIO (0x80) register.RegisterDescription */
659 #define GPIO_DEB_MASK 0x10 660 #define GPIO_DEB_MASK 0x10
660 #define GPIO_DEB_SHIFT 4 661 #define GPIO_DEB_SHIFT 4
661 #define GPIO_PUEN_MASK 0x08 662 #define GPIO_PUEN_MASK 0x08
662 #define GPIO_PUEN_SHIFT 3 663 #define GPIO_PUEN_SHIFT 3
663 #define GPIO_CFG_MASK 0x04 664 #define GPIO_CFG_MASK 0x04
664 #define GPIO_CFG_SHIFT 2 665 #define GPIO_CFG_SHIFT 2
665 #define GPIO_STS_MASK 0x02 666 #define GPIO_STS_MASK 0x02
666 #define GPIO_STS_SHIFT 1 667 #define GPIO_STS_SHIFT 1
667 #define GPIO_SET_MASK 0x01 668 #define GPIO_SET_MASK 0x01
668 #define GPIO_SET_SHIFT 0 669 #define GPIO_SET_SHIFT 0
669 670
670 671
671 /*Register JTAGVERNUM (0x80) register.RegisterDescription */ 672 /*Register JTAGVERNUM (0x80) register.RegisterDescription */
672 #define JTAGVERNUM_VERNUM_MASK 0x0F 673 #define JTAGVERNUM_VERNUM_MASK 0x0F
673 #define JTAGVERNUM_VERNUM_SHIFT 0 674 #define JTAGVERNUM_VERNUM_SHIFT 0
674 675
675 676
676 /* Register VDDCTRL (0x27) bit definitions */ 677 /* Register VDDCTRL (0x27) bit definitions */
677 #define VDDCTRL_ST_MASK 0x03 678 #define VDDCTRL_ST_MASK 0x03
678 #define VDDCTRL_ST_SHIFT 0 679 #define VDDCTRL_ST_SHIFT 0
679 680
680 681
681 /*Register VDDCTRL_OP (0x28) bit definitios */ 682 /*Register VDDCTRL_OP (0x28) bit definitios */
682 #define VDDCTRL_OP_CMD_MASK 0x80 683 #define VDDCTRL_OP_CMD_MASK 0x80
683 #define VDDCTRL_OP_CMD_SHIFT 7 684 #define VDDCTRL_OP_CMD_SHIFT 7
684 #define VDDCTRL_OP_SEL_MASK 0x7F 685 #define VDDCTRL_OP_SEL_MASK 0x7F
685 #define VDDCTRL_OP_SEL_SHIFT 0 686 #define VDDCTRL_OP_SEL_SHIFT 0
686 687
687 688
688 /*Register VDDCTRL_SR (0x29) bit definitions */ 689 /*Register VDDCTRL_SR (0x29) bit definitions */
689 #define VDDCTRL_SR_SEL_MASK 0x7F 690 #define VDDCTRL_SR_SEL_MASK 0x7F
690 #define VDDCTRL_SR_SEL_SHIFT 0 691 #define VDDCTRL_SR_SEL_SHIFT 0
691 692
692 693
693 /* IRQ Definitions */ 694 /* IRQ Definitions */
694 #define TPS65910_IRQ_VBAT_VMBDCH 0 695 #define TPS65910_IRQ_VBAT_VMBDCH 0
695 #define TPS65910_IRQ_VBAT_VMHI 1 696 #define TPS65910_IRQ_VBAT_VMHI 1
696 #define TPS65910_IRQ_PWRON 2 697 #define TPS65910_IRQ_PWRON 2
697 #define TPS65910_IRQ_PWRON_LP 3 698 #define TPS65910_IRQ_PWRON_LP 3
698 #define TPS65910_IRQ_PWRHOLD 4 699 #define TPS65910_IRQ_PWRHOLD 4
699 #define TPS65910_IRQ_HOTDIE 5 700 #define TPS65910_IRQ_HOTDIE 5
700 #define TPS65910_IRQ_RTC_ALARM 6 701 #define TPS65910_IRQ_RTC_ALARM 6
701 #define TPS65910_IRQ_RTC_PERIOD 7 702 #define TPS65910_IRQ_RTC_PERIOD 7
702 #define TPS65910_IRQ_GPIO_R 8 703 #define TPS65910_IRQ_GPIO_R 8
703 #define TPS65910_IRQ_GPIO_F 9 704 #define TPS65910_IRQ_GPIO_F 9
704 #define TPS65910_NUM_IRQ 10 705 #define TPS65910_NUM_IRQ 10
705 706
706 #define TPS65911_IRQ_VBAT_VMBDCH 0 707 #define TPS65911_IRQ_VBAT_VMBDCH 0
707 #define TPS65911_IRQ_VBAT_VMBDCH2L 1 708 #define TPS65911_IRQ_VBAT_VMBDCH2L 1
708 #define TPS65911_IRQ_VBAT_VMBDCH2H 2 709 #define TPS65911_IRQ_VBAT_VMBDCH2H 2
709 #define TPS65911_IRQ_VBAT_VMHI 3 710 #define TPS65911_IRQ_VBAT_VMHI 3
710 #define TPS65911_IRQ_PWRON 4 711 #define TPS65911_IRQ_PWRON 4
711 #define TPS65911_IRQ_PWRON_LP 5 712 #define TPS65911_IRQ_PWRON_LP 5
712 #define TPS65911_IRQ_PWRHOLD_F 6 713 #define TPS65911_IRQ_PWRHOLD_F 6
713 #define TPS65911_IRQ_PWRHOLD_R 7 714 #define TPS65911_IRQ_PWRHOLD_R 7
714 #define TPS65911_IRQ_HOTDIE 8 715 #define TPS65911_IRQ_HOTDIE 8
715 #define TPS65911_IRQ_RTC_ALARM 9 716 #define TPS65911_IRQ_RTC_ALARM 9
716 #define TPS65911_IRQ_RTC_PERIOD 10 717 #define TPS65911_IRQ_RTC_PERIOD 10
717 #define TPS65911_IRQ_GPIO0_R 11 718 #define TPS65911_IRQ_GPIO0_R 11
718 #define TPS65911_IRQ_GPIO0_F 12 719 #define TPS65911_IRQ_GPIO0_F 12
719 #define TPS65911_IRQ_GPIO1_R 13 720 #define TPS65911_IRQ_GPIO1_R 13
720 #define TPS65911_IRQ_GPIO1_F 14 721 #define TPS65911_IRQ_GPIO1_F 14
721 #define TPS65911_IRQ_GPIO2_R 15 722 #define TPS65911_IRQ_GPIO2_R 15
722 #define TPS65911_IRQ_GPIO2_F 16 723 #define TPS65911_IRQ_GPIO2_F 16
723 #define TPS65911_IRQ_GPIO3_R 17 724 #define TPS65911_IRQ_GPIO3_R 17
724 #define TPS65911_IRQ_GPIO3_F 18 725 #define TPS65911_IRQ_GPIO3_F 18
725 #define TPS65911_IRQ_GPIO4_R 19 726 #define TPS65911_IRQ_GPIO4_R 19
726 #define TPS65911_IRQ_GPIO4_F 20 727 #define TPS65911_IRQ_GPIO4_F 20
727 #define TPS65911_IRQ_GPIO5_R 21 728 #define TPS65911_IRQ_GPIO5_R 21
728 #define TPS65911_IRQ_GPIO5_F 22 729 #define TPS65911_IRQ_GPIO5_F 22
729 #define TPS65911_IRQ_WTCHDG 23 730 #define TPS65911_IRQ_WTCHDG 23
730 #define TPS65911_IRQ_PWRDN 24 731 #define TPS65911_IRQ_PWRDN 24
731 732
732 #define TPS65911_NUM_IRQ 25 733 #define TPS65911_NUM_IRQ 25
733 734
734 735
735 /* GPIO Register Definitions */ 736 /* GPIO Register Definitions */
736 #define TPS65910_GPIO_DEB BIT(2) 737 #define TPS65910_GPIO_DEB BIT(2)
737 #define TPS65910_GPIO_PUEN BIT(3) 738 #define TPS65910_GPIO_PUEN BIT(3)
738 #define TPS65910_GPIO_CFG BIT(2) 739 #define TPS65910_GPIO_CFG BIT(2)
739 #define TPS65910_GPIO_STS BIT(1) 740 #define TPS65910_GPIO_STS BIT(1)
740 #define TPS65910_GPIO_SET BIT(0) 741 #define TPS65910_GPIO_SET BIT(0)
741 742
742 /** 743 /**
743 * struct tps65910_board 744 * struct tps65910_board
744 * Board platform data may be used to initialize regulators. 745 * Board platform data may be used to initialize regulators.
745 */ 746 */
746 747
747 struct tps65910_board { 748 struct tps65910_board {
748 int gpio_base; 749 int gpio_base;
749 int irq; 750 int irq;
750 int irq_base; 751 int irq_base;
751 int vmbch_threshold; 752 int vmbch_threshold;
752 int vmbch2_threshold; 753 int vmbch2_threshold;
753 struct regulator_init_data *tps65910_pmic_init_data; 754 struct regulator_init_data *tps65910_pmic_init_data;
754 }; 755 };
755 756
756 /** 757 /**
757 * struct tps65910 - tps65910 sub-driver chip access routines 758 * struct tps65910 - tps65910 sub-driver chip access routines
758 */ 759 */
759 760
760 struct tps65910 { 761 struct tps65910 {
761 struct device *dev; 762 struct device *dev;
762 struct i2c_client *i2c_client; 763 struct i2c_client *i2c_client;
763 struct mutex io_mutex; 764 struct mutex io_mutex;
764 unsigned int id; 765 unsigned int id;
765 int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest); 766 int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest);
766 int (*write)(struct tps65910 *tps65910, u8 reg, int size, void *src); 767 int (*write)(struct tps65910 *tps65910, u8 reg, int size, void *src);
767 768
768 /* Client devices */ 769 /* Client devices */
769 struct tps65910_pmic *pmic; 770 struct tps65910_pmic *pmic;
770 struct tps65910_rtc *rtc; 771 struct tps65910_rtc *rtc;
771 struct tps65910_power *power; 772 struct tps65910_power *power;
772 773
773 /* GPIO Handling */ 774 /* GPIO Handling */
774 struct gpio_chip gpio; 775 struct gpio_chip gpio;
775 776
776 /* IRQ Handling */ 777 /* IRQ Handling */
777 struct mutex irq_lock; 778 struct mutex irq_lock;
778 int chip_irq; 779 int chip_irq;
779 int irq_base; 780 int irq_base;
780 int irq_num; 781 int irq_num;
781 u32 irq_mask; 782 u32 irq_mask;
782 }; 783 };
783 784
784 struct tps65910_platform_data { 785 struct tps65910_platform_data {
785 int irq; 786 int irq;
786 int irq_base; 787 int irq_base;
787 }; 788 };
788 789
789 int tps65910_set_bits(struct tps65910 *tps65910, u8 reg, u8 mask); 790 int tps65910_set_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
790 int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask); 791 int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
791 void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base); 792 void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base);
792 int tps65910_irq_init(struct tps65910 *tps65910, int irq, 793 int tps65910_irq_init(struct tps65910 *tps65910, int irq,
793 struct tps65910_platform_data *pdata); 794 struct tps65910_platform_data *pdata);
794 int tps65910_irq_exit(struct tps65910 *tps65910); 795 int tps65910_irq_exit(struct tps65910 *tps65910);
795 796
796 static inline int tps65910_chip_id(struct tps65910 *tps65910) 797 static inline int tps65910_chip_id(struct tps65910 *tps65910)
797 { 798 {
798 return tps65910->id; 799 return tps65910->id;
799 } 800 }
800 801
801 #endif /* __LINUX_MFD_TPS65910_H */ 802 #endif /* __LINUX_MFD_TPS65910_H */
802 803