Doug / smarc-fsl-linux-kernel

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/*

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/*

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* pata-legacy.c - Legacy port PATA/SATA controller driver.

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* pata-legacy.c - Legacy port PATA/SATA controller driver.

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*

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*

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* This program is free software; you can redistribute it and/or modify

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* This program is free software; you can redistribute it and/or modify

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* it under the terms of the GNU General Public License as published by

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* it under the terms of the GNU General Public License as published by

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* the Free Software Foundation; either version 2, or (at your option)

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* the Free Software Foundation; either version 2, or (at your option)

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* any later version.

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* any later version.

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*

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*

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* This program is distributed in the hope that it will be useful,

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* This program is distributed in the hope that it will be useful,

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* but WITHOUT ANY WARRANTY; without even the implied warranty of

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* but WITHOUT ANY WARRANTY; without even the implied warranty of

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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* GNU General Public License for more details.

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* GNU General Public License for more details.

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*

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*

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* You should have received a copy of the GNU General Public License

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* You should have received a copy of the GNU General Public License

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* along with this program; see the file COPYING. If not, write to

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* along with this program; see the file COPYING. If not, write to

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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.

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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.

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*

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*

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* An ATA driver for the legacy ATA ports.

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* An ATA driver for the legacy ATA ports.

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*

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*

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* Data Sources:

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* Data Sources:

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* Opti 82C465/82C611 support: Data sheets at opti-inc.com

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* Opti 82C465/82C611 support: Data sheets at opti-inc.com

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* HT6560 series:

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* HT6560 series:

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* Promise 20230/20620:

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* Promise 20230/20620:

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* http://www.ryston.cz/petr/vlb/pdc20230b.html

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* http://www.ryston.cz/petr/vlb/pdc20230b.html

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* http://www.ryston.cz/petr/vlb/pdc20230c.html

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* http://www.ryston.cz/petr/vlb/pdc20230c.html

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* http://www.ryston.cz/petr/vlb/pdc20630.html

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* http://www.ryston.cz/petr/vlb/pdc20630.html

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* QDI65x0:

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* QDI65x0:

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* http://www.ryston.cz/petr/vlb/qd6500.html

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* http://www.ryston.cz/petr/vlb/qd6500.html

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* http://www.ryston.cz/petr/vlb/qd6580.html

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* http://www.ryston.cz/petr/vlb/qd6580.html

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*

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*

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* QDI65x0 probe code based on drivers/ide/legacy/qd65xx.c

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* QDI65x0 probe code based on drivers/ide/legacy/qd65xx.c

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* Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by

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* Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by

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* Samuel Thibault <samuel.thibault@ens-lyon.org>

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* Samuel Thibault <samuel.thibault@ens-lyon.org>

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*

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*

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* Unsupported but docs exist:

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* Unsupported but docs exist:

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* Appian/Adaptec AIC25VL01/Cirrus Logic PD7220

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* Appian/Adaptec AIC25VL01/Cirrus Logic PD7220

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*

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*

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* This driver handles legacy (that is "ISA/VLB side") IDE ports found

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* This driver handles legacy (that is "ISA/VLB side") IDE ports found

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* on PC class systems. There are three hybrid devices that are exceptions

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* on PC class systems. There are three hybrid devices that are exceptions

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* The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and

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* The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and

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* the MPIIX where the tuning is PCI side but the IDE is "ISA side".

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* the MPIIX where the tuning is PCI side but the IDE is "ISA side".

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*

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*

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* Specific support is included for the ht6560a/ht6560b/opti82c611a/

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* Specific support is included for the ht6560a/ht6560b/opti82c611a/

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* opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A

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* opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A

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*

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*

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* Support for the Winbond 83759A when operating in advanced mode.

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* Support for the Winbond 83759A when operating in advanced mode.

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* Multichip mode is not currently supported.

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* Multichip mode is not currently supported.

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*

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*

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* Use the autospeed and pio_mask options with:

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* Use the autospeed and pio_mask options with:

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* Appian ADI/2 aka CLPD7220 or AIC25VL01.

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* Appian ADI/2 aka CLPD7220 or AIC25VL01.

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* Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with

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* Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with

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* Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,

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* Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,

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* Winbond W83759A, Promise PDC20230-B

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* Winbond W83759A, Promise PDC20230-B

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*

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*

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* For now use autospeed and pio_mask as above with the W83759A. This may

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* For now use autospeed and pio_mask as above with the W83759A. This may

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* change.

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* change.

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*

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*

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*/

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*/

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#include <linux/async.h>

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#include <linux/async.h>

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#include <linux/kernel.h>

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#include <linux/kernel.h>

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#include <linux/module.h>

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#include <linux/module.h>

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#include <linux/pci.h>

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#include <linux/pci.h>

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#include <linux/init.h>

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#include <linux/init.h>

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#include <linux/blkdev.h>

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#include <linux/blkdev.h>

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#include <linux/delay.h>

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#include <linux/delay.h>

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#include <scsi/scsi_host.h>

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#include <scsi/scsi_host.h>

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#include <linux/ata.h>

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#include <linux/ata.h>

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#include <linux/libata.h>

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#include <linux/libata.h>

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#include <linux/platform_device.h>

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#include <linux/platform_device.h>

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#define DRV_NAME "pata_legacy"

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#define DRV_NAME "pata_legacy"

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#define DRV_VERSION "0.6.5"

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#define DRV_VERSION "0.6.5"

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#define NR_HOST 6

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#define NR_HOST 6

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static int all;

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static int all;

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module_param(all, int, 0444);

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module_param(all, int, 0444);

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MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)");

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MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)");

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struct legacy_data {

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struct legacy_data {

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unsigned long timing;

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unsigned long timing;

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u8 clock[2];

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u8 clock[2];

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u8 last;

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u8 last;

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int fast;

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int fast;

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struct platform_device *platform_dev;

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struct platform_device *platform_dev;

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};

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};

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enum controller {

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enum controller {

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BIOS = 0,

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BIOS = 0,

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SNOOP = 1,

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SNOOP = 1,

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PDC20230 = 2,

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PDC20230 = 2,

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HT6560A = 3,

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HT6560A = 3,

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HT6560B = 4,

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HT6560B = 4,

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OPTI611A = 5,

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OPTI611A = 5,

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OPTI46X = 6,

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OPTI46X = 6,

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QDI6500 = 7,

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QDI6500 = 7,

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QDI6580 = 8,

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QDI6580 = 8,

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QDI6580DP = 9, /* Dual channel mode is different */

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QDI6580DP = 9, /* Dual channel mode is different */

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W83759A = 10,

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W83759A = 10,

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UNKNOWN = -1

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UNKNOWN = -1

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};

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};

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struct legacy_probe {

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struct legacy_probe {

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unsigned char *name;

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unsigned char *name;

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unsigned long port;

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unsigned long port;

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unsigned int irq;

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unsigned int irq;

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unsigned int slot;

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unsigned int slot;

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enum controller type;

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enum controller type;

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unsigned long private;

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unsigned long private;

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};

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};

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struct legacy_controller {

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struct legacy_controller {

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const char *name;

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const char *name;

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struct ata_port_operations *ops;

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struct ata_port_operations *ops;

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unsigned int pio_mask;

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unsigned int pio_mask;

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unsigned int flags;

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unsigned int flags;

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unsigned int pflags;

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unsigned int pflags;

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int (*setup)(struct platform_device *, struct legacy_probe *probe,

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int (*setup)(struct platform_device *, struct legacy_probe *probe,

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struct legacy_data *data);

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struct legacy_data *data);

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};

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};

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static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };

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static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };

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static struct legacy_probe probe_list[NR_HOST];

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static struct legacy_probe probe_list[NR_HOST];

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static struct legacy_data legacy_data[NR_HOST];

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static struct legacy_data legacy_data[NR_HOST];

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static struct ata_host *legacy_host[NR_HOST];

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static struct ata_host *legacy_host[NR_HOST];

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static int nr_legacy_host;

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static int nr_legacy_host;

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static int probe_all; /* Set to check all ISA port ranges */

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static int probe_all; /* Set to check all ISA port ranges */

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static int ht6560a; /* HT 6560A on primary 1, second 2, both 3 */

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static int ht6560a; /* HT 6560A on primary 1, second 2, both 3 */

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static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */

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static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */

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static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */

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static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */

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static int opti82c46x; /* Opti 82c465MV present(pri/sec autodetect) */

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static int opti82c46x; /* Opti 82c465MV present(pri/sec autodetect) */

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static int qdi; /* Set to probe QDI controllers */

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static int autospeed; /* Chip present which snoops speed changes */

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static int autospeed; /* Chip present which snoops speed changes */

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static int pio_mask = ATA_PIO4; /* PIO range for autospeed devices */

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static int pio_mask = ATA_PIO4; /* PIO range for autospeed devices */

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static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */

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static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */

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/* Set to probe QDI controllers */

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#ifdef CONFIG_PATA_QDI_MODULE

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static int qdi = 1;

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#else

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static int qdi;

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#endif

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#ifdef CONFIG_PATA_WINBOND_VLB_MODULE

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#ifdef CONFIG_PATA_WINBOND_VLB_MODULE

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static int winbond = 1; /* Set to probe Winbond controllers,

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static int winbond = 1; /* Set to probe Winbond controllers,

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give I/O port if non standard */

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give I/O port if non standard */

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#else

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#else

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static int winbond; /* Set to probe Winbond controllers,

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static int winbond; /* Set to probe Winbond controllers,

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give I/O port if non standard */

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give I/O port if non standard */

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#endif

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#endif

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/**

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/**

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* legacy_probe_add - Add interface to probe list

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* legacy_probe_add - Add interface to probe list

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* @port: Controller port

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* @port: Controller port

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* @irq: IRQ number

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* @irq: IRQ number

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* @type: Controller type

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* @type: Controller type

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* @private: Controller specific info

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* @private: Controller specific info

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*

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*

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* Add an entry into the probe list for ATA controllers. This is used

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* Add an entry into the probe list for ATA controllers. This is used

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* to add the default ISA slots and then to build up the table

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* to add the default ISA slots and then to build up the table

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* further according to other ISA/VLB/Weird device scans

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* further according to other ISA/VLB/Weird device scans

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*

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*

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* An I/O port list is used to keep ordering stable and sane, as we

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* An I/O port list is used to keep ordering stable and sane, as we

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* don't have any good way to talk about ordering otherwise

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* don't have any good way to talk about ordering otherwise

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*/

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*/

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static int legacy_probe_add(unsigned long port, unsigned int irq,

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static int legacy_probe_add(unsigned long port, unsigned int irq,

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enum controller type, unsigned long private)

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enum controller type, unsigned long private)

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{

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{

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struct legacy_probe *lp = &probe_list[0];

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struct legacy_probe *lp = &probe_list[0];

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int i;

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int i;

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struct legacy_probe *free = NULL;

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struct legacy_probe *free = NULL;

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for (i = 0; i < NR_HOST; i++) {

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for (i = 0; i < NR_HOST; i++) {

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if (lp->port == 0 && free == NULL)

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if (lp->port == 0 && free == NULL)

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free = lp;

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free = lp;

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/* Matching port, or the correct slot for ordering */

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/* Matching port, or the correct slot for ordering */

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if (lp->port == port || legacy_port[i] == port) {

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if (lp->port == port || legacy_port[i] == port) {

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free = lp;

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free = lp;

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break;

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break;

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}

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}

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lp++;

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lp++;

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}

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}

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if (free == NULL) {

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if (free == NULL) {

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printk(KERN_ERR "pata_legacy: Too many interfaces.\n");

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printk(KERN_ERR "pata_legacy: Too many interfaces.\n");

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return -1;

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return -1;

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}

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}

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/* Fill in the entry for later probing */

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/* Fill in the entry for later probing */

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free->port = port;

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free->port = port;

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free->irq = irq;

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free->irq = irq;

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free->type = type;

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free->type = type;

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free->private = private;

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free->private = private;

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return 0;

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return 0;

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}

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}

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/**

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/**

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* legacy_set_mode - mode setting

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* legacy_set_mode - mode setting

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* @link: IDE link

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* @link: IDE link

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* @unused: Device that failed when error is returned

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* @unused: Device that failed when error is returned

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*

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*

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* Use a non standard set_mode function. We don't want to be tuned.

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* Use a non standard set_mode function. We don't want to be tuned.

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*

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*

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* The BIOS configured everything. Our job is not to fiddle. Just use

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* The BIOS configured everything. Our job is not to fiddle. Just use

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* whatever PIO the hardware is using and leave it at that. When we

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* whatever PIO the hardware is using and leave it at that. When we

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* get some kind of nice user driven API for control then we can

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* get some kind of nice user driven API for control then we can

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* expand on this as per hdparm in the base kernel.

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* expand on this as per hdparm in the base kernel.

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*/

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*/

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static int legacy_set_mode(struct ata_link *link, struct ata_device **unused)

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static int legacy_set_mode(struct ata_link *link, struct ata_device **unused)

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{

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{

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struct ata_device *dev;

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struct ata_device *dev;

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ata_for_each_dev(dev, link, ENABLED) {

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ata_for_each_dev(dev, link, ENABLED) {

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ata_dev_info(dev, "configured for PIO\n");

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ata_dev_info(dev, "configured for PIO\n");

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dev->pio_mode = XFER_PIO_0;

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dev->pio_mode = XFER_PIO_0;

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dev->xfer_mode = XFER_PIO_0;

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dev->xfer_mode = XFER_PIO_0;

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dev->xfer_shift = ATA_SHIFT_PIO;

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dev->xfer_shift = ATA_SHIFT_PIO;

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dev->flags |= ATA_DFLAG_PIO;

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dev->flags |= ATA_DFLAG_PIO;

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}

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}

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return 0;

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return 0;

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}

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}

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static struct scsi_host_template legacy_sht = {

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static struct scsi_host_template legacy_sht = {

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ATA_PIO_SHT(DRV_NAME),

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ATA_PIO_SHT(DRV_NAME),

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};

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};

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static const struct ata_port_operations legacy_base_port_ops = {

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static const struct ata_port_operations legacy_base_port_ops = {

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.inherits = &ata_sff_port_ops,

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.inherits = &ata_sff_port_ops,

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.cable_detect = ata_cable_40wire,

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.cable_detect = ata_cable_40wire,

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};

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};

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/*

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/*

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* These ops are used if the user indicates the hardware

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* These ops are used if the user indicates the hardware

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* snoops the commands to decide on the mode and handles the

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* snoops the commands to decide on the mode and handles the

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* mode selection "magically" itself. Several legacy controllers

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* mode selection "magically" itself. Several legacy controllers

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* do this. The mode range can be set if it is not 0x1F by setting

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* do this. The mode range can be set if it is not 0x1F by setting

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* pio_mask as well.

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* pio_mask as well.

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*/

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*/

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static struct ata_port_operations simple_port_ops = {

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static struct ata_port_operations simple_port_ops = {

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.inherits = &legacy_base_port_ops,

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.inherits = &legacy_base_port_ops,

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.sff_data_xfer = ata_sff_data_xfer_noirq,

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.sff_data_xfer = ata_sff_data_xfer_noirq,

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};

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};

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static struct ata_port_operations legacy_port_ops = {

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static struct ata_port_operations legacy_port_ops = {

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.inherits = &legacy_base_port_ops,

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.inherits = &legacy_base_port_ops,

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.sff_data_xfer = ata_sff_data_xfer_noirq,

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.sff_data_xfer = ata_sff_data_xfer_noirq,

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.set_mode = legacy_set_mode,

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.set_mode = legacy_set_mode,

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};

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};

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/*

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/*

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* Promise 20230C and 20620 support

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* Promise 20230C and 20620 support

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*

261

*

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* This controller supports PIO0 to PIO2. We set PIO timings

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* This controller supports PIO0 to PIO2. We set PIO timings

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* conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA

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* conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA

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* support is weird being DMA to controller and PIO'd to the host

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* support is weird being DMA to controller and PIO'd to the host

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* and not supported.

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* and not supported.

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*/

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*/

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static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)

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static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)

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{

269

{

264

int tries = 5;

270

int tries = 5;

265

int pio = adev->pio_mode - XFER_PIO_0;

271

int pio = adev->pio_mode - XFER_PIO_0;

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u8 rt;

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u8 rt;

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unsigned long flags;

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unsigned long flags;

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274

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/* Safe as UP only. Force I/Os to occur together */

275

/* Safe as UP only. Force I/Os to occur together */

270

276

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local_irq_save(flags);

277

local_irq_save(flags);

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278

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/* Unlock the control interface */

279

/* Unlock the control interface */

274

do {

280

do {

275

inb(0x1F5);

281

inb(0x1F5);

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outb(inb(0x1F2) | 0x80, 0x1F2);

282

outb(inb(0x1F2) | 0x80, 0x1F2);

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inb(0x1F2);

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inb(0x1F2);

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inb(0x3F6);

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inb(0x3F6);

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inb(0x3F6);

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inb(0x3F6);

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inb(0x1F2);

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inb(0x1F2);

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inb(0x1F2);

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inb(0x1F2);

282

}

288

}

283

while ((inb(0x1F2) & 0x80) && --tries);

289

while ((inb(0x1F2) & 0x80) && --tries);

284

290

285

local_irq_restore(flags);

291

local_irq_restore(flags);

286

292

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outb(inb(0x1F4) & 0x07, 0x1F4);

293

outb(inb(0x1F4) & 0x07, 0x1F4);

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294

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rt = inb(0x1F3);

295

rt = inb(0x1F3);

290

rt &= 0x07 << (3 * adev->devno);

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rt &= 0x07 << (3 * adev->devno);

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if (pio)

297

if (pio)

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rt |= (1 + 3 * pio) << (3 * adev->devno);

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rt |= (1 + 3 * pio) << (3 * adev->devno);

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299

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udelay(100);

300

udelay(100);

295

outb(inb(0x1F2) | 0x01, 0x1F2);

301

outb(inb(0x1F2) | 0x01, 0x1F2);

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udelay(100);

302

udelay(100);

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inb(0x1F5);

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inb(0x1F5);

298

304

299

}

305

}

300

306

301

static unsigned int pdc_data_xfer_vlb(struct ata_device *dev,

307

static unsigned int pdc_data_xfer_vlb(struct ata_device *dev,

302

unsigned char *buf, unsigned int buflen, int rw)

308

unsigned char *buf, unsigned int buflen, int rw)

303

{

309

{

304

int slop = buflen & 3;

310

int slop = buflen & 3;

305

struct ata_port *ap = dev->link->ap;

311

struct ata_port *ap = dev->link->ap;

306

312

307

/* 32bit I/O capable *and* we need to write a whole number of dwords */

313

/* 32bit I/O capable *and* we need to write a whole number of dwords */

308

if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3)

314

if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3)

309

&& (ap->pflags & ATA_PFLAG_PIO32)) {

315

&& (ap->pflags & ATA_PFLAG_PIO32)) {

310

unsigned long flags;

316

unsigned long flags;

311

317

312

local_irq_save(flags);

318

local_irq_save(flags);

313

319

314

/* Perform the 32bit I/O synchronization sequence */

320

/* Perform the 32bit I/O synchronization sequence */

315

ioread8(ap->ioaddr.nsect_addr);

321

ioread8(ap->ioaddr.nsect_addr);

316

ioread8(ap->ioaddr.nsect_addr);

322

ioread8(ap->ioaddr.nsect_addr);

317

ioread8(ap->ioaddr.nsect_addr);

323

ioread8(ap->ioaddr.nsect_addr);

318

324

319

/* Now the data */

325

/* Now the data */

320

if (rw == READ)

326

if (rw == READ)

321

ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);

327

ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);

322

else

328

else

323

iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);

329

iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);

324

330

325

if (unlikely(slop)) {

331

if (unlikely(slop)) {

326

__le32 pad;

332

__le32 pad;

327

if (rw == READ) {

333

if (rw == READ) {

328

pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));

334

pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));

329

memcpy(buf + buflen - slop, &pad, slop);

335

memcpy(buf + buflen - slop, &pad, slop);

330

} else {

336

} else {

331

memcpy(&pad, buf + buflen - slop, slop);

337

memcpy(&pad, buf + buflen - slop, slop);

332

iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);

338

iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);

333

}

339

}

334

buflen += 4 - slop;

340

buflen += 4 - slop;

335

}

341

}

336

local_irq_restore(flags);

342

local_irq_restore(flags);

337

} else

343

} else

338

buflen = ata_sff_data_xfer_noirq(dev, buf, buflen, rw);

344

buflen = ata_sff_data_xfer_noirq(dev, buf, buflen, rw);

339

345

340

return buflen;

346

return buflen;

341

}

347

}

342

348

343

static struct ata_port_operations pdc20230_port_ops = {

349

static struct ata_port_operations pdc20230_port_ops = {

344

.inherits = &legacy_base_port_ops,

350

.inherits = &legacy_base_port_ops,

345

.set_piomode = pdc20230_set_piomode,

351

.set_piomode = pdc20230_set_piomode,

346

.sff_data_xfer = pdc_data_xfer_vlb,

352

.sff_data_xfer = pdc_data_xfer_vlb,

347

};

353

};

348

354

349

/*

355

/*

350

* Holtek 6560A support

356

* Holtek 6560A support

351

*

357

*

352

* This controller supports PIO0 to PIO2 (no IORDY even though higher

358

* This controller supports PIO0 to PIO2 (no IORDY even though higher

353

* timings can be loaded).

359

* timings can be loaded).

354

*/

360

*/

355

361

356

static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)

362

static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)

357

{

363

{

358

u8 active, recover;

364

u8 active, recover;

359

struct ata_timing t;

365

struct ata_timing t;

360

366

361

/* Get the timing data in cycles. For now play safe at 50Mhz */

367

/* Get the timing data in cycles. For now play safe at 50Mhz */

362

ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);

368

ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);

363

369

364

active = clamp_val(t.active, 2, 15);

370

active = clamp_val(t.active, 2, 15);

365

recover = clamp_val(t.recover, 4, 15);

371

recover = clamp_val(t.recover, 4, 15);

366

372

367

inb(0x3E6);

373

inb(0x3E6);

368

inb(0x3E6);

374

inb(0x3E6);

369

inb(0x3E6);

375

inb(0x3E6);

370

inb(0x3E6);

376

inb(0x3E6);

371

377

372

iowrite8(recover << 4 | active, ap->ioaddr.device_addr);

378

iowrite8(recover << 4 | active, ap->ioaddr.device_addr);

373

ioread8(ap->ioaddr.status_addr);

379

ioread8(ap->ioaddr.status_addr);

374

}

380

}

375

381

376

static struct ata_port_operations ht6560a_port_ops = {

382

static struct ata_port_operations ht6560a_port_ops = {

377

.inherits = &legacy_base_port_ops,

383

.inherits = &legacy_base_port_ops,

378

.set_piomode = ht6560a_set_piomode,

384

.set_piomode = ht6560a_set_piomode,

379

};

385

};

380

386

381

/*

387

/*

382

* Holtek 6560B support

388

* Holtek 6560B support

383

*

389

*

384

* This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO

390

* This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO

385

* setting unless we see an ATAPI device in which case we force it off.

391

* setting unless we see an ATAPI device in which case we force it off.

386

*

392

*

387

* FIXME: need to implement 2nd channel support.

393

* FIXME: need to implement 2nd channel support.

388

*/

394

*/

389

395

390

static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)

396

static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)

391

{

397

{

392

u8 active, recover;

398

u8 active, recover;

393

struct ata_timing t;

399

struct ata_timing t;

394

400

395

/* Get the timing data in cycles. For now play safe at 50Mhz */

401

/* Get the timing data in cycles. For now play safe at 50Mhz */

396

ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);

402

ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);

397

403

398

active = clamp_val(t.active, 2, 15);

404

active = clamp_val(t.active, 2, 15);

399

recover = clamp_val(t.recover, 2, 16);

405

recover = clamp_val(t.recover, 2, 16);

400

recover &= 0x15;

406

recover &= 0x15;

401

407

402

inb(0x3E6);

408

inb(0x3E6);

403

inb(0x3E6);

409

inb(0x3E6);

404

inb(0x3E6);

410

inb(0x3E6);

405

inb(0x3E6);

411

inb(0x3E6);

406

412

407

iowrite8(recover << 4 | active, ap->ioaddr.device_addr);

413

iowrite8(recover << 4 | active, ap->ioaddr.device_addr);

408

414

409

if (adev->class != ATA_DEV_ATA) {

415

if (adev->class != ATA_DEV_ATA) {

410

u8 rconf = inb(0x3E6);

416

u8 rconf = inb(0x3E6);

411

if (rconf & 0x24) {

417

if (rconf & 0x24) {

412

rconf &= ~0x24;

418

rconf &= ~0x24;

413

outb(rconf, 0x3E6);

419

outb(rconf, 0x3E6);

414

}

420

}

415

}

421

}

416

ioread8(ap->ioaddr.status_addr);

422

ioread8(ap->ioaddr.status_addr);

417

}

423

}

418

424

419

static struct ata_port_operations ht6560b_port_ops = {

425

static struct ata_port_operations ht6560b_port_ops = {

420

.inherits = &legacy_base_port_ops,

426

.inherits = &legacy_base_port_ops,

421

.set_piomode = ht6560b_set_piomode,

427

.set_piomode = ht6560b_set_piomode,

422

};

428

};

423

429

424

/*

430

/*

425

* Opti core chipset helpers

431

* Opti core chipset helpers

426

*/

432

*/

427

433

428

/**

434

/**

429

* opti_syscfg - read OPTI chipset configuration

435

* opti_syscfg - read OPTI chipset configuration

430

* @reg: Configuration register to read

436

* @reg: Configuration register to read

431

*

437

*

432

* Returns the value of an OPTI system board configuration register.

438

* Returns the value of an OPTI system board configuration register.

433

*/

439

*/

434

440

435

static u8 opti_syscfg(u8 reg)

441

static u8 opti_syscfg(u8 reg)

436

{

442

{

437

unsigned long flags;

443

unsigned long flags;

438

u8 r;

444

u8 r;

439

445

440

/* Uniprocessor chipset and must force cycles adjancent */

446

/* Uniprocessor chipset and must force cycles adjancent */

441

local_irq_save(flags);

447

local_irq_save(flags);

442

outb(reg, 0x22);

448

outb(reg, 0x22);

443

r = inb(0x24);

449

r = inb(0x24);

444

local_irq_restore(flags);

450

local_irq_restore(flags);

445

return r;

451

return r;

446

}

452

}

447

453

448

/*

454

/*

449

* Opti 82C611A

455

* Opti 82C611A

450

*

456

*

451

* This controller supports PIO0 to PIO3.

457

* This controller supports PIO0 to PIO3.

452

*/

458

*/

453

459

454

static void opti82c611a_set_piomode(struct ata_port *ap,

460

static void opti82c611a_set_piomode(struct ata_port *ap,

455

struct ata_device *adev)

461

struct ata_device *adev)

456

{

462

{

457

u8 active, recover, setup;

463

u8 active, recover, setup;

458

struct ata_timing t;

464

struct ata_timing t;

459

struct ata_device *pair = ata_dev_pair(adev);

465

struct ata_device *pair = ata_dev_pair(adev);

460

int clock;

466

int clock;

461

int khz[4] = { 50000, 40000, 33000, 25000 };

467

int khz[4] = { 50000, 40000, 33000, 25000 };

462

u8 rc;

468

u8 rc;

463

469

464

/* Enter configuration mode */

470

/* Enter configuration mode */

465

ioread16(ap->ioaddr.error_addr);

471

ioread16(ap->ioaddr.error_addr);

466

ioread16(ap->ioaddr.error_addr);

472

ioread16(ap->ioaddr.error_addr);

467

iowrite8(3, ap->ioaddr.nsect_addr);

473

iowrite8(3, ap->ioaddr.nsect_addr);

468

474

469

/* Read VLB clock strapping */

475

/* Read VLB clock strapping */

470

clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03];

476

clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03];

471

477

472

/* Get the timing data in cycles */

478

/* Get the timing data in cycles */

473

ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);

479

ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);

474

480

475

/* Setup timing is shared */

481

/* Setup timing is shared */

476

if (pair) {

482

if (pair) {

477

struct ata_timing tp;

483

struct ata_timing tp;

478

ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);

484

ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);

479

485

480

ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);

486

ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);

481

}

487

}

482

488

483

active = clamp_val(t.active, 2, 17) - 2;

489

active = clamp_val(t.active, 2, 17) - 2;

484

recover = clamp_val(t.recover, 1, 16) - 1;

490

recover = clamp_val(t.recover, 1, 16) - 1;

485

setup = clamp_val(t.setup, 1, 4) - 1;

491

setup = clamp_val(t.setup, 1, 4) - 1;

486

492

487

/* Select the right timing bank for write timing */

493

/* Select the right timing bank for write timing */

488

rc = ioread8(ap->ioaddr.lbal_addr);

494

rc = ioread8(ap->ioaddr.lbal_addr);

489

rc &= 0x7F;

495

rc &= 0x7F;

490

rc |= (adev->devno << 7);

496

rc |= (adev->devno << 7);

491

iowrite8(rc, ap->ioaddr.lbal_addr);

497

iowrite8(rc, ap->ioaddr.lbal_addr);

492

498

493

/* Write the timings */

499

/* Write the timings */

494

iowrite8(active << 4 | recover, ap->ioaddr.error_addr);

500

iowrite8(active << 4 | recover, ap->ioaddr.error_addr);

495

501

496

/* Select the right bank for read timings, also

502

/* Select the right bank for read timings, also

497

load the shared timings for address */

503

load the shared timings for address */

498

rc = ioread8(ap->ioaddr.device_addr);

504

rc = ioread8(ap->ioaddr.device_addr);

499

rc &= 0xC0;

505

rc &= 0xC0;

500

rc |= adev->devno; /* Index select */

506

rc |= adev->devno; /* Index select */

501

rc |= (setup << 4) | 0x04;

507

rc |= (setup << 4) | 0x04;

502

iowrite8(rc, ap->ioaddr.device_addr);

508

iowrite8(rc, ap->ioaddr.device_addr);

503

509

504

/* Load the read timings */

510

/* Load the read timings */

505

iowrite8(active << 4 | recover, ap->ioaddr.data_addr);

511

iowrite8(active << 4 | recover, ap->ioaddr.data_addr);

506

512

507

/* Ensure the timing register mode is right */

513

/* Ensure the timing register mode is right */

508

rc = ioread8(ap->ioaddr.lbal_addr);

514

rc = ioread8(ap->ioaddr.lbal_addr);

509

rc &= 0x73;

515

rc &= 0x73;

510

rc |= 0x84;

516

rc |= 0x84;

511

iowrite8(rc, ap->ioaddr.lbal_addr);

517

iowrite8(rc, ap->ioaddr.lbal_addr);

512

518

513

/* Exit command mode */

519

/* Exit command mode */

514

iowrite8(0x83, ap->ioaddr.nsect_addr);

520

iowrite8(0x83, ap->ioaddr.nsect_addr);

515

}

521

}

516

522

517

523

518

static struct ata_port_operations opti82c611a_port_ops = {

524

static struct ata_port_operations opti82c611a_port_ops = {

519

.inherits = &legacy_base_port_ops,

525

.inherits = &legacy_base_port_ops,

520

.set_piomode = opti82c611a_set_piomode,

526

.set_piomode = opti82c611a_set_piomode,

521

};

527

};

522

528

523

/*

529

/*

524

* Opti 82C465MV

530

* Opti 82C465MV

525

*

531

*

526

* This controller supports PIO0 to PIO3. Unlike the 611A the MVB

532

* This controller supports PIO0 to PIO3. Unlike the 611A the MVB

527

* version is dual channel but doesn't have a lot of unique registers.

533

* version is dual channel but doesn't have a lot of unique registers.

528

*/

534

*/

529

535

530

static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)

536

static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)

531

{

537

{

532

u8 active, recover, setup;

538

u8 active, recover, setup;

533

struct ata_timing t;

539

struct ata_timing t;

534

struct ata_device *pair = ata_dev_pair(adev);

540

struct ata_device *pair = ata_dev_pair(adev);

535

int clock;

541

int clock;

536

int khz[4] = { 50000, 40000, 33000, 25000 };

542

int khz[4] = { 50000, 40000, 33000, 25000 };

537

u8 rc;

543

u8 rc;

538

u8 sysclk;

544

u8 sysclk;

539

545

540

/* Get the clock */

546

/* Get the clock */

541

sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */

547

sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */

542

548

543

/* Enter configuration mode */

549

/* Enter configuration mode */

544

ioread16(ap->ioaddr.error_addr);

550

ioread16(ap->ioaddr.error_addr);

545

ioread16(ap->ioaddr.error_addr);

551

ioread16(ap->ioaddr.error_addr);

546

iowrite8(3, ap->ioaddr.nsect_addr);

552

iowrite8(3, ap->ioaddr.nsect_addr);

547

553

548

/* Read VLB clock strapping */

554

/* Read VLB clock strapping */

549

clock = 1000000000 / khz[sysclk];

555

clock = 1000000000 / khz[sysclk];

550

556

551

/* Get the timing data in cycles */

557

/* Get the timing data in cycles */

552

ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);

558

ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);

553

559

554

/* Setup timing is shared */

560

/* Setup timing is shared */

555

if (pair) {

561

if (pair) {

556

struct ata_timing tp;

562

struct ata_timing tp;

557

ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);

563

ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);

558

564

559

ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);

565

ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);

560

}

566

}

561

567

562

active = clamp_val(t.active, 2, 17) - 2;

568

active = clamp_val(t.active, 2, 17) - 2;

563

recover = clamp_val(t.recover, 1, 16) - 1;

569

recover = clamp_val(t.recover, 1, 16) - 1;

564

setup = clamp_val(t.setup, 1, 4) - 1;

570

setup = clamp_val(t.setup, 1, 4) - 1;

565

571

566

/* Select the right timing bank for write timing */

572

/* Select the right timing bank for write timing */

567

rc = ioread8(ap->ioaddr.lbal_addr);

573

rc = ioread8(ap->ioaddr.lbal_addr);

568

rc &= 0x7F;

574

rc &= 0x7F;

569

rc |= (adev->devno << 7);

575

rc |= (adev->devno << 7);

570

iowrite8(rc, ap->ioaddr.lbal_addr);

576

iowrite8(rc, ap->ioaddr.lbal_addr);

571

577

572

/* Write the timings */

578

/* Write the timings */

573

iowrite8(active << 4 | recover, ap->ioaddr.error_addr);

579

iowrite8(active << 4 | recover, ap->ioaddr.error_addr);

574

580

575

/* Select the right bank for read timings, also

581

/* Select the right bank for read timings, also

576

load the shared timings for address */

582

load the shared timings for address */

577

rc = ioread8(ap->ioaddr.device_addr);

583

rc = ioread8(ap->ioaddr.device_addr);

578

rc &= 0xC0;

584

rc &= 0xC0;

579

rc |= adev->devno; /* Index select */

585

rc |= adev->devno; /* Index select */

580

rc |= (setup << 4) | 0x04;

586

rc |= (setup << 4) | 0x04;

581

iowrite8(rc, ap->ioaddr.device_addr);

587

iowrite8(rc, ap->ioaddr.device_addr);

582

588

583

/* Load the read timings */

589

/* Load the read timings */

584

iowrite8(active << 4 | recover, ap->ioaddr.data_addr);

590

iowrite8(active << 4 | recover, ap->ioaddr.data_addr);

585

591

586

/* Ensure the timing register mode is right */

592

/* Ensure the timing register mode is right */

587

rc = ioread8(ap->ioaddr.lbal_addr);

593

rc = ioread8(ap->ioaddr.lbal_addr);

588

rc &= 0x73;

594

rc &= 0x73;

589

rc |= 0x84;

595

rc |= 0x84;

590

iowrite8(rc, ap->ioaddr.lbal_addr);

596

iowrite8(rc, ap->ioaddr.lbal_addr);

591

597

592

/* Exit command mode */

598

/* Exit command mode */

593

iowrite8(0x83, ap->ioaddr.nsect_addr);

599

iowrite8(0x83, ap->ioaddr.nsect_addr);

594

600

595

/* We need to know this for quad device on the MVB */

601

/* We need to know this for quad device on the MVB */

596

ap->host->private_data = ap;

602

ap->host->private_data = ap;

597

}

603

}

598

604

599

/**

605

/**

600

* opt82c465mv_qc_issue - command issue

606

* opt82c465mv_qc_issue - command issue

601

* @qc: command pending

607

* @qc: command pending

602

*

608

*

603

* Called when the libata layer is about to issue a command. We wrap

609

* Called when the libata layer is about to issue a command. We wrap

604

* this interface so that we can load the correct ATA timings. The

610

* this interface so that we can load the correct ATA timings. The

605

* MVB has a single set of timing registers and these are shared

611

* MVB has a single set of timing registers and these are shared

606

* across channels. As there are two registers we really ought to

612

* across channels. As there are two registers we really ought to

607

* track the last two used values as a sort of register window. For

613

* track the last two used values as a sort of register window. For

608

* now we just reload on a channel switch. On the single channel

614

* now we just reload on a channel switch. On the single channel

609

* setup this condition never fires so we do nothing extra.

615

* setup this condition never fires so we do nothing extra.

610

*

616

*

611

* FIXME: dual channel needs ->serialize support

617

* FIXME: dual channel needs ->serialize support

612

*/

618

*/

613

619

614

static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc)

620

static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc)

615

{

621

{

616

struct ata_port *ap = qc->ap;

622

struct ata_port *ap = qc->ap;

617

struct ata_device *adev = qc->dev;

623

struct ata_device *adev = qc->dev;

618

624

619

/* If timings are set and for the wrong channel (2nd test is

625

/* If timings are set and for the wrong channel (2nd test is

620

due to a libata shortcoming and will eventually go I hope) */

626

due to a libata shortcoming and will eventually go I hope) */

621

if (ap->host->private_data != ap->host

627

if (ap->host->private_data != ap->host

622

&& ap->host->private_data != NULL)

628

&& ap->host->private_data != NULL)

623

opti82c46x_set_piomode(ap, adev);

629

opti82c46x_set_piomode(ap, adev);

624

630

625

return ata_sff_qc_issue(qc);

631

return ata_sff_qc_issue(qc);

626

}

632

}

627

633

628

static struct ata_port_operations opti82c46x_port_ops = {

634

static struct ata_port_operations opti82c46x_port_ops = {

629

.inherits = &legacy_base_port_ops,

635

.inherits = &legacy_base_port_ops,

630

.set_piomode = opti82c46x_set_piomode,

636

.set_piomode = opti82c46x_set_piomode,

631

.qc_issue = opti82c46x_qc_issue,

637

.qc_issue = opti82c46x_qc_issue,

632

};

638

};

633

639

634

static void qdi6500_set_piomode(struct ata_port *ap, struct ata_device *adev)

640

static void qdi6500_set_piomode(struct ata_port *ap, struct ata_device *adev)

635

{

641

{

636

struct ata_timing t;

642

struct ata_timing t;

637

struct legacy_data *ld_qdi = ap->host->private_data;

643

struct legacy_data *ld_qdi = ap->host->private_data;

638

int active, recovery;

644

int active, recovery;

639

u8 timing;

645

u8 timing;

640

646

641

/* Get the timing data in cycles */

647

/* Get the timing data in cycles */

642

ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);

648

ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);

643

649

644

if (ld_qdi->fast) {

650

if (ld_qdi->fast) {

645

active = 8 - clamp_val(t.active, 1, 8);

651

active = 8 - clamp_val(t.active, 1, 8);

646

recovery = 18 - clamp_val(t.recover, 3, 18);

652

recovery = 18 - clamp_val(t.recover, 3, 18);

647

} else {

653

} else {

648

active = 9 - clamp_val(t.active, 2, 9);

654

active = 9 - clamp_val(t.active, 2, 9);

649

recovery = 15 - clamp_val(t.recover, 0, 15);

655

recovery = 15 - clamp_val(t.recover, 0, 15);

650

}

656

}

651

timing = (recovery << 4) | active | 0x08;

657

timing = (recovery << 4) | active | 0x08;

652

658

653

ld_qdi->clock[adev->devno] = timing;

659

ld_qdi->clock[adev->devno] = timing;

654

660

655

outb(timing, ld_qdi->timing);

661

outb(timing, ld_qdi->timing);

656

}

662

}

657

663

658

/**

664

/**

659

* qdi6580dp_set_piomode - PIO setup for dual channel

665

* qdi6580dp_set_piomode - PIO setup for dual channel

660

* @ap: Port

666

* @ap: Port

661

* @adev: Device

667

* @adev: Device

662

*

668

*

663

* In dual channel mode the 6580 has one clock per channel and we have

669

* In dual channel mode the 6580 has one clock per channel and we have

664

* to software clockswitch in qc_issue.

670

* to software clockswitch in qc_issue.

665

*/

671

*/

666

672

667

static void qdi6580dp_set_piomode(struct ata_port *ap, struct ata_device *adev)

673

static void qdi6580dp_set_piomode(struct ata_port *ap, struct ata_device *adev)

668

{

674

{

669

struct ata_timing t;

675

struct ata_timing t;

670

struct legacy_data *ld_qdi = ap->host->private_data;

676

struct legacy_data *ld_qdi = ap->host->private_data;

671

int active, recovery;

677

int active, recovery;

672

u8 timing;

678

u8 timing;

673

679

674

/* Get the timing data in cycles */

680

/* Get the timing data in cycles */

675

ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);

681

ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);

676

682

677

if (ld_qdi->fast) {

683

if (ld_qdi->fast) {

678

active = 8 - clamp_val(t.active, 1, 8);

684

active = 8 - clamp_val(t.active, 1, 8);

679

recovery = 18 - clamp_val(t.recover, 3, 18);

685

recovery = 18 - clamp_val(t.recover, 3, 18);

680

} else {

686

} else {

681

active = 9 - clamp_val(t.active, 2, 9);

687

active = 9 - clamp_val(t.active, 2, 9);

682

recovery = 15 - clamp_val(t.recover, 0, 15);

688

recovery = 15 - clamp_val(t.recover, 0, 15);

683

}

689

}

684

timing = (recovery << 4) | active | 0x08;

690

timing = (recovery << 4) | active | 0x08;

685

691

686

ld_qdi->clock[adev->devno] = timing;

692

ld_qdi->clock[adev->devno] = timing;

687

693

688

outb(timing, ld_qdi->timing + 2 * ap->port_no);

694

outb(timing, ld_qdi->timing + 2 * ap->port_no);

689

/* Clear the FIFO */

695

/* Clear the FIFO */

690

if (adev->class != ATA_DEV_ATA)

696

if (adev->class != ATA_DEV_ATA)

691

outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3);

697

outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3);

692

}

698

}

693

699

694

/**

700

/**

695

* qdi6580_set_piomode - PIO setup for single channel

701

* qdi6580_set_piomode - PIO setup for single channel

696

* @ap: Port

702

* @ap: Port

697

* @adev: Device

703

* @adev: Device

698

*

704

*

699

* In single channel mode the 6580 has one clock per device and we can

705

* In single channel mode the 6580 has one clock per device and we can

700

* avoid the requirement to clock switch. We also have to load the timing

706

* avoid the requirement to clock switch. We also have to load the timing

701

* into the right clock according to whether we are master or slave.

707

* into the right clock according to whether we are master or slave.

702

*/

708

*/

703

709

704

static void qdi6580_set_piomode(struct ata_port *ap, struct ata_device *adev)

710

static void qdi6580_set_piomode(struct ata_port *ap, struct ata_device *adev)

705

{

711

{

706

struct ata_timing t;

712

struct ata_timing t;

707

struct legacy_data *ld_qdi = ap->host->private_data;

713

struct legacy_data *ld_qdi = ap->host->private_data;

708

int active, recovery;

714

int active, recovery;

709

u8 timing;

715

u8 timing;

710

716

711

/* Get the timing data in cycles */

717

/* Get the timing data in cycles */

712

ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);

718

ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);

713

719

714

if (ld_qdi->fast) {

720

if (ld_qdi->fast) {

715

active = 8 - clamp_val(t.active, 1, 8);

721

active = 8 - clamp_val(t.active, 1, 8);

716

recovery = 18 - clamp_val(t.recover, 3, 18);

722

recovery = 18 - clamp_val(t.recover, 3, 18);

717

} else {

723

} else {

718

active = 9 - clamp_val(t.active, 2, 9);

724

active = 9 - clamp_val(t.active, 2, 9);

719

recovery = 15 - clamp_val(t.recover, 0, 15);

725

recovery = 15 - clamp_val(t.recover, 0, 15);

720

}

726

}

721

timing = (recovery << 4) | active | 0x08;

727

timing = (recovery << 4) | active | 0x08;

722

ld_qdi->clock[adev->devno] = timing;

728

ld_qdi->clock[adev->devno] = timing;

723

outb(timing, ld_qdi->timing + 2 * adev->devno);

729

outb(timing, ld_qdi->timing + 2 * adev->devno);

724

/* Clear the FIFO */

730

/* Clear the FIFO */

725

if (adev->class != ATA_DEV_ATA)

731

if (adev->class != ATA_DEV_ATA)

726

outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3);

732

outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3);

727

}

733

}

728

734

729

/**

735

/**

730

* qdi_qc_issue - command issue

736

* qdi_qc_issue - command issue

731

* @qc: command pending

737

* @qc: command pending

732

*

738

*

733

* Called when the libata layer is about to issue a command. We wrap

739

* Called when the libata layer is about to issue a command. We wrap

734

* this interface so that we can load the correct ATA timings.

740

* this interface so that we can load the correct ATA timings.

735

*/

741

*/

736

742

737

static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc)

743

static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc)

738

{

744

{

739

struct ata_port *ap = qc->ap;

745

struct ata_port *ap = qc->ap;

740

struct ata_device *adev = qc->dev;

746

struct ata_device *adev = qc->dev;

741

struct legacy_data *ld_qdi = ap->host->private_data;

747

struct legacy_data *ld_qdi = ap->host->private_data;

742

748

743

if (ld_qdi->clock[adev->devno] != ld_qdi->last) {

749

if (ld_qdi->clock[adev->devno] != ld_qdi->last) {

744

if (adev->pio_mode) {

750

if (adev->pio_mode) {

745

ld_qdi->last = ld_qdi->clock[adev->devno];

751

ld_qdi->last = ld_qdi->clock[adev->devno];

746

outb(ld_qdi->clock[adev->devno], ld_qdi->timing +

752

outb(ld_qdi->clock[adev->devno], ld_qdi->timing +

747

2 * ap->port_no);

753

2 * ap->port_no);

748

}

754

}

749

}

755

}

750

return ata_sff_qc_issue(qc);

756

return ata_sff_qc_issue(qc);

751

}

757

}

752

758

753

static unsigned int vlb32_data_xfer(struct ata_device *adev, unsigned char *buf,

759

static unsigned int vlb32_data_xfer(struct ata_device *adev, unsigned char *buf,

754

unsigned int buflen, int rw)

760

unsigned int buflen, int rw)

755

{

761

{

756

struct ata_port *ap = adev->link->ap;

762

struct ata_port *ap = adev->link->ap;

757

int slop = buflen & 3;

763

int slop = buflen & 3;

758

764

759

if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3)

765

if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3)

760

&& (ap->pflags & ATA_PFLAG_PIO32)) {

766

&& (ap->pflags & ATA_PFLAG_PIO32)) {

761

if (rw == WRITE)

767

if (rw == WRITE)

762

iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);

768

iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);

763

else

769

else

764

ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);

770

ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);

765

771

766

if (unlikely(slop)) {

772

if (unlikely(slop)) {

767

__le32 pad;

773

__le32 pad;

768

if (rw == WRITE) {

774

if (rw == WRITE) {

769

memcpy(&pad, buf + buflen - slop, slop);

775

memcpy(&pad, buf + buflen - slop, slop);

770

iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);

776

iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);

771

} else {

777

} else {

772

pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));

778

pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));

773

memcpy(buf + buflen - slop, &pad, slop);

779

memcpy(buf + buflen - slop, &pad, slop);

774

}

780

}

775

}

781

}

776

return (buflen + 3) & ~3;

782

return (buflen + 3) & ~3;

777

} else

783

} else

778

return ata_sff_data_xfer(adev, buf, buflen, rw);

784

return ata_sff_data_xfer(adev, buf, buflen, rw);

779

}

785

}

780

786

781

static int qdi_port(struct platform_device *dev,

787

static int qdi_port(struct platform_device *dev,

782

struct legacy_probe *lp, struct legacy_data *ld)

788

struct legacy_probe *lp, struct legacy_data *ld)

783

{

789

{

784

if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL)

790

if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL)

785

return -EBUSY;

791

return -EBUSY;

786

ld->timing = lp->private;

792

ld->timing = lp->private;

787

return 0;

793

return 0;

788

}

794

}

789

795

790

static struct ata_port_operations qdi6500_port_ops = {

796

static struct ata_port_operations qdi6500_port_ops = {

791

.inherits = &legacy_base_port_ops,

797

.inherits = &legacy_base_port_ops,

792

.set_piomode = qdi6500_set_piomode,

798

.set_piomode = qdi6500_set_piomode,

793

.qc_issue = qdi_qc_issue,

799

.qc_issue = qdi_qc_issue,

794

.sff_data_xfer = vlb32_data_xfer,

800

.sff_data_xfer = vlb32_data_xfer,

795

};

801

};

796

802

797

static struct ata_port_operations qdi6580_port_ops = {

803

static struct ata_port_operations qdi6580_port_ops = {

798

.inherits = &legacy_base_port_ops,

804

.inherits = &legacy_base_port_ops,

799

.set_piomode = qdi6580_set_piomode,

805

.set_piomode = qdi6580_set_piomode,

800

.sff_data_xfer = vlb32_data_xfer,

806

.sff_data_xfer = vlb32_data_xfer,

801

};

807

};

802

808

803

static struct ata_port_operations qdi6580dp_port_ops = {

809

static struct ata_port_operations qdi6580dp_port_ops = {

804

.inherits = &legacy_base_port_ops,

810

.inherits = &legacy_base_port_ops,

805

.set_piomode = qdi6580dp_set_piomode,

811

.set_piomode = qdi6580dp_set_piomode,

806

.qc_issue = qdi_qc_issue,

812

.qc_issue = qdi_qc_issue,

807

.sff_data_xfer = vlb32_data_xfer,

813

.sff_data_xfer = vlb32_data_xfer,

808

};

814

};

809

815

810

static DEFINE_SPINLOCK(winbond_lock);

816

static DEFINE_SPINLOCK(winbond_lock);

811

817

812

static void winbond_writecfg(unsigned long port, u8 reg, u8 val)

818

static void winbond_writecfg(unsigned long port, u8 reg, u8 val)

813

{

819

{

814

unsigned long flags;

820

unsigned long flags;

815

spin_lock_irqsave(&winbond_lock, flags);

821

spin_lock_irqsave(&winbond_lock, flags);

816

outb(reg, port + 0x01);

822

outb(reg, port + 0x01);

817

outb(val, port + 0x02);

823

outb(val, port + 0x02);

818

spin_unlock_irqrestore(&winbond_lock, flags);

824

spin_unlock_irqrestore(&winbond_lock, flags);

819

}

825

}

820

826

821

static u8 winbond_readcfg(unsigned long port, u8 reg)

827

static u8 winbond_readcfg(unsigned long port, u8 reg)

822

{

828

{

823

u8 val;

829

u8 val;

824

830

825

unsigned long flags;

831

unsigned long flags;

826

spin_lock_irqsave(&winbond_lock, flags);

832

spin_lock_irqsave(&winbond_lock, flags);

827

outb(reg, port + 0x01);

833

outb(reg, port + 0x01);

828

val = inb(port + 0x02);

834

val = inb(port + 0x02);

829

spin_unlock_irqrestore(&winbond_lock, flags);

835

spin_unlock_irqrestore(&winbond_lock, flags);

830

836

831

return val;

837

return val;

832

}

838

}

833

839

834

static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev)

840

static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev)

835

{

841

{

836

struct ata_timing t;

842

struct ata_timing t;

837

struct legacy_data *ld_winbond = ap->host->private_data;

843

struct legacy_data *ld_winbond = ap->host->private_data;

838

int active, recovery;

844

int active, recovery;

839

u8 reg;

845

u8 reg;

840

int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2);

846

int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2);

841

847

842

reg = winbond_readcfg(ld_winbond->timing, 0x81);

848

reg = winbond_readcfg(ld_winbond->timing, 0x81);

843

849

844

/* Get the timing data in cycles */

850

/* Get the timing data in cycles */

845

if (reg & 0x40) /* Fast VLB bus, assume 50MHz */

851

if (reg & 0x40) /* Fast VLB bus, assume 50MHz */

846

ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);

852

ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);

847

else

853

else

848

ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);

854

ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);

849

855

850

active = (clamp_val(t.active, 3, 17) - 1) & 0x0F;

856

active = (clamp_val(t.active, 3, 17) - 1) & 0x0F;

851

recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F;

857

recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F;

852

timing = (active << 4) | recovery;

858

timing = (active << 4) | recovery;

853

winbond_writecfg(ld_winbond->timing, timing, reg);

859

winbond_writecfg(ld_winbond->timing, timing, reg);

854

860

855

/* Load the setup timing */

861

/* Load the setup timing */

856

862

857

reg = 0x35;

863

reg = 0x35;

858

if (adev->class != ATA_DEV_ATA)

864

if (adev->class != ATA_DEV_ATA)

859

reg |= 0x08; /* FIFO off */

865

reg |= 0x08; /* FIFO off */

860

if (!ata_pio_need_iordy(adev))

866

if (!ata_pio_need_iordy(adev))

861

reg |= 0x02; /* IORDY off */

867

reg |= 0x02; /* IORDY off */

862

reg |= (clamp_val(t.setup, 0, 3) << 6);

868

reg |= (clamp_val(t.setup, 0, 3) << 6);

863

winbond_writecfg(ld_winbond->timing, timing + 1, reg);

869

winbond_writecfg(ld_winbond->timing, timing + 1, reg);

864

}

870

}

865

871

866

static int winbond_port(struct platform_device *dev,

872

static int winbond_port(struct platform_device *dev,

867

struct legacy_probe *lp, struct legacy_data *ld)

873

struct legacy_probe *lp, struct legacy_data *ld)

868

{

874

{

869

if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL)

875

if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL)

870

return -EBUSY;

876

return -EBUSY;

871

ld->timing = lp->private;

877

ld->timing = lp->private;

872

return 0;

878

return 0;

873

}

879

}

874

880

875

static struct ata_port_operations winbond_port_ops = {

881

static struct ata_port_operations winbond_port_ops = {

876

.inherits = &legacy_base_port_ops,

882

.inherits = &legacy_base_port_ops,

877

.set_piomode = winbond_set_piomode,

883

.set_piomode = winbond_set_piomode,

878

.sff_data_xfer = vlb32_data_xfer,

884

.sff_data_xfer = vlb32_data_xfer,

879

};

885

};

880

886

881

static struct legacy_controller controllers[] = {

887

static struct legacy_controller controllers[] = {

882

{"BIOS", &legacy_port_ops, 0x1F,

888

{"BIOS", &legacy_port_ops, 0x1F,

883

ATA_FLAG_NO_IORDY, 0, NULL },

889

ATA_FLAG_NO_IORDY, 0, NULL },

884

{"Snooping", &simple_port_ops, 0x1F,

890

{"Snooping", &simple_port_ops, 0x1F,

885

0, 0, NULL },

891

0, 0, NULL },

886

{"PDC20230", &pdc20230_port_ops, 0x7,

892

{"PDC20230", &pdc20230_port_ops, 0x7,

887

ATA_FLAG_NO_IORDY,

893

ATA_FLAG_NO_IORDY,

888

ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, NULL },

894

ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, NULL },

889

{"HT6560A", &ht6560a_port_ops, 0x07,

895

{"HT6560A", &ht6560a_port_ops, 0x07,

890

ATA_FLAG_NO_IORDY, 0, NULL },

896

ATA_FLAG_NO_IORDY, 0, NULL },

891

{"HT6560B", &ht6560b_port_ops, 0x1F,

897

{"HT6560B", &ht6560b_port_ops, 0x1F,

892

ATA_FLAG_NO_IORDY, 0, NULL },

898

ATA_FLAG_NO_IORDY, 0, NULL },

893

{"OPTI82C611A", &opti82c611a_port_ops, 0x0F,

899

{"OPTI82C611A", &opti82c611a_port_ops, 0x0F,

894

0, 0, NULL },

900

0, 0, NULL },

895

{"OPTI82C46X", &opti82c46x_port_ops, 0x0F,

901

{"OPTI82C46X", &opti82c46x_port_ops, 0x0F,

896

0, 0, NULL },

902

0, 0, NULL },

897

{"QDI6500", &qdi6500_port_ops, 0x07,

903

{"QDI6500", &qdi6500_port_ops, 0x07,

898

ATA_FLAG_NO_IORDY,

904

ATA_FLAG_NO_IORDY,

899

ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },

905

ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },

900

{"QDI6580", &qdi6580_port_ops, 0x1F,

906

{"QDI6580", &qdi6580_port_ops, 0x1F,

901

0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },

907

0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },

902

{"QDI6580DP", &qdi6580dp_port_ops, 0x1F,

908

{"QDI6580DP", &qdi6580dp_port_ops, 0x1F,

903

0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },

909

0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },

904

{"W83759A", &winbond_port_ops, 0x1F,

910

{"W83759A", &winbond_port_ops, 0x1F,

905

0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE,

911

0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE,

906

winbond_port }

912

winbond_port }

907

};

913

};

908

914

909

/**

915

/**

910

* probe_chip_type - Discover controller

916

* probe_chip_type - Discover controller

911

* @probe: Probe entry to check

917

* @probe: Probe entry to check

912

*

918

*

913

* Probe an ATA port and identify the type of controller. We don't

919

* Probe an ATA port and identify the type of controller. We don't

914

* check if the controller appears to be driveless at this point.

920

* check if the controller appears to be driveless at this point.

915

*/

921

*/

916

922

917

static __init int probe_chip_type(struct legacy_probe *probe)

923

static __init int probe_chip_type(struct legacy_probe *probe)

918

{

924

{

919

int mask = 1 << probe->slot;

925

int mask = 1 << probe->slot;

920

926

921

if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) {

927

if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) {

922

u8 reg = winbond_readcfg(winbond, 0x81);

928

u8 reg = winbond_readcfg(winbond, 0x81);

923

reg |= 0x80; /* jumpered mode off */

929

reg |= 0x80; /* jumpered mode off */

924

winbond_writecfg(winbond, 0x81, reg);

930

winbond_writecfg(winbond, 0x81, reg);

925

reg = winbond_readcfg(winbond, 0x83);

931

reg = winbond_readcfg(winbond, 0x83);

926

reg |= 0xF0; /* local control */

932

reg |= 0xF0; /* local control */

927

winbond_writecfg(winbond, 0x83, reg);

933

winbond_writecfg(winbond, 0x83, reg);

928

reg = winbond_readcfg(winbond, 0x85);

934

reg = winbond_readcfg(winbond, 0x85);

929

reg |= 0xF0; /* programmable timing */

935

reg |= 0xF0; /* programmable timing */

930

winbond_writecfg(winbond, 0x85, reg);

936

winbond_writecfg(winbond, 0x85, reg);

931

937

932

reg = winbond_readcfg(winbond, 0x81);

938

reg = winbond_readcfg(winbond, 0x81);

933

939

934

if (reg & mask)

940

if (reg & mask)

935

return W83759A;

941

return W83759A;

936

}

942

}

937

if (probe->port == 0x1F0) {

943

if (probe->port == 0x1F0) {

938

unsigned long flags;

944

unsigned long flags;

939

local_irq_save(flags);

945

local_irq_save(flags);

940

/* Probes */

946

/* Probes */

941

outb(inb(0x1F2) | 0x80, 0x1F2);

947

outb(inb(0x1F2) | 0x80, 0x1F2);

942

inb(0x1F5);

948

inb(0x1F5);

943

inb(0x1F2);

949

inb(0x1F2);

944

inb(0x3F6);

950

inb(0x3F6);

945

inb(0x3F6);

951

inb(0x3F6);

946

inb(0x1F2);

952

inb(0x1F2);

947

inb(0x1F2);

953

inb(0x1F2);

948

954

949

if ((inb(0x1F2) & 0x80) == 0) {

955

if ((inb(0x1F2) & 0x80) == 0) {

950

/* PDC20230c or 20630 ? */

956

/* PDC20230c or 20630 ? */

951

printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller"

957

printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller"

952

" detected.\n");

958

" detected.\n");

953

udelay(100);

959

udelay(100);

954

inb(0x1F5);

960

inb(0x1F5);

955

local_irq_restore(flags);

961

local_irq_restore(flags);

956

return PDC20230;

962

return PDC20230;

957

} else {

963

} else {

958

outb(0x55, 0x1F2);

964

outb(0x55, 0x1F2);

959

inb(0x1F2);

965

inb(0x1F2);

960

inb(0x1F2);

966

inb(0x1F2);

961

if (inb(0x1F2) == 0x00)

967

if (inb(0x1F2) == 0x00)

962

printk(KERN_INFO "PDC20230-B VLB ATA "

968

printk(KERN_INFO "PDC20230-B VLB ATA "

963

"controller detected.\n");

969

"controller detected.\n");

964

local_irq_restore(flags);

970

local_irq_restore(flags);

965

return BIOS;

971

return BIOS;

966

}

972

}

967

local_irq_restore(flags);

973

local_irq_restore(flags);

968

}

974

}

969

975

970

if (ht6560a & mask)

976

if (ht6560a & mask)

971

return HT6560A;

977

return HT6560A;

972

if (ht6560b & mask)

978

if (ht6560b & mask)

973

return HT6560B;

979

return HT6560B;

974

if (opti82c611a & mask)

980

if (opti82c611a & mask)

975

return OPTI611A;

981

return OPTI611A;

976

if (opti82c46x & mask)

982

if (opti82c46x & mask)

977

return OPTI46X;

983

return OPTI46X;

978

if (autospeed & mask)

984

if (autospeed & mask)

979

return SNOOP;

985

return SNOOP;

980

return BIOS;

986

return BIOS;

981

}

987

}

982

988

983

989

984

/**

990

/**

985

* legacy_init_one - attach a legacy interface

991

* legacy_init_one - attach a legacy interface

986

* @pl: probe record

992

* @pl: probe record

987

*

993

*

988

* Register an ISA bus IDE interface. Such interfaces are PIO and we

994

* Register an ISA bus IDE interface. Such interfaces are PIO and we

989

* assume do not support IRQ sharing.

995

* assume do not support IRQ sharing.

990

*/

996

*/

991

997

992

static __init int legacy_init_one(struct legacy_probe *probe)

998

static __init int legacy_init_one(struct legacy_probe *probe)

993

{

999

{

994

struct legacy_controller *controller = &controllers[probe->type];

1000

struct legacy_controller *controller = &controllers[probe->type];

995

int pio_modes = controller->pio_mask;

1001

int pio_modes = controller->pio_mask;

996

unsigned long io = probe->port;

1002

unsigned long io = probe->port;

997

u32 mask = (1 << probe->slot);

1003

u32 mask = (1 << probe->slot);

998

struct ata_port_operations *ops = controller->ops;

1004

struct ata_port_operations *ops = controller->ops;

999

struct legacy_data *ld = &legacy_data[probe->slot];

1005

struct legacy_data *ld = &legacy_data[probe->slot];

1000

struct ata_host *host = NULL;

1006

struct ata_host *host = NULL;

1001

struct ata_port *ap;

1007

struct ata_port *ap;

1002

struct platform_device *pdev;

1008

struct platform_device *pdev;

1003

struct ata_device *dev;

1009

struct ata_device *dev;

1004

void __iomem *io_addr, *ctrl_addr;

1010

void __iomem *io_addr, *ctrl_addr;

1005

u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY;

1011

u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY;

1006

int ret;

1012

int ret;

1007

1013

1008

iordy |= controller->flags;

1014

iordy |= controller->flags;

1009

1015

1010

pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0);

1016

pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0);

1011

if (IS_ERR(pdev))

1017

if (IS_ERR(pdev))

1012

return PTR_ERR(pdev);

1018

return PTR_ERR(pdev);

1013

1019

1014

ret = -EBUSY;

1020

ret = -EBUSY;

1015

if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL ||

1021

if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL ||

1016

devm_request_region(&pdev->dev, io + 0x0206, 1,

1022

devm_request_region(&pdev->dev, io + 0x0206, 1,

1017

"pata_legacy") == NULL)

1023

"pata_legacy") == NULL)

1018

goto fail;

1024

goto fail;

1019

1025

1020

ret = -ENOMEM;

1026

ret = -ENOMEM;

1021

io_addr = devm_ioport_map(&pdev->dev, io, 8);

1027

io_addr = devm_ioport_map(&pdev->dev, io, 8);

1022

ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1);

1028

ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1);

1023

if (!io_addr || !ctrl_addr)

1029

if (!io_addr || !ctrl_addr)

1024

goto fail;

1030

goto fail;

1025

if (controller->setup)

1031

if (controller->setup)

1026

if (controller->setup(pdev, probe, ld) < 0)

1032

if (controller->setup(pdev, probe, ld) < 0)

1027

goto fail;

1033

goto fail;

1028

host = ata_host_alloc(&pdev->dev, 1);

1034

host = ata_host_alloc(&pdev->dev, 1);

1029

if (!host)

1035

if (!host)

1030

goto fail;

1036

goto fail;

1031

ap = host->ports[0];

1037

ap = host->ports[0];

1032

1038

1033

ap->ops = ops;

1039

ap->ops = ops;

1034

ap->pio_mask = pio_modes;

1040

ap->pio_mask = pio_modes;

1035

ap->flags |= ATA_FLAG_SLAVE_POSS | iordy;

1041

ap->flags |= ATA_FLAG_SLAVE_POSS | iordy;

1036

ap->pflags |= controller->pflags;

1042

ap->pflags |= controller->pflags;

1037

ap->ioaddr.cmd_addr = io_addr;

1043

ap->ioaddr.cmd_addr = io_addr;

1038

ap->ioaddr.altstatus_addr = ctrl_addr;

1044

ap->ioaddr.altstatus_addr = ctrl_addr;

1039

ap->ioaddr.ctl_addr = ctrl_addr;

1045

ap->ioaddr.ctl_addr = ctrl_addr;

1040

ata_sff_std_ports(&ap->ioaddr);

1046

ata_sff_std_ports(&ap->ioaddr);

1041

ap->host->private_data = ld;

1047

ap->host->private_data = ld;

1042

1048

1043

ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206);

1049

ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206);

1044

1050

1045

ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0,

1051

ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0,

1046

&legacy_sht);

1052

&legacy_sht);

1047

if (ret)

1053

if (ret)

1048

goto fail;

1054

goto fail;

1049

async_synchronize_full();

1055

async_synchronize_full();

1050

ld->platform_dev = pdev;

1056

ld->platform_dev = pdev;

1051

1057

1052

/* Nothing found means we drop the port as its probably not there */

1058

/* Nothing found means we drop the port as its probably not there */

1053

1059

1054

ret = -ENODEV;

1060

ret = -ENODEV;

1055

ata_for_each_dev(dev, &ap->link, ALL) {

1061

ata_for_each_dev(dev, &ap->link, ALL) {

1056

if (!ata_dev_absent(dev)) {

1062

if (!ata_dev_absent(dev)) {

1057

legacy_host[probe->slot] = host;

1063

legacy_host[probe->slot] = host;

1058

ld->platform_dev = pdev;

1064

ld->platform_dev = pdev;

1059

return 0;

1065

return 0;

1060

}

1066

}

1061

}

1067

}

1062

ata_host_detach(host);

1068

ata_host_detach(host);

1063

fail:

1069

fail:

1064

platform_device_unregister(pdev);

1070

platform_device_unregister(pdev);

1065

return ret;

1071

return ret;

1066

}

1072

}

1067

1073

1068

/**

1074

/**

1069

* legacy_check_special_cases - ATA special cases

1075

* legacy_check_special_cases - ATA special cases

1070

* @p: PCI device to check

1076

* @p: PCI device to check

1071

* @master: set this if we find an ATA master

1077

* @master: set this if we find an ATA master

1072

* @master: set this if we find an ATA secondary

1078

* @master: set this if we find an ATA secondary

1073

*

1079

*

1074

* A small number of vendors implemented early PCI ATA interfaces

1080

* A small number of vendors implemented early PCI ATA interfaces

1075

* on bridge logic without the ATA interface being PCI visible.

1081

* on bridge logic without the ATA interface being PCI visible.

1076

* Where we have a matching PCI driver we must skip the relevant

1082

* Where we have a matching PCI driver we must skip the relevant

1077

* device here. If we don't know about it then the legacy driver

1083

* device here. If we don't know about it then the legacy driver

1078

* is the right driver anyway.

1084

* is the right driver anyway.

1079

*/

1085

*/

1080

1086

1081

static void __init legacy_check_special_cases(struct pci_dev *p, int *primary,

1087

static void __init legacy_check_special_cases(struct pci_dev *p, int *primary,

1082

int *secondary)

1088

int *secondary)

1083

{

1089

{

1084

/* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */

1090

/* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */

1085

if (p->vendor == 0x1078 && p->device == 0x0000) {

1091

if (p->vendor == 0x1078 && p->device == 0x0000) {

1086

*primary = *secondary = 1;

1092

*primary = *secondary = 1;

1087

return;

1093

return;

1088

}

1094

}

1089

/* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */

1095

/* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */

1090

if (p->vendor == 0x1078 && p->device == 0x0002) {

1096

if (p->vendor == 0x1078 && p->device == 0x0002) {

1091

*primary = *secondary = 1;

1097

*primary = *secondary = 1;

1092

return;

1098

return;

1093

}

1099

}

1094

/* Intel MPIIX - PIO ATA on non PCI side of bridge */

1100

/* Intel MPIIX - PIO ATA on non PCI side of bridge */

1095

if (p->vendor == 0x8086 && p->device == 0x1234) {

1101

if (p->vendor == 0x8086 && p->device == 0x1234) {

1096

u16 r;

1102

u16 r;

1097

pci_read_config_word(p, 0x6C, &r);

1103

pci_read_config_word(p, 0x6C, &r);

1098

if (r & 0x8000) {

1104

if (r & 0x8000) {

1099

/* ATA port enabled */

1105

/* ATA port enabled */

1100

if (r & 0x4000)

1106

if (r & 0x4000)

1101

*secondary = 1;

1107

*secondary = 1;

1102

else

1108

else

1103

*primary = 1;

1109

*primary = 1;

1104

}

1110

}

1105

return;

1111

return;

1106

}

1112

}

1107

}

1113

}

1108

1114

1109

static __init void probe_opti_vlb(void)

1115

static __init void probe_opti_vlb(void)

1110

{

1116

{

1111

/* If an OPTI 82C46X is present find out where the channels are */

1117

/* If an OPTI 82C46X is present find out where the channels are */

1112

static const char *optis[4] = {

1118

static const char *optis[4] = {

1113

"3/463MV", "5MV",

1119

"3/463MV", "5MV",

1114

"5MVA", "5MVB"

1120

"5MVA", "5MVB"

1115

};

1121

};

1116

u8 chans = 1;

1122

u8 chans = 1;

1117

u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;

1123

u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;

1118

1124

1119

opti82c46x = 3; /* Assume master and slave first */

1125

opti82c46x = 3; /* Assume master and slave first */

1120

printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n",

1126

printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n",

1121

optis[ctrl]);

1127

optis[ctrl]);

1122

if (ctrl == 3)

1128

if (ctrl == 3)

1123

chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1;

1129

chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1;

1124

ctrl = opti_syscfg(0xAC);

1130

ctrl = opti_syscfg(0xAC);

1125

/* Check enabled and this port is the 465MV port. On the

1131

/* Check enabled and this port is the 465MV port. On the

1126

MVB we may have two channels */

1132

MVB we may have two channels */

1127

if (ctrl & 8) {

1133

if (ctrl & 8) {

1128

if (chans == 2) {

1134

if (chans == 2) {

1129

legacy_probe_add(0x1F0, 14, OPTI46X, 0);

1135

legacy_probe_add(0x1F0, 14, OPTI46X, 0);

1130

legacy_probe_add(0x170, 15, OPTI46X, 0);

1136

legacy_probe_add(0x170, 15, OPTI46X, 0);

1131

}

1137

}

1132

if (ctrl & 4)

1138

if (ctrl & 4)

1133

legacy_probe_add(0x170, 15, OPTI46X, 0);

1139

legacy_probe_add(0x170, 15, OPTI46X, 0);

1134

else

1140

else

1135

legacy_probe_add(0x1F0, 14, OPTI46X, 0);

1141

legacy_probe_add(0x1F0, 14, OPTI46X, 0);

1136

} else

1142

} else

1137

legacy_probe_add(0x1F0, 14, OPTI46X, 0);

1143

legacy_probe_add(0x1F0, 14, OPTI46X, 0);

1138

}

1144

}

1139

1145

1140

static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port)

1146

static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port)

1141

{

1147

{

1142

static const unsigned long ide_port[2] = { 0x170, 0x1F0 };

1148

static const unsigned long ide_port[2] = { 0x170, 0x1F0 };

1143

/* Check card type */

1149

/* Check card type */

1144

if ((r & 0xF0) == 0xC0) {

1150

if ((r & 0xF0) == 0xC0) {

1145

/* QD6500: single channel */

1151

/* QD6500: single channel */

1146

if (r & 8)

1152

if (r & 8)

1147

/* Disabled ? */

1153

/* Disabled ? */

1148

return;

1154

return;

1149

legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),

1155

legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),

1150

QDI6500, port);

1156

QDI6500, port);

1151

}

1157

}

1152

if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) {

1158

if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) {

1153

/* QD6580: dual channel */

1159

/* QD6580: dual channel */

1154

if (!request_region(port + 2 , 2, "pata_qdi")) {

1160

if (!request_region(port + 2 , 2, "pata_qdi")) {

1155

release_region(port, 2);

1161

release_region(port, 2);

1156

return;

1162

return;

1157

}

1163

}

1158

res = inb(port + 3);

1164

res = inb(port + 3);

1159

/* Single channel mode ? */

1165

/* Single channel mode ? */

1160

if (res & 1)

1166

if (res & 1)

1161

legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),

1167

legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),

1162

QDI6580, port);

1168

QDI6580, port);

1163

else { /* Dual channel mode */

1169

else { /* Dual channel mode */

1164

legacy_probe_add(0x1F0, 14, QDI6580DP, port);

1170

legacy_probe_add(0x1F0, 14, QDI6580DP, port);

1165

/* port + 0x02, r & 0x04 */

1171

/* port + 0x02, r & 0x04 */

1166

legacy_probe_add(0x170, 15, QDI6580DP, port + 2);

1172

legacy_probe_add(0x170, 15, QDI6580DP, port + 2);

1167

}

1173

}

1168

release_region(port + 2, 2);

1174

release_region(port + 2, 2);

1169

}

1175

}

1170

}

1176

}

1171

1177

1172

static __init void probe_qdi_vlb(void)

1178

static __init void probe_qdi_vlb(void)

1173

{

1179

{

1174

unsigned long flags;

1180

unsigned long flags;

1175

static const unsigned long qd_port[2] = { 0x30, 0xB0 };

1181

static const unsigned long qd_port[2] = { 0x30, 0xB0 };

1176

int i;

1182

int i;

1177

1183

1178

/*

1184

/*

1179

* Check each possible QD65xx base address

1185

* Check each possible QD65xx base address

1180

*/

1186

*/

1181

1187

1182

for (i = 0; i < 2; i++) {

1188

for (i = 0; i < 2; i++) {

1183

unsigned long port = qd_port[i];

1189

unsigned long port = qd_port[i];

1184

u8 r, res;

1190

u8 r, res;

1185

1191

1186

1192

1187

if (request_region(port, 2, "pata_qdi")) {

1193

if (request_region(port, 2, "pata_qdi")) {

1188

/* Check for a card */

1194

/* Check for a card */

1189

local_irq_save(flags);

1195

local_irq_save(flags);

1190

/* I have no h/w that needs this delay but it

1196

/* I have no h/w that needs this delay but it

1191

is present in the historic code */

1197

is present in the historic code */

1192

r = inb(port);

1198

r = inb(port);

1193

udelay(1);

1199

udelay(1);

1194

outb(0x19, port);

1200

outb(0x19, port);

1195

udelay(1);

1201

udelay(1);

1196

res = inb(port);

1202

res = inb(port);

1197

udelay(1);

1203

udelay(1);

1198

outb(r, port);

1204

outb(r, port);

1199

udelay(1);

1205

udelay(1);

1200

local_irq_restore(flags);

1206

local_irq_restore(flags);

1201

1207

1202

/* Fail */

1208

/* Fail */

1203

if (res == 0x19) {

1209

if (res == 0x19) {

1204

release_region(port, 2);

1210

release_region(port, 2);

1205

continue;

1211

continue;

1206

}

1212

}

1207

/* Passes the presence test */

1213

/* Passes the presence test */

1208

r = inb(port + 1);

1214

r = inb(port + 1);

1209

udelay(1);

1215

udelay(1);

1210

/* Check port agrees with port set */

1216

/* Check port agrees with port set */

1211

if ((r & 2) >> 1 == i)

1217

if ((r & 2) >> 1 == i)

1212

qdi65_identify_port(r, res, port);

1218

qdi65_identify_port(r, res, port);

1213

release_region(port, 2);

1219

release_region(port, 2);

1214

}

1220

}

1215

}

1221

}

1216

}

1222

}

1217

1223

1218

/**

1224

/**

1219

* legacy_init - attach legacy interfaces

1225

* legacy_init - attach legacy interfaces

1220

*

1226

*

1221

* Attach legacy IDE interfaces by scanning the usual IRQ/port suspects.

1227

* Attach legacy IDE interfaces by scanning the usual IRQ/port suspects.

1222

* Right now we do not scan the ide0 and ide1 address but should do so

1228

* Right now we do not scan the ide0 and ide1 address but should do so

1223

* for non PCI systems or systems with no PCI IDE legacy mode devices.

1229

* for non PCI systems or systems with no PCI IDE legacy mode devices.

1224

* If you fix that note there are special cases to consider like VLB

1230

* If you fix that note there are special cases to consider like VLB

1225

* drivers and CS5510/20.

1231

* drivers and CS5510/20.

1226

*/

1232

*/

1227

1233

1228

static __init int legacy_init(void)

1234

static __init int legacy_init(void)

1229

{

1235

{

1230

int i;

1236

int i;

1231

int ct = 0;

1237

int ct = 0;

1232

int primary = 0;

1238

int primary = 0;

1233

int secondary = 0;

1239

int secondary = 0;

1234

int pci_present = 0;

1240

int pci_present = 0;

1235

struct legacy_probe *pl = &probe_list[0];

1241

struct legacy_probe *pl = &probe_list[0];

1236

int slot = 0;

1242

int slot = 0;

1237

1243

1238

struct pci_dev *p = NULL;

1244

struct pci_dev *p = NULL;

1239

1245

1240

for_each_pci_dev(p) {

1246

for_each_pci_dev(p) {

1241

int r;

1247

int r;

1242

/* Check for any overlap of the system ATA mappings. Native

1248

/* Check for any overlap of the system ATA mappings. Native

1243

mode controllers stuck on these addresses or some devices

1249

mode controllers stuck on these addresses or some devices

1244

in 'raid' mode won't be found by the storage class test */

1250

in 'raid' mode won't be found by the storage class test */

1245

for (r = 0; r < 6; r++) {

1251

for (r = 0; r < 6; r++) {

1246

if (pci_resource_start(p, r) == 0x1f0)

1252

if (pci_resource_start(p, r) == 0x1f0)

1247

primary = 1;

1253

primary = 1;

1248

if (pci_resource_start(p, r) == 0x170)

1254

if (pci_resource_start(p, r) == 0x170)

1249

secondary = 1;

1255

secondary = 1;

1250

}

1256

}

1251

/* Check for special cases */

1257

/* Check for special cases */

1252

legacy_check_special_cases(p, &primary, &secondary);

1258

legacy_check_special_cases(p, &primary, &secondary);

1253

1259

1254

/* If PCI bus is present then don't probe for tertiary

1260

/* If PCI bus is present then don't probe for tertiary

1255

legacy ports */

1261

legacy ports */

1256

pci_present = 1;

1262

pci_present = 1;

1257

}

1263

}

1258

1264

1259

if (winbond == 1)

1265

if (winbond == 1)

1260

winbond = 0x130; /* Default port, alt is 1B0 */

1266

winbond = 0x130; /* Default port, alt is 1B0 */

1261

1267

1262

if (primary == 0 || all)

1268

if (primary == 0 || all)

1263

legacy_probe_add(0x1F0, 14, UNKNOWN, 0);

1269

legacy_probe_add(0x1F0, 14, UNKNOWN, 0);

1264

if (secondary == 0 || all)

1270

if (secondary == 0 || all)

1265

legacy_probe_add(0x170, 15, UNKNOWN, 0);

1271

legacy_probe_add(0x170, 15, UNKNOWN, 0);

1266

1272

1267

if (probe_all || !pci_present) {

1273

if (probe_all || !pci_present) {

1268

/* ISA/VLB extra ports */

1274

/* ISA/VLB extra ports */

1269

legacy_probe_add(0x1E8, 11, UNKNOWN, 0);

1275

legacy_probe_add(0x1E8, 11, UNKNOWN, 0);

1270

legacy_probe_add(0x168, 10, UNKNOWN, 0);

1276

legacy_probe_add(0x168, 10, UNKNOWN, 0);

1271

legacy_probe_add(0x1E0, 8, UNKNOWN, 0);

1277

legacy_probe_add(0x1E0, 8, UNKNOWN, 0);

1272

legacy_probe_add(0x160, 12, UNKNOWN, 0);

1278

legacy_probe_add(0x160, 12, UNKNOWN, 0);

1273

}

1279

}

1274

1280

1275

if (opti82c46x)

1281

if (opti82c46x)

1276

probe_opti_vlb();

1282

probe_opti_vlb();

1277

if (qdi)

1283

if (qdi)

1278

probe_qdi_vlb();

1284

probe_qdi_vlb();

1279

1285

1280

for (i = 0; i < NR_HOST; i++, pl++) {

1286

for (i = 0; i < NR_HOST; i++, pl++) {

1281

if (pl->port == 0)

1287

if (pl->port == 0)

1282

continue;

1288

continue;

1283

if (pl->type == UNKNOWN)

1289

if (pl->type == UNKNOWN)

1284

pl->type = probe_chip_type(pl);

1290

pl->type = probe_chip_type(pl);

1285

pl->slot = slot++;

1291

pl->slot = slot++;

1286

if (legacy_init_one(pl) == 0)

1292

if (legacy_init_one(pl) == 0)

1287

ct++;

1293

ct++;

1288

}

1294

}

1289

if (ct != 0)

1295

if (ct != 0)

1290

return 0;

1296

return 0;

1291

return -ENODEV;

1297

return -ENODEV;

1292

}

1298

}

1293

1299

1294

static __exit void legacy_exit(void)

1300

static __exit void legacy_exit(void)

1295

{

1301

{

1296

int i;

1302

int i;

1297

1303

1298

for (i = 0; i < nr_legacy_host; i++) {

1304

for (i = 0; i < nr_legacy_host; i++) {

1299

struct legacy_data *ld = &legacy_data[i];

1305

struct legacy_data *ld = &legacy_data[i];

1300

ata_host_detach(legacy_host[i]);

1306

ata_host_detach(legacy_host[i]);

1301

platform_device_unregister(ld->platform_dev);

1307

platform_device_unregister(ld->platform_dev);

1302

}

1308

}

1303

}

1309

}

1304

1310

1305

MODULE_AUTHOR("Alan Cox");

1311

MODULE_AUTHOR("Alan Cox");

1306

MODULE_DESCRIPTION("low-level driver for legacy ATA");

1312

MODULE_DESCRIPTION("low-level driver for legacy ATA");

1307

MODULE_LICENSE("GPL");

1313

MODULE_LICENSE("GPL");

1308

MODULE_VERSION(DRV_VERSION);

1314

MODULE_VERSION(DRV_VERSION);

1315

MODULE_ALIAS("pata_qdi");

1309

MODULE_ALIAS("pata_winbond");

1316

MODULE_ALIAS("pata_winbond");

1310

1317

1311

module_param(probe_all, int, 0);

1318

module_param(probe_all, int, 0);

1312

module_param(autospeed, int, 0);

1319

module_param(autospeed, int, 0);

1313

module_param(ht6560a, int, 0);

1320

module_param(ht6560a, int, 0);

1314

module_param(ht6560b, int, 0);

1321

module_param(ht6560b, int, 0);

1315

module_param(opti82c611a, int, 0);

1322

module_param(opti82c611a, int, 0);

1316

module_param(opti82c46x, int, 0);

1323

module_param(opti82c46x, int, 0);

1317

module_param(qdi, int, 0);

1324

module_param(qdi, int, 0);

1318

module_param(winbond, int, 0);

1325

module_param(winbond, int, 0);

1319

module_param(pio_mask, int, 0);

1326

module_param(pio_mask, int, 0);

1320

module_param(iordy_mask, int, 0);

1327

module_param(iordy_mask, int, 0);

1321

1328

1322

module_init(legacy_init);

1329

module_init(legacy_init);

1323

module_exit(legacy_exit);

1330

module_exit(legacy_exit);

GITLAB

libata: remove no longer needed pata_qdi driver

 #
 # SATA/PATA driver configuration
 #
 config HAVE_PATA_PLATFORM
 	bool
 	help
 	  This is an internal configuration node for any machine that
 	  uses pata-platform driver to enable the relevant driver in the
 	  configuration structure without having to submit endless patches
 	  to update the PATA_PLATFORM entry.
 menuconfig ATA
 	tristate "Serial ATA and Parallel ATA drivers"
 	depends on HAS_IOMEM
 	depends on BLOCK
 	depends on !(M32R || M68K) || BROKEN
 	select SCSI
 	---help---
 	  If you want to use a ATA hard disk, ATA tape drive, ATA CD-ROM or
 	  any other ATA device under Linux, say Y and make sure that you know
 	  the name of your ATA host adapter (the card inside your computer
 	  that "speaks" the ATA protocol, also called ATA controller),
 	  because you will be asked for it.
 	  NOTE: ATA enables basic SCSI support; *however*,
 	  'SCSI disk support', 'SCSI tape support', or
 	  'SCSI CDROM support' may also be needed,
 	  depending on your hardware configuration.
 if ATA
 config ATA_NONSTANDARD
        bool
        default n
 config ATA_VERBOSE_ERROR
 	bool "Verbose ATA error reporting"
 	default y
 	help
 	  This option adds parsing of ATA command descriptions and error bits
 	  in libata kernel output, making it easier to interpret.
 	  This option will enlarge the kernel by approx. 6KB. Disable it only
 	  if kernel size is more important than ease of debugging.
 	  If unsure, say Y.
 config ATA_ACPI
 	bool "ATA ACPI Support"
 	depends on ACPI && PCI
 	default y
 	help
 	  This option adds support for ATA-related ACPI objects.
 	  These ACPI objects add the ability to retrieve taskfiles
 	  from the ACPI BIOS and write them to the disk controller.
 	  These objects may be related to performance, security,
 	  power management, or other areas.
 	  You can disable this at kernel boot time by using the
 	  option libata.noacpi=1
 config SATA_PMP
 	bool "SATA Port Multiplier support"
 	default y
 	help
 	  This option adds support for SATA Port Multipliers
 	  (the SATA version of an ethernet hub, or SAS expander).
 comment "Controllers with non-SFF native interface"
 config SATA_AHCI
 	tristate "AHCI SATA support"
 	depends on PCI
 	help
 	  This option enables support for AHCI Serial ATA.
 	  If unsure, say N.
 config SATA_AHCI_PLATFORM
 	tristate "Platform AHCI SATA support"
 	help
 	  This option enables support for Platform AHCI Serial ATA
 	  controllers.
 	  If unsure, say N.
 config SATA_FSL
 	tristate "Freescale 3.0Gbps SATA support"
 	depends on FSL_SOC
 	help
 	  This option enables support for Freescale 3.0Gbps SATA controller.
 	  It can be found on MPC837x and MPC8315.
 	  If unsure, say N.
 config SATA_INIC162X
 	tristate "Initio 162x SATA support"
 	depends on PCI
 	help
 	  This option enables support for Initio 162x Serial ATA.
 config SATA_ACARD_AHCI
 	tristate "ACard AHCI variant (ATP 8620)"
 	depends on PCI
 	help
 	  This option enables support for Acard.
 	  If unsure, say N.
 config SATA_SIL24
 	tristate "Silicon Image 3124/3132 SATA support"
 	depends on PCI
 	help
 	  This option enables support for Silicon Image 3124/3132 Serial ATA.
 	  If unsure, say N.
 config ATA_SFF
 	bool "ATA SFF support"
 	default y
 	help
 	  This option adds support for ATA controllers with SFF
 	  compliant or similar programming interface.
 	  SFF is the legacy IDE interface that has been around since
 	  the dawn of time.  Almost all PATA controllers have an
 	  SFF interface.  Many SATA controllers have an SFF interface
 	  when configured into a legacy compatibility mode.
 	  For users with exclusively modern controllers like AHCI,
 	  Silicon Image 3124, or Marvell 6440, you may choose to
 	  disable this unneeded SFF support.
 	  If unsure, say Y.
 if ATA_SFF
 comment "SFF controllers with custom DMA interface"
 config PDC_ADMA
 	tristate "Pacific Digital ADMA support"
 	depends on PCI
 	help
 	  This option enables support for Pacific Digital ADMA controllers
 	  If unsure, say N.
 config PATA_OCTEON_CF
 	tristate "OCTEON Boot Bus Compact Flash support"
 	depends on CPU_CAVIUM_OCTEON
 	help
 	  This option enables a polled compact flash driver for use with
 	  compact flash cards attached to the OCTEON boot bus.
 	  If unsure, say N.
 config SATA_QSTOR
 	tristate "Pacific Digital SATA QStor support"
 	depends on PCI
 	help
 	  This option enables support for Pacific Digital Serial ATA QStor.
 	  If unsure, say N.
 config SATA_SX4
 	tristate "Promise SATA SX4 support (Experimental)"
 	depends on PCI && EXPERIMENTAL
 	help
 	  This option enables support for Promise Serial ATA SX4.
 	  If unsure, say N.
 config ATA_BMDMA
 	bool "ATA BMDMA support"
 	default y
 	help
 	  This option adds support for SFF ATA controllers with BMDMA
 	  capability.  BMDMA stands for bus-master DMA and is the
 	  de facto DMA interface for SFF controllers.
 	  If unsure, say Y.
 if ATA_BMDMA
 comment "SATA SFF controllers with BMDMA"
 config ATA_PIIX
 	tristate "Intel ESB, ICH, PIIX3, PIIX4 PATA/SATA support"
 	depends on PCI
 	help
 	  This option enables support for ICH5/6/7/8 Serial ATA
 	  and support for PATA on the Intel ESB/ICH/PIIX3/PIIX4 series
 	  host controllers.
 	  If unsure, say N.
 config SATA_DWC
 	tristate "DesignWare Cores SATA support"
 	depends on 460EX
 	help
 	  This option enables support for the on-chip SATA controller of the
 	  AppliedMicro processor 460EX.
 	  If unsure, say N.
 config SATA_DWC_DEBUG
 	bool "Debugging driver version"
 	depends on SATA_DWC
 	help
 	  This option enables debugging output in the driver.
 config SATA_DWC_VDEBUG
 	bool "Verbose debug output"
 	depends on SATA_DWC_DEBUG
 	help
 	  This option enables the taskfile dumping and NCQ debugging.
 config SATA_MV
 	tristate "Marvell SATA support"
 	help
 	  This option enables support for the Marvell Serial ATA family.
 	  Currently supports 88SX[56]0[48][01] PCI(-X) chips,
 	  as well as the newer [67]042 PCI-X/PCIe and SOC devices.
 	  If unsure, say N.
 config SATA_NV
 	tristate "NVIDIA SATA support"
 	depends on PCI
 	help
 	  This option enables support for NVIDIA Serial ATA.
 	  If unsure, say N.
 config SATA_PROMISE
 	tristate "Promise SATA TX2/TX4 support"
 	depends on PCI
 	help
 	  This option enables support for Promise Serial ATA TX2/TX4.
 	  If unsure, say N.
 config SATA_SIL
 	tristate "Silicon Image SATA support"
 	depends on PCI
 	help
 	  This option enables support for Silicon Image Serial ATA.
 	  If unsure, say N.
 config SATA_SIS
 	tristate "SiS 964/965/966/180 SATA support"
 	depends on PCI
 	select PATA_SIS
 	help
 	  This option enables support for SiS Serial ATA on
 	  SiS 964/965/966/180 and Parallel ATA on SiS 180.
 	  The PATA support for SiS 180 requires additionally to
 	  enable the PATA_SIS driver in the config.
 	  If unsure, say N.
 config SATA_SVW
 	tristate "ServerWorks Frodo / Apple K2 SATA support"
 	depends on PCI
 	help
 	  This option enables support for Broadcom/Serverworks/Apple K2
 	  SATA support.
 	  If unsure, say N.
 config SATA_ULI
 	tristate "ULi Electronics SATA support"
 	depends on PCI
 	help
 	  This option enables support for ULi Electronics SATA.
 	  If unsure, say N.
 config SATA_VIA
 	tristate "VIA SATA support"
 	depends on PCI
 	help
 	  This option enables support for VIA Serial ATA.
 	  If unsure, say N.
 config SATA_VITESSE
 	tristate "VITESSE VSC-7174 / INTEL 31244 SATA support"
 	depends on PCI
 	help
 	  This option enables support for Vitesse VSC7174 and Intel 31244 Serial ATA.
 	  If unsure, say N.
 comment "PATA SFF controllers with BMDMA"
 config PATA_ALI
 	tristate "ALi PATA support"
 	depends on PCI
 	help
 	  This option enables support for the ALi ATA interfaces
 	  found on the many ALi chipsets.
 	  If unsure, say N.
 config PATA_AMD
 	tristate "AMD/NVidia PATA support"
 	depends on PCI
 	help
 	  This option enables support for the AMD and NVidia PATA
 	  interfaces found on the chipsets for Athlon/Athlon64.
 	  If unsure, say N.
 config PATA_ARASAN_CF
 	tristate "ARASAN CompactFlash PATA Controller Support"
 	depends on DMADEVICES
 	select DMA_ENGINE
 	help
 	  Say Y here to support the ARASAN CompactFlash PATA controller
 config PATA_ARTOP
 	tristate "ARTOP 6210/6260 PATA support"
 	depends on PCI
 	help
 	  This option enables support for ARTOP PATA controllers.
 	  If unsure, say N.
 config PATA_ATIIXP
 	tristate "ATI PATA support"
 	depends on PCI
 	help
 	  This option enables support for the ATI ATA interfaces
 	  found on the many ATI chipsets.
 	  If unsure, say N.
 config PATA_ATP867X
 	tristate "ARTOP/Acard ATP867X PATA support"
 	depends on PCI
 	help
 	  This option enables support for ARTOP/Acard ATP867X PATA
 	  controllers.
 	  If unsure, say N.
 config PATA_BF54X
 	tristate "Blackfin 54x ATAPI support"
 	depends on BF542 || BF548 || BF549
 	help
 	  This option enables support for the built-in ATAPI controller on
 	  Blackfin 54x family chips.
 	  If unsure, say N.
 config PATA_CMD64X
 	tristate "CMD64x PATA support"
 	depends on PCI
 	help
 	  This option enables support for the CMD64x series chips
 	  except for the CMD640.
 	  If unsure, say N.
 config PATA_CS5520
 	tristate "CS5510/5520 PATA support"
 	depends on PCI
 	help
 	  This option enables support for the Cyrix 5510/5520
 	  companion chip used with the MediaGX/Geode processor family.
 	  If unsure, say N.
 config PATA_CS5530
 	tristate "CS5530 PATA support"
 	depends on PCI
 	help
 	  This option enables support for the Cyrix/NatSemi/AMD CS5530
 	  companion chip used with the MediaGX/Geode processor family.
 	  If unsure, say N.
 config PATA_CS5535
 	tristate "CS5535 PATA support (Experimental)"
 	depends on PCI && X86 && !X86_64 && EXPERIMENTAL
 	help
 	  This option enables support for the NatSemi/AMD CS5535
 	  companion chip used with the Geode processor family.
 	  If unsure, say N.
 config PATA_CS5536
 	tristate "CS5536 PATA support"
 	depends on PCI
 	help
 	  This option enables support for the AMD CS5536
 	  companion chip used with the Geode LX processor family.
 	  If unsure, say N.
 config PATA_CYPRESS
 	tristate "Cypress CY82C693 PATA support (Very Experimental)"
 	depends on PCI && EXPERIMENTAL
 	help
 	  This option enables support for the Cypress/Contaq CY82C693
 	  chipset found in some Alpha systems
 	  If unsure, say N.
 config PATA_EFAR
 	tristate "EFAR SLC90E66 support"
 	depends on PCI
 	help
 	  This option enables support for the EFAR SLC90E66
 	  IDE controller found on some older machines.
 	  If unsure, say N.
 config PATA_HPT366
 	tristate "HPT 366/368 PATA support"
 	depends on PCI
 	help
 	  This option enables support for the HPT 366 and 368
 	  PATA controllers via the new ATA layer.
 	  If unsure, say N.
 config PATA_HPT37X
 	tristate "HPT 370/370A/371/372/374/302 PATA support"
 	depends on PCI
 	help
 	  This option enables support for the majority of the later HPT
 	  PATA controllers via the new ATA layer.
 	  If unsure, say N.
 config PATA_HPT3X2N
 	tristate "HPT 371N/372N/302N PATA support"
 	depends on PCI
 	help
 	  This option enables support for the N variant HPT PATA
 	  controllers via the new ATA layer.
 	  If unsure, say N.
 config PATA_HPT3X3
 	tristate "HPT 343/363 PATA support"
 	depends on PCI
 	help
 	  This option enables support for the HPT 343/363
 	  PATA controllers via the new ATA layer
 	  If unsure, say N.
 config PATA_HPT3X3_DMA
 	bool "HPT 343/363 DMA support"
 	depends on PATA_HPT3X3
 	help
 	  This option enables DMA support for the HPT343/363
 	  controllers. Enable with care as there are still some
 	  problems with DMA on this chipset.
 config PATA_ICSIDE
 	tristate "Acorn ICS PATA support"
 	depends on ARM && ARCH_ACORN
 	help
 	  On Acorn systems, say Y here if you wish to use the ICS PATA
 	  interface card.  This is not required for ICS partition support.
 	  If you are unsure, say N to this.
 config PATA_IMX
 	tristate "PATA support for Freescale iMX"
 	depends on ARCH_MXC
 	help
 	  This option enables support for the PATA host available on Freescale
           iMX SoCs.
 	  If unsure, say N.
 config PATA_IT8213
 	tristate "IT8213 PATA support (Experimental)"
 	depends on PCI && EXPERIMENTAL
 	help
 	  This option enables support for the ITE 821 PATA
           controllers via the new ATA layer.
 	  If unsure, say N.
 config PATA_IT821X
 	tristate "IT8211/2 PATA support"
 	depends on PCI
 	help
 	  This option enables support for the ITE 8211 and 8212
 	  PATA controllers via the new ATA layer, including RAID
 	  mode.
 	  If unsure, say N.
 config PATA_JMICRON
 	tristate "JMicron PATA support"
 	depends on PCI
 	help
 	  Enable support for the JMicron IDE controller, via the new
 	  ATA layer.
 	  If unsure, say N.
 config PATA_MACIO
 	tristate "Apple PowerMac/PowerBook internal 'MacIO' IDE"
 	depends on PPC_PMAC
 	help
 	  Most IDE capable PowerMacs have IDE busses driven by a variant
           of this controller which is part of the Apple chipset used on
           most PowerMac models. Some models have multiple busses using
           different chipsets, though generally, MacIO is one of them.
 config PATA_MARVELL
 	tristate "Marvell PATA support via legacy mode"
 	depends on PCI
 	help
 	  This option enables limited support for the Marvell 88SE61xx ATA
 	  controllers. If you wish to use only the SATA ports then select
 	  the AHCI driver alone. If you wish to the use the PATA port or
 	  both SATA and PATA include this driver.
 	  If unsure, say N.
 config PATA_MPC52xx
 	tristate "Freescale MPC52xx SoC internal IDE"
 	depends on PPC_MPC52xx && PPC_BESTCOMM
 	select PPC_BESTCOMM_ATA
 	help
 	  This option enables support for integrated IDE controller
 	  of the Freescale MPC52xx SoC.
 	  If unsure, say N.
 config PATA_NETCELL
 	tristate "NETCELL Revolution RAID support"
 	depends on PCI
 	help
 	  This option enables support for the Netcell Revolution RAID
 	  PATA controller.
 	  If unsure, say N.
 config PATA_NINJA32
 	tristate "Ninja32/Delkin Cardbus ATA support"
 	depends on PCI
 	help
 	  This option enables support for the Ninja32, Delkin and
 	  possibly other brands of Cardbus ATA adapter
 	  If unsure, say N.
 config PATA_NS87415
 	tristate "Nat Semi NS87415 PATA support"
 	depends on PCI
 	help
 	  This option enables support for the National Semiconductor
 	  NS87415 PCI-IDE controller.
 	  If unsure, say N.
 config PATA_OLDPIIX
 	tristate "Intel PATA old PIIX support"
 	depends on PCI
 	help
 	  This option enables support for early PIIX PATA support.
 	  If unsure, say N.
 config PATA_OPTIDMA
 	tristate "OPTI FireStar PATA support (Very Experimental)"
 	depends on PCI && EXPERIMENTAL
 	help
 	  This option enables DMA/PIO support for the later OPTi
 	  controllers found on some old motherboards and in some
 	  laptops.
 	  If unsure, say N.
 config PATA_PDC2027X
 	tristate "Promise PATA 2027x support"
 	depends on PCI
 	help
 	  This option enables support for Promise PATA pdc20268 to pdc20277 host adapters.
 	  If unsure, say N.
 config PATA_PDC_OLD
 	tristate "Older Promise PATA controller support"
 	depends on PCI
 	help
 	  This option enables support for the Promise 20246, 20262, 20263,
 	  20265 and 20267 adapters.
 	  If unsure, say N.
 config PATA_RADISYS
 	tristate "RADISYS 82600 PATA support (Experimental)"
 	depends on PCI && EXPERIMENTAL
 	help
 	  This option enables support for the RADISYS 82600
 	  PATA controllers via the new ATA layer
 	  If unsure, say N.
 config PATA_RDC
 	tristate "RDC PATA support"
 	depends on PCI
 	help
 	  This option enables basic support for the later RDC PATA controllers
 	  controllers via the new ATA layer. For the RDC 1010, you need to
 	  enable the IT821X driver instead.
 	  If unsure, say N.
 config PATA_SC1200
 	tristate "SC1200 PATA support"
 	depends on PCI
 	help
 	  This option enables support for the NatSemi/AMD SC1200 SoC
 	  companion chip used with the Geode processor family.
 	  If unsure, say N.
 config PATA_SCC
 	tristate "Toshiba's Cell Reference Set IDE support"
 	depends on PCI && PPC_CELLEB
 	help
 	  This option enables support for the built-in IDE controller on
 	  Toshiba Cell Reference Board.
 	  If unsure, say N.
 config PATA_SCH
 	tristate "Intel SCH PATA support"
 	depends on PCI
 	help
 	  This option enables support for Intel SCH PATA on the Intel
 	  SCH (US15W, US15L, UL11L) series host controllers.
 	  If unsure, say N.
 config PATA_SERVERWORKS
 	tristate "SERVERWORKS OSB4/CSB5/CSB6/HT1000 PATA support"
 	depends on PCI
 	help
 	  This option enables support for the Serverworks OSB4/CSB5/CSB6 and
 	  HT1000 PATA controllers, via the new ATA layer.
 	  If unsure, say N.
 config PATA_SIL680
 	tristate "CMD / Silicon Image 680 PATA support"
 	depends on PCI
 	help
 	  This option enables support for CMD / Silicon Image 680 PATA.
 	  If unsure, say N.
 config PATA_SIS
 	tristate "SiS PATA support"
 	depends on PCI
 	help
 	  This option enables support for SiS PATA controllers
 	  If unsure, say N.
 config PATA_TOSHIBA
 	tristate "Toshiba Piccolo support (Experimental)"
 	depends on PCI && EXPERIMENTAL
 	help
 	  Support for the Toshiba Piccolo controllers. Currently only the
 	  primary channel is supported by this driver.
 	  If unsure, say N.
 config PATA_TRIFLEX
 	tristate "Compaq Triflex PATA support"
 	depends on PCI
 	help
 	  Enable support for the Compaq 'Triflex' IDE controller as found
 	  on many Compaq Pentium-Pro systems, via the new ATA layer.
 	  If unsure, say N.
 config PATA_VIA
 	tristate "VIA PATA support"
 	depends on PCI
 	help
 	  This option enables support for the VIA PATA interfaces
 	  found on the many VIA chipsets.
 	  If unsure, say N.
 config PATA_PXA
 	tristate "PXA DMA-capable PATA support"
 	depends on ARCH_PXA
 	help
 	  This option enables support for harddrive attached to PXA CPU's bus.
 	  NOTE: This driver utilizes PXA DMA controller, in case your hardware
 	        is not capable of doing MWDMA, use pata_platform instead.
 	  If unsure, say N.
 config PATA_WINBOND
 	tristate "Winbond SL82C105 PATA support"
 	depends on PCI
 	help
 	  This option enables support for SL82C105 PATA devices found in the
 	  Netwinder and some other systems
 	  If unsure, say N.
 endif # ATA_BMDMA
 comment "PIO-only SFF controllers"
 config PATA_AT32
 	tristate "Atmel AVR32 PATA support (Experimental)"
 	depends on AVR32 && PLATFORM_AT32AP && EXPERIMENTAL
 	help
 	  This option enables support for the IDE devices on the
 	  Atmel AT32AP platform.
 	  If unsure, say N.
 config PATA_AT91
 	tristate "PATA support for AT91SAM9260"
 	depends on ARM && ARCH_AT91
 	help
 	  This option enables support for IDE devices on the Atmel AT91SAM9260 SoC.
 	  If unsure, say N.
 config PATA_CMD640_PCI
 	tristate "CMD640 PCI PATA support (Experimental)"
 	depends on PCI && EXPERIMENTAL
 	help
 	  This option enables support for the CMD640 PCI IDE
 	  interface chip. Only the primary channel is currently
 	  supported.
 	  If unsure, say N.
 config PATA_ISAPNP
 	tristate "ISA Plug and Play PATA support"
 	depends on ISAPNP
 	help
 	  This option enables support for ISA plug & play ATA
 	  controllers such as those found on old soundcards.
 	  If unsure, say N.
 config PATA_IXP4XX_CF
 	tristate "IXP4XX Compact Flash support"
 	depends on ARCH_IXP4XX
 	help
 	  This option enables support for a Compact Flash connected on
 	  the ixp4xx expansion bus. This driver had been written for
 	  Loft/Avila boards in mind but can work with others.
 	  If unsure, say N.
 config PATA_MPIIX
 	tristate "Intel PATA MPIIX support"
 	depends on PCI
 	help
 	  This option enables support for MPIIX PATA support.
 	  If unsure, say N.
 config PATA_NS87410
 	tristate "Nat Semi NS87410 PATA support"
 	depends on PCI
 	help
 	  This option enables support for the National Semiconductor
 	  NS87410 PCI-IDE controller.
 	  If unsure, say N.
 config PATA_OPTI
 	tristate "OPTI621/6215 PATA support (Very Experimental)"
 	depends on PCI && EXPERIMENTAL
 	help
 	  This option enables full PIO support for the early Opti ATA
 	  controllers found on some old motherboards.
 	  If unsure, say N.
 config PATA_PALMLD
 	tristate "Palm LifeDrive PATA support"
 	depends on MACH_PALMLD
 	help
 	  This option enables support for Palm LifeDrive's internal ATA
 	  port via the new ATA layer.
 	  If unsure, say N.
 config PATA_PCMCIA
 	tristate "PCMCIA PATA support"
 	depends on PCMCIA
 	help
 	  This option enables support for PCMCIA ATA interfaces, including
 	  compact flash card adapters via the new ATA layer.
 	  If unsure, say N.
 config PATA_PLATFORM
 	tristate "Generic platform device PATA support"
 	depends on EXPERT || PPC || HAVE_PATA_PLATFORM
 	help
 	  This option enables support for generic directly connected ATA
 	  devices commonly found on embedded systems.
 	  If unsure, say N.
 config PATA_OF_PLATFORM
 	tristate "OpenFirmware platform device PATA support"
 	depends on PATA_PLATFORM && OF
 	help
 	  This option enables support for generic directly connected ATA
 	  devices commonly found on embedded systems with OpenFirmware
 	  bindings.
 	  If unsure, say N.
 config PATA_QDI
 	tristate "QDI VLB PATA support"
 	depends on ISA
+	select PATA_LEGACY
 	help
 	  Support for QDI 6500 and 6580 PATA controllers on VESA local bus.
 config PATA_RB532
 	tristate "RouterBoard 532 PATA CompactFlash support"
 	depends on MIKROTIK_RB532
 	help
 	  This option enables support for the RouterBoard 532
 	  PATA CompactFlash controller.
 	  If unsure, say N.
 config PATA_RZ1000
 	tristate "PC Tech RZ1000 PATA support"
 	depends on PCI
 	help
 	  This option enables basic support for the PC Tech RZ1000/1
 	  PATA controllers via the new ATA layer
 	  If unsure, say N.
 config PATA_SAMSUNG_CF
 	tristate "Samsung SoC PATA support"
 	depends on SAMSUNG_DEV_IDE
 	help
 	  This option enables basic support for Samsung's S3C/S5P board
 	  PATA controllers via the new ATA layer
 	  If unsure, say N.
 config PATA_WINBOND_VLB
 	tristate "Winbond W83759A VLB PATA support (Experimental)"
 	depends on ISA && EXPERIMENTAL
 	select PATA_LEGACY
 	help
 	  Support for the Winbond W83759A controller on Vesa Local Bus
 	  systems.
 comment "Generic fallback / legacy drivers"
 config PATA_ACPI
 	tristate "ACPI firmware driver for PATA"
 	depends on ATA_ACPI && ATA_BMDMA
 	help
 	  This option enables an ACPI method driver which drives
 	  motherboard PATA controller interfaces through the ACPI
 	  firmware in the BIOS. This driver can sometimes handle
 	  otherwise unsupported hardware.
 config ATA_GENERIC
 	tristate "Generic ATA support"
 	depends on PCI && ATA_BMDMA
 	help
 	  This option enables support for generic BIOS configured
 	  ATA controllers via the new ATA layer
 	  If unsure, say N.
 config PATA_LEGACY
 	tristate "Legacy ISA PATA support (Experimental)"
 	depends on (ISA || PCI) && EXPERIMENTAL
 	help
 	  This option enables support for ISA/VLB/PCI bus legacy PATA
 	  ports and allows them to be accessed via the new ATA layer.
 	  If unsure, say N.
 endif # ATA_SFF
 endif # ATA

 obj-$(CONFIG_ATA)		+= libata.o
 # non-SFF interface
 obj-$(CONFIG_SATA_AHCI)		+= ahci.o libahci.o
 obj-$(CONFIG_SATA_ACARD_AHCI)	+= acard-ahci.o libahci.o
 obj-$(CONFIG_SATA_AHCI_PLATFORM) += ahci_platform.o libahci.o
 obj-$(CONFIG_SATA_FSL)		+= sata_fsl.o
 obj-$(CONFIG_SATA_INIC162X)	+= sata_inic162x.o
 obj-$(CONFIG_SATA_SIL24)	+= sata_sil24.o
 obj-$(CONFIG_SATA_DWC)		+= sata_dwc_460ex.o
 # SFF w/ custom DMA
 obj-$(CONFIG_PDC_ADMA)		+= pdc_adma.o
 obj-$(CONFIG_PATA_ARASAN_CF)	+= pata_arasan_cf.o
 obj-$(CONFIG_PATA_OCTEON_CF)	+= pata_octeon_cf.o
 obj-$(CONFIG_SATA_QSTOR)	+= sata_qstor.o
 obj-$(CONFIG_SATA_SX4)		+= sata_sx4.o
 # SFF SATA w/ BMDMA
 obj-$(CONFIG_ATA_PIIX)		+= ata_piix.o
 obj-$(CONFIG_SATA_MV)		+= sata_mv.o
 obj-$(CONFIG_SATA_NV)		+= sata_nv.o
 obj-$(CONFIG_SATA_PROMISE)	+= sata_promise.o
 obj-$(CONFIG_SATA_SIL)		+= sata_sil.o
 obj-$(CONFIG_SATA_SIS)		+= sata_sis.o
 obj-$(CONFIG_SATA_SVW)		+= sata_svw.o
 obj-$(CONFIG_SATA_ULI)		+= sata_uli.o
 obj-$(CONFIG_SATA_VIA)		+= sata_via.o
 obj-$(CONFIG_SATA_VITESSE)	+= sata_vsc.o
 # SFF PATA w/ BMDMA
 obj-$(CONFIG_PATA_ALI)		+= pata_ali.o
 obj-$(CONFIG_PATA_AMD)		+= pata_amd.o
 obj-$(CONFIG_PATA_ARTOP)	+= pata_artop.o
 obj-$(CONFIG_PATA_ATIIXP)	+= pata_atiixp.o
 obj-$(CONFIG_PATA_ATP867X)	+= pata_atp867x.o
 obj-$(CONFIG_PATA_BF54X)	+= pata_bf54x.o
 obj-$(CONFIG_PATA_CMD64X)	+= pata_cmd64x.o
 obj-$(CONFIG_PATA_CS5520)	+= pata_cs5520.o
 obj-$(CONFIG_PATA_CS5530)	+= pata_cs5530.o
 obj-$(CONFIG_PATA_CS5535)	+= pata_cs5535.o
 obj-$(CONFIG_PATA_CS5536)	+= pata_cs5536.o
 obj-$(CONFIG_PATA_CYPRESS)	+= pata_cypress.o
 obj-$(CONFIG_PATA_EFAR)		+= pata_efar.o
 obj-$(CONFIG_PATA_HPT366)	+= pata_hpt366.o
 obj-$(CONFIG_PATA_HPT37X)	+= pata_hpt37x.o
 obj-$(CONFIG_PATA_HPT3X2N)	+= pata_hpt3x2n.o
 obj-$(CONFIG_PATA_HPT3X3)	+= pata_hpt3x3.o
 obj-$(CONFIG_PATA_ICSIDE)	+= pata_icside.o
 obj-$(CONFIG_PATA_IMX)		+= pata_imx.o
 obj-$(CONFIG_PATA_IT8213)	+= pata_it8213.o
 obj-$(CONFIG_PATA_IT821X)	+= pata_it821x.o
 obj-$(CONFIG_PATA_JMICRON)	+= pata_jmicron.o
 obj-$(CONFIG_PATA_MACIO)	+= pata_macio.o
 obj-$(CONFIG_PATA_MARVELL)	+= pata_marvell.o
 obj-$(CONFIG_PATA_MPC52xx)	+= pata_mpc52xx.o
 obj-$(CONFIG_PATA_NETCELL)	+= pata_netcell.o
 obj-$(CONFIG_PATA_NINJA32)	+= pata_ninja32.o
 obj-$(CONFIG_PATA_NS87415)	+= pata_ns87415.o
 obj-$(CONFIG_PATA_OLDPIIX)	+= pata_oldpiix.o
 obj-$(CONFIG_PATA_OPTIDMA)	+= pata_optidma.o
 obj-$(CONFIG_PATA_PDC2027X)	+= pata_pdc2027x.o
 obj-$(CONFIG_PATA_PDC_OLD)	+= pata_pdc202xx_old.o
 obj-$(CONFIG_PATA_RADISYS)	+= pata_radisys.o
 obj-$(CONFIG_PATA_RDC)		+= pata_rdc.o
 obj-$(CONFIG_PATA_SC1200)	+= pata_sc1200.o
 obj-$(CONFIG_PATA_SCC)		+= pata_scc.o
 obj-$(CONFIG_PATA_SCH)		+= pata_sch.o
 obj-$(CONFIG_PATA_SERVERWORKS)	+= pata_serverworks.o
 obj-$(CONFIG_PATA_SIL680)	+= pata_sil680.o
 obj-$(CONFIG_PATA_SIS)		+= pata_sis.o
 obj-$(CONFIG_PATA_TOSHIBA)	+= pata_piccolo.o
 obj-$(CONFIG_PATA_TRIFLEX)	+= pata_triflex.o
 obj-$(CONFIG_PATA_VIA)		+= pata_via.o
 obj-$(CONFIG_PATA_WINBOND)	+= pata_sl82c105.o
 # SFF PIO only
 obj-$(CONFIG_PATA_AT32)		+= pata_at32.o
 obj-$(CONFIG_PATA_AT91)		+= pata_at91.o
 obj-$(CONFIG_PATA_CMD640_PCI)	+= pata_cmd640.o
 obj-$(CONFIG_PATA_ISAPNP)	+= pata_isapnp.o
 obj-$(CONFIG_PATA_IXP4XX_CF)	+= pata_ixp4xx_cf.o
 obj-$(CONFIG_PATA_MPIIX)	+= pata_mpiix.o
 obj-$(CONFIG_PATA_NS87410)	+= pata_ns87410.o
 obj-$(CONFIG_PATA_OPTI)		+= pata_opti.o
 obj-$(CONFIG_PATA_PCMCIA)	+= pata_pcmcia.o
 obj-$(CONFIG_PATA_PALMLD)	+= pata_palmld.o
 obj-$(CONFIG_PATA_PLATFORM)	+= pata_platform.o
 obj-$(CONFIG_PATA_OF_PLATFORM)	+= pata_of_platform.o
-obj-$(CONFIG_PATA_QDI)		+= pata_qdi.o
 obj-$(CONFIG_PATA_RB532)	+= pata_rb532_cf.o
 obj-$(CONFIG_PATA_RZ1000)	+= pata_rz1000.o
 obj-$(CONFIG_PATA_SAMSUNG_CF)	+= pata_samsung_cf.o
 obj-$(CONFIG_PATA_PXA)		+= pata_pxa.o
 # Should be last but two libata driver
 obj-$(CONFIG_PATA_ACPI)		+= pata_acpi.o
 # Should be last but one libata driver
 obj-$(CONFIG_ATA_GENERIC)	+= ata_generic.o
 # Should be last libata driver
 obj-$(CONFIG_PATA_LEGACY)	+= pata_legacy.o
 libata-y	:= libata-core.o libata-scsi.o libata-eh.o libata-transport.o
 libata-$(CONFIG_ATA_SFF)	+= libata-sff.o
 libata-$(CONFIG_SATA_PMP)	+= libata-pmp.o
 libata-$(CONFIG_ATA_ACPI)	+= libata-acpi.o

 /*
  *   pata-legacy.c - Legacy port PATA/SATA controller driver.
  *   Copyright 2005/2006 Red Hat, all rights reserved.
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *  the Free Software Foundation; either version 2, or (at your option)
  *  any later version.
  *
  *  This program is distributed in the hope that it will be useful,
  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  *  GNU General Public License for more details.
  *
  *  You should have received a copy of the GNU General Public License
  *  along with this program; see the file COPYING.  If not, write to
  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  *
  *   An ATA driver for the legacy ATA ports.
  *
  *   Data Sources:
  *	Opti 82C465/82C611 support: Data sheets at opti-inc.com
  *	HT6560 series:
  *	Promise 20230/20620:
  *		http://www.ryston.cz/petr/vlb/pdc20230b.html
  *		http://www.ryston.cz/petr/vlb/pdc20230c.html
  *		http://www.ryston.cz/petr/vlb/pdc20630.html
  *	QDI65x0:
  *		http://www.ryston.cz/petr/vlb/qd6500.html
  *		http://www.ryston.cz/petr/vlb/qd6580.html
  *
  *	QDI65x0 probe code based on drivers/ide/legacy/qd65xx.c
  *	Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by
  *	Samuel Thibault <samuel.thibault@ens-lyon.org>
  *
  *  Unsupported but docs exist:
  *	Appian/Adaptec AIC25VL01/Cirrus Logic PD7220
  *
  *  This driver handles legacy (that is "ISA/VLB side") IDE ports found
  *  on PC class systems. There are three hybrid devices that are exceptions
  *  The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and
  *  the MPIIX where the tuning is PCI side but the IDE is "ISA side".
  *
  *  Specific support is included for the ht6560a/ht6560b/opti82c611a/
  *  opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A
  *
  *  Support for the Winbond 83759A when operating in advanced mode.
  *  Multichip mode is not currently supported.
  *
  *  Use the autospeed and pio_mask options with:
  *	Appian ADI/2 aka CLPD7220 or AIC25VL01.
  *  Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with
  *	Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,
  *	Winbond W83759A, Promise PDC20230-B
  *
  *  For now use autospeed and pio_mask as above with the W83759A. This may
  *  change.
  *
  */
 #include <linux/async.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/pci.h>
 #include <linux/init.h>
 #include <linux/blkdev.h>
 #include <linux/delay.h>
 #include <scsi/scsi_host.h>
 #include <linux/ata.h>
 #include <linux/libata.h>
 #include <linux/platform_device.h>
 #define DRV_NAME "pata_legacy"
 #define DRV_VERSION "0.6.5"
 #define NR_HOST 6
 static int all;
 module_param(all, int, 0444);
 MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)");
 struct legacy_data {
 	unsigned long timing;
 	u8 clock[2];
 	u8 last;
 	int fast;
 	struct platform_device *platform_dev;
 };
 enum controller {
 	BIOS = 0,
 	SNOOP = 1,
 	PDC20230 = 2,
 	HT6560A = 3,
 	HT6560B = 4,
 	OPTI611A = 5,
 	OPTI46X = 6,
 	QDI6500 = 7,
 	QDI6580 = 8,
 	QDI6580DP = 9,		/* Dual channel mode is different */
 	W83759A = 10,
 	UNKNOWN = -1
 };
 struct legacy_probe {
 	unsigned char *name;
 	unsigned long port;
 	unsigned int irq;
 	unsigned int slot;
 	enum controller type;
 	unsigned long private;
 };
 struct legacy_controller {
 	const char *name;
 	struct ata_port_operations *ops;
 	unsigned int pio_mask;
 	unsigned int flags;
 	unsigned int pflags;
 	int (*setup)(struct platform_device *, struct legacy_probe *probe,
 		struct legacy_data *data);
 };
 static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
 static struct legacy_probe probe_list[NR_HOST];
 static struct legacy_data legacy_data[NR_HOST];
 static struct ata_host *legacy_host[NR_HOST];
 static int nr_legacy_host;
 static int probe_all;		/* Set to check all ISA port ranges */
 static int ht6560a;		/* HT 6560A on primary 1, second 2, both 3 */
 static int ht6560b;		/* HT 6560A on primary 1, second 2, both 3 */
 static int opti82c611a;		/* Opti82c611A on primary 1, sec 2, both 3 */
 static int opti82c46x;		/* Opti 82c465MV present(pri/sec autodetect) */
-static int qdi;			/* Set to probe QDI controllers */
 static int autospeed;		/* Chip present which snoops speed changes */
 static int pio_mask = ATA_PIO4;	/* PIO range for autospeed devices */
 static int iordy_mask = 0xFFFFFFFF;	/* Use iordy if available */
+/* Set to probe QDI controllers */
+#ifdef CONFIG_PATA_QDI_MODULE
+static int qdi = 1;
+#else
+static int qdi;
+#endif
 #ifdef CONFIG_PATA_WINBOND_VLB_MODULE
 static int winbond = 1;		/* Set to probe Winbond controllers,
 					give I/O port if non standard */
 #else
 static int winbond;		/* Set to probe Winbond controllers,
 					give I/O port if non standard */
 #endif
 /**
  *	legacy_probe_add	-	Add interface to probe list
  *	@port: Controller port
  *	@irq: IRQ number
  *	@type: Controller type
  *	@private: Controller specific info
  *
  *	Add an entry into the probe list for ATA controllers. This is used
  *	to add the default ISA slots and then to build up the table
  *	further according to other ISA/VLB/Weird device scans
  *
  *	An I/O port list is used to keep ordering stable and sane, as we
  *	don't have any good way to talk about ordering otherwise
  */
 static int legacy_probe_add(unsigned long port, unsigned int irq,
 				enum controller type, unsigned long private)
 {
 	struct legacy_probe *lp = &probe_list[0];
 	int i;
 	struct legacy_probe *free = NULL;
 	for (i = 0; i < NR_HOST; i++) {
 		if (lp->port == 0 && free == NULL)
 			free = lp;
 		/* Matching port, or the correct slot for ordering */
 		if (lp->port == port || legacy_port[i] == port) {
 			free = lp;
 			break;
 		}
 		lp++;
 	}
 	if (free == NULL) {
 		printk(KERN_ERR "pata_legacy: Too many interfaces.\n");
 		return -1;
 	}
 	/* Fill in the entry for later probing */
 	free->port = port;
 	free->irq = irq;
 	free->type = type;
 	free->private = private;
 	return 0;
 }
 /**
  *	legacy_set_mode		-	mode setting
  *	@link: IDE link
  *	@unused: Device that failed when error is returned
  *
  *	Use a non standard set_mode function. We don't want to be tuned.
  *
  *	The BIOS configured everything. Our job is not to fiddle. Just use
  *	whatever PIO the hardware is using and leave it at that. When we
  *	get some kind of nice user driven API for control then we can
  *	expand on this as per hdparm in the base kernel.
  */
 static int legacy_set_mode(struct ata_link *link, struct ata_device **unused)
 {
 	struct ata_device *dev;
 	ata_for_each_dev(dev, link, ENABLED) {
 		ata_dev_info(dev, "configured for PIO\n");
 		dev->pio_mode = XFER_PIO_0;
 		dev->xfer_mode = XFER_PIO_0;
 		dev->xfer_shift = ATA_SHIFT_PIO;
 		dev->flags |= ATA_DFLAG_PIO;
 	}
 	return 0;
 }
 static struct scsi_host_template legacy_sht = {
 	ATA_PIO_SHT(DRV_NAME),
 };
 static const struct ata_port_operations legacy_base_port_ops = {
 	.inherits	= &ata_sff_port_ops,
 	.cable_detect	= ata_cable_40wire,
 };
 /*
  *	These ops are used if the user indicates the hardware
  *	snoops the commands to decide on the mode and handles the
  *	mode selection "magically" itself. Several legacy controllers
  *	do this. The mode range can be set if it is not 0x1F by setting
  *	pio_mask as well.
  */
 static struct ata_port_operations simple_port_ops = {
 	.inherits	= &legacy_base_port_ops,
 	.sff_data_xfer	= ata_sff_data_xfer_noirq,
 };
 static struct ata_port_operations legacy_port_ops = {
 	.inherits	= &legacy_base_port_ops,
 	.sff_data_xfer	= ata_sff_data_xfer_noirq,
 	.set_mode	= legacy_set_mode,
 };
 /*
  *	Promise 20230C and 20620 support
  *
  *	This controller supports PIO0 to PIO2. We set PIO timings
  *	conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA
  *	support is weird being DMA to controller and PIO'd to the host
  *	and not supported.
  */
 static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
 {
 	int tries = 5;
 	int pio = adev->pio_mode - XFER_PIO_0;
 	u8 rt;
 	unsigned long flags;
 	/* Safe as UP only. Force I/Os to occur together */
 	local_irq_save(flags);
 	/* Unlock the control interface */
 	do {
 		inb(0x1F5);
 		outb(inb(0x1F2) | 0x80, 0x1F2);
 		inb(0x1F2);
 		inb(0x3F6);
 		inb(0x3F6);
 		inb(0x1F2);
 		inb(0x1F2);
 	}
 	while ((inb(0x1F2) & 0x80) && --tries);
 	local_irq_restore(flags);
 	outb(inb(0x1F4) & 0x07, 0x1F4);
 	rt = inb(0x1F3);
 	rt &= 0x07 << (3 * adev->devno);
 	if (pio)
 		rt |= (1 + 3 * pio) << (3 * adev->devno);
 	udelay(100);
 	outb(inb(0x1F2) | 0x01, 0x1F2);
 	udelay(100);
 	inb(0x1F5);
 }
 static unsigned int pdc_data_xfer_vlb(struct ata_device *dev,
 			unsigned char *buf, unsigned int buflen, int rw)
 {
 	int slop = buflen & 3;
 	struct ata_port *ap = dev->link->ap;
 	/* 32bit I/O capable *and* we need to write a whole number of dwords */
 	if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3)
 					&& (ap->pflags & ATA_PFLAG_PIO32)) {
 		unsigned long flags;
 		local_irq_save(flags);
 		/* Perform the 32bit I/O synchronization sequence */
 		ioread8(ap->ioaddr.nsect_addr);
 		ioread8(ap->ioaddr.nsect_addr);
 		ioread8(ap->ioaddr.nsect_addr);
 		/* Now the data */
 		if (rw == READ)
 			ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
 		else
 			iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
 		if (unlikely(slop)) {
 			__le32 pad;
 			if (rw == READ) {
 				pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
 				memcpy(buf + buflen - slop, &pad, slop);
 			} else {
 				memcpy(&pad, buf + buflen - slop, slop);
 				iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
 			}
 			buflen += 4 - slop;
 		}
 		local_irq_restore(flags);
 	} else
 		buflen = ata_sff_data_xfer_noirq(dev, buf, buflen, rw);
 	return buflen;
 }
 static struct ata_port_operations pdc20230_port_ops = {
 	.inherits	= &legacy_base_port_ops,
 	.set_piomode	= pdc20230_set_piomode,
 	.sff_data_xfer	= pdc_data_xfer_vlb,
 };
 /*
  *	Holtek 6560A support
  *
  *	This controller supports PIO0 to PIO2 (no IORDY even though higher
  *	timings can be loaded).
  */
 static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)
 {
 	u8 active, recover;
 	struct ata_timing t;
 	/* Get the timing data in cycles. For now play safe at 50Mhz */
 	ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
 	active = clamp_val(t.active, 2, 15);
 	recover = clamp_val(t.recover, 4, 15);
 	inb(0x3E6);
 	inb(0x3E6);
 	inb(0x3E6);
 	inb(0x3E6);
 	iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
 	ioread8(ap->ioaddr.status_addr);
 }
 static struct ata_port_operations ht6560a_port_ops = {
 	.inherits	= &legacy_base_port_ops,
 	.set_piomode	= ht6560a_set_piomode,
 };
 /*
  *	Holtek 6560B support
  *
  *	This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO
  *	setting unless we see an ATAPI device in which case we force it off.
  *
  *	FIXME: need to implement 2nd channel support.
  */
 static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)
 {
 	u8 active, recover;
 	struct ata_timing t;
 	/* Get the timing data in cycles. For now play safe at 50Mhz */
 	ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
 	active = clamp_val(t.active, 2, 15);
 	recover = clamp_val(t.recover, 2, 16);
 	recover &= 0x15;
 	inb(0x3E6);
 	inb(0x3E6);
 	inb(0x3E6);
 	inb(0x3E6);
 	iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
 	if (adev->class != ATA_DEV_ATA) {
 		u8 rconf = inb(0x3E6);
 		if (rconf & 0x24) {
 			rconf &= ~0x24;
 			outb(rconf, 0x3E6);
 		}
 	}
 	ioread8(ap->ioaddr.status_addr);
 }
 static struct ata_port_operations ht6560b_port_ops = {
 	.inherits	= &legacy_base_port_ops,
 	.set_piomode	= ht6560b_set_piomode,
 };
 /*
  *	Opti core chipset helpers
  */
 /**
  *	opti_syscfg	-	read OPTI chipset configuration
  *	@reg: Configuration register to read
  *
  *	Returns the value of an OPTI system board configuration register.
  */
 static u8 opti_syscfg(u8 reg)
 {
 	unsigned long flags;
 	u8 r;
 	/* Uniprocessor chipset and must force cycles adjancent */
 	local_irq_save(flags);
 	outb(reg, 0x22);
 	r = inb(0x24);
 	local_irq_restore(flags);
 	return r;
 }
 /*
  *	Opti 82C611A
  *
  *	This controller supports PIO0 to PIO3.
  */
 static void opti82c611a_set_piomode(struct ata_port *ap,
 						struct ata_device *adev)
 {
 	u8 active, recover, setup;
 	struct ata_timing t;
 	struct ata_device *pair = ata_dev_pair(adev);
 	int clock;
 	int khz[4] = { 50000, 40000, 33000, 25000 };
 	u8 rc;
 	/* Enter configuration mode */
 	ioread16(ap->ioaddr.error_addr);
 	ioread16(ap->ioaddr.error_addr);
 	iowrite8(3, ap->ioaddr.nsect_addr);
 	/* Read VLB clock strapping */
 	clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03];
 	/* Get the timing data in cycles */
 	ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
 	/* Setup timing is shared */
 	if (pair) {
 		struct ata_timing tp;
 		ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
 		ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
 	}
 	active = clamp_val(t.active, 2, 17) - 2;
 	recover = clamp_val(t.recover, 1, 16) - 1;
 	setup = clamp_val(t.setup, 1, 4) - 1;
 	/* Select the right timing bank for write timing */
 	rc = ioread8(ap->ioaddr.lbal_addr);
 	rc &= 0x7F;
 	rc |= (adev->devno << 7);
 	iowrite8(rc, ap->ioaddr.lbal_addr);
 	/* Write the timings */
 	iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
 	/* Select the right bank for read timings, also
 	   load the shared timings for address */
 	rc = ioread8(ap->ioaddr.device_addr);
 	rc &= 0xC0;
 	rc |= adev->devno;	/* Index select */
 	rc |= (setup << 4) | 0x04;
 	iowrite8(rc, ap->ioaddr.device_addr);
 	/* Load the read timings */
 	iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
 	/* Ensure the timing register mode is right */
 	rc = ioread8(ap->ioaddr.lbal_addr);
 	rc &= 0x73;
 	rc |= 0x84;
 	iowrite8(rc, ap->ioaddr.lbal_addr);
 	/* Exit command mode */
 	iowrite8(0x83,  ap->ioaddr.nsect_addr);
 }
 static struct ata_port_operations opti82c611a_port_ops = {
 	.inherits	= &legacy_base_port_ops,
 	.set_piomode	= opti82c611a_set_piomode,
 };
 /*
  *	Opti 82C465MV
  *
  *	This controller supports PIO0 to PIO3. Unlike the 611A the MVB
  *	version is dual channel but doesn't have a lot of unique registers.
  */
 static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)
 {
 	u8 active, recover, setup;
 	struct ata_timing t;
 	struct ata_device *pair = ata_dev_pair(adev);
 	int clock;
 	int khz[4] = { 50000, 40000, 33000, 25000 };
 	u8 rc;
 	u8 sysclk;
 	/* Get the clock */
 	sysclk = opti_syscfg(0xAC) & 0xC0;	/* BIOS set */
 	/* Enter configuration mode */
 	ioread16(ap->ioaddr.error_addr);
 	ioread16(ap->ioaddr.error_addr);
 	iowrite8(3, ap->ioaddr.nsect_addr);
 	/* Read VLB clock strapping */
 	clock = 1000000000 / khz[sysclk];
 	/* Get the timing data in cycles */
 	ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
 	/* Setup timing is shared */
 	if (pair) {
 		struct ata_timing tp;
 		ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
 		ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
 	}
 	active = clamp_val(t.active, 2, 17) - 2;
 	recover = clamp_val(t.recover, 1, 16) - 1;
 	setup = clamp_val(t.setup, 1, 4) - 1;
 	/* Select the right timing bank for write timing */
 	rc = ioread8(ap->ioaddr.lbal_addr);
 	rc &= 0x7F;
 	rc |= (adev->devno << 7);
 	iowrite8(rc, ap->ioaddr.lbal_addr);
 	/* Write the timings */
 	iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
 	/* Select the right bank for read timings, also
 	   load the shared timings for address */
 	rc = ioread8(ap->ioaddr.device_addr);
 	rc &= 0xC0;
 	rc |= adev->devno;	/* Index select */
 	rc |= (setup << 4) | 0x04;
 	iowrite8(rc, ap->ioaddr.device_addr);
 	/* Load the read timings */
 	iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
 	/* Ensure the timing register mode is right */
 	rc = ioread8(ap->ioaddr.lbal_addr);
 	rc &= 0x73;
 	rc |= 0x84;
 	iowrite8(rc, ap->ioaddr.lbal_addr);
 	/* Exit command mode */
 	iowrite8(0x83,  ap->ioaddr.nsect_addr);
 	/* We need to know this for quad device on the MVB */
 	ap->host->private_data = ap;
 }
 /**
  *	opt82c465mv_qc_issue		-	command issue
  *	@qc: command pending
  *
  *	Called when the libata layer is about to issue a command. We wrap
  *	this interface so that we can load the correct ATA timings. The
  *	MVB has a single set of timing registers and these are shared
  *	across channels. As there are two registers we really ought to
  *	track the last two used values as a sort of register window. For
  *	now we just reload on a channel switch. On the single channel
  *	setup this condition never fires so we do nothing extra.
  *
  *	FIXME: dual channel needs ->serialize support
  */
 static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc)
 {
 	struct ata_port *ap = qc->ap;
 	struct ata_device *adev = qc->dev;
 	/* If timings are set and for the wrong channel (2nd test is
 	   due to a libata shortcoming and will eventually go I hope) */
 	if (ap->host->private_data != ap->host
 	    && ap->host->private_data != NULL)
 		opti82c46x_set_piomode(ap, adev);
 	return ata_sff_qc_issue(qc);
 }
 static struct ata_port_operations opti82c46x_port_ops = {
 	.inherits	= &legacy_base_port_ops,
 	.set_piomode	= opti82c46x_set_piomode,
 	.qc_issue	= opti82c46x_qc_issue,
 };
 static void qdi6500_set_piomode(struct ata_port *ap, struct ata_device *adev)
 {
 	struct ata_timing t;
 	struct legacy_data *ld_qdi = ap->host->private_data;
 	int active, recovery;
 	u8 timing;
 	/* Get the timing data in cycles */
 	ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
 	if (ld_qdi->fast) {
 		active = 8 - clamp_val(t.active, 1, 8);
 		recovery = 18 - clamp_val(t.recover, 3, 18);
 	} else {
 		active = 9 - clamp_val(t.active, 2, 9);
 		recovery = 15 - clamp_val(t.recover, 0, 15);
 	}
 	timing = (recovery << 4) | active | 0x08;
 	ld_qdi->clock[adev->devno] = timing;
 	outb(timing, ld_qdi->timing);
 }
 /**
  *	qdi6580dp_set_piomode		-	PIO setup for dual channel
  *	@ap: Port
  *	@adev: Device
  *
  *	In dual channel mode the 6580 has one clock per channel and we have
  *	to software clockswitch in qc_issue.
  */
 static void qdi6580dp_set_piomode(struct ata_port *ap, struct ata_device *adev)
 {
 	struct ata_timing t;
 	struct legacy_data *ld_qdi = ap->host->private_data;
 	int active, recovery;
 	u8 timing;
 	/* Get the timing data in cycles */
 	ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
 	if (ld_qdi->fast) {
 		active = 8 - clamp_val(t.active, 1, 8);
 		recovery = 18 - clamp_val(t.recover, 3, 18);
 	} else {
 		active = 9 - clamp_val(t.active, 2, 9);
 		recovery = 15 - clamp_val(t.recover, 0, 15);
 	}
 	timing = (recovery << 4) | active | 0x08;
 	ld_qdi->clock[adev->devno] = timing;
 	outb(timing, ld_qdi->timing + 2 * ap->port_no);
 	/* Clear the FIFO */
 	if (adev->class != ATA_DEV_ATA)
 		outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3);
 }
 /**
  *	qdi6580_set_piomode		-	PIO setup for single channel
  *	@ap: Port
  *	@adev: Device
  *
  *	In single channel mode the 6580 has one clock per device and we can
  *	avoid the requirement to clock switch. We also have to load the timing
  *	into the right clock according to whether we are master or slave.
  */
 static void qdi6580_set_piomode(struct ata_port *ap, struct ata_device *adev)
 {
 	struct ata_timing t;
 	struct legacy_data *ld_qdi = ap->host->private_data;
 	int active, recovery;
 	u8 timing;
 	/* Get the timing data in cycles */
 	ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
 	if (ld_qdi->fast) {
 		active = 8 - clamp_val(t.active, 1, 8);
 		recovery = 18 - clamp_val(t.recover, 3, 18);
 	} else {
 		active = 9 - clamp_val(t.active, 2, 9);
 		recovery = 15 - clamp_val(t.recover, 0, 15);
 	}
 	timing = (recovery << 4) | active | 0x08;
 	ld_qdi->clock[adev->devno] = timing;
 	outb(timing, ld_qdi->timing + 2 * adev->devno);
 	/* Clear the FIFO */
 	if (adev->class != ATA_DEV_ATA)
 		outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3);
 }
 /**
  *	qdi_qc_issue		-	command issue
  *	@qc: command pending
  *
  *	Called when the libata layer is about to issue a command. We wrap
  *	this interface so that we can load the correct ATA timings.
  */
 static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc)
 {
 	struct ata_port *ap = qc->ap;
 	struct ata_device *adev = qc->dev;
 	struct legacy_data *ld_qdi = ap->host->private_data;
 	if (ld_qdi->clock[adev->devno] != ld_qdi->last) {
 		if (adev->pio_mode) {
 			ld_qdi->last = ld_qdi->clock[adev->devno];
 			outb(ld_qdi->clock[adev->devno], ld_qdi->timing +
 							2 * ap->port_no);
 		}
 	}
 	return ata_sff_qc_issue(qc);
 }
 static unsigned int vlb32_data_xfer(struct ata_device *adev, unsigned char *buf,
 					unsigned int buflen, int rw)
 {
 	struct ata_port *ap = adev->link->ap;
 	int slop = buflen & 3;
 	if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3)
 					&& (ap->pflags & ATA_PFLAG_PIO32)) {
 		if (rw == WRITE)
 			iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
 		else
 			ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
 		if (unlikely(slop)) {
 			__le32 pad;
 			if (rw == WRITE) {
 				memcpy(&pad, buf + buflen - slop, slop);
 				iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
 			} else {
 				pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
 				memcpy(buf + buflen - slop, &pad, slop);
 			}
 		}
 		return (buflen + 3) & ~3;
 	} else
 		return ata_sff_data_xfer(adev, buf, buflen, rw);
 }
 static int qdi_port(struct platform_device *dev,
 			struct legacy_probe *lp, struct legacy_data *ld)
 {
 	if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL)
 		return -EBUSY;
 	ld->timing = lp->private;
 	return 0;
 }
 static struct ata_port_operations qdi6500_port_ops = {
 	.inherits	= &legacy_base_port_ops,
 	.set_piomode	= qdi6500_set_piomode,
 	.qc_issue	= qdi_qc_issue,
 	.sff_data_xfer	= vlb32_data_xfer,
 };
 static struct ata_port_operations qdi6580_port_ops = {
 	.inherits	= &legacy_base_port_ops,
 	.set_piomode	= qdi6580_set_piomode,
 	.sff_data_xfer	= vlb32_data_xfer,
 };
 static struct ata_port_operations qdi6580dp_port_ops = {
 	.inherits	= &legacy_base_port_ops,
 	.set_piomode	= qdi6580dp_set_piomode,
 	.qc_issue	= qdi_qc_issue,
 	.sff_data_xfer	= vlb32_data_xfer,
 };
 static DEFINE_SPINLOCK(winbond_lock);
 static void winbond_writecfg(unsigned long port, u8 reg, u8 val)
 {
 	unsigned long flags;
 	spin_lock_irqsave(&winbond_lock, flags);
 	outb(reg, port + 0x01);
 	outb(val, port + 0x02);
 	spin_unlock_irqrestore(&winbond_lock, flags);
 }
 static u8 winbond_readcfg(unsigned long port, u8 reg)
 {
 	u8 val;
 	unsigned long flags;
 	spin_lock_irqsave(&winbond_lock, flags);
 	outb(reg, port + 0x01);
 	val = inb(port + 0x02);
 	spin_unlock_irqrestore(&winbond_lock, flags);
 	return val;
 }
 static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev)
 {
 	struct ata_timing t;
 	struct legacy_data *ld_winbond = ap->host->private_data;
 	int active, recovery;
 	u8 reg;
 	int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2);
 	reg = winbond_readcfg(ld_winbond->timing, 0x81);
 	/* Get the timing data in cycles */
 	if (reg & 0x40)		/* Fast VLB bus, assume 50MHz */
 		ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
 	else
 		ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
 	active = (clamp_val(t.active, 3, 17) - 1) & 0x0F;
 	recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F;
 	timing = (active << 4) | recovery;
 	winbond_writecfg(ld_winbond->timing, timing, reg);
 	/* Load the setup timing */
 	reg = 0x35;
 	if (adev->class != ATA_DEV_ATA)
 		reg |= 0x08;	/* FIFO off */
 	if (!ata_pio_need_iordy(adev))
 		reg |= 0x02;	/* IORDY off */
 	reg |= (clamp_val(t.setup, 0, 3) << 6);
 	winbond_writecfg(ld_winbond->timing, timing + 1, reg);
 }
 static int winbond_port(struct platform_device *dev,
 			struct legacy_probe *lp, struct legacy_data *ld)
 {
 	if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL)
 		return -EBUSY;
 	ld->timing = lp->private;
 	return 0;
 }
 static struct ata_port_operations winbond_port_ops = {
 	.inherits	= &legacy_base_port_ops,
 	.set_piomode	= winbond_set_piomode,
 	.sff_data_xfer	= vlb32_data_xfer,
 };
 static struct legacy_controller controllers[] = {
 	{"BIOS",	&legacy_port_ops, 	0x1F,
 			ATA_FLAG_NO_IORDY,	0,			NULL },
 	{"Snooping", 	&simple_port_ops, 	0x1F,
 			0,			0,			NULL },
 	{"PDC20230",	&pdc20230_port_ops,	0x7,
 			ATA_FLAG_NO_IORDY,
 			ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE,	NULL },
 	{"HT6560A",	&ht6560a_port_ops,	0x07,
 			ATA_FLAG_NO_IORDY,	0,			NULL },
 	{"HT6560B",	&ht6560b_port_ops,	0x1F,
 			ATA_FLAG_NO_IORDY,	0,			NULL },
 	{"OPTI82C611A",	&opti82c611a_port_ops,	0x0F,
 			0,			0,			NULL },
 	{"OPTI82C46X",	&opti82c46x_port_ops,	0x0F,
 			0,			0,			NULL },
 	{"QDI6500",	&qdi6500_port_ops,	0x07,
 			ATA_FLAG_NO_IORDY,
 			ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE,    qdi_port },
 	{"QDI6580",	&qdi6580_port_ops,	0x1F,
 			0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
 	{"QDI6580DP",	&qdi6580dp_port_ops,	0x1F,
 			0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
 	{"W83759A",	&winbond_port_ops,	0x1F,
 			0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE,
 								winbond_port }
 };
 /**
  *	probe_chip_type		-	Discover controller
  *	@probe: Probe entry to check
  *
  *	Probe an ATA port and identify the type of controller. We don't
  *	check if the controller appears to be driveless at this point.
  */
 static __init int probe_chip_type(struct legacy_probe *probe)
 {
 	int mask = 1 << probe->slot;
 	if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) {
 		u8 reg = winbond_readcfg(winbond, 0x81);
 		reg |= 0x80;	/* jumpered mode off */
 		winbond_writecfg(winbond, 0x81, reg);
 		reg = winbond_readcfg(winbond, 0x83);
 		reg |= 0xF0;	/* local control */
 		winbond_writecfg(winbond, 0x83, reg);
 		reg = winbond_readcfg(winbond, 0x85);
 		reg |= 0xF0;	/* programmable timing */
 		winbond_writecfg(winbond, 0x85, reg);
 		reg = winbond_readcfg(winbond, 0x81);
 		if (reg & mask)
 			return W83759A;
 	}
 	if (probe->port == 0x1F0) {
 		unsigned long flags;
 		local_irq_save(flags);
 		/* Probes */
 		outb(inb(0x1F2) | 0x80, 0x1F2);
 		inb(0x1F5);
 		inb(0x1F2);
 		inb(0x3F6);
 		inb(0x3F6);
 		inb(0x1F2);
 		inb(0x1F2);
 		if ((inb(0x1F2) & 0x80) == 0) {
 			/* PDC20230c or 20630 ? */
 			printk(KERN_INFO  "PDC20230-C/20630 VLB ATA controller"
 							" detected.\n");
 			udelay(100);
 			inb(0x1F5);
 			local_irq_restore(flags);
 			return PDC20230;
 		} else {
 			outb(0x55, 0x1F2);
 			inb(0x1F2);
 			inb(0x1F2);
 			if (inb(0x1F2) == 0x00)
 				printk(KERN_INFO "PDC20230-B VLB ATA "
 						     "controller detected.\n");
 			local_irq_restore(flags);
 			return BIOS;
 		}
 		local_irq_restore(flags);
 	}
 	if (ht6560a & mask)
 		return HT6560A;
 	if (ht6560b & mask)
 		return HT6560B;
 	if (opti82c611a & mask)
 		return OPTI611A;
 	if (opti82c46x & mask)
 		return OPTI46X;
 	if (autospeed & mask)
 		return SNOOP;
 	return BIOS;
 }
 /**
  *	legacy_init_one		-	attach a legacy interface
  *	@pl: probe record
  *
  *	Register an ISA bus IDE interface. Such interfaces are PIO and we
  *	assume do not support IRQ sharing.
  */
 static __init int legacy_init_one(struct legacy_probe *probe)
 {
 	struct legacy_controller *controller = &controllers[probe->type];
 	int pio_modes = controller->pio_mask;
 	unsigned long io = probe->port;
 	u32 mask = (1 << probe->slot);
 	struct ata_port_operations *ops = controller->ops;
 	struct legacy_data *ld = &legacy_data[probe->slot];
 	struct ata_host *host = NULL;
 	struct ata_port *ap;
 	struct platform_device *pdev;
 	struct ata_device *dev;
 	void __iomem *io_addr, *ctrl_addr;
 	u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY;
 	int ret;
 	iordy |= controller->flags;
 	pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0);
 	if (IS_ERR(pdev))
 		return PTR_ERR(pdev);
 	ret = -EBUSY;
 	if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL ||
 	    devm_request_region(&pdev->dev, io + 0x0206, 1,
 							"pata_legacy") == NULL)
 		goto fail;
 	ret = -ENOMEM;
 	io_addr = devm_ioport_map(&pdev->dev, io, 8);
 	ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1);
 	if (!io_addr || !ctrl_addr)
 		goto fail;
 	if (controller->setup)
 		if (controller->setup(pdev, probe, ld) < 0)
 			goto fail;
 	host = ata_host_alloc(&pdev->dev, 1);
 	if (!host)
 		goto fail;
 	ap = host->ports[0];
 	ap->ops = ops;
 	ap->pio_mask = pio_modes;
 	ap->flags |= ATA_FLAG_SLAVE_POSS | iordy;
 	ap->pflags |= controller->pflags;
 	ap->ioaddr.cmd_addr = io_addr;
 	ap->ioaddr.altstatus_addr = ctrl_addr;
 	ap->ioaddr.ctl_addr = ctrl_addr;
 	ata_sff_std_ports(&ap->ioaddr);
 	ap->host->private_data = ld;
 	ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206);
 	ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0,
 				&legacy_sht);
 	if (ret)
 		goto fail;
 	async_synchronize_full();
 	ld->platform_dev = pdev;
 	/* Nothing found means we drop the port as its probably not there */
 	ret = -ENODEV;
 	ata_for_each_dev(dev, &ap->link, ALL) {
 		if (!ata_dev_absent(dev)) {
 			legacy_host[probe->slot] = host;
 			ld->platform_dev = pdev;
 			return 0;
 		}
 	}
 	ata_host_detach(host);
 fail:
 	platform_device_unregister(pdev);
 	return ret;
 }
 /**
  *	legacy_check_special_cases	-	ATA special cases
  *	@p: PCI device to check
  *	@master: set this if we find an ATA master
  *	@master: set this if we find an ATA secondary
  *
  *	A small number of vendors implemented early PCI ATA interfaces
  *	on bridge logic without the ATA interface being PCI visible.
  *	Where we have a matching PCI driver we must skip the relevant
  *	device here. If we don't know about it then the legacy driver
  *	is the right driver anyway.
  */
 static void __init legacy_check_special_cases(struct pci_dev *p, int *primary,
 								int *secondary)
 {
 	/* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */
 	if (p->vendor == 0x1078 && p->device == 0x0000) {
 		*primary = *secondary = 1;
 		return;
 	}
 	/* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */
 	if (p->vendor == 0x1078 && p->device == 0x0002) {
 		*primary = *secondary = 1;
 		return;
 	}
 	/* Intel MPIIX - PIO ATA on non PCI side of bridge */
 	if (p->vendor == 0x8086 && p->device == 0x1234) {
 		u16 r;
 		pci_read_config_word(p, 0x6C, &r);
 		if (r & 0x8000) {
 			/* ATA port enabled */
 			if (r & 0x4000)
 				*secondary = 1;
 			else
 				*primary = 1;
 		}
 		return;
 	}
 }
 static __init void probe_opti_vlb(void)
 {
 	/* If an OPTI 82C46X is present find out where the channels are */
 	static const char *optis[4] = {
 		"3/463MV", "5MV",
 		"5MVA", "5MVB"
 	};
 	u8 chans = 1;
 	u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;
 	opti82c46x = 3;	/* Assume master and slave first */
 	printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n",
 								optis[ctrl]);
 	if (ctrl == 3)
 		chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1;
 	ctrl = opti_syscfg(0xAC);
 	/* Check enabled and this port is the 465MV port. On the
 	   MVB we may have two channels */
 	if (ctrl & 8) {
 		if (chans == 2) {
 			legacy_probe_add(0x1F0, 14, OPTI46X, 0);
 			legacy_probe_add(0x170, 15, OPTI46X, 0);
 		}
 		if (ctrl & 4)
 			legacy_probe_add(0x170, 15, OPTI46X, 0);
 		else
 			legacy_probe_add(0x1F0, 14, OPTI46X, 0);
 	} else
 		legacy_probe_add(0x1F0, 14, OPTI46X, 0);
 }
 static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port)
 {
 	static const unsigned long ide_port[2] = { 0x170, 0x1F0 };
 	/* Check card type */
 	if ((r & 0xF0) == 0xC0) {
 		/* QD6500: single channel */
 		if (r & 8)
 			/* Disabled ? */
 			return;
 		legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
 								QDI6500, port);
 	}
 	if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) {
 		/* QD6580: dual channel */
 		if (!request_region(port + 2 , 2, "pata_qdi")) {
 			release_region(port, 2);
 			return;
 		}
 		res = inb(port + 3);
 		/* Single channel mode ? */
 		if (res & 1)
 			legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
 								QDI6580, port);
 		else { /* Dual channel mode */
 			legacy_probe_add(0x1F0, 14, QDI6580DP, port);
 			/* port + 0x02, r & 0x04 */
 			legacy_probe_add(0x170, 15, QDI6580DP, port + 2);
 		}
 		release_region(port + 2, 2);
 	}
 }
 static __init void probe_qdi_vlb(void)
 {
 	unsigned long flags;
 	static const unsigned long qd_port[2] = { 0x30, 0xB0 };
 	int i;
 	/*
 	 *	Check each possible QD65xx base address
 	 */
 	for (i = 0; i < 2; i++) {
 		unsigned long port = qd_port[i];
 		u8 r, res;
 		if (request_region(port, 2, "pata_qdi")) {
 			/* Check for a card */
 			local_irq_save(flags);
 			/* I have no h/w that needs this delay but it
 			   is present in the historic code */
 			r = inb(port);
 			udelay(1);
 			outb(0x19, port);
 			udelay(1);
 			res = inb(port);
 			udelay(1);
 			outb(r, port);
 			udelay(1);
 			local_irq_restore(flags);
 			/* Fail */
 			if (res == 0x19) {
 				release_region(port, 2);
 				continue;
 			}
 			/* Passes the presence test */
 			r = inb(port + 1);
 			udelay(1);
 			/* Check port agrees with port set */
 			if ((r & 2) >> 1 == i)
 				qdi65_identify_port(r, res, port);
 			release_region(port, 2);
 		}
 	}
 }
 /**
  *	legacy_init		-	attach legacy interfaces
  *
  *	Attach legacy IDE interfaces by scanning the usual IRQ/port suspects.
  *	Right now we do not scan the ide0 and ide1 address but should do so
  *	for non PCI systems or systems with no PCI IDE legacy mode devices.
  *	If you fix that note there are special cases to consider like VLB
  *	drivers and CS5510/20.
  */
 static __init int legacy_init(void)
 {
 	int i;
 	int ct = 0;
 	int primary = 0;
 	int secondary = 0;
 	int pci_present = 0;
 	struct legacy_probe *pl = &probe_list[0];
 	int slot = 0;
 	struct pci_dev *p = NULL;
 	for_each_pci_dev(p) {
 		int r;
 		/* Check for any overlap of the system ATA mappings. Native
 		   mode controllers stuck on these addresses or some devices
 		   in 'raid' mode won't be found by the storage class test */
 		for (r = 0; r < 6; r++) {
 			if (pci_resource_start(p, r) == 0x1f0)
 				primary = 1;
 			if (pci_resource_start(p, r) == 0x170)
 				secondary = 1;
 		}
 		/* Check for special cases */
 		legacy_check_special_cases(p, &primary, &secondary);
 		/* If PCI bus is present then don't probe for tertiary
 		   legacy ports */
 		pci_present = 1;
 	}
 	if (winbond == 1)
 		winbond = 0x130;	/* Default port, alt is 1B0 */
 	if (primary == 0 || all)
 		legacy_probe_add(0x1F0, 14, UNKNOWN, 0);
 	if (secondary == 0 || all)
 		legacy_probe_add(0x170, 15, UNKNOWN, 0);
 	if (probe_all || !pci_present) {
 		/* ISA/VLB extra ports */
 		legacy_probe_add(0x1E8, 11, UNKNOWN, 0);
 		legacy_probe_add(0x168, 10, UNKNOWN, 0);
 		legacy_probe_add(0x1E0, 8, UNKNOWN, 0);
 		legacy_probe_add(0x160, 12, UNKNOWN, 0);
 	}
 	if (opti82c46x)
 		probe_opti_vlb();
 	if (qdi)
 		probe_qdi_vlb();
 	for (i = 0; i < NR_HOST; i++, pl++) {
 		if (pl->port == 0)
 			continue;
 		if (pl->type == UNKNOWN)
 			pl->type = probe_chip_type(pl);
 		pl->slot = slot++;
 		if (legacy_init_one(pl) == 0)
 			ct++;
 	}
 	if (ct != 0)
 		return 0;
 	return -ENODEV;
 }
 static __exit void legacy_exit(void)
 {
 	int i;
 	for (i = 0; i < nr_legacy_host; i++) {
 		struct legacy_data *ld = &legacy_data[i];
 		ata_host_detach(legacy_host[i]);
 		platform_device_unregister(ld->platform_dev);
 	}
 }
 MODULE_AUTHOR("Alan Cox");
 MODULE_DESCRIPTION("low-level driver for legacy ATA");
 MODULE_LICENSE("GPL");
 MODULE_VERSION(DRV_VERSION);
+MODULE_ALIAS("pata_qdi");
 MODULE_ALIAS("pata_winbond");
 module_param(probe_all, int, 0);
 module_param(autospeed, int, 0);
 module_param(ht6560a, int, 0);
 module_param(ht6560b, int, 0);
 module_param(opti82c611a, int, 0);
 module_param(opti82c46x, int, 0);
 module_param(qdi, int, 0);
 module_param(winbond, int, 0);
 module_param(pio_mask, int, 0);
 module_param(iordy_mask, int, 0);
 module_init(legacy_init);
 module_exit(legacy_exit);

1	/*		File was deleted
2	* pata_qdi.c - QDI VLB ATA controllers
3	* (C) 2006 Red Hat
4	*
5	* This driver mostly exists as a proof of concept for non PCI devices under
6	* libata. While the QDI6580 was 'neat' in 1993 it is no longer terribly
7	* useful.
8	*
9	* Tuning code written from the documentation at
10	* http://www.ryston.cz/petr/vlb/qd6500.html
11	* http://www.ryston.cz/petr/vlb/qd6580.html
12	*
13	* Probe code based on drivers/ide/legacy/qd65xx.c
14	* Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by
15	* Samuel Thibault <samuel.thibault@ens-lyon.org>
16	*/
17
18	#include <linux/kernel.h>
19	#include <linux/module.h>
20	#include <linux/pci.h>
21	#include <linux/init.h>
22	#include <linux/blkdev.h>
23	#include <linux/delay.h>
24	#include <scsi/scsi_host.h>
25	#include <linux/libata.h>
26	#include <linux/platform_device.h>
27
28	#define DRV_NAME "pata_qdi"
29	#define DRV_VERSION "0.3.1"
30
31	#define NR_HOST 4 /* Two 6580s */
32
33	struct qdi_data {
34	unsigned long timing;
35	u8 clock[2];
36	u8 last;
37	int fast;
38	struct platform_device *platform_dev;
39
40	};
41
42	static struct ata_host *qdi_host[NR_HOST];
43	static struct qdi_data qdi_data[NR_HOST];
44	static int nr_qdi_host;
45
46	#ifdef MODULE
47	static int probe_qdi = 1;
48	#else
49	static int probe_qdi;
50	#endif
51
52	static void qdi6500_set_piomode(struct ata_port ap, struct ata_device adev)
53	{
54	struct ata_timing t;
55	struct qdi_data *qdi = ap->host->private_data;
56	int active, recovery;
57	u8 timing;
58
59	/* Get the timing data in cycles */
60	ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
61
62	if (qdi->fast) {
63	active = 8 - clamp_val(t.active, 1, 8);
64	recovery = 18 - clamp_val(t.recover, 3, 18);
65	} else {
66	active = 9 - clamp_val(t.active, 2, 9);
67	recovery = 15 - clamp_val(t.recover, 0, 15);
68	}
69	timing = (recovery << 4) \| active \| 0x08;
70
71	qdi->clock[adev->devno] = timing;
72
73	outb(timing, qdi->timing);
74	}
75
76	static void qdi6580_set_piomode(struct ata_port ap, struct ata_device adev)
77	{
78	struct ata_timing t;
79	struct qdi_data *qdi = ap->host->private_data;
80	int active, recovery;
81	u8 timing;
82
83	/* Get the timing data in cycles */
84	ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
85
86	if (qdi->fast) {
87	active = 8 - clamp_val(t.active, 1, 8);
88	recovery = 18 - clamp_val(t.recover, 3, 18);
89	} else {
90	active = 9 - clamp_val(t.active, 2, 9);
91	recovery = 15 - clamp_val(t.recover, 0, 15);
92	}
93	timing = (recovery << 4) \| active \| 0x08;
94
95	qdi->clock[adev->devno] = timing;
96
97	outb(timing, qdi->timing);
98
99	/* Clear the FIFO */
100	if (adev->class != ATA_DEV_ATA)
101	outb(0x5F, (qdi->timing & 0xFFF0) + 3);
102	}
103
104	/**
105	* qdi_qc_issue - command issue
106	* @qc: command pending
107	*
108	* Called when the libata layer is about to issue a command. We wrap
109	* this interface so that we can load the correct ATA timings.
110	*/
111
112	static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc)
113	{
114	struct ata_port *ap = qc->ap;
115	struct ata_device *adev = qc->dev;
116	struct qdi_data *qdi = ap->host->private_data;
117
118	if (qdi->clock[adev->devno] != qdi->last) {
119	if (adev->pio_mode) {
120	qdi->last = qdi->clock[adev->devno];
121	outb(qdi->clock[adev->devno], qdi->timing);
122	}
123	}
124	return ata_sff_qc_issue(qc);
125	}
126
127	static unsigned int qdi_data_xfer(struct ata_device dev, unsigned char buf,
128	unsigned int buflen, int rw)
129	{
130	if (ata_id_has_dword_io(dev->id)) {
131	struct ata_port *ap = dev->link->ap;
132	int slop = buflen & 3;
133
134	if (rw == READ)
135	ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
136	else
137	iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
138
139	if (unlikely(slop)) {
140	__le32 pad;
141	if (rw == READ) {
142	pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
143	memcpy(buf + buflen - slop, &pad, slop);
144	} else {
145	memcpy(&pad, buf + buflen - slop, slop);
146	iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
147	}
148	buflen += 4 - slop;
149	}
150	} else
151	buflen = ata_sff_data_xfer(dev, buf, buflen, rw);
152
153	return buflen;
154	}
155
156	static struct scsi_host_template qdi_sht = {
157	ATA_PIO_SHT(DRV_NAME),
158	};
159
160	static struct ata_port_operations qdi6500_port_ops = {
161	.inherits = &ata_sff_port_ops,
162	.qc_issue = qdi_qc_issue,
163	.sff_data_xfer = qdi_data_xfer,
164	.cable_detect = ata_cable_40wire,
165	.set_piomode = qdi6500_set_piomode,
166	};
167
168	static struct ata_port_operations qdi6580_port_ops = {
169	.inherits = &qdi6500_port_ops,
170	.set_piomode = qdi6580_set_piomode,
171	};
172
173	/**
174	* qdi_init_one - attach a qdi interface
175	* @type: Type to display
176	* @io: I/O port start
177	* @irq: interrupt line
178	* @fast: True if on a > 33Mhz VLB
179	*
180	* Register an ISA bus IDE interface. Such interfaces are PIO and we
181	* assume do not support IRQ sharing.
182	*/
183
184	static __init int qdi_init_one(unsigned long port, int type, unsigned long io, int irq, int fast)
185	{
186	unsigned long ctl = io + 0x206;
187	struct platform_device *pdev;
188	struct ata_host *host;
189	struct ata_port *ap;
190	void __iomem io_addr, ctl_addr;
191	int ret;
192
193	/*
194	* Fill in a probe structure first of all
195	*/
196
197	pdev = platform_device_register_simple(DRV_NAME, nr_qdi_host, NULL, 0);
198	if (IS_ERR(pdev))
199	return PTR_ERR(pdev);
200
201	ret = -ENOMEM;
202	io_addr = devm_ioport_map(&pdev->dev, io, 8);
203	ctl_addr = devm_ioport_map(&pdev->dev, ctl, 1);
204	if (!io_addr \|\| !ctl_addr)
205	goto fail;
206
207	ret = -ENOMEM;
208	host = ata_host_alloc(&pdev->dev, 1);
209	if (!host)
210	goto fail;
211	ap = host->ports[0];
212
213	if (type == 6580) {
214	ap->ops = &qdi6580_port_ops;
215	ap->pio_mask = ATA_PIO4;
216	ap->flags \|= ATA_FLAG_SLAVE_POSS;
217	} else {
218	ap->ops = &qdi6500_port_ops;
219	ap->pio_mask = ATA_PIO2; /* Actually PIO3 !IORDY is possible */
220	ap->flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_NO_IORDY;
221	}
222
223	ap->ioaddr.cmd_addr = io_addr;
224	ap->ioaddr.altstatus_addr = ctl_addr;
225	ap->ioaddr.ctl_addr = ctl_addr;
226	ata_sff_std_ports(&ap->ioaddr);
227
228	ata_port_desc(ap, "cmd %lx ctl %lx", io, ctl);
229
230	/*
231	* Hook in a private data structure per channel
232	*/
233	ap->private_data = &qdi_data[nr_qdi_host];
234
235	qdi_data[nr_qdi_host].timing = port;
236	qdi_data[nr_qdi_host].fast = fast;
237	qdi_data[nr_qdi_host].platform_dev = pdev;
238
239	printk(KERN_INFO DRV_NAME": qd%d at 0x%lx.\n", type, io);
240
241	/* activate */
242	ret = ata_host_activate(host, irq, ata_sff_interrupt, 0, &qdi_sht);
243	if (ret)
244	goto fail;
245
246	qdi_host[nr_qdi_host++] = dev_get_drvdata(&pdev->dev);
247	return 0;
248
249	fail:
250	platform_device_unregister(pdev);
251	return ret;
252	}
253
254	/**
255	* qdi_init - attach qdi interfaces
256	*
257	* Attach qdi IDE interfaces by scanning the ports it may occupy.
258	*/
259
260	static __init int qdi_init(void)
261	{
262	unsigned long flags;
263	static const unsigned long qd_port[2] = { 0x30, 0xB0 };
264	static const unsigned long ide_port[2] = { 0x170, 0x1F0 };
265	static const int ide_irq[2] = { 14, 15 };
266
267	int ct = 0;
268	int i;
269
270	if (probe_qdi == 0)
271	return -ENODEV;
272
273	/*
274	* Check each possible QD65xx base address
275	*/
276
277	for (i = 0; i < 2; i++) {
278	unsigned long port = qd_port[i];
279	u8 r, res;
280
281
282	if (request_region(port, 2, "pata_qdi")) {
283	/* Check for a card */
284	local_irq_save(flags);
285	r = inb_p(port);
286	outb_p(0x19, port);
287	res = inb_p(port);
288	outb_p(r, port);
289	local_irq_restore(flags);
290
291	/* Fail */
292	if (res == 0x19)
293	{
294	release_region(port, 2);
295	continue;
296	}
297
298	/* Passes the presence test */
299	r = inb_p(port + 1); /* Check port agrees with port set */
300	if ((r & 2) >> 1 != i) {
301	release_region(port, 2);
302	continue;
303	}
304
305	/* Check card type */
306	if ((r & 0xF0) == 0xC0) {
307	/* QD6500: single channel */
308	if (r & 8) {
309	/* Disabled ? */
310	release_region(port, 2);
311	continue;
312	}
313	if (qdi_init_one(port, 6500, ide_port[r & 0x01], ide_irq[r & 0x01], r & 0x04) == 0)
314	ct++;
315	}
316	if (((r & 0xF0) == 0xA0) \|\| (r & 0xF0) == 0x50) {
317	/* QD6580: dual channel */
318	if (!request_region(port + 2 , 2, "pata_qdi"))
319	{
320	release_region(port, 2);
321	continue;
322	}
323	res = inb(port + 3);
324	if (res & 1) {
325	/* Single channel mode */
326	if (qdi_init_one(port, 6580, ide_port[r & 0x01], ide_irq[r & 0x01], r & 0x04) == 0)
327	ct++;
328	} else {
329	/* Dual channel mode */
330	if (qdi_init_one(port, 6580, 0x1F0, 14, r & 0x04) == 0)
331	ct++;
332	if (qdi_init_one(port + 2, 6580, 0x170, 15, r & 0x04) == 0)
333	ct++;
334	}
335	}
336	}
337	}
338	if (ct != 0)
339	return 0;
340	return -ENODEV;
341	}
342
343	static __exit void qdi_exit(void)
344	{
345	int i;
346
347	for (i = 0; i < nr_qdi_host; i++) {
348	ata_host_detach(qdi_host[i]);
349	/* Free the control resource. The 6580 dual channel has the resources
350	* claimed as a pair of 2 byte resources so we need no special cases...
351	*/
352	release_region(qdi_data[i].timing, 2);
353	platform_device_unregister(qdi_data[i].platform_dev);
354	}
355	}
356
357	MODULE_AUTHOR("Alan Cox");
358	MODULE_DESCRIPTION("low-level driver for qdi ATA");
359	MODULE_LICENSE("GPL");
360	MODULE_VERSION(DRV_VERSION);
361
362	module_init(qdi_init);
363	module_exit(qdi_exit);
364
365	module_param(probe_qdi, int, 0);
366		1	/*
367		2	* pata_qdi.c - QDI VLB ATA controllers