Doug / smarc-fsl-linux-kernel | Embedian Git Server

Commit 13882a82ee1646336c3996c93b4a560a55d2a419

Authored by Clemens Ladisch 2011-05-02 15:33:56 +0800

Committed by Stefan Richter 2011-05-11 04:53:45 +0800

Exists in master and in 7 other branches

firewire: optimize iso queueing by setting wake only after the last packet

When queueing iso packets, the run time is dominated by the two
MMIO accesses that set the DMA context's wake bit.  Because most
drivers submit packets in batches, we can save much time by
removing all but the last wakeup.

The internal kernel API is changed to require a call to
fw_iso_context_queue_flush() after a batch of queued packets.
The user space API does not change, so one call to
FW_CDEV_IOC_QUEUE_ISO must specify multiple packets to take
advantage of this optimization.

In my measurements, this patch reduces the time needed to queue
fifty skip packets from userspace to one sixth on a 2.5 GHz CPU,
or to one third at 800 MHz.

Signed-off-by: Clemens Ladisch <clemens@ladisch.de>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>

Showing 9 changed files with 35 additions and 5 deletions Inline Diff

drivers/firewire/core-card.c
drivers/firewire/core-cdev.c
drivers/firewire/core-iso.c
drivers/firewire/core.h
drivers/firewire/net.c
drivers/firewire/ohci.c
drivers/media/dvb/firewire/firedtv-fw.c
include/linux/firewire.h
sound/firewire/amdtp.c

drivers/firewire/core-card.c

Diff comments View file @ 13882a8

 /*
  * Copyright (C) 2005-2007  Kristian Hoegsberg <krh@bitplanet.net>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software Foundation,
  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  */
 #include <linux/bug.h>
 #include <linux/completion.h>
 #include <linux/crc-itu-t.h>
 #include <linux/device.h>
 #include <linux/errno.h>
 #include <linux/firewire.h>
 #include <linux/firewire-constants.h>
 #include <linux/jiffies.h>
 #include <linux/kernel.h>
 #include <linux/kref.h>
 #include <linux/list.h>
 #include <linux/module.h>
 #include <linux/mutex.h>
 #include <linux/spinlock.h>
 #include <linux/workqueue.h>
 #include <asm/atomic.h>
 #include <asm/byteorder.h>
 #include "core.h"
 int fw_compute_block_crc(__be32 *block)
 {
 	int length;
 	u16 crc;
 	length = (be32_to_cpu(block[0]) >> 16) & 0xff;
 	crc = crc_itu_t(0, (u8 *)&block[1], length * 4);
 	*block |= cpu_to_be32(crc);
 	return length;
 }
 static DEFINE_MUTEX(card_mutex);
 static LIST_HEAD(card_list);
 static LIST_HEAD(descriptor_list);
 static int descriptor_count;
 static __be32 tmp_config_rom[256];
 /* ROM header, bus info block, root dir header, capabilities = 7 quadlets */
 static size_t config_rom_length = 1 + 4 + 1 + 1;
 #define BIB_CRC(v)		((v) <<  0)
 #define BIB_CRC_LENGTH(v)	((v) << 16)
 #define BIB_INFO_LENGTH(v)	((v) << 24)
 #define BIB_BUS_NAME		0x31333934 /* "1394" */
 #define BIB_LINK_SPEED(v)	((v) <<  0)
 #define BIB_GENERATION(v)	((v) <<  4)
 #define BIB_MAX_ROM(v)		((v) <<  8)
 #define BIB_MAX_RECEIVE(v)	((v) << 12)
 #define BIB_CYC_CLK_ACC(v)	((v) << 16)
 #define BIB_PMC			((1) << 27)
 #define BIB_BMC			((1) << 28)
 #define BIB_ISC			((1) << 29)
 #define BIB_CMC			((1) << 30)
 #define BIB_IRMC		((1) << 31)
 #define NODE_CAPABILITIES	0x0c0083c0 /* per IEEE 1394 clause 8.3.2.6.5.2 */
 /*
  * IEEE-1394 specifies a default SPLIT_TIMEOUT value of 800 cycles (100 ms),
  * but we have to make it longer because there are many devices whose firmware
  * is just too slow for that.
  */
 #define DEFAULT_SPLIT_TIMEOUT	(2 * 8000)
 #define CANON_OUI		0x000085
 static void generate_config_rom(struct fw_card *card, __be32 *config_rom)
 {
 	struct fw_descriptor *desc;
 	int i, j, k, length;
 	/*
 	 * Initialize contents of config rom buffer.  On the OHCI
 	 * controller, block reads to the config rom accesses the host
 	 * memory, but quadlet read access the hardware bus info block
 	 * registers.  That's just crack, but it means we should make
 	 * sure the contents of bus info block in host memory matches
 	 * the version stored in the OHCI registers.
 	 */
 	config_rom[0] = cpu_to_be32(
 		BIB_CRC_LENGTH(4) | BIB_INFO_LENGTH(4) | BIB_CRC(0));
 	config_rom[1] = cpu_to_be32(BIB_BUS_NAME);
 	config_rom[2] = cpu_to_be32(
 		BIB_LINK_SPEED(card->link_speed) |
 		BIB_GENERATION(card->config_rom_generation++ % 14 + 2) |
 		BIB_MAX_ROM(2) |
 		BIB_MAX_RECEIVE(card->max_receive) |
 		BIB_BMC | BIB_ISC | BIB_CMC | BIB_IRMC);
 	config_rom[3] = cpu_to_be32(card->guid >> 32);
 	config_rom[4] = cpu_to_be32(card->guid);
 	/* Generate root directory. */
 	config_rom[6] = cpu_to_be32(NODE_CAPABILITIES);
 	i = 7;
 	j = 7 + descriptor_count;
 	/* Generate root directory entries for descriptors. */
 	list_for_each_entry (desc, &descriptor_list, link) {
 		if (desc->immediate > 0)
 			config_rom[i++] = cpu_to_be32(desc->immediate);
 		config_rom[i] = cpu_to_be32(desc->key | (j - i));
 		i++;
 		j += desc->length;
 	}
 	/* Update root directory length. */
 	config_rom[5] = cpu_to_be32((i - 5 - 1) << 16);
 	/* End of root directory, now copy in descriptors. */
 	list_for_each_entry (desc, &descriptor_list, link) {
 		for (k = 0; k < desc->length; k++)
 			config_rom[i + k] = cpu_to_be32(desc->data[k]);
 		i += desc->length;
 	}
 	/* Calculate CRCs for all blocks in the config rom.  This
 	 * assumes that CRC length and info length are identical for
 	 * the bus info block, which is always the case for this
 	 * implementation. */
 	for (i = 0; i < j; i += length + 1)
 		length = fw_compute_block_crc(config_rom + i);
 	WARN_ON(j != config_rom_length);
 }
 static void update_config_roms(void)
 {
 	struct fw_card *card;
 	list_for_each_entry (card, &card_list, link) {
 		generate_config_rom(card, tmp_config_rom);
 		card->driver->set_config_rom(card, tmp_config_rom,
 					     config_rom_length);
 	}
 }
 static size_t required_space(struct fw_descriptor *desc)
 {
 	/* descriptor + entry into root dir + optional immediate entry */
 	return desc->length + 1 + (desc->immediate > 0 ? 1 : 0);
 }
 int fw_core_add_descriptor(struct fw_descriptor *desc)
 {
 	size_t i;
 	int ret;
 	/*
 	 * Check descriptor is valid; the length of all blocks in the
 	 * descriptor has to add up to exactly the length of the
 	 * block.
 	 */
 	i = 0;
 	while (i < desc->length)
 		i += (desc->data[i] >> 16) + 1;
 	if (i != desc->length)
 		return -EINVAL;
 	mutex_lock(&card_mutex);
 	if (config_rom_length + required_space(desc) > 256) {
 		ret = -EBUSY;
 	} else {
 		list_add_tail(&desc->link, &descriptor_list);
 		config_rom_length += required_space(desc);
 		descriptor_count++;
 		if (desc->immediate > 0)
 			descriptor_count++;
 		update_config_roms();
 		ret = 0;
 	}
 	mutex_unlock(&card_mutex);
 	return ret;
 }
 EXPORT_SYMBOL(fw_core_add_descriptor);
 void fw_core_remove_descriptor(struct fw_descriptor *desc)
 {
 	mutex_lock(&card_mutex);
 	list_del(&desc->link);
 	config_rom_length -= required_space(desc);
 	descriptor_count--;
 	if (desc->immediate > 0)
 		descriptor_count--;
 	update_config_roms();
 	mutex_unlock(&card_mutex);
 }
 EXPORT_SYMBOL(fw_core_remove_descriptor);
 static int reset_bus(struct fw_card *card, bool short_reset)
 {
 	int reg = short_reset ? 5 : 1;
 	int bit = short_reset ? PHY_BUS_SHORT_RESET : PHY_BUS_RESET;
 	return card->driver->update_phy_reg(card, reg, 0, bit);
 }
 void fw_schedule_bus_reset(struct fw_card *card, bool delayed, bool short_reset)
 {
 	/* We don't try hard to sort out requests of long vs. short resets. */
 	card->br_short = short_reset;
 	/* Use an arbitrary short delay to combine multiple reset requests. */
 	fw_card_get(card);
 	if (!schedule_delayed_work(&card->br_work,
 				   delayed ? DIV_ROUND_UP(HZ, 100) : 0))
 		fw_card_put(card);
 }
 EXPORT_SYMBOL(fw_schedule_bus_reset);
 static void br_work(struct work_struct *work)
 {
 	struct fw_card *card = container_of(work, struct fw_card, br_work.work);
 	/* Delay for 2s after last reset per IEEE 1394 clause 8.2.1. */
 	if (card->reset_jiffies != 0 &&
 	    time_before64(get_jiffies_64(), card->reset_jiffies + 2 * HZ)) {
 		if (!schedule_delayed_work(&card->br_work, 2 * HZ))
 			fw_card_put(card);
 		return;
 	}
 	fw_send_phy_config(card, FW_PHY_CONFIG_NO_NODE_ID, card->generation,
 			   FW_PHY_CONFIG_CURRENT_GAP_COUNT);
 	reset_bus(card, card->br_short);
 	fw_card_put(card);
 }
 static void allocate_broadcast_channel(struct fw_card *card, int generation)
 {
 	int channel, bandwidth = 0;
 	if (!card->broadcast_channel_allocated) {
 		fw_iso_resource_manage(card, generation, 1ULL << 31,
 				       &channel, &bandwidth, true);
 		if (channel != 31) {
 			fw_notify("failed to allocate broadcast channel\n");
 			return;
 		}
 		card->broadcast_channel_allocated = true;
 	}
 	device_for_each_child(card->device, (void *)(long)generation,
 			      fw_device_set_broadcast_channel);
 }
 static const char gap_count_table[] = {
 	63, 5, 7, 8, 10, 13, 16, 18, 21, 24, 26, 29, 32, 35, 37, 40
 };
 void fw_schedule_bm_work(struct fw_card *card, unsigned long delay)
 {
 	fw_card_get(card);
 	if (!schedule_delayed_work(&card->bm_work, delay))
 		fw_card_put(card);
 }
 static void bm_work(struct work_struct *work)
 {
 	struct fw_card *card = container_of(work, struct fw_card, bm_work.work);
 	struct fw_device *root_device, *irm_device;
 	struct fw_node *root_node;
 	int root_id, new_root_id, irm_id, bm_id, local_id;
 	int gap_count, generation, grace, rcode;
 	bool do_reset = false;
 	bool root_device_is_running;
 	bool root_device_is_cmc;
 	bool irm_is_1394_1995_only;
 	bool keep_this_irm;
 	__be32 transaction_data[2];
 	spin_lock_irq(&card->lock);
 	if (card->local_node == NULL) {
 		spin_unlock_irq(&card->lock);
 		goto out_put_card;
 	}
 	generation = card->generation;
 	root_node = card->root_node;
 	fw_node_get(root_node);
 	root_device = root_node->data;
 	root_device_is_running = root_device &&
 			atomic_read(&root_device->state) == FW_DEVICE_RUNNING;
 	root_device_is_cmc = root_device && root_device->cmc;
 	irm_device = card->irm_node->data;
 	irm_is_1394_1995_only = irm_device && irm_device->config_rom &&
 			(irm_device->config_rom[2] & 0x000000f0) == 0;
 	/* Canon MV5i works unreliably if it is not root node. */
 	keep_this_irm = irm_device && irm_device->config_rom &&
 			irm_device->config_rom[3] >> 8 == CANON_OUI;
 	root_id  = root_node->node_id;
 	irm_id   = card->irm_node->node_id;
 	local_id = card->local_node->node_id;
 	grace = time_after64(get_jiffies_64(),
 			     card->reset_jiffies + DIV_ROUND_UP(HZ, 8));
 	if ((is_next_generation(generation, card->bm_generation) &&
 	     !card->bm_abdicate) ||
 	    (card->bm_generation != generation && grace)) {
 		/*
 		 * This first step is to figure out who is IRM and
 		 * then try to become bus manager.  If the IRM is not
 		 * well defined (e.g. does not have an active link
 		 * layer or does not responds to our lock request, we
 		 * will have to do a little vigilante bus management.
 		 * In that case, we do a goto into the gap count logic
 		 * so that when we do the reset, we still optimize the
 		 * gap count.  That could well save a reset in the
 		 * next generation.
 		 */
 		if (!card->irm_node->link_on) {
 			new_root_id = local_id;
 			fw_notify("%s, making local node (%02x) root.\n",
 				  "IRM has link off", new_root_id);
 			goto pick_me;
 		}
 		if (irm_is_1394_1995_only && !keep_this_irm) {
 			new_root_id = local_id;
 			fw_notify("%s, making local node (%02x) root.\n",
 				  "IRM is not 1394a compliant", new_root_id);
 			goto pick_me;
 		}
 		transaction_data[0] = cpu_to_be32(0x3f);
 		transaction_data[1] = cpu_to_be32(local_id);
 		spin_unlock_irq(&card->lock);
 		rcode = fw_run_transaction(card, TCODE_LOCK_COMPARE_SWAP,
 				irm_id, generation, SCODE_100,
 				CSR_REGISTER_BASE + CSR_BUS_MANAGER_ID,
 				transaction_data, 8);
 		if (rcode == RCODE_GENERATION)
 			/* Another bus reset, BM work has been rescheduled. */
 			goto out;
 		bm_id = be32_to_cpu(transaction_data[0]);
 		spin_lock_irq(&card->lock);
 		if (rcode == RCODE_COMPLETE && generation == card->generation)
 			card->bm_node_id =
 			    bm_id == 0x3f ? local_id : 0xffc0 | bm_id;
 		spin_unlock_irq(&card->lock);
 		if (rcode == RCODE_COMPLETE && bm_id != 0x3f) {
 			/* Somebody else is BM.  Only act as IRM. */
 			if (local_id == irm_id)
 				allocate_broadcast_channel(card, generation);
 			goto out;
 		}
 		if (rcode == RCODE_SEND_ERROR) {
 			/*
 			 * We have been unable to send the lock request due to
 			 * some local problem.  Let's try again later and hope
 			 * that the problem has gone away by then.
 			 */
 			fw_schedule_bm_work(card, DIV_ROUND_UP(HZ, 8));
 			goto out;
 		}
 		spin_lock_irq(&card->lock);
 		if (rcode != RCODE_COMPLETE && !keep_this_irm) {
 			/*
 			 * The lock request failed, maybe the IRM
 			 * isn't really IRM capable after all. Let's
 			 * do a bus reset and pick the local node as
 			 * root, and thus, IRM.
 			 */
 			new_root_id = local_id;
 			fw_notify("%s, making local node (%02x) root.\n",
 				  "BM lock failed", new_root_id);
 			goto pick_me;
 		}
 	} else if (card->bm_generation != generation) {
 		/*
 		 * We weren't BM in the last generation, and the last
 		 * bus reset is less than 125ms ago.  Reschedule this job.
 		 */
 		spin_unlock_irq(&card->lock);
 		fw_schedule_bm_work(card, DIV_ROUND_UP(HZ, 8));
 		goto out;
 	}
 	/*
 	 * We're bus manager for this generation, so next step is to
 	 * make sure we have an active cycle master and do gap count
 	 * optimization.
 	 */
 	card->bm_generation = generation;
 	if (root_device == NULL) {
 		/*
 		 * Either link_on is false, or we failed to read the
 		 * config rom.  In either case, pick another root.
 		 */
 		new_root_id = local_id;
 	} else if (!root_device_is_running) {
 		/*
 		 * If we haven't probed this device yet, bail out now
 		 * and let's try again once that's done.
 		 */
 		spin_unlock_irq(&card->lock);
 		goto out;
 	} else if (root_device_is_cmc) {
 		/*
 		 * We will send out a force root packet for this
 		 * node as part of the gap count optimization.
 		 */
 		new_root_id = root_id;
 	} else {
 		/*
 		 * Current root has an active link layer and we
 		 * successfully read the config rom, but it's not
 		 * cycle master capable.
 		 */
 		new_root_id = local_id;
 	}
  pick_me:
 	/*
 	 * Pick a gap count from 1394a table E-1.  The table doesn't cover
 	 * the typically much larger 1394b beta repeater delays though.
 	 */
 	if (!card->beta_repeaters_present &&
 	    root_node->max_hops < ARRAY_SIZE(gap_count_table))
 		gap_count = gap_count_table[root_node->max_hops];
 	else
 		gap_count = 63;
 	/*
 	 * Finally, figure out if we should do a reset or not.  If we have
 	 * done less than 5 resets with the same physical topology and we
 	 * have either a new root or a new gap count setting, let's do it.
 	 */
 	if (card->bm_retries++ < 5 &&
 	    (card->gap_count != gap_count || new_root_id != root_id))
 		do_reset = true;
 	spin_unlock_irq(&card->lock);
 	if (do_reset) {
 		fw_notify("phy config: card %d, new root=%x, gap_count=%d\n",
 			  card->index, new_root_id, gap_count);
 		fw_send_phy_config(card, new_root_id, generation, gap_count);
 		reset_bus(card, true);
 		/* Will allocate broadcast channel after the reset. */
 		goto out;
 	}
 	if (root_device_is_cmc) {
 		/*
 		 * Make sure that the cycle master sends cycle start packets.
 		 */
 		transaction_data[0] = cpu_to_be32(CSR_STATE_BIT_CMSTR);
 		rcode = fw_run_transaction(card, TCODE_WRITE_QUADLET_REQUEST,
 				root_id, generation, SCODE_100,
 				CSR_REGISTER_BASE + CSR_STATE_SET,
 				transaction_data, 4);
 		if (rcode == RCODE_GENERATION)
 			goto out;
 	}
 	if (local_id == irm_id)
 		allocate_broadcast_channel(card, generation);
  out:
 	fw_node_put(root_node);
  out_put_card:
 	fw_card_put(card);
 }
 void fw_card_initialize(struct fw_card *card,
 			const struct fw_card_driver *driver,
 			struct device *device)
 {
 	static atomic_t index = ATOMIC_INIT(-1);
 	card->index = atomic_inc_return(&index);
 	card->driver = driver;
 	card->device = device;
 	card->current_tlabel = 0;
 	card->tlabel_mask = 0;
 	card->split_timeout_hi = DEFAULT_SPLIT_TIMEOUT / 8000;
 	card->split_timeout_lo = (DEFAULT_SPLIT_TIMEOUT % 8000) << 19;
 	card->split_timeout_cycles = DEFAULT_SPLIT_TIMEOUT;
 	card->split_timeout_jiffies =
 			DIV_ROUND_UP(DEFAULT_SPLIT_TIMEOUT * HZ, 8000);
 	card->color = 0;
 	card->broadcast_channel = BROADCAST_CHANNEL_INITIAL;
 	kref_init(&card->kref);
 	init_completion(&card->done);
 	INIT_LIST_HEAD(&card->transaction_list);
 	INIT_LIST_HEAD(&card->phy_receiver_list);
 	spin_lock_init(&card->lock);
 	card->local_node = NULL;
 	INIT_DELAYED_WORK(&card->br_work, br_work);
 	INIT_DELAYED_WORK(&card->bm_work, bm_work);
 }
 EXPORT_SYMBOL(fw_card_initialize);
 int fw_card_add(struct fw_card *card,
 		u32 max_receive, u32 link_speed, u64 guid)
 {
 	int ret;
 	card->max_receive = max_receive;
 	card->link_speed = link_speed;
 	card->guid = guid;
 	mutex_lock(&card_mutex);
 	generate_config_rom(card, tmp_config_rom);
 	ret = card->driver->enable(card, tmp_config_rom, config_rom_length);
 	if (ret == 0)
 		list_add_tail(&card->link, &card_list);
 	mutex_unlock(&card_mutex);
 	return ret;
 }
 EXPORT_SYMBOL(fw_card_add);
 /*
  * The next few functions implement a dummy driver that is used once a card
  * driver shuts down an fw_card.  This allows the driver to cleanly unload,
  * as all IO to the card will be handled (and failed) by the dummy driver
  * instead of calling into the module.  Only functions for iso context
  * shutdown still need to be provided by the card driver.
  *
  * .read/write_csr() should never be called anymore after the dummy driver
  * was bound since they are only used within request handler context.
  * .set_config_rom() is never called since the card is taken out of card_list
  * before switching to the dummy driver.
  */
 static int dummy_read_phy_reg(struct fw_card *card, int address)
 {
 	return -ENODEV;
 }
 static int dummy_update_phy_reg(struct fw_card *card, int address,
 				int clear_bits, int set_bits)
 {
 	return -ENODEV;
 }
 static void dummy_send_request(struct fw_card *card, struct fw_packet *packet)
 {
 	packet->callback(packet, card, RCODE_CANCELLED);
 }
 static void dummy_send_response(struct fw_card *card, struct fw_packet *packet)
 {
 	packet->callback(packet, card, RCODE_CANCELLED);
 }
 static int dummy_cancel_packet(struct fw_card *card, struct fw_packet *packet)
 {
 	return -ENOENT;
 }
 static int dummy_enable_phys_dma(struct fw_card *card,
 				 int node_id, int generation)
 {
 	return -ENODEV;
 }
 static struct fw_iso_context *dummy_allocate_iso_context(struct fw_card *card,
 				int type, int channel, size_t header_size)
 {
 	return ERR_PTR(-ENODEV);
 }
 static int dummy_start_iso(struct fw_iso_context *ctx,
 			   s32 cycle, u32 sync, u32 tags)
 {
 	return -ENODEV;
 }
 static int dummy_set_iso_channels(struct fw_iso_context *ctx, u64 *channels)
 {
 	return -ENODEV;
 }
 static int dummy_queue_iso(struct fw_iso_context *ctx, struct fw_iso_packet *p,
 			   struct fw_iso_buffer *buffer, unsigned long payload)
 {
 	return -ENODEV;
 }
+static void dummy_flush_queue_iso(struct fw_iso_context *ctx)
+{
+}
 static const struct fw_card_driver dummy_driver_template = {
 	.read_phy_reg		= dummy_read_phy_reg,
 	.update_phy_reg		= dummy_update_phy_reg,
 	.send_request		= dummy_send_request,
 	.send_response		= dummy_send_response,
 	.cancel_packet		= dummy_cancel_packet,
 	.enable_phys_dma	= dummy_enable_phys_dma,
 	.allocate_iso_context	= dummy_allocate_iso_context,
 	.start_iso		= dummy_start_iso,
 	.set_iso_channels	= dummy_set_iso_channels,
 	.queue_iso		= dummy_queue_iso,
+	.flush_queue_iso	= dummy_flush_queue_iso,
 };
 void fw_card_release(struct kref *kref)
 {
 	struct fw_card *card = container_of(kref, struct fw_card, kref);
 	complete(&card->done);
 }
 void fw_core_remove_card(struct fw_card *card)
 {
 	struct fw_card_driver dummy_driver = dummy_driver_template;
 	card->driver->update_phy_reg(card, 4,
 				     PHY_LINK_ACTIVE | PHY_CONTENDER, 0);
 	fw_schedule_bus_reset(card, false, true);
 	mutex_lock(&card_mutex);
 	list_del_init(&card->link);
 	mutex_unlock(&card_mutex);
 	/* Switch off most of the card driver interface. */
 	dummy_driver.free_iso_context	= card->driver->free_iso_context;
 	dummy_driver.stop_iso		= card->driver->stop_iso;
 	card->driver = &dummy_driver;
 	fw_destroy_nodes(card);
 	/* Wait for all users, especially device workqueue jobs, to finish. */
 	fw_card_put(card);
 	wait_for_completion(&card->done);
 	WARN_ON(!list_empty(&card->transaction_list));
 }
 EXPORT_SYMBOL(fw_core_remove_card);

drivers/firewire/core-cdev.c

Diff comments View file @ 13882a8

 /*
  * Char device for device raw access
  *
  * Copyright (C) 2005-2007  Kristian Hoegsberg <krh@bitplanet.net>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software Foundation,
  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  */
 #include <linux/bug.h>
 #include <linux/compat.h>
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/errno.h>
 #include <linux/firewire.h>
 #include <linux/firewire-cdev.h>
 #include <linux/idr.h>
 #include <linux/irqflags.h>
 #include <linux/jiffies.h>
 #include <linux/kernel.h>
 #include <linux/kref.h>
 #include <linux/mm.h>
 #include <linux/module.h>
 #include <linux/mutex.h>
 #include <linux/poll.h>
 #include <linux/sched.h> /* required for linux/wait.h */
 #include <linux/slab.h>
 #include <linux/spinlock.h>
 #include <linux/string.h>
 #include <linux/time.h>
 #include <linux/uaccess.h>
 #include <linux/vmalloc.h>
 #include <linux/wait.h>
 #include <linux/workqueue.h>
 #include <asm/system.h>
 #include "core.h"
 /*
  * ABI version history is documented in linux/firewire-cdev.h.
  */
 #define FW_CDEV_KERNEL_VERSION			4
 #define FW_CDEV_VERSION_EVENT_REQUEST2		4
 #define FW_CDEV_VERSION_ALLOCATE_REGION_END	4
 struct client {
 	u32 version;
 	struct fw_device *device;
 	spinlock_t lock;
 	bool in_shutdown;
 	struct idr resource_idr;
 	struct list_head event_list;
 	wait_queue_head_t wait;
 	wait_queue_head_t tx_flush_wait;
 	u64 bus_reset_closure;
 	struct fw_iso_context *iso_context;
 	u64 iso_closure;
 	struct fw_iso_buffer buffer;
 	unsigned long vm_start;
 	struct list_head phy_receiver_link;
 	u64 phy_receiver_closure;
 	struct list_head link;
 	struct kref kref;
 };
 static inline void client_get(struct client *client)
 {
 	kref_get(&client->kref);
 }
 static void client_release(struct kref *kref)
 {
 	struct client *client = container_of(kref, struct client, kref);
 	fw_device_put(client->device);
 	kfree(client);
 }
 static void client_put(struct client *client)
 {
 	kref_put(&client->kref, client_release);
 }
 struct client_resource;
 typedef void (*client_resource_release_fn_t)(struct client *,
 					     struct client_resource *);
 struct client_resource {
 	client_resource_release_fn_t release;
 	int handle;
 };
 struct address_handler_resource {
 	struct client_resource resource;
 	struct fw_address_handler handler;
 	__u64 closure;
 	struct client *client;
 };
 struct outbound_transaction_resource {
 	struct client_resource resource;
 	struct fw_transaction transaction;
 };
 struct inbound_transaction_resource {
 	struct client_resource resource;
 	struct fw_card *card;
 	struct fw_request *request;
 	void *data;
 	size_t length;
 };
 struct descriptor_resource {
 	struct client_resource resource;
 	struct fw_descriptor descriptor;
 	u32 data[0];
 };
 struct iso_resource {
 	struct client_resource resource;
 	struct client *client;
 	/* Schedule work and access todo only with client->lock held. */
 	struct delayed_work work;
 	enum {ISO_RES_ALLOC, ISO_RES_REALLOC, ISO_RES_DEALLOC,
 	      ISO_RES_ALLOC_ONCE, ISO_RES_DEALLOC_ONCE,} todo;
 	int generation;
 	u64 channels;
 	s32 bandwidth;
 	struct iso_resource_event *e_alloc, *e_dealloc;
 };
 static void release_iso_resource(struct client *, struct client_resource *);
 static void schedule_iso_resource(struct iso_resource *r, unsigned long delay)
 {
 	client_get(r->client);
 	if (!schedule_delayed_work(&r->work, delay))
 		client_put(r->client);
 }
 static void schedule_if_iso_resource(struct client_resource *resource)
 {
 	if (resource->release == release_iso_resource)
 		schedule_iso_resource(container_of(resource,
 					struct iso_resource, resource), 0);
 }
 /*
  * dequeue_event() just kfree()'s the event, so the event has to be
  * the first field in a struct XYZ_event.
  */
 struct event {
 	struct { void *data; size_t size; } v[2];
 	struct list_head link;
 };
 struct bus_reset_event {
 	struct event event;
 	struct fw_cdev_event_bus_reset reset;
 };
 struct outbound_transaction_event {
 	struct event event;
 	struct client *client;
 	struct outbound_transaction_resource r;
 	struct fw_cdev_event_response response;
 };
 struct inbound_transaction_event {
 	struct event event;
 	union {
 		struct fw_cdev_event_request request;
 		struct fw_cdev_event_request2 request2;
 	} req;
 };
 struct iso_interrupt_event {
 	struct event event;
 	struct fw_cdev_event_iso_interrupt interrupt;
 };
 struct iso_interrupt_mc_event {
 	struct event event;
 	struct fw_cdev_event_iso_interrupt_mc interrupt;
 };
 struct iso_resource_event {
 	struct event event;
 	struct fw_cdev_event_iso_resource iso_resource;
 };
 struct outbound_phy_packet_event {
 	struct event event;
 	struct client *client;
 	struct fw_packet p;
 	struct fw_cdev_event_phy_packet phy_packet;
 };
 struct inbound_phy_packet_event {
 	struct event event;
 	struct fw_cdev_event_phy_packet phy_packet;
 };
 static inline void __user *u64_to_uptr(__u64 value)
 {
 	return (void __user *)(unsigned long)value;
 }
 static inline __u64 uptr_to_u64(void __user *ptr)
 {
 	return (__u64)(unsigned long)ptr;
 }
 static int fw_device_op_open(struct inode *inode, struct file *file)
 {
 	struct fw_device *device;
 	struct client *client;
 	device = fw_device_get_by_devt(inode->i_rdev);
 	if (device == NULL)
 		return -ENODEV;
 	if (fw_device_is_shutdown(device)) {
 		fw_device_put(device);
 		return -ENODEV;
 	}
 	client = kzalloc(sizeof(*client), GFP_KERNEL);
 	if (client == NULL) {
 		fw_device_put(device);
 		return -ENOMEM;
 	}
 	client->device = device;
 	spin_lock_init(&client->lock);
 	idr_init(&client->resource_idr);
 	INIT_LIST_HEAD(&client->event_list);
 	init_waitqueue_head(&client->wait);
 	init_waitqueue_head(&client->tx_flush_wait);
 	INIT_LIST_HEAD(&client->phy_receiver_link);
 	kref_init(&client->kref);
 	file->private_data = client;
 	mutex_lock(&device->client_list_mutex);
 	list_add_tail(&client->link, &device->client_list);
 	mutex_unlock(&device->client_list_mutex);
 	return nonseekable_open(inode, file);
 }
 static void queue_event(struct client *client, struct event *event,
 			void *data0, size_t size0, void *data1, size_t size1)
 {
 	unsigned long flags;
 	event->v[0].data = data0;
 	event->v[0].size = size0;
 	event->v[1].data = data1;
 	event->v[1].size = size1;
 	spin_lock_irqsave(&client->lock, flags);
 	if (client->in_shutdown)
 		kfree(event);
 	else
 		list_add_tail(&event->link, &client->event_list);
 	spin_unlock_irqrestore(&client->lock, flags);
 	wake_up_interruptible(&client->wait);
 }
 static int dequeue_event(struct client *client,
 			 char __user *buffer, size_t count)
 {
 	struct event *event;
 	size_t size, total;
 	int i, ret;
 	ret = wait_event_interruptible(client->wait,
 			!list_empty(&client->event_list) ||
 			fw_device_is_shutdown(client->device));
 	if (ret < 0)
 		return ret;
 	if (list_empty(&client->event_list) &&
 		       fw_device_is_shutdown(client->device))
 		return -ENODEV;
 	spin_lock_irq(&client->lock);
 	event = list_first_entry(&client->event_list, struct event, link);
 	list_del(&event->link);
 	spin_unlock_irq(&client->lock);
 	total = 0;
 	for (i = 0; i < ARRAY_SIZE(event->v) && total < count; i++) {
 		size = min(event->v[i].size, count - total);
 		if (copy_to_user(buffer + total, event->v[i].data, size)) {
 			ret = -EFAULT;
 			goto out;
 		}
 		total += size;
 	}
 	ret = total;
  out:
 	kfree(event);
 	return ret;
 }
 static ssize_t fw_device_op_read(struct file *file, char __user *buffer,
 				 size_t count, loff_t *offset)
 {
 	struct client *client = file->private_data;
 	return dequeue_event(client, buffer, count);
 }
 static void fill_bus_reset_event(struct fw_cdev_event_bus_reset *event,
 				 struct client *client)
 {
 	struct fw_card *card = client->device->card;
 	spin_lock_irq(&card->lock);
 	event->closure	     = client->bus_reset_closure;
 	event->type          = FW_CDEV_EVENT_BUS_RESET;
 	event->generation    = client->device->generation;
 	event->node_id       = client->device->node_id;
 	event->local_node_id = card->local_node->node_id;
 	event->bm_node_id    = card->bm_node_id;
 	event->irm_node_id   = card->irm_node->node_id;
 	event->root_node_id  = card->root_node->node_id;
 	spin_unlock_irq(&card->lock);
 }
 static void for_each_client(struct fw_device *device,
 			    void (*callback)(struct client *client))
 {
 	struct client *c;
 	mutex_lock(&device->client_list_mutex);
 	list_for_each_entry(c, &device->client_list, link)
 		callback(c);
 	mutex_unlock(&device->client_list_mutex);
 }
 static int schedule_reallocations(int id, void *p, void *data)
 {
 	schedule_if_iso_resource(p);
 	return 0;
 }
 static void queue_bus_reset_event(struct client *client)
 {
 	struct bus_reset_event *e;
 	e = kzalloc(sizeof(*e), GFP_KERNEL);
 	if (e == NULL) {
 		fw_notify("Out of memory when allocating event\n");
 		return;
 	}
 	fill_bus_reset_event(&e->reset, client);
 	queue_event(client, &e->event,
 		    &e->reset, sizeof(e->reset), NULL, 0);
 	spin_lock_irq(&client->lock);
 	idr_for_each(&client->resource_idr, schedule_reallocations, client);
 	spin_unlock_irq(&client->lock);
 }
 void fw_device_cdev_update(struct fw_device *device)
 {
 	for_each_client(device, queue_bus_reset_event);
 }
 static void wake_up_client(struct client *client)
 {
 	wake_up_interruptible(&client->wait);
 }
 void fw_device_cdev_remove(struct fw_device *device)
 {
 	for_each_client(device, wake_up_client);
 }
 union ioctl_arg {
 	struct fw_cdev_get_info			get_info;
 	struct fw_cdev_send_request		send_request;
 	struct fw_cdev_allocate			allocate;
 	struct fw_cdev_deallocate		deallocate;
 	struct fw_cdev_send_response		send_response;
 	struct fw_cdev_initiate_bus_reset	initiate_bus_reset;
 	struct fw_cdev_add_descriptor		add_descriptor;
 	struct fw_cdev_remove_descriptor	remove_descriptor;
 	struct fw_cdev_create_iso_context	create_iso_context;
 	struct fw_cdev_queue_iso		queue_iso;
 	struct fw_cdev_start_iso		start_iso;
 	struct fw_cdev_stop_iso			stop_iso;
 	struct fw_cdev_get_cycle_timer		get_cycle_timer;
 	struct fw_cdev_allocate_iso_resource	allocate_iso_resource;
 	struct fw_cdev_send_stream_packet	send_stream_packet;
 	struct fw_cdev_get_cycle_timer2		get_cycle_timer2;
 	struct fw_cdev_send_phy_packet		send_phy_packet;
 	struct fw_cdev_receive_phy_packets	receive_phy_packets;
 	struct fw_cdev_set_iso_channels		set_iso_channels;
 };
 static int ioctl_get_info(struct client *client, union ioctl_arg *arg)
 {
 	struct fw_cdev_get_info *a = &arg->get_info;
 	struct fw_cdev_event_bus_reset bus_reset;
 	unsigned long ret = 0;
 	client->version = a->version;
 	a->version = FW_CDEV_KERNEL_VERSION;
 	a->card = client->device->card->index;
 	down_read(&fw_device_rwsem);
 	if (a->rom != 0) {
 		size_t want = a->rom_length;
 		size_t have = client->device->config_rom_length * 4;
 		ret = copy_to_user(u64_to_uptr(a->rom),
 				   client->device->config_rom, min(want, have));
 	}
 	a->rom_length = client->device->config_rom_length * 4;
 	up_read(&fw_device_rwsem);
 	if (ret != 0)
 		return -EFAULT;
 	client->bus_reset_closure = a->bus_reset_closure;
 	if (a->bus_reset != 0) {
 		fill_bus_reset_event(&bus_reset, client);
 		if (copy_to_user(u64_to_uptr(a->bus_reset),
 				 &bus_reset, sizeof(bus_reset)))
 			return -EFAULT;
 	}
 	return 0;
 }
 static int add_client_resource(struct client *client,
 			       struct client_resource *resource, gfp_t gfp_mask)
 {
 	unsigned long flags;
 	int ret;
  retry:
 	if (idr_pre_get(&client->resource_idr, gfp_mask) == 0)
 		return -ENOMEM;
 	spin_lock_irqsave(&client->lock, flags);
 	if (client->in_shutdown)
 		ret = -ECANCELED;
 	else
 		ret = idr_get_new(&client->resource_idr, resource,
 				  &resource->handle);
 	if (ret >= 0) {
 		client_get(client);
 		schedule_if_iso_resource(resource);
 	}
 	spin_unlock_irqrestore(&client->lock, flags);
 	if (ret == -EAGAIN)
 		goto retry;
 	return ret < 0 ? ret : 0;
 }
 static int release_client_resource(struct client *client, u32 handle,
 				   client_resource_release_fn_t release,
 				   struct client_resource **return_resource)
 {
 	struct client_resource *resource;
 	spin_lock_irq(&client->lock);
 	if (client->in_shutdown)
 		resource = NULL;
 	else
 		resource = idr_find(&client->resource_idr, handle);
 	if (resource && resource->release == release)
 		idr_remove(&client->resource_idr, handle);
 	spin_unlock_irq(&client->lock);
 	if (!(resource && resource->release == release))
 		return -EINVAL;
 	if (return_resource)
 		*return_resource = resource;
 	else
 		resource->release(client, resource);
 	client_put(client);
 	return 0;
 }
 static void release_transaction(struct client *client,
 				struct client_resource *resource)
 {
 }
 static void complete_transaction(struct fw_card *card, int rcode,
 				 void *payload, size_t length, void *data)
 {
 	struct outbound_transaction_event *e = data;
 	struct fw_cdev_event_response *rsp = &e->response;
 	struct client *client = e->client;
 	unsigned long flags;
 	if (length < rsp->length)
 		rsp->length = length;
 	if (rcode == RCODE_COMPLETE)
 		memcpy(rsp->data, payload, rsp->length);
 	spin_lock_irqsave(&client->lock, flags);
 	idr_remove(&client->resource_idr, e->r.resource.handle);
 	if (client->in_shutdown)
 		wake_up(&client->tx_flush_wait);
 	spin_unlock_irqrestore(&client->lock, flags);
 	rsp->type = FW_CDEV_EVENT_RESPONSE;
 	rsp->rcode = rcode;
 	/*
 	 * In the case that sizeof(*rsp) doesn't align with the position of the
 	 * data, and the read is short, preserve an extra copy of the data
 	 * to stay compatible with a pre-2.6.27 bug.  Since the bug is harmless
 	 * for short reads and some apps depended on it, this is both safe
 	 * and prudent for compatibility.
 	 */
 	if (rsp->length <= sizeof(*rsp) - offsetof(typeof(*rsp), data))
 		queue_event(client, &e->event, rsp, sizeof(*rsp),
 			    rsp->data, rsp->length);
 	else
 		queue_event(client, &e->event, rsp, sizeof(*rsp) + rsp->length,
 			    NULL, 0);
 	/* Drop the idr's reference */
 	client_put(client);
 }
 static int init_request(struct client *client,
 			struct fw_cdev_send_request *request,
 			int destination_id, int speed)
 {
 	struct outbound_transaction_event *e;
 	int ret;
 	if (request->tcode != TCODE_STREAM_DATA &&
 	    (request->length > 4096 || request->length > 512 << speed))
 		return -EIO;
 	if (request->tcode == TCODE_WRITE_QUADLET_REQUEST &&
 	    request->length < 4)
 		return -EINVAL;
 	e = kmalloc(sizeof(*e) + request->length, GFP_KERNEL);
 	if (e == NULL)
 		return -ENOMEM;
 	e->client = client;
 	e->response.length = request->length;
 	e->response.closure = request->closure;
 	if (request->data &&
 	    copy_from_user(e->response.data,
 			   u64_to_uptr(request->data), request->length)) {
 		ret = -EFAULT;
 		goto failed;
 	}
 	e->r.resource.release = release_transaction;
 	ret = add_client_resource(client, &e->r.resource, GFP_KERNEL);
 	if (ret < 0)
 		goto failed;
 	fw_send_request(client->device->card, &e->r.transaction,
 			request->tcode, destination_id, request->generation,
 			speed, request->offset, e->response.data,
 			request->length, complete_transaction, e);
 	return 0;
  failed:
 	kfree(e);
 	return ret;
 }
 static int ioctl_send_request(struct client *client, union ioctl_arg *arg)
 {
 	switch (arg->send_request.tcode) {
 	case TCODE_WRITE_QUADLET_REQUEST:
 	case TCODE_WRITE_BLOCK_REQUEST:
 	case TCODE_READ_QUADLET_REQUEST:
 	case TCODE_READ_BLOCK_REQUEST:
 	case TCODE_LOCK_MASK_SWAP:
 	case TCODE_LOCK_COMPARE_SWAP:
 	case TCODE_LOCK_FETCH_ADD:
 	case TCODE_LOCK_LITTLE_ADD:
 	case TCODE_LOCK_BOUNDED_ADD:
 	case TCODE_LOCK_WRAP_ADD:
 	case TCODE_LOCK_VENDOR_DEPENDENT:
 		break;
 	default:
 		return -EINVAL;
 	}
 	return init_request(client, &arg->send_request, client->device->node_id,
 			    client->device->max_speed);
 }
 static inline bool is_fcp_request(struct fw_request *request)
 {
 	return request == NULL;
 }
 static void release_request(struct client *client,
 			    struct client_resource *resource)
 {
 	struct inbound_transaction_resource *r = container_of(resource,
 			struct inbound_transaction_resource, resource);
 	if (is_fcp_request(r->request))
 		kfree(r->data);
 	else
 		fw_send_response(r->card, r->request, RCODE_CONFLICT_ERROR);
 	fw_card_put(r->card);
 	kfree(r);
 }
 static void handle_request(struct fw_card *card, struct fw_request *request,
 			   int tcode, int destination, int source,
 			   int generation, unsigned long long offset,
 			   void *payload, size_t length, void *callback_data)
 {
 	struct address_handler_resource *handler = callback_data;
 	struct inbound_transaction_resource *r;
 	struct inbound_transaction_event *e;
 	size_t event_size0;
 	void *fcp_frame = NULL;
 	int ret;
 	/* card may be different from handler->client->device->card */
 	fw_card_get(card);
 	r = kmalloc(sizeof(*r), GFP_ATOMIC);
 	e = kmalloc(sizeof(*e), GFP_ATOMIC);
 	if (r == NULL || e == NULL) {
 		fw_notify("Out of memory when allocating event\n");
 		goto failed;
 	}
 	r->card    = card;
 	r->request = request;
 	r->data    = payload;
 	r->length  = length;
 	if (is_fcp_request(request)) {
 		/*
 		 * FIXME: Let core-transaction.c manage a
 		 * single reference-counted copy?
 		 */
 		fcp_frame = kmemdup(payload, length, GFP_ATOMIC);
 		if (fcp_frame == NULL)
 			goto failed;
 		r->data = fcp_frame;
 	}
 	r->resource.release = release_request;
 	ret = add_client_resource(handler->client, &r->resource, GFP_ATOMIC);
 	if (ret < 0)
 		goto failed;
 	if (handler->client->version < FW_CDEV_VERSION_EVENT_REQUEST2) {
 		struct fw_cdev_event_request *req = &e->req.request;
 		if (tcode & 0x10)
 			tcode = TCODE_LOCK_REQUEST;
 		req->type	= FW_CDEV_EVENT_REQUEST;
 		req->tcode	= tcode;
 		req->offset	= offset;
 		req->length	= length;
 		req->handle	= r->resource.handle;
 		req->closure	= handler->closure;
 		event_size0	= sizeof(*req);
 	} else {
 		struct fw_cdev_event_request2 *req = &e->req.request2;
 		req->type	= FW_CDEV_EVENT_REQUEST2;
 		req->tcode	= tcode;
 		req->offset	= offset;
 		req->source_node_id = source;
 		req->destination_node_id = destination;
 		req->card	= card->index;
 		req->generation	= generation;
 		req->length	= length;
 		req->handle	= r->resource.handle;
 		req->closure	= handler->closure;
 		event_size0	= sizeof(*req);
 	}
 	queue_event(handler->client, &e->event,
 		    &e->req, event_size0, r->data, length);
 	return;
  failed:
 	kfree(r);
 	kfree(e);
 	kfree(fcp_frame);
 	if (!is_fcp_request(request))
 		fw_send_response(card, request, RCODE_CONFLICT_ERROR);
 	fw_card_put(card);
 }
 static void release_address_handler(struct client *client,
 				    struct client_resource *resource)
 {
 	struct address_handler_resource *r =
 	    container_of(resource, struct address_handler_resource, resource);
 	fw_core_remove_address_handler(&r->handler);
 	kfree(r);
 }
 static int ioctl_allocate(struct client *client, union ioctl_arg *arg)
 {
 	struct fw_cdev_allocate *a = &arg->allocate;
 	struct address_handler_resource *r;
 	struct fw_address_region region;
 	int ret;
 	r = kmalloc(sizeof(*r), GFP_KERNEL);
 	if (r == NULL)
 		return -ENOMEM;
 	region.start = a->offset;
 	if (client->version < FW_CDEV_VERSION_ALLOCATE_REGION_END)
 		region.end = a->offset + a->length;
 	else
 		region.end = a->region_end;
 	r->handler.length           = a->length;
 	r->handler.address_callback = handle_request;
 	r->handler.callback_data    = r;
 	r->closure   = a->closure;
 	r->client    = client;
 	ret = fw_core_add_address_handler(&r->handler, &region);
 	if (ret < 0) {
 		kfree(r);
 		return ret;
 	}
 	a->offset = r->handler.offset;
 	r->resource.release = release_address_handler;
 	ret = add_client_resource(client, &r->resource, GFP_KERNEL);
 	if (ret < 0) {
 		release_address_handler(client, &r->resource);
 		return ret;
 	}
 	a->handle = r->resource.handle;
 	return 0;
 }
 static int ioctl_deallocate(struct client *client, union ioctl_arg *arg)
 {
 	return release_client_resource(client, arg->deallocate.handle,
 				       release_address_handler, NULL);
 }
 static int ioctl_send_response(struct client *client, union ioctl_arg *arg)
 {
 	struct fw_cdev_send_response *a = &arg->send_response;
 	struct client_resource *resource;
 	struct inbound_transaction_resource *r;
 	int ret = 0;
 	if (release_client_resource(client, a->handle,
 				    release_request, &resource) < 0)
 		return -EINVAL;
 	r = container_of(resource, struct inbound_transaction_resource,
 			 resource);
 	if (is_fcp_request(r->request))
 		goto out;
 	if (a->length != fw_get_response_length(r->request)) {
 		ret = -EINVAL;
 		kfree(r->request);
 		goto out;
 	}
 	if (copy_from_user(r->data, u64_to_uptr(a->data), a->length)) {
 		ret = -EFAULT;
 		kfree(r->request);
 		goto out;
 	}
 	fw_send_response(r->card, r->request, a->rcode);
  out:
 	fw_card_put(r->card);
 	kfree(r);
 	return ret;
 }
 static int ioctl_initiate_bus_reset(struct client *client, union ioctl_arg *arg)
 {
 	fw_schedule_bus_reset(client->device->card, true,
 			arg->initiate_bus_reset.type == FW_CDEV_SHORT_RESET);
 	return 0;
 }
 static void release_descriptor(struct client *client,
 			       struct client_resource *resource)
 {
 	struct descriptor_resource *r =
 		container_of(resource, struct descriptor_resource, resource);
 	fw_core_remove_descriptor(&r->descriptor);
 	kfree(r);
 }
 static int ioctl_add_descriptor(struct client *client, union ioctl_arg *arg)
 {
 	struct fw_cdev_add_descriptor *a = &arg->add_descriptor;
 	struct descriptor_resource *r;
 	int ret;
 	/* Access policy: Allow this ioctl only on local nodes' device files. */
 	if (!client->device->is_local)
 		return -ENOSYS;
 	if (a->length > 256)
 		return -EINVAL;
 	r = kmalloc(sizeof(*r) + a->length * 4, GFP_KERNEL);
 	if (r == NULL)
 		return -ENOMEM;
 	if (copy_from_user(r->data, u64_to_uptr(a->data), a->length * 4)) {
 		ret = -EFAULT;
 		goto failed;
 	}
 	r->descriptor.length    = a->length;
 	r->descriptor.immediate = a->immediate;
 	r->descriptor.key       = a->key;
 	r->descriptor.data      = r->data;
 	ret = fw_core_add_descriptor(&r->descriptor);
 	if (ret < 0)
 		goto failed;
 	r->resource.release = release_descriptor;
 	ret = add_client_resource(client, &r->resource, GFP_KERNEL);
 	if (ret < 0) {
 		fw_core_remove_descriptor(&r->descriptor);
 		goto failed;
 	}
 	a->handle = r->resource.handle;
 	return 0;
  failed:
 	kfree(r);
 	return ret;
 }
 static int ioctl_remove_descriptor(struct client *client, union ioctl_arg *arg)
 {
 	return release_client_resource(client, arg->remove_descriptor.handle,
 				       release_descriptor, NULL);
 }
 static void iso_callback(struct fw_iso_context *context, u32 cycle,
 			 size_t header_length, void *header, void *data)
 {
 	struct client *client = data;
 	struct iso_interrupt_event *e;
 	e = kmalloc(sizeof(*e) + header_length, GFP_ATOMIC);
 	if (e == NULL) {
 		fw_notify("Out of memory when allocating event\n");
 		return;
 	}
 	e->interrupt.type      = FW_CDEV_EVENT_ISO_INTERRUPT;
 	e->interrupt.closure   = client->iso_closure;
 	e->interrupt.cycle     = cycle;
 	e->interrupt.header_length = header_length;
 	memcpy(e->interrupt.header, header, header_length);
 	queue_event(client, &e->event, &e->interrupt,
 		    sizeof(e->interrupt) + header_length, NULL, 0);
 }
 static void iso_mc_callback(struct fw_iso_context *context,
 			    dma_addr_t completed, void *data)
 {
 	struct client *client = data;
 	struct iso_interrupt_mc_event *e;
 	e = kmalloc(sizeof(*e), GFP_ATOMIC);
 	if (e == NULL) {
 		fw_notify("Out of memory when allocating event\n");
 		return;
 	}
 	e->interrupt.type      = FW_CDEV_EVENT_ISO_INTERRUPT_MULTICHANNEL;
 	e->interrupt.closure   = client->iso_closure;
 	e->interrupt.completed = fw_iso_buffer_lookup(&client->buffer,
 						      completed);
 	queue_event(client, &e->event, &e->interrupt,
 		    sizeof(e->interrupt), NULL, 0);
 }
 static int ioctl_create_iso_context(struct client *client, union ioctl_arg *arg)
 {
 	struct fw_cdev_create_iso_context *a = &arg->create_iso_context;
 	struct fw_iso_context *context;
 	fw_iso_callback_t cb;
 	BUILD_BUG_ON(FW_CDEV_ISO_CONTEXT_TRANSMIT != FW_ISO_CONTEXT_TRANSMIT ||
 		     FW_CDEV_ISO_CONTEXT_RECEIVE  != FW_ISO_CONTEXT_RECEIVE  ||
 		     FW_CDEV_ISO_CONTEXT_RECEIVE_MULTICHANNEL !=
 					FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL);
 	switch (a->type) {
 	case FW_ISO_CONTEXT_TRANSMIT:
 		if (a->speed > SCODE_3200 || a->channel > 63)
 			return -EINVAL;
 		cb = iso_callback;
 		break;
 	case FW_ISO_CONTEXT_RECEIVE:
 		if (a->header_size < 4 || (a->header_size & 3) ||
 		    a->channel > 63)
 			return -EINVAL;
 		cb = iso_callback;
 		break;
 	case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
 		cb = (fw_iso_callback_t)iso_mc_callback;
 		break;
 	default:
 		return -EINVAL;
 	}
 	context = fw_iso_context_create(client->device->card, a->type,
 			a->channel, a->speed, a->header_size, cb, client);
 	if (IS_ERR(context))
 		return PTR_ERR(context);
 	/* We only support one context at this time. */
 	spin_lock_irq(&client->lock);
 	if (client->iso_context != NULL) {
 		spin_unlock_irq(&client->lock);
 		fw_iso_context_destroy(context);
 		return -EBUSY;
 	}
 	client->iso_closure = a->closure;
 	client->iso_context = context;
 	spin_unlock_irq(&client->lock);
 	a->handle = 0;
 	return 0;
 }
 static int ioctl_set_iso_channels(struct client *client, union ioctl_arg *arg)
 {
 	struct fw_cdev_set_iso_channels *a = &arg->set_iso_channels;
 	struct fw_iso_context *ctx = client->iso_context;
 	if (ctx == NULL || a->handle != 0)
 		return -EINVAL;
 	return fw_iso_context_set_channels(ctx, &a->channels);
 }
 /* Macros for decoding the iso packet control header. */
 #define GET_PAYLOAD_LENGTH(v)	((v) & 0xffff)
 #define GET_INTERRUPT(v)	(((v) >> 16) & 0x01)
 #define GET_SKIP(v)		(((v) >> 17) & 0x01)
 #define GET_TAG(v)		(((v) >> 18) & 0x03)
 #define GET_SY(v)		(((v) >> 20) & 0x0f)
 #define GET_HEADER_LENGTH(v)	(((v) >> 24) & 0xff)
 static int ioctl_queue_iso(struct client *client, union ioctl_arg *arg)
 {
 	struct fw_cdev_queue_iso *a = &arg->queue_iso;
 	struct fw_cdev_iso_packet __user *p, *end, *next;
 	struct fw_iso_context *ctx = client->iso_context;
 	unsigned long payload, buffer_end, transmit_header_bytes = 0;
 	u32 control;
 	int count;
 	struct {
 		struct fw_iso_packet packet;
 		u8 header[256];
 	} u;
 	if (ctx == NULL || a->handle != 0)
 		return -EINVAL;
 	/*
 	 * If the user passes a non-NULL data pointer, has mmap()'ed
 	 * the iso buffer, and the pointer points inside the buffer,
 	 * we setup the payload pointers accordingly.  Otherwise we
 	 * set them both to 0, which will still let packets with
 	 * payload_length == 0 through.  In other words, if no packets
 	 * use the indirect payload, the iso buffer need not be mapped
 	 * and the a->data pointer is ignored.
 	 */
 	payload = (unsigned long)a->data - client->vm_start;
 	buffer_end = client->buffer.page_count << PAGE_SHIFT;
 	if (a->data == 0 || client->buffer.pages == NULL ||
 	    payload >= buffer_end) {
 		payload = 0;
 		buffer_end = 0;
 	}
 	if (ctx->type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL && payload & 3)
 		return -EINVAL;
 	p = (struct fw_cdev_iso_packet __user *)u64_to_uptr(a->packets);
 	if (!access_ok(VERIFY_READ, p, a->size))
 		return -EFAULT;
 	end = (void __user *)p + a->size;
 	count = 0;
 	while (p < end) {
 		if (get_user(control, &p->control))
 			return -EFAULT;
 		u.packet.payload_length = GET_PAYLOAD_LENGTH(control);
 		u.packet.interrupt = GET_INTERRUPT(control);
 		u.packet.skip = GET_SKIP(control);
 		u.packet.tag = GET_TAG(control);
 		u.packet.sy = GET_SY(control);
 		u.packet.header_length = GET_HEADER_LENGTH(control);
 		switch (ctx->type) {
 		case FW_ISO_CONTEXT_TRANSMIT:
 			if (u.packet.header_length & 3)
 				return -EINVAL;
 			transmit_header_bytes = u.packet.header_length;
 			break;
 		case FW_ISO_CONTEXT_RECEIVE:
 			if (u.packet.header_length == 0 ||
 			    u.packet.header_length % ctx->header_size != 0)
 				return -EINVAL;
 			break;
 		case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
 			if (u.packet.payload_length == 0 ||
 			    u.packet.payload_length & 3)
 				return -EINVAL;
 			break;
 		}
 		next = (struct fw_cdev_iso_packet __user *)
 			&p->header[transmit_header_bytes / 4];
 		if (next > end)
 			return -EINVAL;
 		if (__copy_from_user
 		    (u.packet.header, p->header, transmit_header_bytes))
 			return -EFAULT;
 		if (u.packet.skip && ctx->type == FW_ISO_CONTEXT_TRANSMIT &&
 		    u.packet.header_length + u.packet.payload_length > 0)
 			return -EINVAL;
 		if (payload + u.packet.payload_length > buffer_end)
 			return -EINVAL;
 		if (fw_iso_context_queue(ctx, &u.packet,
 					 &client->buffer, payload))
 			break;
 		p = next;
 		payload += u.packet.payload_length;
 		count++;
 	}
+	fw_iso_context_queue_flush(ctx);
 	a->size    -= uptr_to_u64(p) - a->packets;
 	a->packets  = uptr_to_u64(p);
 	a->data     = client->vm_start + payload;
 	return count;
 }
 static int ioctl_start_iso(struct client *client, union ioctl_arg *arg)
 {
 	struct fw_cdev_start_iso *a = &arg->start_iso;
 	BUILD_BUG_ON(
 	    FW_CDEV_ISO_CONTEXT_MATCH_TAG0 != FW_ISO_CONTEXT_MATCH_TAG0 ||
 	    FW_CDEV_ISO_CONTEXT_MATCH_TAG1 != FW_ISO_CONTEXT_MATCH_TAG1 ||
 	    FW_CDEV_ISO_CONTEXT_MATCH_TAG2 != FW_ISO_CONTEXT_MATCH_TAG2 ||
 	    FW_CDEV_ISO_CONTEXT_MATCH_TAG3 != FW_ISO_CONTEXT_MATCH_TAG3 ||
 	    FW_CDEV_ISO_CONTEXT_MATCH_ALL_TAGS != FW_ISO_CONTEXT_MATCH_ALL_TAGS);
 	if (client->iso_context == NULL || a->handle != 0)
 		return -EINVAL;
 	if (client->iso_context->type == FW_ISO_CONTEXT_RECEIVE &&
 	    (a->tags == 0 || a->tags > 15 || a->sync > 15))
 		return -EINVAL;
 	return fw_iso_context_start(client->iso_context,
 				    a->cycle, a->sync, a->tags);
 }
 static int ioctl_stop_iso(struct client *client, union ioctl_arg *arg)
 {
 	struct fw_cdev_stop_iso *a = &arg->stop_iso;
 	if (client->iso_context == NULL || a->handle != 0)
 		return -EINVAL;
 	return fw_iso_context_stop(client->iso_context);
 }
 static int ioctl_get_cycle_timer2(struct client *client, union ioctl_arg *arg)
 {
 	struct fw_cdev_get_cycle_timer2 *a = &arg->get_cycle_timer2;
 	struct fw_card *card = client->device->card;
 	struct timespec ts = {0, 0};
 	u32 cycle_time;
 	int ret = 0;
 	local_irq_disable();
 	cycle_time = card->driver->read_csr(card, CSR_CYCLE_TIME);
 	switch (a->clk_id) {
 	case CLOCK_REALTIME:      getnstimeofday(&ts);                   break;
 	case CLOCK_MONOTONIC:     do_posix_clock_monotonic_gettime(&ts); break;
 	case CLOCK_MONOTONIC_RAW: getrawmonotonic(&ts);                  break;
 	default:
 		ret = -EINVAL;
 	}
 	local_irq_enable();
 	a->tv_sec      = ts.tv_sec;
 	a->tv_nsec     = ts.tv_nsec;
 	a->cycle_timer = cycle_time;
 	return ret;
 }
 static int ioctl_get_cycle_timer(struct client *client, union ioctl_arg *arg)
 {
 	struct fw_cdev_get_cycle_timer *a = &arg->get_cycle_timer;
 	struct fw_cdev_get_cycle_timer2 ct2;
 	ct2.clk_id = CLOCK_REALTIME;
 	ioctl_get_cycle_timer2(client, (union ioctl_arg *)&ct2);
 	a->local_time = ct2.tv_sec * USEC_PER_SEC + ct2.tv_nsec / NSEC_PER_USEC;
 	a->cycle_timer = ct2.cycle_timer;
 	return 0;
 }
 static void iso_resource_work(struct work_struct *work)
 {
 	struct iso_resource_event *e;
 	struct iso_resource *r =
 			container_of(work, struct iso_resource, work.work);
 	struct client *client = r->client;
 	int generation, channel, bandwidth, todo;
 	bool skip, free, success;
 	spin_lock_irq(&client->lock);
 	generation = client->device->generation;
 	todo = r->todo;
 	/* Allow 1000ms grace period for other reallocations. */
 	if (todo == ISO_RES_ALLOC &&
 	    time_before64(get_jiffies_64(),
 			  client->device->card->reset_jiffies + HZ)) {
 		schedule_iso_resource(r, DIV_ROUND_UP(HZ, 3));
 		skip = true;
 	} else {
 		/* We could be called twice within the same generation. */
 		skip = todo == ISO_RES_REALLOC &&
 		       r->generation == generation;
 	}
 	free = todo == ISO_RES_DEALLOC ||
 	       todo == ISO_RES_ALLOC_ONCE ||
 	       todo == ISO_RES_DEALLOC_ONCE;
 	r->generation = generation;
 	spin_unlock_irq(&client->lock);
 	if (skip)
 		goto out;
 	bandwidth = r->bandwidth;
 	fw_iso_resource_manage(client->device->card, generation,
 			r->channels, &channel, &bandwidth,
 			todo == ISO_RES_ALLOC ||
 			todo == ISO_RES_REALLOC ||
 			todo == ISO_RES_ALLOC_ONCE);
 	/*
 	 * Is this generation outdated already?  As long as this resource sticks
 	 * in the idr, it will be scheduled again for a newer generation or at
 	 * shutdown.
 	 */
 	if (channel == -EAGAIN &&
 	    (todo == ISO_RES_ALLOC || todo == ISO_RES_REALLOC))
 		goto out;
 	success = channel >= 0 || bandwidth > 0;
 	spin_lock_irq(&client->lock);
 	/*
 	 * Transit from allocation to reallocation, except if the client
 	 * requested deallocation in the meantime.
 	 */
 	if (r->todo == ISO_RES_ALLOC)
 		r->todo = ISO_RES_REALLOC;
 	/*
 	 * Allocation or reallocation failure?  Pull this resource out of the
 	 * idr and prepare for deletion, unless the client is shutting down.
 	 */
 	if (r->todo == ISO_RES_REALLOC && !success &&
 	    !client->in_shutdown &&
 	    idr_find(&client->resource_idr, r->resource.handle)) {
 		idr_remove(&client->resource_idr, r->resource.handle);
 		client_put(client);
 		free = true;
 	}
 	spin_unlock_irq(&client->lock);
 	if (todo == ISO_RES_ALLOC && channel >= 0)
 		r->channels = 1ULL << channel;
 	if (todo == ISO_RES_REALLOC && success)
 		goto out;
 	if (todo == ISO_RES_ALLOC || todo == ISO_RES_ALLOC_ONCE) {
 		e = r->e_alloc;
 		r->e_alloc = NULL;
 	} else {
 		e = r->e_dealloc;
 		r->e_dealloc = NULL;
 	}
 	e->iso_resource.handle    = r->resource.handle;
 	e->iso_resource.channel   = channel;
 	e->iso_resource.bandwidth = bandwidth;
 	queue_event(client, &e->event,
 		    &e->iso_resource, sizeof(e->iso_resource), NULL, 0);
 	if (free) {
 		cancel_delayed_work(&r->work);
 		kfree(r->e_alloc);
 		kfree(r->e_dealloc);
 		kfree(r);
 	}
  out:
 	client_put(client);
 }
 static void release_iso_resource(struct client *client,
 				 struct client_resource *resource)
 {
 	struct iso_resource *r =
 		container_of(resource, struct iso_resource, resource);
 	spin_lock_irq(&client->lock);
 	r->todo = ISO_RES_DEALLOC;
 	schedule_iso_resource(r, 0);
 	spin_unlock_irq(&client->lock);
 }
 static int init_iso_resource(struct client *client,
 		struct fw_cdev_allocate_iso_resource *request, int todo)
 {
 	struct iso_resource_event *e1, *e2;
 	struct iso_resource *r;
 	int ret;
 	if ((request->channels == 0 && request->bandwidth == 0) ||
 	    request->bandwidth > BANDWIDTH_AVAILABLE_INITIAL ||
 	    request->bandwidth < 0)
 		return -EINVAL;
 	r  = kmalloc(sizeof(*r), GFP_KERNEL);
 	e1 = kmalloc(sizeof(*e1), GFP_KERNEL);
 	e2 = kmalloc(sizeof(*e2), GFP_KERNEL);
 	if (r == NULL || e1 == NULL || e2 == NULL) {
 		ret = -ENOMEM;
 		goto fail;
 	}
 	INIT_DELAYED_WORK(&r->work, iso_resource_work);
 	r->client	= client;
 	r->todo		= todo;
 	r->generation	= -1;
 	r->channels	= request->channels;
 	r->bandwidth	= request->bandwidth;
 	r->e_alloc	= e1;
 	r->e_dealloc	= e2;
 	e1->iso_resource.closure = request->closure;
 	e1->iso_resource.type    = FW_CDEV_EVENT_ISO_RESOURCE_ALLOCATED;
 	e2->iso_resource.closure = request->closure;
 	e2->iso_resource.type    = FW_CDEV_EVENT_ISO_RESOURCE_DEALLOCATED;
 	if (todo == ISO_RES_ALLOC) {
 		r->resource.release = release_iso_resource;
 		ret = add_client_resource(client, &r->resource, GFP_KERNEL);
 		if (ret < 0)
 			goto fail;
 	} else {
 		r->resource.release = NULL;
 		r->resource.handle = -1;
 		schedule_iso_resource(r, 0);
 	}
 	request->handle = r->resource.handle;
 	return 0;
  fail:
 	kfree(r);
 	kfree(e1);
 	kfree(e2);
 	return ret;
 }
 static int ioctl_allocate_iso_resource(struct client *client,
 				       union ioctl_arg *arg)
 {
 	return init_iso_resource(client,
 			&arg->allocate_iso_resource, ISO_RES_ALLOC);
 }
 static int ioctl_deallocate_iso_resource(struct client *client,
 					 union ioctl_arg *arg)
 {
 	return release_client_resource(client,
 			arg->deallocate.handle, release_iso_resource, NULL);
 }
 static int ioctl_allocate_iso_resource_once(struct client *client,
 					    union ioctl_arg *arg)
 {
 	return init_iso_resource(client,
 			&arg->allocate_iso_resource, ISO_RES_ALLOC_ONCE);
 }
 static int ioctl_deallocate_iso_resource_once(struct client *client,
 					      union ioctl_arg *arg)
 {
 	return init_iso_resource(client,
 			&arg->allocate_iso_resource, ISO_RES_DEALLOC_ONCE);
 }
 /*
  * Returns a speed code:  Maximum speed to or from this device,
  * limited by the device's link speed, the local node's link speed,
  * and all PHY port speeds between the two links.
  */
 static int ioctl_get_speed(struct client *client, union ioctl_arg *arg)
 {
 	return client->device->max_speed;
 }
 static int ioctl_send_broadcast_request(struct client *client,
 					union ioctl_arg *arg)
 {
 	struct fw_cdev_send_request *a = &arg->send_request;
 	switch (a->tcode) {
 	case TCODE_WRITE_QUADLET_REQUEST:
 	case TCODE_WRITE_BLOCK_REQUEST:
 		break;
 	default:
 		return -EINVAL;
 	}
 	/* Security policy: Only allow accesses to Units Space. */
 	if (a->offset < CSR_REGISTER_BASE + CSR_CONFIG_ROM_END)
 		return -EACCES;
 	return init_request(client, a, LOCAL_BUS | 0x3f, SCODE_100);
 }
 static int ioctl_send_stream_packet(struct client *client, union ioctl_arg *arg)
 {
 	struct fw_cdev_send_stream_packet *a = &arg->send_stream_packet;
 	struct fw_cdev_send_request request;
 	int dest;
 	if (a->speed > client->device->card->link_speed ||
 	    a->length > 1024 << a->speed)
 		return -EIO;
 	if (a->tag > 3 || a->channel > 63 || a->sy > 15)
 		return -EINVAL;
 	dest = fw_stream_packet_destination_id(a->tag, a->channel, a->sy);
 	request.tcode		= TCODE_STREAM_DATA;
 	request.length		= a->length;
 	request.closure		= a->closure;
 	request.data		= a->data;
 	request.generation	= a->generation;
 	return init_request(client, &request, dest, a->speed);
 }
 static void outbound_phy_packet_callback(struct fw_packet *packet,
 					 struct fw_card *card, int status)
 {
 	struct outbound_phy_packet_event *e =
 		container_of(packet, struct outbound_phy_packet_event, p);
 	switch (status) {
 	/* expected: */
 	case ACK_COMPLETE:	e->phy_packet.rcode = RCODE_COMPLETE;	break;
 	/* should never happen with PHY packets: */
 	case ACK_PENDING:	e->phy_packet.rcode = RCODE_COMPLETE;	break;
 	case ACK_BUSY_X:
 	case ACK_BUSY_A:
 	case ACK_BUSY_B:	e->phy_packet.rcode = RCODE_BUSY;	break;
 	case ACK_DATA_ERROR:	e->phy_packet.rcode = RCODE_DATA_ERROR;	break;
 	case ACK_TYPE_ERROR:	e->phy_packet.rcode = RCODE_TYPE_ERROR;	break;
 	/* stale generation; cancelled; on certain controllers: no ack */
 	default:		e->phy_packet.rcode = status;		break;
 	}
 	e->phy_packet.data[0] = packet->timestamp;
 	queue_event(e->client, &e->event, &e->phy_packet,
 		    sizeof(e->phy_packet) + e->phy_packet.length, NULL, 0);
 	client_put(e->client);
 }
 static int ioctl_send_phy_packet(struct client *client, union ioctl_arg *arg)
 {
 	struct fw_cdev_send_phy_packet *a = &arg->send_phy_packet;
 	struct fw_card *card = client->device->card;
 	struct outbound_phy_packet_event *e;
 	/* Access policy: Allow this ioctl only on local nodes' device files. */
 	if (!client->device->is_local)
 		return -ENOSYS;
 	e = kzalloc(sizeof(*e) + 4, GFP_KERNEL);
 	if (e == NULL)
 		return -ENOMEM;
 	client_get(client);
 	e->client		= client;
 	e->p.speed		= SCODE_100;
 	e->p.generation		= a->generation;
 	e->p.header[0]		= TCODE_LINK_INTERNAL << 4;
 	e->p.header[1]		= a->data[0];
 	e->p.header[2]		= a->data[1];
 	e->p.header_length	= 12;
 	e->p.callback		= outbound_phy_packet_callback;
 	e->phy_packet.closure	= a->closure;
 	e->phy_packet.type	= FW_CDEV_EVENT_PHY_PACKET_SENT;
 	if (is_ping_packet(a->data))
 			e->phy_packet.length = 4;
 	card->driver->send_request(card, &e->p);
 	return 0;
 }
 static int ioctl_receive_phy_packets(struct client *client, union ioctl_arg *arg)
 {
 	struct fw_cdev_receive_phy_packets *a = &arg->receive_phy_packets;
 	struct fw_card *card = client->device->card;
 	/* Access policy: Allow this ioctl only on local nodes' device files. */
 	if (!client->device->is_local)
 		return -ENOSYS;
 	spin_lock_irq(&card->lock);
 	list_move_tail(&client->phy_receiver_link, &card->phy_receiver_list);
 	client->phy_receiver_closure = a->closure;
 	spin_unlock_irq(&card->lock);
 	return 0;
 }
 void fw_cdev_handle_phy_packet(struct fw_card *card, struct fw_packet *p)
 {
 	struct client *client;
 	struct inbound_phy_packet_event *e;
 	unsigned long flags;
 	spin_lock_irqsave(&card->lock, flags);
 	list_for_each_entry(client, &card->phy_receiver_list, phy_receiver_link) {
 		e = kmalloc(sizeof(*e) + 8, GFP_ATOMIC);
 		if (e == NULL) {
 			fw_notify("Out of memory when allocating event\n");
 			break;
 		}
 		e->phy_packet.closure	= client->phy_receiver_closure;
 		e->phy_packet.type	= FW_CDEV_EVENT_PHY_PACKET_RECEIVED;
 		e->phy_packet.rcode	= RCODE_COMPLETE;
 		e->phy_packet.length	= 8;
 		e->phy_packet.data[0]	= p->header[1];
 		e->phy_packet.data[1]	= p->header[2];
 		queue_event(client, &e->event,
 			    &e->phy_packet, sizeof(e->phy_packet) + 8, NULL, 0);
 	}
 	spin_unlock_irqrestore(&card->lock, flags);
 }
 static int (* const ioctl_handlers[])(struct client *, union ioctl_arg *) = {
 	[0x00] = ioctl_get_info,
 	[0x01] = ioctl_send_request,
 	[0x02] = ioctl_allocate,
 	[0x03] = ioctl_deallocate,
 	[0x04] = ioctl_send_response,
 	[0x05] = ioctl_initiate_bus_reset,
 	[0x06] = ioctl_add_descriptor,
 	[0x07] = ioctl_remove_descriptor,
 	[0x08] = ioctl_create_iso_context,
 	[0x09] = ioctl_queue_iso,
 	[0x0a] = ioctl_start_iso,
 	[0x0b] = ioctl_stop_iso,
 	[0x0c] = ioctl_get_cycle_timer,
 	[0x0d] = ioctl_allocate_iso_resource,
 	[0x0e] = ioctl_deallocate_iso_resource,
 	[0x0f] = ioctl_allocate_iso_resource_once,
 	[0x10] = ioctl_deallocate_iso_resource_once,
 	[0x11] = ioctl_get_speed,
 	[0x12] = ioctl_send_broadcast_request,
 	[0x13] = ioctl_send_stream_packet,
 	[0x14] = ioctl_get_cycle_timer2,
 	[0x15] = ioctl_send_phy_packet,
 	[0x16] = ioctl_receive_phy_packets,
 	[0x17] = ioctl_set_iso_channels,
 };
 static int dispatch_ioctl(struct client *client,
 			  unsigned int cmd, void __user *arg)
 {
 	union ioctl_arg buffer;
 	int ret;
 	if (fw_device_is_shutdown(client->device))
 		return -ENODEV;
 	if (_IOC_TYPE(cmd) != '#' ||
 	    _IOC_NR(cmd) >= ARRAY_SIZE(ioctl_handlers) ||
 	    _IOC_SIZE(cmd) > sizeof(buffer))
 		return -EINVAL;
 	if (_IOC_DIR(cmd) == _IOC_READ)
 		memset(&buffer, 0, _IOC_SIZE(cmd));
 	if (_IOC_DIR(cmd) & _IOC_WRITE)
 		if (copy_from_user(&buffer, arg, _IOC_SIZE(cmd)))
 			return -EFAULT;
 	ret = ioctl_handlers[_IOC_NR(cmd)](client, &buffer);
 	if (ret < 0)
 		return ret;
 	if (_IOC_DIR(cmd) & _IOC_READ)
 		if (copy_to_user(arg, &buffer, _IOC_SIZE(cmd)))
 			return -EFAULT;
 	return ret;
 }
 static long fw_device_op_ioctl(struct file *file,
 			       unsigned int cmd, unsigned long arg)
 {
 	return dispatch_ioctl(file->private_data, cmd, (void __user *)arg);
 }
 #ifdef CONFIG_COMPAT
 static long fw_device_op_compat_ioctl(struct file *file,
 				      unsigned int cmd, unsigned long arg)
 {
 	return dispatch_ioctl(file->private_data, cmd, compat_ptr(arg));
 }
 #endif
 static int fw_device_op_mmap(struct file *file, struct vm_area_struct *vma)
 {
 	struct client *client = file->private_data;
 	enum dma_data_direction direction;
 	unsigned long size;
 	int page_count, ret;
 	if (fw_device_is_shutdown(client->device))
 		return -ENODEV;
 	/* FIXME: We could support multiple buffers, but we don't. */
 	if (client->buffer.pages != NULL)
 		return -EBUSY;
 	if (!(vma->vm_flags & VM_SHARED))
 		return -EINVAL;
 	if (vma->vm_start & ~PAGE_MASK)
 		return -EINVAL;
 	client->vm_start = vma->vm_start;
 	size = vma->vm_end - vma->vm_start;
 	page_count = size >> PAGE_SHIFT;
 	if (size & ~PAGE_MASK)
 		return -EINVAL;
 	if (vma->vm_flags & VM_WRITE)
 		direction = DMA_TO_DEVICE;
 	else
 		direction = DMA_FROM_DEVICE;
 	ret = fw_iso_buffer_init(&client->buffer, client->device->card,
 				 page_count, direction);
 	if (ret < 0)
 		return ret;
 	ret = fw_iso_buffer_map(&client->buffer, vma);
 	if (ret < 0)
 		fw_iso_buffer_destroy(&client->buffer, client->device->card);
 	return ret;
 }
 static int is_outbound_transaction_resource(int id, void *p, void *data)
 {
 	struct client_resource *resource = p;
 	return resource->release == release_transaction;
 }
 static int has_outbound_transactions(struct client *client)
 {
 	int ret;
 	spin_lock_irq(&client->lock);
 	ret = idr_for_each(&client->resource_idr,
 			   is_outbound_transaction_resource, NULL);
 	spin_unlock_irq(&client->lock);
 	return ret;
 }
 static int shutdown_resource(int id, void *p, void *data)
 {
 	struct client_resource *resource = p;
 	struct client *client = data;
 	resource->release(client, resource);
 	client_put(client);
 	return 0;
 }
 static int fw_device_op_release(struct inode *inode, struct file *file)
 {
 	struct client *client = file->private_data;
 	struct event *event, *next_event;
 	spin_lock_irq(&client->device->card->lock);
 	list_del(&client->phy_receiver_link);
 	spin_unlock_irq(&client->device->card->lock);
 	mutex_lock(&client->device->client_list_mutex);
 	list_del(&client->link);
 	mutex_unlock(&client->device->client_list_mutex);
 	if (client->iso_context)
 		fw_iso_context_destroy(client->iso_context);
 	if (client->buffer.pages)
 		fw_iso_buffer_destroy(&client->buffer, client->device->card);
 	/* Freeze client->resource_idr and client->event_list */
 	spin_lock_irq(&client->lock);
 	client->in_shutdown = true;
 	spin_unlock_irq(&client->lock);
 	wait_event(client->tx_flush_wait, !has_outbound_transactions(client));
 	idr_for_each(&client->resource_idr, shutdown_resource, client);
 	idr_remove_all(&client->resource_idr);
 	idr_destroy(&client->resource_idr);
 	list_for_each_entry_safe(event, next_event, &client->event_list, link)
 		kfree(event);
 	client_put(client);
 	return 0;
 }
 static unsigned int fw_device_op_poll(struct file *file, poll_table * pt)
 {
 	struct client *client = file->private_data;
 	unsigned int mask = 0;
 	poll_wait(file, &client->wait, pt);
 	if (fw_device_is_shutdown(client->device))
 		mask |= POLLHUP | POLLERR;
 	if (!list_empty(&client->event_list))
 		mask |= POLLIN | POLLRDNORM;
 	return mask;
 }
 const struct file_operations fw_device_ops = {
 	.owner		= THIS_MODULE,
 	.llseek		= no_llseek,
 	.open		= fw_device_op_open,
 	.read		= fw_device_op_read,
 	.unlocked_ioctl	= fw_device_op_ioctl,
 	.mmap		= fw_device_op_mmap,
 	.release	= fw_device_op_release,
 	.poll		= fw_device_op_poll,
 #ifdef CONFIG_COMPAT
 	.compat_ioctl	= fw_device_op_compat_ioctl,
 #endif
 };

drivers/firewire/core-iso.c

Diff comments View file @ 13882a8

 /*
  * Isochronous I/O functionality:
  *   - Isochronous DMA context management
  *   - Isochronous bus resource management (channels, bandwidth), client side
  *
  * Copyright (C) 2006 Kristian Hoegsberg <krh@bitplanet.net>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software Foundation,
  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  */
 #include <linux/dma-mapping.h>
 #include <linux/errno.h>
 #include <linux/firewire.h>
 #include <linux/firewire-constants.h>
 #include <linux/kernel.h>
 #include <linux/mm.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
 #include <linux/vmalloc.h>
 #include <asm/byteorder.h>
 #include "core.h"
 /*
  * Isochronous DMA context management
  */
 int fw_iso_buffer_init(struct fw_iso_buffer *buffer, struct fw_card *card,
 		       int page_count, enum dma_data_direction direction)
 {
 	int i, j;
 	dma_addr_t address;
 	buffer->page_count = page_count;
 	buffer->direction = direction;
 	buffer->pages = kmalloc(page_count * sizeof(buffer->pages[0]),
 				GFP_KERNEL);
 	if (buffer->pages == NULL)
 		goto out;
 	for (i = 0; i < buffer->page_count; i++) {
 		buffer->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
 		if (buffer->pages[i] == NULL)
 			goto out_pages;
 		address = dma_map_page(card->device, buffer->pages[i],
 				       0, PAGE_SIZE, direction);
 		if (dma_mapping_error(card->device, address)) {
 			__free_page(buffer->pages[i]);
 			goto out_pages;
 		}
 		set_page_private(buffer->pages[i], address);
 	}
 	return 0;
  out_pages:
 	for (j = 0; j < i; j++) {
 		address = page_private(buffer->pages[j]);
 		dma_unmap_page(card->device, address,
 			       PAGE_SIZE, direction);
 		__free_page(buffer->pages[j]);
 	}
 	kfree(buffer->pages);
  out:
 	buffer->pages = NULL;
 	return -ENOMEM;
 }
 EXPORT_SYMBOL(fw_iso_buffer_init);
 int fw_iso_buffer_map(struct fw_iso_buffer *buffer, struct vm_area_struct *vma)
 {
 	unsigned long uaddr;
 	int i, err;
 	uaddr = vma->vm_start;
 	for (i = 0; i < buffer->page_count; i++) {
 		err = vm_insert_page(vma, uaddr, buffer->pages[i]);
 		if (err)
 			return err;
 		uaddr += PAGE_SIZE;
 	}
 	return 0;
 }
 void fw_iso_buffer_destroy(struct fw_iso_buffer *buffer,
 			   struct fw_card *card)
 {
 	int i;
 	dma_addr_t address;
 	for (i = 0; i < buffer->page_count; i++) {
 		address = page_private(buffer->pages[i]);
 		dma_unmap_page(card->device, address,
 			       PAGE_SIZE, buffer->direction);
 		__free_page(buffer->pages[i]);
 	}
 	kfree(buffer->pages);
 	buffer->pages = NULL;
 }
 EXPORT_SYMBOL(fw_iso_buffer_destroy);
 /* Convert DMA address to offset into virtually contiguous buffer. */
 size_t fw_iso_buffer_lookup(struct fw_iso_buffer *buffer, dma_addr_t completed)
 {
 	int i;
 	dma_addr_t address;
 	ssize_t offset;
 	for (i = 0; i < buffer->page_count; i++) {
 		address = page_private(buffer->pages[i]);
 		offset = (ssize_t)completed - (ssize_t)address;
 		if (offset > 0 && offset <= PAGE_SIZE)
 			return (i << PAGE_SHIFT) + offset;
 	}
 	return 0;
 }
 struct fw_iso_context *fw_iso_context_create(struct fw_card *card,
 		int type, int channel, int speed, size_t header_size,
 		fw_iso_callback_t callback, void *callback_data)
 {
 	struct fw_iso_context *ctx;
 	ctx = card->driver->allocate_iso_context(card,
 						 type, channel, header_size);
 	if (IS_ERR(ctx))
 		return ctx;
 	ctx->card = card;
 	ctx->type = type;
 	ctx->channel = channel;
 	ctx->speed = speed;
 	ctx->header_size = header_size;
 	ctx->callback.sc = callback;
 	ctx->callback_data = callback_data;
 	return ctx;
 }
 EXPORT_SYMBOL(fw_iso_context_create);
 void fw_iso_context_destroy(struct fw_iso_context *ctx)
 {
 	ctx->card->driver->free_iso_context(ctx);
 }
 EXPORT_SYMBOL(fw_iso_context_destroy);
 int fw_iso_context_start(struct fw_iso_context *ctx,
 			 int cycle, int sync, int tags)
 {
 	return ctx->card->driver->start_iso(ctx, cycle, sync, tags);
 }
 EXPORT_SYMBOL(fw_iso_context_start);
 int fw_iso_context_set_channels(struct fw_iso_context *ctx, u64 *channels)
 {
 	return ctx->card->driver->set_iso_channels(ctx, channels);
 }
 int fw_iso_context_queue(struct fw_iso_context *ctx,
 			 struct fw_iso_packet *packet,
 			 struct fw_iso_buffer *buffer,
 			 unsigned long payload)
 {
 	return ctx->card->driver->queue_iso(ctx, packet, buffer, payload);
 }
 EXPORT_SYMBOL(fw_iso_context_queue);
+void fw_iso_context_queue_flush(struct fw_iso_context *ctx)
+{
+	ctx->card->driver->flush_queue_iso(ctx);
+}
+EXPORT_SYMBOL(fw_iso_context_queue_flush);
 int fw_iso_context_stop(struct fw_iso_context *ctx)
 {
 	return ctx->card->driver->stop_iso(ctx);
 }
 EXPORT_SYMBOL(fw_iso_context_stop);
 /*
  * Isochronous bus resource management (channels, bandwidth), client side
  */
 static int manage_bandwidth(struct fw_card *card, int irm_id, int generation,
 			    int bandwidth, bool allocate)
 {
 	int try, new, old = allocate ? BANDWIDTH_AVAILABLE_INITIAL : 0;
 	__be32 data[2];
 	/*
 	 * On a 1394a IRM with low contention, try < 1 is enough.
 	 * On a 1394-1995 IRM, we need at least try < 2.
 	 * Let's just do try < 5.
 	 */
 	for (try = 0; try < 5; try++) {
 		new = allocate ? old - bandwidth : old + bandwidth;
 		if (new < 0 || new > BANDWIDTH_AVAILABLE_INITIAL)
 			return -EBUSY;
 		data[0] = cpu_to_be32(old);
 		data[1] = cpu_to_be32(new);
 		switch (fw_run_transaction(card, TCODE_LOCK_COMPARE_SWAP,
 				irm_id, generation, SCODE_100,
 				CSR_REGISTER_BASE + CSR_BANDWIDTH_AVAILABLE,
 				data, 8)) {
 		case RCODE_GENERATION:
 			/* A generation change frees all bandwidth. */
 			return allocate ? -EAGAIN : bandwidth;
 		case RCODE_COMPLETE:
 			if (be32_to_cpup(data) == old)
 				return bandwidth;
 			old = be32_to_cpup(data);
 			/* Fall through. */
 		}
 	}
 	return -EIO;
 }
 static int manage_channel(struct fw_card *card, int irm_id, int generation,
 		u32 channels_mask, u64 offset, bool allocate)
 {
 	__be32 bit, all, old;
 	__be32 data[2];
 	int channel, ret = -EIO, retry = 5;
 	old = all = allocate ? cpu_to_be32(~0) : 0;
 	for (channel = 0; channel < 32; channel++) {
 		if (!(channels_mask & 1 << channel))
 			continue;
 		ret = -EBUSY;
 		bit = cpu_to_be32(1 << (31 - channel));
 		if ((old & bit) != (all & bit))
 			continue;
 		data[0] = old;
 		data[1] = old ^ bit;
 		switch (fw_run_transaction(card, TCODE_LOCK_COMPARE_SWAP,
 					   irm_id, generation, SCODE_100,
 					   offset, data, 8)) {
 		case RCODE_GENERATION:
 			/* A generation change frees all channels. */
 			return allocate ? -EAGAIN : channel;
 		case RCODE_COMPLETE:
 			if (data[0] == old)
 				return channel;
 			old = data[0];
 			/* Is the IRM 1394a-2000 compliant? */
 			if ((data[0] & bit) == (data[1] & bit))
 				continue;
 			/* 1394-1995 IRM, fall through to retry. */
 		default:
 			if (retry) {
 				retry--;
 				channel--;
 			} else {
 				ret = -EIO;
 			}
 		}
 	}
 	return ret;
 }
 static void deallocate_channel(struct fw_card *card, int irm_id,
 			       int generation, int channel)
 {
 	u32 mask;
 	u64 offset;
 	mask = channel < 32 ? 1 << channel : 1 << (channel - 32);
 	offset = channel < 32 ? CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_HI :
 				CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_LO;
 	manage_channel(card, irm_id, generation, mask, offset, false);
 }
 /**
  * fw_iso_resource_manage() - Allocate or deallocate a channel and/or bandwidth
  *
  * In parameters: card, generation, channels_mask, bandwidth, allocate
  * Out parameters: channel, bandwidth
  * This function blocks (sleeps) during communication with the IRM.
  *
  * Allocates or deallocates at most one channel out of channels_mask.
  * channels_mask is a bitfield with MSB for channel 63 and LSB for channel 0.
  * (Note, the IRM's CHANNELS_AVAILABLE is a big-endian bitfield with MSB for
  * channel 0 and LSB for channel 63.)
  * Allocates or deallocates as many bandwidth allocation units as specified.
  *
  * Returns channel < 0 if no channel was allocated or deallocated.
  * Returns bandwidth = 0 if no bandwidth was allocated or deallocated.
  *
  * If generation is stale, deallocations succeed but allocations fail with
  * channel = -EAGAIN.
  *
  * If channel allocation fails, no bandwidth will be allocated either.
  * If bandwidth allocation fails, no channel will be allocated either.
  * But deallocations of channel and bandwidth are tried independently
  * of each other's success.
  */
 void fw_iso_resource_manage(struct fw_card *card, int generation,
 			    u64 channels_mask, int *channel, int *bandwidth,
 			    bool allocate)
 {
 	u32 channels_hi = channels_mask;	/* channels 31...0 */
 	u32 channels_lo = channels_mask >> 32;	/* channels 63...32 */
 	int irm_id, ret, c = -EINVAL;
 	spin_lock_irq(&card->lock);
 	irm_id = card->irm_node->node_id;
 	spin_unlock_irq(&card->lock);
 	if (channels_hi)
 		c = manage_channel(card, irm_id, generation, channels_hi,
 				CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_HI,
 				allocate);
 	if (channels_lo && c < 0) {
 		c = manage_channel(card, irm_id, generation, channels_lo,
 				CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_LO,
 				allocate);
 		if (c >= 0)
 			c += 32;
 	}
 	*channel = c;
 	if (allocate && channels_mask != 0 && c < 0)
 		*bandwidth = 0;
 	if (*bandwidth == 0)
 		return;
 	ret = manage_bandwidth(card, irm_id, generation, *bandwidth, allocate);
 	if (ret < 0)
 		*bandwidth = 0;
 	if (allocate && ret < 0) {
 		if (c >= 0)
 			deallocate_channel(card, irm_id, generation, c);
 		*channel = ret;
 	}
 }
 EXPORT_SYMBOL(fw_iso_resource_manage);

drivers/firewire/core.h

Diff comments View file @ 13882a8

 #ifndef _FIREWIRE_CORE_H
 #define _FIREWIRE_CORE_H
 #include <linux/fs.h>
 #include <linux/list.h>
 #include <linux/idr.h>
 #include <linux/mm_types.h>
 #include <linux/rwsem.h>
 #include <linux/slab.h>
 #include <linux/types.h>
 #include <asm/atomic.h>
 struct device;
 struct fw_card;
 struct fw_device;
 struct fw_iso_buffer;
 struct fw_iso_context;
 struct fw_iso_packet;
 struct fw_node;
 struct fw_packet;
 /* -card */
 /* bitfields within the PHY registers */
 #define PHY_LINK_ACTIVE		0x80
 #define PHY_CONTENDER		0x40
 #define PHY_BUS_RESET		0x40
 #define PHY_EXTENDED_REGISTERS	0xe0
 #define PHY_BUS_SHORT_RESET	0x40
 #define PHY_INT_STATUS_BITS	0x3c
 #define PHY_ENABLE_ACCEL	0x02
 #define PHY_ENABLE_MULTI	0x01
 #define PHY_PAGE_SELECT		0xe0
 #define BANDWIDTH_AVAILABLE_INITIAL	4915
 #define BROADCAST_CHANNEL_INITIAL	(1 << 31 | 31)
 #define BROADCAST_CHANNEL_VALID		(1 << 30)
 #define CSR_STATE_BIT_CMSTR	(1 << 8)
 #define CSR_STATE_BIT_ABDICATE	(1 << 10)
 struct fw_card_driver {
 	/*
 	 * Enable the given card with the given initial config rom.
 	 * This function is expected to activate the card, and either
 	 * enable the PHY or set the link_on bit and initiate a bus
 	 * reset.
 	 */
 	int (*enable)(struct fw_card *card,
 		      const __be32 *config_rom, size_t length);
 	int (*read_phy_reg)(struct fw_card *card, int address);
 	int (*update_phy_reg)(struct fw_card *card, int address,
 			      int clear_bits, int set_bits);
 	/*
 	 * Update the config rom for an enabled card.  This function
 	 * should change the config rom that is presented on the bus
 	 * and initiate a bus reset.
 	 */
 	int (*set_config_rom)(struct fw_card *card,
 			      const __be32 *config_rom, size_t length);
 	void (*send_request)(struct fw_card *card, struct fw_packet *packet);
 	void (*send_response)(struct fw_card *card, struct fw_packet *packet);
 	/* Calling cancel is valid once a packet has been submitted. */
 	int (*cancel_packet)(struct fw_card *card, struct fw_packet *packet);
 	/*
 	 * Allow the specified node ID to do direct DMA out and in of
 	 * host memory.  The card will disable this for all node when
 	 * a bus reset happens, so driver need to reenable this after
 	 * bus reset.  Returns 0 on success, -ENODEV if the card
 	 * doesn't support this, -ESTALE if the generation doesn't
 	 * match.
 	 */
 	int (*enable_phys_dma)(struct fw_card *card,
 			       int node_id, int generation);
 	u32 (*read_csr)(struct fw_card *card, int csr_offset);
 	void (*write_csr)(struct fw_card *card, int csr_offset, u32 value);
 	struct fw_iso_context *
 	(*allocate_iso_context)(struct fw_card *card,
 				int type, int channel, size_t header_size);
 	void (*free_iso_context)(struct fw_iso_context *ctx);
 	int (*start_iso)(struct fw_iso_context *ctx,
 			 s32 cycle, u32 sync, u32 tags);
 	int (*set_iso_channels)(struct fw_iso_context *ctx, u64 *channels);
 	int (*queue_iso)(struct fw_iso_context *ctx,
 			 struct fw_iso_packet *packet,
 			 struct fw_iso_buffer *buffer,
 			 unsigned long payload);
+	void (*flush_queue_iso)(struct fw_iso_context *ctx);
 	int (*stop_iso)(struct fw_iso_context *ctx);
 };
 void fw_card_initialize(struct fw_card *card,
 		const struct fw_card_driver *driver, struct device *device);
 int fw_card_add(struct fw_card *card,
 		u32 max_receive, u32 link_speed, u64 guid);
 void fw_core_remove_card(struct fw_card *card);
 int fw_compute_block_crc(__be32 *block);
 void fw_schedule_bus_reset(struct fw_card *card, bool delayed, bool short_reset);
 void fw_schedule_bm_work(struct fw_card *card, unsigned long delay);
 static inline struct fw_card *fw_card_get(struct fw_card *card)
 {
 	kref_get(&card->kref);
 	return card;
 }
 void fw_card_release(struct kref *kref);
 static inline void fw_card_put(struct fw_card *card)
 {
 	kref_put(&card->kref, fw_card_release);
 }
 /* -cdev */
 extern const struct file_operations fw_device_ops;
 void fw_device_cdev_update(struct fw_device *device);
 void fw_device_cdev_remove(struct fw_device *device);
 void fw_cdev_handle_phy_packet(struct fw_card *card, struct fw_packet *p);
 /* -device */
 extern struct rw_semaphore fw_device_rwsem;
 extern struct idr fw_device_idr;
 extern int fw_cdev_major;
 struct fw_device *fw_device_get_by_devt(dev_t devt);
 int fw_device_set_broadcast_channel(struct device *dev, void *gen);
 void fw_node_event(struct fw_card *card, struct fw_node *node, int event);
 /* -iso */
 int fw_iso_buffer_map(struct fw_iso_buffer *buffer, struct vm_area_struct *vma);
 /* -topology */
 enum {
 	FW_NODE_CREATED,
 	FW_NODE_UPDATED,
 	FW_NODE_DESTROYED,
 	FW_NODE_LINK_ON,
 	FW_NODE_LINK_OFF,
 	FW_NODE_INITIATED_RESET,
 };
 struct fw_node {
 	u16 node_id;
 	u8 color;
 	u8 port_count;
 	u8 link_on:1;
 	u8 initiated_reset:1;
 	u8 b_path:1;
 	u8 phy_speed:2;	/* As in the self ID packet. */
 	u8 max_speed:2;	/* Minimum of all phy-speeds on the path from the
 			 * local node to this node. */
 	u8 max_depth:4;	/* Maximum depth to any leaf node */
 	u8 max_hops:4;	/* Max hops in this sub tree */
 	atomic_t ref_count;
 	/* For serializing node topology into a list. */
 	struct list_head link;
 	/* Upper layer specific data. */
 	void *data;
 	struct fw_node *ports[0];
 };
 static inline struct fw_node *fw_node_get(struct fw_node *node)
 {
 	atomic_inc(&node->ref_count);
 	return node;
 }
 static inline void fw_node_put(struct fw_node *node)
 {
 	if (atomic_dec_and_test(&node->ref_count))
 		kfree(node);
 }
 void fw_core_handle_bus_reset(struct fw_card *card, int node_id,
 	int generation, int self_id_count, u32 *self_ids, bool bm_abdicate);
 void fw_destroy_nodes(struct fw_card *card);
 /*
  * Check whether new_generation is the immediate successor of old_generation.
  * Take counter roll-over at 255 (as per OHCI) into account.
  */
 static inline bool is_next_generation(int new_generation, int old_generation)
 {
 	return (new_generation & 0xff) == ((old_generation + 1) & 0xff);
 }
 /* -transaction */
 #define TCODE_LINK_INTERNAL		0xe
 #define TCODE_IS_READ_REQUEST(tcode)	(((tcode) & ~1) == 4)
 #define TCODE_IS_BLOCK_PACKET(tcode)	(((tcode) &  1) != 0)
 #define TCODE_IS_LINK_INTERNAL(tcode)	((tcode) == TCODE_LINK_INTERNAL)
 #define TCODE_IS_REQUEST(tcode)		(((tcode) &  2) == 0)
 #define TCODE_IS_RESPONSE(tcode)	(((tcode) &  2) != 0)
 #define TCODE_HAS_REQUEST_DATA(tcode)	(((tcode) & 12) != 4)
 #define TCODE_HAS_RESPONSE_DATA(tcode)	(((tcode) & 12) != 0)
 #define LOCAL_BUS 0xffc0
 void fw_core_handle_request(struct fw_card *card, struct fw_packet *request);
 void fw_core_handle_response(struct fw_card *card, struct fw_packet *packet);
 int fw_get_response_length(struct fw_request *request);
 void fw_fill_response(struct fw_packet *response, u32 *request_header,
 		      int rcode, void *payload, size_t length);
 #define FW_PHY_CONFIG_NO_NODE_ID	-1
 #define FW_PHY_CONFIG_CURRENT_GAP_COUNT	-1
 void fw_send_phy_config(struct fw_card *card,
 			int node_id, int generation, int gap_count);
 static inline bool is_ping_packet(u32 *data)
 {
 	return (data[0] & 0xc0ffffff) == 0 && ~data[0] == data[1];
 }
 #endif /* _FIREWIRE_CORE_H */

drivers/firewire/net.c

Diff comments View file @ 13882a8

 /*
  * IPv4 over IEEE 1394, per RFC 2734
  *
  * Copyright (C) 2009 Jay Fenlason <fenlason@redhat.com>
  *
  * based on eth1394 by Ben Collins et al
  */
 #include <linux/bug.h>
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/ethtool.h>
 #include <linux/firewire.h>
 #include <linux/firewire-constants.h>
 #include <linux/highmem.h>
 #include <linux/in.h>
 #include <linux/ip.h>
 #include <linux/jiffies.h>
 #include <linux/mod_devicetable.h>
 #include <linux/module.h>
 #include <linux/moduleparam.h>
 #include <linux/mutex.h>
 #include <linux/netdevice.h>
 #include <linux/skbuff.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
 #include <asm/unaligned.h>
 #include <net/arp.h>
 /* rx limits */
 #define FWNET_MAX_FRAGMENTS		30 /* arbitrary, > TX queue depth */
 #define FWNET_ISO_PAGE_COUNT		(PAGE_SIZE < 16*1024 ? 4 : 2)
 /* tx limits */
 #define FWNET_MAX_QUEUED_DATAGRAMS	20 /* < 64 = number of tlabels */
 #define FWNET_MIN_QUEUED_DATAGRAMS	10 /* should keep AT DMA busy enough */
 #define FWNET_TX_QUEUE_LEN		FWNET_MAX_QUEUED_DATAGRAMS /* ? */
 #define IEEE1394_BROADCAST_CHANNEL	31
 #define IEEE1394_ALL_NODES		(0xffc0 | 0x003f)
 #define IEEE1394_MAX_PAYLOAD_S100	512
 #define FWNET_NO_FIFO_ADDR		(~0ULL)
 #define IANA_SPECIFIER_ID		0x00005eU
 #define RFC2734_SW_VERSION		0x000001U
 #define IEEE1394_GASP_HDR_SIZE	8
 #define RFC2374_UNFRAG_HDR_SIZE	4
 #define RFC2374_FRAG_HDR_SIZE	8
 #define RFC2374_FRAG_OVERHEAD	4
 #define RFC2374_HDR_UNFRAG	0	/* unfragmented		*/
 #define RFC2374_HDR_FIRSTFRAG	1	/* first fragment	*/
 #define RFC2374_HDR_LASTFRAG	2	/* last fragment	*/
 #define RFC2374_HDR_INTFRAG	3	/* interior fragment	*/
 #define RFC2734_HW_ADDR_LEN	16
 struct rfc2734_arp {
 	__be16 hw_type;		/* 0x0018	*/
 	__be16 proto_type;	/* 0x0806       */
 	u8 hw_addr_len;		/* 16		*/
 	u8 ip_addr_len;		/* 4		*/
 	__be16 opcode;		/* ARP Opcode	*/
 	/* Above is exactly the same format as struct arphdr */
 	__be64 s_uniq_id;	/* Sender's 64bit EUI			*/
 	u8 max_rec;		/* Sender's max packet size		*/
 	u8 sspd;		/* Sender's max speed			*/
 	__be16 fifo_hi;		/* hi 16bits of sender's FIFO addr	*/
 	__be32 fifo_lo;		/* lo 32bits of sender's FIFO addr	*/
 	__be32 sip;		/* Sender's IP Address			*/
 	__be32 tip;		/* IP Address of requested hw addr	*/
 } __attribute__((packed));
 /* This header format is specific to this driver implementation. */
 #define FWNET_ALEN	8
 #define FWNET_HLEN	10
 struct fwnet_header {
 	u8 h_dest[FWNET_ALEN];	/* destination address */
 	__be16 h_proto;		/* packet type ID field */
 } __attribute__((packed));
 /* IPv4 and IPv6 encapsulation header */
 struct rfc2734_header {
 	u32 w0;
 	u32 w1;
 };
 #define fwnet_get_hdr_lf(h)		(((h)->w0 & 0xc0000000) >> 30)
 #define fwnet_get_hdr_ether_type(h)	(((h)->w0 & 0x0000ffff))
 #define fwnet_get_hdr_dg_size(h)	(((h)->w0 & 0x0fff0000) >> 16)
 #define fwnet_get_hdr_fg_off(h)		(((h)->w0 & 0x00000fff))
 #define fwnet_get_hdr_dgl(h)		(((h)->w1 & 0xffff0000) >> 16)
 #define fwnet_set_hdr_lf(lf)		((lf)  << 30)
 #define fwnet_set_hdr_ether_type(et)	(et)
 #define fwnet_set_hdr_dg_size(dgs)	((dgs) << 16)
 #define fwnet_set_hdr_fg_off(fgo)	(fgo)
 #define fwnet_set_hdr_dgl(dgl)		((dgl) << 16)
 static inline void fwnet_make_uf_hdr(struct rfc2734_header *hdr,
 		unsigned ether_type)
 {
 	hdr->w0 = fwnet_set_hdr_lf(RFC2374_HDR_UNFRAG)
 		  | fwnet_set_hdr_ether_type(ether_type);
 }
 static inline void fwnet_make_ff_hdr(struct rfc2734_header *hdr,
 		unsigned ether_type, unsigned dg_size, unsigned dgl)
 {
 	hdr->w0 = fwnet_set_hdr_lf(RFC2374_HDR_FIRSTFRAG)
 		  | fwnet_set_hdr_dg_size(dg_size)
 		  | fwnet_set_hdr_ether_type(ether_type);
 	hdr->w1 = fwnet_set_hdr_dgl(dgl);
 }
 static inline void fwnet_make_sf_hdr(struct rfc2734_header *hdr,
 		unsigned lf, unsigned dg_size, unsigned fg_off, unsigned dgl)
 {
 	hdr->w0 = fwnet_set_hdr_lf(lf)
 		  | fwnet_set_hdr_dg_size(dg_size)
 		  | fwnet_set_hdr_fg_off(fg_off);
 	hdr->w1 = fwnet_set_hdr_dgl(dgl);
 }
 /* This list keeps track of what parts of the datagram have been filled in */
 struct fwnet_fragment_info {
 	struct list_head fi_link;
 	u16 offset;
 	u16 len;
 };
 struct fwnet_partial_datagram {
 	struct list_head pd_link;
 	struct list_head fi_list;
 	struct sk_buff *skb;
 	/* FIXME Why not use skb->data? */
 	char *pbuf;
 	u16 datagram_label;
 	u16 ether_type;
 	u16 datagram_size;
 };
 static DEFINE_MUTEX(fwnet_device_mutex);
 static LIST_HEAD(fwnet_device_list);
 struct fwnet_device {
 	struct list_head dev_link;
 	spinlock_t lock;
 	enum {
 		FWNET_BROADCAST_ERROR,
 		FWNET_BROADCAST_RUNNING,
 		FWNET_BROADCAST_STOPPED,
 	} broadcast_state;
 	struct fw_iso_context *broadcast_rcv_context;
 	struct fw_iso_buffer broadcast_rcv_buffer;
 	void **broadcast_rcv_buffer_ptrs;
 	unsigned broadcast_rcv_next_ptr;
 	unsigned num_broadcast_rcv_ptrs;
 	unsigned rcv_buffer_size;
 	/*
 	 * This value is the maximum unfragmented datagram size that can be
 	 * sent by the hardware.  It already has the GASP overhead and the
 	 * unfragmented datagram header overhead calculated into it.
 	 */
 	unsigned broadcast_xmt_max_payload;
 	u16 broadcast_xmt_datagramlabel;
 	/*
 	 * The CSR address that remote nodes must send datagrams to for us to
 	 * receive them.
 	 */
 	struct fw_address_handler handler;
 	u64 local_fifo;
 	/* Number of tx datagrams that have been queued but not yet acked */
 	int queued_datagrams;
 	int peer_count;
 	struct list_head peer_list;
 	struct fw_card *card;
 	struct net_device *netdev;
 };
 struct fwnet_peer {
 	struct list_head peer_link;
 	struct fwnet_device *dev;
 	u64 guid;
 	u64 fifo;
 	__be32 ip;
 	/* guarded by dev->lock */
 	struct list_head pd_list; /* received partial datagrams */
 	unsigned pdg_size;        /* pd_list size */
 	u16 datagram_label;       /* outgoing datagram label */
 	u16 max_payload;          /* includes RFC2374_FRAG_HDR_SIZE overhead */
 	int node_id;
 	int generation;
 	unsigned speed;
 };
 /* This is our task struct. It's used for the packet complete callback.  */
 struct fwnet_packet_task {
 	struct fw_transaction transaction;
 	struct rfc2734_header hdr;
 	struct sk_buff *skb;
 	struct fwnet_device *dev;
 	int outstanding_pkts;
 	u64 fifo_addr;
 	u16 dest_node;
 	u16 max_payload;
 	u8 generation;
 	u8 speed;
 	u8 enqueued;
 };
 /*
  * saddr == NULL means use device source address.
  * daddr == NULL means leave destination address (eg unresolved arp).
  */
 static int fwnet_header_create(struct sk_buff *skb, struct net_device *net,
 			unsigned short type, const void *daddr,
 			const void *saddr, unsigned len)
 {
 	struct fwnet_header *h;
 	h = (struct fwnet_header *)skb_push(skb, sizeof(*h));
 	put_unaligned_be16(type, &h->h_proto);
 	if (net->flags & (IFF_LOOPBACK | IFF_NOARP)) {
 		memset(h->h_dest, 0, net->addr_len);
 		return net->hard_header_len;
 	}
 	if (daddr) {
 		memcpy(h->h_dest, daddr, net->addr_len);
 		return net->hard_header_len;
 	}
 	return -net->hard_header_len;
 }
 static int fwnet_header_rebuild(struct sk_buff *skb)
 {
 	struct fwnet_header *h = (struct fwnet_header *)skb->data;
 	if (get_unaligned_be16(&h->h_proto) == ETH_P_IP)
 		return arp_find((unsigned char *)&h->h_dest, skb);
 	fw_notify("%s: unable to resolve type %04x addresses\n",
 		  skb->dev->name, be16_to_cpu(h->h_proto));
 	return 0;
 }
 static int fwnet_header_cache(const struct neighbour *neigh,
 			      struct hh_cache *hh)
 {
 	struct net_device *net;
 	struct fwnet_header *h;
 	if (hh->hh_type == cpu_to_be16(ETH_P_802_3))
 		return -1;
 	net = neigh->dev;
 	h = (struct fwnet_header *)((u8 *)hh->hh_data + 16 - sizeof(*h));
 	h->h_proto = hh->hh_type;
 	memcpy(h->h_dest, neigh->ha, net->addr_len);
 	hh->hh_len = FWNET_HLEN;
 	return 0;
 }
 /* Called by Address Resolution module to notify changes in address. */
 static void fwnet_header_cache_update(struct hh_cache *hh,
 		const struct net_device *net, const unsigned char *haddr)
 {
 	memcpy((u8 *)hh->hh_data + 16 - FWNET_HLEN, haddr, net->addr_len);
 }
 static int fwnet_header_parse(const struct sk_buff *skb, unsigned char *haddr)
 {
 	memcpy(haddr, skb->dev->dev_addr, FWNET_ALEN);
 	return FWNET_ALEN;
 }
 static const struct header_ops fwnet_header_ops = {
 	.create         = fwnet_header_create,
 	.rebuild        = fwnet_header_rebuild,
 	.cache		= fwnet_header_cache,
 	.cache_update	= fwnet_header_cache_update,
 	.parse          = fwnet_header_parse,
 };
 /* FIXME: is this correct for all cases? */
 static bool fwnet_frag_overlap(struct fwnet_partial_datagram *pd,
 			       unsigned offset, unsigned len)
 {
 	struct fwnet_fragment_info *fi;
 	unsigned end = offset + len;
 	list_for_each_entry(fi, &pd->fi_list, fi_link)
 		if (offset < fi->offset + fi->len && end > fi->offset)
 			return true;
 	return false;
 }
 /* Assumes that new fragment does not overlap any existing fragments */
 static struct fwnet_fragment_info *fwnet_frag_new(
 	struct fwnet_partial_datagram *pd, unsigned offset, unsigned len)
 {
 	struct fwnet_fragment_info *fi, *fi2, *new;
 	struct list_head *list;
 	list = &pd->fi_list;
 	list_for_each_entry(fi, &pd->fi_list, fi_link) {
 		if (fi->offset + fi->len == offset) {
 			/* The new fragment can be tacked on to the end */
 			/* Did the new fragment plug a hole? */
 			fi2 = list_entry(fi->fi_link.next,
 					 struct fwnet_fragment_info, fi_link);
 			if (fi->offset + fi->len == fi2->offset) {
 				/* glue fragments together */
 				fi->len += len + fi2->len;
 				list_del(&fi2->fi_link);
 				kfree(fi2);
 			} else {
 				fi->len += len;
 			}
 			return fi;
 		}
 		if (offset + len == fi->offset) {
 			/* The new fragment can be tacked on to the beginning */
 			/* Did the new fragment plug a hole? */
 			fi2 = list_entry(fi->fi_link.prev,
 					 struct fwnet_fragment_info, fi_link);
 			if (fi2->offset + fi2->len == fi->offset) {
 				/* glue fragments together */
 				fi2->len += fi->len + len;
 				list_del(&fi->fi_link);
 				kfree(fi);
 				return fi2;
 			}
 			fi->offset = offset;
 			fi->len += len;
 			return fi;
 		}
 		if (offset > fi->offset + fi->len) {
 			list = &fi->fi_link;
 			break;
 		}
 		if (offset + len < fi->offset) {
 			list = fi->fi_link.prev;
 			break;
 		}
 	}
 	new = kmalloc(sizeof(*new), GFP_ATOMIC);
 	if (!new) {
 		fw_error("out of memory\n");
 		return NULL;
 	}
 	new->offset = offset;
 	new->len = len;
 	list_add(&new->fi_link, list);
 	return new;
 }
 static struct fwnet_partial_datagram *fwnet_pd_new(struct net_device *net,
 		struct fwnet_peer *peer, u16 datagram_label, unsigned dg_size,
 		void *frag_buf, unsigned frag_off, unsigned frag_len)
 {
 	struct fwnet_partial_datagram *new;
 	struct fwnet_fragment_info *fi;
 	new = kmalloc(sizeof(*new), GFP_ATOMIC);
 	if (!new)
 		goto fail;
 	INIT_LIST_HEAD(&new->fi_list);
 	fi = fwnet_frag_new(new, frag_off, frag_len);
 	if (fi == NULL)
 		goto fail_w_new;
 	new->datagram_label = datagram_label;
 	new->datagram_size = dg_size;
 	new->skb = dev_alloc_skb(dg_size + net->hard_header_len + 15);
 	if (new->skb == NULL)
 		goto fail_w_fi;
 	skb_reserve(new->skb, (net->hard_header_len + 15) & ~15);
 	new->pbuf = skb_put(new->skb, dg_size);
 	memcpy(new->pbuf + frag_off, frag_buf, frag_len);
 	list_add_tail(&new->pd_link, &peer->pd_list);
 	return new;
 fail_w_fi:
 	kfree(fi);
 fail_w_new:
 	kfree(new);
 fail:
 	fw_error("out of memory\n");
 	return NULL;
 }
 static struct fwnet_partial_datagram *fwnet_pd_find(struct fwnet_peer *peer,
 						    u16 datagram_label)
 {
 	struct fwnet_partial_datagram *pd;
 	list_for_each_entry(pd, &peer->pd_list, pd_link)
 		if (pd->datagram_label == datagram_label)
 			return pd;
 	return NULL;
 }
 static void fwnet_pd_delete(struct fwnet_partial_datagram *old)
 {
 	struct fwnet_fragment_info *fi, *n;
 	list_for_each_entry_safe(fi, n, &old->fi_list, fi_link)
 		kfree(fi);
 	list_del(&old->pd_link);
 	dev_kfree_skb_any(old->skb);
 	kfree(old);
 }
 static bool fwnet_pd_update(struct fwnet_peer *peer,
 		struct fwnet_partial_datagram *pd, void *frag_buf,
 		unsigned frag_off, unsigned frag_len)
 {
 	if (fwnet_frag_new(pd, frag_off, frag_len) == NULL)
 		return false;
 	memcpy(pd->pbuf + frag_off, frag_buf, frag_len);
 	/*
 	 * Move list entry to beginning of list so that oldest partial
 	 * datagrams percolate to the end of the list
 	 */
 	list_move_tail(&pd->pd_link, &peer->pd_list);
 	return true;
 }
 static bool fwnet_pd_is_complete(struct fwnet_partial_datagram *pd)
 {
 	struct fwnet_fragment_info *fi;
 	fi = list_entry(pd->fi_list.next, struct fwnet_fragment_info, fi_link);
 	return fi->len == pd->datagram_size;
 }
 /* caller must hold dev->lock */
 static struct fwnet_peer *fwnet_peer_find_by_guid(struct fwnet_device *dev,
 						  u64 guid)
 {
 	struct fwnet_peer *peer;
 	list_for_each_entry(peer, &dev->peer_list, peer_link)
 		if (peer->guid == guid)
 			return peer;
 	return NULL;
 }
 /* caller must hold dev->lock */
 static struct fwnet_peer *fwnet_peer_find_by_node_id(struct fwnet_device *dev,
 						int node_id, int generation)
 {
 	struct fwnet_peer *peer;
 	list_for_each_entry(peer, &dev->peer_list, peer_link)
 		if (peer->node_id    == node_id &&
 		    peer->generation == generation)
 			return peer;
 	return NULL;
 }
 /* See IEEE 1394-2008 table 6-4, table 8-8, table 16-18. */
 static unsigned fwnet_max_payload(unsigned max_rec, unsigned speed)
 {
 	max_rec = min(max_rec, speed + 8);
 	max_rec = min(max_rec, 0xbU); /* <= 4096 */
 	if (max_rec < 8) {
 		fw_notify("max_rec %x out of range\n", max_rec);
 		max_rec = 8;
 	}
 	return (1 << (max_rec + 1)) - RFC2374_FRAG_HDR_SIZE;
 }
 static int fwnet_finish_incoming_packet(struct net_device *net,
 					struct sk_buff *skb, u16 source_node_id,
 					bool is_broadcast, u16 ether_type)
 {
 	struct fwnet_device *dev;
 	static const __be64 broadcast_hw = cpu_to_be64(~0ULL);
 	int status;
 	__be64 guid;
 	dev = netdev_priv(net);
 	/* Write metadata, and then pass to the receive level */
 	skb->dev = net;
 	skb->ip_summed = CHECKSUM_UNNECESSARY;  /* don't check it */
 	/*
 	 * Parse the encapsulation header. This actually does the job of
 	 * converting to an ethernet frame header, as well as arp
 	 * conversion if needed. ARP conversion is easier in this
 	 * direction, since we are using ethernet as our backend.
 	 */
 	/*
 	 * If this is an ARP packet, convert it. First, we want to make
 	 * use of some of the fields, since they tell us a little bit
 	 * about the sending machine.
 	 */
 	if (ether_type == ETH_P_ARP) {
 		struct rfc2734_arp *arp1394;
 		struct arphdr *arp;
 		unsigned char *arp_ptr;
 		u64 fifo_addr;
 		u64 peer_guid;
 		unsigned sspd;
 		u16 max_payload;
 		struct fwnet_peer *peer;
 		unsigned long flags;
 		arp1394   = (struct rfc2734_arp *)skb->data;
 		arp       = (struct arphdr *)skb->data;
 		arp_ptr   = (unsigned char *)(arp + 1);
 		peer_guid = get_unaligned_be64(&arp1394->s_uniq_id);
 		fifo_addr = (u64)get_unaligned_be16(&arp1394->fifo_hi) << 32
 				| get_unaligned_be32(&arp1394->fifo_lo);
 		sspd = arp1394->sspd;
 		/* Sanity check.  OS X 10.3 PPC reportedly sends 131. */
 		if (sspd > SCODE_3200) {
 			fw_notify("sspd %x out of range\n", sspd);
 			sspd = SCODE_3200;
 		}
 		max_payload = fwnet_max_payload(arp1394->max_rec, sspd);
 		spin_lock_irqsave(&dev->lock, flags);
 		peer = fwnet_peer_find_by_guid(dev, peer_guid);
 		if (peer) {
 			peer->fifo = fifo_addr;
 			if (peer->speed > sspd)
 				peer->speed = sspd;
 			if (peer->max_payload > max_payload)
 				peer->max_payload = max_payload;
 			peer->ip = arp1394->sip;
 		}
 		spin_unlock_irqrestore(&dev->lock, flags);
 		if (!peer) {
 			fw_notify("No peer for ARP packet from %016llx\n",
 				  (unsigned long long)peer_guid);
 			goto no_peer;
 		}
 		/*
 		 * Now that we're done with the 1394 specific stuff, we'll
 		 * need to alter some of the data.  Believe it or not, all
 		 * that needs to be done is sender_IP_address needs to be
 		 * moved, the destination hardware address get stuffed
 		 * in and the hardware address length set to 8.
 		 *
 		 * IMPORTANT: The code below overwrites 1394 specific data
 		 * needed above so keep the munging of the data for the
 		 * higher level IP stack last.
 		 */
 		arp->ar_hln = 8;
 		/* skip over sender unique id */
 		arp_ptr += arp->ar_hln;
 		/* move sender IP addr */
 		put_unaligned(arp1394->sip, (u32 *)arp_ptr);
 		/* skip over sender IP addr */
 		arp_ptr += arp->ar_pln;
 		if (arp->ar_op == htons(ARPOP_REQUEST))
 			memset(arp_ptr, 0, sizeof(u64));
 		else
 			memcpy(arp_ptr, net->dev_addr, sizeof(u64));
 	}
 	/* Now add the ethernet header. */
 	guid = cpu_to_be64(dev->card->guid);
 	if (dev_hard_header(skb, net, ether_type,
 			   is_broadcast ? &broadcast_hw : &guid,
 			   NULL, skb->len) >= 0) {
 		struct fwnet_header *eth;
 		u16 *rawp;
 		__be16 protocol;
 		skb_reset_mac_header(skb);
 		skb_pull(skb, sizeof(*eth));
 		eth = (struct fwnet_header *)skb_mac_header(skb);
 		if (*eth->h_dest & 1) {
 			if (memcmp(eth->h_dest, net->broadcast,
 				   net->addr_len) == 0)
 				skb->pkt_type = PACKET_BROADCAST;
 #if 0
 			else
 				skb->pkt_type = PACKET_MULTICAST;
 #endif
 		} else {
 			if (memcmp(eth->h_dest, net->dev_addr, net->addr_len))
 				skb->pkt_type = PACKET_OTHERHOST;
 		}
 		if (ntohs(eth->h_proto) >= 1536) {
 			protocol = eth->h_proto;
 		} else {
 			rawp = (u16 *)skb->data;
 			if (*rawp == 0xffff)
 				protocol = htons(ETH_P_802_3);
 			else
 				protocol = htons(ETH_P_802_2);
 		}
 		skb->protocol = protocol;
 	}
 	status = netif_rx(skb);
 	if (status == NET_RX_DROP) {
 		net->stats.rx_errors++;
 		net->stats.rx_dropped++;
 	} else {
 		net->stats.rx_packets++;
 		net->stats.rx_bytes += skb->len;
 	}
 	return 0;
  no_peer:
 	net->stats.rx_errors++;
 	net->stats.rx_dropped++;
 	dev_kfree_skb_any(skb);
 	return -ENOENT;
 }
 static int fwnet_incoming_packet(struct fwnet_device *dev, __be32 *buf, int len,
 				 int source_node_id, int generation,
 				 bool is_broadcast)
 {
 	struct sk_buff *skb;
 	struct net_device *net = dev->netdev;
 	struct rfc2734_header hdr;
 	unsigned lf;
 	unsigned long flags;
 	struct fwnet_peer *peer;
 	struct fwnet_partial_datagram *pd;
 	int fg_off;
 	int dg_size;
 	u16 datagram_label;
 	int retval;
 	u16 ether_type;
 	hdr.w0 = be32_to_cpu(buf[0]);
 	lf = fwnet_get_hdr_lf(&hdr);
 	if (lf == RFC2374_HDR_UNFRAG) {
 		/*
 		 * An unfragmented datagram has been received by the ieee1394
 		 * bus. Build an skbuff around it so we can pass it to the
 		 * high level network layer.
 		 */
 		ether_type = fwnet_get_hdr_ether_type(&hdr);
 		buf++;
 		len -= RFC2374_UNFRAG_HDR_SIZE;
 		skb = dev_alloc_skb(len + net->hard_header_len + 15);
 		if (unlikely(!skb)) {
 			fw_error("out of memory\n");
 			net->stats.rx_dropped++;
 			return -ENOMEM;
 		}
 		skb_reserve(skb, (net->hard_header_len + 15) & ~15);
 		memcpy(skb_put(skb, len), buf, len);
 		return fwnet_finish_incoming_packet(net, skb, source_node_id,
 						    is_broadcast, ether_type);
 	}
 	/* A datagram fragment has been received, now the fun begins. */
 	hdr.w1 = ntohl(buf[1]);
 	buf += 2;
 	len -= RFC2374_FRAG_HDR_SIZE;
 	if (lf == RFC2374_HDR_FIRSTFRAG) {
 		ether_type = fwnet_get_hdr_ether_type(&hdr);
 		fg_off = 0;
 	} else {
 		ether_type = 0;
 		fg_off = fwnet_get_hdr_fg_off(&hdr);
 	}
 	datagram_label = fwnet_get_hdr_dgl(&hdr);
 	dg_size = fwnet_get_hdr_dg_size(&hdr); /* ??? + 1 */
 	spin_lock_irqsave(&dev->lock, flags);
 	peer = fwnet_peer_find_by_node_id(dev, source_node_id, generation);
 	if (!peer) {
 		retval = -ENOENT;
 		goto fail;
 	}
 	pd = fwnet_pd_find(peer, datagram_label);
 	if (pd == NULL) {
 		while (peer->pdg_size >= FWNET_MAX_FRAGMENTS) {
 			/* remove the oldest */
 			fwnet_pd_delete(list_first_entry(&peer->pd_list,
 				struct fwnet_partial_datagram, pd_link));
 			peer->pdg_size--;
 		}
 		pd = fwnet_pd_new(net, peer, datagram_label,
 				  dg_size, buf, fg_off, len);
 		if (pd == NULL) {
 			retval = -ENOMEM;
 			goto fail;
 		}
 		peer->pdg_size++;
 	} else {
 		if (fwnet_frag_overlap(pd, fg_off, len) ||
 		    pd->datagram_size != dg_size) {
 			/*
 			 * Differing datagram sizes or overlapping fragments,
 			 * discard old datagram and start a new one.
 			 */
 			fwnet_pd_delete(pd);
 			pd = fwnet_pd_new(net, peer, datagram_label,
 					  dg_size, buf, fg_off, len);
 			if (pd == NULL) {
 				peer->pdg_size--;
 				retval = -ENOMEM;
 				goto fail;
 			}
 		} else {
 			if (!fwnet_pd_update(peer, pd, buf, fg_off, len)) {
 				/*
 				 * Couldn't save off fragment anyway
 				 * so might as well obliterate the
 				 * datagram now.
 				 */
 				fwnet_pd_delete(pd);
 				peer->pdg_size--;
 				retval = -ENOMEM;
 				goto fail;
 			}
 		}
 	} /* new datagram or add to existing one */
 	if (lf == RFC2374_HDR_FIRSTFRAG)
 		pd->ether_type = ether_type;
 	if (fwnet_pd_is_complete(pd)) {
 		ether_type = pd->ether_type;
 		peer->pdg_size--;
 		skb = skb_get(pd->skb);
 		fwnet_pd_delete(pd);
 		spin_unlock_irqrestore(&dev->lock, flags);
 		return fwnet_finish_incoming_packet(net, skb, source_node_id,
 						    false, ether_type);
 	}
 	/*
 	 * Datagram is not complete, we're done for the
 	 * moment.
 	 */
 	retval = 0;
  fail:
 	spin_unlock_irqrestore(&dev->lock, flags);
 	return retval;
 }
 static void fwnet_receive_packet(struct fw_card *card, struct fw_request *r,
 		int tcode, int destination, int source, int generation,
 		unsigned long long offset, void *payload, size_t length,
 		void *callback_data)
 {
 	struct fwnet_device *dev = callback_data;
 	int rcode;
 	if (destination == IEEE1394_ALL_NODES) {
 		kfree(r);
 		return;
 	}
 	if (offset != dev->handler.offset)
 		rcode = RCODE_ADDRESS_ERROR;
 	else if (tcode != TCODE_WRITE_BLOCK_REQUEST)
 		rcode = RCODE_TYPE_ERROR;
 	else if (fwnet_incoming_packet(dev, payload, length,
 				       source, generation, false) != 0) {
 		fw_error("Incoming packet failure\n");
 		rcode = RCODE_CONFLICT_ERROR;
 	} else
 		rcode = RCODE_COMPLETE;
 	fw_send_response(card, r, rcode);
 }
 static void fwnet_receive_broadcast(struct fw_iso_context *context,
 		u32 cycle, size_t header_length, void *header, void *data)
 {
 	struct fwnet_device *dev;
 	struct fw_iso_packet packet;
 	struct fw_card *card;
 	__be16 *hdr_ptr;
 	__be32 *buf_ptr;
 	int retval;
 	u32 length;
 	u16 source_node_id;
 	u32 specifier_id;
 	u32 ver;
 	unsigned long offset;
 	unsigned long flags;
 	dev = data;
 	card = dev->card;
 	hdr_ptr = header;
 	length = be16_to_cpup(hdr_ptr);
 	spin_lock_irqsave(&dev->lock, flags);
 	offset = dev->rcv_buffer_size * dev->broadcast_rcv_next_ptr;
 	buf_ptr = dev->broadcast_rcv_buffer_ptrs[dev->broadcast_rcv_next_ptr++];
 	if (dev->broadcast_rcv_next_ptr == dev->num_broadcast_rcv_ptrs)
 		dev->broadcast_rcv_next_ptr = 0;
 	spin_unlock_irqrestore(&dev->lock, flags);
 	specifier_id =    (be32_to_cpu(buf_ptr[0]) & 0xffff) << 8
 			| (be32_to_cpu(buf_ptr[1]) & 0xff000000) >> 24;
 	ver = be32_to_cpu(buf_ptr[1]) & 0xffffff;
 	source_node_id = be32_to_cpu(buf_ptr[0]) >> 16;
 	if (specifier_id == IANA_SPECIFIER_ID && ver == RFC2734_SW_VERSION) {
 		buf_ptr += 2;
 		length -= IEEE1394_GASP_HDR_SIZE;
 		fwnet_incoming_packet(dev, buf_ptr, length,
 				      source_node_id, -1, true);
 	}
 	packet.payload_length = dev->rcv_buffer_size;
 	packet.interrupt = 1;
 	packet.skip = 0;
 	packet.tag = 3;
 	packet.sy = 0;
 	packet.header_length = IEEE1394_GASP_HDR_SIZE;
 	spin_lock_irqsave(&dev->lock, flags);
 	retval = fw_iso_context_queue(dev->broadcast_rcv_context, &packet,
 				      &dev->broadcast_rcv_buffer, offset);
 	spin_unlock_irqrestore(&dev->lock, flags);
-	if (retval < 0)
+	if (retval >= 0)
+		fw_iso_context_queue_flush(dev->broadcast_rcv_context);
+	else
 		fw_error("requeue failed\n");
 }
 static struct kmem_cache *fwnet_packet_task_cache;
 static void fwnet_free_ptask(struct fwnet_packet_task *ptask)
 {
 	dev_kfree_skb_any(ptask->skb);
 	kmem_cache_free(fwnet_packet_task_cache, ptask);
 }
 /* Caller must hold dev->lock. */
 static void dec_queued_datagrams(struct fwnet_device *dev)
 {
 	if (--dev->queued_datagrams == FWNET_MIN_QUEUED_DATAGRAMS)
 		netif_wake_queue(dev->netdev);
 }
 static int fwnet_send_packet(struct fwnet_packet_task *ptask);
 static void fwnet_transmit_packet_done(struct fwnet_packet_task *ptask)
 {
 	struct fwnet_device *dev = ptask->dev;
 	struct sk_buff *skb = ptask->skb;
 	unsigned long flags;
 	bool free;
 	spin_lock_irqsave(&dev->lock, flags);
 	ptask->outstanding_pkts--;
 	/* Check whether we or the networking TX soft-IRQ is last user. */
 	free = (ptask->outstanding_pkts == 0 && ptask->enqueued);
 	if (free)
 		dec_queued_datagrams(dev);
 	if (ptask->outstanding_pkts == 0) {
 		dev->netdev->stats.tx_packets++;
 		dev->netdev->stats.tx_bytes += skb->len;
 	}
 	spin_unlock_irqrestore(&dev->lock, flags);
 	if (ptask->outstanding_pkts > 0) {
 		u16 dg_size;
 		u16 fg_off;
 		u16 datagram_label;
 		u16 lf;
 		/* Update the ptask to point to the next fragment and send it */
 		lf = fwnet_get_hdr_lf(&ptask->hdr);
 		switch (lf) {
 		case RFC2374_HDR_LASTFRAG:
 		case RFC2374_HDR_UNFRAG:
 		default:
 			fw_error("Outstanding packet %x lf %x, header %x,%x\n",
 				 ptask->outstanding_pkts, lf, ptask->hdr.w0,
 				 ptask->hdr.w1);
 			BUG();
 		case RFC2374_HDR_FIRSTFRAG:
 			/* Set frag type here for future interior fragments */
 			dg_size = fwnet_get_hdr_dg_size(&ptask->hdr);
 			fg_off = ptask->max_payload - RFC2374_FRAG_HDR_SIZE;
 			datagram_label = fwnet_get_hdr_dgl(&ptask->hdr);
 			break;
 		case RFC2374_HDR_INTFRAG:
 			dg_size = fwnet_get_hdr_dg_size(&ptask->hdr);
 			fg_off = fwnet_get_hdr_fg_off(&ptask->hdr)
 				  + ptask->max_payload - RFC2374_FRAG_HDR_SIZE;
 			datagram_label = fwnet_get_hdr_dgl(&ptask->hdr);
 			break;
 		}
 		skb_pull(skb, ptask->max_payload);
 		if (ptask->outstanding_pkts > 1) {
 			fwnet_make_sf_hdr(&ptask->hdr, RFC2374_HDR_INTFRAG,
 					  dg_size, fg_off, datagram_label);
 		} else {
 			fwnet_make_sf_hdr(&ptask->hdr, RFC2374_HDR_LASTFRAG,
 					  dg_size, fg_off, datagram_label);
 			ptask->max_payload = skb->len + RFC2374_FRAG_HDR_SIZE;
 		}
 		fwnet_send_packet(ptask);
 	}
 	if (free)
 		fwnet_free_ptask(ptask);
 }
 static void fwnet_transmit_packet_failed(struct fwnet_packet_task *ptask)
 {
 	struct fwnet_device *dev = ptask->dev;
 	unsigned long flags;
 	bool free;
 	spin_lock_irqsave(&dev->lock, flags);
 	/* One fragment failed; don't try to send remaining fragments. */
 	ptask->outstanding_pkts = 0;
 	/* Check whether we or the networking TX soft-IRQ is last user. */
 	free = ptask->enqueued;
 	if (free)
 		dec_queued_datagrams(dev);
 	dev->netdev->stats.tx_dropped++;
 	dev->netdev->stats.tx_errors++;
 	spin_unlock_irqrestore(&dev->lock, flags);
 	if (free)
 		fwnet_free_ptask(ptask);
 }
 static void fwnet_write_complete(struct fw_card *card, int rcode,
 				 void *payload, size_t length, void *data)
 {
 	struct fwnet_packet_task *ptask = data;
 	static unsigned long j;
 	static int last_rcode, errors_skipped;
 	if (rcode == RCODE_COMPLETE) {
 		fwnet_transmit_packet_done(ptask);
 	} else {
 		fwnet_transmit_packet_failed(ptask);
 		if (printk_timed_ratelimit(&j,  1000) || rcode != last_rcode) {
 			fw_error("fwnet_write_complete: "
 				"failed: %x (skipped %d)\n", rcode, errors_skipped);
 			errors_skipped = 0;
 			last_rcode = rcode;
 		} else
 			errors_skipped++;
 	}
 }
 static int fwnet_send_packet(struct fwnet_packet_task *ptask)
 {
 	struct fwnet_device *dev;
 	unsigned tx_len;
 	struct rfc2734_header *bufhdr;
 	unsigned long flags;
 	bool free;
 	dev = ptask->dev;
 	tx_len = ptask->max_payload;
 	switch (fwnet_get_hdr_lf(&ptask->hdr)) {
 	case RFC2374_HDR_UNFRAG:
 		bufhdr = (struct rfc2734_header *)
 				skb_push(ptask->skb, RFC2374_UNFRAG_HDR_SIZE);
 		put_unaligned_be32(ptask->hdr.w0, &bufhdr->w0);
 		break;
 	case RFC2374_HDR_FIRSTFRAG:
 	case RFC2374_HDR_INTFRAG:
 	case RFC2374_HDR_LASTFRAG:
 		bufhdr = (struct rfc2734_header *)
 				skb_push(ptask->skb, RFC2374_FRAG_HDR_SIZE);
 		put_unaligned_be32(ptask->hdr.w0, &bufhdr->w0);
 		put_unaligned_be32(ptask->hdr.w1, &bufhdr->w1);
 		break;
 	default:
 		BUG();
 	}
 	if (ptask->dest_node == IEEE1394_ALL_NODES) {
 		u8 *p;
 		int generation;
 		int node_id;
 		/* ptask->generation may not have been set yet */
 		generation = dev->card->generation;
 		smp_rmb();
 		node_id = dev->card->node_id;
 		p = skb_push(ptask->skb, 8);
 		put_unaligned_be32(node_id << 16 | IANA_SPECIFIER_ID >> 8, p);
 		put_unaligned_be32((IANA_SPECIFIER_ID & 0xff) << 24
 						| RFC2734_SW_VERSION, &p[4]);
 		/* We should not transmit if broadcast_channel.valid == 0. */
 		fw_send_request(dev->card, &ptask->transaction,
 				TCODE_STREAM_DATA,
 				fw_stream_packet_destination_id(3,
 						IEEE1394_BROADCAST_CHANNEL, 0),
 				generation, SCODE_100, 0ULL, ptask->skb->data,
 				tx_len + 8, fwnet_write_complete, ptask);
 		spin_lock_irqsave(&dev->lock, flags);
 		/* If the AT tasklet already ran, we may be last user. */
 		free = (ptask->outstanding_pkts == 0 && !ptask->enqueued);
 		if (!free)
 			ptask->enqueued = true;
 		else
 			dec_queued_datagrams(dev);
 		spin_unlock_irqrestore(&dev->lock, flags);
 		goto out;
 	}
 	fw_send_request(dev->card, &ptask->transaction,
 			TCODE_WRITE_BLOCK_REQUEST, ptask->dest_node,
 			ptask->generation, ptask->speed, ptask->fifo_addr,
 			ptask->skb->data, tx_len, fwnet_write_complete, ptask);
 	spin_lock_irqsave(&dev->lock, flags);
 	/* If the AT tasklet already ran, we may be last user. */
 	free = (ptask->outstanding_pkts == 0 && !ptask->enqueued);
 	if (!free)
 		ptask->enqueued = true;
 	else
 		dec_queued_datagrams(dev);
 	spin_unlock_irqrestore(&dev->lock, flags);
 	dev->netdev->trans_start = jiffies;
  out:
 	if (free)
 		fwnet_free_ptask(ptask);
 	return 0;
 }
 static int fwnet_broadcast_start(struct fwnet_device *dev)
 {
 	struct fw_iso_context *context;
 	int retval;
 	unsigned num_packets;
 	unsigned max_receive;
 	struct fw_iso_packet packet;
 	unsigned long offset;
 	unsigned u;
 	if (dev->local_fifo == FWNET_NO_FIFO_ADDR) {
 		/* outside OHCI posted write area? */
 		static const struct fw_address_region region = {
 			.start = 0xffff00000000ULL,
 			.end   = CSR_REGISTER_BASE,
 		};
 		dev->handler.length = 4096;
 		dev->handler.address_callback = fwnet_receive_packet;
 		dev->handler.callback_data = dev;
 		retval = fw_core_add_address_handler(&dev->handler, &region);
 		if (retval < 0)
 			goto failed_initial;
 		dev->local_fifo = dev->handler.offset;
 	}
 	max_receive = 1U << (dev->card->max_receive + 1);
 	num_packets = (FWNET_ISO_PAGE_COUNT * PAGE_SIZE) / max_receive;
 	if (!dev->broadcast_rcv_context) {
 		void **ptrptr;
 		context = fw_iso_context_create(dev->card,
 		    FW_ISO_CONTEXT_RECEIVE, IEEE1394_BROADCAST_CHANNEL,
 		    dev->card->link_speed, 8, fwnet_receive_broadcast, dev);
 		if (IS_ERR(context)) {
 			retval = PTR_ERR(context);
 			goto failed_context_create;
 		}
 		retval = fw_iso_buffer_init(&dev->broadcast_rcv_buffer,
 		    dev->card, FWNET_ISO_PAGE_COUNT, DMA_FROM_DEVICE);
 		if (retval < 0)
 			goto failed_buffer_init;
 		ptrptr = kmalloc(sizeof(void *) * num_packets, GFP_KERNEL);
 		if (!ptrptr) {
 			retval = -ENOMEM;
 			goto failed_ptrs_alloc;
 		}
 		dev->broadcast_rcv_buffer_ptrs = ptrptr;
 		for (u = 0; u < FWNET_ISO_PAGE_COUNT; u++) {
 			void *ptr;
 			unsigned v;
 			ptr = kmap(dev->broadcast_rcv_buffer.pages[u]);
 			for (v = 0; v < num_packets / FWNET_ISO_PAGE_COUNT; v++)
 				*ptrptr++ = (void *)
 						((char *)ptr + v * max_receive);
 		}
 		dev->broadcast_rcv_context = context;
 	} else {
 		context = dev->broadcast_rcv_context;
 	}
 	packet.payload_length = max_receive;
 	packet.interrupt = 1;
 	packet.skip = 0;
 	packet.tag = 3;
 	packet.sy = 0;
 	packet.header_length = IEEE1394_GASP_HDR_SIZE;
 	offset = 0;
 	for (u = 0; u < num_packets; u++) {
 		retval = fw_iso_context_queue(context, &packet,
 				&dev->broadcast_rcv_buffer, offset);
 		if (retval < 0)
 			goto failed_rcv_queue;
 		offset += max_receive;
 	}
 	dev->num_broadcast_rcv_ptrs = num_packets;
 	dev->rcv_buffer_size = max_receive;
 	dev->broadcast_rcv_next_ptr = 0U;
 	retval = fw_iso_context_start(context, -1, 0,
 			FW_ISO_CONTEXT_MATCH_ALL_TAGS); /* ??? sync */
 	if (retval < 0)
 		goto failed_rcv_queue;
 	/* FIXME: adjust it according to the min. speed of all known peers? */
 	dev->broadcast_xmt_max_payload = IEEE1394_MAX_PAYLOAD_S100
 			- IEEE1394_GASP_HDR_SIZE - RFC2374_UNFRAG_HDR_SIZE;
 	dev->broadcast_state = FWNET_BROADCAST_RUNNING;
 	return 0;
  failed_rcv_queue:
 	kfree(dev->broadcast_rcv_buffer_ptrs);
 	dev->broadcast_rcv_buffer_ptrs = NULL;
  failed_ptrs_alloc:
 	fw_iso_buffer_destroy(&dev->broadcast_rcv_buffer, dev->card);
  failed_buffer_init:
 	fw_iso_context_destroy(context);
 	dev->broadcast_rcv_context = NULL;
  failed_context_create:
 	fw_core_remove_address_handler(&dev->handler);
  failed_initial:
 	dev->local_fifo = FWNET_NO_FIFO_ADDR;
 	return retval;
 }
 static void set_carrier_state(struct fwnet_device *dev)
 {
 	if (dev->peer_count > 1)
 		netif_carrier_on(dev->netdev);
 	else
 		netif_carrier_off(dev->netdev);
 }
 /* ifup */
 static int fwnet_open(struct net_device *net)
 {
 	struct fwnet_device *dev = netdev_priv(net);
 	int ret;
 	if (dev->broadcast_state == FWNET_BROADCAST_ERROR) {
 		ret = fwnet_broadcast_start(dev);
 		if (ret)
 			return ret;
 	}
 	netif_start_queue(net);
 	spin_lock_irq(&dev->lock);
 	set_carrier_state(dev);
 	spin_unlock_irq(&dev->lock);
 	return 0;
 }
 /* ifdown */
 static int fwnet_stop(struct net_device *net)
 {
 	netif_stop_queue(net);
 	/* Deallocate iso context for use by other applications? */
 	return 0;
 }
 static netdev_tx_t fwnet_tx(struct sk_buff *skb, struct net_device *net)
 {
 	struct fwnet_header hdr_buf;
 	struct fwnet_device *dev = netdev_priv(net);
 	__be16 proto;
 	u16 dest_node;
 	unsigned max_payload;
 	u16 dg_size;
 	u16 *datagram_label_ptr;
 	struct fwnet_packet_task *ptask;
 	struct fwnet_peer *peer;
 	unsigned long flags;
 	spin_lock_irqsave(&dev->lock, flags);
 	/* Can this happen? */
 	if (netif_queue_stopped(dev->netdev)) {
 		spin_unlock_irqrestore(&dev->lock, flags);
 		return NETDEV_TX_BUSY;
 	}
 	ptask = kmem_cache_alloc(fwnet_packet_task_cache, GFP_ATOMIC);
 	if (ptask == NULL)
 		goto fail;
 	skb = skb_share_check(skb, GFP_ATOMIC);
 	if (!skb)
 		goto fail;
 	/*
 	 * Make a copy of the driver-specific header.
 	 * We might need to rebuild the header on tx failure.
 	 */
 	memcpy(&hdr_buf, skb->data, sizeof(hdr_buf));
 	skb_pull(skb, sizeof(hdr_buf));
 	proto = hdr_buf.h_proto;
 	dg_size = skb->len;
 	/*
 	 * Set the transmission type for the packet.  ARP packets and IP
 	 * broadcast packets are sent via GASP.
 	 */
 	if (memcmp(hdr_buf.h_dest, net->broadcast, FWNET_ALEN) == 0
 	    || proto == htons(ETH_P_ARP)
 	    || (proto == htons(ETH_P_IP)
 		&& IN_MULTICAST(ntohl(ip_hdr(skb)->daddr)))) {
 		max_payload        = dev->broadcast_xmt_max_payload;
 		datagram_label_ptr = &dev->broadcast_xmt_datagramlabel;
 		ptask->fifo_addr   = FWNET_NO_FIFO_ADDR;
 		ptask->generation  = 0;
 		ptask->dest_node   = IEEE1394_ALL_NODES;
 		ptask->speed       = SCODE_100;
 	} else {
 		__be64 guid = get_unaligned((__be64 *)hdr_buf.h_dest);
 		u8 generation;
 		peer = fwnet_peer_find_by_guid(dev, be64_to_cpu(guid));
 		if (!peer || peer->fifo == FWNET_NO_FIFO_ADDR)
 			goto fail;
 		generation         = peer->generation;
 		dest_node          = peer->node_id;
 		max_payload        = peer->max_payload;
 		datagram_label_ptr = &peer->datagram_label;
 		ptask->fifo_addr   = peer->fifo;
 		ptask->generation  = generation;
 		ptask->dest_node   = dest_node;
 		ptask->speed       = peer->speed;
 	}
 	/* If this is an ARP packet, convert it */
 	if (proto == htons(ETH_P_ARP)) {
 		struct arphdr *arp = (struct arphdr *)skb->data;
 		unsigned char *arp_ptr = (unsigned char *)(arp + 1);
 		struct rfc2734_arp *arp1394 = (struct rfc2734_arp *)skb->data;
 		__be32 ipaddr;
 		ipaddr = get_unaligned((__be32 *)(arp_ptr + FWNET_ALEN));
 		arp1394->hw_addr_len    = RFC2734_HW_ADDR_LEN;
 		arp1394->max_rec        = dev->card->max_receive;
 		arp1394->sspd		= dev->card->link_speed;
 		put_unaligned_be16(dev->local_fifo >> 32,
 				   &arp1394->fifo_hi);
 		put_unaligned_be32(dev->local_fifo & 0xffffffff,
 				   &arp1394->fifo_lo);
 		put_unaligned(ipaddr, &arp1394->sip);
 	}
 	ptask->hdr.w0 = 0;
 	ptask->hdr.w1 = 0;
 	ptask->skb = skb;
 	ptask->dev = dev;
 	/* Does it all fit in one packet? */
 	if (dg_size <= max_payload) {
 		fwnet_make_uf_hdr(&ptask->hdr, ntohs(proto));
 		ptask->outstanding_pkts = 1;
 		max_payload = dg_size + RFC2374_UNFRAG_HDR_SIZE;
 	} else {
 		u16 datagram_label;
 		max_payload -= RFC2374_FRAG_OVERHEAD;
 		datagram_label = (*datagram_label_ptr)++;
 		fwnet_make_ff_hdr(&ptask->hdr, ntohs(proto), dg_size,
 				  datagram_label);
 		ptask->outstanding_pkts = DIV_ROUND_UP(dg_size, max_payload);
 		max_payload += RFC2374_FRAG_HDR_SIZE;
 	}
 	if (++dev->queued_datagrams == FWNET_MAX_QUEUED_DATAGRAMS)
 		netif_stop_queue(dev->netdev);
 	spin_unlock_irqrestore(&dev->lock, flags);
 	ptask->max_payload = max_payload;
 	ptask->enqueued    = 0;
 	fwnet_send_packet(ptask);
 	return NETDEV_TX_OK;
  fail:
 	spin_unlock_irqrestore(&dev->lock, flags);
 	if (ptask)
 		kmem_cache_free(fwnet_packet_task_cache, ptask);
 	if (skb != NULL)
 		dev_kfree_skb(skb);
 	net->stats.tx_dropped++;
 	net->stats.tx_errors++;
 	/*
 	 * FIXME: According to a patch from 2003-02-26, "returning non-zero
 	 * causes serious problems" here, allegedly.  Before that patch,
 	 * -ERRNO was returned which is not appropriate under Linux 2.6.
 	 * Perhaps more needs to be done?  Stop the queue in serious
 	 * conditions and restart it elsewhere?
 	 */
 	return NETDEV_TX_OK;
 }
 static int fwnet_change_mtu(struct net_device *net, int new_mtu)
 {
 	if (new_mtu < 68)
 		return -EINVAL;
 	net->mtu = new_mtu;
 	return 0;
 }
 static const struct ethtool_ops fwnet_ethtool_ops = {
 	.get_link	= ethtool_op_get_link,
 };
 static const struct net_device_ops fwnet_netdev_ops = {
 	.ndo_open       = fwnet_open,
 	.ndo_stop	= fwnet_stop,
 	.ndo_start_xmit = fwnet_tx,
 	.ndo_change_mtu = fwnet_change_mtu,
 };
 static void fwnet_init_dev(struct net_device *net)
 {
 	net->header_ops		= &fwnet_header_ops;
 	net->netdev_ops		= &fwnet_netdev_ops;
 	net->watchdog_timeo	= 2 * HZ;
 	net->flags		= IFF_BROADCAST | IFF_MULTICAST;
 	net->features		= NETIF_F_HIGHDMA;
 	net->addr_len		= FWNET_ALEN;
 	net->hard_header_len	= FWNET_HLEN;
 	net->type		= ARPHRD_IEEE1394;
 	net->tx_queue_len	= FWNET_TX_QUEUE_LEN;
 	net->ethtool_ops	= &fwnet_ethtool_ops;
 }
 /* caller must hold fwnet_device_mutex */
 static struct fwnet_device *fwnet_dev_find(struct fw_card *card)
 {
 	struct fwnet_device *dev;
 	list_for_each_entry(dev, &fwnet_device_list, dev_link)
 		if (dev->card == card)
 			return dev;
 	return NULL;
 }
 static int fwnet_add_peer(struct fwnet_device *dev,
 			  struct fw_unit *unit, struct fw_device *device)
 {
 	struct fwnet_peer *peer;
 	peer = kmalloc(sizeof(*peer), GFP_KERNEL);
 	if (!peer)
 		return -ENOMEM;
 	dev_set_drvdata(&unit->device, peer);
 	peer->dev = dev;
 	peer->guid = (u64)device->config_rom[3] << 32 | device->config_rom[4];
 	peer->fifo = FWNET_NO_FIFO_ADDR;
 	peer->ip = 0;
 	INIT_LIST_HEAD(&peer->pd_list);
 	peer->pdg_size = 0;
 	peer->datagram_label = 0;
 	peer->speed = device->max_speed;
 	peer->max_payload = fwnet_max_payload(device->max_rec, peer->speed);
 	peer->generation = device->generation;
 	smp_rmb();
 	peer->node_id = device->node_id;
 	spin_lock_irq(&dev->lock);
 	list_add_tail(&peer->peer_link, &dev->peer_list);
 	dev->peer_count++;
 	set_carrier_state(dev);
 	spin_unlock_irq(&dev->lock);
 	return 0;
 }
 static int fwnet_probe(struct device *_dev)
 {
 	struct fw_unit *unit = fw_unit(_dev);
 	struct fw_device *device = fw_parent_device(unit);
 	struct fw_card *card = device->card;
 	struct net_device *net;
 	bool allocated_netdev = false;
 	struct fwnet_device *dev;
 	unsigned max_mtu;
 	int ret;
 	mutex_lock(&fwnet_device_mutex);
 	dev = fwnet_dev_find(card);
 	if (dev) {
 		net = dev->netdev;
 		goto have_dev;
 	}
 	net = alloc_netdev(sizeof(*dev), "firewire%d", fwnet_init_dev);
 	if (net == NULL) {
 		ret = -ENOMEM;
 		goto out;
 	}
 	allocated_netdev = true;
 	SET_NETDEV_DEV(net, card->device);
 	dev = netdev_priv(net);
 	spin_lock_init(&dev->lock);
 	dev->broadcast_state = FWNET_BROADCAST_ERROR;
 	dev->broadcast_rcv_context = NULL;
 	dev->broadcast_xmt_max_payload = 0;
 	dev->broadcast_xmt_datagramlabel = 0;
 	dev->local_fifo = FWNET_NO_FIFO_ADDR;
 	dev->queued_datagrams = 0;
 	INIT_LIST_HEAD(&dev->peer_list);
 	dev->card = card;
 	dev->netdev = net;
 	/*
 	 * Use the RFC 2734 default 1500 octets or the maximum payload
 	 * as initial MTU
 	 */
 	max_mtu = (1 << (card->max_receive + 1))
 		  - sizeof(struct rfc2734_header) - IEEE1394_GASP_HDR_SIZE;
 	net->mtu = min(1500U, max_mtu);
 	/* Set our hardware address while we're at it */
 	put_unaligned_be64(card->guid, net->dev_addr);
 	put_unaligned_be64(~0ULL, net->broadcast);
 	ret = register_netdev(net);
 	if (ret) {
 		fw_error("Cannot register the driver\n");
 		goto out;
 	}
 	list_add_tail(&dev->dev_link, &fwnet_device_list);
 	fw_notify("%s: IPv4 over FireWire on device %016llx\n",
 		  net->name, (unsigned long long)card->guid);
  have_dev:
 	ret = fwnet_add_peer(dev, unit, device);
 	if (ret && allocated_netdev) {
 		unregister_netdev(net);
 		list_del(&dev->dev_link);
 	}
  out:
 	if (ret && allocated_netdev)
 		free_netdev(net);
 	mutex_unlock(&fwnet_device_mutex);
 	return ret;
 }
 static void fwnet_remove_peer(struct fwnet_peer *peer, struct fwnet_device *dev)
 {
 	struct fwnet_partial_datagram *pd, *pd_next;
 	spin_lock_irq(&dev->lock);
 	list_del(&peer->peer_link);
 	dev->peer_count--;
 	set_carrier_state(dev);
 	spin_unlock_irq(&dev->lock);
 	list_for_each_entry_safe(pd, pd_next, &peer->pd_list, pd_link)
 		fwnet_pd_delete(pd);
 	kfree(peer);
 }
 static int fwnet_remove(struct device *_dev)
 {
 	struct fwnet_peer *peer = dev_get_drvdata(_dev);
 	struct fwnet_device *dev = peer->dev;
 	struct net_device *net;
 	int i;
 	mutex_lock(&fwnet_device_mutex);
 	net = dev->netdev;
 	if (net && peer->ip)
 		arp_invalidate(net, peer->ip);
 	fwnet_remove_peer(peer, dev);
 	if (list_empty(&dev->peer_list)) {
 		unregister_netdev(net);
 		if (dev->local_fifo != FWNET_NO_FIFO_ADDR)
 			fw_core_remove_address_handler(&dev->handler);
 		if (dev->broadcast_rcv_context) {
 			fw_iso_context_stop(dev->broadcast_rcv_context);
 			fw_iso_buffer_destroy(&dev->broadcast_rcv_buffer,
 					      dev->card);
 			fw_iso_context_destroy(dev->broadcast_rcv_context);
 		}
 		for (i = 0; dev->queued_datagrams && i < 5; i++)
 			ssleep(1);
 		WARN_ON(dev->queued_datagrams);
 		list_del(&dev->dev_link);
 		free_netdev(net);
 	}
 	mutex_unlock(&fwnet_device_mutex);
 	return 0;
 }
 /*
  * FIXME abort partially sent fragmented datagrams,
  * discard partially received fragmented datagrams
  */
 static void fwnet_update(struct fw_unit *unit)
 {
 	struct fw_device *device = fw_parent_device(unit);
 	struct fwnet_peer *peer = dev_get_drvdata(&unit->device);
 	int generation;
 	generation = device->generation;
 	spin_lock_irq(&peer->dev->lock);
 	peer->node_id    = device->node_id;
 	peer->generation = generation;
 	spin_unlock_irq(&peer->dev->lock);
 }
 static const struct ieee1394_device_id fwnet_id_table[] = {
 	{
 		.match_flags  = IEEE1394_MATCH_SPECIFIER_ID |
 				IEEE1394_MATCH_VERSION,
 		.specifier_id = IANA_SPECIFIER_ID,
 		.version      = RFC2734_SW_VERSION,
 	},
 	{ }
 };
 static struct fw_driver fwnet_driver = {
 	.driver = {
 		.owner  = THIS_MODULE,
 		.name   = "net",
 		.bus    = &fw_bus_type,
 		.probe  = fwnet_probe,
 		.remove = fwnet_remove,
 	},
 	.update   = fwnet_update,
 	.id_table = fwnet_id_table,
 };
 static const u32 rfc2374_unit_directory_data[] = {
 	0x00040000,	/* directory_length		*/
 	0x1200005e,	/* unit_specifier_id: IANA	*/
 	0x81000003,	/* textual descriptor offset	*/
 	0x13000001,	/* unit_sw_version: RFC 2734	*/
 	0x81000005,	/* textual descriptor offset	*/
 	0x00030000,	/* descriptor_length		*/
 	0x00000000,	/* text				*/
 	0x00000000,	/* minimal ASCII, en		*/
 	0x49414e41,	/* I A N A			*/
 	0x00030000,	/* descriptor_length		*/
 	0x00000000,	/* text				*/
 	0x00000000,	/* minimal ASCII, en		*/
 	0x49507634,	/* I P v 4			*/
 };
 static struct fw_descriptor rfc2374_unit_directory = {
 	.length = ARRAY_SIZE(rfc2374_unit_directory_data),
 	.key    = (CSR_DIRECTORY | CSR_UNIT) << 24,
 	.data   = rfc2374_unit_directory_data
 };
 static int __init fwnet_init(void)
 {
 	int err;
 	err = fw_core_add_descriptor(&rfc2374_unit_directory);
 	if (err)
 		return err;
 	fwnet_packet_task_cache = kmem_cache_create("packet_task",
 			sizeof(struct fwnet_packet_task), 0, 0, NULL);
 	if (!fwnet_packet_task_cache) {
 		err = -ENOMEM;
 		goto out;
 	}
 	err = driver_register(&fwnet_driver.driver);
 	if (!err)
 		return 0;
 	kmem_cache_destroy(fwnet_packet_task_cache);
 out:
 	fw_core_remove_descriptor(&rfc2374_unit_directory);
 	return err;
 }
 module_init(fwnet_init);
 static void __exit fwnet_cleanup(void)
 {
 	driver_unregister(&fwnet_driver.driver);
 	kmem_cache_destroy(fwnet_packet_task_cache);
 	fw_core_remove_descriptor(&rfc2374_unit_directory);
 }
 module_exit(fwnet_cleanup);
 MODULE_AUTHOR("Jay Fenlason <fenlason@redhat.com>");
 MODULE_DESCRIPTION("IPv4 over IEEE1394 as per RFC 2734");
 MODULE_LICENSE("GPL");
 MODULE_DEVICE_TABLE(ieee1394, fwnet_id_table);

drivers/firewire/ohci.c

Diff comments View file @ 13882a8

 /*
  * Driver for OHCI 1394 controllers
  *
  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software Foundation,
  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  */
 #include <linux/bitops.h>
 #include <linux/bug.h>
 #include <linux/compiler.h>
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/dma-mapping.h>
 #include <linux/firewire.h>
 #include <linux/firewire-constants.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
 #include <linux/list.h>
 #include <linux/mm.h>
 #include <linux/module.h>
 #include <linux/moduleparam.h>
 #include <linux/mutex.h>
 #include <linux/pci.h>
 #include <linux/pci_ids.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
 #include <linux/string.h>
 #include <linux/time.h>
 #include <linux/vmalloc.h>
 #include <asm/byteorder.h>
 #include <asm/page.h>
 #include <asm/system.h>
 #ifdef CONFIG_PPC_PMAC
 #include <asm/pmac_feature.h>
 #endif
 #include "core.h"
 #include "ohci.h"
 #define DESCRIPTOR_OUTPUT_MORE		0
 #define DESCRIPTOR_OUTPUT_LAST		(1 << 12)
 #define DESCRIPTOR_INPUT_MORE		(2 << 12)
 #define DESCRIPTOR_INPUT_LAST		(3 << 12)
 #define DESCRIPTOR_STATUS		(1 << 11)
 #define DESCRIPTOR_KEY_IMMEDIATE	(2 << 8)
 #define DESCRIPTOR_PING			(1 << 7)
 #define DESCRIPTOR_YY			(1 << 6)
 #define DESCRIPTOR_NO_IRQ		(0 << 4)
 #define DESCRIPTOR_IRQ_ERROR		(1 << 4)
 #define DESCRIPTOR_IRQ_ALWAYS		(3 << 4)
 #define DESCRIPTOR_BRANCH_ALWAYS	(3 << 2)
 #define DESCRIPTOR_WAIT			(3 << 0)
 struct descriptor {
 	__le16 req_count;
 	__le16 control;
 	__le32 data_address;
 	__le32 branch_address;
 	__le16 res_count;
 	__le16 transfer_status;
 } __attribute__((aligned(16)));
 #define CONTROL_SET(regs)	(regs)
 #define CONTROL_CLEAR(regs)	((regs) + 4)
 #define COMMAND_PTR(regs)	((regs) + 12)
 #define CONTEXT_MATCH(regs)	((regs) + 16)
 #define AR_BUFFER_SIZE	(32*1024)
 #define AR_BUFFERS_MIN	DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
 /* we need at least two pages for proper list management */
 #define AR_BUFFERS	(AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
 #define MAX_ASYNC_PAYLOAD	4096
 #define MAX_AR_PACKET_SIZE	(16 + MAX_ASYNC_PAYLOAD + 4)
 #define AR_WRAPAROUND_PAGES	DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
 struct ar_context {
 	struct fw_ohci *ohci;
 	struct page *pages[AR_BUFFERS];
 	void *buffer;
 	struct descriptor *descriptors;
 	dma_addr_t descriptors_bus;
 	void *pointer;
 	unsigned int last_buffer_index;
 	u32 regs;
 	struct tasklet_struct tasklet;
 };
 struct context;
 typedef int (*descriptor_callback_t)(struct context *ctx,
 				     struct descriptor *d,
 				     struct descriptor *last);
 /*
  * A buffer that contains a block of DMA-able coherent memory used for
  * storing a portion of a DMA descriptor program.
  */
 struct descriptor_buffer {
 	struct list_head list;
 	dma_addr_t buffer_bus;
 	size_t buffer_size;
 	size_t used;
 	struct descriptor buffer[0];
 };
 struct context {
 	struct fw_ohci *ohci;
 	u32 regs;
 	int total_allocation;
 	bool running;
 	bool flushing;
 	/*
 	 * List of page-sized buffers for storing DMA descriptors.
 	 * Head of list contains buffers in use and tail of list contains
 	 * free buffers.
 	 */
 	struct list_head buffer_list;
 	/*
 	 * Pointer to a buffer inside buffer_list that contains the tail
 	 * end of the current DMA program.
 	 */
 	struct descriptor_buffer *buffer_tail;
 	/*
 	 * The descriptor containing the branch address of the first
 	 * descriptor that has not yet been filled by the device.
 	 */
 	struct descriptor *last;
 	/*
 	 * The last descriptor in the DMA program.  It contains the branch
 	 * address that must be updated upon appending a new descriptor.
 	 */
 	struct descriptor *prev;
 	descriptor_callback_t callback;
 	struct tasklet_struct tasklet;
 };
 #define IT_HEADER_SY(v)          ((v) <<  0)
 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 #define IT_HEADER_TAG(v)         ((v) << 14)
 #define IT_HEADER_SPEED(v)       ((v) << 16)
 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 struct iso_context {
 	struct fw_iso_context base;
 	struct context context;
 	int excess_bytes;
 	void *header;
 	size_t header_length;
 	u8 sync;
 	u8 tags;
 };
 #define CONFIG_ROM_SIZE 1024
 struct fw_ohci {
 	struct fw_card card;
 	__iomem char *registers;
 	int node_id;
 	int generation;
 	int request_generation;	/* for timestamping incoming requests */
 	unsigned quirks;
 	unsigned int pri_req_max;
 	u32 bus_time;
 	bool is_root;
 	bool csr_state_setclear_abdicate;
 	int n_ir;
 	int n_it;
 	/*
 	 * Spinlock for accessing fw_ohci data.  Never call out of
 	 * this driver with this lock held.
 	 */
 	spinlock_t lock;
 	struct mutex phy_reg_mutex;
 	void *misc_buffer;
 	dma_addr_t misc_buffer_bus;
 	struct ar_context ar_request_ctx;
 	struct ar_context ar_response_ctx;
 	struct context at_request_ctx;
 	struct context at_response_ctx;
 	u32 it_context_support;
 	u32 it_context_mask;     /* unoccupied IT contexts */
 	struct iso_context *it_context_list;
 	u64 ir_context_channels; /* unoccupied channels */
 	u32 ir_context_support;
 	u32 ir_context_mask;     /* unoccupied IR contexts */
 	struct iso_context *ir_context_list;
 	u64 mc_channels; /* channels in use by the multichannel IR context */
 	bool mc_allocated;
 	__be32    *config_rom;
 	dma_addr_t config_rom_bus;
 	__be32    *next_config_rom;
 	dma_addr_t next_config_rom_bus;
 	__be32     next_header;
 	__le32    *self_id_cpu;
 	dma_addr_t self_id_bus;
 	struct tasklet_struct bus_reset_tasklet;
 	u32 self_id_buffer[512];
 };
 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 {
 	return container_of(card, struct fw_ohci, card);
 }
 #define IT_CONTEXT_CYCLE_MATCH_ENABLE	0x80000000
 #define IR_CONTEXT_BUFFER_FILL		0x80000000
 #define IR_CONTEXT_ISOCH_HEADER		0x40000000
 #define IR_CONTEXT_CYCLE_MATCH_ENABLE	0x20000000
 #define IR_CONTEXT_MULTI_CHANNEL_MODE	0x10000000
 #define IR_CONTEXT_DUAL_BUFFER_MODE	0x08000000
 #define CONTEXT_RUN	0x8000
 #define CONTEXT_WAKE	0x1000
 #define CONTEXT_DEAD	0x0800
 #define CONTEXT_ACTIVE	0x0400
 #define OHCI1394_MAX_AT_REQ_RETRIES	0xf
 #define OHCI1394_MAX_AT_RESP_RETRIES	0x2
 #define OHCI1394_MAX_PHYS_RESP_RETRIES	0x8
 #define OHCI1394_REGISTER_SIZE		0x800
 #define OHCI_LOOP_COUNT			500
 #define OHCI1394_PCI_HCI_Control	0x40
 #define SELF_ID_BUF_SIZE		0x800
 #define OHCI_TCODE_PHY_PACKET		0x0e
 #define OHCI_VERSION_1_1		0x010010
 static char ohci_driver_name[] = KBUILD_MODNAME;
 #define PCI_DEVICE_ID_AGERE_FW643	0x5901
 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW	0x2380
 #define PCI_DEVICE_ID_TI_TSB12LV22	0x8009
 #define QUIRK_CYCLE_TIMER		1
 #define QUIRK_RESET_PACKET		2
 #define QUIRK_BE_HEADERS		4
 #define QUIRK_NO_1394A			8
 #define QUIRK_NO_MSI			16
 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
 static const struct {
 	unsigned short vendor, device, revision, flags;
 } ohci_quirks[] = {
 	{PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
 		QUIRK_CYCLE_TIMER},
 	{PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
 		QUIRK_BE_HEADERS},
 	{PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
 		QUIRK_NO_MSI},
 	{PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
 		QUIRK_NO_MSI},
 	{PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
 		QUIRK_CYCLE_TIMER},
 	{PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
 		QUIRK_CYCLE_TIMER},
 	{PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
 		QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
 	{PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
 		QUIRK_RESET_PACKET},
 	{PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
 		QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
 };
 /* This overrides anything that was found in ohci_quirks[]. */
 static int param_quirks;
 module_param_named(quirks, param_quirks, int, 0644);
 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
 	", nonatomic cycle timer = "	__stringify(QUIRK_CYCLE_TIMER)
 	", reset packet generation = "	__stringify(QUIRK_RESET_PACKET)
 	", AR/selfID endianess = "	__stringify(QUIRK_BE_HEADERS)
 	", no 1394a enhancements = "	__stringify(QUIRK_NO_1394A)
 	", disable MSI = "		__stringify(QUIRK_NO_MSI)
 	")");
 #define OHCI_PARAM_DEBUG_AT_AR		1
 #define OHCI_PARAM_DEBUG_SELFIDS	2
 #define OHCI_PARAM_DEBUG_IRQS		4
 #define OHCI_PARAM_DEBUG_BUSRESETS	8 /* only effective before chip init */
 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
 static int param_debug;
 module_param_named(debug, param_debug, int, 0644);
 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
 	", AT/AR events = "	__stringify(OHCI_PARAM_DEBUG_AT_AR)
 	", self-IDs = "		__stringify(OHCI_PARAM_DEBUG_SELFIDS)
 	", IRQs = "		__stringify(OHCI_PARAM_DEBUG_IRQS)
 	", busReset events = "	__stringify(OHCI_PARAM_DEBUG_BUSRESETS)
 	", or a combination, or all = -1)");
 static void log_irqs(u32 evt)
 {
 	if (likely(!(param_debug &
 			(OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
 		return;
 	if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
 	    !(evt & OHCI1394_busReset))
 		return;
 	fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
 	    evt & OHCI1394_selfIDComplete	? " selfID"		: "",
 	    evt & OHCI1394_RQPkt		? " AR_req"		: "",
 	    evt & OHCI1394_RSPkt		? " AR_resp"		: "",
 	    evt & OHCI1394_reqTxComplete	? " AT_req"		: "",
 	    evt & OHCI1394_respTxComplete	? " AT_resp"		: "",
 	    evt & OHCI1394_isochRx		? " IR"			: "",
 	    evt & OHCI1394_isochTx		? " IT"			: "",
 	    evt & OHCI1394_postedWriteErr	? " postedWriteErr"	: "",
 	    evt & OHCI1394_cycleTooLong		? " cycleTooLong"	: "",
 	    evt & OHCI1394_cycle64Seconds	? " cycle64Seconds"	: "",
 	    evt & OHCI1394_cycleInconsistent	? " cycleInconsistent"	: "",
 	    evt & OHCI1394_regAccessFail	? " regAccessFail"	: "",
 	    evt & OHCI1394_unrecoverableError	? " unrecoverableError"	: "",
 	    evt & OHCI1394_busReset		? " busReset"		: "",
 	    evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
 		    OHCI1394_RSPkt | OHCI1394_reqTxComplete |
 		    OHCI1394_respTxComplete | OHCI1394_isochRx |
 		    OHCI1394_isochTx | OHCI1394_postedWriteErr |
 		    OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
 		    OHCI1394_cycleInconsistent |
 		    OHCI1394_regAccessFail | OHCI1394_busReset)
 						? " ?"			: "");
 }
 static const char *speed[] = {
 	[0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
 };
 static const char *power[] = {
 	[0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
 	[4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
 };
 static const char port[] = { '.', '-', 'p', 'c', };
 static char _p(u32 *s, int shift)
 {
 	return port[*s >> shift & 3];
 }
 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
 {
 	if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
 		return;
 	fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
 		  self_id_count, generation, node_id);
 	for (; self_id_count--; ++s)
 		if ((*s & 1 << 23) == 0)
 			fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
 			    "%s gc=%d %s %s%s%s\n",
 			    *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
 			    speed[*s >> 14 & 3], *s >> 16 & 63,
 			    power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
 			    *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
 		else
 			fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
 			    *s, *s >> 24 & 63,
 			    _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
 			    _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
 }
 static const char *evts[] = {
 	[0x00] = "evt_no_status",	[0x01] = "-reserved-",
 	[0x02] = "evt_long_packet",	[0x03] = "evt_missing_ack",
 	[0x04] = "evt_underrun",	[0x05] = "evt_overrun",
 	[0x06] = "evt_descriptor_read",	[0x07] = "evt_data_read",
 	[0x08] = "evt_data_write",	[0x09] = "evt_bus_reset",
 	[0x0a] = "evt_timeout",		[0x0b] = "evt_tcode_err",
 	[0x0c] = "-reserved-",		[0x0d] = "-reserved-",
 	[0x0e] = "evt_unknown",		[0x0f] = "evt_flushed",
 	[0x10] = "-reserved-",		[0x11] = "ack_complete",
 	[0x12] = "ack_pending ",	[0x13] = "-reserved-",
 	[0x14] = "ack_busy_X",		[0x15] = "ack_busy_A",
 	[0x16] = "ack_busy_B",		[0x17] = "-reserved-",
 	[0x18] = "-reserved-",		[0x19] = "-reserved-",
 	[0x1a] = "-reserved-",		[0x1b] = "ack_tardy",
 	[0x1c] = "-reserved-",		[0x1d] = "ack_data_error",
 	[0x1e] = "ack_type_error",	[0x1f] = "-reserved-",
 	[0x20] = "pending/cancelled",
 };
 static const char *tcodes[] = {
 	[0x0] = "QW req",		[0x1] = "BW req",
 	[0x2] = "W resp",		[0x3] = "-reserved-",
 	[0x4] = "QR req",		[0x5] = "BR req",
 	[0x6] = "QR resp",		[0x7] = "BR resp",
 	[0x8] = "cycle start",		[0x9] = "Lk req",
 	[0xa] = "async stream packet",	[0xb] = "Lk resp",
 	[0xc] = "-reserved-",		[0xd] = "-reserved-",
 	[0xe] = "link internal",	[0xf] = "-reserved-",
 };
 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
 {
 	int tcode = header[0] >> 4 & 0xf;
 	char specific[12];
 	if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
 		return;
 	if (unlikely(evt >= ARRAY_SIZE(evts)))
 			evt = 0x1f;
 	if (evt == OHCI1394_evt_bus_reset) {
 		fw_notify("A%c evt_bus_reset, generation %d\n",
 		    dir, (header[2] >> 16) & 0xff);
 		return;
 	}
 	switch (tcode) {
 	case 0x0: case 0x6: case 0x8:
 		snprintf(specific, sizeof(specific), " = %08x",
 			 be32_to_cpu((__force __be32)header[3]));
 		break;
 	case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
 		snprintf(specific, sizeof(specific), " %x,%x",
 			 header[3] >> 16, header[3] & 0xffff);
 		break;
 	default:
 		specific[0] = '\0';
 	}
 	switch (tcode) {
 	case 0xa:
 		fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
 		break;
 	case 0xe:
 		fw_notify("A%c %s, PHY %08x %08x\n",
 			  dir, evts[evt], header[1], header[2]);
 		break;
 	case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
 		fw_notify("A%c spd %x tl %02x, "
 		    "%04x -> %04x, %s, "
 		    "%s, %04x%08x%s\n",
 		    dir, speed, header[0] >> 10 & 0x3f,
 		    header[1] >> 16, header[0] >> 16, evts[evt],
 		    tcodes[tcode], header[1] & 0xffff, header[2], specific);
 		break;
 	default:
 		fw_notify("A%c spd %x tl %02x, "
 		    "%04x -> %04x, %s, "
 		    "%s%s\n",
 		    dir, speed, header[0] >> 10 & 0x3f,
 		    header[1] >> 16, header[0] >> 16, evts[evt],
 		    tcodes[tcode], specific);
 	}
 }
 #else
 #define param_debug 0
 static inline void log_irqs(u32 evt) {}
 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 {
 	writel(data, ohci->registers + offset);
 }
 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 {
 	return readl(ohci->registers + offset);
 }
 static inline void flush_writes(const struct fw_ohci *ohci)
 {
 	/* Do a dummy read to flush writes. */
 	reg_read(ohci, OHCI1394_Version);
 }
 static int read_phy_reg(struct fw_ohci *ohci, int addr)
 {
 	u32 val;
 	int i;
 	reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 	for (i = 0; i < 3 + 100; i++) {
 		val = reg_read(ohci, OHCI1394_PhyControl);
 		if (val & OHCI1394_PhyControl_ReadDone)
 			return OHCI1394_PhyControl_ReadData(val);
 		/*
 		 * Try a few times without waiting.  Sleeping is necessary
 		 * only when the link/PHY interface is busy.
 		 */
 		if (i >= 3)
 			msleep(1);
 	}
 	fw_error("failed to read phy reg\n");
 	return -EBUSY;
 }
 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
 {
 	int i;
 	reg_write(ohci, OHCI1394_PhyControl,
 		  OHCI1394_PhyControl_Write(addr, val));
 	for (i = 0; i < 3 + 100; i++) {
 		val = reg_read(ohci, OHCI1394_PhyControl);
 		if (!(val & OHCI1394_PhyControl_WritePending))
 			return 0;
 		if (i >= 3)
 			msleep(1);
 	}
 	fw_error("failed to write phy reg\n");
 	return -EBUSY;
 }
 static int update_phy_reg(struct fw_ohci *ohci, int addr,
 			  int clear_bits, int set_bits)
 {
 	int ret = read_phy_reg(ohci, addr);
 	if (ret < 0)
 		return ret;
 	/*
 	 * The interrupt status bits are cleared by writing a one bit.
 	 * Avoid clearing them unless explicitly requested in set_bits.
 	 */
 	if (addr == 5)
 		clear_bits |= PHY_INT_STATUS_BITS;
 	return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
 }
 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
 {
 	int ret;
 	ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
 	if (ret < 0)
 		return ret;
 	return read_phy_reg(ohci, addr);
 }
 static int ohci_read_phy_reg(struct fw_card *card, int addr)
 {
 	struct fw_ohci *ohci = fw_ohci(card);
 	int ret;
 	mutex_lock(&ohci->phy_reg_mutex);
 	ret = read_phy_reg(ohci, addr);
 	mutex_unlock(&ohci->phy_reg_mutex);
 	return ret;
 }
 static int ohci_update_phy_reg(struct fw_card *card, int addr,
 			       int clear_bits, int set_bits)
 {
 	struct fw_ohci *ohci = fw_ohci(card);
 	int ret;
 	mutex_lock(&ohci->phy_reg_mutex);
 	ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
 	mutex_unlock(&ohci->phy_reg_mutex);
 	return ret;
 }
 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
 {
 	return page_private(ctx->pages[i]);
 }
 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
 {
 	struct descriptor *d;
 	d = &ctx->descriptors[index];
 	d->branch_address  &= cpu_to_le32(~0xf);
 	d->res_count       =  cpu_to_le16(PAGE_SIZE);
 	d->transfer_status =  0;
 	wmb(); /* finish init of new descriptors before branch_address update */
 	d = &ctx->descriptors[ctx->last_buffer_index];
 	d->branch_address  |= cpu_to_le32(1);
 	ctx->last_buffer_index = index;
 	reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 	flush_writes(ctx->ohci);
 }
 static void ar_context_release(struct ar_context *ctx)
 {
 	unsigned int i;
 	if (ctx->buffer)
 		vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
 	for (i = 0; i < AR_BUFFERS; i++)
 		if (ctx->pages[i]) {
 			dma_unmap_page(ctx->ohci->card.device,
 				       ar_buffer_bus(ctx, i),
 				       PAGE_SIZE, DMA_FROM_DEVICE);
 			__free_page(ctx->pages[i]);
 		}
 }
 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
 {
 	if (reg_read(ctx->ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
 		reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 		flush_writes(ctx->ohci);
 		fw_error("AR error: %s; DMA stopped\n", error_msg);
 	}
 	/* FIXME: restart? */
 }
 static inline unsigned int ar_next_buffer_index(unsigned int index)
 {
 	return (index + 1) % AR_BUFFERS;
 }
 static inline unsigned int ar_prev_buffer_index(unsigned int index)
 {
 	return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
 }
 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
 {
 	return ar_next_buffer_index(ctx->last_buffer_index);
 }
 /*
  * We search for the buffer that contains the last AR packet DMA data written
  * by the controller.
  */
 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
 						 unsigned int *buffer_offset)
 {
 	unsigned int i, next_i, last = ctx->last_buffer_index;
 	__le16 res_count, next_res_count;
 	i = ar_first_buffer_index(ctx);
 	res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
 	/* A buffer that is not yet completely filled must be the last one. */
 	while (i != last && res_count == 0) {
 		/* Peek at the next descriptor. */
 		next_i = ar_next_buffer_index(i);
 		rmb(); /* read descriptors in order */
 		next_res_count = ACCESS_ONCE(
 				ctx->descriptors[next_i].res_count);
 		/*
 		 * If the next descriptor is still empty, we must stop at this
 		 * descriptor.
 		 */
 		if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
 			/*
 			 * The exception is when the DMA data for one packet is
 			 * split over three buffers; in this case, the middle
 			 * buffer's descriptor might be never updated by the
 			 * controller and look still empty, and we have to peek
 			 * at the third one.
 			 */
 			if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
 				next_i = ar_next_buffer_index(next_i);
 				rmb();
 				next_res_count = ACCESS_ONCE(
 					ctx->descriptors[next_i].res_count);
 				if (next_res_count != cpu_to_le16(PAGE_SIZE))
 					goto next_buffer_is_active;
 			}
 			break;
 		}
 next_buffer_is_active:
 		i = next_i;
 		res_count = next_res_count;
 	}
 	rmb(); /* read res_count before the DMA data */
 	*buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
 	if (*buffer_offset > PAGE_SIZE) {
 		*buffer_offset = 0;
 		ar_context_abort(ctx, "corrupted descriptor");
 	}
 	return i;
 }
 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
 				    unsigned int end_buffer_index,
 				    unsigned int end_buffer_offset)
 {
 	unsigned int i;
 	i = ar_first_buffer_index(ctx);
 	while (i != end_buffer_index) {
 		dma_sync_single_for_cpu(ctx->ohci->card.device,
 					ar_buffer_bus(ctx, i),
 					PAGE_SIZE, DMA_FROM_DEVICE);
 		i = ar_next_buffer_index(i);
 	}
 	if (end_buffer_offset > 0)
 		dma_sync_single_for_cpu(ctx->ohci->card.device,
 					ar_buffer_bus(ctx, i),
 					end_buffer_offset, DMA_FROM_DEVICE);
 }
 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
 #define cond_le32_to_cpu(v) \
 	(ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
 #else
 #define cond_le32_to_cpu(v) le32_to_cpu(v)
 #endif
 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 {
 	struct fw_ohci *ohci = ctx->ohci;
 	struct fw_packet p;
 	u32 status, length, tcode;
 	int evt;
 	p.header[0] = cond_le32_to_cpu(buffer[0]);
 	p.header[1] = cond_le32_to_cpu(buffer[1]);
 	p.header[2] = cond_le32_to_cpu(buffer[2]);
 	tcode = (p.header[0] >> 4) & 0x0f;
 	switch (tcode) {
 	case TCODE_WRITE_QUADLET_REQUEST:
 	case TCODE_READ_QUADLET_RESPONSE:
 		p.header[3] = (__force __u32) buffer[3];
 		p.header_length = 16;
 		p.payload_length = 0;
 		break;
 	case TCODE_READ_BLOCK_REQUEST :
 		p.header[3] = cond_le32_to_cpu(buffer[3]);
 		p.header_length = 16;
 		p.payload_length = 0;
 		break;
 	case TCODE_WRITE_BLOCK_REQUEST:
 	case TCODE_READ_BLOCK_RESPONSE:
 	case TCODE_LOCK_REQUEST:
 	case TCODE_LOCK_RESPONSE:
 		p.header[3] = cond_le32_to_cpu(buffer[3]);
 		p.header_length = 16;
 		p.payload_length = p.header[3] >> 16;
 		if (p.payload_length > MAX_ASYNC_PAYLOAD) {
 			ar_context_abort(ctx, "invalid packet length");
 			return NULL;
 		}
 		break;
 	case TCODE_WRITE_RESPONSE:
 	case TCODE_READ_QUADLET_REQUEST:
 	case OHCI_TCODE_PHY_PACKET:
 		p.header_length = 12;
 		p.payload_length = 0;
 		break;
 	default:
 		ar_context_abort(ctx, "invalid tcode");
 		return NULL;
 	}
 	p.payload = (void *) buffer + p.header_length;
 	/* FIXME: What to do about evt_* errors? */
 	length = (p.header_length + p.payload_length + 3) / 4;
 	status = cond_le32_to_cpu(buffer[length]);
 	evt    = (status >> 16) & 0x1f;
 	p.ack        = evt - 16;
 	p.speed      = (status >> 21) & 0x7;
 	p.timestamp  = status & 0xffff;
 	p.generation = ohci->request_generation;
 	log_ar_at_event('R', p.speed, p.header, evt);
 	/*
 	 * Several controllers, notably from NEC and VIA, forget to
 	 * write ack_complete status at PHY packet reception.
 	 */
 	if (evt == OHCI1394_evt_no_status &&
 	    (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
 		p.ack = ACK_COMPLETE;
 	/*
 	 * The OHCI bus reset handler synthesizes a PHY packet with
 	 * the new generation number when a bus reset happens (see
 	 * section 8.4.2.3).  This helps us determine when a request
 	 * was received and make sure we send the response in the same
 	 * generation.  We only need this for requests; for responses
 	 * we use the unique tlabel for finding the matching
 	 * request.
 	 *
 	 * Alas some chips sometimes emit bus reset packets with a
 	 * wrong generation.  We set the correct generation for these
 	 * at a slightly incorrect time (in bus_reset_tasklet).
 	 */
 	if (evt == OHCI1394_evt_bus_reset) {
 		if (!(ohci->quirks & QUIRK_RESET_PACKET))
 			ohci->request_generation = (p.header[2] >> 16) & 0xff;
 	} else if (ctx == &ohci->ar_request_ctx) {
 		fw_core_handle_request(&ohci->card, &p);
 	} else {
 		fw_core_handle_response(&ohci->card, &p);
 	}
 	return buffer + length + 1;
 }
 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
 {
 	void *next;
 	while (p < end) {
 		next = handle_ar_packet(ctx, p);
 		if (!next)
 			return p;
 		p = next;
 	}
 	return p;
 }
 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
 {
 	unsigned int i;
 	i = ar_first_buffer_index(ctx);
 	while (i != end_buffer) {
 		dma_sync_single_for_device(ctx->ohci->card.device,
 					   ar_buffer_bus(ctx, i),
 					   PAGE_SIZE, DMA_FROM_DEVICE);
 		ar_context_link_page(ctx, i);
 		i = ar_next_buffer_index(i);
 	}
 }
 static void ar_context_tasklet(unsigned long data)
 {
 	struct ar_context *ctx = (struct ar_context *)data;
 	unsigned int end_buffer_index, end_buffer_offset;
 	void *p, *end;
 	p = ctx->pointer;
 	if (!p)
 		return;
 	end_buffer_index = ar_search_last_active_buffer(ctx,
 							&end_buffer_offset);
 	ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
 	end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
 	if (end_buffer_index < ar_first_buffer_index(ctx)) {
 		/*
 		 * The filled part of the overall buffer wraps around; handle
 		 * all packets up to the buffer end here.  If the last packet
 		 * wraps around, its tail will be visible after the buffer end
 		 * because the buffer start pages are mapped there again.
 		 */
 		void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
 		p = handle_ar_packets(ctx, p, buffer_end);
 		if (p < buffer_end)
 			goto error;
 		/* adjust p to point back into the actual buffer */
 		p -= AR_BUFFERS * PAGE_SIZE;
 	}
 	p = handle_ar_packets(ctx, p, end);
 	if (p != end) {
 		if (p > end)
 			ar_context_abort(ctx, "inconsistent descriptor");
 		goto error;
 	}
 	ctx->pointer = p;
 	ar_recycle_buffers(ctx, end_buffer_index);
 	return;
 error:
 	ctx->pointer = NULL;
 }
 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
 			   unsigned int descriptors_offset, u32 regs)
 {
 	unsigned int i;
 	dma_addr_t dma_addr;
 	struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
 	struct descriptor *d;
 	ctx->regs        = regs;
 	ctx->ohci        = ohci;
 	tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 	for (i = 0; i < AR_BUFFERS; i++) {
 		ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
 		if (!ctx->pages[i])
 			goto out_of_memory;
 		dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
 					0, PAGE_SIZE, DMA_FROM_DEVICE);
 		if (dma_mapping_error(ohci->card.device, dma_addr)) {
 			__free_page(ctx->pages[i]);
 			ctx->pages[i] = NULL;
 			goto out_of_memory;
 		}
 		set_page_private(ctx->pages[i], dma_addr);
 	}
 	for (i = 0; i < AR_BUFFERS; i++)
 		pages[i]              = ctx->pages[i];
 	for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
 		pages[AR_BUFFERS + i] = ctx->pages[i];
 	ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
 				 -1, PAGE_KERNEL);
 	if (!ctx->buffer)
 		goto out_of_memory;
 	ctx->descriptors     = ohci->misc_buffer     + descriptors_offset;
 	ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
 	for (i = 0; i < AR_BUFFERS; i++) {
 		d = &ctx->descriptors[i];
 		d->req_count      = cpu_to_le16(PAGE_SIZE);
 		d->control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
 						DESCRIPTOR_STATUS |
 						DESCRIPTOR_BRANCH_ALWAYS);
 		d->data_address   = cpu_to_le32(ar_buffer_bus(ctx, i));
 		d->branch_address = cpu_to_le32(ctx->descriptors_bus +
 			ar_next_buffer_index(i) * sizeof(struct descriptor));
 	}
 	return 0;
 out_of_memory:
 	ar_context_release(ctx);
 	return -ENOMEM;
 }
 static void ar_context_run(struct ar_context *ctx)
 {
 	unsigned int i;
 	for (i = 0; i < AR_BUFFERS; i++)
 		ar_context_link_page(ctx, i);
 	ctx->pointer = ctx->buffer;
 	reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
 	reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
 	flush_writes(ctx->ohci);
 }
 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
 {
 	__le16 branch;
 	branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
 	/* figure out which descriptor the branch address goes in */
 	if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
 		return d;
 	else
 		return d + z - 1;
 }
 static void context_tasklet(unsigned long data)
 {
 	struct context *ctx = (struct context *) data;
 	struct descriptor *d, *last;
 	u32 address;
 	int z;
 	struct descriptor_buffer *desc;
 	desc = list_entry(ctx->buffer_list.next,
 			struct descriptor_buffer, list);
 	last = ctx->last;
 	while (last->branch_address != 0) {
 		struct descriptor_buffer *old_desc = desc;
 		address = le32_to_cpu(last->branch_address);
 		z = address & 0xf;
 		address &= ~0xf;
 		/* If the branch address points to a buffer outside of the
 		 * current buffer, advance to the next buffer. */
 		if (address < desc->buffer_bus ||
 				address >= desc->buffer_bus + desc->used)
 			desc = list_entry(desc->list.next,
 					struct descriptor_buffer, list);
 		d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
 		last = find_branch_descriptor(d, z);
 		if (!ctx->callback(ctx, d, last))
 			break;
 		if (old_desc != desc) {
 			/* If we've advanced to the next buffer, move the
 			 * previous buffer to the free list. */
 			unsigned long flags;
 			old_desc->used = 0;
 			spin_lock_irqsave(&ctx->ohci->lock, flags);
 			list_move_tail(&old_desc->list, &ctx->buffer_list);
 			spin_unlock_irqrestore(&ctx->ohci->lock, flags);
 		}
 		ctx->last = last;
 	}
 }
 /*
  * Allocate a new buffer and add it to the list of free buffers for this
  * context.  Must be called with ohci->lock held.
  */
 static int context_add_buffer(struct context *ctx)
 {
 	struct descriptor_buffer *desc;
 	dma_addr_t uninitialized_var(bus_addr);
 	int offset;
 	/*
 	 * 16MB of descriptors should be far more than enough for any DMA
 	 * program.  This will catch run-away userspace or DoS attacks.
 	 */
 	if (ctx->total_allocation >= 16*1024*1024)
 		return -ENOMEM;
 	desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
 			&bus_addr, GFP_ATOMIC);
 	if (!desc)
 		return -ENOMEM;
 	offset = (void *)&desc->buffer - (void *)desc;
 	desc->buffer_size = PAGE_SIZE - offset;
 	desc->buffer_bus = bus_addr + offset;
 	desc->used = 0;
 	list_add_tail(&desc->list, &ctx->buffer_list);
 	ctx->total_allocation += PAGE_SIZE;
 	return 0;
 }
 static int context_init(struct context *ctx, struct fw_ohci *ohci,
 			u32 regs, descriptor_callback_t callback)
 {
 	ctx->ohci = ohci;
 	ctx->regs = regs;
 	ctx->total_allocation = 0;
 	INIT_LIST_HEAD(&ctx->buffer_list);
 	if (context_add_buffer(ctx) < 0)
 		return -ENOMEM;
 	ctx->buffer_tail = list_entry(ctx->buffer_list.next,
 			struct descriptor_buffer, list);
 	tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
 	ctx->callback = callback;
 	/*
 	 * We put a dummy descriptor in the buffer that has a NULL
 	 * branch address and looks like it's been sent.  That way we
 	 * have a descriptor to append DMA programs to.
 	 */
 	memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
 	ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
 	ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
 	ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
 	ctx->last = ctx->buffer_tail->buffer;
 	ctx->prev = ctx->buffer_tail->buffer;
 	return 0;
 }
 static void context_release(struct context *ctx)
 {
 	struct fw_card *card = &ctx->ohci->card;
 	struct descriptor_buffer *desc, *tmp;
 	list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
 		dma_free_coherent(card->device, PAGE_SIZE, desc,
 			desc->buffer_bus -
 			((void *)&desc->buffer - (void *)desc));
 }
 /* Must be called with ohci->lock held */
 static struct descriptor *context_get_descriptors(struct context *ctx,
 						  int z, dma_addr_t *d_bus)
 {
 	struct descriptor *d = NULL;
 	struct descriptor_buffer *desc = ctx->buffer_tail;
 	if (z * sizeof(*d) > desc->buffer_size)
 		return NULL;
 	if (z * sizeof(*d) > desc->buffer_size - desc->used) {
 		/* No room for the descriptor in this buffer, so advance to the
 		 * next one. */
 		if (desc->list.next == &ctx->buffer_list) {
 			/* If there is no free buffer next in the list,
 			 * allocate one. */
 			if (context_add_buffer(ctx) < 0)
 				return NULL;
 		}
 		desc = list_entry(desc->list.next,
 				struct descriptor_buffer, list);
 		ctx->buffer_tail = desc;
 	}
 	d = desc->buffer + desc->used / sizeof(*d);
 	memset(d, 0, z * sizeof(*d));
 	*d_bus = desc->buffer_bus + desc->used;
 	return d;
 }
 static void context_run(struct context *ctx, u32 extra)
 {
 	struct fw_ohci *ohci = ctx->ohci;
 	reg_write(ohci, COMMAND_PTR(ctx->regs),
 		  le32_to_cpu(ctx->last->branch_address));
 	reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
 	reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
 	ctx->running = true;
 	flush_writes(ohci);
 }
 static void context_append(struct context *ctx,
 			   struct descriptor *d, int z, int extra)
 {
 	dma_addr_t d_bus;
 	struct descriptor_buffer *desc = ctx->buffer_tail;
 	d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
 	desc->used += (z + extra) * sizeof(*d);
 	wmb(); /* finish init of new descriptors before branch_address update */
 	ctx->prev->branch_address = cpu_to_le32(d_bus | z);
 	ctx->prev = find_branch_descriptor(d, z);
-	reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
-	flush_writes(ctx->ohci);
 }
 static void context_stop(struct context *ctx)
 {
 	u32 reg;
 	int i;
 	reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 	ctx->running = false;
 	flush_writes(ctx->ohci);
 	for (i = 0; i < 10; i++) {
 		reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
 		if ((reg & CONTEXT_ACTIVE) == 0)
 			return;
 		mdelay(1);
 	}
 	fw_error("Error: DMA context still active (0x%08x)\n", reg);
 }
 struct driver_data {
 	u8 inline_data[8];
 	struct fw_packet *packet;
 };
 /*
  * This function apppends a packet to the DMA queue for transmission.
  * Must always be called with the ochi->lock held to ensure proper
  * generation handling and locking around packet queue manipulation.
  */
 static int at_context_queue_packet(struct context *ctx,
 				   struct fw_packet *packet)
 {
 	struct fw_ohci *ohci = ctx->ohci;
 	dma_addr_t d_bus, uninitialized_var(payload_bus);
 	struct driver_data *driver_data;
 	struct descriptor *d, *last;
 	__le32 *header;
 	int z, tcode;
 	d = context_get_descriptors(ctx, 4, &d_bus);
 	if (d == NULL) {
 		packet->ack = RCODE_SEND_ERROR;
 		return -1;
 	}
 	d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
 	d[0].res_count = cpu_to_le16(packet->timestamp);
 	/*
 	 * The DMA format for asyncronous link packets is different
 	 * from the IEEE1394 layout, so shift the fields around
 	 * accordingly.
 	 */
 	tcode = (packet->header[0] >> 4) & 0x0f;
 	header = (__le32 *) &d[1];
 	switch (tcode) {
 	case TCODE_WRITE_QUADLET_REQUEST:
 	case TCODE_WRITE_BLOCK_REQUEST:
 	case TCODE_WRITE_RESPONSE:
 	case TCODE_READ_QUADLET_REQUEST:
 	case TCODE_READ_BLOCK_REQUEST:
 	case TCODE_READ_QUADLET_RESPONSE:
 	case TCODE_READ_BLOCK_RESPONSE:
 	case TCODE_LOCK_REQUEST:
 	case TCODE_LOCK_RESPONSE:
 		header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
 					(packet->speed << 16));
 		header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
 					(packet->header[0] & 0xffff0000));
 		header[2] = cpu_to_le32(packet->header[2]);
 		if (TCODE_IS_BLOCK_PACKET(tcode))
 			header[3] = cpu_to_le32(packet->header[3]);
 		else
 			header[3] = (__force __le32) packet->header[3];
 		d[0].req_count = cpu_to_le16(packet->header_length);
 		break;
 	case TCODE_LINK_INTERNAL:
 		header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
 					(packet->speed << 16));
 		header[1] = cpu_to_le32(packet->header[1]);
 		header[2] = cpu_to_le32(packet->header[2]);
 		d[0].req_count = cpu_to_le16(12);
 		if (is_ping_packet(&packet->header[1]))
 			d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
 		break;
 	case TCODE_STREAM_DATA:
 		header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
 					(packet->speed << 16));
 		header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
 		d[0].req_count = cpu_to_le16(8);
 		break;
 	default:
 		/* BUG(); */
 		packet->ack = RCODE_SEND_ERROR;
 		return -1;
 	}
 	BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
 	driver_data = (struct driver_data *) &d[3];
 	driver_data->packet = packet;
 	packet->driver_data = driver_data;
 	if (packet->payload_length > 0) {
 		if (packet->payload_length > sizeof(driver_data->inline_data)) {
 			payload_bus = dma_map_single(ohci->card.device,
 						     packet->payload,
 						     packet->payload_length,
 						     DMA_TO_DEVICE);
 			if (dma_mapping_error(ohci->card.device, payload_bus)) {
 				packet->ack = RCODE_SEND_ERROR;
 				return -1;
 			}
 			packet->payload_bus	= payload_bus;
 			packet->payload_mapped	= true;
 		} else {
 			memcpy(driver_data->inline_data, packet->payload,
 			       packet->payload_length);
 			payload_bus = d_bus + 3 * sizeof(*d);
 		}
 		d[2].req_count    = cpu_to_le16(packet->payload_length);
 		d[2].data_address = cpu_to_le32(payload_bus);
 		last = &d[2];
 		z = 3;
 	} else {
 		last = &d[0];
 		z = 2;
 	}
 	last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
 				     DESCRIPTOR_IRQ_ALWAYS |
 				     DESCRIPTOR_BRANCH_ALWAYS);
 	/* FIXME: Document how the locking works. */
 	if (ohci->generation != packet->generation) {
 		if (packet->payload_mapped)
 			dma_unmap_single(ohci->card.device, payload_bus,
 					 packet->payload_length, DMA_TO_DEVICE);
 		packet->ack = RCODE_GENERATION;
 		return -1;
 	}
 	context_append(ctx, d, z, 4 - z);
-	if (!ctx->running)
+	if (ctx->running) {
+		reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
+		flush_writes(ohci);
+	} else {
 		context_run(ctx, 0);
+	}
 	return 0;
 }
 static void at_context_flush(struct context *ctx)
 {
 	tasklet_disable(&ctx->tasklet);
 	ctx->flushing = true;
 	context_tasklet((unsigned long)ctx);
 	ctx->flushing = false;
 	tasklet_enable(&ctx->tasklet);
 }
 static int handle_at_packet(struct context *context,
 			    struct descriptor *d,
 			    struct descriptor *last)
 {
 	struct driver_data *driver_data;
 	struct fw_packet *packet;
 	struct fw_ohci *ohci = context->ohci;
 	int evt;
 	if (last->transfer_status == 0 && !context->flushing)
 		/* This descriptor isn't done yet, stop iteration. */
 		return 0;
 	driver_data = (struct driver_data *) &d[3];
 	packet = driver_data->packet;
 	if (packet == NULL)
 		/* This packet was cancelled, just continue. */
 		return 1;
 	if (packet->payload_mapped)
 		dma_unmap_single(ohci->card.device, packet->payload_bus,
 				 packet->payload_length, DMA_TO_DEVICE);
 	evt = le16_to_cpu(last->transfer_status) & 0x1f;
 	packet->timestamp = le16_to_cpu(last->res_count);
 	log_ar_at_event('T', packet->speed, packet->header, evt);
 	switch (evt) {
 	case OHCI1394_evt_timeout:
 		/* Async response transmit timed out. */
 		packet->ack = RCODE_CANCELLED;
 		break;
 	case OHCI1394_evt_flushed:
 		/*
 		 * The packet was flushed should give same error as
 		 * when we try to use a stale generation count.
 		 */
 		packet->ack = RCODE_GENERATION;
 		break;
 	case OHCI1394_evt_missing_ack:
 		if (context->flushing)
 			packet->ack = RCODE_GENERATION;
 		else {
 			/*
 			 * Using a valid (current) generation count, but the
 			 * node is not on the bus or not sending acks.
 			 */
 			packet->ack = RCODE_NO_ACK;
 		}
 		break;
 	case ACK_COMPLETE + 0x10:
 	case ACK_PENDING + 0x10:
 	case ACK_BUSY_X + 0x10:
 	case ACK_BUSY_A + 0x10:
 	case ACK_BUSY_B + 0x10:
 	case ACK_DATA_ERROR + 0x10:
 	case ACK_TYPE_ERROR + 0x10:
 		packet->ack = evt - 0x10;
 		break;
 	case OHCI1394_evt_no_status:
 		if (context->flushing) {
 			packet->ack = RCODE_GENERATION;
 			break;
 		}
 		/* fall through */
 	default:
 		packet->ack = RCODE_SEND_ERROR;
 		break;
 	}
 	packet->callback(packet, &ohci->card, packet->ack);
 	return 1;
 }
 #define HEADER_GET_DESTINATION(q)	(((q) >> 16) & 0xffff)
 #define HEADER_GET_TCODE(q)		(((q) >> 4) & 0x0f)
 #define HEADER_GET_OFFSET_HIGH(q)	(((q) >> 0) & 0xffff)
 #define HEADER_GET_DATA_LENGTH(q)	(((q) >> 16) & 0xffff)
 #define HEADER_GET_EXTENDED_TCODE(q)	(((q) >> 0) & 0xffff)
 static void handle_local_rom(struct fw_ohci *ohci,
 			     struct fw_packet *packet, u32 csr)
 {
 	struct fw_packet response;
 	int tcode, length, i;
 	tcode = HEADER_GET_TCODE(packet->header[0]);
 	if (TCODE_IS_BLOCK_PACKET(tcode))
 		length = HEADER_GET_DATA_LENGTH(packet->header[3]);
 	else
 		length = 4;
 	i = csr - CSR_CONFIG_ROM;
 	if (i + length > CONFIG_ROM_SIZE) {
 		fw_fill_response(&response, packet->header,
 				 RCODE_ADDRESS_ERROR, NULL, 0);
 	} else if (!TCODE_IS_READ_REQUEST(tcode)) {
 		fw_fill_response(&response, packet->header,
 				 RCODE_TYPE_ERROR, NULL, 0);
 	} else {
 		fw_fill_response(&response, packet->header, RCODE_COMPLETE,
 				 (void *) ohci->config_rom + i, length);
 	}
 	fw_core_handle_response(&ohci->card, &response);
 }
 static void handle_local_lock(struct fw_ohci *ohci,
 			      struct fw_packet *packet, u32 csr)
 {
 	struct fw_packet response;
 	int tcode, length, ext_tcode, sel, try;
 	__be32 *payload, lock_old;
 	u32 lock_arg, lock_data;
 	tcode = HEADER_GET_TCODE(packet->header[0]);
 	length = HEADER_GET_DATA_LENGTH(packet->header[3]);
 	payload = packet->payload;
 	ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
 	if (tcode == TCODE_LOCK_REQUEST &&
 	    ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
 		lock_arg = be32_to_cpu(payload[0]);
 		lock_data = be32_to_cpu(payload[1]);
 	} else if (tcode == TCODE_READ_QUADLET_REQUEST) {
 		lock_arg = 0;
 		lock_data = 0;
 	} else {
 		fw_fill_response(&response, packet->header,
 				 RCODE_TYPE_ERROR, NULL, 0);
 		goto out;
 	}
 	sel = (csr - CSR_BUS_MANAGER_ID) / 4;
 	reg_write(ohci, OHCI1394_CSRData, lock_data);
 	reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
 	reg_write(ohci, OHCI1394_CSRControl, sel);
 	for (try = 0; try < 20; try++)
 		if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
 			lock_old = cpu_to_be32(reg_read(ohci,
 							OHCI1394_CSRData));
 			fw_fill_response(&response, packet->header,
 					 RCODE_COMPLETE,
 					 &lock_old, sizeof(lock_old));
 			goto out;
 		}
 	fw_error("swap not done (CSR lock timeout)\n");
 	fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
  out:
 	fw_core_handle_response(&ohci->card, &response);
 }
 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
 {
 	u64 offset, csr;
 	if (ctx == &ctx->ohci->at_request_ctx) {
 		packet->ack = ACK_PENDING;
 		packet->callback(packet, &ctx->ohci->card, packet->ack);
 	}
 	offset =
 		((unsigned long long)
 		 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
 		packet->header[2];
 	csr = offset - CSR_REGISTER_BASE;
 	/* Handle config rom reads. */
 	if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
 		handle_local_rom(ctx->ohci, packet, csr);
 	else switch (csr) {
 	case CSR_BUS_MANAGER_ID:
 	case CSR_BANDWIDTH_AVAILABLE:
 	case CSR_CHANNELS_AVAILABLE_HI:
 	case CSR_CHANNELS_AVAILABLE_LO:
 		handle_local_lock(ctx->ohci, packet, csr);
 		break;
 	default:
 		if (ctx == &ctx->ohci->at_request_ctx)
 			fw_core_handle_request(&ctx->ohci->card, packet);
 		else
 			fw_core_handle_response(&ctx->ohci->card, packet);
 		break;
 	}
 	if (ctx == &ctx->ohci->at_response_ctx) {
 		packet->ack = ACK_COMPLETE;
 		packet->callback(packet, &ctx->ohci->card, packet->ack);
 	}
 }
 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
 {
 	unsigned long flags;
 	int ret;
 	spin_lock_irqsave(&ctx->ohci->lock, flags);
 	if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
 	    ctx->ohci->generation == packet->generation) {
 		spin_unlock_irqrestore(&ctx->ohci->lock, flags);
 		handle_local_request(ctx, packet);
 		return;
 	}
 	ret = at_context_queue_packet(ctx, packet);
 	spin_unlock_irqrestore(&ctx->ohci->lock, flags);
 	if (ret < 0)
 		packet->callback(packet, &ctx->ohci->card, packet->ack);
 }
 static void detect_dead_context(struct fw_ohci *ohci,
 				const char *name, unsigned int regs)
 {
 	u32 ctl;
 	ctl = reg_read(ohci, CONTROL_SET(regs));
 	if (ctl & CONTEXT_DEAD) {
 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
 		fw_error("DMA context %s has stopped, error code: %s\n",
 			 name, evts[ctl & 0x1f]);
 #else
 		fw_error("DMA context %s has stopped, error code: %#x\n",
 			 name, ctl & 0x1f);
 #endif
 	}
 }
 static void handle_dead_contexts(struct fw_ohci *ohci)
 {
 	unsigned int i;
 	char name[8];
 	detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
 	detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
 	detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
 	detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
 	for (i = 0; i < 32; ++i) {
 		if (!(ohci->it_context_support & (1 << i)))
 			continue;
 		sprintf(name, "IT%u", i);
 		detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
 	}
 	for (i = 0; i < 32; ++i) {
 		if (!(ohci->ir_context_support & (1 << i)))
 			continue;
 		sprintf(name, "IR%u", i);
 		detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
 	}
 	/* TODO: maybe try to flush and restart the dead contexts */
 }
 static u32 cycle_timer_ticks(u32 cycle_timer)
 {
 	u32 ticks;
 	ticks = cycle_timer & 0xfff;
 	ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
 	ticks += (3072 * 8000) * (cycle_timer >> 25);
 	return ticks;
 }
 /*
  * Some controllers exhibit one or more of the following bugs when updating the
  * iso cycle timer register:
  *  - When the lowest six bits are wrapping around to zero, a read that happens
  *    at the same time will return garbage in the lowest ten bits.
  *  - When the cycleOffset field wraps around to zero, the cycleCount field is
  *    not incremented for about 60 ns.
  *  - Occasionally, the entire register reads zero.
  *
  * To catch these, we read the register three times and ensure that the
  * difference between each two consecutive reads is approximately the same, i.e.
  * less than twice the other.  Furthermore, any negative difference indicates an
  * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
  * execute, so we have enough precision to compute the ratio of the differences.)
  */
 static u32 get_cycle_time(struct fw_ohci *ohci)
 {
 	u32 c0, c1, c2;
 	u32 t0, t1, t2;
 	s32 diff01, diff12;
 	int i;
 	c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
 	if (ohci->quirks & QUIRK_CYCLE_TIMER) {
 		i = 0;
 		c1 = c2;
 		c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
 		do {
 			c0 = c1;
 			c1 = c2;
 			c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
 			t0 = cycle_timer_ticks(c0);
 			t1 = cycle_timer_ticks(c1);
 			t2 = cycle_timer_ticks(c2);
 			diff01 = t1 - t0;
 			diff12 = t2 - t1;
 		} while ((diff01 <= 0 || diff12 <= 0 ||
 			  diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
 			 && i++ < 20);
 	}
 	return c2;
 }
 /*
  * This function has to be called at least every 64 seconds.  The bus_time
  * field stores not only the upper 25 bits of the BUS_TIME register but also
  * the most significant bit of the cycle timer in bit 6 so that we can detect
  * changes in this bit.
  */
 static u32 update_bus_time(struct fw_ohci *ohci)
 {
 	u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
 	if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
 		ohci->bus_time += 0x40;
 	return ohci->bus_time | cycle_time_seconds;
 }
 static void bus_reset_tasklet(unsigned long data)
 {
 	struct fw_ohci *ohci = (struct fw_ohci *)data;
 	int self_id_count, i, j, reg;
 	int generation, new_generation;
 	unsigned long flags;
 	void *free_rom = NULL;
 	dma_addr_t free_rom_bus = 0;
 	bool is_new_root;
 	reg = reg_read(ohci, OHCI1394_NodeID);
 	if (!(reg & OHCI1394_NodeID_idValid)) {
 		fw_notify("node ID not valid, new bus reset in progress\n");
 		return;
 	}
 	if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
 		fw_notify("malconfigured bus\n");
 		return;
 	}
 	ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
 			       OHCI1394_NodeID_nodeNumber);
 	is_new_root = (reg & OHCI1394_NodeID_root) != 0;
 	if (!(ohci->is_root && is_new_root))
 		reg_write(ohci, OHCI1394_LinkControlSet,
 			  OHCI1394_LinkControl_cycleMaster);
 	ohci->is_root = is_new_root;
 	reg = reg_read(ohci, OHCI1394_SelfIDCount);
 	if (reg & OHCI1394_SelfIDCount_selfIDError) {
 		fw_notify("inconsistent self IDs\n");
 		return;
 	}
 	/*
 	 * The count in the SelfIDCount register is the number of
 	 * bytes in the self ID receive buffer.  Since we also receive
 	 * the inverted quadlets and a header quadlet, we shift one
 	 * bit extra to get the actual number of self IDs.
 	 */
 	self_id_count = (reg >> 3) & 0xff;
 	if (self_id_count == 0 || self_id_count > 252) {
 		fw_notify("inconsistent self IDs\n");
 		return;
 	}
 	generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
 	rmb();
 	for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
 		if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
 			fw_notify("inconsistent self IDs\n");
 			return;
 		}
 		ohci->self_id_buffer[j] =
 				cond_le32_to_cpu(ohci->self_id_cpu[i]);
 	}
 	rmb();
 	/*
 	 * Check the consistency of the self IDs we just read.  The
 	 * problem we face is that a new bus reset can start while we
 	 * read out the self IDs from the DMA buffer. If this happens,
 	 * the DMA buffer will be overwritten with new self IDs and we
 	 * will read out inconsistent data.  The OHCI specification
 	 * (section 11.2) recommends a technique similar to
 	 * linux/seqlock.h, where we remember the generation of the
 	 * self IDs in the buffer before reading them out and compare
 	 * it to the current generation after reading them out.  If
 	 * the two generations match we know we have a consistent set
 	 * of self IDs.
 	 */
 	new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
 	if (new_generation != generation) {
 		fw_notify("recursive bus reset detected, "
 			  "discarding self ids\n");
 		return;
 	}
 	/* FIXME: Document how the locking works. */
 	spin_lock_irqsave(&ohci->lock, flags);
 	ohci->generation = -1; /* prevent AT packet queueing */
 	context_stop(&ohci->at_request_ctx);
 	context_stop(&ohci->at_response_ctx);
 	spin_unlock_irqrestore(&ohci->lock, flags);
 	/*
 	 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
 	 * packets in the AT queues and software needs to drain them.
 	 * Some OHCI 1.1 controllers (JMicron) apparently require this too.
 	 */
 	at_context_flush(&ohci->at_request_ctx);
 	at_context_flush(&ohci->at_response_ctx);
 	spin_lock_irqsave(&ohci->lock, flags);
 	ohci->generation = generation;
 	reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
 	if (ohci->quirks & QUIRK_RESET_PACKET)
 		ohci->request_generation = generation;
 	/*
 	 * This next bit is unrelated to the AT context stuff but we
 	 * have to do it under the spinlock also.  If a new config rom
 	 * was set up before this reset, the old one is now no longer
 	 * in use and we can free it. Update the config rom pointers
 	 * to point to the current config rom and clear the
 	 * next_config_rom pointer so a new update can take place.
 	 */
 	if (ohci->next_config_rom != NULL) {
 		if (ohci->next_config_rom != ohci->config_rom) {
 			free_rom      = ohci->config_rom;
 			free_rom_bus  = ohci->config_rom_bus;
 		}
 		ohci->config_rom      = ohci->next_config_rom;
 		ohci->config_rom_bus  = ohci->next_config_rom_bus;
 		ohci->next_config_rom = NULL;
 		/*
 		 * Restore config_rom image and manually update
 		 * config_rom registers.  Writing the header quadlet
 		 * will indicate that the config rom is ready, so we
 		 * do that last.
 		 */
 		reg_write(ohci, OHCI1394_BusOptions,
 			  be32_to_cpu(ohci->config_rom[2]));
 		ohci->config_rom[0] = ohci->next_header;
 		reg_write(ohci, OHCI1394_ConfigROMhdr,
 			  be32_to_cpu(ohci->next_header));
 	}
 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
 	reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
 	reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
 #endif
 	spin_unlock_irqrestore(&ohci->lock, flags);
 	if (free_rom)
 		dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
 				  free_rom, free_rom_bus);
 	log_selfids(ohci->node_id, generation,
 		    self_id_count, ohci->self_id_buffer);
 	fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
 				 self_id_count, ohci->self_id_buffer,
 				 ohci->csr_state_setclear_abdicate);
 	ohci->csr_state_setclear_abdicate = false;
 }
 static irqreturn_t irq_handler(int irq, void *data)
 {
 	struct fw_ohci *ohci = data;
 	u32 event, iso_event;
 	int i;
 	event = reg_read(ohci, OHCI1394_IntEventClear);
 	if (!event || !~event)
 		return IRQ_NONE;
 	/*
 	 * busReset and postedWriteErr must not be cleared yet
 	 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
 	 */
 	reg_write(ohci, OHCI1394_IntEventClear,
 		  event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
 	log_irqs(event);
 	if (event & OHCI1394_selfIDComplete)
 		tasklet_schedule(&ohci->bus_reset_tasklet);
 	if (event & OHCI1394_RQPkt)
 		tasklet_schedule(&ohci->ar_request_ctx.tasklet);
 	if (event & OHCI1394_RSPkt)
 		tasklet_schedule(&ohci->ar_response_ctx.tasklet);
 	if (event & OHCI1394_reqTxComplete)
 		tasklet_schedule(&ohci->at_request_ctx.tasklet);
 	if (event & OHCI1394_respTxComplete)
 		tasklet_schedule(&ohci->at_response_ctx.tasklet);
 	if (event & OHCI1394_isochRx) {
 		iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
 		reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
 		while (iso_event) {
 			i = ffs(iso_event) - 1;
 			tasklet_schedule(
 				&ohci->ir_context_list[i].context.tasklet);
 			iso_event &= ~(1 << i);
 		}
 	}
 	if (event & OHCI1394_isochTx) {
 		iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
 		reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
 		while (iso_event) {
 			i = ffs(iso_event) - 1;
 			tasklet_schedule(
 				&ohci->it_context_list[i].context.tasklet);
 			iso_event &= ~(1 << i);
 		}
 	}
 	if (unlikely(event & OHCI1394_regAccessFail))
 		fw_error("Register access failure - "
 			 "please notify linux1394-devel@lists.sf.net\n");
 	if (unlikely(event & OHCI1394_postedWriteErr)) {
 		reg_read(ohci, OHCI1394_PostedWriteAddressHi);
 		reg_read(ohci, OHCI1394_PostedWriteAddressLo);
 		reg_write(ohci, OHCI1394_IntEventClear,
 			  OHCI1394_postedWriteErr);
 		fw_error("PCI posted write error\n");
 	}
 	if (unlikely(event & OHCI1394_cycleTooLong)) {
 		if (printk_ratelimit())
 			fw_notify("isochronous cycle too long\n");
 		reg_write(ohci, OHCI1394_LinkControlSet,
 			  OHCI1394_LinkControl_cycleMaster);
 	}
 	if (unlikely(event & OHCI1394_cycleInconsistent)) {
 		/*
 		 * We need to clear this event bit in order to make
 		 * cycleMatch isochronous I/O work.  In theory we should
 		 * stop active cycleMatch iso contexts now and restart
 		 * them at least two cycles later.  (FIXME?)
 		 */
 		if (printk_ratelimit())
 			fw_notify("isochronous cycle inconsistent\n");
 	}
 	if (unlikely(event & OHCI1394_unrecoverableError))
 		handle_dead_contexts(ohci);
 	if (event & OHCI1394_cycle64Seconds) {
 		spin_lock(&ohci->lock);
 		update_bus_time(ohci);
 		spin_unlock(&ohci->lock);
 	} else
 		flush_writes(ohci);
 	return IRQ_HANDLED;
 }
 static int software_reset(struct fw_ohci *ohci)
 {
 	int i;
 	reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
 	for (i = 0; i < OHCI_LOOP_COUNT; i++) {
 		if ((reg_read(ohci, OHCI1394_HCControlSet) &
 		     OHCI1394_HCControl_softReset) == 0)
 			return 0;
 		msleep(1);
 	}
 	return -EBUSY;
 }
 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
 {
 	size_t size = length * 4;
 	memcpy(dest, src, size);
 	if (size < CONFIG_ROM_SIZE)
 		memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
 }
 static int configure_1394a_enhancements(struct fw_ohci *ohci)
 {
 	bool enable_1394a;
 	int ret, clear, set, offset;
 	/* Check if the driver should configure link and PHY. */
 	if (!(reg_read(ohci, OHCI1394_HCControlSet) &
 	      OHCI1394_HCControl_programPhyEnable))
 		return 0;
 	/* Paranoia: check whether the PHY supports 1394a, too. */
 	enable_1394a = false;
 	ret = read_phy_reg(ohci, 2);
 	if (ret < 0)
 		return ret;
 	if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
 		ret = read_paged_phy_reg(ohci, 1, 8);
 		if (ret < 0)
 			return ret;
 		if (ret >= 1)
 			enable_1394a = true;
 	}
 	if (ohci->quirks & QUIRK_NO_1394A)
 		enable_1394a = false;
 	/* Configure PHY and link consistently. */
 	if (enable_1394a) {
 		clear = 0;
 		set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
 	} else {
 		clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
 		set = 0;
 	}
 	ret = update_phy_reg(ohci, 5, clear, set);
 	if (ret < 0)
 		return ret;
 	if (enable_1394a)
 		offset = OHCI1394_HCControlSet;
 	else
 		offset = OHCI1394_HCControlClear;
 	reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
 	/* Clean up: configuration has been taken care of. */
 	reg_write(ohci, OHCI1394_HCControlClear,
 		  OHCI1394_HCControl_programPhyEnable);
 	return 0;
 }
 static int ohci_enable(struct fw_card *card,
 		       const __be32 *config_rom, size_t length)
 {
 	struct fw_ohci *ohci = fw_ohci(card);
 	struct pci_dev *dev = to_pci_dev(card->device);
 	u32 lps, seconds, version, irqs;
 	int i, ret;
 	if (software_reset(ohci)) {
 		fw_error("Failed to reset ohci card.\n");
 		return -EBUSY;
 	}
 	/*
 	 * Now enable LPS, which we need in order to start accessing
 	 * most of the registers.  In fact, on some cards (ALI M5251),
 	 * accessing registers in the SClk domain without LPS enabled
 	 * will lock up the machine.  Wait 50msec to make sure we have
 	 * full link enabled.  However, with some cards (well, at least
 	 * a JMicron PCIe card), we have to try again sometimes.
 	 */
 	reg_write(ohci, OHCI1394_HCControlSet,
 		  OHCI1394_HCControl_LPS |
 		  OHCI1394_HCControl_postedWriteEnable);
 	flush_writes(ohci);
 	for (lps = 0, i = 0; !lps && i < 3; i++) {
 		msleep(50);
 		lps = reg_read(ohci, OHCI1394_HCControlSet) &
 		      OHCI1394_HCControl_LPS;
 	}
 	if (!lps) {
 		fw_error("Failed to set Link Power Status\n");
 		return -EIO;
 	}
 	reg_write(ohci, OHCI1394_HCControlClear,
 		  OHCI1394_HCControl_noByteSwapData);
 	reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
 	reg_write(ohci, OHCI1394_LinkControlSet,
 		  OHCI1394_LinkControl_cycleTimerEnable |
 		  OHCI1394_LinkControl_cycleMaster);
 	reg_write(ohci, OHCI1394_ATRetries,
 		  OHCI1394_MAX_AT_REQ_RETRIES |
 		  (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
 		  (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
 		  (200 << 16));
 	seconds = lower_32_bits(get_seconds());
 	reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
 	ohci->bus_time = seconds & ~0x3f;
 	version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
 	if (version >= OHCI_VERSION_1_1) {
 		reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
 			  0xfffffffe);
 		card->broadcast_channel_auto_allocated = true;
 	}
 	/* Get implemented bits of the priority arbitration request counter. */
 	reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
 	ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
 	reg_write(ohci, OHCI1394_FairnessControl, 0);
 	card->priority_budget_implemented = ohci->pri_req_max != 0;
 	reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
 	reg_write(ohci, OHCI1394_IntEventClear, ~0);
 	reg_write(ohci, OHCI1394_IntMaskClear, ~0);
 	ret = configure_1394a_enhancements(ohci);
 	if (ret < 0)
 		return ret;
 	/* Activate link_on bit and contender bit in our self ID packets.*/
 	ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
 	if (ret < 0)
 		return ret;
 	/*
 	 * When the link is not yet enabled, the atomic config rom
 	 * update mechanism described below in ohci_set_config_rom()
 	 * is not active.  We have to update ConfigRomHeader and
 	 * BusOptions manually, and the write to ConfigROMmap takes
 	 * effect immediately.  We tie this to the enabling of the
 	 * link, so we have a valid config rom before enabling - the
 	 * OHCI requires that ConfigROMhdr and BusOptions have valid
 	 * values before enabling.
 	 *
 	 * However, when the ConfigROMmap is written, some controllers
 	 * always read back quadlets 0 and 2 from the config rom to
 	 * the ConfigRomHeader and BusOptions registers on bus reset.
 	 * They shouldn't do that in this initial case where the link
 	 * isn't enabled.  This means we have to use the same
 	 * workaround here, setting the bus header to 0 and then write
 	 * the right values in the bus reset tasklet.
 	 */
 	if (config_rom) {
 		ohci->next_config_rom =
 			dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
 					   &ohci->next_config_rom_bus,
 					   GFP_KERNEL);
 		if (ohci->next_config_rom == NULL)
 			return -ENOMEM;
 		copy_config_rom(ohci->next_config_rom, config_rom, length);
 	} else {
 		/*
 		 * In the suspend case, config_rom is NULL, which
 		 * means that we just reuse the old config rom.
 		 */
 		ohci->next_config_rom = ohci->config_rom;
 		ohci->next_config_rom_bus = ohci->config_rom_bus;
 	}
 	ohci->next_header = ohci->next_config_rom[0];
 	ohci->next_config_rom[0] = 0;
 	reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
 	reg_write(ohci, OHCI1394_BusOptions,
 		  be32_to_cpu(ohci->next_config_rom[2]));
 	reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
 	reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
 	if (!(ohci->quirks & QUIRK_NO_MSI))
 		pci_enable_msi(dev);
 	if (request_irq(dev->irq, irq_handler,
 			pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
 			ohci_driver_name, ohci)) {
 		fw_error("Failed to allocate interrupt %d.\n", dev->irq);
 		pci_disable_msi(dev);
 		dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
 				  ohci->config_rom, ohci->config_rom_bus);
 		return -EIO;
 	}
 	irqs =	OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
 		OHCI1394_RQPkt | OHCI1394_RSPkt |
 		OHCI1394_isochTx | OHCI1394_isochRx |
 		OHCI1394_postedWriteErr |
 		OHCI1394_selfIDComplete |
 		OHCI1394_regAccessFail |
 		OHCI1394_cycle64Seconds |
 		OHCI1394_cycleInconsistent |
 		OHCI1394_unrecoverableError |
 		OHCI1394_cycleTooLong |
 		OHCI1394_masterIntEnable;
 	if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
 		irqs |= OHCI1394_busReset;
 	reg_write(ohci, OHCI1394_IntMaskSet, irqs);
 	reg_write(ohci, OHCI1394_HCControlSet,
 		  OHCI1394_HCControl_linkEnable |
 		  OHCI1394_HCControl_BIBimageValid);
 	reg_write(ohci, OHCI1394_LinkControlSet,
 		  OHCI1394_LinkControl_rcvSelfID |
 		  OHCI1394_LinkControl_rcvPhyPkt);
 	ar_context_run(&ohci->ar_request_ctx);
 	ar_context_run(&ohci->ar_response_ctx); /* also flushes writes */
 	/* We are ready to go, reset bus to finish initialization. */
 	fw_schedule_bus_reset(&ohci->card, false, true);
 	return 0;
 }
 static int ohci_set_config_rom(struct fw_card *card,
 			       const __be32 *config_rom, size_t length)
 {
 	struct fw_ohci *ohci;
 	unsigned long flags;
 	__be32 *next_config_rom;
 	dma_addr_t uninitialized_var(next_config_rom_bus);
 	ohci = fw_ohci(card);
 	/*
 	 * When the OHCI controller is enabled, the config rom update
 	 * mechanism is a bit tricky, but easy enough to use.  See
 	 * section 5.5.6 in the OHCI specification.
 	 *
 	 * The OHCI controller caches the new config rom address in a
 	 * shadow register (ConfigROMmapNext) and needs a bus reset
 	 * for the changes to take place.  When the bus reset is
 	 * detected, the controller loads the new values for the
 	 * ConfigRomHeader and BusOptions registers from the specified
 	 * config rom and loads ConfigROMmap from the ConfigROMmapNext
 	 * shadow register. All automatically and atomically.
 	 *
 	 * Now, there's a twist to this story.  The automatic load of
 	 * ConfigRomHeader and BusOptions doesn't honor the
 	 * noByteSwapData bit, so with a be32 config rom, the
 	 * controller will load be32 values in to these registers
 	 * during the atomic update, even on litte endian
 	 * architectures.  The workaround we use is to put a 0 in the
 	 * header quadlet; 0 is endian agnostic and means that the
 	 * config rom isn't ready yet.  In the bus reset tasklet we
 	 * then set up the real values for the two registers.
 	 *
 	 * We use ohci->lock to avoid racing with the code that sets
 	 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
 	 */
 	next_config_rom =
 		dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
 				   &next_config_rom_bus, GFP_KERNEL);
 	if (next_config_rom == NULL)
 		return -ENOMEM;
 	spin_lock_irqsave(&ohci->lock, flags);
 	/*
 	 * If there is not an already pending config_rom update,
 	 * push our new allocation into the ohci->next_config_rom
 	 * and then mark the local variable as null so that we
 	 * won't deallocate the new buffer.
 	 *
 	 * OTOH, if there is a pending config_rom update, just
 	 * use that buffer with the new config_rom data, and
 	 * let this routine free the unused DMA allocation.
 	 */
 	if (ohci->next_config_rom == NULL) {
 		ohci->next_config_rom = next_config_rom;
 		ohci->next_config_rom_bus = next_config_rom_bus;
 		next_config_rom = NULL;
 	}
 	copy_config_rom(ohci->next_config_rom, config_rom, length);
 	ohci->next_header = config_rom[0];
 	ohci->next_config_rom[0] = 0;
 	reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
 	spin_unlock_irqrestore(&ohci->lock, flags);
 	/* If we didn't use the DMA allocation, delete it. */
 	if (next_config_rom != NULL)
 		dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
 				  next_config_rom, next_config_rom_bus);
 	/*
 	 * Now initiate a bus reset to have the changes take
 	 * effect. We clean up the old config rom memory and DMA
 	 * mappings in the bus reset tasklet, since the OHCI
 	 * controller could need to access it before the bus reset
 	 * takes effect.
 	 */
 	fw_schedule_bus_reset(&ohci->card, true, true);
 	return 0;
 }
 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
 {
 	struct fw_ohci *ohci = fw_ohci(card);
 	at_context_transmit(&ohci->at_request_ctx, packet);
 }
 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
 {
 	struct fw_ohci *ohci = fw_ohci(card);
 	at_context_transmit(&ohci->at_response_ctx, packet);
 }
 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
 {
 	struct fw_ohci *ohci = fw_ohci(card);
 	struct context *ctx = &ohci->at_request_ctx;
 	struct driver_data *driver_data = packet->driver_data;
 	int ret = -ENOENT;
 	tasklet_disable(&ctx->tasklet);
 	if (packet->ack != 0)
 		goto out;
 	if (packet->payload_mapped)
 		dma_unmap_single(ohci->card.device, packet->payload_bus,
 				 packet->payload_length, DMA_TO_DEVICE);
 	log_ar_at_event('T', packet->speed, packet->header, 0x20);
 	driver_data->packet = NULL;
 	packet->ack = RCODE_CANCELLED;
 	packet->callback(packet, &ohci->card, packet->ack);
 	ret = 0;
  out:
 	tasklet_enable(&ctx->tasklet);
 	return ret;
 }
 static int ohci_enable_phys_dma(struct fw_card *card,
 				int node_id, int generation)
 {
 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
 	return 0;
 #else
 	struct fw_ohci *ohci = fw_ohci(card);
 	unsigned long flags;
 	int n, ret = 0;
 	/*
 	 * FIXME:  Make sure this bitmask is cleared when we clear the busReset
 	 * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
 	 */
 	spin_lock_irqsave(&ohci->lock, flags);
 	if (ohci->generation != generation) {
 		ret = -ESTALE;
 		goto out;
 	}
 	/*
 	 * Note, if the node ID contains a non-local bus ID, physical DMA is
 	 * enabled for _all_ nodes on remote buses.
 	 */
 	n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
 	if (n < 32)
 		reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
 	else
 		reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
 	flush_writes(ohci);
  out:
 	spin_unlock_irqrestore(&ohci->lock, flags);
 	return ret;
 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
 }
 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
 {
 	struct fw_ohci *ohci = fw_ohci(card);
 	unsigned long flags;
 	u32 value;
 	switch (csr_offset) {
 	case CSR_STATE_CLEAR:
 	case CSR_STATE_SET:
 		if (ohci->is_root &&
 		    (reg_read(ohci, OHCI1394_LinkControlSet) &
 		     OHCI1394_LinkControl_cycleMaster))
 			value = CSR_STATE_BIT_CMSTR;
 		else
 			value = 0;
 		if (ohci->csr_state_setclear_abdicate)
 			value |= CSR_STATE_BIT_ABDICATE;
 		return value;
 	case CSR_NODE_IDS:
 		return reg_read(ohci, OHCI1394_NodeID) << 16;
 	case CSR_CYCLE_TIME:
 		return get_cycle_time(ohci);
 	case CSR_BUS_TIME:
 		/*
 		 * We might be called just after the cycle timer has wrapped
 		 * around but just before the cycle64Seconds handler, so we
 		 * better check here, too, if the bus time needs to be updated.
 		 */
 		spin_lock_irqsave(&ohci->lock, flags);
 		value = update_bus_time(ohci);
 		spin_unlock_irqrestore(&ohci->lock, flags);
 		return value;
 	case CSR_BUSY_TIMEOUT:
 		value = reg_read(ohci, OHCI1394_ATRetries);
 		return (value >> 4) & 0x0ffff00f;
 	case CSR_PRIORITY_BUDGET:
 		return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
 			(ohci->pri_req_max << 8);
 	default:
 		WARN_ON(1);
 		return 0;
 	}
 }
 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
 {
 	struct fw_ohci *ohci = fw_ohci(card);
 	unsigned long flags;
 	switch (csr_offset) {
 	case CSR_STATE_CLEAR:
 		if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
 			reg_write(ohci, OHCI1394_LinkControlClear,
 				  OHCI1394_LinkControl_cycleMaster);
 			flush_writes(ohci);
 		}
 		if (value & CSR_STATE_BIT_ABDICATE)
 			ohci->csr_state_setclear_abdicate = false;
 		break;
 	case CSR_STATE_SET:
 		if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
 			reg_write(ohci, OHCI1394_LinkControlSet,
 				  OHCI1394_LinkControl_cycleMaster);
 			flush_writes(ohci);
 		}
 		if (value & CSR_STATE_BIT_ABDICATE)
 			ohci->csr_state_setclear_abdicate = true;
 		break;
 	case CSR_NODE_IDS:
 		reg_write(ohci, OHCI1394_NodeID, value >> 16);
 		flush_writes(ohci);
 		break;
 	case CSR_CYCLE_TIME:
 		reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
 		reg_write(ohci, OHCI1394_IntEventSet,
 			  OHCI1394_cycleInconsistent);
 		flush_writes(ohci);
 		break;
 	case CSR_BUS_TIME:
 		spin_lock_irqsave(&ohci->lock, flags);
 		ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
 		spin_unlock_irqrestore(&ohci->lock, flags);
 		break;
 	case CSR_BUSY_TIMEOUT:
 		value = (value & 0xf) | ((value & 0xf) << 4) |
 			((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
 		reg_write(ohci, OHCI1394_ATRetries, value);
 		flush_writes(ohci);
 		break;
 	case CSR_PRIORITY_BUDGET:
 		reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
 		flush_writes(ohci);
 		break;
 	default:
 		WARN_ON(1);
 		break;
 	}
 }
 static void copy_iso_headers(struct iso_context *ctx, void *p)
 {
 	int i = ctx->header_length;
 	if (i + ctx->base.header_size > PAGE_SIZE)
 		return;
 	/*
 	 * The iso header is byteswapped to little endian by
 	 * the controller, but the remaining header quadlets
 	 * are big endian.  We want to present all the headers
 	 * as big endian, so we have to swap the first quadlet.
 	 */
 	if (ctx->base.header_size > 0)
 		*(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
 	if (ctx->base.header_size > 4)
 		*(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
 	if (ctx->base.header_size > 8)
 		memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
 	ctx->header_length += ctx->base.header_size;
 }
 static int handle_ir_packet_per_buffer(struct context *context,
 				       struct descriptor *d,
 				       struct descriptor *last)
 {
 	struct iso_context *ctx =
 		container_of(context, struct iso_context, context);
 	struct descriptor *pd;
 	__le32 *ir_header;
 	void *p;
 	for (pd = d; pd <= last; pd++)
 		if (pd->transfer_status)
 			break;
 	if (pd > last)
 		/* Descriptor(s) not done yet, stop iteration */
 		return 0;
 	p = last + 1;
 	copy_iso_headers(ctx, p);
 	if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
 		ir_header = (__le32 *) p;
 		ctx->base.callback.sc(&ctx->base,
 				      le32_to_cpu(ir_header[0]) & 0xffff,
 				      ctx->header_length, ctx->header,
 				      ctx->base.callback_data);
 		ctx->header_length = 0;
 	}
 	return 1;
 }
 /* d == last because each descriptor block is only a single descriptor. */
 static int handle_ir_buffer_fill(struct context *context,
 				 struct descriptor *d,
 				 struct descriptor *last)
 {
 	struct iso_context *ctx =
 		container_of(context, struct iso_context, context);
 	if (!last->transfer_status)
 		/* Descriptor(s) not done yet, stop iteration */
 		return 0;
 	if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
 		ctx->base.callback.mc(&ctx->base,
 				      le32_to_cpu(last->data_address) +
 				      le16_to_cpu(last->req_count) -
 				      le16_to_cpu(last->res_count),
 				      ctx->base.callback_data);
 	return 1;
 }
 static int handle_it_packet(struct context *context,
 			    struct descriptor *d,
 			    struct descriptor *last)
 {
 	struct iso_context *ctx =
 		container_of(context, struct iso_context, context);
 	int i;
 	struct descriptor *pd;
 	for (pd = d; pd <= last; pd++)
 		if (pd->transfer_status)
 			break;
 	if (pd > last)
 		/* Descriptor(s) not done yet, stop iteration */
 		return 0;
 	i = ctx->header_length;
 	if (i + 4 < PAGE_SIZE) {
 		/* Present this value as big-endian to match the receive code */
 		*(__be32 *)(ctx->header + i) = cpu_to_be32(
 				((u32)le16_to_cpu(pd->transfer_status) << 16) |
 				le16_to_cpu(pd->res_count));
 		ctx->header_length += 4;
 	}
 	if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
 		ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
 				      ctx->header_length, ctx->header,
 				      ctx->base.callback_data);
 		ctx->header_length = 0;
 	}
 	return 1;
 }
 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
 {
 	u32 hi = channels >> 32, lo = channels;
 	reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
 	reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
 	reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
 	reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
 	mmiowb();
 	ohci->mc_channels = channels;
 }
 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
 				int type, int channel, size_t header_size)
 {
 	struct fw_ohci *ohci = fw_ohci(card);
 	struct iso_context *uninitialized_var(ctx);
 	descriptor_callback_t uninitialized_var(callback);
 	u64 *uninitialized_var(channels);
 	u32 *uninitialized_var(mask), uninitialized_var(regs);
 	unsigned long flags;
 	int index, ret = -EBUSY;
 	spin_lock_irqsave(&ohci->lock, flags);
 	switch (type) {
 	case FW_ISO_CONTEXT_TRANSMIT:
 		mask     = &ohci->it_context_mask;
 		callback = handle_it_packet;
 		index    = ffs(*mask) - 1;
 		if (index >= 0) {
 			*mask &= ~(1 << index);
 			regs = OHCI1394_IsoXmitContextBase(index);
 			ctx  = &ohci->it_context_list[index];
 		}
 		break;
 	case FW_ISO_CONTEXT_RECEIVE:
 		channels = &ohci->ir_context_channels;
 		mask     = &ohci->ir_context_mask;
 		callback = handle_ir_packet_per_buffer;
 		index    = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
 		if (index >= 0) {
 			*channels &= ~(1ULL << channel);
 			*mask     &= ~(1 << index);
 			regs = OHCI1394_IsoRcvContextBase(index);
 			ctx  = &ohci->ir_context_list[index];
 		}
 		break;
 	case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
 		mask     = &ohci->ir_context_mask;
 		callback = handle_ir_buffer_fill;
 		index    = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
 		if (index >= 0) {
 			ohci->mc_allocated = true;
 			*mask &= ~(1 << index);
 			regs = OHCI1394_IsoRcvContextBase(index);
 			ctx  = &ohci->ir_context_list[index];
 		}
 		break;
 	default:
 		index = -1;
 		ret = -ENOSYS;
 	}
 	spin_unlock_irqrestore(&ohci->lock, flags);
 	if (index < 0)
 		return ERR_PTR(ret);
 	memset(ctx, 0, sizeof(*ctx));
 	ctx->header_length = 0;
 	ctx->header = (void *) __get_free_page(GFP_KERNEL);
 	if (ctx->header == NULL) {
 		ret = -ENOMEM;
 		goto out;
 	}
 	ret = context_init(&ctx->context, ohci, regs, callback);
 	if (ret < 0)
 		goto out_with_header;
 	if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
 		set_multichannel_mask(ohci, 0);
 	return &ctx->base;
  out_with_header:
 	free_page((unsigned long)ctx->header);
  out:
 	spin_lock_irqsave(&ohci->lock, flags);
 	switch (type) {
 	case FW_ISO_CONTEXT_RECEIVE:
 		*channels |= 1ULL << channel;
 		break;
 	case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
 		ohci->mc_allocated = false;
 		break;
 	}
 	*mask |= 1 << index;
 	spin_unlock_irqrestore(&ohci->lock, flags);
 	return ERR_PTR(ret);
 }
 static int ohci_start_iso(struct fw_iso_context *base,
 			  s32 cycle, u32 sync, u32 tags)
 {
 	struct iso_context *ctx = container_of(base, struct iso_context, base);
 	struct fw_ohci *ohci = ctx->context.ohci;
 	u32 control = IR_CONTEXT_ISOCH_HEADER, match;
 	int index;
 	/* the controller cannot start without any queued packets */
 	if (ctx->context.last->branch_address == 0)
 		return -ENODATA;
 	switch (ctx->base.type) {
 	case FW_ISO_CONTEXT_TRANSMIT:
 		index = ctx - ohci->it_context_list;
 		match = 0;
 		if (cycle >= 0)
 			match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
 				(cycle & 0x7fff) << 16;
 		reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
 		reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
 		context_run(&ctx->context, match);
 		break;
 	case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
 		control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
 		/* fall through */
 	case FW_ISO_CONTEXT_RECEIVE:
 		index = ctx - ohci->ir_context_list;
 		match = (tags << 28) | (sync << 8) | ctx->base.channel;
 		if (cycle >= 0) {
 			match |= (cycle & 0x07fff) << 12;
 			control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
 		}
 		reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
 		reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
 		reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
 		context_run(&ctx->context, control);
 		ctx->sync = sync;
 		ctx->tags = tags;
 		break;
 	}
 	return 0;
 }
 static int ohci_stop_iso(struct fw_iso_context *base)
 {
 	struct fw_ohci *ohci = fw_ohci(base->card);
 	struct iso_context *ctx = container_of(base, struct iso_context, base);
 	int index;
 	switch (ctx->base.type) {
 	case FW_ISO_CONTEXT_TRANSMIT:
 		index = ctx - ohci->it_context_list;
 		reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
 		break;
 	case FW_ISO_CONTEXT_RECEIVE:
 	case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
 		index = ctx - ohci->ir_context_list;
 		reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
 		break;
 	}
 	flush_writes(ohci);
 	context_stop(&ctx->context);
 	tasklet_kill(&ctx->context.tasklet);
 	return 0;
 }
 static void ohci_free_iso_context(struct fw_iso_context *base)
 {
 	struct fw_ohci *ohci = fw_ohci(base->card);
 	struct iso_context *ctx = container_of(base, struct iso_context, base);
 	unsigned long flags;
 	int index;
 	ohci_stop_iso(base);
 	context_release(&ctx->context);
 	free_page((unsigned long)ctx->header);
 	spin_lock_irqsave(&ohci->lock, flags);
 	switch (base->type) {
 	case FW_ISO_CONTEXT_TRANSMIT:
 		index = ctx - ohci->it_context_list;
 		ohci->it_context_mask |= 1 << index;
 		break;
 	case FW_ISO_CONTEXT_RECEIVE:
 		index = ctx - ohci->ir_context_list;
 		ohci->ir_context_mask |= 1 << index;
 		ohci->ir_context_channels |= 1ULL << base->channel;
 		break;
 	case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
 		index = ctx - ohci->ir_context_list;
 		ohci->ir_context_mask |= 1 << index;
 		ohci->ir_context_channels |= ohci->mc_channels;
 		ohci->mc_channels = 0;
 		ohci->mc_allocated = false;
 		break;
 	}
 	spin_unlock_irqrestore(&ohci->lock, flags);
 }
 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
 {
 	struct fw_ohci *ohci = fw_ohci(base->card);
 	unsigned long flags;
 	int ret;
 	switch (base->type) {
 	case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
 		spin_lock_irqsave(&ohci->lock, flags);
 		/* Don't allow multichannel to grab other contexts' channels. */
 		if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
 			*channels = ohci->ir_context_channels;
 			ret = -EBUSY;
 		} else {
 			set_multichannel_mask(ohci, *channels);
 			ret = 0;
 		}
 		spin_unlock_irqrestore(&ohci->lock, flags);
 		break;
 	default:
 		ret = -EINVAL;
 	}
 	return ret;
 }
 #ifdef CONFIG_PM
 static void ohci_resume_iso_dma(struct fw_ohci *ohci)
 {
 	int i;
 	struct iso_context *ctx;
 	for (i = 0 ; i < ohci->n_ir ; i++) {
 		ctx = &ohci->ir_context_list[i];
 		if (ctx->context.running)
 			ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
 	}
 	for (i = 0 ; i < ohci->n_it ; i++) {
 		ctx = &ohci->it_context_list[i];
 		if (ctx->context.running)
 			ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
 	}
 }
 #endif
 static int queue_iso_transmit(struct iso_context *ctx,
 			      struct fw_iso_packet *packet,
 			      struct fw_iso_buffer *buffer,
 			      unsigned long payload)
 {
 	struct descriptor *d, *last, *pd;
 	struct fw_iso_packet *p;
 	__le32 *header;
 	dma_addr_t d_bus, page_bus;
 	u32 z, header_z, payload_z, irq;
 	u32 payload_index, payload_end_index, next_page_index;
 	int page, end_page, i, length, offset;
 	p = packet;
 	payload_index = payload;
 	if (p->skip)
 		z = 1;
 	else
 		z = 2;
 	if (p->header_length > 0)
 		z++;
 	/* Determine the first page the payload isn't contained in. */
 	end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
 	if (p->payload_length > 0)
 		payload_z = end_page - (payload_index >> PAGE_SHIFT);
 	else
 		payload_z = 0;
 	z += payload_z;
 	/* Get header size in number of descriptors. */
 	header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
 	d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
 	if (d == NULL)
 		return -ENOMEM;
 	if (!p->skip) {
 		d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
 		d[0].req_count = cpu_to_le16(8);
 		/*
 		 * Link the skip address to this descriptor itself.  This causes
 		 * a context to skip a cycle whenever lost cycles or FIFO
 		 * overruns occur, without dropping the data.  The application
 		 * should then decide whether this is an error condition or not.
 		 * FIXME:  Make the context's cycle-lost behaviour configurable?
 		 */
 		d[0].branch_address = cpu_to_le32(d_bus | z);
 		header = (__le32 *) &d[1];
 		header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
 					IT_HEADER_TAG(p->tag) |
 					IT_HEADER_TCODE(TCODE_STREAM_DATA) |
 					IT_HEADER_CHANNEL(ctx->base.channel) |
 					IT_HEADER_SPEED(ctx->base.speed));
 		header[1] =
 			cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
 							  p->payload_length));
 	}
 	if (p->header_length > 0) {
 		d[2].req_count    = cpu_to_le16(p->header_length);
 		d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
 		memcpy(&d[z], p->header, p->header_length);
 	}
 	pd = d + z - payload_z;
 	payload_end_index = payload_index + p->payload_length;
 	for (i = 0; i < payload_z; i++) {
 		page               = payload_index >> PAGE_SHIFT;
 		offset             = payload_index & ~PAGE_MASK;
 		next_page_index    = (page + 1) << PAGE_SHIFT;
 		length             =
 			min(next_page_index, payload_end_index) - payload_index;
 		pd[i].req_count    = cpu_to_le16(length);
 		page_bus = page_private(buffer->pages[page]);
 		pd[i].data_address = cpu_to_le32(page_bus + offset);
 		payload_index += length;
 	}
 	if (p->interrupt)
 		irq = DESCRIPTOR_IRQ_ALWAYS;
 	else
 		irq = DESCRIPTOR_NO_IRQ;
 	last = z == 2 ? d : d + z - 1;
 	last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
 				     DESCRIPTOR_STATUS |
 				     DESCRIPTOR_BRANCH_ALWAYS |
 				     irq);
 	context_append(&ctx->context, d, z, header_z);
 	return 0;
 }
 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
 				       struct fw_iso_packet *packet,
 				       struct fw_iso_buffer *buffer,
 				       unsigned long payload)
 {
 	struct descriptor *d, *pd;
 	dma_addr_t d_bus, page_bus;
 	u32 z, header_z, rest;
 	int i, j, length;
 	int page, offset, packet_count, header_size, payload_per_buffer;
 	/*
 	 * The OHCI controller puts the isochronous header and trailer in the
 	 * buffer, so we need at least 8 bytes.
 	 */
 	packet_count = packet->header_length / ctx->base.header_size;
 	header_size  = max(ctx->base.header_size, (size_t)8);
 	/* Get header size in number of descriptors. */
 	header_z = DIV_ROUND_UP(header_size, sizeof(*d));
 	page     = payload >> PAGE_SHIFT;
 	offset   = payload & ~PAGE_MASK;
 	payload_per_buffer = packet->payload_length / packet_count;
 	for (i = 0; i < packet_count; i++) {
 		/* d points to the header descriptor */
 		z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
 		d = context_get_descriptors(&ctx->context,
 				z + header_z, &d_bus);
 		if (d == NULL)
 			return -ENOMEM;
 		d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
 					      DESCRIPTOR_INPUT_MORE);
 		if (packet->skip && i == 0)
 			d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
 		d->req_count    = cpu_to_le16(header_size);
 		d->res_count    = d->req_count;
 		d->transfer_status = 0;
 		d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
 		rest = payload_per_buffer;
 		pd = d;
 		for (j = 1; j < z; j++) {
 			pd++;
 			pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
 						  DESCRIPTOR_INPUT_MORE);
 			if (offset + rest < PAGE_SIZE)
 				length = rest;
 			else
 				length = PAGE_SIZE - offset;
 			pd->req_count = cpu_to_le16(length);
 			pd->res_count = pd->req_count;
 			pd->transfer_status = 0;
 			page_bus = page_private(buffer->pages[page]);
 			pd->data_address = cpu_to_le32(page_bus + offset);
 			offset = (offset + length) & ~PAGE_MASK;
 			rest -= length;
 			if (offset == 0)
 				page++;
 		}
 		pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
 					  DESCRIPTOR_INPUT_LAST |
 					  DESCRIPTOR_BRANCH_ALWAYS);
 		if (packet->interrupt && i == packet_count - 1)
 			pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
 		context_append(&ctx->context, d, z, header_z);
 	}
 	return 0;
 }
 static int queue_iso_buffer_fill(struct iso_context *ctx,
 				 struct fw_iso_packet *packet,
 				 struct fw_iso_buffer *buffer,
 				 unsigned long payload)
 {
 	struct descriptor *d;
 	dma_addr_t d_bus, page_bus;
 	int page, offset, rest, z, i, length;
 	page   = payload >> PAGE_SHIFT;
 	offset = payload & ~PAGE_MASK;
 	rest   = packet->payload_length;
 	/* We need one descriptor for each page in the buffer. */
 	z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
 	if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
 		return -EFAULT;
 	for (i = 0; i < z; i++) {
 		d = context_get_descriptors(&ctx->context, 1, &d_bus);
 		if (d == NULL)
 			return -ENOMEM;
 		d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
 					 DESCRIPTOR_BRANCH_ALWAYS);
 		if (packet->skip && i == 0)
 			d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
 		if (packet->interrupt && i == z - 1)
 			d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
 		if (offset + rest < PAGE_SIZE)
 			length = rest;
 		else
 			length = PAGE_SIZE - offset;
 		d->req_count = cpu_to_le16(length);
 		d->res_count = d->req_count;
 		d->transfer_status = 0;
 		page_bus = page_private(buffer->pages[page]);
 		d->data_address = cpu_to_le32(page_bus + offset);
 		rest -= length;
 		offset = 0;
 		page++;
 		context_append(&ctx->context, d, 1, 0);
 	}
 	return 0;
 }
 static int ohci_queue_iso(struct fw_iso_context *base,
 			  struct fw_iso_packet *packet,
 			  struct fw_iso_buffer *buffer,
 			  unsigned long payload)
 {
 	struct iso_context *ctx = container_of(base, struct iso_context, base);
 	unsigned long flags;
 	int ret = -ENOSYS;
 	spin_lock_irqsave(&ctx->context.ohci->lock, flags);
 	switch (base->type) {
 	case FW_ISO_CONTEXT_TRANSMIT:
 		ret = queue_iso_transmit(ctx, packet, buffer, payload);
 		break;
 	case FW_ISO_CONTEXT_RECEIVE:
 		ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
 		break;
 	case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
 		ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
 		break;
 	}
 	spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
 	return ret;
 }
+static void ohci_flush_queue_iso(struct fw_iso_context *base)
+{
+	struct context *ctx =
+			&container_of(base, struct iso_context, base)->context;
+	reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
+	flush_writes(ctx->ohci);
+}
 static const struct fw_card_driver ohci_driver = {
 	.enable			= ohci_enable,
 	.read_phy_reg		= ohci_read_phy_reg,
 	.update_phy_reg		= ohci_update_phy_reg,
 	.set_config_rom		= ohci_set_config_rom,
 	.send_request		= ohci_send_request,
 	.send_response		= ohci_send_response,
 	.cancel_packet		= ohci_cancel_packet,
 	.enable_phys_dma	= ohci_enable_phys_dma,
 	.read_csr		= ohci_read_csr,
 	.write_csr		= ohci_write_csr,
 	.allocate_iso_context	= ohci_allocate_iso_context,
 	.free_iso_context	= ohci_free_iso_context,
 	.set_iso_channels	= ohci_set_iso_channels,
 	.queue_iso		= ohci_queue_iso,
+	.flush_queue_iso	= ohci_flush_queue_iso,
 	.start_iso		= ohci_start_iso,
 	.stop_iso		= ohci_stop_iso,
 };
 #ifdef CONFIG_PPC_PMAC
 static void pmac_ohci_on(struct pci_dev *dev)
 {
 	if (machine_is(powermac)) {
 		struct device_node *ofn = pci_device_to_OF_node(dev);
 		if (ofn) {
 			pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
 			pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
 		}
 	}
 }
 static void pmac_ohci_off(struct pci_dev *dev)
 {
 	if (machine_is(powermac)) {
 		struct device_node *ofn = pci_device_to_OF_node(dev);
 		if (ofn) {
 			pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
 			pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
 		}
 	}
 }
 #else
 static inline void pmac_ohci_on(struct pci_dev *dev) {}
 static inline void pmac_ohci_off(struct pci_dev *dev) {}
 #endif /* CONFIG_PPC_PMAC */
 static int __devinit pci_probe(struct pci_dev *dev,
 			       const struct pci_device_id *ent)
 {
 	struct fw_ohci *ohci;
 	u32 bus_options, max_receive, link_speed, version;
 	u64 guid;
 	int i, err;
 	size_t size;
 	ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
 	if (ohci == NULL) {
 		err = -ENOMEM;
 		goto fail;
 	}
 	fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
 	pmac_ohci_on(dev);
 	err = pci_enable_device(dev);
 	if (err) {
 		fw_error("Failed to enable OHCI hardware\n");
 		goto fail_free;
 	}
 	pci_set_master(dev);
 	pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
 	pci_set_drvdata(dev, ohci);
 	spin_lock_init(&ohci->lock);
 	mutex_init(&ohci->phy_reg_mutex);
 	tasklet_init(&ohci->bus_reset_tasklet,
 		     bus_reset_tasklet, (unsigned long)ohci);
 	err = pci_request_region(dev, 0, ohci_driver_name);
 	if (err) {
 		fw_error("MMIO resource unavailable\n");
 		goto fail_disable;
 	}
 	ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
 	if (ohci->registers == NULL) {
 		fw_error("Failed to remap registers\n");
 		err = -ENXIO;
 		goto fail_iomem;
 	}
 	for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
 		if ((ohci_quirks[i].vendor == dev->vendor) &&
 		    (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
 		     ohci_quirks[i].device == dev->device) &&
 		    (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
 		     ohci_quirks[i].revision >= dev->revision)) {
 			ohci->quirks = ohci_quirks[i].flags;
 			break;
 		}
 	if (param_quirks)
 		ohci->quirks = param_quirks;
 	/*
 	 * Because dma_alloc_coherent() allocates at least one page,
 	 * we save space by using a common buffer for the AR request/
 	 * response descriptors and the self IDs buffer.
 	 */
 	BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
 	BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
 	ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
 					       PAGE_SIZE,
 					       &ohci->misc_buffer_bus,
 					       GFP_KERNEL);
 	if (!ohci->misc_buffer) {
 		err = -ENOMEM;
 		goto fail_iounmap;
 	}
 	err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
 			      OHCI1394_AsReqRcvContextControlSet);
 	if (err < 0)
 		goto fail_misc_buf;
 	err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
 			      OHCI1394_AsRspRcvContextControlSet);
 	if (err < 0)
 		goto fail_arreq_ctx;
 	err = context_init(&ohci->at_request_ctx, ohci,
 			   OHCI1394_AsReqTrContextControlSet, handle_at_packet);
 	if (err < 0)
 		goto fail_arrsp_ctx;
 	err = context_init(&ohci->at_response_ctx, ohci,
 			   OHCI1394_AsRspTrContextControlSet, handle_at_packet);
 	if (err < 0)
 		goto fail_atreq_ctx;
 	reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
 	ohci->ir_context_channels = ~0ULL;
 	ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
 	reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
 	ohci->ir_context_mask = ohci->ir_context_support;
 	ohci->n_ir = hweight32(ohci->ir_context_mask);
 	size = sizeof(struct iso_context) * ohci->n_ir;
 	ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
 	reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
 	ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
 	reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
 	ohci->it_context_mask = ohci->it_context_support;
 	ohci->n_it = hweight32(ohci->it_context_mask);
 	size = sizeof(struct iso_context) * ohci->n_it;
 	ohci->it_context_list = kzalloc(size, GFP_KERNEL);
 	if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
 		err = -ENOMEM;
 		goto fail_contexts;
 	}
 	ohci->self_id_cpu = ohci->misc_buffer     + PAGE_SIZE/2;
 	ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
 	bus_options = reg_read(ohci, OHCI1394_BusOptions);
 	max_receive = (bus_options >> 12) & 0xf;
 	link_speed = bus_options & 0x7;
 	guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
 		reg_read(ohci, OHCI1394_GUIDLo);
 	err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
 	if (err)
 		goto fail_contexts;
 	version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
 	fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
 		  "%d IR + %d IT contexts, quirks 0x%x\n",
 		  dev_name(&dev->dev), version >> 16, version & 0xff,
 		  ohci->n_ir, ohci->n_it, ohci->quirks);
 	return 0;
  fail_contexts:
 	kfree(ohci->ir_context_list);
 	kfree(ohci->it_context_list);
 	context_release(&ohci->at_response_ctx);
  fail_atreq_ctx:
 	context_release(&ohci->at_request_ctx);
  fail_arrsp_ctx:
 	ar_context_release(&ohci->ar_response_ctx);
  fail_arreq_ctx:
 	ar_context_release(&ohci->ar_request_ctx);
  fail_misc_buf:
 	dma_free_coherent(ohci->card.device, PAGE_SIZE,
 			  ohci->misc_buffer, ohci->misc_buffer_bus);
  fail_iounmap:
 	pci_iounmap(dev, ohci->registers);
  fail_iomem:
 	pci_release_region(dev, 0);
  fail_disable:
 	pci_disable_device(dev);
  fail_free:
 	kfree(ohci);
 	pmac_ohci_off(dev);
  fail:
 	if (err == -ENOMEM)
 		fw_error("Out of memory\n");
 	return err;
 }
 static void pci_remove(struct pci_dev *dev)
 {
 	struct fw_ohci *ohci;
 	ohci = pci_get_drvdata(dev);
 	reg_write(ohci, OHCI1394_IntMaskClear, ~0);
 	flush_writes(ohci);
 	fw_core_remove_card(&ohci->card);
 	/*
 	 * FIXME: Fail all pending packets here, now that the upper
 	 * layers can't queue any more.
 	 */
 	software_reset(ohci);
 	free_irq(dev->irq, ohci);
 	if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
 		dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
 				  ohci->next_config_rom, ohci->next_config_rom_bus);
 	if (ohci->config_rom)
 		dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
 				  ohci->config_rom, ohci->config_rom_bus);
 	ar_context_release(&ohci->ar_request_ctx);
 	ar_context_release(&ohci->ar_response_ctx);
 	dma_free_coherent(ohci->card.device, PAGE_SIZE,
 			  ohci->misc_buffer, ohci->misc_buffer_bus);
 	context_release(&ohci->at_request_ctx);
 	context_release(&ohci->at_response_ctx);
 	kfree(ohci->it_context_list);
 	kfree(ohci->ir_context_list);
 	pci_disable_msi(dev);
 	pci_iounmap(dev, ohci->registers);
 	pci_release_region(dev, 0);
 	pci_disable_device(dev);
 	kfree(ohci);
 	pmac_ohci_off(dev);
 	fw_notify("Removed fw-ohci device.\n");
 }
 #ifdef CONFIG_PM
 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
 {
 	struct fw_ohci *ohci = pci_get_drvdata(dev);
 	int err;
 	software_reset(ohci);
 	free_irq(dev->irq, ohci);
 	pci_disable_msi(dev);
 	err = pci_save_state(dev);
 	if (err) {
 		fw_error("pci_save_state failed\n");
 		return err;
 	}
 	err = pci_set_power_state(dev, pci_choose_state(dev, state));
 	if (err)
 		fw_error("pci_set_power_state failed with %d\n", err);
 	pmac_ohci_off(dev);
 	return 0;
 }
 static int pci_resume(struct pci_dev *dev)
 {
 	struct fw_ohci *ohci = pci_get_drvdata(dev);
 	int err;
 	pmac_ohci_on(dev);
 	pci_set_power_state(dev, PCI_D0);
 	pci_restore_state(dev);
 	err = pci_enable_device(dev);
 	if (err) {
 		fw_error("pci_enable_device failed\n");
 		return err;
 	}
 	/* Some systems don't setup GUID register on resume from ram  */
 	if (!reg_read(ohci, OHCI1394_GUIDLo) &&
 					!reg_read(ohci, OHCI1394_GUIDHi)) {
 		reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
 		reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
 	}
 	err = ohci_enable(&ohci->card, NULL, 0);
 	if (err)
 		return err;
 	ohci_resume_iso_dma(ohci);
 	return 0;
 }
 #endif
 static const struct pci_device_id pci_table[] = {
 	{ PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
 	{ }
 };
 MODULE_DEVICE_TABLE(pci, pci_table);
 static struct pci_driver fw_ohci_pci_driver = {
 	.name		= ohci_driver_name,
 	.id_table	= pci_table,
 	.probe		= pci_probe,
 	.remove		= pci_remove,
 #ifdef CONFIG_PM
 	.resume		= pci_resume,
 	.suspend	= pci_suspend,
 #endif
 };
 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
 MODULE_LICENSE("GPL");
 /* Provide a module alias so root-on-sbp2 initrds don't break. */
 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
 MODULE_ALIAS("ohci1394");
 #endif
 static int __init fw_ohci_init(void)
 {
 	return pci_register_driver(&fw_ohci_pci_driver);
 }
 static void __exit fw_ohci_cleanup(void)
 {
 	pci_unregister_driver(&fw_ohci_pci_driver);
 }

drivers/media/dvb/firewire/firedtv-fw.c

Diff comments View file @ 13882a8

 /*
  * FireDTV driver -- firewire I/O backend
  */
 #include <linux/device.h>
 #include <linux/errno.h>
 #include <linux/firewire.h>
 #include <linux/firewire-constants.h>
 #include <linux/kernel.h>
 #include <linux/list.h>
 #include <linux/mm.h>
 #include <linux/mod_devicetable.h>
 #include <linux/module.h>
 #include <linux/mutex.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
 #include <linux/string.h>
 #include <linux/types.h>
 #include <linux/wait.h>
 #include <linux/workqueue.h>
 #include <asm/page.h>
 #include <asm/system.h>
 #include <dvb_demux.h>
 #include "firedtv.h"
 static LIST_HEAD(node_list);
 static DEFINE_SPINLOCK(node_list_lock);
 static inline struct fw_device *device_of(struct firedtv *fdtv)
 {
 	return fw_device(fdtv->device->parent);
 }
 static int node_req(struct firedtv *fdtv, u64 addr, void *data, size_t len,
 		    int tcode)
 {
 	struct fw_device *device = device_of(fdtv);
 	int rcode, generation = device->generation;
 	smp_rmb(); /* node_id vs. generation */
 	rcode = fw_run_transaction(device->card, tcode, device->node_id,
 			generation, device->max_speed, addr, data, len);
 	return rcode != RCODE_COMPLETE ? -EIO : 0;
 }
 int fdtv_lock(struct firedtv *fdtv, u64 addr, void *data)
 {
 	return node_req(fdtv, addr, data, 8, TCODE_LOCK_COMPARE_SWAP);
 }
 int fdtv_read(struct firedtv *fdtv, u64 addr, void *data)
 {
 	return node_req(fdtv, addr, data, 4, TCODE_READ_QUADLET_REQUEST);
 }
 int fdtv_write(struct firedtv *fdtv, u64 addr, void *data, size_t len)
 {
 	return node_req(fdtv, addr, data, len, TCODE_WRITE_BLOCK_REQUEST);
 }
 #define ISO_HEADER_SIZE			4
 #define CIP_HEADER_SIZE			8
 #define MPEG2_TS_HEADER_SIZE		4
 #define MPEG2_TS_SOURCE_PACKET_SIZE	(4 + 188)
 #define MAX_PACKET_SIZE		1024  /* 776, rounded up to 2^n */
 #define PACKETS_PER_PAGE	(PAGE_SIZE / MAX_PACKET_SIZE)
 #define N_PACKETS		64    /* buffer size */
 #define N_PAGES			DIV_ROUND_UP(N_PACKETS, PACKETS_PER_PAGE)
 #define IRQ_INTERVAL		16
 struct fdtv_ir_context {
 	struct fw_iso_context *context;
 	struct fw_iso_buffer buffer;
 	int interrupt_packet;
 	int current_packet;
 	char *pages[N_PAGES];
 };
 static int queue_iso(struct fdtv_ir_context *ctx, int index)
 {
 	struct fw_iso_packet p;
 	p.payload_length = MAX_PACKET_SIZE;
 	p.interrupt = !(++ctx->interrupt_packet & (IRQ_INTERVAL - 1));
 	p.skip = 0;
 	p.header_length = ISO_HEADER_SIZE;
 	return fw_iso_context_queue(ctx->context, &p, &ctx->buffer,
 				    index * MAX_PACKET_SIZE);
 }
 static void handle_iso(struct fw_iso_context *context, u32 cycle,
 		       size_t header_length, void *header, void *data)
 {
 	struct firedtv *fdtv = data;
 	struct fdtv_ir_context *ctx = fdtv->ir_context;
 	__be32 *h, *h_end;
 	int length, err, i = ctx->current_packet;
 	char *p, *p_end;
 	for (h = header, h_end = h + header_length / 4; h < h_end; h++) {
 		length = be32_to_cpup(h) >> 16;
 		if (unlikely(length > MAX_PACKET_SIZE)) {
 			dev_err(fdtv->device, "length = %d\n", length);
 			length = MAX_PACKET_SIZE;
 		}
 		p = ctx->pages[i / PACKETS_PER_PAGE]
 				+ (i % PACKETS_PER_PAGE) * MAX_PACKET_SIZE;
 		p_end = p + length;
 		for (p += CIP_HEADER_SIZE + MPEG2_TS_HEADER_SIZE; p < p_end;
 		     p += MPEG2_TS_SOURCE_PACKET_SIZE)
 			dvb_dmx_swfilter_packets(&fdtv->demux, p, 1);
 		err = queue_iso(ctx, i);
 		if (unlikely(err))
 			dev_err(fdtv->device, "requeue failed\n");
 		i = (i + 1) & (N_PACKETS - 1);
 	}
+	fw_iso_context_queue_flush(ctx->context);
 	ctx->current_packet = i;
 }
 int fdtv_start_iso(struct firedtv *fdtv)
 {
 	struct fdtv_ir_context *ctx;
 	struct fw_device *device = device_of(fdtv);
 	int i, err;
 	ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
 	if (!ctx)
 		return -ENOMEM;
 	ctx->context = fw_iso_context_create(device->card,
 			FW_ISO_CONTEXT_RECEIVE, fdtv->isochannel,
 			device->max_speed, ISO_HEADER_SIZE, handle_iso, fdtv);
 	if (IS_ERR(ctx->context)) {
 		err = PTR_ERR(ctx->context);
 		goto fail_free;
 	}
 	err = fw_iso_buffer_init(&ctx->buffer, device->card,
 				 N_PAGES, DMA_FROM_DEVICE);
 	if (err)
 		goto fail_context_destroy;
 	ctx->interrupt_packet = 0;
 	ctx->current_packet = 0;
 	for (i = 0; i < N_PAGES; i++)
 		ctx->pages[i] = page_address(ctx->buffer.pages[i]);
 	for (i = 0; i < N_PACKETS; i++) {
 		err = queue_iso(ctx, i);
 		if (err)
 			goto fail;
 	}
 	err = fw_iso_context_start(ctx->context, -1, 0,
 				   FW_ISO_CONTEXT_MATCH_ALL_TAGS);
 	if (err)
 		goto fail;
 	fdtv->ir_context = ctx;
 	return 0;
 fail:
 	fw_iso_buffer_destroy(&ctx->buffer, device->card);
 fail_context_destroy:
 	fw_iso_context_destroy(ctx->context);
 fail_free:
 	kfree(ctx);
 	return err;
 }
 void fdtv_stop_iso(struct firedtv *fdtv)
 {
 	struct fdtv_ir_context *ctx = fdtv->ir_context;
 	fw_iso_context_stop(ctx->context);
 	fw_iso_buffer_destroy(&ctx->buffer, device_of(fdtv)->card);
 	fw_iso_context_destroy(ctx->context);
 	kfree(ctx);
 }
 static void handle_fcp(struct fw_card *card, struct fw_request *request,
 		       int tcode, int destination, int source, int generation,
 		       unsigned long long offset, void *payload, size_t length,
 		       void *callback_data)
 {
 	struct firedtv *f, *fdtv = NULL;
 	struct fw_device *device;
 	unsigned long flags;
 	int su;
 	if (length < 2 || (((u8 *)payload)[0] & 0xf0) != 0)
 		return;
 	su = ((u8 *)payload)[1] & 0x7;
 	spin_lock_irqsave(&node_list_lock, flags);
 	list_for_each_entry(f, &node_list, list) {
 		device = device_of(f);
 		if (device->generation != generation)
 			continue;
 		smp_rmb(); /* node_id vs. generation */
 		if (device->card == card &&
 		    device->node_id == source &&
 		    (f->subunit == su || (f->subunit == 0 && su == 0x7))) {
 			fdtv = f;
 			break;
 		}
 	}
 	spin_unlock_irqrestore(&node_list_lock, flags);
 	if (fdtv)
 		avc_recv(fdtv, payload, length);
 }
 static struct fw_address_handler fcp_handler = {
 	.length           = CSR_FCP_END - CSR_FCP_RESPONSE,
 	.address_callback = handle_fcp,
 };
 static const struct fw_address_region fcp_region = {
 	.start	= CSR_REGISTER_BASE + CSR_FCP_RESPONSE,
 	.end	= CSR_REGISTER_BASE + CSR_FCP_END,
 };
 static const char * const model_names[] = {
 	[FIREDTV_UNKNOWN] = "unknown type",
 	[FIREDTV_DVB_S]   = "FireDTV S/CI",
 	[FIREDTV_DVB_C]   = "FireDTV C/CI",
 	[FIREDTV_DVB_T]   = "FireDTV T/CI",
 	[FIREDTV_DVB_S2]  = "FireDTV S2  ",
 };
 /* Adjust the template string if models with longer names appear. */
 #define MAX_MODEL_NAME_LEN sizeof("FireDTV ????")
 static int node_probe(struct device *dev)
 {
 	struct firedtv *fdtv;
 	char name[MAX_MODEL_NAME_LEN];
 	int name_len, i, err;
 	fdtv = kzalloc(sizeof(*fdtv), GFP_KERNEL);
 	if (!fdtv)
 		return -ENOMEM;
 	dev_set_drvdata(dev, fdtv);
 	fdtv->device		= dev;
 	fdtv->isochannel	= -1;
 	fdtv->voltage		= 0xff;
 	fdtv->tone		= 0xff;
 	mutex_init(&fdtv->avc_mutex);
 	init_waitqueue_head(&fdtv->avc_wait);
 	mutex_init(&fdtv->demux_mutex);
 	INIT_WORK(&fdtv->remote_ctrl_work, avc_remote_ctrl_work);
 	name_len = fw_csr_string(fw_unit(dev)->directory, CSR_MODEL,
 				 name, sizeof(name));
 	for (i = ARRAY_SIZE(model_names); --i; )
 		if (strlen(model_names[i]) <= name_len &&
 		    strncmp(name, model_names[i], name_len) == 0)
 			break;
 	fdtv->type = i;
 	err = fdtv_register_rc(fdtv, dev);
 	if (err)
 		goto fail_free;
 	spin_lock_irq(&node_list_lock);
 	list_add_tail(&fdtv->list, &node_list);
 	spin_unlock_irq(&node_list_lock);
 	err = avc_identify_subunit(fdtv);
 	if (err)
 		goto fail;
 	err = fdtv_dvb_register(fdtv, model_names[fdtv->type]);
 	if (err)
 		goto fail;
 	avc_register_remote_control(fdtv);
 	return 0;
 fail:
 	spin_lock_irq(&node_list_lock);
 	list_del(&fdtv->list);
 	spin_unlock_irq(&node_list_lock);
 	fdtv_unregister_rc(fdtv);
 fail_free:
 	kfree(fdtv);
 	return err;
 }
 static int node_remove(struct device *dev)
 {
 	struct firedtv *fdtv = dev_get_drvdata(dev);
 	fdtv_dvb_unregister(fdtv);
 	spin_lock_irq(&node_list_lock);
 	list_del(&fdtv->list);
 	spin_unlock_irq(&node_list_lock);
 	fdtv_unregister_rc(fdtv);
 	kfree(fdtv);
 	return 0;
 }
 static void node_update(struct fw_unit *unit)
 {
 	struct firedtv *fdtv = dev_get_drvdata(&unit->device);
 	if (fdtv->isochannel >= 0)
 		cmp_establish_pp_connection(fdtv, fdtv->subunit,
 					    fdtv->isochannel);
 }
 #define MATCH_FLAGS (IEEE1394_MATCH_VENDOR_ID | IEEE1394_MATCH_MODEL_ID | \
 		     IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION)
 #define DIGITAL_EVERYWHERE_OUI	0x001287
 #define AVC_UNIT_SPEC_ID_ENTRY	0x00a02d
 #define AVC_SW_VERSION_ENTRY	0x010001
 static const struct ieee1394_device_id fdtv_id_table[] = {
 	{
 		/* FloppyDTV S/CI and FloppyDTV S2 */
 		.match_flags	= MATCH_FLAGS,
 		.vendor_id	= DIGITAL_EVERYWHERE_OUI,
 		.model_id	= 0x000024,
 		.specifier_id	= AVC_UNIT_SPEC_ID_ENTRY,
 		.version	= AVC_SW_VERSION_ENTRY,
 	}, {
 		/* FloppyDTV T/CI */
 		.match_flags	= MATCH_FLAGS,
 		.vendor_id	= DIGITAL_EVERYWHERE_OUI,
 		.model_id	= 0x000025,
 		.specifier_id	= AVC_UNIT_SPEC_ID_ENTRY,
 		.version	= AVC_SW_VERSION_ENTRY,
 	}, {
 		/* FloppyDTV C/CI */
 		.match_flags	= MATCH_FLAGS,
 		.vendor_id	= DIGITAL_EVERYWHERE_OUI,
 		.model_id	= 0x000026,
 		.specifier_id	= AVC_UNIT_SPEC_ID_ENTRY,
 		.version	= AVC_SW_VERSION_ENTRY,
 	}, {
 		/* FireDTV S/CI and FloppyDTV S2 */
 		.match_flags	= MATCH_FLAGS,
 		.vendor_id	= DIGITAL_EVERYWHERE_OUI,
 		.model_id	= 0x000034,
 		.specifier_id	= AVC_UNIT_SPEC_ID_ENTRY,
 		.version	= AVC_SW_VERSION_ENTRY,
 	}, {
 		/* FireDTV T/CI */
 		.match_flags	= MATCH_FLAGS,
 		.vendor_id	= DIGITAL_EVERYWHERE_OUI,
 		.model_id	= 0x000035,
 		.specifier_id	= AVC_UNIT_SPEC_ID_ENTRY,
 		.version	= AVC_SW_VERSION_ENTRY,
 	}, {
 		/* FireDTV C/CI */
 		.match_flags	= MATCH_FLAGS,
 		.vendor_id	= DIGITAL_EVERYWHERE_OUI,
 		.model_id	= 0x000036,
 		.specifier_id	= AVC_UNIT_SPEC_ID_ENTRY,
 		.version	= AVC_SW_VERSION_ENTRY,
 	}, {}
 };
 MODULE_DEVICE_TABLE(ieee1394, fdtv_id_table);
 static struct fw_driver fdtv_driver = {
 	.driver   = {
 		.owner  = THIS_MODULE,
 		.name   = "firedtv",
 		.bus    = &fw_bus_type,
 		.probe  = node_probe,
 		.remove = node_remove,
 	},
 	.update   = node_update,
 	.id_table = fdtv_id_table,
 };
 static int __init fdtv_init(void)
 {
 	int ret;
 	ret = fw_core_add_address_handler(&fcp_handler, &fcp_region);
 	if (ret < 0)
 		return ret;
 	ret = driver_register(&fdtv_driver.driver);
 	if (ret < 0)
 		fw_core_remove_address_handler(&fcp_handler);
 	return ret;
 }
 static void __exit fdtv_exit(void)
 {
 	driver_unregister(&fdtv_driver.driver);
 	fw_core_remove_address_handler(&fcp_handler);
 }
 module_init(fdtv_init);
 module_exit(fdtv_exit);
 MODULE_AUTHOR("Andreas Monitzer <andy@monitzer.com>");
 MODULE_AUTHOR("Ben Backx <ben@bbackx.com>");
 MODULE_DESCRIPTION("FireDTV DVB Driver");
 MODULE_LICENSE("GPL");
 MODULE_SUPPORTED_DEVICE("FireDTV DVB");

include/linux/firewire.h

Diff comments View file @ 13882a8

 #ifndef _LINUX_FIREWIRE_H
 #define _LINUX_FIREWIRE_H
 #include <linux/completion.h>
 #include <linux/device.h>
 #include <linux/dma-mapping.h>
 #include <linux/kernel.h>
 #include <linux/kref.h>
 #include <linux/list.h>
 #include <linux/mutex.h>
 #include <linux/spinlock.h>
 #include <linux/sysfs.h>
 #include <linux/timer.h>
 #include <linux/types.h>
 #include <linux/workqueue.h>
 #include <asm/atomic.h>
 #include <asm/byteorder.h>
 #define fw_notify(s, args...) printk(KERN_NOTICE KBUILD_MODNAME ": " s, ## args)
 #define fw_error(s, args...) printk(KERN_ERR KBUILD_MODNAME ": " s, ## args)
 #define CSR_REGISTER_BASE		0xfffff0000000ULL
 /* register offsets are relative to CSR_REGISTER_BASE */
 #define CSR_STATE_CLEAR			0x0
 #define CSR_STATE_SET			0x4
 #define CSR_NODE_IDS			0x8
 #define CSR_RESET_START			0xc
 #define CSR_SPLIT_TIMEOUT_HI		0x18
 #define CSR_SPLIT_TIMEOUT_LO		0x1c
 #define CSR_CYCLE_TIME			0x200
 #define CSR_BUS_TIME			0x204
 #define CSR_BUSY_TIMEOUT		0x210
 #define CSR_PRIORITY_BUDGET		0x218
 #define CSR_BUS_MANAGER_ID		0x21c
 #define CSR_BANDWIDTH_AVAILABLE		0x220
 #define CSR_CHANNELS_AVAILABLE		0x224
 #define CSR_CHANNELS_AVAILABLE_HI	0x224
 #define CSR_CHANNELS_AVAILABLE_LO	0x228
 #define CSR_MAINT_UTILITY		0x230
 #define CSR_BROADCAST_CHANNEL		0x234
 #define CSR_CONFIG_ROM			0x400
 #define CSR_CONFIG_ROM_END		0x800
 #define CSR_OMPR			0x900
 #define CSR_OPCR(i)			(0x904 + (i) * 4)
 #define CSR_IMPR			0x980
 #define CSR_IPCR(i)			(0x984 + (i) * 4)
 #define CSR_FCP_COMMAND			0xB00
 #define CSR_FCP_RESPONSE		0xD00
 #define CSR_FCP_END			0xF00
 #define CSR_TOPOLOGY_MAP		0x1000
 #define CSR_TOPOLOGY_MAP_END		0x1400
 #define CSR_SPEED_MAP			0x2000
 #define CSR_SPEED_MAP_END		0x3000
 #define CSR_OFFSET		0x40
 #define CSR_LEAF		0x80
 #define CSR_DIRECTORY		0xc0
 #define CSR_DESCRIPTOR		0x01
 #define CSR_VENDOR		0x03
 #define CSR_HARDWARE_VERSION	0x04
 #define CSR_UNIT		0x11
 #define CSR_SPECIFIER_ID	0x12
 #define CSR_VERSION		0x13
 #define CSR_DEPENDENT_INFO	0x14
 #define CSR_MODEL		0x17
 #define CSR_DIRECTORY_ID	0x20
 struct fw_csr_iterator {
 	const u32 *p;
 	const u32 *end;
 };
 void fw_csr_iterator_init(struct fw_csr_iterator *ci, const u32 *p);
 int fw_csr_iterator_next(struct fw_csr_iterator *ci, int *key, int *value);
 int fw_csr_string(const u32 *directory, int key, char *buf, size_t size);
 extern struct bus_type fw_bus_type;
 struct fw_card_driver;
 struct fw_node;
 struct fw_card {
 	const struct fw_card_driver *driver;
 	struct device *device;
 	struct kref kref;
 	struct completion done;
 	int node_id;
 	int generation;
 	int current_tlabel;
 	u64 tlabel_mask;
 	struct list_head transaction_list;
 	u64 reset_jiffies;
 	u32 split_timeout_hi;
 	u32 split_timeout_lo;
 	unsigned int split_timeout_cycles;
 	unsigned int split_timeout_jiffies;
 	unsigned long long guid;
 	unsigned max_receive;
 	int link_speed;
 	int config_rom_generation;
 	spinlock_t lock; /* Take this lock when handling the lists in
 			  * this struct. */
 	struct fw_node *local_node;
 	struct fw_node *root_node;
 	struct fw_node *irm_node;
 	u8 color; /* must be u8 to match the definition in struct fw_node */
 	int gap_count;
 	bool beta_repeaters_present;
 	int index;
 	struct list_head link;
 	struct list_head phy_receiver_list;
 	struct delayed_work br_work; /* bus reset job */
 	bool br_short;
 	struct delayed_work bm_work; /* bus manager job */
 	int bm_retries;
 	int bm_generation;
 	int bm_node_id;
 	bool bm_abdicate;
 	bool priority_budget_implemented;	/* controller feature */
 	bool broadcast_channel_auto_allocated;	/* controller feature */
 	bool broadcast_channel_allocated;
 	u32 broadcast_channel;
 	__be32 topology_map[(CSR_TOPOLOGY_MAP_END - CSR_TOPOLOGY_MAP) / 4];
 	__be32 maint_utility_register;
 };
 struct fw_attribute_group {
 	struct attribute_group *groups[2];
 	struct attribute_group group;
 	struct attribute *attrs[12];
 };
 enum fw_device_state {
 	FW_DEVICE_INITIALIZING,
 	FW_DEVICE_RUNNING,
 	FW_DEVICE_GONE,
 	FW_DEVICE_SHUTDOWN,
 };
 /*
  * Note, fw_device.generation always has to be read before fw_device.node_id.
  * Use SMP memory barriers to ensure this.  Otherwise requests will be sent
  * to an outdated node_id if the generation was updated in the meantime due
  * to a bus reset.
  *
  * Likewise, fw-core will take care to update .node_id before .generation so
  * that whenever fw_device.generation is current WRT the actual bus generation,
  * fw_device.node_id is guaranteed to be current too.
  *
  * The same applies to fw_device.card->node_id vs. fw_device.generation.
  *
  * fw_device.config_rom and fw_device.config_rom_length may be accessed during
  * the lifetime of any fw_unit belonging to the fw_device, before device_del()
  * was called on the last fw_unit.  Alternatively, they may be accessed while
  * holding fw_device_rwsem.
  */
 struct fw_device {
 	atomic_t state;
 	struct fw_node *node;
 	int node_id;
 	int generation;
 	unsigned max_speed;
 	struct fw_card *card;
 	struct device device;
 	struct mutex client_list_mutex;
 	struct list_head client_list;
 	const u32 *config_rom;
 	size_t config_rom_length;
 	int config_rom_retries;
 	unsigned is_local:1;
 	unsigned max_rec:4;
 	unsigned cmc:1;
 	unsigned irmc:1;
 	unsigned bc_implemented:2;
 	struct delayed_work work;
 	struct fw_attribute_group attribute_group;
 };
 static inline struct fw_device *fw_device(struct device *dev)
 {
 	return container_of(dev, struct fw_device, device);
 }
 static inline int fw_device_is_shutdown(struct fw_device *device)
 {
 	return atomic_read(&device->state) == FW_DEVICE_SHUTDOWN;
 }
 static inline struct fw_device *fw_device_get(struct fw_device *device)
 {
 	get_device(&device->device);
 	return device;
 }
 static inline void fw_device_put(struct fw_device *device)
 {
 	put_device(&device->device);
 }
 int fw_device_enable_phys_dma(struct fw_device *device);
 /*
  * fw_unit.directory must not be accessed after device_del(&fw_unit.device).
  */
 struct fw_unit {
 	struct device device;
 	const u32 *directory;
 	struct fw_attribute_group attribute_group;
 };
 static inline struct fw_unit *fw_unit(struct device *dev)
 {
 	return container_of(dev, struct fw_unit, device);
 }
 static inline struct fw_unit *fw_unit_get(struct fw_unit *unit)
 {
 	get_device(&unit->device);
 	return unit;
 }
 static inline void fw_unit_put(struct fw_unit *unit)
 {
 	put_device(&unit->device);
 }
 static inline struct fw_device *fw_parent_device(struct fw_unit *unit)
 {
 	return fw_device(unit->device.parent);
 }
 struct ieee1394_device_id;
 struct fw_driver {
 	struct device_driver driver;
 	/* Called when the parent device sits through a bus reset. */
 	void (*update)(struct fw_unit *unit);
 	const struct ieee1394_device_id *id_table;
 };
 struct fw_packet;
 struct fw_request;
 typedef void (*fw_packet_callback_t)(struct fw_packet *packet,
 				     struct fw_card *card, int status);
 typedef void (*fw_transaction_callback_t)(struct fw_card *card, int rcode,
 					  void *data, size_t length,
 					  void *callback_data);
 /*
  * Important note:  Except for the FCP registers, the callback must guarantee
  * that either fw_send_response() or kfree() is called on the @request.
  */
 typedef void (*fw_address_callback_t)(struct fw_card *card,
 				      struct fw_request *request,
 				      int tcode, int destination, int source,
 				      int generation,
 				      unsigned long long offset,
 				      void *data, size_t length,
 				      void *callback_data);
 struct fw_packet {
 	int speed;
 	int generation;
 	u32 header[4];
 	size_t header_length;
 	void *payload;
 	size_t payload_length;
 	dma_addr_t payload_bus;
 	bool payload_mapped;
 	u32 timestamp;
 	/*
 	 * This callback is called when the packet transmission has completed.
 	 * For successful transmission, the status code is the ack received
 	 * from the destination.  Otherwise it is one of the juju-specific
 	 * rcodes:  RCODE_SEND_ERROR, _CANCELLED, _BUSY, _GENERATION, _NO_ACK.
 	 * The callback can be called from tasklet context and thus
 	 * must never block.
 	 */
 	fw_packet_callback_t callback;
 	int ack;
 	struct list_head link;
 	void *driver_data;
 };
 struct fw_transaction {
 	int node_id; /* The generation is implied; it is always the current. */
 	int tlabel;
 	struct list_head link;
 	struct fw_card *card;
 	bool is_split_transaction;
 	struct timer_list split_timeout_timer;
 	struct fw_packet packet;
 	/*
 	 * The data passed to the callback is valid only during the
 	 * callback.
 	 */
 	fw_transaction_callback_t callback;
 	void *callback_data;
 };
 struct fw_address_handler {
 	u64 offset;
 	size_t length;
 	fw_address_callback_t address_callback;
 	void *callback_data;
 	struct list_head link;
 };
 struct fw_address_region {
 	u64 start;
 	u64 end;
 };
 extern const struct fw_address_region fw_high_memory_region;
 int fw_core_add_address_handler(struct fw_address_handler *handler,
 				const struct fw_address_region *region);
 void fw_core_remove_address_handler(struct fw_address_handler *handler);
 void fw_send_response(struct fw_card *card,
 		      struct fw_request *request, int rcode);
 void fw_send_request(struct fw_card *card, struct fw_transaction *t,
 		     int tcode, int destination_id, int generation, int speed,
 		     unsigned long long offset, void *payload, size_t length,
 		     fw_transaction_callback_t callback, void *callback_data);
 int fw_cancel_transaction(struct fw_card *card,
 			  struct fw_transaction *transaction);
 int fw_run_transaction(struct fw_card *card, int tcode, int destination_id,
 		       int generation, int speed, unsigned long long offset,
 		       void *payload, size_t length);
 static inline int fw_stream_packet_destination_id(int tag, int channel, int sy)
 {
 	return tag << 14 | channel << 8 | sy;
 }
 struct fw_descriptor {
 	struct list_head link;
 	size_t length;
 	u32 immediate;
 	u32 key;
 	const u32 *data;
 };
 int fw_core_add_descriptor(struct fw_descriptor *desc);
 void fw_core_remove_descriptor(struct fw_descriptor *desc);
 /*
  * The iso packet format allows for an immediate header/payload part
  * stored in 'header' immediately after the packet info plus an
  * indirect payload part that is pointer to by the 'payload' field.
  * Applications can use one or the other or both to implement simple
  * low-bandwidth streaming (e.g. audio) or more advanced
  * scatter-gather streaming (e.g. assembling video frame automatically).
  */
 struct fw_iso_packet {
 	u16 payload_length;	/* Length of indirect payload		*/
 	u32 interrupt:1;	/* Generate interrupt on this packet	*/
 	u32 skip:1;		/* tx: Set to not send packet at all	*/
 				/* rx: Sync bit, wait for matching sy	*/
 	u32 tag:2;		/* tx: Tag in packet header		*/
 	u32 sy:4;		/* tx: Sy in packet header		*/
 	u32 header_length:8;	/* Length of immediate header		*/
 	u32 header[0];		/* tx: Top of 1394 isoch. data_block	*/
 };
 #define FW_ISO_CONTEXT_TRANSMIT			0
 #define FW_ISO_CONTEXT_RECEIVE			1
 #define FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL	2
 #define FW_ISO_CONTEXT_MATCH_TAG0	 1
 #define FW_ISO_CONTEXT_MATCH_TAG1	 2
 #define FW_ISO_CONTEXT_MATCH_TAG2	 4
 #define FW_ISO_CONTEXT_MATCH_TAG3	 8
 #define FW_ISO_CONTEXT_MATCH_ALL_TAGS	15
 /*
  * An iso buffer is just a set of pages mapped for DMA in the
  * specified direction.  Since the pages are to be used for DMA, they
  * are not mapped into the kernel virtual address space.  We store the
  * DMA address in the page private. The helper function
  * fw_iso_buffer_map() will map the pages into a given vma.
  */
 struct fw_iso_buffer {
 	enum dma_data_direction direction;
 	struct page **pages;
 	int page_count;
 };
 int fw_iso_buffer_init(struct fw_iso_buffer *buffer, struct fw_card *card,
 		       int page_count, enum dma_data_direction direction);
 void fw_iso_buffer_destroy(struct fw_iso_buffer *buffer, struct fw_card *card);
 size_t fw_iso_buffer_lookup(struct fw_iso_buffer *buffer, dma_addr_t completed);
 struct fw_iso_context;
 typedef void (*fw_iso_callback_t)(struct fw_iso_context *context,
 				  u32 cycle, size_t header_length,
 				  void *header, void *data);
 typedef void (*fw_iso_mc_callback_t)(struct fw_iso_context *context,
 				     dma_addr_t completed, void *data);
 struct fw_iso_context {
 	struct fw_card *card;
 	int type;
 	int channel;
 	int speed;
 	size_t header_size;
 	union {
 		fw_iso_callback_t sc;
 		fw_iso_mc_callback_t mc;
 	} callback;
 	void *callback_data;
 };
 struct fw_iso_context *fw_iso_context_create(struct fw_card *card,
 		int type, int channel, int speed, size_t header_size,
 		fw_iso_callback_t callback, void *callback_data);
 int fw_iso_context_set_channels(struct fw_iso_context *ctx, u64 *channels);
 int fw_iso_context_queue(struct fw_iso_context *ctx,
 			 struct fw_iso_packet *packet,
 			 struct fw_iso_buffer *buffer,
 			 unsigned long payload);
+void fw_iso_context_queue_flush(struct fw_iso_context *ctx);
 int fw_iso_context_start(struct fw_iso_context *ctx,
 			 int cycle, int sync, int tags);
 int fw_iso_context_stop(struct fw_iso_context *ctx);
 void fw_iso_context_destroy(struct fw_iso_context *ctx);
 void fw_iso_resource_manage(struct fw_card *card, int generation,
 			    u64 channels_mask, int *channel, int *bandwidth,
 			    bool allocate);
 #endif /* _LINUX_FIREWIRE_H */

sound/firewire/amdtp.c

Diff comments View file @ 13882a8

 /*
  * Audio and Music Data Transmission Protocol (IEC 61883-6) streams
  * with Common Isochronous Packet (IEC 61883-1) headers
  *
  * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
  * Licensed under the terms of the GNU General Public License, version 2.
  */
 #include <linux/device.h>
 #include <linux/err.h>
 #include <linux/firewire.h>
 #include <linux/module.h>
 #include <linux/slab.h>
 #include <sound/pcm.h>
 #include "amdtp.h"
 #define TICKS_PER_CYCLE		3072
 #define CYCLES_PER_SECOND	8000
 #define TICKS_PER_SECOND	(TICKS_PER_CYCLE * CYCLES_PER_SECOND)
 #define TRANSFER_DELAY_TICKS	0x2e00 /* 479.17 µs */
 #define TAG_CIP			1
 #define CIP_EOH			(1u << 31)
 #define CIP_FMT_AM		(0x10 << 24)
 #define AMDTP_FDF_AM824		(0 << 19)
 #define AMDTP_FDF_SFC_SHIFT	16
 /* TODO: make these configurable */
 #define INTERRUPT_INTERVAL	16
 #define QUEUE_LENGTH		48
 /**
  * amdtp_out_stream_init - initialize an AMDTP output stream structure
  * @s: the AMDTP output stream to initialize
  * @unit: the target of the stream
  * @flags: the packet transmission method to use
  */
 int amdtp_out_stream_init(struct amdtp_out_stream *s, struct fw_unit *unit,
 			  enum cip_out_flags flags)
 {
 	if (flags != CIP_NONBLOCKING)
 		return -EINVAL;
 	s->unit = fw_unit_get(unit);
 	s->flags = flags;
 	s->context = ERR_PTR(-1);
 	mutex_init(&s->mutex);
 	s->packet_index = 0;
 	return 0;
 }
 EXPORT_SYMBOL(amdtp_out_stream_init);
 /**
  * amdtp_out_stream_destroy - free stream resources
  * @s: the AMDTP output stream to destroy
  */
 void amdtp_out_stream_destroy(struct amdtp_out_stream *s)
 {
 	WARN_ON(!IS_ERR(s->context));
 	mutex_destroy(&s->mutex);
 	fw_unit_put(s->unit);
 }
 EXPORT_SYMBOL(amdtp_out_stream_destroy);
 /**
  * amdtp_out_stream_set_rate - set the sample rate
  * @s: the AMDTP output stream to configure
  * @rate: the sample rate
  *
  * The sample rate must be set before the stream is started, and must not be
  * changed while the stream is running.
  */
 void amdtp_out_stream_set_rate(struct amdtp_out_stream *s, unsigned int rate)
 {
 	static const struct {
 		unsigned int rate;
 		unsigned int syt_interval;
 	} rate_info[] = {
 		[CIP_SFC_32000]  = {  32000,  8, },
 		[CIP_SFC_44100]  = {  44100,  8, },
 		[CIP_SFC_48000]  = {  48000,  8, },
 		[CIP_SFC_88200]  = {  88200, 16, },
 		[CIP_SFC_96000]  = {  96000, 16, },
 		[CIP_SFC_176400] = { 176400, 32, },
 		[CIP_SFC_192000] = { 192000, 32, },
 	};
 	unsigned int sfc;
 	if (WARN_ON(!IS_ERR(s->context)))
 		return;
 	for (sfc = 0; sfc < ARRAY_SIZE(rate_info); ++sfc)
 		if (rate_info[sfc].rate == rate) {
 			s->sfc = sfc;
 			s->syt_interval = rate_info[sfc].syt_interval;
 			return;
 		}
 	WARN_ON(1);
 }
 EXPORT_SYMBOL(amdtp_out_stream_set_rate);
 /**
  * amdtp_out_stream_get_max_payload - get the stream's packet size
  * @s: the AMDTP output stream
  *
  * This function must not be called before the stream has been configured
  * with amdtp_out_stream_set_hw_params(), amdtp_out_stream_set_pcm(), and
  * amdtp_out_stream_set_midi().
  */
 unsigned int amdtp_out_stream_get_max_payload(struct amdtp_out_stream *s)
 {
 	static const unsigned int max_data_blocks[] = {
 		[CIP_SFC_32000]  =  4,
 		[CIP_SFC_44100]  =  6,
 		[CIP_SFC_48000]  =  6,
 		[CIP_SFC_88200]  = 12,
 		[CIP_SFC_96000]  = 12,
 		[CIP_SFC_176400] = 23,
 		[CIP_SFC_192000] = 24,
 	};
 	s->data_block_quadlets = s->pcm_channels;
 	s->data_block_quadlets += DIV_ROUND_UP(s->midi_ports, 8);
 	return 8 + max_data_blocks[s->sfc] * 4 * s->data_block_quadlets;
 }
 EXPORT_SYMBOL(amdtp_out_stream_get_max_payload);
 static void amdtp_write_s16(struct amdtp_out_stream *s,
 			    struct snd_pcm_substream *pcm,
 			    __be32 *buffer, unsigned int frames);
 static void amdtp_write_s32(struct amdtp_out_stream *s,
 			    struct snd_pcm_substream *pcm,
 			    __be32 *buffer, unsigned int frames);
 /**
  * amdtp_out_stream_set_pcm_format - set the PCM format
  * @s: the AMDTP output stream to configure
  * @format: the format of the ALSA PCM device
  *
  * The sample format must be set before the stream is started, and must not be
  * changed while the stream is running.
  */
 void amdtp_out_stream_set_pcm_format(struct amdtp_out_stream *s,
 				     snd_pcm_format_t format)
 {
 	if (WARN_ON(!IS_ERR(s->context)))
 		return;
 	switch (format) {
 	default:
 		WARN_ON(1);
 		/* fall through */
 	case SNDRV_PCM_FORMAT_S16:
 		s->transfer_samples = amdtp_write_s16;
 		break;
 	case SNDRV_PCM_FORMAT_S32:
 		s->transfer_samples = amdtp_write_s32;
 		break;
 	}
 }
 EXPORT_SYMBOL(amdtp_out_stream_set_pcm_format);
 static unsigned int calculate_data_blocks(struct amdtp_out_stream *s)
 {
 	unsigned int phase, data_blocks;
 	if (!cip_sfc_is_base_44100(s->sfc)) {
 		/* Sample_rate / 8000 is an integer, and precomputed. */
 		data_blocks = s->data_block_state;
 	} else {
 		phase = s->data_block_state;
 		/*
 		 * This calculates the number of data blocks per packet so that
 		 * 1) the overall rate is correct and exactly synchronized to
 		 *    the bus clock, and
 		 * 2) packets with a rounded-up number of blocks occur as early
 		 *    as possible in the sequence (to prevent underruns of the
 		 *    device's buffer).
 		 */
 		if (s->sfc == CIP_SFC_44100)
 			/* 6 6 5 6 5 6 5 ... */
 			data_blocks = 5 + ((phase & 1) ^
 					   (phase == 0 || phase >= 40));
 		else
 			/* 12 11 11 11 11 ... or 23 22 22 22 22 ... */
 			data_blocks = 11 * (s->sfc >> 1) + (phase == 0);
 		if (++phase >= (80 >> (s->sfc >> 1)))
 			phase = 0;
 		s->data_block_state = phase;
 	}
 	return data_blocks;
 }
 static unsigned int calculate_syt(struct amdtp_out_stream *s,
 				  unsigned int cycle)
 {
 	unsigned int syt_offset, phase, index, syt;
 	if (s->last_syt_offset < TICKS_PER_CYCLE) {
 		if (!cip_sfc_is_base_44100(s->sfc))
 			syt_offset = s->last_syt_offset + s->syt_offset_state;
 		else {
 		/*
 		 * The time, in ticks, of the n'th SYT_INTERVAL sample is:
 		 *   n * SYT_INTERVAL * 24576000 / sample_rate
 		 * Modulo TICKS_PER_CYCLE, the difference between successive
 		 * elements is about 1386.23.  Rounding the results of this
 		 * formula to the SYT precision results in a sequence of
 		 * differences that begins with:
 		 *   1386 1386 1387 1386 1386 1386 1387 1386 1386 1386 1387 ...
 		 * This code generates _exactly_ the same sequence.
 		 */
 			phase = s->syt_offset_state;
 			index = phase % 13;
 			syt_offset = s->last_syt_offset;
 			syt_offset += 1386 + ((index && !(index & 3)) ||
 					      phase == 146);
 			if (++phase >= 147)
 				phase = 0;
 			s->syt_offset_state = phase;
 		}
 	} else
 		syt_offset = s->last_syt_offset - TICKS_PER_CYCLE;
 	s->last_syt_offset = syt_offset;
 	if (syt_offset < TICKS_PER_CYCLE) {
 		syt_offset += TRANSFER_DELAY_TICKS - TICKS_PER_CYCLE;
 		syt = (cycle + syt_offset / TICKS_PER_CYCLE) << 12;
 		syt += syt_offset % TICKS_PER_CYCLE;
 		return syt & 0xffff;
 	} else {
 		return 0xffff; /* no info */
 	}
 }
 static void amdtp_write_s32(struct amdtp_out_stream *s,
 			    struct snd_pcm_substream *pcm,
 			    __be32 *buffer, unsigned int frames)
 {
 	struct snd_pcm_runtime *runtime = pcm->runtime;
 	unsigned int channels, remaining_frames, frame_step, i, c;
 	const u32 *src;
 	channels = s->pcm_channels;
 	src = (void *)runtime->dma_area +
 			s->pcm_buffer_pointer * (runtime->frame_bits / 8);
 	remaining_frames = runtime->buffer_size - s->pcm_buffer_pointer;
 	frame_step = s->data_block_quadlets - channels;
 	for (i = 0; i < frames; ++i) {
 		for (c = 0; c < channels; ++c) {
 			*buffer = cpu_to_be32((*src >> 8) | 0x40000000);
 			src++;
 			buffer++;
 		}
 		buffer += frame_step;
 		if (--remaining_frames == 0)
 			src = (void *)runtime->dma_area;
 	}
 }
 static void amdtp_write_s16(struct amdtp_out_stream *s,
 			    struct snd_pcm_substream *pcm,
 			    __be32 *buffer, unsigned int frames)
 {
 	struct snd_pcm_runtime *runtime = pcm->runtime;
 	unsigned int channels, remaining_frames, frame_step, i, c;
 	const u16 *src;
 	channels = s->pcm_channels;
 	src = (void *)runtime->dma_area +
 			s->pcm_buffer_pointer * (runtime->frame_bits / 8);
 	remaining_frames = runtime->buffer_size - s->pcm_buffer_pointer;
 	frame_step = s->data_block_quadlets - channels;
 	for (i = 0; i < frames; ++i) {
 		for (c = 0; c < channels; ++c) {
 			*buffer = cpu_to_be32((*src << 8) | 0x40000000);
 			src++;
 			buffer++;
 		}
 		buffer += frame_step;
 		if (--remaining_frames == 0)
 			src = (void *)runtime->dma_area;
 	}
 }
 static void amdtp_fill_pcm_silence(struct amdtp_out_stream *s,
 				   __be32 *buffer, unsigned int frames)
 {
 	unsigned int i, c;
 	for (i = 0; i < frames; ++i) {
 		for (c = 0; c < s->pcm_channels; ++c)
 			buffer[c] = cpu_to_be32(0x40000000);
 		buffer += s->data_block_quadlets;
 	}
 }
 static void amdtp_fill_midi(struct amdtp_out_stream *s,
 			    __be32 *buffer, unsigned int frames)
 {
 	unsigned int i;
 	for (i = 0; i < frames; ++i)
 		buffer[s->pcm_channels + i * s->data_block_quadlets] =
 						cpu_to_be32(0x80000000);
 }
 static void queue_out_packet(struct amdtp_out_stream *s, unsigned int cycle)
 {
 	__be32 *buffer;
 	unsigned int index, data_blocks, syt, ptr;
 	struct snd_pcm_substream *pcm;
 	struct fw_iso_packet packet;
 	int err;
 	if (s->packet_index < 0)
 		return;
 	index = s->packet_index;
 	data_blocks = calculate_data_blocks(s);
 	syt = calculate_syt(s, cycle);
 	buffer = s->buffer.packets[index].buffer;
 	buffer[0] = cpu_to_be32(ACCESS_ONCE(s->source_node_id_field) |
 				(s->data_block_quadlets << 16) |
 				s->data_block_counter);
 	buffer[1] = cpu_to_be32(CIP_EOH | CIP_FMT_AM | AMDTP_FDF_AM824 |
 				(s->sfc << AMDTP_FDF_SFC_SHIFT) | syt);
 	buffer += 2;
 	pcm = ACCESS_ONCE(s->pcm);
 	if (pcm)
 		s->transfer_samples(s, pcm, buffer, data_blocks);
 	else
 		amdtp_fill_pcm_silence(s, buffer, data_blocks);
 	if (s->midi_ports)
 		amdtp_fill_midi(s, buffer, data_blocks);
 	s->data_block_counter = (s->data_block_counter + data_blocks) & 0xff;
 	packet.payload_length = 8 + data_blocks * 4 * s->data_block_quadlets;
 	packet.interrupt = IS_ALIGNED(index + 1, INTERRUPT_INTERVAL);
 	packet.skip = 0;
 	packet.tag = TAG_CIP;
 	packet.sy = 0;
 	packet.header_length = 0;
 	err = fw_iso_context_queue(s->context, &packet, &s->buffer.iso_buffer,
 				   s->buffer.packets[index].offset);
 	if (err < 0) {
 		dev_err(&s->unit->device, "queueing error: %d\n", err);
 		s->packet_index = -1;
 		amdtp_out_stream_pcm_abort(s);
 		return;
 	}
 	if (++index >= QUEUE_LENGTH)
 		index = 0;
 	s->packet_index = index;
 	if (pcm) {
 		ptr = s->pcm_buffer_pointer + data_blocks;
 		if (ptr >= pcm->runtime->buffer_size)
 			ptr -= pcm->runtime->buffer_size;
 		ACCESS_ONCE(s->pcm_buffer_pointer) = ptr;
 		s->pcm_period_pointer += data_blocks;
 		if (s->pcm_period_pointer >= pcm->runtime->period_size) {
 			s->pcm_period_pointer -= pcm->runtime->period_size;
 			snd_pcm_period_elapsed(pcm);
 		}
 	}
 }
 static void out_packet_callback(struct fw_iso_context *context, u32 cycle,
 				size_t header_length, void *header, void *data)
 {
 	struct amdtp_out_stream *s = data;
 	unsigned int i, packets = header_length / 4;
 	/*
 	 * Compute the cycle of the last queued packet.
 	 * (We need only the four lowest bits for the SYT, so we can ignore
 	 * that bits 0-11 must wrap around at 3072.)
 	 */
 	cycle += QUEUE_LENGTH - packets;
 	for (i = 0; i < packets; ++i)
 		queue_out_packet(s, ++cycle);
+	fw_iso_context_queue_flush(s->context);
 }
 static int queue_initial_skip_packets(struct amdtp_out_stream *s)
 {
 	struct fw_iso_packet skip_packet = {
 		.skip = 1,
 	};
 	unsigned int i;
 	int err;
 	for (i = 0; i < QUEUE_LENGTH; ++i) {
 		skip_packet.interrupt = IS_ALIGNED(s->packet_index + 1,
 						   INTERRUPT_INTERVAL);
 		err = fw_iso_context_queue(s->context, &skip_packet, NULL, 0);
 		if (err < 0)
 			return err;
 		if (++s->packet_index >= QUEUE_LENGTH)
 			s->packet_index = 0;
 	}
 	return 0;
 }
 /**
  * amdtp_out_stream_start - start sending packets
  * @s: the AMDTP output stream to start
  * @channel: the isochronous channel on the bus
  * @speed: firewire speed code
  *
  * The stream cannot be started until it has been configured with
  * amdtp_out_stream_set_hw_params(), amdtp_out_stream_set_pcm(), and
  * amdtp_out_stream_set_midi(); and it must be started before any
  * PCM or MIDI device can be started.
  */
 int amdtp_out_stream_start(struct amdtp_out_stream *s, int channel, int speed)
 {
 	static const struct {
 		unsigned int data_block;
 		unsigned int syt_offset;
 	} initial_state[] = {
 		[CIP_SFC_32000]  = {  4, 3072 },
 		[CIP_SFC_48000]  = {  6, 1024 },
 		[CIP_SFC_96000]  = { 12, 1024 },
 		[CIP_SFC_192000] = { 24, 1024 },
 		[CIP_SFC_44100]  = {  0,   67 },
 		[CIP_SFC_88200]  = {  0,   67 },
 		[CIP_SFC_176400] = {  0,   67 },
 	};
 	int err;
 	mutex_lock(&s->mutex);
 	if (WARN_ON(!IS_ERR(s->context) ||
 		    (!s->pcm_channels && !s->midi_ports))) {
 		err = -EBADFD;
 		goto err_unlock;
 	}
 	s->data_block_state = initial_state[s->sfc].data_block;
 	s->syt_offset_state = initial_state[s->sfc].syt_offset;
 	s->last_syt_offset = TICKS_PER_CYCLE;
 	err = iso_packets_buffer_init(&s->buffer, s->unit, QUEUE_LENGTH,
 				      amdtp_out_stream_get_max_payload(s),
 				      DMA_TO_DEVICE);
 	if (err < 0)
 		goto err_unlock;
 	s->context = fw_iso_context_create(fw_parent_device(s->unit)->card,
 					   FW_ISO_CONTEXT_TRANSMIT,
 					   channel, speed, 0,
 					   out_packet_callback, s);
 	if (IS_ERR(s->context)) {
 		err = PTR_ERR(s->context);
 		if (err == -EBUSY)
 			dev_err(&s->unit->device,
 				"no free output stream on this controller\n");
 		goto err_buffer;
 	}
 	amdtp_out_stream_update(s);
 	s->packet_index = 0;
 	s->data_block_counter = 0;
 	err = queue_initial_skip_packets(s);
 	if (err < 0)
 		goto err_context;
 	err = fw_iso_context_start(s->context, -1, 0, 0);
 	if (err < 0)
 		goto err_context;
 	mutex_unlock(&s->mutex);
 	return 0;
 err_context:
 	fw_iso_context_destroy(s->context);
 	s->context = ERR_PTR(-1);
 err_buffer:
 	iso_packets_buffer_destroy(&s->buffer, s->unit);
 err_unlock:
 	mutex_unlock(&s->mutex);
 	return err;
 }
 EXPORT_SYMBOL(amdtp_out_stream_start);
 /**
  * amdtp_out_stream_update - update the stream after a bus reset
  * @s: the AMDTP output stream
  */
 void amdtp_out_stream_update(struct amdtp_out_stream *s)
 {
 	ACCESS_ONCE(s->source_node_id_field) =
 		(fw_parent_device(s->unit)->card->node_id & 0x3f) << 24;
 }
 EXPORT_SYMBOL(amdtp_out_stream_update);
 /**
  * amdtp_out_stream_stop - stop sending packets
  * @s: the AMDTP output stream to stop
  *
  * All PCM and MIDI devices of the stream must be stopped before the stream
  * itself can be stopped.
  */
 void amdtp_out_stream_stop(struct amdtp_out_stream *s)
 {
 	mutex_lock(&s->mutex);
 	if (IS_ERR(s->context)) {
 		mutex_unlock(&s->mutex);
 		return;
 	}
 	fw_iso_context_stop(s->context);
 	fw_iso_context_destroy(s->context);
 	s->context = ERR_PTR(-1);
 	iso_packets_buffer_destroy(&s->buffer, s->unit);
 	mutex_unlock(&s->mutex);
 }
 EXPORT_SYMBOL(amdtp_out_stream_stop);
 /**
  * amdtp_out_stream_pcm_abort - abort the running PCM device
  * @s: the AMDTP stream about to be stopped
  *
  * If the isochronous stream needs to be stopped asynchronously, call this
  * function first to stop the PCM device.
  */
 void amdtp_out_stream_pcm_abort(struct amdtp_out_stream *s)
 {
 	struct snd_pcm_substream *pcm;
 	pcm = ACCESS_ONCE(s->pcm);
 	if (pcm) {
 		snd_pcm_stream_lock_irq(pcm);
 		if (snd_pcm_running(pcm))
 			snd_pcm_stop(pcm, SNDRV_PCM_STATE_XRUN);
 		snd_pcm_stream_unlock_irq(pcm);
 	}
 }
 EXPORT_SYMBOL(amdtp_out_stream_pcm_abort);