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Commit 13e859745cf8cf0e6602759b1ef2abcb9ced7991

Authored by Andy Shevchenko 2012-08-02 21:06:47 +0800

Committed by David Woodhouse 2012-09-29 21:59:28 +0800

Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches

mtd: use %*ph[CN] to dump small buffers

There is new format specified that helps to dump small buffers. It makes the
code simpler and nicer.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Jiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>

Showing 4 changed files with 14 additions and 41 deletions Inline Diff

drivers/mtd/devices/doc2001plus.c
drivers/mtd/devices/docg3.c
drivers/mtd/nand/bcm_umi_bch.c
drivers/mtd/nand/s3c2410.c

drivers/mtd/devices/doc2001plus.c

Diff comments View file @ 13e8597

 /*
  * Linux driver for Disk-On-Chip Millennium Plus
  *
  * (c) 2002-2003 Greg Ungerer <gerg@snapgear.com>
  * (c) 2002-2003 SnapGear Inc
  * (c) 1999 Machine Vision Holdings, Inc.
  * (c) 1999, 2000 David Woodhouse <dwmw2@infradead.org>
  *
  * Released under GPL
  */
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/uaccess.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
 #include <linux/init.h>
 #include <linux/types.h>
 #include <linux/bitops.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/doc2000.h>
 /* #define ECC_DEBUG */
 /* I have no idea why some DoC chips can not use memcop_form|to_io().
  * This may be due to the different revisions of the ASIC controller built-in or
  * simplily a QA/Bug issue. Who knows ?? If you have trouble, please uncomment
  * this:*/
 #undef USE_MEMCPY
 static int doc_read(struct mtd_info *mtd, loff_t from, size_t len,
 		size_t *retlen, u_char *buf);
 static int doc_write(struct mtd_info *mtd, loff_t to, size_t len,
 		size_t *retlen, const u_char *buf);
 static int doc_read_oob(struct mtd_info *mtd, loff_t ofs,
 			struct mtd_oob_ops *ops);
 static int doc_write_oob(struct mtd_info *mtd, loff_t ofs,
 			 struct mtd_oob_ops *ops);
 static int doc_erase (struct mtd_info *mtd, struct erase_info *instr);
 static struct mtd_info *docmilpluslist = NULL;
 /* Perform the required delay cycles by writing to the NOP register */
 static void DoC_Delay(void __iomem * docptr, int cycles)
 {
 	int i;
 	for (i = 0; (i < cycles); i++)
 		WriteDOC(0, docptr, Mplus_NOP);
 }
 #define	CDSN_CTRL_FR_B_MASK	(CDSN_CTRL_FR_B0 | CDSN_CTRL_FR_B1)
 /* DOC_WaitReady: Wait for RDY line to be asserted by the flash chip */
 static int _DoC_WaitReady(void __iomem * docptr)
 {
 	unsigned int c = 0xffff;
 	pr_debug("_DoC_WaitReady called for out-of-line wait\n");
 	/* Out-of-line routine to wait for chip response */
 	while (((ReadDOC(docptr, Mplus_FlashControl) & CDSN_CTRL_FR_B_MASK) != CDSN_CTRL_FR_B_MASK) && --c)
 		;
 	if (c == 0)
 		pr_debug("_DoC_WaitReady timed out.\n");
 	return (c == 0);
 }
 static inline int DoC_WaitReady(void __iomem * docptr)
 {
 	/* This is inline, to optimise the common case, where it's ready instantly */
 	int ret = 0;
 	/* read form NOP register should be issued prior to the read from CDSNControl
 	   see Software Requirement 11.4 item 2. */
 	DoC_Delay(docptr, 4);
 	if ((ReadDOC(docptr, Mplus_FlashControl) & CDSN_CTRL_FR_B_MASK) != CDSN_CTRL_FR_B_MASK)
 		/* Call the out-of-line routine to wait */
 		ret = _DoC_WaitReady(docptr);
 	return ret;
 }
 /* For some reason the Millennium Plus seems to occasionally put itself
  * into reset mode. For me this happens randomly, with no pattern that I
  * can detect. M-systems suggest always check this on any block level
  * operation and setting to normal mode if in reset mode.
  */
 static inline void DoC_CheckASIC(void __iomem * docptr)
 {
 	/* Make sure the DoC is in normal mode */
 	if ((ReadDOC(docptr, Mplus_DOCControl) & DOC_MODE_NORMAL) == 0) {
 		WriteDOC((DOC_MODE_NORMAL | DOC_MODE_MDWREN), docptr, Mplus_DOCControl);
 		WriteDOC(~(DOC_MODE_NORMAL | DOC_MODE_MDWREN), docptr, Mplus_CtrlConfirm);
 	}
 }
 /* DoC_Command: Send a flash command to the flash chip through the Flash
  * command register. Need 2 Write Pipeline Terminates to complete send.
  */
 static void DoC_Command(void __iomem * docptr, unsigned char command,
 			       unsigned char xtraflags)
 {
 	WriteDOC(command, docptr, Mplus_FlashCmd);
 	WriteDOC(command, docptr, Mplus_WritePipeTerm);
 	WriteDOC(command, docptr, Mplus_WritePipeTerm);
 }
 /* DoC_Address: Set the current address for the flash chip through the Flash
  * Address register. Need 2 Write Pipeline Terminates to complete send.
  */
 static inline void DoC_Address(struct DiskOnChip *doc, int numbytes,
 			       unsigned long ofs, unsigned char xtraflags1,
 			       unsigned char xtraflags2)
 {
 	void __iomem * docptr = doc->virtadr;
 	/* Allow for possible Mill Plus internal flash interleaving */
 	ofs >>= doc->interleave;
 	switch (numbytes) {
 	case 1:
 		/* Send single byte, bits 0-7. */
 		WriteDOC(ofs & 0xff, docptr, Mplus_FlashAddress);
 		break;
 	case 2:
 		/* Send bits 9-16 followed by 17-23 */
 		WriteDOC((ofs >> 9)  & 0xff, docptr, Mplus_FlashAddress);
 		WriteDOC((ofs >> 17) & 0xff, docptr, Mplus_FlashAddress);
 		break;
 	case 3:
 		/* Send 0-7, 9-16, then 17-23 */
 		WriteDOC(ofs & 0xff, docptr, Mplus_FlashAddress);
 		WriteDOC((ofs >> 9)  & 0xff, docptr, Mplus_FlashAddress);
 		WriteDOC((ofs >> 17) & 0xff, docptr, Mplus_FlashAddress);
 		break;
 	default:
 		return;
 	}
 	WriteDOC(0x00, docptr, Mplus_WritePipeTerm);
 	WriteDOC(0x00, docptr, Mplus_WritePipeTerm);
 }
 /* DoC_SelectChip: Select a given flash chip within the current floor */
 static int DoC_SelectChip(void __iomem * docptr, int chip)
 {
 	/* No choice for flash chip on Millennium Plus */
 	return 0;
 }
 /* DoC_SelectFloor: Select a given floor (bank of flash chips) */
 static int DoC_SelectFloor(void __iomem * docptr, int floor)
 {
 	WriteDOC((floor & 0x3), docptr, Mplus_DeviceSelect);
 	return 0;
 }
 /*
  * Translate the given offset into the appropriate command and offset.
  * This does the mapping using the 16bit interleave layout defined by
  * M-Systems, and looks like this for a sector pair:
  *  +-----------+-------+-------+-------+--------------+---------+-----------+
  *  | 0 --- 511 |512-517|518-519|520-521| 522 --- 1033 |1034-1039|1040 - 1055|
  *  +-----------+-------+-------+-------+--------------+---------+-----------+
  *  | Data 0    | ECC 0 |Flags0 |Flags1 | Data 1       |ECC 1    | OOB 1 + 2 |
  *  +-----------+-------+-------+-------+--------------+---------+-----------+
  */
 /* FIXME: This lives in INFTL not here. Other users of flash devices
    may not want it */
 static unsigned int DoC_GetDataOffset(struct mtd_info *mtd, loff_t *from)
 {
 	struct DiskOnChip *this = mtd->priv;
 	if (this->interleave) {
 		unsigned int ofs = *from & 0x3ff;
 		unsigned int cmd;
 		if (ofs < 512) {
 			cmd = NAND_CMD_READ0;
 			ofs &= 0x1ff;
 		} else if (ofs < 1014) {
 			cmd = NAND_CMD_READ1;
 			ofs = (ofs & 0x1ff) + 10;
 		} else {
 			cmd = NAND_CMD_READOOB;
 			ofs = ofs - 1014;
 		}
 		*from = (*from & ~0x3ff) | ofs;
 		return cmd;
 	} else {
 		/* No interleave */
 		if ((*from) & 0x100)
 			return NAND_CMD_READ1;
 		return NAND_CMD_READ0;
 	}
 }
 static unsigned int DoC_GetECCOffset(struct mtd_info *mtd, loff_t *from)
 {
 	unsigned int ofs, cmd;
 	if (*from & 0x200) {
 		cmd = NAND_CMD_READOOB;
 		ofs = 10 + (*from & 0xf);
 	} else {
 		cmd = NAND_CMD_READ1;
 		ofs = (*from & 0xf);
 	}
 	*from = (*from & ~0x3ff) | ofs;
 	return cmd;
 }
 static unsigned int DoC_GetFlagsOffset(struct mtd_info *mtd, loff_t *from)
 {
 	unsigned int ofs, cmd;
 	cmd = NAND_CMD_READ1;
 	ofs = (*from & 0x200) ? 8 : 6;
 	*from = (*from & ~0x3ff) | ofs;
 	return cmd;
 }
 static unsigned int DoC_GetHdrOffset(struct mtd_info *mtd, loff_t *from)
 {
 	unsigned int ofs, cmd;
 	cmd = NAND_CMD_READOOB;
 	ofs = (*from & 0x200) ? 24 : 16;
 	*from = (*from & ~0x3ff) | ofs;
 	return cmd;
 }
 static inline void MemReadDOC(void __iomem * docptr, unsigned char *buf, int len)
 {
 #ifndef USE_MEMCPY
 	int i;
 	for (i = 0; i < len; i++)
 		buf[i] = ReadDOC(docptr, Mil_CDSN_IO + i);
 #else
 	memcpy_fromio(buf, docptr + DoC_Mil_CDSN_IO, len);
 #endif
 }
 static inline void MemWriteDOC(void __iomem * docptr, unsigned char *buf, int len)
 {
 #ifndef USE_MEMCPY
 	int i;
 	for (i = 0; i < len; i++)
 		WriteDOC(buf[i], docptr, Mil_CDSN_IO + i);
 #else
 	memcpy_toio(docptr + DoC_Mil_CDSN_IO, buf, len);
 #endif
 }
 /* DoC_IdentChip: Identify a given NAND chip given {floor,chip} */
 static int DoC_IdentChip(struct DiskOnChip *doc, int floor, int chip)
 {
 	int mfr, id, i, j;
 	volatile char dummy;
 	void __iomem * docptr = doc->virtadr;
 	/* Page in the required floor/chip */
 	DoC_SelectFloor(docptr, floor);
 	DoC_SelectChip(docptr, chip);
 	/* Millennium Plus bus cycle sequence as per figure 2, section 2.4 */
 	WriteDOC((DOC_FLASH_CE | DOC_FLASH_WP), docptr, Mplus_FlashSelect);
 	/* Reset the chip, see Software Requirement 11.4 item 1. */
 	DoC_Command(docptr, NAND_CMD_RESET, 0);
 	DoC_WaitReady(docptr);
 	/* Read the NAND chip ID: 1. Send ReadID command */
 	DoC_Command(docptr, NAND_CMD_READID, 0);
 	/* Read the NAND chip ID: 2. Send address byte zero */
 	DoC_Address(doc, 1, 0x00, 0, 0x00);
 	WriteDOC(0, docptr, Mplus_FlashControl);
 	DoC_WaitReady(docptr);
 	/* Read the manufacturer and device id codes of the flash device through
 	   CDSN IO register see Software Requirement 11.4 item 5.*/
 	dummy = ReadDOC(docptr, Mplus_ReadPipeInit);
 	dummy = ReadDOC(docptr, Mplus_ReadPipeInit);
 	mfr = ReadDOC(docptr, Mil_CDSN_IO);
 	if (doc->interleave)
 		dummy = ReadDOC(docptr, Mil_CDSN_IO); /* 2 way interleave */
 	id  = ReadDOC(docptr, Mil_CDSN_IO);
 	if (doc->interleave)
 		dummy = ReadDOC(docptr, Mil_CDSN_IO); /* 2 way interleave */
 	dummy = ReadDOC(docptr, Mplus_LastDataRead);
 	dummy = ReadDOC(docptr, Mplus_LastDataRead);
 	/* Disable flash internally */
 	WriteDOC(0, docptr, Mplus_FlashSelect);
 	/* No response - return failure */
 	if (mfr == 0xff || mfr == 0)
 		return 0;
 	for (i = 0; nand_flash_ids[i].name != NULL; i++) {
 		if (id == nand_flash_ids[i].id) {
 			/* Try to identify manufacturer */
 			for (j = 0; nand_manuf_ids[j].id != 0x0; j++) {
 				if (nand_manuf_ids[j].id == mfr)
 					break;
 			}
 			printk(KERN_INFO "Flash chip found: Manufacturer ID: %2.2X, "
 			       "Chip ID: %2.2X (%s:%s)\n", mfr, id,
 			       nand_manuf_ids[j].name, nand_flash_ids[i].name);
 			doc->mfr = mfr;
 			doc->id = id;
 			doc->chipshift = ffs((nand_flash_ids[i].chipsize << 20)) - 1;
 			doc->erasesize = nand_flash_ids[i].erasesize << doc->interleave;
 			break;
 		}
 	}
 	if (nand_flash_ids[i].name == NULL)
 		return 0;
 	return 1;
 }
 /* DoC_ScanChips: Find all NAND chips present in a DiskOnChip, and identify them */
 static void DoC_ScanChips(struct DiskOnChip *this)
 {
 	int floor, chip;
 	int numchips[MAX_FLOORS_MPLUS];
 	int ret;
 	this->numchips = 0;
 	this->mfr = 0;
 	this->id = 0;
 	/* Work out the intended interleave setting */
 	this->interleave = 0;
 	if (this->ChipID == DOC_ChipID_DocMilPlus32)
 		this->interleave = 1;
 	/* Check the ASIC agrees */
 	if ( (this->interleave << 2) !=
 	     (ReadDOC(this->virtadr, Mplus_Configuration) & 4)) {
 		u_char conf = ReadDOC(this->virtadr, Mplus_Configuration);
 		printk(KERN_NOTICE "Setting DiskOnChip Millennium Plus interleave to %s\n",
 		       this->interleave?"on (16-bit)":"off (8-bit)");
 		conf ^= 4;
 		WriteDOC(conf, this->virtadr, Mplus_Configuration);
 	}
 	/* For each floor, find the number of valid chips it contains */
 	for (floor = 0,ret = 1; floor < MAX_FLOORS_MPLUS; floor++) {
 		numchips[floor] = 0;
 		for (chip = 0; chip < MAX_CHIPS_MPLUS && ret != 0; chip++) {
 			ret = DoC_IdentChip(this, floor, chip);
 			if (ret) {
 				numchips[floor]++;
 				this->numchips++;
 			}
 		}
 	}
 	/* If there are none at all that we recognise, bail */
 	if (!this->numchips) {
 		printk("No flash chips recognised.\n");
 		return;
 	}
 	/* Allocate an array to hold the information for each chip */
 	this->chips = kmalloc(sizeof(struct Nand) * this->numchips, GFP_KERNEL);
 	if (!this->chips){
 		printk("MTD: No memory for allocating chip info structures\n");
 		return;
 	}
 	/* Fill out the chip array with {floor, chipno} for each
 	 * detected chip in the device. */
 	for (floor = 0, ret = 0; floor < MAX_FLOORS_MPLUS; floor++) {
 		for (chip = 0 ; chip < numchips[floor] ; chip++) {
 			this->chips[ret].floor = floor;
 			this->chips[ret].chip = chip;
 			this->chips[ret].curadr = 0;
 			this->chips[ret].curmode = 0x50;
 			ret++;
 		}
 	}
 	/* Calculate and print the total size of the device */
 	this->totlen = this->numchips * (1 << this->chipshift);
 	printk(KERN_INFO "%d flash chips found. Total DiskOnChip size: %ld MiB\n",
 	       this->numchips ,this->totlen >> 20);
 }
 static int DoCMilPlus_is_alias(struct DiskOnChip *doc1, struct DiskOnChip *doc2)
 {
 	int tmp1, tmp2, retval;
 	if (doc1->physadr == doc2->physadr)
 		return 1;
 	/* Use the alias resolution register which was set aside for this
 	 * purpose. If it's value is the same on both chips, they might
 	 * be the same chip, and we write to one and check for a change in
 	 * the other. It's unclear if this register is usuable in the
 	 * DoC 2000 (it's in the Millennium docs), but it seems to work. */
 	tmp1 = ReadDOC(doc1->virtadr, Mplus_AliasResolution);
 	tmp2 = ReadDOC(doc2->virtadr, Mplus_AliasResolution);
 	if (tmp1 != tmp2)
 		return 0;
 	WriteDOC((tmp1+1) % 0xff, doc1->virtadr, Mplus_AliasResolution);
 	tmp2 = ReadDOC(doc2->virtadr, Mplus_AliasResolution);
 	if (tmp2 == (tmp1+1) % 0xff)
 		retval = 1;
 	else
 		retval = 0;
 	/* Restore register contents.  May not be necessary, but do it just to
 	 * be safe. */
 	WriteDOC(tmp1, doc1->virtadr, Mplus_AliasResolution);
 	return retval;
 }
 /* This routine is found from the docprobe code by symbol_get(),
  * which will bump the use count of this module. */
 void DoCMilPlus_init(struct mtd_info *mtd)
 {
 	struct DiskOnChip *this = mtd->priv;
 	struct DiskOnChip *old = NULL;
 	/* We must avoid being called twice for the same device. */
 	if (docmilpluslist)
 		old = docmilpluslist->priv;
 	while (old) {
 		if (DoCMilPlus_is_alias(this, old)) {
 			printk(KERN_NOTICE "Ignoring DiskOnChip Millennium "
 				"Plus at 0x%lX - already configured\n",
 				this->physadr);
 			iounmap(this->virtadr);
 			kfree(mtd);
 			return;
 		}
 		if (old->nextdoc)
 			old = old->nextdoc->priv;
 		else
 			old = NULL;
 	}
 	mtd->name = "DiskOnChip Millennium Plus";
 	printk(KERN_NOTICE "DiskOnChip Millennium Plus found at "
 		"address 0x%lX\n", this->physadr);
 	mtd->type = MTD_NANDFLASH;
 	mtd->flags = MTD_CAP_NANDFLASH;
 	mtd->writebufsize = mtd->writesize = 512;
 	mtd->oobsize = 16;
 	mtd->ecc_strength = 2;
 	mtd->owner = THIS_MODULE;
 	mtd->_erase = doc_erase;
 	mtd->_read = doc_read;
 	mtd->_write = doc_write;
 	mtd->_read_oob = doc_read_oob;
 	mtd->_write_oob = doc_write_oob;
 	this->curfloor = -1;
 	this->curchip = -1;
 	/* Ident all the chips present. */
 	DoC_ScanChips(this);
 	if (!this->totlen) {
 		kfree(mtd);
 		iounmap(this->virtadr);
 	} else {
 		this->nextdoc = docmilpluslist;
 		docmilpluslist = mtd;
 		mtd->size  = this->totlen;
 		mtd->erasesize = this->erasesize;
 		mtd_device_register(mtd, NULL, 0);
 		return;
 	}
 }
 EXPORT_SYMBOL_GPL(DoCMilPlus_init);
 #if 0
 static int doc_dumpblk(struct mtd_info *mtd, loff_t from)
 {
 	int i;
 	loff_t fofs;
 	struct DiskOnChip *this = mtd->priv;
 	void __iomem * docptr = this->virtadr;
 	struct Nand *mychip = &this->chips[from >> (this->chipshift)];
 	unsigned char *bp, buf[1056];
 	char c[32];
 	from &= ~0x3ff;
 	/* Don't allow read past end of device */
 	if (from >= this->totlen)
 		return -EINVAL;
 	DoC_CheckASIC(docptr);
 	/* Find the chip which is to be used and select it */
 	if (this->curfloor != mychip->floor) {
 		DoC_SelectFloor(docptr, mychip->floor);
 		DoC_SelectChip(docptr, mychip->chip);
 	} else if (this->curchip != mychip->chip) {
 		DoC_SelectChip(docptr, mychip->chip);
 	}
 	this->curfloor = mychip->floor;
 	this->curchip = mychip->chip;
 	/* Millennium Plus bus cycle sequence as per figure 2, section 2.4 */
 	WriteDOC((DOC_FLASH_CE | DOC_FLASH_WP), docptr, Mplus_FlashSelect);
 	/* Reset the chip, see Software Requirement 11.4 item 1. */
 	DoC_Command(docptr, NAND_CMD_RESET, 0);
 	DoC_WaitReady(docptr);
 	fofs = from;
 	DoC_Command(docptr, DoC_GetDataOffset(mtd, &fofs), 0);
 	DoC_Address(this, 3, fofs, 0, 0x00);
 	WriteDOC(0, docptr, Mplus_FlashControl);
 	DoC_WaitReady(docptr);
 	/* disable the ECC engine */
 	WriteDOC(DOC_ECC_RESET, docptr, Mplus_ECCConf);
 	ReadDOC(docptr, Mplus_ReadPipeInit);
 	ReadDOC(docptr, Mplus_ReadPipeInit);
 	/* Read the data via the internal pipeline through CDSN IO
 	   register, see Pipelined Read Operations 11.3 */
 	MemReadDOC(docptr, buf, 1054);
 	buf[1054] = ReadDOC(docptr, Mplus_LastDataRead);
 	buf[1055] = ReadDOC(docptr, Mplus_LastDataRead);
 	memset(&c[0], 0, sizeof(c));
 	printk("DUMP OFFSET=%x:\n", (int)from);
         for (i = 0, bp = &buf[0]; (i < 1056); i++) {
                 if ((i % 16) == 0)
                         printk("%08x: ", i);
                 printk(" %02x", *bp);
                 c[(i & 0xf)] = ((*bp >= 0x20) && (*bp <= 0x7f)) ? *bp : '.';
                 bp++;
                 if (((i + 1) % 16) == 0)
                         printk("    %s\n", c);
         }
 	printk("\n");
 	/* Disable flash internally */
 	WriteDOC(0, docptr, Mplus_FlashSelect);
 	return 0;
 }
 #endif
 static int doc_read(struct mtd_info *mtd, loff_t from, size_t len,
 		    size_t *retlen, u_char *buf)
 {
 	int ret, i;
 	volatile char dummy;
 	loff_t fofs;
 	unsigned char syndrome[6], eccbuf[6];
 	struct DiskOnChip *this = mtd->priv;
 	void __iomem * docptr = this->virtadr;
 	struct Nand *mychip = &this->chips[from >> (this->chipshift)];
 	/* Don't allow a single read to cross a 512-byte block boundary */
 	if (from + len > ((from | 0x1ff) + 1))
 		len = ((from | 0x1ff) + 1) - from;
 	DoC_CheckASIC(docptr);
 	/* Find the chip which is to be used and select it */
 	if (this->curfloor != mychip->floor) {
 		DoC_SelectFloor(docptr, mychip->floor);
 		DoC_SelectChip(docptr, mychip->chip);
 	} else if (this->curchip != mychip->chip) {
 		DoC_SelectChip(docptr, mychip->chip);
 	}
 	this->curfloor = mychip->floor;
 	this->curchip = mychip->chip;
 	/* Millennium Plus bus cycle sequence as per figure 2, section 2.4 */
 	WriteDOC((DOC_FLASH_CE | DOC_FLASH_WP), docptr, Mplus_FlashSelect);
 	/* Reset the chip, see Software Requirement 11.4 item 1. */
 	DoC_Command(docptr, NAND_CMD_RESET, 0);
 	DoC_WaitReady(docptr);
 	fofs = from;
 	DoC_Command(docptr, DoC_GetDataOffset(mtd, &fofs), 0);
 	DoC_Address(this, 3, fofs, 0, 0x00);
 	WriteDOC(0, docptr, Mplus_FlashControl);
 	DoC_WaitReady(docptr);
 	/* init the ECC engine, see Reed-Solomon EDC/ECC 11.1 .*/
 	WriteDOC(DOC_ECC_RESET, docptr, Mplus_ECCConf);
 	WriteDOC(DOC_ECC_EN, docptr, Mplus_ECCConf);
 	/* Let the caller know we completed it */
 	*retlen = len;
 	ret = 0;
 	ReadDOC(docptr, Mplus_ReadPipeInit);
 	ReadDOC(docptr, Mplus_ReadPipeInit);
 	/* Read the data via the internal pipeline through CDSN IO
 	   register, see Pipelined Read Operations 11.3 */
 	MemReadDOC(docptr, buf, len);
 	/* Read the ECC data following raw data */
 	MemReadDOC(docptr, eccbuf, 4);
 	eccbuf[4] = ReadDOC(docptr, Mplus_LastDataRead);
 	eccbuf[5] = ReadDOC(docptr, Mplus_LastDataRead);
 	/* Flush the pipeline */
 	dummy = ReadDOC(docptr, Mplus_ECCConf);
 	dummy = ReadDOC(docptr, Mplus_ECCConf);
 	/* Check the ECC Status */
 	if (ReadDOC(docptr, Mplus_ECCConf) & 0x80) {
 		int nb_errors;
 		/* There was an ECC error */
 #ifdef ECC_DEBUG
 		printk("DiskOnChip ECC Error: Read at %lx\n", (long)from);
 #endif
 		/* Read the ECC syndrome through the DiskOnChip ECC logic.
 		   These syndrome will be all ZERO when there is no error */
 		for (i = 0; i < 6; i++)
 			syndrome[i] = ReadDOC(docptr, Mplus_ECCSyndrome0 + i);
 		nb_errors = doc_decode_ecc(buf, syndrome);
 #ifdef ECC_DEBUG
 		printk("ECC Errors corrected: %x\n", nb_errors);
 #endif
 		if (nb_errors < 0) {
 			/* We return error, but have actually done the
 			   read. Not that this can be told to user-space, via
 			   sys_read(), but at least MTD-aware stuff can know
 			   about it by checking *retlen */
 #ifdef ECC_DEBUG
 			printk("%s(%d): Millennium Plus ECC error (from=0x%x:\n",
 				__FILE__, __LINE__, (int)from);
-			printk("        syndrome= %02x:%02x:%02x:%02x:%02x:"
+			printk("        syndrome= %*phC\n", 6, syndrome);
-				"%02x\n",
+			printk("        eccbuf= %*phC\n", 6, eccbuf);
-				syndrome[0], syndrome[1], syndrome[2],
-				syndrome[3], syndrome[4], syndrome[5]);
-			printk("          eccbuf= %02x:%02x:%02x:%02x:%02x:"
-				"%02x\n",
-				eccbuf[0], eccbuf[1], eccbuf[2],
-				eccbuf[3], eccbuf[4], eccbuf[5]);
 #endif
 				ret = -EIO;
 		}
 	}
 #ifdef PSYCHO_DEBUG
-	printk("ECC DATA at %lx: %2.2X %2.2X %2.2X %2.2X %2.2X %2.2X\n",
+	printk("ECC DATA at %lx: %*ph\n", (long)from, 6, eccbuf);
-	       (long)from, eccbuf[0], eccbuf[1], eccbuf[2], eccbuf[3],
-	       eccbuf[4], eccbuf[5]);
 #endif
 	/* disable the ECC engine */
 	WriteDOC(DOC_ECC_DIS, docptr , Mplus_ECCConf);
 	/* Disable flash internally */
 	WriteDOC(0, docptr, Mplus_FlashSelect);
 	return ret;
 }
 static int doc_write(struct mtd_info *mtd, loff_t to, size_t len,
 		     size_t *retlen, const u_char *buf)
 {
 	int i, before, ret = 0;
 	loff_t fto;
 	volatile char dummy;
 	char eccbuf[6];
 	struct DiskOnChip *this = mtd->priv;
 	void __iomem * docptr = this->virtadr;
 	struct Nand *mychip = &this->chips[to >> (this->chipshift)];
 	/* Don't allow writes which aren't exactly one block (512 bytes) */
 	if ((to & 0x1ff) || (len != 0x200))
 		return -EINVAL;
 	/* Determine position of OOB flags, before or after data */
 	before = (this->interleave && (to & 0x200));
 	DoC_CheckASIC(docptr);
 	/* Find the chip which is to be used and select it */
 	if (this->curfloor != mychip->floor) {
 		DoC_SelectFloor(docptr, mychip->floor);
 		DoC_SelectChip(docptr, mychip->chip);
 	} else if (this->curchip != mychip->chip) {
 		DoC_SelectChip(docptr, mychip->chip);
 	}
 	this->curfloor = mychip->floor;
 	this->curchip = mychip->chip;
 	/* Millennium Plus bus cycle sequence as per figure 2, section 2.4 */
 	WriteDOC(DOC_FLASH_CE, docptr, Mplus_FlashSelect);
 	/* Reset the chip, see Software Requirement 11.4 item 1. */
 	DoC_Command(docptr, NAND_CMD_RESET, 0);
 	DoC_WaitReady(docptr);
 	/* Set device to appropriate plane of flash */
 	fto = to;
 	WriteDOC(DoC_GetDataOffset(mtd, &fto), docptr, Mplus_FlashCmd);
 	/* On interleaved devices the flags for 2nd half 512 are before data */
 	if (before)
 		fto -= 2;
 	/* issue the Serial Data In command to initial the Page Program process */
 	DoC_Command(docptr, NAND_CMD_SEQIN, 0x00);
 	DoC_Address(this, 3, fto, 0x00, 0x00);
 	/* Disable the ECC engine */
 	WriteDOC(DOC_ECC_RESET, docptr, Mplus_ECCConf);
 	if (before) {
 		/* Write the block status BLOCK_USED (0x5555) */
 		WriteDOC(0x55, docptr, Mil_CDSN_IO);
 		WriteDOC(0x55, docptr, Mil_CDSN_IO);
 	}
 	/* init the ECC engine, see Reed-Solomon EDC/ECC 11.1 .*/
 	WriteDOC(DOC_ECC_EN | DOC_ECC_RW, docptr, Mplus_ECCConf);
 	MemWriteDOC(docptr, (unsigned char *) buf, len);
 	/* Write ECC data to flash, the ECC info is generated by
 	   the DiskOnChip ECC logic see Reed-Solomon EDC/ECC 11.1 */
 	DoC_Delay(docptr, 3);
 	/* Read the ECC data through the DiskOnChip ECC logic */
 	for (i = 0; i < 6; i++)
 		eccbuf[i] = ReadDOC(docptr, Mplus_ECCSyndrome0 + i);
 	/* disable the ECC engine */
 	WriteDOC(DOC_ECC_DIS, docptr, Mplus_ECCConf);
 	/* Write the ECC data to flash */
 	MemWriteDOC(docptr, eccbuf, 6);
 	if (!before) {
 		/* Write the block status BLOCK_USED (0x5555) */
 		WriteDOC(0x55, docptr, Mil_CDSN_IO+6);
 		WriteDOC(0x55, docptr, Mil_CDSN_IO+7);
 	}
 #ifdef PSYCHO_DEBUG
 	printk("OOB data at %lx is %2.2X %2.2X %2.2X %2.2X %2.2X %2.2X\n",
 	       (long) to, eccbuf[0], eccbuf[1], eccbuf[2], eccbuf[3],
 	       eccbuf[4], eccbuf[5]);
 #endif
 	WriteDOC(0x00, docptr, Mplus_WritePipeTerm);
 	WriteDOC(0x00, docptr, Mplus_WritePipeTerm);
 	/* Commit the Page Program command and wait for ready
 	   see Software Requirement 11.4 item 1.*/
 	DoC_Command(docptr, NAND_CMD_PAGEPROG, 0x00);
 	DoC_WaitReady(docptr);
 	/* Read the status of the flash device through CDSN IO register
 	   see Software Requirement 11.4 item 5.*/
 	DoC_Command(docptr, NAND_CMD_STATUS, 0);
 	dummy = ReadDOC(docptr, Mplus_ReadPipeInit);
 	dummy = ReadDOC(docptr, Mplus_ReadPipeInit);
 	DoC_Delay(docptr, 2);
 	if ((dummy = ReadDOC(docptr, Mplus_LastDataRead)) & 1) {
 		printk("MTD: Error 0x%x programming at 0x%x\n", dummy, (int)to);
 		/* Error in programming
 		   FIXME: implement Bad Block Replacement (in nftl.c ??) */
 		ret = -EIO;
 	}
 	dummy = ReadDOC(docptr, Mplus_LastDataRead);
 	/* Disable flash internally */
 	WriteDOC(0, docptr, Mplus_FlashSelect);
 	/* Let the caller know we completed it */
 	*retlen = len;
 	return ret;
 }
 static int doc_read_oob(struct mtd_info *mtd, loff_t ofs,
 			struct mtd_oob_ops *ops)
 {
 	loff_t fofs, base;
 	struct DiskOnChip *this = mtd->priv;
 	void __iomem * docptr = this->virtadr;
 	struct Nand *mychip = &this->chips[ofs >> this->chipshift];
 	size_t i, size, got, want;
 	uint8_t *buf = ops->oobbuf;
 	size_t len = ops->len;
 	BUG_ON(ops->mode != MTD_OPS_PLACE_OOB);
 	ofs += ops->ooboffs;
 	DoC_CheckASIC(docptr);
 	/* Find the chip which is to be used and select it */
 	if (this->curfloor != mychip->floor) {
 		DoC_SelectFloor(docptr, mychip->floor);
 		DoC_SelectChip(docptr, mychip->chip);
 	} else if (this->curchip != mychip->chip) {
 		DoC_SelectChip(docptr, mychip->chip);
 	}
 	this->curfloor = mychip->floor;
 	this->curchip = mychip->chip;
 	/* Millennium Plus bus cycle sequence as per figure 2, section 2.4 */
 	WriteDOC((DOC_FLASH_CE | DOC_FLASH_WP), docptr, Mplus_FlashSelect);
 	/* disable the ECC engine */
 	WriteDOC(DOC_ECC_RESET, docptr, Mplus_ECCConf);
 	DoC_WaitReady(docptr);
 	/* Maximum of 16 bytes in the OOB region, so limit read to that */
 	if (len > 16)
 		len = 16;
 	got = 0;
 	want = len;
 	for (i = 0; ((i < 3) && (want > 0)); i++) {
 		/* Figure out which region we are accessing... */
 		fofs = ofs;
 		base = ofs & 0xf;
 		if (!this->interleave) {
 			DoC_Command(docptr, NAND_CMD_READOOB, 0);
 			size = 16 - base;
 		} else if (base < 6) {
 			DoC_Command(docptr, DoC_GetECCOffset(mtd, &fofs), 0);
 			size = 6 - base;
 		} else if (base < 8) {
 			DoC_Command(docptr, DoC_GetFlagsOffset(mtd, &fofs), 0);
 			size = 8 - base;
 		} else {
 			DoC_Command(docptr, DoC_GetHdrOffset(mtd, &fofs), 0);
 			size = 16 - base;
 		}
 		if (size > want)
 			size = want;
 		/* Issue read command */
 		DoC_Address(this, 3, fofs, 0, 0x00);
 		WriteDOC(0, docptr, Mplus_FlashControl);
 		DoC_WaitReady(docptr);
 		ReadDOC(docptr, Mplus_ReadPipeInit);
 		ReadDOC(docptr, Mplus_ReadPipeInit);
 		MemReadDOC(docptr, &buf[got], size - 2);
 		buf[got + size - 2] = ReadDOC(docptr, Mplus_LastDataRead);
 		buf[got + size - 1] = ReadDOC(docptr, Mplus_LastDataRead);
 		ofs += size;
 		got += size;
 		want -= size;
 	}
 	/* Disable flash internally */
 	WriteDOC(0, docptr, Mplus_FlashSelect);
 	ops->retlen = len;
 	return 0;
 }
 static int doc_write_oob(struct mtd_info *mtd, loff_t ofs,
 			 struct mtd_oob_ops *ops)
 {
 	volatile char dummy;
 	loff_t fofs, base;
 	struct DiskOnChip *this = mtd->priv;
 	void __iomem * docptr = this->virtadr;
 	struct Nand *mychip = &this->chips[ofs >> this->chipshift];
 	size_t i, size, got, want;
 	int ret = 0;
 	uint8_t *buf = ops->oobbuf;
 	size_t len = ops->len;
 	BUG_ON(ops->mode != MTD_OPS_PLACE_OOB);
 	ofs += ops->ooboffs;
 	DoC_CheckASIC(docptr);
 	/* Find the chip which is to be used and select it */
 	if (this->curfloor != mychip->floor) {
 		DoC_SelectFloor(docptr, mychip->floor);
 		DoC_SelectChip(docptr, mychip->chip);
 	} else if (this->curchip != mychip->chip) {
 		DoC_SelectChip(docptr, mychip->chip);
 	}
 	this->curfloor = mychip->floor;
 	this->curchip = mychip->chip;
 	/* Millennium Plus bus cycle sequence as per figure 2, section 2.4 */
 	WriteDOC(DOC_FLASH_CE, docptr, Mplus_FlashSelect);
 	/* Maximum of 16 bytes in the OOB region, so limit write to that */
 	if (len > 16)
 		len = 16;
 	got = 0;
 	want = len;
 	for (i = 0; ((i < 3) && (want > 0)); i++) {
 		/* Reset the chip, see Software Requirement 11.4 item 1. */
 		DoC_Command(docptr, NAND_CMD_RESET, 0);
 		DoC_WaitReady(docptr);
 		/* Figure out which region we are accessing... */
 		fofs = ofs;
 		base = ofs & 0x0f;
 		if (!this->interleave) {
 			WriteDOC(NAND_CMD_READOOB, docptr, Mplus_FlashCmd);
 			size = 16 - base;
 		} else if (base < 6) {
 			WriteDOC(DoC_GetECCOffset(mtd, &fofs), docptr, Mplus_FlashCmd);
 			size = 6 - base;
 		} else if (base < 8) {
 			WriteDOC(DoC_GetFlagsOffset(mtd, &fofs), docptr, Mplus_FlashCmd);
 			size = 8 - base;
 		} else {
 			WriteDOC(DoC_GetHdrOffset(mtd, &fofs), docptr, Mplus_FlashCmd);
 			size = 16 - base;
 		}
 		if (size > want)
 			size = want;
 		/* Issue the Serial Data In command to initial the Page Program process */
 		DoC_Command(docptr, NAND_CMD_SEQIN, 0x00);
 		DoC_Address(this, 3, fofs, 0, 0x00);
 		/* Disable the ECC engine */
 		WriteDOC(DOC_ECC_RESET, docptr, Mplus_ECCConf);
 		/* Write the data via the internal pipeline through CDSN IO
 		   register, see Pipelined Write Operations 11.2 */
 		MemWriteDOC(docptr, (unsigned char *) &buf[got], size);
 		WriteDOC(0x00, docptr, Mplus_WritePipeTerm);
 		WriteDOC(0x00, docptr, Mplus_WritePipeTerm);
 		/* Commit the Page Program command and wait for ready
 	 	   see Software Requirement 11.4 item 1.*/
 		DoC_Command(docptr, NAND_CMD_PAGEPROG, 0x00);
 		DoC_WaitReady(docptr);
 		/* Read the status of the flash device through CDSN IO register
 		   see Software Requirement 11.4 item 5.*/
 		DoC_Command(docptr, NAND_CMD_STATUS, 0x00);
 		dummy = ReadDOC(docptr, Mplus_ReadPipeInit);
 		dummy = ReadDOC(docptr, Mplus_ReadPipeInit);
 		DoC_Delay(docptr, 2);
 		if ((dummy = ReadDOC(docptr, Mplus_LastDataRead)) & 1) {
 			printk("MTD: Error 0x%x programming oob at 0x%x\n",
 				dummy, (int)ofs);
 			/* FIXME: implement Bad Block Replacement */
 			ops->retlen = 0;
 			ret = -EIO;
 		}
 		dummy = ReadDOC(docptr, Mplus_LastDataRead);
 		ofs += size;
 		got += size;
 		want -= size;
 	}
 	/* Disable flash internally */
 	WriteDOC(0, docptr, Mplus_FlashSelect);
 	ops->retlen = len;
 	return ret;
 }
 int doc_erase(struct mtd_info *mtd, struct erase_info *instr)
 {
 	volatile char dummy;
 	struct DiskOnChip *this = mtd->priv;
 	__u32 ofs = instr->addr;
 	__u32 len = instr->len;
 	void __iomem * docptr = this->virtadr;
 	struct Nand *mychip = &this->chips[ofs >> this->chipshift];
 	DoC_CheckASIC(docptr);
 	if (len != mtd->erasesize)
 		printk(KERN_WARNING "MTD: Erase not right size (%x != %x)n",
 		       len, mtd->erasesize);
 	/* Find the chip which is to be used and select it */
 	if (this->curfloor != mychip->floor) {
 		DoC_SelectFloor(docptr, mychip->floor);
 		DoC_SelectChip(docptr, mychip->chip);
 	} else if (this->curchip != mychip->chip) {
 		DoC_SelectChip(docptr, mychip->chip);
 	}
 	this->curfloor = mychip->floor;
 	this->curchip = mychip->chip;
 	instr->state = MTD_ERASE_PENDING;
 	/* Millennium Plus bus cycle sequence as per figure 2, section 2.4 */
 	WriteDOC(DOC_FLASH_CE, docptr, Mplus_FlashSelect);
 	DoC_Command(docptr, NAND_CMD_RESET, 0x00);
 	DoC_WaitReady(docptr);
 	DoC_Command(docptr, NAND_CMD_ERASE1, 0);
 	DoC_Address(this, 2, ofs, 0, 0x00);
 	DoC_Command(docptr, NAND_CMD_ERASE2, 0);
 	DoC_WaitReady(docptr);
 	instr->state = MTD_ERASING;
 	/* Read the status of the flash device through CDSN IO register
 	   see Software Requirement 11.4 item 5. */
 	DoC_Command(docptr, NAND_CMD_STATUS, 0);
 	dummy = ReadDOC(docptr, Mplus_ReadPipeInit);
 	dummy = ReadDOC(docptr, Mplus_ReadPipeInit);
 	if ((dummy = ReadDOC(docptr, Mplus_LastDataRead)) & 1) {
 		printk("MTD: Error 0x%x erasing at 0x%x\n", dummy, ofs);
 		/* FIXME: implement Bad Block Replacement (in nftl.c ??) */
 		instr->state = MTD_ERASE_FAILED;
 	} else {
 		instr->state = MTD_ERASE_DONE;
 	}
 	dummy = ReadDOC(docptr, Mplus_LastDataRead);
 	/* Disable flash internally */
 	WriteDOC(0, docptr, Mplus_FlashSelect);
 	mtd_erase_callback(instr);
 	return 0;
 }
 /****************************************************************************
  *
  * Module stuff
  *
  ****************************************************************************/
 static void __exit cleanup_doc2001plus(void)
 {
 	struct mtd_info *mtd;
 	struct DiskOnChip *this;
 	while ((mtd=docmilpluslist)) {
 		this = mtd->priv;
 		docmilpluslist = this->nextdoc;
 		mtd_device_unregister(mtd);
 		iounmap(this->virtadr);
 		kfree(this->chips);
 		kfree(mtd);
 	}
 }
 module_exit(cleanup_doc2001plus);
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Greg Ungerer <gerg@snapgear.com> et al.");
 MODULE_DESCRIPTION("Driver for DiskOnChip Millennium Plus");

drivers/mtd/devices/docg3.c

Diff comments View file @ 13e8597

 /*
  * Handles the M-Systems DiskOnChip G3 chip
  *
  * Copyright (C) 2011 Robert Jarzmik
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  *
  */
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/errno.h>
 #include <linux/platform_device.h>
 #include <linux/string.h>
 #include <linux/slab.h>
 #include <linux/io.h>
 #include <linux/delay.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/bitmap.h>
 #include <linux/bitrev.h>
 #include <linux/bch.h>
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
 #define CREATE_TRACE_POINTS
 #include "docg3.h"
 /*
  * This driver handles the DiskOnChip G3 flash memory.
  *
  * As no specification is available from M-Systems/Sandisk, this drivers lacks
  * several functions available on the chip, as :
  *  - IPL write
  *
  * The bus data width (8bits versus 16bits) is not handled (if_cfg flag), and
  * the driver assumes a 16bits data bus.
  *
  * DocG3 relies on 2 ECC algorithms, which are handled in hardware :
  *  - a 1 byte Hamming code stored in the OOB for each page
  *  - a 7 bytes BCH code stored in the OOB for each page
  * The BCH ECC is :
  *  - BCH is in GF(2^14)
  *  - BCH is over data of 520 bytes (512 page + 7 page_info bytes
  *                                   + 1 hamming byte)
  *  - BCH can correct up to 4 bits (t = 4)
  *  - BCH syndroms are calculated in hardware, and checked in hardware as well
  *
  */
 static unsigned int reliable_mode;
 module_param(reliable_mode, uint, 0);
 MODULE_PARM_DESC(reliable_mode, "Set the docg3 mode (0=normal MLC, 1=fast, "
 		 "2=reliable) : MLC normal operations are in normal mode");
 /**
  * struct docg3_oobinfo - DiskOnChip G3 OOB layout
  * @eccbytes: 8 bytes are used (1 for Hamming ECC, 7 for BCH ECC)
  * @eccpos: ecc positions (byte 7 is Hamming ECC, byte 8-14 are BCH ECC)
  * @oobfree: free pageinfo bytes (byte 0 until byte 6, byte 15
  * @oobavail: 8 available bytes remaining after ECC toll
  */
 static struct nand_ecclayout docg3_oobinfo = {
 	.eccbytes = 8,
 	.eccpos = {7, 8, 9, 10, 11, 12, 13, 14},
 	.oobfree = {{0, 7}, {15, 1} },
 	.oobavail = 8,
 };
 static inline u8 doc_readb(struct docg3 *docg3, u16 reg)
 {
 	u8 val = readb(docg3->cascade->base + reg);
 	trace_docg3_io(0, 8, reg, (int)val);
 	return val;
 }
 static inline u16 doc_readw(struct docg3 *docg3, u16 reg)
 {
 	u16 val = readw(docg3->cascade->base + reg);
 	trace_docg3_io(0, 16, reg, (int)val);
 	return val;
 }
 static inline void doc_writeb(struct docg3 *docg3, u8 val, u16 reg)
 {
 	writeb(val, docg3->cascade->base + reg);
 	trace_docg3_io(1, 8, reg, val);
 }
 static inline void doc_writew(struct docg3 *docg3, u16 val, u16 reg)
 {
 	writew(val, docg3->cascade->base + reg);
 	trace_docg3_io(1, 16, reg, val);
 }
 static inline void doc_flash_command(struct docg3 *docg3, u8 cmd)
 {
 	doc_writeb(docg3, cmd, DOC_FLASHCOMMAND);
 }
 static inline void doc_flash_sequence(struct docg3 *docg3, u8 seq)
 {
 	doc_writeb(docg3, seq, DOC_FLASHSEQUENCE);
 }
 static inline void doc_flash_address(struct docg3 *docg3, u8 addr)
 {
 	doc_writeb(docg3, addr, DOC_FLASHADDRESS);
 }
 static char const *part_probes[] = { "cmdlinepart", "saftlpart", NULL };
 static int doc_register_readb(struct docg3 *docg3, int reg)
 {
 	u8 val;
 	doc_writew(docg3, reg, DOC_READADDRESS);
 	val = doc_readb(docg3, reg);
 	doc_vdbg("Read register %04x : %02x\n", reg, val);
 	return val;
 }
 static int doc_register_readw(struct docg3 *docg3, int reg)
 {
 	u16 val;
 	doc_writew(docg3, reg, DOC_READADDRESS);
 	val = doc_readw(docg3, reg);
 	doc_vdbg("Read register %04x : %04x\n", reg, val);
 	return val;
 }
 /**
  * doc_delay - delay docg3 operations
  * @docg3: the device
  * @nbNOPs: the number of NOPs to issue
  *
  * As no specification is available, the right timings between chip commands are
  * unknown. The only available piece of information are the observed nops on a
  * working docg3 chip.
  * Therefore, doc_delay relies on a busy loop of NOPs, instead of scheduler
  * friendlier msleep() functions or blocking mdelay().
  */
 static void doc_delay(struct docg3 *docg3, int nbNOPs)
 {
 	int i;
 	doc_vdbg("NOP x %d\n", nbNOPs);
 	for (i = 0; i < nbNOPs; i++)
 		doc_writeb(docg3, 0, DOC_NOP);
 }
 static int is_prot_seq_error(struct docg3 *docg3)
 {
 	int ctrl;
 	ctrl = doc_register_readb(docg3, DOC_FLASHCONTROL);
 	return ctrl & (DOC_CTRL_PROTECTION_ERROR | DOC_CTRL_SEQUENCE_ERROR);
 }
 static int doc_is_ready(struct docg3 *docg3)
 {
 	int ctrl;
 	ctrl = doc_register_readb(docg3, DOC_FLASHCONTROL);
 	return ctrl & DOC_CTRL_FLASHREADY;
 }
 static int doc_wait_ready(struct docg3 *docg3)
 {
 	int maxWaitCycles = 100;
 	do {
 		doc_delay(docg3, 4);
 		cpu_relax();
 	} while (!doc_is_ready(docg3) && maxWaitCycles--);
 	doc_delay(docg3, 2);
 	if (maxWaitCycles > 0)
 		return 0;
 	else
 		return -EIO;
 }
 static int doc_reset_seq(struct docg3 *docg3)
 {
 	int ret;
 	doc_writeb(docg3, 0x10, DOC_FLASHCONTROL);
 	doc_flash_sequence(docg3, DOC_SEQ_RESET);
 	doc_flash_command(docg3, DOC_CMD_RESET);
 	doc_delay(docg3, 2);
 	ret = doc_wait_ready(docg3);
 	doc_dbg("doc_reset_seq() -> isReady=%s\n", ret ? "false" : "true");
 	return ret;
 }
 /**
  * doc_read_data_area - Read data from data area
  * @docg3: the device
  * @buf: the buffer to fill in (might be NULL is dummy reads)
  * @len: the length to read
  * @first: first time read, DOC_READADDRESS should be set
  *
  * Reads bytes from flash data. Handles the single byte / even bytes reads.
  */
 static void doc_read_data_area(struct docg3 *docg3, void *buf, int len,
 			       int first)
 {
 	int i, cdr, len4;
 	u16 data16, *dst16;
 	u8 data8, *dst8;
 	doc_dbg("doc_read_data_area(buf=%p, len=%d)\n", buf, len);
 	cdr = len & 0x1;
 	len4 = len - cdr;
 	if (first)
 		doc_writew(docg3, DOC_IOSPACE_DATA, DOC_READADDRESS);
 	dst16 = buf;
 	for (i = 0; i < len4; i += 2) {
 		data16 = doc_readw(docg3, DOC_IOSPACE_DATA);
 		if (dst16) {
 			*dst16 = data16;
 			dst16++;
 		}
 	}
 	if (cdr) {
 		doc_writew(docg3, DOC_IOSPACE_DATA | DOC_READADDR_ONE_BYTE,
 			   DOC_READADDRESS);
 		doc_delay(docg3, 1);
 		dst8 = (u8 *)dst16;
 		for (i = 0; i < cdr; i++) {
 			data8 = doc_readb(docg3, DOC_IOSPACE_DATA);
 			if (dst8) {
 				*dst8 = data8;
 				dst8++;
 			}
 		}
 	}
 }
 /**
  * doc_write_data_area - Write data into data area
  * @docg3: the device
  * @buf: the buffer to get input bytes from
  * @len: the length to write
  *
  * Writes bytes into flash data. Handles the single byte / even bytes writes.
  */
 static void doc_write_data_area(struct docg3 *docg3, const void *buf, int len)
 {
 	int i, cdr, len4;
 	u16 *src16;
 	u8 *src8;
 	doc_dbg("doc_write_data_area(buf=%p, len=%d)\n", buf, len);
 	cdr = len & 0x3;
 	len4 = len - cdr;
 	doc_writew(docg3, DOC_IOSPACE_DATA, DOC_READADDRESS);
 	src16 = (u16 *)buf;
 	for (i = 0; i < len4; i += 2) {
 		doc_writew(docg3, *src16, DOC_IOSPACE_DATA);
 		src16++;
 	}
 	src8 = (u8 *)src16;
 	for (i = 0; i < cdr; i++) {
 		doc_writew(docg3, DOC_IOSPACE_DATA | DOC_READADDR_ONE_BYTE,
 			   DOC_READADDRESS);
 		doc_writeb(docg3, *src8, DOC_IOSPACE_DATA);
 		src8++;
 	}
 }
 /**
  * doc_set_data_mode - Sets the flash to normal or reliable data mode
  * @docg3: the device
  *
  * The reliable data mode is a bit slower than the fast mode, but less errors
  * occur.  Entering the reliable mode cannot be done without entering the fast
  * mode first.
  *
  * In reliable mode, pages 2*n and 2*n+1 are clones. Writing to page 0 of blocks
  * (4,5) make the hardware write also to page 1 of blocks blocks(4,5). Reading
  * from page 0 of blocks (4,5) or from page 1 of blocks (4,5) gives the same
  * result, which is a logical and between bytes from page 0 and page 1 (which is
  * consistent with the fact that writing to a page is _clearing_ bits of that
  * page).
  */
 static void doc_set_reliable_mode(struct docg3 *docg3)
 {
 	static char *strmode[] = { "normal", "fast", "reliable", "invalid" };
 	doc_dbg("doc_set_reliable_mode(%s)\n", strmode[docg3->reliable]);
 	switch (docg3->reliable) {
 	case 0:
 		break;
 	case 1:
 		doc_flash_sequence(docg3, DOC_SEQ_SET_FASTMODE);
 		doc_flash_command(docg3, DOC_CMD_FAST_MODE);
 		break;
 	case 2:
 		doc_flash_sequence(docg3, DOC_SEQ_SET_RELIABLEMODE);
 		doc_flash_command(docg3, DOC_CMD_FAST_MODE);
 		doc_flash_command(docg3, DOC_CMD_RELIABLE_MODE);
 		break;
 	default:
 		doc_err("doc_set_reliable_mode(): invalid mode\n");
 		break;
 	}
 	doc_delay(docg3, 2);
 }
 /**
  * doc_set_asic_mode - Set the ASIC mode
  * @docg3: the device
  * @mode: the mode
  *
  * The ASIC can work in 3 modes :
  *  - RESET: all registers are zeroed
  *  - NORMAL: receives and handles commands
  *  - POWERDOWN: minimal poweruse, flash parts shut off
  */
 static void doc_set_asic_mode(struct docg3 *docg3, u8 mode)
 {
 	int i;
 	for (i = 0; i < 12; i++)
 		doc_readb(docg3, DOC_IOSPACE_IPL);
 	mode |= DOC_ASICMODE_MDWREN;
 	doc_dbg("doc_set_asic_mode(%02x)\n", mode);
 	doc_writeb(docg3, mode, DOC_ASICMODE);
 	doc_writeb(docg3, ~mode, DOC_ASICMODECONFIRM);
 	doc_delay(docg3, 1);
 }
 /**
  * doc_set_device_id - Sets the devices id for cascaded G3 chips
  * @docg3: the device
  * @id: the chip to select (amongst 0, 1, 2, 3)
  *
  * There can be 4 cascaded G3 chips. This function selects the one which will
  * should be the active one.
  */
 static void doc_set_device_id(struct docg3 *docg3, int id)
 {
 	u8 ctrl;
 	doc_dbg("doc_set_device_id(%d)\n", id);
 	doc_writeb(docg3, id, DOC_DEVICESELECT);
 	ctrl = doc_register_readb(docg3, DOC_FLASHCONTROL);
 	ctrl &= ~DOC_CTRL_VIOLATION;
 	ctrl |= DOC_CTRL_CE;
 	doc_writeb(docg3, ctrl, DOC_FLASHCONTROL);
 }
 /**
  * doc_set_extra_page_mode - Change flash page layout
  * @docg3: the device
  *
  * Normally, the flash page is split into the data (512 bytes) and the out of
  * band data (16 bytes). For each, 4 more bytes can be accessed, where the wear
  * leveling counters are stored.  To access this last area of 4 bytes, a special
  * mode must be input to the flash ASIC.
  *
  * Returns 0 if no error occurred, -EIO else.
  */
 static int doc_set_extra_page_mode(struct docg3 *docg3)
 {
 	int fctrl;
 	doc_dbg("doc_set_extra_page_mode()\n");
 	doc_flash_sequence(docg3, DOC_SEQ_PAGE_SIZE_532);
 	doc_flash_command(docg3, DOC_CMD_PAGE_SIZE_532);
 	doc_delay(docg3, 2);
 	fctrl = doc_register_readb(docg3, DOC_FLASHCONTROL);
 	if (fctrl & (DOC_CTRL_PROTECTION_ERROR | DOC_CTRL_SEQUENCE_ERROR))
 		return -EIO;
 	else
 		return 0;
 }
 /**
  * doc_setup_addr_sector - Setup blocks/page/ofs address for one plane
  * @docg3: the device
  * @sector: the sector
  */
 static void doc_setup_addr_sector(struct docg3 *docg3, int sector)
 {
 	doc_delay(docg3, 1);
 	doc_flash_address(docg3, sector & 0xff);
 	doc_flash_address(docg3, (sector >> 8) & 0xff);
 	doc_flash_address(docg3, (sector >> 16) & 0xff);
 	doc_delay(docg3, 1);
 }
 /**
  * doc_setup_writeaddr_sector - Setup blocks/page/ofs address for one plane
  * @docg3: the device
  * @sector: the sector
  * @ofs: the offset in the page, between 0 and (512 + 16 + 512)
  */
 static void doc_setup_writeaddr_sector(struct docg3 *docg3, int sector, int ofs)
 {
 	ofs = ofs >> 2;
 	doc_delay(docg3, 1);
 	doc_flash_address(docg3, ofs & 0xff);
 	doc_flash_address(docg3, sector & 0xff);
 	doc_flash_address(docg3, (sector >> 8) & 0xff);
 	doc_flash_address(docg3, (sector >> 16) & 0xff);
 	doc_delay(docg3, 1);
 }
 /**
  * doc_seek - Set both flash planes to the specified block, page for reading
  * @docg3: the device
  * @block0: the first plane block index
  * @block1: the second plane block index
  * @page: the page index within the block
  * @wear: if true, read will occur on the 4 extra bytes of the wear area
  * @ofs: offset in page to read
  *
  * Programs the flash even and odd planes to the specific block and page.
  * Alternatively, programs the flash to the wear area of the specified page.
  */
 static int doc_read_seek(struct docg3 *docg3, int block0, int block1, int page,
 			 int wear, int ofs)
 {
 	int sector, ret = 0;
 	doc_dbg("doc_seek(blocks=(%d,%d), page=%d, ofs=%d, wear=%d)\n",
 		block0, block1, page, ofs, wear);
 	if (!wear && (ofs < 2 * DOC_LAYOUT_PAGE_SIZE)) {
 		doc_flash_sequence(docg3, DOC_SEQ_SET_PLANE1);
 		doc_flash_command(docg3, DOC_CMD_READ_PLANE1);
 		doc_delay(docg3, 2);
 	} else {
 		doc_flash_sequence(docg3, DOC_SEQ_SET_PLANE2);
 		doc_flash_command(docg3, DOC_CMD_READ_PLANE2);
 		doc_delay(docg3, 2);
 	}
 	doc_set_reliable_mode(docg3);
 	if (wear)
 		ret = doc_set_extra_page_mode(docg3);
 	if (ret)
 		goto out;
 	doc_flash_sequence(docg3, DOC_SEQ_READ);
 	sector = (block0 << DOC_ADDR_BLOCK_SHIFT) + (page & DOC_ADDR_PAGE_MASK);
 	doc_flash_command(docg3, DOC_CMD_PROG_BLOCK_ADDR);
 	doc_setup_addr_sector(docg3, sector);
 	sector = (block1 << DOC_ADDR_BLOCK_SHIFT) + (page & DOC_ADDR_PAGE_MASK);
 	doc_flash_command(docg3, DOC_CMD_PROG_BLOCK_ADDR);
 	doc_setup_addr_sector(docg3, sector);
 	doc_delay(docg3, 1);
 out:
 	return ret;
 }
 /**
  * doc_write_seek - Set both flash planes to the specified block, page for writing
  * @docg3: the device
  * @block0: the first plane block index
  * @block1: the second plane block index
  * @page: the page index within the block
  * @ofs: offset in page to write
  *
  * Programs the flash even and odd planes to the specific block and page.
  * Alternatively, programs the flash to the wear area of the specified page.
  */
 static int doc_write_seek(struct docg3 *docg3, int block0, int block1, int page,
 			 int ofs)
 {
 	int ret = 0, sector;
 	doc_dbg("doc_write_seek(blocks=(%d,%d), page=%d, ofs=%d)\n",
 		block0, block1, page, ofs);
 	doc_set_reliable_mode(docg3);
 	if (ofs < 2 * DOC_LAYOUT_PAGE_SIZE) {
 		doc_flash_sequence(docg3, DOC_SEQ_SET_PLANE1);
 		doc_flash_command(docg3, DOC_CMD_READ_PLANE1);
 		doc_delay(docg3, 2);
 	} else {
 		doc_flash_sequence(docg3, DOC_SEQ_SET_PLANE2);
 		doc_flash_command(docg3, DOC_CMD_READ_PLANE2);
 		doc_delay(docg3, 2);
 	}
 	doc_flash_sequence(docg3, DOC_SEQ_PAGE_SETUP);
 	doc_flash_command(docg3, DOC_CMD_PROG_CYCLE1);
 	sector = (block0 << DOC_ADDR_BLOCK_SHIFT) + (page & DOC_ADDR_PAGE_MASK);
 	doc_setup_writeaddr_sector(docg3, sector, ofs);
 	doc_flash_command(docg3, DOC_CMD_PROG_CYCLE3);
 	doc_delay(docg3, 2);
 	ret = doc_wait_ready(docg3);
 	if (ret)
 		goto out;
 	doc_flash_command(docg3, DOC_CMD_PROG_CYCLE1);
 	sector = (block1 << DOC_ADDR_BLOCK_SHIFT) + (page & DOC_ADDR_PAGE_MASK);
 	doc_setup_writeaddr_sector(docg3, sector, ofs);
 	doc_delay(docg3, 1);
 out:
 	return ret;
 }
 /**
  * doc_read_page_ecc_init - Initialize hardware ECC engine
  * @docg3: the device
  * @len: the number of bytes covered by the ECC (BCH covered)
  *
  * The function does initialize the hardware ECC engine to compute the Hamming
  * ECC (on 1 byte) and the BCH hardware ECC (on 7 bytes).
  *
  * Return 0 if succeeded, -EIO on error
  */
 static int doc_read_page_ecc_init(struct docg3 *docg3, int len)
 {
 	doc_writew(docg3, DOC_ECCCONF0_READ_MODE
 		   | DOC_ECCCONF0_BCH_ENABLE | DOC_ECCCONF0_HAMMING_ENABLE
 		   | (len & DOC_ECCCONF0_DATA_BYTES_MASK),
 		   DOC_ECCCONF0);
 	doc_delay(docg3, 4);
 	doc_register_readb(docg3, DOC_FLASHCONTROL);
 	return doc_wait_ready(docg3);
 }
 /**
  * doc_write_page_ecc_init - Initialize hardware BCH ECC engine
  * @docg3: the device
  * @len: the number of bytes covered by the ECC (BCH covered)
  *
  * The function does initialize the hardware ECC engine to compute the Hamming
  * ECC (on 1 byte) and the BCH hardware ECC (on 7 bytes).
  *
  * Return 0 if succeeded, -EIO on error
  */
 static int doc_write_page_ecc_init(struct docg3 *docg3, int len)
 {
 	doc_writew(docg3, DOC_ECCCONF0_WRITE_MODE
 		   | DOC_ECCCONF0_BCH_ENABLE | DOC_ECCCONF0_HAMMING_ENABLE
 		   | (len & DOC_ECCCONF0_DATA_BYTES_MASK),
 		   DOC_ECCCONF0);
 	doc_delay(docg3, 4);
 	doc_register_readb(docg3, DOC_FLASHCONTROL);
 	return doc_wait_ready(docg3);
 }
 /**
  * doc_ecc_disable - Disable Hamming and BCH ECC hardware calculator
  * @docg3: the device
  *
  * Disables the hardware ECC generator and checker, for unchecked reads (as when
  * reading OOB only or write status byte).
  */
 static void doc_ecc_disable(struct docg3 *docg3)
 {
 	doc_writew(docg3, DOC_ECCCONF0_READ_MODE, DOC_ECCCONF0);
 	doc_delay(docg3, 4);
 }
 /**
  * doc_hamming_ecc_init - Initialize hardware Hamming ECC engine
  * @docg3: the device
  * @nb_bytes: the number of bytes covered by the ECC (Hamming covered)
  *
  * This function programs the ECC hardware to compute the hamming code on the
  * last provided N bytes to the hardware generator.
  */
 static void doc_hamming_ecc_init(struct docg3 *docg3, int nb_bytes)
 {
 	u8 ecc_conf1;
 	ecc_conf1 = doc_register_readb(docg3, DOC_ECCCONF1);
 	ecc_conf1 &= ~DOC_ECCCONF1_HAMMING_BITS_MASK;
 	ecc_conf1 |= (nb_bytes & DOC_ECCCONF1_HAMMING_BITS_MASK);
 	doc_writeb(docg3, ecc_conf1, DOC_ECCCONF1);
 }
 /**
  * doc_ecc_bch_fix_data - Fix if need be read data from flash
  * @docg3: the device
  * @buf: the buffer of read data (512 + 7 + 1 bytes)
  * @hwecc: the hardware calculated ECC.
  *         It's in fact recv_ecc ^ calc_ecc, where recv_ecc was read from OOB
  *         area data, and calc_ecc the ECC calculated by the hardware generator.
  *
  * Checks if the received data matches the ECC, and if an error is detected,
  * tries to fix the bit flips (at most 4) in the buffer buf.  As the docg3
  * understands the (data, ecc, syndroms) in an inverted order in comparison to
  * the BCH library, the function reverses the order of bits (ie. bit7 and bit0,
  * bit6 and bit 1, ...) for all ECC data.
  *
  * The hardware ecc unit produces oob_ecc ^ calc_ecc.  The kernel's bch
  * algorithm is used to decode this.  However the hw operates on page
  * data in a bit order that is the reverse of that of the bch alg,
  * requiring that the bits be reversed on the result.  Thanks to Ivan
  * Djelic for his analysis.
  *
  * Returns number of fixed bits (0, 1, 2, 3, 4) or -EBADMSG if too many bit
  * errors were detected and cannot be fixed.
  */
 static int doc_ecc_bch_fix_data(struct docg3 *docg3, void *buf, u8 *hwecc)
 {
 	u8 ecc[DOC_ECC_BCH_SIZE];
 	int errorpos[DOC_ECC_BCH_T], i, numerrs;
 	for (i = 0; i < DOC_ECC_BCH_SIZE; i++)
 		ecc[i] = bitrev8(hwecc[i]);
 	numerrs = decode_bch(docg3->cascade->bch, NULL,
 			     DOC_ECC_BCH_COVERED_BYTES,
 			     NULL, ecc, NULL, errorpos);
 	BUG_ON(numerrs == -EINVAL);
 	if (numerrs < 0)
 		goto out;
 	for (i = 0; i < numerrs; i++)
 		errorpos[i] = (errorpos[i] & ~7) | (7 - (errorpos[i] & 7));
 	for (i = 0; i < numerrs; i++)
 		if (errorpos[i] < DOC_ECC_BCH_COVERED_BYTES*8)
 			/* error is located in data, correct it */
 			change_bit(errorpos[i], buf);
 out:
 	doc_dbg("doc_ecc_bch_fix_data: flipped %d bits\n", numerrs);
 	return numerrs;
 }
 /**
  * doc_read_page_prepare - Prepares reading data from a flash page
  * @docg3: the device
  * @block0: the first plane block index on flash memory
  * @block1: the second plane block index on flash memory
  * @page: the page index in the block
  * @offset: the offset in the page (must be a multiple of 4)
  *
  * Prepares the page to be read in the flash memory :
  *   - tell ASIC to map the flash pages
  *   - tell ASIC to be in read mode
  *
  * After a call to this method, a call to doc_read_page_finish is mandatory,
  * to end the read cycle of the flash.
  *
  * Read data from a flash page. The length to be read must be between 0 and
  * (page_size + oob_size + wear_size), ie. 532, and a multiple of 4 (because
  * the extra bytes reading is not implemented).
  *
  * As pages are grouped by 2 (in 2 planes), reading from a page must be done
  * in two steps:
  *  - one read of 512 bytes at offset 0
  *  - one read of 512 bytes at offset 512 + 16
  *
  * Returns 0 if successful, -EIO if a read error occurred.
  */
 static int doc_read_page_prepare(struct docg3 *docg3, int block0, int block1,
 				 int page, int offset)
 {
 	int wear_area = 0, ret = 0;
 	doc_dbg("doc_read_page_prepare(blocks=(%d,%d), page=%d, ofsInPage=%d)\n",
 		block0, block1, page, offset);
 	if (offset >= DOC_LAYOUT_WEAR_OFFSET)
 		wear_area = 1;
 	if (!wear_area && offset > (DOC_LAYOUT_PAGE_OOB_SIZE * 2))
 		return -EINVAL;
 	doc_set_device_id(docg3, docg3->device_id);
 	ret = doc_reset_seq(docg3);
 	if (ret)
 		goto err;
 	/* Program the flash address block and page */
 	ret = doc_read_seek(docg3, block0, block1, page, wear_area, offset);
 	if (ret)
 		goto err;
 	doc_flash_command(docg3, DOC_CMD_READ_ALL_PLANES);
 	doc_delay(docg3, 2);
 	doc_wait_ready(docg3);
 	doc_flash_command(docg3, DOC_CMD_SET_ADDR_READ);
 	doc_delay(docg3, 1);
 	if (offset >= DOC_LAYOUT_PAGE_SIZE * 2)
 		offset -= 2 * DOC_LAYOUT_PAGE_SIZE;
 	doc_flash_address(docg3, offset >> 2);
 	doc_delay(docg3, 1);
 	doc_wait_ready(docg3);
 	doc_flash_command(docg3, DOC_CMD_READ_FLASH);
 	return 0;
 err:
 	doc_writeb(docg3, 0, DOC_DATAEND);
 	doc_delay(docg3, 2);
 	return -EIO;
 }
 /**
  * doc_read_page_getbytes - Reads bytes from a prepared page
  * @docg3: the device
  * @len: the number of bytes to be read (must be a multiple of 4)
  * @buf: the buffer to be filled in (or NULL is forget bytes)
  * @first: 1 if first time read, DOC_READADDRESS should be set
  * @last_odd: 1 if last read ended up on an odd byte
  *
  * Reads bytes from a prepared page. There is a trickery here : if the last read
  * ended up on an odd offset in the 1024 bytes double page, ie. between the 2
  * planes, the first byte must be read apart. If a word (16bit) read was used,
  * the read would return the byte of plane 2 as low *and* high endian, which
  * will mess the read.
  *
  */
 static int doc_read_page_getbytes(struct docg3 *docg3, int len, u_char *buf,
 				  int first, int last_odd)
 {
 	if (last_odd && len > 0) {
 		doc_read_data_area(docg3, buf, 1, first);
 		doc_read_data_area(docg3, buf ? buf + 1 : buf, len - 1, 0);
 	} else {
 		doc_read_data_area(docg3, buf, len, first);
 	}
 	doc_delay(docg3, 2);
 	return len;
 }
 /**
  * doc_write_page_putbytes - Writes bytes into a prepared page
  * @docg3: the device
  * @len: the number of bytes to be written
  * @buf: the buffer of input bytes
  *
  */
 static void doc_write_page_putbytes(struct docg3 *docg3, int len,
 				    const u_char *buf)
 {
 	doc_write_data_area(docg3, buf, len);
 	doc_delay(docg3, 2);
 }
 /**
  * doc_get_bch_hw_ecc - Get hardware calculated BCH ECC
  * @docg3: the device
  * @hwecc:  the array of 7 integers where the hardware ecc will be stored
  */
 static void doc_get_bch_hw_ecc(struct docg3 *docg3, u8 *hwecc)
 {
 	int i;
 	for (i = 0; i < DOC_ECC_BCH_SIZE; i++)
 		hwecc[i] = doc_register_readb(docg3, DOC_BCH_HW_ECC(i));
 }
 /**
  * doc_page_finish - Ends reading/writing of a flash page
  * @docg3: the device
  */
 static void doc_page_finish(struct docg3 *docg3)
 {
 	doc_writeb(docg3, 0, DOC_DATAEND);
 	doc_delay(docg3, 2);
 }
 /**
  * doc_read_page_finish - Ends reading of a flash page
  * @docg3: the device
  *
  * As a side effect, resets the chip selector to 0. This ensures that after each
  * read operation, the floor 0 is selected. Therefore, if the systems halts, the
  * reboot will boot on floor 0, where the IPL is.
  */
 static void doc_read_page_finish(struct docg3 *docg3)
 {
 	doc_page_finish(docg3);
 	doc_set_device_id(docg3, 0);
 }
 /**
  * calc_block_sector - Calculate blocks, pages and ofs.
  * @from: offset in flash
  * @block0: first plane block index calculated
  * @block1: second plane block index calculated
  * @page: page calculated
  * @ofs: offset in page
  * @reliable: 0 if docg3 in normal mode, 1 if docg3 in fast mode, 2 if docg3 in
  * reliable mode.
  *
  * The calculation is based on the reliable/normal mode. In normal mode, the 64
  * pages of a block are available. In reliable mode, as pages 2*n and 2*n+1 are
  * clones, only 32 pages per block are available.
  */
 static void calc_block_sector(loff_t from, int *block0, int *block1, int *page,
 			      int *ofs, int reliable)
 {
 	uint sector, pages_biblock;
 	pages_biblock = DOC_LAYOUT_PAGES_PER_BLOCK * DOC_LAYOUT_NBPLANES;
 	if (reliable == 1 || reliable == 2)
 		pages_biblock /= 2;
 	sector = from / DOC_LAYOUT_PAGE_SIZE;
 	*block0 = sector / pages_biblock * DOC_LAYOUT_NBPLANES;
 	*block1 = *block0 + 1;
 	*page = sector % pages_biblock;
 	*page /= DOC_LAYOUT_NBPLANES;
 	if (reliable == 1 || reliable == 2)
 		*page *= 2;
 	if (sector % 2)
 		*ofs = DOC_LAYOUT_PAGE_OOB_SIZE;
 	else
 		*ofs = 0;
 }
 /**
  * doc_read_oob - Read out of band bytes from flash
  * @mtd: the device
  * @from: the offset from first block and first page, in bytes, aligned on page
  *        size
  * @ops: the mtd oob structure
  *
  * Reads flash memory OOB area of pages.
  *
  * Returns 0 if read successful, of -EIO, -EINVAL if an error occurred
  */
 static int doc_read_oob(struct mtd_info *mtd, loff_t from,
 			struct mtd_oob_ops *ops)
 {
 	struct docg3 *docg3 = mtd->priv;
 	int block0, block1, page, ret, skip, ofs = 0;
 	u8 *oobbuf = ops->oobbuf;
 	u8 *buf = ops->datbuf;
 	size_t len, ooblen, nbdata, nboob;
 	u8 hwecc[DOC_ECC_BCH_SIZE], eccconf1;
 	int max_bitflips = 0;
 	if (buf)
 		len = ops->len;
 	else
 		len = 0;
 	if (oobbuf)
 		ooblen = ops->ooblen;
 	else
 		ooblen = 0;
 	if (oobbuf && ops->mode == MTD_OPS_PLACE_OOB)
 		oobbuf += ops->ooboffs;
 	doc_dbg("doc_read_oob(from=%lld, mode=%d, data=(%p:%zu), oob=(%p:%zu))\n",
 		from, ops->mode, buf, len, oobbuf, ooblen);
 	if (ooblen % DOC_LAYOUT_OOB_SIZE)
 		return -EINVAL;
 	if (from + len > mtd->size)
 		return -EINVAL;
 	ops->oobretlen = 0;
 	ops->retlen = 0;
 	ret = 0;
 	skip = from % DOC_LAYOUT_PAGE_SIZE;
 	mutex_lock(&docg3->cascade->lock);
 	while (ret >= 0 && (len > 0 || ooblen > 0)) {
 		calc_block_sector(from - skip, &block0, &block1, &page, &ofs,
 			docg3->reliable);
 		nbdata = min_t(size_t, len, DOC_LAYOUT_PAGE_SIZE - skip);
 		nboob = min_t(size_t, ooblen, (size_t)DOC_LAYOUT_OOB_SIZE);
 		ret = doc_read_page_prepare(docg3, block0, block1, page, ofs);
 		if (ret < 0)
 			goto out;
 		ret = doc_read_page_ecc_init(docg3, DOC_ECC_BCH_TOTAL_BYTES);
 		if (ret < 0)
 			goto err_in_read;
 		ret = doc_read_page_getbytes(docg3, skip, NULL, 1, 0);
 		if (ret < skip)
 			goto err_in_read;
 		ret = doc_read_page_getbytes(docg3, nbdata, buf, 0, skip % 2);
 		if (ret < nbdata)
 			goto err_in_read;
 		doc_read_page_getbytes(docg3,
 				       DOC_LAYOUT_PAGE_SIZE - nbdata - skip,
 				       NULL, 0, (skip + nbdata) % 2);
 		ret = doc_read_page_getbytes(docg3, nboob, oobbuf, 0, 0);
 		if (ret < nboob)
 			goto err_in_read;
 		doc_read_page_getbytes(docg3, DOC_LAYOUT_OOB_SIZE - nboob,
 				       NULL, 0, nboob % 2);
 		doc_get_bch_hw_ecc(docg3, hwecc);
 		eccconf1 = doc_register_readb(docg3, DOC_ECCCONF1);
 		if (nboob >= DOC_LAYOUT_OOB_SIZE) {
-			doc_dbg("OOB - INFO: %02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
+			doc_dbg("OOB - INFO: %*phC\n", 7, oobbuf);
-				oobbuf[0], oobbuf[1], oobbuf[2], oobbuf[3],
-				oobbuf[4], oobbuf[5], oobbuf[6]);
 			doc_dbg("OOB - HAMMING: %02x\n", oobbuf[7]);
-			doc_dbg("OOB - BCH_ECC: %02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
+			doc_dbg("OOB - BCH_ECC: %*phC\n", 7, oobbuf + 8);
-				oobbuf[8], oobbuf[9], oobbuf[10], oobbuf[11],
-				oobbuf[12], oobbuf[13], oobbuf[14]);
 			doc_dbg("OOB - UNUSED: %02x\n", oobbuf[15]);
 		}
 		doc_dbg("ECC checks: ECCConf1=%x\n", eccconf1);
-		doc_dbg("ECC HW_ECC: %02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
+		doc_dbg("ECC HW_ECC: %*phC\n", 7, hwecc);
-			hwecc[0], hwecc[1], hwecc[2], hwecc[3], hwecc[4],
-			hwecc[5], hwecc[6]);
 		ret = -EIO;
 		if (is_prot_seq_error(docg3))
 			goto err_in_read;
 		ret = 0;
 		if ((block0 >= DOC_LAYOUT_BLOCK_FIRST_DATA) &&
 		    (eccconf1 & DOC_ECCCONF1_BCH_SYNDROM_ERR) &&
 		    (eccconf1 & DOC_ECCCONF1_PAGE_IS_WRITTEN) &&
 		    (ops->mode != MTD_OPS_RAW) &&
 		    (nbdata == DOC_LAYOUT_PAGE_SIZE)) {
 			ret = doc_ecc_bch_fix_data(docg3, buf, hwecc);
 			if (ret < 0) {
 				mtd->ecc_stats.failed++;
 				ret = -EBADMSG;
 			}
 			if (ret > 0) {
 				mtd->ecc_stats.corrected += ret;
 				max_bitflips = max(max_bitflips, ret);
 				ret = max_bitflips;
 			}
 		}
 		doc_read_page_finish(docg3);
 		ops->retlen += nbdata;
 		ops->oobretlen += nboob;
 		buf += nbdata;
 		oobbuf += nboob;
 		len -= nbdata;
 		ooblen -= nboob;
 		from += DOC_LAYOUT_PAGE_SIZE;
 		skip = 0;
 	}
 out:
 	mutex_unlock(&docg3->cascade->lock);
 	return ret;
 err_in_read:
 	doc_read_page_finish(docg3);
 	goto out;
 }
 /**
  * doc_read - Read bytes from flash
  * @mtd: the device
  * @from: the offset from first block and first page, in bytes, aligned on page
  *        size
  * @len: the number of bytes to read (must be a multiple of 4)
  * @retlen: the number of bytes actually read
  * @buf: the filled in buffer
  *
  * Reads flash memory pages. This function does not read the OOB chunk, but only
  * the page data.
  *
  * Returns 0 if read successful, of -EIO, -EINVAL if an error occurred
  */
 static int doc_read(struct mtd_info *mtd, loff_t from, size_t len,
 	     size_t *retlen, u_char *buf)
 {
 	struct mtd_oob_ops ops;
 	size_t ret;
 	memset(&ops, 0, sizeof(ops));
 	ops.datbuf = buf;
 	ops.len = len;
 	ops.mode = MTD_OPS_AUTO_OOB;
 	ret = doc_read_oob(mtd, from, &ops);
 	*retlen = ops.retlen;
 	return ret;
 }
 static int doc_reload_bbt(struct docg3 *docg3)
 {
 	int block = DOC_LAYOUT_BLOCK_BBT;
 	int ret = 0, nbpages, page;
 	u_char *buf = docg3->bbt;
 	nbpages = DIV_ROUND_UP(docg3->max_block + 1, 8 * DOC_LAYOUT_PAGE_SIZE);
 	for (page = 0; !ret && (page < nbpages); page++) {
 		ret = doc_read_page_prepare(docg3, block, block + 1,
 					    page + DOC_LAYOUT_PAGE_BBT, 0);
 		if (!ret)
 			ret = doc_read_page_ecc_init(docg3,
 						     DOC_LAYOUT_PAGE_SIZE);
 		if (!ret)
 			doc_read_page_getbytes(docg3, DOC_LAYOUT_PAGE_SIZE,
 					       buf, 1, 0);
 		buf += DOC_LAYOUT_PAGE_SIZE;
 	}
 	doc_read_page_finish(docg3);
 	return ret;
 }
 /**
  * doc_block_isbad - Checks whether a block is good or not
  * @mtd: the device
  * @from: the offset to find the correct block
  *
  * Returns 1 if block is bad, 0 if block is good
  */
 static int doc_block_isbad(struct mtd_info *mtd, loff_t from)
 {
 	struct docg3 *docg3 = mtd->priv;
 	int block0, block1, page, ofs, is_good;
 	calc_block_sector(from, &block0, &block1, &page, &ofs,
 		docg3->reliable);
 	doc_dbg("doc_block_isbad(from=%lld) => block=(%d,%d), page=%d, ofs=%d\n",
 		from, block0, block1, page, ofs);
 	if (block0 < DOC_LAYOUT_BLOCK_FIRST_DATA)
 		return 0;
 	if (block1 > docg3->max_block)
 		return -EINVAL;
 	is_good = docg3->bbt[block0 >> 3] & (1 << (block0 & 0x7));
 	return !is_good;
 }
 #if 0
 /**
  * doc_get_erase_count - Get block erase count
  * @docg3: the device
  * @from: the offset in which the block is.
  *
  * Get the number of times a block was erased. The number is the maximum of
  * erase times between first and second plane (which should be equal normally).
  *
  * Returns The number of erases, or -EINVAL or -EIO on error.
  */
 static int doc_get_erase_count(struct docg3 *docg3, loff_t from)
 {
 	u8 buf[DOC_LAYOUT_WEAR_SIZE];
 	int ret, plane1_erase_count, plane2_erase_count;
 	int block0, block1, page, ofs;
 	doc_dbg("doc_get_erase_count(from=%lld, buf=%p)\n", from, buf);
 	if (from % DOC_LAYOUT_PAGE_SIZE)
 		return -EINVAL;
 	calc_block_sector(from, &block0, &block1, &page, &ofs, docg3->reliable);
 	if (block1 > docg3->max_block)
 		return -EINVAL;
 	ret = doc_reset_seq(docg3);
 	if (!ret)
 		ret = doc_read_page_prepare(docg3, block0, block1, page,
 					    ofs + DOC_LAYOUT_WEAR_OFFSET, 0);
 	if (!ret)
 		ret = doc_read_page_getbytes(docg3, DOC_LAYOUT_WEAR_SIZE,
 					     buf, 1, 0);
 	doc_read_page_finish(docg3);
 	if (ret || (buf[0] != DOC_ERASE_MARK) || (buf[2] != DOC_ERASE_MARK))
 		return -EIO;
 	plane1_erase_count = (u8)(~buf[1]) | ((u8)(~buf[4]) << 8)
 		| ((u8)(~buf[5]) << 16);
 	plane2_erase_count = (u8)(~buf[3]) | ((u8)(~buf[6]) << 8)
 		| ((u8)(~buf[7]) << 16);
 	return max(plane1_erase_count, plane2_erase_count);
 }
 #endif
 /**
  * doc_get_op_status - get erase/write operation status
  * @docg3: the device
  *
  * Queries the status from the chip, and returns it
  *
  * Returns the status (bits DOC_PLANES_STATUS_*)
  */
 static int doc_get_op_status(struct docg3 *docg3)
 {
 	u8 status;
 	doc_flash_sequence(docg3, DOC_SEQ_PLANES_STATUS);
 	doc_flash_command(docg3, DOC_CMD_PLANES_STATUS);
 	doc_delay(docg3, 5);
 	doc_ecc_disable(docg3);
 	doc_read_data_area(docg3, &status, 1, 1);
 	return status;
 }
 /**
  * doc_write_erase_wait_status - wait for write or erase completion
  * @docg3: the device
  *
  * Wait for the chip to be ready again after erase or write operation, and check
  * erase/write status.
  *
  * Returns 0 if erase successful, -EIO if erase/write issue, -ETIMEOUT if
  * timeout
  */
 static int doc_write_erase_wait_status(struct docg3 *docg3)
 {
 	int i, status, ret = 0;
 	for (i = 0; !doc_is_ready(docg3) && i < 5; i++)
 		msleep(20);
 	if (!doc_is_ready(docg3)) {
 		doc_dbg("Timeout reached and the chip is still not ready\n");
 		ret = -EAGAIN;
 		goto out;
 	}
 	status = doc_get_op_status(docg3);
 	if (status & DOC_PLANES_STATUS_FAIL) {
 		doc_dbg("Erase/Write failed on (a) plane(s), status = %x\n",
 			status);
 		ret = -EIO;
 	}
 out:
 	doc_page_finish(docg3);
 	return ret;
 }
 /**
  * doc_erase_block - Erase a couple of blocks
  * @docg3: the device
  * @block0: the first block to erase (leftmost plane)
  * @block1: the second block to erase (rightmost plane)
  *
  * Erase both blocks, and return operation status
  *
  * Returns 0 if erase successful, -EIO if erase issue, -ETIMEOUT if chip not
  * ready for too long
  */
 static int doc_erase_block(struct docg3 *docg3, int block0, int block1)
 {
 	int ret, sector;
 	doc_dbg("doc_erase_block(blocks=(%d,%d))\n", block0, block1);
 	ret = doc_reset_seq(docg3);
 	if (ret)
 		return -EIO;
 	doc_set_reliable_mode(docg3);
 	doc_flash_sequence(docg3, DOC_SEQ_ERASE);
 	sector = block0 << DOC_ADDR_BLOCK_SHIFT;
 	doc_flash_command(docg3, DOC_CMD_PROG_BLOCK_ADDR);
 	doc_setup_addr_sector(docg3, sector);
 	sector = block1 << DOC_ADDR_BLOCK_SHIFT;
 	doc_flash_command(docg3, DOC_CMD_PROG_BLOCK_ADDR);
 	doc_setup_addr_sector(docg3, sector);
 	doc_delay(docg3, 1);
 	doc_flash_command(docg3, DOC_CMD_ERASECYCLE2);
 	doc_delay(docg3, 2);
 	if (is_prot_seq_error(docg3)) {
 		doc_err("Erase blocks %d,%d error\n", block0, block1);
 		return -EIO;
 	}
 	return doc_write_erase_wait_status(docg3);
 }
 /**
  * doc_erase - Erase a portion of the chip
  * @mtd: the device
  * @info: the erase info
  *
  * Erase a bunch of contiguous blocks, by pairs, as a "mtd" page of 1024 is
  * split into 2 pages of 512 bytes on 2 contiguous blocks.
  *
  * Returns 0 if erase successful, -EINVAL if addressing error, -EIO if erase
  * issue
  */
 static int doc_erase(struct mtd_info *mtd, struct erase_info *info)
 {
 	struct docg3 *docg3 = mtd->priv;
 	uint64_t len;
 	int block0, block1, page, ret, ofs = 0;
 	doc_dbg("doc_erase(from=%lld, len=%lld\n", info->addr, info->len);
 	info->state = MTD_ERASE_PENDING;
 	calc_block_sector(info->addr + info->len, &block0, &block1, &page,
 			  &ofs, docg3->reliable);
 	ret = -EINVAL;
 	if (info->addr + info->len > mtd->size || page || ofs)
 		goto reset_err;
 	ret = 0;
 	calc_block_sector(info->addr, &block0, &block1, &page, &ofs,
 			  docg3->reliable);
 	mutex_lock(&docg3->cascade->lock);
 	doc_set_device_id(docg3, docg3->device_id);
 	doc_set_reliable_mode(docg3);
 	for (len = info->len; !ret && len > 0; len -= mtd->erasesize) {
 		info->state = MTD_ERASING;
 		ret = doc_erase_block(docg3, block0, block1);
 		block0 += 2;
 		block1 += 2;
 	}
 	mutex_unlock(&docg3->cascade->lock);
 	if (ret)
 		goto reset_err;
 	info->state = MTD_ERASE_DONE;
 	return 0;
 reset_err:
 	info->state = MTD_ERASE_FAILED;
 	return ret;
 }
 /**
  * doc_write_page - Write a single page to the chip
  * @docg3: the device
  * @to: the offset from first block and first page, in bytes, aligned on page
  *      size
  * @buf: buffer to get bytes from
  * @oob: buffer to get out of band bytes from (can be NULL if no OOB should be
  *       written)
  * @autoecc: if 0, all 16 bytes from OOB are taken, regardless of HW Hamming or
  *           BCH computations. If 1, only bytes 0-7 and byte 15 are taken,
  *           remaining ones are filled with hardware Hamming and BCH
  *           computations. Its value is not meaningfull is oob == NULL.
  *
  * Write one full page (ie. 1 page split on two planes), of 512 bytes, with the
  * OOB data. The OOB ECC is automatically computed by the hardware Hamming and
  * BCH generator if autoecc is not null.
  *
  * Returns 0 if write successful, -EIO if write error, -EAGAIN if timeout
  */
 static int doc_write_page(struct docg3 *docg3, loff_t to, const u_char *buf,
 			  const u_char *oob, int autoecc)
 {
 	int block0, block1, page, ret, ofs = 0;
 	u8 hwecc[DOC_ECC_BCH_SIZE], hamming;
 	doc_dbg("doc_write_page(to=%lld)\n", to);
 	calc_block_sector(to, &block0, &block1, &page, &ofs, docg3->reliable);
 	doc_set_device_id(docg3, docg3->device_id);
 	ret = doc_reset_seq(docg3);
 	if (ret)
 		goto err;
 	/* Program the flash address block and page */
 	ret = doc_write_seek(docg3, block0, block1, page, ofs);
 	if (ret)
 		goto err;
 	doc_write_page_ecc_init(docg3, DOC_ECC_BCH_TOTAL_BYTES);
 	doc_delay(docg3, 2);
 	doc_write_page_putbytes(docg3, DOC_LAYOUT_PAGE_SIZE, buf);
 	if (oob && autoecc) {
 		doc_write_page_putbytes(docg3, DOC_LAYOUT_OOB_PAGEINFO_SZ, oob);
 		doc_delay(docg3, 2);
 		oob += DOC_LAYOUT_OOB_UNUSED_OFS;
 		hamming = doc_register_readb(docg3, DOC_HAMMINGPARITY);
 		doc_delay(docg3, 2);
 		doc_write_page_putbytes(docg3, DOC_LAYOUT_OOB_HAMMING_SZ,
 					&hamming);
 		doc_delay(docg3, 2);
 		doc_get_bch_hw_ecc(docg3, hwecc);
 		doc_write_page_putbytes(docg3, DOC_LAYOUT_OOB_BCH_SZ, hwecc);
 		doc_delay(docg3, 2);
 		doc_write_page_putbytes(docg3, DOC_LAYOUT_OOB_UNUSED_SZ, oob);
 	}
 	if (oob && !autoecc)
 		doc_write_page_putbytes(docg3, DOC_LAYOUT_OOB_SIZE, oob);
 	doc_delay(docg3, 2);
 	doc_page_finish(docg3);
 	doc_delay(docg3, 2);
 	doc_flash_command(docg3, DOC_CMD_PROG_CYCLE2);
 	doc_delay(docg3, 2);
 	/*
 	 * The wait status will perform another doc_page_finish() call, but that
 	 * seems to please the docg3, so leave it.
 	 */
 	ret = doc_write_erase_wait_status(docg3);
 	return ret;
 err:
 	doc_read_page_finish(docg3);
 	return ret;
 }
 /**
  * doc_guess_autoecc - Guess autoecc mode from mbd_oob_ops
  * @ops: the oob operations
  *
  * Returns 0 or 1 if success, -EINVAL if invalid oob mode
  */
 static int doc_guess_autoecc(struct mtd_oob_ops *ops)
 {
 	int autoecc;
 	switch (ops->mode) {
 	case MTD_OPS_PLACE_OOB:
 	case MTD_OPS_AUTO_OOB:
 		autoecc = 1;
 		break;
 	case MTD_OPS_RAW:
 		autoecc = 0;
 		break;
 	default:
 		autoecc = -EINVAL;
 	}
 	return autoecc;
 }
 /**
  * doc_fill_autooob - Fill a 16 bytes OOB from 8 non-ECC bytes
  * @dst: the target 16 bytes OOB buffer
  * @oobsrc: the source 8 bytes non-ECC OOB buffer
  *
  */
 static void doc_fill_autooob(u8 *dst, u8 *oobsrc)
 {
 	memcpy(dst, oobsrc, DOC_LAYOUT_OOB_PAGEINFO_SZ);
 	dst[DOC_LAYOUT_OOB_UNUSED_OFS] = oobsrc[DOC_LAYOUT_OOB_PAGEINFO_SZ];
 }
 /**
  * doc_backup_oob - Backup OOB into docg3 structure
  * @docg3: the device
  * @to: the page offset in the chip
  * @ops: the OOB size and buffer
  *
  * As the docg3 should write a page with its OOB in one pass, and some userland
  * applications do write_oob() to setup the OOB and then write(), store the OOB
  * into a temporary storage. This is very dangerous, as 2 concurrent
  * applications could store an OOB, and then write their pages (which will
  * result into one having its OOB corrupted).
  *
  * The only reliable way would be for userland to call doc_write_oob() with both
  * the page data _and_ the OOB area.
  *
  * Returns 0 if success, -EINVAL if ops content invalid
  */
 static int doc_backup_oob(struct docg3 *docg3, loff_t to,
 			  struct mtd_oob_ops *ops)
 {
 	int ooblen = ops->ooblen, autoecc;
 	if (ooblen != DOC_LAYOUT_OOB_SIZE)
 		return -EINVAL;
 	autoecc = doc_guess_autoecc(ops);
 	if (autoecc < 0)
 		return autoecc;
 	docg3->oob_write_ofs = to;
 	docg3->oob_autoecc = autoecc;
 	if (ops->mode == MTD_OPS_AUTO_OOB) {
 		doc_fill_autooob(docg3->oob_write_buf, ops->oobbuf);
 		ops->oobretlen = 8;
 	} else {
 		memcpy(docg3->oob_write_buf, ops->oobbuf, DOC_LAYOUT_OOB_SIZE);
 		ops->oobretlen = DOC_LAYOUT_OOB_SIZE;
 	}
 	return 0;
 }
 /**
  * doc_write_oob - Write out of band bytes to flash
  * @mtd: the device
  * @ofs: the offset from first block and first page, in bytes, aligned on page
  *       size
  * @ops: the mtd oob structure
  *
  * Either write OOB data into a temporary buffer, for the subsequent write
  * page. The provided OOB should be 16 bytes long. If a data buffer is provided
  * as well, issue the page write.
  * Or provide data without OOB, and then a all zeroed OOB will be used (ECC will
  * still be filled in if asked for).
  *
  * Returns 0 is successful, EINVAL if length is not 14 bytes
  */
 static int doc_write_oob(struct mtd_info *mtd, loff_t ofs,
 			 struct mtd_oob_ops *ops)
 {
 	struct docg3 *docg3 = mtd->priv;
 	int ret, autoecc, oobdelta;
 	u8 *oobbuf = ops->oobbuf;
 	u8 *buf = ops->datbuf;
 	size_t len, ooblen;
 	u8 oob[DOC_LAYOUT_OOB_SIZE];
 	if (buf)
 		len = ops->len;
 	else
 		len = 0;
 	if (oobbuf)
 		ooblen = ops->ooblen;
 	else
 		ooblen = 0;
 	if (oobbuf && ops->mode == MTD_OPS_PLACE_OOB)
 		oobbuf += ops->ooboffs;
 	doc_dbg("doc_write_oob(from=%lld, mode=%d, data=(%p:%zu), oob=(%p:%zu))\n",
 		ofs, ops->mode, buf, len, oobbuf, ooblen);
 	switch (ops->mode) {
 	case MTD_OPS_PLACE_OOB:
 	case MTD_OPS_RAW:
 		oobdelta = mtd->oobsize;
 		break;
 	case MTD_OPS_AUTO_OOB:
 		oobdelta = mtd->ecclayout->oobavail;
 		break;
 	default:
 		oobdelta = 0;
 	}
 	if ((len % DOC_LAYOUT_PAGE_SIZE) || (ooblen % oobdelta) ||
 	    (ofs % DOC_LAYOUT_PAGE_SIZE))
 		return -EINVAL;
 	if (len && ooblen &&
 	    (len / DOC_LAYOUT_PAGE_SIZE) != (ooblen / oobdelta))
 		return -EINVAL;
 	if (ofs + len > mtd->size)
 		return -EINVAL;
 	ops->oobretlen = 0;
 	ops->retlen = 0;
 	ret = 0;
 	if (len == 0 && ooblen == 0)
 		return -EINVAL;
 	if (len == 0 && ooblen > 0)
 		return doc_backup_oob(docg3, ofs, ops);
 	autoecc = doc_guess_autoecc(ops);
 	if (autoecc < 0)
 		return autoecc;
 	mutex_lock(&docg3->cascade->lock);
 	while (!ret && len > 0) {
 		memset(oob, 0, sizeof(oob));
 		if (ofs == docg3->oob_write_ofs)
 			memcpy(oob, docg3->oob_write_buf, DOC_LAYOUT_OOB_SIZE);
 		else if (ooblen > 0 && ops->mode == MTD_OPS_AUTO_OOB)
 			doc_fill_autooob(oob, oobbuf);
 		else if (ooblen > 0)
 			memcpy(oob, oobbuf, DOC_LAYOUT_OOB_SIZE);
 		ret = doc_write_page(docg3, ofs, buf, oob, autoecc);
 		ofs += DOC_LAYOUT_PAGE_SIZE;
 		len -= DOC_LAYOUT_PAGE_SIZE;
 		buf += DOC_LAYOUT_PAGE_SIZE;
 		if (ooblen) {
 			oobbuf += oobdelta;
 			ooblen -= oobdelta;
 			ops->oobretlen += oobdelta;
 		}
 		ops->retlen += DOC_LAYOUT_PAGE_SIZE;
 	}
 	doc_set_device_id(docg3, 0);
 	mutex_unlock(&docg3->cascade->lock);
 	return ret;
 }
 /**
  * doc_write - Write a buffer to the chip
  * @mtd: the device
  * @to: the offset from first block and first page, in bytes, aligned on page
  *      size
  * @len: the number of bytes to write (must be a full page size, ie. 512)
  * @retlen: the number of bytes actually written (0 or 512)
  * @buf: the buffer to get bytes from
  *
  * Writes data to the chip.
  *
  * Returns 0 if write successful, -EIO if write error
  */
 static int doc_write(struct mtd_info *mtd, loff_t to, size_t len,
 		     size_t *retlen, const u_char *buf)
 {
 	struct docg3 *docg3 = mtd->priv;
 	int ret;
 	struct mtd_oob_ops ops;
 	doc_dbg("doc_write(to=%lld, len=%zu)\n", to, len);
 	ops.datbuf = (char *)buf;
 	ops.len = len;
 	ops.mode = MTD_OPS_PLACE_OOB;
 	ops.oobbuf = NULL;
 	ops.ooblen = 0;
 	ops.ooboffs = 0;
 	ret = doc_write_oob(mtd, to, &ops);
 	*retlen = ops.retlen;
 	return ret;
 }
 static struct docg3 *sysfs_dev2docg3(struct device *dev,
 				     struct device_attribute *attr)
 {
 	int floor;
 	struct platform_device *pdev = to_platform_device(dev);
 	struct mtd_info **docg3_floors = platform_get_drvdata(pdev);
 	floor = attr->attr.name[1] - '0';
 	if (floor < 0 || floor >= DOC_MAX_NBFLOORS)
 		return NULL;
 	else
 		return docg3_floors[floor]->priv;
 }
 static ssize_t dps0_is_key_locked(struct device *dev,
 				  struct device_attribute *attr, char *buf)
 {
 	struct docg3 *docg3 = sysfs_dev2docg3(dev, attr);
 	int dps0;
 	mutex_lock(&docg3->cascade->lock);
 	doc_set_device_id(docg3, docg3->device_id);
 	dps0 = doc_register_readb(docg3, DOC_DPS0_STATUS);
 	doc_set_device_id(docg3, 0);
 	mutex_unlock(&docg3->cascade->lock);
 	return sprintf(buf, "%d\n", !(dps0 & DOC_DPS_KEY_OK));
 }
 static ssize_t dps1_is_key_locked(struct device *dev,
 				  struct device_attribute *attr, char *buf)
 {
 	struct docg3 *docg3 = sysfs_dev2docg3(dev, attr);
 	int dps1;
 	mutex_lock(&docg3->cascade->lock);
 	doc_set_device_id(docg3, docg3->device_id);
 	dps1 = doc_register_readb(docg3, DOC_DPS1_STATUS);
 	doc_set_device_id(docg3, 0);
 	mutex_unlock(&docg3->cascade->lock);
 	return sprintf(buf, "%d\n", !(dps1 & DOC_DPS_KEY_OK));
 }
 static ssize_t dps0_insert_key(struct device *dev,
 			       struct device_attribute *attr,
 			       const char *buf, size_t count)
 {
 	struct docg3 *docg3 = sysfs_dev2docg3(dev, attr);
 	int i;
 	if (count != DOC_LAYOUT_DPS_KEY_LENGTH)
 		return -EINVAL;
 	mutex_lock(&docg3->cascade->lock);
 	doc_set_device_id(docg3, docg3->device_id);
 	for (i = 0; i < DOC_LAYOUT_DPS_KEY_LENGTH; i++)
 		doc_writeb(docg3, buf[i], DOC_DPS0_KEY);
 	doc_set_device_id(docg3, 0);
 	mutex_unlock(&docg3->cascade->lock);
 	return count;
 }
 static ssize_t dps1_insert_key(struct device *dev,
 			       struct device_attribute *attr,
 			       const char *buf, size_t count)
 {
 	struct docg3 *docg3 = sysfs_dev2docg3(dev, attr);
 	int i;
 	if (count != DOC_LAYOUT_DPS_KEY_LENGTH)
 		return -EINVAL;
 	mutex_lock(&docg3->cascade->lock);
 	doc_set_device_id(docg3, docg3->device_id);
 	for (i = 0; i < DOC_LAYOUT_DPS_KEY_LENGTH; i++)
 		doc_writeb(docg3, buf[i], DOC_DPS1_KEY);
 	doc_set_device_id(docg3, 0);
 	mutex_unlock(&docg3->cascade->lock);
 	return count;
 }
 #define FLOOR_SYSFS(id) { \
 	__ATTR(f##id##_dps0_is_keylocked, S_IRUGO, dps0_is_key_locked, NULL), \
 	__ATTR(f##id##_dps1_is_keylocked, S_IRUGO, dps1_is_key_locked, NULL), \
 	__ATTR(f##id##_dps0_protection_key, S_IWUGO, NULL, dps0_insert_key), \
 	__ATTR(f##id##_dps1_protection_key, S_IWUGO, NULL, dps1_insert_key), \
 }
 static struct device_attribute doc_sys_attrs[DOC_MAX_NBFLOORS][4] = {
 	FLOOR_SYSFS(0), FLOOR_SYSFS(1), FLOOR_SYSFS(2), FLOOR_SYSFS(3)
 };
 static int doc_register_sysfs(struct platform_device *pdev,
 			      struct docg3_cascade *cascade)
 {
 	int ret = 0, floor, i = 0;
 	struct device *dev = &pdev->dev;
 	for (floor = 0; !ret && floor < DOC_MAX_NBFLOORS &&
 		     cascade->floors[floor]; floor++)
 		for (i = 0; !ret && i < 4; i++)
 			ret = device_create_file(dev, &doc_sys_attrs[floor][i]);
 	if (!ret)
 		return 0;
 	do {
 		while (--i >= 0)
 			device_remove_file(dev, &doc_sys_attrs[floor][i]);
 		i = 4;
 	} while (--floor >= 0);
 	return ret;
 }
 static void doc_unregister_sysfs(struct platform_device *pdev,
 				 struct docg3_cascade *cascade)
 {
 	struct device *dev = &pdev->dev;
 	int floor, i;
 	for (floor = 0; floor < DOC_MAX_NBFLOORS && cascade->floors[floor];
 	     floor++)
 		for (i = 0; i < 4; i++)
 			device_remove_file(dev, &doc_sys_attrs[floor][i]);
 }
 /*
  * Debug sysfs entries
  */
 static int dbg_flashctrl_show(struct seq_file *s, void *p)
 {
 	struct docg3 *docg3 = (struct docg3 *)s->private;
 	int pos = 0;
 	u8 fctrl;
 	mutex_lock(&docg3->cascade->lock);
 	fctrl = doc_register_readb(docg3, DOC_FLASHCONTROL);
 	mutex_unlock(&docg3->cascade->lock);
 	pos += seq_printf(s,
 		 "FlashControl : 0x%02x (%s,CE# %s,%s,%s,flash %s)\n",
 		 fctrl,
 		 fctrl & DOC_CTRL_VIOLATION ? "protocol violation" : "-",
 		 fctrl & DOC_CTRL_CE ? "active" : "inactive",
 		 fctrl & DOC_CTRL_PROTECTION_ERROR ? "protection error" : "-",
 		 fctrl & DOC_CTRL_SEQUENCE_ERROR ? "sequence error" : "-",
 		 fctrl & DOC_CTRL_FLASHREADY ? "ready" : "not ready");
 	return pos;
 }
 DEBUGFS_RO_ATTR(flashcontrol, dbg_flashctrl_show);
 static int dbg_asicmode_show(struct seq_file *s, void *p)
 {
 	struct docg3 *docg3 = (struct docg3 *)s->private;
 	int pos = 0, pctrl, mode;
 	mutex_lock(&docg3->cascade->lock);
 	pctrl = doc_register_readb(docg3, DOC_ASICMODE);
 	mode = pctrl & 0x03;
 	mutex_unlock(&docg3->cascade->lock);
 	pos += seq_printf(s,
 			 "%04x : RAM_WE=%d,RSTIN_RESET=%d,BDETCT_RESET=%d,WRITE_ENABLE=%d,POWERDOWN=%d,MODE=%d%d (",
 			 pctrl,
 			 pctrl & DOC_ASICMODE_RAM_WE ? 1 : 0,
 			 pctrl & DOC_ASICMODE_RSTIN_RESET ? 1 : 0,
 			 pctrl & DOC_ASICMODE_BDETCT_RESET ? 1 : 0,
 			 pctrl & DOC_ASICMODE_MDWREN ? 1 : 0,
 			 pctrl & DOC_ASICMODE_POWERDOWN ? 1 : 0,
 			 mode >> 1, mode & 0x1);
 	switch (mode) {
 	case DOC_ASICMODE_RESET:
 		pos += seq_printf(s, "reset");
 		break;
 	case DOC_ASICMODE_NORMAL:
 		pos += seq_printf(s, "normal");
 		break;
 	case DOC_ASICMODE_POWERDOWN:
 		pos += seq_printf(s, "powerdown");
 		break;
 	}
 	pos += seq_printf(s, ")\n");
 	return pos;
 }
 DEBUGFS_RO_ATTR(asic_mode, dbg_asicmode_show);
 static int dbg_device_id_show(struct seq_file *s, void *p)
 {
 	struct docg3 *docg3 = (struct docg3 *)s->private;
 	int pos = 0;
 	int id;
 	mutex_lock(&docg3->cascade->lock);
 	id = doc_register_readb(docg3, DOC_DEVICESELECT);
 	mutex_unlock(&docg3->cascade->lock);
 	pos += seq_printf(s, "DeviceId = %d\n", id);
 	return pos;
 }
 DEBUGFS_RO_ATTR(device_id, dbg_device_id_show);
 static int dbg_protection_show(struct seq_file *s, void *p)
 {
 	struct docg3 *docg3 = (struct docg3 *)s->private;
 	int pos = 0;
 	int protect, dps0, dps0_low, dps0_high, dps1, dps1_low, dps1_high;
 	mutex_lock(&docg3->cascade->lock);
 	protect = doc_register_readb(docg3, DOC_PROTECTION);
 	dps0 = doc_register_readb(docg3, DOC_DPS0_STATUS);
 	dps0_low = doc_register_readw(docg3, DOC_DPS0_ADDRLOW);
 	dps0_high = doc_register_readw(docg3, DOC_DPS0_ADDRHIGH);
 	dps1 = doc_register_readb(docg3, DOC_DPS1_STATUS);
 	dps1_low = doc_register_readw(docg3, DOC_DPS1_ADDRLOW);
 	dps1_high = doc_register_readw(docg3, DOC_DPS1_ADDRHIGH);
 	mutex_unlock(&docg3->cascade->lock);
 	pos += seq_printf(s, "Protection = 0x%02x (",
 			 protect);
 	if (protect & DOC_PROTECT_FOUNDRY_OTP_LOCK)
 		pos += seq_printf(s, "FOUNDRY_OTP_LOCK,");
 	if (protect & DOC_PROTECT_CUSTOMER_OTP_LOCK)
 		pos += seq_printf(s, "CUSTOMER_OTP_LOCK,");
 	if (protect & DOC_PROTECT_LOCK_INPUT)
 		pos += seq_printf(s, "LOCK_INPUT,");
 	if (protect & DOC_PROTECT_STICKY_LOCK)
 		pos += seq_printf(s, "STICKY_LOCK,");
 	if (protect & DOC_PROTECT_PROTECTION_ENABLED)
 		pos += seq_printf(s, "PROTECTION ON,");
 	if (protect & DOC_PROTECT_IPL_DOWNLOAD_LOCK)
 		pos += seq_printf(s, "IPL_DOWNLOAD_LOCK,");
 	if (protect & DOC_PROTECT_PROTECTION_ERROR)
 		pos += seq_printf(s, "PROTECT_ERR,");
 	else
 		pos += seq_printf(s, "NO_PROTECT_ERR");
 	pos += seq_printf(s, ")\n");
 	pos += seq_printf(s, "DPS0 = 0x%02x : "
 			 "Protected area [0x%x - 0x%x] : OTP=%d, READ=%d, "
 			 "WRITE=%d, HW_LOCK=%d, KEY_OK=%d\n",
 			 dps0, dps0_low, dps0_high,
 			 !!(dps0 & DOC_DPS_OTP_PROTECTED),
 			 !!(dps0 & DOC_DPS_READ_PROTECTED),
 			 !!(dps0 & DOC_DPS_WRITE_PROTECTED),
 			 !!(dps0 & DOC_DPS_HW_LOCK_ENABLED),
 			 !!(dps0 & DOC_DPS_KEY_OK));
 	pos += seq_printf(s, "DPS1 = 0x%02x : "
 			 "Protected area [0x%x - 0x%x] : OTP=%d, READ=%d, "
 			 "WRITE=%d, HW_LOCK=%d, KEY_OK=%d\n",
 			 dps1, dps1_low, dps1_high,
 			 !!(dps1 & DOC_DPS_OTP_PROTECTED),
 			 !!(dps1 & DOC_DPS_READ_PROTECTED),
 			 !!(dps1 & DOC_DPS_WRITE_PROTECTED),
 			 !!(dps1 & DOC_DPS_HW_LOCK_ENABLED),
 			 !!(dps1 & DOC_DPS_KEY_OK));
 	return pos;
 }
 DEBUGFS_RO_ATTR(protection, dbg_protection_show);
 static int __init doc_dbg_register(struct docg3 *docg3)
 {
 	struct dentry *root, *entry;
 	root = debugfs_create_dir("docg3", NULL);
 	if (!root)
 		return -ENOMEM;
 	entry = debugfs_create_file("flashcontrol", S_IRUSR, root, docg3,
 				  &flashcontrol_fops);
 	if (entry)
 		entry = debugfs_create_file("asic_mode", S_IRUSR, root,
 					    docg3, &asic_mode_fops);
 	if (entry)
 		entry = debugfs_create_file("device_id", S_IRUSR, root,
 					    docg3, &device_id_fops);
 	if (entry)
 		entry = debugfs_create_file("protection", S_IRUSR, root,
 					    docg3, &protection_fops);
 	if (entry) {
 		docg3->debugfs_root = root;
 		return 0;
 	} else {
 		debugfs_remove_recursive(root);
 		return -ENOMEM;
 	}
 }
 static void __exit doc_dbg_unregister(struct docg3 *docg3)
 {
 	debugfs_remove_recursive(docg3->debugfs_root);
 }
 /**
  * doc_set_driver_info - Fill the mtd_info structure and docg3 structure
  * @chip_id: The chip ID of the supported chip
  * @mtd: The structure to fill
  */
 static void __init doc_set_driver_info(int chip_id, struct mtd_info *mtd)
 {
 	struct docg3 *docg3 = mtd->priv;
 	int cfg;
 	cfg = doc_register_readb(docg3, DOC_CONFIGURATION);
 	docg3->if_cfg = (cfg & DOC_CONF_IF_CFG ? 1 : 0);
 	docg3->reliable = reliable_mode;
 	switch (chip_id) {
 	case DOC_CHIPID_G3:
 		mtd->name = kasprintf(GFP_KERNEL, "docg3.%d",
 				      docg3->device_id);
 		docg3->max_block = 2047;
 		break;
 	}
 	mtd->type = MTD_NANDFLASH;
 	mtd->flags = MTD_CAP_NANDFLASH;
 	mtd->size = (docg3->max_block + 1) * DOC_LAYOUT_BLOCK_SIZE;
 	if (docg3->reliable == 2)
 		mtd->size /= 2;
 	mtd->erasesize = DOC_LAYOUT_BLOCK_SIZE * DOC_LAYOUT_NBPLANES;
 	if (docg3->reliable == 2)
 		mtd->erasesize /= 2;
 	mtd->writebufsize = mtd->writesize = DOC_LAYOUT_PAGE_SIZE;
 	mtd->oobsize = DOC_LAYOUT_OOB_SIZE;
 	mtd->owner = THIS_MODULE;
 	mtd->_erase = doc_erase;
 	mtd->_read = doc_read;
 	mtd->_write = doc_write;
 	mtd->_read_oob = doc_read_oob;
 	mtd->_write_oob = doc_write_oob;
 	mtd->_block_isbad = doc_block_isbad;
 	mtd->ecclayout = &docg3_oobinfo;
 	mtd->ecc_strength = DOC_ECC_BCH_T;
 }
 /**
  * doc_probe_device - Check if a device is available
  * @base: the io space where the device is probed
  * @floor: the floor of the probed device
  * @dev: the device
  * @cascade: the cascade of chips this devices will belong to
  *
  * Checks whether a device at the specified IO range, and floor is available.
  *
  * Returns a mtd_info struct if there is a device, ENODEV if none found, ENOMEM
  * if a memory allocation failed. If floor 0 is checked, a reset of the ASIC is
  * launched.
  */
 static struct mtd_info * __init
 doc_probe_device(struct docg3_cascade *cascade, int floor, struct device *dev)
 {
 	int ret, bbt_nbpages;
 	u16 chip_id, chip_id_inv;
 	struct docg3 *docg3;
 	struct mtd_info *mtd;
 	ret = -ENOMEM;
 	docg3 = kzalloc(sizeof(struct docg3), GFP_KERNEL);
 	if (!docg3)
 		goto nomem1;
 	mtd = kzalloc(sizeof(struct mtd_info), GFP_KERNEL);
 	if (!mtd)
 		goto nomem2;
 	mtd->priv = docg3;
 	bbt_nbpages = DIV_ROUND_UP(docg3->max_block + 1,
 				   8 * DOC_LAYOUT_PAGE_SIZE);
 	docg3->bbt = kzalloc(bbt_nbpages * DOC_LAYOUT_PAGE_SIZE, GFP_KERNEL);
 	if (!docg3->bbt)
 		goto nomem3;
 	docg3->dev = dev;
 	docg3->device_id = floor;
 	docg3->cascade = cascade;
 	doc_set_device_id(docg3, docg3->device_id);
 	if (!floor)
 		doc_set_asic_mode(docg3, DOC_ASICMODE_RESET);
 	doc_set_asic_mode(docg3, DOC_ASICMODE_NORMAL);
 	chip_id = doc_register_readw(docg3, DOC_CHIPID);
 	chip_id_inv = doc_register_readw(docg3, DOC_CHIPID_INV);
 	ret = 0;
 	if (chip_id != (u16)(~chip_id_inv)) {
 		goto nomem3;
 	}
 	switch (chip_id) {
 	case DOC_CHIPID_G3:
 		doc_info("Found a G3 DiskOnChip at addr %p, floor %d\n",
 			 docg3->cascade->base, floor);
 		break;
 	default:
 		doc_err("Chip id %04x is not a DiskOnChip G3 chip\n", chip_id);
 		goto nomem3;
 	}
 	doc_set_driver_info(chip_id, mtd);
 	doc_hamming_ecc_init(docg3, DOC_LAYOUT_OOB_PAGEINFO_SZ);
 	doc_reload_bbt(docg3);
 	return mtd;
 nomem3:
 	kfree(mtd);
 nomem2:
 	kfree(docg3);
 nomem1:
 	return ERR_PTR(ret);
 }
 /**
  * doc_release_device - Release a docg3 floor
  * @mtd: the device
  */
 static void doc_release_device(struct mtd_info *mtd)
 {
 	struct docg3 *docg3 = mtd->priv;
 	mtd_device_unregister(mtd);
 	kfree(docg3->bbt);
 	kfree(docg3);
 	kfree(mtd->name);
 	kfree(mtd);
 }
 /**
  * docg3_resume - Awakens docg3 floor
  * @pdev: platfrom device
  *
  * Returns 0 (always successful)
  */
 static int docg3_resume(struct platform_device *pdev)
 {
 	int i;
 	struct docg3_cascade *cascade;
 	struct mtd_info **docg3_floors, *mtd;
 	struct docg3 *docg3;
 	cascade = platform_get_drvdata(pdev);
 	docg3_floors = cascade->floors;
 	mtd = docg3_floors[0];
 	docg3 = mtd->priv;
 	doc_dbg("docg3_resume()\n");
 	for (i = 0; i < 12; i++)
 		doc_readb(docg3, DOC_IOSPACE_IPL);
 	return 0;
 }
 /**
  * docg3_suspend - Put in low power mode the docg3 floor
  * @pdev: platform device
  * @state: power state
  *
  * Shuts off most of docg3 circuitery to lower power consumption.
  *
  * Returns 0 if suspend succeeded, -EIO if chip refused suspend
  */
 static int docg3_suspend(struct platform_device *pdev, pm_message_t state)
 {
 	int floor, i;
 	struct docg3_cascade *cascade;
 	struct mtd_info **docg3_floors, *mtd;
 	struct docg3 *docg3;
 	u8 ctrl, pwr_down;
 	cascade = platform_get_drvdata(pdev);
 	docg3_floors = cascade->floors;
 	for (floor = 0; floor < DOC_MAX_NBFLOORS; floor++) {
 		mtd = docg3_floors[floor];
 		if (!mtd)
 			continue;
 		docg3 = mtd->priv;
 		doc_writeb(docg3, floor, DOC_DEVICESELECT);
 		ctrl = doc_register_readb(docg3, DOC_FLASHCONTROL);
 		ctrl &= ~DOC_CTRL_VIOLATION & ~DOC_CTRL_CE;
 		doc_writeb(docg3, ctrl, DOC_FLASHCONTROL);
 		for (i = 0; i < 10; i++) {
 			usleep_range(3000, 4000);
 			pwr_down = doc_register_readb(docg3, DOC_POWERMODE);
 			if (pwr_down & DOC_POWERDOWN_READY)
 				break;
 		}
 		if (pwr_down & DOC_POWERDOWN_READY) {
 			doc_dbg("docg3_suspend(): floor %d powerdown ok\n",
 				floor);
 		} else {
 			doc_err("docg3_suspend(): floor %d powerdown failed\n",
 				floor);
 			return -EIO;
 		}
 	}
 	mtd = docg3_floors[0];
 	docg3 = mtd->priv;
 	doc_set_asic_mode(docg3, DOC_ASICMODE_POWERDOWN);
 	return 0;
 }
 /**
  * doc_probe - Probe the IO space for a DiskOnChip G3 chip
  * @pdev: platform device
  *
  * Probes for a G3 chip at the specified IO space in the platform data
  * ressources. The floor 0 must be available.
  *
  * Returns 0 on success, -ENOMEM, -ENXIO on error
  */
 static int __init docg3_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct mtd_info *mtd;
 	struct resource *ress;
 	void __iomem *base;
 	int ret, floor, found = 0;
 	struct docg3_cascade *cascade;
 	ret = -ENXIO;
 	ress = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!ress) {
 		dev_err(dev, "No I/O memory resource defined\n");
 		goto noress;
 	}
 	base = ioremap(ress->start, DOC_IOSPACE_SIZE);
 	ret = -ENOMEM;
 	cascade = kzalloc(sizeof(*cascade) * DOC_MAX_NBFLOORS,
 			  GFP_KERNEL);
 	if (!cascade)
 		goto nomem1;
 	cascade->base = base;
 	mutex_init(&cascade->lock);
 	cascade->bch = init_bch(DOC_ECC_BCH_M, DOC_ECC_BCH_T,
 			     DOC_ECC_BCH_PRIMPOLY);
 	if (!cascade->bch)
 		goto nomem2;
 	for (floor = 0; floor < DOC_MAX_NBFLOORS; floor++) {
 		mtd = doc_probe_device(cascade, floor, dev);
 		if (IS_ERR(mtd)) {
 			ret = PTR_ERR(mtd);
 			goto err_probe;
 		}
 		if (!mtd) {
 			if (floor == 0)
 				goto notfound;
 			else
 				continue;
 		}
 		cascade->floors[floor] = mtd;
 		ret = mtd_device_parse_register(mtd, part_probes, NULL, NULL,
 						0);
 		if (ret)
 			goto err_probe;
 		found++;
 	}
 	ret = doc_register_sysfs(pdev, cascade);
 	if (ret)
 		goto err_probe;
 	if (!found)
 		goto notfound;
 	platform_set_drvdata(pdev, cascade);
 	doc_dbg_register(cascade->floors[0]->priv);
 	return 0;
 notfound:
 	ret = -ENODEV;
 	dev_info(dev, "No supported DiskOnChip found\n");
 err_probe:
 	kfree(cascade->bch);
 	for (floor = 0; floor < DOC_MAX_NBFLOORS; floor++)
 		if (cascade->floors[floor])
 			doc_release_device(cascade->floors[floor]);
 nomem2:
 	kfree(cascade);
 nomem1:
 	iounmap(base);
 noress:
 	return ret;
 }
 /**
  * docg3_release - Release the driver
  * @pdev: the platform device
  *
  * Returns 0
  */
 static int __exit docg3_release(struct platform_device *pdev)
 {
 	struct docg3_cascade *cascade = platform_get_drvdata(pdev);
 	struct docg3 *docg3 = cascade->floors[0]->priv;
 	void __iomem *base = cascade->base;
 	int floor;
 	doc_unregister_sysfs(pdev, cascade);
 	doc_dbg_unregister(docg3);
 	for (floor = 0; floor < DOC_MAX_NBFLOORS; floor++)
 		if (cascade->floors[floor])
 			doc_release_device(cascade->floors[floor]);
 	free_bch(docg3->cascade->bch);
 	kfree(cascade);
 	iounmap(base);
 	return 0;
 }
 static struct platform_driver g3_driver = {
 	.driver		= {
 		.name	= "docg3",
 		.owner	= THIS_MODULE,
 	},
 	.suspend	= docg3_suspend,
 	.resume		= docg3_resume,
 	.remove		= __exit_p(docg3_release),
 };
 static int __init docg3_init(void)
 {
 	return platform_driver_probe(&g3_driver, docg3_probe);
 }
 module_init(docg3_init);
 static void __exit docg3_exit(void)
 {
 	platform_driver_unregister(&g3_driver);
 }
 module_exit(docg3_exit);
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
 MODULE_DESCRIPTION("MTD driver for DiskOnChip G3");

drivers/mtd/nand/bcm_umi_bch.c

Diff comments View file @ 13e8597

 /*****************************************************************************
 * Copyright 2004 - 2009 Broadcom Corporation.  All rights reserved.
 *
 * Unless you and Broadcom execute a separate written software license
 * agreement governing use of this software, this software is licensed to you
 * under the terms of the GNU General Public License version 2, available at
 * http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
 *
 * Notwithstanding the above, under no circumstances may you combine this
 * software in any way with any other Broadcom software provided under a
 * license other than the GPL, without Broadcom's express prior written
 * consent.
 *****************************************************************************/
 /* ---- Include Files ---------------------------------------------------- */
 #include "nand_bcm_umi.h"
 /* ---- External Variable Declarations ----------------------------------- */
 /* ---- External Function Prototypes ------------------------------------- */
 /* ---- Public Variables ------------------------------------------------- */
 /* ---- Private Constants and Types -------------------------------------- */
 /* ---- Private Function Prototypes -------------------------------------- */
 static int bcm_umi_bch_read_page_hwecc(struct mtd_info *mtd,
 	struct nand_chip *chip, uint8_t *buf, int oob_required, int page);
 static int bcm_umi_bch_write_page_hwecc(struct mtd_info *mtd,
 	struct nand_chip *chip, const uint8_t *buf, int oob_required);
 /* ---- Private Variables ------------------------------------------------ */
 /*
 ** nand_hw_eccoob
 ** New oob placement block for use with hardware ecc generation.
 */
 static struct nand_ecclayout nand_hw_eccoob_512 = {
 	/* Reserve 5 for BI indicator */
 	.oobfree = {
 #if (NAND_ECC_NUM_BYTES > 3)
 		    {.offset = 0, .length = 2}
 #else
 		    {.offset = 0, .length = 5},
 		    {.offset = 6, .length = 7}
 #endif
 		    }
 };
 /*
 ** We treat the OOB for a 2K page as if it were 4 512 byte oobs,
 ** except the BI is at byte 0.
 */
 static struct nand_ecclayout nand_hw_eccoob_2048 = {
 	/* Reserve 0 as BI indicator */
 	.oobfree = {
 #if (NAND_ECC_NUM_BYTES > 10)
 		    {.offset = 1, .length = 2},
 #elif (NAND_ECC_NUM_BYTES > 7)
 		    {.offset = 1, .length = 5},
 		    {.offset = 16, .length = 6},
 		    {.offset = 32, .length = 6},
 		    {.offset = 48, .length = 6}
 #else
 		    {.offset = 1, .length = 8},
 		    {.offset = 16, .length = 9},
 		    {.offset = 32, .length = 9},
 		    {.offset = 48, .length = 9}
 #endif
 		    }
 };
 /* We treat the OOB for a 4K page as if it were 8 512 byte oobs,
  * except the BI is at byte 0. */
 static struct nand_ecclayout nand_hw_eccoob_4096 = {
 	/* Reserve 0 as BI indicator */
 	.oobfree = {
 #if (NAND_ECC_NUM_BYTES > 10)
 		    {.offset = 1, .length = 2},
 		    {.offset = 16, .length = 3},
 		    {.offset = 32, .length = 3},
 		    {.offset = 48, .length = 3},
 		    {.offset = 64, .length = 3},
 		    {.offset = 80, .length = 3},
 		    {.offset = 96, .length = 3},
 		    {.offset = 112, .length = 3}
 #else
 		    {.offset = 1, .length = 5},
 		    {.offset = 16, .length = 6},
 		    {.offset = 32, .length = 6},
 		    {.offset = 48, .length = 6},
 		    {.offset = 64, .length = 6},
 		    {.offset = 80, .length = 6},
 		    {.offset = 96, .length = 6},
 		    {.offset = 112, .length = 6}
 #endif
 		    }
 };
 /* ---- Private Functions ------------------------------------------------ */
 /* ==== Public Functions ================================================= */
 /****************************************************************************
 *
 *  bcm_umi_bch_read_page_hwecc - hardware ecc based page read function
 *  @mtd:	mtd info structure
 *  @chip:	nand chip info structure
 *  @buf:	buffer to store read data
 *  @oob_required:	caller expects OOB data read to chip->oob_poi
 *
 ***************************************************************************/
 static int bcm_umi_bch_read_page_hwecc(struct mtd_info *mtd,
 				       struct nand_chip *chip, uint8_t * buf,
 				       int oob_required, int page)
 {
 	int sectorIdx = 0;
 	int eccsize = chip->ecc.size;
 	int eccsteps = chip->ecc.steps;
 	uint8_t *datap = buf;
 	uint8_t eccCalc[NAND_ECC_NUM_BYTES];
 	int sectorOobSize = mtd->oobsize / eccsteps;
 	int stat;
 	unsigned int max_bitflips = 0;
 	for (sectorIdx = 0; sectorIdx < eccsteps;
 			sectorIdx++, datap += eccsize) {
 		if (sectorIdx > 0) {
 			/* Seek to page location within sector */
 			chip->cmdfunc(mtd, NAND_CMD_RNDOUT, sectorIdx * eccsize,
 				      -1);
 		}
 		/* Enable hardware ECC before reading the buf */
 		nand_bcm_umi_bch_enable_read_hwecc();
 		/* Read in data */
 		bcm_umi_nand_read_buf(mtd, datap, eccsize);
 		/* Pause hardware ECC after reading the buf */
 		nand_bcm_umi_bch_pause_read_ecc_calc();
 		/* Read the OOB ECC */
 		chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
 			      mtd->writesize + sectorIdx * sectorOobSize, -1);
 		nand_bcm_umi_bch_read_oobEcc(mtd->writesize, eccCalc,
 					     NAND_ECC_NUM_BYTES,
 					     chip->oob_poi +
 					     sectorIdx * sectorOobSize);
 		/* Correct any ECC detected errors */
 		stat =
 		    nand_bcm_umi_bch_correct_page(datap, eccCalc,
 						  NAND_ECC_NUM_BYTES);
 		/* Update Stats */
 		if (stat < 0) {
 #if defined(NAND_BCM_UMI_DEBUG)
 			printk(KERN_WARNING "%s uncorr_err sectorIdx=%d\n",
 			       __func__, sectorIdx);
-			printk(KERN_WARNING
+			printk(KERN_WARNING "%s data %*ph\n",
-			       "%s data %02x %02x %02x %02x "
+			       __func__, 8, datap);
-					 "%02x %02x %02x %02x\n",
+			printk(KERN_WARNING "%s ecc  %*ph\n",
-			       __func__, datap[0], datap[1], datap[2], datap[3],
+			       __func__, 13, eccCalc);
-			       datap[4], datap[5], datap[6], datap[7]);
-			printk(KERN_WARNING
-			       "%s ecc  %02x %02x %02x %02x "
-					 "%02x %02x %02x %02x %02x %02x "
-					 "%02x %02x %02x\n",
-			       __func__, eccCalc[0], eccCalc[1], eccCalc[2],
-			       eccCalc[3], eccCalc[4], eccCalc[5], eccCalc[6],
-			       eccCalc[7], eccCalc[8], eccCalc[9], eccCalc[10],
-			       eccCalc[11], eccCalc[12]);
 			BUG();
 #endif
 			mtd->ecc_stats.failed++;
 		} else {
 #if defined(NAND_BCM_UMI_DEBUG)
 			if (stat > 0) {
 				printk(KERN_INFO
 				       "%s %d correctable_errors detected\n",
 				       __func__, stat);
 			}
 #endif
 			mtd->ecc_stats.corrected += stat;
 			max_bitflips = max_t(unsigned int, max_bitflips, stat);
 		}
 	}
 	return max_bitflips;
 }
 /****************************************************************************
 *
 *  bcm_umi_bch_write_page_hwecc - hardware ecc based page write function
 *  @mtd:	mtd info structure
 *  @chip:	nand chip info structure
 *  @buf:	data buffer
 *  @oob_required:	must write chip->oob_poi to OOB
 *
 ***************************************************************************/
 static int bcm_umi_bch_write_page_hwecc(struct mtd_info *mtd,
 	struct nand_chip *chip, const uint8_t *buf, int oob_required)
 {
 	int sectorIdx = 0;
 	int eccsize = chip->ecc.size;
 	int eccsteps = chip->ecc.steps;
 	const uint8_t *datap = buf;
 	uint8_t *oobp = chip->oob_poi;
 	int sectorOobSize = mtd->oobsize / eccsteps;
 	for (sectorIdx = 0; sectorIdx < eccsteps;
 	     sectorIdx++, datap += eccsize, oobp += sectorOobSize) {
 		/* Enable hardware ECC before writing the buf */
 		nand_bcm_umi_bch_enable_write_hwecc();
 		bcm_umi_nand_write_buf(mtd, datap, eccsize);
 		nand_bcm_umi_bch_write_oobEcc(mtd->writesize, oobp,
 					      NAND_ECC_NUM_BYTES);
 	}
 	bcm_umi_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 	return 0;
 }

drivers/mtd/nand/s3c2410.c

Diff comments View file @ 13e8597

 /* linux/drivers/mtd/nand/s3c2410.c
  *
  * Copyright © 2004-2008 Simtec Electronics
  *	http://armlinux.simtec.co.uk/
  *	Ben Dooks <ben@simtec.co.uk>
  *
  * Samsung S3C2410/S3C2440/S3C2412 NAND driver
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
 #define pr_fmt(fmt) "nand-s3c2410: " fmt
 #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
 #define DEBUG
 #endif
 #include <linux/module.h>
 #include <linux/types.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/string.h>
 #include <linux/io.h>
 #include <linux/ioport.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/slab.h>
 #include <linux/clk.h>
 #include <linux/cpufreq.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/partitions.h>
 #include <plat/regs-nand.h>
 #include <plat/nand.h>
 /* new oob placement block for use with hardware ecc generation
  */
 static struct nand_ecclayout nand_hw_eccoob = {
 	.eccbytes = 3,
 	.eccpos = {0, 1, 2},
 	.oobfree = {{8, 8}}
 };
 /* controller and mtd information */
 struct s3c2410_nand_info;
 /**
  * struct s3c2410_nand_mtd - driver MTD structure
  * @mtd: The MTD instance to pass to the MTD layer.
  * @chip: The NAND chip information.
  * @set: The platform information supplied for this set of NAND chips.
  * @info: Link back to the hardware information.
  * @scan_res: The result from calling nand_scan_ident().
 */
 struct s3c2410_nand_mtd {
 	struct mtd_info			mtd;
 	struct nand_chip		chip;
 	struct s3c2410_nand_set		*set;
 	struct s3c2410_nand_info	*info;
 	int				scan_res;
 };
 enum s3c_cpu_type {
 	TYPE_S3C2410,
 	TYPE_S3C2412,
 	TYPE_S3C2440,
 };
 enum s3c_nand_clk_state {
 	CLOCK_DISABLE	= 0,
 	CLOCK_ENABLE,
 	CLOCK_SUSPEND,
 };
 /* overview of the s3c2410 nand state */
 /**
  * struct s3c2410_nand_info - NAND controller state.
  * @mtds: An array of MTD instances on this controoler.
  * @platform: The platform data for this board.
  * @device: The platform device we bound to.
  * @area: The IO area resource that came from request_mem_region().
  * @clk: The clock resource for this controller.
  * @regs: The area mapped for the hardware registers described by @area.
  * @sel_reg: Pointer to the register controlling the NAND selection.
  * @sel_bit: The bit in @sel_reg to select the NAND chip.
  * @mtd_count: The number of MTDs created from this controller.
  * @save_sel: The contents of @sel_reg to be saved over suspend.
  * @clk_rate: The clock rate from @clk.
  * @clk_state: The current clock state.
  * @cpu_type: The exact type of this controller.
  */
 struct s3c2410_nand_info {
 	/* mtd info */
 	struct nand_hw_control		controller;
 	struct s3c2410_nand_mtd		*mtds;
 	struct s3c2410_platform_nand	*platform;
 	/* device info */
 	struct device			*device;
 	struct resource			*area;
 	struct clk			*clk;
 	void __iomem			*regs;
 	void __iomem			*sel_reg;
 	int				sel_bit;
 	int				mtd_count;
 	unsigned long			save_sel;
 	unsigned long			clk_rate;
 	enum s3c_nand_clk_state		clk_state;
 	enum s3c_cpu_type		cpu_type;
 #ifdef CONFIG_CPU_FREQ
 	struct notifier_block	freq_transition;
 #endif
 };
 /* conversion functions */
 static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
 {
 	return container_of(mtd, struct s3c2410_nand_mtd, mtd);
 }
 static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
 {
 	return s3c2410_nand_mtd_toours(mtd)->info;
 }
 static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev)
 {
 	return platform_get_drvdata(dev);
 }
 static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev)
 {
 	return dev->dev.platform_data;
 }
 static inline int allow_clk_suspend(struct s3c2410_nand_info *info)
 {
 #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
 	return 1;
 #else
 	return 0;
 #endif
 }
 /**
  * s3c2410_nand_clk_set_state - Enable, disable or suspend NAND clock.
  * @info: The controller instance.
  * @new_state: State to which clock should be set.
  */
 static void s3c2410_nand_clk_set_state(struct s3c2410_nand_info *info,
 		enum s3c_nand_clk_state new_state)
 {
 	if (!allow_clk_suspend(info) && new_state == CLOCK_SUSPEND)
 		return;
 	if (info->clk_state == CLOCK_ENABLE) {
 		if (new_state != CLOCK_ENABLE)
 			clk_disable(info->clk);
 	} else {
 		if (new_state == CLOCK_ENABLE)
 			clk_enable(info->clk);
 	}
 	info->clk_state = new_state;
 }
 /* timing calculations */
 #define NS_IN_KHZ 1000000
 /**
  * s3c_nand_calc_rate - calculate timing data.
  * @wanted: The cycle time in nanoseconds.
  * @clk: The clock rate in kHz.
  * @max: The maximum divider value.
  *
  * Calculate the timing value from the given parameters.
  */
 static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max)
 {
 	int result;
 	result = DIV_ROUND_UP((wanted * clk), NS_IN_KHZ);
 	pr_debug("result %d from %ld, %d\n", result, clk, wanted);
 	if (result > max) {
 		pr_err("%d ns is too big for current clock rate %ld\n",
 			wanted, clk);
 		return -1;
 	}
 	if (result < 1)
 		result = 1;
 	return result;
 }
 #define to_ns(ticks, clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
 /* controller setup */
 /**
  * s3c2410_nand_setrate - setup controller timing information.
  * @info: The controller instance.
  *
  * Given the information supplied by the platform, calculate and set
  * the necessary timing registers in the hardware to generate the
  * necessary timing cycles to the hardware.
  */
 static int s3c2410_nand_setrate(struct s3c2410_nand_info *info)
 {
 	struct s3c2410_platform_nand *plat = info->platform;
 	int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4;
 	int tacls, twrph0, twrph1;
 	unsigned long clkrate = clk_get_rate(info->clk);
 	unsigned long uninitialized_var(set), cfg, uninitialized_var(mask);
 	unsigned long flags;
 	/* calculate the timing information for the controller */
 	info->clk_rate = clkrate;
 	clkrate /= 1000;	/* turn clock into kHz for ease of use */
 	if (plat != NULL) {
 		tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max);
 		twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8);
 		twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8);
 	} else {
 		/* default timings */
 		tacls = tacls_max;
 		twrph0 = 8;
 		twrph1 = 8;
 	}
 	if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
 		dev_err(info->device, "cannot get suitable timings\n");
 		return -EINVAL;
 	}
 	dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
 		tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate),
 						twrph1, to_ns(twrph1, clkrate));
 	switch (info->cpu_type) {
 	case TYPE_S3C2410:
 		mask = (S3C2410_NFCONF_TACLS(3) |
 			S3C2410_NFCONF_TWRPH0(7) |
 			S3C2410_NFCONF_TWRPH1(7));
 		set = S3C2410_NFCONF_EN;
 		set |= S3C2410_NFCONF_TACLS(tacls - 1);
 		set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
 		set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
 		break;
 	case TYPE_S3C2440:
 	case TYPE_S3C2412:
 		mask = (S3C2440_NFCONF_TACLS(tacls_max - 1) |
 			S3C2440_NFCONF_TWRPH0(7) |
 			S3C2440_NFCONF_TWRPH1(7));
 		set = S3C2440_NFCONF_TACLS(tacls - 1);
 		set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
 		set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
 		break;
 	default:
 		BUG();
 	}
 	local_irq_save(flags);
 	cfg = readl(info->regs + S3C2410_NFCONF);
 	cfg &= ~mask;
 	cfg |= set;
 	writel(cfg, info->regs + S3C2410_NFCONF);
 	local_irq_restore(flags);
 	dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
 	return 0;
 }
 /**
  * s3c2410_nand_inithw - basic hardware initialisation
  * @info: The hardware state.
  *
  * Do the basic initialisation of the hardware, using s3c2410_nand_setrate()
  * to setup the hardware access speeds and set the controller to be enabled.
 */
 static int s3c2410_nand_inithw(struct s3c2410_nand_info *info)
 {
 	int ret;
 	ret = s3c2410_nand_setrate(info);
 	if (ret < 0)
 		return ret;
 	switch (info->cpu_type) {
 	case TYPE_S3C2410:
 	default:
 		break;
 	case TYPE_S3C2440:
 	case TYPE_S3C2412:
 		/* enable the controller and de-assert nFCE */
 		writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT);
 	}
 	return 0;
 }
 /**
  * s3c2410_nand_select_chip - select the given nand chip
  * @mtd: The MTD instance for this chip.
  * @chip: The chip number.
  *
  * This is called by the MTD layer to either select a given chip for the
  * @mtd instance, or to indicate that the access has finished and the
  * chip can be de-selected.
  *
  * The routine ensures that the nFCE line is correctly setup, and any
  * platform specific selection code is called to route nFCE to the specific
  * chip.
  */
 static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
 {
 	struct s3c2410_nand_info *info;
 	struct s3c2410_nand_mtd *nmtd;
 	struct nand_chip *this = mtd->priv;
 	unsigned long cur;
 	nmtd = this->priv;
 	info = nmtd->info;
 	if (chip != -1)
 		s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
 	cur = readl(info->sel_reg);
 	if (chip == -1) {
 		cur |= info->sel_bit;
 	} else {
 		if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
 			dev_err(info->device, "invalid chip %d\n", chip);
 			return;
 		}
 		if (info->platform != NULL) {
 			if (info->platform->select_chip != NULL)
 				(info->platform->select_chip) (nmtd->set, chip);
 		}
 		cur &= ~info->sel_bit;
 	}
 	writel(cur, info->sel_reg);
 	if (chip == -1)
 		s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
 }
 /* s3c2410_nand_hwcontrol
  *
  * Issue command and address cycles to the chip
 */
 static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd,
 				   unsigned int ctrl)
 {
 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 	if (cmd == NAND_CMD_NONE)
 		return;
 	if (ctrl & NAND_CLE)
 		writeb(cmd, info->regs + S3C2410_NFCMD);
 	else
 		writeb(cmd, info->regs + S3C2410_NFADDR);
 }
 /* command and control functions */
 static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd,
 				   unsigned int ctrl)
 {
 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 	if (cmd == NAND_CMD_NONE)
 		return;
 	if (ctrl & NAND_CLE)
 		writeb(cmd, info->regs + S3C2440_NFCMD);
 	else
 		writeb(cmd, info->regs + S3C2440_NFADDR);
 }
 /* s3c2410_nand_devready()
  *
  * returns 0 if the nand is busy, 1 if it is ready
 */
 static int s3c2410_nand_devready(struct mtd_info *mtd)
 {
 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 	return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
 }
 static int s3c2440_nand_devready(struct mtd_info *mtd)
 {
 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 	return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
 }
 static int s3c2412_nand_devready(struct mtd_info *mtd)
 {
 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 	return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY;
 }
 /* ECC handling functions */
 static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 				     u_char *read_ecc, u_char *calc_ecc)
 {
 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 	unsigned int diff0, diff1, diff2;
 	unsigned int bit, byte;
 	pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc);
 	diff0 = read_ecc[0] ^ calc_ecc[0];
 	diff1 = read_ecc[1] ^ calc_ecc[1];
 	diff2 = read_ecc[2] ^ calc_ecc[2];
-	pr_debug("%s: rd %02x%02x%02x calc %02x%02x%02x diff %02x%02x%02x\n",
+	pr_debug("%s: rd %*phN calc %*phN diff %02x%02x%02x\n",
-		 __func__,
+		 __func__, 3, read_ecc, 3, calc_ecc,
-		 read_ecc[0], read_ecc[1], read_ecc[2],
-		 calc_ecc[0], calc_ecc[1], calc_ecc[2],
 		 diff0, diff1, diff2);
 	if (diff0 == 0 && diff1 == 0 && diff2 == 0)
 		return 0;		/* ECC is ok */
 	/* sometimes people do not think about using the ECC, so check
 	 * to see if we have an 0xff,0xff,0xff read ECC and then ignore
 	 * the error, on the assumption that this is an un-eccd page.
 	 */
 	if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff
 	    && info->platform->ignore_unset_ecc)
 		return 0;
 	/* Can we correct this ECC (ie, one row and column change).
 	 * Note, this is similar to the 256 error code on smartmedia */
 	if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 &&
 	    ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 &&
 	    ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) {
 		/* calculate the bit position of the error */
 		bit  = ((diff2 >> 3) & 1) |
 		       ((diff2 >> 4) & 2) |
 		       ((diff2 >> 5) & 4);
 		/* calculate the byte position of the error */
 		byte = ((diff2 << 7) & 0x100) |
 		       ((diff1 << 0) & 0x80)  |
 		       ((diff1 << 1) & 0x40)  |
 		       ((diff1 << 2) & 0x20)  |
 		       ((diff1 << 3) & 0x10)  |
 		       ((diff0 >> 4) & 0x08)  |
 		       ((diff0 >> 3) & 0x04)  |
 		       ((diff0 >> 2) & 0x02)  |
 		       ((diff0 >> 1) & 0x01);
 		dev_dbg(info->device, "correcting error bit %d, byte %d\n",
 			bit, byte);
 		dat[byte] ^= (1 << bit);
 		return 1;
 	}
 	/* if there is only one bit difference in the ECC, then
 	 * one of only a row or column parity has changed, which
 	 * means the error is most probably in the ECC itself */
 	diff0 |= (diff1 << 8);
 	diff0 |= (diff2 << 16);
 	if ((diff0 & ~(1<<fls(diff0))) == 0)
 		return 1;
 	return -1;
 }
 /* ECC functions
  *
  * These allow the s3c2410 and s3c2440 to use the controller's ECC
  * generator block to ECC the data as it passes through]
 */
 static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 {
 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 	unsigned long ctrl;
 	ctrl = readl(info->regs + S3C2410_NFCONF);
 	ctrl |= S3C2410_NFCONF_INITECC;
 	writel(ctrl, info->regs + S3C2410_NFCONF);
 }
 static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 {
 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 	unsigned long ctrl;
 	ctrl = readl(info->regs + S3C2440_NFCONT);
 	writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC,
 	       info->regs + S3C2440_NFCONT);
 }
 static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 {
 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 	unsigned long ctrl;
 	ctrl = readl(info->regs + S3C2440_NFCONT);
 	writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
 }
 static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 				      u_char *ecc_code)
 {
 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 	ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
 	ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
 	ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
-	pr_debug("%s: returning ecc %02x%02x%02x\n", __func__,
+	pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code);
-		 ecc_code[0], ecc_code[1], ecc_code[2]);
 	return 0;
 }
 static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 				      u_char *ecc_code)
 {
 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 	unsigned long ecc = readl(info->regs + S3C2412_NFMECC0);
 	ecc_code[0] = ecc;
 	ecc_code[1] = ecc >> 8;
 	ecc_code[2] = ecc >> 16;
-	pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n",
+	pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code);
-		 ecc_code[0], ecc_code[1], ecc_code[2]);
 	return 0;
 }
 static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 				      u_char *ecc_code)
 {
 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 	unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
 	ecc_code[0] = ecc;
 	ecc_code[1] = ecc >> 8;
 	ecc_code[2] = ecc >> 16;
 	pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff);
 	return 0;
 }
 /* over-ride the standard functions for a little more speed. We can
  * use read/write block to move the data buffers to/from the controller
 */
 static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 {
 	struct nand_chip *this = mtd->priv;
 	readsb(this->IO_ADDR_R, buf, len);
 }
 static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 {
 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 	readsl(info->regs + S3C2440_NFDATA, buf, len >> 2);
 	/* cleanup if we've got less than a word to do */
 	if (len & 3) {
 		buf += len & ~3;
 		for (; len & 3; len--)
 			*buf++ = readb(info->regs + S3C2440_NFDATA);
 	}
 }
 static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
 				   int len)
 {
 	struct nand_chip *this = mtd->priv;
 	writesb(this->IO_ADDR_W, buf, len);
 }
 static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
 				   int len)
 {
 	struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 	writesl(info->regs + S3C2440_NFDATA, buf, len >> 2);
 	/* cleanup any fractional write */
 	if (len & 3) {
 		buf += len & ~3;
 		for (; len & 3; len--, buf++)
 			writeb(*buf, info->regs + S3C2440_NFDATA);
 	}
 }
 /* cpufreq driver support */
 #ifdef CONFIG_CPU_FREQ
 static int s3c2410_nand_cpufreq_transition(struct notifier_block *nb,
 					  unsigned long val, void *data)
 {
 	struct s3c2410_nand_info *info;
 	unsigned long newclk;
 	info = container_of(nb, struct s3c2410_nand_info, freq_transition);
 	newclk = clk_get_rate(info->clk);
 	if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) ||
 	    (val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) {
 		s3c2410_nand_setrate(info);
 	}
 	return 0;
 }
 static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
 {
 	info->freq_transition.notifier_call = s3c2410_nand_cpufreq_transition;
 	return cpufreq_register_notifier(&info->freq_transition,
 					 CPUFREQ_TRANSITION_NOTIFIER);
 }
 static inline void
 s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
 {
 	cpufreq_unregister_notifier(&info->freq_transition,
 				    CPUFREQ_TRANSITION_NOTIFIER);
 }
 #else
 static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
 {
 	return 0;
 }
 static inline void
 s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
 {
 }
 #endif
 /* device management functions */
 static int s3c24xx_nand_remove(struct platform_device *pdev)
 {
 	struct s3c2410_nand_info *info = to_nand_info(pdev);
 	platform_set_drvdata(pdev, NULL);
 	if (info == NULL)
 		return 0;
 	s3c2410_nand_cpufreq_deregister(info);
 	/* Release all our mtds  and their partitions, then go through
 	 * freeing the resources used
 	 */
 	if (info->mtds != NULL) {
 		struct s3c2410_nand_mtd *ptr = info->mtds;
 		int mtdno;
 		for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
 			pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
 			nand_release(&ptr->mtd);
 		}
 		kfree(info->mtds);
 	}
 	/* free the common resources */
 	if (!IS_ERR(info->clk)) {
 		s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);
 		clk_put(info->clk);
 	}
 	if (info->regs != NULL) {
 		iounmap(info->regs);
 		info->regs = NULL;
 	}
 	if (info->area != NULL) {
 		release_resource(info->area);
 		kfree(info->area);
 		info->area = NULL;
 	}
 	kfree(info);
 	return 0;
 }
 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
 				      struct s3c2410_nand_mtd *mtd,
 				      struct s3c2410_nand_set *set)
 {
 	if (set)
 		mtd->mtd.name = set->name;
 	return mtd_device_parse_register(&mtd->mtd, NULL, NULL,
 					 set->partitions, set->nr_partitions);
 }
 /**
  * s3c2410_nand_init_chip - initialise a single instance of an chip
  * @info: The base NAND controller the chip is on.
  * @nmtd: The new controller MTD instance to fill in.
  * @set: The information passed from the board specific platform data.
  *
  * Initialise the given @nmtd from the information in @info and @set. This
  * readies the structure for use with the MTD layer functions by ensuring
  * all pointers are setup and the necessary control routines selected.
  */
 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
 				   struct s3c2410_nand_mtd *nmtd,
 				   struct s3c2410_nand_set *set)
 {
 	struct nand_chip *chip = &nmtd->chip;
 	void __iomem *regs = info->regs;
 	chip->write_buf    = s3c2410_nand_write_buf;
 	chip->read_buf     = s3c2410_nand_read_buf;
 	chip->select_chip  = s3c2410_nand_select_chip;
 	chip->chip_delay   = 50;
 	chip->priv	   = nmtd;
 	chip->options	   = set->options;
 	chip->controller   = &info->controller;
 	switch (info->cpu_type) {
 	case TYPE_S3C2410:
 		chip->IO_ADDR_W = regs + S3C2410_NFDATA;
 		info->sel_reg   = regs + S3C2410_NFCONF;
 		info->sel_bit	= S3C2410_NFCONF_nFCE;
 		chip->cmd_ctrl  = s3c2410_nand_hwcontrol;
 		chip->dev_ready = s3c2410_nand_devready;
 		break;
 	case TYPE_S3C2440:
 		chip->IO_ADDR_W = regs + S3C2440_NFDATA;
 		info->sel_reg   = regs + S3C2440_NFCONT;
 		info->sel_bit	= S3C2440_NFCONT_nFCE;
 		chip->cmd_ctrl  = s3c2440_nand_hwcontrol;
 		chip->dev_ready = s3c2440_nand_devready;
 		chip->read_buf  = s3c2440_nand_read_buf;
 		chip->write_buf	= s3c2440_nand_write_buf;
 		break;
 	case TYPE_S3C2412:
 		chip->IO_ADDR_W = regs + S3C2440_NFDATA;
 		info->sel_reg   = regs + S3C2440_NFCONT;
 		info->sel_bit	= S3C2412_NFCONT_nFCE0;
 		chip->cmd_ctrl  = s3c2440_nand_hwcontrol;
 		chip->dev_ready = s3c2412_nand_devready;
 		if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT)
 			dev_info(info->device, "System booted from NAND\n");
 		break;
 	}
 	chip->IO_ADDR_R = chip->IO_ADDR_W;
 	nmtd->info	   = info;
 	nmtd->mtd.priv	   = chip;
 	nmtd->mtd.owner    = THIS_MODULE;
 	nmtd->set	   = set;
 #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
 	chip->ecc.calculate = s3c2410_nand_calculate_ecc;
 	chip->ecc.correct   = s3c2410_nand_correct_data;
 	chip->ecc.mode	    = NAND_ECC_HW;
 	chip->ecc.strength  = 1;
 	switch (info->cpu_type) {
 	case TYPE_S3C2410:
 		chip->ecc.hwctl	    = s3c2410_nand_enable_hwecc;
 		chip->ecc.calculate = s3c2410_nand_calculate_ecc;
 		break;
 	case TYPE_S3C2412:
 		chip->ecc.hwctl     = s3c2412_nand_enable_hwecc;
 		chip->ecc.calculate = s3c2412_nand_calculate_ecc;
 		break;
 	case TYPE_S3C2440:
 		chip->ecc.hwctl     = s3c2440_nand_enable_hwecc;
 		chip->ecc.calculate = s3c2440_nand_calculate_ecc;
 		break;
 	}
 #else
 	chip->ecc.mode	    = NAND_ECC_SOFT;
 #endif
 	if (set->ecc_layout != NULL)
 		chip->ecc.layout = set->ecc_layout;
 	if (set->disable_ecc)
 		chip->ecc.mode	= NAND_ECC_NONE;
 	switch (chip->ecc.mode) {
 	case NAND_ECC_NONE:
 		dev_info(info->device, "NAND ECC disabled\n");
 		break;
 	case NAND_ECC_SOFT:
 		dev_info(info->device, "NAND soft ECC\n");
 		break;
 	case NAND_ECC_HW:
 		dev_info(info->device, "NAND hardware ECC\n");
 		break;
 	default:
 		dev_info(info->device, "NAND ECC UNKNOWN\n");
 		break;
 	}
 	/* If you use u-boot BBT creation code, specifying this flag will
 	 * let the kernel fish out the BBT from the NAND, and also skip the
 	 * full NAND scan that can take 1/2s or so. Little things... */
 	if (set->flash_bbt) {
 		chip->bbt_options |= NAND_BBT_USE_FLASH;
 		chip->options |= NAND_SKIP_BBTSCAN;
 	}
 }
 /**
  * s3c2410_nand_update_chip - post probe update
  * @info: The controller instance.
  * @nmtd: The driver version of the MTD instance.
  *
  * This routine is called after the chip probe has successfully completed
  * and the relevant per-chip information updated. This call ensure that
  * we update the internal state accordingly.
  *
  * The internal state is currently limited to the ECC state information.
 */
 static void s3c2410_nand_update_chip(struct s3c2410_nand_info *info,
 				     struct s3c2410_nand_mtd *nmtd)
 {
 	struct nand_chip *chip = &nmtd->chip;
 	dev_dbg(info->device, "chip %p => page shift %d\n",
 		chip, chip->page_shift);
 	if (chip->ecc.mode != NAND_ECC_HW)
 		return;
 		/* change the behaviour depending on wether we are using
 		 * the large or small page nand device */
 	if (chip->page_shift > 10) {
 		chip->ecc.size	    = 256;
 		chip->ecc.bytes	    = 3;
 	} else {
 		chip->ecc.size	    = 512;
 		chip->ecc.bytes	    = 3;
 		chip->ecc.layout    = &nand_hw_eccoob;
 	}
 }
 /* s3c24xx_nand_probe
  *
  * called by device layer when it finds a device matching
  * one our driver can handled. This code checks to see if
  * it can allocate all necessary resources then calls the
  * nand layer to look for devices
 */
 static int s3c24xx_nand_probe(struct platform_device *pdev)
 {
 	struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
 	enum s3c_cpu_type cpu_type;
 	struct s3c2410_nand_info *info;
 	struct s3c2410_nand_mtd *nmtd;
 	struct s3c2410_nand_set *sets;
 	struct resource *res;
 	int err = 0;
 	int size;
 	int nr_sets;
 	int setno;
 	cpu_type = platform_get_device_id(pdev)->driver_data;
 	pr_debug("s3c2410_nand_probe(%p)\n", pdev);
 	info = kzalloc(sizeof(*info), GFP_KERNEL);
 	if (info == NULL) {
 		dev_err(&pdev->dev, "no memory for flash info\n");
 		err = -ENOMEM;
 		goto exit_error;
 	}
 	platform_set_drvdata(pdev, info);
 	spin_lock_init(&info->controller.lock);
 	init_waitqueue_head(&info->controller.wq);
 	/* get the clock source and enable it */
 	info->clk = clk_get(&pdev->dev, "nand");
 	if (IS_ERR(info->clk)) {
 		dev_err(&pdev->dev, "failed to get clock\n");
 		err = -ENOENT;
 		goto exit_error;
 	}
 	s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
 	/* allocate and map the resource */
 	/* currently we assume we have the one resource */
 	res  = pdev->resource;
 	size = resource_size(res);
 	info->area = request_mem_region(res->start, size, pdev->name);
 	if (info->area == NULL) {
 		dev_err(&pdev->dev, "cannot reserve register region\n");
 		err = -ENOENT;
 		goto exit_error;
 	}
 	info->device     = &pdev->dev;
 	info->platform   = plat;
 	info->regs       = ioremap(res->start, size);
 	info->cpu_type   = cpu_type;
 	if (info->regs == NULL) {
 		dev_err(&pdev->dev, "cannot reserve register region\n");
 		err = -EIO;
 		goto exit_error;
 	}
 	dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
 	/* initialise the hardware */
 	err = s3c2410_nand_inithw(info);
 	if (err != 0)
 		goto exit_error;
 	sets = (plat != NULL) ? plat->sets : NULL;
 	nr_sets = (plat != NULL) ? plat->nr_sets : 1;
 	info->mtd_count = nr_sets;
 	/* allocate our information */
 	size = nr_sets * sizeof(*info->mtds);
 	info->mtds = kzalloc(size, GFP_KERNEL);
 	if (info->mtds == NULL) {
 		dev_err(&pdev->dev, "failed to allocate mtd storage\n");
 		err = -ENOMEM;
 		goto exit_error;
 	}
 	/* initialise all possible chips */
 	nmtd = info->mtds;
 	for (setno = 0; setno < nr_sets; setno++, nmtd++) {
 		pr_debug("initialising set %d (%p, info %p)\n",
 			 setno, nmtd, info);
 		s3c2410_nand_init_chip(info, nmtd, sets);
 		nmtd->scan_res = nand_scan_ident(&nmtd->mtd,
 						 (sets) ? sets->nr_chips : 1,
 						 NULL);
 		if (nmtd->scan_res == 0) {
 			s3c2410_nand_update_chip(info, nmtd);
 			nand_scan_tail(&nmtd->mtd);
 			s3c2410_nand_add_partition(info, nmtd, sets);
 		}
 		if (sets != NULL)
 			sets++;
 	}
 	err = s3c2410_nand_cpufreq_register(info);
 	if (err < 0) {
 		dev_err(&pdev->dev, "failed to init cpufreq support\n");
 		goto exit_error;
 	}
 	if (allow_clk_suspend(info)) {
 		dev_info(&pdev->dev, "clock idle support enabled\n");
 		s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
 	}
 	pr_debug("initialised ok\n");
 	return 0;
  exit_error:
 	s3c24xx_nand_remove(pdev);
 	if (err == 0)
 		err = -EINVAL;
 	return err;
 }
 /* PM Support */
 #ifdef CONFIG_PM
 static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
 {
 	struct s3c2410_nand_info *info = platform_get_drvdata(dev);
 	if (info) {
 		info->save_sel = readl(info->sel_reg);
 		/* For the moment, we must ensure nFCE is high during
 		 * the time we are suspended. This really should be
 		 * handled by suspending the MTDs we are using, but
 		 * that is currently not the case. */
 		writel(info->save_sel | info->sel_bit, info->sel_reg);
 		s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);
 	}
 	return 0;
 }
 static int s3c24xx_nand_resume(struct platform_device *dev)
 {
 	struct s3c2410_nand_info *info = platform_get_drvdata(dev);
 	unsigned long sel;
 	if (info) {
 		s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
 		s3c2410_nand_inithw(info);
 		/* Restore the state of the nFCE line. */
 		sel = readl(info->sel_reg);
 		sel &= ~info->sel_bit;
 		sel |= info->save_sel & info->sel_bit;
 		writel(sel, info->sel_reg);
 		s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
 	}
 	return 0;
 }
 #else
 #define s3c24xx_nand_suspend NULL
 #define s3c24xx_nand_resume NULL
 #endif
 /* driver device registration */
 static struct platform_device_id s3c24xx_driver_ids[] = {
 	{
 		.name		= "s3c2410-nand",
 		.driver_data	= TYPE_S3C2410,
 	}, {
 		.name		= "s3c2440-nand",
 		.driver_data	= TYPE_S3C2440,
 	}, {
 		.name		= "s3c2412-nand",
 		.driver_data	= TYPE_S3C2412,
 	}, {
 		.name		= "s3c6400-nand",
 		.driver_data	= TYPE_S3C2412, /* compatible with 2412 */
 	},
 	{ }
 };
 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
 static struct platform_driver s3c24xx_nand_driver = {
 	.probe		= s3c24xx_nand_probe,
 	.remove		= s3c24xx_nand_remove,
 	.suspend	= s3c24xx_nand_suspend,
 	.resume		= s3c24xx_nand_resume,
 	.id_table	= s3c24xx_driver_ids,
 	.driver		= {
 		.name	= "s3c24xx-nand",
 		.owner	= THIS_MODULE,
 	},
 };
 module_platform_driver(s3c24xx_nand_driver);
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
 MODULE_DESCRIPTION("S3C24XX MTD NAND driver");