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Commit 24ffbd62583024f85bdba72cd373d050aa1a1b15

Authored by Bartlomiej Zolnierkiewicz
1 parent 34c69b601b
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

it821x/jmicron: fix return value of {it821x,jmicron}_init_one() 

Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>

Showing 2 changed files with 2 additions and 4 deletions Inline Diff

drivers/ide/pci/it821x.c
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1 1
2 /* 2 /*
3 * linux/drivers/ide/pci/it821x.c Version 0.16 Jul 3 2007 3 * linux/drivers/ide/pci/it821x.c Version 0.16 Jul 3 2007
4 * 4 *
5 * Copyright (C) 2004 Red Hat <alan@redhat.com> 5 * Copyright (C) 2004 Red Hat <alan@redhat.com>
6 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz 6 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
7 * 7 *
8 * May be copied or modified under the terms of the GNU General Public License 8 * May be copied or modified under the terms of the GNU General Public License
9 * Based in part on the ITE vendor provided SCSI driver. 9 * Based in part on the ITE vendor provided SCSI driver.
10 * 10 *
11 * Documentation available from 11 * Documentation available from
12 * http://www.ite.com.tw/pc/IT8212F_V04.pdf 12 * http://www.ite.com.tw/pc/IT8212F_V04.pdf
13 * Some other documents are NDA. 13 * Some other documents are NDA.
14 * 14 *
15 * The ITE8212 isn't exactly a standard IDE controller. It has two 15 * The ITE8212 isn't exactly a standard IDE controller. It has two
16 * modes. In pass through mode then it is an IDE controller. In its smart 16 * modes. In pass through mode then it is an IDE controller. In its smart
17 * mode its actually quite a capable hardware raid controller disguised 17 * mode its actually quite a capable hardware raid controller disguised
18 * as an IDE controller. Smart mode only understands DMA read/write and 18 * as an IDE controller. Smart mode only understands DMA read/write and
19 * identify, none of the fancier commands apply. The IT8211 is identical 19 * identify, none of the fancier commands apply. The IT8211 is identical
20 * in other respects but lacks the raid mode. 20 * in other respects but lacks the raid mode.
21 * 21 *
22 * Errata: 22 * Errata:
23 * o Rev 0x10 also requires master/slave hold the same DMA timings and 23 * o Rev 0x10 also requires master/slave hold the same DMA timings and
24 * cannot do ATAPI MWDMA. 24 * cannot do ATAPI MWDMA.
25 * o The identify data for raid volumes lacks CHS info (technically ok) 25 * o The identify data for raid volumes lacks CHS info (technically ok)
26 * but also fails to set the LBA28 and other bits. We fix these in 26 * but also fails to set the LBA28 and other bits. We fix these in
27 * the IDE probe quirk code. 27 * the IDE probe quirk code.
28 * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode 28 * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode
29 * raid then the controller firmware dies 29 * raid then the controller firmware dies
30 * o Smart mode without RAID doesn't clear all the necessary identify 30 * o Smart mode without RAID doesn't clear all the necessary identify
31 * bits to reduce the command set to the one used 31 * bits to reduce the command set to the one used
32 * 32 *
33 * This has a few impacts on the driver 33 * This has a few impacts on the driver
34 * - In pass through mode we do all the work you would expect 34 * - In pass through mode we do all the work you would expect
35 * - In smart mode the clocking set up is done by the controller generally 35 * - In smart mode the clocking set up is done by the controller generally
36 * but we must watch the other limits and filter. 36 * but we must watch the other limits and filter.
37 * - There are a few extra vendor commands that actually talk to the 37 * - There are a few extra vendor commands that actually talk to the
38 * controller but only work PIO with no IRQ. 38 * controller but only work PIO with no IRQ.
39 * 39 *
40 * Vendor areas of the identify block in smart mode are used for the 40 * Vendor areas of the identify block in smart mode are used for the
41 * timing and policy set up. Each HDD in raid mode also has a serial 41 * timing and policy set up. Each HDD in raid mode also has a serial
42 * block on the disk. The hardware extra commands are get/set chip status, 42 * block on the disk. The hardware extra commands are get/set chip status,
43 * rebuild, get rebuild status. 43 * rebuild, get rebuild status.
44 * 44 *
45 * In Linux the driver supports pass through mode as if the device was 45 * In Linux the driver supports pass through mode as if the device was
46 * just another IDE controller. If the smart mode is running then 46 * just another IDE controller. If the smart mode is running then
47 * volumes are managed by the controller firmware and each IDE "disk" 47 * volumes are managed by the controller firmware and each IDE "disk"
48 * is a raid volume. Even more cute - the controller can do automated 48 * is a raid volume. Even more cute - the controller can do automated
49 * hotplug and rebuild. 49 * hotplug and rebuild.
50 * 50 *
51 * The pass through controller itself is a little demented. It has a 51 * The pass through controller itself is a little demented. It has a
52 * flaw that it has a single set of PIO/MWDMA timings per channel so 52 * flaw that it has a single set of PIO/MWDMA timings per channel so
53 * non UDMA devices restrict each others performance. It also has a 53 * non UDMA devices restrict each others performance. It also has a
54 * single clock source per channel so mixed UDMA100/133 performance 54 * single clock source per channel so mixed UDMA100/133 performance
55 * isn't perfect and we have to pick a clock. Thankfully none of this 55 * isn't perfect and we have to pick a clock. Thankfully none of this
56 * matters in smart mode. ATAPI DMA is not currently supported. 56 * matters in smart mode. ATAPI DMA is not currently supported.
57 * 57 *
58 * It seems the smart mode is a win for RAID1/RAID10 but otherwise not. 58 * It seems the smart mode is a win for RAID1/RAID10 but otherwise not.
59 * 59 *
60 * TODO 60 * TODO
61 * - ATAPI UDMA is ok but not MWDMA it seems 61 * - ATAPI UDMA is ok but not MWDMA it seems
62 * - RAID configuration ioctls 62 * - RAID configuration ioctls
63 * - Move to libata once it grows up 63 * - Move to libata once it grows up
64 */ 64 */
65 65
66 #include <linux/types.h> 66 #include <linux/types.h>
67 #include <linux/module.h> 67 #include <linux/module.h>
68 #include <linux/pci.h> 68 #include <linux/pci.h>
69 #include <linux/delay.h> 69 #include <linux/delay.h>
70 #include <linux/hdreg.h> 70 #include <linux/hdreg.h>
71 #include <linux/ide.h> 71 #include <linux/ide.h>
72 #include <linux/init.h> 72 #include <linux/init.h>
73 73
74 #include <asm/io.h> 74 #include <asm/io.h>
75 75
76 struct it821x_dev 76 struct it821x_dev
77 { 77 {
78 unsigned int smart:1, /* Are we in smart raid mode */ 78 unsigned int smart:1, /* Are we in smart raid mode */
79 timing10:1; /* Rev 0x10 */ 79 timing10:1; /* Rev 0x10 */
80 u8 clock_mode; /* 0, ATA_50 or ATA_66 */ 80 u8 clock_mode; /* 0, ATA_50 or ATA_66 */
81 u8 want[2][2]; /* Mode/Pri log for master slave */ 81 u8 want[2][2]; /* Mode/Pri log for master slave */
82 /* We need these for switching the clock when DMA goes on/off 82 /* We need these for switching the clock when DMA goes on/off
83 The high byte is the 66Mhz timing */ 83 The high byte is the 66Mhz timing */
84 u16 pio[2]; /* Cached PIO values */ 84 u16 pio[2]; /* Cached PIO values */
85 u16 mwdma[2]; /* Cached MWDMA values */ 85 u16 mwdma[2]; /* Cached MWDMA values */
86 u16 udma[2]; /* Cached UDMA values (per drive) */ 86 u16 udma[2]; /* Cached UDMA values (per drive) */
87 }; 87 };
88 88
89 #define ATA_66 0 89 #define ATA_66 0
90 #define ATA_50 1 90 #define ATA_50 1
91 #define ATA_ANY 2 91 #define ATA_ANY 2
92 92
93 #define UDMA_OFF 0 93 #define UDMA_OFF 0
94 #define MWDMA_OFF 0 94 #define MWDMA_OFF 0
95 95
96 /* 96 /*
97 * We allow users to force the card into non raid mode without 97 * We allow users to force the card into non raid mode without
98 * flashing the alternative BIOS. This is also necessary right now 98 * flashing the alternative BIOS. This is also necessary right now
99 * for embedded platforms that cannot run a PC BIOS but are using this 99 * for embedded platforms that cannot run a PC BIOS but are using this
100 * device. 100 * device.
101 */ 101 */
102 102
103 static int it8212_noraid; 103 static int it8212_noraid;
104 104
105 /** 105 /**
106 * it821x_program - program the PIO/MWDMA registers 106 * it821x_program - program the PIO/MWDMA registers
107 * @drive: drive to tune 107 * @drive: drive to tune
108 * @timing: timing info 108 * @timing: timing info
109 * 109 *
110 * Program the PIO/MWDMA timing for this channel according to the 110 * Program the PIO/MWDMA timing for this channel according to the
111 * current clock. 111 * current clock.
112 */ 112 */
113 113
114 static void it821x_program(ide_drive_t *drive, u16 timing) 114 static void it821x_program(ide_drive_t *drive, u16 timing)
115 { 115 {
116 ide_hwif_t *hwif = drive->hwif; 116 ide_hwif_t *hwif = drive->hwif;
117 struct it821x_dev *itdev = ide_get_hwifdata(hwif); 117 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
118 int channel = hwif->channel; 118 int channel = hwif->channel;
119 u8 conf; 119 u8 conf;
120 120
121 /* Program PIO/MWDMA timing bits */ 121 /* Program PIO/MWDMA timing bits */
122 if(itdev->clock_mode == ATA_66) 122 if(itdev->clock_mode == ATA_66)
123 conf = timing >> 8; 123 conf = timing >> 8;
124 else 124 else
125 conf = timing & 0xFF; 125 conf = timing & 0xFF;
126 pci_write_config_byte(hwif->pci_dev, 0x54 + 4 * channel, conf); 126 pci_write_config_byte(hwif->pci_dev, 0x54 + 4 * channel, conf);
127 } 127 }
128 128
129 /** 129 /**
130 * it821x_program_udma - program the UDMA registers 130 * it821x_program_udma - program the UDMA registers
131 * @drive: drive to tune 131 * @drive: drive to tune
132 * @timing: timing info 132 * @timing: timing info
133 * 133 *
134 * Program the UDMA timing for this drive according to the 134 * Program the UDMA timing for this drive according to the
135 * current clock. 135 * current clock.
136 */ 136 */
137 137
138 static void it821x_program_udma(ide_drive_t *drive, u16 timing) 138 static void it821x_program_udma(ide_drive_t *drive, u16 timing)
139 { 139 {
140 ide_hwif_t *hwif = drive->hwif; 140 ide_hwif_t *hwif = drive->hwif;
141 struct it821x_dev *itdev = ide_get_hwifdata(hwif); 141 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
142 int channel = hwif->channel; 142 int channel = hwif->channel;
143 int unit = drive->select.b.unit; 143 int unit = drive->select.b.unit;
144 u8 conf; 144 u8 conf;
145 145
146 /* Program UDMA timing bits */ 146 /* Program UDMA timing bits */
147 if(itdev->clock_mode == ATA_66) 147 if(itdev->clock_mode == ATA_66)
148 conf = timing >> 8; 148 conf = timing >> 8;
149 else 149 else
150 conf = timing & 0xFF; 150 conf = timing & 0xFF;
151 if(itdev->timing10 == 0) 151 if(itdev->timing10 == 0)
152 pci_write_config_byte(hwif->pci_dev, 0x56 + 4 * channel + unit, conf); 152 pci_write_config_byte(hwif->pci_dev, 0x56 + 4 * channel + unit, conf);
153 else { 153 else {
154 pci_write_config_byte(hwif->pci_dev, 0x56 + 4 * channel, conf); 154 pci_write_config_byte(hwif->pci_dev, 0x56 + 4 * channel, conf);
155 pci_write_config_byte(hwif->pci_dev, 0x56 + 4 * channel + 1, conf); 155 pci_write_config_byte(hwif->pci_dev, 0x56 + 4 * channel + 1, conf);
156 } 156 }
157 } 157 }
158 158
159 /** 159 /**
160 * it821x_clock_strategy 160 * it821x_clock_strategy
161 * @drive: drive to set up 161 * @drive: drive to set up
162 * 162 *
163 * Select between the 50 and 66Mhz base clocks to get the best 163 * Select between the 50 and 66Mhz base clocks to get the best
164 * results for this interface. 164 * results for this interface.
165 */ 165 */
166 166
167 static void it821x_clock_strategy(ide_drive_t *drive) 167 static void it821x_clock_strategy(ide_drive_t *drive)
168 { 168 {
169 ide_hwif_t *hwif = drive->hwif; 169 ide_hwif_t *hwif = drive->hwif;
170 struct it821x_dev *itdev = ide_get_hwifdata(hwif); 170 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
171 171
172 u8 unit = drive->select.b.unit; 172 u8 unit = drive->select.b.unit;
173 ide_drive_t *pair = &hwif->drives[1-unit]; 173 ide_drive_t *pair = &hwif->drives[1-unit];
174 174
175 int clock, altclock; 175 int clock, altclock;
176 u8 v; 176 u8 v;
177 int sel = 0; 177 int sel = 0;
178 178
179 if(itdev->want[0][0] > itdev->want[1][0]) { 179 if(itdev->want[0][0] > itdev->want[1][0]) {
180 clock = itdev->want[0][1]; 180 clock = itdev->want[0][1];
181 altclock = itdev->want[1][1]; 181 altclock = itdev->want[1][1];
182 } else { 182 } else {
183 clock = itdev->want[1][1]; 183 clock = itdev->want[1][1];
184 altclock = itdev->want[0][1]; 184 altclock = itdev->want[0][1];
185 } 185 }
186 186
187 /* 187 /*
188 * if both clocks can be used for the mode with the higher priority 188 * if both clocks can be used for the mode with the higher priority
189 * use the clock needed by the mode with the lower priority 189 * use the clock needed by the mode with the lower priority
190 */ 190 */
191 if (clock == ATA_ANY) 191 if (clock == ATA_ANY)
192 clock = altclock; 192 clock = altclock;
193 193
194 /* Nobody cares - keep the same clock */ 194 /* Nobody cares - keep the same clock */
195 if(clock == ATA_ANY) 195 if(clock == ATA_ANY)
196 return; 196 return;
197 /* No change */ 197 /* No change */
198 if(clock == itdev->clock_mode) 198 if(clock == itdev->clock_mode)
199 return; 199 return;
200 200
201 /* Load this into the controller ? */ 201 /* Load this into the controller ? */
202 if(clock == ATA_66) 202 if(clock == ATA_66)
203 itdev->clock_mode = ATA_66; 203 itdev->clock_mode = ATA_66;
204 else { 204 else {
205 itdev->clock_mode = ATA_50; 205 itdev->clock_mode = ATA_50;
206 sel = 1; 206 sel = 1;
207 } 207 }
208 pci_read_config_byte(hwif->pci_dev, 0x50, &v); 208 pci_read_config_byte(hwif->pci_dev, 0x50, &v);
209 v &= ~(1 << (1 + hwif->channel)); 209 v &= ~(1 << (1 + hwif->channel));
210 v |= sel << (1 + hwif->channel); 210 v |= sel << (1 + hwif->channel);
211 pci_write_config_byte(hwif->pci_dev, 0x50, v); 211 pci_write_config_byte(hwif->pci_dev, 0x50, v);
212 212
213 /* 213 /*
214 * Reprogram the UDMA/PIO of the pair drive for the switch 214 * Reprogram the UDMA/PIO of the pair drive for the switch
215 * MWDMA will be dealt with by the dma switcher 215 * MWDMA will be dealt with by the dma switcher
216 */ 216 */
217 if(pair && itdev->udma[1-unit] != UDMA_OFF) { 217 if(pair && itdev->udma[1-unit] != UDMA_OFF) {
218 it821x_program_udma(pair, itdev->udma[1-unit]); 218 it821x_program_udma(pair, itdev->udma[1-unit]);
219 it821x_program(pair, itdev->pio[1-unit]); 219 it821x_program(pair, itdev->pio[1-unit]);
220 } 220 }
221 /* 221 /*
222 * Reprogram the UDMA/PIO of our drive for the switch. 222 * Reprogram the UDMA/PIO of our drive for the switch.
223 * MWDMA will be dealt with by the dma switcher 223 * MWDMA will be dealt with by the dma switcher
224 */ 224 */
225 if(itdev->udma[unit] != UDMA_OFF) { 225 if(itdev->udma[unit] != UDMA_OFF) {
226 it821x_program_udma(drive, itdev->udma[unit]); 226 it821x_program_udma(drive, itdev->udma[unit]);
227 it821x_program(drive, itdev->pio[unit]); 227 it821x_program(drive, itdev->pio[unit]);
228 } 228 }
229 } 229 }
230 230
231 /** 231 /**
232 * it821x_set_pio_mode - set host controller for PIO mode 232 * it821x_set_pio_mode - set host controller for PIO mode
233 * @drive: drive 233 * @drive: drive
234 * @pio: PIO mode number 234 * @pio: PIO mode number
235 * 235 *
236 * Tune the host to the desired PIO mode taking into the consideration 236 * Tune the host to the desired PIO mode taking into the consideration
237 * the maximum PIO mode supported by the other device on the cable. 237 * the maximum PIO mode supported by the other device on the cable.
238 */ 238 */
239 239
240 static void it821x_set_pio_mode(ide_drive_t *drive, const u8 pio) 240 static void it821x_set_pio_mode(ide_drive_t *drive, const u8 pio)
241 { 241 {
242 ide_hwif_t *hwif = drive->hwif; 242 ide_hwif_t *hwif = drive->hwif;
243 struct it821x_dev *itdev = ide_get_hwifdata(hwif); 243 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
244 int unit = drive->select.b.unit; 244 int unit = drive->select.b.unit;
245 ide_drive_t *pair = &hwif->drives[1 - unit]; 245 ide_drive_t *pair = &hwif->drives[1 - unit];
246 u8 set_pio = pio; 246 u8 set_pio = pio;
247 247
248 /* Spec says 89 ref driver uses 88 */ 248 /* Spec says 89 ref driver uses 88 */
249 static u16 pio_timings[]= { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 }; 249 static u16 pio_timings[]= { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 };
250 static u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY }; 250 static u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY };
251 251
252 /* 252 /*
253 * Compute the best PIO mode we can for a given device. We must 253 * Compute the best PIO mode we can for a given device. We must
254 * pick a speed that does not cause problems with the other device 254 * pick a speed that does not cause problems with the other device
255 * on the cable. 255 * on the cable.
256 */ 256 */
257 if (pair) { 257 if (pair) {
258 u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4); 258 u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4);
259 /* trim PIO to the slowest of the master/slave */ 259 /* trim PIO to the slowest of the master/slave */
260 if (pair_pio < set_pio) 260 if (pair_pio < set_pio)
261 set_pio = pair_pio; 261 set_pio = pair_pio;
262 } 262 }
263 263
264 /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */ 264 /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */
265 itdev->want[unit][1] = pio_want[set_pio]; 265 itdev->want[unit][1] = pio_want[set_pio];
266 itdev->want[unit][0] = 1; /* PIO is lowest priority */ 266 itdev->want[unit][0] = 1; /* PIO is lowest priority */
267 itdev->pio[unit] = pio_timings[set_pio]; 267 itdev->pio[unit] = pio_timings[set_pio];
268 it821x_clock_strategy(drive); 268 it821x_clock_strategy(drive);
269 it821x_program(drive, itdev->pio[unit]); 269 it821x_program(drive, itdev->pio[unit]);
270 } 270 }
271 271
272 /** 272 /**
273 * it821x_tune_mwdma - tune a channel for MWDMA 273 * it821x_tune_mwdma - tune a channel for MWDMA
274 * @drive: drive to set up 274 * @drive: drive to set up
275 * @mode_wanted: the target operating mode 275 * @mode_wanted: the target operating mode
276 * 276 *
277 * Load the timing settings for this device mode into the 277 * Load the timing settings for this device mode into the
278 * controller when doing MWDMA in pass through mode. The caller 278 * controller when doing MWDMA in pass through mode. The caller
279 * must manage the whole lack of per device MWDMA/PIO timings and 279 * must manage the whole lack of per device MWDMA/PIO timings and
280 * the shared MWDMA/PIO timing register. 280 * the shared MWDMA/PIO timing register.
281 */ 281 */
282 282
283 static void it821x_tune_mwdma (ide_drive_t *drive, byte mode_wanted) 283 static void it821x_tune_mwdma (ide_drive_t *drive, byte mode_wanted)
284 { 284 {
285 ide_hwif_t *hwif = drive->hwif; 285 ide_hwif_t *hwif = drive->hwif;
286 struct it821x_dev *itdev = (void *)ide_get_hwifdata(hwif); 286 struct it821x_dev *itdev = (void *)ide_get_hwifdata(hwif);
287 int unit = drive->select.b.unit; 287 int unit = drive->select.b.unit;
288 int channel = hwif->channel; 288 int channel = hwif->channel;
289 u8 conf; 289 u8 conf;
290 290
291 static u16 dma[] = { 0x8866, 0x3222, 0x3121 }; 291 static u16 dma[] = { 0x8866, 0x3222, 0x3121 };
292 static u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY }; 292 static u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY };
293 293
294 itdev->want[unit][1] = mwdma_want[mode_wanted]; 294 itdev->want[unit][1] = mwdma_want[mode_wanted];
295 itdev->want[unit][0] = 2; /* MWDMA is low priority */ 295 itdev->want[unit][0] = 2; /* MWDMA is low priority */
296 itdev->mwdma[unit] = dma[mode_wanted]; 296 itdev->mwdma[unit] = dma[mode_wanted];
297 itdev->udma[unit] = UDMA_OFF; 297 itdev->udma[unit] = UDMA_OFF;
298 298
299 /* UDMA bits off - Revision 0x10 do them in pairs */ 299 /* UDMA bits off - Revision 0x10 do them in pairs */
300 pci_read_config_byte(hwif->pci_dev, 0x50, &conf); 300 pci_read_config_byte(hwif->pci_dev, 0x50, &conf);
301 if(itdev->timing10) 301 if(itdev->timing10)
302 conf |= channel ? 0x60: 0x18; 302 conf |= channel ? 0x60: 0x18;
303 else 303 else
304 conf |= 1 << (3 + 2 * channel + unit); 304 conf |= 1 << (3 + 2 * channel + unit);
305 pci_write_config_byte(hwif->pci_dev, 0x50, conf); 305 pci_write_config_byte(hwif->pci_dev, 0x50, conf);
306 306
307 it821x_clock_strategy(drive); 307 it821x_clock_strategy(drive);
308 /* FIXME: do we need to program this ? */ 308 /* FIXME: do we need to program this ? */
309 /* it821x_program(drive, itdev->mwdma[unit]); */ 309 /* it821x_program(drive, itdev->mwdma[unit]); */
310 } 310 }
311 311
312 /** 312 /**
313 * it821x_tune_udma - tune a channel for UDMA 313 * it821x_tune_udma - tune a channel for UDMA
314 * @drive: drive to set up 314 * @drive: drive to set up
315 * @mode_wanted: the target operating mode 315 * @mode_wanted: the target operating mode
316 * 316 *
317 * Load the timing settings for this device mode into the 317 * Load the timing settings for this device mode into the
318 * controller when doing UDMA modes in pass through. 318 * controller when doing UDMA modes in pass through.
319 */ 319 */
320 320
321 static void it821x_tune_udma (ide_drive_t *drive, byte mode_wanted) 321 static void it821x_tune_udma (ide_drive_t *drive, byte mode_wanted)
322 { 322 {
323 ide_hwif_t *hwif = drive->hwif; 323 ide_hwif_t *hwif = drive->hwif;
324 struct it821x_dev *itdev = ide_get_hwifdata(hwif); 324 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
325 int unit = drive->select.b.unit; 325 int unit = drive->select.b.unit;
326 int channel = hwif->channel; 326 int channel = hwif->channel;
327 u8 conf; 327 u8 conf;
328 328
329 static u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 }; 329 static u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 };
330 static u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 }; 330 static u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 };
331 331
332 itdev->want[unit][1] = udma_want[mode_wanted]; 332 itdev->want[unit][1] = udma_want[mode_wanted];
333 itdev->want[unit][0] = 3; /* UDMA is high priority */ 333 itdev->want[unit][0] = 3; /* UDMA is high priority */
334 itdev->mwdma[unit] = MWDMA_OFF; 334 itdev->mwdma[unit] = MWDMA_OFF;
335 itdev->udma[unit] = udma[mode_wanted]; 335 itdev->udma[unit] = udma[mode_wanted];
336 if(mode_wanted >= 5) 336 if(mode_wanted >= 5)
337 itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */ 337 itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */
338 338
339 /* UDMA on. Again revision 0x10 must do the pair */ 339 /* UDMA on. Again revision 0x10 must do the pair */
340 pci_read_config_byte(hwif->pci_dev, 0x50, &conf); 340 pci_read_config_byte(hwif->pci_dev, 0x50, &conf);
341 if(itdev->timing10) 341 if(itdev->timing10)
342 conf &= channel ? 0x9F: 0xE7; 342 conf &= channel ? 0x9F: 0xE7;
343 else 343 else
344 conf &= ~ (1 << (3 + 2 * channel + unit)); 344 conf &= ~ (1 << (3 + 2 * channel + unit));
345 pci_write_config_byte(hwif->pci_dev, 0x50, conf); 345 pci_write_config_byte(hwif->pci_dev, 0x50, conf);
346 346
347 it821x_clock_strategy(drive); 347 it821x_clock_strategy(drive);
348 it821x_program_udma(drive, itdev->udma[unit]); 348 it821x_program_udma(drive, itdev->udma[unit]);
349 349
350 } 350 }
351 351
352 /** 352 /**
353 * it821x_dma_read - DMA hook 353 * it821x_dma_read - DMA hook
354 * @drive: drive for DMA 354 * @drive: drive for DMA
355 * 355 *
356 * The IT821x has a single timing register for MWDMA and for PIO 356 * The IT821x has a single timing register for MWDMA and for PIO
357 * operations. As we flip back and forth we have to reload the 357 * operations. As we flip back and forth we have to reload the
358 * clock. In addition the rev 0x10 device only works if the same 358 * clock. In addition the rev 0x10 device only works if the same
359 * timing value is loaded into the master and slave UDMA clock 359 * timing value is loaded into the master and slave UDMA clock
360 * so we must also reload that. 360 * so we must also reload that.
361 * 361 *
362 * FIXME: we could figure out in advance if we need to do reloads 362 * FIXME: we could figure out in advance if we need to do reloads
363 */ 363 */
364 364
365 static void it821x_dma_start(ide_drive_t *drive) 365 static void it821x_dma_start(ide_drive_t *drive)
366 { 366 {
367 ide_hwif_t *hwif = drive->hwif; 367 ide_hwif_t *hwif = drive->hwif;
368 struct it821x_dev *itdev = ide_get_hwifdata(hwif); 368 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
369 int unit = drive->select.b.unit; 369 int unit = drive->select.b.unit;
370 if(itdev->mwdma[unit] != MWDMA_OFF) 370 if(itdev->mwdma[unit] != MWDMA_OFF)
371 it821x_program(drive, itdev->mwdma[unit]); 371 it821x_program(drive, itdev->mwdma[unit]);
372 else if(itdev->udma[unit] != UDMA_OFF && itdev->timing10) 372 else if(itdev->udma[unit] != UDMA_OFF && itdev->timing10)
373 it821x_program_udma(drive, itdev->udma[unit]); 373 it821x_program_udma(drive, itdev->udma[unit]);
374 ide_dma_start(drive); 374 ide_dma_start(drive);
375 } 375 }
376 376
377 /** 377 /**
378 * it821x_dma_write - DMA hook 378 * it821x_dma_write - DMA hook
379 * @drive: drive for DMA stop 379 * @drive: drive for DMA stop
380 * 380 *
381 * The IT821x has a single timing register for MWDMA and for PIO 381 * The IT821x has a single timing register for MWDMA and for PIO
382 * operations. As we flip back and forth we have to reload the 382 * operations. As we flip back and forth we have to reload the
383 * clock. 383 * clock.
384 */ 384 */
385 385
386 static int it821x_dma_end(ide_drive_t *drive) 386 static int it821x_dma_end(ide_drive_t *drive)
387 { 387 {
388 ide_hwif_t *hwif = drive->hwif; 388 ide_hwif_t *hwif = drive->hwif;
389 int unit = drive->select.b.unit; 389 int unit = drive->select.b.unit;
390 struct it821x_dev *itdev = ide_get_hwifdata(hwif); 390 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
391 int ret = __ide_dma_end(drive); 391 int ret = __ide_dma_end(drive);
392 if(itdev->mwdma[unit] != MWDMA_OFF) 392 if(itdev->mwdma[unit] != MWDMA_OFF)
393 it821x_program(drive, itdev->pio[unit]); 393 it821x_program(drive, itdev->pio[unit]);
394 return ret; 394 return ret;
395 } 395 }
396 396
397 /** 397 /**
398 * it821x_set_dma_mode - set host controller for DMA mode 398 * it821x_set_dma_mode - set host controller for DMA mode
399 * @drive: drive 399 * @drive: drive
400 * @speed: DMA mode 400 * @speed: DMA mode
401 * 401 *
402 * Tune the ITE chipset for the desired DMA mode. 402 * Tune the ITE chipset for the desired DMA mode.
403 */ 403 */
404 404
405 static void it821x_set_dma_mode(ide_drive_t *drive, const u8 speed) 405 static void it821x_set_dma_mode(ide_drive_t *drive, const u8 speed)
406 { 406 {
407 /* 407 /*
408 * MWDMA tuning is really hard because our MWDMA and PIO 408 * MWDMA tuning is really hard because our MWDMA and PIO
409 * timings are kept in the same place. We can switch in the 409 * timings are kept in the same place. We can switch in the
410 * host dma on/off callbacks. 410 * host dma on/off callbacks.
411 */ 411 */
412 if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_6) 412 if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_6)
413 it821x_tune_udma(drive, speed - XFER_UDMA_0); 413 it821x_tune_udma(drive, speed - XFER_UDMA_0);
414 else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) 414 else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
415 it821x_tune_mwdma(drive, speed - XFER_MW_DMA_0); 415 it821x_tune_mwdma(drive, speed - XFER_MW_DMA_0);
416 } 416 }
417 417
418 /** 418 /**
419 * ata66_it821x - check for 80 pin cable 419 * ata66_it821x - check for 80 pin cable
420 * @hwif: interface to check 420 * @hwif: interface to check
421 * 421 *
422 * Check for the presence of an ATA66 capable cable on the 422 * Check for the presence of an ATA66 capable cable on the
423 * interface. Problematic as it seems some cards don't have 423 * interface. Problematic as it seems some cards don't have
424 * the needed logic onboard. 424 * the needed logic onboard.
425 */ 425 */
426 426
427 static u8 __devinit ata66_it821x(ide_hwif_t *hwif) 427 static u8 __devinit ata66_it821x(ide_hwif_t *hwif)
428 { 428 {
429 /* The reference driver also only does disk side */ 429 /* The reference driver also only does disk side */
430 return ATA_CBL_PATA80; 430 return ATA_CBL_PATA80;
431 } 431 }
432 432
433 /** 433 /**
434 * it821x_fixup - post init callback 434 * it821x_fixup - post init callback
435 * @hwif: interface 435 * @hwif: interface
436 * 436 *
437 * This callback is run after the drives have been probed but 437 * This callback is run after the drives have been probed but
438 * before anything gets attached. It allows drivers to do any 438 * before anything gets attached. It allows drivers to do any
439 * final tuning that is needed, or fixups to work around bugs. 439 * final tuning that is needed, or fixups to work around bugs.
440 */ 440 */
441 441
442 static void __devinit it821x_fixups(ide_hwif_t *hwif) 442 static void __devinit it821x_fixups(ide_hwif_t *hwif)
443 { 443 {
444 struct it821x_dev *itdev = ide_get_hwifdata(hwif); 444 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
445 int i; 445 int i;
446 446
447 if(!itdev->smart) { 447 if(!itdev->smart) {
448 /* 448 /*
449 * If we are in pass through mode then not much 449 * If we are in pass through mode then not much
450 * needs to be done, but we do bother to clear the 450 * needs to be done, but we do bother to clear the
451 * IRQ mask as we may well be in PIO (eg rev 0x10) 451 * IRQ mask as we may well be in PIO (eg rev 0x10)
452 * for now and we know unmasking is safe on this chipset. 452 * for now and we know unmasking is safe on this chipset.
453 */ 453 */
454 for (i = 0; i < 2; i++) { 454 for (i = 0; i < 2; i++) {
455 ide_drive_t *drive = &hwif->drives[i]; 455 ide_drive_t *drive = &hwif->drives[i];
456 if(drive->present) 456 if(drive->present)
457 drive->unmask = 1; 457 drive->unmask = 1;
458 } 458 }
459 return; 459 return;
460 } 460 }
461 /* 461 /*
462 * Perform fixups on smart mode. We need to "lose" some 462 * Perform fixups on smart mode. We need to "lose" some
463 * capabilities the firmware lacks but does not filter, and 463 * capabilities the firmware lacks but does not filter, and
464 * also patch up some capability bits that it forgets to set 464 * also patch up some capability bits that it forgets to set
465 * in RAID mode. 465 * in RAID mode.
466 */ 466 */
467 467
468 for(i = 0; i < 2; i++) { 468 for(i = 0; i < 2; i++) {
469 ide_drive_t *drive = &hwif->drives[i]; 469 ide_drive_t *drive = &hwif->drives[i];
470 struct hd_driveid *id; 470 struct hd_driveid *id;
471 u16 *idbits; 471 u16 *idbits;
472 472
473 if(!drive->present) 473 if(!drive->present)
474 continue; 474 continue;
475 id = drive->id; 475 id = drive->id;
476 idbits = (u16 *)drive->id; 476 idbits = (u16 *)drive->id;
477 477
478 /* Check for RAID v native */ 478 /* Check for RAID v native */
479 if(strstr(id->model, "Integrated Technology Express")) { 479 if(strstr(id->model, "Integrated Technology Express")) {
480 /* In raid mode the ident block is slightly buggy 480 /* In raid mode the ident block is slightly buggy
481 We need to set the bits so that the IDE layer knows 481 We need to set the bits so that the IDE layer knows
482 LBA28. LBA48 and DMA ar valid */ 482 LBA28. LBA48 and DMA ar valid */
483 id->capability |= 3; /* LBA28, DMA */ 483 id->capability |= 3; /* LBA28, DMA */
484 id->command_set_2 |= 0x0400; /* LBA48 valid */ 484 id->command_set_2 |= 0x0400; /* LBA48 valid */
485 id->cfs_enable_2 |= 0x0400; /* LBA48 on */ 485 id->cfs_enable_2 |= 0x0400; /* LBA48 on */
486 /* Reporting logic */ 486 /* Reporting logic */
487 printk(KERN_INFO "%s: IT8212 %sRAID %d volume", 487 printk(KERN_INFO "%s: IT8212 %sRAID %d volume",
488 drive->name, 488 drive->name,
489 idbits[147] ? "Bootable ":"", 489 idbits[147] ? "Bootable ":"",
490 idbits[129]); 490 idbits[129]);
491 if(idbits[129] != 1) 491 if(idbits[129] != 1)
492 printk("(%dK stripe)", idbits[146]); 492 printk("(%dK stripe)", idbits[146]);
493 printk(".\n"); 493 printk(".\n");
494 } else { 494 } else {
495 /* Non RAID volume. Fixups to stop the core code 495 /* Non RAID volume. Fixups to stop the core code
496 doing unsupported things */ 496 doing unsupported things */
497 id->field_valid &= 3; 497 id->field_valid &= 3;
498 id->queue_depth = 0; 498 id->queue_depth = 0;
499 id->command_set_1 = 0; 499 id->command_set_1 = 0;
500 id->command_set_2 &= 0xC400; 500 id->command_set_2 &= 0xC400;
501 id->cfsse &= 0xC000; 501 id->cfsse &= 0xC000;
502 id->cfs_enable_1 = 0; 502 id->cfs_enable_1 = 0;
503 id->cfs_enable_2 &= 0xC400; 503 id->cfs_enable_2 &= 0xC400;
504 id->csf_default &= 0xC000; 504 id->csf_default &= 0xC000;
505 id->word127 = 0; 505 id->word127 = 0;
506 id->dlf = 0; 506 id->dlf = 0;
507 id->csfo = 0; 507 id->csfo = 0;
508 id->cfa_power = 0; 508 id->cfa_power = 0;
509 printk(KERN_INFO "%s: Performing identify fixups.\n", 509 printk(KERN_INFO "%s: Performing identify fixups.\n",
510 drive->name); 510 drive->name);
511 } 511 }
512 512
513 /* 513 /*
514 * Set MWDMA0 mode as enabled/support - just to tell 514 * Set MWDMA0 mode as enabled/support - just to tell
515 * IDE core that DMA is supported (it821x hardware 515 * IDE core that DMA is supported (it821x hardware
516 * takes care of DMA mode programming). 516 * takes care of DMA mode programming).
517 */ 517 */
518 if (id->capability & 1) { 518 if (id->capability & 1) {
519 id->dma_mword |= 0x0101; 519 id->dma_mword |= 0x0101;
520 drive->current_speed = XFER_MW_DMA_0; 520 drive->current_speed = XFER_MW_DMA_0;
521 } 521 }
522 } 522 }
523 523
524 } 524 }
525 525
526 /** 526 /**
527 * init_hwif_it821x - set up hwif structs 527 * init_hwif_it821x - set up hwif structs
528 * @hwif: interface to set up 528 * @hwif: interface to set up
529 * 529 *
530 * We do the basic set up of the interface structure. The IT8212 530 * We do the basic set up of the interface structure. The IT8212
531 * requires several custom handlers so we override the default 531 * requires several custom handlers so we override the default
532 * ide DMA handlers appropriately 532 * ide DMA handlers appropriately
533 */ 533 */
534 534
535 static void __devinit init_hwif_it821x(ide_hwif_t *hwif) 535 static void __devinit init_hwif_it821x(ide_hwif_t *hwif)
536 { 536 {
537 struct it821x_dev *idev = kzalloc(sizeof(struct it821x_dev), GFP_KERNEL); 537 struct it821x_dev *idev = kzalloc(sizeof(struct it821x_dev), GFP_KERNEL);
538 u8 conf; 538 u8 conf;
539 539
540 if (idev == NULL) { 540 if (idev == NULL) {
541 printk(KERN_ERR "it821x: out of memory, falling back to legacy behaviour.\n"); 541 printk(KERN_ERR "it821x: out of memory, falling back to legacy behaviour.\n");
542 return; 542 return;
543 } 543 }
544 544
545 ide_set_hwifdata(hwif, idev); 545 ide_set_hwifdata(hwif, idev);
546 546
547 pci_read_config_byte(hwif->pci_dev, 0x50, &conf); 547 pci_read_config_byte(hwif->pci_dev, 0x50, &conf);
548 if (conf & 1) { 548 if (conf & 1) {
549 idev->smart = 1; 549 idev->smart = 1;
550 hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA; 550 hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
551 /* Long I/O's although allowed in LBA48 space cause the 551 /* Long I/O's although allowed in LBA48 space cause the
552 onboard firmware to enter the twighlight zone */ 552 onboard firmware to enter the twighlight zone */
553 hwif->rqsize = 256; 553 hwif->rqsize = 256;
554 } 554 }
555 555
556 /* Pull the current clocks from 0x50 also */ 556 /* Pull the current clocks from 0x50 also */
557 if (conf & (1 << (1 + hwif->channel))) 557 if (conf & (1 << (1 + hwif->channel)))
558 idev->clock_mode = ATA_50; 558 idev->clock_mode = ATA_50;
559 else 559 else
560 idev->clock_mode = ATA_66; 560 idev->clock_mode = ATA_66;
561 561
562 idev->want[0][1] = ATA_ANY; 562 idev->want[0][1] = ATA_ANY;
563 idev->want[1][1] = ATA_ANY; 563 idev->want[1][1] = ATA_ANY;
564 564
565 /* 565 /*
566 * Not in the docs but according to the reference driver 566 * Not in the docs but according to the reference driver
567 * this is necessary. 567 * this is necessary.
568 */ 568 */
569 569
570 pci_read_config_byte(hwif->pci_dev, 0x08, &conf); 570 pci_read_config_byte(hwif->pci_dev, 0x08, &conf);
571 if (conf == 0x10) { 571 if (conf == 0x10) {
572 idev->timing10 = 1; 572 idev->timing10 = 1;
573 hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA; 573 hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
574 if (idev->smart == 0) 574 if (idev->smart == 0)
575 printk(KERN_WARNING "it821x: Revision 0x10, workarounds activated.\n"); 575 printk(KERN_WARNING "it821x: Revision 0x10, workarounds activated.\n");
576 } 576 }
577 577
578 if (idev->smart == 0) { 578 if (idev->smart == 0) {
579 hwif->set_pio_mode = &it821x_set_pio_mode; 579 hwif->set_pio_mode = &it821x_set_pio_mode;
580 hwif->set_dma_mode = &it821x_set_dma_mode; 580 hwif->set_dma_mode = &it821x_set_dma_mode;
581 581
582 /* MWDMA/PIO clock switching for pass through mode */ 582 /* MWDMA/PIO clock switching for pass through mode */
583 hwif->dma_start = &it821x_dma_start; 583 hwif->dma_start = &it821x_dma_start;
584 hwif->ide_dma_end = &it821x_dma_end; 584 hwif->ide_dma_end = &it821x_dma_end;
585 } else 585 } else
586 hwif->host_flags |= IDE_HFLAG_NO_SET_MODE; 586 hwif->host_flags |= IDE_HFLAG_NO_SET_MODE;
587 587
588 if (hwif->dma_base == 0) 588 if (hwif->dma_base == 0)
589 return; 589 return;
590 590
591 hwif->ultra_mask = ATA_UDMA6; 591 hwif->ultra_mask = ATA_UDMA6;
592 hwif->mwdma_mask = ATA_MWDMA2; 592 hwif->mwdma_mask = ATA_MWDMA2;
593 593
594 if (hwif->cbl != ATA_CBL_PATA40_SHORT) 594 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
595 hwif->cbl = ata66_it821x(hwif); 595 hwif->cbl = ata66_it821x(hwif);
596 } 596 }
597 597
598 static void __devinit it8212_disable_raid(struct pci_dev *dev) 598 static void __devinit it8212_disable_raid(struct pci_dev *dev)
599 { 599 {
600 /* Reset local CPU, and set BIOS not ready */ 600 /* Reset local CPU, and set BIOS not ready */
601 pci_write_config_byte(dev, 0x5E, 0x01); 601 pci_write_config_byte(dev, 0x5E, 0x01);
602 602
603 /* Set to bypass mode, and reset PCI bus */ 603 /* Set to bypass mode, and reset PCI bus */
604 pci_write_config_byte(dev, 0x50, 0x00); 604 pci_write_config_byte(dev, 0x50, 0x00);
605 pci_write_config_word(dev, PCI_COMMAND, 605 pci_write_config_word(dev, PCI_COMMAND,
606 PCI_COMMAND_PARITY | PCI_COMMAND_IO | 606 PCI_COMMAND_PARITY | PCI_COMMAND_IO |
607 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 607 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
608 pci_write_config_word(dev, 0x40, 0xA0F3); 608 pci_write_config_word(dev, 0x40, 0xA0F3);
609 609
610 pci_write_config_dword(dev,0x4C, 0x02040204); 610 pci_write_config_dword(dev,0x4C, 0x02040204);
611 pci_write_config_byte(dev, 0x42, 0x36); 611 pci_write_config_byte(dev, 0x42, 0x36);
612 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20); 612 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
613 } 613 }
614 614
615 static unsigned int __devinit init_chipset_it821x(struct pci_dev *dev, const char *name) 615 static unsigned int __devinit init_chipset_it821x(struct pci_dev *dev, const char *name)
616 { 616 {
617 u8 conf; 617 u8 conf;
618 static char *mode[2] = { "pass through", "smart" }; 618 static char *mode[2] = { "pass through", "smart" };
619 619
620 /* Force the card into bypass mode if so requested */ 620 /* Force the card into bypass mode if so requested */
621 if (it8212_noraid) { 621 if (it8212_noraid) {
622 printk(KERN_INFO "it8212: forcing bypass mode.\n"); 622 printk(KERN_INFO "it8212: forcing bypass mode.\n");
623 it8212_disable_raid(dev); 623 it8212_disable_raid(dev);
624 } 624 }
625 pci_read_config_byte(dev, 0x50, &conf); 625 pci_read_config_byte(dev, 0x50, &conf);
626 printk(KERN_INFO "it821x: controller in %s mode.\n", mode[conf & 1]); 626 printk(KERN_INFO "it821x: controller in %s mode.\n", mode[conf & 1]);
627 return 0; 627 return 0;
628 } 628 }
629 629
630 630
631 #define DECLARE_ITE_DEV(name_str) \ 631 #define DECLARE_ITE_DEV(name_str) \
632 { \ 632 { \
633 .name = name_str, \ 633 .name = name_str, \
634 .init_chipset = init_chipset_it821x, \ 634 .init_chipset = init_chipset_it821x, \
635 .init_hwif = init_hwif_it821x, \ 635 .init_hwif = init_hwif_it821x, \
636 .fixup = it821x_fixups, \ 636 .fixup = it821x_fixups, \
637 .host_flags = IDE_HFLAG_BOOTABLE, \ 637 .host_flags = IDE_HFLAG_BOOTABLE, \
638 .pio_mask = ATA_PIO4, \ 638 .pio_mask = ATA_PIO4, \
639 } 639 }
640 640
641 static const struct ide_port_info it821x_chipsets[] __devinitdata = { 641 static const struct ide_port_info it821x_chipsets[] __devinitdata = {
642 /* 0 */ DECLARE_ITE_DEV("IT8212"), 642 /* 0 */ DECLARE_ITE_DEV("IT8212"),
643 }; 643 };
644 644
645 /** 645 /**
646 * it821x_init_one - pci layer discovery entry 646 * it821x_init_one - pci layer discovery entry
647 * @dev: PCI device 647 * @dev: PCI device
648 * @id: ident table entry 648 * @id: ident table entry
649 * 649 *
650 * Called by the PCI code when it finds an ITE821x controller. 650 * Called by the PCI code when it finds an ITE821x controller.
651 * We then use the IDE PCI generic helper to do most of the work. 651 * We then use the IDE PCI generic helper to do most of the work.
652 */ 652 */
653 653
654 static int __devinit it821x_init_one(struct pci_dev *dev, const struct pci_device_id *id) 654 static int __devinit it821x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
655 { 655 {
656 ide_setup_pci_device(dev, &it821x_chipsets[id->driver_data]); 656 return ide_setup_pci_device(dev, &it821x_chipsets[id->driver_data]);
657 return 0;
658 } 657 }
659 658
660 static const struct pci_device_id it821x_pci_tbl[] = { 659 static const struct pci_device_id it821x_pci_tbl[] = {
661 { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8211), 0 }, 660 { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8211), 0 },
662 { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8212), 0 }, 661 { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8212), 0 },
663 { 0, }, 662 { 0, },
664 }; 663 };
665 664
666 MODULE_DEVICE_TABLE(pci, it821x_pci_tbl); 665 MODULE_DEVICE_TABLE(pci, it821x_pci_tbl);
667 666
668 static struct pci_driver driver = { 667 static struct pci_driver driver = {
669 .name = "ITE821x IDE", 668 .name = "ITE821x IDE",
670 .id_table = it821x_pci_tbl, 669 .id_table = it821x_pci_tbl,
671 .probe = it821x_init_one, 670 .probe = it821x_init_one,
672 }; 671 };
673 672
674 static int __init it821x_ide_init(void) 673 static int __init it821x_ide_init(void)
675 { 674 {
676 return ide_pci_register_driver(&driver); 675 return ide_pci_register_driver(&driver);
677 } 676 }
678 677
679 module_init(it821x_ide_init); 678 module_init(it821x_ide_init);
680 679
681 module_param_named(noraid, it8212_noraid, int, S_IRUGO); 680 module_param_named(noraid, it8212_noraid, int, S_IRUGO);
682 MODULE_PARM_DESC(it8212_noraid, "Force card into bypass mode"); 681 MODULE_PARM_DESC(it8212_noraid, "Force card into bypass mode");
683 682
684 MODULE_AUTHOR("Alan Cox"); 683 MODULE_AUTHOR("Alan Cox");
685 MODULE_DESCRIPTION("PCI driver module for the ITE 821x"); 684 MODULE_DESCRIPTION("PCI driver module for the ITE 821x");
686 MODULE_LICENSE("GPL"); 685 MODULE_LICENSE("GPL");
687 686
drivers/ide/pci/jmicron.c
Diff comments   View file @ 24ffbd6
1 1
2 /* 2 /*
3 * Copyright (C) 2006 Red Hat <alan@redhat.com> 3 * Copyright (C) 2006 Red Hat <alan@redhat.com>
4 * 4 *
5 * May be copied or modified under the terms of the GNU General Public License 5 * May be copied or modified under the terms of the GNU General Public License
6 */ 6 */
7 7
8 #include <linux/types.h> 8 #include <linux/types.h>
9 #include <linux/module.h> 9 #include <linux/module.h>
10 #include <linux/pci.h> 10 #include <linux/pci.h>
11 #include <linux/delay.h> 11 #include <linux/delay.h>
12 #include <linux/hdreg.h> 12 #include <linux/hdreg.h>
13 #include <linux/ide.h> 13 #include <linux/ide.h>
14 #include <linux/init.h> 14 #include <linux/init.h>
15 15
16 #include <asm/io.h> 16 #include <asm/io.h>
17 17
18 typedef enum { 18 typedef enum {
19 PORT_PATA0 = 0, 19 PORT_PATA0 = 0,
20 PORT_PATA1 = 1, 20 PORT_PATA1 = 1,
21 PORT_SATA = 2, 21 PORT_SATA = 2,
22 } port_type; 22 } port_type;
23 23
24 /** 24 /**
25 * ata66_jmicron - Cable check 25 * ata66_jmicron - Cable check
26 * @hwif: IDE port 26 * @hwif: IDE port
27 * 27 *
28 * Returns the cable type. 28 * Returns the cable type.
29 */ 29 */
30 30
31 static u8 __devinit ata66_jmicron(ide_hwif_t *hwif) 31 static u8 __devinit ata66_jmicron(ide_hwif_t *hwif)
32 { 32 {
33 struct pci_dev *pdev = hwif->pci_dev; 33 struct pci_dev *pdev = hwif->pci_dev;
34 34
35 u32 control; 35 u32 control;
36 u32 control5; 36 u32 control5;
37 37
38 int port = hwif->channel; 38 int port = hwif->channel;
39 port_type port_map[2]; 39 port_type port_map[2];
40 40
41 pci_read_config_dword(pdev, 0x40, &control); 41 pci_read_config_dword(pdev, 0x40, &control);
42 42
43 /* There are two basic mappings. One has the two SATA ports merged 43 /* There are two basic mappings. One has the two SATA ports merged
44 as master/slave and the secondary as PATA, the other has only the 44 as master/slave and the secondary as PATA, the other has only the
45 SATA port mapped */ 45 SATA port mapped */
46 if (control & (1 << 23)) { 46 if (control & (1 << 23)) {
47 port_map[0] = PORT_SATA; 47 port_map[0] = PORT_SATA;
48 port_map[1] = PORT_PATA0; 48 port_map[1] = PORT_PATA0;
49 } else { 49 } else {
50 port_map[0] = PORT_SATA; 50 port_map[0] = PORT_SATA;
51 port_map[1] = PORT_SATA; 51 port_map[1] = PORT_SATA;
52 } 52 }
53 53
54 /* The 365/366 may have this bit set to map the second PATA port 54 /* The 365/366 may have this bit set to map the second PATA port
55 as the internal primary channel */ 55 as the internal primary channel */
56 pci_read_config_dword(pdev, 0x80, &control5); 56 pci_read_config_dword(pdev, 0x80, &control5);
57 if (control5 & (1<<24)) 57 if (control5 & (1<<24))
58 port_map[0] = PORT_PATA1; 58 port_map[0] = PORT_PATA1;
59 59
60 /* The two ports may then be logically swapped by the firmware */ 60 /* The two ports may then be logically swapped by the firmware */
61 if (control & (1 << 22)) 61 if (control & (1 << 22))
62 port = port ^ 1; 62 port = port ^ 1;
63 63
64 /* 64 /*
65 * Now we know which physical port we are talking about we can 65 * Now we know which physical port we are talking about we can
66 * actually do our cable checking etc. Thankfully we don't need 66 * actually do our cable checking etc. Thankfully we don't need
67 * to do the plumbing for other cases. 67 * to do the plumbing for other cases.
68 */ 68 */
69 switch (port_map[port]) 69 switch (port_map[port])
70 { 70 {
71 case PORT_PATA0: 71 case PORT_PATA0:
72 if (control & (1 << 3)) /* 40/80 pin primary */ 72 if (control & (1 << 3)) /* 40/80 pin primary */
73 return ATA_CBL_PATA40; 73 return ATA_CBL_PATA40;
74 return ATA_CBL_PATA80; 74 return ATA_CBL_PATA80;
75 case PORT_PATA1: 75 case PORT_PATA1:
76 if (control5 & (1 << 19)) /* 40/80 pin secondary */ 76 if (control5 & (1 << 19)) /* 40/80 pin secondary */
77 return ATA_CBL_PATA40; 77 return ATA_CBL_PATA40;
78 return ATA_CBL_PATA80; 78 return ATA_CBL_PATA80;
79 case PORT_SATA: 79 case PORT_SATA:
80 break; 80 break;
81 } 81 }
82 /* Avoid bogus "control reaches end of non-void function" */ 82 /* Avoid bogus "control reaches end of non-void function" */
83 return ATA_CBL_PATA80; 83 return ATA_CBL_PATA80;
84 } 84 }
85 85
86 static void jmicron_set_pio_mode(ide_drive_t *drive, const u8 pio) 86 static void jmicron_set_pio_mode(ide_drive_t *drive, const u8 pio)
87 { 87 {
88 } 88 }
89 89
90 /** 90 /**
91 * jmicron_set_dma_mode - set host controller for DMA mode 91 * jmicron_set_dma_mode - set host controller for DMA mode
92 * @drive: drive 92 * @drive: drive
93 * @mode: DMA mode 93 * @mode: DMA mode
94 * 94 *
95 * As the JMicron snoops for timings we don't need to do anything here. 95 * As the JMicron snoops for timings we don't need to do anything here.
96 */ 96 */
97 97
98 static void jmicron_set_dma_mode(ide_drive_t *drive, const u8 mode) 98 static void jmicron_set_dma_mode(ide_drive_t *drive, const u8 mode)
99 { 99 {
100 } 100 }
101 101
102 /** 102 /**
103 * init_hwif_jmicron - set up hwif structs 103 * init_hwif_jmicron - set up hwif structs
104 * @hwif: interface to set up 104 * @hwif: interface to set up
105 * 105 *
106 * Minimal set up is required for the Jmicron hardware. 106 * Minimal set up is required for the Jmicron hardware.
107 */ 107 */
108 108
109 static void __devinit init_hwif_jmicron(ide_hwif_t *hwif) 109 static void __devinit init_hwif_jmicron(ide_hwif_t *hwif)
110 { 110 {
111 hwif->set_pio_mode = &jmicron_set_pio_mode; 111 hwif->set_pio_mode = &jmicron_set_pio_mode;
112 hwif->set_dma_mode = &jmicron_set_dma_mode; 112 hwif->set_dma_mode = &jmicron_set_dma_mode;
113 113
114 if (hwif->dma_base == 0) 114 if (hwif->dma_base == 0)
115 return; 115 return;
116 116
117 if (hwif->cbl != ATA_CBL_PATA40_SHORT) 117 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
118 hwif->cbl = ata66_jmicron(hwif); 118 hwif->cbl = ata66_jmicron(hwif);
119 } 119 }
120 120
121 static const struct ide_port_info jmicron_chipset __devinitdata = { 121 static const struct ide_port_info jmicron_chipset __devinitdata = {
122 .name = "JMB", 122 .name = "JMB",
123 .init_hwif = init_hwif_jmicron, 123 .init_hwif = init_hwif_jmicron,
124 .host_flags = IDE_HFLAG_BOOTABLE, 124 .host_flags = IDE_HFLAG_BOOTABLE,
125 .enablebits = { { 0x40, 0x01, 0x01 }, { 0x40, 0x10, 0x10 } }, 125 .enablebits = { { 0x40, 0x01, 0x01 }, { 0x40, 0x10, 0x10 } },
126 .pio_mask = ATA_PIO5, 126 .pio_mask = ATA_PIO5,
127 .mwdma_mask = ATA_MWDMA2, 127 .mwdma_mask = ATA_MWDMA2,
128 .udma_mask = ATA_UDMA6, 128 .udma_mask = ATA_UDMA6,
129 }; 129 };
130 130
131 /** 131 /**
132 * jmicron_init_one - pci layer discovery entry 132 * jmicron_init_one - pci layer discovery entry
133 * @dev: PCI device 133 * @dev: PCI device
134 * @id: ident table entry 134 * @id: ident table entry
135 * 135 *
136 * Called by the PCI code when it finds a Jmicron controller. 136 * Called by the PCI code when it finds a Jmicron controller.
137 * We then use the IDE PCI generic helper to do most of the work. 137 * We then use the IDE PCI generic helper to do most of the work.
138 */ 138 */
139 139
140 static int __devinit jmicron_init_one(struct pci_dev *dev, const struct pci_device_id *id) 140 static int __devinit jmicron_init_one(struct pci_dev *dev, const struct pci_device_id *id)
141 { 141 {
142 ide_setup_pci_device(dev, &jmicron_chipset); 142 return ide_setup_pci_device(dev, &jmicron_chipset);
143 return 0;
144 } 143 }
145 144
146 /* All JMB PATA controllers have and will continue to have the same 145 /* All JMB PATA controllers have and will continue to have the same
147 * interface. Matching vendor and device class is enough for all 146 * interface. Matching vendor and device class is enough for all
148 * current and future controllers if the controller is programmed 147 * current and future controllers if the controller is programmed
149 * properly. 148 * properly.
150 * 149 *
151 * If libata is configured, jmicron PCI quirk programs the controller 150 * If libata is configured, jmicron PCI quirk programs the controller
152 * into the correct mode. If libata isn't configured, match known 151 * into the correct mode. If libata isn't configured, match known
153 * device IDs too to maintain backward compatibility. 152 * device IDs too to maintain backward compatibility.
154 */ 153 */
155 static struct pci_device_id jmicron_pci_tbl[] = { 154 static struct pci_device_id jmicron_pci_tbl[] = {
156 #if !defined(CONFIG_ATA) && !defined(CONFIG_ATA_MODULE) 155 #if !defined(CONFIG_ATA) && !defined(CONFIG_ATA_MODULE)
157 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB361) }, 156 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB361) },
158 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB363) }, 157 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB363) },
159 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB365) }, 158 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB365) },
160 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB366) }, 159 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB366) },
161 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB368) }, 160 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB368) },
162 #endif 161 #endif
163 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 162 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
164 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, 0 }, 163 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, 0 },
165 { 0, }, 164 { 0, },
166 }; 165 };
167 166
168 MODULE_DEVICE_TABLE(pci, jmicron_pci_tbl); 167 MODULE_DEVICE_TABLE(pci, jmicron_pci_tbl);
169 168
170 static struct pci_driver driver = { 169 static struct pci_driver driver = {
171 .name = "JMicron IDE", 170 .name = "JMicron IDE",
172 .id_table = jmicron_pci_tbl, 171 .id_table = jmicron_pci_tbl,
173 .probe = jmicron_init_one, 172 .probe = jmicron_init_one,
174 }; 173 };
175 174
176 static int __init jmicron_ide_init(void) 175 static int __init jmicron_ide_init(void)
177 { 176 {
178 return ide_pci_register_driver(&driver); 177 return ide_pci_register_driver(&driver);
179 } 178 }
180 179
181 module_init(jmicron_ide_init); 180 module_init(jmicron_ide_init);
182 181
183 MODULE_AUTHOR("Alan Cox"); 182 MODULE_AUTHOR("Alan Cox");
184 MODULE_DESCRIPTION("PCI driver module for the JMicron in legacy modes"); 183 MODULE_DESCRIPTION("PCI driver module for the JMicron in legacy modes");
185 MODULE_LICENSE("GPL"); 184 MODULE_LICENSE("GPL");
186 185