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Commit 3e9635e4060238549ffac239de34f6122b053653

Authored by Deepak Saxena
Committed by Russell King
1 parent a427ceef93
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

[ARM] 2999/1: Replace map_desc.physical with map_desc.pfn: H720x 

Patch from Deepak Saxena

H720x map_desc.pfn conversion

Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Showing 1 changed file with 6 additions and 1 deletions Inline Diff

arch/arm/mach-h720x/common.c
Diff comments   View file @ 3e9635e
1 /* 1 /*
2 * linux/arch/arm/mach-h720x/common.c 2 * linux/arch/arm/mach-h720x/common.c
3 * 3 *
4 * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de> 4 * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
5 * 2003 Robert Schwebel <r.schwebel@pengutronix.de> 5 * 2003 Robert Schwebel <r.schwebel@pengutronix.de>
6 * 2004 Sascha Hauer <s.hauer@pengutronix.de> 6 * 2004 Sascha Hauer <s.hauer@pengutronix.de>
7 * 7 *
8 * common stuff for Hynix h720x processors 8 * common stuff for Hynix h720x processors
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as 11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13 * 13 *
14 */ 14 */
15 15
16 #include <linux/sched.h> 16 #include <linux/sched.h>
17 #include <linux/slab.h> 17 #include <linux/slab.h>
18 #include <linux/mman.h> 18 #include <linux/mman.h>
19 #include <linux/init.h> 19 #include <linux/init.h>
20 #include <linux/interrupt.h> 20 #include <linux/interrupt.h>
21 21
22 #include <asm/page.h> 22 #include <asm/page.h>
23 #include <asm/pgtable.h> 23 #include <asm/pgtable.h>
24 #include <asm/dma.h> 24 #include <asm/dma.h>
25 #include <asm/io.h> 25 #include <asm/io.h>
26 #include <asm/hardware.h> 26 #include <asm/hardware.h>
27 #include <asm/irq.h> 27 #include <asm/irq.h>
28 #include <asm/mach/irq.h> 28 #include <asm/mach/irq.h>
29 #include <asm/mach/map.h> 29 #include <asm/mach/map.h>
30 #include <asm/arch/irqs.h> 30 #include <asm/arch/irqs.h>
31 31
32 #include <asm/mach/dma.h> 32 #include <asm/mach/dma.h>
33 33
34 #if 0 34 #if 0
35 #define IRQDBG(args...) printk(args) 35 #define IRQDBG(args...) printk(args)
36 #else 36 #else
37 #define IRQDBG(args...) do {} while(0) 37 #define IRQDBG(args...) do {} while(0)
38 #endif 38 #endif
39 39
40 void __init arch_dma_init(dma_t *dma) 40 void __init arch_dma_init(dma_t *dma)
41 { 41 {
42 } 42 }
43 43
44 /* 44 /*
45 * Return usecs since last timer reload 45 * Return usecs since last timer reload
46 * (timercount * (usecs perjiffie)) / (ticks per jiffie) 46 * (timercount * (usecs perjiffie)) / (ticks per jiffie)
47 */ 47 */
48 unsigned long h720x_gettimeoffset(void) 48 unsigned long h720x_gettimeoffset(void)
49 { 49 {
50 return (CPU_REG (TIMER_VIRT, TM0_COUNT) * tick_usec) / LATCH; 50 return (CPU_REG (TIMER_VIRT, TM0_COUNT) * tick_usec) / LATCH;
51 } 51 }
52 52
53 /* 53 /*
54 * mask Global irq's 54 * mask Global irq's
55 */ 55 */
56 static void mask_global_irq (unsigned int irq ) 56 static void mask_global_irq (unsigned int irq )
57 { 57 {
58 CPU_REG (IRQC_VIRT, IRQC_IER) &= ~(1 << irq); 58 CPU_REG (IRQC_VIRT, IRQC_IER) &= ~(1 << irq);
59 } 59 }
60 60
61 /* 61 /*
62 * unmask Global irq's 62 * unmask Global irq's
63 */ 63 */
64 static void unmask_global_irq (unsigned int irq ) 64 static void unmask_global_irq (unsigned int irq )
65 { 65 {
66 CPU_REG (IRQC_VIRT, IRQC_IER) |= (1 << irq); 66 CPU_REG (IRQC_VIRT, IRQC_IER) |= (1 << irq);
67 } 67 }
68 68
69 69
70 /* 70 /*
71 * ack GPIO irq's 71 * ack GPIO irq's
72 * Ack only for edge triggered int's valid 72 * Ack only for edge triggered int's valid
73 */ 73 */
74 static void inline ack_gpio_irq(u32 irq) 74 static void inline ack_gpio_irq(u32 irq)
75 { 75 {
76 u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq)); 76 u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
77 u32 bit = IRQ_TO_BIT(irq); 77 u32 bit = IRQ_TO_BIT(irq);
78 if ( (CPU_REG (reg_base, GPIO_EDGE) & bit)) 78 if ( (CPU_REG (reg_base, GPIO_EDGE) & bit))
79 CPU_REG (reg_base, GPIO_CLR) = bit; 79 CPU_REG (reg_base, GPIO_CLR) = bit;
80 } 80 }
81 81
82 /* 82 /*
83 * mask GPIO irq's 83 * mask GPIO irq's
84 */ 84 */
85 static void inline mask_gpio_irq(u32 irq) 85 static void inline mask_gpio_irq(u32 irq)
86 { 86 {
87 u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq)); 87 u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
88 u32 bit = IRQ_TO_BIT(irq); 88 u32 bit = IRQ_TO_BIT(irq);
89 CPU_REG (reg_base, GPIO_MASK) &= ~bit; 89 CPU_REG (reg_base, GPIO_MASK) &= ~bit;
90 } 90 }
91 91
92 /* 92 /*
93 * unmask GPIO irq's 93 * unmask GPIO irq's
94 */ 94 */
95 static void inline unmask_gpio_irq(u32 irq) 95 static void inline unmask_gpio_irq(u32 irq)
96 { 96 {
97 u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq)); 97 u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
98 u32 bit = IRQ_TO_BIT(irq); 98 u32 bit = IRQ_TO_BIT(irq);
99 CPU_REG (reg_base, GPIO_MASK) |= bit; 99 CPU_REG (reg_base, GPIO_MASK) |= bit;
100 } 100 }
101 101
102 static void 102 static void
103 h720x_gpio_handler(unsigned int mask, unsigned int irq, 103 h720x_gpio_handler(unsigned int mask, unsigned int irq,
104 struct irqdesc *desc, struct pt_regs *regs) 104 struct irqdesc *desc, struct pt_regs *regs)
105 { 105 {
106 IRQDBG("%s irq: %d\n",__FUNCTION__,irq); 106 IRQDBG("%s irq: %d\n",__FUNCTION__,irq);
107 desc = irq_desc + irq; 107 desc = irq_desc + irq;
108 while (mask) { 108 while (mask) {
109 if (mask & 1) { 109 if (mask & 1) {
110 IRQDBG("handling irq %d\n", irq); 110 IRQDBG("handling irq %d\n", irq);
111 desc_handle_irq(irq, desc, regs); 111 desc_handle_irq(irq, desc, regs);
112 } 112 }
113 irq++; 113 irq++;
114 desc++; 114 desc++;
115 mask >>= 1; 115 mask >>= 1;
116 } 116 }
117 } 117 }
118 118
119 static void 119 static void
120 h720x_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc, 120 h720x_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
121 struct pt_regs *regs) 121 struct pt_regs *regs)
122 { 122 {
123 unsigned int mask, irq; 123 unsigned int mask, irq;
124 124
125 mask = CPU_REG(GPIO_A_VIRT,GPIO_STAT); 125 mask = CPU_REG(GPIO_A_VIRT,GPIO_STAT);
126 irq = IRQ_CHAINED_GPIOA(0); 126 irq = IRQ_CHAINED_GPIOA(0);
127 IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq); 127 IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
128 h720x_gpio_handler(mask, irq, desc, regs); 128 h720x_gpio_handler(mask, irq, desc, regs);
129 } 129 }
130 130
131 static void 131 static void
132 h720x_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc, 132 h720x_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
133 struct pt_regs *regs) 133 struct pt_regs *regs)
134 { 134 {
135 unsigned int mask, irq; 135 unsigned int mask, irq;
136 mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT); 136 mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT);
137 irq = IRQ_CHAINED_GPIOB(0); 137 irq = IRQ_CHAINED_GPIOB(0);
138 IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq); 138 IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
139 h720x_gpio_handler(mask, irq, desc, regs); 139 h720x_gpio_handler(mask, irq, desc, regs);
140 } 140 }
141 141
142 static void 142 static void
143 h720x_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc, 143 h720x_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
144 struct pt_regs *regs) 144 struct pt_regs *regs)
145 { 145 {
146 unsigned int mask, irq; 146 unsigned int mask, irq;
147 147
148 mask = CPU_REG(GPIO_C_VIRT,GPIO_STAT); 148 mask = CPU_REG(GPIO_C_VIRT,GPIO_STAT);
149 irq = IRQ_CHAINED_GPIOC(0); 149 irq = IRQ_CHAINED_GPIOC(0);
150 IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq); 150 IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
151 h720x_gpio_handler(mask, irq, desc, regs); 151 h720x_gpio_handler(mask, irq, desc, regs);
152 } 152 }
153 153
154 static void 154 static void
155 h720x_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc, 155 h720x_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
156 struct pt_regs *regs) 156 struct pt_regs *regs)
157 { 157 {
158 unsigned int mask, irq; 158 unsigned int mask, irq;
159 159
160 mask = CPU_REG(GPIO_D_VIRT,GPIO_STAT); 160 mask = CPU_REG(GPIO_D_VIRT,GPIO_STAT);
161 irq = IRQ_CHAINED_GPIOD(0); 161 irq = IRQ_CHAINED_GPIOD(0);
162 IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq); 162 IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
163 h720x_gpio_handler(mask, irq, desc, regs); 163 h720x_gpio_handler(mask, irq, desc, regs);
164 } 164 }
165 165
166 #ifdef CONFIG_CPU_H7202 166 #ifdef CONFIG_CPU_H7202
167 static void 167 static void
168 h720x_gpioe_demux_handler(unsigned int irq_unused, struct irqdesc *desc, 168 h720x_gpioe_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
169 struct pt_regs *regs) 169 struct pt_regs *regs)
170 { 170 {
171 unsigned int mask, irq; 171 unsigned int mask, irq;
172 172
173 mask = CPU_REG(GPIO_E_VIRT,GPIO_STAT); 173 mask = CPU_REG(GPIO_E_VIRT,GPIO_STAT);
174 irq = IRQ_CHAINED_GPIOE(0); 174 irq = IRQ_CHAINED_GPIOE(0);
175 IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq); 175 IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
176 h720x_gpio_handler(mask, irq, desc, regs); 176 h720x_gpio_handler(mask, irq, desc, regs);
177 } 177 }
178 #endif 178 #endif
179 179
180 static struct irqchip h720x_global_chip = { 180 static struct irqchip h720x_global_chip = {
181 .ack = mask_global_irq, 181 .ack = mask_global_irq,
182 .mask = mask_global_irq, 182 .mask = mask_global_irq,
183 .unmask = unmask_global_irq, 183 .unmask = unmask_global_irq,
184 }; 184 };
185 185
186 static struct irqchip h720x_gpio_chip = { 186 static struct irqchip h720x_gpio_chip = {
187 .ack = ack_gpio_irq, 187 .ack = ack_gpio_irq,
188 .mask = mask_gpio_irq, 188 .mask = mask_gpio_irq,
189 .unmask = unmask_gpio_irq, 189 .unmask = unmask_gpio_irq,
190 }; 190 };
191 191
192 /* 192 /*
193 * Initialize IRQ's, mask all, enable multiplexed irq's 193 * Initialize IRQ's, mask all, enable multiplexed irq's
194 */ 194 */
195 void __init h720x_init_irq (void) 195 void __init h720x_init_irq (void)
196 { 196 {
197 int irq; 197 int irq;
198 198
199 /* Mask global irq's */ 199 /* Mask global irq's */
200 CPU_REG (IRQC_VIRT, IRQC_IER) = 0x0; 200 CPU_REG (IRQC_VIRT, IRQC_IER) = 0x0;
201 201
202 /* Mask all multiplexed irq's */ 202 /* Mask all multiplexed irq's */
203 CPU_REG (GPIO_A_VIRT, GPIO_MASK) = 0x0; 203 CPU_REG (GPIO_A_VIRT, GPIO_MASK) = 0x0;
204 CPU_REG (GPIO_B_VIRT, GPIO_MASK) = 0x0; 204 CPU_REG (GPIO_B_VIRT, GPIO_MASK) = 0x0;
205 CPU_REG (GPIO_C_VIRT, GPIO_MASK) = 0x0; 205 CPU_REG (GPIO_C_VIRT, GPIO_MASK) = 0x0;
206 CPU_REG (GPIO_D_VIRT, GPIO_MASK) = 0x0; 206 CPU_REG (GPIO_D_VIRT, GPIO_MASK) = 0x0;
207 207
208 /* Initialize global IRQ's, fast path */ 208 /* Initialize global IRQ's, fast path */
209 for (irq = 0; irq < NR_GLBL_IRQS; irq++) { 209 for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
210 set_irq_chip(irq, &h720x_global_chip); 210 set_irq_chip(irq, &h720x_global_chip);
211 set_irq_handler(irq, do_level_IRQ); 211 set_irq_handler(irq, do_level_IRQ);
212 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 212 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
213 } 213 }
214 214
215 /* Initialize multiplexed IRQ's, slow path */ 215 /* Initialize multiplexed IRQ's, slow path */
216 for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) { 216 for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
217 set_irq_chip(irq, &h720x_gpio_chip); 217 set_irq_chip(irq, &h720x_gpio_chip);
218 set_irq_handler(irq, do_edge_IRQ); 218 set_irq_handler(irq, do_edge_IRQ);
219 set_irq_flags(irq, IRQF_VALID ); 219 set_irq_flags(irq, IRQF_VALID );
220 } 220 }
221 set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler); 221 set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
222 set_irq_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler); 222 set_irq_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
223 set_irq_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler); 223 set_irq_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
224 set_irq_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler); 224 set_irq_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);
225 225
226 #ifdef CONFIG_CPU_H7202 226 #ifdef CONFIG_CPU_H7202
227 for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) { 227 for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
228 set_irq_chip(irq, &h720x_gpio_chip); 228 set_irq_chip(irq, &h720x_gpio_chip);
229 set_irq_handler(irq, do_edge_IRQ); 229 set_irq_handler(irq, do_edge_IRQ);
230 set_irq_flags(irq, IRQF_VALID ); 230 set_irq_flags(irq, IRQF_VALID );
231 } 231 }
232 set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler); 232 set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
233 #endif 233 #endif
234 234
235 /* Enable multiplexed irq's */ 235 /* Enable multiplexed irq's */
236 CPU_REG (IRQC_VIRT, IRQC_IER) = IRQ_ENA_MUX; 236 CPU_REG (IRQC_VIRT, IRQC_IER) = IRQ_ENA_MUX;
237 } 237 }
238 238
239 static struct map_desc h720x_io_desc[] __initdata = { 239 static struct map_desc h720x_io_desc[] __initdata = {
240 { IO_VIRT, IO_PHYS, IO_SIZE, MT_DEVICE }, 240 {
241 .virtual = IO_VIRT,
242 .pfn = __phys_to_pfn(IO_PHYS),
243 .length = IO_SIZE,
244 .type = MT_DEVICE
245 },
241 }; 246 };
242 247
243 /* Initialize io tables */ 248 /* Initialize io tables */
244 void __init h720x_map_io(void) 249 void __init h720x_map_io(void)
245 { 250 {
246 iotable_init(h720x_io_desc,ARRAY_SIZE(h720x_io_desc)); 251 iotable_init(h720x_io_desc,ARRAY_SIZE(h720x_io_desc));
247 } 252 }
248 253