Commit 459773ae8dbbd480886d186181c6bc2e8556025f

Authored by Michael Hennerich
Committed by Linus Torvalds
1 parent ead6db0843

gpio: adp5588-gpio: support interrupt controller

Implement irq_chip functionality on ADP5588/5587 GPIO expanders.  Only
level sensitive interrupts are supported.  Interrupts provided by this
irq_chip must be requested using request_threaded_irq().

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

Showing 3 changed files with 278 additions and 21 deletions Inline Diff

drivers/gpio/Kconfig
1 # 1 #
2 # platform-neutral GPIO infrastructure and expanders 2 # platform-neutral GPIO infrastructure and expanders
3 # 3 #
4 4
5 config ARCH_WANT_OPTIONAL_GPIOLIB 5 config ARCH_WANT_OPTIONAL_GPIOLIB
6 bool 6 bool
7 help 7 help
8 Select this config option from the architecture Kconfig, if 8 Select this config option from the architecture Kconfig, if
9 it is possible to use gpiolib on the architecture, but let the 9 it is possible to use gpiolib on the architecture, but let the
10 user decide whether to actually build it or not. 10 user decide whether to actually build it or not.
11 Select this instead of ARCH_REQUIRE_GPIOLIB, if your architecture does 11 Select this instead of ARCH_REQUIRE_GPIOLIB, if your architecture does
12 not depend on GPIOs being available, but rather let the user 12 not depend on GPIOs being available, but rather let the user
13 decide whether he needs it or not. 13 decide whether he needs it or not.
14 14
15 config ARCH_REQUIRE_GPIOLIB 15 config ARCH_REQUIRE_GPIOLIB
16 bool 16 bool
17 select GPIOLIB 17 select GPIOLIB
18 help 18 help
19 Platforms select gpiolib if they use this infrastructure 19 Platforms select gpiolib if they use this infrastructure
20 for all their GPIOs, usually starting with ones integrated 20 for all their GPIOs, usually starting with ones integrated
21 into SOC processors. 21 into SOC processors.
22 Selecting this from the architecture code will cause the gpiolib 22 Selecting this from the architecture code will cause the gpiolib
23 code to always get built in. 23 code to always get built in.
24 24
25 25
26 26
27 menuconfig GPIOLIB 27 menuconfig GPIOLIB
28 bool "GPIO Support" 28 bool "GPIO Support"
29 depends on ARCH_WANT_OPTIONAL_GPIOLIB || ARCH_REQUIRE_GPIOLIB 29 depends on ARCH_WANT_OPTIONAL_GPIOLIB || ARCH_REQUIRE_GPIOLIB
30 select GENERIC_GPIO 30 select GENERIC_GPIO
31 help 31 help
32 This enables GPIO support through the generic GPIO library. 32 This enables GPIO support through the generic GPIO library.
33 You only need to enable this, if you also want to enable 33 You only need to enable this, if you also want to enable
34 one or more of the GPIO expansion card drivers below. 34 one or more of the GPIO expansion card drivers below.
35 35
36 If unsure, say N. 36 If unsure, say N.
37 37
38 if GPIOLIB 38 if GPIOLIB
39 39
40 config DEBUG_GPIO 40 config DEBUG_GPIO
41 bool "Debug GPIO calls" 41 bool "Debug GPIO calls"
42 depends on DEBUG_KERNEL 42 depends on DEBUG_KERNEL
43 help 43 help
44 Say Y here to add some extra checks and diagnostics to GPIO calls. 44 Say Y here to add some extra checks and diagnostics to GPIO calls.
45 These checks help ensure that GPIOs have been properly initialized 45 These checks help ensure that GPIOs have been properly initialized
46 before they are used, and that sleeping calls are not made from 46 before they are used, and that sleeping calls are not made from
47 non-sleeping contexts. They can make bitbanged serial protocols 47 non-sleeping contexts. They can make bitbanged serial protocols
48 slower. The diagnostics help catch the type of setup errors 48 slower. The diagnostics help catch the type of setup errors
49 that are most common when setting up new platforms or boards. 49 that are most common when setting up new platforms or boards.
50 50
51 config GPIO_SYSFS 51 config GPIO_SYSFS
52 bool "/sys/class/gpio/... (sysfs interface)" 52 bool "/sys/class/gpio/... (sysfs interface)"
53 depends on SYSFS && EXPERIMENTAL 53 depends on SYSFS && EXPERIMENTAL
54 help 54 help
55 Say Y here to add a sysfs interface for GPIOs. 55 Say Y here to add a sysfs interface for GPIOs.
56 56
57 This is mostly useful to work around omissions in a system's 57 This is mostly useful to work around omissions in a system's
58 kernel support. Those are common in custom and semicustom 58 kernel support. Those are common in custom and semicustom
59 hardware assembled using standard kernels with a minimum of 59 hardware assembled using standard kernels with a minimum of
60 custom patches. In those cases, userspace code may import 60 custom patches. In those cases, userspace code may import
61 a given GPIO from the kernel, if no kernel driver requested it. 61 a given GPIO from the kernel, if no kernel driver requested it.
62 62
63 Kernel drivers may also request that a particular GPIO be 63 Kernel drivers may also request that a particular GPIO be
64 exported to userspace; this can be useful when debugging. 64 exported to userspace; this can be useful when debugging.
65 65
66 # put expanders in the right section, in alphabetical order 66 # put expanders in the right section, in alphabetical order
67 67
68 config GPIO_MAX730X 68 config GPIO_MAX730X
69 tristate 69 tristate
70 70
71 comment "Memory mapped GPIO expanders:" 71 comment "Memory mapped GPIO expanders:"
72 72
73 config GPIO_BASIC_MMIO 73 config GPIO_BASIC_MMIO
74 tristate "Basic memory-mapped GPIO controllers support" 74 tristate "Basic memory-mapped GPIO controllers support"
75 help 75 help
76 Say yes here to support basic memory-mapped GPIO controllers. 76 Say yes here to support basic memory-mapped GPIO controllers.
77 77
78 config GPIO_IT8761E 78 config GPIO_IT8761E
79 tristate "IT8761E GPIO support" 79 tristate "IT8761E GPIO support"
80 depends on GPIOLIB 80 depends on GPIOLIB
81 help 81 help
82 Say yes here to support GPIO functionality of IT8761E super I/O chip. 82 Say yes here to support GPIO functionality of IT8761E super I/O chip.
83 83
84 config GPIO_PL061 84 config GPIO_PL061
85 bool "PrimeCell PL061 GPIO support" 85 bool "PrimeCell PL061 GPIO support"
86 depends on ARM_AMBA 86 depends on ARM_AMBA
87 help 87 help
88 Say yes here to support the PrimeCell PL061 GPIO device 88 Say yes here to support the PrimeCell PL061 GPIO device
89 89
90 config GPIO_XILINX 90 config GPIO_XILINX
91 bool "Xilinx GPIO support" 91 bool "Xilinx GPIO support"
92 depends on PPC_OF || MICROBLAZE 92 depends on PPC_OF || MICROBLAZE
93 help 93 help
94 Say yes here to support the Xilinx FPGA GPIO device 94 Say yes here to support the Xilinx FPGA GPIO device
95 95
96 config GPIO_VR41XX 96 config GPIO_VR41XX
97 tristate "NEC VR4100 series General-purpose I/O Uint support" 97 tristate "NEC VR4100 series General-purpose I/O Uint support"
98 depends on CPU_VR41XX 98 depends on CPU_VR41XX
99 help 99 help
100 Say yes here to support the NEC VR4100 series General-purpose I/O Uint 100 Say yes here to support the NEC VR4100 series General-purpose I/O Uint
101 101
102 config GPIO_SCH 102 config GPIO_SCH
103 tristate "Intel SCH GPIO" 103 tristate "Intel SCH GPIO"
104 depends on GPIOLIB && PCI 104 depends on GPIOLIB && PCI
105 select MFD_CORE 105 select MFD_CORE
106 select LPC_SCH 106 select LPC_SCH
107 help 107 help
108 Say yes here to support GPIO interface on Intel Poulsbo SCH. 108 Say yes here to support GPIO interface on Intel Poulsbo SCH.
109 The Intel SCH contains a total of 14 GPIO pins. Ten GPIOs are 109 The Intel SCH contains a total of 14 GPIO pins. Ten GPIOs are
110 powered by the core power rail and are turned off during sleep 110 powered by the core power rail and are turned off during sleep
111 modes (S3 and higher). The remaining four GPIOs are powered by 111 modes (S3 and higher). The remaining four GPIOs are powered by
112 the Intel SCH suspend power supply. These GPIOs remain 112 the Intel SCH suspend power supply. These GPIOs remain
113 active during S3. The suspend powered GPIOs can be used to wake the 113 active during S3. The suspend powered GPIOs can be used to wake the
114 system from the Suspend-to-RAM state. 114 system from the Suspend-to-RAM state.
115 115
116 This driver can also be built as a module. If so, the module 116 This driver can also be built as a module. If so, the module
117 will be called sch-gpio. 117 will be called sch-gpio.
118 118
119 comment "I2C GPIO expanders:" 119 comment "I2C GPIO expanders:"
120 120
121 config GPIO_MAX7300 121 config GPIO_MAX7300
122 tristate "Maxim MAX7300 GPIO expander" 122 tristate "Maxim MAX7300 GPIO expander"
123 depends on I2C 123 depends on I2C
124 select GPIO_MAX730X 124 select GPIO_MAX730X
125 help 125 help
126 GPIO driver for Maxim MAX7301 I2C-based GPIO expander. 126 GPIO driver for Maxim MAX7301 I2C-based GPIO expander.
127 127
128 config GPIO_MAX732X 128 config GPIO_MAX732X
129 tristate "MAX7319, MAX7320-7327 I2C Port Expanders" 129 tristate "MAX7319, MAX7320-7327 I2C Port Expanders"
130 depends on I2C 130 depends on I2C
131 help 131 help
132 Say yes here to support the MAX7319, MAX7320-7327 series of I2C 132 Say yes here to support the MAX7319, MAX7320-7327 series of I2C
133 Port Expanders. Each IO port on these chips has a fixed role of 133 Port Expanders. Each IO port on these chips has a fixed role of
134 Input (designated by 'I'), Push-Pull Output ('O'), or Open-Drain 134 Input (designated by 'I'), Push-Pull Output ('O'), or Open-Drain
135 Input and Output (designed by 'P'). The combinations are listed 135 Input and Output (designed by 'P'). The combinations are listed
136 below: 136 below:
137 137
138 8 bits: max7319 (8I), max7320 (8O), max7321 (8P), 138 8 bits: max7319 (8I), max7320 (8O), max7321 (8P),
139 max7322 (4I4O), max7323 (4P4O) 139 max7322 (4I4O), max7323 (4P4O)
140 140
141 16 bits: max7324 (8I8O), max7325 (8P8O), 141 16 bits: max7324 (8I8O), max7325 (8P8O),
142 max7326 (4I12O), max7327 (4P12O) 142 max7326 (4I12O), max7327 (4P12O)
143 143
144 Board setup code must specify the model to use, and the start 144 Board setup code must specify the model to use, and the start
145 number for these GPIOs. 145 number for these GPIOs.
146 146
147 config GPIO_MAX732X_IRQ 147 config GPIO_MAX732X_IRQ
148 bool "Interrupt controller support for MAX732x" 148 bool "Interrupt controller support for MAX732x"
149 depends on GPIO_MAX732X=y && GENERIC_HARDIRQS 149 depends on GPIO_MAX732X=y && GENERIC_HARDIRQS
150 help 150 help
151 Say yes here to enable the max732x to be used as an interrupt 151 Say yes here to enable the max732x to be used as an interrupt
152 controller. It requires the driver to be built in the kernel. 152 controller. It requires the driver to be built in the kernel.
153 153
154 config GPIO_PCA953X 154 config GPIO_PCA953X
155 tristate "PCA953x, PCA955x, TCA64xx, and MAX7310 I/O ports" 155 tristate "PCA953x, PCA955x, TCA64xx, and MAX7310 I/O ports"
156 depends on I2C 156 depends on I2C
157 help 157 help
158 Say yes here to provide access to several register-oriented 158 Say yes here to provide access to several register-oriented
159 SMBus I/O expanders, made mostly by NXP or TI. Compatible 159 SMBus I/O expanders, made mostly by NXP or TI. Compatible
160 models include: 160 models include:
161 161
162 4 bits: pca9536, pca9537 162 4 bits: pca9536, pca9537
163 163
164 8 bits: max7310, pca9534, pca9538, pca9554, pca9557, 164 8 bits: max7310, pca9534, pca9538, pca9554, pca9557,
165 tca6408 165 tca6408
166 166
167 16 bits: pca9535, pca9539, pca9555, tca6416 167 16 bits: pca9535, pca9539, pca9555, tca6416
168 168
169 This driver can also be built as a module. If so, the module 169 This driver can also be built as a module. If so, the module
170 will be called pca953x. 170 will be called pca953x.
171 171
172 config GPIO_PCA953X_IRQ 172 config GPIO_PCA953X_IRQ
173 bool "Interrupt controller support for PCA953x" 173 bool "Interrupt controller support for PCA953x"
174 depends on GPIO_PCA953X=y 174 depends on GPIO_PCA953X=y
175 help 175 help
176 Say yes here to enable the pca953x to be used as an interrupt 176 Say yes here to enable the pca953x to be used as an interrupt
177 controller. It requires the driver to be built in the kernel. 177 controller. It requires the driver to be built in the kernel.
178 178
179 config GPIO_PCF857X 179 config GPIO_PCF857X
180 tristate "PCF857x, PCA{85,96}7x, and MAX732[89] I2C GPIO expanders" 180 tristate "PCF857x, PCA{85,96}7x, and MAX732[89] I2C GPIO expanders"
181 depends on I2C 181 depends on I2C
182 help 182 help
183 Say yes here to provide access to most "quasi-bidirectional" I2C 183 Say yes here to provide access to most "quasi-bidirectional" I2C
184 GPIO expanders used for additional digital outputs or inputs. 184 GPIO expanders used for additional digital outputs or inputs.
185 Most of these parts are from NXP, though TI is a second source for 185 Most of these parts are from NXP, though TI is a second source for
186 some of them. Compatible models include: 186 some of them. Compatible models include:
187 187
188 8 bits: pcf8574, pcf8574a, pca8574, pca8574a, 188 8 bits: pcf8574, pcf8574a, pca8574, pca8574a,
189 pca9670, pca9672, pca9674, pca9674a, 189 pca9670, pca9672, pca9674, pca9674a,
190 max7328, max7329 190 max7328, max7329
191 191
192 16 bits: pcf8575, pcf8575c, pca8575, 192 16 bits: pcf8575, pcf8575c, pca8575,
193 pca9671, pca9673, pca9675 193 pca9671, pca9673, pca9675
194 194
195 Your board setup code will need to declare the expanders in 195 Your board setup code will need to declare the expanders in
196 use, and assign numbers to the GPIOs they expose. Those GPIOs 196 use, and assign numbers to the GPIOs they expose. Those GPIOs
197 can then be used from drivers and other kernel code, just like 197 can then be used from drivers and other kernel code, just like
198 other GPIOs, but only accessible from task contexts. 198 other GPIOs, but only accessible from task contexts.
199 199
200 This driver provides an in-kernel interface to those GPIOs using 200 This driver provides an in-kernel interface to those GPIOs using
201 platform-neutral GPIO calls. 201 platform-neutral GPIO calls.
202 202
203 config GPIO_SX150X 203 config GPIO_SX150X
204 bool "Semtech SX150x I2C GPIO expander" 204 bool "Semtech SX150x I2C GPIO expander"
205 depends on I2C=y 205 depends on I2C=y
206 default n 206 default n
207 help 207 help
208 Say yes here to provide support for Semtech SX150-series I2C 208 Say yes here to provide support for Semtech SX150-series I2C
209 GPIO expanders. Compatible models include: 209 GPIO expanders. Compatible models include:
210 210
211 8 bits: sx1508q 211 8 bits: sx1508q
212 16 bits: sx1509q 212 16 bits: sx1509q
213 213
214 config GPIO_STMPE 214 config GPIO_STMPE
215 bool "STMPE GPIOs" 215 bool "STMPE GPIOs"
216 depends on MFD_STMPE 216 depends on MFD_STMPE
217 help 217 help
218 This enables support for the GPIOs found on the STMPE I/O 218 This enables support for the GPIOs found on the STMPE I/O
219 Expanders. 219 Expanders.
220 220
221 config GPIO_TC35892 221 config GPIO_TC35892
222 bool "TC35892 GPIOs" 222 bool "TC35892 GPIOs"
223 depends on MFD_TC35892 223 depends on MFD_TC35892
224 help 224 help
225 This enables support for the GPIOs found on the TC35892 225 This enables support for the GPIOs found on the TC35892
226 I/O Expander. 226 I/O Expander.
227 227
228 config GPIO_TWL4030 228 config GPIO_TWL4030
229 tristate "TWL4030, TWL5030, and TPS659x0 GPIOs" 229 tristate "TWL4030, TWL5030, and TPS659x0 GPIOs"
230 depends on TWL4030_CORE 230 depends on TWL4030_CORE
231 help 231 help
232 Say yes here to access the GPIO signals of various multi-function 232 Say yes here to access the GPIO signals of various multi-function
233 power management chips from Texas Instruments. 233 power management chips from Texas Instruments.
234 234
235 config GPIO_WM831X 235 config GPIO_WM831X
236 tristate "WM831x GPIOs" 236 tristate "WM831x GPIOs"
237 depends on MFD_WM831X 237 depends on MFD_WM831X
238 help 238 help
239 Say yes here to access the GPIO signals of WM831x power management 239 Say yes here to access the GPIO signals of WM831x power management
240 chips from Wolfson Microelectronics. 240 chips from Wolfson Microelectronics.
241 241
242 config GPIO_WM8350 242 config GPIO_WM8350
243 tristate "WM8350 GPIOs" 243 tristate "WM8350 GPIOs"
244 depends on MFD_WM8350 244 depends on MFD_WM8350
245 help 245 help
246 Say yes here to access the GPIO signals of WM8350 power management 246 Say yes here to access the GPIO signals of WM8350 power management
247 chips from Wolfson Microelectronics. 247 chips from Wolfson Microelectronics.
248 248
249 config GPIO_WM8994 249 config GPIO_WM8994
250 tristate "WM8994 GPIOs" 250 tristate "WM8994 GPIOs"
251 depends on MFD_WM8994 251 depends on MFD_WM8994
252 help 252 help
253 Say yes here to access the GPIO signals of WM8994 audio hub 253 Say yes here to access the GPIO signals of WM8994 audio hub
254 CODECs from Wolfson Microelectronics. 254 CODECs from Wolfson Microelectronics.
255 255
256 config GPIO_ADP5520 256 config GPIO_ADP5520
257 tristate "GPIO Support for ADP5520 PMIC" 257 tristate "GPIO Support for ADP5520 PMIC"
258 depends on PMIC_ADP5520 258 depends on PMIC_ADP5520
259 help 259 help
260 This option enables support for on-chip GPIO found 260 This option enables support for on-chip GPIO found
261 on Analog Devices ADP5520 PMICs. 261 on Analog Devices ADP5520 PMICs.
262 262
263 To compile this driver as a module, choose M here: the module will 263 To compile this driver as a module, choose M here: the module will
264 be called adp5520-gpio. 264 be called adp5520-gpio.
265 265
266 config GPIO_ADP5588 266 config GPIO_ADP5588
267 tristate "ADP5588 I2C GPIO expander" 267 tristate "ADP5588 I2C GPIO expander"
268 depends on I2C 268 depends on I2C
269 help 269 help
270 This option enables support for 18 GPIOs found 270 This option enables support for 18 GPIOs found
271 on Analog Devices ADP5588 GPIO Expanders. 271 on Analog Devices ADP5588 GPIO Expanders.
272 To compile this driver as a module, choose M here: the module will be 272 To compile this driver as a module, choose M here: the module will be
273 called adp5588-gpio. 273 called adp5588-gpio.
274 274
275 config GPIO_ADP5588_IRQ
276 bool "Interrupt controller support for ADP5588"
277 depends on GPIO_ADP5588=y
278 help
279 Say yes here to enable the adp5588 to be used as an interrupt
280 controller. It requires the driver to be built in the kernel.
281
275 comment "PCI GPIO expanders:" 282 comment "PCI GPIO expanders:"
276 283
277 config GPIO_CS5535 284 config GPIO_CS5535
278 tristate "AMD CS5535/CS5536 GPIO support" 285 tristate "AMD CS5535/CS5536 GPIO support"
279 depends on PCI && !CS5535_GPIO 286 depends on PCI && !CS5535_GPIO
280 help 287 help
281 The AMD CS5535 and CS5536 southbridges support 28 GPIO pins that 288 The AMD CS5535 and CS5536 southbridges support 28 GPIO pins that
282 can be used for quite a number of things. The CS5535/6 is found on 289 can be used for quite a number of things. The CS5535/6 is found on
283 AMD Geode and Lemote Yeeloong devices. 290 AMD Geode and Lemote Yeeloong devices.
284 291
285 If unsure, say N. 292 If unsure, say N.
286 293
287 config GPIO_BT8XX 294 config GPIO_BT8XX
288 tristate "BT8XX GPIO abuser" 295 tristate "BT8XX GPIO abuser"
289 depends on PCI && VIDEO_BT848=n 296 depends on PCI && VIDEO_BT848=n
290 help 297 help
291 The BT8xx frame grabber chip has 24 GPIO pins than can be abused 298 The BT8xx frame grabber chip has 24 GPIO pins than can be abused
292 as a cheap PCI GPIO card. 299 as a cheap PCI GPIO card.
293 300
294 This chip can be found on Miro, Hauppauge and STB TV-cards. 301 This chip can be found on Miro, Hauppauge and STB TV-cards.
295 302
296 The card needs to be physically altered for using it as a 303 The card needs to be physically altered for using it as a
297 GPIO card. For more information on how to build a GPIO card 304 GPIO card. For more information on how to build a GPIO card
298 from a BT8xx TV card, see the documentation file at 305 from a BT8xx TV card, see the documentation file at
299 Documentation/bt8xxgpio.txt 306 Documentation/bt8xxgpio.txt
300 307
301 If unsure, say N. 308 If unsure, say N.
302 309
303 config GPIO_LANGWELL 310 config GPIO_LANGWELL
304 bool "Intel Langwell/Penwell GPIO support" 311 bool "Intel Langwell/Penwell GPIO support"
305 depends on PCI 312 depends on PCI
306 help 313 help
307 Say Y here to support Intel Langwell/Penwell GPIO. 314 Say Y here to support Intel Langwell/Penwell GPIO.
308 315
309 config GPIO_TIMBERDALE 316 config GPIO_TIMBERDALE
310 bool "Support for timberdale GPIO IP" 317 bool "Support for timberdale GPIO IP"
311 depends on MFD_TIMBERDALE && GPIOLIB && HAS_IOMEM 318 depends on MFD_TIMBERDALE && GPIOLIB && HAS_IOMEM
312 ---help--- 319 ---help---
313 Add support for the GPIO IP in the timberdale FPGA. 320 Add support for the GPIO IP in the timberdale FPGA.
314 321
315 config GPIO_RDC321X 322 config GPIO_RDC321X
316 tristate "RDC R-321x GPIO support" 323 tristate "RDC R-321x GPIO support"
317 depends on PCI && GPIOLIB 324 depends on PCI && GPIOLIB
318 select MFD_CORE 325 select MFD_CORE
319 select MFD_RDC321X 326 select MFD_RDC321X
320 help 327 help
321 Support for the RDC R321x SoC GPIOs over southbridge 328 Support for the RDC R321x SoC GPIOs over southbridge
322 PCI configuration space. 329 PCI configuration space.
323 330
324 comment "SPI GPIO expanders:" 331 comment "SPI GPIO expanders:"
325 332
326 config GPIO_MAX7301 333 config GPIO_MAX7301
327 tristate "Maxim MAX7301 GPIO expander" 334 tristate "Maxim MAX7301 GPIO expander"
328 depends on SPI_MASTER 335 depends on SPI_MASTER
329 select GPIO_MAX730X 336 select GPIO_MAX730X
330 help 337 help
331 GPIO driver for Maxim MAX7301 SPI-based GPIO expander. 338 GPIO driver for Maxim MAX7301 SPI-based GPIO expander.
332 339
333 config GPIO_MCP23S08 340 config GPIO_MCP23S08
334 tristate "Microchip MCP23S08 I/O expander" 341 tristate "Microchip MCP23S08 I/O expander"
335 depends on SPI_MASTER 342 depends on SPI_MASTER
336 help 343 help
337 SPI driver for Microchip MCP23S08 I/O expander. This provides 344 SPI driver for Microchip MCP23S08 I/O expander. This provides
338 a GPIO interface supporting inputs and outputs. 345 a GPIO interface supporting inputs and outputs.
339 346
340 config GPIO_MC33880 347 config GPIO_MC33880
341 tristate "Freescale MC33880 high-side/low-side switch" 348 tristate "Freescale MC33880 high-side/low-side switch"
342 depends on SPI_MASTER 349 depends on SPI_MASTER
343 help 350 help
344 SPI driver for Freescale MC33880 high-side/low-side switch. 351 SPI driver for Freescale MC33880 high-side/low-side switch.
345 This provides GPIO interface supporting inputs and outputs. 352 This provides GPIO interface supporting inputs and outputs.
346 353
347 config GPIO_74X164 354 config GPIO_74X164
348 tristate "74x164 serial-in/parallel-out 8-bits shift register" 355 tristate "74x164 serial-in/parallel-out 8-bits shift register"
349 depends on SPI_MASTER 356 depends on SPI_MASTER
350 help 357 help
351 Platform driver for 74x164 compatible serial-in/parallel-out 358 Platform driver for 74x164 compatible serial-in/parallel-out
352 8-outputs shift registers. This driver can be used to provide access 359 8-outputs shift registers. This driver can be used to provide access
353 to more gpio outputs. 360 to more gpio outputs.
354 361
355 comment "AC97 GPIO expanders:" 362 comment "AC97 GPIO expanders:"
356 363
357 config GPIO_UCB1400 364 config GPIO_UCB1400
358 bool "Philips UCB1400 GPIO" 365 bool "Philips UCB1400 GPIO"
359 depends on UCB1400_CORE 366 depends on UCB1400_CORE
360 help 367 help
361 This enables support for the Philips UCB1400 GPIO pins. 368 This enables support for the Philips UCB1400 GPIO pins.
362 The UCB1400 is an AC97 audio codec. 369 The UCB1400 is an AC97 audio codec.
363 370
364 To compile this driver as a module, choose M here: the 371 To compile this driver as a module, choose M here: the
365 module will be called ucb1400_gpio. 372 module will be called ucb1400_gpio.
366 373
367 comment "MODULbus GPIO expanders:" 374 comment "MODULbus GPIO expanders:"
368 375
369 config GPIO_JANZ_TTL 376 config GPIO_JANZ_TTL
370 tristate "Janz VMOD-TTL Digital IO Module" 377 tristate "Janz VMOD-TTL Digital IO Module"
371 depends on MFD_JANZ_CMODIO 378 depends on MFD_JANZ_CMODIO
372 help 379 help
373 This enables support for the Janz VMOD-TTL Digital IO module. 380 This enables support for the Janz VMOD-TTL Digital IO module.
374 This driver provides support for driving the pins in output 381 This driver provides support for driving the pins in output
375 mode only. Input mode is not supported. 382 mode only. Input mode is not supported.
376 383
377 endif 384 endif
378 385
drivers/gpio/adp5588-gpio.c
1 /* 1 /*
2 * GPIO Chip driver for Analog Devices 2 * GPIO Chip driver for Analog Devices
3 * ADP5588 I/O Expander and QWERTY Keypad Controller 3 * ADP5588/ADP5587 I/O Expander and QWERTY Keypad Controller
4 * 4 *
5 * Copyright 2009 Analog Devices Inc. 5 * Copyright 2009-2010 Analog Devices Inc.
6 * 6 *
7 * Licensed under the GPL-2 or later. 7 * Licensed under the GPL-2 or later.
8 */ 8 */
9 9
10 #include <linux/module.h> 10 #include <linux/module.h>
11 #include <linux/kernel.h> 11 #include <linux/kernel.h>
12 #include <linux/slab.h> 12 #include <linux/slab.h>
13 #include <linux/init.h> 13 #include <linux/init.h>
14 #include <linux/i2c.h> 14 #include <linux/i2c.h>
15 #include <linux/gpio.h> 15 #include <linux/gpio.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
16 18
17 #include <linux/i2c/adp5588.h> 19 #include <linux/i2c/adp5588.h>
18 20
19 #define DRV_NAME "adp5588-gpio" 21 #define DRV_NAME "adp5588-gpio"
20 #define MAXGPIO 18
21 #define ADP_BANK(offs) ((offs) >> 3)
22 #define ADP_BIT(offs) (1u << ((offs) & 0x7))
23 22
23 /*
24 * Early pre 4.0 Silicon required to delay readout by at least 25ms,
25 * since the Event Counter Register updated 25ms after the interrupt
26 * asserted.
27 */
28 #define WA_DELAYED_READOUT_REVID(rev) ((rev) < 4)
29
24 struct adp5588_gpio { 30 struct adp5588_gpio {
25 struct i2c_client *client; 31 struct i2c_client *client;
26 struct gpio_chip gpio_chip; 32 struct gpio_chip gpio_chip;
27 struct mutex lock; /* protect cached dir, dat_out */ 33 struct mutex lock; /* protect cached dir, dat_out */
34 /* protect serialized access to the interrupt controller bus */
35 struct mutex irq_lock;
28 unsigned gpio_start; 36 unsigned gpio_start;
37 unsigned irq_base;
29 uint8_t dat_out[3]; 38 uint8_t dat_out[3];
30 uint8_t dir[3]; 39 uint8_t dir[3];
40 uint8_t int_lvl[3];
41 uint8_t int_en[3];
42 uint8_t irq_mask[3];
43 uint8_t irq_stat[3];
31 }; 44 };
32 45
33 static int adp5588_gpio_read(struct i2c_client *client, u8 reg) 46 static int adp5588_gpio_read(struct i2c_client *client, u8 reg)
34 { 47 {
35 int ret = i2c_smbus_read_byte_data(client, reg); 48 int ret = i2c_smbus_read_byte_data(client, reg);
36 49
37 if (ret < 0) 50 if (ret < 0)
38 dev_err(&client->dev, "Read Error\n"); 51 dev_err(&client->dev, "Read Error\n");
39 52
40 return ret; 53 return ret;
41 } 54 }
42 55
43 static int adp5588_gpio_write(struct i2c_client *client, u8 reg, u8 val) 56 static int adp5588_gpio_write(struct i2c_client *client, u8 reg, u8 val)
44 { 57 {
45 int ret = i2c_smbus_write_byte_data(client, reg, val); 58 int ret = i2c_smbus_write_byte_data(client, reg, val);
46 59
47 if (ret < 0) 60 if (ret < 0)
48 dev_err(&client->dev, "Write Error\n"); 61 dev_err(&client->dev, "Write Error\n");
49 62
50 return ret; 63 return ret;
51 } 64 }
52 65
53 static int adp5588_gpio_get_value(struct gpio_chip *chip, unsigned off) 66 static int adp5588_gpio_get_value(struct gpio_chip *chip, unsigned off)
54 { 67 {
55 struct adp5588_gpio *dev = 68 struct adp5588_gpio *dev =
56 container_of(chip, struct adp5588_gpio, gpio_chip); 69 container_of(chip, struct adp5588_gpio, gpio_chip);
57 70
58 return !!(adp5588_gpio_read(dev->client, GPIO_DAT_STAT1 + ADP_BANK(off)) 71 return !!(adp5588_gpio_read(dev->client,
59 & ADP_BIT(off)); 72 GPIO_DAT_STAT1 + ADP5588_BANK(off)) & ADP5588_BIT(off));
60 } 73 }
61 74
62 static void adp5588_gpio_set_value(struct gpio_chip *chip, 75 static void adp5588_gpio_set_value(struct gpio_chip *chip,
63 unsigned off, int val) 76 unsigned off, int val)
64 { 77 {
65 unsigned bank, bit; 78 unsigned bank, bit;
66 struct adp5588_gpio *dev = 79 struct adp5588_gpio *dev =
67 container_of(chip, struct adp5588_gpio, gpio_chip); 80 container_of(chip, struct adp5588_gpio, gpio_chip);
68 81
69 bank = ADP_BANK(off); 82 bank = ADP5588_BANK(off);
70 bit = ADP_BIT(off); 83 bit = ADP5588_BIT(off);
71 84
72 mutex_lock(&dev->lock); 85 mutex_lock(&dev->lock);
73 if (val) 86 if (val)
74 dev->dat_out[bank] |= bit; 87 dev->dat_out[bank] |= bit;
75 else 88 else
76 dev->dat_out[bank] &= ~bit; 89 dev->dat_out[bank] &= ~bit;
77 90
78 adp5588_gpio_write(dev->client, GPIO_DAT_OUT1 + bank, 91 adp5588_gpio_write(dev->client, GPIO_DAT_OUT1 + bank,
79 dev->dat_out[bank]); 92 dev->dat_out[bank]);
80 mutex_unlock(&dev->lock); 93 mutex_unlock(&dev->lock);
81 } 94 }
82 95
83 static int adp5588_gpio_direction_input(struct gpio_chip *chip, unsigned off) 96 static int adp5588_gpio_direction_input(struct gpio_chip *chip, unsigned off)
84 { 97 {
85 int ret; 98 int ret;
86 unsigned bank; 99 unsigned bank;
87 struct adp5588_gpio *dev = 100 struct adp5588_gpio *dev =
88 container_of(chip, struct adp5588_gpio, gpio_chip); 101 container_of(chip, struct adp5588_gpio, gpio_chip);
89 102
90 bank = ADP_BANK(off); 103 bank = ADP5588_BANK(off);
91 104
92 mutex_lock(&dev->lock); 105 mutex_lock(&dev->lock);
93 dev->dir[bank] &= ~ADP_BIT(off); 106 dev->dir[bank] &= ~ADP5588_BIT(off);
94 ret = adp5588_gpio_write(dev->client, GPIO_DIR1 + bank, dev->dir[bank]); 107 ret = adp5588_gpio_write(dev->client, GPIO_DIR1 + bank, dev->dir[bank]);
95 mutex_unlock(&dev->lock); 108 mutex_unlock(&dev->lock);
96 109
97 return ret; 110 return ret;
98 } 111 }
99 112
100 static int adp5588_gpio_direction_output(struct gpio_chip *chip, 113 static int adp5588_gpio_direction_output(struct gpio_chip *chip,
101 unsigned off, int val) 114 unsigned off, int val)
102 { 115 {
103 int ret; 116 int ret;
104 unsigned bank, bit; 117 unsigned bank, bit;
105 struct adp5588_gpio *dev = 118 struct adp5588_gpio *dev =
106 container_of(chip, struct adp5588_gpio, gpio_chip); 119 container_of(chip, struct adp5588_gpio, gpio_chip);
107 120
108 bank = ADP_BANK(off); 121 bank = ADP5588_BANK(off);
109 bit = ADP_BIT(off); 122 bit = ADP5588_BIT(off);
110 123
111 mutex_lock(&dev->lock); 124 mutex_lock(&dev->lock);
112 dev->dir[bank] |= bit; 125 dev->dir[bank] |= bit;
113 126
114 if (val) 127 if (val)
115 dev->dat_out[bank] |= bit; 128 dev->dat_out[bank] |= bit;
116 else 129 else
117 dev->dat_out[bank] &= ~bit; 130 dev->dat_out[bank] &= ~bit;
118 131
119 ret = adp5588_gpio_write(dev->client, GPIO_DAT_OUT1 + bank, 132 ret = adp5588_gpio_write(dev->client, GPIO_DAT_OUT1 + bank,
120 dev->dat_out[bank]); 133 dev->dat_out[bank]);
121 ret |= adp5588_gpio_write(dev->client, GPIO_DIR1 + bank, 134 ret |= adp5588_gpio_write(dev->client, GPIO_DIR1 + bank,
122 dev->dir[bank]); 135 dev->dir[bank]);
123 mutex_unlock(&dev->lock); 136 mutex_unlock(&dev->lock);
124 137
125 return ret; 138 return ret;
126 } 139 }
127 140
141 #ifdef CONFIG_GPIO_ADP5588_IRQ
142 static int adp5588_gpio_to_irq(struct gpio_chip *chip, unsigned off)
143 {
144 struct adp5588_gpio *dev =
145 container_of(chip, struct adp5588_gpio, gpio_chip);
146 return dev->irq_base + off;
147 }
148
149 static void adp5588_irq_bus_lock(unsigned int irq)
150 {
151 struct adp5588_gpio *dev = get_irq_chip_data(irq);
152 mutex_lock(&dev->irq_lock);
153 }
154
155 /*
156 * genirq core code can issue chip->mask/unmask from atomic context.
157 * This doesn't work for slow busses where an access needs to sleep.
158 * bus_sync_unlock() is therefore called outside the atomic context,
159 * syncs the current irq mask state with the slow external controller
160 * and unlocks the bus.
161 */
162
163 static void adp5588_irq_bus_sync_unlock(unsigned int irq)
164 {
165 struct adp5588_gpio *dev = get_irq_chip_data(irq);
166 int i;
167
168 for (i = 0; i <= ADP5588_BANK(ADP5588_MAXGPIO); i++)
169 if (dev->int_en[i] ^ dev->irq_mask[i]) {
170 dev->int_en[i] = dev->irq_mask[i];
171 adp5588_gpio_write(dev->client, GPIO_INT_EN1 + i,
172 dev->int_en[i]);
173 }
174
175 mutex_unlock(&dev->irq_lock);
176 }
177
178 static void adp5588_irq_mask(unsigned int irq)
179 {
180 struct adp5588_gpio *dev = get_irq_chip_data(irq);
181 unsigned gpio = irq - dev->irq_base;
182
183 dev->irq_mask[ADP5588_BANK(gpio)] &= ~ADP5588_BIT(gpio);
184 }
185
186 static void adp5588_irq_unmask(unsigned int irq)
187 {
188 struct adp5588_gpio *dev = get_irq_chip_data(irq);
189 unsigned gpio = irq - dev->irq_base;
190
191 dev->irq_mask[ADP5588_BANK(gpio)] |= ADP5588_BIT(gpio);
192 }
193
194 static int adp5588_irq_set_type(unsigned int irq, unsigned int type)
195 {
196 struct adp5588_gpio *dev = get_irq_chip_data(irq);
197 uint16_t gpio = irq - dev->irq_base;
198 unsigned bank, bit;
199
200 if ((type & IRQ_TYPE_EDGE_BOTH)) {
201 dev_err(&dev->client->dev, "irq %d: unsupported type %d\n",
202 irq, type);
203 return -EINVAL;
204 }
205
206 bank = ADP5588_BANK(gpio);
207 bit = ADP5588_BIT(gpio);
208
209 if (type & IRQ_TYPE_LEVEL_HIGH)
210 dev->int_lvl[bank] |= bit;
211 else if (type & IRQ_TYPE_LEVEL_LOW)
212 dev->int_lvl[bank] &= ~bit;
213 else
214 return -EINVAL;
215
216 adp5588_gpio_direction_input(&dev->gpio_chip, gpio);
217 adp5588_gpio_write(dev->client, GPIO_INT_LVL1 + bank,
218 dev->int_lvl[bank]);
219
220 return 0;
221 }
222
223 static struct irq_chip adp5588_irq_chip = {
224 .name = "adp5588",
225 .mask = adp5588_irq_mask,
226 .unmask = adp5588_irq_unmask,
227 .bus_lock = adp5588_irq_bus_lock,
228 .bus_sync_unlock = adp5588_irq_bus_sync_unlock,
229 .set_type = adp5588_irq_set_type,
230 };
231
232 static int adp5588_gpio_read_intstat(struct i2c_client *client, u8 *buf)
233 {
234 int ret = i2c_smbus_read_i2c_block_data(client, GPIO_INT_STAT1, 3, buf);
235
236 if (ret < 0)
237 dev_err(&client->dev, "Read INT_STAT Error\n");
238
239 return ret;
240 }
241
242 static irqreturn_t adp5588_irq_handler(int irq, void *devid)
243 {
244 struct adp5588_gpio *dev = devid;
245 unsigned status, bank, bit, pending;
246 int ret;
247 status = adp5588_gpio_read(dev->client, INT_STAT);
248
249 if (status & ADP5588_GPI_INT) {
250 ret = adp5588_gpio_read_intstat(dev->client, dev->irq_stat);
251 if (ret < 0)
252 memset(dev->irq_stat, 0, ARRAY_SIZE(dev->irq_stat));
253
254 for (bank = 0; bank <= ADP5588_BANK(ADP5588_MAXGPIO);
255 bank++, bit = 0) {
256 pending = dev->irq_stat[bank] & dev->irq_mask[bank];
257
258 while (pending) {
259 if (pending & (1 << bit)) {
260 handle_nested_irq(dev->irq_base +
261 (bank << 3) + bit);
262 pending &= ~(1 << bit);
263
264 }
265 bit++;
266 }
267 }
268 }
269
270 adp5588_gpio_write(dev->client, INT_STAT, status); /* Status is W1C */
271
272 return IRQ_HANDLED;
273 }
274
275 static int adp5588_irq_setup(struct adp5588_gpio *dev)
276 {
277 struct i2c_client *client = dev->client;
278 struct adp5588_gpio_platform_data *pdata = client->dev.platform_data;
279 unsigned gpio;
280 int ret;
281
282 adp5588_gpio_write(client, CFG, ADP5588_AUTO_INC);
283 adp5588_gpio_write(client, INT_STAT, -1); /* status is W1C */
284 adp5588_gpio_read_intstat(client, dev->irq_stat); /* read to clear */
285
286 dev->irq_base = pdata->irq_base;
287 mutex_init(&dev->irq_lock);
288
289 for (gpio = 0; gpio < dev->gpio_chip.ngpio; gpio++) {
290 int irq = gpio + dev->irq_base;
291 set_irq_chip_data(irq, dev);
292 set_irq_chip_and_handler(irq, &adp5588_irq_chip,
293 handle_level_irq);
294 set_irq_nested_thread(irq, 1);
295 #ifdef CONFIG_ARM
296 /*
297 * ARM needs us to explicitly flag the IRQ as VALID,
298 * once we do so, it will also set the noprobe.
299 */
300 set_irq_flags(irq, IRQF_VALID);
301 #else
302 set_irq_noprobe(irq);
303 #endif
304 }
305
306 ret = request_threaded_irq(client->irq,
307 NULL,
308 adp5588_irq_handler,
309 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
310 dev_name(&client->dev), dev);
311 if (ret) {
312 dev_err(&client->dev, "failed to request irq %d\n",
313 client->irq);
314 goto out;
315 }
316
317 dev->gpio_chip.to_irq = adp5588_gpio_to_irq;
318 adp5588_gpio_write(client, CFG,
319 ADP5588_AUTO_INC | ADP5588_INT_CFG | ADP5588_GPI_INT);
320
321 return 0;
322
323 out:
324 dev->irq_base = 0;
325 return ret;
326 }
327
328 static void adp5588_irq_teardown(struct adp5588_gpio *dev)
329 {
330 if (dev->irq_base)
331 free_irq(dev->client->irq, dev);
332 }
333
334 #else
335 static int adp5588_irq_setup(struct adp5588_gpio *dev)
336 {
337 struct i2c_client *client = dev->client;
338 dev_warn(&client->dev, "interrupt support not compiled in\n");
339
340 return 0;
341 }
342
343 static void adp5588_irq_teardown(struct adp5588_gpio *dev)
344 {
345 }
346 #endif /* CONFIG_GPIO_ADP5588_IRQ */
347
128 static int __devinit adp5588_gpio_probe(struct i2c_client *client, 348 static int __devinit adp5588_gpio_probe(struct i2c_client *client,
129 const struct i2c_device_id *id) 349 const struct i2c_device_id *id)
130 { 350 {
131 struct adp5588_gpio_platform_data *pdata = client->dev.platform_data; 351 struct adp5588_gpio_platform_data *pdata = client->dev.platform_data;
132 struct adp5588_gpio *dev; 352 struct adp5588_gpio *dev;
133 struct gpio_chip *gc; 353 struct gpio_chip *gc;
134 int ret, i, revid; 354 int ret, i, revid;
135 355
136 if (pdata == NULL) { 356 if (pdata == NULL) {
137 dev_err(&client->dev, "missing platform data\n"); 357 dev_err(&client->dev, "missing platform data\n");
138 return -ENODEV; 358 return -ENODEV;
139 } 359 }
140 360
141 if (!i2c_check_functionality(client->adapter, 361 if (!i2c_check_functionality(client->adapter,
142 I2C_FUNC_SMBUS_BYTE_DATA)) { 362 I2C_FUNC_SMBUS_BYTE_DATA)) {
143 dev_err(&client->dev, "SMBUS Byte Data not Supported\n"); 363 dev_err(&client->dev, "SMBUS Byte Data not Supported\n");
144 return -EIO; 364 return -EIO;
145 } 365 }
146 366
147 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 367 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
148 if (dev == NULL) { 368 if (dev == NULL) {
149 dev_err(&client->dev, "failed to alloc memory\n"); 369 dev_err(&client->dev, "failed to alloc memory\n");
150 return -ENOMEM; 370 return -ENOMEM;
151 } 371 }
152 372
153 dev->client = client; 373 dev->client = client;
154 374
155 gc = &dev->gpio_chip; 375 gc = &dev->gpio_chip;
156 gc->direction_input = adp5588_gpio_direction_input; 376 gc->direction_input = adp5588_gpio_direction_input;
157 gc->direction_output = adp5588_gpio_direction_output; 377 gc->direction_output = adp5588_gpio_direction_output;
158 gc->get = adp5588_gpio_get_value; 378 gc->get = adp5588_gpio_get_value;
159 gc->set = adp5588_gpio_set_value; 379 gc->set = adp5588_gpio_set_value;
160 gc->can_sleep = 1; 380 gc->can_sleep = 1;
161 381
162 gc->base = pdata->gpio_start; 382 gc->base = pdata->gpio_start;
163 gc->ngpio = MAXGPIO; 383 gc->ngpio = ADP5588_MAXGPIO;
164 gc->label = client->name; 384 gc->label = client->name;
165 gc->owner = THIS_MODULE; 385 gc->owner = THIS_MODULE;
166 386
167 mutex_init(&dev->lock); 387 mutex_init(&dev->lock);
168 388
169
170 ret = adp5588_gpio_read(dev->client, DEV_ID); 389 ret = adp5588_gpio_read(dev->client, DEV_ID);
171 if (ret < 0) 390 if (ret < 0)
172 goto err; 391 goto err;
173 392
174 revid = ret & ADP5588_DEVICE_ID_MASK; 393 revid = ret & ADP5588_DEVICE_ID_MASK;
175 394
176 for (i = 0, ret = 0; i <= ADP_BANK(MAXGPIO); i++) { 395 for (i = 0, ret = 0; i <= ADP5588_BANK(ADP5588_MAXGPIO); i++) {
177 dev->dat_out[i] = adp5588_gpio_read(client, GPIO_DAT_OUT1 + i); 396 dev->dat_out[i] = adp5588_gpio_read(client, GPIO_DAT_OUT1 + i);
178 dev->dir[i] = adp5588_gpio_read(client, GPIO_DIR1 + i); 397 dev->dir[i] = adp5588_gpio_read(client, GPIO_DIR1 + i);
179 ret |= adp5588_gpio_write(client, KP_GPIO1 + i, 0); 398 ret |= adp5588_gpio_write(client, KP_GPIO1 + i, 0);
180 ret |= adp5588_gpio_write(client, GPIO_PULL1 + i, 399 ret |= adp5588_gpio_write(client, GPIO_PULL1 + i,
181 (pdata->pullup_dis_mask >> (8 * i)) & 0xFF); 400 (pdata->pullup_dis_mask >> (8 * i)) & 0xFF);
182 401 ret |= adp5588_gpio_write(client, GPIO_INT_EN1 + i, 0);
183 if (ret) 402 if (ret)
184 goto err; 403 goto err;
185 } 404 }
186 405
406 if (pdata->irq_base) {
407 if (WA_DELAYED_READOUT_REVID(revid)) {
408 dev_warn(&client->dev, "GPIO int not supported\n");
409 } else {
410 ret = adp5588_irq_setup(dev);
411 if (ret)
412 goto err;
413 }
414 }
415
187 ret = gpiochip_add(&dev->gpio_chip); 416 ret = gpiochip_add(&dev->gpio_chip);
188 if (ret) 417 if (ret)
189 goto err; 418 goto err_irq;
190 419
191 dev_info(&client->dev, "gpios %d..%d on a %s Rev. %d\n", 420 dev_info(&client->dev, "gpios %d..%d (IRQ Base %d) on a %s Rev. %d\n",
192 gc->base, gc->base + gc->ngpio - 1, 421 gc->base, gc->base + gc->ngpio - 1,
193 client->name, revid); 422 pdata->irq_base, client->name, revid);
194 423
195 if (pdata->setup) { 424 if (pdata->setup) {
196 ret = pdata->setup(client, gc->base, gc->ngpio, pdata->context); 425 ret = pdata->setup(client, gc->base, gc->ngpio, pdata->context);
197 if (ret < 0) 426 if (ret < 0)
198 dev_warn(&client->dev, "setup failed, %d\n", ret); 427 dev_warn(&client->dev, "setup failed, %d\n", ret);
199 } 428 }
200 429
201 i2c_set_clientdata(client, dev); 430 i2c_set_clientdata(client, dev);
431
202 return 0; 432 return 0;
203 433
434 err_irq:
435 adp5588_irq_teardown(dev);
204 err: 436 err:
205 kfree(dev); 437 kfree(dev);
206 return ret; 438 return ret;
207 } 439 }
208 440
209 static int __devexit adp5588_gpio_remove(struct i2c_client *client) 441 static int __devexit adp5588_gpio_remove(struct i2c_client *client)
210 { 442 {
211 struct adp5588_gpio_platform_data *pdata = client->dev.platform_data; 443 struct adp5588_gpio_platform_data *pdata = client->dev.platform_data;
212 struct adp5588_gpio *dev = i2c_get_clientdata(client); 444 struct adp5588_gpio *dev = i2c_get_clientdata(client);
213 int ret; 445 int ret;
214 446
215 if (pdata->teardown) { 447 if (pdata->teardown) {
216 ret = pdata->teardown(client, 448 ret = pdata->teardown(client,
217 dev->gpio_chip.base, dev->gpio_chip.ngpio, 449 dev->gpio_chip.base, dev->gpio_chip.ngpio,
218 pdata->context); 450 pdata->context);
219 if (ret < 0) { 451 if (ret < 0) {
220 dev_err(&client->dev, "teardown failed %d\n", ret); 452 dev_err(&client->dev, "teardown failed %d\n", ret);
221 return ret; 453 return ret;
222 } 454 }
223 } 455 }
456
457 if (dev->irq_base)
458 free_irq(dev->client->irq, dev);
224 459
225 ret = gpiochip_remove(&dev->gpio_chip); 460 ret = gpiochip_remove(&dev->gpio_chip);
226 if (ret) { 461 if (ret) {
227 dev_err(&client->dev, "gpiochip_remove failed %d\n", ret); 462 dev_err(&client->dev, "gpiochip_remove failed %d\n", ret);
228 return ret; 463 return ret;
229 } 464 }
230 465
231 kfree(dev); 466 kfree(dev);
232 return 0; 467 return 0;
233 } 468 }
234 469
235 static const struct i2c_device_id adp5588_gpio_id[] = { 470 static const struct i2c_device_id adp5588_gpio_id[] = {
236 {DRV_NAME, 0}, 471 {DRV_NAME, 0},
237 {} 472 {}
238 }; 473 };
239 474
240 MODULE_DEVICE_TABLE(i2c, adp5588_gpio_id); 475 MODULE_DEVICE_TABLE(i2c, adp5588_gpio_id);
241 476
242 static struct i2c_driver adp5588_gpio_driver = { 477 static struct i2c_driver adp5588_gpio_driver = {
243 .driver = { 478 .driver = {
244 .name = DRV_NAME, 479 .name = DRV_NAME,
245 }, 480 },
246 .probe = adp5588_gpio_probe, 481 .probe = adp5588_gpio_probe,
247 .remove = __devexit_p(adp5588_gpio_remove), 482 .remove = __devexit_p(adp5588_gpio_remove),
248 .id_table = adp5588_gpio_id, 483 .id_table = adp5588_gpio_id,
249 }; 484 };
250 485
251 static int __init adp5588_gpio_init(void) 486 static int __init adp5588_gpio_init(void)
252 { 487 {
253 return i2c_add_driver(&adp5588_gpio_driver); 488 return i2c_add_driver(&adp5588_gpio_driver);
254 } 489 }
255 490
256 module_init(adp5588_gpio_init); 491 module_init(adp5588_gpio_init);
257 492
258 static void __exit adp5588_gpio_exit(void) 493 static void __exit adp5588_gpio_exit(void)
259 { 494 {
260 i2c_del_driver(&adp5588_gpio_driver); 495 i2c_del_driver(&adp5588_gpio_driver);
261 } 496 }
262 497
263 module_exit(adp5588_gpio_exit); 498 module_exit(adp5588_gpio_exit);
264 499
include/linux/i2c/adp5588.h
1 /* 1 /*
2 * Analog Devices ADP5588 I/O Expander and QWERTY Keypad Controller 2 * Analog Devices ADP5588 I/O Expander and QWERTY Keypad Controller
3 * 3 *
4 * Copyright 2009 Analog Devices Inc. 4 * Copyright 2009 Analog Devices Inc.
5 * 5 *
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
9 #ifndef _ADP5588_H 9 #ifndef _ADP5588_H
10 #define _ADP5588_H 10 #define _ADP5588_H
11 11
12 #define DEV_ID 0x00 /* Device ID */ 12 #define DEV_ID 0x00 /* Device ID */
13 #define CFG 0x01 /* Configuration Register1 */ 13 #define CFG 0x01 /* Configuration Register1 */
14 #define INT_STAT 0x02 /* Interrupt Status Register */ 14 #define INT_STAT 0x02 /* Interrupt Status Register */
15 #define KEY_LCK_EC_STAT 0x03 /* Key Lock and Event Counter Register */ 15 #define KEY_LCK_EC_STAT 0x03 /* Key Lock and Event Counter Register */
16 #define Key_EVENTA 0x04 /* Key Event Register A */ 16 #define Key_EVENTA 0x04 /* Key Event Register A */
17 #define Key_EVENTB 0x05 /* Key Event Register B */ 17 #define Key_EVENTB 0x05 /* Key Event Register B */
18 #define Key_EVENTC 0x06 /* Key Event Register C */ 18 #define Key_EVENTC 0x06 /* Key Event Register C */
19 #define Key_EVENTD 0x07 /* Key Event Register D */ 19 #define Key_EVENTD 0x07 /* Key Event Register D */
20 #define Key_EVENTE 0x08 /* Key Event Register E */ 20 #define Key_EVENTE 0x08 /* Key Event Register E */
21 #define Key_EVENTF 0x09 /* Key Event Register F */ 21 #define Key_EVENTF 0x09 /* Key Event Register F */
22 #define Key_EVENTG 0x0A /* Key Event Register G */ 22 #define Key_EVENTG 0x0A /* Key Event Register G */
23 #define Key_EVENTH 0x0B /* Key Event Register H */ 23 #define Key_EVENTH 0x0B /* Key Event Register H */
24 #define Key_EVENTI 0x0C /* Key Event Register I */ 24 #define Key_EVENTI 0x0C /* Key Event Register I */
25 #define Key_EVENTJ 0x0D /* Key Event Register J */ 25 #define Key_EVENTJ 0x0D /* Key Event Register J */
26 #define KP_LCK_TMR 0x0E /* Keypad Lock1 to Lock2 Timer */ 26 #define KP_LCK_TMR 0x0E /* Keypad Lock1 to Lock2 Timer */
27 #define UNLOCK1 0x0F /* Unlock Key1 */ 27 #define UNLOCK1 0x0F /* Unlock Key1 */
28 #define UNLOCK2 0x10 /* Unlock Key2 */ 28 #define UNLOCK2 0x10 /* Unlock Key2 */
29 #define GPIO_INT_STAT1 0x11 /* GPIO Interrupt Status */ 29 #define GPIO_INT_STAT1 0x11 /* GPIO Interrupt Status */
30 #define GPIO_INT_STAT2 0x12 /* GPIO Interrupt Status */ 30 #define GPIO_INT_STAT2 0x12 /* GPIO Interrupt Status */
31 #define GPIO_INT_STAT3 0x13 /* GPIO Interrupt Status */ 31 #define GPIO_INT_STAT3 0x13 /* GPIO Interrupt Status */
32 #define GPIO_DAT_STAT1 0x14 /* GPIO Data Status, Read twice to clear */ 32 #define GPIO_DAT_STAT1 0x14 /* GPIO Data Status, Read twice to clear */
33 #define GPIO_DAT_STAT2 0x15 /* GPIO Data Status, Read twice to clear */ 33 #define GPIO_DAT_STAT2 0x15 /* GPIO Data Status, Read twice to clear */
34 #define GPIO_DAT_STAT3 0x16 /* GPIO Data Status, Read twice to clear */ 34 #define GPIO_DAT_STAT3 0x16 /* GPIO Data Status, Read twice to clear */
35 #define GPIO_DAT_OUT1 0x17 /* GPIO DATA OUT */ 35 #define GPIO_DAT_OUT1 0x17 /* GPIO DATA OUT */
36 #define GPIO_DAT_OUT2 0x18 /* GPIO DATA OUT */ 36 #define GPIO_DAT_OUT2 0x18 /* GPIO DATA OUT */
37 #define GPIO_DAT_OUT3 0x19 /* GPIO DATA OUT */ 37 #define GPIO_DAT_OUT3 0x19 /* GPIO DATA OUT */
38 #define GPIO_INT_EN1 0x1A /* GPIO Interrupt Enable */ 38 #define GPIO_INT_EN1 0x1A /* GPIO Interrupt Enable */
39 #define GPIO_INT_EN2 0x1B /* GPIO Interrupt Enable */ 39 #define GPIO_INT_EN2 0x1B /* GPIO Interrupt Enable */
40 #define GPIO_INT_EN3 0x1C /* GPIO Interrupt Enable */ 40 #define GPIO_INT_EN3 0x1C /* GPIO Interrupt Enable */
41 #define KP_GPIO1 0x1D /* Keypad or GPIO Selection */ 41 #define KP_GPIO1 0x1D /* Keypad or GPIO Selection */
42 #define KP_GPIO2 0x1E /* Keypad or GPIO Selection */ 42 #define KP_GPIO2 0x1E /* Keypad or GPIO Selection */
43 #define KP_GPIO3 0x1F /* Keypad or GPIO Selection */ 43 #define KP_GPIO3 0x1F /* Keypad or GPIO Selection */
44 #define GPI_EM1 0x20 /* GPI Event Mode 1 */ 44 #define GPI_EM1 0x20 /* GPI Event Mode 1 */
45 #define GPI_EM2 0x21 /* GPI Event Mode 2 */ 45 #define GPI_EM2 0x21 /* GPI Event Mode 2 */
46 #define GPI_EM3 0x22 /* GPI Event Mode 3 */ 46 #define GPI_EM3 0x22 /* GPI Event Mode 3 */
47 #define GPIO_DIR1 0x23 /* GPIO Data Direction */ 47 #define GPIO_DIR1 0x23 /* GPIO Data Direction */
48 #define GPIO_DIR2 0x24 /* GPIO Data Direction */ 48 #define GPIO_DIR2 0x24 /* GPIO Data Direction */
49 #define GPIO_DIR3 0x25 /* GPIO Data Direction */ 49 #define GPIO_DIR3 0x25 /* GPIO Data Direction */
50 #define GPIO_INT_LVL1 0x26 /* GPIO Edge/Level Detect */ 50 #define GPIO_INT_LVL1 0x26 /* GPIO Edge/Level Detect */
51 #define GPIO_INT_LVL2 0x27 /* GPIO Edge/Level Detect */ 51 #define GPIO_INT_LVL2 0x27 /* GPIO Edge/Level Detect */
52 #define GPIO_INT_LVL3 0x28 /* GPIO Edge/Level Detect */ 52 #define GPIO_INT_LVL3 0x28 /* GPIO Edge/Level Detect */
53 #define Debounce_DIS1 0x29 /* Debounce Disable */ 53 #define Debounce_DIS1 0x29 /* Debounce Disable */
54 #define Debounce_DIS2 0x2A /* Debounce Disable */ 54 #define Debounce_DIS2 0x2A /* Debounce Disable */
55 #define Debounce_DIS3 0x2B /* Debounce Disable */ 55 #define Debounce_DIS3 0x2B /* Debounce Disable */
56 #define GPIO_PULL1 0x2C /* GPIO Pull Disable */ 56 #define GPIO_PULL1 0x2C /* GPIO Pull Disable */
57 #define GPIO_PULL2 0x2D /* GPIO Pull Disable */ 57 #define GPIO_PULL2 0x2D /* GPIO Pull Disable */
58 #define GPIO_PULL3 0x2E /* GPIO Pull Disable */ 58 #define GPIO_PULL3 0x2E /* GPIO Pull Disable */
59 #define CMP_CFG_STAT 0x30 /* Comparator Configuration and Status Register */ 59 #define CMP_CFG_STAT 0x30 /* Comparator Configuration and Status Register */
60 #define CMP_CONFG_SENS1 0x31 /* Sensor1 Comparator Configuration Register */ 60 #define CMP_CONFG_SENS1 0x31 /* Sensor1 Comparator Configuration Register */
61 #define CMP_CONFG_SENS2 0x32 /* L2 Light Sensor Reference Level, Output Falling for Sensor 1 */ 61 #define CMP_CONFG_SENS2 0x32 /* L2 Light Sensor Reference Level, Output Falling for Sensor 1 */
62 #define CMP1_LVL2_TRIP 0x33 /* L2 Light Sensor Hysteresis (Active when Output Rising) for Sensor 1 */ 62 #define CMP1_LVL2_TRIP 0x33 /* L2 Light Sensor Hysteresis (Active when Output Rising) for Sensor 1 */
63 #define CMP1_LVL2_HYS 0x34 /* L3 Light Sensor Reference Level, Output Falling For Sensor 1 */ 63 #define CMP1_LVL2_HYS 0x34 /* L3 Light Sensor Reference Level, Output Falling For Sensor 1 */
64 #define CMP1_LVL3_TRIP 0x35 /* L3 Light Sensor Hysteresis (Active when Output Rising) For Sensor 1 */ 64 #define CMP1_LVL3_TRIP 0x35 /* L3 Light Sensor Hysteresis (Active when Output Rising) For Sensor 1 */
65 #define CMP1_LVL3_HYS 0x36 /* Sensor 2 Comparator Configuration Register */ 65 #define CMP1_LVL3_HYS 0x36 /* Sensor 2 Comparator Configuration Register */
66 #define CMP2_LVL2_TRIP 0x37 /* L2 Light Sensor Reference Level, Output Falling for Sensor 2 */ 66 #define CMP2_LVL2_TRIP 0x37 /* L2 Light Sensor Reference Level, Output Falling for Sensor 2 */
67 #define CMP2_LVL2_HYS 0x38 /* L2 Light Sensor Hysteresis (Active when Output Rising) for Sensor 2 */ 67 #define CMP2_LVL2_HYS 0x38 /* L2 Light Sensor Hysteresis (Active when Output Rising) for Sensor 2 */
68 #define CMP2_LVL3_TRIP 0x39 /* L3 Light Sensor Reference Level, Output Falling For Sensor 2 */ 68 #define CMP2_LVL3_TRIP 0x39 /* L3 Light Sensor Reference Level, Output Falling For Sensor 2 */
69 #define CMP2_LVL3_HYS 0x3A /* L3 Light Sensor Hysteresis (Active when Output Rising) For Sensor 2 */ 69 #define CMP2_LVL3_HYS 0x3A /* L3 Light Sensor Hysteresis (Active when Output Rising) For Sensor 2 */
70 #define CMP1_ADC_DAT_R1 0x3B /* Comparator 1 ADC data Register1 */ 70 #define CMP1_ADC_DAT_R1 0x3B /* Comparator 1 ADC data Register1 */
71 #define CMP1_ADC_DAT_R2 0x3C /* Comparator 1 ADC data Register2 */ 71 #define CMP1_ADC_DAT_R2 0x3C /* Comparator 1 ADC data Register2 */
72 #define CMP2_ADC_DAT_R1 0x3D /* Comparator 2 ADC data Register1 */ 72 #define CMP2_ADC_DAT_R1 0x3D /* Comparator 2 ADC data Register1 */
73 #define CMP2_ADC_DAT_R2 0x3E /* Comparator 2 ADC data Register2 */ 73 #define CMP2_ADC_DAT_R2 0x3E /* Comparator 2 ADC data Register2 */
74 74
75 #define ADP5588_DEVICE_ID_MASK 0xF 75 #define ADP5588_DEVICE_ID_MASK 0xF
76 76
77 /* Configuration Register1 */
78 #define ADP5588_AUTO_INC (1 << 7)
79 #define ADP5588_GPIEM_CFG (1 << 6)
80 #define ADP5588_INT_CFG (1 << 4)
81 #define ADP5588_GPI_IEN (1 << 1)
82
83 /* Interrupt Status Register */
84 #define ADP5588_GPI_INT (1 << 1)
85 #define ADP5588_KE_INT (1 << 0)
86
87 #define ADP5588_MAXGPIO 18
88 #define ADP5588_BANK(offs) ((offs) >> 3)
89 #define ADP5588_BIT(offs) (1u << ((offs) & 0x7))
90
77 /* Put one of these structures in i2c_board_info platform_data */ 91 /* Put one of these structures in i2c_board_info platform_data */
78 92
79 #define ADP5588_KEYMAPSIZE 80 93 #define ADP5588_KEYMAPSIZE 80
80 94
81 #define GPI_PIN_ROW0 97 95 #define GPI_PIN_ROW0 97
82 #define GPI_PIN_ROW1 98 96 #define GPI_PIN_ROW1 98
83 #define GPI_PIN_ROW2 99 97 #define GPI_PIN_ROW2 99
84 #define GPI_PIN_ROW3 100 98 #define GPI_PIN_ROW3 100
85 #define GPI_PIN_ROW4 101 99 #define GPI_PIN_ROW4 101
86 #define GPI_PIN_ROW5 102 100 #define GPI_PIN_ROW5 102
87 #define GPI_PIN_ROW6 103 101 #define GPI_PIN_ROW6 103
88 #define GPI_PIN_ROW7 104 102 #define GPI_PIN_ROW7 104
89 #define GPI_PIN_COL0 105 103 #define GPI_PIN_COL0 105
90 #define GPI_PIN_COL1 106 104 #define GPI_PIN_COL1 106
91 #define GPI_PIN_COL2 107 105 #define GPI_PIN_COL2 107
92 #define GPI_PIN_COL3 108 106 #define GPI_PIN_COL3 108
93 #define GPI_PIN_COL4 109 107 #define GPI_PIN_COL4 109
94 #define GPI_PIN_COL5 110 108 #define GPI_PIN_COL5 110
95 #define GPI_PIN_COL6 111 109 #define GPI_PIN_COL6 111
96 #define GPI_PIN_COL7 112 110 #define GPI_PIN_COL7 112
97 #define GPI_PIN_COL8 113 111 #define GPI_PIN_COL8 113
98 #define GPI_PIN_COL9 114 112 #define GPI_PIN_COL9 114
99 113
100 #define GPI_PIN_ROW_BASE GPI_PIN_ROW0 114 #define GPI_PIN_ROW_BASE GPI_PIN_ROW0
101 #define GPI_PIN_ROW_END GPI_PIN_ROW7 115 #define GPI_PIN_ROW_END GPI_PIN_ROW7
102 #define GPI_PIN_COL_BASE GPI_PIN_COL0 116 #define GPI_PIN_COL_BASE GPI_PIN_COL0
103 #define GPI_PIN_COL_END GPI_PIN_COL9 117 #define GPI_PIN_COL_END GPI_PIN_COL9
104 118
105 #define GPI_PIN_BASE GPI_PIN_ROW_BASE 119 #define GPI_PIN_BASE GPI_PIN_ROW_BASE
106 #define GPI_PIN_END GPI_PIN_COL_END 120 #define GPI_PIN_END GPI_PIN_COL_END
107 121
108 #define ADP5588_GPIMAPSIZE_MAX (GPI_PIN_END - GPI_PIN_BASE + 1) 122 #define ADP5588_GPIMAPSIZE_MAX (GPI_PIN_END - GPI_PIN_BASE + 1)
109 123
110 struct adp5588_gpi_map { 124 struct adp5588_gpi_map {
111 unsigned short pin; 125 unsigned short pin;
112 unsigned short sw_evt; 126 unsigned short sw_evt;
113 }; 127 };
114 128
115 struct adp5588_kpad_platform_data { 129 struct adp5588_kpad_platform_data {
116 int rows; /* Number of rows */ 130 int rows; /* Number of rows */
117 int cols; /* Number of columns */ 131 int cols; /* Number of columns */
118 const unsigned short *keymap; /* Pointer to keymap */ 132 const unsigned short *keymap; /* Pointer to keymap */
119 unsigned short keymapsize; /* Keymap size */ 133 unsigned short keymapsize; /* Keymap size */
120 unsigned repeat:1; /* Enable key repeat */ 134 unsigned repeat:1; /* Enable key repeat */
121 unsigned en_keylock:1; /* Enable Key Lock feature */ 135 unsigned en_keylock:1; /* Enable Key Lock feature */
122 unsigned short unlock_key1; /* Unlock Key 1 */ 136 unsigned short unlock_key1; /* Unlock Key 1 */
123 unsigned short unlock_key2; /* Unlock Key 2 */ 137 unsigned short unlock_key2; /* Unlock Key 2 */
124 const struct adp5588_gpi_map *gpimap; 138 const struct adp5588_gpi_map *gpimap;
125 unsigned short gpimapsize; 139 unsigned short gpimapsize;
126 const struct adp5588_gpio_platform_data *gpio_data; 140 const struct adp5588_gpio_platform_data *gpio_data;
127 }; 141 };
128 142
129 struct adp5588_gpio_platform_data { 143 struct adp5588_gpio_platform_data {
130 unsigned gpio_start; /* GPIO Chip base # */ 144 unsigned gpio_start; /* GPIO Chip base # */
145 unsigned irq_base; /* interrupt base # */
131 unsigned pullup_dis_mask; /* Pull-Up Disable Mask */ 146 unsigned pullup_dis_mask; /* Pull-Up Disable Mask */
132 int (*setup)(struct i2c_client *client, 147 int (*setup)(struct i2c_client *client,
133 int gpio, unsigned ngpio, 148 int gpio, unsigned ngpio,
134 void *context); 149 void *context);
135 int (*teardown)(struct i2c_client *client, 150 int (*teardown)(struct i2c_client *client,
136 int gpio, unsigned ngpio, 151 int gpio, unsigned ngpio,
137 void *context); 152 void *context);
138 void *context; 153 void *context;
139 }; 154 };
140 155
141 #endif 156 #endif
142 157