Doug / smarc-fsl-linux-kernel

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/* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */

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/* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */

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/*

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/*

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Written 1998-2001 by Donald Becker.

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Written 1998-2001 by Donald Becker.

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Current Maintainer: Roger Luethi <rl@hellgate.ch>

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Current Maintainer: Roger Luethi <rl@hellgate.ch>

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This software may be used and distributed according to the terms of

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This software may be used and distributed according to the terms of

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the GNU General Public License (GPL), incorporated herein by reference.

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the GNU General Public License (GPL), incorporated herein by reference.

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Drivers based on or derived from this code fall under the GPL and must

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Drivers based on or derived from this code fall under the GPL and must

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retain the authorship, copyright and license notice. This file is not

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retain the authorship, copyright and license notice. This file is not

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a complete program and may only be used when the entire operating

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a complete program and may only be used when the entire operating

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system is licensed under the GPL.

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system is licensed under the GPL.

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This driver is designed for the VIA VT86C100A Rhine-I.

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This driver is designed for the VIA VT86C100A Rhine-I.

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It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM

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It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM

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and management NIC 6105M).

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and management NIC 6105M).

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The author may be reached as becker@scyld.com, or C/O

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The author may be reached as becker@scyld.com, or C/O

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Scyld Computing Corporation

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Scyld Computing Corporation

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410 Severn Ave., Suite 210

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410 Severn Ave., Suite 210

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Annapolis MD 21403

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Annapolis MD 21403

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This driver contains some changes from the original Donald Becker

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This driver contains some changes from the original Donald Becker

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version. He may or may not be interested in bug reports on this

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version. He may or may not be interested in bug reports on this

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code. You can find his versions at:

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code. You can find his versions at:

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http://www.scyld.com/network/via-rhine.html

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http://www.scyld.com/network/via-rhine.html

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[link no longer provides useful info -jgarzik]

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[link no longer provides useful info -jgarzik]

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*/

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*/

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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

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#define DRV_NAME "via-rhine"

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#define DRV_NAME "via-rhine"

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#define DRV_VERSION "1.5.0"

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#define DRV_VERSION "1.5.0"

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#define DRV_RELDATE "2010-10-09"

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#define DRV_RELDATE "2010-10-09"

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/* A few user-configurable values.

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/* A few user-configurable values.

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These may be modified when a driver module is loaded. */

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These may be modified when a driver module is loaded. */

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#define DEBUG

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#define DEBUG

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static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */

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static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */

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static int max_interrupt_work = 20;

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static int max_interrupt_work = 20;

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/* Set the copy breakpoint for the copy-only-tiny-frames scheme.

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/* Set the copy breakpoint for the copy-only-tiny-frames scheme.

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Setting to > 1518 effectively disables this feature. */

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Setting to > 1518 effectively disables this feature. */

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#if defined(__alpha__) || defined(__arm__) || defined(__hppa__) || \

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#if defined(__alpha__) || defined(__arm__) || defined(__hppa__) || \

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defined(CONFIG_SPARC) || defined(__ia64__) || \

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defined(CONFIG_SPARC) || defined(__ia64__) || \

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defined(__sh__) || defined(__mips__)

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defined(__sh__) || defined(__mips__)

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static int rx_copybreak = 1518;

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static int rx_copybreak = 1518;

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#else

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#else

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static int rx_copybreak;

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static int rx_copybreak;

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#endif

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#endif

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/* Work-around for broken BIOSes: they are unable to get the chip back out of

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/* Work-around for broken BIOSes: they are unable to get the chip back out of

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power state D3 so PXE booting fails. bootparam(7): via-rhine.avoid_D3=1 */

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power state D3 so PXE booting fails. bootparam(7): via-rhine.avoid_D3=1 */

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static int avoid_D3;

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static int avoid_D3;

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/*

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/*

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* In case you are looking for 'options[]' or 'full_duplex[]', they

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* In case you are looking for 'options[]' or 'full_duplex[]', they

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* are gone. Use ethtool(8) instead.

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* are gone. Use ethtool(8) instead.

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*/

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*/

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/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).

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/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).

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The Rhine has a 64 element 8390-like hash table. */

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The Rhine has a 64 element 8390-like hash table. */

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static const int multicast_filter_limit = 32;

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static const int multicast_filter_limit = 32;

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/* Operational parameters that are set at compile time. */

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/* Operational parameters that are set at compile time. */

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/* Keep the ring sizes a power of two for compile efficiency.

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/* Keep the ring sizes a power of two for compile efficiency.

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The compiler will convert <unsigned>'%'<2^N> into a bit mask.

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The compiler will convert <unsigned>'%'<2^N> into a bit mask.

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Making the Tx ring too large decreases the effectiveness of channel

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Making the Tx ring too large decreases the effectiveness of channel

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bonding and packet priority.

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bonding and packet priority.

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There are no ill effects from too-large receive rings. */

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There are no ill effects from too-large receive rings. */

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#define TX_RING_SIZE 16

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#define TX_RING_SIZE 16

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#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */

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#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */

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#define RX_RING_SIZE 64

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#define RX_RING_SIZE 64

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/* Operational parameters that usually are not changed. */

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/* Operational parameters that usually are not changed. */

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/* Time in jiffies before concluding the transmitter is hung. */

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/* Time in jiffies before concluding the transmitter is hung. */

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#define TX_TIMEOUT (2*HZ)

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#define TX_TIMEOUT (2*HZ)

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#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/

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#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/

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#include <linux/module.h>

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#include <linux/module.h>

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#include <linux/moduleparam.h>

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#include <linux/moduleparam.h>

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#include <linux/kernel.h>

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#include <linux/kernel.h>

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#include <linux/string.h>

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#include <linux/string.h>

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#include <linux/timer.h>

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#include <linux/timer.h>

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#include <linux/errno.h>

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#include <linux/errno.h>

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#include <linux/ioport.h>

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#include <linux/ioport.h>

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#include <linux/interrupt.h>

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#include <linux/interrupt.h>

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#include <linux/pci.h>

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#include <linux/pci.h>

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#include <linux/dma-mapping.h>

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#include <linux/dma-mapping.h>

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#include <linux/netdevice.h>

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#include <linux/netdevice.h>

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#include <linux/etherdevice.h>

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#include <linux/etherdevice.h>

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#include <linux/skbuff.h>

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#include <linux/skbuff.h>

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#include <linux/init.h>

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#include <linux/init.h>

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#include <linux/delay.h>

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#include <linux/delay.h>

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#include <linux/mii.h>

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#include <linux/mii.h>

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#include <linux/ethtool.h>

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#include <linux/ethtool.h>

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#include <linux/crc32.h>

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#include <linux/crc32.h>

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#include <linux/if_vlan.h>

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#include <linux/if_vlan.h>

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#include <linux/bitops.h>

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#include <linux/bitops.h>

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#include <linux/workqueue.h>

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#include <linux/workqueue.h>

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#include <asm/processor.h> /* Processor type for cache alignment. */

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#include <asm/processor.h> /* Processor type for cache alignment. */

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#include <asm/io.h>

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#include <asm/io.h>

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#include <asm/irq.h>

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#include <asm/irq.h>

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#include <asm/uaccess.h>

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#include <asm/uaccess.h>

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#include <linux/dmi.h>

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#include <linux/dmi.h>

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/* These identify the driver base version and may not be removed. */

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/* These identify the driver base version and may not be removed. */

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static const char version[] __devinitconst =

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static const char version[] __devinitconst =

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"v1.10-LK" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker";

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"v1.10-LK" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker";

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/* This driver was written to use PCI memory space. Some early versions

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/* This driver was written to use PCI memory space. Some early versions

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of the Rhine may only work correctly with I/O space accesses. */

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of the Rhine may only work correctly with I/O space accesses. */

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#ifdef CONFIG_VIA_RHINE_MMIO

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#ifdef CONFIG_VIA_RHINE_MMIO

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#define USE_MMIO

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#define USE_MMIO

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#else

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#else

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#endif

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#endif

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MODULE_AUTHOR("Donald Becker <becker@scyld.com>");

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MODULE_AUTHOR("Donald Becker <becker@scyld.com>");

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MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver");

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MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver");

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MODULE_LICENSE("GPL");

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MODULE_LICENSE("GPL");

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module_param(max_interrupt_work, int, 0);

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module_param(max_interrupt_work, int, 0);

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module_param(debug, int, 0);

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module_param(debug, int, 0);

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module_param(rx_copybreak, int, 0);

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module_param(rx_copybreak, int, 0);

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module_param(avoid_D3, bool, 0);

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module_param(avoid_D3, bool, 0);

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MODULE_PARM_DESC(max_interrupt_work, "VIA Rhine maximum events handled per interrupt");

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MODULE_PARM_DESC(max_interrupt_work, "VIA Rhine maximum events handled per interrupt");

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MODULE_PARM_DESC(debug, "VIA Rhine debug level (0-7)");

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MODULE_PARM_DESC(debug, "VIA Rhine debug level (0-7)");

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MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");

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MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");

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MODULE_PARM_DESC(avoid_D3, "Avoid power state D3 (work-around for broken BIOSes)");

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MODULE_PARM_DESC(avoid_D3, "Avoid power state D3 (work-around for broken BIOSes)");

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#define MCAM_SIZE 32

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#define MCAM_SIZE 32

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#define VCAM_SIZE 32

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#define VCAM_SIZE 32

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/*

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/*

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Theory of Operation

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Theory of Operation

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I. Board Compatibility

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I. Board Compatibility

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This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet

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This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet

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controller.

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controller.

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II. Board-specific settings

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II. Board-specific settings

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Boards with this chip are functional only in a bus-master PCI slot.

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Boards with this chip are functional only in a bus-master PCI slot.

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Many operational settings are loaded from the EEPROM to the Config word at

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Many operational settings are loaded from the EEPROM to the Config word at

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offset 0x78. For most of these settings, this driver assumes that they are

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offset 0x78. For most of these settings, this driver assumes that they are

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correct.

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correct.

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If this driver is compiled to use PCI memory space operations the EEPROM

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If this driver is compiled to use PCI memory space operations the EEPROM

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must be configured to enable memory ops.

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must be configured to enable memory ops.

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III. Driver operation

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III. Driver operation

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IIIa. Ring buffers

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IIIa. Ring buffers

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This driver uses two statically allocated fixed-size descriptor lists

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This driver uses two statically allocated fixed-size descriptor lists

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formed into rings by a branch from the final descriptor to the beginning of

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formed into rings by a branch from the final descriptor to the beginning of

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the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.

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the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.

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IIIb/c. Transmit/Receive Structure

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IIIb/c. Transmit/Receive Structure

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This driver attempts to use a zero-copy receive and transmit scheme.

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This driver attempts to use a zero-copy receive and transmit scheme.

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Alas, all data buffers are required to start on a 32 bit boundary, so

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Alas, all data buffers are required to start on a 32 bit boundary, so

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the driver must often copy transmit packets into bounce buffers.

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the driver must often copy transmit packets into bounce buffers.

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The driver allocates full frame size skbuffs for the Rx ring buffers at

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The driver allocates full frame size skbuffs for the Rx ring buffers at

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open() time and passes the skb->data field to the chip as receive data

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open() time and passes the skb->data field to the chip as receive data

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buffers. When an incoming frame is less than RX_COPYBREAK bytes long,

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buffers. When an incoming frame is less than RX_COPYBREAK bytes long,

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a fresh skbuff is allocated and the frame is copied to the new skbuff.

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a fresh skbuff is allocated and the frame is copied to the new skbuff.

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When the incoming frame is larger, the skbuff is passed directly up the

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When the incoming frame is larger, the skbuff is passed directly up the

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protocol stack. Buffers consumed this way are replaced by newly allocated

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protocol stack. Buffers consumed this way are replaced by newly allocated

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skbuffs in the last phase of rhine_rx().

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skbuffs in the last phase of rhine_rx().

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The RX_COPYBREAK value is chosen to trade-off the memory wasted by

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The RX_COPYBREAK value is chosen to trade-off the memory wasted by

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using a full-sized skbuff for small frames vs. the copying costs of larger

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using a full-sized skbuff for small frames vs. the copying costs of larger

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frames. New boards are typically used in generously configured machines

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frames. New boards are typically used in generously configured machines

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and the underfilled buffers have negligible impact compared to the benefit of

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and the underfilled buffers have negligible impact compared to the benefit of

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a single allocation size, so the default value of zero results in never

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a single allocation size, so the default value of zero results in never

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copying packets. When copying is done, the cost is usually mitigated by using

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copying packets. When copying is done, the cost is usually mitigated by using

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a combined copy/checksum routine. Copying also preloads the cache, which is

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a combined copy/checksum routine. Copying also preloads the cache, which is

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most useful with small frames.

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most useful with small frames.

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Since the VIA chips are only able to transfer data to buffers on 32 bit

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Since the VIA chips are only able to transfer data to buffers on 32 bit

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boundaries, the IP header at offset 14 in an ethernet frame isn't

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boundaries, the IP header at offset 14 in an ethernet frame isn't

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longword aligned for further processing. Copying these unaligned buffers

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longword aligned for further processing. Copying these unaligned buffers

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has the beneficial effect of 16-byte aligning the IP header.

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has the beneficial effect of 16-byte aligning the IP header.

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IIId. Synchronization

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IIId. Synchronization

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The driver runs as two independent, single-threaded flows of control. One

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The driver runs as two independent, single-threaded flows of control. One

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is the send-packet routine, which enforces single-threaded use by the

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is the send-packet routine, which enforces single-threaded use by the

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netdev_priv(dev)->lock spinlock. The other thread is the interrupt handler,

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netdev_priv(dev)->lock spinlock. The other thread is the interrupt handler,

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which is single threaded by the hardware and interrupt handling software.

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which is single threaded by the hardware and interrupt handling software.

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The send packet thread has partial control over the Tx ring. It locks the

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The send packet thread has partial control over the Tx ring. It locks the

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netdev_priv(dev)->lock whenever it's queuing a Tx packet. If the next slot in

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netdev_priv(dev)->lock whenever it's queuing a Tx packet. If the next slot in

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the ring is not available it stops the transmit queue by

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the ring is not available it stops the transmit queue by

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calling netif_stop_queue.

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calling netif_stop_queue.

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The interrupt handler has exclusive control over the Rx ring and records stats

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The interrupt handler has exclusive control over the Rx ring and records stats

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from the Tx ring. After reaping the stats, it marks the Tx queue entry as

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from the Tx ring. After reaping the stats, it marks the Tx queue entry as

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empty by incrementing the dirty_tx mark. If at least half of the entries in

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empty by incrementing the dirty_tx mark. If at least half of the entries in

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the Rx ring are available the transmit queue is woken up if it was stopped.

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the Rx ring are available the transmit queue is woken up if it was stopped.

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IV. Notes

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IV. Notes

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IVb. References

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IVb. References

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Preliminary VT86C100A manual from http://www.via.com.tw/

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Preliminary VT86C100A manual from http://www.via.com.tw/

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http://www.scyld.com/expert/100mbps.html

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http://www.scyld.com/expert/100mbps.html

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http://www.scyld.com/expert/NWay.html

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http://www.scyld.com/expert/NWay.html

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ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf

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ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf

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ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF

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ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF

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IVc. Errata

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IVc. Errata

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The VT86C100A manual is not reliable information.

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The VT86C100A manual is not reliable information.

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The 3043 chip does not handle unaligned transmit or receive buffers, resulting

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The 3043 chip does not handle unaligned transmit or receive buffers, resulting

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in significant performance degradation for bounce buffer copies on transmit

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in significant performance degradation for bounce buffer copies on transmit

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and unaligned IP headers on receive.

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and unaligned IP headers on receive.

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The chip does not pad to minimum transmit length.

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The chip does not pad to minimum transmit length.

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*/

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*/

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/* This table drives the PCI probe routines. It's mostly boilerplate in all

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/* This table drives the PCI probe routines. It's mostly boilerplate in all

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of the drivers, and will likely be provided by some future kernel.

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of the drivers, and will likely be provided by some future kernel.

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Note the matching code -- the first table entry matchs all 56** cards but

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Note the matching code -- the first table entry matchs all 56** cards but

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second only the 1234 card.

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second only the 1234 card.

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*/

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*/

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enum rhine_revs {

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enum rhine_revs {

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VT86C100A = 0x00,

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VT86C100A = 0x00,

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VTunknown0 = 0x20,

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VTunknown0 = 0x20,

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VT6102 = 0x40,

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VT6102 = 0x40,

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VT8231 = 0x50, /* Integrated MAC */

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VT8231 = 0x50, /* Integrated MAC */

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VT8233 = 0x60, /* Integrated MAC */

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VT8233 = 0x60, /* Integrated MAC */

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VT8235 = 0x74, /* Integrated MAC */

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VT8235 = 0x74, /* Integrated MAC */

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VT8237 = 0x78, /* Integrated MAC */

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VT8237 = 0x78, /* Integrated MAC */

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VTunknown1 = 0x7C,

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VTunknown1 = 0x7C,

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VT6105 = 0x80,

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VT6105 = 0x80,

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VT6105_B0 = 0x83,

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VT6105_B0 = 0x83,

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VT6105L = 0x8A,

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VT6105L = 0x8A,

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VT6107 = 0x8C,

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VT6107 = 0x8C,

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VTunknown2 = 0x8E,

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VTunknown2 = 0x8E,

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VT6105M = 0x90, /* Management adapter */

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VT6105M = 0x90, /* Management adapter */

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};

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};

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enum rhine_quirks {

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enum rhine_quirks {

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rqWOL = 0x0001, /* Wake-On-LAN support */

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rqWOL = 0x0001, /* Wake-On-LAN support */

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rqForceReset = 0x0002,

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rqForceReset = 0x0002,

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rq6patterns = 0x0040, /* 6 instead of 4 patterns for WOL */

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rq6patterns = 0x0040, /* 6 instead of 4 patterns for WOL */

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rqStatusWBRace = 0x0080, /* Tx Status Writeback Error possible */

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rqStatusWBRace = 0x0080, /* Tx Status Writeback Error possible */

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rqRhineI = 0x0100, /* See comment below */

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rqRhineI = 0x0100, /* See comment below */

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};

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};

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/*

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/*

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* rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable

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* rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable

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* MMIO as well as for the collision counter and the Tx FIFO underflow

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* MMIO as well as for the collision counter and the Tx FIFO underflow

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* indicator. In addition, Tx and Rx buffers need to 4 byte aligned.

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* indicator. In addition, Tx and Rx buffers need to 4 byte aligned.

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*/

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*/

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/* Beware of PCI posted writes */

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/* Beware of PCI posted writes */

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#define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)

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#define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)

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static DEFINE_PCI_DEVICE_TABLE(rhine_pci_tbl) = {

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static DEFINE_PCI_DEVICE_TABLE(rhine_pci_tbl) = {

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{ 0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, }, /* VT86C100A */

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{ 0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, }, /* VT86C100A */

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{ 0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6102 */

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{ 0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6102 */

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{ 0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, }, /* 6105{,L,LOM} */

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{ 0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, }, /* 6105{,L,LOM} */

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{ 0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6105M */

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{ 0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6105M */

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{ } /* terminate list */

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{ } /* terminate list */

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};

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};

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MODULE_DEVICE_TABLE(pci, rhine_pci_tbl);

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MODULE_DEVICE_TABLE(pci, rhine_pci_tbl);

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/* Offsets to the device registers. */

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/* Offsets to the device registers. */

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enum register_offsets {

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enum register_offsets {

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StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,

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StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,

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ChipCmd1=0x09, TQWake=0x0A,

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ChipCmd1=0x09, TQWake=0x0A,

289

IntrStatus=0x0C, IntrEnable=0x0E,

289

IntrStatus=0x0C, IntrEnable=0x0E,

290

MulticastFilter0=0x10, MulticastFilter1=0x14,

290

MulticastFilter0=0x10, MulticastFilter1=0x14,

291

RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,

291

RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,

292

MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E, PCIBusConfig1=0x6F,

292

MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E, PCIBusConfig1=0x6F,

293

MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,

293

MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,

294

ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,

294

ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,

295

RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,

295

RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,

296

StickyHW=0x83, IntrStatus2=0x84,

296

StickyHW=0x83, IntrStatus2=0x84,

297

CamMask=0x88, CamCon=0x92, CamAddr=0x93,

297

CamMask=0x88, CamCon=0x92, CamAddr=0x93,

298

WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4,

298

WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4,

299

WOLcrClr1=0xA6, WOLcgClr=0xA7,

299

WOLcrClr1=0xA6, WOLcgClr=0xA7,

300

PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD,

300

PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD,

301

};

301

};

302

303

/* Bits in ConfigD */

303

/* Bits in ConfigD */

304

enum backoff_bits {

304

enum backoff_bits {

305

BackOptional=0x01, BackModify=0x02,

305

BackOptional=0x01, BackModify=0x02,

306

BackCaptureEffect=0x04, BackRandom=0x08

306

BackCaptureEffect=0x04, BackRandom=0x08

307

};

307

};

308

309

/* Bits in the TxConfig (TCR) register */

309

/* Bits in the TxConfig (TCR) register */

310

enum tcr_bits {

310

enum tcr_bits {

311

TCR_PQEN=0x01,

311

TCR_PQEN=0x01,

312

TCR_LB0=0x02, /* loopback[0] */

312

TCR_LB0=0x02, /* loopback[0] */

313

TCR_LB1=0x04, /* loopback[1] */

313

TCR_LB1=0x04, /* loopback[1] */

314

TCR_OFSET=0x08,

314

TCR_OFSET=0x08,

315

TCR_RTGOPT=0x10,

315

TCR_RTGOPT=0x10,

316

TCR_RTFT0=0x20,

316

TCR_RTFT0=0x20,

317

TCR_RTFT1=0x40,

317

TCR_RTFT1=0x40,

318

TCR_RTSF=0x80,

318

TCR_RTSF=0x80,

319

};

319

};

320

321

/* Bits in the CamCon (CAMC) register */

321

/* Bits in the CamCon (CAMC) register */

322

enum camcon_bits {

322

enum camcon_bits {

323

CAMC_CAMEN=0x01,

323

CAMC_CAMEN=0x01,

324

CAMC_VCAMSL=0x02,

324

CAMC_VCAMSL=0x02,

325

CAMC_CAMWR=0x04,

325

CAMC_CAMWR=0x04,

326

CAMC_CAMRD=0x08,

326

CAMC_CAMRD=0x08,

327

};

327

};

328

329

/* Bits in the PCIBusConfig1 (BCR1) register */

329

/* Bits in the PCIBusConfig1 (BCR1) register */

330

enum bcr1_bits {

330

enum bcr1_bits {

331

BCR1_POT0=0x01,

331

BCR1_POT0=0x01,

332

BCR1_POT1=0x02,

332

BCR1_POT1=0x02,

333

BCR1_POT2=0x04,

333

BCR1_POT2=0x04,

334

BCR1_CTFT0=0x08,

334

BCR1_CTFT0=0x08,

335

BCR1_CTFT1=0x10,

335

BCR1_CTFT1=0x10,

336

BCR1_CTSF=0x20,

336

BCR1_CTSF=0x20,

337

BCR1_TXQNOBK=0x40, /* for VT6105 */

337

BCR1_TXQNOBK=0x40, /* for VT6105 */

338

BCR1_VIDFR=0x80, /* for VT6105 */

338

BCR1_VIDFR=0x80, /* for VT6105 */

339

BCR1_MED0=0x40, /* for VT6102 */

339

BCR1_MED0=0x40, /* for VT6102 */

340

BCR1_MED1=0x80, /* for VT6102 */

340

BCR1_MED1=0x80, /* for VT6102 */

341

};

341

};

342

343

#ifdef USE_MMIO

343

#ifdef USE_MMIO

344

/* Registers we check that mmio and reg are the same. */

344

/* Registers we check that mmio and reg are the same. */

345

static const int mmio_verify_registers[] = {

345

static const int mmio_verify_registers[] = {

346

RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD,

346

RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD,

347

0

347

0

348

};

348

};

349

#endif

349

#endif

350

351

/* Bits in the interrupt status/mask registers. */

351

/* Bits in the interrupt status/mask registers. */

352

enum intr_status_bits {

352

enum intr_status_bits {

353

IntrRxDone=0x0001, IntrRxErr=0x0004, IntrRxEmpty=0x0020,

353

IntrRxDone=0x0001, IntrRxErr=0x0004, IntrRxEmpty=0x0020,

354

IntrTxDone=0x0002, IntrTxError=0x0008, IntrTxUnderrun=0x0210,

354

IntrTxDone=0x0002, IntrTxError=0x0008, IntrTxUnderrun=0x0210,

355

IntrPCIErr=0x0040,

355

IntrPCIErr=0x0040,

356

IntrStatsMax=0x0080, IntrRxEarly=0x0100,

356

IntrStatsMax=0x0080, IntrRxEarly=0x0100,

357

IntrRxOverflow=0x0400, IntrRxDropped=0x0800, IntrRxNoBuf=0x1000,

357

IntrRxOverflow=0x0400, IntrRxDropped=0x0800, IntrRxNoBuf=0x1000,

358

IntrTxAborted=0x2000, IntrLinkChange=0x4000,

358

IntrTxAborted=0x2000, IntrLinkChange=0x4000,

359

IntrRxWakeUp=0x8000,

359

IntrRxWakeUp=0x8000,

360

IntrNormalSummary=0x0003, IntrAbnormalSummary=0xC260,

360

IntrNormalSummary=0x0003, IntrAbnormalSummary=0xC260,

361

IntrTxDescRace=0x080000, /* mapped from IntrStatus2 */

361

IntrTxDescRace=0x080000, /* mapped from IntrStatus2 */

362

IntrTxErrSummary=0x082218,

362

IntrTxErrSummary=0x082218,

363

};

363

};

364

365

/* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */

365

/* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */

366

enum wol_bits {

366

enum wol_bits {

367

WOLucast = 0x10,

367

WOLucast = 0x10,

368

WOLmagic = 0x20,

368

WOLmagic = 0x20,

369

WOLbmcast = 0x30,

369

WOLbmcast = 0x30,

370

WOLlnkon = 0x40,

370

WOLlnkon = 0x40,

371

WOLlnkoff = 0x80,

371

WOLlnkoff = 0x80,

372

};

372

};

373

374

/* The Rx and Tx buffer descriptors. */

374

/* The Rx and Tx buffer descriptors. */

375

struct rx_desc {

375

struct rx_desc {

376

__le32 rx_status;

376

__le32 rx_status;

377

__le32 desc_length; /* Chain flag, Buffer/frame length */

377

__le32 desc_length; /* Chain flag, Buffer/frame length */

378

__le32 addr;

378

__le32 addr;

379

__le32 next_desc;

379

__le32 next_desc;

380

};

380

};

381

struct tx_desc {

381

struct tx_desc {

382

__le32 tx_status;

382

__le32 tx_status;

383

__le32 desc_length; /* Chain flag, Tx Config, Frame length */

383

__le32 desc_length; /* Chain flag, Tx Config, Frame length */

384

__le32 addr;

384

__le32 addr;

385

__le32 next_desc;

385

__le32 next_desc;

386

};

386

};

387

388

/* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */

388

/* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */

389

#define TXDESC 0x00e08000

389

#define TXDESC 0x00e08000

390

391

enum rx_status_bits {

391

enum rx_status_bits {

392

RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F

392

RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F

393

};

393

};

394

395

/* Bits in *_desc.*_status */

395

/* Bits in *_desc.*_status */

396

enum desc_status_bits {

396

enum desc_status_bits {

397

DescOwn=0x80000000

397

DescOwn=0x80000000

398

};

398

};

399

400

/* Bits in *_desc.*_length */

400

/* Bits in *_desc.*_length */

401

enum desc_length_bits {

401

enum desc_length_bits {

402

DescTag=0x00010000

402

DescTag=0x00010000

403

};

403

};

404

405

/* Bits in ChipCmd. */

405

/* Bits in ChipCmd. */

406

enum chip_cmd_bits {

406

enum chip_cmd_bits {

407

CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08,

407

CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08,

408

CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40,

408

CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40,

409

Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04,

409

Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04,

410

Cmd1NoTxPoll=0x08, Cmd1Reset=0x80,

410

Cmd1NoTxPoll=0x08, Cmd1Reset=0x80,

411

};

411

};

412

413

struct rhine_private {

413

struct rhine_private {

414

/* Bit mask for configured VLAN ids */

414

/* Bit mask for configured VLAN ids */

415

unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];

415

unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];

416

417

/* Descriptor rings */

417

/* Descriptor rings */

418

struct rx_desc *rx_ring;

418

struct rx_desc *rx_ring;

419

struct tx_desc *tx_ring;

419

struct tx_desc *tx_ring;

420

dma_addr_t rx_ring_dma;

420

dma_addr_t rx_ring_dma;

421

dma_addr_t tx_ring_dma;

421

dma_addr_t tx_ring_dma;

422

423

/* The addresses of receive-in-place skbuffs. */

423

/* The addresses of receive-in-place skbuffs. */

424

struct sk_buff *rx_skbuff[RX_RING_SIZE];

424

struct sk_buff *rx_skbuff[RX_RING_SIZE];

425

dma_addr_t rx_skbuff_dma[RX_RING_SIZE];

425

dma_addr_t rx_skbuff_dma[RX_RING_SIZE];

426

427

/* The saved address of a sent-in-place packet/buffer, for later free(). */

427

/* The saved address of a sent-in-place packet/buffer, for later free(). */

428

struct sk_buff *tx_skbuff[TX_RING_SIZE];

428

struct sk_buff *tx_skbuff[TX_RING_SIZE];

429

dma_addr_t tx_skbuff_dma[TX_RING_SIZE];

429

dma_addr_t tx_skbuff_dma[TX_RING_SIZE];

430

431

/* Tx bounce buffers (Rhine-I only) */

431

/* Tx bounce buffers (Rhine-I only) */

432

unsigned char *tx_buf[TX_RING_SIZE];

432

unsigned char *tx_buf[TX_RING_SIZE];

433

unsigned char *tx_bufs;

433

unsigned char *tx_bufs;

434

dma_addr_t tx_bufs_dma;

434

dma_addr_t tx_bufs_dma;

435

436

struct pci_dev *pdev;

436

struct pci_dev *pdev;

437

long pioaddr;

437

long pioaddr;

438

struct net_device *dev;

438

struct net_device *dev;

439

struct napi_struct napi;

439

struct napi_struct napi;

440

spinlock_t lock;

440

spinlock_t lock;

441

struct work_struct reset_task;

441

struct work_struct reset_task;

442

443

/* Frequently used values: keep some adjacent for cache effect. */

443

/* Frequently used values: keep some adjacent for cache effect. */

444

u32 quirks;

444

u32 quirks;

445

struct rx_desc *rx_head_desc;

445

struct rx_desc *rx_head_desc;

446

unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */

446

unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */

447

unsigned int cur_tx, dirty_tx;

447

unsigned int cur_tx, dirty_tx;

448

unsigned int rx_buf_sz; /* Based on MTU+slack. */

448

unsigned int rx_buf_sz; /* Based on MTU+slack. */

449

u8 wolopts;

449

u8 wolopts;

450

451

u8 tx_thresh, rx_thresh;

451

u8 tx_thresh, rx_thresh;

452

453

struct mii_if_info mii_if;

453

struct mii_if_info mii_if;

454

void __iomem *base;

454

void __iomem *base;

455

};

455

};

456

457

#define BYTE_REG_BITS_ON(x, p) do { iowrite8((ioread8((p))|(x)), (p)); } while (0)

457

#define BYTE_REG_BITS_ON(x, p) do { iowrite8((ioread8((p))|(x)), (p)); } while (0)

458

#define WORD_REG_BITS_ON(x, p) do { iowrite16((ioread16((p))|(x)), (p)); } while (0)

458

#define WORD_REG_BITS_ON(x, p) do { iowrite16((ioread16((p))|(x)), (p)); } while (0)

459

#define DWORD_REG_BITS_ON(x, p) do { iowrite32((ioread32((p))|(x)), (p)); } while (0)

459

#define DWORD_REG_BITS_ON(x, p) do { iowrite32((ioread32((p))|(x)), (p)); } while (0)

460

461

#define BYTE_REG_BITS_IS_ON(x, p) (ioread8((p)) & (x))

461

#define BYTE_REG_BITS_IS_ON(x, p) (ioread8((p)) & (x))

462

#define WORD_REG_BITS_IS_ON(x, p) (ioread16((p)) & (x))

462

#define WORD_REG_BITS_IS_ON(x, p) (ioread16((p)) & (x))

463

#define DWORD_REG_BITS_IS_ON(x, p) (ioread32((p)) & (x))

463

#define DWORD_REG_BITS_IS_ON(x, p) (ioread32((p)) & (x))

464

465

#define BYTE_REG_BITS_OFF(x, p) do { iowrite8(ioread8((p)) & (~(x)), (p)); } while (0)

465

#define BYTE_REG_BITS_OFF(x, p) do { iowrite8(ioread8((p)) & (~(x)), (p)); } while (0)

466

#define WORD_REG_BITS_OFF(x, p) do { iowrite16(ioread16((p)) & (~(x)), (p)); } while (0)

466

#define WORD_REG_BITS_OFF(x, p) do { iowrite16(ioread16((p)) & (~(x)), (p)); } while (0)

467

#define DWORD_REG_BITS_OFF(x, p) do { iowrite32(ioread32((p)) & (~(x)), (p)); } while (0)

467

#define DWORD_REG_BITS_OFF(x, p) do { iowrite32(ioread32((p)) & (~(x)), (p)); } while (0)

468

469

#define BYTE_REG_BITS_SET(x, m, p) do { iowrite8((ioread8((p)) & (~(m)))|(x), (p)); } while (0)

469

#define BYTE_REG_BITS_SET(x, m, p) do { iowrite8((ioread8((p)) & (~(m)))|(x), (p)); } while (0)

470

#define WORD_REG_BITS_SET(x, m, p) do { iowrite16((ioread16((p)) & (~(m)))|(x), (p)); } while (0)

470

#define WORD_REG_BITS_SET(x, m, p) do { iowrite16((ioread16((p)) & (~(m)))|(x), (p)); } while (0)

471

#define DWORD_REG_BITS_SET(x, m, p) do { iowrite32((ioread32((p)) & (~(m)))|(x), (p)); } while (0)

471

#define DWORD_REG_BITS_SET(x, m, p) do { iowrite32((ioread32((p)) & (~(m)))|(x), (p)); } while (0)

472

473

474

static int mdio_read(struct net_device *dev, int phy_id, int location);

474

static int mdio_read(struct net_device *dev, int phy_id, int location);

475

static void mdio_write(struct net_device *dev, int phy_id, int location, int value);

475

static void mdio_write(struct net_device *dev, int phy_id, int location, int value);

476

static int rhine_open(struct net_device *dev);

476

static int rhine_open(struct net_device *dev);

477

static void rhine_reset_task(struct work_struct *work);

477

static void rhine_reset_task(struct work_struct *work);

478

static void rhine_tx_timeout(struct net_device *dev);

478

static void rhine_tx_timeout(struct net_device *dev);

479

static netdev_tx_t rhine_start_tx(struct sk_buff *skb,

479

static netdev_tx_t rhine_start_tx(struct sk_buff *skb,

480

struct net_device *dev);

480

struct net_device *dev);

481

static irqreturn_t rhine_interrupt(int irq, void *dev_instance);

481

static irqreturn_t rhine_interrupt(int irq, void *dev_instance);

482

static void rhine_tx(struct net_device *dev);

482

static void rhine_tx(struct net_device *dev);

483

static int rhine_rx(struct net_device *dev, int limit);

483

static int rhine_rx(struct net_device *dev, int limit);

484

static void rhine_error(struct net_device *dev, int intr_status);

484

static void rhine_error(struct net_device *dev, int intr_status);

485

static void rhine_set_rx_mode(struct net_device *dev);

485

static void rhine_set_rx_mode(struct net_device *dev);

486

static struct net_device_stats *rhine_get_stats(struct net_device *dev);

486

static struct net_device_stats *rhine_get_stats(struct net_device *dev);

487

static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);

487

static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);

488

static const struct ethtool_ops netdev_ethtool_ops;

488

static const struct ethtool_ops netdev_ethtool_ops;

489

static int rhine_close(struct net_device *dev);

489

static int rhine_close(struct net_device *dev);

490

static void rhine_shutdown (struct pci_dev *pdev);

490

static void rhine_shutdown (struct pci_dev *pdev);

491

static void rhine_vlan_rx_add_vid(struct net_device *dev, unsigned short vid);

491

static void rhine_vlan_rx_add_vid(struct net_device *dev, unsigned short vid);

492

static void rhine_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid);

492

static void rhine_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid);

493

static void rhine_set_cam(void __iomem *ioaddr, int idx, u8 *addr);

493

static void rhine_set_cam(void __iomem *ioaddr, int idx, u8 *addr);

494

static void rhine_set_vlan_cam(void __iomem *ioaddr, int idx, u8 *addr);

494

static void rhine_set_vlan_cam(void __iomem *ioaddr, int idx, u8 *addr);

495

static void rhine_set_cam_mask(void __iomem *ioaddr, u32 mask);

495

static void rhine_set_cam_mask(void __iomem *ioaddr, u32 mask);

496

static void rhine_set_vlan_cam_mask(void __iomem *ioaddr, u32 mask);

496

static void rhine_set_vlan_cam_mask(void __iomem *ioaddr, u32 mask);

497

static void rhine_init_cam_filter(struct net_device *dev);

497

static void rhine_init_cam_filter(struct net_device *dev);

498

static void rhine_update_vcam(struct net_device *dev);

498

static void rhine_update_vcam(struct net_device *dev);

499

500

#define RHINE_WAIT_FOR(condition) \

500

#define RHINE_WAIT_FOR(condition) \

501

do { \

501

do { \

502

int i = 1024; \

502

int i = 1024; \

503

while (!(condition) && --i) \

503

while (!(condition) && --i) \

504

; \

504

; \

505

if (debug > 1 && i < 512) \

505

if (debug > 1 && i < 512) \

506

pr_info("%4d cycles used @ %s:%d\n", \

506

pr_info("%4d cycles used @ %s:%d\n", \

507

1024 - i, __func__, __LINE__); \

507

1024 - i, __func__, __LINE__); \

508

} while (0)

508

} while (0)

509

510

static inline u32 get_intr_status(struct net_device *dev)

510

static inline u32 get_intr_status(struct net_device *dev)

511

{

511

{

512

struct rhine_private *rp = netdev_priv(dev);

512

struct rhine_private *rp = netdev_priv(dev);

513

void __iomem *ioaddr = rp->base;

513

void __iomem *ioaddr = rp->base;

514

u32 intr_status;

514

u32 intr_status;

515

516

intr_status = ioread16(ioaddr + IntrStatus);

516

intr_status = ioread16(ioaddr + IntrStatus);

517

/* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */

517

/* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */

518

if (rp->quirks & rqStatusWBRace)

518

if (rp->quirks & rqStatusWBRace)

519

intr_status |= ioread8(ioaddr + IntrStatus2) << 16;

519

intr_status |= ioread8(ioaddr + IntrStatus2) << 16;

520

return intr_status;

520

return intr_status;

521

}

521

}

522

523

/*

523

/*

524

* Get power related registers into sane state.

524

* Get power related registers into sane state.

525

* Notify user about past WOL event.

525

* Notify user about past WOL event.

526

*/

526

*/

527

static void rhine_power_init(struct net_device *dev)

527

static void rhine_power_init(struct net_device *dev)

528

{

528

{

529

struct rhine_private *rp = netdev_priv(dev);

529

struct rhine_private *rp = netdev_priv(dev);

530

void __iomem *ioaddr = rp->base;

530

void __iomem *ioaddr = rp->base;

531

u16 wolstat;

531

u16 wolstat;

532

533

if (rp->quirks & rqWOL) {

533

if (rp->quirks & rqWOL) {

534

/* Make sure chip is in power state D0 */

534

/* Make sure chip is in power state D0 */

535

iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);

535

iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);

536

537

/* Disable "force PME-enable" */

537

/* Disable "force PME-enable" */

538

iowrite8(0x80, ioaddr + WOLcgClr);

538

iowrite8(0x80, ioaddr + WOLcgClr);

539

540

/* Clear power-event config bits (WOL) */

540

/* Clear power-event config bits (WOL) */

541

iowrite8(0xFF, ioaddr + WOLcrClr);

541

iowrite8(0xFF, ioaddr + WOLcrClr);

542

/* More recent cards can manage two additional patterns */

542

/* More recent cards can manage two additional patterns */

543

if (rp->quirks & rq6patterns)

543

if (rp->quirks & rq6patterns)

544

iowrite8(0x03, ioaddr + WOLcrClr1);

544

iowrite8(0x03, ioaddr + WOLcrClr1);

545

546

/* Save power-event status bits */

546

/* Save power-event status bits */

547

wolstat = ioread8(ioaddr + PwrcsrSet);

547

wolstat = ioread8(ioaddr + PwrcsrSet);

548

if (rp->quirks & rq6patterns)

548

if (rp->quirks & rq6patterns)

549

wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8;

549

wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8;

550

551

/* Clear power-event status bits */

551

/* Clear power-event status bits */

552

iowrite8(0xFF, ioaddr + PwrcsrClr);

552

iowrite8(0xFF, ioaddr + PwrcsrClr);

553

if (rp->quirks & rq6patterns)

553

if (rp->quirks & rq6patterns)

554

iowrite8(0x03, ioaddr + PwrcsrClr1);

554

iowrite8(0x03, ioaddr + PwrcsrClr1);

555

556

if (wolstat) {

556

if (wolstat) {

557

char *reason;

557

char *reason;

558

switch (wolstat) {

558

switch (wolstat) {

559

case WOLmagic:

559

case WOLmagic:

560

reason = "Magic packet";

560

reason = "Magic packet";

561

break;

561

break;

562

case WOLlnkon:

562

case WOLlnkon:

563

reason = "Link went up";

563

reason = "Link went up";

564

break;

564

break;

565

case WOLlnkoff:

565

case WOLlnkoff:

566

reason = "Link went down";

566

reason = "Link went down";

567

break;

567

break;

568

case WOLucast:

568

case WOLucast:

569

reason = "Unicast packet";

569

reason = "Unicast packet";

570

break;

570

break;

571

case WOLbmcast:

571

case WOLbmcast:

572

reason = "Multicast/broadcast packet";

572

reason = "Multicast/broadcast packet";

573

break;

573

break;

574

default:

574

default:

575

reason = "Unknown";

575

reason = "Unknown";

576

}

576

}

577

netdev_info(dev, "Woke system up. Reason: %s\n",

577

netdev_info(dev, "Woke system up. Reason: %s\n",

578

reason);

578

reason);

579

}

579

}

580

}

580

}

581

}

581

}

582

583

static void rhine_chip_reset(struct net_device *dev)

583

static void rhine_chip_reset(struct net_device *dev)

584

{

584

{

585

struct rhine_private *rp = netdev_priv(dev);

585

struct rhine_private *rp = netdev_priv(dev);

586

void __iomem *ioaddr = rp->base;

586

void __iomem *ioaddr = rp->base;

587

588

iowrite8(Cmd1Reset, ioaddr + ChipCmd1);

588

iowrite8(Cmd1Reset, ioaddr + ChipCmd1);

589

IOSYNC;

589

IOSYNC;

590

591

if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) {

591

if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) {

592

netdev_info(dev, "Reset not complete yet. Trying harder.\n");

592

netdev_info(dev, "Reset not complete yet. Trying harder.\n");

593

594

/* Force reset */

594

/* Force reset */

595

if (rp->quirks & rqForceReset)

595

if (rp->quirks & rqForceReset)

596

iowrite8(0x40, ioaddr + MiscCmd);

596

iowrite8(0x40, ioaddr + MiscCmd);

597

598

/* Reset can take somewhat longer (rare) */

598

/* Reset can take somewhat longer (rare) */

599

RHINE_WAIT_FOR(!(ioread8(ioaddr + ChipCmd1) & Cmd1Reset));

599

RHINE_WAIT_FOR(!(ioread8(ioaddr + ChipCmd1) & Cmd1Reset));

600

}

600

}

601

602

if (debug > 1)

602

if (debug > 1)

603

netdev_info(dev, "Reset %s\n",

603

netdev_info(dev, "Reset %s\n",

604

(ioread8(ioaddr + ChipCmd1) & Cmd1Reset) ?

604

(ioread8(ioaddr + ChipCmd1) & Cmd1Reset) ?

605

"failed" : "succeeded");

605

"failed" : "succeeded");

606

}

606

}

607

608

#ifdef USE_MMIO

608

#ifdef USE_MMIO

609

static void enable_mmio(long pioaddr, u32 quirks)

609

static void enable_mmio(long pioaddr, u32 quirks)

610

{

610

{

611

int n;

611

int n;

612

if (quirks & rqRhineI) {

612

if (quirks & rqRhineI) {

613

/* More recent docs say that this bit is reserved ... */

613

/* More recent docs say that this bit is reserved ... */

614

n = inb(pioaddr + ConfigA) | 0x20;

614

n = inb(pioaddr + ConfigA) | 0x20;

615

outb(n, pioaddr + ConfigA);

615

outb(n, pioaddr + ConfigA);

616

} else {

616

} else {

617

n = inb(pioaddr + ConfigD) | 0x80;

617

n = inb(pioaddr + ConfigD) | 0x80;

618

outb(n, pioaddr + ConfigD);

618

outb(n, pioaddr + ConfigD);

619

}

619

}

620

}

620

}

621

#endif

621

#endif

622

623

/*

623

/*

624

* Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM

624

* Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM

625

* (plus 0x6C for Rhine-I/II)

625

* (plus 0x6C for Rhine-I/II)

626

*/

626

*/

627

static void __devinit rhine_reload_eeprom(long pioaddr, struct net_device *dev)

627

static void __devinit rhine_reload_eeprom(long pioaddr, struct net_device *dev)

628

{

628

{

629

struct rhine_private *rp = netdev_priv(dev);

629

struct rhine_private *rp = netdev_priv(dev);

630

void __iomem *ioaddr = rp->base;

630

void __iomem *ioaddr = rp->base;

631

632

outb(0x20, pioaddr + MACRegEEcsr);

632

outb(0x20, pioaddr + MACRegEEcsr);

633

RHINE_WAIT_FOR(!(inb(pioaddr + MACRegEEcsr) & 0x20));

633

RHINE_WAIT_FOR(!(inb(pioaddr + MACRegEEcsr) & 0x20));

634

635

#ifdef USE_MMIO

635

#ifdef USE_MMIO

636

/*

636

/*

637

* Reloading from EEPROM overwrites ConfigA-D, so we must re-enable

637

* Reloading from EEPROM overwrites ConfigA-D, so we must re-enable

638

* MMIO. If reloading EEPROM was done first this could be avoided, but

638

* MMIO. If reloading EEPROM was done first this could be avoided, but

639

* it is not known if that still works with the "win98-reboot" problem.

639

* it is not known if that still works with the "win98-reboot" problem.

640

*/

640

*/

641

enable_mmio(pioaddr, rp->quirks);

641

enable_mmio(pioaddr, rp->quirks);

642

#endif

642

#endif

643

644

/* Turn off EEPROM-controlled wake-up (magic packet) */

644

/* Turn off EEPROM-controlled wake-up (magic packet) */

645

if (rp->quirks & rqWOL)

645

if (rp->quirks & rqWOL)

646

iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);

646

iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);

647

648

}

648

}

649

650

#ifdef CONFIG_NET_POLL_CONTROLLER

650

#ifdef CONFIG_NET_POLL_CONTROLLER

651

static void rhine_poll(struct net_device *dev)

651

static void rhine_poll(struct net_device *dev)

652

{

652

{

653

disable_irq(dev->irq);

653

disable_irq(dev->irq);

654

rhine_interrupt(dev->irq, (void *)dev);

654

rhine_interrupt(dev->irq, (void *)dev);

655

enable_irq(dev->irq);

655

enable_irq(dev->irq);

656

}

656

}

657

#endif

657

#endif

658

659

static int rhine_napipoll(struct napi_struct *napi, int budget)

659

static int rhine_napipoll(struct napi_struct *napi, int budget)

660

{

660

{

661

struct rhine_private *rp = container_of(napi, struct rhine_private, napi);

661

struct rhine_private *rp = container_of(napi, struct rhine_private, napi);

662

struct net_device *dev = rp->dev;

662

struct net_device *dev = rp->dev;

663

void __iomem *ioaddr = rp->base;

663

void __iomem *ioaddr = rp->base;

664

int work_done;

664

int work_done;

665

666

work_done = rhine_rx(dev, budget);

666

work_done = rhine_rx(dev, budget);

667

668

if (work_done < budget) {

668

if (work_done < budget) {

669

napi_complete(napi);

669

napi_complete(napi);

670

671

iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |

671

iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |

672

IntrRxDropped | IntrRxNoBuf | IntrTxAborted |

672

IntrRxDropped | IntrRxNoBuf | IntrTxAborted |

673

IntrTxDone | IntrTxError | IntrTxUnderrun |

673

IntrTxDone | IntrTxError | IntrTxUnderrun |

674

IntrPCIErr | IntrStatsMax | IntrLinkChange,

674

IntrPCIErr | IntrStatsMax | IntrLinkChange,

675

ioaddr + IntrEnable);

675

ioaddr + IntrEnable);

676

}

676

}

677

return work_done;

677

return work_done;

678

}

678

}

679

680

static void __devinit rhine_hw_init(struct net_device *dev, long pioaddr)

680

static void __devinit rhine_hw_init(struct net_device *dev, long pioaddr)

681

{

681

{

682

struct rhine_private *rp = netdev_priv(dev);

682

struct rhine_private *rp = netdev_priv(dev);

683

684

/* Reset the chip to erase previous misconfiguration. */

684

/* Reset the chip to erase previous misconfiguration. */

685

rhine_chip_reset(dev);

685

rhine_chip_reset(dev);

686

687

/* Rhine-I needs extra time to recuperate before EEPROM reload */

687

/* Rhine-I needs extra time to recuperate before EEPROM reload */

688

if (rp->quirks & rqRhineI)

688

if (rp->quirks & rqRhineI)

689

msleep(5);

689

msleep(5);

690

691

/* Reload EEPROM controlled bytes cleared by soft reset */

691

/* Reload EEPROM controlled bytes cleared by soft reset */

692

rhine_reload_eeprom(pioaddr, dev);

692

rhine_reload_eeprom(pioaddr, dev);

693

}

693

}

694

695

static const struct net_device_ops rhine_netdev_ops = {

695

static const struct net_device_ops rhine_netdev_ops = {

696

.ndo_open = rhine_open,

696

.ndo_open = rhine_open,

697

.ndo_stop = rhine_close,

697

.ndo_stop = rhine_close,

698

.ndo_start_xmit = rhine_start_tx,

698

.ndo_start_xmit = rhine_start_tx,

699

.ndo_get_stats = rhine_get_stats,

699

.ndo_get_stats = rhine_get_stats,

700

.ndo_set_multicast_list = rhine_set_rx_mode,

700

.ndo_set_multicast_list = rhine_set_rx_mode,

701

.ndo_change_mtu = eth_change_mtu,

701

.ndo_change_mtu = eth_change_mtu,

702

.ndo_validate_addr = eth_validate_addr,

702

.ndo_validate_addr = eth_validate_addr,

703

.ndo_set_mac_address = eth_mac_addr,

703

.ndo_set_mac_address = eth_mac_addr,

704

.ndo_do_ioctl = netdev_ioctl,

704

.ndo_do_ioctl = netdev_ioctl,

705

.ndo_tx_timeout = rhine_tx_timeout,

705

.ndo_tx_timeout = rhine_tx_timeout,

706

.ndo_vlan_rx_add_vid = rhine_vlan_rx_add_vid,

706

.ndo_vlan_rx_add_vid = rhine_vlan_rx_add_vid,

707

.ndo_vlan_rx_kill_vid = rhine_vlan_rx_kill_vid,

707

.ndo_vlan_rx_kill_vid = rhine_vlan_rx_kill_vid,

708

#ifdef CONFIG_NET_POLL_CONTROLLER

708

#ifdef CONFIG_NET_POLL_CONTROLLER

709

.ndo_poll_controller = rhine_poll,

709

.ndo_poll_controller = rhine_poll,

710

#endif

710

#endif

711

};

711

};

712

713

static int __devinit rhine_init_one(struct pci_dev *pdev,

713

static int __devinit rhine_init_one(struct pci_dev *pdev,

714

const struct pci_device_id *ent)

714

const struct pci_device_id *ent)

715

{

715

{

716

struct net_device *dev;

716

struct net_device *dev;

717

struct rhine_private *rp;

717

struct rhine_private *rp;

718

int i, rc;

718

int i, rc;

719

u32 quirks;

719

u32 quirks;

720

long pioaddr;

720

long pioaddr;

721

long memaddr;

721

long memaddr;

722

void __iomem *ioaddr;

722

void __iomem *ioaddr;

723

int io_size, phy_id;

723

int io_size, phy_id;

724

const char *name;

724

const char *name;

725

#ifdef USE_MMIO

725

#ifdef USE_MMIO

726

int bar = 1;

726

int bar = 1;

727

#else

727

#else

728

int bar = 0;

728

int bar = 0;

729

#endif

729

#endif

730

731

/* when built into the kernel, we only print version if device is found */

731

/* when built into the kernel, we only print version if device is found */

732

#ifndef MODULE

732

#ifndef MODULE

733

pr_info_once("%s\n", version);

733

pr_info_once("%s\n", version);

734

#endif

734

#endif

735

736

io_size = 256;

736

io_size = 256;

737

phy_id = 0;

737

phy_id = 0;

738

quirks = 0;

738

quirks = 0;

739

name = "Rhine";

739

name = "Rhine";

740

if (pdev->revision < VTunknown0) {

740

if (pdev->revision < VTunknown0) {

741

quirks = rqRhineI;

741

quirks = rqRhineI;

742

io_size = 128;

742

io_size = 128;

743

}

743

}

744

else if (pdev->revision >= VT6102) {

744

else if (pdev->revision >= VT6102) {

745

quirks = rqWOL | rqForceReset;

745

quirks = rqWOL | rqForceReset;

746

if (pdev->revision < VT6105) {

746

if (pdev->revision < VT6105) {

747

name = "Rhine II";

747

name = "Rhine II";

748

quirks |= rqStatusWBRace; /* Rhine-II exclusive */

748

quirks |= rqStatusWBRace; /* Rhine-II exclusive */

749

}

749

}

750

else {

750

else {

751

phy_id = 1; /* Integrated PHY, phy_id fixed to 1 */

751

phy_id = 1; /* Integrated PHY, phy_id fixed to 1 */

752

if (pdev->revision >= VT6105_B0)

752

if (pdev->revision >= VT6105_B0)

753

quirks |= rq6patterns;

753

quirks |= rq6patterns;

754

if (pdev->revision < VT6105M)

754

if (pdev->revision < VT6105M)

755

name = "Rhine III";

755

name = "Rhine III";

756

else

756

else

757

name = "Rhine III (Management Adapter)";

757

name = "Rhine III (Management Adapter)";

758

}

758

}

759

}

759

}

760

761

rc = pci_enable_device(pdev);

761

rc = pci_enable_device(pdev);

762

if (rc)

762

if (rc)

763

goto err_out;

763

goto err_out;

764

765

/* this should always be supported */

765

/* this should always be supported */

766

rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));

766

rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));

767

if (rc) {

767

if (rc) {

768

dev_err(&pdev->dev,

768

dev_err(&pdev->dev,

769

"32-bit PCI DMA addresses not supported by the card!?\n");

769

"32-bit PCI DMA addresses not supported by the card!?\n");

770

goto err_out;

770

goto err_out;

771

}

771

}

772

773

/* sanity check */

773

/* sanity check */

774

if ((pci_resource_len(pdev, 0) < io_size) ||

774

if ((pci_resource_len(pdev, 0) < io_size) ||

775

(pci_resource_len(pdev, 1) < io_size)) {

775

(pci_resource_len(pdev, 1) < io_size)) {

776

rc = -EIO;

776

rc = -EIO;

777

dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n");

777

dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n");

778

goto err_out;

778

goto err_out;

779

}

779

}

780

781

pioaddr = pci_resource_start(pdev, 0);

781

pioaddr = pci_resource_start(pdev, 0);

782

memaddr = pci_resource_start(pdev, 1);

782

memaddr = pci_resource_start(pdev, 1);

783

784

pci_set_master(pdev);

784

pci_set_master(pdev);

785

786

dev = alloc_etherdev(sizeof(struct rhine_private));

786

dev = alloc_etherdev(sizeof(struct rhine_private));

787

if (!dev) {

787

if (!dev) {

788

rc = -ENOMEM;

788

rc = -ENOMEM;

789

dev_err(&pdev->dev, "alloc_etherdev failed\n");

789

dev_err(&pdev->dev, "alloc_etherdev failed\n");

790

goto err_out;

790

goto err_out;

791

}

791

}

792

SET_NETDEV_DEV(dev, &pdev->dev);

792

SET_NETDEV_DEV(dev, &pdev->dev);

793

794

rp = netdev_priv(dev);

794

rp = netdev_priv(dev);

795

rp->dev = dev;

795

rp->dev = dev;

796

rp->quirks = quirks;

796

rp->quirks = quirks;

797

rp->pioaddr = pioaddr;

797

rp->pioaddr = pioaddr;

798

rp->pdev = pdev;

798

rp->pdev = pdev;

799

800

rc = pci_request_regions(pdev, DRV_NAME);

800

rc = pci_request_regions(pdev, DRV_NAME);

801

if (rc)

801

if (rc)

802

goto err_out_free_netdev;

802

goto err_out_free_netdev;

803

804

ioaddr = pci_iomap(pdev, bar, io_size);

804

ioaddr = pci_iomap(pdev, bar, io_size);

805

if (!ioaddr) {

805

if (!ioaddr) {

806

rc = -EIO;

806

rc = -EIO;

807

dev_err(&pdev->dev,

807

dev_err(&pdev->dev,

808

"ioremap failed for device %s, region 0x%X @ 0x%lX\n",

808

"ioremap failed for device %s, region 0x%X @ 0x%lX\n",

809

pci_name(pdev), io_size, memaddr);

809

pci_name(pdev), io_size, memaddr);

810

goto err_out_free_res;

810

goto err_out_free_res;

811

}

811

}

812

813

#ifdef USE_MMIO

813

#ifdef USE_MMIO

814

enable_mmio(pioaddr, quirks);

814

enable_mmio(pioaddr, quirks);

815

816

/* Check that selected MMIO registers match the PIO ones */

816

/* Check that selected MMIO registers match the PIO ones */

817

i = 0;

817

i = 0;

818

while (mmio_verify_registers[i]) {

818

while (mmio_verify_registers[i]) {

819

int reg = mmio_verify_registers[i++];

819

int reg = mmio_verify_registers[i++];

820

unsigned char a = inb(pioaddr+reg);

820

unsigned char a = inb(pioaddr+reg);

821

unsigned char b = readb(ioaddr+reg);

821

unsigned char b = readb(ioaddr+reg);

822

if (a != b) {

822

if (a != b) {

823

rc = -EIO;

823

rc = -EIO;

824

dev_err(&pdev->dev,

824

dev_err(&pdev->dev,

825

"MMIO do not match PIO [%02x] (%02x != %02x)\n",

825

"MMIO do not match PIO [%02x] (%02x != %02x)\n",

826

reg, a, b);

826

reg, a, b);

827

goto err_out_unmap;

827

goto err_out_unmap;

828

}

828

}

829

}

829

}

830

#endif /* USE_MMIO */

830

#endif /* USE_MMIO */

831

832

dev->base_addr = (unsigned long)ioaddr;

832

dev->base_addr = (unsigned long)ioaddr;

833

rp->base = ioaddr;

833

rp->base = ioaddr;

834

835

/* Get chip registers into a sane state */

835

/* Get chip registers into a sane state */

836

rhine_power_init(dev);

836

rhine_power_init(dev);

837

rhine_hw_init(dev, pioaddr);

837

rhine_hw_init(dev, pioaddr);

838

839

for (i = 0; i < 6; i++)

839

for (i = 0; i < 6; i++)

840

dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i);

840

dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i);

841

memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);

842

841

843

if (!is_valid_ether_addr(dev->perm_addr)) {

842

if (!is_valid_ether_addr(dev->dev_addr)) {

844

rc = -EIO;

843

/* Report it and use a random ethernet address instead */

845

dev_err(&pdev->dev, "Invalid MAC address\n");

844

netdev_err(dev, "Invalid MAC address: %pM\n", dev->dev_addr);

846

goto err_out_unmap;

845

random_ether_addr(dev->dev_addr);

846

netdev_info(dev, "Using random MAC address: %pM\n",

847

dev->dev_addr);

847

}

848

}

849

memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);

848

850

849

/* For Rhine-I/II, phy_id is loaded from EEPROM */

851

/* For Rhine-I/II, phy_id is loaded from EEPROM */

850

if (!phy_id)

852

if (!phy_id)

851

phy_id = ioread8(ioaddr + 0x6C);

853

phy_id = ioread8(ioaddr + 0x6C);

852

854

853

dev->irq = pdev->irq;

855

dev->irq = pdev->irq;

854

856

855

spin_lock_init(&rp->lock);

857

spin_lock_init(&rp->lock);

856

INIT_WORK(&rp->reset_task, rhine_reset_task);

858

INIT_WORK(&rp->reset_task, rhine_reset_task);

857

859

858

rp->mii_if.dev = dev;

860

rp->mii_if.dev = dev;

859

rp->mii_if.mdio_read = mdio_read;

861

rp->mii_if.mdio_read = mdio_read;

860

rp->mii_if.mdio_write = mdio_write;

862

rp->mii_if.mdio_write = mdio_write;

861

rp->mii_if.phy_id_mask = 0x1f;

863

rp->mii_if.phy_id_mask = 0x1f;

862

rp->mii_if.reg_num_mask = 0x1f;

864

rp->mii_if.reg_num_mask = 0x1f;

863

865

864

/* The chip-specific entries in the device structure. */

866

/* The chip-specific entries in the device structure. */

865

dev->netdev_ops = &rhine_netdev_ops;

867

dev->netdev_ops = &rhine_netdev_ops;

866

dev->ethtool_ops = &netdev_ethtool_ops,

868

dev->ethtool_ops = &netdev_ethtool_ops,

867

dev->watchdog_timeo = TX_TIMEOUT;

869

dev->watchdog_timeo = TX_TIMEOUT;

868

870

869

netif_napi_add(dev, &rp->napi, rhine_napipoll, 64);

871

netif_napi_add(dev, &rp->napi, rhine_napipoll, 64);

870

872

871

if (rp->quirks & rqRhineI)

873

if (rp->quirks & rqRhineI)

872

dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;

874

dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;

873

875

874

if (pdev->revision >= VT6105M)

876

if (pdev->revision >= VT6105M)

875

dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX |

877

dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX |

876

NETIF_F_HW_VLAN_FILTER;

878

NETIF_F_HW_VLAN_FILTER;

877

879

878

/* dev->name not defined before register_netdev()! */

880

/* dev->name not defined before register_netdev()! */

879

rc = register_netdev(dev);

881

rc = register_netdev(dev);

880

if (rc)

882

if (rc)

881

goto err_out_unmap;

883

goto err_out_unmap;

882

884

883

netdev_info(dev, "VIA %s at 0x%lx, %pM, IRQ %d\n",

885

netdev_info(dev, "VIA %s at 0x%lx, %pM, IRQ %d\n",

884

name,

886

name,

885

#ifdef USE_MMIO

887

#ifdef USE_MMIO

886

memaddr,

888

memaddr,

887

#else

889

#else

888

(long)ioaddr,

890

(long)ioaddr,

889

#endif

891

#endif

890

dev->dev_addr, pdev->irq);

892

dev->dev_addr, pdev->irq);

891

893

892

pci_set_drvdata(pdev, dev);

894

pci_set_drvdata(pdev, dev);

893

895

894

{

896

{

895

u16 mii_cmd;

897

u16 mii_cmd;

896

int mii_status = mdio_read(dev, phy_id, 1);

898

int mii_status = mdio_read(dev, phy_id, 1);

897

mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE;

899

mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE;

898

mdio_write(dev, phy_id, MII_BMCR, mii_cmd);

900

mdio_write(dev, phy_id, MII_BMCR, mii_cmd);

899

if (mii_status != 0xffff && mii_status != 0x0000) {

901

if (mii_status != 0xffff && mii_status != 0x0000) {

900

rp->mii_if.advertising = mdio_read(dev, phy_id, 4);

902

rp->mii_if.advertising = mdio_read(dev, phy_id, 4);

901

netdev_info(dev,

903

netdev_info(dev,

902

"MII PHY found at address %d, status 0x%04x advertising %04x Link %04x\n",

904

"MII PHY found at address %d, status 0x%04x advertising %04x Link %04x\n",

903

phy_id,

905

phy_id,

904

mii_status, rp->mii_if.advertising,

906

mii_status, rp->mii_if.advertising,

905

mdio_read(dev, phy_id, 5));

907

mdio_read(dev, phy_id, 5));

906

908

907

/* set IFF_RUNNING */

909

/* set IFF_RUNNING */

908

if (mii_status & BMSR_LSTATUS)

910

if (mii_status & BMSR_LSTATUS)

909

netif_carrier_on(dev);

911

netif_carrier_on(dev);

910

else

912

else

911

netif_carrier_off(dev);

913

netif_carrier_off(dev);

912

914

913

}

915

}

914

}

916

}

915

rp->mii_if.phy_id = phy_id;

917

rp->mii_if.phy_id = phy_id;

916

if (debug > 1 && avoid_D3)

918

if (debug > 1 && avoid_D3)

917

netdev_info(dev, "No D3 power state at shutdown\n");

919

netdev_info(dev, "No D3 power state at shutdown\n");

918

920

919

return 0;

921

return 0;

920

922

921

err_out_unmap:

923

err_out_unmap:

922

pci_iounmap(pdev, ioaddr);

924

pci_iounmap(pdev, ioaddr);

923

err_out_free_res:

925

err_out_free_res:

924

pci_release_regions(pdev);

926

pci_release_regions(pdev);

925

err_out_free_netdev:

927

err_out_free_netdev:

926

free_netdev(dev);

928

free_netdev(dev);

927

err_out:

929

err_out:

928

return rc;

930

return rc;

929

}

931

}

930

932

931

static int alloc_ring(struct net_device* dev)

933

static int alloc_ring(struct net_device* dev)

932

{

934

{

933

struct rhine_private *rp = netdev_priv(dev);

935

struct rhine_private *rp = netdev_priv(dev);

934

void *ring;

936

void *ring;

935

dma_addr_t ring_dma;

937

dma_addr_t ring_dma;

936

938

937

ring = pci_alloc_consistent(rp->pdev,

939

ring = pci_alloc_consistent(rp->pdev,

938

RX_RING_SIZE * sizeof(struct rx_desc) +

940

RX_RING_SIZE * sizeof(struct rx_desc) +

939

TX_RING_SIZE * sizeof(struct tx_desc),

941

TX_RING_SIZE * sizeof(struct tx_desc),

940

&ring_dma);

942

&ring_dma);

941

if (!ring) {

943

if (!ring) {

942

netdev_err(dev, "Could not allocate DMA memory\n");

944

netdev_err(dev, "Could not allocate DMA memory\n");

943

return -ENOMEM;

945

return -ENOMEM;

944

}

946

}

945

if (rp->quirks & rqRhineI) {

947

if (rp->quirks & rqRhineI) {

946

rp->tx_bufs = pci_alloc_consistent(rp->pdev,

948

rp->tx_bufs = pci_alloc_consistent(rp->pdev,

947

PKT_BUF_SZ * TX_RING_SIZE,

949

PKT_BUF_SZ * TX_RING_SIZE,

948

&rp->tx_bufs_dma);

950

&rp->tx_bufs_dma);

949

if (rp->tx_bufs == NULL) {

951

if (rp->tx_bufs == NULL) {

950

pci_free_consistent(rp->pdev,

952

pci_free_consistent(rp->pdev,

951

RX_RING_SIZE * sizeof(struct rx_desc) +

953

RX_RING_SIZE * sizeof(struct rx_desc) +

952

TX_RING_SIZE * sizeof(struct tx_desc),

954

TX_RING_SIZE * sizeof(struct tx_desc),

953

ring, ring_dma);

955

ring, ring_dma);

954

return -ENOMEM;

956

return -ENOMEM;

955

}

957

}

956

}

958

}

957

959

958

rp->rx_ring = ring;

960

rp->rx_ring = ring;

959

rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc);

961

rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc);

960

rp->rx_ring_dma = ring_dma;

962

rp->rx_ring_dma = ring_dma;

961

rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc);

963

rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc);

962

964

963

return 0;

965

return 0;

964

}

966

}

965

967

966

static void free_ring(struct net_device* dev)

968

static void free_ring(struct net_device* dev)

967

{

969

{

968

struct rhine_private *rp = netdev_priv(dev);

970

struct rhine_private *rp = netdev_priv(dev);

969

971

970

pci_free_consistent(rp->pdev,

972

pci_free_consistent(rp->pdev,

971

RX_RING_SIZE * sizeof(struct rx_desc) +

973

RX_RING_SIZE * sizeof(struct rx_desc) +

972

TX_RING_SIZE * sizeof(struct tx_desc),

974

TX_RING_SIZE * sizeof(struct tx_desc),

973

rp->rx_ring, rp->rx_ring_dma);

975

rp->rx_ring, rp->rx_ring_dma);

974

rp->tx_ring = NULL;

976

rp->tx_ring = NULL;

975

977

976

if (rp->tx_bufs)

978

if (rp->tx_bufs)

977

pci_free_consistent(rp->pdev, PKT_BUF_SZ * TX_RING_SIZE,

979

pci_free_consistent(rp->pdev, PKT_BUF_SZ * TX_RING_SIZE,

978

rp->tx_bufs, rp->tx_bufs_dma);

980

rp->tx_bufs, rp->tx_bufs_dma);

979

981

980

rp->tx_bufs = NULL;

982

rp->tx_bufs = NULL;

981

983

982

}

984

}

983

985

984

static void alloc_rbufs(struct net_device *dev)

986

static void alloc_rbufs(struct net_device *dev)

985

{

987

{

986

struct rhine_private *rp = netdev_priv(dev);

988

struct rhine_private *rp = netdev_priv(dev);

987

dma_addr_t next;

989

dma_addr_t next;

988

int i;

990

int i;

989

991

990

rp->dirty_rx = rp->cur_rx = 0;

992

rp->dirty_rx = rp->cur_rx = 0;

991

993

992

rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);

994

rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);

993

rp->rx_head_desc = &rp->rx_ring[0];

995

rp->rx_head_desc = &rp->rx_ring[0];

994

next = rp->rx_ring_dma;

996

next = rp->rx_ring_dma;

995

997

996

/* Init the ring entries */

998

/* Init the ring entries */

997

for (i = 0; i < RX_RING_SIZE; i++) {

999

for (i = 0; i < RX_RING_SIZE; i++) {

998

rp->rx_ring[i].rx_status = 0;

1000

rp->rx_ring[i].rx_status = 0;

999

rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz);

1001

rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz);

1000

next += sizeof(struct rx_desc);

1002

next += sizeof(struct rx_desc);

1001

rp->rx_ring[i].next_desc = cpu_to_le32(next);

1003

rp->rx_ring[i].next_desc = cpu_to_le32(next);

1002

rp->rx_skbuff[i] = NULL;

1004

rp->rx_skbuff[i] = NULL;

1003

}

1005

}

1004

/* Mark the last entry as wrapping the ring. */

1006

/* Mark the last entry as wrapping the ring. */

1005

rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma);

1007

rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma);

1006

1008

1007

/* Fill in the Rx buffers. Handle allocation failure gracefully. */

1009

/* Fill in the Rx buffers. Handle allocation failure gracefully. */

1008

for (i = 0; i < RX_RING_SIZE; i++) {

1010

for (i = 0; i < RX_RING_SIZE; i++) {

1009

struct sk_buff *skb = netdev_alloc_skb(dev, rp->rx_buf_sz);

1011

struct sk_buff *skb = netdev_alloc_skb(dev, rp->rx_buf_sz);

1010

rp->rx_skbuff[i] = skb;

1012

rp->rx_skbuff[i] = skb;

1011

if (skb == NULL)

1013

if (skb == NULL)

1012

break;

1014

break;

1013

skb->dev = dev; /* Mark as being used by this device. */

1015

skb->dev = dev; /* Mark as being used by this device. */

1014

1016

1015

rp->rx_skbuff_dma[i] =

1017

rp->rx_skbuff_dma[i] =

1016

pci_map_single(rp->pdev, skb->data, rp->rx_buf_sz,

1018

pci_map_single(rp->pdev, skb->data, rp->rx_buf_sz,

1017

PCI_DMA_FROMDEVICE);

1019

PCI_DMA_FROMDEVICE);

1018

1020

1019

rp->rx_ring[i].addr = cpu_to_le32(rp->rx_skbuff_dma[i]);

1021

rp->rx_ring[i].addr = cpu_to_le32(rp->rx_skbuff_dma[i]);

1020

rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn);

1022

rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn);

1021

}

1023

}

1022

rp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);

1024

rp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);

1023

}

1025

}

1024

1026

1025

static void free_rbufs(struct net_device* dev)

1027

static void free_rbufs(struct net_device* dev)

1026

{

1028

{

1027

struct rhine_private *rp = netdev_priv(dev);

1029

struct rhine_private *rp = netdev_priv(dev);

1028

int i;

1030

int i;

1029

1031

1030

/* Free all the skbuffs in the Rx queue. */

1032

/* Free all the skbuffs in the Rx queue. */

1031

for (i = 0; i < RX_RING_SIZE; i++) {

1033

for (i = 0; i < RX_RING_SIZE; i++) {

1032

rp->rx_ring[i].rx_status = 0;

1034

rp->rx_ring[i].rx_status = 0;

1033

rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */

1035

rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */

1034

if (rp->rx_skbuff[i]) {

1036

if (rp->rx_skbuff[i]) {

1035

pci_unmap_single(rp->pdev,

1037

pci_unmap_single(rp->pdev,

1036

rp->rx_skbuff_dma[i],

1038

rp->rx_skbuff_dma[i],

1037

rp->rx_buf_sz, PCI_DMA_FROMDEVICE);

1039

rp->rx_buf_sz, PCI_DMA_FROMDEVICE);

1038

dev_kfree_skb(rp->rx_skbuff[i]);

1040

dev_kfree_skb(rp->rx_skbuff[i]);

1039

}

1041

}

1040

rp->rx_skbuff[i] = NULL;

1042

rp->rx_skbuff[i] = NULL;

1041

}

1043

}

1042

}

1044

}

1043

1045

1044

static void alloc_tbufs(struct net_device* dev)

1046

static void alloc_tbufs(struct net_device* dev)

1045

{

1047

{

1046

struct rhine_private *rp = netdev_priv(dev);

1048

struct rhine_private *rp = netdev_priv(dev);

1047

dma_addr_t next;

1049

dma_addr_t next;

1048

int i;

1050

int i;

1049

1051

1050

rp->dirty_tx = rp->cur_tx = 0;

1052

rp->dirty_tx = rp->cur_tx = 0;

1051

next = rp->tx_ring_dma;

1053

next = rp->tx_ring_dma;

1052

for (i = 0; i < TX_RING_SIZE; i++) {

1054

for (i = 0; i < TX_RING_SIZE; i++) {

1053

rp->tx_skbuff[i] = NULL;

1055

rp->tx_skbuff[i] = NULL;

1054

rp->tx_ring[i].tx_status = 0;

1056

rp->tx_ring[i].tx_status = 0;

1055

rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);

1057

rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);

1056

next += sizeof(struct tx_desc);

1058

next += sizeof(struct tx_desc);

1057

rp->tx_ring[i].next_desc = cpu_to_le32(next);

1059

rp->tx_ring[i].next_desc = cpu_to_le32(next);

1058

if (rp->quirks & rqRhineI)

1060

if (rp->quirks & rqRhineI)

1059

rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ];

1061

rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ];

1060

}

1062

}

1061

rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma);

1063

rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma);

1062

1064

1063

}

1065

}

1064

1066

1065

static void free_tbufs(struct net_device* dev)

1067

static void free_tbufs(struct net_device* dev)

1066

{

1068

{

1067

struct rhine_private *rp = netdev_priv(dev);

1069

struct rhine_private *rp = netdev_priv(dev);

1068

int i;

1070

int i;

1069

1071

1070

for (i = 0; i < TX_RING_SIZE; i++) {

1072

for (i = 0; i < TX_RING_SIZE; i++) {

1071

rp->tx_ring[i].tx_status = 0;

1073

rp->tx_ring[i].tx_status = 0;

1072

rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);

1074

rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);

1073

rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */

1075

rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */

1074

if (rp->tx_skbuff[i]) {

1076

if (rp->tx_skbuff[i]) {

1075

if (rp->tx_skbuff_dma[i]) {

1077

if (rp->tx_skbuff_dma[i]) {

1076

pci_unmap_single(rp->pdev,

1078

pci_unmap_single(rp->pdev,

1077

rp->tx_skbuff_dma[i],

1079

rp->tx_skbuff_dma[i],

1078

rp->tx_skbuff[i]->len,

1080

rp->tx_skbuff[i]->len,

1079

PCI_DMA_TODEVICE);

1081

PCI_DMA_TODEVICE);

1080

}

1082

}

1081

dev_kfree_skb(rp->tx_skbuff[i]);

1083

dev_kfree_skb(rp->tx_skbuff[i]);

1082

}

1084

}

1083

rp->tx_skbuff[i] = NULL;

1085

rp->tx_skbuff[i] = NULL;

1084

rp->tx_buf[i] = NULL;

1086

rp->tx_buf[i] = NULL;

1085

}

1087

}

1086

}

1088

}

1087

1089

1088

static void rhine_check_media(struct net_device *dev, unsigned int init_media)

1090

static void rhine_check_media(struct net_device *dev, unsigned int init_media)

1089

{

1091

{

1090

struct rhine_private *rp = netdev_priv(dev);

1092

struct rhine_private *rp = netdev_priv(dev);

1091

void __iomem *ioaddr = rp->base;

1093

void __iomem *ioaddr = rp->base;

1092

1094

1093

mii_check_media(&rp->mii_if, debug, init_media);

1095

mii_check_media(&rp->mii_if, debug, init_media);

1094

1096

1095

if (rp->mii_if.full_duplex)

1097

if (rp->mii_if.full_duplex)

1096

iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex,

1098

iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex,

1097

ioaddr + ChipCmd1);

1099

ioaddr + ChipCmd1);

1098

else

1100

else

1099

iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex,

1101

iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex,

1100

ioaddr + ChipCmd1);

1102

ioaddr + ChipCmd1);

1101

if (debug > 1)

1103

if (debug > 1)

1102

netdev_info(dev, "force_media %d, carrier %d\n",

1104

netdev_info(dev, "force_media %d, carrier %d\n",

1103

rp->mii_if.force_media, netif_carrier_ok(dev));

1105

rp->mii_if.force_media, netif_carrier_ok(dev));

1104

}

1106

}

1105

1107

1106

/* Called after status of force_media possibly changed */

1108

/* Called after status of force_media possibly changed */

1107

static void rhine_set_carrier(struct mii_if_info *mii)

1109

static void rhine_set_carrier(struct mii_if_info *mii)

1108

{

1110

{

1109

if (mii->force_media) {

1111

if (mii->force_media) {

1110

/* autoneg is off: Link is always assumed to be up */

1112

/* autoneg is off: Link is always assumed to be up */

1111

if (!netif_carrier_ok(mii->dev))

1113

if (!netif_carrier_ok(mii->dev))

1112

netif_carrier_on(mii->dev);

1114

netif_carrier_on(mii->dev);

1113

}

1115

}

1114

else /* Let MMI library update carrier status */

1116

else /* Let MMI library update carrier status */

1115

rhine_check_media(mii->dev, 0);

1117

rhine_check_media(mii->dev, 0);

1116

if (debug > 1)

1118

if (debug > 1)

1117

netdev_info(mii->dev, "force_media %d, carrier %d\n",

1119

netdev_info(mii->dev, "force_media %d, carrier %d\n",

1118

mii->force_media, netif_carrier_ok(mii->dev));

1120

mii->force_media, netif_carrier_ok(mii->dev));

1119

}

1121

}

1120

1122

1121

/**

1123

/**

1122

* rhine_set_cam - set CAM multicast filters

1124

* rhine_set_cam - set CAM multicast filters

1123

* @ioaddr: register block of this Rhine

1125

* @ioaddr: register block of this Rhine

1124

* @idx: multicast CAM index [0..MCAM_SIZE-1]

1126

* @idx: multicast CAM index [0..MCAM_SIZE-1]

1125

* @addr: multicast address (6 bytes)

1127

* @addr: multicast address (6 bytes)

1126

*

1128

*

1127

* Load addresses into multicast filters.

1129

* Load addresses into multicast filters.

1128

*/

1130

*/

1129

static void rhine_set_cam(void __iomem *ioaddr, int idx, u8 *addr)

1131

static void rhine_set_cam(void __iomem *ioaddr, int idx, u8 *addr)

1130

{

1132

{

1131

int i;

1133

int i;

1132

1134

1133

iowrite8(CAMC_CAMEN, ioaddr + CamCon);

1135

iowrite8(CAMC_CAMEN, ioaddr + CamCon);

1134

wmb();

1136

wmb();

1135

1137

1136

/* Paranoid -- idx out of range should never happen */

1138

/* Paranoid -- idx out of range should never happen */

1137

idx &= (MCAM_SIZE - 1);

1139

idx &= (MCAM_SIZE - 1);

1138

1140

1139

iowrite8((u8) idx, ioaddr + CamAddr);

1141

iowrite8((u8) idx, ioaddr + CamAddr);

1140

1142

1141

for (i = 0; i < 6; i++, addr++)

1143

for (i = 0; i < 6; i++, addr++)

1142

iowrite8(*addr, ioaddr + MulticastFilter0 + i);

1144

iowrite8(*addr, ioaddr + MulticastFilter0 + i);

1143

udelay(10);

1145

udelay(10);

1144

wmb();

1146

wmb();

1145

1147

1146

iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);

1148

iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);

1147

udelay(10);

1149

udelay(10);

1148

1150

1149

iowrite8(0, ioaddr + CamCon);

1151

iowrite8(0, ioaddr + CamCon);

1150

}

1152

}

1151

1153

1152

/**

1154

/**

1153

* rhine_set_vlan_cam - set CAM VLAN filters

1155

* rhine_set_vlan_cam - set CAM VLAN filters

1154

* @ioaddr: register block of this Rhine

1156

* @ioaddr: register block of this Rhine

1155

* @idx: VLAN CAM index [0..VCAM_SIZE-1]

1157

* @idx: VLAN CAM index [0..VCAM_SIZE-1]

1156

* @addr: VLAN ID (2 bytes)

1158

* @addr: VLAN ID (2 bytes)

1157

*

1159

*

1158

* Load addresses into VLAN filters.

1160

* Load addresses into VLAN filters.

1159

*/

1161

*/

1160

static void rhine_set_vlan_cam(void __iomem *ioaddr, int idx, u8 *addr)

1162

static void rhine_set_vlan_cam(void __iomem *ioaddr, int idx, u8 *addr)

1161

{

1163

{

1162

iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);

1164

iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);

1163

wmb();

1165

wmb();

1164

1166

1165

/* Paranoid -- idx out of range should never happen */

1167

/* Paranoid -- idx out of range should never happen */

1166

idx &= (VCAM_SIZE - 1);

1168

idx &= (VCAM_SIZE - 1);

1167

1169

1168

iowrite8((u8) idx, ioaddr + CamAddr);

1170

iowrite8((u8) idx, ioaddr + CamAddr);

1169

1171

1170

iowrite16(*((u16 *) addr), ioaddr + MulticastFilter0 + 6);

1172

iowrite16(*((u16 *) addr), ioaddr + MulticastFilter0 + 6);

1171

udelay(10);

1173

udelay(10);

1172

wmb();

1174

wmb();

1173

1175

1174

iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);

1176

iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);

1175

udelay(10);

1177

udelay(10);

1176

1178

1177

iowrite8(0, ioaddr + CamCon);

1179

iowrite8(0, ioaddr + CamCon);

1178

}

1180

}

1179

1181

1180

/**

1182

/**

1181

* rhine_set_cam_mask - set multicast CAM mask

1183

* rhine_set_cam_mask - set multicast CAM mask

1182

* @ioaddr: register block of this Rhine

1184

* @ioaddr: register block of this Rhine

1183

* @mask: multicast CAM mask

1185

* @mask: multicast CAM mask

1184

*

1186

*

1185

* Mask sets multicast filters active/inactive.

1187

* Mask sets multicast filters active/inactive.

1186

*/

1188

*/

1187

static void rhine_set_cam_mask(void __iomem *ioaddr, u32 mask)

1189

static void rhine_set_cam_mask(void __iomem *ioaddr, u32 mask)

1188

{

1190

{

1189

iowrite8(CAMC_CAMEN, ioaddr + CamCon);

1191

iowrite8(CAMC_CAMEN, ioaddr + CamCon);

1190

wmb();

1192

wmb();

1191

1193

1192

/* write mask */

1194

/* write mask */

1193

iowrite32(mask, ioaddr + CamMask);

1195

iowrite32(mask, ioaddr + CamMask);

1194

1196

1195

/* disable CAMEN */

1197

/* disable CAMEN */

1196

iowrite8(0, ioaddr + CamCon);

1198

iowrite8(0, ioaddr + CamCon);

1197

}

1199

}

1198

1200

1199

/**

1201

/**

1200

* rhine_set_vlan_cam_mask - set VLAN CAM mask

1202

* rhine_set_vlan_cam_mask - set VLAN CAM mask

1201

* @ioaddr: register block of this Rhine

1203

* @ioaddr: register block of this Rhine

1202

* @mask: VLAN CAM mask

1204

* @mask: VLAN CAM mask

1203

*

1205

*

1204

* Mask sets VLAN filters active/inactive.

1206

* Mask sets VLAN filters active/inactive.

1205

*/

1207

*/

1206

static void rhine_set_vlan_cam_mask(void __iomem *ioaddr, u32 mask)

1208

static void rhine_set_vlan_cam_mask(void __iomem *ioaddr, u32 mask)

1207

{

1209

{

1208

iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);

1210

iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);

1209

wmb();

1211

wmb();

1210

1212

1211

/* write mask */

1213

/* write mask */

1212

iowrite32(mask, ioaddr + CamMask);

1214

iowrite32(mask, ioaddr + CamMask);

1213

1215

1214

/* disable CAMEN */

1216

/* disable CAMEN */

1215

iowrite8(0, ioaddr + CamCon);

1217

iowrite8(0, ioaddr + CamCon);

1216

}

1218

}

1217

1219

1218

/**

1220

/**

1219

* rhine_init_cam_filter - initialize CAM filters

1221

* rhine_init_cam_filter - initialize CAM filters

1220

* @dev: network device

1222

* @dev: network device

1221

*

1223

*

1222

* Initialize (disable) hardware VLAN and multicast support on this

1224

* Initialize (disable) hardware VLAN and multicast support on this

1223

* Rhine.

1225

* Rhine.

1224

*/

1226

*/

1225

static void rhine_init_cam_filter(struct net_device *dev)

1227

static void rhine_init_cam_filter(struct net_device *dev)

1226

{

1228

{

1227

struct rhine_private *rp = netdev_priv(dev);

1229

struct rhine_private *rp = netdev_priv(dev);

1228

void __iomem *ioaddr = rp->base;

1230

void __iomem *ioaddr = rp->base;

1229

1231

1230

/* Disable all CAMs */

1232

/* Disable all CAMs */

1231

rhine_set_vlan_cam_mask(ioaddr, 0);

1233

rhine_set_vlan_cam_mask(ioaddr, 0);

1232

rhine_set_cam_mask(ioaddr, 0);

1234

rhine_set_cam_mask(ioaddr, 0);

1233

1235

1234

/* disable hardware VLAN support */

1236

/* disable hardware VLAN support */

1235

BYTE_REG_BITS_ON(TCR_PQEN, ioaddr + TxConfig);

1237

BYTE_REG_BITS_ON(TCR_PQEN, ioaddr + TxConfig);

1236

BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1);

1238

BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1);

1237

}

1239

}

1238

1240

1239

/**

1241

/**

1240

* rhine_update_vcam - update VLAN CAM filters

1242

* rhine_update_vcam - update VLAN CAM filters

1241

* @rp: rhine_private data of this Rhine

1243

* @rp: rhine_private data of this Rhine

1242

*

1244

*

1243

* Update VLAN CAM filters to match configuration change.

1245

* Update VLAN CAM filters to match configuration change.

1244

*/

1246

*/

1245

static void rhine_update_vcam(struct net_device *dev)

1247

static void rhine_update_vcam(struct net_device *dev)

1246

{

1248

{

1247

struct rhine_private *rp = netdev_priv(dev);

1249

struct rhine_private *rp = netdev_priv(dev);

1248

void __iomem *ioaddr = rp->base;

1250

void __iomem *ioaddr = rp->base;

1249

u16 vid;

1251

u16 vid;

1250

u32 vCAMmask = 0; /* 32 vCAMs (6105M and better) */

1252

u32 vCAMmask = 0; /* 32 vCAMs (6105M and better) */

1251

unsigned int i = 0;

1253

unsigned int i = 0;

1252

1254

1253

for_each_set_bit(vid, rp->active_vlans, VLAN_N_VID) {

1255

for_each_set_bit(vid, rp->active_vlans, VLAN_N_VID) {

1254

rhine_set_vlan_cam(ioaddr, i, (u8 *)&vid);

1256

rhine_set_vlan_cam(ioaddr, i, (u8 *)&vid);

1255

vCAMmask |= 1 << i;

1257

vCAMmask |= 1 << i;

1256

if (++i >= VCAM_SIZE)

1258

if (++i >= VCAM_SIZE)

1257

break;

1259

break;

1258

}

1260

}

1259

rhine_set_vlan_cam_mask(ioaddr, vCAMmask);

1261

rhine_set_vlan_cam_mask(ioaddr, vCAMmask);

1260

}

1262

}

1261

1263

1262

static void rhine_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)

1264

static void rhine_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)

1263

{

1265

{

1264

struct rhine_private *rp = netdev_priv(dev);

1266

struct rhine_private *rp = netdev_priv(dev);

1265

1267

1266

spin_lock_irq(&rp->lock);

1268

spin_lock_irq(&rp->lock);

1267

set_bit(vid, rp->active_vlans);

1269

set_bit(vid, rp->active_vlans);

1268

rhine_update_vcam(dev);

1270

rhine_update_vcam(dev);

1269

spin_unlock_irq(&rp->lock);

1271

spin_unlock_irq(&rp->lock);

1270

}

1272

}

1271

1273

1272

static void rhine_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)

1274

static void rhine_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)

1273

{

1275

{

1274

struct rhine_private *rp = netdev_priv(dev);

1276

struct rhine_private *rp = netdev_priv(dev);

1275

1277

1276

spin_lock_irq(&rp->lock);

1278

spin_lock_irq(&rp->lock);

1277

clear_bit(vid, rp->active_vlans);

1279

clear_bit(vid, rp->active_vlans);

1278

rhine_update_vcam(dev);

1280

rhine_update_vcam(dev);

1279

spin_unlock_irq(&rp->lock);

1281

spin_unlock_irq(&rp->lock);

1280

}

1282

}

1281

1283

1282

static void init_registers(struct net_device *dev)

1284

static void init_registers(struct net_device *dev)

1283

{

1285

{

1284

struct rhine_private *rp = netdev_priv(dev);

1286

struct rhine_private *rp = netdev_priv(dev);

1285

void __iomem *ioaddr = rp->base;

1287

void __iomem *ioaddr = rp->base;

1286

int i;

1288

int i;

1287

1289

1288

for (i = 0; i < 6; i++)

1290

for (i = 0; i < 6; i++)

1289

iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);

1291

iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);

1290

1292

1291

/* Initialize other registers. */

1293

/* Initialize other registers. */

1292

iowrite16(0x0006, ioaddr + PCIBusConfig); /* Tune configuration??? */

1294

iowrite16(0x0006, ioaddr + PCIBusConfig); /* Tune configuration??? */

1293

/* Configure initial FIFO thresholds. */

1295

/* Configure initial FIFO thresholds. */

1294

iowrite8(0x20, ioaddr + TxConfig);

1296

iowrite8(0x20, ioaddr + TxConfig);

1295

rp->tx_thresh = 0x20;

1297

rp->tx_thresh = 0x20;

1296

rp->rx_thresh = 0x60; /* Written in rhine_set_rx_mode(). */

1298

rp->rx_thresh = 0x60; /* Written in rhine_set_rx_mode(). */

1297

1299

1298

iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr);

1300

iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr);

1299

iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr);

1301

iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr);

1300

1302

1301

rhine_set_rx_mode(dev);

1303

rhine_set_rx_mode(dev);

1302

1304

1303

if (rp->pdev->revision >= VT6105M)

1305

if (rp->pdev->revision >= VT6105M)

1304

rhine_init_cam_filter(dev);

1306

rhine_init_cam_filter(dev);

1305

1307

1306

napi_enable(&rp->napi);

1308

napi_enable(&rp->napi);

1307

1309

1308

/* Enable interrupts by setting the interrupt mask. */

1310

/* Enable interrupts by setting the interrupt mask. */

1309

iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |

1311

iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |

1310

IntrRxDropped | IntrRxNoBuf | IntrTxAborted |

1312

IntrRxDropped | IntrRxNoBuf | IntrTxAborted |

1311

IntrTxDone | IntrTxError | IntrTxUnderrun |

1313

IntrTxDone | IntrTxError | IntrTxUnderrun |

1312

IntrPCIErr | IntrStatsMax | IntrLinkChange,

1314

IntrPCIErr | IntrStatsMax | IntrLinkChange,

1313

ioaddr + IntrEnable);

1315

ioaddr + IntrEnable);

1314

1316

1315

iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8),

1317

iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8),

1316

ioaddr + ChipCmd);

1318

ioaddr + ChipCmd);

1317

rhine_check_media(dev, 1);

1319

rhine_check_media(dev, 1);

1318

}

1320

}

1319

1321

1320

/* Enable MII link status auto-polling (required for IntrLinkChange) */

1322

/* Enable MII link status auto-polling (required for IntrLinkChange) */

1321

static void rhine_enable_linkmon(void __iomem *ioaddr)

1323

static void rhine_enable_linkmon(void __iomem *ioaddr)

1322

{

1324

{

1323

iowrite8(0, ioaddr + MIICmd);

1325

iowrite8(0, ioaddr + MIICmd);

1324

iowrite8(MII_BMSR, ioaddr + MIIRegAddr);

1326

iowrite8(MII_BMSR, ioaddr + MIIRegAddr);

1325

iowrite8(0x80, ioaddr + MIICmd);

1327

iowrite8(0x80, ioaddr + MIICmd);

1326

1328

1327

RHINE_WAIT_FOR((ioread8(ioaddr + MIIRegAddr) & 0x20));

1329

RHINE_WAIT_FOR((ioread8(ioaddr + MIIRegAddr) & 0x20));

1328

1330

1329

iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr);

1331

iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr);

1330

}

1332

}

1331

1333

1332

/* Disable MII link status auto-polling (required for MDIO access) */

1334

/* Disable MII link status auto-polling (required for MDIO access) */

1333

static void rhine_disable_linkmon(void __iomem *ioaddr, u32 quirks)

1335

static void rhine_disable_linkmon(void __iomem *ioaddr, u32 quirks)

1334

{

1336

{

1335

iowrite8(0, ioaddr + MIICmd);

1337

iowrite8(0, ioaddr + MIICmd);

1336

1338

1337

if (quirks & rqRhineI) {

1339

if (quirks & rqRhineI) {

1338

iowrite8(0x01, ioaddr + MIIRegAddr); // MII_BMSR

1340

iowrite8(0x01, ioaddr + MIIRegAddr); // MII_BMSR

1339

1341

1340

/* Can be called from ISR. Evil. */

1342

/* Can be called from ISR. Evil. */

1341

mdelay(1);

1343

mdelay(1);

1342

1344

1343

/* 0x80 must be set immediately before turning it off */

1345

/* 0x80 must be set immediately before turning it off */

1344

iowrite8(0x80, ioaddr + MIICmd);

1346

iowrite8(0x80, ioaddr + MIICmd);

1345

1347

1346

RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x20);

1348

RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x20);

1347

1349

1348

/* Heh. Now clear 0x80 again. */

1350

/* Heh. Now clear 0x80 again. */

1349

iowrite8(0, ioaddr + MIICmd);

1351

iowrite8(0, ioaddr + MIICmd);

1350

}

1352

}

1351

else

1353

else

1352

RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x80);

1354

RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x80);

1353

}

1355

}

1354

1356

1355

/* Read and write over the MII Management Data I/O (MDIO) interface. */

1357

/* Read and write over the MII Management Data I/O (MDIO) interface. */

1356

1358

1357

static int mdio_read(struct net_device *dev, int phy_id, int regnum)

1359

static int mdio_read(struct net_device *dev, int phy_id, int regnum)

1358

{

1360

{

1359

struct rhine_private *rp = netdev_priv(dev);

1361

struct rhine_private *rp = netdev_priv(dev);

1360

void __iomem *ioaddr = rp->base;

1362

void __iomem *ioaddr = rp->base;

1361

int result;

1363

int result;

1362

1364

1363

rhine_disable_linkmon(ioaddr, rp->quirks);

1365

rhine_disable_linkmon(ioaddr, rp->quirks);

1364

1366

1365

/* rhine_disable_linkmon already cleared MIICmd */

1367

/* rhine_disable_linkmon already cleared MIICmd */

1366

iowrite8(phy_id, ioaddr + MIIPhyAddr);

1368

iowrite8(phy_id, ioaddr + MIIPhyAddr);

1367

iowrite8(regnum, ioaddr + MIIRegAddr);

1369

iowrite8(regnum, ioaddr + MIIRegAddr);

1368

iowrite8(0x40, ioaddr + MIICmd); /* Trigger read */

1370

iowrite8(0x40, ioaddr + MIICmd); /* Trigger read */

1369

RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x40));

1371

RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x40));

1370

result = ioread16(ioaddr + MIIData);

1372

result = ioread16(ioaddr + MIIData);

1371

1373

1372

rhine_enable_linkmon(ioaddr);

1374

rhine_enable_linkmon(ioaddr);

1373

return result;

1375

return result;

1374

}

1376

}

1375

1377

1376

static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value)

1378

static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value)

1377

{

1379

{

1378

struct rhine_private *rp = netdev_priv(dev);

1380

struct rhine_private *rp = netdev_priv(dev);

1379

void __iomem *ioaddr = rp->base;

1381

void __iomem *ioaddr = rp->base;

1380

1382

1381

rhine_disable_linkmon(ioaddr, rp->quirks);

1383

rhine_disable_linkmon(ioaddr, rp->quirks);

1382

1384

1383

/* rhine_disable_linkmon already cleared MIICmd */

1385

/* rhine_disable_linkmon already cleared MIICmd */

1384

iowrite8(phy_id, ioaddr + MIIPhyAddr);

1386

iowrite8(phy_id, ioaddr + MIIPhyAddr);

1385

iowrite8(regnum, ioaddr + MIIRegAddr);

1387

iowrite8(regnum, ioaddr + MIIRegAddr);

1386

iowrite16(value, ioaddr + MIIData);

1388

iowrite16(value, ioaddr + MIIData);

1387

iowrite8(0x20, ioaddr + MIICmd); /* Trigger write */

1389

iowrite8(0x20, ioaddr + MIICmd); /* Trigger write */

1388

RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x20));

1390

RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x20));

1389

1391

1390

rhine_enable_linkmon(ioaddr);

1392

rhine_enable_linkmon(ioaddr);

1391

}

1393

}

1392

1394

1393

static int rhine_open(struct net_device *dev)

1395

static int rhine_open(struct net_device *dev)

1394

{

1396

{

1395

struct rhine_private *rp = netdev_priv(dev);

1397

struct rhine_private *rp = netdev_priv(dev);

1396

void __iomem *ioaddr = rp->base;

1398

void __iomem *ioaddr = rp->base;

1397

int rc;

1399

int rc;

1398

1400

1399

rc = request_irq(rp->pdev->irq, rhine_interrupt, IRQF_SHARED, dev->name,

1401

rc = request_irq(rp->pdev->irq, rhine_interrupt, IRQF_SHARED, dev->name,

1400

dev);

1402

dev);

1401

if (rc)

1403

if (rc)

1402

return rc;

1404

return rc;

1403

1405

1404

if (debug > 1)

1406

if (debug > 1)

1405

netdev_dbg(dev, "%s() irq %d\n", __func__, rp->pdev->irq);

1407

netdev_dbg(dev, "%s() irq %d\n", __func__, rp->pdev->irq);

1406

1408

1407

rc = alloc_ring(dev);

1409

rc = alloc_ring(dev);

1408

if (rc) {

1410

if (rc) {

1409

free_irq(rp->pdev->irq, dev);

1411

free_irq(rp->pdev->irq, dev);

1410

return rc;

1412

return rc;

1411

}

1413

}

1412

alloc_rbufs(dev);

1414

alloc_rbufs(dev);

1413

alloc_tbufs(dev);

1415

alloc_tbufs(dev);

1414

rhine_chip_reset(dev);

1416

rhine_chip_reset(dev);

1415

init_registers(dev);

1417

init_registers(dev);

1416

if (debug > 2)

1418

if (debug > 2)

1417

netdev_dbg(dev, "%s() Done - status %04x MII status: %04x\n",

1419

netdev_dbg(dev, "%s() Done - status %04x MII status: %04x\n",

1418

__func__, ioread16(ioaddr + ChipCmd),

1420

__func__, ioread16(ioaddr + ChipCmd),

1419

mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));

1421

mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));

1420

1422

1421

netif_start_queue(dev);

1423

netif_start_queue(dev);

1422

1424

1423

return 0;

1425

return 0;

1424

}

1426

}

1425

1427

1426

static void rhine_reset_task(struct work_struct *work)

1428

static void rhine_reset_task(struct work_struct *work)

1427

{

1429

{

1428

struct rhine_private *rp = container_of(work, struct rhine_private,

1430

struct rhine_private *rp = container_of(work, struct rhine_private,

1429

reset_task);

1431

reset_task);

1430

struct net_device *dev = rp->dev;

1432

struct net_device *dev = rp->dev;

1431

1433

1432

/* protect against concurrent rx interrupts */

1434

/* protect against concurrent rx interrupts */

1433

disable_irq(rp->pdev->irq);

1435

disable_irq(rp->pdev->irq);

1434

1436

1435

napi_disable(&rp->napi);

1437

napi_disable(&rp->napi);

1436

1438

1437

spin_lock_bh(&rp->lock);

1439

spin_lock_bh(&rp->lock);

1438

1440

1439

/* clear all descriptors */

1441

/* clear all descriptors */

1440

free_tbufs(dev);

1442

free_tbufs(dev);

1441

free_rbufs(dev);

1443

free_rbufs(dev);

1442

alloc_tbufs(dev);

1444

alloc_tbufs(dev);

1443

alloc_rbufs(dev);

1445

alloc_rbufs(dev);

1444

1446

1445

/* Reinitialize the hardware. */

1447

/* Reinitialize the hardware. */

1446

rhine_chip_reset(dev);

1448

rhine_chip_reset(dev);

1447

init_registers(dev);

1449

init_registers(dev);

1448

1450

1449

spin_unlock_bh(&rp->lock);

1451

spin_unlock_bh(&rp->lock);

1450

enable_irq(rp->pdev->irq);

1452

enable_irq(rp->pdev->irq);

1451

1453

1452

dev->trans_start = jiffies; /* prevent tx timeout */

1454

dev->trans_start = jiffies; /* prevent tx timeout */

1453

dev->stats.tx_errors++;

1455

dev->stats.tx_errors++;

1454

netif_wake_queue(dev);

1456

netif_wake_queue(dev);

1455

}

1457

}

1456

1458

1457

static void rhine_tx_timeout(struct net_device *dev)

1459

static void rhine_tx_timeout(struct net_device *dev)

1458

{

1460

{

1459

struct rhine_private *rp = netdev_priv(dev);

1461

struct rhine_private *rp = netdev_priv(dev);

1460

void __iomem *ioaddr = rp->base;

1462

void __iomem *ioaddr = rp->base;

1461

1463

1462

netdev_warn(dev, "Transmit timed out, status %04x, PHY status %04x, resetting...\n",

1464

netdev_warn(dev, "Transmit timed out, status %04x, PHY status %04x, resetting...\n",

1463

ioread16(ioaddr + IntrStatus),

1465

ioread16(ioaddr + IntrStatus),

1464

mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));

1466

mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));

1465

1467

1466

schedule_work(&rp->reset_task);

1468

schedule_work(&rp->reset_task);

1467

}

1469

}

1468

1470

1469

static netdev_tx_t rhine_start_tx(struct sk_buff *skb,

1471

static netdev_tx_t rhine_start_tx(struct sk_buff *skb,

1470

struct net_device *dev)

1472

struct net_device *dev)

1471

{

1473

{

1472

struct rhine_private *rp = netdev_priv(dev);

1474

struct rhine_private *rp = netdev_priv(dev);

1473

void __iomem *ioaddr = rp->base;

1475

void __iomem *ioaddr = rp->base;

1474

unsigned entry;

1476

unsigned entry;

1475

unsigned long flags;

1477

unsigned long flags;

1476

1478

1477

/* Caution: the write order is important here, set the field

1479

/* Caution: the write order is important here, set the field

1478

with the "ownership" bits last. */

1480

with the "ownership" bits last. */

1479

1481

1480

/* Calculate the next Tx descriptor entry. */

1482

/* Calculate the next Tx descriptor entry. */

1481

entry = rp->cur_tx % TX_RING_SIZE;

1483

entry = rp->cur_tx % TX_RING_SIZE;

1482

1484

1483

if (skb_padto(skb, ETH_ZLEN))

1485

if (skb_padto(skb, ETH_ZLEN))

1484

return NETDEV_TX_OK;

1486

return NETDEV_TX_OK;

1485

1487

1486

rp->tx_skbuff[entry] = skb;

1488

rp->tx_skbuff[entry] = skb;

1487

1489

1488

if ((rp->quirks & rqRhineI) &&

1490

if ((rp->quirks & rqRhineI) &&

1489

(((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_PARTIAL)) {

1491

(((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_PARTIAL)) {

1490

/* Must use alignment buffer. */

1492

/* Must use alignment buffer. */

1491

if (skb->len > PKT_BUF_SZ) {

1493

if (skb->len > PKT_BUF_SZ) {

1492

/* packet too long, drop it */

1494

/* packet too long, drop it */

1493

dev_kfree_skb(skb);

1495

dev_kfree_skb(skb);

1494

rp->tx_skbuff[entry] = NULL;

1496

rp->tx_skbuff[entry] = NULL;

1495

dev->stats.tx_dropped++;

1497

dev->stats.tx_dropped++;

1496

return NETDEV_TX_OK;

1498

return NETDEV_TX_OK;

1497

}

1499

}

1498

1500

1499

/* Padding is not copied and so must be redone. */

1501

/* Padding is not copied and so must be redone. */

1500

skb_copy_and_csum_dev(skb, rp->tx_buf[entry]);

1502

skb_copy_and_csum_dev(skb, rp->tx_buf[entry]);

1501

if (skb->len < ETH_ZLEN)

1503

if (skb->len < ETH_ZLEN)

1502

memset(rp->tx_buf[entry] + skb->len, 0,

1504

memset(rp->tx_buf[entry] + skb->len, 0,

1503

ETH_ZLEN - skb->len);

1505

ETH_ZLEN - skb->len);

1504

rp->tx_skbuff_dma[entry] = 0;

1506

rp->tx_skbuff_dma[entry] = 0;

1505

rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma +

1507

rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma +

1506

(rp->tx_buf[entry] -

1508

(rp->tx_buf[entry] -

1507

rp->tx_bufs));

1509

rp->tx_bufs));

1508

} else {

1510

} else {

1509

rp->tx_skbuff_dma[entry] =

1511

rp->tx_skbuff_dma[entry] =

1510

pci_map_single(rp->pdev, skb->data, skb->len,

1512

pci_map_single(rp->pdev, skb->data, skb->len,

1511

PCI_DMA_TODEVICE);

1513

PCI_DMA_TODEVICE);

1512

rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]);

1514

rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]);

1513

}

1515

}

1514

1516

1515

rp->tx_ring[entry].desc_length =

1517

rp->tx_ring[entry].desc_length =

1516

cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));

1518

cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));

1517

1519

1518

if (unlikely(vlan_tx_tag_present(skb))) {

1520

if (unlikely(vlan_tx_tag_present(skb))) {

1519

rp->tx_ring[entry].tx_status = cpu_to_le32((vlan_tx_tag_get(skb)) << 16);

1521

rp->tx_ring[entry].tx_status = cpu_to_le32((vlan_tx_tag_get(skb)) << 16);

1520

/* request tagging */

1522

/* request tagging */

1521

rp->tx_ring[entry].desc_length |= cpu_to_le32(0x020000);

1523

rp->tx_ring[entry].desc_length |= cpu_to_le32(0x020000);

1522

}

1524

}

1523

else

1525

else

1524

rp->tx_ring[entry].tx_status = 0;

1526

rp->tx_ring[entry].tx_status = 0;

1525

1527

1526

/* lock eth irq */

1528

/* lock eth irq */

1527

spin_lock_irqsave(&rp->lock, flags);

1529

spin_lock_irqsave(&rp->lock, flags);

1528

wmb();

1530

wmb();

1529

rp->tx_ring[entry].tx_status |= cpu_to_le32(DescOwn);

1531

rp->tx_ring[entry].tx_status |= cpu_to_le32(DescOwn);

1530

wmb();

1532

wmb();

1531

1533

1532

rp->cur_tx++;

1534

rp->cur_tx++;

1533

1535

1534

/* Non-x86 Todo: explicitly flush cache lines here. */

1536

/* Non-x86 Todo: explicitly flush cache lines here. */

1535

1537

1536

if (vlan_tx_tag_present(skb))

1538

if (vlan_tx_tag_present(skb))

1537

/* Tx queues are bits 7-0 (first Tx queue: bit 7) */

1539

/* Tx queues are bits 7-0 (first Tx queue: bit 7) */

1538

BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake);

1540

BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake);

1539

1541

1540

/* Wake the potentially-idle transmit channel */

1542

/* Wake the potentially-idle transmit channel */

1541

iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,

1543

iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,

1542

ioaddr + ChipCmd1);

1544

ioaddr + ChipCmd1);

1543

IOSYNC;

1545

IOSYNC;

1544

1546

1545

if (rp->cur_tx == rp->dirty_tx + TX_QUEUE_LEN)

1547

if (rp->cur_tx == rp->dirty_tx + TX_QUEUE_LEN)

1546

netif_stop_queue(dev);

1548

netif_stop_queue(dev);

1547

1549

1548

spin_unlock_irqrestore(&rp->lock, flags);

1550

spin_unlock_irqrestore(&rp->lock, flags);

1549

1551

1550

if (debug > 4) {

1552

if (debug > 4) {

1551

netdev_dbg(dev, "Transmit frame #%d queued in slot %d\n",

1553

netdev_dbg(dev, "Transmit frame #%d queued in slot %d\n",

1552

rp->cur_tx-1, entry);

1554

rp->cur_tx-1, entry);

1553

}

1555

}

1554

return NETDEV_TX_OK;

1556

return NETDEV_TX_OK;

1555

}

1557

}

1556

1558

1557

/* The interrupt handler does all of the Rx thread work and cleans up

1559

/* The interrupt handler does all of the Rx thread work and cleans up

1558

after the Tx thread. */

1560

after the Tx thread. */

1559

static irqreturn_t rhine_interrupt(int irq, void *dev_instance)

1561

static irqreturn_t rhine_interrupt(int irq, void *dev_instance)

1560

{

1562

{

1561

struct net_device *dev = dev_instance;

1563

struct net_device *dev = dev_instance;

1562

struct rhine_private *rp = netdev_priv(dev);

1564

struct rhine_private *rp = netdev_priv(dev);

1563

void __iomem *ioaddr = rp->base;

1565

void __iomem *ioaddr = rp->base;

1564

u32 intr_status;

1566

u32 intr_status;

1565

int boguscnt = max_interrupt_work;

1567

int boguscnt = max_interrupt_work;

1566

int handled = 0;

1568

int handled = 0;

1567

1569

1568

while ((intr_status = get_intr_status(dev))) {

1570

while ((intr_status = get_intr_status(dev))) {

1569

handled = 1;

1571

handled = 1;

1570

1572

1571

/* Acknowledge all of the current interrupt sources ASAP. */

1573

/* Acknowledge all of the current interrupt sources ASAP. */

1572

if (intr_status & IntrTxDescRace)

1574

if (intr_status & IntrTxDescRace)

1573

iowrite8(0x08, ioaddr + IntrStatus2);

1575

iowrite8(0x08, ioaddr + IntrStatus2);

1574

iowrite16(intr_status & 0xffff, ioaddr + IntrStatus);

1576

iowrite16(intr_status & 0xffff, ioaddr + IntrStatus);

1575

IOSYNC;

1577

IOSYNC;

1576

1578

1577

if (debug > 4)

1579

if (debug > 4)

1578

netdev_dbg(dev, "Interrupt, status %08x\n",

1580

netdev_dbg(dev, "Interrupt, status %08x\n",

1579

intr_status);

1581

intr_status);

1580

1582

1581

if (intr_status & (IntrRxDone | IntrRxErr | IntrRxDropped |

1583

if (intr_status & (IntrRxDone | IntrRxErr | IntrRxDropped |

1582

IntrRxWakeUp | IntrRxEmpty | IntrRxNoBuf)) {

1584

IntrRxWakeUp | IntrRxEmpty | IntrRxNoBuf)) {

1583

iowrite16(IntrTxAborted |

1585

iowrite16(IntrTxAborted |

1584

IntrTxDone | IntrTxError | IntrTxUnderrun |

1586

IntrTxDone | IntrTxError | IntrTxUnderrun |

1585

IntrPCIErr | IntrStatsMax | IntrLinkChange,

1587

IntrPCIErr | IntrStatsMax | IntrLinkChange,

1586

ioaddr + IntrEnable);

1588

ioaddr + IntrEnable);

1587

1589

1588

napi_schedule(&rp->napi);

1590

napi_schedule(&rp->napi);

1589

}

1591

}

1590

1592

1591

if (intr_status & (IntrTxErrSummary | IntrTxDone)) {

1593

if (intr_status & (IntrTxErrSummary | IntrTxDone)) {

1592

if (intr_status & IntrTxErrSummary) {

1594

if (intr_status & IntrTxErrSummary) {

1593

/* Avoid scavenging before Tx engine turned off */

1595

/* Avoid scavenging before Tx engine turned off */

1594

RHINE_WAIT_FOR(!(ioread8(ioaddr+ChipCmd) & CmdTxOn));

1596

RHINE_WAIT_FOR(!(ioread8(ioaddr+ChipCmd) & CmdTxOn));

1595

if (debug > 2 &&

1597

if (debug > 2 &&

1596

ioread8(ioaddr+ChipCmd) & CmdTxOn)

1598

ioread8(ioaddr+ChipCmd) & CmdTxOn)

1597

netdev_warn(dev,

1599

netdev_warn(dev,

1598

"%s: Tx engine still on\n",

1600

"%s: Tx engine still on\n",

1599

__func__);

1601

__func__);

1600

}

1602

}

1601

rhine_tx(dev);

1603

rhine_tx(dev);

1602

}

1604

}

1603

1605

1604

/* Abnormal error summary/uncommon events handlers. */

1606

/* Abnormal error summary/uncommon events handlers. */

1605

if (intr_status & (IntrPCIErr | IntrLinkChange |

1607

if (intr_status & (IntrPCIErr | IntrLinkChange |

1606

IntrStatsMax | IntrTxError | IntrTxAborted |

1608

IntrStatsMax | IntrTxError | IntrTxAborted |

1607

IntrTxUnderrun | IntrTxDescRace))

1609

IntrTxUnderrun | IntrTxDescRace))

1608

rhine_error(dev, intr_status);

1610

rhine_error(dev, intr_status);

1609

1611

1610

if (--boguscnt < 0) {

1612

if (--boguscnt < 0) {

1611

netdev_warn(dev, "Too much work at interrupt, status=%#08x\n",

1613

netdev_warn(dev, "Too much work at interrupt, status=%#08x\n",

1612

intr_status);

1614

intr_status);

1613

break;

1615

break;

1614

}

1616

}

1615

}

1617

}

1616

1618

1617

if (debug > 3)

1619

if (debug > 3)

1618

netdev_dbg(dev, "exiting interrupt, status=%08x\n",

1620

netdev_dbg(dev, "exiting interrupt, status=%08x\n",

1619

ioread16(ioaddr + IntrStatus));

1621

ioread16(ioaddr + IntrStatus));

1620

return IRQ_RETVAL(handled);

1622

return IRQ_RETVAL(handled);

1621

}

1623

}

1622

1624

1623

/* This routine is logically part of the interrupt handler, but isolated

1625

/* This routine is logically part of the interrupt handler, but isolated

1624

for clarity. */

1626

for clarity. */

1625

static void rhine_tx(struct net_device *dev)

1627

static void rhine_tx(struct net_device *dev)

1626

{

1628

{

1627

struct rhine_private *rp = netdev_priv(dev);

1629

struct rhine_private *rp = netdev_priv(dev);

1628

int txstatus = 0, entry = rp->dirty_tx % TX_RING_SIZE;

1630

int txstatus = 0, entry = rp->dirty_tx % TX_RING_SIZE;

1629

1631

1630

spin_lock(&rp->lock);

1632

spin_lock(&rp->lock);

1631

1633

1632

/* find and cleanup dirty tx descriptors */

1634

/* find and cleanup dirty tx descriptors */

1633

while (rp->dirty_tx != rp->cur_tx) {

1635

while (rp->dirty_tx != rp->cur_tx) {

1634

txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status);

1636

txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status);

1635

if (debug > 6)

1637

if (debug > 6)

1636

netdev_dbg(dev, "Tx scavenge %d status %08x\n",

1638

netdev_dbg(dev, "Tx scavenge %d status %08x\n",

1637

entry, txstatus);

1639

entry, txstatus);

1638

if (txstatus & DescOwn)

1640

if (txstatus & DescOwn)

1639

break;

1641

break;

1640

if (txstatus & 0x8000) {

1642

if (txstatus & 0x8000) {

1641

if (debug > 1)

1643

if (debug > 1)

1642

netdev_dbg(dev, "Transmit error, Tx status %08x\n",

1644

netdev_dbg(dev, "Transmit error, Tx status %08x\n",

1643

txstatus);

1645

txstatus);

1644

dev->stats.tx_errors++;

1646

dev->stats.tx_errors++;

1645

if (txstatus & 0x0400)

1647

if (txstatus & 0x0400)

1646

dev->stats.tx_carrier_errors++;

1648

dev->stats.tx_carrier_errors++;

1647

if (txstatus & 0x0200)

1649

if (txstatus & 0x0200)

1648

dev->stats.tx_window_errors++;

1650

dev->stats.tx_window_errors++;

1649

if (txstatus & 0x0100)

1651

if (txstatus & 0x0100)

1650

dev->stats.tx_aborted_errors++;

1652

dev->stats.tx_aborted_errors++;

1651

if (txstatus & 0x0080)

1653

if (txstatus & 0x0080)

1652

dev->stats.tx_heartbeat_errors++;

1654

dev->stats.tx_heartbeat_errors++;

1653

if (((rp->quirks & rqRhineI) && txstatus & 0x0002) ||

1655

if (((rp->quirks & rqRhineI) && txstatus & 0x0002) ||

1654

(txstatus & 0x0800) || (txstatus & 0x1000)) {

1656

(txstatus & 0x0800) || (txstatus & 0x1000)) {

1655

dev->stats.tx_fifo_errors++;

1657

dev->stats.tx_fifo_errors++;

1656

rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);

1658

rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);

1657

break; /* Keep the skb - we try again */

1659

break; /* Keep the skb - we try again */

1658

}

1660

}

1659

/* Transmitter restarted in 'abnormal' handler. */

1661

/* Transmitter restarted in 'abnormal' handler. */

1660

} else {

1662

} else {

1661

if (rp->quirks & rqRhineI)

1663

if (rp->quirks & rqRhineI)

1662

dev->stats.collisions += (txstatus >> 3) & 0x0F;

1664

dev->stats.collisions += (txstatus >> 3) & 0x0F;

1663

else

1665

else

1664

dev->stats.collisions += txstatus & 0x0F;

1666

dev->stats.collisions += txstatus & 0x0F;

1665

if (debug > 6)

1667

if (debug > 6)

1666

netdev_dbg(dev, "collisions: %1.1x:%1.1x\n",

1668

netdev_dbg(dev, "collisions: %1.1x:%1.1x\n",

1667

(txstatus >> 3) & 0xF,

1669

(txstatus >> 3) & 0xF,

1668

txstatus & 0xF);

1670

txstatus & 0xF);

1669

dev->stats.tx_bytes += rp->tx_skbuff[entry]->len;

1671

dev->stats.tx_bytes += rp->tx_skbuff[entry]->len;

1670

dev->stats.tx_packets++;

1672

dev->stats.tx_packets++;

1671

}

1673

}

1672

/* Free the original skb. */

1674

/* Free the original skb. */

1673

if (rp->tx_skbuff_dma[entry]) {

1675

if (rp->tx_skbuff_dma[entry]) {

1674

pci_unmap_single(rp->pdev,

1676

pci_unmap_single(rp->pdev,

1675

rp->tx_skbuff_dma[entry],

1677

rp->tx_skbuff_dma[entry],

1676

rp->tx_skbuff[entry]->len,

1678

rp->tx_skbuff[entry]->len,

1677

PCI_DMA_TODEVICE);

1679

PCI_DMA_TODEVICE);

1678

}

1680

}

1679

dev_kfree_skb_irq(rp->tx_skbuff[entry]);

1681

dev_kfree_skb_irq(rp->tx_skbuff[entry]);

1680

rp->tx_skbuff[entry] = NULL;

1682

rp->tx_skbuff[entry] = NULL;

1681

entry = (++rp->dirty_tx) % TX_RING_SIZE;

1683

entry = (++rp->dirty_tx) % TX_RING_SIZE;

1682

}

1684

}

1683

if ((rp->cur_tx - rp->dirty_tx) < TX_QUEUE_LEN - 4)

1685

if ((rp->cur_tx - rp->dirty_tx) < TX_QUEUE_LEN - 4)

1684

netif_wake_queue(dev);

1686

netif_wake_queue(dev);

1685

1687

1686

spin_unlock(&rp->lock);

1688

spin_unlock(&rp->lock);

1687

}

1689

}

1688

1690

1689

/**

1691

/**

1690

* rhine_get_vlan_tci - extract TCI from Rx data buffer

1692

* rhine_get_vlan_tci - extract TCI from Rx data buffer

1691

* @skb: pointer to sk_buff

1693

* @skb: pointer to sk_buff

1692

* @data_size: used data area of the buffer including CRC

1694

* @data_size: used data area of the buffer including CRC

1693

*

1695

*

1694

* If hardware VLAN tag extraction is enabled and the chip indicates a 802.1Q

1696

* If hardware VLAN tag extraction is enabled and the chip indicates a 802.1Q

1695

* packet, the extracted 802.1Q header (2 bytes TPID + 2 bytes TCI) is 4-byte

1697

* packet, the extracted 802.1Q header (2 bytes TPID + 2 bytes TCI) is 4-byte

1696

* aligned following the CRC.

1698

* aligned following the CRC.

1697

*/

1699

*/

1698

static inline u16 rhine_get_vlan_tci(struct sk_buff *skb, int data_size)

1700

static inline u16 rhine_get_vlan_tci(struct sk_buff *skb, int data_size)

1699

{

1701

{

1700

u8 *trailer = (u8 *)skb->data + ((data_size + 3) & ~3) + 2;

1702

u8 *trailer = (u8 *)skb->data + ((data_size + 3) & ~3) + 2;

1701

return be16_to_cpup((__be16 *)trailer);

1703

return be16_to_cpup((__be16 *)trailer);

1702

}

1704

}

1703

1705

1704

/* Process up to limit frames from receive ring */

1706

/* Process up to limit frames from receive ring */

1705

static int rhine_rx(struct net_device *dev, int limit)

1707

static int rhine_rx(struct net_device *dev, int limit)

1706

{

1708

{

1707

struct rhine_private *rp = netdev_priv(dev);

1709

struct rhine_private *rp = netdev_priv(dev);

1708

int count;

1710

int count;

1709

int entry = rp->cur_rx % RX_RING_SIZE;

1711

int entry = rp->cur_rx % RX_RING_SIZE;

1710

1712

1711

if (debug > 4) {

1713

if (debug > 4) {

1712

netdev_dbg(dev, "%s(), entry %d status %08x\n",

1714

netdev_dbg(dev, "%s(), entry %d status %08x\n",

1713

__func__, entry,

1715

__func__, entry,

1714

le32_to_cpu(rp->rx_head_desc->rx_status));

1716

le32_to_cpu(rp->rx_head_desc->rx_status));

1715

}

1717

}

1716

1718

1717

/* If EOP is set on the next entry, it's a new packet. Send it up. */

1719

/* If EOP is set on the next entry, it's a new packet. Send it up. */

1718

for (count = 0; count < limit; ++count) {

1720

for (count = 0; count < limit; ++count) {

1719

struct rx_desc *desc = rp->rx_head_desc;

1721

struct rx_desc *desc = rp->rx_head_desc;

1720

u32 desc_status = le32_to_cpu(desc->rx_status);

1722

u32 desc_status = le32_to_cpu(desc->rx_status);

1721

u32 desc_length = le32_to_cpu(desc->desc_length);

1723

u32 desc_length = le32_to_cpu(desc->desc_length);

1722

int data_size = desc_status >> 16;

1724

int data_size = desc_status >> 16;

1723

1725

1724

if (desc_status & DescOwn)

1726

if (desc_status & DescOwn)

1725

break;

1727

break;

1726

1728

1727

if (debug > 4)

1729

if (debug > 4)

1728

netdev_dbg(dev, "%s() status is %08x\n",

1730

netdev_dbg(dev, "%s() status is %08x\n",

1729

__func__, desc_status);

1731

__func__, desc_status);

1730

1732

1731

if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) {

1733

if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) {

1732

if ((desc_status & RxWholePkt) != RxWholePkt) {

1734

if ((desc_status & RxWholePkt) != RxWholePkt) {

1733

netdev_warn(dev,

1735

netdev_warn(dev,

1734

"Oversized Ethernet frame spanned multiple buffers, "

1736

"Oversized Ethernet frame spanned multiple buffers, "

1735

"entry %#x length %d status %08x!\n",

1737

"entry %#x length %d status %08x!\n",

1736

entry, data_size,

1738

entry, data_size,

1737

desc_status);

1739

desc_status);

1738

netdev_warn(dev,

1740

netdev_warn(dev,

1739

"Oversized Ethernet frame %p vs %p\n",

1741

"Oversized Ethernet frame %p vs %p\n",

1740

rp->rx_head_desc,

1742

rp->rx_head_desc,

1741

&rp->rx_ring[entry]);

1743

&rp->rx_ring[entry]);

1742

dev->stats.rx_length_errors++;

1744

dev->stats.rx_length_errors++;

1743

} else if (desc_status & RxErr) {

1745

} else if (desc_status & RxErr) {

1744

/* There was a error. */

1746

/* There was a error. */

1745

if (debug > 2)

1747

if (debug > 2)

1746

netdev_dbg(dev, "%s() Rx error was %08x\n",

1748

netdev_dbg(dev, "%s() Rx error was %08x\n",

1747

__func__, desc_status);

1749

__func__, desc_status);

1748

dev->stats.rx_errors++;

1750

dev->stats.rx_errors++;

1749

if (desc_status & 0x0030)

1751

if (desc_status & 0x0030)

1750

dev->stats.rx_length_errors++;

1752

dev->stats.rx_length_errors++;

1751

if (desc_status & 0x0048)

1753

if (desc_status & 0x0048)

1752

dev->stats.rx_fifo_errors++;

1754

dev->stats.rx_fifo_errors++;

1753

if (desc_status & 0x0004)

1755

if (desc_status & 0x0004)

1754

dev->stats.rx_frame_errors++;

1756

dev->stats.rx_frame_errors++;

1755

if (desc_status & 0x0002) {

1757

if (desc_status & 0x0002) {

1756

/* this can also be updated outside the interrupt handler */

1758

/* this can also be updated outside the interrupt handler */

1757

spin_lock(&rp->lock);

1759

spin_lock(&rp->lock);

1758

dev->stats.rx_crc_errors++;

1760

dev->stats.rx_crc_errors++;

1759

spin_unlock(&rp->lock);

1761

spin_unlock(&rp->lock);

1760

}

1762

}

1761

}

1763

}

1762

} else {

1764

} else {

1763

struct sk_buff *skb = NULL;

1765

struct sk_buff *skb = NULL;

1764

/* Length should omit the CRC */

1766

/* Length should omit the CRC */

1765

int pkt_len = data_size - 4;

1767

int pkt_len = data_size - 4;

1766

u16 vlan_tci = 0;

1768

u16 vlan_tci = 0;

1767

1769

1768

/* Check if the packet is long enough to accept without

1770

/* Check if the packet is long enough to accept without

1769

copying to a minimally-sized skbuff. */

1771

copying to a minimally-sized skbuff. */

1770

if (pkt_len < rx_copybreak)

1772

if (pkt_len < rx_copybreak)

1771

skb = netdev_alloc_skb_ip_align(dev, pkt_len);

1773

skb = netdev_alloc_skb_ip_align(dev, pkt_len);

1772

if (skb) {

1774

if (skb) {

1773

pci_dma_sync_single_for_cpu(rp->pdev,

1775

pci_dma_sync_single_for_cpu(rp->pdev,

1774

rp->rx_skbuff_dma[entry],

1776

rp->rx_skbuff_dma[entry],

1775

rp->rx_buf_sz,

1777

rp->rx_buf_sz,

1776

PCI_DMA_FROMDEVICE);

1778

PCI_DMA_FROMDEVICE);

1777

1779

1778

skb_copy_to_linear_data(skb,

1780

skb_copy_to_linear_data(skb,

1779

rp->rx_skbuff[entry]->data,

1781

rp->rx_skbuff[entry]->data,

1780

pkt_len);

1782

pkt_len);

1781

skb_put(skb, pkt_len);

1783

skb_put(skb, pkt_len);

1782

pci_dma_sync_single_for_device(rp->pdev,

1784

pci_dma_sync_single_for_device(rp->pdev,

1783

rp->rx_skbuff_dma[entry],

1785

rp->rx_skbuff_dma[entry],

1784

rp->rx_buf_sz,

1786

rp->rx_buf_sz,

1785

PCI_DMA_FROMDEVICE);

1787

PCI_DMA_FROMDEVICE);

1786

} else {

1788

} else {

1787

skb = rp->rx_skbuff[entry];

1789

skb = rp->rx_skbuff[entry];

1788

if (skb == NULL) {

1790

if (skb == NULL) {

1789

netdev_err(dev, "Inconsistent Rx descriptor chain\n");

1791

netdev_err(dev, "Inconsistent Rx descriptor chain\n");

1790

break;

1792

break;

1791

}

1793

}

1792

rp->rx_skbuff[entry] = NULL;

1794

rp->rx_skbuff[entry] = NULL;

1793

skb_put(skb, pkt_len);

1795

skb_put(skb, pkt_len);

1794

pci_unmap_single(rp->pdev,

1796

pci_unmap_single(rp->pdev,

1795

rp->rx_skbuff_dma[entry],

1797

rp->rx_skbuff_dma[entry],

1796

rp->rx_buf_sz,

1798

rp->rx_buf_sz,

1797

PCI_DMA_FROMDEVICE);

1799

PCI_DMA_FROMDEVICE);

1798

}

1800

}

1799

1801

1800

if (unlikely(desc_length & DescTag))

1802

if (unlikely(desc_length & DescTag))

1801

vlan_tci = rhine_get_vlan_tci(skb, data_size);

1803

vlan_tci = rhine_get_vlan_tci(skb, data_size);

1802

1804

1803

skb->protocol = eth_type_trans(skb, dev);

1805

skb->protocol = eth_type_trans(skb, dev);

1804

1806

1805

if (unlikely(desc_length & DescTag))

1807

if (unlikely(desc_length & DescTag))

1806

__vlan_hwaccel_put_tag(skb, vlan_tci);

1808

__vlan_hwaccel_put_tag(skb, vlan_tci);

1807

netif_receive_skb(skb);

1809

netif_receive_skb(skb);

1808

dev->stats.rx_bytes += pkt_len;

1810

dev->stats.rx_bytes += pkt_len;

1809

dev->stats.rx_packets++;

1811

dev->stats.rx_packets++;

1810

}

1812

}

1811

entry = (++rp->cur_rx) % RX_RING_SIZE;

1813

entry = (++rp->cur_rx) % RX_RING_SIZE;

1812

rp->rx_head_desc = &rp->rx_ring[entry];

1814

rp->rx_head_desc = &rp->rx_ring[entry];

1813

}

1815

}

1814

1816

1815

/* Refill the Rx ring buffers. */

1817

/* Refill the Rx ring buffers. */

1816

for (; rp->cur_rx - rp->dirty_rx > 0; rp->dirty_rx++) {

1818

for (; rp->cur_rx - rp->dirty_rx > 0; rp->dirty_rx++) {

1817

struct sk_buff *skb;

1819

struct sk_buff *skb;

1818

entry = rp->dirty_rx % RX_RING_SIZE;

1820

entry = rp->dirty_rx % RX_RING_SIZE;

1819

if (rp->rx_skbuff[entry] == NULL) {

1821

if (rp->rx_skbuff[entry] == NULL) {

1820

skb = netdev_alloc_skb(dev, rp->rx_buf_sz);

1822

skb = netdev_alloc_skb(dev, rp->rx_buf_sz);

1821

rp->rx_skbuff[entry] = skb;

1823

rp->rx_skbuff[entry] = skb;

1822

if (skb == NULL)

1824

if (skb == NULL)

1823

break; /* Better luck next round. */

1825

break; /* Better luck next round. */

1824

skb->dev = dev; /* Mark as being used by this device. */

1826

skb->dev = dev; /* Mark as being used by this device. */

1825

rp->rx_skbuff_dma[entry] =

1827

rp->rx_skbuff_dma[entry] =

1826

pci_map_single(rp->pdev, skb->data,

1828

pci_map_single(rp->pdev, skb->data,

1827

rp->rx_buf_sz,

1829

rp->rx_buf_sz,

1828

PCI_DMA_FROMDEVICE);

1830

PCI_DMA_FROMDEVICE);

1829

rp->rx_ring[entry].addr = cpu_to_le32(rp->rx_skbuff_dma[entry]);

1831

rp->rx_ring[entry].addr = cpu_to_le32(rp->rx_skbuff_dma[entry]);

1830

}

1832

}

1831

rp->rx_ring[entry].rx_status = cpu_to_le32(DescOwn);

1833

rp->rx_ring[entry].rx_status = cpu_to_le32(DescOwn);

1832

}

1834

}

1833

1835

1834

return count;

1836

return count;

1835

}

1837

}

1836

1838

1837

/*

1839

/*

1838

* Clears the "tally counters" for CRC errors and missed frames(?).

1840

* Clears the "tally counters" for CRC errors and missed frames(?).

1839

* It has been reported that some chips need a write of 0 to clear

1841

* It has been reported that some chips need a write of 0 to clear

1840

* these, for others the counters are set to 1 when written to and

1842

* these, for others the counters are set to 1 when written to and

1841

* instead cleared when read. So we clear them both ways ...

1843

* instead cleared when read. So we clear them both ways ...

1842

*/

1844

*/

1843

static inline void clear_tally_counters(void __iomem *ioaddr)

1845

static inline void clear_tally_counters(void __iomem *ioaddr)

1844

{

1846

{

1845

iowrite32(0, ioaddr + RxMissed);

1847

iowrite32(0, ioaddr + RxMissed);

1846

ioread16(ioaddr + RxCRCErrs);

1848

ioread16(ioaddr + RxCRCErrs);

1847

ioread16(ioaddr + RxMissed);

1849

ioread16(ioaddr + RxMissed);

1848

}

1850

}

1849

1851

1850

static void rhine_restart_tx(struct net_device *dev) {

1852

static void rhine_restart_tx(struct net_device *dev) {

1851

struct rhine_private *rp = netdev_priv(dev);

1853

struct rhine_private *rp = netdev_priv(dev);

1852

void __iomem *ioaddr = rp->base;

1854

void __iomem *ioaddr = rp->base;

1853

int entry = rp->dirty_tx % TX_RING_SIZE;

1855

int entry = rp->dirty_tx % TX_RING_SIZE;

1854

u32 intr_status;

1856

u32 intr_status;

1855

1857

1856

/*

1858

/*

1857

* If new errors occurred, we need to sort them out before doing Tx.

1859

* If new errors occurred, we need to sort them out before doing Tx.

1858

* In that case the ISR will be back here RSN anyway.

1860

* In that case the ISR will be back here RSN anyway.

1859

*/

1861

*/

1860

intr_status = get_intr_status(dev);

1862

intr_status = get_intr_status(dev);

1861

1863

1862

if ((intr_status & IntrTxErrSummary) == 0) {

1864

if ((intr_status & IntrTxErrSummary) == 0) {

1863

1865

1864

/* We know better than the chip where it should continue. */

1866

/* We know better than the chip where it should continue. */

1865

iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc),

1867

iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc),

1866

ioaddr + TxRingPtr);

1868

ioaddr + TxRingPtr);

1867

1869

1868

iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn,

1870

iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn,

1869

ioaddr + ChipCmd);

1871

ioaddr + ChipCmd);

1870

1872

1871

if (rp->tx_ring[entry].desc_length & cpu_to_le32(0x020000))

1873

if (rp->tx_ring[entry].desc_length & cpu_to_le32(0x020000))

1872

/* Tx queues are bits 7-0 (first Tx queue: bit 7) */

1874

/* Tx queues are bits 7-0 (first Tx queue: bit 7) */

1873

BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake);

1875

BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake);

1874

1876

1875

iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,

1877

iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,

1876

ioaddr + ChipCmd1);

1878

ioaddr + ChipCmd1);

1877

IOSYNC;

1879

IOSYNC;

1878

}

1880

}

1879

else {

1881

else {

1880

/* This should never happen */

1882

/* This should never happen */

1881

if (debug > 1)

1883

if (debug > 1)

1882

netdev_warn(dev, "%s() Another error occurred %08x\n",

1884

netdev_warn(dev, "%s() Another error occurred %08x\n",

1883

__func__, intr_status);

1885

__func__, intr_status);

1884

}

1886

}

1885

1887

1886

}

1888

}

1887

1889

1888

static void rhine_error(struct net_device *dev, int intr_status)

1890

static void rhine_error(struct net_device *dev, int intr_status)

1889

{

1891

{

1890

struct rhine_private *rp = netdev_priv(dev);

1892

struct rhine_private *rp = netdev_priv(dev);

1891

void __iomem *ioaddr = rp->base;

1893

void __iomem *ioaddr = rp->base;

1892

1894

1893

spin_lock(&rp->lock);

1895

spin_lock(&rp->lock);

1894

1896

1895

if (intr_status & IntrLinkChange)

1897

if (intr_status & IntrLinkChange)

1896

rhine_check_media(dev, 0);

1898

rhine_check_media(dev, 0);

1897

if (intr_status & IntrStatsMax) {

1899

if (intr_status & IntrStatsMax) {

1898

dev->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);

1900

dev->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);

1899

dev->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);

1901

dev->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);

1900

clear_tally_counters(ioaddr);

1902

clear_tally_counters(ioaddr);

1901

}

1903

}

1902

if (intr_status & IntrTxAborted) {

1904

if (intr_status & IntrTxAborted) {

1903

if (debug > 1)

1905

if (debug > 1)

1904

netdev_info(dev, "Abort %08x, frame dropped\n",

1906

netdev_info(dev, "Abort %08x, frame dropped\n",

1905

intr_status);

1907

intr_status);

1906

}

1908

}

1907

if (intr_status & IntrTxUnderrun) {

1909

if (intr_status & IntrTxUnderrun) {

1908

if (rp->tx_thresh < 0xE0)

1910

if (rp->tx_thresh < 0xE0)

1909

BYTE_REG_BITS_SET((rp->tx_thresh += 0x20), 0x80, ioaddr + TxConfig);

1911

BYTE_REG_BITS_SET((rp->tx_thresh += 0x20), 0x80, ioaddr + TxConfig);

1910

if (debug > 1)

1912

if (debug > 1)

1911

netdev_info(dev, "Transmitter underrun, Tx threshold now %02x\n",

1913

netdev_info(dev, "Transmitter underrun, Tx threshold now %02x\n",

1912

rp->tx_thresh);

1914

rp->tx_thresh);

1913

}

1915

}

1914

if (intr_status & IntrTxDescRace) {

1916

if (intr_status & IntrTxDescRace) {

1915

if (debug > 2)

1917

if (debug > 2)

1916

netdev_info(dev, "Tx descriptor write-back race\n");

1918

netdev_info(dev, "Tx descriptor write-back race\n");

1917

}

1919

}

1918

if ((intr_status & IntrTxError) &&

1920

if ((intr_status & IntrTxError) &&

1919

(intr_status & (IntrTxAborted |

1921

(intr_status & (IntrTxAborted |

1920

IntrTxUnderrun | IntrTxDescRace)) == 0) {

1922

IntrTxUnderrun | IntrTxDescRace)) == 0) {

1921

if (rp->tx_thresh < 0xE0) {

1923

if (rp->tx_thresh < 0xE0) {

1922

BYTE_REG_BITS_SET((rp->tx_thresh += 0x20), 0x80, ioaddr + TxConfig);

1924

BYTE_REG_BITS_SET((rp->tx_thresh += 0x20), 0x80, ioaddr + TxConfig);

1923

}

1925

}

1924

if (debug > 1)

1926

if (debug > 1)

1925

netdev_info(dev, "Unspecified error. Tx threshold now %02x\n",

1927

netdev_info(dev, "Unspecified error. Tx threshold now %02x\n",

1926

rp->tx_thresh);

1928

rp->tx_thresh);

1927

}

1929

}

1928

if (intr_status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace |

1930

if (intr_status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace |

1929

IntrTxError))

1931

IntrTxError))

1930

rhine_restart_tx(dev);

1932

rhine_restart_tx(dev);

1931

1933

1932

if (intr_status & ~(IntrLinkChange | IntrStatsMax | IntrTxUnderrun |

1934

if (intr_status & ~(IntrLinkChange | IntrStatsMax | IntrTxUnderrun |

1933

IntrTxError | IntrTxAborted | IntrNormalSummary |

1935

IntrTxError | IntrTxAborted | IntrNormalSummary |

1934

IntrTxDescRace)) {

1936

IntrTxDescRace)) {

1935

if (debug > 1)

1937

if (debug > 1)

1936

netdev_err(dev, "Something Wicked happened! %08x\n",

1938

netdev_err(dev, "Something Wicked happened! %08x\n",

1937

intr_status);

1939

intr_status);

1938

}

1940

}

1939

1941

1940

spin_unlock(&rp->lock);

1942

spin_unlock(&rp->lock);

1941

}

1943

}

1942

1944

1943

static struct net_device_stats *rhine_get_stats(struct net_device *dev)

1945

static struct net_device_stats *rhine_get_stats(struct net_device *dev)

1944

{

1946

{

1945

struct rhine_private *rp = netdev_priv(dev);

1947

struct rhine_private *rp = netdev_priv(dev);

1946

void __iomem *ioaddr = rp->base;

1948

void __iomem *ioaddr = rp->base;

1947

unsigned long flags;

1949

unsigned long flags;

1948

1950

1949

spin_lock_irqsave(&rp->lock, flags);

1951

spin_lock_irqsave(&rp->lock, flags);

1950

dev->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);

1952

dev->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);

1951

dev->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);

1953

dev->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);

1952

clear_tally_counters(ioaddr);

1954

clear_tally_counters(ioaddr);

1953

spin_unlock_irqrestore(&rp->lock, flags);

1955

spin_unlock_irqrestore(&rp->lock, flags);

1954

1956

1955

return &dev->stats;

1957

return &dev->stats;

1956

}

1958

}

1957

1959

1958

static void rhine_set_rx_mode(struct net_device *dev)

1960

static void rhine_set_rx_mode(struct net_device *dev)

1959

{

1961

{

1960

struct rhine_private *rp = netdev_priv(dev);

1962

struct rhine_private *rp = netdev_priv(dev);

1961

void __iomem *ioaddr = rp->base;

1963

void __iomem *ioaddr = rp->base;

1962

u32 mc_filter[2]; /* Multicast hash filter */

1964

u32 mc_filter[2]; /* Multicast hash filter */

1963

u8 rx_mode = 0x0C; /* Note: 0x02=accept runt, 0x01=accept errs */

1965

u8 rx_mode = 0x0C; /* Note: 0x02=accept runt, 0x01=accept errs */

1964

struct netdev_hw_addr *ha;

1966

struct netdev_hw_addr *ha;

1965

1967

1966

if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */

1968

if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */

1967

rx_mode = 0x1C;

1969

rx_mode = 0x1C;

1968

iowrite32(0xffffffff, ioaddr + MulticastFilter0);

1970

iowrite32(0xffffffff, ioaddr + MulticastFilter0);

1969

iowrite32(0xffffffff, ioaddr + MulticastFilter1);

1971

iowrite32(0xffffffff, ioaddr + MulticastFilter1);

1970

} else if ((netdev_mc_count(dev) > multicast_filter_limit) ||

1972

} else if ((netdev_mc_count(dev) > multicast_filter_limit) ||

1971

(dev->flags & IFF_ALLMULTI)) {

1973

(dev->flags & IFF_ALLMULTI)) {

1972

/* Too many to match, or accept all multicasts. */

1974

/* Too many to match, or accept all multicasts. */

1973

iowrite32(0xffffffff, ioaddr + MulticastFilter0);

1975

iowrite32(0xffffffff, ioaddr + MulticastFilter0);

1974

iowrite32(0xffffffff, ioaddr + MulticastFilter1);

1976

iowrite32(0xffffffff, ioaddr + MulticastFilter1);

1975

} else if (rp->pdev->revision >= VT6105M) {

1977

} else if (rp->pdev->revision >= VT6105M) {

1976

int i = 0;

1978

int i = 0;

1977

u32 mCAMmask = 0; /* 32 mCAMs (6105M and better) */

1979

u32 mCAMmask = 0; /* 32 mCAMs (6105M and better) */

1978

netdev_for_each_mc_addr(ha, dev) {

1980

netdev_for_each_mc_addr(ha, dev) {

1979

if (i == MCAM_SIZE)

1981

if (i == MCAM_SIZE)

1980

break;

1982

break;

1981

rhine_set_cam(ioaddr, i, ha->addr);

1983

rhine_set_cam(ioaddr, i, ha->addr);

1982

mCAMmask |= 1 << i;

1984

mCAMmask |= 1 << i;

1983

i++;

1985

i++;

1984

}

1986

}

1985

rhine_set_cam_mask(ioaddr, mCAMmask);

1987

rhine_set_cam_mask(ioaddr, mCAMmask);

1986

} else {

1988

} else {

1987

memset(mc_filter, 0, sizeof(mc_filter));

1989

memset(mc_filter, 0, sizeof(mc_filter));

1988

netdev_for_each_mc_addr(ha, dev) {

1990

netdev_for_each_mc_addr(ha, dev) {

1989

int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;

1991

int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;

1990

1992

1991

mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);

1993

mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);

1992

}

1994

}

1993

iowrite32(mc_filter[0], ioaddr + MulticastFilter0);

1995

iowrite32(mc_filter[0], ioaddr + MulticastFilter0);

1994

iowrite32(mc_filter[1], ioaddr + MulticastFilter1);

1996

iowrite32(mc_filter[1], ioaddr + MulticastFilter1);

1995

}

1997

}

1996

/* enable/disable VLAN receive filtering */

1998

/* enable/disable VLAN receive filtering */

1997

if (rp->pdev->revision >= VT6105M) {

1999

if (rp->pdev->revision >= VT6105M) {

1998

if (dev->flags & IFF_PROMISC)

2000

if (dev->flags & IFF_PROMISC)

1999

BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1);

2001

BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1);

2000

else

2002

else

2001

BYTE_REG_BITS_ON(BCR1_VIDFR, ioaddr + PCIBusConfig1);

2003

BYTE_REG_BITS_ON(BCR1_VIDFR, ioaddr + PCIBusConfig1);

2002

}

2004

}

2003

BYTE_REG_BITS_ON(rx_mode, ioaddr + RxConfig);

2005

BYTE_REG_BITS_ON(rx_mode, ioaddr + RxConfig);

2004

}

2006

}

2005

2007

2006

static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)

2008

static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)

2007

{

2009

{

2008

struct rhine_private *rp = netdev_priv(dev);

2010

struct rhine_private *rp = netdev_priv(dev);

2009

2011

2010

strcpy(info->driver, DRV_NAME);

2012

strcpy(info->driver, DRV_NAME);

2011

strcpy(info->version, DRV_VERSION);

2013

strcpy(info->version, DRV_VERSION);

2012

strcpy(info->bus_info, pci_name(rp->pdev));

2014

strcpy(info->bus_info, pci_name(rp->pdev));

2013

}

2015

}

2014

2016

2015

static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)

2017

static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)

2016

{

2018

{

2017

struct rhine_private *rp = netdev_priv(dev);

2019

struct rhine_private *rp = netdev_priv(dev);

2018

int rc;

2020

int rc;

2019

2021

2020

spin_lock_irq(&rp->lock);

2022

spin_lock_irq(&rp->lock);

2021

rc = mii_ethtool_gset(&rp->mii_if, cmd);

2023

rc = mii_ethtool_gset(&rp->mii_if, cmd);

2022

spin_unlock_irq(&rp->lock);

2024

spin_unlock_irq(&rp->lock);

2023

2025

2024

return rc;

2026

return rc;

2025

}

2027

}

2026

2028

2027

static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)

2029

static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)

2028

{

2030

{

2029

struct rhine_private *rp = netdev_priv(dev);

2031

struct rhine_private *rp = netdev_priv(dev);

2030

int rc;

2032

int rc;

2031

2033

2032

spin_lock_irq(&rp->lock);

2034

spin_lock_irq(&rp->lock);

2033

rc = mii_ethtool_sset(&rp->mii_if, cmd);

2035

rc = mii_ethtool_sset(&rp->mii_if, cmd);

2034

spin_unlock_irq(&rp->lock);

2036

spin_unlock_irq(&rp->lock);

2035

rhine_set_carrier(&rp->mii_if);

2037

rhine_set_carrier(&rp->mii_if);

2036

2038

2037

return rc;

2039

return rc;

2038

}

2040

}

2039

2041

2040

static int netdev_nway_reset(struct net_device *dev)

2042

static int netdev_nway_reset(struct net_device *dev)

2041

{

2043

{

2042

struct rhine_private *rp = netdev_priv(dev);

2044

struct rhine_private *rp = netdev_priv(dev);

2043

2045

2044

return mii_nway_restart(&rp->mii_if);

2046

return mii_nway_restart(&rp->mii_if);

2045

}

2047

}

2046

2048

2047

static u32 netdev_get_link(struct net_device *dev)

2049

static u32 netdev_get_link(struct net_device *dev)

2048

{

2050

{

2049

struct rhine_private *rp = netdev_priv(dev);

2051

struct rhine_private *rp = netdev_priv(dev);

2050

2052

2051

return mii_link_ok(&rp->mii_if);

2053

return mii_link_ok(&rp->mii_if);

2052

}

2054

}

2053

2055

2054

static u32 netdev_get_msglevel(struct net_device *dev)

2056

static u32 netdev_get_msglevel(struct net_device *dev)

2055

{

2057

{

2056

return debug;

2058

return debug;

2057

}

2059

}

2058

2060

2059

static void netdev_set_msglevel(struct net_device *dev, u32 value)

2061

static void netdev_set_msglevel(struct net_device *dev, u32 value)

2060

{

2062

{

2061

debug = value;

2063

debug = value;

2062

}

2064

}

2063

2065

2064

static void rhine_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)

2066

static void rhine_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)

2065

{

2067

{

2066

struct rhine_private *rp = netdev_priv(dev);

2068

struct rhine_private *rp = netdev_priv(dev);

2067

2069

2068

if (!(rp->quirks & rqWOL))

2070

if (!(rp->quirks & rqWOL))

2069

return;

2071

return;

2070

2072

2071

spin_lock_irq(&rp->lock);

2073

spin_lock_irq(&rp->lock);

2072

wol->supported = WAKE_PHY | WAKE_MAGIC |

2074

wol->supported = WAKE_PHY | WAKE_MAGIC |

2073

WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */

2075

WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */

2074

wol->wolopts = rp->wolopts;

2076

wol->wolopts = rp->wolopts;

2075

spin_unlock_irq(&rp->lock);

2077

spin_unlock_irq(&rp->lock);

2076

}

2078

}

2077

2079

2078

static int rhine_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)

2080

static int rhine_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)

2079

{

2081

{

2080

struct rhine_private *rp = netdev_priv(dev);

2082

struct rhine_private *rp = netdev_priv(dev);

2081

u32 support = WAKE_PHY | WAKE_MAGIC |

2083

u32 support = WAKE_PHY | WAKE_MAGIC |

2082

WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */

2084

WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */

2083

2085

2084

if (!(rp->quirks & rqWOL))

2086

if (!(rp->quirks & rqWOL))

2085

return -EINVAL;

2087

return -EINVAL;

2086

2088

2087

if (wol->wolopts & ~support)

2089

if (wol->wolopts & ~support)

2088

return -EINVAL;

2090

return -EINVAL;

2089

2091

2090

spin_lock_irq(&rp->lock);

2092

spin_lock_irq(&rp->lock);

2091

rp->wolopts = wol->wolopts;

2093

rp->wolopts = wol->wolopts;

2092

spin_unlock_irq(&rp->lock);

2094

spin_unlock_irq(&rp->lock);

2093

2095

2094

return 0;

2096

return 0;

2095

}

2097

}

2096

2098

2097

static const struct ethtool_ops netdev_ethtool_ops = {

2099

static const struct ethtool_ops netdev_ethtool_ops = {

2098

.get_drvinfo = netdev_get_drvinfo,

2100

.get_drvinfo = netdev_get_drvinfo,

2099

.get_settings = netdev_get_settings,

2101

.get_settings = netdev_get_settings,

2100

.set_settings = netdev_set_settings,

2102

.set_settings = netdev_set_settings,

2101

.nway_reset = netdev_nway_reset,

2103

.nway_reset = netdev_nway_reset,

2102

.get_link = netdev_get_link,

2104

.get_link = netdev_get_link,

2103

.get_msglevel = netdev_get_msglevel,

2105

.get_msglevel = netdev_get_msglevel,

2104

.set_msglevel = netdev_set_msglevel,

2106

.set_msglevel = netdev_set_msglevel,

2105

.get_wol = rhine_get_wol,

2107

.get_wol = rhine_get_wol,

2106

.set_wol = rhine_set_wol,

2108

.set_wol = rhine_set_wol,

2107

};

2109

};

2108

2110

2109

static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)

2111

static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)

2110

{

2112

{

2111

struct rhine_private *rp = netdev_priv(dev);

2113

struct rhine_private *rp = netdev_priv(dev);

2112

int rc;

2114

int rc;

2113

2115

2114

if (!netif_running(dev))

2116

if (!netif_running(dev))

2115

return -EINVAL;

2117

return -EINVAL;

2116

2118

2117

spin_lock_irq(&rp->lock);

2119

spin_lock_irq(&rp->lock);

2118

rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL);

2120

rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL);

2119

spin_unlock_irq(&rp->lock);

2121

spin_unlock_irq(&rp->lock);

2120

rhine_set_carrier(&rp->mii_if);

2122

rhine_set_carrier(&rp->mii_if);

2121

2123

2122

return rc;

2124

return rc;

2123

}

2125

}

2124

2126

2125

static int rhine_close(struct net_device *dev)

2127

static int rhine_close(struct net_device *dev)

2126

{

2128

{

2127

struct rhine_private *rp = netdev_priv(dev);

2129

struct rhine_private *rp = netdev_priv(dev);

2128

void __iomem *ioaddr = rp->base;

2130

void __iomem *ioaddr = rp->base;

2129

2131

2130

napi_disable(&rp->napi);

2132

napi_disable(&rp->napi);

2131

cancel_work_sync(&rp->reset_task);

2133

cancel_work_sync(&rp->reset_task);

2132

netif_stop_queue(dev);

2134

netif_stop_queue(dev);

2133

2135

2134

spin_lock_irq(&rp->lock);

2136

spin_lock_irq(&rp->lock);

2135

2137

2136

if (debug > 1)

2138

if (debug > 1)

2137

netdev_dbg(dev, "Shutting down ethercard, status was %04x\n",

2139

netdev_dbg(dev, "Shutting down ethercard, status was %04x\n",

2138

ioread16(ioaddr + ChipCmd));

2140

ioread16(ioaddr + ChipCmd));

2139

2141

2140

/* Switch to loopback mode to avoid hardware races. */

2142

/* Switch to loopback mode to avoid hardware races. */

2141

iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig);

2143

iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig);

2142

2144

2143

/* Disable interrupts by clearing the interrupt mask. */

2145

/* Disable interrupts by clearing the interrupt mask. */

2144

iowrite16(0x0000, ioaddr + IntrEnable);

2146

iowrite16(0x0000, ioaddr + IntrEnable);

2145

2147

2146

/* Stop the chip's Tx and Rx processes. */

2148

/* Stop the chip's Tx and Rx processes. */

2147

iowrite16(CmdStop, ioaddr + ChipCmd);

2149

iowrite16(CmdStop, ioaddr + ChipCmd);

2148

2150

2149

spin_unlock_irq(&rp->lock);

2151

spin_unlock_irq(&rp->lock);

2150

2152

2151

free_irq(rp->pdev->irq, dev);

2153

free_irq(rp->pdev->irq, dev);

2152

free_rbufs(dev);

2154

free_rbufs(dev);

2153

free_tbufs(dev);

2155

free_tbufs(dev);

2154

free_ring(dev);

2156

free_ring(dev);

2155

2157

2156

return 0;

2158

return 0;

2157

}

2159

}

2158

2160

2159

2161

2160

static void __devexit rhine_remove_one(struct pci_dev *pdev)

2162

static void __devexit rhine_remove_one(struct pci_dev *pdev)

2161

{

2163

{

2162

struct net_device *dev = pci_get_drvdata(pdev);

2164

struct net_device *dev = pci_get_drvdata(pdev);

2163

struct rhine_private *rp = netdev_priv(dev);

2165

struct rhine_private *rp = netdev_priv(dev);

2164

2166

2165

unregister_netdev(dev);

2167

unregister_netdev(dev);

2166

2168

2167

pci_iounmap(pdev, rp->base);

2169

pci_iounmap(pdev, rp->base);

2168

pci_release_regions(pdev);

2170

pci_release_regions(pdev);

2169

2171

2170

free_netdev(dev);

2172

free_netdev(dev);

2171

pci_disable_device(pdev);

2173

pci_disable_device(pdev);

2172

pci_set_drvdata(pdev, NULL);

2174

pci_set_drvdata(pdev, NULL);

2173

}

2175

}

2174

2176

2175

static void rhine_shutdown (struct pci_dev *pdev)

2177

static void rhine_shutdown (struct pci_dev *pdev)

2176

{

2178

{

2177

struct net_device *dev = pci_get_drvdata(pdev);

2179

struct net_device *dev = pci_get_drvdata(pdev);

2178

struct rhine_private *rp = netdev_priv(dev);

2180

struct rhine_private *rp = netdev_priv(dev);

2179

void __iomem *ioaddr = rp->base;

2181

void __iomem *ioaddr = rp->base;

2180

2182

2181

if (!(rp->quirks & rqWOL))

2183

if (!(rp->quirks & rqWOL))

2182

return; /* Nothing to do for non-WOL adapters */

2184

return; /* Nothing to do for non-WOL adapters */

2183

2185

2184

rhine_power_init(dev);

2186

rhine_power_init(dev);

2185

2187

2186

/* Make sure we use pattern 0, 1 and not 4, 5 */

2188

/* Make sure we use pattern 0, 1 and not 4, 5 */

2187

if (rp->quirks & rq6patterns)

2189

if (rp->quirks & rq6patterns)

2188

iowrite8(0x04, ioaddr + WOLcgClr);

2190

iowrite8(0x04, ioaddr + WOLcgClr);

2189

2191

2190

if (rp->wolopts & WAKE_MAGIC) {

2192

if (rp->wolopts & WAKE_MAGIC) {

2191

iowrite8(WOLmagic, ioaddr + WOLcrSet);

2193

iowrite8(WOLmagic, ioaddr + WOLcrSet);

2192

/*

2194

/*

2193

* Turn EEPROM-controlled wake-up back on -- some hardware may

2195

* Turn EEPROM-controlled wake-up back on -- some hardware may

2194

* not cooperate otherwise.

2196

* not cooperate otherwise.

2195

*/

2197

*/

2196

iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA);

2198

iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA);

2197

}

2199

}

2198

2200

2199

if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST))

2201

if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST))

2200

iowrite8(WOLbmcast, ioaddr + WOLcgSet);

2202

iowrite8(WOLbmcast, ioaddr + WOLcgSet);

2201

2203

2202

if (rp->wolopts & WAKE_PHY)

2204

if (rp->wolopts & WAKE_PHY)

2203

iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet);

2205

iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet);

2204

2206

2205

if (rp->wolopts & WAKE_UCAST)

2207

if (rp->wolopts & WAKE_UCAST)

2206

iowrite8(WOLucast, ioaddr + WOLcrSet);

2208

iowrite8(WOLucast, ioaddr + WOLcrSet);

2207

2209

2208

if (rp->wolopts) {

2210

if (rp->wolopts) {

2209

/* Enable legacy WOL (for old motherboards) */

2211

/* Enable legacy WOL (for old motherboards) */

2210

iowrite8(0x01, ioaddr + PwcfgSet);

2212

iowrite8(0x01, ioaddr + PwcfgSet);

2211

iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW);

2213

iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW);

2212

}

2214

}

2213

2215

2214

/* Hit power state D3 (sleep) */

2216

/* Hit power state D3 (sleep) */

2215

if (!avoid_D3)

2217

if (!avoid_D3)

2216

iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW);

2218

iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW);

2217

2219

2218

/* TODO: Check use of pci_enable_wake() */

2220

/* TODO: Check use of pci_enable_wake() */

2219

2221

2220

}

2222

}

2221

2223

2222

#ifdef CONFIG_PM

2224

#ifdef CONFIG_PM

2223

static int rhine_suspend(struct pci_dev *pdev, pm_message_t state)

2225

static int rhine_suspend(struct pci_dev *pdev, pm_message_t state)

2224

{

2226

{

2225

struct net_device *dev = pci_get_drvdata(pdev);

2227

struct net_device *dev = pci_get_drvdata(pdev);

2226

struct rhine_private *rp = netdev_priv(dev);

2228

struct rhine_private *rp = netdev_priv(dev);

2227

unsigned long flags;

2229

unsigned long flags;

2228

2230

2229

if (!netif_running(dev))

2231

if (!netif_running(dev))

2230

return 0;

2232

return 0;

2231

2233

2232

napi_disable(&rp->napi);

2234

napi_disable(&rp->napi);

2233

2235

2234

netif_device_detach(dev);

2236

netif_device_detach(dev);

2235

pci_save_state(pdev);

2237

pci_save_state(pdev);

2236

2238

2237

spin_lock_irqsave(&rp->lock, flags);

2239

spin_lock_irqsave(&rp->lock, flags);

2238

rhine_shutdown(pdev);

2240

rhine_shutdown(pdev);

2239

spin_unlock_irqrestore(&rp->lock, flags);

2241

spin_unlock_irqrestore(&rp->lock, flags);

2240

2242

2241

free_irq(dev->irq, dev);

2243

free_irq(dev->irq, dev);

2242

return 0;

2244

return 0;

2243

}

2245

}

2244

2246

2245

static int rhine_resume(struct pci_dev *pdev)

2247

static int rhine_resume(struct pci_dev *pdev)

2246

{

2248

{

2247

struct net_device *dev = pci_get_drvdata(pdev);

2249

struct net_device *dev = pci_get_drvdata(pdev);

2248

struct rhine_private *rp = netdev_priv(dev);

2250

struct rhine_private *rp = netdev_priv(dev);

2249

unsigned long flags;

2251

unsigned long flags;

2250

int ret;

2252

int ret;

2251

2253

2252

if (!netif_running(dev))

2254

if (!netif_running(dev))

2253

return 0;

2255

return 0;

2254

2256

2255

if (request_irq(dev->irq, rhine_interrupt, IRQF_SHARED, dev->name, dev))

2257

if (request_irq(dev->irq, rhine_interrupt, IRQF_SHARED, dev->name, dev))

2256

netdev_err(dev, "request_irq failed\n");

2258

netdev_err(dev, "request_irq failed\n");

2257

2259

2258

ret = pci_set_power_state(pdev, PCI_D0);

2260

ret = pci_set_power_state(pdev, PCI_D0);

2259

if (debug > 1)

2261

if (debug > 1)

2260

netdev_info(dev, "Entering power state D0 %s (%d)\n",

2262

netdev_info(dev, "Entering power state D0 %s (%d)\n",

2261

ret ? "failed" : "succeeded", ret);

2263

ret ? "failed" : "succeeded", ret);

2262

2264

2263

pci_restore_state(pdev);

2265

pci_restore_state(pdev);

2264

2266

2265

spin_lock_irqsave(&rp->lock, flags);

2267

spin_lock_irqsave(&rp->lock, flags);

2266

#ifdef USE_MMIO

2268

#ifdef USE_MMIO

2267

enable_mmio(rp->pioaddr, rp->quirks);

2269

enable_mmio(rp->pioaddr, rp->quirks);

2268

#endif

2270

#endif

2269

rhine_power_init(dev);

2271

rhine_power_init(dev);

2270

free_tbufs(dev);

2272

free_tbufs(dev);

2271

free_rbufs(dev);

2273

free_rbufs(dev);

2272

alloc_tbufs(dev);

2274

alloc_tbufs(dev);

2273

alloc_rbufs(dev);

2275

alloc_rbufs(dev);

2274

init_registers(dev);

2276

init_registers(dev);

2275

spin_unlock_irqrestore(&rp->lock, flags);

2277

spin_unlock_irqrestore(&rp->lock, flags);

2276

2278

2277

netif_device_attach(dev);

2279

netif_device_attach(dev);

2278

2280

2279

return 0;

2281

return 0;

2280

}

2282

}

2281

#endif /* CONFIG_PM */

2283

#endif /* CONFIG_PM */

2282

2284

2283

static struct pci_driver rhine_driver = {

2285

static struct pci_driver rhine_driver = {

2284

.name = DRV_NAME,

2286

.name = DRV_NAME,

2285

.id_table = rhine_pci_tbl,

2287

.id_table = rhine_pci_tbl,

2286

.probe = rhine_init_one,

2288

.probe = rhine_init_one,

2287

.remove = __devexit_p(rhine_remove_one),

2289

.remove = __devexit_p(rhine_remove_one),

2288

#ifdef CONFIG_PM

2290

#ifdef CONFIG_PM

2289

.suspend = rhine_suspend,

2291

.suspend = rhine_suspend,

2290

.resume = rhine_resume,

2292

.resume = rhine_resume,

2291

#endif /* CONFIG_PM */

2293

#endif /* CONFIG_PM */

2292

.shutdown = rhine_shutdown,

2294

.shutdown = rhine_shutdown,

2293

};

2295

};

2294

2296

2295

static struct dmi_system_id __initdata rhine_dmi_table[] = {

2297

static struct dmi_system_id __initdata rhine_dmi_table[] = {

2296

{

2298

{

2297

.ident = "EPIA-M",

2299

.ident = "EPIA-M",

2298

.matches = {

2300

.matches = {

2299

DMI_MATCH(DMI_BIOS_VENDOR, "Award Software International, Inc."),

2301

DMI_MATCH(DMI_BIOS_VENDOR, "Award Software International, Inc."),

2300

DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),

2302

DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),

2301

},

2303

},

2302

},

2304

},

2303

{

2305

{

2304

.ident = "KV7",

2306

.ident = "KV7",

2305

.matches = {

2307

.matches = {

2306

DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"),

2308

DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"),

2307

DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),

2309

DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),

2308

},

2310

},

2309

},

2311

},

2310

{ NULL }

2312

{ NULL }

2311

};

2313

};

2312

2314

2313

static int __init rhine_init(void)

2315

static int __init rhine_init(void)

2314

{

2316

{

2315

/* when a module, this is printed whether or not devices are found in probe */

2317

/* when a module, this is printed whether or not devices are found in probe */

2316

#ifdef MODULE

2318

#ifdef MODULE

2317

pr_info("%s\n", version);

2319

pr_info("%s\n", version);

2318

#endif

2320

#endif

2319

if (dmi_check_system(rhine_dmi_table)) {

2321

if (dmi_check_system(rhine_dmi_table)) {

2320

/* these BIOSes fail at PXE boot if chip is in D3 */

2322

/* these BIOSes fail at PXE boot if chip is in D3 */

2321

avoid_D3 = 1;

2323

avoid_D3 = 1;

2322

pr_warn("Broken BIOS detected, avoid_D3 enabled\n");

2324

pr_warn("Broken BIOS detected, avoid_D3 enabled\n");

2323

}

2325

}

2324

else if (avoid_D3)

2326

else if (avoid_D3)

2325

pr_info("avoid_D3 set\n");

2327

pr_info("avoid_D3 set\n");

2326

2328

2327

return pci_register_driver(&rhine_driver);

2329

return pci_register_driver(&rhine_driver);

2328

}

2330

}

2329

2331

2330

2332

2331

static void __exit rhine_cleanup(void)

2333

static void __exit rhine_cleanup(void)

2332

{

2334

{

2333

pci_unregister_driver(&rhine_driver);

2335

pci_unregister_driver(&rhine_driver);

2334

}

2336

}

2335

2337

2336

2338

2337

module_init(rhine_init);

2339

module_init(rhine_init);

2338

module_exit(rhine_cleanup);

2340

module_exit(rhine_cleanup);

GITLAB

via-rhine: Assign random MAC address if necessary

 /* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */
 /*
 	Written 1998-2001 by Donald Becker.
 	Current Maintainer: Roger Luethi <rl@hellgate.ch>
 	This software may be used and distributed according to the terms of
 	the GNU General Public License (GPL), incorporated herein by reference.
 	Drivers based on or derived from this code fall under the GPL and must
 	retain the authorship, copyright and license notice.  This file is not
 	a complete program and may only be used when the entire operating
 	system is licensed under the GPL.
 	This driver is designed for the VIA VT86C100A Rhine-I.
 	It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM
 	and management NIC 6105M).
 	The author may be reached as becker@scyld.com, or C/O
 	Scyld Computing Corporation
 	410 Severn Ave., Suite 210
 	Annapolis MD 21403
 	This driver contains some changes from the original Donald Becker
 	version. He may or may not be interested in bug reports on this
 	code. You can find his versions at:
 	http://www.scyld.com/network/via-rhine.html
 	[link no longer provides useful info -jgarzik]
 */
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 #define DRV_NAME	"via-rhine"
 #define DRV_VERSION	"1.5.0"
 #define DRV_RELDATE	"2010-10-09"
 /* A few user-configurable values.
    These may be modified when a driver module is loaded. */
 #define DEBUG
 static int debug = 1;	/* 1 normal messages, 0 quiet .. 7 verbose. */
 static int max_interrupt_work = 20;
 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
    Setting to > 1518 effectively disables this feature. */
 #if defined(__alpha__) || defined(__arm__) || defined(__hppa__) || \
 	defined(CONFIG_SPARC) || defined(__ia64__) ||		   \
 	defined(__sh__) || defined(__mips__)
 static int rx_copybreak = 1518;
 #else
 static int rx_copybreak;
 #endif
 /* Work-around for broken BIOSes: they are unable to get the chip back out of
    power state D3 so PXE booting fails. bootparam(7): via-rhine.avoid_D3=1 */
 static int avoid_D3;
 /*
  * In case you are looking for 'options[]' or 'full_duplex[]', they
  * are gone. Use ethtool(8) instead.
  */
 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
    The Rhine has a 64 element 8390-like hash table. */
 static const int multicast_filter_limit = 32;
 /* Operational parameters that are set at compile time. */
 /* Keep the ring sizes a power of two for compile efficiency.
    The compiler will convert <unsigned>'%'<2^N> into a bit mask.
    Making the Tx ring too large decreases the effectiveness of channel
    bonding and packet priority.
    There are no ill effects from too-large receive rings. */
 #define TX_RING_SIZE	16
 #define TX_QUEUE_LEN	10	/* Limit ring entries actually used. */
 #define RX_RING_SIZE	64
 /* Operational parameters that usually are not changed. */
 /* Time in jiffies before concluding the transmitter is hung. */
 #define TX_TIMEOUT	(2*HZ)
 #define PKT_BUF_SZ	1536	/* Size of each temporary Rx buffer.*/
 #include <linux/module.h>
 #include <linux/moduleparam.h>
 #include <linux/kernel.h>
 #include <linux/string.h>
 #include <linux/timer.h>
 #include <linux/errno.h>
 #include <linux/ioport.h>
 #include <linux/interrupt.h>
 #include <linux/pci.h>
 #include <linux/dma-mapping.h>
 #include <linux/netdevice.h>
 #include <linux/etherdevice.h>
 #include <linux/skbuff.h>
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/mii.h>
 #include <linux/ethtool.h>
 #include <linux/crc32.h>
 #include <linux/if_vlan.h>
 #include <linux/bitops.h>
 #include <linux/workqueue.h>
 #include <asm/processor.h>	/* Processor type for cache alignment. */
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/uaccess.h>
 #include <linux/dmi.h>
 /* These identify the driver base version and may not be removed. */
 static const char version[] __devinitconst =
 	"v1.10-LK" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker";
 /* This driver was written to use PCI memory space. Some early versions
    of the Rhine may only work correctly with I/O space accesses. */
 #ifdef CONFIG_VIA_RHINE_MMIO
 #define USE_MMIO
 #else
 #endif
 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
 MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver");
 MODULE_LICENSE("GPL");
 module_param(max_interrupt_work, int, 0);
 module_param(debug, int, 0);
 module_param(rx_copybreak, int, 0);
 module_param(avoid_D3, bool, 0);
 MODULE_PARM_DESC(max_interrupt_work, "VIA Rhine maximum events handled per interrupt");
 MODULE_PARM_DESC(debug, "VIA Rhine debug level (0-7)");
 MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
 MODULE_PARM_DESC(avoid_D3, "Avoid power state D3 (work-around for broken BIOSes)");
 #define MCAM_SIZE	32
 #define VCAM_SIZE	32
 /*
 		Theory of Operation
 I. Board Compatibility
 This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet
 controller.
 II. Board-specific settings
 Boards with this chip are functional only in a bus-master PCI slot.
 Many operational settings are loaded from the EEPROM to the Config word at
 offset 0x78. For most of these settings, this driver assumes that they are
 correct.
 If this driver is compiled to use PCI memory space operations the EEPROM
 must be configured to enable memory ops.
 III. Driver operation
 IIIa. Ring buffers
 This driver uses two statically allocated fixed-size descriptor lists
 formed into rings by a branch from the final descriptor to the beginning of
 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
 IIIb/c. Transmit/Receive Structure
 This driver attempts to use a zero-copy receive and transmit scheme.
 Alas, all data buffers are required to start on a 32 bit boundary, so
 the driver must often copy transmit packets into bounce buffers.
 The driver allocates full frame size skbuffs for the Rx ring buffers at
 open() time and passes the skb->data field to the chip as receive data
 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
 a fresh skbuff is allocated and the frame is copied to the new skbuff.
 When the incoming frame is larger, the skbuff is passed directly up the
 protocol stack. Buffers consumed this way are replaced by newly allocated
 skbuffs in the last phase of rhine_rx().
 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
 using a full-sized skbuff for small frames vs. the copying costs of larger
 frames. New boards are typically used in generously configured machines
 and the underfilled buffers have negligible impact compared to the benefit of
 a single allocation size, so the default value of zero results in never
 copying packets. When copying is done, the cost is usually mitigated by using
 a combined copy/checksum routine. Copying also preloads the cache, which is
 most useful with small frames.
 Since the VIA chips are only able to transfer data to buffers on 32 bit
 boundaries, the IP header at offset 14 in an ethernet frame isn't
 longword aligned for further processing. Copying these unaligned buffers
 has the beneficial effect of 16-byte aligning the IP header.
 IIId. Synchronization
 The driver runs as two independent, single-threaded flows of control. One
 is the send-packet routine, which enforces single-threaded use by the
 netdev_priv(dev)->lock spinlock. The other thread is the interrupt handler,
 which is single threaded by the hardware and interrupt handling software.
 The send packet thread has partial control over the Tx ring. It locks the
 netdev_priv(dev)->lock whenever it's queuing a Tx packet. If the next slot in
 the ring is not available it stops the transmit queue by
 calling netif_stop_queue.
 The interrupt handler has exclusive control over the Rx ring and records stats
 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
 empty by incrementing the dirty_tx mark. If at least half of the entries in
 the Rx ring are available the transmit queue is woken up if it was stopped.
 IV. Notes
 IVb. References
 Preliminary VT86C100A manual from http://www.via.com.tw/
 http://www.scyld.com/expert/100mbps.html
 http://www.scyld.com/expert/NWay.html
 ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf
 ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF
 IVc. Errata
 The VT86C100A manual is not reliable information.
 The 3043 chip does not handle unaligned transmit or receive buffers, resulting
 in significant performance degradation for bounce buffer copies on transmit
 and unaligned IP headers on receive.
 The chip does not pad to minimum transmit length.
 */
 /* This table drives the PCI probe routines. It's mostly boilerplate in all
    of the drivers, and will likely be provided by some future kernel.
    Note the matching code -- the first table entry matchs all 56** cards but
    second only the 1234 card.
 */
 enum rhine_revs {
 	VT86C100A	= 0x00,
 	VTunknown0	= 0x20,
 	VT6102		= 0x40,
 	VT8231		= 0x50,	/* Integrated MAC */
 	VT8233		= 0x60,	/* Integrated MAC */
 	VT8235		= 0x74,	/* Integrated MAC */
 	VT8237		= 0x78,	/* Integrated MAC */
 	VTunknown1	= 0x7C,
 	VT6105		= 0x80,
 	VT6105_B0	= 0x83,
 	VT6105L		= 0x8A,
 	VT6107		= 0x8C,
 	VTunknown2	= 0x8E,
 	VT6105M		= 0x90,	/* Management adapter */
 };
 enum rhine_quirks {
 	rqWOL		= 0x0001,	/* Wake-On-LAN support */
 	rqForceReset	= 0x0002,
 	rq6patterns	= 0x0040,	/* 6 instead of 4 patterns for WOL */
 	rqStatusWBRace	= 0x0080,	/* Tx Status Writeback Error possible */
 	rqRhineI	= 0x0100,	/* See comment below */
 };
 /*
  * rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable
  * MMIO as well as for the collision counter and the Tx FIFO underflow
  * indicator. In addition, Tx and Rx buffers need to 4 byte aligned.
  */
 /* Beware of PCI posted writes */
 #define IOSYNC	do { ioread8(ioaddr + StationAddr); } while (0)
 static DEFINE_PCI_DEVICE_TABLE(rhine_pci_tbl) = {
 	{ 0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, },	/* VT86C100A */
 	{ 0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, },	/* VT6102 */
 	{ 0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, },	/* 6105{,L,LOM} */
 	{ 0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, },	/* VT6105M */
 	{ }	/* terminate list */
 };
 MODULE_DEVICE_TABLE(pci, rhine_pci_tbl);
 /* Offsets to the device registers. */
 enum register_offsets {
 	StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
 	ChipCmd1=0x09, TQWake=0x0A,
 	IntrStatus=0x0C, IntrEnable=0x0E,
 	MulticastFilter0=0x10, MulticastFilter1=0x14,
 	RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
 	MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E, PCIBusConfig1=0x6F,
 	MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
 	ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
 	RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
 	StickyHW=0x83, IntrStatus2=0x84,
 	CamMask=0x88, CamCon=0x92, CamAddr=0x93,
 	WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4,
 	WOLcrClr1=0xA6, WOLcgClr=0xA7,
 	PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD,
 };
 /* Bits in ConfigD */
 enum backoff_bits {
 	BackOptional=0x01, BackModify=0x02,
 	BackCaptureEffect=0x04, BackRandom=0x08
 };
 /* Bits in the TxConfig (TCR) register */
 enum tcr_bits {
 	TCR_PQEN=0x01,
 	TCR_LB0=0x02,		/* loopback[0] */
 	TCR_LB1=0x04,		/* loopback[1] */
 	TCR_OFSET=0x08,
 	TCR_RTGOPT=0x10,
 	TCR_RTFT0=0x20,
 	TCR_RTFT1=0x40,
 	TCR_RTSF=0x80,
 };
 /* Bits in the CamCon (CAMC) register */
 enum camcon_bits {
 	CAMC_CAMEN=0x01,
 	CAMC_VCAMSL=0x02,
 	CAMC_CAMWR=0x04,
 	CAMC_CAMRD=0x08,
 };
 /* Bits in the PCIBusConfig1 (BCR1) register */
 enum bcr1_bits {
 	BCR1_POT0=0x01,
 	BCR1_POT1=0x02,
 	BCR1_POT2=0x04,
 	BCR1_CTFT0=0x08,
 	BCR1_CTFT1=0x10,
 	BCR1_CTSF=0x20,
 	BCR1_TXQNOBK=0x40,	/* for VT6105 */
 	BCR1_VIDFR=0x80,	/* for VT6105 */
 	BCR1_MED0=0x40,		/* for VT6102 */
 	BCR1_MED1=0x80,		/* for VT6102 */
 };
 #ifdef USE_MMIO
 /* Registers we check that mmio and reg are the same. */
 static const int mmio_verify_registers[] = {
 	RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD,
 	0
 };
 #endif
 /* Bits in the interrupt status/mask registers. */
 enum intr_status_bits {
 	IntrRxDone=0x0001, IntrRxErr=0x0004, IntrRxEmpty=0x0020,
 	IntrTxDone=0x0002, IntrTxError=0x0008, IntrTxUnderrun=0x0210,
 	IntrPCIErr=0x0040,
 	IntrStatsMax=0x0080, IntrRxEarly=0x0100,
 	IntrRxOverflow=0x0400, IntrRxDropped=0x0800, IntrRxNoBuf=0x1000,
 	IntrTxAborted=0x2000, IntrLinkChange=0x4000,
 	IntrRxWakeUp=0x8000,
 	IntrNormalSummary=0x0003, IntrAbnormalSummary=0xC260,
 	IntrTxDescRace=0x080000,	/* mapped from IntrStatus2 */
 	IntrTxErrSummary=0x082218,
 };
 /* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */
 enum wol_bits {
 	WOLucast	= 0x10,
 	WOLmagic	= 0x20,
 	WOLbmcast	= 0x30,
 	WOLlnkon	= 0x40,
 	WOLlnkoff	= 0x80,
 };
 /* The Rx and Tx buffer descriptors. */
 struct rx_desc {
 	__le32 rx_status;
 	__le32 desc_length; /* Chain flag, Buffer/frame length */
 	__le32 addr;
 	__le32 next_desc;
 };
 struct tx_desc {
 	__le32 tx_status;
 	__le32 desc_length; /* Chain flag, Tx Config, Frame length */
 	__le32 addr;
 	__le32 next_desc;
 };
 /* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */
 #define TXDESC		0x00e08000
 enum rx_status_bits {
 	RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F
 };
 /* Bits in *_desc.*_status */
 enum desc_status_bits {
 	DescOwn=0x80000000
 };
 /* Bits in *_desc.*_length */
 enum desc_length_bits {
 	DescTag=0x00010000
 };
 /* Bits in ChipCmd. */
 enum chip_cmd_bits {
 	CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08,
 	CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40,
 	Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04,
 	Cmd1NoTxPoll=0x08, Cmd1Reset=0x80,
 };
 struct rhine_private {
 	/* Bit mask for configured VLAN ids */
 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 	/* Descriptor rings */
 	struct rx_desc *rx_ring;
 	struct tx_desc *tx_ring;
 	dma_addr_t rx_ring_dma;
 	dma_addr_t tx_ring_dma;
 	/* The addresses of receive-in-place skbuffs. */
 	struct sk_buff *rx_skbuff[RX_RING_SIZE];
 	dma_addr_t rx_skbuff_dma[RX_RING_SIZE];
 	/* The saved address of a sent-in-place packet/buffer, for later free(). */
 	struct sk_buff *tx_skbuff[TX_RING_SIZE];
 	dma_addr_t tx_skbuff_dma[TX_RING_SIZE];
 	/* Tx bounce buffers (Rhine-I only) */
 	unsigned char *tx_buf[TX_RING_SIZE];
 	unsigned char *tx_bufs;
 	dma_addr_t tx_bufs_dma;
 	struct pci_dev *pdev;
 	long pioaddr;
 	struct net_device *dev;
 	struct napi_struct napi;
 	spinlock_t lock;
 	struct work_struct reset_task;
 	/* Frequently used values: keep some adjacent for cache effect. */
 	u32 quirks;
 	struct rx_desc *rx_head_desc;
 	unsigned int cur_rx, dirty_rx;	/* Producer/consumer ring indices */
 	unsigned int cur_tx, dirty_tx;
 	unsigned int rx_buf_sz;		/* Based on MTU+slack. */
 	u8 wolopts;
 	u8 tx_thresh, rx_thresh;
 	struct mii_if_info mii_if;
 	void __iomem *base;
 };
 #define BYTE_REG_BITS_ON(x, p)      do { iowrite8((ioread8((p))|(x)), (p)); } while (0)
 #define WORD_REG_BITS_ON(x, p)      do { iowrite16((ioread16((p))|(x)), (p)); } while (0)
 #define DWORD_REG_BITS_ON(x, p)     do { iowrite32((ioread32((p))|(x)), (p)); } while (0)
 #define BYTE_REG_BITS_IS_ON(x, p)   (ioread8((p)) & (x))
 #define WORD_REG_BITS_IS_ON(x, p)   (ioread16((p)) & (x))
 #define DWORD_REG_BITS_IS_ON(x, p)  (ioread32((p)) & (x))
 #define BYTE_REG_BITS_OFF(x, p)     do { iowrite8(ioread8((p)) & (~(x)), (p)); } while (0)
 #define WORD_REG_BITS_OFF(x, p)     do { iowrite16(ioread16((p)) & (~(x)), (p)); } while (0)
 #define DWORD_REG_BITS_OFF(x, p)    do { iowrite32(ioread32((p)) & (~(x)), (p)); } while (0)
 #define BYTE_REG_BITS_SET(x, m, p)   do { iowrite8((ioread8((p)) & (~(m)))|(x), (p)); } while (0)
 #define WORD_REG_BITS_SET(x, m, p)   do { iowrite16((ioread16((p)) & (~(m)))|(x), (p)); } while (0)
 #define DWORD_REG_BITS_SET(x, m, p)  do { iowrite32((ioread32((p)) & (~(m)))|(x), (p)); } while (0)
 static int  mdio_read(struct net_device *dev, int phy_id, int location);
 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
 static int  rhine_open(struct net_device *dev);
 static void rhine_reset_task(struct work_struct *work);
 static void rhine_tx_timeout(struct net_device *dev);
 static netdev_tx_t rhine_start_tx(struct sk_buff *skb,
 				  struct net_device *dev);
 static irqreturn_t rhine_interrupt(int irq, void *dev_instance);
 static void rhine_tx(struct net_device *dev);
 static int rhine_rx(struct net_device *dev, int limit);
 static void rhine_error(struct net_device *dev, int intr_status);
 static void rhine_set_rx_mode(struct net_device *dev);
 static struct net_device_stats *rhine_get_stats(struct net_device *dev);
 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 static const struct ethtool_ops netdev_ethtool_ops;
 static int  rhine_close(struct net_device *dev);
 static void rhine_shutdown (struct pci_dev *pdev);
 static void rhine_vlan_rx_add_vid(struct net_device *dev, unsigned short vid);
 static void rhine_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid);
 static void rhine_set_cam(void __iomem *ioaddr, int idx, u8 *addr);
 static void rhine_set_vlan_cam(void __iomem *ioaddr, int idx, u8 *addr);
 static void rhine_set_cam_mask(void __iomem *ioaddr, u32 mask);
 static void rhine_set_vlan_cam_mask(void __iomem *ioaddr, u32 mask);
 static void rhine_init_cam_filter(struct net_device *dev);
 static void rhine_update_vcam(struct net_device *dev);
 #define RHINE_WAIT_FOR(condition)				\
 do {								\
 	int i = 1024;						\
 	while (!(condition) && --i)				\
 		;						\
 	if (debug > 1 && i < 512)				\
 		pr_info("%4d cycles used @ %s:%d\n",		\
 			1024 - i, __func__, __LINE__);		\
 } while (0)
 static inline u32 get_intr_status(struct net_device *dev)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	void __iomem *ioaddr = rp->base;
 	u32 intr_status;
 	intr_status = ioread16(ioaddr + IntrStatus);
 	/* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
 	if (rp->quirks & rqStatusWBRace)
 		intr_status |= ioread8(ioaddr + IntrStatus2) << 16;
 	return intr_status;
 }
 /*
  * Get power related registers into sane state.
  * Notify user about past WOL event.
  */
 static void rhine_power_init(struct net_device *dev)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	void __iomem *ioaddr = rp->base;
 	u16 wolstat;
 	if (rp->quirks & rqWOL) {
 		/* Make sure chip is in power state D0 */
 		iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);
 		/* Disable "force PME-enable" */
 		iowrite8(0x80, ioaddr + WOLcgClr);
 		/* Clear power-event config bits (WOL) */
 		iowrite8(0xFF, ioaddr + WOLcrClr);
 		/* More recent cards can manage two additional patterns */
 		if (rp->quirks & rq6patterns)
 			iowrite8(0x03, ioaddr + WOLcrClr1);
 		/* Save power-event status bits */
 		wolstat = ioread8(ioaddr + PwrcsrSet);
 		if (rp->quirks & rq6patterns)
 			wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8;
 		/* Clear power-event status bits */
 		iowrite8(0xFF, ioaddr + PwrcsrClr);
 		if (rp->quirks & rq6patterns)
 			iowrite8(0x03, ioaddr + PwrcsrClr1);
 		if (wolstat) {
 			char *reason;
 			switch (wolstat) {
 			case WOLmagic:
 				reason = "Magic packet";
 				break;
 			case WOLlnkon:
 				reason = "Link went up";
 				break;
 			case WOLlnkoff:
 				reason = "Link went down";
 				break;
 			case WOLucast:
 				reason = "Unicast packet";
 				break;
 			case WOLbmcast:
 				reason = "Multicast/broadcast packet";
 				break;
 			default:
 				reason = "Unknown";
 			}
 			netdev_info(dev, "Woke system up. Reason: %s\n",
 				    reason);
 		}
 	}
 }
 static void rhine_chip_reset(struct net_device *dev)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	void __iomem *ioaddr = rp->base;
 	iowrite8(Cmd1Reset, ioaddr + ChipCmd1);
 	IOSYNC;
 	if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) {
 		netdev_info(dev, "Reset not complete yet. Trying harder.\n");
 		/* Force reset */
 		if (rp->quirks & rqForceReset)
 			iowrite8(0x40, ioaddr + MiscCmd);
 		/* Reset can take somewhat longer (rare) */
 		RHINE_WAIT_FOR(!(ioread8(ioaddr + ChipCmd1) & Cmd1Reset));
 	}
 	if (debug > 1)
 		netdev_info(dev, "Reset %s\n",
 			    (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) ?
 			    "failed" : "succeeded");
 }
 #ifdef USE_MMIO
 static void enable_mmio(long pioaddr, u32 quirks)
 {
 	int n;
 	if (quirks & rqRhineI) {
 		/* More recent docs say that this bit is reserved ... */
 		n = inb(pioaddr + ConfigA) | 0x20;
 		outb(n, pioaddr + ConfigA);
 	} else {
 		n = inb(pioaddr + ConfigD) | 0x80;
 		outb(n, pioaddr + ConfigD);
 	}
 }
 #endif
 /*
  * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM
  * (plus 0x6C for Rhine-I/II)
  */
 static void __devinit rhine_reload_eeprom(long pioaddr, struct net_device *dev)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	void __iomem *ioaddr = rp->base;
 	outb(0x20, pioaddr + MACRegEEcsr);
 	RHINE_WAIT_FOR(!(inb(pioaddr + MACRegEEcsr) & 0x20));
 #ifdef USE_MMIO
 	/*
 	 * Reloading from EEPROM overwrites ConfigA-D, so we must re-enable
 	 * MMIO. If reloading EEPROM was done first this could be avoided, but
 	 * it is not known if that still works with the "win98-reboot" problem.
 	 */
 	enable_mmio(pioaddr, rp->quirks);
 #endif
 	/* Turn off EEPROM-controlled wake-up (magic packet) */
 	if (rp->quirks & rqWOL)
 		iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);
 }
 #ifdef CONFIG_NET_POLL_CONTROLLER
 static void rhine_poll(struct net_device *dev)
 {
 	disable_irq(dev->irq);
 	rhine_interrupt(dev->irq, (void *)dev);
 	enable_irq(dev->irq);
 }
 #endif
 static int rhine_napipoll(struct napi_struct *napi, int budget)
 {
 	struct rhine_private *rp = container_of(napi, struct rhine_private, napi);
 	struct net_device *dev = rp->dev;
 	void __iomem *ioaddr = rp->base;
 	int work_done;
 	work_done = rhine_rx(dev, budget);
 	if (work_done < budget) {
 		napi_complete(napi);
 		iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
 			  IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
 			  IntrTxDone | IntrTxError | IntrTxUnderrun |
 			  IntrPCIErr | IntrStatsMax | IntrLinkChange,
 			  ioaddr + IntrEnable);
 	}
 	return work_done;
 }
 static void __devinit rhine_hw_init(struct net_device *dev, long pioaddr)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	/* Reset the chip to erase previous misconfiguration. */
 	rhine_chip_reset(dev);
 	/* Rhine-I needs extra time to recuperate before EEPROM reload */
 	if (rp->quirks & rqRhineI)
 		msleep(5);
 	/* Reload EEPROM controlled bytes cleared by soft reset */
 	rhine_reload_eeprom(pioaddr, dev);
 }
 static const struct net_device_ops rhine_netdev_ops = {
 	.ndo_open		 = rhine_open,
 	.ndo_stop		 = rhine_close,
 	.ndo_start_xmit		 = rhine_start_tx,
 	.ndo_get_stats		 = rhine_get_stats,
 	.ndo_set_multicast_list	 = rhine_set_rx_mode,
 	.ndo_change_mtu		 = eth_change_mtu,
 	.ndo_validate_addr	 = eth_validate_addr,
 	.ndo_set_mac_address 	 = eth_mac_addr,
 	.ndo_do_ioctl		 = netdev_ioctl,
 	.ndo_tx_timeout 	 = rhine_tx_timeout,
 	.ndo_vlan_rx_add_vid	 = rhine_vlan_rx_add_vid,
 	.ndo_vlan_rx_kill_vid	 = rhine_vlan_rx_kill_vid,
 #ifdef CONFIG_NET_POLL_CONTROLLER
 	.ndo_poll_controller	 = rhine_poll,
 #endif
 };
 static int __devinit rhine_init_one(struct pci_dev *pdev,
 				    const struct pci_device_id *ent)
 {
 	struct net_device *dev;
 	struct rhine_private *rp;
 	int i, rc;
 	u32 quirks;
 	long pioaddr;
 	long memaddr;
 	void __iomem *ioaddr;
 	int io_size, phy_id;
 	const char *name;
 #ifdef USE_MMIO
 	int bar = 1;
 #else
 	int bar = 0;
 #endif
 /* when built into the kernel, we only print version if device is found */
 #ifndef MODULE
 	pr_info_once("%s\n", version);
 #endif
 	io_size = 256;
 	phy_id = 0;
 	quirks = 0;
 	name = "Rhine";
 	if (pdev->revision < VTunknown0) {
 		quirks = rqRhineI;
 		io_size = 128;
 	}
 	else if (pdev->revision >= VT6102) {
 		quirks = rqWOL | rqForceReset;
 		if (pdev->revision < VT6105) {
 			name = "Rhine II";
 			quirks |= rqStatusWBRace;	/* Rhine-II exclusive */
 		}
 		else {
 			phy_id = 1;	/* Integrated PHY, phy_id fixed to 1 */
 			if (pdev->revision >= VT6105_B0)
 				quirks |= rq6patterns;
 			if (pdev->revision < VT6105M)
 				name = "Rhine III";
 			else
 				name = "Rhine III (Management Adapter)";
 		}
 	}
 	rc = pci_enable_device(pdev);
 	if (rc)
 		goto err_out;
 	/* this should always be supported */
 	rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 	if (rc) {
 		dev_err(&pdev->dev,
 			"32-bit PCI DMA addresses not supported by the card!?\n");
 		goto err_out;
 	}
 	/* sanity check */
 	if ((pci_resource_len(pdev, 0) < io_size) ||
 	    (pci_resource_len(pdev, 1) < io_size)) {
 		rc = -EIO;
 		dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n");
 		goto err_out;
 	}
 	pioaddr = pci_resource_start(pdev, 0);
 	memaddr = pci_resource_start(pdev, 1);
 	pci_set_master(pdev);
 	dev = alloc_etherdev(sizeof(struct rhine_private));
 	if (!dev) {
 		rc = -ENOMEM;
 		dev_err(&pdev->dev, "alloc_etherdev failed\n");
 		goto err_out;
 	}
 	SET_NETDEV_DEV(dev, &pdev->dev);
 	rp = netdev_priv(dev);
 	rp->dev = dev;
 	rp->quirks = quirks;
 	rp->pioaddr = pioaddr;
 	rp->pdev = pdev;
 	rc = pci_request_regions(pdev, DRV_NAME);
 	if (rc)
 		goto err_out_free_netdev;
 	ioaddr = pci_iomap(pdev, bar, io_size);
 	if (!ioaddr) {
 		rc = -EIO;
 		dev_err(&pdev->dev,
 			"ioremap failed for device %s, region 0x%X @ 0x%lX\n",
 			pci_name(pdev), io_size, memaddr);
 		goto err_out_free_res;
 	}
 #ifdef USE_MMIO
 	enable_mmio(pioaddr, quirks);
 	/* Check that selected MMIO registers match the PIO ones */
 	i = 0;
 	while (mmio_verify_registers[i]) {
 		int reg = mmio_verify_registers[i++];
 		unsigned char a = inb(pioaddr+reg);
 		unsigned char b = readb(ioaddr+reg);
 		if (a != b) {
 			rc = -EIO;
 			dev_err(&pdev->dev,
 				"MMIO do not match PIO [%02x] (%02x != %02x)\n",
 				reg, a, b);
 			goto err_out_unmap;
 		}
 	}
 #endif /* USE_MMIO */
 	dev->base_addr = (unsigned long)ioaddr;
 	rp->base = ioaddr;
 	/* Get chip registers into a sane state */
 	rhine_power_init(dev);
 	rhine_hw_init(dev, pioaddr);
 	for (i = 0; i < 6; i++)
 		dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i);
-	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
-	if (!is_valid_ether_addr(dev->perm_addr)) {
+	if (!is_valid_ether_addr(dev->dev_addr)) {
-		rc = -EIO;
+		/* Report it and use a random ethernet address instead */
-		dev_err(&pdev->dev, "Invalid MAC address\n");
+		netdev_err(dev, "Invalid MAC address: %pM\n", dev->dev_addr);
-		goto err_out_unmap;
+		random_ether_addr(dev->dev_addr);
+		netdev_info(dev, "Using random MAC address: %pM\n",
+			    dev->dev_addr);
 	}
+	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
 	/* For Rhine-I/II, phy_id is loaded from EEPROM */
 	if (!phy_id)
 		phy_id = ioread8(ioaddr + 0x6C);
 	dev->irq = pdev->irq;
 	spin_lock_init(&rp->lock);
 	INIT_WORK(&rp->reset_task, rhine_reset_task);
 	rp->mii_if.dev = dev;
 	rp->mii_if.mdio_read = mdio_read;
 	rp->mii_if.mdio_write = mdio_write;
 	rp->mii_if.phy_id_mask = 0x1f;
 	rp->mii_if.reg_num_mask = 0x1f;
 	/* The chip-specific entries in the device structure. */
 	dev->netdev_ops = &rhine_netdev_ops;
 	dev->ethtool_ops = &netdev_ethtool_ops,
 	dev->watchdog_timeo = TX_TIMEOUT;
 	netif_napi_add(dev, &rp->napi, rhine_napipoll, 64);
 	if (rp->quirks & rqRhineI)
 		dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
 	if (pdev->revision >= VT6105M)
 		dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX |
 		NETIF_F_HW_VLAN_FILTER;
 	/* dev->name not defined before register_netdev()! */
 	rc = register_netdev(dev);
 	if (rc)
 		goto err_out_unmap;
 	netdev_info(dev, "VIA %s at 0x%lx, %pM, IRQ %d\n",
 		    name,
 #ifdef USE_MMIO
 		    memaddr,
 #else
 		    (long)ioaddr,
 #endif
 		    dev->dev_addr, pdev->irq);
 	pci_set_drvdata(pdev, dev);
 	{
 		u16 mii_cmd;
 		int mii_status = mdio_read(dev, phy_id, 1);
 		mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE;
 		mdio_write(dev, phy_id, MII_BMCR, mii_cmd);
 		if (mii_status != 0xffff && mii_status != 0x0000) {
 			rp->mii_if.advertising = mdio_read(dev, phy_id, 4);
 			netdev_info(dev,
 				    "MII PHY found at address %d, status 0x%04x advertising %04x Link %04x\n",
 				    phy_id,
 				    mii_status, rp->mii_if.advertising,
 				    mdio_read(dev, phy_id, 5));
 			/* set IFF_RUNNING */
 			if (mii_status & BMSR_LSTATUS)
 				netif_carrier_on(dev);
 			else
 				netif_carrier_off(dev);
 		}
 	}
 	rp->mii_if.phy_id = phy_id;
 	if (debug > 1 && avoid_D3)
 		netdev_info(dev, "No D3 power state at shutdown\n");
 	return 0;
 err_out_unmap:
 	pci_iounmap(pdev, ioaddr);
 err_out_free_res:
 	pci_release_regions(pdev);
 err_out_free_netdev:
 	free_netdev(dev);
 err_out:
 	return rc;
 }
 static int alloc_ring(struct net_device* dev)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	void *ring;
 	dma_addr_t ring_dma;
 	ring = pci_alloc_consistent(rp->pdev,
 				    RX_RING_SIZE * sizeof(struct rx_desc) +
 				    TX_RING_SIZE * sizeof(struct tx_desc),
 				    &ring_dma);
 	if (!ring) {
 		netdev_err(dev, "Could not allocate DMA memory\n");
 		return -ENOMEM;
 	}
 	if (rp->quirks & rqRhineI) {
 		rp->tx_bufs = pci_alloc_consistent(rp->pdev,
 						   PKT_BUF_SZ * TX_RING_SIZE,
 						   &rp->tx_bufs_dma);
 		if (rp->tx_bufs == NULL) {
 			pci_free_consistent(rp->pdev,
 				    RX_RING_SIZE * sizeof(struct rx_desc) +
 				    TX_RING_SIZE * sizeof(struct tx_desc),
 				    ring, ring_dma);
 			return -ENOMEM;
 		}
 	}
 	rp->rx_ring = ring;
 	rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc);
 	rp->rx_ring_dma = ring_dma;
 	rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc);
 	return 0;
 }
 static void free_ring(struct net_device* dev)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	pci_free_consistent(rp->pdev,
 			    RX_RING_SIZE * sizeof(struct rx_desc) +
 			    TX_RING_SIZE * sizeof(struct tx_desc),
 			    rp->rx_ring, rp->rx_ring_dma);
 	rp->tx_ring = NULL;
 	if (rp->tx_bufs)
 		pci_free_consistent(rp->pdev, PKT_BUF_SZ * TX_RING_SIZE,
 				    rp->tx_bufs, rp->tx_bufs_dma);
 	rp->tx_bufs = NULL;
 }
 static void alloc_rbufs(struct net_device *dev)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	dma_addr_t next;
 	int i;
 	rp->dirty_rx = rp->cur_rx = 0;
 	rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
 	rp->rx_head_desc = &rp->rx_ring[0];
 	next = rp->rx_ring_dma;
 	/* Init the ring entries */
 	for (i = 0; i < RX_RING_SIZE; i++) {
 		rp->rx_ring[i].rx_status = 0;
 		rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz);
 		next += sizeof(struct rx_desc);
 		rp->rx_ring[i].next_desc = cpu_to_le32(next);
 		rp->rx_skbuff[i] = NULL;
 	}
 	/* Mark the last entry as wrapping the ring. */
 	rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma);
 	/* Fill in the Rx buffers.  Handle allocation failure gracefully. */
 	for (i = 0; i < RX_RING_SIZE; i++) {
 		struct sk_buff *skb = netdev_alloc_skb(dev, rp->rx_buf_sz);
 		rp->rx_skbuff[i] = skb;
 		if (skb == NULL)
 			break;
 		skb->dev = dev;                 /* Mark as being used by this device. */
 		rp->rx_skbuff_dma[i] =
 			pci_map_single(rp->pdev, skb->data, rp->rx_buf_sz,
 				       PCI_DMA_FROMDEVICE);
 		rp->rx_ring[i].addr = cpu_to_le32(rp->rx_skbuff_dma[i]);
 		rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn);
 	}
 	rp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
 }
 static void free_rbufs(struct net_device* dev)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	int i;
 	/* Free all the skbuffs in the Rx queue. */
 	for (i = 0; i < RX_RING_SIZE; i++) {
 		rp->rx_ring[i].rx_status = 0;
 		rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
 		if (rp->rx_skbuff[i]) {
 			pci_unmap_single(rp->pdev,
 					 rp->rx_skbuff_dma[i],
 					 rp->rx_buf_sz, PCI_DMA_FROMDEVICE);
 			dev_kfree_skb(rp->rx_skbuff[i]);
 		}
 		rp->rx_skbuff[i] = NULL;
 	}
 }
 static void alloc_tbufs(struct net_device* dev)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	dma_addr_t next;
 	int i;
 	rp->dirty_tx = rp->cur_tx = 0;
 	next = rp->tx_ring_dma;
 	for (i = 0; i < TX_RING_SIZE; i++) {
 		rp->tx_skbuff[i] = NULL;
 		rp->tx_ring[i].tx_status = 0;
 		rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
 		next += sizeof(struct tx_desc);
 		rp->tx_ring[i].next_desc = cpu_to_le32(next);
 		if (rp->quirks & rqRhineI)
 			rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ];
 	}
 	rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma);
 }
 static void free_tbufs(struct net_device* dev)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	int i;
 	for (i = 0; i < TX_RING_SIZE; i++) {
 		rp->tx_ring[i].tx_status = 0;
 		rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
 		rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
 		if (rp->tx_skbuff[i]) {
 			if (rp->tx_skbuff_dma[i]) {
 				pci_unmap_single(rp->pdev,
 						 rp->tx_skbuff_dma[i],
 						 rp->tx_skbuff[i]->len,
 						 PCI_DMA_TODEVICE);
 			}
 			dev_kfree_skb(rp->tx_skbuff[i]);
 		}
 		rp->tx_skbuff[i] = NULL;
 		rp->tx_buf[i] = NULL;
 	}
 }
 static void rhine_check_media(struct net_device *dev, unsigned int init_media)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	void __iomem *ioaddr = rp->base;
 	mii_check_media(&rp->mii_if, debug, init_media);
 	if (rp->mii_if.full_duplex)
 	    iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex,
 		   ioaddr + ChipCmd1);
 	else
 	    iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex,
 		   ioaddr + ChipCmd1);
 	if (debug > 1)
 		netdev_info(dev, "force_media %d, carrier %d\n",
 			    rp->mii_if.force_media, netif_carrier_ok(dev));
 }
 /* Called after status of force_media possibly changed */
 static void rhine_set_carrier(struct mii_if_info *mii)
 {
 	if (mii->force_media) {
 		/* autoneg is off: Link is always assumed to be up */
 		if (!netif_carrier_ok(mii->dev))
 			netif_carrier_on(mii->dev);
 	}
 	else	/* Let MMI library update carrier status */
 		rhine_check_media(mii->dev, 0);
 	if (debug > 1)
 		netdev_info(mii->dev, "force_media %d, carrier %d\n",
 			    mii->force_media, netif_carrier_ok(mii->dev));
 }
 /**
  * rhine_set_cam - set CAM multicast filters
  * @ioaddr: register block of this Rhine
  * @idx: multicast CAM index [0..MCAM_SIZE-1]
  * @addr: multicast address (6 bytes)
  *
  * Load addresses into multicast filters.
  */
 static void rhine_set_cam(void __iomem *ioaddr, int idx, u8 *addr)
 {
 	int i;
 	iowrite8(CAMC_CAMEN, ioaddr + CamCon);
 	wmb();
 	/* Paranoid -- idx out of range should never happen */
 	idx &= (MCAM_SIZE - 1);
 	iowrite8((u8) idx, ioaddr + CamAddr);
 	for (i = 0; i < 6; i++, addr++)
 		iowrite8(*addr, ioaddr + MulticastFilter0 + i);
 	udelay(10);
 	wmb();
 	iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);
 	udelay(10);
 	iowrite8(0, ioaddr + CamCon);
 }
 /**
  * rhine_set_vlan_cam - set CAM VLAN filters
  * @ioaddr: register block of this Rhine
  * @idx: VLAN CAM index [0..VCAM_SIZE-1]
  * @addr: VLAN ID (2 bytes)
  *
  * Load addresses into VLAN filters.
  */
 static void rhine_set_vlan_cam(void __iomem *ioaddr, int idx, u8 *addr)
 {
 	iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);
 	wmb();
 	/* Paranoid -- idx out of range should never happen */
 	idx &= (VCAM_SIZE - 1);
 	iowrite8((u8) idx, ioaddr + CamAddr);
 	iowrite16(*((u16 *) addr), ioaddr + MulticastFilter0 + 6);
 	udelay(10);
 	wmb();
 	iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);
 	udelay(10);
 	iowrite8(0, ioaddr + CamCon);
 }
 /**
  * rhine_set_cam_mask - set multicast CAM mask
  * @ioaddr: register block of this Rhine
  * @mask: multicast CAM mask
  *
  * Mask sets multicast filters active/inactive.
  */
 static void rhine_set_cam_mask(void __iomem *ioaddr, u32 mask)
 {
 	iowrite8(CAMC_CAMEN, ioaddr + CamCon);
 	wmb();
 	/* write mask */
 	iowrite32(mask, ioaddr + CamMask);
 	/* disable CAMEN */
 	iowrite8(0, ioaddr + CamCon);
 }
 /**
  * rhine_set_vlan_cam_mask - set VLAN CAM mask
  * @ioaddr: register block of this Rhine
  * @mask: VLAN CAM mask
  *
  * Mask sets VLAN filters active/inactive.
  */
 static void rhine_set_vlan_cam_mask(void __iomem *ioaddr, u32 mask)
 {
 	iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);
 	wmb();
 	/* write mask */
 	iowrite32(mask, ioaddr + CamMask);
 	/* disable CAMEN */
 	iowrite8(0, ioaddr + CamCon);
 }
 /**
  * rhine_init_cam_filter - initialize CAM filters
  * @dev: network device
  *
  * Initialize (disable) hardware VLAN and multicast support on this
  * Rhine.
  */
 static void rhine_init_cam_filter(struct net_device *dev)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	void __iomem *ioaddr = rp->base;
 	/* Disable all CAMs */
 	rhine_set_vlan_cam_mask(ioaddr, 0);
 	rhine_set_cam_mask(ioaddr, 0);
 	/* disable hardware VLAN support */
 	BYTE_REG_BITS_ON(TCR_PQEN, ioaddr + TxConfig);
 	BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1);
 }
 /**
  * rhine_update_vcam - update VLAN CAM filters
  * @rp: rhine_private data of this Rhine
  *
  * Update VLAN CAM filters to match configuration change.
  */
 static void rhine_update_vcam(struct net_device *dev)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	void __iomem *ioaddr = rp->base;
 	u16 vid;
 	u32 vCAMmask = 0;	/* 32 vCAMs (6105M and better) */
 	unsigned int i = 0;
 	for_each_set_bit(vid, rp->active_vlans, VLAN_N_VID) {
 		rhine_set_vlan_cam(ioaddr, i, (u8 *)&vid);
 		vCAMmask |= 1 << i;
 		if (++i >= VCAM_SIZE)
 			break;
 	}
 	rhine_set_vlan_cam_mask(ioaddr, vCAMmask);
 }
 static void rhine_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	spin_lock_irq(&rp->lock);
 	set_bit(vid, rp->active_vlans);
 	rhine_update_vcam(dev);
 	spin_unlock_irq(&rp->lock);
 }
 static void rhine_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	spin_lock_irq(&rp->lock);
 	clear_bit(vid, rp->active_vlans);
 	rhine_update_vcam(dev);
 	spin_unlock_irq(&rp->lock);
 }
 static void init_registers(struct net_device *dev)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	void __iomem *ioaddr = rp->base;
 	int i;
 	for (i = 0; i < 6; i++)
 		iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
 	/* Initialize other registers. */
 	iowrite16(0x0006, ioaddr + PCIBusConfig);	/* Tune configuration??? */
 	/* Configure initial FIFO thresholds. */
 	iowrite8(0x20, ioaddr + TxConfig);
 	rp->tx_thresh = 0x20;
 	rp->rx_thresh = 0x60;		/* Written in rhine_set_rx_mode(). */
 	iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr);
 	iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr);
 	rhine_set_rx_mode(dev);
 	if (rp->pdev->revision >= VT6105M)
 		rhine_init_cam_filter(dev);
 	napi_enable(&rp->napi);
 	/* Enable interrupts by setting the interrupt mask. */
 	iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
 	       IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
 	       IntrTxDone | IntrTxError | IntrTxUnderrun |
 	       IntrPCIErr | IntrStatsMax | IntrLinkChange,
 	       ioaddr + IntrEnable);
 	iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8),
 	       ioaddr + ChipCmd);
 	rhine_check_media(dev, 1);
 }
 /* Enable MII link status auto-polling (required for IntrLinkChange) */
 static void rhine_enable_linkmon(void __iomem *ioaddr)
 {
 	iowrite8(0, ioaddr + MIICmd);
 	iowrite8(MII_BMSR, ioaddr + MIIRegAddr);
 	iowrite8(0x80, ioaddr + MIICmd);
 	RHINE_WAIT_FOR((ioread8(ioaddr + MIIRegAddr) & 0x20));
 	iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr);
 }
 /* Disable MII link status auto-polling (required for MDIO access) */
 static void rhine_disable_linkmon(void __iomem *ioaddr, u32 quirks)
 {
 	iowrite8(0, ioaddr + MIICmd);
 	if (quirks & rqRhineI) {
 		iowrite8(0x01, ioaddr + MIIRegAddr);	// MII_BMSR
 		/* Can be called from ISR. Evil. */
 		mdelay(1);
 		/* 0x80 must be set immediately before turning it off */
 		iowrite8(0x80, ioaddr + MIICmd);
 		RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x20);
 		/* Heh. Now clear 0x80 again. */
 		iowrite8(0, ioaddr + MIICmd);
 	}
 	else
 		RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x80);
 }
 /* Read and write over the MII Management Data I/O (MDIO) interface. */
 static int mdio_read(struct net_device *dev, int phy_id, int regnum)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	void __iomem *ioaddr = rp->base;
 	int result;
 	rhine_disable_linkmon(ioaddr, rp->quirks);
 	/* rhine_disable_linkmon already cleared MIICmd */
 	iowrite8(phy_id, ioaddr + MIIPhyAddr);
 	iowrite8(regnum, ioaddr + MIIRegAddr);
 	iowrite8(0x40, ioaddr + MIICmd);		/* Trigger read */
 	RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x40));
 	result = ioread16(ioaddr + MIIData);
 	rhine_enable_linkmon(ioaddr);
 	return result;
 }
 static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	void __iomem *ioaddr = rp->base;
 	rhine_disable_linkmon(ioaddr, rp->quirks);
 	/* rhine_disable_linkmon already cleared MIICmd */
 	iowrite8(phy_id, ioaddr + MIIPhyAddr);
 	iowrite8(regnum, ioaddr + MIIRegAddr);
 	iowrite16(value, ioaddr + MIIData);
 	iowrite8(0x20, ioaddr + MIICmd);		/* Trigger write */
 	RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x20));
 	rhine_enable_linkmon(ioaddr);
 }
 static int rhine_open(struct net_device *dev)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	void __iomem *ioaddr = rp->base;
 	int rc;
 	rc = request_irq(rp->pdev->irq, rhine_interrupt, IRQF_SHARED, dev->name,
 			dev);
 	if (rc)
 		return rc;
 	if (debug > 1)
 		netdev_dbg(dev, "%s() irq %d\n", __func__, rp->pdev->irq);
 	rc = alloc_ring(dev);
 	if (rc) {
 		free_irq(rp->pdev->irq, dev);
 		return rc;
 	}
 	alloc_rbufs(dev);
 	alloc_tbufs(dev);
 	rhine_chip_reset(dev);
 	init_registers(dev);
 	if (debug > 2)
 		netdev_dbg(dev, "%s() Done - status %04x MII status: %04x\n",
 			   __func__, ioread16(ioaddr + ChipCmd),
 			   mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
 	netif_start_queue(dev);
 	return 0;
 }
 static void rhine_reset_task(struct work_struct *work)
 {
 	struct rhine_private *rp = container_of(work, struct rhine_private,
 						reset_task);
 	struct net_device *dev = rp->dev;
 	/* protect against concurrent rx interrupts */
 	disable_irq(rp->pdev->irq);
 	napi_disable(&rp->napi);
 	spin_lock_bh(&rp->lock);
 	/* clear all descriptors */
 	free_tbufs(dev);
 	free_rbufs(dev);
 	alloc_tbufs(dev);
 	alloc_rbufs(dev);
 	/* Reinitialize the hardware. */
 	rhine_chip_reset(dev);
 	init_registers(dev);
 	spin_unlock_bh(&rp->lock);
 	enable_irq(rp->pdev->irq);
 	dev->trans_start = jiffies; /* prevent tx timeout */
 	dev->stats.tx_errors++;
 	netif_wake_queue(dev);
 }
 static void rhine_tx_timeout(struct net_device *dev)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	void __iomem *ioaddr = rp->base;
 	netdev_warn(dev, "Transmit timed out, status %04x, PHY status %04x, resetting...\n",
 		    ioread16(ioaddr + IntrStatus),
 		    mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
 	schedule_work(&rp->reset_task);
 }
 static netdev_tx_t rhine_start_tx(struct sk_buff *skb,
 				  struct net_device *dev)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	void __iomem *ioaddr = rp->base;
 	unsigned entry;
 	unsigned long flags;
 	/* Caution: the write order is important here, set the field
 	   with the "ownership" bits last. */
 	/* Calculate the next Tx descriptor entry. */
 	entry = rp->cur_tx % TX_RING_SIZE;
 	if (skb_padto(skb, ETH_ZLEN))
 		return NETDEV_TX_OK;
 	rp->tx_skbuff[entry] = skb;
 	if ((rp->quirks & rqRhineI) &&
 	    (((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_PARTIAL)) {
 		/* Must use alignment buffer. */
 		if (skb->len > PKT_BUF_SZ) {
 			/* packet too long, drop it */
 			dev_kfree_skb(skb);
 			rp->tx_skbuff[entry] = NULL;
 			dev->stats.tx_dropped++;
 			return NETDEV_TX_OK;
 		}
 		/* Padding is not copied and so must be redone. */
 		skb_copy_and_csum_dev(skb, rp->tx_buf[entry]);
 		if (skb->len < ETH_ZLEN)
 			memset(rp->tx_buf[entry] + skb->len, 0,
 			       ETH_ZLEN - skb->len);
 		rp->tx_skbuff_dma[entry] = 0;
 		rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma +
 						      (rp->tx_buf[entry] -
 						       rp->tx_bufs));
 	} else {
 		rp->tx_skbuff_dma[entry] =
 			pci_map_single(rp->pdev, skb->data, skb->len,
 				       PCI_DMA_TODEVICE);
 		rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]);
 	}
 	rp->tx_ring[entry].desc_length =
 		cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
 	if (unlikely(vlan_tx_tag_present(skb))) {
 		rp->tx_ring[entry].tx_status = cpu_to_le32((vlan_tx_tag_get(skb)) << 16);
 		/* request tagging */
 		rp->tx_ring[entry].desc_length |= cpu_to_le32(0x020000);
 	}
 	else
 		rp->tx_ring[entry].tx_status = 0;
 	/* lock eth irq */
 	spin_lock_irqsave(&rp->lock, flags);
 	wmb();
 	rp->tx_ring[entry].tx_status |= cpu_to_le32(DescOwn);
 	wmb();
 	rp->cur_tx++;
 	/* Non-x86 Todo: explicitly flush cache lines here. */
 	if (vlan_tx_tag_present(skb))
 		/* Tx queues are bits 7-0 (first Tx queue: bit 7) */
 		BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake);
 	/* Wake the potentially-idle transmit channel */
 	iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
 	       ioaddr + ChipCmd1);
 	IOSYNC;
 	if (rp->cur_tx == rp->dirty_tx + TX_QUEUE_LEN)
 		netif_stop_queue(dev);
 	spin_unlock_irqrestore(&rp->lock, flags);
 	if (debug > 4) {
 		netdev_dbg(dev, "Transmit frame #%d queued in slot %d\n",
 			   rp->cur_tx-1, entry);
 	}
 	return NETDEV_TX_OK;
 }
 /* The interrupt handler does all of the Rx thread work and cleans up
    after the Tx thread. */
 static irqreturn_t rhine_interrupt(int irq, void *dev_instance)
 {
 	struct net_device *dev = dev_instance;
 	struct rhine_private *rp = netdev_priv(dev);
 	void __iomem *ioaddr = rp->base;
 	u32 intr_status;
 	int boguscnt = max_interrupt_work;
 	int handled = 0;
 	while ((intr_status = get_intr_status(dev))) {
 		handled = 1;
 		/* Acknowledge all of the current interrupt sources ASAP. */
 		if (intr_status & IntrTxDescRace)
 			iowrite8(0x08, ioaddr + IntrStatus2);
 		iowrite16(intr_status & 0xffff, ioaddr + IntrStatus);
 		IOSYNC;
 		if (debug > 4)
 			netdev_dbg(dev, "Interrupt, status %08x\n",
 				   intr_status);
 		if (intr_status & (IntrRxDone | IntrRxErr | IntrRxDropped |
 				   IntrRxWakeUp | IntrRxEmpty | IntrRxNoBuf)) {
 			iowrite16(IntrTxAborted |
 				  IntrTxDone | IntrTxError | IntrTxUnderrun |
 				  IntrPCIErr | IntrStatsMax | IntrLinkChange,
 				  ioaddr + IntrEnable);
 			napi_schedule(&rp->napi);
 		}
 		if (intr_status & (IntrTxErrSummary | IntrTxDone)) {
 			if (intr_status & IntrTxErrSummary) {
 				/* Avoid scavenging before Tx engine turned off */
 				RHINE_WAIT_FOR(!(ioread8(ioaddr+ChipCmd) & CmdTxOn));
 				if (debug > 2 &&
 				    ioread8(ioaddr+ChipCmd) & CmdTxOn)
 					netdev_warn(dev,
 						    "%s: Tx engine still on\n",
 						    __func__);
 			}
 			rhine_tx(dev);
 		}
 		/* Abnormal error summary/uncommon events handlers. */
 		if (intr_status & (IntrPCIErr | IntrLinkChange |
 				   IntrStatsMax | IntrTxError | IntrTxAborted |
 				   IntrTxUnderrun | IntrTxDescRace))
 			rhine_error(dev, intr_status);
 		if (--boguscnt < 0) {
 			netdev_warn(dev, "Too much work at interrupt, status=%#08x\n",
 				    intr_status);
 			break;
 		}
 	}
 	if (debug > 3)
 		netdev_dbg(dev, "exiting interrupt, status=%08x\n",
 			   ioread16(ioaddr + IntrStatus));
 	return IRQ_RETVAL(handled);
 }
 /* This routine is logically part of the interrupt handler, but isolated
    for clarity. */
 static void rhine_tx(struct net_device *dev)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	int txstatus = 0, entry = rp->dirty_tx % TX_RING_SIZE;
 	spin_lock(&rp->lock);
 	/* find and cleanup dirty tx descriptors */
 	while (rp->dirty_tx != rp->cur_tx) {
 		txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status);
 		if (debug > 6)
 			netdev_dbg(dev, "Tx scavenge %d status %08x\n",
 				   entry, txstatus);
 		if (txstatus & DescOwn)
 			break;
 		if (txstatus & 0x8000) {
 			if (debug > 1)
 				netdev_dbg(dev, "Transmit error, Tx status %08x\n",
 					   txstatus);
 			dev->stats.tx_errors++;
 			if (txstatus & 0x0400)
 				dev->stats.tx_carrier_errors++;
 			if (txstatus & 0x0200)
 				dev->stats.tx_window_errors++;
 			if (txstatus & 0x0100)
 				dev->stats.tx_aborted_errors++;
 			if (txstatus & 0x0080)
 				dev->stats.tx_heartbeat_errors++;
 			if (((rp->quirks & rqRhineI) && txstatus & 0x0002) ||
 			    (txstatus & 0x0800) || (txstatus & 0x1000)) {
 				dev->stats.tx_fifo_errors++;
 				rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
 				break; /* Keep the skb - we try again */
 			}
 			/* Transmitter restarted in 'abnormal' handler. */
 		} else {
 			if (rp->quirks & rqRhineI)
 				dev->stats.collisions += (txstatus >> 3) & 0x0F;
 			else
 				dev->stats.collisions += txstatus & 0x0F;
 			if (debug > 6)
 				netdev_dbg(dev, "collisions: %1.1x:%1.1x\n",
 					   (txstatus >> 3) & 0xF,
 					   txstatus & 0xF);
 			dev->stats.tx_bytes += rp->tx_skbuff[entry]->len;
 			dev->stats.tx_packets++;
 		}
 		/* Free the original skb. */
 		if (rp->tx_skbuff_dma[entry]) {
 			pci_unmap_single(rp->pdev,
 					 rp->tx_skbuff_dma[entry],
 					 rp->tx_skbuff[entry]->len,
 					 PCI_DMA_TODEVICE);
 		}
 		dev_kfree_skb_irq(rp->tx_skbuff[entry]);
 		rp->tx_skbuff[entry] = NULL;
 		entry = (++rp->dirty_tx) % TX_RING_SIZE;
 	}
 	if ((rp->cur_tx - rp->dirty_tx) < TX_QUEUE_LEN - 4)
 		netif_wake_queue(dev);
 	spin_unlock(&rp->lock);
 }
 /**
  * rhine_get_vlan_tci - extract TCI from Rx data buffer
  * @skb: pointer to sk_buff
  * @data_size: used data area of the buffer including CRC
  *
  * If hardware VLAN tag extraction is enabled and the chip indicates a 802.1Q
  * packet, the extracted 802.1Q header (2 bytes TPID + 2 bytes TCI) is 4-byte
  * aligned following the CRC.
  */
 static inline u16 rhine_get_vlan_tci(struct sk_buff *skb, int data_size)
 {
 	u8 *trailer = (u8 *)skb->data + ((data_size + 3) & ~3) + 2;
 	return be16_to_cpup((__be16 *)trailer);
 }
 /* Process up to limit frames from receive ring */
 static int rhine_rx(struct net_device *dev, int limit)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	int count;
 	int entry = rp->cur_rx % RX_RING_SIZE;
 	if (debug > 4) {
 		netdev_dbg(dev, "%s(), entry %d status %08x\n",
 			   __func__, entry,
 			   le32_to_cpu(rp->rx_head_desc->rx_status));
 	}
 	/* If EOP is set on the next entry, it's a new packet. Send it up. */
 	for (count = 0; count < limit; ++count) {
 		struct rx_desc *desc = rp->rx_head_desc;
 		u32 desc_status = le32_to_cpu(desc->rx_status);
 		u32 desc_length = le32_to_cpu(desc->desc_length);
 		int data_size = desc_status >> 16;
 		if (desc_status & DescOwn)
 			break;
 		if (debug > 4)
 			netdev_dbg(dev, "%s() status is %08x\n",
 				   __func__, desc_status);
 		if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) {
 			if ((desc_status & RxWholePkt) != RxWholePkt) {
 				netdev_warn(dev,
 	"Oversized Ethernet frame spanned multiple buffers, "
 	"entry %#x length %d status %08x!\n",
 					    entry, data_size,
 					    desc_status);
 				netdev_warn(dev,
 					    "Oversized Ethernet frame %p vs %p\n",
 					    rp->rx_head_desc,
 					    &rp->rx_ring[entry]);
 				dev->stats.rx_length_errors++;
 			} else if (desc_status & RxErr) {
 				/* There was a error. */
 				if (debug > 2)
 					netdev_dbg(dev, "%s() Rx error was %08x\n",
 						   __func__, desc_status);
 				dev->stats.rx_errors++;
 				if (desc_status & 0x0030)
 					dev->stats.rx_length_errors++;
 				if (desc_status & 0x0048)
 					dev->stats.rx_fifo_errors++;
 				if (desc_status & 0x0004)
 					dev->stats.rx_frame_errors++;
 				if (desc_status & 0x0002) {
 					/* this can also be updated outside the interrupt handler */
 					spin_lock(&rp->lock);
 					dev->stats.rx_crc_errors++;
 					spin_unlock(&rp->lock);
 				}
 			}
 		} else {
 			struct sk_buff *skb = NULL;
 			/* Length should omit the CRC */
 			int pkt_len = data_size - 4;
 			u16 vlan_tci = 0;
 			/* Check if the packet is long enough to accept without
 			   copying to a minimally-sized skbuff. */
 			if (pkt_len < rx_copybreak)
 				skb = netdev_alloc_skb_ip_align(dev, pkt_len);
 			if (skb) {
 				pci_dma_sync_single_for_cpu(rp->pdev,
 							    rp->rx_skbuff_dma[entry],
 							    rp->rx_buf_sz,
 							    PCI_DMA_FROMDEVICE);
 				skb_copy_to_linear_data(skb,
 						 rp->rx_skbuff[entry]->data,
 						 pkt_len);
 				skb_put(skb, pkt_len);
 				pci_dma_sync_single_for_device(rp->pdev,
 							       rp->rx_skbuff_dma[entry],
 							       rp->rx_buf_sz,
 							       PCI_DMA_FROMDEVICE);
 			} else {
 				skb = rp->rx_skbuff[entry];
 				if (skb == NULL) {
 					netdev_err(dev, "Inconsistent Rx descriptor chain\n");
 					break;
 				}
 				rp->rx_skbuff[entry] = NULL;
 				skb_put(skb, pkt_len);
 				pci_unmap_single(rp->pdev,
 						 rp->rx_skbuff_dma[entry],
 						 rp->rx_buf_sz,
 						 PCI_DMA_FROMDEVICE);
 			}
 			if (unlikely(desc_length & DescTag))
 				vlan_tci = rhine_get_vlan_tci(skb, data_size);
 			skb->protocol = eth_type_trans(skb, dev);
 			if (unlikely(desc_length & DescTag))
 				__vlan_hwaccel_put_tag(skb, vlan_tci);
 			netif_receive_skb(skb);
 			dev->stats.rx_bytes += pkt_len;
 			dev->stats.rx_packets++;
 		}
 		entry = (++rp->cur_rx) % RX_RING_SIZE;
 		rp->rx_head_desc = &rp->rx_ring[entry];
 	}
 	/* Refill the Rx ring buffers. */
 	for (; rp->cur_rx - rp->dirty_rx > 0; rp->dirty_rx++) {
 		struct sk_buff *skb;
 		entry = rp->dirty_rx % RX_RING_SIZE;
 		if (rp->rx_skbuff[entry] == NULL) {
 			skb = netdev_alloc_skb(dev, rp->rx_buf_sz);
 			rp->rx_skbuff[entry] = skb;
 			if (skb == NULL)
 				break;	/* Better luck next round. */
 			skb->dev = dev;	/* Mark as being used by this device. */
 			rp->rx_skbuff_dma[entry] =
 				pci_map_single(rp->pdev, skb->data,
 					       rp->rx_buf_sz,
 					       PCI_DMA_FROMDEVICE);
 			rp->rx_ring[entry].addr = cpu_to_le32(rp->rx_skbuff_dma[entry]);
 		}
 		rp->rx_ring[entry].rx_status = cpu_to_le32(DescOwn);
 	}
 	return count;
 }
 /*
  * Clears the "tally counters" for CRC errors and missed frames(?).
  * It has been reported that some chips need a write of 0 to clear
  * these, for others the counters are set to 1 when written to and
  * instead cleared when read. So we clear them both ways ...
  */
 static inline void clear_tally_counters(void __iomem *ioaddr)
 {
 	iowrite32(0, ioaddr + RxMissed);
 	ioread16(ioaddr + RxCRCErrs);
 	ioread16(ioaddr + RxMissed);
 }
 static void rhine_restart_tx(struct net_device *dev) {
 	struct rhine_private *rp = netdev_priv(dev);
 	void __iomem *ioaddr = rp->base;
 	int entry = rp->dirty_tx % TX_RING_SIZE;
 	u32 intr_status;
 	/*
 	 * If new errors occurred, we need to sort them out before doing Tx.
 	 * In that case the ISR will be back here RSN anyway.
 	 */
 	intr_status = get_intr_status(dev);
 	if ((intr_status & IntrTxErrSummary) == 0) {
 		/* We know better than the chip where it should continue. */
 		iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc),
 		       ioaddr + TxRingPtr);
 		iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn,
 		       ioaddr + ChipCmd);
 		if (rp->tx_ring[entry].desc_length & cpu_to_le32(0x020000))
 			/* Tx queues are bits 7-0 (first Tx queue: bit 7) */
 			BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake);
 		iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
 		       ioaddr + ChipCmd1);
 		IOSYNC;
 	}
 	else {
 		/* This should never happen */
 		if (debug > 1)
 			netdev_warn(dev, "%s() Another error occurred %08x\n",
 				   __func__, intr_status);
 	}
 }
 static void rhine_error(struct net_device *dev, int intr_status)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	void __iomem *ioaddr = rp->base;
 	spin_lock(&rp->lock);
 	if (intr_status & IntrLinkChange)
 		rhine_check_media(dev, 0);
 	if (intr_status & IntrStatsMax) {
 		dev->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
 		dev->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
 		clear_tally_counters(ioaddr);
 	}
 	if (intr_status & IntrTxAborted) {
 		if (debug > 1)
 			netdev_info(dev, "Abort %08x, frame dropped\n",
 				    intr_status);
 	}
 	if (intr_status & IntrTxUnderrun) {
 		if (rp->tx_thresh < 0xE0)
 			BYTE_REG_BITS_SET((rp->tx_thresh += 0x20), 0x80, ioaddr + TxConfig);
 		if (debug > 1)
 			netdev_info(dev, "Transmitter underrun, Tx threshold now %02x\n",
 				    rp->tx_thresh);
 	}
 	if (intr_status & IntrTxDescRace) {
 		if (debug > 2)
 			netdev_info(dev, "Tx descriptor write-back race\n");
 	}
 	if ((intr_status & IntrTxError) &&
 	    (intr_status & (IntrTxAborted |
 	     IntrTxUnderrun | IntrTxDescRace)) == 0) {
 		if (rp->tx_thresh < 0xE0) {
 			BYTE_REG_BITS_SET((rp->tx_thresh += 0x20), 0x80, ioaddr + TxConfig);
 		}
 		if (debug > 1)
 			netdev_info(dev, "Unspecified error. Tx threshold now %02x\n",
 				    rp->tx_thresh);
 	}
 	if (intr_status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace |
 			   IntrTxError))
 		rhine_restart_tx(dev);
 	if (intr_status & ~(IntrLinkChange | IntrStatsMax | IntrTxUnderrun |
 			    IntrTxError | IntrTxAborted | IntrNormalSummary |
 			    IntrTxDescRace)) {
 		if (debug > 1)
 			netdev_err(dev, "Something Wicked happened! %08x\n",
 				   intr_status);
 	}
 	spin_unlock(&rp->lock);
 }
 static struct net_device_stats *rhine_get_stats(struct net_device *dev)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	void __iomem *ioaddr = rp->base;
 	unsigned long flags;
 	spin_lock_irqsave(&rp->lock, flags);
 	dev->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
 	dev->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
 	clear_tally_counters(ioaddr);
 	spin_unlock_irqrestore(&rp->lock, flags);
 	return &dev->stats;
 }
 static void rhine_set_rx_mode(struct net_device *dev)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	void __iomem *ioaddr = rp->base;
 	u32 mc_filter[2];	/* Multicast hash filter */
 	u8 rx_mode = 0x0C;	/* Note: 0x02=accept runt, 0x01=accept errs */
 	struct netdev_hw_addr *ha;
 	if (dev->flags & IFF_PROMISC) {		/* Set promiscuous. */
 		rx_mode = 0x1C;
 		iowrite32(0xffffffff, ioaddr + MulticastFilter0);
 		iowrite32(0xffffffff, ioaddr + MulticastFilter1);
 	} else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
 		   (dev->flags & IFF_ALLMULTI)) {
 		/* Too many to match, or accept all multicasts. */
 		iowrite32(0xffffffff, ioaddr + MulticastFilter0);
 		iowrite32(0xffffffff, ioaddr + MulticastFilter1);
 	} else if (rp->pdev->revision >= VT6105M) {
 		int i = 0;
 		u32 mCAMmask = 0;	/* 32 mCAMs (6105M and better) */
 		netdev_for_each_mc_addr(ha, dev) {
 			if (i == MCAM_SIZE)
 				break;
 			rhine_set_cam(ioaddr, i, ha->addr);
 			mCAMmask |= 1 << i;
 			i++;
 		}
 		rhine_set_cam_mask(ioaddr, mCAMmask);
 	} else {
 		memset(mc_filter, 0, sizeof(mc_filter));
 		netdev_for_each_mc_addr(ha, dev) {
 			int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
 			mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
 		}
 		iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
 		iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
 	}
 	/* enable/disable VLAN receive filtering */
 	if (rp->pdev->revision >= VT6105M) {
 		if (dev->flags & IFF_PROMISC)
 			BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1);
 		else
 			BYTE_REG_BITS_ON(BCR1_VIDFR, ioaddr + PCIBusConfig1);
 	}
 	BYTE_REG_BITS_ON(rx_mode, ioaddr + RxConfig);
 }
 static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	strcpy(info->driver, DRV_NAME);
 	strcpy(info->version, DRV_VERSION);
 	strcpy(info->bus_info, pci_name(rp->pdev));
 }
 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	int rc;
 	spin_lock_irq(&rp->lock);
 	rc = mii_ethtool_gset(&rp->mii_if, cmd);
 	spin_unlock_irq(&rp->lock);
 	return rc;
 }
 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	int rc;
 	spin_lock_irq(&rp->lock);
 	rc = mii_ethtool_sset(&rp->mii_if, cmd);
 	spin_unlock_irq(&rp->lock);
 	rhine_set_carrier(&rp->mii_if);
 	return rc;
 }
 static int netdev_nway_reset(struct net_device *dev)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	return mii_nway_restart(&rp->mii_if);
 }
 static u32 netdev_get_link(struct net_device *dev)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	return mii_link_ok(&rp->mii_if);
 }
 static u32 netdev_get_msglevel(struct net_device *dev)
 {
 	return debug;
 }
 static void netdev_set_msglevel(struct net_device *dev, u32 value)
 {
 	debug = value;
 }
 static void rhine_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	if (!(rp->quirks & rqWOL))
 		return;
 	spin_lock_irq(&rp->lock);
 	wol->supported = WAKE_PHY | WAKE_MAGIC |
 			 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;	/* Untested */
 	wol->wolopts = rp->wolopts;
 	spin_unlock_irq(&rp->lock);
 }
 static int rhine_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	u32 support = WAKE_PHY | WAKE_MAGIC |
 		      WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;	/* Untested */
 	if (!(rp->quirks & rqWOL))
 		return -EINVAL;
 	if (wol->wolopts & ~support)
 		return -EINVAL;
 	spin_lock_irq(&rp->lock);
 	rp->wolopts = wol->wolopts;
 	spin_unlock_irq(&rp->lock);
 	return 0;
 }
 static const struct ethtool_ops netdev_ethtool_ops = {
 	.get_drvinfo		= netdev_get_drvinfo,
 	.get_settings		= netdev_get_settings,
 	.set_settings		= netdev_set_settings,
 	.nway_reset		= netdev_nway_reset,
 	.get_link		= netdev_get_link,
 	.get_msglevel		= netdev_get_msglevel,
 	.set_msglevel		= netdev_set_msglevel,
 	.get_wol		= rhine_get_wol,
 	.set_wol		= rhine_set_wol,
 };
 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	int rc;
 	if (!netif_running(dev))
 		return -EINVAL;
 	spin_lock_irq(&rp->lock);
 	rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL);
 	spin_unlock_irq(&rp->lock);
 	rhine_set_carrier(&rp->mii_if);
 	return rc;
 }
 static int rhine_close(struct net_device *dev)
 {
 	struct rhine_private *rp = netdev_priv(dev);
 	void __iomem *ioaddr = rp->base;
 	napi_disable(&rp->napi);
 	cancel_work_sync(&rp->reset_task);
 	netif_stop_queue(dev);
 	spin_lock_irq(&rp->lock);
 	if (debug > 1)
 		netdev_dbg(dev, "Shutting down ethercard, status was %04x\n",
 			   ioread16(ioaddr + ChipCmd));
 	/* Switch to loopback mode to avoid hardware races. */
 	iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig);
 	/* Disable interrupts by clearing the interrupt mask. */
 	iowrite16(0x0000, ioaddr + IntrEnable);
 	/* Stop the chip's Tx and Rx processes. */
 	iowrite16(CmdStop, ioaddr + ChipCmd);
 	spin_unlock_irq(&rp->lock);
 	free_irq(rp->pdev->irq, dev);
 	free_rbufs(dev);
 	free_tbufs(dev);
 	free_ring(dev);
 	return 0;
 }
 static void __devexit rhine_remove_one(struct pci_dev *pdev)
 {
 	struct net_device *dev = pci_get_drvdata(pdev);
 	struct rhine_private *rp = netdev_priv(dev);
 	unregister_netdev(dev);
 	pci_iounmap(pdev, rp->base);
 	pci_release_regions(pdev);
 	free_netdev(dev);
 	pci_disable_device(pdev);
 	pci_set_drvdata(pdev, NULL);
 }
 static void rhine_shutdown (struct pci_dev *pdev)
 {
 	struct net_device *dev = pci_get_drvdata(pdev);
 	struct rhine_private *rp = netdev_priv(dev);
 	void __iomem *ioaddr = rp->base;
 	if (!(rp->quirks & rqWOL))
 		return; /* Nothing to do for non-WOL adapters */
 	rhine_power_init(dev);
 	/* Make sure we use pattern 0, 1 and not 4, 5 */
 	if (rp->quirks & rq6patterns)
 		iowrite8(0x04, ioaddr + WOLcgClr);
 	if (rp->wolopts & WAKE_MAGIC) {
 		iowrite8(WOLmagic, ioaddr + WOLcrSet);
 		/*
 		 * Turn EEPROM-controlled wake-up back on -- some hardware may
 		 * not cooperate otherwise.
 		 */
 		iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA);
 	}
 	if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST))
 		iowrite8(WOLbmcast, ioaddr + WOLcgSet);
 	if (rp->wolopts & WAKE_PHY)
 		iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet);
 	if (rp->wolopts & WAKE_UCAST)
 		iowrite8(WOLucast, ioaddr + WOLcrSet);
 	if (rp->wolopts) {
 		/* Enable legacy WOL (for old motherboards) */
 		iowrite8(0x01, ioaddr + PwcfgSet);
 		iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW);
 	}
 	/* Hit power state D3 (sleep) */
 	if (!avoid_D3)
 		iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW);
 	/* TODO: Check use of pci_enable_wake() */
 }
 #ifdef CONFIG_PM
 static int rhine_suspend(struct pci_dev *pdev, pm_message_t state)
 {
 	struct net_device *dev = pci_get_drvdata(pdev);
 	struct rhine_private *rp = netdev_priv(dev);
 	unsigned long flags;
 	if (!netif_running(dev))
 		return 0;
 	napi_disable(&rp->napi);
 	netif_device_detach(dev);
 	pci_save_state(pdev);
 	spin_lock_irqsave(&rp->lock, flags);
 	rhine_shutdown(pdev);
 	spin_unlock_irqrestore(&rp->lock, flags);
 	free_irq(dev->irq, dev);
 	return 0;
 }
 static int rhine_resume(struct pci_dev *pdev)
 {
 	struct net_device *dev = pci_get_drvdata(pdev);
 	struct rhine_private *rp = netdev_priv(dev);
 	unsigned long flags;
 	int ret;
 	if (!netif_running(dev))
 		return 0;
 	if (request_irq(dev->irq, rhine_interrupt, IRQF_SHARED, dev->name, dev))
 		netdev_err(dev, "request_irq failed\n");
 	ret = pci_set_power_state(pdev, PCI_D0);
 	if (debug > 1)
 		netdev_info(dev, "Entering power state D0 %s (%d)\n",
 			    ret ? "failed" : "succeeded", ret);
 	pci_restore_state(pdev);
 	spin_lock_irqsave(&rp->lock, flags);
 #ifdef USE_MMIO
 	enable_mmio(rp->pioaddr, rp->quirks);
 #endif
 	rhine_power_init(dev);
 	free_tbufs(dev);
 	free_rbufs(dev);
 	alloc_tbufs(dev);
 	alloc_rbufs(dev);
 	init_registers(dev);
 	spin_unlock_irqrestore(&rp->lock, flags);
 	netif_device_attach(dev);
 	return 0;
 }
 #endif /* CONFIG_PM */
 static struct pci_driver rhine_driver = {
 	.name		= DRV_NAME,
 	.id_table	= rhine_pci_tbl,
 	.probe		= rhine_init_one,
 	.remove		= __devexit_p(rhine_remove_one),
 #ifdef CONFIG_PM
 	.suspend	= rhine_suspend,
 	.resume		= rhine_resume,
 #endif /* CONFIG_PM */
 	.shutdown =	rhine_shutdown,
 };
 static struct dmi_system_id __initdata rhine_dmi_table[] = {
 	{
 		.ident = "EPIA-M",
 		.matches = {
 			DMI_MATCH(DMI_BIOS_VENDOR, "Award Software International, Inc."),
 			DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
 		},
 	},
 	{
 		.ident = "KV7",
 		.matches = {
 			DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"),
 			DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
 		},
 	},
 	{ NULL }
 };
 static int __init rhine_init(void)
 {
 /* when a module, this is printed whether or not devices are found in probe */
 #ifdef MODULE
 	pr_info("%s\n", version);
 #endif
 	if (dmi_check_system(rhine_dmi_table)) {
 		/* these BIOSes fail at PXE boot if chip is in D3 */
 		avoid_D3 = 1;
 		pr_warn("Broken BIOS detected, avoid_D3 enabled\n");
 	}
 	else if (avoid_D3)
 		pr_info("avoid_D3 set\n");
 	return pci_register_driver(&rhine_driver);
 }
 static void __exit rhine_cleanup(void)
 {
 	pci_unregister_driver(&rhine_driver);
 }
 module_init(rhine_init);
 module_exit(rhine_cleanup);