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Commit 494336f3a6eabeede8ce07b73f5023ff4f7c745d

Authored by Linus Walleij
1 parent d468bf9eca
Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch imx_3.14.28_1.0.0_ga

pinctrl: nomadik: mark GPIO lines used for IRQ 

When an IRQ is started on a GPIO line, mark this GPIO as IRQ in
the gpiolib so we can keep track of the usage centrally.

Cc: Enric Balletbo i Serra <eballetbo@gmail.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Showing 1 changed file with 5 additions and 0 deletions Inline Diff

drivers/pinctrl/pinctrl-nomadik.c
Diff comments   View file @ 494336f
1 /* 1 /*
2 * Generic GPIO driver for logic cells found in the Nomadik SoC 2 * Generic GPIO driver for logic cells found in the Nomadik SoC
3 * 3 *
4 * Copyright (C) 2008,2009 STMicroelectronics 4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> 5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> 6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org> 7 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org>
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 */ 12 */
13 #include <linux/kernel.h> 13 #include <linux/kernel.h>
14 #include <linux/module.h> 14 #include <linux/module.h>
15 #include <linux/init.h> 15 #include <linux/init.h>
16 #include <linux/device.h> 16 #include <linux/device.h>
17 #include <linux/platform_device.h> 17 #include <linux/platform_device.h>
18 #include <linux/io.h> 18 #include <linux/io.h>
19 #include <linux/clk.h> 19 #include <linux/clk.h>
20 #include <linux/err.h> 20 #include <linux/err.h>
21 #include <linux/gpio.h> 21 #include <linux/gpio.h>
22 #include <linux/spinlock.h> 22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h> 23 #include <linux/interrupt.h>
24 #include <linux/irq.h> 24 #include <linux/irq.h>
25 #include <linux/irqdomain.h> 25 #include <linux/irqdomain.h>
26 #include <linux/irqchip/chained_irq.h> 26 #include <linux/irqchip/chained_irq.h>
27 #include <linux/slab.h> 27 #include <linux/slab.h>
28 #include <linux/of_device.h> 28 #include <linux/of_device.h>
29 #include <linux/of_address.h> 29 #include <linux/of_address.h>
30 #include <linux/pinctrl/machine.h> 30 #include <linux/pinctrl/machine.h>
31 #include <linux/pinctrl/pinctrl.h> 31 #include <linux/pinctrl/pinctrl.h>
32 #include <linux/pinctrl/pinmux.h> 32 #include <linux/pinctrl/pinmux.h>
33 #include <linux/pinctrl/pinconf.h> 33 #include <linux/pinctrl/pinconf.h>
34 /* Since we request GPIOs from ourself */ 34 /* Since we request GPIOs from ourself */
35 #include <linux/pinctrl/consumer.h> 35 #include <linux/pinctrl/consumer.h>
36 #include <linux/platform_data/pinctrl-nomadik.h> 36 #include <linux/platform_data/pinctrl-nomadik.h>
37 #include "pinctrl-nomadik.h" 37 #include "pinctrl-nomadik.h"
38 #include "core.h" 38 #include "core.h"
39 39
40 /* 40 /*
41 * The GPIO module in the Nomadik family of Systems-on-Chip is an 41 * The GPIO module in the Nomadik family of Systems-on-Chip is an
42 * AMBA device, managing 32 pins and alternate functions. The logic block 42 * AMBA device, managing 32 pins and alternate functions. The logic block
43 * is currently used in the Nomadik and ux500. 43 * is currently used in the Nomadik and ux500.
44 * 44 *
45 * Symbols in this file are called "nmk_gpio" for "nomadik gpio" 45 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
46 */ 46 */
47 47
48 struct nmk_gpio_chip { 48 struct nmk_gpio_chip {
49 struct gpio_chip chip; 49 struct gpio_chip chip;
50 struct irq_domain *domain; 50 struct irq_domain *domain;
51 void __iomem *addr; 51 void __iomem *addr;
52 struct clk *clk; 52 struct clk *clk;
53 unsigned int bank; 53 unsigned int bank;
54 unsigned int parent_irq; 54 unsigned int parent_irq;
55 int secondary_parent_irq; 55 int secondary_parent_irq;
56 u32 (*get_secondary_status)(unsigned int bank); 56 u32 (*get_secondary_status)(unsigned int bank);
57 void (*set_ioforce)(bool enable); 57 void (*set_ioforce)(bool enable);
58 spinlock_t lock; 58 spinlock_t lock;
59 bool sleepmode; 59 bool sleepmode;
60 /* Keep track of configured edges */ 60 /* Keep track of configured edges */
61 u32 edge_rising; 61 u32 edge_rising;
62 u32 edge_falling; 62 u32 edge_falling;
63 u32 real_wake; 63 u32 real_wake;
64 u32 rwimsc; 64 u32 rwimsc;
65 u32 fwimsc; 65 u32 fwimsc;
66 u32 rimsc; 66 u32 rimsc;
67 u32 fimsc; 67 u32 fimsc;
68 u32 pull_up; 68 u32 pull_up;
69 u32 lowemi; 69 u32 lowemi;
70 }; 70 };
71 71
72 /** 72 /**
73 * struct nmk_pinctrl - state container for the Nomadik pin controller 73 * struct nmk_pinctrl - state container for the Nomadik pin controller
74 * @dev: containing device pointer 74 * @dev: containing device pointer
75 * @pctl: corresponding pin controller device 75 * @pctl: corresponding pin controller device
76 * @soc: SoC data for this specific chip 76 * @soc: SoC data for this specific chip
77 * @prcm_base: PRCM register range virtual base 77 * @prcm_base: PRCM register range virtual base
78 */ 78 */
79 struct nmk_pinctrl { 79 struct nmk_pinctrl {
80 struct device *dev; 80 struct device *dev;
81 struct pinctrl_dev *pctl; 81 struct pinctrl_dev *pctl;
82 const struct nmk_pinctrl_soc_data *soc; 82 const struct nmk_pinctrl_soc_data *soc;
83 void __iomem *prcm_base; 83 void __iomem *prcm_base;
84 }; 84 };
85 85
86 static struct nmk_gpio_chip * 86 static struct nmk_gpio_chip *
87 nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)]; 87 nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
88 88
89 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); 89 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
90 90
91 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) 91 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
92 92
93 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, 93 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
94 unsigned offset, int gpio_mode) 94 unsigned offset, int gpio_mode)
95 { 95 {
96 u32 bit = 1 << offset; 96 u32 bit = 1 << offset;
97 u32 afunc, bfunc; 97 u32 afunc, bfunc;
98 98
99 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; 99 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
100 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit; 100 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
101 if (gpio_mode & NMK_GPIO_ALT_A) 101 if (gpio_mode & NMK_GPIO_ALT_A)
102 afunc |= bit; 102 afunc |= bit;
103 if (gpio_mode & NMK_GPIO_ALT_B) 103 if (gpio_mode & NMK_GPIO_ALT_B)
104 bfunc |= bit; 104 bfunc |= bit;
105 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); 105 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
106 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); 106 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
107 } 107 }
108 108
109 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, 109 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
110 unsigned offset, enum nmk_gpio_slpm mode) 110 unsigned offset, enum nmk_gpio_slpm mode)
111 { 111 {
112 u32 bit = 1 << offset; 112 u32 bit = 1 << offset;
113 u32 slpm; 113 u32 slpm;
114 114
115 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); 115 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
116 if (mode == NMK_GPIO_SLPM_NOCHANGE) 116 if (mode == NMK_GPIO_SLPM_NOCHANGE)
117 slpm |= bit; 117 slpm |= bit;
118 else 118 else
119 slpm &= ~bit; 119 slpm &= ~bit;
120 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); 120 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
121 } 121 }
122 122
123 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, 123 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
124 unsigned offset, enum nmk_gpio_pull pull) 124 unsigned offset, enum nmk_gpio_pull pull)
125 { 125 {
126 u32 bit = 1 << offset; 126 u32 bit = 1 << offset;
127 u32 pdis; 127 u32 pdis;
128 128
129 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); 129 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
130 if (pull == NMK_GPIO_PULL_NONE) { 130 if (pull == NMK_GPIO_PULL_NONE) {
131 pdis |= bit; 131 pdis |= bit;
132 nmk_chip->pull_up &= ~bit; 132 nmk_chip->pull_up &= ~bit;
133 } else { 133 } else {
134 pdis &= ~bit; 134 pdis &= ~bit;
135 } 135 }
136 136
137 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); 137 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
138 138
139 if (pull == NMK_GPIO_PULL_UP) { 139 if (pull == NMK_GPIO_PULL_UP) {
140 nmk_chip->pull_up |= bit; 140 nmk_chip->pull_up |= bit;
141 writel(bit, nmk_chip->addr + NMK_GPIO_DATS); 141 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
142 } else if (pull == NMK_GPIO_PULL_DOWN) { 142 } else if (pull == NMK_GPIO_PULL_DOWN) {
143 nmk_chip->pull_up &= ~bit; 143 nmk_chip->pull_up &= ~bit;
144 writel(bit, nmk_chip->addr + NMK_GPIO_DATC); 144 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
145 } 145 }
146 } 146 }
147 147
148 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, 148 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
149 unsigned offset, bool lowemi) 149 unsigned offset, bool lowemi)
150 { 150 {
151 u32 bit = BIT(offset); 151 u32 bit = BIT(offset);
152 bool enabled = nmk_chip->lowemi & bit; 152 bool enabled = nmk_chip->lowemi & bit;
153 153
154 if (lowemi == enabled) 154 if (lowemi == enabled)
155 return; 155 return;
156 156
157 if (lowemi) 157 if (lowemi)
158 nmk_chip->lowemi |= bit; 158 nmk_chip->lowemi |= bit;
159 else 159 else
160 nmk_chip->lowemi &= ~bit; 160 nmk_chip->lowemi &= ~bit;
161 161
162 writel_relaxed(nmk_chip->lowemi, 162 writel_relaxed(nmk_chip->lowemi,
163 nmk_chip->addr + NMK_GPIO_LOWEMI); 163 nmk_chip->addr + NMK_GPIO_LOWEMI);
164 } 164 }
165 165
166 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, 166 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
167 unsigned offset) 167 unsigned offset)
168 { 168 {
169 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); 169 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
170 } 170 }
171 171
172 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, 172 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
173 unsigned offset, int val) 173 unsigned offset, int val)
174 { 174 {
175 if (val) 175 if (val)
176 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS); 176 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
177 else 177 else
178 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC); 178 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
179 } 179 }
180 180
181 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, 181 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
182 unsigned offset, int val) 182 unsigned offset, int val)
183 { 183 {
184 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); 184 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
185 __nmk_gpio_set_output(nmk_chip, offset, val); 185 __nmk_gpio_set_output(nmk_chip, offset, val);
186 } 186 }
187 187
188 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, 188 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
189 unsigned offset, int gpio_mode, 189 unsigned offset, int gpio_mode,
190 bool glitch) 190 bool glitch)
191 { 191 {
192 u32 rwimsc = nmk_chip->rwimsc; 192 u32 rwimsc = nmk_chip->rwimsc;
193 u32 fwimsc = nmk_chip->fwimsc; 193 u32 fwimsc = nmk_chip->fwimsc;
194 194
195 if (glitch && nmk_chip->set_ioforce) { 195 if (glitch && nmk_chip->set_ioforce) {
196 u32 bit = BIT(offset); 196 u32 bit = BIT(offset);
197 197
198 /* Prevent spurious wakeups */ 198 /* Prevent spurious wakeups */
199 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); 199 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
200 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); 200 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
201 201
202 nmk_chip->set_ioforce(true); 202 nmk_chip->set_ioforce(true);
203 } 203 }
204 204
205 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); 205 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
206 206
207 if (glitch && nmk_chip->set_ioforce) { 207 if (glitch && nmk_chip->set_ioforce) {
208 nmk_chip->set_ioforce(false); 208 nmk_chip->set_ioforce(false);
209 209
210 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); 210 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
211 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); 211 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
212 } 212 }
213 } 213 }
214 214
215 static void 215 static void
216 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) 216 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
217 { 217 {
218 u32 falling = nmk_chip->fimsc & BIT(offset); 218 u32 falling = nmk_chip->fimsc & BIT(offset);
219 u32 rising = nmk_chip->rimsc & BIT(offset); 219 u32 rising = nmk_chip->rimsc & BIT(offset);
220 int gpio = nmk_chip->chip.base + offset; 220 int gpio = nmk_chip->chip.base + offset;
221 int irq = irq_find_mapping(nmk_chip->domain, offset); 221 int irq = irq_find_mapping(nmk_chip->domain, offset);
222 struct irq_data *d = irq_get_irq_data(irq); 222 struct irq_data *d = irq_get_irq_data(irq);
223 223
224 if (!rising && !falling) 224 if (!rising && !falling)
225 return; 225 return;
226 226
227 if (!d || !irqd_irq_disabled(d)) 227 if (!d || !irqd_irq_disabled(d))
228 return; 228 return;
229 229
230 if (rising) { 230 if (rising) {
231 nmk_chip->rimsc &= ~BIT(offset); 231 nmk_chip->rimsc &= ~BIT(offset);
232 writel_relaxed(nmk_chip->rimsc, 232 writel_relaxed(nmk_chip->rimsc,
233 nmk_chip->addr + NMK_GPIO_RIMSC); 233 nmk_chip->addr + NMK_GPIO_RIMSC);
234 } 234 }
235 235
236 if (falling) { 236 if (falling) {
237 nmk_chip->fimsc &= ~BIT(offset); 237 nmk_chip->fimsc &= ~BIT(offset);
238 writel_relaxed(nmk_chip->fimsc, 238 writel_relaxed(nmk_chip->fimsc,
239 nmk_chip->addr + NMK_GPIO_FIMSC); 239 nmk_chip->addr + NMK_GPIO_FIMSC);
240 } 240 }
241 241
242 dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio); 242 dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
243 } 243 }
244 244
245 static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value) 245 static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value)
246 { 246 {
247 u32 val; 247 u32 val;
248 248
249 val = readl(reg); 249 val = readl(reg);
250 val = ((val & ~mask) | (value & mask)); 250 val = ((val & ~mask) | (value & mask));
251 writel(val, reg); 251 writel(val, reg);
252 } 252 }
253 253
254 static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct, 254 static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
255 unsigned offset, unsigned alt_num) 255 unsigned offset, unsigned alt_num)
256 { 256 {
257 int i; 257 int i;
258 u16 reg; 258 u16 reg;
259 u8 bit; 259 u8 bit;
260 u8 alt_index; 260 u8 alt_index;
261 const struct prcm_gpiocr_altcx_pin_desc *pin_desc; 261 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
262 const u16 *gpiocr_regs; 262 const u16 *gpiocr_regs;
263 263
264 if (!npct->prcm_base) 264 if (!npct->prcm_base)
265 return; 265 return;
266 266
267 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) { 267 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
268 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n", 268 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
269 alt_num); 269 alt_num);
270 return; 270 return;
271 } 271 }
272 272
273 for (i = 0 ; i < npct->soc->npins_altcx ; i++) { 273 for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
274 if (npct->soc->altcx_pins[i].pin == offset) 274 if (npct->soc->altcx_pins[i].pin == offset)
275 break; 275 break;
276 } 276 }
277 if (i == npct->soc->npins_altcx) { 277 if (i == npct->soc->npins_altcx) {
278 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n", 278 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
279 offset); 279 offset);
280 return; 280 return;
281 } 281 }
282 282
283 pin_desc = npct->soc->altcx_pins + i; 283 pin_desc = npct->soc->altcx_pins + i;
284 gpiocr_regs = npct->soc->prcm_gpiocr_registers; 284 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
285 285
286 /* 286 /*
287 * If alt_num is NULL, just clear current ALTCx selection 287 * If alt_num is NULL, just clear current ALTCx selection
288 * to make sure we come back to a pure ALTC selection 288 * to make sure we come back to a pure ALTC selection
289 */ 289 */
290 if (!alt_num) { 290 if (!alt_num) {
291 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { 291 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
292 if (pin_desc->altcx[i].used == true) { 292 if (pin_desc->altcx[i].used == true) {
293 reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 293 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
294 bit = pin_desc->altcx[i].control_bit; 294 bit = pin_desc->altcx[i].control_bit;
295 if (readl(npct->prcm_base + reg) & BIT(bit)) { 295 if (readl(npct->prcm_base + reg) & BIT(bit)) {
296 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); 296 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
297 dev_dbg(npct->dev, 297 dev_dbg(npct->dev,
298 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", 298 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
299 offset, i+1); 299 offset, i+1);
300 } 300 }
301 } 301 }
302 } 302 }
303 return; 303 return;
304 } 304 }
305 305
306 alt_index = alt_num - 1; 306 alt_index = alt_num - 1;
307 if (pin_desc->altcx[alt_index].used == false) { 307 if (pin_desc->altcx[alt_index].used == false) {
308 dev_warn(npct->dev, 308 dev_warn(npct->dev,
309 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n", 309 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
310 offset, alt_num); 310 offset, alt_num);
311 return; 311 return;
312 } 312 }
313 313
314 /* 314 /*
315 * Check if any other ALTCx functions are activated on this pin 315 * Check if any other ALTCx functions are activated on this pin
316 * and disable it first. 316 * and disable it first.
317 */ 317 */
318 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { 318 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
319 if (i == alt_index) 319 if (i == alt_index)
320 continue; 320 continue;
321 if (pin_desc->altcx[i].used == true) { 321 if (pin_desc->altcx[i].used == true) {
322 reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 322 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
323 bit = pin_desc->altcx[i].control_bit; 323 bit = pin_desc->altcx[i].control_bit;
324 if (readl(npct->prcm_base + reg) & BIT(bit)) { 324 if (readl(npct->prcm_base + reg) & BIT(bit)) {
325 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); 325 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
326 dev_dbg(npct->dev, 326 dev_dbg(npct->dev,
327 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", 327 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
328 offset, i+1); 328 offset, i+1);
329 } 329 }
330 } 330 }
331 } 331 }
332 332
333 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index]; 333 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
334 bit = pin_desc->altcx[alt_index].control_bit; 334 bit = pin_desc->altcx[alt_index].control_bit;
335 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n", 335 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
336 offset, alt_index+1); 336 offset, alt_index+1);
337 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit)); 337 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));
338 } 338 }
339 339
340 /* 340 /*
341 * Safe sequence used to switch IOs between GPIO and Alternate-C mode: 341 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
342 * - Save SLPM registers 342 * - Save SLPM registers
343 * - Set SLPM=0 for the IOs you want to switch and others to 1 343 * - Set SLPM=0 for the IOs you want to switch and others to 1
344 * - Configure the GPIO registers for the IOs that are being switched 344 * - Configure the GPIO registers for the IOs that are being switched
345 * - Set IOFORCE=1 345 * - Set IOFORCE=1
346 * - Modify the AFLSA/B registers for the IOs that are being switched 346 * - Modify the AFLSA/B registers for the IOs that are being switched
347 * - Set IOFORCE=0 347 * - Set IOFORCE=0
348 * - Restore SLPM registers 348 * - Restore SLPM registers
349 * - Any spurious wake up event during switch sequence to be ignored and 349 * - Any spurious wake up event during switch sequence to be ignored and
350 * cleared 350 * cleared
351 */ 351 */
352 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) 352 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
353 { 353 {
354 int i; 354 int i;
355 355
356 for (i = 0; i < NUM_BANKS; i++) { 356 for (i = 0; i < NUM_BANKS; i++) {
357 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 357 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
358 unsigned int temp = slpm[i]; 358 unsigned int temp = slpm[i];
359 359
360 if (!chip) 360 if (!chip)
361 break; 361 break;
362 362
363 clk_enable(chip->clk); 363 clk_enable(chip->clk);
364 364
365 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); 365 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
366 writel(temp, chip->addr + NMK_GPIO_SLPC); 366 writel(temp, chip->addr + NMK_GPIO_SLPC);
367 } 367 }
368 } 368 }
369 369
370 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) 370 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
371 { 371 {
372 int i; 372 int i;
373 373
374 for (i = 0; i < NUM_BANKS; i++) { 374 for (i = 0; i < NUM_BANKS; i++) {
375 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 375 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
376 376
377 if (!chip) 377 if (!chip)
378 break; 378 break;
379 379
380 writel(slpm[i], chip->addr + NMK_GPIO_SLPC); 380 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
381 381
382 clk_disable(chip->clk); 382 clk_disable(chip->clk);
383 } 383 }
384 } 384 }
385 385
386 static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio) 386 static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
387 { 387 {
388 int i; 388 int i;
389 u16 reg; 389 u16 reg;
390 u8 bit; 390 u8 bit;
391 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 391 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
392 const struct prcm_gpiocr_altcx_pin_desc *pin_desc; 392 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
393 const u16 *gpiocr_regs; 393 const u16 *gpiocr_regs;
394 394
395 if (!npct->prcm_base) 395 if (!npct->prcm_base)
396 return NMK_GPIO_ALT_C; 396 return NMK_GPIO_ALT_C;
397 397
398 for (i = 0; i < npct->soc->npins_altcx; i++) { 398 for (i = 0; i < npct->soc->npins_altcx; i++) {
399 if (npct->soc->altcx_pins[i].pin == gpio) 399 if (npct->soc->altcx_pins[i].pin == gpio)
400 break; 400 break;
401 } 401 }
402 if (i == npct->soc->npins_altcx) 402 if (i == npct->soc->npins_altcx)
403 return NMK_GPIO_ALT_C; 403 return NMK_GPIO_ALT_C;
404 404
405 pin_desc = npct->soc->altcx_pins + i; 405 pin_desc = npct->soc->altcx_pins + i;
406 gpiocr_regs = npct->soc->prcm_gpiocr_registers; 406 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
407 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) { 407 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) {
408 if (pin_desc->altcx[i].used == true) { 408 if (pin_desc->altcx[i].used == true) {
409 reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; 409 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
410 bit = pin_desc->altcx[i].control_bit; 410 bit = pin_desc->altcx[i].control_bit;
411 if (readl(npct->prcm_base + reg) & BIT(bit)) 411 if (readl(npct->prcm_base + reg) & BIT(bit))
412 return NMK_GPIO_ALT_C+i+1; 412 return NMK_GPIO_ALT_C+i+1;
413 } 413 }
414 } 414 }
415 return NMK_GPIO_ALT_C; 415 return NMK_GPIO_ALT_C;
416 } 416 }
417 417
418 int nmk_gpio_get_mode(int gpio) 418 int nmk_gpio_get_mode(int gpio)
419 { 419 {
420 struct nmk_gpio_chip *nmk_chip; 420 struct nmk_gpio_chip *nmk_chip;
421 u32 afunc, bfunc, bit; 421 u32 afunc, bfunc, bit;
422 422
423 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; 423 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
424 if (!nmk_chip) 424 if (!nmk_chip)
425 return -EINVAL; 425 return -EINVAL;
426 426
427 bit = 1 << (gpio % NMK_GPIO_PER_CHIP); 427 bit = 1 << (gpio % NMK_GPIO_PER_CHIP);
428 428
429 clk_enable(nmk_chip->clk); 429 clk_enable(nmk_chip->clk);
430 430
431 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit; 431 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
432 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit; 432 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
433 433
434 clk_disable(nmk_chip->clk); 434 clk_disable(nmk_chip->clk);
435 435
436 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); 436 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
437 } 437 }
438 EXPORT_SYMBOL(nmk_gpio_get_mode); 438 EXPORT_SYMBOL(nmk_gpio_get_mode);
439 439
440 440
441 /* IRQ functions */ 441 /* IRQ functions */
442 static inline int nmk_gpio_get_bitmask(int gpio) 442 static inline int nmk_gpio_get_bitmask(int gpio)
443 { 443 {
444 return 1 << (gpio % NMK_GPIO_PER_CHIP); 444 return 1 << (gpio % NMK_GPIO_PER_CHIP);
445 } 445 }
446 446
447 static void nmk_gpio_irq_ack(struct irq_data *d) 447 static void nmk_gpio_irq_ack(struct irq_data *d)
448 { 448 {
449 struct nmk_gpio_chip *nmk_chip; 449 struct nmk_gpio_chip *nmk_chip;
450 450
451 nmk_chip = irq_data_get_irq_chip_data(d); 451 nmk_chip = irq_data_get_irq_chip_data(d);
452 if (!nmk_chip) 452 if (!nmk_chip)
453 return; 453 return;
454 454
455 clk_enable(nmk_chip->clk); 455 clk_enable(nmk_chip->clk);
456 writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); 456 writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
457 clk_disable(nmk_chip->clk); 457 clk_disable(nmk_chip->clk);
458 } 458 }
459 459
460 enum nmk_gpio_irq_type { 460 enum nmk_gpio_irq_type {
461 NORMAL, 461 NORMAL,
462 WAKE, 462 WAKE,
463 }; 463 };
464 464
465 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, 465 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
466 int gpio, enum nmk_gpio_irq_type which, 466 int gpio, enum nmk_gpio_irq_type which,
467 bool enable) 467 bool enable)
468 { 468 {
469 u32 bitmask = nmk_gpio_get_bitmask(gpio); 469 u32 bitmask = nmk_gpio_get_bitmask(gpio);
470 u32 *rimscval; 470 u32 *rimscval;
471 u32 *fimscval; 471 u32 *fimscval;
472 u32 rimscreg; 472 u32 rimscreg;
473 u32 fimscreg; 473 u32 fimscreg;
474 474
475 if (which == NORMAL) { 475 if (which == NORMAL) {
476 rimscreg = NMK_GPIO_RIMSC; 476 rimscreg = NMK_GPIO_RIMSC;
477 fimscreg = NMK_GPIO_FIMSC; 477 fimscreg = NMK_GPIO_FIMSC;
478 rimscval = &nmk_chip->rimsc; 478 rimscval = &nmk_chip->rimsc;
479 fimscval = &nmk_chip->fimsc; 479 fimscval = &nmk_chip->fimsc;
480 } else { 480 } else {
481 rimscreg = NMK_GPIO_RWIMSC; 481 rimscreg = NMK_GPIO_RWIMSC;
482 fimscreg = NMK_GPIO_FWIMSC; 482 fimscreg = NMK_GPIO_FWIMSC;
483 rimscval = &nmk_chip->rwimsc; 483 rimscval = &nmk_chip->rwimsc;
484 fimscval = &nmk_chip->fwimsc; 484 fimscval = &nmk_chip->fwimsc;
485 } 485 }
486 486
487 /* we must individually set/clear the two edges */ 487 /* we must individually set/clear the two edges */
488 if (nmk_chip->edge_rising & bitmask) { 488 if (nmk_chip->edge_rising & bitmask) {
489 if (enable) 489 if (enable)
490 *rimscval |= bitmask; 490 *rimscval |= bitmask;
491 else 491 else
492 *rimscval &= ~bitmask; 492 *rimscval &= ~bitmask;
493 writel(*rimscval, nmk_chip->addr + rimscreg); 493 writel(*rimscval, nmk_chip->addr + rimscreg);
494 } 494 }
495 if (nmk_chip->edge_falling & bitmask) { 495 if (nmk_chip->edge_falling & bitmask) {
496 if (enable) 496 if (enable)
497 *fimscval |= bitmask; 497 *fimscval |= bitmask;
498 else 498 else
499 *fimscval &= ~bitmask; 499 *fimscval &= ~bitmask;
500 writel(*fimscval, nmk_chip->addr + fimscreg); 500 writel(*fimscval, nmk_chip->addr + fimscreg);
501 } 501 }
502 } 502 }
503 503
504 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, 504 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
505 int gpio, bool on) 505 int gpio, bool on)
506 { 506 {
507 /* 507 /*
508 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is 508 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
509 * disabled, since setting SLPM to 1 increases power consumption, and 509 * disabled, since setting SLPM to 1 increases power consumption, and
510 * wakeup is anyhow controlled by the RIMSC and FIMSC registers. 510 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
511 */ 511 */
512 if (nmk_chip->sleepmode && on) { 512 if (nmk_chip->sleepmode && on) {
513 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, 513 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP,
514 NMK_GPIO_SLPM_WAKEUP_ENABLE); 514 NMK_GPIO_SLPM_WAKEUP_ENABLE);
515 } 515 }
516 516
517 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); 517 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
518 } 518 }
519 519
520 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) 520 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
521 { 521 {
522 struct nmk_gpio_chip *nmk_chip; 522 struct nmk_gpio_chip *nmk_chip;
523 unsigned long flags; 523 unsigned long flags;
524 u32 bitmask; 524 u32 bitmask;
525 525
526 nmk_chip = irq_data_get_irq_chip_data(d); 526 nmk_chip = irq_data_get_irq_chip_data(d);
527 bitmask = nmk_gpio_get_bitmask(d->hwirq); 527 bitmask = nmk_gpio_get_bitmask(d->hwirq);
528 if (!nmk_chip) 528 if (!nmk_chip)
529 return -EINVAL; 529 return -EINVAL;
530 530
531 clk_enable(nmk_chip->clk); 531 clk_enable(nmk_chip->clk);
532 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 532 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
533 spin_lock(&nmk_chip->lock); 533 spin_lock(&nmk_chip->lock);
534 534
535 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); 535 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
536 536
537 if (!(nmk_chip->real_wake & bitmask)) 537 if (!(nmk_chip->real_wake & bitmask))
538 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); 538 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
539 539
540 spin_unlock(&nmk_chip->lock); 540 spin_unlock(&nmk_chip->lock);
541 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 541 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
542 clk_disable(nmk_chip->clk); 542 clk_disable(nmk_chip->clk);
543 543
544 return 0; 544 return 0;
545 } 545 }
546 546
547 static void nmk_gpio_irq_mask(struct irq_data *d) 547 static void nmk_gpio_irq_mask(struct irq_data *d)
548 { 548 {
549 nmk_gpio_irq_maskunmask(d, false); 549 nmk_gpio_irq_maskunmask(d, false);
550 } 550 }
551 551
552 static void nmk_gpio_irq_unmask(struct irq_data *d) 552 static void nmk_gpio_irq_unmask(struct irq_data *d)
553 { 553 {
554 nmk_gpio_irq_maskunmask(d, true); 554 nmk_gpio_irq_maskunmask(d, true);
555 } 555 }
556 556
557 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 557 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
558 { 558 {
559 struct nmk_gpio_chip *nmk_chip; 559 struct nmk_gpio_chip *nmk_chip;
560 unsigned long flags; 560 unsigned long flags;
561 u32 bitmask; 561 u32 bitmask;
562 562
563 nmk_chip = irq_data_get_irq_chip_data(d); 563 nmk_chip = irq_data_get_irq_chip_data(d);
564 if (!nmk_chip) 564 if (!nmk_chip)
565 return -EINVAL; 565 return -EINVAL;
566 bitmask = nmk_gpio_get_bitmask(d->hwirq); 566 bitmask = nmk_gpio_get_bitmask(d->hwirq);
567 567
568 clk_enable(nmk_chip->clk); 568 clk_enable(nmk_chip->clk);
569 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 569 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
570 spin_lock(&nmk_chip->lock); 570 spin_lock(&nmk_chip->lock);
571 571
572 if (irqd_irq_disabled(d)) 572 if (irqd_irq_disabled(d))
573 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); 573 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
574 574
575 if (on) 575 if (on)
576 nmk_chip->real_wake |= bitmask; 576 nmk_chip->real_wake |= bitmask;
577 else 577 else
578 nmk_chip->real_wake &= ~bitmask; 578 nmk_chip->real_wake &= ~bitmask;
579 579
580 spin_unlock(&nmk_chip->lock); 580 spin_unlock(&nmk_chip->lock);
581 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 581 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
582 clk_disable(nmk_chip->clk); 582 clk_disable(nmk_chip->clk);
583 583
584 return 0; 584 return 0;
585 } 585 }
586 586
587 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) 587 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
588 { 588 {
589 bool enabled = !irqd_irq_disabled(d); 589 bool enabled = !irqd_irq_disabled(d);
590 bool wake = irqd_is_wakeup_set(d); 590 bool wake = irqd_is_wakeup_set(d);
591 struct nmk_gpio_chip *nmk_chip; 591 struct nmk_gpio_chip *nmk_chip;
592 unsigned long flags; 592 unsigned long flags;
593 u32 bitmask; 593 u32 bitmask;
594 594
595 nmk_chip = irq_data_get_irq_chip_data(d); 595 nmk_chip = irq_data_get_irq_chip_data(d);
596 bitmask = nmk_gpio_get_bitmask(d->hwirq); 596 bitmask = nmk_gpio_get_bitmask(d->hwirq);
597 if (!nmk_chip) 597 if (!nmk_chip)
598 return -EINVAL; 598 return -EINVAL;
599 if (type & IRQ_TYPE_LEVEL_HIGH) 599 if (type & IRQ_TYPE_LEVEL_HIGH)
600 return -EINVAL; 600 return -EINVAL;
601 if (type & IRQ_TYPE_LEVEL_LOW) 601 if (type & IRQ_TYPE_LEVEL_LOW)
602 return -EINVAL; 602 return -EINVAL;
603 603
604 clk_enable(nmk_chip->clk); 604 clk_enable(nmk_chip->clk);
605 spin_lock_irqsave(&nmk_chip->lock, flags); 605 spin_lock_irqsave(&nmk_chip->lock, flags);
606 606
607 if (enabled) 607 if (enabled)
608 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); 608 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
609 609
610 if (enabled || wake) 610 if (enabled || wake)
611 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); 611 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
612 612
613 nmk_chip->edge_rising &= ~bitmask; 613 nmk_chip->edge_rising &= ~bitmask;
614 if (type & IRQ_TYPE_EDGE_RISING) 614 if (type & IRQ_TYPE_EDGE_RISING)
615 nmk_chip->edge_rising |= bitmask; 615 nmk_chip->edge_rising |= bitmask;
616 616
617 nmk_chip->edge_falling &= ~bitmask; 617 nmk_chip->edge_falling &= ~bitmask;
618 if (type & IRQ_TYPE_EDGE_FALLING) 618 if (type & IRQ_TYPE_EDGE_FALLING)
619 nmk_chip->edge_falling |= bitmask; 619 nmk_chip->edge_falling |= bitmask;
620 620
621 if (enabled) 621 if (enabled)
622 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); 622 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
623 623
624 if (enabled || wake) 624 if (enabled || wake)
625 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); 625 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
626 626
627 spin_unlock_irqrestore(&nmk_chip->lock, flags); 627 spin_unlock_irqrestore(&nmk_chip->lock, flags);
628 clk_disable(nmk_chip->clk); 628 clk_disable(nmk_chip->clk);
629 629
630 return 0; 630 return 0;
631 } 631 }
632 632
633 static unsigned int nmk_gpio_irq_startup(struct irq_data *d) 633 static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
634 { 634 {
635 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); 635 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
636 636
637 if (gpio_lock_as_irq(&nmk_chip->chip, d->hwirq))
638 dev_err(nmk_chip->chip.dev,
639 "unable to lock HW IRQ %lu for IRQ\n",
640 d->hwirq);
637 clk_enable(nmk_chip->clk); 641 clk_enable(nmk_chip->clk);
638 nmk_gpio_irq_unmask(d); 642 nmk_gpio_irq_unmask(d);
639 return 0; 643 return 0;
640 } 644 }
641 645
642 static void nmk_gpio_irq_shutdown(struct irq_data *d) 646 static void nmk_gpio_irq_shutdown(struct irq_data *d)
643 { 647 {
644 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); 648 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
645 649
646 nmk_gpio_irq_mask(d); 650 nmk_gpio_irq_mask(d);
647 clk_disable(nmk_chip->clk); 651 clk_disable(nmk_chip->clk);
652 gpio_unlock_as_irq(&nmk_chip->chip, d->hwirq);
648 } 653 }
649 654
650 static struct irq_chip nmk_gpio_irq_chip = { 655 static struct irq_chip nmk_gpio_irq_chip = {
651 .name = "Nomadik-GPIO", 656 .name = "Nomadik-GPIO",
652 .irq_ack = nmk_gpio_irq_ack, 657 .irq_ack = nmk_gpio_irq_ack,
653 .irq_mask = nmk_gpio_irq_mask, 658 .irq_mask = nmk_gpio_irq_mask,
654 .irq_unmask = nmk_gpio_irq_unmask, 659 .irq_unmask = nmk_gpio_irq_unmask,
655 .irq_set_type = nmk_gpio_irq_set_type, 660 .irq_set_type = nmk_gpio_irq_set_type,
656 .irq_set_wake = nmk_gpio_irq_set_wake, 661 .irq_set_wake = nmk_gpio_irq_set_wake,
657 .irq_startup = nmk_gpio_irq_startup, 662 .irq_startup = nmk_gpio_irq_startup,
658 .irq_shutdown = nmk_gpio_irq_shutdown, 663 .irq_shutdown = nmk_gpio_irq_shutdown,
659 .flags = IRQCHIP_MASK_ON_SUSPEND, 664 .flags = IRQCHIP_MASK_ON_SUSPEND,
660 }; 665 };
661 666
662 static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, 667 static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
663 u32 status) 668 u32 status)
664 { 669 {
665 struct nmk_gpio_chip *nmk_chip; 670 struct nmk_gpio_chip *nmk_chip;
666 struct irq_chip *host_chip = irq_get_chip(irq); 671 struct irq_chip *host_chip = irq_get_chip(irq);
667 672
668 chained_irq_enter(host_chip, desc); 673 chained_irq_enter(host_chip, desc);
669 674
670 nmk_chip = irq_get_handler_data(irq); 675 nmk_chip = irq_get_handler_data(irq);
671 while (status) { 676 while (status) {
672 int bit = __ffs(status); 677 int bit = __ffs(status);
673 678
674 generic_handle_irq(irq_find_mapping(nmk_chip->domain, bit)); 679 generic_handle_irq(irq_find_mapping(nmk_chip->domain, bit));
675 status &= ~BIT(bit); 680 status &= ~BIT(bit);
676 } 681 }
677 682
678 chained_irq_exit(host_chip, desc); 683 chained_irq_exit(host_chip, desc);
679 } 684 }
680 685
681 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 686 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
682 { 687 {
683 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); 688 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
684 u32 status; 689 u32 status;
685 690
686 clk_enable(nmk_chip->clk); 691 clk_enable(nmk_chip->clk);
687 status = readl(nmk_chip->addr + NMK_GPIO_IS); 692 status = readl(nmk_chip->addr + NMK_GPIO_IS);
688 clk_disable(nmk_chip->clk); 693 clk_disable(nmk_chip->clk);
689 694
690 __nmk_gpio_irq_handler(irq, desc, status); 695 __nmk_gpio_irq_handler(irq, desc, status);
691 } 696 }
692 697
693 static void nmk_gpio_secondary_irq_handler(unsigned int irq, 698 static void nmk_gpio_secondary_irq_handler(unsigned int irq,
694 struct irq_desc *desc) 699 struct irq_desc *desc)
695 { 700 {
696 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); 701 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
697 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank); 702 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
698 703
699 __nmk_gpio_irq_handler(irq, desc, status); 704 __nmk_gpio_irq_handler(irq, desc, status);
700 } 705 }
701 706
702 static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) 707 static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
703 { 708 {
704 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); 709 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
705 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip); 710 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
706 711
707 if (nmk_chip->secondary_parent_irq >= 0) { 712 if (nmk_chip->secondary_parent_irq >= 0) {
708 irq_set_chained_handler(nmk_chip->secondary_parent_irq, 713 irq_set_chained_handler(nmk_chip->secondary_parent_irq,
709 nmk_gpio_secondary_irq_handler); 714 nmk_gpio_secondary_irq_handler);
710 irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip); 715 irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
711 } 716 }
712 717
713 return 0; 718 return 0;
714 } 719 }
715 720
716 /* I/O Functions */ 721 /* I/O Functions */
717 722
718 static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset) 723 static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset)
719 { 724 {
720 /* 725 /*
721 * Map back to global GPIO space and request muxing, the direction 726 * Map back to global GPIO space and request muxing, the direction
722 * parameter does not matter for this controller. 727 * parameter does not matter for this controller.
723 */ 728 */
724 int gpio = chip->base + offset; 729 int gpio = chip->base + offset;
725 730
726 return pinctrl_request_gpio(gpio); 731 return pinctrl_request_gpio(gpio);
727 } 732 }
728 733
729 static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset) 734 static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset)
730 { 735 {
731 int gpio = chip->base + offset; 736 int gpio = chip->base + offset;
732 737
733 pinctrl_free_gpio(gpio); 738 pinctrl_free_gpio(gpio);
734 } 739 }
735 740
736 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) 741 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
737 { 742 {
738 struct nmk_gpio_chip *nmk_chip = 743 struct nmk_gpio_chip *nmk_chip =
739 container_of(chip, struct nmk_gpio_chip, chip); 744 container_of(chip, struct nmk_gpio_chip, chip);
740 745
741 clk_enable(nmk_chip->clk); 746 clk_enable(nmk_chip->clk);
742 747
743 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); 748 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
744 749
745 clk_disable(nmk_chip->clk); 750 clk_disable(nmk_chip->clk);
746 751
747 return 0; 752 return 0;
748 } 753 }
749 754
750 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) 755 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
751 { 756 {
752 struct nmk_gpio_chip *nmk_chip = 757 struct nmk_gpio_chip *nmk_chip =
753 container_of(chip, struct nmk_gpio_chip, chip); 758 container_of(chip, struct nmk_gpio_chip, chip);
754 u32 bit = 1 << offset; 759 u32 bit = 1 << offset;
755 int value; 760 int value;
756 761
757 clk_enable(nmk_chip->clk); 762 clk_enable(nmk_chip->clk);
758 763
759 value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0; 764 value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
760 765
761 clk_disable(nmk_chip->clk); 766 clk_disable(nmk_chip->clk);
762 767
763 return value; 768 return value;
764 } 769 }
765 770
766 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, 771 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
767 int val) 772 int val)
768 { 773 {
769 struct nmk_gpio_chip *nmk_chip = 774 struct nmk_gpio_chip *nmk_chip =
770 container_of(chip, struct nmk_gpio_chip, chip); 775 container_of(chip, struct nmk_gpio_chip, chip);
771 776
772 clk_enable(nmk_chip->clk); 777 clk_enable(nmk_chip->clk);
773 778
774 __nmk_gpio_set_output(nmk_chip, offset, val); 779 __nmk_gpio_set_output(nmk_chip, offset, val);
775 780
776 clk_disable(nmk_chip->clk); 781 clk_disable(nmk_chip->clk);
777 } 782 }
778 783
779 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, 784 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
780 int val) 785 int val)
781 { 786 {
782 struct nmk_gpio_chip *nmk_chip = 787 struct nmk_gpio_chip *nmk_chip =
783 container_of(chip, struct nmk_gpio_chip, chip); 788 container_of(chip, struct nmk_gpio_chip, chip);
784 789
785 clk_enable(nmk_chip->clk); 790 clk_enable(nmk_chip->clk);
786 791
787 __nmk_gpio_make_output(nmk_chip, offset, val); 792 __nmk_gpio_make_output(nmk_chip, offset, val);
788 793
789 clk_disable(nmk_chip->clk); 794 clk_disable(nmk_chip->clk);
790 795
791 return 0; 796 return 0;
792 } 797 }
793 798
794 static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 799 static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
795 { 800 {
796 struct nmk_gpio_chip *nmk_chip = 801 struct nmk_gpio_chip *nmk_chip =
797 container_of(chip, struct nmk_gpio_chip, chip); 802 container_of(chip, struct nmk_gpio_chip, chip);
798 803
799 return irq_create_mapping(nmk_chip->domain, offset); 804 return irq_create_mapping(nmk_chip->domain, offset);
800 } 805 }
801 806
802 #ifdef CONFIG_DEBUG_FS 807 #ifdef CONFIG_DEBUG_FS
803 808
804 #include <linux/seq_file.h> 809 #include <linux/seq_file.h>
805 810
806 static void nmk_gpio_dbg_show_one(struct seq_file *s, 811 static void nmk_gpio_dbg_show_one(struct seq_file *s,
807 struct pinctrl_dev *pctldev, struct gpio_chip *chip, 812 struct pinctrl_dev *pctldev, struct gpio_chip *chip,
808 unsigned offset, unsigned gpio) 813 unsigned offset, unsigned gpio)
809 { 814 {
810 const char *label = gpiochip_is_requested(chip, offset); 815 const char *label = gpiochip_is_requested(chip, offset);
811 struct nmk_gpio_chip *nmk_chip = 816 struct nmk_gpio_chip *nmk_chip =
812 container_of(chip, struct nmk_gpio_chip, chip); 817 container_of(chip, struct nmk_gpio_chip, chip);
813 int mode; 818 int mode;
814 bool is_out; 819 bool is_out;
815 bool pull; 820 bool pull;
816 u32 bit = 1 << offset; 821 u32 bit = 1 << offset;
817 const char *modes[] = { 822 const char *modes[] = {
818 [NMK_GPIO_ALT_GPIO] = "gpio", 823 [NMK_GPIO_ALT_GPIO] = "gpio",
819 [NMK_GPIO_ALT_A] = "altA", 824 [NMK_GPIO_ALT_A] = "altA",
820 [NMK_GPIO_ALT_B] = "altB", 825 [NMK_GPIO_ALT_B] = "altB",
821 [NMK_GPIO_ALT_C] = "altC", 826 [NMK_GPIO_ALT_C] = "altC",
822 [NMK_GPIO_ALT_C+1] = "altC1", 827 [NMK_GPIO_ALT_C+1] = "altC1",
823 [NMK_GPIO_ALT_C+2] = "altC2", 828 [NMK_GPIO_ALT_C+2] = "altC2",
824 [NMK_GPIO_ALT_C+3] = "altC3", 829 [NMK_GPIO_ALT_C+3] = "altC3",
825 [NMK_GPIO_ALT_C+4] = "altC4", 830 [NMK_GPIO_ALT_C+4] = "altC4",
826 }; 831 };
827 832
828 clk_enable(nmk_chip->clk); 833 clk_enable(nmk_chip->clk);
829 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit); 834 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
830 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); 835 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
831 mode = nmk_gpio_get_mode(gpio); 836 mode = nmk_gpio_get_mode(gpio);
832 if ((mode == NMK_GPIO_ALT_C) && pctldev) 837 if ((mode == NMK_GPIO_ALT_C) && pctldev)
833 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio); 838 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
834 839
835 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", 840 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
836 gpio, label ?: "(none)", 841 gpio, label ?: "(none)",
837 is_out ? "out" : "in ", 842 is_out ? "out" : "in ",
838 chip->get 843 chip->get
839 ? (chip->get(chip, offset) ? "hi" : "lo") 844 ? (chip->get(chip, offset) ? "hi" : "lo")
840 : "? ", 845 : "? ",
841 (mode < 0) ? "unknown" : modes[mode], 846 (mode < 0) ? "unknown" : modes[mode],
842 pull ? "pull" : "none"); 847 pull ? "pull" : "none");
843 848
844 if (label && !is_out) { 849 if (label && !is_out) {
845 int irq = gpio_to_irq(gpio); 850 int irq = gpio_to_irq(gpio);
846 struct irq_desc *desc = irq_to_desc(irq); 851 struct irq_desc *desc = irq_to_desc(irq);
847 852
848 /* This races with request_irq(), set_irq_type(), 853 /* This races with request_irq(), set_irq_type(),
849 * and set_irq_wake() ... but those are "rare". 854 * and set_irq_wake() ... but those are "rare".
850 */ 855 */
851 if (irq >= 0 && desc->action) { 856 if (irq >= 0 && desc->action) {
852 char *trigger; 857 char *trigger;
853 u32 bitmask = nmk_gpio_get_bitmask(gpio); 858 u32 bitmask = nmk_gpio_get_bitmask(gpio);
854 859
855 if (nmk_chip->edge_rising & bitmask) 860 if (nmk_chip->edge_rising & bitmask)
856 trigger = "edge-rising"; 861 trigger = "edge-rising";
857 else if (nmk_chip->edge_falling & bitmask) 862 else if (nmk_chip->edge_falling & bitmask)
858 trigger = "edge-falling"; 863 trigger = "edge-falling";
859 else 864 else
860 trigger = "edge-undefined"; 865 trigger = "edge-undefined";
861 866
862 seq_printf(s, " irq-%d %s%s", 867 seq_printf(s, " irq-%d %s%s",
863 irq, trigger, 868 irq, trigger,
864 irqd_is_wakeup_set(&desc->irq_data) 869 irqd_is_wakeup_set(&desc->irq_data)
865 ? " wakeup" : ""); 870 ? " wakeup" : "");
866 } 871 }
867 } 872 }
868 clk_disable(nmk_chip->clk); 873 clk_disable(nmk_chip->clk);
869 } 874 }
870 875
871 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 876 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
872 { 877 {
873 unsigned i; 878 unsigned i;
874 unsigned gpio = chip->base; 879 unsigned gpio = chip->base;
875 880
876 for (i = 0; i < chip->ngpio; i++, gpio++) { 881 for (i = 0; i < chip->ngpio; i++, gpio++) {
877 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio); 882 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio);
878 seq_printf(s, "\n"); 883 seq_printf(s, "\n");
879 } 884 }
880 } 885 }
881 886
882 #else 887 #else
883 static inline void nmk_gpio_dbg_show_one(struct seq_file *s, 888 static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
884 struct pinctrl_dev *pctldev, 889 struct pinctrl_dev *pctldev,
885 struct gpio_chip *chip, 890 struct gpio_chip *chip,
886 unsigned offset, unsigned gpio) 891 unsigned offset, unsigned gpio)
887 { 892 {
888 } 893 }
889 #define nmk_gpio_dbg_show NULL 894 #define nmk_gpio_dbg_show NULL
890 #endif 895 #endif
891 896
892 /* This structure is replicated for each GPIO block allocated at probe time */ 897 /* This structure is replicated for each GPIO block allocated at probe time */
893 static struct gpio_chip nmk_gpio_template = { 898 static struct gpio_chip nmk_gpio_template = {
894 .request = nmk_gpio_request, 899 .request = nmk_gpio_request,
895 .free = nmk_gpio_free, 900 .free = nmk_gpio_free,
896 .direction_input = nmk_gpio_make_input, 901 .direction_input = nmk_gpio_make_input,
897 .get = nmk_gpio_get_input, 902 .get = nmk_gpio_get_input,
898 .direction_output = nmk_gpio_make_output, 903 .direction_output = nmk_gpio_make_output,
899 .set = nmk_gpio_set_output, 904 .set = nmk_gpio_set_output,
900 .to_irq = nmk_gpio_to_irq, 905 .to_irq = nmk_gpio_to_irq,
901 .dbg_show = nmk_gpio_dbg_show, 906 .dbg_show = nmk_gpio_dbg_show,
902 .can_sleep = 0, 907 .can_sleep = 0,
903 }; 908 };
904 909
905 void nmk_gpio_clocks_enable(void) 910 void nmk_gpio_clocks_enable(void)
906 { 911 {
907 int i; 912 int i;
908 913
909 for (i = 0; i < NUM_BANKS; i++) { 914 for (i = 0; i < NUM_BANKS; i++) {
910 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 915 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
911 916
912 if (!chip) 917 if (!chip)
913 continue; 918 continue;
914 919
915 clk_enable(chip->clk); 920 clk_enable(chip->clk);
916 } 921 }
917 } 922 }
918 923
919 void nmk_gpio_clocks_disable(void) 924 void nmk_gpio_clocks_disable(void)
920 { 925 {
921 int i; 926 int i;
922 927
923 for (i = 0; i < NUM_BANKS; i++) { 928 for (i = 0; i < NUM_BANKS; i++) {
924 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 929 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
925 930
926 if (!chip) 931 if (!chip)
927 continue; 932 continue;
928 933
929 clk_disable(chip->clk); 934 clk_disable(chip->clk);
930 } 935 }
931 } 936 }
932 937
933 /* 938 /*
934 * Called from the suspend/resume path to only keep the real wakeup interrupts 939 * Called from the suspend/resume path to only keep the real wakeup interrupts
935 * (those that have had set_irq_wake() called on them) as wakeup interrupts, 940 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
936 * and not the rest of the interrupts which we needed to have as wakeups for 941 * and not the rest of the interrupts which we needed to have as wakeups for
937 * cpuidle. 942 * cpuidle.
938 * 943 *
939 * PM ops are not used since this needs to be done at the end, after all the 944 * PM ops are not used since this needs to be done at the end, after all the
940 * other drivers are done with their suspend callbacks. 945 * other drivers are done with their suspend callbacks.
941 */ 946 */
942 void nmk_gpio_wakeups_suspend(void) 947 void nmk_gpio_wakeups_suspend(void)
943 { 948 {
944 int i; 949 int i;
945 950
946 for (i = 0; i < NUM_BANKS; i++) { 951 for (i = 0; i < NUM_BANKS; i++) {
947 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 952 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
948 953
949 if (!chip) 954 if (!chip)
950 break; 955 break;
951 956
952 clk_enable(chip->clk); 957 clk_enable(chip->clk);
953 958
954 writel(chip->rwimsc & chip->real_wake, 959 writel(chip->rwimsc & chip->real_wake,
955 chip->addr + NMK_GPIO_RWIMSC); 960 chip->addr + NMK_GPIO_RWIMSC);
956 writel(chip->fwimsc & chip->real_wake, 961 writel(chip->fwimsc & chip->real_wake,
957 chip->addr + NMK_GPIO_FWIMSC); 962 chip->addr + NMK_GPIO_FWIMSC);
958 963
959 clk_disable(chip->clk); 964 clk_disable(chip->clk);
960 } 965 }
961 } 966 }
962 967
963 void nmk_gpio_wakeups_resume(void) 968 void nmk_gpio_wakeups_resume(void)
964 { 969 {
965 int i; 970 int i;
966 971
967 for (i = 0; i < NUM_BANKS; i++) { 972 for (i = 0; i < NUM_BANKS; i++) {
968 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 973 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
969 974
970 if (!chip) 975 if (!chip)
971 break; 976 break;
972 977
973 clk_enable(chip->clk); 978 clk_enable(chip->clk);
974 979
975 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); 980 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
976 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); 981 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
977 982
978 clk_disable(chip->clk); 983 clk_disable(chip->clk);
979 } 984 }
980 } 985 }
981 986
982 /* 987 /*
983 * Read the pull up/pull down status. 988 * Read the pull up/pull down status.
984 * A bit set in 'pull_up' means that pull up 989 * A bit set in 'pull_up' means that pull up
985 * is selected if pull is enabled in PDIS register. 990 * is selected if pull is enabled in PDIS register.
986 * Note: only pull up/down set via this driver can 991 * Note: only pull up/down set via this driver can
987 * be detected due to HW limitations. 992 * be detected due to HW limitations.
988 */ 993 */
989 void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) 994 void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
990 { 995 {
991 if (gpio_bank < NUM_BANKS) { 996 if (gpio_bank < NUM_BANKS) {
992 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank]; 997 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
993 998
994 if (!chip) 999 if (!chip)
995 return; 1000 return;
996 1001
997 *pull_up = chip->pull_up; 1002 *pull_up = chip->pull_up;
998 } 1003 }
999 } 1004 }
1000 1005
1001 static int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq, 1006 static int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1002 irq_hw_number_t hwirq) 1007 irq_hw_number_t hwirq)
1003 { 1008 {
1004 struct nmk_gpio_chip *nmk_chip = d->host_data; 1009 struct nmk_gpio_chip *nmk_chip = d->host_data;
1005 1010
1006 if (!nmk_chip) 1011 if (!nmk_chip)
1007 return -EINVAL; 1012 return -EINVAL;
1008 1013
1009 irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq); 1014 irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq);
1010 set_irq_flags(irq, IRQF_VALID); 1015 set_irq_flags(irq, IRQF_VALID);
1011 irq_set_chip_data(irq, nmk_chip); 1016 irq_set_chip_data(irq, nmk_chip);
1012 irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING); 1017 irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING);
1013 1018
1014 return 0; 1019 return 0;
1015 } 1020 }
1016 1021
1017 static const struct irq_domain_ops nmk_gpio_irq_simple_ops = { 1022 static const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
1018 .map = nmk_gpio_irq_map, 1023 .map = nmk_gpio_irq_map,
1019 .xlate = irq_domain_xlate_twocell, 1024 .xlate = irq_domain_xlate_twocell,
1020 }; 1025 };
1021 1026
1022 static int nmk_gpio_probe(struct platform_device *dev) 1027 static int nmk_gpio_probe(struct platform_device *dev)
1023 { 1028 {
1024 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; 1029 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
1025 struct device_node *np = dev->dev.of_node; 1030 struct device_node *np = dev->dev.of_node;
1026 struct nmk_gpio_chip *nmk_chip; 1031 struct nmk_gpio_chip *nmk_chip;
1027 struct gpio_chip *chip; 1032 struct gpio_chip *chip;
1028 struct resource *res; 1033 struct resource *res;
1029 struct clk *clk; 1034 struct clk *clk;
1030 int secondary_irq; 1035 int secondary_irq;
1031 void __iomem *base; 1036 void __iomem *base;
1032 int irq_start = 0; 1037 int irq_start = 0;
1033 int irq; 1038 int irq;
1034 int ret; 1039 int ret;
1035 1040
1036 if (!pdata && !np) { 1041 if (!pdata && !np) {
1037 dev_err(&dev->dev, "No platform data or device tree found\n"); 1042 dev_err(&dev->dev, "No platform data or device tree found\n");
1038 return -ENODEV; 1043 return -ENODEV;
1039 } 1044 }
1040 1045
1041 if (np) { 1046 if (np) {
1042 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL); 1047 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
1043 if (!pdata) 1048 if (!pdata)
1044 return -ENOMEM; 1049 return -ENOMEM;
1045 1050
1046 if (of_get_property(np, "st,supports-sleepmode", NULL)) 1051 if (of_get_property(np, "st,supports-sleepmode", NULL))
1047 pdata->supports_sleepmode = true; 1052 pdata->supports_sleepmode = true;
1048 1053
1049 if (of_property_read_u32(np, "gpio-bank", &dev->id)) { 1054 if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
1050 dev_err(&dev->dev, "gpio-bank property not found\n"); 1055 dev_err(&dev->dev, "gpio-bank property not found\n");
1051 return -EINVAL; 1056 return -EINVAL;
1052 } 1057 }
1053 1058
1054 pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP; 1059 pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
1055 pdata->num_gpio = NMK_GPIO_PER_CHIP; 1060 pdata->num_gpio = NMK_GPIO_PER_CHIP;
1056 } 1061 }
1057 1062
1058 irq = platform_get_irq(dev, 0); 1063 irq = platform_get_irq(dev, 0);
1059 if (irq < 0) 1064 if (irq < 0)
1060 return irq; 1065 return irq;
1061 1066
1062 secondary_irq = platform_get_irq(dev, 1); 1067 secondary_irq = platform_get_irq(dev, 1);
1063 if (secondary_irq >= 0 && !pdata->get_secondary_status) 1068 if (secondary_irq >= 0 && !pdata->get_secondary_status)
1064 return -EINVAL; 1069 return -EINVAL;
1065 1070
1066 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 1071 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1067 base = devm_ioremap_resource(&dev->dev, res); 1072 base = devm_ioremap_resource(&dev->dev, res);
1068 if (IS_ERR(base)) 1073 if (IS_ERR(base))
1069 return PTR_ERR(base); 1074 return PTR_ERR(base);
1070 1075
1071 clk = devm_clk_get(&dev->dev, NULL); 1076 clk = devm_clk_get(&dev->dev, NULL);
1072 if (IS_ERR(clk)) 1077 if (IS_ERR(clk))
1073 return PTR_ERR(clk); 1078 return PTR_ERR(clk);
1074 clk_prepare(clk); 1079 clk_prepare(clk);
1075 1080
1076 nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL); 1081 nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1077 if (!nmk_chip) 1082 if (!nmk_chip)
1078 return -ENOMEM; 1083 return -ENOMEM;
1079 1084
1080 /* 1085 /*
1081 * The virt address in nmk_chip->addr is in the nomadik register space, 1086 * The virt address in nmk_chip->addr is in the nomadik register space,
1082 * so we can simply convert the resource address, without remapping 1087 * so we can simply convert the resource address, without remapping
1083 */ 1088 */
1084 nmk_chip->bank = dev->id; 1089 nmk_chip->bank = dev->id;
1085 nmk_chip->clk = clk; 1090 nmk_chip->clk = clk;
1086 nmk_chip->addr = base; 1091 nmk_chip->addr = base;
1087 nmk_chip->chip = nmk_gpio_template; 1092 nmk_chip->chip = nmk_gpio_template;
1088 nmk_chip->parent_irq = irq; 1093 nmk_chip->parent_irq = irq;
1089 nmk_chip->secondary_parent_irq = secondary_irq; 1094 nmk_chip->secondary_parent_irq = secondary_irq;
1090 nmk_chip->get_secondary_status = pdata->get_secondary_status; 1095 nmk_chip->get_secondary_status = pdata->get_secondary_status;
1091 nmk_chip->set_ioforce = pdata->set_ioforce; 1096 nmk_chip->set_ioforce = pdata->set_ioforce;
1092 nmk_chip->sleepmode = pdata->supports_sleepmode; 1097 nmk_chip->sleepmode = pdata->supports_sleepmode;
1093 spin_lock_init(&nmk_chip->lock); 1098 spin_lock_init(&nmk_chip->lock);
1094 1099
1095 chip = &nmk_chip->chip; 1100 chip = &nmk_chip->chip;
1096 chip->base = pdata->first_gpio; 1101 chip->base = pdata->first_gpio;
1097 chip->ngpio = pdata->num_gpio; 1102 chip->ngpio = pdata->num_gpio;
1098 chip->label = pdata->name ?: dev_name(&dev->dev); 1103 chip->label = pdata->name ?: dev_name(&dev->dev);
1099 chip->dev = &dev->dev; 1104 chip->dev = &dev->dev;
1100 chip->owner = THIS_MODULE; 1105 chip->owner = THIS_MODULE;
1101 1106
1102 clk_enable(nmk_chip->clk); 1107 clk_enable(nmk_chip->clk);
1103 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); 1108 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1104 clk_disable(nmk_chip->clk); 1109 clk_disable(nmk_chip->clk);
1105 1110
1106 #ifdef CONFIG_OF_GPIO 1111 #ifdef CONFIG_OF_GPIO
1107 chip->of_node = np; 1112 chip->of_node = np;
1108 #endif 1113 #endif
1109 1114
1110 ret = gpiochip_add(&nmk_chip->chip); 1115 ret = gpiochip_add(&nmk_chip->chip);
1111 if (ret) 1116 if (ret)
1112 return ret; 1117 return ret;
1113 1118
1114 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); 1119 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1115 1120
1116 nmk_gpio_chips[nmk_chip->bank] = nmk_chip; 1121 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1117 1122
1118 platform_set_drvdata(dev, nmk_chip); 1123 platform_set_drvdata(dev, nmk_chip);
1119 1124
1120 if (!np) 1125 if (!np)
1121 irq_start = pdata->first_irq; 1126 irq_start = pdata->first_irq;
1122 nmk_chip->domain = irq_domain_add_simple(np, 1127 nmk_chip->domain = irq_domain_add_simple(np,
1123 NMK_GPIO_PER_CHIP, irq_start, 1128 NMK_GPIO_PER_CHIP, irq_start,
1124 &nmk_gpio_irq_simple_ops, nmk_chip); 1129 &nmk_gpio_irq_simple_ops, nmk_chip);
1125 if (!nmk_chip->domain) { 1130 if (!nmk_chip->domain) {
1126 dev_err(&dev->dev, "failed to create irqdomain\n"); 1131 dev_err(&dev->dev, "failed to create irqdomain\n");
1127 /* Just do this, no matter if it fails */ 1132 /* Just do this, no matter if it fails */
1128 ret = gpiochip_remove(&nmk_chip->chip); 1133 ret = gpiochip_remove(&nmk_chip->chip);
1129 return -ENOSYS; 1134 return -ENOSYS;
1130 } 1135 }
1131 1136
1132 nmk_gpio_init_irq(nmk_chip); 1137 nmk_gpio_init_irq(nmk_chip);
1133 1138
1134 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); 1139 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1135 1140
1136 return 0; 1141 return 0;
1137 } 1142 }
1138 1143
1139 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev) 1144 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1140 { 1145 {
1141 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1146 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1142 1147
1143 return npct->soc->ngroups; 1148 return npct->soc->ngroups;
1144 } 1149 }
1145 1150
1146 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev, 1151 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1147 unsigned selector) 1152 unsigned selector)
1148 { 1153 {
1149 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1154 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1150 1155
1151 return npct->soc->groups[selector].name; 1156 return npct->soc->groups[selector].name;
1152 } 1157 }
1153 1158
1154 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 1159 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1155 const unsigned **pins, 1160 const unsigned **pins,
1156 unsigned *num_pins) 1161 unsigned *num_pins)
1157 { 1162 {
1158 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1163 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1159 1164
1160 *pins = npct->soc->groups[selector].pins; 1165 *pins = npct->soc->groups[selector].pins;
1161 *num_pins = npct->soc->groups[selector].npins; 1166 *num_pins = npct->soc->groups[selector].npins;
1162 return 0; 1167 return 0;
1163 } 1168 }
1164 1169
1165 static struct pinctrl_gpio_range * 1170 static struct pinctrl_gpio_range *
1166 nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset) 1171 nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset)
1167 { 1172 {
1168 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1173 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1169 int i; 1174 int i;
1170 1175
1171 for (i = 0; i < npct->soc->gpio_num_ranges; i++) { 1176 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1172 struct pinctrl_gpio_range *range; 1177 struct pinctrl_gpio_range *range;
1173 1178
1174 range = &npct->soc->gpio_ranges[i]; 1179 range = &npct->soc->gpio_ranges[i];
1175 if (offset >= range->pin_base && 1180 if (offset >= range->pin_base &&
1176 offset <= (range->pin_base + range->npins - 1)) 1181 offset <= (range->pin_base + range->npins - 1))
1177 return range; 1182 return range;
1178 } 1183 }
1179 return NULL; 1184 return NULL;
1180 } 1185 }
1181 1186
1182 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 1187 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1183 unsigned offset) 1188 unsigned offset)
1184 { 1189 {
1185 struct pinctrl_gpio_range *range; 1190 struct pinctrl_gpio_range *range;
1186 struct gpio_chip *chip; 1191 struct gpio_chip *chip;
1187 1192
1188 range = nmk_match_gpio_range(pctldev, offset); 1193 range = nmk_match_gpio_range(pctldev, offset);
1189 if (!range || !range->gc) { 1194 if (!range || !range->gc) {
1190 seq_printf(s, "invalid pin offset"); 1195 seq_printf(s, "invalid pin offset");
1191 return; 1196 return;
1192 } 1197 }
1193 chip = range->gc; 1198 chip = range->gc;
1194 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset); 1199 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
1195 } 1200 }
1196 1201
1197 static void nmk_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, 1202 static void nmk_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
1198 struct pinctrl_map *map, unsigned num_maps) 1203 struct pinctrl_map *map, unsigned num_maps)
1199 { 1204 {
1200 int i; 1205 int i;
1201 1206
1202 for (i = 0; i < num_maps; i++) 1207 for (i = 0; i < num_maps; i++)
1203 if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 1208 if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
1204 kfree(map[i].data.configs.configs); 1209 kfree(map[i].data.configs.configs);
1205 kfree(map); 1210 kfree(map);
1206 } 1211 }
1207 1212
1208 static int nmk_dt_reserve_map(struct pinctrl_map **map, unsigned *reserved_maps, 1213 static int nmk_dt_reserve_map(struct pinctrl_map **map, unsigned *reserved_maps,
1209 unsigned *num_maps, unsigned reserve) 1214 unsigned *num_maps, unsigned reserve)
1210 { 1215 {
1211 unsigned old_num = *reserved_maps; 1216 unsigned old_num = *reserved_maps;
1212 unsigned new_num = *num_maps + reserve; 1217 unsigned new_num = *num_maps + reserve;
1213 struct pinctrl_map *new_map; 1218 struct pinctrl_map *new_map;
1214 1219
1215 if (old_num >= new_num) 1220 if (old_num >= new_num)
1216 return 0; 1221 return 0;
1217 1222
1218 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); 1223 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
1219 if (!new_map) 1224 if (!new_map)
1220 return -ENOMEM; 1225 return -ENOMEM;
1221 1226
1222 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); 1227 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
1223 1228
1224 *map = new_map; 1229 *map = new_map;
1225 *reserved_maps = new_num; 1230 *reserved_maps = new_num;
1226 1231
1227 return 0; 1232 return 0;
1228 } 1233 }
1229 1234
1230 static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, 1235 static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
1231 unsigned *num_maps, const char *group, 1236 unsigned *num_maps, const char *group,
1232 const char *function) 1237 const char *function)
1233 { 1238 {
1234 if (*num_maps == *reserved_maps) 1239 if (*num_maps == *reserved_maps)
1235 return -ENOSPC; 1240 return -ENOSPC;
1236 1241
1237 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 1242 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
1238 (*map)[*num_maps].data.mux.group = group; 1243 (*map)[*num_maps].data.mux.group = group;
1239 (*map)[*num_maps].data.mux.function = function; 1244 (*map)[*num_maps].data.mux.function = function;
1240 (*num_maps)++; 1245 (*num_maps)++;
1241 1246
1242 return 0; 1247 return 0;
1243 } 1248 }
1244 1249
1245 static int nmk_dt_add_map_configs(struct pinctrl_map **map, 1250 static int nmk_dt_add_map_configs(struct pinctrl_map **map,
1246 unsigned *reserved_maps, 1251 unsigned *reserved_maps,
1247 unsigned *num_maps, const char *group, 1252 unsigned *num_maps, const char *group,
1248 unsigned long *configs, unsigned num_configs) 1253 unsigned long *configs, unsigned num_configs)
1249 { 1254 {
1250 unsigned long *dup_configs; 1255 unsigned long *dup_configs;
1251 1256
1252 if (*num_maps == *reserved_maps) 1257 if (*num_maps == *reserved_maps)
1253 return -ENOSPC; 1258 return -ENOSPC;
1254 1259
1255 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), 1260 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
1256 GFP_KERNEL); 1261 GFP_KERNEL);
1257 if (!dup_configs) 1262 if (!dup_configs)
1258 return -ENOMEM; 1263 return -ENOMEM;
1259 1264
1260 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN; 1265 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
1261 1266
1262 (*map)[*num_maps].data.configs.group_or_pin = group; 1267 (*map)[*num_maps].data.configs.group_or_pin = group;
1263 (*map)[*num_maps].data.configs.configs = dup_configs; 1268 (*map)[*num_maps].data.configs.configs = dup_configs;
1264 (*map)[*num_maps].data.configs.num_configs = num_configs; 1269 (*map)[*num_maps].data.configs.num_configs = num_configs;
1265 (*num_maps)++; 1270 (*num_maps)++;
1266 1271
1267 return 0; 1272 return 0;
1268 } 1273 }
1269 1274
1270 #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, } 1275 #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, }
1271 #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \ 1276 #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \
1272 .size = ARRAY_SIZE(y), } 1277 .size = ARRAY_SIZE(y), }
1273 1278
1274 static const unsigned long nmk_pin_input_modes[] = { 1279 static const unsigned long nmk_pin_input_modes[] = {
1275 PIN_INPUT_NOPULL, 1280 PIN_INPUT_NOPULL,
1276 PIN_INPUT_PULLUP, 1281 PIN_INPUT_PULLUP,
1277 PIN_INPUT_PULLDOWN, 1282 PIN_INPUT_PULLDOWN,
1278 }; 1283 };
1279 1284
1280 static const unsigned long nmk_pin_output_modes[] = { 1285 static const unsigned long nmk_pin_output_modes[] = {
1281 PIN_OUTPUT_LOW, 1286 PIN_OUTPUT_LOW,
1282 PIN_OUTPUT_HIGH, 1287 PIN_OUTPUT_HIGH,
1283 PIN_DIR_OUTPUT, 1288 PIN_DIR_OUTPUT,
1284 }; 1289 };
1285 1290
1286 static const unsigned long nmk_pin_sleep_modes[] = { 1291 static const unsigned long nmk_pin_sleep_modes[] = {
1287 PIN_SLEEPMODE_DISABLED, 1292 PIN_SLEEPMODE_DISABLED,
1288 PIN_SLEEPMODE_ENABLED, 1293 PIN_SLEEPMODE_ENABLED,
1289 }; 1294 };
1290 1295
1291 static const unsigned long nmk_pin_sleep_input_modes[] = { 1296 static const unsigned long nmk_pin_sleep_input_modes[] = {
1292 PIN_SLPM_INPUT_NOPULL, 1297 PIN_SLPM_INPUT_NOPULL,
1293 PIN_SLPM_INPUT_PULLUP, 1298 PIN_SLPM_INPUT_PULLUP,
1294 PIN_SLPM_INPUT_PULLDOWN, 1299 PIN_SLPM_INPUT_PULLDOWN,
1295 PIN_SLPM_DIR_INPUT, 1300 PIN_SLPM_DIR_INPUT,
1296 }; 1301 };
1297 1302
1298 static const unsigned long nmk_pin_sleep_output_modes[] = { 1303 static const unsigned long nmk_pin_sleep_output_modes[] = {
1299 PIN_SLPM_OUTPUT_LOW, 1304 PIN_SLPM_OUTPUT_LOW,
1300 PIN_SLPM_OUTPUT_HIGH, 1305 PIN_SLPM_OUTPUT_HIGH,
1301 PIN_SLPM_DIR_OUTPUT, 1306 PIN_SLPM_DIR_OUTPUT,
1302 }; 1307 };
1303 1308
1304 static const unsigned long nmk_pin_sleep_wakeup_modes[] = { 1309 static const unsigned long nmk_pin_sleep_wakeup_modes[] = {
1305 PIN_SLPM_WAKEUP_DISABLE, 1310 PIN_SLPM_WAKEUP_DISABLE,
1306 PIN_SLPM_WAKEUP_ENABLE, 1311 PIN_SLPM_WAKEUP_ENABLE,
1307 }; 1312 };
1308 1313
1309 static const unsigned long nmk_pin_gpio_modes[] = { 1314 static const unsigned long nmk_pin_gpio_modes[] = {
1310 PIN_GPIOMODE_DISABLED, 1315 PIN_GPIOMODE_DISABLED,
1311 PIN_GPIOMODE_ENABLED, 1316 PIN_GPIOMODE_ENABLED,
1312 }; 1317 };
1313 1318
1314 static const unsigned long nmk_pin_sleep_pdis_modes[] = { 1319 static const unsigned long nmk_pin_sleep_pdis_modes[] = {
1315 PIN_SLPM_PDIS_DISABLED, 1320 PIN_SLPM_PDIS_DISABLED,
1316 PIN_SLPM_PDIS_ENABLED, 1321 PIN_SLPM_PDIS_ENABLED,
1317 }; 1322 };
1318 1323
1319 struct nmk_cfg_param { 1324 struct nmk_cfg_param {
1320 const char *property; 1325 const char *property;
1321 unsigned long config; 1326 unsigned long config;
1322 const unsigned long *choice; 1327 const unsigned long *choice;
1323 int size; 1328 int size;
1324 }; 1329 };
1325 1330
1326 static const struct nmk_cfg_param nmk_cfg_params[] = { 1331 static const struct nmk_cfg_param nmk_cfg_params[] = {
1327 NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes), 1332 NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes),
1328 NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes), 1333 NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes),
1329 NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes), 1334 NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes),
1330 NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes), 1335 NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes),
1331 NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes), 1336 NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes),
1332 NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes), 1337 NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes),
1333 NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes), 1338 NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes),
1334 NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes), 1339 NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes),
1335 }; 1340 };
1336 1341
1337 static int nmk_dt_pin_config(int index, int val, unsigned long *config) 1342 static int nmk_dt_pin_config(int index, int val, unsigned long *config)
1338 { 1343 {
1339 int ret = 0; 1344 int ret = 0;
1340 1345
1341 if (nmk_cfg_params[index].choice == NULL) 1346 if (nmk_cfg_params[index].choice == NULL)
1342 *config = nmk_cfg_params[index].config; 1347 *config = nmk_cfg_params[index].config;
1343 else { 1348 else {
1344 /* test if out of range */ 1349 /* test if out of range */
1345 if (val < nmk_cfg_params[index].size) { 1350 if (val < nmk_cfg_params[index].size) {
1346 *config = nmk_cfg_params[index].config | 1351 *config = nmk_cfg_params[index].config |
1347 nmk_cfg_params[index].choice[val]; 1352 nmk_cfg_params[index].choice[val];
1348 } 1353 }
1349 } 1354 }
1350 return ret; 1355 return ret;
1351 } 1356 }
1352 1357
1353 static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name) 1358 static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name)
1354 { 1359 {
1355 int i, pin_number; 1360 int i, pin_number;
1356 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1361 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1357 1362
1358 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1) 1363 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
1359 for (i = 0; i < npct->soc->npins; i++) 1364 for (i = 0; i < npct->soc->npins; i++)
1360 if (npct->soc->pins[i].number == pin_number) 1365 if (npct->soc->pins[i].number == pin_number)
1361 return npct->soc->pins[i].name; 1366 return npct->soc->pins[i].name;
1362 return NULL; 1367 return NULL;
1363 } 1368 }
1364 1369
1365 static bool nmk_pinctrl_dt_get_config(struct device_node *np, 1370 static bool nmk_pinctrl_dt_get_config(struct device_node *np,
1366 unsigned long *configs) 1371 unsigned long *configs)
1367 { 1372 {
1368 bool has_config = 0; 1373 bool has_config = 0;
1369 unsigned long cfg = 0; 1374 unsigned long cfg = 0;
1370 int i, val, ret; 1375 int i, val, ret;
1371 1376
1372 for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) { 1377 for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) {
1373 ret = of_property_read_u32(np, 1378 ret = of_property_read_u32(np,
1374 nmk_cfg_params[i].property, &val); 1379 nmk_cfg_params[i].property, &val);
1375 if (ret != -EINVAL) { 1380 if (ret != -EINVAL) {
1376 if (nmk_dt_pin_config(i, val, &cfg) == 0) { 1381 if (nmk_dt_pin_config(i, val, &cfg) == 0) {
1377 *configs |= cfg; 1382 *configs |= cfg;
1378 has_config = 1; 1383 has_config = 1;
1379 } 1384 }
1380 } 1385 }
1381 } 1386 }
1382 1387
1383 return has_config; 1388 return has_config;
1384 } 1389 }
1385 1390
1386 static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 1391 static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
1387 struct device_node *np, 1392 struct device_node *np,
1388 struct pinctrl_map **map, 1393 struct pinctrl_map **map,
1389 unsigned *reserved_maps, 1394 unsigned *reserved_maps,
1390 unsigned *num_maps) 1395 unsigned *num_maps)
1391 { 1396 {
1392 int ret; 1397 int ret;
1393 const char *function = NULL; 1398 const char *function = NULL;
1394 unsigned long configs = 0; 1399 unsigned long configs = 0;
1395 bool has_config = 0; 1400 bool has_config = 0;
1396 unsigned reserve = 0; 1401 unsigned reserve = 0;
1397 struct property *prop; 1402 struct property *prop;
1398 const char *group, *gpio_name; 1403 const char *group, *gpio_name;
1399 struct device_node *np_config; 1404 struct device_node *np_config;
1400 1405
1401 ret = of_property_read_string(np, "ste,function", &function); 1406 ret = of_property_read_string(np, "ste,function", &function);
1402 if (ret >= 0) 1407 if (ret >= 0)
1403 reserve = 1; 1408 reserve = 1;
1404 1409
1405 has_config = nmk_pinctrl_dt_get_config(np, &configs); 1410 has_config = nmk_pinctrl_dt_get_config(np, &configs);
1406 1411
1407 np_config = of_parse_phandle(np, "ste,config", 0); 1412 np_config = of_parse_phandle(np, "ste,config", 0);
1408 if (np_config) 1413 if (np_config)
1409 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs); 1414 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
1410 1415
1411 ret = of_property_count_strings(np, "ste,pins"); 1416 ret = of_property_count_strings(np, "ste,pins");
1412 if (ret < 0) 1417 if (ret < 0)
1413 goto exit; 1418 goto exit;
1414 1419
1415 if (has_config) 1420 if (has_config)
1416 reserve++; 1421 reserve++;
1417 1422
1418 reserve *= ret; 1423 reserve *= ret;
1419 1424
1420 ret = nmk_dt_reserve_map(map, reserved_maps, num_maps, reserve); 1425 ret = nmk_dt_reserve_map(map, reserved_maps, num_maps, reserve);
1421 if (ret < 0) 1426 if (ret < 0)
1422 goto exit; 1427 goto exit;
1423 1428
1424 of_property_for_each_string(np, "ste,pins", prop, group) { 1429 of_property_for_each_string(np, "ste,pins", prop, group) {
1425 if (function) { 1430 if (function) {
1426 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps, 1431 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
1427 group, function); 1432 group, function);
1428 if (ret < 0) 1433 if (ret < 0)
1429 goto exit; 1434 goto exit;
1430 } 1435 }
1431 if (has_config) { 1436 if (has_config) {
1432 gpio_name = nmk_find_pin_name(pctldev, group); 1437 gpio_name = nmk_find_pin_name(pctldev, group);
1433 1438
1434 ret = nmk_dt_add_map_configs(map, reserved_maps, num_maps, 1439 ret = nmk_dt_add_map_configs(map, reserved_maps, num_maps,
1435 gpio_name, &configs, 1); 1440 gpio_name, &configs, 1);
1436 if (ret < 0) 1441 if (ret < 0)
1437 goto exit; 1442 goto exit;
1438 } 1443 }
1439 1444
1440 } 1445 }
1441 exit: 1446 exit:
1442 return ret; 1447 return ret;
1443 } 1448 }
1444 1449
1445 static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 1450 static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
1446 struct device_node *np_config, 1451 struct device_node *np_config,
1447 struct pinctrl_map **map, unsigned *num_maps) 1452 struct pinctrl_map **map, unsigned *num_maps)
1448 { 1453 {
1449 unsigned reserved_maps; 1454 unsigned reserved_maps;
1450 struct device_node *np; 1455 struct device_node *np;
1451 int ret; 1456 int ret;
1452 1457
1453 reserved_maps = 0; 1458 reserved_maps = 0;
1454 *map = NULL; 1459 *map = NULL;
1455 *num_maps = 0; 1460 *num_maps = 0;
1456 1461
1457 for_each_child_of_node(np_config, np) { 1462 for_each_child_of_node(np_config, np) {
1458 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map, 1463 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
1459 &reserved_maps, num_maps); 1464 &reserved_maps, num_maps);
1460 if (ret < 0) { 1465 if (ret < 0) {
1461 nmk_pinctrl_dt_free_map(pctldev, *map, *num_maps); 1466 nmk_pinctrl_dt_free_map(pctldev, *map, *num_maps);
1462 return ret; 1467 return ret;
1463 } 1468 }
1464 } 1469 }
1465 1470
1466 return 0; 1471 return 0;
1467 } 1472 }
1468 1473
1469 static const struct pinctrl_ops nmk_pinctrl_ops = { 1474 static const struct pinctrl_ops nmk_pinctrl_ops = {
1470 .get_groups_count = nmk_get_groups_cnt, 1475 .get_groups_count = nmk_get_groups_cnt,
1471 .get_group_name = nmk_get_group_name, 1476 .get_group_name = nmk_get_group_name,
1472 .get_group_pins = nmk_get_group_pins, 1477 .get_group_pins = nmk_get_group_pins,
1473 .pin_dbg_show = nmk_pin_dbg_show, 1478 .pin_dbg_show = nmk_pin_dbg_show,
1474 .dt_node_to_map = nmk_pinctrl_dt_node_to_map, 1479 .dt_node_to_map = nmk_pinctrl_dt_node_to_map,
1475 .dt_free_map = nmk_pinctrl_dt_free_map, 1480 .dt_free_map = nmk_pinctrl_dt_free_map,
1476 }; 1481 };
1477 1482
1478 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 1483 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1479 { 1484 {
1480 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1485 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1481 1486
1482 return npct->soc->nfunctions; 1487 return npct->soc->nfunctions;
1483 } 1488 }
1484 1489
1485 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev, 1490 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1486 unsigned function) 1491 unsigned function)
1487 { 1492 {
1488 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1493 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1489 1494
1490 return npct->soc->functions[function].name; 1495 return npct->soc->functions[function].name;
1491 } 1496 }
1492 1497
1493 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev, 1498 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1494 unsigned function, 1499 unsigned function,
1495 const char * const **groups, 1500 const char * const **groups,
1496 unsigned * const num_groups) 1501 unsigned * const num_groups)
1497 { 1502 {
1498 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1503 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1499 1504
1500 *groups = npct->soc->functions[function].groups; 1505 *groups = npct->soc->functions[function].groups;
1501 *num_groups = npct->soc->functions[function].ngroups; 1506 *num_groups = npct->soc->functions[function].ngroups;
1502 1507
1503 return 0; 1508 return 0;
1504 } 1509 }
1505 1510
1506 static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, 1511 static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
1507 unsigned group) 1512 unsigned group)
1508 { 1513 {
1509 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1514 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1510 const struct nmk_pingroup *g; 1515 const struct nmk_pingroup *g;
1511 static unsigned int slpm[NUM_BANKS]; 1516 static unsigned int slpm[NUM_BANKS];
1512 unsigned long flags = 0; 1517 unsigned long flags = 0;
1513 bool glitch; 1518 bool glitch;
1514 int ret = -EINVAL; 1519 int ret = -EINVAL;
1515 int i; 1520 int i;
1516 1521
1517 g = &npct->soc->groups[group]; 1522 g = &npct->soc->groups[group];
1518 1523
1519 if (g->altsetting < 0) 1524 if (g->altsetting < 0)
1520 return -EINVAL; 1525 return -EINVAL;
1521 1526
1522 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins); 1527 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1523 1528
1524 /* 1529 /*
1525 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1, 1530 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
1526 * we may pass through an undesired state. In this case we take 1531 * we may pass through an undesired state. In this case we take
1527 * some extra care. 1532 * some extra care.
1528 * 1533 *
1529 * Safe sequence used to switch IOs between GPIO and Alternate-C mode: 1534 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
1530 * - Save SLPM registers (since we have a shadow register in the 1535 * - Save SLPM registers (since we have a shadow register in the
1531 * nmk_chip we're using that as backup) 1536 * nmk_chip we're using that as backup)
1532 * - Set SLPM=0 for the IOs you want to switch and others to 1 1537 * - Set SLPM=0 for the IOs you want to switch and others to 1
1533 * - Configure the GPIO registers for the IOs that are being switched 1538 * - Configure the GPIO registers for the IOs that are being switched
1534 * - Set IOFORCE=1 1539 * - Set IOFORCE=1
1535 * - Modify the AFLSA/B registers for the IOs that are being switched 1540 * - Modify the AFLSA/B registers for the IOs that are being switched
1536 * - Set IOFORCE=0 1541 * - Set IOFORCE=0
1537 * - Restore SLPM registers 1542 * - Restore SLPM registers
1538 * - Any spurious wake up event during switch sequence to be ignored 1543 * - Any spurious wake up event during switch sequence to be ignored
1539 * and cleared 1544 * and cleared
1540 * 1545 *
1541 * We REALLY need to save ALL slpm registers, because the external 1546 * We REALLY need to save ALL slpm registers, because the external
1542 * IOFORCE will switch *all* ports to their sleepmode setting to as 1547 * IOFORCE will switch *all* ports to their sleepmode setting to as
1543 * to avoid glitches. (Not just one port!) 1548 * to avoid glitches. (Not just one port!)
1544 */ 1549 */
1545 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C); 1550 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
1546 1551
1547 if (glitch) { 1552 if (glitch) {
1548 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 1553 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1549 1554
1550 /* Initially don't put any pins to sleep when switching */ 1555 /* Initially don't put any pins to sleep when switching */
1551 memset(slpm, 0xff, sizeof(slpm)); 1556 memset(slpm, 0xff, sizeof(slpm));
1552 1557
1553 /* 1558 /*
1554 * Then mask the pins that need to be sleeping now when we're 1559 * Then mask the pins that need to be sleeping now when we're
1555 * switching to the ALT C function. 1560 * switching to the ALT C function.
1556 */ 1561 */
1557 for (i = 0; i < g->npins; i++) 1562 for (i = 0; i < g->npins; i++)
1558 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]); 1563 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1559 nmk_gpio_glitch_slpm_init(slpm); 1564 nmk_gpio_glitch_slpm_init(slpm);
1560 } 1565 }
1561 1566
1562 for (i = 0; i < g->npins; i++) { 1567 for (i = 0; i < g->npins; i++) {
1563 struct pinctrl_gpio_range *range; 1568 struct pinctrl_gpio_range *range;
1564 struct nmk_gpio_chip *nmk_chip; 1569 struct nmk_gpio_chip *nmk_chip;
1565 struct gpio_chip *chip; 1570 struct gpio_chip *chip;
1566 unsigned bit; 1571 unsigned bit;
1567 1572
1568 range = nmk_match_gpio_range(pctldev, g->pins[i]); 1573 range = nmk_match_gpio_range(pctldev, g->pins[i]);
1569 if (!range) { 1574 if (!range) {
1570 dev_err(npct->dev, 1575 dev_err(npct->dev,
1571 "invalid pin offset %d in group %s at index %d\n", 1576 "invalid pin offset %d in group %s at index %d\n",
1572 g->pins[i], g->name, i); 1577 g->pins[i], g->name, i);
1573 goto out_glitch; 1578 goto out_glitch;
1574 } 1579 }
1575 if (!range->gc) { 1580 if (!range->gc) {
1576 dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n", 1581 dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n",
1577 g->pins[i], g->name, i); 1582 g->pins[i], g->name, i);
1578 goto out_glitch; 1583 goto out_glitch;
1579 } 1584 }
1580 chip = range->gc; 1585 chip = range->gc;
1581 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); 1586 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1582 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting); 1587 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1583 1588
1584 clk_enable(nmk_chip->clk); 1589 clk_enable(nmk_chip->clk);
1585 bit = g->pins[i] % NMK_GPIO_PER_CHIP; 1590 bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1586 /* 1591 /*
1587 * If the pin is switching to altfunc, and there was an 1592 * If the pin is switching to altfunc, and there was an
1588 * interrupt installed on it which has been lazy disabled, 1593 * interrupt installed on it which has been lazy disabled,
1589 * actually mask the interrupt to prevent spurious interrupts 1594 * actually mask the interrupt to prevent spurious interrupts
1590 * that would occur while the pin is under control of the 1595 * that would occur while the pin is under control of the
1591 * peripheral. Only SKE does this. 1596 * peripheral. Only SKE does this.
1592 */ 1597 */
1593 nmk_gpio_disable_lazy_irq(nmk_chip, bit); 1598 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1594 1599
1595 __nmk_gpio_set_mode_safe(nmk_chip, bit, 1600 __nmk_gpio_set_mode_safe(nmk_chip, bit,
1596 (g->altsetting & NMK_GPIO_ALT_C), glitch); 1601 (g->altsetting & NMK_GPIO_ALT_C), glitch);
1597 clk_disable(nmk_chip->clk); 1602 clk_disable(nmk_chip->clk);
1598 1603
1599 /* 1604 /*
1600 * Call PRCM GPIOCR config function in case ALTC 1605 * Call PRCM GPIOCR config function in case ALTC
1601 * has been selected: 1606 * has been selected:
1602 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers 1607 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
1603 * must be set. 1608 * must be set.
1604 * - If selection is pure ALTC and previous selection was ALTCx, 1609 * - If selection is pure ALTC and previous selection was ALTCx,
1605 * then some bits in PRCM GPIOCR registers must be cleared. 1610 * then some bits in PRCM GPIOCR registers must be cleared.
1606 */ 1611 */
1607 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C) 1612 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
1608 nmk_prcm_altcx_set_mode(npct, g->pins[i], 1613 nmk_prcm_altcx_set_mode(npct, g->pins[i],
1609 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT); 1614 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
1610 } 1615 }
1611 1616
1612 /* When all pins are successfully reconfigured we get here */ 1617 /* When all pins are successfully reconfigured we get here */
1613 ret = 0; 1618 ret = 0;
1614 1619
1615 out_glitch: 1620 out_glitch:
1616 if (glitch) { 1621 if (glitch) {
1617 nmk_gpio_glitch_slpm_restore(slpm); 1622 nmk_gpio_glitch_slpm_restore(slpm);
1618 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 1623 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1619 } 1624 }
1620 1625
1621 return ret; 1626 return ret;
1622 } 1627 }
1623 1628
1624 static void nmk_pmx_disable(struct pinctrl_dev *pctldev, 1629 static void nmk_pmx_disable(struct pinctrl_dev *pctldev,
1625 unsigned function, unsigned group) 1630 unsigned function, unsigned group)
1626 { 1631 {
1627 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1632 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1628 const struct nmk_pingroup *g; 1633 const struct nmk_pingroup *g;
1629 1634
1630 g = &npct->soc->groups[group]; 1635 g = &npct->soc->groups[group];
1631 1636
1632 if (g->altsetting < 0) 1637 if (g->altsetting < 0)
1633 return; 1638 return;
1634 1639
1635 /* Poke out the mux, set the pin to some default state? */ 1640 /* Poke out the mux, set the pin to some default state? */
1636 dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins); 1641 dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins);
1637 } 1642 }
1638 1643
1639 static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev, 1644 static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1640 struct pinctrl_gpio_range *range, 1645 struct pinctrl_gpio_range *range,
1641 unsigned offset) 1646 unsigned offset)
1642 { 1647 {
1643 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1648 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1644 struct nmk_gpio_chip *nmk_chip; 1649 struct nmk_gpio_chip *nmk_chip;
1645 struct gpio_chip *chip; 1650 struct gpio_chip *chip;
1646 unsigned bit; 1651 unsigned bit;
1647 1652
1648 if (!range) { 1653 if (!range) {
1649 dev_err(npct->dev, "invalid range\n"); 1654 dev_err(npct->dev, "invalid range\n");
1650 return -EINVAL; 1655 return -EINVAL;
1651 } 1656 }
1652 if (!range->gc) { 1657 if (!range->gc) {
1653 dev_err(npct->dev, "missing GPIO chip in range\n"); 1658 dev_err(npct->dev, "missing GPIO chip in range\n");
1654 return -EINVAL; 1659 return -EINVAL;
1655 } 1660 }
1656 chip = range->gc; 1661 chip = range->gc;
1657 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); 1662 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1658 1663
1659 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); 1664 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1660 1665
1661 clk_enable(nmk_chip->clk); 1666 clk_enable(nmk_chip->clk);
1662 bit = offset % NMK_GPIO_PER_CHIP; 1667 bit = offset % NMK_GPIO_PER_CHIP;
1663 /* There is no glitch when converting any pin to GPIO */ 1668 /* There is no glitch when converting any pin to GPIO */
1664 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); 1669 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1665 clk_disable(nmk_chip->clk); 1670 clk_disable(nmk_chip->clk);
1666 1671
1667 return 0; 1672 return 0;
1668 } 1673 }
1669 1674
1670 static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev, 1675 static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1671 struct pinctrl_gpio_range *range, 1676 struct pinctrl_gpio_range *range,
1672 unsigned offset) 1677 unsigned offset)
1673 { 1678 {
1674 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1679 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1675 1680
1676 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); 1681 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1677 /* Set the pin to some default state, GPIO is usually default */ 1682 /* Set the pin to some default state, GPIO is usually default */
1678 } 1683 }
1679 1684
1680 static const struct pinmux_ops nmk_pinmux_ops = { 1685 static const struct pinmux_ops nmk_pinmux_ops = {
1681 .get_functions_count = nmk_pmx_get_funcs_cnt, 1686 .get_functions_count = nmk_pmx_get_funcs_cnt,
1682 .get_function_name = nmk_pmx_get_func_name, 1687 .get_function_name = nmk_pmx_get_func_name,
1683 .get_function_groups = nmk_pmx_get_func_groups, 1688 .get_function_groups = nmk_pmx_get_func_groups,
1684 .enable = nmk_pmx_enable, 1689 .enable = nmk_pmx_enable,
1685 .disable = nmk_pmx_disable, 1690 .disable = nmk_pmx_disable,
1686 .gpio_request_enable = nmk_gpio_request_enable, 1691 .gpio_request_enable = nmk_gpio_request_enable,
1687 .gpio_disable_free = nmk_gpio_disable_free, 1692 .gpio_disable_free = nmk_gpio_disable_free,
1688 }; 1693 };
1689 1694
1690 static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, 1695 static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
1691 unsigned long *config) 1696 unsigned long *config)
1692 { 1697 {
1693 /* Not implemented */ 1698 /* Not implemented */
1694 return -EINVAL; 1699 return -EINVAL;
1695 } 1700 }
1696 1701
1697 static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, 1702 static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1698 unsigned long *configs, unsigned num_configs) 1703 unsigned long *configs, unsigned num_configs)
1699 { 1704 {
1700 static const char *pullnames[] = { 1705 static const char *pullnames[] = {
1701 [NMK_GPIO_PULL_NONE] = "none", 1706 [NMK_GPIO_PULL_NONE] = "none",
1702 [NMK_GPIO_PULL_UP] = "up", 1707 [NMK_GPIO_PULL_UP] = "up",
1703 [NMK_GPIO_PULL_DOWN] = "down", 1708 [NMK_GPIO_PULL_DOWN] = "down",
1704 [3] /* illegal */ = "??" 1709 [3] /* illegal */ = "??"
1705 }; 1710 };
1706 static const char *slpmnames[] = { 1711 static const char *slpmnames[] = {
1707 [NMK_GPIO_SLPM_INPUT] = "input/wakeup", 1712 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
1708 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", 1713 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
1709 }; 1714 };
1710 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1715 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1711 struct nmk_gpio_chip *nmk_chip; 1716 struct nmk_gpio_chip *nmk_chip;
1712 struct pinctrl_gpio_range *range; 1717 struct pinctrl_gpio_range *range;
1713 struct gpio_chip *chip; 1718 struct gpio_chip *chip;
1714 unsigned bit; 1719 unsigned bit;
1715 pin_cfg_t cfg; 1720 pin_cfg_t cfg;
1716 int pull, slpm, output, val, i; 1721 int pull, slpm, output, val, i;
1717 bool lowemi, gpiomode, sleep; 1722 bool lowemi, gpiomode, sleep;
1718 1723
1719 range = nmk_match_gpio_range(pctldev, pin); 1724 range = nmk_match_gpio_range(pctldev, pin);
1720 if (!range) { 1725 if (!range) {
1721 dev_err(npct->dev, "invalid pin offset %d\n", pin); 1726 dev_err(npct->dev, "invalid pin offset %d\n", pin);
1722 return -EINVAL; 1727 return -EINVAL;
1723 } 1728 }
1724 if (!range->gc) { 1729 if (!range->gc) {
1725 dev_err(npct->dev, "GPIO chip missing in range for pin %d\n", 1730 dev_err(npct->dev, "GPIO chip missing in range for pin %d\n",
1726 pin); 1731 pin);
1727 return -EINVAL; 1732 return -EINVAL;
1728 } 1733 }
1729 chip = range->gc; 1734 chip = range->gc;
1730 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); 1735 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1731 1736
1732 for (i = 0; i < num_configs; i++) { 1737 for (i = 0; i < num_configs; i++) {
1733 /* 1738 /*
1734 * The pin config contains pin number and altfunction fields, 1739 * The pin config contains pin number and altfunction fields,
1735 * here we just ignore that part. It's being handled by the 1740 * here we just ignore that part. It's being handled by the
1736 * framework and pinmux callback respectively. 1741 * framework and pinmux callback respectively.
1737 */ 1742 */
1738 cfg = (pin_cfg_t) configs[i]; 1743 cfg = (pin_cfg_t) configs[i];
1739 pull = PIN_PULL(cfg); 1744 pull = PIN_PULL(cfg);
1740 slpm = PIN_SLPM(cfg); 1745 slpm = PIN_SLPM(cfg);
1741 output = PIN_DIR(cfg); 1746 output = PIN_DIR(cfg);
1742 val = PIN_VAL(cfg); 1747 val = PIN_VAL(cfg);
1743 lowemi = PIN_LOWEMI(cfg); 1748 lowemi = PIN_LOWEMI(cfg);
1744 gpiomode = PIN_GPIOMODE(cfg); 1749 gpiomode = PIN_GPIOMODE(cfg);
1745 sleep = PIN_SLEEPMODE(cfg); 1750 sleep = PIN_SLEEPMODE(cfg);
1746 1751
1747 if (sleep) { 1752 if (sleep) {
1748 int slpm_pull = PIN_SLPM_PULL(cfg); 1753 int slpm_pull = PIN_SLPM_PULL(cfg);
1749 int slpm_output = PIN_SLPM_DIR(cfg); 1754 int slpm_output = PIN_SLPM_DIR(cfg);
1750 int slpm_val = PIN_SLPM_VAL(cfg); 1755 int slpm_val = PIN_SLPM_VAL(cfg);
1751 1756
1752 /* All pins go into GPIO mode at sleep */ 1757 /* All pins go into GPIO mode at sleep */
1753 gpiomode = true; 1758 gpiomode = true;
1754 1759
1755 /* 1760 /*
1756 * The SLPM_* values are normal values + 1 to allow zero 1761 * The SLPM_* values are normal values + 1 to allow zero
1757 * to mean "same as normal". 1762 * to mean "same as normal".
1758 */ 1763 */
1759 if (slpm_pull) 1764 if (slpm_pull)
1760 pull = slpm_pull - 1; 1765 pull = slpm_pull - 1;
1761 if (slpm_output) 1766 if (slpm_output)
1762 output = slpm_output - 1; 1767 output = slpm_output - 1;
1763 if (slpm_val) 1768 if (slpm_val)
1764 val = slpm_val - 1; 1769 val = slpm_val - 1;
1765 1770
1766 dev_dbg(nmk_chip->chip.dev, 1771 dev_dbg(nmk_chip->chip.dev,
1767 "pin %d: sleep pull %s, dir %s, val %s\n", 1772 "pin %d: sleep pull %s, dir %s, val %s\n",
1768 pin, 1773 pin,
1769 slpm_pull ? pullnames[pull] : "same", 1774 slpm_pull ? pullnames[pull] : "same",
1770 slpm_output ? (output ? "output" : "input") 1775 slpm_output ? (output ? "output" : "input")
1771 : "same", 1776 : "same",
1772 slpm_val ? (val ? "high" : "low") : "same"); 1777 slpm_val ? (val ? "high" : "low") : "same");
1773 } 1778 }
1774 1779
1775 dev_dbg(nmk_chip->chip.dev, 1780 dev_dbg(nmk_chip->chip.dev,
1776 "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", 1781 "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1777 pin, cfg, pullnames[pull], slpmnames[slpm], 1782 pin, cfg, pullnames[pull], slpmnames[slpm],
1778 output ? "output " : "input", 1783 output ? "output " : "input",
1779 output ? (val ? "high" : "low") : "", 1784 output ? (val ? "high" : "low") : "",
1780 lowemi ? "on" : "off"); 1785 lowemi ? "on" : "off");
1781 1786
1782 clk_enable(nmk_chip->clk); 1787 clk_enable(nmk_chip->clk);
1783 bit = pin % NMK_GPIO_PER_CHIP; 1788 bit = pin % NMK_GPIO_PER_CHIP;
1784 if (gpiomode) 1789 if (gpiomode)
1785 /* No glitch when going to GPIO mode */ 1790 /* No glitch when going to GPIO mode */
1786 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); 1791 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1787 if (output) 1792 if (output)
1788 __nmk_gpio_make_output(nmk_chip, bit, val); 1793 __nmk_gpio_make_output(nmk_chip, bit, val);
1789 else { 1794 else {
1790 __nmk_gpio_make_input(nmk_chip, bit); 1795 __nmk_gpio_make_input(nmk_chip, bit);
1791 __nmk_gpio_set_pull(nmk_chip, bit, pull); 1796 __nmk_gpio_set_pull(nmk_chip, bit, pull);
1792 } 1797 }
1793 /* TODO: isn't this only applicable on output pins? */ 1798 /* TODO: isn't this only applicable on output pins? */
1794 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); 1799 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1795 1800
1796 __nmk_gpio_set_slpm(nmk_chip, bit, slpm); 1801 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1797 clk_disable(nmk_chip->clk); 1802 clk_disable(nmk_chip->clk);
1798 } /* for each config */ 1803 } /* for each config */
1799 1804
1800 return 0; 1805 return 0;
1801 } 1806 }
1802 1807
1803 static const struct pinconf_ops nmk_pinconf_ops = { 1808 static const struct pinconf_ops nmk_pinconf_ops = {
1804 .pin_config_get = nmk_pin_config_get, 1809 .pin_config_get = nmk_pin_config_get,
1805 .pin_config_set = nmk_pin_config_set, 1810 .pin_config_set = nmk_pin_config_set,
1806 }; 1811 };
1807 1812
1808 static struct pinctrl_desc nmk_pinctrl_desc = { 1813 static struct pinctrl_desc nmk_pinctrl_desc = {
1809 .name = "pinctrl-nomadik", 1814 .name = "pinctrl-nomadik",
1810 .pctlops = &nmk_pinctrl_ops, 1815 .pctlops = &nmk_pinctrl_ops,
1811 .pmxops = &nmk_pinmux_ops, 1816 .pmxops = &nmk_pinmux_ops,
1812 .confops = &nmk_pinconf_ops, 1817 .confops = &nmk_pinconf_ops,
1813 .owner = THIS_MODULE, 1818 .owner = THIS_MODULE,
1814 }; 1819 };
1815 1820
1816 static const struct of_device_id nmk_pinctrl_match[] = { 1821 static const struct of_device_id nmk_pinctrl_match[] = {
1817 { 1822 {
1818 .compatible = "stericsson,stn8815-pinctrl", 1823 .compatible = "stericsson,stn8815-pinctrl",
1819 .data = (void *)PINCTRL_NMK_STN8815, 1824 .data = (void *)PINCTRL_NMK_STN8815,
1820 }, 1825 },
1821 { 1826 {
1822 .compatible = "stericsson,db8500-pinctrl", 1827 .compatible = "stericsson,db8500-pinctrl",
1823 .data = (void *)PINCTRL_NMK_DB8500, 1828 .data = (void *)PINCTRL_NMK_DB8500,
1824 }, 1829 },
1825 { 1830 {
1826 .compatible = "stericsson,db8540-pinctrl", 1831 .compatible = "stericsson,db8540-pinctrl",
1827 .data = (void *)PINCTRL_NMK_DB8540, 1832 .data = (void *)PINCTRL_NMK_DB8540,
1828 }, 1833 },
1829 {}, 1834 {},
1830 }; 1835 };
1831 1836
1832 static int nmk_pinctrl_suspend(struct platform_device *pdev, pm_message_t state) 1837 static int nmk_pinctrl_suspend(struct platform_device *pdev, pm_message_t state)
1833 { 1838 {
1834 struct nmk_pinctrl *npct; 1839 struct nmk_pinctrl *npct;
1835 1840
1836 npct = platform_get_drvdata(pdev); 1841 npct = platform_get_drvdata(pdev);
1837 if (!npct) 1842 if (!npct)
1838 return -EINVAL; 1843 return -EINVAL;
1839 1844
1840 return pinctrl_force_sleep(npct->pctl); 1845 return pinctrl_force_sleep(npct->pctl);
1841 } 1846 }
1842 1847
1843 static int nmk_pinctrl_resume(struct platform_device *pdev) 1848 static int nmk_pinctrl_resume(struct platform_device *pdev)
1844 { 1849 {
1845 struct nmk_pinctrl *npct; 1850 struct nmk_pinctrl *npct;
1846 1851
1847 npct = platform_get_drvdata(pdev); 1852 npct = platform_get_drvdata(pdev);
1848 if (!npct) 1853 if (!npct)
1849 return -EINVAL; 1854 return -EINVAL;
1850 1855
1851 return pinctrl_force_default(npct->pctl); 1856 return pinctrl_force_default(npct->pctl);
1852 } 1857 }
1853 1858
1854 static int nmk_pinctrl_probe(struct platform_device *pdev) 1859 static int nmk_pinctrl_probe(struct platform_device *pdev)
1855 { 1860 {
1856 const struct platform_device_id *platid = platform_get_device_id(pdev); 1861 const struct platform_device_id *platid = platform_get_device_id(pdev);
1857 struct device_node *np = pdev->dev.of_node; 1862 struct device_node *np = pdev->dev.of_node;
1858 struct device_node *prcm_np; 1863 struct device_node *prcm_np;
1859 struct nmk_pinctrl *npct; 1864 struct nmk_pinctrl *npct;
1860 struct resource *res; 1865 struct resource *res;
1861 unsigned int version = 0; 1866 unsigned int version = 0;
1862 int i; 1867 int i;
1863 1868
1864 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL); 1869 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1865 if (!npct) 1870 if (!npct)
1866 return -ENOMEM; 1871 return -ENOMEM;
1867 1872
1868 if (platid) 1873 if (platid)
1869 version = platid->driver_data; 1874 version = platid->driver_data;
1870 else if (np) { 1875 else if (np) {
1871 const struct of_device_id *match; 1876 const struct of_device_id *match;
1872 1877
1873 match = of_match_device(nmk_pinctrl_match, &pdev->dev); 1878 match = of_match_device(nmk_pinctrl_match, &pdev->dev);
1874 if (!match) 1879 if (!match)
1875 return -ENODEV; 1880 return -ENODEV;
1876 version = (unsigned int) match->data; 1881 version = (unsigned int) match->data;
1877 } 1882 }
1878 1883
1879 /* Poke in other ASIC variants here */ 1884 /* Poke in other ASIC variants here */
1880 if (version == PINCTRL_NMK_STN8815) 1885 if (version == PINCTRL_NMK_STN8815)
1881 nmk_pinctrl_stn8815_init(&npct->soc); 1886 nmk_pinctrl_stn8815_init(&npct->soc);
1882 if (version == PINCTRL_NMK_DB8500) 1887 if (version == PINCTRL_NMK_DB8500)
1883 nmk_pinctrl_db8500_init(&npct->soc); 1888 nmk_pinctrl_db8500_init(&npct->soc);
1884 if (version == PINCTRL_NMK_DB8540) 1889 if (version == PINCTRL_NMK_DB8540)
1885 nmk_pinctrl_db8540_init(&npct->soc); 1890 nmk_pinctrl_db8540_init(&npct->soc);
1886 1891
1887 if (np) { 1892 if (np) {
1888 prcm_np = of_parse_phandle(np, "prcm", 0); 1893 prcm_np = of_parse_phandle(np, "prcm", 0);
1889 if (prcm_np) 1894 if (prcm_np)
1890 npct->prcm_base = of_iomap(prcm_np, 0); 1895 npct->prcm_base = of_iomap(prcm_np, 0);
1891 } 1896 }
1892 1897
1893 /* Allow platform passed information to over-write DT. */ 1898 /* Allow platform passed information to over-write DT. */
1894 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1899 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1895 if (res) 1900 if (res)
1896 npct->prcm_base = devm_ioremap(&pdev->dev, res->start, 1901 npct->prcm_base = devm_ioremap(&pdev->dev, res->start,
1897 resource_size(res)); 1902 resource_size(res));
1898 if (!npct->prcm_base) { 1903 if (!npct->prcm_base) {
1899 if (version == PINCTRL_NMK_STN8815) { 1904 if (version == PINCTRL_NMK_STN8815) {
1900 dev_info(&pdev->dev, 1905 dev_info(&pdev->dev,
1901 "No PRCM base, " 1906 "No PRCM base, "
1902 "assuming no ALT-Cx control is available\n"); 1907 "assuming no ALT-Cx control is available\n");
1903 } else { 1908 } else {
1904 dev_err(&pdev->dev, "missing PRCM base address\n"); 1909 dev_err(&pdev->dev, "missing PRCM base address\n");
1905 return -EINVAL; 1910 return -EINVAL;
1906 } 1911 }
1907 } 1912 }
1908 1913
1909 /* 1914 /*
1910 * We need all the GPIO drivers to probe FIRST, or we will not be able 1915 * We need all the GPIO drivers to probe FIRST, or we will not be able
1911 * to obtain references to the struct gpio_chip * for them, and we 1916 * to obtain references to the struct gpio_chip * for them, and we
1912 * need this to proceed. 1917 * need this to proceed.
1913 */ 1918 */
1914 for (i = 0; i < npct->soc->gpio_num_ranges; i++) { 1919 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1915 if (!nmk_gpio_chips[npct->soc->gpio_ranges[i].id]) { 1920 if (!nmk_gpio_chips[npct->soc->gpio_ranges[i].id]) {
1916 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i); 1921 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
1917 return -EPROBE_DEFER; 1922 return -EPROBE_DEFER;
1918 } 1923 }
1919 npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[npct->soc->gpio_ranges[i].id]->chip; 1924 npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[npct->soc->gpio_ranges[i].id]->chip;
1920 } 1925 }
1921 1926
1922 nmk_pinctrl_desc.pins = npct->soc->pins; 1927 nmk_pinctrl_desc.pins = npct->soc->pins;
1923 nmk_pinctrl_desc.npins = npct->soc->npins; 1928 nmk_pinctrl_desc.npins = npct->soc->npins;
1924 npct->dev = &pdev->dev; 1929 npct->dev = &pdev->dev;
1925 1930
1926 npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct); 1931 npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct);
1927 if (!npct->pctl) { 1932 if (!npct->pctl) {
1928 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n"); 1933 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
1929 return -EINVAL; 1934 return -EINVAL;
1930 } 1935 }
1931 1936
1932 /* We will handle a range of GPIO pins */ 1937 /* We will handle a range of GPIO pins */
1933 for (i = 0; i < npct->soc->gpio_num_ranges; i++) 1938 for (i = 0; i < npct->soc->gpio_num_ranges; i++)
1934 pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]); 1939 pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]);
1935 1940
1936 platform_set_drvdata(pdev, npct); 1941 platform_set_drvdata(pdev, npct);
1937 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n"); 1942 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
1938 1943
1939 return 0; 1944 return 0;
1940 } 1945 }
1941 1946
1942 static const struct of_device_id nmk_gpio_match[] = { 1947 static const struct of_device_id nmk_gpio_match[] = {
1943 { .compatible = "st,nomadik-gpio", }, 1948 { .compatible = "st,nomadik-gpio", },
1944 {} 1949 {}
1945 }; 1950 };
1946 1951
1947 static struct platform_driver nmk_gpio_driver = { 1952 static struct platform_driver nmk_gpio_driver = {
1948 .driver = { 1953 .driver = {
1949 .owner = THIS_MODULE, 1954 .owner = THIS_MODULE,
1950 .name = "gpio", 1955 .name = "gpio",
1951 .of_match_table = nmk_gpio_match, 1956 .of_match_table = nmk_gpio_match,
1952 }, 1957 },
1953 .probe = nmk_gpio_probe, 1958 .probe = nmk_gpio_probe,
1954 }; 1959 };
1955 1960
1956 static const struct platform_device_id nmk_pinctrl_id[] = { 1961 static const struct platform_device_id nmk_pinctrl_id[] = {
1957 { "pinctrl-stn8815", PINCTRL_NMK_STN8815 }, 1962 { "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
1958 { "pinctrl-db8500", PINCTRL_NMK_DB8500 }, 1963 { "pinctrl-db8500", PINCTRL_NMK_DB8500 },
1959 { "pinctrl-db8540", PINCTRL_NMK_DB8540 }, 1964 { "pinctrl-db8540", PINCTRL_NMK_DB8540 },
1960 { } 1965 { }
1961 }; 1966 };
1962 1967
1963 static struct platform_driver nmk_pinctrl_driver = { 1968 static struct platform_driver nmk_pinctrl_driver = {
1964 .driver = { 1969 .driver = {
1965 .owner = THIS_MODULE, 1970 .owner = THIS_MODULE,
1966 .name = "pinctrl-nomadik", 1971 .name = "pinctrl-nomadik",
1967 .of_match_table = nmk_pinctrl_match, 1972 .of_match_table = nmk_pinctrl_match,
1968 }, 1973 },
1969 .probe = nmk_pinctrl_probe, 1974 .probe = nmk_pinctrl_probe,
1970 .id_table = nmk_pinctrl_id, 1975 .id_table = nmk_pinctrl_id,
1971 #ifdef CONFIG_PM 1976 #ifdef CONFIG_PM
1972 .suspend = nmk_pinctrl_suspend, 1977 .suspend = nmk_pinctrl_suspend,
1973 .resume = nmk_pinctrl_resume, 1978 .resume = nmk_pinctrl_resume,
1974 #endif 1979 #endif
1975 }; 1980 };
1976 1981
1977 static int __init nmk_gpio_init(void) 1982 static int __init nmk_gpio_init(void)
1978 { 1983 {
1979 int ret; 1984 int ret;
1980 1985
1981 ret = platform_driver_register(&nmk_gpio_driver); 1986 ret = platform_driver_register(&nmk_gpio_driver);
1982 if (ret) 1987 if (ret)
1983 return ret; 1988 return ret;
1984 return platform_driver_register(&nmk_pinctrl_driver); 1989 return platform_driver_register(&nmk_pinctrl_driver);
1985 } 1990 }
1986 1991
1987 core_initcall(nmk_gpio_init); 1992 core_initcall(nmk_gpio_init);
1988 1993
1989 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); 1994 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
1990 MODULE_DESCRIPTION("Nomadik GPIO Driver"); 1995 MODULE_DESCRIPTION("Nomadik GPIO Driver");
1991 MODULE_LICENSE("GPL"); 1996 MODULE_LICENSE("GPL");
1992 1997