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Commit 4980f9bc2cec0f8ff0e0f2b021d46c7606ae1849

Authored by Linus Walleij 2012-09-06 16:08:24 +0800

Committed by Russell King 2012-09-18 06:20:22 +0800

Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches

ARM: 7517/1: integrator: initial device tree support

This is initial device tree support for the ARM Integrator family,
we create a very basic device tree, #ifdef out the non-DT machines
when compiling for device tree.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Showing 6 changed files with 360 additions and 68 deletions Inline Diff

Documentation/devicetree/bindings/arm/arm-boards
arch/arm/boot/dts/integrator.dtsi
arch/arm/boot/dts/integratorap.dts
arch/arm/boot/dts/integratorcp.dts
arch/arm/mach-integrator/integrator_ap.c
arch/arm/mach-integrator/integrator_cp.c

Documentation/devicetree/bindings/arm/arm-boards

Diff comments View file @ 4980f9b

+ARM Integrator/AP (Application Platform) and Integrator/CP (Compact Platform)
+-----------------------------------------------------------------------------
+ARM's oldest Linux-supported platform with connectors for different core
+tiles of ARMv4, ARMv5 and ARMv6 type.
+Required properties (in root node):
+	compatible = "arm,integrator-ap";  /* Application Platform */
+	compatible = "arm,integrator-cp";  /* Compact Platform */
+FPGA type interrupt controllers, see the versatile-fpga-irq binding doc.
 ARM Versatile Application and Platform Baseboards
 -------------------------------------------------
 ARM's development hardware platform with connectors for customizable
 core tiles.  The hardware configuration of the Versatile boards is
 highly customizable.
 Required properties (in root node):
 	compatible = "arm,versatile-ab";  /* Application baseboard */
 	compatible = "arm,versatile-pb";  /* Platform baseboard */
 Interrupt controllers:
 - VIC required properties:
 	compatible = "arm,versatile-vic";
 	interrupt-controller;
 	#interrupt-cells = <1>;
 - SIC required properties:
 	compatible = "arm,versatile-sic";
 	interrupt-controller;
 	#interrupt-cells = <1>;

arch/arm/boot/dts/integrator.dtsi

Diff comments View file @ 4980f9b

File was created	1	/*
	2	* SoC core Device Tree for the ARM Integrator platforms
	3	*/
	4
	5	/include/ "skeleton.dtsi"
	6
	7	/ {
	8	timer@13000000 {
	9	reg = <0x13000000 0x100>;
	10	interrupt-parent = <&pic>;
	11	interrupts = <5>;
	12	};
	13
	14	timer@13000100 {
	15	reg = <0x13000100 0x100>;
	16	interrupt-parent = <&pic>;
	17	interrupts = <6>;
	18	};
	19
	20	timer@13000200 {
	21	reg = <0x13000200 0x100>;
	22	interrupt-parent = <&pic>;
	23	interrupts = <7>;
	24	};
	25
	26	pic@14000000 {
	27	compatible = "arm,versatile-fpga-irq";
	28	#interrupt-cells = <1>;
	29	interrupt-controller;
	30	reg = <0x14000000 0x100>;
	31	clear-mask = <0xffffffff>;
	32	};
	33	};
	34

arch/arm/boot/dts/integratorap.dts

Diff comments View file @ 4980f9b

File was created	1	/*
	2	* Device Tree for the ARM Integrator/AP platform
	3	*/
	4
	5	/dts-v1/;
	6	/include/ "integrator.dtsi"
	7
	8	/ {
	9	model = "ARM Integrator/AP";
	10	compatible = "arm,integrator-ap";
	11
	12	aliases {
	13	arm,timer-primary = &timer2;
	14	arm,timer-secondary = &timer1;
	15	};
	16
	17	chosen {
	18	bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
	19	};
	20
	21	timer0: timer@13000000 {
	22	compatible = "arm,integrator-timer";
	23	};
	24
	25	timer1: timer@13000100 {
	26	compatible = "arm,integrator-timer";
	27	};
	28
	29	timer2: timer@13000200 {
	30	compatible = "arm,integrator-timer";
	31	};
	32
	33	pic: pic@14000000 {
	34	valid-mask = <0x003fffff>;
	35	};
	36	};
	37

arch/arm/boot/dts/integratorcp.dts

Diff comments View file @ 4980f9b

File was created	1	/*
	2	* Device Tree for the ARM Integrator/CP platform
	3	*/
	4
	5	/dts-v1/;
	6	/include/ "integrator.dtsi"
	7
	8	/ {
	9	model = "ARM Integrator/CP";
	10	compatible = "arm,integrator-cp";
	11
	12	aliases {
	13	arm,timer-primary = &timer2;
	14	arm,timer-secondary = &timer1;
	15	};
	16
	17	chosen {
	18	bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
	19	};
	20
	21	timer0: timer@13000000 {
	22	compatible = "arm,sp804", "arm,primecell";
	23	};
	24
	25	timer1: timer@13000100 {
	26	compatible = "arm,sp804", "arm,primecell";
	27	};
	28
	29	timer2: timer@13000200 {
	30	compatible = "arm,sp804", "arm,primecell";
	31	};
	32
	33	pic: pic@14000000 {
	34	valid-mask = <0x1fc003ff>;
	35	};
	36
	37	cic: cic@10000040 {
	38	compatible = "arm,versatile-fpga-irq";
	39	#interrupt-cells = <1>;
	40	interrupt-controller;
	41	reg = <0x10000040 0x100>;
	42	clear-mask = <0xffffffff>;
	43	valid-mask = <0x00000007>;
	44	};
	45
	46	sic: sic@ca000000 {
	47	compatible = "arm,versatile-fpga-irq";
	48	#interrupt-cells = <1>;
	49	interrupt-controller;
	50	reg = <0xca000000 0x100>;
	51	clear-mask = <0x00000fff>;
	52	valid-mask = <0x00000fff>;
	53	};
	54	};
	55

arch/arm/mach-integrator/integrator_ap.c

Diff comments View file @ 4980f9b

 /*
  *  linux/arch/arm/mach-integrator/integrator_ap.c
  *
  *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 #include <linux/types.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/string.h>
 #include <linux/syscore_ops.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/kmi.h>
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/mtd/physmap.h>
 #include <linux/clk.h>
 #include <linux/platform_data/clk-integrator.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
 #include <video/vga.h>
 #include <mach/hardware.h>
 #include <mach/platform.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/setup.h>
 #include <asm/param.h>		/* HZ */
 #include <asm/mach-types.h>
 #include <asm/sched_clock.h>
 #include <mach/lm.h>
 #include <mach/irqs.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <plat/fpga-irq.h>
 #include "common.h"
 /*
  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  * is the (PA >> 12).
  *
  * Setup a VA for the Integrator interrupt controller (for header #0,
  * just for now).
  */
 #define VA_IC_BASE	__io_address(INTEGRATOR_IC_BASE)
 #define VA_SC_BASE	__io_address(INTEGRATOR_SC_BASE)
 #define VA_EBI_BASE	__io_address(INTEGRATOR_EBI_BASE)
 #define VA_CMIC_BASE	__io_address(INTEGRATOR_HDR_IC)
 /*
  * Logical      Physical
  * e8000000	40000000	PCI memory		PHYS_PCI_MEM_BASE	(max 512M)
  * ec000000	61000000	PCI config space	PHYS_PCI_CONFIG_BASE	(max 16M)
  * ed000000	62000000	PCI V3 regs		PHYS_PCI_V3_BASE	(max 64k)
  * ee000000	60000000	PCI IO			PHYS_PCI_IO_BASE	(max 16M)
  * ef000000			Cache flush
  * f1000000	10000000	Core module registers
  * f1100000	11000000	System controller registers
  * f1200000	12000000	EBI registers
  * f1300000	13000000	Counter/Timer
  * f1400000	14000000	Interrupt controller
  * f1600000	16000000	UART 0
  * f1700000	17000000	UART 1
  * f1a00000	1a000000	Debug LEDs
  * f1b00000	1b000000	GPIO
  */
 static struct map_desc ap_io_desc[] __initdata = {
 	{
 		.virtual	= IO_ADDRESS(INTEGRATOR_HDR_BASE),
 		.pfn		= __phys_to_pfn(INTEGRATOR_HDR_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= IO_ADDRESS(INTEGRATOR_SC_BASE),
 		.pfn		= __phys_to_pfn(INTEGRATOR_SC_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= IO_ADDRESS(INTEGRATOR_EBI_BASE),
 		.pfn		= __phys_to_pfn(INTEGRATOR_EBI_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= IO_ADDRESS(INTEGRATOR_CT_BASE),
 		.pfn		= __phys_to_pfn(INTEGRATOR_CT_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= IO_ADDRESS(INTEGRATOR_IC_BASE),
 		.pfn		= __phys_to_pfn(INTEGRATOR_IC_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= IO_ADDRESS(INTEGRATOR_UART0_BASE),
 		.pfn		= __phys_to_pfn(INTEGRATOR_UART0_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= IO_ADDRESS(INTEGRATOR_UART1_BASE),
 		.pfn		= __phys_to_pfn(INTEGRATOR_UART1_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= IO_ADDRESS(INTEGRATOR_DBG_BASE),
 		.pfn		= __phys_to_pfn(INTEGRATOR_DBG_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
 		.pfn		= __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= PCI_MEMORY_VADDR,
 		.pfn		= __phys_to_pfn(PHYS_PCI_MEM_BASE),
 		.length		= SZ_16M,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= PCI_CONFIG_VADDR,
 		.pfn		= __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
 		.length		= SZ_16M,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= PCI_V3_VADDR,
 		.pfn		= __phys_to_pfn(PHYS_PCI_V3_BASE),
 		.length		= SZ_64K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= PCI_IO_VADDR,
 		.pfn		= __phys_to_pfn(PHYS_PCI_IO_BASE),
 		.length		= SZ_64K,
 		.type		= MT_DEVICE
 	}
 };
 static void __init ap_map_io(void)
 {
 	iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
 	vga_base = PCI_MEMORY_VADDR;
 }
-#define INTEGRATOR_SC_VALID_INT	0x003fffff
-static void __init ap_init_irq(void)
-{
-	/* Disable all interrupts initially. */
-	/* Do the core module ones */
-	writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
-	/* do the header card stuff next */
-	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
-	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
-	fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
-		-1, INTEGRATOR_SC_VALID_INT, NULL);
-	integrator_clk_init(false);
-}
 #ifdef CONFIG_PM
 static unsigned long ic_irq_enable;
 static int irq_suspend(void)
 {
 	ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
 	return 0;
 }
 static void irq_resume(void)
 {
 	/* disable all irq sources */
 	writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
 	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
 	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
 	writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
 }
 #else
 #define irq_suspend NULL
 #define irq_resume NULL
 #endif
 static struct syscore_ops irq_syscore_ops = {
 	.suspend	= irq_suspend,
 	.resume		= irq_resume,
 };
 static int __init irq_syscore_init(void)
 {
 	register_syscore_ops(&irq_syscore_ops);
 	return 0;
 }
 device_initcall(irq_syscore_init);
 /*
  * Flash handling.
  */
 #define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
 #define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
 #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
 #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
 static int ap_flash_init(struct platform_device *dev)
 {
 	u32 tmp;
 	writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
 	tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
 	writel(tmp, EBI_CSR1);
 	if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
 		writel(0xa05f, EBI_LOCK);
 		writel(tmp, EBI_CSR1);
 		writel(0, EBI_LOCK);
 	}
 	return 0;
 }
 static void ap_flash_exit(struct platform_device *dev)
 {
 	u32 tmp;
 	writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
 	tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
 	writel(tmp, EBI_CSR1);
 	if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
 		writel(0xa05f, EBI_LOCK);
 		writel(tmp, EBI_CSR1);
 		writel(0, EBI_LOCK);
 	}
 }
 static void ap_flash_set_vpp(struct platform_device *pdev, int on)
 {
 	void __iomem *reg = on ? SC_CTRLS : SC_CTRLC;
 	writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
 }
 static struct physmap_flash_data ap_flash_data = {
 	.width		= 4,
 	.init		= ap_flash_init,
 	.exit		= ap_flash_exit,
 	.set_vpp	= ap_flash_set_vpp,
 };
 static struct resource cfi_flash_resource = {
 	.start		= INTEGRATOR_FLASH_BASE,
 	.end		= INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
 	.flags		= IORESOURCE_MEM,
 };
 static struct platform_device cfi_flash_device = {
 	.name		= "physmap-flash",
 	.id		= 0,
 	.dev		= {
 		.platform_data	= &ap_flash_data,
 	},
 	.num_resources	= 1,
 	.resource	= &cfi_flash_resource,
 };
 static void __init ap_init(void)
 {
 	unsigned long sc_dec;
 	int i;
 	platform_device_register(&cfi_flash_device);
 	sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
 	for (i = 0; i < 4; i++) {
 		struct lm_device *lmdev;
 		if ((sc_dec & (16 << i)) == 0)
 			continue;
 		lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
 		if (!lmdev)
 			continue;
 		lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
 		lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
 		lmdev->resource.flags = IORESOURCE_MEM;
 		lmdev->irq = IRQ_AP_EXPINT0 + i;
 		lmdev->id = i;
 		lm_device_register(lmdev);
 	}
 	integrator_init(false);
 }
 /*
  * Where is the timer (VA)?
  */
 #define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
 #define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
 #define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)
 static unsigned long timer_reload;
 static u32 notrace integrator_read_sched_clock(void)
 {
 	return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
 }
-static void integrator_clocksource_init(unsigned long inrate)
+static void integrator_clocksource_init(unsigned long inrate,
+					void __iomem *base)
 {
-	void __iomem *base = (void __iomem *)TIMER2_VA_BASE;
 	u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
 	unsigned long rate = inrate;
 	if (rate >= 1500000) {
 		rate /= 16;
 		ctrl |= TIMER_CTRL_DIV16;
 	}
 	writel(0xffff, base + TIMER_LOAD);
 	writel(ctrl, base + TIMER_CTRL);
 	clocksource_mmio_init(base + TIMER_VALUE, "timer2",
 			rate, 200, 16, clocksource_mmio_readl_down);
 	setup_sched_clock(integrator_read_sched_clock, 16, rate);
 }
-static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;
+static void __iomem * clkevt_base;
 /*
  * IRQ handler for the timer
  */
 static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
 {
 	struct clock_event_device *evt = dev_id;
 	/* clear the interrupt */
 	writel(1, clkevt_base + TIMER_INTCLR);
 	evt->event_handler(evt);
 	return IRQ_HANDLED;
 }
 static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
 {
 	u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
 	/* Disable timer */
 	writel(ctrl, clkevt_base + TIMER_CTRL);
 	switch (mode) {
 	case CLOCK_EVT_MODE_PERIODIC:
 		/* Enable the timer and start the periodic tick */
 		writel(timer_reload, clkevt_base + TIMER_LOAD);
 		ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
 		writel(ctrl, clkevt_base + TIMER_CTRL);
 		break;
 	case CLOCK_EVT_MODE_ONESHOT:
 		/* Leave the timer disabled, .set_next_event will enable it */
 		ctrl &= ~TIMER_CTRL_PERIODIC;
 		writel(ctrl, clkevt_base + TIMER_CTRL);
 		break;
 	case CLOCK_EVT_MODE_UNUSED:
 	case CLOCK_EVT_MODE_SHUTDOWN:
 	case CLOCK_EVT_MODE_RESUME:
 	default:
 		/* Just leave in disabled state */
 		break;
 	}
 }
 static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
 {
 	unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
 	writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
 	writel(next, clkevt_base + TIMER_LOAD);
 	writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
 	return 0;
 }
 static struct clock_event_device integrator_clockevent = {
 	.name		= "timer1",
 	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 	.set_mode	= clkevt_set_mode,
 	.set_next_event	= clkevt_set_next_event,
 	.rating		= 300,
 };
 static struct irqaction integrator_timer_irq = {
 	.name		= "timer",
 	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 	.handler	= integrator_timer_interrupt,
 	.dev_id		= &integrator_clockevent,
 };
-static void integrator_clockevent_init(unsigned long inrate)
+static void integrator_clockevent_init(unsigned long inrate,
+				void __iomem *base, int irq)
 {
 	unsigned long rate = inrate;
 	unsigned int ctrl = 0;
+	clkevt_base = base;
 	/* Calculate and program a divisor */
 	if (rate > 0x100000 * HZ) {
 		rate /= 256;
 		ctrl |= TIMER_CTRL_DIV256;
 	} else if (rate > 0x10000 * HZ) {
 		rate /= 16;
 		ctrl |= TIMER_CTRL_DIV16;
 	}
 	timer_reload = rate / HZ;
 	writel(ctrl, clkevt_base + TIMER_CTRL);
-	setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
+	setup_irq(irq, &integrator_timer_irq);
 	clockevents_config_and_register(&integrator_clockevent,
 					rate,
 					1,
 					0xffffU);
 }
 void __init ap_init_early(void)
 {
 }
+#ifdef CONFIG_OF
+static void __init ap_init_timer_of(void)
+{
+	struct device_node *node;
+	const char *path;
+	void __iomem *base;
+	int err;
+	int irq;
+	struct clk *clk;
+	unsigned long rate;
+	clk = clk_get_sys("ap_timer", NULL);
+	BUG_ON(IS_ERR(clk));
+	clk_prepare_enable(clk);
+	rate = clk_get_rate(clk);
+	err = of_property_read_string(of_aliases,
+				"arm,timer-primary", &path);
+	if (WARN_ON(err))
+		return;
+	node = of_find_node_by_path(path);
+	base = of_iomap(node, 0);
+	if (WARN_ON(!base))
+		return;
+	writel(0, base + TIMER_CTRL);
+	integrator_clocksource_init(rate, base);
+	err = of_property_read_string(of_aliases,
+				"arm,timer-secondary", &path);
+	if (WARN_ON(err))
+		return;
+	node = of_find_node_by_path(path);
+	base = of_iomap(node, 0);
+	if (WARN_ON(!base))
+		return;
+	irq = irq_of_parse_and_map(node, 0);
+	writel(0, base + TIMER_CTRL);
+	integrator_clockevent_init(rate, base, irq);
+}
+static struct sys_timer ap_of_timer = {
+	.init		= ap_init_timer_of,
+};
+static const struct of_device_id fpga_irq_of_match[] __initconst = {
+	{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
+	{ /* Sentinel */ }
+};
+static void __init ap_init_irq_of(void)
+{
+	/* disable core module IRQs */
+	writel(0xffffffffU, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
+	of_irq_init(fpga_irq_of_match);
+	integrator_clk_init(false);
+}
+static const char * ap_dt_board_compat[] = {
+	"arm,integrator-ap",
+	NULL,
+};
+DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
+	.reserve	= integrator_reserve,
+	.map_io		= ap_map_io,
+	.nr_irqs	= NR_IRQS_INTEGRATOR_AP,
+	.init_early	= ap_init_early,
+	.init_irq	= ap_init_irq_of,
+	.handle_irq	= fpga_handle_irq,
+	.timer		= &ap_of_timer,
+	.init_machine	= ap_init,
+	.restart	= integrator_restart,
+	.dt_compat      = ap_dt_board_compat,
+MACHINE_END
+#endif
+#ifdef CONFIG_ATAGS
 /*
- * Set up timer(s).
+ * This is where non-devicetree initialization code is collected and stashed
+ * for eventual deletion.
  */
 static void __init ap_init_timer(void)
 {
 	struct clk *clk;
 	unsigned long rate;
 	clk = clk_get_sys("ap_timer", NULL);
 	BUG_ON(IS_ERR(clk));
 	clk_prepare_enable(clk);
 	rate = clk_get_rate(clk);
 	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 	writel(0, TIMER2_VA_BASE + TIMER_CTRL);
-	integrator_clocksource_init(rate);
+	integrator_clocksource_init(rate, (void __iomem *)TIMER2_VA_BASE);
-	integrator_clockevent_init(rate);
+	integrator_clockevent_init(rate, (void __iomem *)TIMER1_VA_BASE,
+				IRQ_TIMERINT1);
 }
 static struct sys_timer ap_timer = {
 	.init		= ap_init_timer,
 };
+#define INTEGRATOR_SC_VALID_INT	0x003fffff
+static void __init ap_init_irq(void)
+{
+	/* Disable all interrupts initially. */
+	/* Do the core module ones */
+	writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
+	/* do the header card stuff next */
+	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
+	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
+	fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
+		-1, INTEGRATOR_SC_VALID_INT, NULL);
+	integrator_clk_init(false);

arch/arm/mach-integrator/integrator_cp.c

Diff comments View file @ 4980f9b

 /*
  *  linux/arch/arm/mach-integrator/integrator_cp.c
  *
  *  Copyright (C) 2003 Deep Blue Solutions Ltd
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License.
  */
 #include <linux/types.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/string.h>
 #include <linux/device.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/kmi.h>
 #include <linux/amba/clcd.h>
 #include <linux/amba/mmci.h>
 #include <linux/io.h>
 #include <linux/gfp.h>
 #include <linux/mtd/physmap.h>
 #include <linux/platform_data/clk-integrator.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
 #include <mach/hardware.h>
 #include <mach/platform.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/icst.h>
 #include <mach/cm.h>
 #include <mach/lm.h>
 #include <mach/irqs.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/hardware/timer-sp.h>
 #include <plat/clcd.h>
 #include <plat/fpga-irq.h>
 #include <plat/sched_clock.h>
 #include "common.h"
 #define INTCP_PA_FLASH_BASE		0x24000000
 #define INTCP_FLASH_SIZE		SZ_32M
 #define INTCP_PA_CLCD_BASE		0xc0000000
-#define INTCP_VA_CIC_BASE		__io_address(INTEGRATOR_HDR_BASE + 0x40)
-#define INTCP_VA_PIC_BASE		__io_address(INTEGRATOR_IC_BASE)
-#define INTCP_VA_SIC_BASE		__io_address(INTEGRATOR_CP_SIC_BASE)
 #define INTCP_ETH_SIZE			0x10
 #define INTCP_VA_CTRL_BASE		IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
 #define INTCP_FLASHPROG			0x04
 #define CINTEGRATOR_FLASHPROG_FLVPPEN	(1 << 0)
 #define CINTEGRATOR_FLASHPROG_FLWREN	(1 << 1)
 /*
  * Logical      Physical
  * f1000000	10000000	Core module registers
  * f1100000	11000000	System controller registers
  * f1200000	12000000	EBI registers
  * f1300000	13000000	Counter/Timer
  * f1400000	14000000	Interrupt controller
  * f1600000	16000000	UART 0
  * f1700000	17000000	UART 1
  * f1a00000	1a000000	Debug LEDs
  * fc900000	c9000000	GPIO
  * fca00000	ca000000	SIC
  * fcb00000	cb000000	CP system control
  */
 static struct map_desc intcp_io_desc[] __initdata = {
 	{
 		.virtual	= IO_ADDRESS(INTEGRATOR_HDR_BASE),
 		.pfn		= __phys_to_pfn(INTEGRATOR_HDR_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= IO_ADDRESS(INTEGRATOR_SC_BASE),
 		.pfn		= __phys_to_pfn(INTEGRATOR_SC_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= IO_ADDRESS(INTEGRATOR_EBI_BASE),
 		.pfn		= __phys_to_pfn(INTEGRATOR_EBI_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= IO_ADDRESS(INTEGRATOR_CT_BASE),
 		.pfn		= __phys_to_pfn(INTEGRATOR_CT_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= IO_ADDRESS(INTEGRATOR_IC_BASE),
 		.pfn		= __phys_to_pfn(INTEGRATOR_IC_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= IO_ADDRESS(INTEGRATOR_UART0_BASE),
 		.pfn		= __phys_to_pfn(INTEGRATOR_UART0_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= IO_ADDRESS(INTEGRATOR_UART1_BASE),
 		.pfn		= __phys_to_pfn(INTEGRATOR_UART1_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= IO_ADDRESS(INTEGRATOR_DBG_BASE),
 		.pfn		= __phys_to_pfn(INTEGRATOR_DBG_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
 		.pfn		= __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
 		.pfn		= __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
 		.pfn		= __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}
 };
 static void __init intcp_map_io(void)
 {
 	iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
 }
-static void __init intcp_init_irq(void)
-{
-	u32 pic_mask, cic_mask, sic_mask;
-	/* These masks are for the HW IRQ registers */
-	pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
-	pic_mask |= (~((~0u) << (29 - 22))) << 22;
-	cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
-	sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
-	/*
-	 * Disable all interrupt sources
-	 */
-	writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
-	writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
-	writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
-	writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
-	writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
-	writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
-	fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
-		      -1, pic_mask, NULL);
-	fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
-		      -1, cic_mask, NULL);
-	fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
-		      IRQ_CP_CPPLDINT, sic_mask, NULL);
-	integrator_clk_init(true);
-}
 /*
  * Flash handling.
  */
 static int intcp_flash_init(struct platform_device *dev)
 {
 	u32 val;
 	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 	val |= CINTEGRATOR_FLASHPROG_FLWREN;
 	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 	return 0;
 }
 static void intcp_flash_exit(struct platform_device *dev)
 {
 	u32 val;
 	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 	val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
 	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 }
 static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
 {
 	u32 val;
 	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 	if (on)
 		val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
 	else
 		val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
 	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 }
 static struct physmap_flash_data intcp_flash_data = {
 	.width		= 4,
 	.init		= intcp_flash_init,
 	.exit		= intcp_flash_exit,
 	.set_vpp	= intcp_flash_set_vpp,
 };
 static struct resource intcp_flash_resource = {
 	.start		= INTCP_PA_FLASH_BASE,
 	.end		= INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
 	.flags		= IORESOURCE_MEM,
 };
 static struct platform_device intcp_flash_device = {
 	.name		= "physmap-flash",
 	.id		= 0,
 	.dev		= {
 		.platform_data	= &intcp_flash_data,
 	},
 	.num_resources	= 1,
 	.resource	= &intcp_flash_resource,
 };
 static struct resource smc91x_resources[] = {
 	[0] = {
 		.start	= INTEGRATOR_CP_ETH_BASE,
 		.end	= INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
 		.start	= IRQ_CP_ETHINT,
 		.end	= IRQ_CP_ETHINT,
 		.flags	= IORESOURCE_IRQ,
 	},
 };
 static struct platform_device smc91x_device = {
 	.name		= "smc91x",
 	.id		= 0,
 	.num_resources	= ARRAY_SIZE(smc91x_resources),
 	.resource	= smc91x_resources,
 };
 static struct platform_device *intcp_devs[] __initdata = {
 	&intcp_flash_device,
 	&smc91x_device,
 };
 /*
  * It seems that the card insertion interrupt remains active after
  * we've acknowledged it.  We therefore ignore the interrupt, and
  * rely on reading it from the SIC.  This also means that we must
  * clear the latched interrupt.
  */
 static unsigned int mmc_status(struct device *dev)
 {
 	unsigned int status = readl(IO_ADDRESS(0xca000000 + 4));
 	writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8));
 	return status & 8;
 }
 static struct mmci_platform_data mmc_data = {
 	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
 	.status		= mmc_status,
 	.gpio_wp	= -1,
 	.gpio_cd	= -1,
 };
 #define INTEGRATOR_CP_MMC_IRQS	{ IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
 #define INTEGRATOR_CP_AACI_IRQS	{ IRQ_CP_AACIINT }
 static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE,
 	INTEGRATOR_CP_MMC_IRQS, &mmc_data);
 static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE,
 	INTEGRATOR_CP_AACI_IRQS, NULL);
 /*
  * CLCD support
  */
 /*
  * Ensure VGA is selected.
  */
 static void cp_clcd_enable(struct clcd_fb *fb)
 {
 	struct fb_var_screeninfo *var = &fb->fb.var;
 	u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2;
 	if (var->bits_per_pixel <= 8 ||
 	    (var->bits_per_pixel == 16 && var->green.length == 5))
 		/* Pseudocolor, RGB555, BGR555 */
 		val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
 	else if (fb->fb.var.bits_per_pixel <= 16)
 		/* truecolor RGB565 */
 		val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
 	else
 		val = 0; /* no idea for this, don't trust the docs */
 	cm_control(CM_CTRL_LCDMUXSEL_MASK|
 		   CM_CTRL_LCDEN0|
 		   CM_CTRL_LCDEN1|
 		   CM_CTRL_STATIC1|
 		   CM_CTRL_STATIC2|
 		   CM_CTRL_STATIC|
 		   CM_CTRL_n24BITEN, val);
 }
 static int cp_clcd_setup(struct clcd_fb *fb)
 {
 	fb->panel = versatile_clcd_get_panel("VGA");
 	if (!fb->panel)
 		return -EINVAL;
 	return versatile_clcd_setup_dma(fb, SZ_1M);
 }
 static struct clcd_board clcd_data = {
 	.name		= "Integrator/CP",
 	.caps		= CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888,
 	.check		= clcdfb_check,
 	.decode		= clcdfb_decode,
 	.enable		= cp_clcd_enable,
 	.setup		= cp_clcd_setup,
 	.mmap		= versatile_clcd_mmap_dma,
 	.remove		= versatile_clcd_remove_dma,
 };
 static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE,
 	{ IRQ_CP_CLCDCINT }, &clcd_data);
 static struct amba_device *amba_devs[] __initdata = {
 	&mmc_device,
 	&aaci_device,
 	&clcd_device,
 };
 #define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
 static void __init intcp_init_early(void)
 {
 #ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
 	versatile_sched_clock_init(REFCOUNTER, 24000000);
 #endif
 }
-static void __init intcp_init(void)
+static void __init intcp_timer_init_of(void)
 {
-	int i;
+	struct device_node *node;
+	const char *path;
+	void __iomem *base;
+	int err;
+	int irq;
-	platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
+	err = of_property_read_string(of_aliases,
+				"arm,timer-primary", &path);
+	if (WARN_ON(err))
+		return;
+	node = of_find_node_by_path(path);
+	base = of_iomap(node, 0);
+	if (WARN_ON(!base))
+		return;
+	writel(0, base + TIMER_CTRL);
+	sp804_clocksource_init(base, node->name);
-	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
+	err = of_property_read_string(of_aliases,
-		struct amba_device *d = amba_devs[i];
+				"arm,timer-secondary", &path);
-		amba_device_register(d, &iomem_resource);
+	if (WARN_ON(err))
-	}
+		return;
-	integrator_init(true);
+	node = of_find_node_by_path(path);
+	base = of_iomap(node, 0);
+	if (WARN_ON(!base))
+		return;
+	irq = irq_of_parse_and_map(node, 0);
+	writel(0, base + TIMER_CTRL);
+	sp804_clockevents_init(base, irq, node->name);
 }
+static struct sys_timer cp_of_timer = {
+	.init		= intcp_timer_init_of,
+};
+#ifdef CONFIG_OF
+static const struct of_device_id fpga_irq_of_match[] __initconst = {
+	{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
+	{ /* Sentinel */ }
+};
+static void __init intcp_init_irq_of(void)
+{
+	of_irq_init(fpga_irq_of_match);
+	integrator_clk_init(true);
+}
+static const char * intcp_dt_board_compat[] = {
+	"arm,integrator-cp",
+	NULL,
+};
+DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
+	.reserve	= integrator_reserve,
+	.map_io		= intcp_map_io,
+	.nr_irqs	= NR_IRQS_INTEGRATOR_CP,
+	.init_early	= intcp_init_early,
+	.init_irq	= intcp_init_irq_of,
+	.handle_irq	= fpga_handle_irq,
+	.timer		= &cp_of_timer,
+	.init_machine	= intcp_init,
+	.restart	= integrator_restart,
+	.dt_compat      = intcp_dt_board_compat,
+MACHINE_END
+#endif
+#ifdef CONFIG_ATAGS
+/*
+ * This is where non-devicetree initialization code is collected and stashed
+ * for eventual deletion.
+ */
+#define INTCP_VA_CIC_BASE		__io_address(INTEGRATOR_HDR_BASE + 0x40)
+#define INTCP_VA_PIC_BASE		__io_address(INTEGRATOR_IC_BASE)
+#define INTCP_VA_SIC_BASE		__io_address(INTEGRATOR_CP_SIC_BASE)
+static void __init intcp_init_irq(void)
+{
+	u32 pic_mask, cic_mask, sic_mask;
+	/* These masks are for the HW IRQ registers */
+	pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
+	pic_mask |= (~((~0u) << (29 - 22))) << 22;
+	cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
+	sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
+	/*
+	 * Disable all interrupt sources
+	 */
+	writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
+	writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
+	writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
+	writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
+	writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
+	writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
+	fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
+		      -1, pic_mask, NULL);
+	fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
+		      -1, cic_mask, NULL);
+	fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
+		      IRQ_CP_CPPLDINT, sic_mask, NULL);
+	integrator_clk_init(true);
+}