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Commit 4a9b7f9f2704405c05b213f8f51e9f7f1fe02d1a

Authored by Julia Lawall
Committed by Tejun Heo
1 parent 404eafe137
Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch imx_3.14.28_1.0.0_ga

drivers/ata/sata_rcar.c: simplify use of devm_ioremap_resource 

Remove unneeded error handling on the result of a call to
platform_get_resource when the value is passed to devm_ioremap_resource.

Move the call to platform_get_resource adjacent to the call to
devm_ioremap_resource to make the connection between them more clear.

A simplified version of the semantic patch that makes this change is as
follows: (http://coccinelle.lip6.fr/)

// <smpl>
@@
expression pdev,res,n,e,e1;
expression ret != 0;
identifier l;
@@

- res = platform_get_resource(pdev, IORESOURCE_MEM, n);
  ... when != res
- if (res == NULL) { ... \(goto l;\|return ret;\) }
  ... when != res
+ res = platform_get_resource(pdev, IORESOURCE_MEM, n);
  e = devm_ioremap_resource(e1, res);
// </smpl>

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Tejun Heo <tj@kernel.org>

Showing 1 changed file with 1 additions and 4 deletions Inline Diff

drivers/ata/sata_rcar.c
Diff comments   View file @ 4a9b7f9
1 /* 1 /*
2 * Renesas R-Car SATA driver 2 * Renesas R-Car SATA driver
3 * 3 *
4 * Author: Vladimir Barinov <source@cogentembedded.com> 4 * Author: Vladimir Barinov <source@cogentembedded.com>
5 * Copyright (C) 2013 Cogent Embedded, Inc. 5 * Copyright (C) 2013 Cogent Embedded, Inc.
6 * Copyright (C) 2013 Renesas Solutions Corp. 6 * Copyright (C) 2013 Renesas Solutions Corp.
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify it 8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the 9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your 10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version. 11 * option) any later version.
12 */ 12 */
13 13
14 #include <linux/kernel.h> 14 #include <linux/kernel.h>
15 #include <linux/module.h> 15 #include <linux/module.h>
16 #include <linux/ata.h> 16 #include <linux/ata.h>
17 #include <linux/libata.h> 17 #include <linux/libata.h>
18 #include <linux/platform_device.h> 18 #include <linux/platform_device.h>
19 #include <linux/clk.h> 19 #include <linux/clk.h>
20 #include <linux/err.h> 20 #include <linux/err.h>
21 21
22 #define DRV_NAME "sata_rcar" 22 #define DRV_NAME "sata_rcar"
23 23
24 /* SH-Navi2G/ATAPI-ATA compatible task registers */ 24 /* SH-Navi2G/ATAPI-ATA compatible task registers */
25 #define DATA_REG 0x100 25 #define DATA_REG 0x100
26 #define SDEVCON_REG 0x138 26 #define SDEVCON_REG 0x138
27 27
28 /* SH-Navi2G/ATAPI module compatible control registers */ 28 /* SH-Navi2G/ATAPI module compatible control registers */
29 #define ATAPI_CONTROL1_REG 0x180 29 #define ATAPI_CONTROL1_REG 0x180
30 #define ATAPI_STATUS_REG 0x184 30 #define ATAPI_STATUS_REG 0x184
31 #define ATAPI_INT_ENABLE_REG 0x188 31 #define ATAPI_INT_ENABLE_REG 0x188
32 #define ATAPI_DTB_ADR_REG 0x198 32 #define ATAPI_DTB_ADR_REG 0x198
33 #define ATAPI_DMA_START_ADR_REG 0x19C 33 #define ATAPI_DMA_START_ADR_REG 0x19C
34 #define ATAPI_DMA_TRANS_CNT_REG 0x1A0 34 #define ATAPI_DMA_TRANS_CNT_REG 0x1A0
35 #define ATAPI_CONTROL2_REG 0x1A4 35 #define ATAPI_CONTROL2_REG 0x1A4
36 #define ATAPI_SIG_ST_REG 0x1B0 36 #define ATAPI_SIG_ST_REG 0x1B0
37 #define ATAPI_BYTE_SWAP_REG 0x1BC 37 #define ATAPI_BYTE_SWAP_REG 0x1BC
38 38
39 /* ATAPI control 1 register (ATAPI_CONTROL1) bits */ 39 /* ATAPI control 1 register (ATAPI_CONTROL1) bits */
40 #define ATAPI_CONTROL1_ISM BIT(16) 40 #define ATAPI_CONTROL1_ISM BIT(16)
41 #define ATAPI_CONTROL1_DTA32M BIT(11) 41 #define ATAPI_CONTROL1_DTA32M BIT(11)
42 #define ATAPI_CONTROL1_RESET BIT(7) 42 #define ATAPI_CONTROL1_RESET BIT(7)
43 #define ATAPI_CONTROL1_DESE BIT(3) 43 #define ATAPI_CONTROL1_DESE BIT(3)
44 #define ATAPI_CONTROL1_RW BIT(2) 44 #define ATAPI_CONTROL1_RW BIT(2)
45 #define ATAPI_CONTROL1_STOP BIT(1) 45 #define ATAPI_CONTROL1_STOP BIT(1)
46 #define ATAPI_CONTROL1_START BIT(0) 46 #define ATAPI_CONTROL1_START BIT(0)
47 47
48 /* ATAPI status register (ATAPI_STATUS) bits */ 48 /* ATAPI status register (ATAPI_STATUS) bits */
49 #define ATAPI_STATUS_SATAINT BIT(11) 49 #define ATAPI_STATUS_SATAINT BIT(11)
50 #define ATAPI_STATUS_DNEND BIT(6) 50 #define ATAPI_STATUS_DNEND BIT(6)
51 #define ATAPI_STATUS_DEVTRM BIT(5) 51 #define ATAPI_STATUS_DEVTRM BIT(5)
52 #define ATAPI_STATUS_DEVINT BIT(4) 52 #define ATAPI_STATUS_DEVINT BIT(4)
53 #define ATAPI_STATUS_ERR BIT(2) 53 #define ATAPI_STATUS_ERR BIT(2)
54 #define ATAPI_STATUS_NEND BIT(1) 54 #define ATAPI_STATUS_NEND BIT(1)
55 #define ATAPI_STATUS_ACT BIT(0) 55 #define ATAPI_STATUS_ACT BIT(0)
56 56
57 /* Interrupt enable register (ATAPI_INT_ENABLE) bits */ 57 /* Interrupt enable register (ATAPI_INT_ENABLE) bits */
58 #define ATAPI_INT_ENABLE_SATAINT BIT(11) 58 #define ATAPI_INT_ENABLE_SATAINT BIT(11)
59 #define ATAPI_INT_ENABLE_DNEND BIT(6) 59 #define ATAPI_INT_ENABLE_DNEND BIT(6)
60 #define ATAPI_INT_ENABLE_DEVTRM BIT(5) 60 #define ATAPI_INT_ENABLE_DEVTRM BIT(5)
61 #define ATAPI_INT_ENABLE_DEVINT BIT(4) 61 #define ATAPI_INT_ENABLE_DEVINT BIT(4)
62 #define ATAPI_INT_ENABLE_ERR BIT(2) 62 #define ATAPI_INT_ENABLE_ERR BIT(2)
63 #define ATAPI_INT_ENABLE_NEND BIT(1) 63 #define ATAPI_INT_ENABLE_NEND BIT(1)
64 #define ATAPI_INT_ENABLE_ACT BIT(0) 64 #define ATAPI_INT_ENABLE_ACT BIT(0)
65 65
66 /* Access control registers for physical layer control register */ 66 /* Access control registers for physical layer control register */
67 #define SATAPHYADDR_REG 0x200 67 #define SATAPHYADDR_REG 0x200
68 #define SATAPHYWDATA_REG 0x204 68 #define SATAPHYWDATA_REG 0x204
69 #define SATAPHYACCEN_REG 0x208 69 #define SATAPHYACCEN_REG 0x208
70 #define SATAPHYRESET_REG 0x20C 70 #define SATAPHYRESET_REG 0x20C
71 #define SATAPHYRDATA_REG 0x210 71 #define SATAPHYRDATA_REG 0x210
72 #define SATAPHYACK_REG 0x214 72 #define SATAPHYACK_REG 0x214
73 73
74 /* Physical layer control address command register (SATAPHYADDR) bits */ 74 /* Physical layer control address command register (SATAPHYADDR) bits */
75 #define SATAPHYADDR_PHYRATEMODE BIT(10) 75 #define SATAPHYADDR_PHYRATEMODE BIT(10)
76 #define SATAPHYADDR_PHYCMD_READ BIT(9) 76 #define SATAPHYADDR_PHYCMD_READ BIT(9)
77 #define SATAPHYADDR_PHYCMD_WRITE BIT(8) 77 #define SATAPHYADDR_PHYCMD_WRITE BIT(8)
78 78
79 /* Physical layer control enable register (SATAPHYACCEN) bits */ 79 /* Physical layer control enable register (SATAPHYACCEN) bits */
80 #define SATAPHYACCEN_PHYLANE BIT(0) 80 #define SATAPHYACCEN_PHYLANE BIT(0)
81 81
82 /* Physical layer control reset register (SATAPHYRESET) bits */ 82 /* Physical layer control reset register (SATAPHYRESET) bits */
83 #define SATAPHYRESET_PHYRST BIT(1) 83 #define SATAPHYRESET_PHYRST BIT(1)
84 #define SATAPHYRESET_PHYSRES BIT(0) 84 #define SATAPHYRESET_PHYSRES BIT(0)
85 85
86 /* Physical layer control acknowledge register (SATAPHYACK) bits */ 86 /* Physical layer control acknowledge register (SATAPHYACK) bits */
87 #define SATAPHYACK_PHYACK BIT(0) 87 #define SATAPHYACK_PHYACK BIT(0)
88 88
89 /* Serial-ATA HOST control registers */ 89 /* Serial-ATA HOST control registers */
90 #define BISTCONF_REG 0x102C 90 #define BISTCONF_REG 0x102C
91 #define SDATA_REG 0x1100 91 #define SDATA_REG 0x1100
92 #define SSDEVCON_REG 0x1204 92 #define SSDEVCON_REG 0x1204
93 93
94 #define SCRSSTS_REG 0x1400 94 #define SCRSSTS_REG 0x1400
95 #define SCRSERR_REG 0x1404 95 #define SCRSERR_REG 0x1404
96 #define SCRSCON_REG 0x1408 96 #define SCRSCON_REG 0x1408
97 #define SCRSACT_REG 0x140C 97 #define SCRSACT_REG 0x140C
98 98
99 #define SATAINTSTAT_REG 0x1508 99 #define SATAINTSTAT_REG 0x1508
100 #define SATAINTMASK_REG 0x150C 100 #define SATAINTMASK_REG 0x150C
101 101
102 /* SATA INT status register (SATAINTSTAT) bits */ 102 /* SATA INT status register (SATAINTSTAT) bits */
103 #define SATAINTSTAT_SERR BIT(3) 103 #define SATAINTSTAT_SERR BIT(3)
104 #define SATAINTSTAT_ATA BIT(0) 104 #define SATAINTSTAT_ATA BIT(0)
105 105
106 /* SATA INT mask register (SATAINTSTAT) bits */ 106 /* SATA INT mask register (SATAINTSTAT) bits */
107 #define SATAINTMASK_SERRMSK BIT(3) 107 #define SATAINTMASK_SERRMSK BIT(3)
108 #define SATAINTMASK_ERRMSK BIT(2) 108 #define SATAINTMASK_ERRMSK BIT(2)
109 #define SATAINTMASK_ERRCRTMSK BIT(1) 109 #define SATAINTMASK_ERRCRTMSK BIT(1)
110 #define SATAINTMASK_ATAMSK BIT(0) 110 #define SATAINTMASK_ATAMSK BIT(0)
111 111
112 #define SATA_RCAR_INT_MASK (SATAINTMASK_SERRMSK | \ 112 #define SATA_RCAR_INT_MASK (SATAINTMASK_SERRMSK | \
113 SATAINTMASK_ATAMSK) 113 SATAINTMASK_ATAMSK)
114 114
115 /* Physical Layer Control Registers */ 115 /* Physical Layer Control Registers */
116 #define SATAPCTLR1_REG 0x43 116 #define SATAPCTLR1_REG 0x43
117 #define SATAPCTLR2_REG 0x52 117 #define SATAPCTLR2_REG 0x52
118 #define SATAPCTLR3_REG 0x5A 118 #define SATAPCTLR3_REG 0x5A
119 #define SATAPCTLR4_REG 0x60 119 #define SATAPCTLR4_REG 0x60
120 120
121 /* Descriptor table word 0 bit (when DTA32M = 1) */ 121 /* Descriptor table word 0 bit (when DTA32M = 1) */
122 #define SATA_RCAR_DTEND BIT(0) 122 #define SATA_RCAR_DTEND BIT(0)
123 123
124 #define SATA_RCAR_DMA_BOUNDARY 0x1FFFFFFEUL 124 #define SATA_RCAR_DMA_BOUNDARY 0x1FFFFFFEUL
125 125
126 struct sata_rcar_priv { 126 struct sata_rcar_priv {
127 void __iomem *base; 127 void __iomem *base;
128 struct clk *clk; 128 struct clk *clk;
129 }; 129 };
130 130
131 static void sata_rcar_phy_initialize(struct sata_rcar_priv *priv) 131 static void sata_rcar_phy_initialize(struct sata_rcar_priv *priv)
132 { 132 {
133 void __iomem *base = priv->base; 133 void __iomem *base = priv->base;
134 134
135 /* idle state */ 135 /* idle state */
136 iowrite32(0, base + SATAPHYADDR_REG); 136 iowrite32(0, base + SATAPHYADDR_REG);
137 /* reset */ 137 /* reset */
138 iowrite32(SATAPHYRESET_PHYRST, base + SATAPHYRESET_REG); 138 iowrite32(SATAPHYRESET_PHYRST, base + SATAPHYRESET_REG);
139 udelay(10); 139 udelay(10);
140 /* deassert reset */ 140 /* deassert reset */
141 iowrite32(0, base + SATAPHYRESET_REG); 141 iowrite32(0, base + SATAPHYRESET_REG);
142 } 142 }
143 143
144 static void sata_rcar_phy_write(struct sata_rcar_priv *priv, u16 reg, u32 val, 144 static void sata_rcar_phy_write(struct sata_rcar_priv *priv, u16 reg, u32 val,
145 int group) 145 int group)
146 { 146 {
147 void __iomem *base = priv->base; 147 void __iomem *base = priv->base;
148 int timeout; 148 int timeout;
149 149
150 /* deassert reset */ 150 /* deassert reset */
151 iowrite32(0, base + SATAPHYRESET_REG); 151 iowrite32(0, base + SATAPHYRESET_REG);
152 /* lane 1 */ 152 /* lane 1 */
153 iowrite32(SATAPHYACCEN_PHYLANE, base + SATAPHYACCEN_REG); 153 iowrite32(SATAPHYACCEN_PHYLANE, base + SATAPHYACCEN_REG);
154 /* write phy register value */ 154 /* write phy register value */
155 iowrite32(val, base + SATAPHYWDATA_REG); 155 iowrite32(val, base + SATAPHYWDATA_REG);
156 /* set register group */ 156 /* set register group */
157 if (group) 157 if (group)
158 reg |= SATAPHYADDR_PHYRATEMODE; 158 reg |= SATAPHYADDR_PHYRATEMODE;
159 /* write command */ 159 /* write command */
160 iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, base + SATAPHYADDR_REG); 160 iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, base + SATAPHYADDR_REG);
161 /* wait for ack */ 161 /* wait for ack */
162 for (timeout = 0; timeout < 100; timeout++) { 162 for (timeout = 0; timeout < 100; timeout++) {
163 val = ioread32(base + SATAPHYACK_REG); 163 val = ioread32(base + SATAPHYACK_REG);
164 if (val & SATAPHYACK_PHYACK) 164 if (val & SATAPHYACK_PHYACK)
165 break; 165 break;
166 } 166 }
167 if (timeout >= 100) 167 if (timeout >= 100)
168 pr_err("%s timeout\n", __func__); 168 pr_err("%s timeout\n", __func__);
169 /* idle state */ 169 /* idle state */
170 iowrite32(0, base + SATAPHYADDR_REG); 170 iowrite32(0, base + SATAPHYADDR_REG);
171 } 171 }
172 172
173 static void sata_rcar_freeze(struct ata_port *ap) 173 static void sata_rcar_freeze(struct ata_port *ap)
174 { 174 {
175 struct sata_rcar_priv *priv = ap->host->private_data; 175 struct sata_rcar_priv *priv = ap->host->private_data;
176 176
177 /* mask */ 177 /* mask */
178 iowrite32(0x7ff, priv->base + SATAINTMASK_REG); 178 iowrite32(0x7ff, priv->base + SATAINTMASK_REG);
179 179
180 ata_sff_freeze(ap); 180 ata_sff_freeze(ap);
181 } 181 }
182 182
183 static void sata_rcar_thaw(struct ata_port *ap) 183 static void sata_rcar_thaw(struct ata_port *ap)
184 { 184 {
185 struct sata_rcar_priv *priv = ap->host->private_data; 185 struct sata_rcar_priv *priv = ap->host->private_data;
186 void __iomem *base = priv->base; 186 void __iomem *base = priv->base;
187 187
188 /* ack */ 188 /* ack */
189 iowrite32(~(u32)SATA_RCAR_INT_MASK, base + SATAINTSTAT_REG); 189 iowrite32(~(u32)SATA_RCAR_INT_MASK, base + SATAINTSTAT_REG);
190 190
191 ata_sff_thaw(ap); 191 ata_sff_thaw(ap);
192 192
193 /* unmask */ 193 /* unmask */
194 iowrite32(0x7ff & ~SATA_RCAR_INT_MASK, base + SATAINTMASK_REG); 194 iowrite32(0x7ff & ~SATA_RCAR_INT_MASK, base + SATAINTMASK_REG);
195 } 195 }
196 196
197 static void sata_rcar_ioread16_rep(void __iomem *reg, void *buffer, int count) 197 static void sata_rcar_ioread16_rep(void __iomem *reg, void *buffer, int count)
198 { 198 {
199 u16 *ptr = buffer; 199 u16 *ptr = buffer;
200 200
201 while (count--) { 201 while (count--) {
202 u16 data = ioread32(reg); 202 u16 data = ioread32(reg);
203 203
204 *ptr++ = data; 204 *ptr++ = data;
205 } 205 }
206 } 206 }
207 207
208 static void sata_rcar_iowrite16_rep(void __iomem *reg, void *buffer, int count) 208 static void sata_rcar_iowrite16_rep(void __iomem *reg, void *buffer, int count)
209 { 209 {
210 const u16 *ptr = buffer; 210 const u16 *ptr = buffer;
211 211
212 while (count--) 212 while (count--)
213 iowrite32(*ptr++, reg); 213 iowrite32(*ptr++, reg);
214 } 214 }
215 215
216 static u8 sata_rcar_check_status(struct ata_port *ap) 216 static u8 sata_rcar_check_status(struct ata_port *ap)
217 { 217 {
218 return ioread32(ap->ioaddr.status_addr); 218 return ioread32(ap->ioaddr.status_addr);
219 } 219 }
220 220
221 static u8 sata_rcar_check_altstatus(struct ata_port *ap) 221 static u8 sata_rcar_check_altstatus(struct ata_port *ap)
222 { 222 {
223 return ioread32(ap->ioaddr.altstatus_addr); 223 return ioread32(ap->ioaddr.altstatus_addr);
224 } 224 }
225 225
226 static void sata_rcar_set_devctl(struct ata_port *ap, u8 ctl) 226 static void sata_rcar_set_devctl(struct ata_port *ap, u8 ctl)
227 { 227 {
228 iowrite32(ctl, ap->ioaddr.ctl_addr); 228 iowrite32(ctl, ap->ioaddr.ctl_addr);
229 } 229 }
230 230
231 static void sata_rcar_dev_select(struct ata_port *ap, unsigned int device) 231 static void sata_rcar_dev_select(struct ata_port *ap, unsigned int device)
232 { 232 {
233 iowrite32(ATA_DEVICE_OBS, ap->ioaddr.device_addr); 233 iowrite32(ATA_DEVICE_OBS, ap->ioaddr.device_addr);
234 ata_sff_pause(ap); /* needed; also flushes, for mmio */ 234 ata_sff_pause(ap); /* needed; also flushes, for mmio */
235 } 235 }
236 236
237 static unsigned int sata_rcar_ata_devchk(struct ata_port *ap, 237 static unsigned int sata_rcar_ata_devchk(struct ata_port *ap,
238 unsigned int device) 238 unsigned int device)
239 { 239 {
240 struct ata_ioports *ioaddr = &ap->ioaddr; 240 struct ata_ioports *ioaddr = &ap->ioaddr;
241 u8 nsect, lbal; 241 u8 nsect, lbal;
242 242
243 sata_rcar_dev_select(ap, device); 243 sata_rcar_dev_select(ap, device);
244 244
245 iowrite32(0x55, ioaddr->nsect_addr); 245 iowrite32(0x55, ioaddr->nsect_addr);
246 iowrite32(0xaa, ioaddr->lbal_addr); 246 iowrite32(0xaa, ioaddr->lbal_addr);
247 247
248 iowrite32(0xaa, ioaddr->nsect_addr); 248 iowrite32(0xaa, ioaddr->nsect_addr);
249 iowrite32(0x55, ioaddr->lbal_addr); 249 iowrite32(0x55, ioaddr->lbal_addr);
250 250
251 iowrite32(0x55, ioaddr->nsect_addr); 251 iowrite32(0x55, ioaddr->nsect_addr);
252 iowrite32(0xaa, ioaddr->lbal_addr); 252 iowrite32(0xaa, ioaddr->lbal_addr);
253 253
254 nsect = ioread32(ioaddr->nsect_addr); 254 nsect = ioread32(ioaddr->nsect_addr);
255 lbal = ioread32(ioaddr->lbal_addr); 255 lbal = ioread32(ioaddr->lbal_addr);
256 256
257 if (nsect == 0x55 && lbal == 0xaa) 257 if (nsect == 0x55 && lbal == 0xaa)
258 return 1; /* found a device */ 258 return 1; /* found a device */
259 259
260 return 0; /* nothing found */ 260 return 0; /* nothing found */
261 } 261 }
262 262
263 static int sata_rcar_wait_after_reset(struct ata_link *link, 263 static int sata_rcar_wait_after_reset(struct ata_link *link,
264 unsigned long deadline) 264 unsigned long deadline)
265 { 265 {
266 struct ata_port *ap = link->ap; 266 struct ata_port *ap = link->ap;
267 267
268 ata_msleep(ap, ATA_WAIT_AFTER_RESET); 268 ata_msleep(ap, ATA_WAIT_AFTER_RESET);
269 269
270 return ata_sff_wait_ready(link, deadline); 270 return ata_sff_wait_ready(link, deadline);
271 } 271 }
272 272
273 static int sata_rcar_bus_softreset(struct ata_port *ap, unsigned long deadline) 273 static int sata_rcar_bus_softreset(struct ata_port *ap, unsigned long deadline)
274 { 274 {
275 struct ata_ioports *ioaddr = &ap->ioaddr; 275 struct ata_ioports *ioaddr = &ap->ioaddr;
276 276
277 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id); 277 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
278 278
279 /* software reset. causes dev0 to be selected */ 279 /* software reset. causes dev0 to be selected */
280 iowrite32(ap->ctl, ioaddr->ctl_addr); 280 iowrite32(ap->ctl, ioaddr->ctl_addr);
281 udelay(20); 281 udelay(20);
282 iowrite32(ap->ctl | ATA_SRST, ioaddr->ctl_addr); 282 iowrite32(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
283 udelay(20); 283 udelay(20);
284 iowrite32(ap->ctl, ioaddr->ctl_addr); 284 iowrite32(ap->ctl, ioaddr->ctl_addr);
285 ap->last_ctl = ap->ctl; 285 ap->last_ctl = ap->ctl;
286 286
287 /* wait the port to become ready */ 287 /* wait the port to become ready */
288 return sata_rcar_wait_after_reset(&ap->link, deadline); 288 return sata_rcar_wait_after_reset(&ap->link, deadline);
289 } 289 }
290 290
291 static int sata_rcar_softreset(struct ata_link *link, unsigned int *classes, 291 static int sata_rcar_softreset(struct ata_link *link, unsigned int *classes,
292 unsigned long deadline) 292 unsigned long deadline)
293 { 293 {
294 struct ata_port *ap = link->ap; 294 struct ata_port *ap = link->ap;
295 unsigned int devmask = 0; 295 unsigned int devmask = 0;
296 int rc; 296 int rc;
297 u8 err; 297 u8 err;
298 298
299 /* determine if device 0 is present */ 299 /* determine if device 0 is present */
300 if (sata_rcar_ata_devchk(ap, 0)) 300 if (sata_rcar_ata_devchk(ap, 0))
301 devmask |= 1 << 0; 301 devmask |= 1 << 0;
302 302
303 /* issue bus reset */ 303 /* issue bus reset */
304 DPRINTK("about to softreset, devmask=%x\n", devmask); 304 DPRINTK("about to softreset, devmask=%x\n", devmask);
305 rc = sata_rcar_bus_softreset(ap, deadline); 305 rc = sata_rcar_bus_softreset(ap, deadline);
306 /* if link is occupied, -ENODEV too is an error */ 306 /* if link is occupied, -ENODEV too is an error */
307 if (rc && (rc != -ENODEV || sata_scr_valid(link))) { 307 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
308 ata_link_err(link, "SRST failed (errno=%d)\n", rc); 308 ata_link_err(link, "SRST failed (errno=%d)\n", rc);
309 return rc; 309 return rc;
310 } 310 }
311 311
312 /* determine by signature whether we have ATA or ATAPI devices */ 312 /* determine by signature whether we have ATA or ATAPI devices */
313 classes[0] = ata_sff_dev_classify(&link->device[0], devmask, &err); 313 classes[0] = ata_sff_dev_classify(&link->device[0], devmask, &err);
314 314
315 DPRINTK("classes[0]=%u\n", classes[0]); 315 DPRINTK("classes[0]=%u\n", classes[0]);
316 return 0; 316 return 0;
317 } 317 }
318 318
319 static void sata_rcar_tf_load(struct ata_port *ap, 319 static void sata_rcar_tf_load(struct ata_port *ap,
320 const struct ata_taskfile *tf) 320 const struct ata_taskfile *tf)
321 { 321 {
322 struct ata_ioports *ioaddr = &ap->ioaddr; 322 struct ata_ioports *ioaddr = &ap->ioaddr;
323 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; 323 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
324 324
325 if (tf->ctl != ap->last_ctl) { 325 if (tf->ctl != ap->last_ctl) {
326 iowrite32(tf->ctl, ioaddr->ctl_addr); 326 iowrite32(tf->ctl, ioaddr->ctl_addr);
327 ap->last_ctl = tf->ctl; 327 ap->last_ctl = tf->ctl;
328 ata_wait_idle(ap); 328 ata_wait_idle(ap);
329 } 329 }
330 330
331 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { 331 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
332 iowrite32(tf->hob_feature, ioaddr->feature_addr); 332 iowrite32(tf->hob_feature, ioaddr->feature_addr);
333 iowrite32(tf->hob_nsect, ioaddr->nsect_addr); 333 iowrite32(tf->hob_nsect, ioaddr->nsect_addr);
334 iowrite32(tf->hob_lbal, ioaddr->lbal_addr); 334 iowrite32(tf->hob_lbal, ioaddr->lbal_addr);
335 iowrite32(tf->hob_lbam, ioaddr->lbam_addr); 335 iowrite32(tf->hob_lbam, ioaddr->lbam_addr);
336 iowrite32(tf->hob_lbah, ioaddr->lbah_addr); 336 iowrite32(tf->hob_lbah, ioaddr->lbah_addr);
337 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", 337 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
338 tf->hob_feature, 338 tf->hob_feature,
339 tf->hob_nsect, 339 tf->hob_nsect,
340 tf->hob_lbal, 340 tf->hob_lbal,
341 tf->hob_lbam, 341 tf->hob_lbam,
342 tf->hob_lbah); 342 tf->hob_lbah);
343 } 343 }
344 344
345 if (is_addr) { 345 if (is_addr) {
346 iowrite32(tf->feature, ioaddr->feature_addr); 346 iowrite32(tf->feature, ioaddr->feature_addr);
347 iowrite32(tf->nsect, ioaddr->nsect_addr); 347 iowrite32(tf->nsect, ioaddr->nsect_addr);
348 iowrite32(tf->lbal, ioaddr->lbal_addr); 348 iowrite32(tf->lbal, ioaddr->lbal_addr);
349 iowrite32(tf->lbam, ioaddr->lbam_addr); 349 iowrite32(tf->lbam, ioaddr->lbam_addr);
350 iowrite32(tf->lbah, ioaddr->lbah_addr); 350 iowrite32(tf->lbah, ioaddr->lbah_addr);
351 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", 351 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
352 tf->feature, 352 tf->feature,
353 tf->nsect, 353 tf->nsect,
354 tf->lbal, 354 tf->lbal,
355 tf->lbam, 355 tf->lbam,
356 tf->lbah); 356 tf->lbah);
357 } 357 }
358 358
359 if (tf->flags & ATA_TFLAG_DEVICE) { 359 if (tf->flags & ATA_TFLAG_DEVICE) {
360 iowrite32(tf->device, ioaddr->device_addr); 360 iowrite32(tf->device, ioaddr->device_addr);
361 VPRINTK("device 0x%X\n", tf->device); 361 VPRINTK("device 0x%X\n", tf->device);
362 } 362 }
363 363
364 ata_wait_idle(ap); 364 ata_wait_idle(ap);
365 } 365 }
366 366
367 static void sata_rcar_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 367 static void sata_rcar_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
368 { 368 {
369 struct ata_ioports *ioaddr = &ap->ioaddr; 369 struct ata_ioports *ioaddr = &ap->ioaddr;
370 370
371 tf->command = sata_rcar_check_status(ap); 371 tf->command = sata_rcar_check_status(ap);
372 tf->feature = ioread32(ioaddr->error_addr); 372 tf->feature = ioread32(ioaddr->error_addr);
373 tf->nsect = ioread32(ioaddr->nsect_addr); 373 tf->nsect = ioread32(ioaddr->nsect_addr);
374 tf->lbal = ioread32(ioaddr->lbal_addr); 374 tf->lbal = ioread32(ioaddr->lbal_addr);
375 tf->lbam = ioread32(ioaddr->lbam_addr); 375 tf->lbam = ioread32(ioaddr->lbam_addr);
376 tf->lbah = ioread32(ioaddr->lbah_addr); 376 tf->lbah = ioread32(ioaddr->lbah_addr);
377 tf->device = ioread32(ioaddr->device_addr); 377 tf->device = ioread32(ioaddr->device_addr);
378 378
379 if (tf->flags & ATA_TFLAG_LBA48) { 379 if (tf->flags & ATA_TFLAG_LBA48) {
380 iowrite32(tf->ctl | ATA_HOB, ioaddr->ctl_addr); 380 iowrite32(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
381 tf->hob_feature = ioread32(ioaddr->error_addr); 381 tf->hob_feature = ioread32(ioaddr->error_addr);
382 tf->hob_nsect = ioread32(ioaddr->nsect_addr); 382 tf->hob_nsect = ioread32(ioaddr->nsect_addr);
383 tf->hob_lbal = ioread32(ioaddr->lbal_addr); 383 tf->hob_lbal = ioread32(ioaddr->lbal_addr);
384 tf->hob_lbam = ioread32(ioaddr->lbam_addr); 384 tf->hob_lbam = ioread32(ioaddr->lbam_addr);
385 tf->hob_lbah = ioread32(ioaddr->lbah_addr); 385 tf->hob_lbah = ioread32(ioaddr->lbah_addr);
386 iowrite32(tf->ctl, ioaddr->ctl_addr); 386 iowrite32(tf->ctl, ioaddr->ctl_addr);
387 ap->last_ctl = tf->ctl; 387 ap->last_ctl = tf->ctl;
388 } 388 }
389 } 389 }
390 390
391 static void sata_rcar_exec_command(struct ata_port *ap, 391 static void sata_rcar_exec_command(struct ata_port *ap,
392 const struct ata_taskfile *tf) 392 const struct ata_taskfile *tf)
393 { 393 {
394 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); 394 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
395 395
396 iowrite32(tf->command, ap->ioaddr.command_addr); 396 iowrite32(tf->command, ap->ioaddr.command_addr);
397 ata_sff_pause(ap); 397 ata_sff_pause(ap);
398 } 398 }
399 399
400 static unsigned int sata_rcar_data_xfer(struct ata_device *dev, 400 static unsigned int sata_rcar_data_xfer(struct ata_device *dev,
401 unsigned char *buf, 401 unsigned char *buf,
402 unsigned int buflen, int rw) 402 unsigned int buflen, int rw)
403 { 403 {
404 struct ata_port *ap = dev->link->ap; 404 struct ata_port *ap = dev->link->ap;
405 void __iomem *data_addr = ap->ioaddr.data_addr; 405 void __iomem *data_addr = ap->ioaddr.data_addr;
406 unsigned int words = buflen >> 1; 406 unsigned int words = buflen >> 1;
407 407
408 /* Transfer multiple of 2 bytes */ 408 /* Transfer multiple of 2 bytes */
409 if (rw == READ) 409 if (rw == READ)
410 sata_rcar_ioread16_rep(data_addr, buf, words); 410 sata_rcar_ioread16_rep(data_addr, buf, words);
411 else 411 else
412 sata_rcar_iowrite16_rep(data_addr, buf, words); 412 sata_rcar_iowrite16_rep(data_addr, buf, words);
413 413
414 /* Transfer trailing byte, if any. */ 414 /* Transfer trailing byte, if any. */
415 if (unlikely(buflen & 0x01)) { 415 if (unlikely(buflen & 0x01)) {
416 unsigned char pad[2] = { }; 416 unsigned char pad[2] = { };
417 417
418 /* Point buf to the tail of buffer */ 418 /* Point buf to the tail of buffer */
419 buf += buflen - 1; 419 buf += buflen - 1;
420 420
421 /* 421 /*
422 * Use io*16_rep() accessors here as well to avoid pointlessly 422 * Use io*16_rep() accessors here as well to avoid pointlessly
423 * swapping bytes to and from on the big endian machines... 423 * swapping bytes to and from on the big endian machines...
424 */ 424 */
425 if (rw == READ) { 425 if (rw == READ) {
426 sata_rcar_ioread16_rep(data_addr, pad, 1); 426 sata_rcar_ioread16_rep(data_addr, pad, 1);
427 *buf = pad[0]; 427 *buf = pad[0];
428 } else { 428 } else {
429 pad[0] = *buf; 429 pad[0] = *buf;
430 sata_rcar_iowrite16_rep(data_addr, pad, 1); 430 sata_rcar_iowrite16_rep(data_addr, pad, 1);
431 } 431 }
432 words++; 432 words++;
433 } 433 }
434 434
435 return words << 1; 435 return words << 1;
436 } 436 }
437 437
438 static void sata_rcar_drain_fifo(struct ata_queued_cmd *qc) 438 static void sata_rcar_drain_fifo(struct ata_queued_cmd *qc)
439 { 439 {
440 int count; 440 int count;
441 struct ata_port *ap; 441 struct ata_port *ap;
442 442
443 /* We only need to flush incoming data when a command was running */ 443 /* We only need to flush incoming data when a command was running */
444 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE) 444 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
445 return; 445 return;
446 446
447 ap = qc->ap; 447 ap = qc->ap;
448 /* Drain up to 64K of data before we give up this recovery method */ 448 /* Drain up to 64K of data before we give up this recovery method */
449 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) && 449 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) &&
450 count < 65536; count += 2) 450 count < 65536; count += 2)
451 ioread32(ap->ioaddr.data_addr); 451 ioread32(ap->ioaddr.data_addr);
452 452
453 /* Can become DEBUG later */ 453 /* Can become DEBUG later */
454 if (count) 454 if (count)
455 ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count); 455 ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count);
456 } 456 }
457 457
458 static int sata_rcar_scr_read(struct ata_link *link, unsigned int sc_reg, 458 static int sata_rcar_scr_read(struct ata_link *link, unsigned int sc_reg,
459 u32 *val) 459 u32 *val)
460 { 460 {
461 if (sc_reg > SCR_ACTIVE) 461 if (sc_reg > SCR_ACTIVE)
462 return -EINVAL; 462 return -EINVAL;
463 463
464 *val = ioread32(link->ap->ioaddr.scr_addr + (sc_reg << 2)); 464 *val = ioread32(link->ap->ioaddr.scr_addr + (sc_reg << 2));
465 return 0; 465 return 0;
466 } 466 }
467 467
468 static int sata_rcar_scr_write(struct ata_link *link, unsigned int sc_reg, 468 static int sata_rcar_scr_write(struct ata_link *link, unsigned int sc_reg,
469 u32 val) 469 u32 val)
470 { 470 {
471 if (sc_reg > SCR_ACTIVE) 471 if (sc_reg > SCR_ACTIVE)
472 return -EINVAL; 472 return -EINVAL;
473 473
474 iowrite32(val, link->ap->ioaddr.scr_addr + (sc_reg << 2)); 474 iowrite32(val, link->ap->ioaddr.scr_addr + (sc_reg << 2));
475 return 0; 475 return 0;
476 } 476 }
477 477
478 static void sata_rcar_bmdma_fill_sg(struct ata_queued_cmd *qc) 478 static void sata_rcar_bmdma_fill_sg(struct ata_queued_cmd *qc)
479 { 479 {
480 struct ata_port *ap = qc->ap; 480 struct ata_port *ap = qc->ap;
481 struct ata_bmdma_prd *prd = ap->bmdma_prd; 481 struct ata_bmdma_prd *prd = ap->bmdma_prd;
482 struct scatterlist *sg; 482 struct scatterlist *sg;
483 unsigned int si; 483 unsigned int si;
484 484
485 for_each_sg(qc->sg, sg, qc->n_elem, si) { 485 for_each_sg(qc->sg, sg, qc->n_elem, si) {
486 u32 addr, sg_len; 486 u32 addr, sg_len;
487 487
488 /* 488 /*
489 * Note: h/w doesn't support 64-bit, so we unconditionally 489 * Note: h/w doesn't support 64-bit, so we unconditionally
490 * truncate dma_addr_t to u32. 490 * truncate dma_addr_t to u32.
491 */ 491 */
492 addr = (u32)sg_dma_address(sg); 492 addr = (u32)sg_dma_address(sg);
493 sg_len = sg_dma_len(sg); 493 sg_len = sg_dma_len(sg);
494 494
495 prd[si].addr = cpu_to_le32(addr); 495 prd[si].addr = cpu_to_le32(addr);
496 prd[si].flags_len = cpu_to_le32(sg_len); 496 prd[si].flags_len = cpu_to_le32(sg_len);
497 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", si, addr, sg_len); 497 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", si, addr, sg_len);
498 } 498 }
499 499
500 /* end-of-table flag */ 500 /* end-of-table flag */
501 prd[si - 1].addr |= cpu_to_le32(SATA_RCAR_DTEND); 501 prd[si - 1].addr |= cpu_to_le32(SATA_RCAR_DTEND);
502 } 502 }
503 503
504 static void sata_rcar_qc_prep(struct ata_queued_cmd *qc) 504 static void sata_rcar_qc_prep(struct ata_queued_cmd *qc)
505 { 505 {
506 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 506 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
507 return; 507 return;
508 508
509 sata_rcar_bmdma_fill_sg(qc); 509 sata_rcar_bmdma_fill_sg(qc);
510 } 510 }
511 511
512 static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc) 512 static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc)
513 { 513 {
514 struct ata_port *ap = qc->ap; 514 struct ata_port *ap = qc->ap;
515 unsigned int rw = qc->tf.flags & ATA_TFLAG_WRITE; 515 unsigned int rw = qc->tf.flags & ATA_TFLAG_WRITE;
516 struct sata_rcar_priv *priv = ap->host->private_data; 516 struct sata_rcar_priv *priv = ap->host->private_data;
517 void __iomem *base = priv->base; 517 void __iomem *base = priv->base;
518 u32 dmactl; 518 u32 dmactl;
519 519
520 /* load PRD table addr. */ 520 /* load PRD table addr. */
521 mb(); /* make sure PRD table writes are visible to controller */ 521 mb(); /* make sure PRD table writes are visible to controller */
522 iowrite32(ap->bmdma_prd_dma, base + ATAPI_DTB_ADR_REG); 522 iowrite32(ap->bmdma_prd_dma, base + ATAPI_DTB_ADR_REG);
523 523
524 /* specify data direction, triple-check start bit is clear */ 524 /* specify data direction, triple-check start bit is clear */
525 dmactl = ioread32(base + ATAPI_CONTROL1_REG); 525 dmactl = ioread32(base + ATAPI_CONTROL1_REG);
526 dmactl &= ~(ATAPI_CONTROL1_RW | ATAPI_CONTROL1_STOP); 526 dmactl &= ~(ATAPI_CONTROL1_RW | ATAPI_CONTROL1_STOP);
527 if (dmactl & ATAPI_CONTROL1_START) { 527 if (dmactl & ATAPI_CONTROL1_START) {
528 dmactl &= ~ATAPI_CONTROL1_START; 528 dmactl &= ~ATAPI_CONTROL1_START;
529 dmactl |= ATAPI_CONTROL1_STOP; 529 dmactl |= ATAPI_CONTROL1_STOP;
530 } 530 }
531 if (!rw) 531 if (!rw)
532 dmactl |= ATAPI_CONTROL1_RW; 532 dmactl |= ATAPI_CONTROL1_RW;
533 iowrite32(dmactl, base + ATAPI_CONTROL1_REG); 533 iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
534 534
535 /* issue r/w command */ 535 /* issue r/w command */
536 ap->ops->sff_exec_command(ap, &qc->tf); 536 ap->ops->sff_exec_command(ap, &qc->tf);
537 } 537 }
538 538
539 static void sata_rcar_bmdma_start(struct ata_queued_cmd *qc) 539 static void sata_rcar_bmdma_start(struct ata_queued_cmd *qc)
540 { 540 {
541 struct ata_port *ap = qc->ap; 541 struct ata_port *ap = qc->ap;
542 struct sata_rcar_priv *priv = ap->host->private_data; 542 struct sata_rcar_priv *priv = ap->host->private_data;
543 void __iomem *base = priv->base; 543 void __iomem *base = priv->base;
544 u32 dmactl; 544 u32 dmactl;
545 545
546 /* start host DMA transaction */ 546 /* start host DMA transaction */
547 dmactl = ioread32(base + ATAPI_CONTROL1_REG); 547 dmactl = ioread32(base + ATAPI_CONTROL1_REG);
548 dmactl &= ~ATAPI_CONTROL1_STOP; 548 dmactl &= ~ATAPI_CONTROL1_STOP;
549 dmactl |= ATAPI_CONTROL1_START; 549 dmactl |= ATAPI_CONTROL1_START;
550 iowrite32(dmactl, base + ATAPI_CONTROL1_REG); 550 iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
551 } 551 }
552 552
553 static void sata_rcar_bmdma_stop(struct ata_queued_cmd *qc) 553 static void sata_rcar_bmdma_stop(struct ata_queued_cmd *qc)
554 { 554 {
555 struct ata_port *ap = qc->ap; 555 struct ata_port *ap = qc->ap;
556 struct sata_rcar_priv *priv = ap->host->private_data; 556 struct sata_rcar_priv *priv = ap->host->private_data;
557 void __iomem *base = priv->base; 557 void __iomem *base = priv->base;
558 u32 dmactl; 558 u32 dmactl;
559 559
560 /* force termination of DMA transfer if active */ 560 /* force termination of DMA transfer if active */
561 dmactl = ioread32(base + ATAPI_CONTROL1_REG); 561 dmactl = ioread32(base + ATAPI_CONTROL1_REG);
562 if (dmactl & ATAPI_CONTROL1_START) { 562 if (dmactl & ATAPI_CONTROL1_START) {
563 dmactl &= ~ATAPI_CONTROL1_START; 563 dmactl &= ~ATAPI_CONTROL1_START;
564 dmactl |= ATAPI_CONTROL1_STOP; 564 dmactl |= ATAPI_CONTROL1_STOP;
565 iowrite32(dmactl, base + ATAPI_CONTROL1_REG); 565 iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
566 } 566 }
567 567
568 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ 568 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
569 ata_sff_dma_pause(ap); 569 ata_sff_dma_pause(ap);
570 } 570 }
571 571
572 static u8 sata_rcar_bmdma_status(struct ata_port *ap) 572 static u8 sata_rcar_bmdma_status(struct ata_port *ap)
573 { 573 {
574 struct sata_rcar_priv *priv = ap->host->private_data; 574 struct sata_rcar_priv *priv = ap->host->private_data;
575 u8 host_stat = 0; 575 u8 host_stat = 0;
576 u32 status; 576 u32 status;
577 577
578 status = ioread32(priv->base + ATAPI_STATUS_REG); 578 status = ioread32(priv->base + ATAPI_STATUS_REG);
579 if (status & ATAPI_STATUS_DEVINT) 579 if (status & ATAPI_STATUS_DEVINT)
580 host_stat |= ATA_DMA_INTR; 580 host_stat |= ATA_DMA_INTR;
581 if (status & ATAPI_STATUS_ACT) 581 if (status & ATAPI_STATUS_ACT)
582 host_stat |= ATA_DMA_ACTIVE; 582 host_stat |= ATA_DMA_ACTIVE;
583 583
584 return host_stat; 584 return host_stat;
585 } 585 }
586 586
587 static struct scsi_host_template sata_rcar_sht = { 587 static struct scsi_host_template sata_rcar_sht = {
588 ATA_BASE_SHT(DRV_NAME), 588 ATA_BASE_SHT(DRV_NAME),
589 /* 589 /*
590 * This controller allows transfer chunks up to 512MB which cross 64KB 590 * This controller allows transfer chunks up to 512MB which cross 64KB
591 * boundaries, therefore the DMA limits are more relaxed than standard 591 * boundaries, therefore the DMA limits are more relaxed than standard
592 * ATA SFF. 592 * ATA SFF.
593 */ 593 */
594 .sg_tablesize = ATA_MAX_PRD, 594 .sg_tablesize = ATA_MAX_PRD,
595 .dma_boundary = SATA_RCAR_DMA_BOUNDARY, 595 .dma_boundary = SATA_RCAR_DMA_BOUNDARY,
596 }; 596 };
597 597
598 static struct ata_port_operations sata_rcar_port_ops = { 598 static struct ata_port_operations sata_rcar_port_ops = {
599 .inherits = &ata_bmdma_port_ops, 599 .inherits = &ata_bmdma_port_ops,
600 600
601 .freeze = sata_rcar_freeze, 601 .freeze = sata_rcar_freeze,
602 .thaw = sata_rcar_thaw, 602 .thaw = sata_rcar_thaw,
603 .softreset = sata_rcar_softreset, 603 .softreset = sata_rcar_softreset,
604 604
605 .scr_read = sata_rcar_scr_read, 605 .scr_read = sata_rcar_scr_read,
606 .scr_write = sata_rcar_scr_write, 606 .scr_write = sata_rcar_scr_write,
607 607
608 .sff_dev_select = sata_rcar_dev_select, 608 .sff_dev_select = sata_rcar_dev_select,
609 .sff_set_devctl = sata_rcar_set_devctl, 609 .sff_set_devctl = sata_rcar_set_devctl,
610 .sff_check_status = sata_rcar_check_status, 610 .sff_check_status = sata_rcar_check_status,
611 .sff_check_altstatus = sata_rcar_check_altstatus, 611 .sff_check_altstatus = sata_rcar_check_altstatus,
612 .sff_tf_load = sata_rcar_tf_load, 612 .sff_tf_load = sata_rcar_tf_load,
613 .sff_tf_read = sata_rcar_tf_read, 613 .sff_tf_read = sata_rcar_tf_read,
614 .sff_exec_command = sata_rcar_exec_command, 614 .sff_exec_command = sata_rcar_exec_command,
615 .sff_data_xfer = sata_rcar_data_xfer, 615 .sff_data_xfer = sata_rcar_data_xfer,
616 .sff_drain_fifo = sata_rcar_drain_fifo, 616 .sff_drain_fifo = sata_rcar_drain_fifo,
617 617
618 .qc_prep = sata_rcar_qc_prep, 618 .qc_prep = sata_rcar_qc_prep,
619 619
620 .bmdma_setup = sata_rcar_bmdma_setup, 620 .bmdma_setup = sata_rcar_bmdma_setup,
621 .bmdma_start = sata_rcar_bmdma_start, 621 .bmdma_start = sata_rcar_bmdma_start,
622 .bmdma_stop = sata_rcar_bmdma_stop, 622 .bmdma_stop = sata_rcar_bmdma_stop,
623 .bmdma_status = sata_rcar_bmdma_status, 623 .bmdma_status = sata_rcar_bmdma_status,
624 }; 624 };
625 625
626 static void sata_rcar_serr_interrupt(struct ata_port *ap) 626 static void sata_rcar_serr_interrupt(struct ata_port *ap)
627 { 627 {
628 struct sata_rcar_priv *priv = ap->host->private_data; 628 struct sata_rcar_priv *priv = ap->host->private_data;
629 struct ata_eh_info *ehi = &ap->link.eh_info; 629 struct ata_eh_info *ehi = &ap->link.eh_info;
630 int freeze = 0; 630 int freeze = 0;
631 u32 serror; 631 u32 serror;
632 632
633 serror = ioread32(priv->base + SCRSERR_REG); 633 serror = ioread32(priv->base + SCRSERR_REG);
634 if (!serror) 634 if (!serror)
635 return; 635 return;
636 636
637 DPRINTK("SError @host_intr: 0x%x\n", serror); 637 DPRINTK("SError @host_intr: 0x%x\n", serror);
638 638
639 /* first, analyze and record host port events */ 639 /* first, analyze and record host port events */
640 ata_ehi_clear_desc(ehi); 640 ata_ehi_clear_desc(ehi);
641 641
642 if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) { 642 if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) {
643 /* Setup a soft-reset EH action */ 643 /* Setup a soft-reset EH action */
644 ata_ehi_hotplugged(ehi); 644 ata_ehi_hotplugged(ehi);
645 ata_ehi_push_desc(ehi, "%s", "hotplug"); 645 ata_ehi_push_desc(ehi, "%s", "hotplug");
646 646
647 freeze = serror & SERR_COMM_WAKE ? 0 : 1; 647 freeze = serror & SERR_COMM_WAKE ? 0 : 1;
648 } 648 }
649 649
650 /* freeze or abort */ 650 /* freeze or abort */
651 if (freeze) 651 if (freeze)
652 ata_port_freeze(ap); 652 ata_port_freeze(ap);
653 else 653 else
654 ata_port_abort(ap); 654 ata_port_abort(ap);
655 } 655 }
656 656
657 static void sata_rcar_ata_interrupt(struct ata_port *ap) 657 static void sata_rcar_ata_interrupt(struct ata_port *ap)
658 { 658 {
659 struct ata_queued_cmd *qc; 659 struct ata_queued_cmd *qc;
660 int handled = 0; 660 int handled = 0;
661 661
662 qc = ata_qc_from_tag(ap, ap->link.active_tag); 662 qc = ata_qc_from_tag(ap, ap->link.active_tag);
663 if (qc) 663 if (qc)
664 handled |= ata_bmdma_port_intr(ap, qc); 664 handled |= ata_bmdma_port_intr(ap, qc);
665 665
666 /* be sure to clear ATA interrupt */ 666 /* be sure to clear ATA interrupt */
667 if (!handled) 667 if (!handled)
668 sata_rcar_check_status(ap); 668 sata_rcar_check_status(ap);
669 } 669 }
670 670
671 static irqreturn_t sata_rcar_interrupt(int irq, void *dev_instance) 671 static irqreturn_t sata_rcar_interrupt(int irq, void *dev_instance)
672 { 672 {
673 struct ata_host *host = dev_instance; 673 struct ata_host *host = dev_instance;
674 struct sata_rcar_priv *priv = host->private_data; 674 struct sata_rcar_priv *priv = host->private_data;
675 void __iomem *base = priv->base; 675 void __iomem *base = priv->base;
676 unsigned int handled = 0; 676 unsigned int handled = 0;
677 struct ata_port *ap; 677 struct ata_port *ap;
678 u32 sataintstat; 678 u32 sataintstat;
679 unsigned long flags; 679 unsigned long flags;
680 680
681 spin_lock_irqsave(&host->lock, flags); 681 spin_lock_irqsave(&host->lock, flags);
682 682
683 sataintstat = ioread32(base + SATAINTSTAT_REG); 683 sataintstat = ioread32(base + SATAINTSTAT_REG);
684 sataintstat &= SATA_RCAR_INT_MASK; 684 sataintstat &= SATA_RCAR_INT_MASK;
685 if (!sataintstat) 685 if (!sataintstat)
686 goto done; 686 goto done;
687 /* ack */ 687 /* ack */
688 iowrite32(~sataintstat & 0x7ff, base + SATAINTSTAT_REG); 688 iowrite32(~sataintstat & 0x7ff, base + SATAINTSTAT_REG);
689 689
690 ap = host->ports[0]; 690 ap = host->ports[0];
691 691
692 if (sataintstat & SATAINTSTAT_ATA) 692 if (sataintstat & SATAINTSTAT_ATA)
693 sata_rcar_ata_interrupt(ap); 693 sata_rcar_ata_interrupt(ap);
694 694
695 if (sataintstat & SATAINTSTAT_SERR) 695 if (sataintstat & SATAINTSTAT_SERR)
696 sata_rcar_serr_interrupt(ap); 696 sata_rcar_serr_interrupt(ap);
697 697
698 handled = 1; 698 handled = 1;
699 done: 699 done:
700 spin_unlock_irqrestore(&host->lock, flags); 700 spin_unlock_irqrestore(&host->lock, flags);
701 701
702 return IRQ_RETVAL(handled); 702 return IRQ_RETVAL(handled);
703 } 703 }
704 704
705 static void sata_rcar_setup_port(struct ata_host *host) 705 static void sata_rcar_setup_port(struct ata_host *host)
706 { 706 {
707 struct ata_port *ap = host->ports[0]; 707 struct ata_port *ap = host->ports[0];
708 struct ata_ioports *ioaddr = &ap->ioaddr; 708 struct ata_ioports *ioaddr = &ap->ioaddr;
709 struct sata_rcar_priv *priv = host->private_data; 709 struct sata_rcar_priv *priv = host->private_data;
710 void __iomem *base = priv->base; 710 void __iomem *base = priv->base;
711 711
712 ap->ops = &sata_rcar_port_ops; 712 ap->ops = &sata_rcar_port_ops;
713 ap->pio_mask = ATA_PIO4; 713 ap->pio_mask = ATA_PIO4;
714 ap->udma_mask = ATA_UDMA6; 714 ap->udma_mask = ATA_UDMA6;
715 ap->flags |= ATA_FLAG_SATA; 715 ap->flags |= ATA_FLAG_SATA;
716 716
717 ioaddr->cmd_addr = base + SDATA_REG; 717 ioaddr->cmd_addr = base + SDATA_REG;
718 ioaddr->ctl_addr = base + SSDEVCON_REG; 718 ioaddr->ctl_addr = base + SSDEVCON_REG;
719 ioaddr->scr_addr = base + SCRSSTS_REG; 719 ioaddr->scr_addr = base + SCRSSTS_REG;
720 ioaddr->altstatus_addr = ioaddr->ctl_addr; 720 ioaddr->altstatus_addr = ioaddr->ctl_addr;
721 721
722 ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << 2); 722 ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << 2);
723 ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << 2); 723 ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << 2);
724 ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << 2); 724 ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << 2);
725 ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << 2); 725 ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << 2);
726 ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << 2); 726 ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << 2);
727 ioaddr->lbam_addr = ioaddr->cmd_addr + (ATA_REG_LBAM << 2); 727 ioaddr->lbam_addr = ioaddr->cmd_addr + (ATA_REG_LBAM << 2);
728 ioaddr->lbah_addr = ioaddr->cmd_addr + (ATA_REG_LBAH << 2); 728 ioaddr->lbah_addr = ioaddr->cmd_addr + (ATA_REG_LBAH << 2);
729 ioaddr->device_addr = ioaddr->cmd_addr + (ATA_REG_DEVICE << 2); 729 ioaddr->device_addr = ioaddr->cmd_addr + (ATA_REG_DEVICE << 2);
730 ioaddr->status_addr = ioaddr->cmd_addr + (ATA_REG_STATUS << 2); 730 ioaddr->status_addr = ioaddr->cmd_addr + (ATA_REG_STATUS << 2);
731 ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << 2); 731 ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << 2);
732 } 732 }
733 733
734 static void sata_rcar_init_controller(struct ata_host *host) 734 static void sata_rcar_init_controller(struct ata_host *host)
735 { 735 {
736 struct sata_rcar_priv *priv = host->private_data; 736 struct sata_rcar_priv *priv = host->private_data;
737 void __iomem *base = priv->base; 737 void __iomem *base = priv->base;
738 u32 val; 738 u32 val;
739 739
740 /* reset and setup phy */ 740 /* reset and setup phy */
741 sata_rcar_phy_initialize(priv); 741 sata_rcar_phy_initialize(priv);
742 sata_rcar_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 0); 742 sata_rcar_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 0);
743 sata_rcar_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 1); 743 sata_rcar_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 1);
744 sata_rcar_phy_write(priv, SATAPCTLR3_REG, 0x0000A061, 0); 744 sata_rcar_phy_write(priv, SATAPCTLR3_REG, 0x0000A061, 0);
745 sata_rcar_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 0); 745 sata_rcar_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 0);
746 sata_rcar_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 1); 746 sata_rcar_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 1);
747 sata_rcar_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0); 747 sata_rcar_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0);
748 748
749 /* SATA-IP reset state */ 749 /* SATA-IP reset state */
750 val = ioread32(base + ATAPI_CONTROL1_REG); 750 val = ioread32(base + ATAPI_CONTROL1_REG);
751 val |= ATAPI_CONTROL1_RESET; 751 val |= ATAPI_CONTROL1_RESET;
752 iowrite32(val, base + ATAPI_CONTROL1_REG); 752 iowrite32(val, base + ATAPI_CONTROL1_REG);
753 753
754 /* ISM mode, PRD mode, DTEND flag at bit 0 */ 754 /* ISM mode, PRD mode, DTEND flag at bit 0 */
755 val = ioread32(base + ATAPI_CONTROL1_REG); 755 val = ioread32(base + ATAPI_CONTROL1_REG);
756 val |= ATAPI_CONTROL1_ISM; 756 val |= ATAPI_CONTROL1_ISM;
757 val |= ATAPI_CONTROL1_DESE; 757 val |= ATAPI_CONTROL1_DESE;
758 val |= ATAPI_CONTROL1_DTA32M; 758 val |= ATAPI_CONTROL1_DTA32M;
759 iowrite32(val, base + ATAPI_CONTROL1_REG); 759 iowrite32(val, base + ATAPI_CONTROL1_REG);
760 760
761 /* Release the SATA-IP from the reset state */ 761 /* Release the SATA-IP from the reset state */
762 val = ioread32(base + ATAPI_CONTROL1_REG); 762 val = ioread32(base + ATAPI_CONTROL1_REG);
763 val &= ~ATAPI_CONTROL1_RESET; 763 val &= ~ATAPI_CONTROL1_RESET;
764 iowrite32(val, base + ATAPI_CONTROL1_REG); 764 iowrite32(val, base + ATAPI_CONTROL1_REG);
765 765
766 /* ack and mask */ 766 /* ack and mask */
767 iowrite32(0, base + SATAINTSTAT_REG); 767 iowrite32(0, base + SATAINTSTAT_REG);
768 iowrite32(0x7ff, base + SATAINTMASK_REG); 768 iowrite32(0x7ff, base + SATAINTMASK_REG);
769 /* enable interrupts */ 769 /* enable interrupts */
770 iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG); 770 iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG);
771 } 771 }
772 772
773 static int sata_rcar_probe(struct platform_device *pdev) 773 static int sata_rcar_probe(struct platform_device *pdev)
774 { 774 {
775 struct ata_host *host; 775 struct ata_host *host;
776 struct sata_rcar_priv *priv; 776 struct sata_rcar_priv *priv;
777 struct resource *mem; 777 struct resource *mem;
778 int irq; 778 int irq;
779 int ret = 0; 779 int ret = 0;
780 780
781 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
782 if (mem == NULL)
783 return -EINVAL;
784
785 irq = platform_get_irq(pdev, 0); 781 irq = platform_get_irq(pdev, 0);
786 if (irq <= 0) 782 if (irq <= 0)
787 return -EINVAL; 783 return -EINVAL;
788 784
789 priv = devm_kzalloc(&pdev->dev, sizeof(struct sata_rcar_priv), 785 priv = devm_kzalloc(&pdev->dev, sizeof(struct sata_rcar_priv),
790 GFP_KERNEL); 786 GFP_KERNEL);
791 if (!priv) 787 if (!priv)
792 return -ENOMEM; 788 return -ENOMEM;
793 789
794 priv->clk = devm_clk_get(&pdev->dev, NULL); 790 priv->clk = devm_clk_get(&pdev->dev, NULL);
795 if (IS_ERR(priv->clk)) { 791 if (IS_ERR(priv->clk)) {
796 dev_err(&pdev->dev, "failed to get access to sata clock\n"); 792 dev_err(&pdev->dev, "failed to get access to sata clock\n");
797 return PTR_ERR(priv->clk); 793 return PTR_ERR(priv->clk);
798 } 794 }
799 clk_enable(priv->clk); 795 clk_enable(priv->clk);
800 796
801 host = ata_host_alloc(&pdev->dev, 1); 797 host = ata_host_alloc(&pdev->dev, 1);
802 if (!host) { 798 if (!host) {
803 dev_err(&pdev->dev, "ata_host_alloc failed\n"); 799 dev_err(&pdev->dev, "ata_host_alloc failed\n");
804 ret = -ENOMEM; 800 ret = -ENOMEM;
805 goto cleanup; 801 goto cleanup;
806 } 802 }
807 803
808 host->private_data = priv; 804 host->private_data = priv;
809 805
806 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
810 priv->base = devm_ioremap_resource(&pdev->dev, mem); 807 priv->base = devm_ioremap_resource(&pdev->dev, mem);
811 if (IS_ERR(priv->base)) { 808 if (IS_ERR(priv->base)) {
812 ret = PTR_ERR(priv->base); 809 ret = PTR_ERR(priv->base);
813 goto cleanup; 810 goto cleanup;
814 } 811 }
815 812
816 /* setup port */ 813 /* setup port */
817 sata_rcar_setup_port(host); 814 sata_rcar_setup_port(host);
818 815
819 /* initialize host controller */ 816 /* initialize host controller */
820 sata_rcar_init_controller(host); 817 sata_rcar_init_controller(host);
821 818
822 ret = ata_host_activate(host, irq, sata_rcar_interrupt, 0, 819 ret = ata_host_activate(host, irq, sata_rcar_interrupt, 0,
823 &sata_rcar_sht); 820 &sata_rcar_sht);
824 if (!ret) 821 if (!ret)
825 return 0; 822 return 0;
826 823
827 cleanup: 824 cleanup:
828 clk_disable(priv->clk); 825 clk_disable(priv->clk);
829 826
830 return ret; 827 return ret;
831 } 828 }
832 829
833 static int sata_rcar_remove(struct platform_device *pdev) 830 static int sata_rcar_remove(struct platform_device *pdev)
834 { 831 {
835 struct ata_host *host = platform_get_drvdata(pdev); 832 struct ata_host *host = platform_get_drvdata(pdev);
836 struct sata_rcar_priv *priv = host->private_data; 833 struct sata_rcar_priv *priv = host->private_data;
837 void __iomem *base = priv->base; 834 void __iomem *base = priv->base;
838 835
839 ata_host_detach(host); 836 ata_host_detach(host);
840 837
841 /* disable interrupts */ 838 /* disable interrupts */
842 iowrite32(0, base + ATAPI_INT_ENABLE_REG); 839 iowrite32(0, base + ATAPI_INT_ENABLE_REG);
843 /* ack and mask */ 840 /* ack and mask */
844 iowrite32(0, base + SATAINTSTAT_REG); 841 iowrite32(0, base + SATAINTSTAT_REG);
845 iowrite32(0x7ff, base + SATAINTMASK_REG); 842 iowrite32(0x7ff, base + SATAINTMASK_REG);
846 843
847 clk_disable(priv->clk); 844 clk_disable(priv->clk);
848 845
849 return 0; 846 return 0;
850 } 847 }
851 848
852 #ifdef CONFIG_PM 849 #ifdef CONFIG_PM
853 static int sata_rcar_suspend(struct device *dev) 850 static int sata_rcar_suspend(struct device *dev)
854 { 851 {
855 struct ata_host *host = dev_get_drvdata(dev); 852 struct ata_host *host = dev_get_drvdata(dev);
856 struct sata_rcar_priv *priv = host->private_data; 853 struct sata_rcar_priv *priv = host->private_data;
857 void __iomem *base = priv->base; 854 void __iomem *base = priv->base;
858 int ret; 855 int ret;
859 856
860 ret = ata_host_suspend(host, PMSG_SUSPEND); 857 ret = ata_host_suspend(host, PMSG_SUSPEND);
861 if (!ret) { 858 if (!ret) {
862 /* disable interrupts */ 859 /* disable interrupts */
863 iowrite32(0, base + ATAPI_INT_ENABLE_REG); 860 iowrite32(0, base + ATAPI_INT_ENABLE_REG);
864 /* mask */ 861 /* mask */
865 iowrite32(0x7ff, base + SATAINTMASK_REG); 862 iowrite32(0x7ff, base + SATAINTMASK_REG);
866 863
867 clk_disable(priv->clk); 864 clk_disable(priv->clk);
868 } 865 }
869 866
870 return ret; 867 return ret;
871 } 868 }
872 869
873 static int sata_rcar_resume(struct device *dev) 870 static int sata_rcar_resume(struct device *dev)
874 { 871 {
875 struct ata_host *host = dev_get_drvdata(dev); 872 struct ata_host *host = dev_get_drvdata(dev);
876 struct sata_rcar_priv *priv = host->private_data; 873 struct sata_rcar_priv *priv = host->private_data;
877 void __iomem *base = priv->base; 874 void __iomem *base = priv->base;
878 875
879 clk_enable(priv->clk); 876 clk_enable(priv->clk);
880 877
881 /* ack and mask */ 878 /* ack and mask */
882 iowrite32(0, base + SATAINTSTAT_REG); 879 iowrite32(0, base + SATAINTSTAT_REG);
883 iowrite32(0x7ff, base + SATAINTMASK_REG); 880 iowrite32(0x7ff, base + SATAINTMASK_REG);
884 /* enable interrupts */ 881 /* enable interrupts */
885 iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG); 882 iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG);
886 883
887 ata_host_resume(host); 884 ata_host_resume(host);
888 885
889 return 0; 886 return 0;
890 } 887 }
891 888
892 static const struct dev_pm_ops sata_rcar_pm_ops = { 889 static const struct dev_pm_ops sata_rcar_pm_ops = {
893 .suspend = sata_rcar_suspend, 890 .suspend = sata_rcar_suspend,
894 .resume = sata_rcar_resume, 891 .resume = sata_rcar_resume,
895 }; 892 };
896 #endif 893 #endif
897 894
898 static struct of_device_id sata_rcar_match[] = { 895 static struct of_device_id sata_rcar_match[] = {
899 { .compatible = "renesas,rcar-sata", }, 896 { .compatible = "renesas,rcar-sata", },
900 {}, 897 {},
901 }; 898 };
902 MODULE_DEVICE_TABLE(of, sata_rcar_match); 899 MODULE_DEVICE_TABLE(of, sata_rcar_match);
903 900
904 static struct platform_driver sata_rcar_driver = { 901 static struct platform_driver sata_rcar_driver = {
905 .probe = sata_rcar_probe, 902 .probe = sata_rcar_probe,
906 .remove = sata_rcar_remove, 903 .remove = sata_rcar_remove,
907 .driver = { 904 .driver = {
908 .name = DRV_NAME, 905 .name = DRV_NAME,
909 .owner = THIS_MODULE, 906 .owner = THIS_MODULE,
910 .of_match_table = sata_rcar_match, 907 .of_match_table = sata_rcar_match,
911 #ifdef CONFIG_PM 908 #ifdef CONFIG_PM
912 .pm = &sata_rcar_pm_ops, 909 .pm = &sata_rcar_pm_ops,
913 #endif 910 #endif
914 }, 911 },
915 }; 912 };
916 913
917 module_platform_driver(sata_rcar_driver); 914 module_platform_driver(sata_rcar_driver);
918 915
919 MODULE_LICENSE("GPL"); 916 MODULE_LICENSE("GPL");
920 MODULE_AUTHOR("Vladimir Barinov"); 917 MODULE_AUTHOR("Vladimir Barinov");
921 MODULE_DESCRIPTION("Renesas R-Car SATA controller low level driver"); 918 MODULE_DESCRIPTION("Renesas R-Car SATA controller low level driver");