Commit 4dc9783ea9e4d6f97e40b808991b324a4719a837

Authored by Grant Likely
Committed by Josh Boyer
1 parent 36660cef73

[POWERPC] Virtex: add xilinx interrupt controller driver

Adds support for the Xilinx opb-intc interrupt controller

Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>

Showing 3 changed files with 172 additions and 0 deletions Inline Diff

arch/powerpc/sysdev/Makefile
1 ifeq ($(CONFIG_PPC64),y) 1 ifeq ($(CONFIG_PPC64),y)
2 EXTRA_CFLAGS += -mno-minimal-toc 2 EXTRA_CFLAGS += -mno-minimal-toc
3 endif 3 endif
4 4
5 mpic-msi-obj-$(CONFIG_PCI_MSI) += mpic_msi.o mpic_u3msi.o 5 mpic-msi-obj-$(CONFIG_PCI_MSI) += mpic_msi.o mpic_u3msi.o
6 obj-$(CONFIG_MPIC) += mpic.o $(mpic-msi-obj-y) 6 obj-$(CONFIG_MPIC) += mpic.o $(mpic-msi-obj-y)
7 7
8 obj-$(CONFIG_PPC_MPC106) += grackle.o 8 obj-$(CONFIG_PPC_MPC106) += grackle.o
9 obj-$(CONFIG_PPC_DCR) += dcr.o 9 obj-$(CONFIG_PPC_DCR) += dcr.o
10 obj-$(CONFIG_PPC_DCR_NATIVE) += dcr-low.o 10 obj-$(CONFIG_PPC_DCR_NATIVE) += dcr-low.o
11 obj-$(CONFIG_PPC_PMI) += pmi.o 11 obj-$(CONFIG_PPC_PMI) += pmi.o
12 obj-$(CONFIG_U3_DART) += dart_iommu.o 12 obj-$(CONFIG_U3_DART) += dart_iommu.o
13 obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o 13 obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
14 obj-$(CONFIG_FSL_SOC) += fsl_soc.o 14 obj-$(CONFIG_FSL_SOC) += fsl_soc.o
15 obj-$(CONFIG_FSL_PCI) += fsl_pci.o 15 obj-$(CONFIG_FSL_PCI) += fsl_pci.o
16 obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o 16 obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
17 obj-$(CONFIG_QUICC_ENGINE) += qe_lib/ 17 obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
18 mv64x60-$(CONFIG_PCI) += mv64x60_pci.o 18 mv64x60-$(CONFIG_PCI) += mv64x60_pci.o
19 obj-$(CONFIG_MV64X60) += $(mv64x60-y) mv64x60_pic.o mv64x60_dev.o \ 19 obj-$(CONFIG_MV64X60) += $(mv64x60-y) mv64x60_pic.o mv64x60_dev.o \
20 mv64x60_udbg.o 20 mv64x60_udbg.o
21 obj-$(CONFIG_RTC_DRV_CMOS) += rtc_cmos_setup.o 21 obj-$(CONFIG_RTC_DRV_CMOS) += rtc_cmos_setup.o
22 obj-$(CONFIG_AXON_RAM) += axonram.o 22 obj-$(CONFIG_AXON_RAM) += axonram.o
23 23
24 ifeq ($(CONFIG_PPC_MERGE),y) 24 ifeq ($(CONFIG_PPC_MERGE),y)
25 obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o 25 obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o
26 obj-$(CONFIG_PPC_I8259) += i8259.o 26 obj-$(CONFIG_PPC_I8259) += i8259.o
27 obj-$(CONFIG_PPC_83xx) += ipic.o 27 obj-$(CONFIG_PPC_83xx) += ipic.o
28 obj-$(CONFIG_4xx) += uic.o 28 obj-$(CONFIG_4xx) += uic.o
29 obj-$(CONFIG_XILINX_VIRTEX) += xilinx_intc.o
29 endif 30 endif
30 31
31 # Temporary hack until we have migrated to asm-powerpc 32 # Temporary hack until we have migrated to asm-powerpc
32 ifeq ($(ARCH),powerpc) 33 ifeq ($(ARCH),powerpc)
33 obj-$(CONFIG_CPM2) += cpm2_common.o cpm2_pic.o 34 obj-$(CONFIG_CPM2) += cpm2_common.o cpm2_pic.o
34 obj-$(CONFIG_8xx) += mpc8xx_pic.o commproc.o 35 obj-$(CONFIG_8xx) += mpc8xx_pic.o commproc.o
35 obj-$(CONFIG_UCODE_PATCH) += micropatch.o 36 obj-$(CONFIG_UCODE_PATCH) += micropatch.o
36 endif 37 endif
37 38
arch/powerpc/sysdev/xilinx_intc.c
File was created 1 /*
2 * Interrupt controller driver for Xilinx Virtex FPGAs
3 *
4 * Copyright (C) 2007 Secret Lab Technologies Ltd.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 *
10 */
11
12 /*
13 * This is a driver for the interrupt controller typically found in
14 * Xilinx Virtex FPGA designs.
15 *
16 * The interrupt sense levels are hard coded into the FPGA design with
17 * typically a 1:1 relationship between irq lines and devices (no shared
18 * irq lines). Therefore, this driver does not attempt to handle edge
19 * and level interrupts differently.
20 */
21 #undef DEBUG
22
23 #include <linux/kernel.h>
24 #include <linux/irq.h>
25 #include <linux/of.h>
26 #include <asm/io.h>
27 #include <asm/processor.h>
28 #include <asm/irq.h>
29
30 /*
31 * INTC Registers
32 */
33 #define XINTC_ISR 0 /* Interrupt Status */
34 #define XINTC_IPR 4 /* Interrupt Pending */
35 #define XINTC_IER 8 /* Interrupt Enable */
36 #define XINTC_IAR 12 /* Interrupt Acknowledge */
37 #define XINTC_SIE 16 /* Set Interrupt Enable bits */
38 #define XINTC_CIE 20 /* Clear Interrupt Enable bits */
39 #define XINTC_IVR 24 /* Interrupt Vector */
40 #define XINTC_MER 28 /* Master Enable */
41
42 static struct irq_host *master_irqhost;
43
44 /*
45 * IRQ Chip operations
46 */
47 static void xilinx_intc_mask(unsigned int virq)
48 {
49 int irq = virq_to_hw(virq);
50 void * regs = get_irq_chip_data(virq);
51 pr_debug("mask: %d\n", irq);
52 out_be32(regs + XINTC_CIE, 1 << irq);
53 }
54
55 static void xilinx_intc_unmask(unsigned int virq)
56 {
57 int irq = virq_to_hw(virq);
58 void * regs = get_irq_chip_data(virq);
59 pr_debug("unmask: %d\n", irq);
60 out_be32(regs + XINTC_SIE, 1 << irq);
61 }
62
63 static void xilinx_intc_ack(unsigned int virq)
64 {
65 int irq = virq_to_hw(virq);
66 void * regs = get_irq_chip_data(virq);
67 pr_debug("ack: %d\n", irq);
68 out_be32(regs + XINTC_IAR, 1 << irq);
69 }
70
71 static struct irq_chip xilinx_intc_irqchip = {
72 .typename = "Xilinx INTC",
73 .mask = xilinx_intc_mask,
74 .unmask = xilinx_intc_unmask,
75 .ack = xilinx_intc_ack,
76 };
77
78 /*
79 * IRQ Host operations
80 */
81 static int xilinx_intc_map(struct irq_host *h, unsigned int virq,
82 irq_hw_number_t irq)
83 {
84 set_irq_chip_data(virq, h->host_data);
85 set_irq_chip_and_handler(virq, &xilinx_intc_irqchip, handle_level_irq);
86 set_irq_type(virq, IRQ_TYPE_NONE);
87 return 0;
88 }
89
90 static struct irq_host_ops xilinx_intc_ops = {
91 .map = xilinx_intc_map,
92 };
93
94 struct irq_host * __init
95 xilinx_intc_init(struct device_node *np)
96 {
97 struct irq_host * irq;
98 struct resource res;
99 void * regs;
100 int rc;
101
102 /* Find and map the intc registers */
103 rc = of_address_to_resource(np, 0, &res);
104 if (rc) {
105 printk(KERN_ERR __FILE__ ": of_address_to_resource() failed\n");
106 return NULL;
107 }
108 regs = ioremap(res.start, 32);
109
110 printk(KERN_INFO "Xilinx intc at 0x%08X mapped to 0x%p\n",
111 res.start, regs);
112
113 /* Setup interrupt controller */
114 out_be32(regs + XINTC_IER, 0); /* disable all irqs */
115 out_be32(regs + XINTC_IAR, ~(u32) 0); /* Acknowledge pending irqs */
116 out_be32(regs + XINTC_MER, 0x3UL); /* Turn on the Master Enable. */
117
118 /* Allocate and initialize an irq_host structure. */
119 irq = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, 32, &xilinx_intc_ops, -1);
120 if (!irq)
121 panic(__FILE__ ": Cannot allocate IRQ host\n");
122 irq->host_data = regs;
123 return irq;
124 }
125
126 int xilinx_intc_get_irq(void)
127 {
128 void * regs = master_irqhost->host_data;
129 pr_debug("get_irq:\n");
130 return irq_linear_revmap(master_irqhost, in_be32(regs + XINTC_IVR));
131 }
132
133 void __init xilinx_intc_init_tree(void)
134 {
135 struct device_node *np;
136
137 /* find top level interrupt controller */
138 for_each_compatible_node(np, NULL, "xilinx,intc") {
139 if (!of_get_property(np, "interrupts", NULL))
140 break;
141 }
142
143 /* xilinx interrupt controller needs to be top level */
144 BUG_ON(!np);
145
146 master_irqhost = xilinx_intc_init(np);
147 BUG_ON(!master_irqhost);
148
149 irq_set_default_host(master_irqhost);
150 of_node_put(np);
151 }
152
include/asm-powerpc/xilinx_intc.h
File was created 1 /*
2 * Xilinx intc external definitions
3 *
4 * Copyright 2007 Secret Lab Technologies Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11 #ifndef _ASM_POWERPC_XILINX_INTC_H
12 #define _ASM_POWERPC_XILINX_INTC_H
13
14 #ifdef __KERNEL__
15
16 extern void __init xilinx_intc_init_tree(void);
17 extern unsigned int xilinx_intc_get_irq(void);
18
19 #endif /* __KERNEL__ */
20 #endif /* _ASM_POWERPC_XILINX_INTC_H */
21