Doug / smarc-fsl-linux-kernel | Embedian Git Server

Commit 5076c15862644edb91d2e3436b2fa3e07b28385d

Authored by Helge Deller 2006-03-28 03:52:15 +0800

Committed by Kyle McMartin 2006-03-31 01:48:42 +0800

Exists in master and in 7 other branches

[PARISC] I/O-Space must be ioremap_nocache()'d

Addresses in F-space must be accessed uncached on most parisc machines.

Signed-off-by: Helge Deller <deller@parisc-linux.org>
Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>

Showing 13 changed files with 48 additions and 54 deletions Inline Diff

arch/parisc/kernel/perf.c
drivers/input/serio/gscps2.c
drivers/parisc/ccio-dma.c
drivers/parisc/dino.c
drivers/parisc/eisa.c
drivers/parisc/iosapic.c
drivers/parisc/lba_pci.c
drivers/parisc/sba_iommu.c
drivers/parisc/superio.c
drivers/scsi/lasi700.c
drivers/scsi/zalon.c
drivers/serial/8250_gsc.c
drivers/serial/mux.c

arch/parisc/kernel/perf.c

Diff comments View file @ 5076c15

1	/*	1	/*
2	* Parisc performance counters	2	* Parisc performance counters
3	* Copyright (C) 2001 Randolph Chung <tausq@debian.org>	3	* Copyright (C) 2001 Randolph Chung <tausq@debian.org>
4	*	4	*
5	* This code is derived, with permission, from HP/UX sources.	5	* This code is derived, with permission, from HP/UX sources.
6	*	6	*
7	* This program is free software; you can redistribute it and/or modify	7	* This program is free software; you can redistribute it and/or modify
8	* it under the terms of the GNU General Public License as published by	8	* it under the terms of the GNU General Public License as published by
9	* the Free Software Foundation; either version 2, or (at your option)	9	* the Free Software Foundation; either version 2, or (at your option)
10	* any later version.	10	* any later version.
11	*	11	*
12	* This program is distributed in the hope that it will be useful,	12	* This program is distributed in the hope that it will be useful,
13	* but WITHOUT ANY WARRANTY; without even the implied warranty of	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15	* GNU General Public License for more details.	15	* GNU General Public License for more details.
16	*	16	*
17	* You should have received a copy of the GNU General Public License	17	* You should have received a copy of the GNU General Public License
18	* along with this program; if not, write to the Free Software	18	* along with this program; if not, write to the Free Software
19	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.	19	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20	*/	20	*/
21		21
22	/*	22	/*
23	* Edited comment from original sources:	23	* Edited comment from original sources:
24	*	24	*
25	* This driver programs the PCX-U/PCX-W performance counters	25	* This driver programs the PCX-U/PCX-W performance counters
26	* on the PA-RISC 2.0 chips. The driver keeps all images now	26	* on the PA-RISC 2.0 chips. The driver keeps all images now
27	* internally to the kernel to hopefully eliminate the possiblity	27	* internally to the kernel to hopefully eliminate the possiblity
28	* of a bad image halting the CPU. Also, there are different	28	* of a bad image halting the CPU. Also, there are different
29	* images for the PCX-W and later chips vs the PCX-U chips.	29	* images for the PCX-W and later chips vs the PCX-U chips.
30	*	30	*
31	* Only 1 process is allowed to access the driver at any time,	31	* Only 1 process is allowed to access the driver at any time,
32	* so the only protection that is needed is at open and close.	32	* so the only protection that is needed is at open and close.
33	* A variable "perf_enabled" is used to hold the state of the	33	* A variable "perf_enabled" is used to hold the state of the
34	* driver. The spinlock "perf_lock" is used to protect the	34	* driver. The spinlock "perf_lock" is used to protect the
35	* modification of the state during open/close operations so	35	* modification of the state during open/close operations so
36	* multiple processes don't get into the driver simultaneously.	36	* multiple processes don't get into the driver simultaneously.
37	*	37	*
38	* This driver accesses the processor directly vs going through	38	* This driver accesses the processor directly vs going through
39	* the PDC INTRIGUE calls. This is done to eliminate bugs introduced	39	* the PDC INTRIGUE calls. This is done to eliminate bugs introduced
40	* in various PDC revisions. The code is much more maintainable	40	* in various PDC revisions. The code is much more maintainable
41	* and reliable this way vs having to debug on every version of PDC	41	* and reliable this way vs having to debug on every version of PDC
42	* on every box.	42	* on every box.
43	*/	43	*/
44		44
45	#include <linux/capability.h>	45	#include <linux/capability.h>
46	#include <linux/init.h>	46	#include <linux/init.h>
47	#include <linux/proc_fs.h>	47	#include <linux/proc_fs.h>
48	#include <linux/miscdevice.h>	48	#include <linux/miscdevice.h>
49	#include <linux/spinlock.h>	49	#include <linux/spinlock.h>
50		50
51	#include <asm/uaccess.h>	51	#include <asm/uaccess.h>
52	#include <asm/perf.h>	52	#include <asm/perf.h>
53	#include <asm/parisc-device.h>	53	#include <asm/parisc-device.h>
54	#include <asm/processor.h>	54	#include <asm/processor.h>
55	#include <asm/runway.h>	55	#include <asm/runway.h>
56	#include <asm/io.h> /* for __raw_read() */	56	#include <asm/io.h> /* for __raw_read() */
57		57
58	#include "perf_images.h"	58	#include "perf_images.h"
59		59
60	#define MAX_RDR_WORDS 24	60	#define MAX_RDR_WORDS 24
61	#define PERF_VERSION 2 /* derived from hpux's PI v2 interface */	61	#define PERF_VERSION 2 /* derived from hpux's PI v2 interface */
62		62
63	/* definition of RDR regs */	63	/* definition of RDR regs */
64	struct rdr_tbl_ent {	64	struct rdr_tbl_ent {
65	uint16_t width;	65	uint16_t width;
66	uint8_t num_words;	66	uint8_t num_words;
67	uint8_t write_control;	67	uint8_t write_control;
68	};	68	};
69		69
70	static int perf_processor_interface __read_mostly = UNKNOWN_INTF;	70	static int perf_processor_interface __read_mostly = UNKNOWN_INTF;
71	static int perf_enabled __read_mostly;	71	static int perf_enabled __read_mostly;
72	static spinlock_t perf_lock;	72	static spinlock_t perf_lock;
73	struct parisc_device *cpu_device __read_mostly;	73	struct parisc_device *cpu_device __read_mostly;
74		74
75	/* RDRs to write for PCX-W */	75	/* RDRs to write for PCX-W */
76	static const int perf_rdrs_W[] =	76	static const int perf_rdrs_W[] =
77	{ 0, 1, 4, 5, 6, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 };	77	{ 0, 1, 4, 5, 6, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 };
78		78
79	/* RDRs to write for PCX-U */	79	/* RDRs to write for PCX-U */
80	static const int perf_rdrs_U[] =	80	static const int perf_rdrs_U[] =
81	{ 0, 1, 4, 5, 6, 7, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 };	81	{ 0, 1, 4, 5, 6, 7, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 };
82		82
83	/* RDR register descriptions for PCX-W */	83	/* RDR register descriptions for PCX-W */
84	static const struct rdr_tbl_ent perf_rdr_tbl_W[] = {	84	static const struct rdr_tbl_ent perf_rdr_tbl_W[] = {
85	{ 19, 1, 8 }, /* RDR 0 */	85	{ 19, 1, 8 }, /* RDR 0 */
86	{ 16, 1, 16 }, /* RDR 1 */	86	{ 16, 1, 16 }, /* RDR 1 */
87	{ 72, 2, 0 }, /* RDR 2 */	87	{ 72, 2, 0 }, /* RDR 2 */
88	{ 81, 2, 0 }, /* RDR 3 */	88	{ 81, 2, 0 }, /* RDR 3 */
89	{ 328, 6, 0 }, /* RDR 4 */	89	{ 328, 6, 0 }, /* RDR 4 */
90	{ 160, 3, 0 }, /* RDR 5 */	90	{ 160, 3, 0 }, /* RDR 5 */
91	{ 336, 6, 0 }, /* RDR 6 */	91	{ 336, 6, 0 }, /* RDR 6 */
92	{ 164, 3, 0 }, /* RDR 7 */	92	{ 164, 3, 0 }, /* RDR 7 */
93	{ 0, 0, 0 }, /* RDR 8 */	93	{ 0, 0, 0 }, /* RDR 8 */
94	{ 35, 1, 0 }, /* RDR 9 */	94	{ 35, 1, 0 }, /* RDR 9 */
95	{ 6, 1, 0 }, /* RDR 10 */	95	{ 6, 1, 0 }, /* RDR 10 */
96	{ 18, 1, 0 }, /* RDR 11 */	96	{ 18, 1, 0 }, /* RDR 11 */
97	{ 13, 1, 0 }, /* RDR 12 */	97	{ 13, 1, 0 }, /* RDR 12 */
98	{ 8, 1, 0 }, /* RDR 13 */	98	{ 8, 1, 0 }, /* RDR 13 */
99	{ 8, 1, 0 }, /* RDR 14 */	99	{ 8, 1, 0 }, /* RDR 14 */
100	{ 8, 1, 0 }, /* RDR 15 */	100	{ 8, 1, 0 }, /* RDR 15 */
101	{ 1530, 24, 0 }, /* RDR 16 */	101	{ 1530, 24, 0 }, /* RDR 16 */
102	{ 16, 1, 0 }, /* RDR 17 */	102	{ 16, 1, 0 }, /* RDR 17 */
103	{ 4, 1, 0 }, /* RDR 18 */	103	{ 4, 1, 0 }, /* RDR 18 */
104	{ 0, 0, 0 }, /* RDR 19 */	104	{ 0, 0, 0 }, /* RDR 19 */
105	{ 152, 3, 24 }, /* RDR 20 */	105	{ 152, 3, 24 }, /* RDR 20 */
106	{ 152, 3, 24 }, /* RDR 21 */	106	{ 152, 3, 24 }, /* RDR 21 */
107	{ 233, 4, 48 }, /* RDR 22 */	107	{ 233, 4, 48 }, /* RDR 22 */
108	{ 233, 4, 48 }, /* RDR 23 */	108	{ 233, 4, 48 }, /* RDR 23 */
109	{ 71, 2, 0 }, /* RDR 24 */	109	{ 71, 2, 0 }, /* RDR 24 */
110	{ 71, 2, 0 }, /* RDR 25 */	110	{ 71, 2, 0 }, /* RDR 25 */
111	{ 11, 1, 0 }, /* RDR 26 */	111	{ 11, 1, 0 }, /* RDR 26 */
112	{ 18, 1, 0 }, /* RDR 27 */	112	{ 18, 1, 0 }, /* RDR 27 */
113	{ 128, 2, 0 }, /* RDR 28 */	113	{ 128, 2, 0 }, /* RDR 28 */
114	{ 0, 0, 0 }, /* RDR 29 */	114	{ 0, 0, 0 }, /* RDR 29 */
115	{ 16, 1, 0 }, /* RDR 30 */	115	{ 16, 1, 0 }, /* RDR 30 */
116	{ 16, 1, 0 }, /* RDR 31 */	116	{ 16, 1, 0 }, /* RDR 31 */
117	};	117	};
118		118
119	/* RDR register descriptions for PCX-U */	119	/* RDR register descriptions for PCX-U */
120	static const struct rdr_tbl_ent perf_rdr_tbl_U[] = {	120	static const struct rdr_tbl_ent perf_rdr_tbl_U[] = {
121	{ 19, 1, 8 }, /* RDR 0 */	121	{ 19, 1, 8 }, /* RDR 0 */
122	{ 32, 1, 16 }, /* RDR 1 */	122	{ 32, 1, 16 }, /* RDR 1 */
123	{ 20, 1, 0 }, /* RDR 2 */	123	{ 20, 1, 0 }, /* RDR 2 */
124	{ 0, 0, 0 }, /* RDR 3 */	124	{ 0, 0, 0 }, /* RDR 3 */
125	{ 344, 6, 0 }, /* RDR 4 */	125	{ 344, 6, 0 }, /* RDR 4 */
126	{ 176, 3, 0 }, /* RDR 5 */	126	{ 176, 3, 0 }, /* RDR 5 */
127	{ 336, 6, 0 }, /* RDR 6 */	127	{ 336, 6, 0 }, /* RDR 6 */
128	{ 0, 0, 0 }, /* RDR 7 */	128	{ 0, 0, 0 }, /* RDR 7 */
129	{ 0, 0, 0 }, /* RDR 8 */	129	{ 0, 0, 0 }, /* RDR 8 */
130	{ 0, 0, 0 }, /* RDR 9 */	130	{ 0, 0, 0 }, /* RDR 9 */
131	{ 28, 1, 0 }, /* RDR 10 */	131	{ 28, 1, 0 }, /* RDR 10 */
132	{ 33, 1, 0 }, /* RDR 11 */	132	{ 33, 1, 0 }, /* RDR 11 */
133	{ 0, 0, 0 }, /* RDR 12 */	133	{ 0, 0, 0 }, /* RDR 12 */
134	{ 230, 4, 0 }, /* RDR 13 */	134	{ 230, 4, 0 }, /* RDR 13 */
135	{ 32, 1, 0 }, /* RDR 14 */	135	{ 32, 1, 0 }, /* RDR 14 */
136	{ 128, 2, 0 }, /* RDR 15 */	136	{ 128, 2, 0 }, /* RDR 15 */
137	{ 1494, 24, 0 }, /* RDR 16 */	137	{ 1494, 24, 0 }, /* RDR 16 */
138	{ 18, 1, 0 }, /* RDR 17 */	138	{ 18, 1, 0 }, /* RDR 17 */
139	{ 4, 1, 0 }, /* RDR 18 */	139	{ 4, 1, 0 }, /* RDR 18 */
140	{ 0, 0, 0 }, /* RDR 19 */	140	{ 0, 0, 0 }, /* RDR 19 */
141	{ 158, 3, 24 }, /* RDR 20 */	141	{ 158, 3, 24 }, /* RDR 20 */
142	{ 158, 3, 24 }, /* RDR 21 */	142	{ 158, 3, 24 }, /* RDR 21 */
143	{ 194, 4, 48 }, /* RDR 22 */	143	{ 194, 4, 48 }, /* RDR 22 */
144	{ 194, 4, 48 }, /* RDR 23 */	144	{ 194, 4, 48 }, /* RDR 23 */
145	{ 71, 2, 0 }, /* RDR 24 */	145	{ 71, 2, 0 }, /* RDR 24 */
146	{ 71, 2, 0 }, /* RDR 25 */	146	{ 71, 2, 0 }, /* RDR 25 */
147	{ 28, 1, 0 }, /* RDR 26 */	147	{ 28, 1, 0 }, /* RDR 26 */
148	{ 33, 1, 0 }, /* RDR 27 */	148	{ 33, 1, 0 }, /* RDR 27 */
149	{ 88, 2, 0 }, /* RDR 28 */	149	{ 88, 2, 0 }, /* RDR 28 */
150	{ 32, 1, 0 }, /* RDR 29 */	150	{ 32, 1, 0 }, /* RDR 29 */
151	{ 24, 1, 0 }, /* RDR 30 */	151	{ 24, 1, 0 }, /* RDR 30 */
152	{ 16, 1, 0 }, /* RDR 31 */	152	{ 16, 1, 0 }, /* RDR 31 */
153	};	153	};
154		154
155	/*	155	/*
156	* A non-zero write_control in the above tables is a byte offset into	156	* A non-zero write_control in the above tables is a byte offset into
157	* this array.	157	* this array.
158	*/	158	*/
159	static const uint64_t perf_bitmasks[] = {	159	static const uint64_t perf_bitmasks[] = {
160	0x0000000000000000ul, /* first dbl word must be zero */	160	0x0000000000000000ul, /* first dbl word must be zero */
161	0xfdffe00000000000ul, /* RDR0 bitmask */	161	0xfdffe00000000000ul, /* RDR0 bitmask */
162	0x003f000000000000ul, /* RDR1 bitmask */	162	0x003f000000000000ul, /* RDR1 bitmask */
163	0x00fffffffffffffful, /* RDR20-RDR21 bitmask (152 bits) */	163	0x00fffffffffffffful, /* RDR20-RDR21 bitmask (152 bits) */
164	0xfffffffffffffffful,	164	0xfffffffffffffffful,
165	0xfffffffc00000000ul,	165	0xfffffffc00000000ul,
166	0xfffffffffffffffful, /* RDR22-RDR23 bitmask (233 bits) */	166	0xfffffffffffffffful, /* RDR22-RDR23 bitmask (233 bits) */
167	0xfffffffffffffffful,	167	0xfffffffffffffffful,
168	0xfffffffffffffffcul,	168	0xfffffffffffffffcul,
169	0xff00000000000000ul	169	0xff00000000000000ul
170	};	170	};
171		171
172	/*	172	/*
173	* Write control bitmasks for Pa-8700 processor given	173	* Write control bitmasks for Pa-8700 processor given
174	* somethings have changed slightly.	174	* somethings have changed slightly.
175	*/	175	*/
176	static const uint64_t perf_bitmasks_piranha[] = {	176	static const uint64_t perf_bitmasks_piranha[] = {
177	0x0000000000000000ul, /* first dbl word must be zero */	177	0x0000000000000000ul, /* first dbl word must be zero */
178	0xfdffe00000000000ul, /* RDR0 bitmask */	178	0xfdffe00000000000ul, /* RDR0 bitmask */
179	0x003f000000000000ul, /* RDR1 bitmask */	179	0x003f000000000000ul, /* RDR1 bitmask */
180	0x00fffffffffffffful, /* RDR20-RDR21 bitmask (158 bits) */	180	0x00fffffffffffffful, /* RDR20-RDR21 bitmask (158 bits) */
181	0xfffffffffffffffful,	181	0xfffffffffffffffful,
182	0xfffffffc00000000ul,	182	0xfffffffc00000000ul,
183	0xfffffffffffffffful, /* RDR22-RDR23 bitmask (210 bits) */	183	0xfffffffffffffffful, /* RDR22-RDR23 bitmask (210 bits) */
184	0xfffffffffffffffful,	184	0xfffffffffffffffful,
185	0xfffffffffffffffful,	185	0xfffffffffffffffful,
186	0xfffc000000000000ul	186	0xfffc000000000000ul
187	};	187	};
188		188
189	static const uint64_t bitmask_array; / array of bitmasks to use */	189	static const uint64_t bitmask_array; / array of bitmasks to use */
190		190
191	/******************************************************************************	191	/******************************************************************************
192	* Function Prototypes	192	* Function Prototypes
193	*****************************************************************************/	193	*****************************************************************************/
194	static int perf_config(uint32_t *image_ptr);	194	static int perf_config(uint32_t *image_ptr);
195	static int perf_release(struct inode inode, struct file file);	195	static int perf_release(struct inode inode, struct file file);
196	static int perf_open(struct inode inode, struct file file);	196	static int perf_open(struct inode inode, struct file file);
197	static ssize_t perf_read(struct file file, char __user buf, size_t cnt, loff_t *ppos);	197	static ssize_t perf_read(struct file file, char __user buf, size_t cnt, loff_t *ppos);
198	static ssize_t perf_write(struct file file, const char __user buf, size_t count,	198	static ssize_t perf_write(struct file file, const char __user buf, size_t count,
199	loff_t *ppos);	199	loff_t *ppos);
200	static long perf_ioctl(struct file *file, unsigned int cmd, unsigned long arg);	200	static long perf_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
201	static void perf_start_counters(void);	201	static void perf_start_counters(void);
202	static int perf_stop_counters(uint32_t *raddr);	202	static int perf_stop_counters(uint32_t *raddr);
203	static const struct rdr_tbl_ent * perf_rdr_get_entry(uint32_t rdr_num);	203	static const struct rdr_tbl_ent * perf_rdr_get_entry(uint32_t rdr_num);
204	static int perf_rdr_read_ubuf(uint32_t rdr_num, uint64_t *buffer);	204	static int perf_rdr_read_ubuf(uint32_t rdr_num, uint64_t *buffer);
205	static int perf_rdr_clear(uint32_t rdr_num);	205	static int perf_rdr_clear(uint32_t rdr_num);
206	static int perf_write_image(uint64_t *memaddr);	206	static int perf_write_image(uint64_t *memaddr);
207	static void perf_rdr_write(uint32_t rdr_num, uint64_t *buffer);	207	static void perf_rdr_write(uint32_t rdr_num, uint64_t *buffer);
208		208
209	/* External Assembly Routines */	209	/* External Assembly Routines */
210	extern uint64_t perf_rdr_shift_in_W (uint32_t rdr_num, uint16_t width);	210	extern uint64_t perf_rdr_shift_in_W (uint32_t rdr_num, uint16_t width);
211	extern uint64_t perf_rdr_shift_in_U (uint32_t rdr_num, uint16_t width);	211	extern uint64_t perf_rdr_shift_in_U (uint32_t rdr_num, uint16_t width);
212	extern void perf_rdr_shift_out_W (uint32_t rdr_num, uint64_t buffer);	212	extern void perf_rdr_shift_out_W (uint32_t rdr_num, uint64_t buffer);
213	extern void perf_rdr_shift_out_U (uint32_t rdr_num, uint64_t buffer);	213	extern void perf_rdr_shift_out_U (uint32_t rdr_num, uint64_t buffer);
214	extern void perf_intrigue_enable_perf_counters (void);	214	extern void perf_intrigue_enable_perf_counters (void);
215	extern void perf_intrigue_disable_perf_counters (void);	215	extern void perf_intrigue_disable_perf_counters (void);
216		216
217	/******************************************************************************	217	/******************************************************************************
218	* Function Definitions	218	* Function Definitions
219	*****************************************************************************/	219	*****************************************************************************/
220		220
221		221
222	/*	222	/*
223	* configure:	223	* configure:
224	*	224	*
225	* Configure the cpu with a given data image. First turn off the counters,	225	* Configure the cpu with a given data image. First turn off the counters,
226	* then download the image, then turn the counters back on.	226	* then download the image, then turn the counters back on.
227	*/	227	*/
228	static int perf_config(uint32_t *image_ptr)	228	static int perf_config(uint32_t *image_ptr)
229	{	229	{
230	long error;	230	long error;
231	uint32_t raddr[4];	231	uint32_t raddr[4];
232		232
233	/* Stop the counters*/	233	/* Stop the counters*/
234	error = perf_stop_counters(raddr);	234	error = perf_stop_counters(raddr);
235	if (error != 0) {	235	if (error != 0) {
236	printk("perf_config: perf_stop_counters = %ld\n", error);	236	printk("perf_config: perf_stop_counters = %ld\n", error);
237	return -EINVAL;	237	return -EINVAL;
238	}	238	}
239		239
240	printk("Preparing to write image\n");	240	printk("Preparing to write image\n");
241	/* Write the image to the chip */	241	/* Write the image to the chip */
242	error = perf_write_image((uint64_t *)image_ptr);	242	error = perf_write_image((uint64_t *)image_ptr);
243	if (error != 0) {	243	if (error != 0) {
244	printk("perf_config: DOWNLOAD = %ld\n", error);	244	printk("perf_config: DOWNLOAD = %ld\n", error);
245	return -EINVAL;	245	return -EINVAL;
246	}	246	}
247		247
248	printk("Preparing to start counters\n");	248	printk("Preparing to start counters\n");
249		249
250	/* Start the counters */	250	/* Start the counters */
251	perf_start_counters();	251	perf_start_counters();
252		252
253	return sizeof(uint32_t);	253	return sizeof(uint32_t);
254	}	254	}
255		255
256	/*	256	/*
257	* Open the device and initialize all of its memory. The device is only	257	* Open the device and initialize all of its memory. The device is only
258	* opened once, but can be "queried" by multiple processes that know its	258	* opened once, but can be "queried" by multiple processes that know its
259	* file descriptor.	259	* file descriptor.
260	*/	260	*/
261	static int perf_open(struct inode inode, struct file file)	261	static int perf_open(struct inode inode, struct file file)
262	{	262	{
263	spin_lock(&perf_lock);	263	spin_lock(&perf_lock);
264	if (perf_enabled) {	264	if (perf_enabled) {
265	spin_unlock(&perf_lock);	265	spin_unlock(&perf_lock);
266	return -EBUSY;	266	return -EBUSY;
267	}	267	}
268	perf_enabled = 1;	268	perf_enabled = 1;
269	spin_unlock(&perf_lock);	269	spin_unlock(&perf_lock);
270		270
271	return 0;	271	return 0;
272	}	272	}
273		273
274	/*	274	/*
275	* Close the device.	275	* Close the device.
276	*/	276	*/
277	static int perf_release(struct inode inode, struct file file)	277	static int perf_release(struct inode inode, struct file file)
278	{	278	{
279	spin_lock(&perf_lock);	279	spin_lock(&perf_lock);
280	perf_enabled = 0;	280	perf_enabled = 0;
281	spin_unlock(&perf_lock);	281	spin_unlock(&perf_lock);
282		282
283	return 0;	283	return 0;
284	}	284	}
285		285
286	/*	286	/*
287	* Read does nothing for this driver	287	* Read does nothing for this driver
288	*/	288	*/
289	static ssize_t perf_read(struct file file, char __user buf, size_t cnt, loff_t *ppos)	289	static ssize_t perf_read(struct file file, char __user buf, size_t cnt, loff_t *ppos)
290	{	290	{
291	return 0;	291	return 0;
292	}	292	}
293		293
294	/*	294	/*
295	* write:	295	* write:
296	*	296	*
297	* This routine downloads the image to the chip. It must be	297	* This routine downloads the image to the chip. It must be
298	* called on the processor that the download should happen	298	* called on the processor that the download should happen
299	* on.	299	* on.
300	*/	300	*/
301	static ssize_t perf_write(struct file file, const char __user buf, size_t count,	301	static ssize_t perf_write(struct file file, const char __user buf, size_t count,
302	loff_t *ppos)	302	loff_t *ppos)
303	{	303	{
304	int err;	304	int err;
305	size_t image_size;	305	size_t image_size;
306	uint32_t image_type;	306	uint32_t image_type;
307	uint32_t interface_type;	307	uint32_t interface_type;
308	uint32_t test;	308	uint32_t test;
309		309
310	if (perf_processor_interface == ONYX_INTF)	310	if (perf_processor_interface == ONYX_INTF)
311	image_size = PCXU_IMAGE_SIZE;	311	image_size = PCXU_IMAGE_SIZE;
312	else if (perf_processor_interface == CUDA_INTF)	312	else if (perf_processor_interface == CUDA_INTF)
313	image_size = PCXW_IMAGE_SIZE;	313	image_size = PCXW_IMAGE_SIZE;
314	else	314	else
315	return -EFAULT;	315	return -EFAULT;
316		316
317	if (!capable(CAP_SYS_ADMIN))	317	if (!capable(CAP_SYS_ADMIN))
318	return -EACCES;	318	return -EACCES;
319		319
320	if (count != sizeof(uint32_t))	320	if (count != sizeof(uint32_t))
321	return -EIO;	321	return -EIO;
322		322
323	if ((err = copy_from_user(&image_type, buf, sizeof(uint32_t))) != 0)	323	if ((err = copy_from_user(&image_type, buf, sizeof(uint32_t))) != 0)
324	return err;	324	return err;
325		325
326	/* Get the interface type and test type */	326	/* Get the interface type and test type */
327	interface_type = (image_type >> 16) & 0xffff;	327	interface_type = (image_type >> 16) & 0xffff;
328	test = (image_type & 0xffff);	328	test = (image_type & 0xffff);
329		329
330	/* Make sure everything makes sense */	330	/* Make sure everything makes sense */
331		331
332	/* First check the machine type is correct for	332	/* First check the machine type is correct for
333	the requested image */	333	the requested image */
334	if (((perf_processor_interface == CUDA_INTF) &&	334	if (((perf_processor_interface == CUDA_INTF) &&
335	(interface_type != CUDA_INTF)) \|\|	335	(interface_type != CUDA_INTF)) \|\|
336	((perf_processor_interface == ONYX_INTF) &&	336	((perf_processor_interface == ONYX_INTF) &&
337	(interface_type != ONYX_INTF)))	337	(interface_type != ONYX_INTF)))
338	return -EINVAL;	338	return -EINVAL;
339		339
340	/* Next check to make sure the requested image	340	/* Next check to make sure the requested image
341	is valid */	341	is valid */
342	if (((interface_type == CUDA_INTF) &&	342	if (((interface_type == CUDA_INTF) &&
343	(test >= MAX_CUDA_IMAGES)) \|\|	343	(test >= MAX_CUDA_IMAGES)) \|\|
344	((interface_type == ONYX_INTF) &&	344	((interface_type == ONYX_INTF) &&
345	(test >= MAX_ONYX_IMAGES)))	345	(test >= MAX_ONYX_IMAGES)))
346	return -EINVAL;	346	return -EINVAL;
347		347
348	/* Copy the image into the processor */	348	/* Copy the image into the processor */
349	if (interface_type == CUDA_INTF)	349	if (interface_type == CUDA_INTF)
350	return perf_config(cuda_images[test]);	350	return perf_config(cuda_images[test]);
351	else	351	else
352	return perf_config(onyx_images[test]);	352	return perf_config(onyx_images[test]);
353		353
354	return count;	354	return count;
355	}	355	}
356		356
357	/*	357	/*
358	* Patch the images that need to know the IVA addresses.	358	* Patch the images that need to know the IVA addresses.
359	*/	359	*/
360	static void perf_patch_images(void)	360	static void perf_patch_images(void)
361	{	361	{
362	#if 0 /* FIXME!! */	362	#if 0 /* FIXME!! */
363	/*	363	/*
364	* NOTE: this routine is VERY specific to the current TLB image.	364	* NOTE: this routine is VERY specific to the current TLB image.
365	* If the image is changed, this routine might also need to be changed.	365	* If the image is changed, this routine might also need to be changed.
366	*/	366	*/
367	extern void $i_itlb_miss_2_0();	367	extern void $i_itlb_miss_2_0();
368	extern void $i_dtlb_miss_2_0();	368	extern void $i_dtlb_miss_2_0();
369	extern void PA2_0_iva();	369	extern void PA2_0_iva();
370		370
371	/*	371	/*
372	* We can only use the lower 32-bits, the upper 32-bits should be 0	372	* We can only use the lower 32-bits, the upper 32-bits should be 0
373	* anyway given this is in the kernel	373	* anyway given this is in the kernel
374	*/	374	*/
375	uint32_t itlb_addr = (uint32_t)&($i_itlb_miss_2_0);	375	uint32_t itlb_addr = (uint32_t)&($i_itlb_miss_2_0);
376	uint32_t dtlb_addr = (uint32_t)&($i_dtlb_miss_2_0);	376	uint32_t dtlb_addr = (uint32_t)&($i_dtlb_miss_2_0);
377	uint32_t IVAaddress = (uint32_t)&PA2_0_iva;	377	uint32_t IVAaddress = (uint32_t)&PA2_0_iva;
378		378
379	if (perf_processor_interface == ONYX_INTF) {	379	if (perf_processor_interface == ONYX_INTF) {
380	/* clear last 2 bytes */	380	/* clear last 2 bytes */
381	onyx_images[TLBMISS][15] &= 0xffffff00;	381	onyx_images[TLBMISS][15] &= 0xffffff00;
382	/* set 2 bytes */	382	/* set 2 bytes */
383	onyx_images[TLBMISS][15] \|= (0x000000ff&((dtlb_addr) >> 24));	383	onyx_images[TLBMISS][15] \|= (0x000000ff&((dtlb_addr) >> 24));
384	onyx_images[TLBMISS][16] = (dtlb_addr << 8)&0xffffff00;	384	onyx_images[TLBMISS][16] = (dtlb_addr << 8)&0xffffff00;
385	onyx_images[TLBMISS][17] = itlb_addr;	385	onyx_images[TLBMISS][17] = itlb_addr;
386		386
387	/* clear last 2 bytes */	387	/* clear last 2 bytes */
388	onyx_images[TLBHANDMISS][15] &= 0xffffff00;	388	onyx_images[TLBHANDMISS][15] &= 0xffffff00;
389	/* set 2 bytes */	389	/* set 2 bytes */
390	onyx_images[TLBHANDMISS][15] \|= (0x000000ff&((dtlb_addr) >> 24));	390	onyx_images[TLBHANDMISS][15] \|= (0x000000ff&((dtlb_addr) >> 24));
391	onyx_images[TLBHANDMISS][16] = (dtlb_addr << 8)&0xffffff00;	391	onyx_images[TLBHANDMISS][16] = (dtlb_addr << 8)&0xffffff00;
392	onyx_images[TLBHANDMISS][17] = itlb_addr;	392	onyx_images[TLBHANDMISS][17] = itlb_addr;
393		393
394	/* clear last 2 bytes */	394	/* clear last 2 bytes */
395	onyx_images[BIG_CPI][15] &= 0xffffff00;	395	onyx_images[BIG_CPI][15] &= 0xffffff00;
396	/* set 2 bytes */	396	/* set 2 bytes */
397	onyx_images[BIG_CPI][15] \|= (0x000000ff&((dtlb_addr) >> 24));	397	onyx_images[BIG_CPI][15] \|= (0x000000ff&((dtlb_addr) >> 24));
398	onyx_images[BIG_CPI][16] = (dtlb_addr << 8)&0xffffff00;	398	onyx_images[BIG_CPI][16] = (dtlb_addr << 8)&0xffffff00;
399	onyx_images[BIG_CPI][17] = itlb_addr;	399	onyx_images[BIG_CPI][17] = itlb_addr;
400		400
401	onyx_images[PANIC][15] &= 0xffffff00; /* clear last 2 bytes */	401	onyx_images[PANIC][15] &= 0xffffff00; /* clear last 2 bytes */
402	onyx_images[PANIC][15] \|= (0x000000ff&((IVAaddress) >> 24)); /* set 2 bytes */	402	onyx_images[PANIC][15] \|= (0x000000ff&((IVAaddress) >> 24)); /* set 2 bytes */
403	onyx_images[PANIC][16] = (IVAaddress << 8)&0xffffff00;	403	onyx_images[PANIC][16] = (IVAaddress << 8)&0xffffff00;
404		404
405		405
406	} else if (perf_processor_interface == CUDA_INTF) {	406	} else if (perf_processor_interface == CUDA_INTF) {
407	/* Cuda interface */	407	/* Cuda interface */
408	cuda_images[TLBMISS][16] =	408	cuda_images[TLBMISS][16] =
409	(cuda_images[TLBMISS][16]&0xffff0000) \|	409	(cuda_images[TLBMISS][16]&0xffff0000) \|
410	((dtlb_addr >> 8)&0x0000ffff);	410	((dtlb_addr >> 8)&0x0000ffff);
411	cuda_images[TLBMISS][17] =	411	cuda_images[TLBMISS][17] =
412	((dtlb_addr << 24)&0xff000000) \| ((itlb_addr >> 16)&0x000000ff);	412	((dtlb_addr << 24)&0xff000000) \| ((itlb_addr >> 16)&0x000000ff);
413	cuda_images[TLBMISS][18] = (itlb_addr << 16)&0xffff0000;	413	cuda_images[TLBMISS][18] = (itlb_addr << 16)&0xffff0000;
414		414
415	cuda_images[TLBHANDMISS][16] =	415	cuda_images[TLBHANDMISS][16] =
416	(cuda_images[TLBHANDMISS][16]&0xffff0000) \|	416	(cuda_images[TLBHANDMISS][16]&0xffff0000) \|
417	((dtlb_addr >> 8)&0x0000ffff);	417	((dtlb_addr >> 8)&0x0000ffff);
418	cuda_images[TLBHANDMISS][17] =	418	cuda_images[TLBHANDMISS][17] =
419	((dtlb_addr << 24)&0xff000000) \| ((itlb_addr >> 16)&0x000000ff);	419	((dtlb_addr << 24)&0xff000000) \| ((itlb_addr >> 16)&0x000000ff);
420	cuda_images[TLBHANDMISS][18] = (itlb_addr << 16)&0xffff0000;	420	cuda_images[TLBHANDMISS][18] = (itlb_addr << 16)&0xffff0000;
421		421
422	cuda_images[BIG_CPI][16] =	422	cuda_images[BIG_CPI][16] =
423	(cuda_images[BIG_CPI][16]&0xffff0000) \|	423	(cuda_images[BIG_CPI][16]&0xffff0000) \|
424	((dtlb_addr >> 8)&0x0000ffff);	424	((dtlb_addr >> 8)&0x0000ffff);
425	cuda_images[BIG_CPI][17] =	425	cuda_images[BIG_CPI][17] =
426	((dtlb_addr << 24)&0xff000000) \| ((itlb_addr >> 16)&0x000000ff);	426	((dtlb_addr << 24)&0xff000000) \| ((itlb_addr >> 16)&0x000000ff);
427	cuda_images[BIG_CPI][18] = (itlb_addr << 16)&0xffff0000;	427	cuda_images[BIG_CPI][18] = (itlb_addr << 16)&0xffff0000;
428	} else {	428	} else {
429	/* Unknown type */	429	/* Unknown type */
430	}	430	}
431	#endif	431	#endif
432	}	432	}
433		433
434		434
435	/*	435	/*
436	* ioctl routine	436	* ioctl routine
437	* All routines effect the processor that they are executed on. Thus you	437	* All routines effect the processor that they are executed on. Thus you
438	* must be running on the processor that you wish to change.	438	* must be running on the processor that you wish to change.
439	*/	439	*/
440		440
441	static long perf_ioctl(struct file *file, unsigned int cmd, unsigned long arg)	441	static long perf_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
442	{	442	{
443	long error_start;	443	long error_start;
444	uint32_t raddr[4];	444	uint32_t raddr[4];
445	int error = 0;	445	int error = 0;
446		446
447	switch (cmd) {	447	switch (cmd) {
448		448
449	case PA_PERF_ON:	449	case PA_PERF_ON:
450	/* Start the counters */	450	/* Start the counters */
451	perf_start_counters();	451	perf_start_counters();
452	break;	452	break;
453		453
454	case PA_PERF_OFF:	454	case PA_PERF_OFF:
455	error_start = perf_stop_counters(raddr);	455	error_start = perf_stop_counters(raddr);
456	if (error_start != 0) {	456	if (error_start != 0) {
457	printk(KERN_ERR "perf_off: perf_stop_counters = %ld\n", error_start);	457	printk(KERN_ERR "perf_off: perf_stop_counters = %ld\n", error_start);
458	error = -EFAULT;	458	error = -EFAULT;
459	break;	459	break;
460	}	460	}
461		461
462	/* copy out the Counters */	462	/* copy out the Counters */
463	if (copy_to_user((void __user *)arg, raddr,	463	if (copy_to_user((void __user *)arg, raddr,
464	sizeof (raddr)) != 0) {	464	sizeof (raddr)) != 0) {
465	error = -EFAULT;	465	error = -EFAULT;
466	break;	466	break;
467	}	467	}
468	break;	468	break;
469		469
470	case PA_PERF_VERSION:	470	case PA_PERF_VERSION:
471	/* Return the version # */	471	/* Return the version # */
472	error = put_user(PERF_VERSION, (int *)arg);	472	error = put_user(PERF_VERSION, (int *)arg);
473	break;	473	break;
474		474
475	default:	475	default:
476	error = -ENOTTY;	476	error = -ENOTTY;
477	}	477	}
478		478
479	return error;	479	return error;
480	}	480	}
481		481
482	static struct file_operations perf_fops = {	482	static struct file_operations perf_fops = {
483	.llseek = no_llseek,	483	.llseek = no_llseek,
484	.read = perf_read,	484	.read = perf_read,
485	.write = perf_write,	485	.write = perf_write,
486	.unlocked_ioctl = perf_ioctl,	486	.unlocked_ioctl = perf_ioctl,
487	.compat_ioctl = perf_ioctl,	487	.compat_ioctl = perf_ioctl,
488	.open = perf_open,	488	.open = perf_open,
489	.release = perf_release	489	.release = perf_release
490	};	490	};
491		491
492	static struct miscdevice perf_dev = {	492	static struct miscdevice perf_dev = {
493	MISC_DYNAMIC_MINOR,	493	MISC_DYNAMIC_MINOR,
494	PA_PERF_DEV,	494	PA_PERF_DEV,
495	&perf_fops	495	&perf_fops
496	};	496	};
497		497
498	/*	498	/*
499	* Initialize the module	499	* Initialize the module
500	*/	500	*/
501	static int __init perf_init(void)	501	static int __init perf_init(void)
502	{	502	{
503	int ret;	503	int ret;
504		504
505	/* Determine correct processor interface to use */	505	/* Determine correct processor interface to use */
506	bitmask_array = perf_bitmasks;	506	bitmask_array = perf_bitmasks;
507		507
508	if (boot_cpu_data.cpu_type == pcxu \|\|	508	if (boot_cpu_data.cpu_type == pcxu \|\|
509	boot_cpu_data.cpu_type == pcxu_) {	509	boot_cpu_data.cpu_type == pcxu_) {
510	perf_processor_interface = ONYX_INTF;	510	perf_processor_interface = ONYX_INTF;
511	} else if (boot_cpu_data.cpu_type == pcxw \|\|	511	} else if (boot_cpu_data.cpu_type == pcxw \|\|
512	boot_cpu_data.cpu_type == pcxw_ \|\|	512	boot_cpu_data.cpu_type == pcxw_ \|\|
513	boot_cpu_data.cpu_type == pcxw2 \|\|	513	boot_cpu_data.cpu_type == pcxw2 \|\|
514	boot_cpu_data.cpu_type == mako) {	514	boot_cpu_data.cpu_type == mako) {
515	perf_processor_interface = CUDA_INTF;	515	perf_processor_interface = CUDA_INTF;
516	if (boot_cpu_data.cpu_type == pcxw2 \|\|	516	if (boot_cpu_data.cpu_type == pcxw2 \|\|
517	boot_cpu_data.cpu_type == mako)	517	boot_cpu_data.cpu_type == mako)
518	bitmask_array = perf_bitmasks_piranha;	518	bitmask_array = perf_bitmasks_piranha;
519	} else {	519	} else {
520	perf_processor_interface = UNKNOWN_INTF;	520	perf_processor_interface = UNKNOWN_INTF;
521	printk("Performance monitoring counters not supported on this processor\n");	521	printk("Performance monitoring counters not supported on this processor\n");
522	return -ENODEV;	522	return -ENODEV;
523	}	523	}
524		524
525	ret = misc_register(&perf_dev);	525	ret = misc_register(&perf_dev);
526	if (ret) {	526	if (ret) {
527	printk(KERN_ERR "Performance monitoring counters: "	527	printk(KERN_ERR "Performance monitoring counters: "
528	"cannot register misc device.\n");	528	"cannot register misc device.\n");
529	return ret;	529	return ret;
530	}	530	}
531		531
532	/* Patch the images to match the system */	532	/* Patch the images to match the system */
533	perf_patch_images();	533	perf_patch_images();
534		534
535	spin_lock_init(&perf_lock);	535	spin_lock_init(&perf_lock);
536		536
537	/* TODO: this only lets us access the first cpu.. what to do for SMP? */	537	/* TODO: this only lets us access the first cpu.. what to do for SMP? */
538	cpu_device = cpu_data[0].dev;	538	cpu_device = cpu_data[0].dev;
539	printk("Performance monitoring counters enabled for %s\n",	539	printk("Performance monitoring counters enabled for %s\n",
540	cpu_data[0].dev->name);	540	cpu_data[0].dev->name);
541		541
542	return 0;	542	return 0;
543	}	543	}
544		544
545	/*	545	/*
546	* perf_start_counters(void)	546	* perf_start_counters(void)
547	*	547	*
548	* Start the counters.	548	* Start the counters.
549	*/	549	*/
550	static void perf_start_counters(void)	550	static void perf_start_counters(void)
551	{	551	{
552	/* Enable performance monitor counters */	552	/* Enable performance monitor counters */
553	perf_intrigue_enable_perf_counters();	553	perf_intrigue_enable_perf_counters();
554	}	554	}
555		555
556	/*	556	/*
557	* perf_stop_counters	557	* perf_stop_counters
558	*	558	*
559	* Stop the performance counters and save counts	559	* Stop the performance counters and save counts
560	* in a per_processor array.	560	* in a per_processor array.
561	*/	561	*/
562	static int perf_stop_counters(uint32_t *raddr)	562	static int perf_stop_counters(uint32_t *raddr)
563	{	563	{
564	uint64_t userbuf[MAX_RDR_WORDS];	564	uint64_t userbuf[MAX_RDR_WORDS];
565		565
566	/* Disable performance counters */	566	/* Disable performance counters */
567	perf_intrigue_disable_perf_counters();	567	perf_intrigue_disable_perf_counters();
568		568
569	if (perf_processor_interface == ONYX_INTF) {	569	if (perf_processor_interface == ONYX_INTF) {
570	uint64_t tmp64;	570	uint64_t tmp64;
571	/*	571	/*
572	* Read the counters	572	* Read the counters
573	*/	573	*/
574	if (!perf_rdr_read_ubuf(16, userbuf))	574	if (!perf_rdr_read_ubuf(16, userbuf))
575	return -13;	575	return -13;
576		576
577	/* Counter0 is bits 1398 thru 1429 */	577	/* Counter0 is bits 1398 thru 1429 */
578	tmp64 = (userbuf[21] << 22) & 0x00000000ffc00000;	578	tmp64 = (userbuf[21] << 22) & 0x00000000ffc00000;
579	tmp64 \|= (userbuf[22] >> 42) & 0x00000000003fffff;	579	tmp64 \|= (userbuf[22] >> 42) & 0x00000000003fffff;
580	/* OR sticky0 (bit 1430) to counter0 bit 32 */	580	/* OR sticky0 (bit 1430) to counter0 bit 32 */
581	tmp64 \|= (userbuf[22] >> 10) & 0x0000000080000000;	581	tmp64 \|= (userbuf[22] >> 10) & 0x0000000080000000;
582	raddr[0] = (uint32_t)tmp64;	582	raddr[0] = (uint32_t)tmp64;
583		583
584	/* Counter1 is bits 1431 thru 1462 */	584	/* Counter1 is bits 1431 thru 1462 */
585	tmp64 = (userbuf[22] >> 9) & 0x00000000ffffffff;	585	tmp64 = (userbuf[22] >> 9) & 0x00000000ffffffff;
586	/* OR sticky1 (bit 1463) to counter1 bit 32 */	586	/* OR sticky1 (bit 1463) to counter1 bit 32 */
587	tmp64 \|= (userbuf[22] << 23) & 0x0000000080000000;	587	tmp64 \|= (userbuf[22] << 23) & 0x0000000080000000;
588	raddr[1] = (uint32_t)tmp64;	588	raddr[1] = (uint32_t)tmp64;
589		589
590	/* Counter2 is bits 1464 thru 1495 */	590	/* Counter2 is bits 1464 thru 1495 */
591	tmp64 = (userbuf[22] << 24) & 0x00000000ff000000;	591	tmp64 = (userbuf[22] << 24) & 0x00000000ff000000;
592	tmp64 \|= (userbuf[23] >> 40) & 0x0000000000ffffff;	592	tmp64 \|= (userbuf[23] >> 40) & 0x0000000000ffffff;
593	/* OR sticky2 (bit 1496) to counter2 bit 32 */	593	/* OR sticky2 (bit 1496) to counter2 bit 32 */
594	tmp64 \|= (userbuf[23] >> 8) & 0x0000000080000000;	594	tmp64 \|= (userbuf[23] >> 8) & 0x0000000080000000;
595	raddr[2] = (uint32_t)tmp64;	595	raddr[2] = (uint32_t)tmp64;
596		596
597	/* Counter3 is bits 1497 thru 1528 */	597	/* Counter3 is bits 1497 thru 1528 */
598	tmp64 = (userbuf[23] >> 7) & 0x00000000ffffffff;	598	tmp64 = (userbuf[23] >> 7) & 0x00000000ffffffff;
599	/* OR sticky3 (bit 1529) to counter3 bit 32 */	599	/* OR sticky3 (bit 1529) to counter3 bit 32 */
600	tmp64 \|= (userbuf[23] << 25) & 0x0000000080000000;	600	tmp64 \|= (userbuf[23] << 25) & 0x0000000080000000;
601	raddr[3] = (uint32_t)tmp64;	601	raddr[3] = (uint32_t)tmp64;
602		602
603	/*	603	/*
604	* Zero out the counters	604	* Zero out the counters
605	*/	605	*/
606		606
607	/*	607	/*
608	* The counters and sticky-bits comprise the last 132 bits	608	* The counters and sticky-bits comprise the last 132 bits
609	* (1398 - 1529) of RDR16 on a U chip. We'll zero these	609	* (1398 - 1529) of RDR16 on a U chip. We'll zero these
610	* out the easy way: zero out last 10 bits of dword 21,	610	* out the easy way: zero out last 10 bits of dword 21,
611	* all of dword 22 and 58 bits (plus 6 don't care bits) of	611	* all of dword 22 and 58 bits (plus 6 don't care bits) of
612	* dword 23.	612	* dword 23.
613	*/	613	*/
614	userbuf[21] &= 0xfffffffffffffc00ul; /* 0 to last 10 bits */	614	userbuf[21] &= 0xfffffffffffffc00ul; /* 0 to last 10 bits */
615	userbuf[22] = 0;	615	userbuf[22] = 0;
616	userbuf[23] = 0;	616	userbuf[23] = 0;
617		617
618	/*	618	/*
619	* Write back the zero'ed bytes + the image given	619	* Write back the zero'ed bytes + the image given
620	* the read was destructive.	620	* the read was destructive.
621	*/	621	*/
622	perf_rdr_write(16, userbuf);	622	perf_rdr_write(16, userbuf);
623	} else {	623	} else {
624		624
625	/*	625	/*
626	* Read RDR-15 which contains the counters and sticky bits	626	* Read RDR-15 which contains the counters and sticky bits
627	*/	627	*/
628	if (!perf_rdr_read_ubuf(15, userbuf)) {	628	if (!perf_rdr_read_ubuf(15, userbuf)) {
629	return -13;	629	return -13;
630	}	630	}
631		631
632	/*	632	/*
633	* Clear out the counters	633	* Clear out the counters
634	*/	634	*/
635	perf_rdr_clear(15);	635	perf_rdr_clear(15);
636		636
637	/*	637	/*
638	* Copy the counters	638	* Copy the counters
639	*/	639	*/
640	raddr[0] = (uint32_t)((userbuf[0] >> 32) & 0x00000000ffffffffUL);	640	raddr[0] = (uint32_t)((userbuf[0] >> 32) & 0x00000000ffffffffUL);
641	raddr[1] = (uint32_t)(userbuf[0] & 0x00000000ffffffffUL);	641	raddr[1] = (uint32_t)(userbuf[0] & 0x00000000ffffffffUL);
642	raddr[2] = (uint32_t)((userbuf[1] >> 32) & 0x00000000ffffffffUL);	642	raddr[2] = (uint32_t)((userbuf[1] >> 32) & 0x00000000ffffffffUL);
643	raddr[3] = (uint32_t)(userbuf[1] & 0x00000000ffffffffUL);	643	raddr[3] = (uint32_t)(userbuf[1] & 0x00000000ffffffffUL);
644	}	644	}
645		645
646	return 0;	646	return 0;
647	}	647	}
648		648
649	/*	649	/*
650	* perf_rdr_get_entry	650	* perf_rdr_get_entry
651	*	651	*
652	* Retrieve a pointer to the description of what this	652	* Retrieve a pointer to the description of what this
653	* RDR contains.	653	* RDR contains.
654	*/	654	*/
655	static const struct rdr_tbl_ent * perf_rdr_get_entry(uint32_t rdr_num)	655	static const struct rdr_tbl_ent * perf_rdr_get_entry(uint32_t rdr_num)
656	{	656	{
657	if (perf_processor_interface == ONYX_INTF) {	657	if (perf_processor_interface == ONYX_INTF) {
658	return &perf_rdr_tbl_U[rdr_num];	658	return &perf_rdr_tbl_U[rdr_num];
659	} else {	659	} else {
660	return &perf_rdr_tbl_W[rdr_num];	660	return &perf_rdr_tbl_W[rdr_num];
661	}	661	}
662	}	662	}
663		663
664	/*	664	/*
665	* perf_rdr_read_ubuf	665	* perf_rdr_read_ubuf
666	*	666	*
667	* Read the RDR value into the buffer specified.	667	* Read the RDR value into the buffer specified.
668	*/	668	*/
669	static int perf_rdr_read_ubuf(uint32_t rdr_num, uint64_t *buffer)	669	static int perf_rdr_read_ubuf(uint32_t rdr_num, uint64_t *buffer)
670	{	670	{
671	uint64_t data, data_mask = 0;	671	uint64_t data, data_mask = 0;
672	uint32_t width, xbits, i;	672	uint32_t width, xbits, i;
673	const struct rdr_tbl_ent *tentry;	673	const struct rdr_tbl_ent *tentry;
674		674
675	tentry = perf_rdr_get_entry(rdr_num);	675	tentry = perf_rdr_get_entry(rdr_num);
676	if ((width = tentry->width) == 0)	676	if ((width = tentry->width) == 0)
677	return 0;	677	return 0;
678		678
679	/* Clear out buffer */	679	/* Clear out buffer */
680	i = tentry->num_words;	680	i = tentry->num_words;
681	while (i--) {	681	while (i--) {
682	buffer[i] = 0;	682	buffer[i] = 0;
683	}	683	}
684		684
685	/* Check for bits an even number of 64 */	685	/* Check for bits an even number of 64 */
686	if ((xbits = width & 0x03f) != 0) {	686	if ((xbits = width & 0x03f) != 0) {
687	data_mask = 1;	687	data_mask = 1;
688	data_mask <<= (64 - xbits);	688	data_mask <<= (64 - xbits);
689	data_mask--;	689	data_mask--;
690	}	690	}
691		691
692	/* Grab all of the data */	692	/* Grab all of the data */
693	i = tentry->num_words;	693	i = tentry->num_words;
694	while (i--) {	694	while (i--) {
695		695
696	if (perf_processor_interface == ONYX_INTF) {	696	if (perf_processor_interface == ONYX_INTF) {
697	data = perf_rdr_shift_in_U(rdr_num, width);	697	data = perf_rdr_shift_in_U(rdr_num, width);
698	} else {	698	} else {
699	data = perf_rdr_shift_in_W(rdr_num, width);	699	data = perf_rdr_shift_in_W(rdr_num, width);
700	}	700	}
701	if (xbits) {	701	if (xbits) {
702	buffer[i] \|= (data << (64 - xbits));	702	buffer[i] \|= (data << (64 - xbits));
703	if (i) {	703	if (i) {
704	buffer[i-1] \|= ((data >> xbits) & data_mask);	704	buffer[i-1] \|= ((data >> xbits) & data_mask);
705	}	705	}
706	} else {	706	} else {
707	buffer[i] = data;	707	buffer[i] = data;
708	}	708	}
709	}	709	}
710		710
711	return 1;	711	return 1;
712	}	712	}
713		713
714	/*	714	/*
715	* perf_rdr_clear	715	* perf_rdr_clear
716	*	716	*
717	* Zero out the given RDR register	717	* Zero out the given RDR register
718	*/	718	*/
719	static int perf_rdr_clear(uint32_t rdr_num)	719	static int perf_rdr_clear(uint32_t rdr_num)
720	{	720	{
721	const struct rdr_tbl_ent *tentry;	721	const struct rdr_tbl_ent *tentry;
722	int32_t i;	722	int32_t i;
723		723
724	tentry = perf_rdr_get_entry(rdr_num);	724	tentry = perf_rdr_get_entry(rdr_num);
725		725
726	if (tentry->width == 0) {	726	if (tentry->width == 0) {
727	return -1;	727	return -1;
728	}	728	}
729		729
730	i = tentry->num_words;	730	i = tentry->num_words;
731	while (i--) {	731	while (i--) {
732	if (perf_processor_interface == ONYX_INTF) {	732	if (perf_processor_interface == ONYX_INTF) {
733	perf_rdr_shift_out_U(rdr_num, 0UL);	733	perf_rdr_shift_out_U(rdr_num, 0UL);
734	} else {	734	} else {
735	perf_rdr_shift_out_W(rdr_num, 0UL);	735	perf_rdr_shift_out_W(rdr_num, 0UL);
736	}	736	}
737	}	737	}
738		738
739	return 0;	739	return 0;
740	}	740	}
741		741
742		742
743	/*	743	/*
744	* perf_write_image	744	* perf_write_image
745	*	745	*
746	* Write the given image out to the processor	746	* Write the given image out to the processor
747	*/	747	*/
748	static int perf_write_image(uint64_t *memaddr)	748	static int perf_write_image(uint64_t *memaddr)
749	{	749	{
750	uint64_t buffer[MAX_RDR_WORDS];	750	uint64_t buffer[MAX_RDR_WORDS];
751	uint64_t *bptr;	751	uint64_t *bptr;
752	uint32_t dwords;	752	uint32_t dwords;
753	const uint32_t *intrigue_rdr;	753	const uint32_t *intrigue_rdr;
754	const uint64_t *intrigue_bitmask;	754	const uint64_t *intrigue_bitmask;
755	uint64_t tmp64;	755	uint64_t tmp64;
756	void __iomem *runway;	756	void __iomem *runway;
757	const struct rdr_tbl_ent *tentry;	757	const struct rdr_tbl_ent *tentry;
758	int i;	758	int i;
759		759
760	/* Clear out counters */	760	/* Clear out counters */
761	if (perf_processor_interface == ONYX_INTF) {	761	if (perf_processor_interface == ONYX_INTF) {
762		762
763	perf_rdr_clear(16);	763	perf_rdr_clear(16);
764		764
765	/* Toggle performance monitor */	765	/* Toggle performance monitor */
766	perf_intrigue_enable_perf_counters();	766	perf_intrigue_enable_perf_counters();
767	perf_intrigue_disable_perf_counters();	767	perf_intrigue_disable_perf_counters();
768		768
769	intrigue_rdr = perf_rdrs_U;	769	intrigue_rdr = perf_rdrs_U;
770	} else {	770	} else {
771	perf_rdr_clear(15);	771	perf_rdr_clear(15);
772	intrigue_rdr = perf_rdrs_W;	772	intrigue_rdr = perf_rdrs_W;
773	}	773	}
774		774
775	/* Write all RDRs */	775	/* Write all RDRs */
776	while (*intrigue_rdr != -1) {	776	while (*intrigue_rdr != -1) {
777	tentry = perf_rdr_get_entry(*intrigue_rdr);	777	tentry = perf_rdr_get_entry(*intrigue_rdr);
778	perf_rdr_read_ubuf(*intrigue_rdr, buffer);	778	perf_rdr_read_ubuf(*intrigue_rdr, buffer);
779	bptr = &buffer[0];	779	bptr = &buffer[0];
780	dwords = tentry->num_words;	780	dwords = tentry->num_words;
781	if (tentry->write_control) {	781	if (tentry->write_control) {
782	intrigue_bitmask = &bitmask_array[tentry->write_control >> 3];	782	intrigue_bitmask = &bitmask_array[tentry->write_control >> 3];
783	while (dwords--) {	783	while (dwords--) {
784	tmp64 = intrigue_bitmask & memaddr++;	784	tmp64 = intrigue_bitmask & memaddr++;
785	tmp64 \|= (~(intrigue_bitmask++)) & bptr;	785	tmp64 \|= (~(intrigue_bitmask++)) & bptr;
786	*bptr++ = tmp64;	786	*bptr++ = tmp64;
787	}	787	}
788	} else {	788	} else {
789	while (dwords--) {	789	while (dwords--) {
790	bptr++ = memaddr++;	790	bptr++ = memaddr++;
791	}	791	}
792	}	792	}
793		793
794	perf_rdr_write(*intrigue_rdr, buffer);	794	perf_rdr_write(*intrigue_rdr, buffer);
795	intrigue_rdr++;	795	intrigue_rdr++;
796	}	796	}
797		797
798	/*	798	/*
799	* Now copy out the Runway stuff which is not in RDRs	799	* Now copy out the Runway stuff which is not in RDRs
800	*/	800	*/
801		801
802	if (cpu_device == NULL)	802	if (cpu_device == NULL)
803	{	803	{
804	printk(KERN_ERR "write_image: cpu_device not yet initialized!\n");	804	printk(KERN_ERR "write_image: cpu_device not yet initialized!\n");
805	return -1;	805	return -1;
806	}	806	}
807		807
808	runway = ioremap(cpu_device->hpa.start, 4096);	808	runway = ioremap_nocache(cpu_device->hpa.start, 4096);
809		809
810	/* Merge intrigue bits into Runway STATUS 0 */	810	/* Merge intrigue bits into Runway STATUS 0 */
811	tmp64 = __raw_readq(runway + RUNWAY_STATUS) & 0xffecfffffffffffful;	811	tmp64 = __raw_readq(runway + RUNWAY_STATUS) & 0xffecfffffffffffful;
812	__raw_writeq(tmp64 \| (*memaddr++ & 0x0013000000000000ul),	812	__raw_writeq(tmp64 \| (*memaddr++ & 0x0013000000000000ul),
813	runway + RUNWAY_STATUS);	813	runway + RUNWAY_STATUS);
814		814
815	/* Write RUNWAY DEBUG registers */	815	/* Write RUNWAY DEBUG registers */
816	for (i = 0; i < 8; i++) {	816	for (i = 0; i < 8; i++) {
817	__raw_writeq(*memaddr++, runway + RUNWAY_DEBUG);	817	__raw_writeq(*memaddr++, runway + RUNWAY_DEBUG);
818	}	818	}
819		819
820	return 0;	820	return 0;
821	}	821	}
822		822
823	/*	823	/*
824	* perf_rdr_write	824	* perf_rdr_write
825	*	825	*
826	* Write the given RDR register with the contents	826	* Write the given RDR register with the contents
827	* of the given buffer.	827	* of the given buffer.
828	*/	828	*/
829	static void perf_rdr_write(uint32_t rdr_num, uint64_t *buffer)	829	static void perf_rdr_write(uint32_t rdr_num, uint64_t *buffer)
830	{	830	{
831	const struct rdr_tbl_ent *tentry;	831	const struct rdr_tbl_ent *tentry;
832	int32_t i;	832	int32_t i;
833		833
834	printk("perf_rdr_write\n");	834	printk("perf_rdr_write\n");
835	tentry = perf_rdr_get_entry(rdr_num);	835	tentry = perf_rdr_get_entry(rdr_num);
836	if (tentry->width == 0) { return; }	836	if (tentry->width == 0) { return; }
837		837
838	i = tentry->num_words;	838	i = tentry->num_words;
839	while (i--) {	839	while (i--) {
840	if (perf_processor_interface == ONYX_INTF) {	840	if (perf_processor_interface == ONYX_INTF) {
841	perf_rdr_shift_out_U(rdr_num, buffer[i]);	841	perf_rdr_shift_out_U(rdr_num, buffer[i]);
842	} else {	842	} else {
843	perf_rdr_shift_out_W(rdr_num, buffer[i]);	843	perf_rdr_shift_out_W(rdr_num, buffer[i]);
844	}	844	}
845	}	845	}
846	printk("perf_rdr_write done\n");	846	printk("perf_rdr_write done\n");
847	}	847	}
848		848
849	module_init(perf_init);	849	module_init(perf_init);
850		850

drivers/input/serio/gscps2.c

Diff comments View file @ 5076c15

1	/*	1	/*
2	* drivers/input/serio/gscps2.c	2	* drivers/input/serio/gscps2.c
3	*	3	*
4	* Copyright (c) 2004 Helge Deller <deller@gmx.de>	4	* Copyright (c) 2004-2006 Helge Deller <deller@gmx.de>
5	* Copyright (c) 2002 Laurent Canet <canetl@esiee.fr>	5	* Copyright (c) 2002 Laurent Canet <canetl@esiee.fr>
6	* Copyright (c) 2002 Thibaut Varene <varenet@parisc-linux.org>	6	* Copyright (c) 2002 Thibaut Varene <varenet@parisc-linux.org>
7	*	7	*
8	* Pieces of code based on linux-2.4's hp_mouse.c & hp_keyb.c	8	* Pieces of code based on linux-2.4's hp_mouse.c & hp_keyb.c
9	* Copyright (c) 1999 Alex deVries <alex@onefishtwo.ca>	9	* Copyright (c) 1999 Alex deVries <alex@onefishtwo.ca>
10	* Copyright (c) 1999-2000 Philipp Rumpf <prumpf@tux.org>	10	* Copyright (c) 1999-2000 Philipp Rumpf <prumpf@tux.org>
11	* Copyright (c) 2000 Xavier Debacker <debackex@esiee.fr>	11	* Copyright (c) 2000 Xavier Debacker <debackex@esiee.fr>
12	* Copyright (c) 2000-2001 Thomas Marteau <marteaut@esiee.fr>	12	* Copyright (c) 2000-2001 Thomas Marteau <marteaut@esiee.fr>
13	*	13	*
14	* HP GSC PS/2 port driver, found in PA/RISC Workstations	14	* HP GSC PS/2 port driver, found in PA/RISC Workstations
15	*	15	*
16	* This file is subject to the terms and conditions of the GNU General Public	16	* This file is subject to the terms and conditions of the GNU General Public
17	* License. See the file "COPYING" in the main directory of this archive	17	* License. See the file "COPYING" in the main directory of this archive
18	* for more details.	18	* for more details.
19	*	19	*
20	* TODO:	20	* TODO:
21	* - Dino testing (did HP ever shipped a machine on which this port	21	* - Dino testing (did HP ever shipped a machine on which this port
22	* was usable/enabled ?)	22	* was usable/enabled ?)
23	*/	23	*/
24		24
25	#include <linux/config.h>	25	#include <linux/config.h>
26	#include <linux/init.h>	26	#include <linux/init.h>
27	#include <linux/module.h>	27	#include <linux/module.h>
28	#include <linux/serio.h>	28	#include <linux/serio.h>
29	#include <linux/input.h>	29	#include <linux/input.h>
30	#include <linux/interrupt.h>	30	#include <linux/interrupt.h>
31	#include <linux/spinlock.h>	31	#include <linux/spinlock.h>
32	#include <linux/delay.h>	32	#include <linux/delay.h>
33	#include <linux/ioport.h>	33	#include <linux/ioport.h>
34	#include <linux/pci_ids.h>	34	#include <linux/pci_ids.h>
35		35
36	#include <asm/irq.h>	36	#include <asm/irq.h>
37	#include <asm/io.h>	37	#include <asm/io.h>
38	#include <asm/parisc-device.h>	38	#include <asm/parisc-device.h>
39		39
40	MODULE_AUTHOR("Laurent Canet <canetl@esiee.fr>, Thibaut Varene <varenet@parisc-linux.org>, Helge Deller <deller@gmx.de>");	40	MODULE_AUTHOR("Laurent Canet <canetl@esiee.fr>, Thibaut Varene <varenet@parisc-linux.org>, Helge Deller <deller@gmx.de>");
41	MODULE_DESCRIPTION("HP GSC PS2 port driver");	41	MODULE_DESCRIPTION("HP GSC PS2 port driver");
42	MODULE_LICENSE("GPL");	42	MODULE_LICENSE("GPL");
43	MODULE_DEVICE_TABLE(parisc, gscps2_device_tbl);	43	MODULE_DEVICE_TABLE(parisc, gscps2_device_tbl);
44		44
45	#define PFX "gscps2.c: "	45	#define PFX "gscps2.c: "
46		46
47	/*	47	/*
48	* Driver constants	48	* Driver constants
49	*/	49	*/
50		50
51	/* various constants */	51	/* various constants */
52	#define ENABLE 1	52	#define ENABLE 1
53	#define DISABLE 0	53	#define DISABLE 0
54		54
55	#define GSC_DINO_OFFSET 0x0800 /* offset for DINO controller versus LASI one */	55	#define GSC_DINO_OFFSET 0x0800 /* offset for DINO controller versus LASI one */
56		56
57	/* PS/2 IO port offsets */	57	/* PS/2 IO port offsets */
58	#define GSC_ID 0x00 /* device ID offset (see: GSC_ID_XXX) */	58	#define GSC_ID 0x00 /* device ID offset (see: GSC_ID_XXX) */
59	#define GSC_RESET 0x00 /* reset port offset */	59	#define GSC_RESET 0x00 /* reset port offset */
60	#define GSC_RCVDATA 0x04 /* receive port offset */	60	#define GSC_RCVDATA 0x04 /* receive port offset */
61	#define GSC_XMTDATA 0x04 /* transmit port offset */	61	#define GSC_XMTDATA 0x04 /* transmit port offset */
62	#define GSC_CONTROL 0x08 /* see: Control register bits */	62	#define GSC_CONTROL 0x08 /* see: Control register bits */
63	#define GSC_STATUS 0x0C /* see: Status register bits */	63	#define GSC_STATUS 0x0C /* see: Status register bits */
64		64
65	/* Control register bits */	65	/* Control register bits */
66	#define GSC_CTRL_ENBL 0x01 /* enable interface */	66	#define GSC_CTRL_ENBL 0x01 /* enable interface */
67	#define GSC_CTRL_LPBXR 0x02 /* loopback operation */	67	#define GSC_CTRL_LPBXR 0x02 /* loopback operation */
68	#define GSC_CTRL_DIAG 0x20 /* directly control clock/data line */	68	#define GSC_CTRL_DIAG 0x20 /* directly control clock/data line */
69	#define GSC_CTRL_DATDIR 0x40 /* data line direct control */	69	#define GSC_CTRL_DATDIR 0x40 /* data line direct control */
70	#define GSC_CTRL_CLKDIR 0x80 /* clock line direct control */	70	#define GSC_CTRL_CLKDIR 0x80 /* clock line direct control */
71		71
72	/* Status register bits */	72	/* Status register bits */
73	#define GSC_STAT_RBNE 0x01 /* Receive Buffer Not Empty */	73	#define GSC_STAT_RBNE 0x01 /* Receive Buffer Not Empty */
74	#define GSC_STAT_TBNE 0x02 /* Transmit Buffer Not Empty */	74	#define GSC_STAT_TBNE 0x02 /* Transmit Buffer Not Empty */
75	#define GSC_STAT_TERR 0x04 /* Timeout Error */	75	#define GSC_STAT_TERR 0x04 /* Timeout Error */
76	#define GSC_STAT_PERR 0x08 /* Parity Error */	76	#define GSC_STAT_PERR 0x08 /* Parity Error */
77	#define GSC_STAT_CMPINTR 0x10 /* Composite Interrupt = irq on any port */	77	#define GSC_STAT_CMPINTR 0x10 /* Composite Interrupt = irq on any port */
78	#define GSC_STAT_DATSHD 0x40 /* Data Line Shadow */	78	#define GSC_STAT_DATSHD 0x40 /* Data Line Shadow */
79	#define GSC_STAT_CLKSHD 0x80 /* Clock Line Shadow */	79	#define GSC_STAT_CLKSHD 0x80 /* Clock Line Shadow */
80		80
81	/* IDs returned by GSC_ID port register */	81	/* IDs returned by GSC_ID port register */
82	#define GSC_ID_KEYBOARD 0 /* device ID values */	82	#define GSC_ID_KEYBOARD 0 /* device ID values */
83	#define GSC_ID_MOUSE 1	83	#define GSC_ID_MOUSE 1
84		84
85		85
86	static irqreturn_t gscps2_interrupt(int irq, void dev, struct pt_regs regs);	86	static irqreturn_t gscps2_interrupt(int irq, void dev, struct pt_regs regs);
87		87
88	#define BUFFER_SIZE 0x0f	88	#define BUFFER_SIZE 0x0f
89		89
90	/* GSC PS/2 port device struct */	90	/* GSC PS/2 port device struct */
91	struct gscps2port {	91	struct gscps2port {
92	struct list_head node;	92	struct list_head node;
93	struct parisc_device *padev;	93	struct parisc_device *padev;
94	struct serio *port;	94	struct serio *port;
95	spinlock_t lock;	95	spinlock_t lock;
96	char *addr;	96	char *addr;
97	u8 act, append; /* position in buffer[] */	97	u8 act, append; /* position in buffer[] */
98	struct {	98	struct {
99	u8 data;	99	u8 data;
100	u8 str;	100	u8 str;
101	} buffer[BUFFER_SIZE+1];	101	} buffer[BUFFER_SIZE+1];
102	int id;	102	int id;
103	};	103	};
104		104
105	/*	105	/*
106	* Various HW level routines	106	* Various HW level routines
107	*/	107	*/
108		108
109	#define gscps2_readb_input(x) readb((x)+GSC_RCVDATA)	109	#define gscps2_readb_input(x) readb((x)+GSC_RCVDATA)
110	#define gscps2_readb_control(x) readb((x)+GSC_CONTROL)	110	#define gscps2_readb_control(x) readb((x)+GSC_CONTROL)
111	#define gscps2_readb_status(x) readb((x)+GSC_STATUS)	111	#define gscps2_readb_status(x) readb((x)+GSC_STATUS)
112	#define gscps2_writeb_control(x, y) writeb((x), (y)+GSC_CONTROL)	112	#define gscps2_writeb_control(x, y) writeb((x), (y)+GSC_CONTROL)
113		113
114		114
115	/*	115	/*
116	* wait_TBE() - wait for Transmit Buffer Empty	116	* wait_TBE() - wait for Transmit Buffer Empty
117	*/	117	*/
118		118
119	static int wait_TBE(char *addr)	119	static int wait_TBE(char *addr)
120	{	120	{
121	int timeout = 25000; /* device is expected to react within 250 msec */	121	int timeout = 25000; /* device is expected to react within 250 msec */
122	while (gscps2_readb_status(addr) & GSC_STAT_TBNE) {	122	while (gscps2_readb_status(addr) & GSC_STAT_TBNE) {
123	if (!--timeout)	123	if (!--timeout)
124	return 0; /* This should not happen */	124	return 0; /* This should not happen */
125	udelay(10);	125	udelay(10);
126	}	126	}
127	return 1;	127	return 1;
128	}	128	}
129		129
130		130
131	/*	131	/*
132	* gscps2_flush() - flush the receive buffer	132	* gscps2_flush() - flush the receive buffer
133	*/	133	*/
134		134
135	static void gscps2_flush(struct gscps2port *ps2port)	135	static void gscps2_flush(struct gscps2port *ps2port)
136	{	136	{
137	while (gscps2_readb_status(ps2port->addr) & GSC_STAT_RBNE)	137	while (gscps2_readb_status(ps2port->addr) & GSC_STAT_RBNE)
138	gscps2_readb_input(ps2port->addr);	138	gscps2_readb_input(ps2port->addr);
139	ps2port->act = ps2port->append = 0;	139	ps2port->act = ps2port->append = 0;
140	}	140	}
141		141
142	/*	142	/*
143	* gscps2_writeb_output() - write a byte to the port	143	* gscps2_writeb_output() - write a byte to the port
144	*	144	*
145	* returns 1 on sucess, 0 on error	145	* returns 1 on sucess, 0 on error
146	*/	146	*/
147		147
148	static inline int gscps2_writeb_output(struct gscps2port *ps2port, u8 data)	148	static inline int gscps2_writeb_output(struct gscps2port *ps2port, u8 data)
149	{	149	{
150	unsigned long flags;	150	unsigned long flags;
151	char *addr = ps2port->addr;	151	char *addr = ps2port->addr;
152		152
153	if (!wait_TBE(addr)) {	153	if (!wait_TBE(addr)) {
154	printk(KERN_DEBUG PFX "timeout - could not write byte %#x\n", data);	154	printk(KERN_DEBUG PFX "timeout - could not write byte %#x\n", data);
155	return 0;	155	return 0;
156	}	156	}
157		157
158	while (gscps2_readb_status(ps2port->addr) & GSC_STAT_RBNE)	158	while (gscps2_readb_status(ps2port->addr) & GSC_STAT_RBNE)
159	/* wait */;	159	/* wait */;
160		160
161	spin_lock_irqsave(&ps2port->lock, flags);	161	spin_lock_irqsave(&ps2port->lock, flags);
162	writeb(data, addr+GSC_XMTDATA);	162	writeb(data, addr+GSC_XMTDATA);
163	spin_unlock_irqrestore(&ps2port->lock, flags);	163	spin_unlock_irqrestore(&ps2port->lock, flags);
164		164
165	/* this is ugly, but due to timing of the port it seems to be necessary. */	165	/* this is ugly, but due to timing of the port it seems to be necessary. */
166	mdelay(6);	166	mdelay(6);
167		167
168	/* make sure any received data is returned as fast as possible */	168	/* make sure any received data is returned as fast as possible */
169	/* this is important e.g. when we set the LEDs on the keyboard */	169	/* this is important e.g. when we set the LEDs on the keyboard */
170	gscps2_interrupt(0, NULL, NULL);	170	gscps2_interrupt(0, NULL, NULL);
171		171
172	return 1;	172	return 1;
173	}	173	}
174		174
175		175
176	/*	176	/*
177	* gscps2_enable() - enables or disables the port	177	* gscps2_enable() - enables or disables the port
178	*/	178	*/
179		179
180	static void gscps2_enable(struct gscps2port *ps2port, int enable)	180	static void gscps2_enable(struct gscps2port *ps2port, int enable)
181	{	181	{
182	unsigned long flags;	182	unsigned long flags;
183	u8 data;	183	u8 data;
184		184
185	/* now enable/disable the port */	185	/* now enable/disable the port */
186	spin_lock_irqsave(&ps2port->lock, flags);	186	spin_lock_irqsave(&ps2port->lock, flags);
187	gscps2_flush(ps2port);	187	gscps2_flush(ps2port);
188	data = gscps2_readb_control(ps2port->addr);	188	data = gscps2_readb_control(ps2port->addr);
189	if (enable)	189	if (enable)
190	data \|= GSC_CTRL_ENBL;	190	data \|= GSC_CTRL_ENBL;
191	else	191	else
192	data &= ~GSC_CTRL_ENBL;	192	data &= ~GSC_CTRL_ENBL;
193	gscps2_writeb_control(data, ps2port->addr);	193	gscps2_writeb_control(data, ps2port->addr);
194	spin_unlock_irqrestore(&ps2port->lock, flags);	194	spin_unlock_irqrestore(&ps2port->lock, flags);
195	wait_TBE(ps2port->addr);	195	wait_TBE(ps2port->addr);
196	gscps2_flush(ps2port);	196	gscps2_flush(ps2port);
197	}	197	}
198		198
199	/*	199	/*
200	* gscps2_reset() - resets the PS/2 port	200	* gscps2_reset() - resets the PS/2 port
201	*/	201	*/
202		202
203	static void gscps2_reset(struct gscps2port *ps2port)	203	static void gscps2_reset(struct gscps2port *ps2port)
204	{	204	{
205	char *addr = ps2port->addr;	205	char *addr = ps2port->addr;
206	unsigned long flags;	206	unsigned long flags;
207		207
208	/* reset the interface */	208	/* reset the interface */
209	spin_lock_irqsave(&ps2port->lock, flags);	209	spin_lock_irqsave(&ps2port->lock, flags);
210	gscps2_flush(ps2port);	210	gscps2_flush(ps2port);
211	writeb(0xff, addr+GSC_RESET);	211	writeb(0xff, addr+GSC_RESET);
212	gscps2_flush(ps2port);	212	gscps2_flush(ps2port);
213	spin_unlock_irqrestore(&ps2port->lock, flags);	213	spin_unlock_irqrestore(&ps2port->lock, flags);
214	}	214	}
215		215
216	static LIST_HEAD(ps2port_list);	216	static LIST_HEAD(ps2port_list);
217		217
218	/**	218	/**
219	* gscps2_interrupt() - Interruption service routine	219	* gscps2_interrupt() - Interruption service routine
220	*	220	*
221	* This function reads received PS/2 bytes and processes them on	221	* This function reads received PS/2 bytes and processes them on
222	* all interfaces.	222	* all interfaces.
223	* The problematic part here is, that the keyboard and mouse PS/2 port	223	* The problematic part here is, that the keyboard and mouse PS/2 port
224	* share the same interrupt and it's not possible to send data if any	224	* share the same interrupt and it's not possible to send data if any
225	* one of them holds input data. To solve this problem we try to receive	225	* one of them holds input data. To solve this problem we try to receive
226	* the data as fast as possible and handle the reporting to the upper layer	226	* the data as fast as possible and handle the reporting to the upper layer
227	* later.	227	* later.
228	*/	228	*/
229		229
230	static irqreturn_t gscps2_interrupt(int irq, void dev, struct pt_regs regs)	230	static irqreturn_t gscps2_interrupt(int irq, void dev, struct pt_regs regs)
231	{	231	{
232	struct gscps2port *ps2port;	232	struct gscps2port *ps2port;
233		233
234	list_for_each_entry(ps2port, &ps2port_list, node) {	234	list_for_each_entry(ps2port, &ps2port_list, node) {
235		235
236	unsigned long flags;	236	unsigned long flags;
237	spin_lock_irqsave(&ps2port->lock, flags);	237	spin_lock_irqsave(&ps2port->lock, flags);
238		238
239	while ( (ps2port->buffer[ps2port->append].str =	239	while ( (ps2port->buffer[ps2port->append].str =
240	gscps2_readb_status(ps2port->addr)) & GSC_STAT_RBNE ) {	240	gscps2_readb_status(ps2port->addr)) & GSC_STAT_RBNE ) {
241	ps2port->buffer[ps2port->append].data =	241	ps2port->buffer[ps2port->append].data =
242	gscps2_readb_input(ps2port->addr);	242	gscps2_readb_input(ps2port->addr);
243	ps2port->append = ((ps2port->append+1) & BUFFER_SIZE);	243	ps2port->append = ((ps2port->append+1) & BUFFER_SIZE);
244	}	244	}
245		245
246	spin_unlock_irqrestore(&ps2port->lock, flags);	246	spin_unlock_irqrestore(&ps2port->lock, flags);
247		247
248	} /* list_for_each_entry */	248	} /* list_for_each_entry */
249		249
250	/* all data was read from the ports - now report the data to upper layer */	250	/* all data was read from the ports - now report the data to upper layer */
251		251
252	list_for_each_entry(ps2port, &ps2port_list, node) {	252	list_for_each_entry(ps2port, &ps2port_list, node) {
253		253
254	while (ps2port->act != ps2port->append) {	254	while (ps2port->act != ps2port->append) {
255		255
256	unsigned int rxflags;	256	unsigned int rxflags;
257	u8 data, status;	257	u8 data, status;
258		258
259	/* Did new data arrived while we read existing data ?	259	/* Did new data arrived while we read existing data ?
260	If yes, exit now and let the new irq handler start over again */	260	If yes, exit now and let the new irq handler start over again */
261	if (gscps2_readb_status(ps2port->addr) & GSC_STAT_CMPINTR)	261	if (gscps2_readb_status(ps2port->addr) & GSC_STAT_CMPINTR)
262	return IRQ_HANDLED;	262	return IRQ_HANDLED;
263		263
264	status = ps2port->buffer[ps2port->act].str;	264	status = ps2port->buffer[ps2port->act].str;
265	data = ps2port->buffer[ps2port->act].data;	265	data = ps2port->buffer[ps2port->act].data;
266		266
267	ps2port->act = ((ps2port->act+1) & BUFFER_SIZE);	267	ps2port->act = ((ps2port->act+1) & BUFFER_SIZE);
268	rxflags = ((status & GSC_STAT_TERR) ? SERIO_TIMEOUT : 0 ) \|	268	rxflags = ((status & GSC_STAT_TERR) ? SERIO_TIMEOUT : 0 ) \|
269	((status & GSC_STAT_PERR) ? SERIO_PARITY : 0 );	269	((status & GSC_STAT_PERR) ? SERIO_PARITY : 0 );
270		270
271	serio_interrupt(ps2port->port, data, rxflags, regs);	271	serio_interrupt(ps2port->port, data, rxflags, regs);
272		272
273	} /* while() */	273	} /* while() */
274		274
275	} /* list_for_each_entry */	275	} /* list_for_each_entry */
276		276
277	return IRQ_HANDLED;	277	return IRQ_HANDLED;
278	}	278	}
279		279
280		280
281	/*	281	/*
282	* gscps2_write() - send a byte out through the aux interface.	282	* gscps2_write() - send a byte out through the aux interface.
283	*/	283	*/
284		284
285	static int gscps2_write(struct serio *port, unsigned char data)	285	static int gscps2_write(struct serio *port, unsigned char data)
286	{	286	{
287	struct gscps2port *ps2port = port->port_data;	287	struct gscps2port *ps2port = port->port_data;
288		288
289	if (!gscps2_writeb_output(ps2port, data)) {	289	if (!gscps2_writeb_output(ps2port, data)) {
290	printk(KERN_DEBUG PFX "sending byte %#x failed.\n", data);	290	printk(KERN_DEBUG PFX "sending byte %#x failed.\n", data);
291	return -1;	291	return -1;
292	}	292	}
293	return 0;	293	return 0;
294	}	294	}
295		295
296	/*	296	/*
297	* gscps2_open() is called when a port is opened by the higher layer.	297	* gscps2_open() is called when a port is opened by the higher layer.
298	* It resets and enables the port.	298	* It resets and enables the port.
299	*/	299	*/
300		300
301	static int gscps2_open(struct serio *port)	301	static int gscps2_open(struct serio *port)
302	{	302	{
303	struct gscps2port *ps2port = port->port_data;	303	struct gscps2port *ps2port = port->port_data;
304		304
305	gscps2_reset(ps2port);	305	gscps2_reset(ps2port);
306		306
307	/* enable it */	307	/* enable it */
308	gscps2_enable(ps2port, ENABLE);	308	gscps2_enable(ps2port, ENABLE);
309		309
310	gscps2_interrupt(0, NULL, NULL);	310	gscps2_interrupt(0, NULL, NULL);
311		311
312	return 0;	312	return 0;
313	}	313	}
314		314
315	/*	315	/*
316	* gscps2_close() disables the port	316	* gscps2_close() disables the port
317	*/	317	*/
318		318
319	static void gscps2_close(struct serio *port)	319	static void gscps2_close(struct serio *port)
320	{	320	{
321	struct gscps2port *ps2port = port->port_data;	321	struct gscps2port *ps2port = port->port_data;
322	gscps2_enable(ps2port, DISABLE);	322	gscps2_enable(ps2port, DISABLE);
323	}	323	}
324		324
325	/**	325	/**
326	* gscps2_probe() - Probes PS2 devices	326	* gscps2_probe() - Probes PS2 devices
327	* @return: success/error report	327	* @return: success/error report
328	*/	328	*/
329		329
330	static int __init gscps2_probe(struct parisc_device *dev)	330	static int __init gscps2_probe(struct parisc_device *dev)
331	{	331	{
332	struct gscps2port *ps2port;	332	struct gscps2port *ps2port;
333	struct serio *serio;	333	struct serio *serio;
334	unsigned long hpa = dev->hpa.start;	334	unsigned long hpa = dev->hpa.start;
335	int ret;	335	int ret;
336		336
337	if (!dev->irq)	337	if (!dev->irq)
338	return -ENODEV;	338	return -ENODEV;
339		339
340	/* Offset for DINO PS/2. Works with LASI even */	340	/* Offset for DINO PS/2. Works with LASI even */
341	if (dev->id.sversion == 0x96)	341	if (dev->id.sversion == 0x96)
342	hpa += GSC_DINO_OFFSET;	342	hpa += GSC_DINO_OFFSET;
343		343
344	ps2port = kmalloc(sizeof(struct gscps2port), GFP_KERNEL);	344	ps2port = kmalloc(sizeof(struct gscps2port), GFP_KERNEL);
345	serio = kmalloc(sizeof(struct serio), GFP_KERNEL);	345	serio = kmalloc(sizeof(struct serio), GFP_KERNEL);
346	if (!ps2port \|\| !serio) {	346	if (!ps2port \|\| !serio) {
347	ret = -ENOMEM;	347	ret = -ENOMEM;
348	goto fail_nomem;	348	goto fail_nomem;
349	}	349	}
350		350
351	dev_set_drvdata(&dev->dev, ps2port);	351	dev_set_drvdata(&dev->dev, ps2port);
352		352
353	memset(ps2port, 0, sizeof(struct gscps2port));	353	memset(ps2port, 0, sizeof(struct gscps2port));
354	memset(serio, 0, sizeof(struct serio));	354	memset(serio, 0, sizeof(struct serio));
355	ps2port->port = serio;	355	ps2port->port = serio;
356	ps2port->padev = dev;	356	ps2port->padev = dev;
357	ps2port->addr = ioremap(hpa, GSC_STATUS + 4);	357	ps2port->addr = ioremap_nocache(hpa, GSC_STATUS + 4);
358	spin_lock_init(&ps2port->lock);	358	spin_lock_init(&ps2port->lock);
359		359
360	gscps2_reset(ps2port);	360	gscps2_reset(ps2port);
361	ps2port->id = readb(ps2port->addr + GSC_ID) & 0x0f;	361	ps2port->id = readb(ps2port->addr + GSC_ID) & 0x0f;
362		362
363	snprintf(serio->name, sizeof(serio->name), "GSC PS/2 %s",	363	snprintf(serio->name, sizeof(serio->name), "GSC PS/2 %s",
364	(ps2port->id == GSC_ID_KEYBOARD) ? "keyboard" : "mouse");	364	(ps2port->id == GSC_ID_KEYBOARD) ? "keyboard" : "mouse");
365	strlcpy(serio->phys, dev->dev.bus_id, sizeof(serio->phys));	365	strlcpy(serio->phys, dev->dev.bus_id, sizeof(serio->phys));
366	serio->id.type = SERIO_8042;	366	serio->id.type = SERIO_8042;
367	serio->write = gscps2_write;	367	serio->write = gscps2_write;
368	serio->open = gscps2_open;	368	serio->open = gscps2_open;
369	serio->close = gscps2_close;	369	serio->close = gscps2_close;
370	serio->port_data = ps2port;	370	serio->port_data = ps2port;
371	serio->dev.parent = &dev->dev;	371	serio->dev.parent = &dev->dev;
372		372
373	ret = -EBUSY;	373	ret = -EBUSY;
374	if (request_irq(dev->irq, gscps2_interrupt, SA_SHIRQ, ps2port->port->name, ps2port))	374	if (request_irq(dev->irq, gscps2_interrupt, SA_SHIRQ, ps2port->port->name, ps2port))
375	goto fail_miserably;	375	goto fail_miserably;
376		376
377	if (ps2port->id != GSC_ID_KEYBOARD && ps2port->id != GSC_ID_MOUSE) {	377	if (ps2port->id != GSC_ID_KEYBOARD && ps2port->id != GSC_ID_MOUSE) {
378	printk(KERN_WARNING PFX "Unsupported PS/2 port at 0x%08lx (id=%d) ignored\n",	378	printk(KERN_WARNING PFX "Unsupported PS/2 port at 0x%08lx (id=%d) ignored\n",
379	hpa, ps2port->id);	379	hpa, ps2port->id);
380	ret = -ENODEV;	380	ret = -ENODEV;
381	goto fail;	381	goto fail;
382	}	382	}
383		383
384	#if 0	384	#if 0
385	if (!request_mem_region(hpa, GSC_STATUS + 4, ps2port->port.name))	385	if (!request_mem_region(hpa, GSC_STATUS + 4, ps2port->port.name))
386	goto fail;	386	goto fail;
387	#endif	387	#endif
388		388
389	printk(KERN_INFO "serio: %s port at 0x%p irq %d @ %s\n",	389	printk(KERN_INFO "serio: %s port at 0x%p irq %d @ %s\n",
390	ps2port->port->name,	390	ps2port->port->name,
391	ps2port->addr,	391	ps2port->addr,
392	ps2port->padev->irq,	392	ps2port->padev->irq,
393	ps2port->port->phys);	393	ps2port->port->phys);
394		394
395	serio_register_port(ps2port->port);	395	serio_register_port(ps2port->port);
396		396
397	list_add_tail(&ps2port->node, &ps2port_list);	397	list_add_tail(&ps2port->node, &ps2port_list);
398		398
399	return 0;	399	return 0;
400		400
401	fail:	401	fail:
402	free_irq(dev->irq, ps2port);	402	free_irq(dev->irq, ps2port);
403		403
404	fail_miserably:	404	fail_miserably:
405	iounmap(ps2port->addr);	405	iounmap(ps2port->addr);
406	release_mem_region(dev->hpa.start, GSC_STATUS + 4);	406	release_mem_region(dev->hpa.start, GSC_STATUS + 4);
407		407
408	fail_nomem:	408	fail_nomem:
409	kfree(ps2port);	409	kfree(ps2port);
410	kfree(serio);	410	kfree(serio);
411	return ret;	411	return ret;
412	}	412	}
413		413
414	/**	414	/**
415	* gscps2_remove() - Removes PS2 devices	415	* gscps2_remove() - Removes PS2 devices
416	* @return: success/error report	416	* @return: success/error report
417	*/	417	*/
418		418
419	static int __devexit gscps2_remove(struct parisc_device *dev)	419	static int __devexit gscps2_remove(struct parisc_device *dev)
420	{	420	{
421	struct gscps2port *ps2port = dev_get_drvdata(&dev->dev);	421	struct gscps2port *ps2port = dev_get_drvdata(&dev->dev);
422		422
423	serio_unregister_port(ps2port->port);	423	serio_unregister_port(ps2port->port);
424	free_irq(dev->irq, ps2port);	424	free_irq(dev->irq, ps2port);
425	gscps2_flush(ps2port);	425	gscps2_flush(ps2port);
426	list_del(&ps2port->node);	426	list_del(&ps2port->node);
427	iounmap(ps2port->addr);	427	iounmap(ps2port->addr);
428	#if 0	428	#if 0
429	release_mem_region(dev->hpa, GSC_STATUS + 4);	429	release_mem_region(dev->hpa, GSC_STATUS + 4);
430	#endif	430	#endif
431	dev_set_drvdata(&dev->dev, NULL);	431	dev_set_drvdata(&dev->dev, NULL);
432	kfree(ps2port);	432	kfree(ps2port);
433	return 0;	433	return 0;
434	}	434	}
435		435
436		436
437	static struct parisc_device_id gscps2_device_tbl[] = {	437	static struct parisc_device_id gscps2_device_tbl[] = {
438	{ HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00084 }, /* LASI PS/2 */	438	{ HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00084 }, /* LASI PS/2 */
439	#ifdef DINO_TESTED	439	#ifdef DINO_TESTED
440	{ HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00096 }, /* DINO PS/2 */	440	{ HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00096 }, /* DINO PS/2 */
441	#endif	441	#endif
442	{ 0, } /* 0 terminated list */	442	{ 0, } /* 0 terminated list */
443	};	443	};
444		444
445	static struct parisc_driver parisc_ps2_driver = {	445	static struct parisc_driver parisc_ps2_driver = {
446	.name = "gsc_ps2",	446	.name = "gsc_ps2",
447	.id_table = gscps2_device_tbl,	447	.id_table = gscps2_device_tbl,
448	.probe = gscps2_probe,	448	.probe = gscps2_probe,
449	.remove = gscps2_remove,	449	.remove = gscps2_remove,
450	};	450	};
451		451
452	static int __init gscps2_init(void)	452	static int __init gscps2_init(void)
453	{	453	{
454	register_parisc_driver(&parisc_ps2_driver);	454	register_parisc_driver(&parisc_ps2_driver);
455	return 0;	455	return 0;
456	}	456	}
457		457
458	static void __exit gscps2_exit(void)	458	static void __exit gscps2_exit(void)
459	{	459	{
460	unregister_parisc_driver(&parisc_ps2_driver);	460	unregister_parisc_driver(&parisc_ps2_driver);
461	}	461	}
462		462
463		463
464	module_init(gscps2_init);	464	module_init(gscps2_init);
465	module_exit(gscps2_exit);	465	module_exit(gscps2_exit);
466		466
467		467

drivers/parisc/ccio-dma.c

Diff comments View file @ 5076c15

drivers/parisc/dino.c

Diff comments View file @ 5076c15

 /*
 **	DINO manager
 **
 **	(c) Copyright 1999 Red Hat Software
 **	(c) Copyright 1999 SuSE GmbH
 **	(c) Copyright 1999,2000 Hewlett-Packard Company
 **	(c) Copyright 2000 Grant Grundler
+**	(c) Copyright 2006 Helge Deller
 **
 **	This program is free software; you can redistribute it and/or modify
 **	it under the terms of the GNU General Public License as published by
 **      the Free Software Foundation; either version 2 of the License, or
 **      (at your option) any later version.
 **
 **	This module provides access to Dino PCI bus (config/IOport spaces)
 **	and helps manage Dino IRQ lines.
 **
 **	Dino interrupt handling is a bit complicated.
 **	Dino always writes to the broadcast EIR via irr0 for now.
 **	(BIG WARNING: using broadcast EIR is a really bad thing for SMP!)
 **	Only one processor interrupt is used for the 11 IRQ line
 **	inputs to dino.
 **
 **	The different between Built-in Dino and Card-Mode
 **	dino is in chip initialization and pci device initialization.
 **
 **	Linux drivers can only use Card-Mode Dino if pci devices I/O port
 **	BARs are configured and used by the driver. Programming MMIO address
 **	requires substantial knowledge of available Host I/O address ranges
 **	is currently not supported.  Port/Config accessor functions are the
 **	same. "BIOS" differences are handled within the existing routines.
 */
 /*	Changes :
 **	2001-06-14 : Clement Moyroud (moyroudc@esiee.fr)
 **		- added support for the integrated RS232.
 */
 /*
 ** TODO: create a virtual address for each Dino HPA.
 **       GSC code might be able to do this since IODC data tells us
 **       how many pages are used. PCI subsystem could (must?) do this
 **       for PCI drivers devices which implement/use MMIO registers.
 */
 #include <linux/config.h>
 #include <linux/delay.h>
 #include <linux/types.h>
 #include <linux/kernel.h>
 #include <linux/pci.h>
 #include <linux/init.h>
 #include <linux/ioport.h>
 #include <linux/slab.h>
 #include <linux/interrupt.h>	/* for struct irqaction */
 #include <linux/spinlock.h>	/* for spinlock_t and prototypes */
 #include <asm/pdc.h>
 #include <asm/page.h>
 #include <asm/system.h>
 #include <asm/io.h>
 #include <asm/hardware.h>
 #include "gsc.h"
 #undef DINO_DEBUG
 #ifdef DINO_DEBUG
 #define DBG(x...) printk(x)
 #else
 #define DBG(x...)
 #endif
 /*
 ** Config accessor functions only pass in the 8-bit bus number
 ** and not the 8-bit "PCI Segment" number. Each Dino will be
 ** assigned a PCI bus number based on "when" it's discovered.
 **
 ** The "secondary" bus number is set to this before calling
 ** pci_scan_bus(). If any PPB's are present, the scan will
 ** discover them and update the "secondary" and "subordinate"
 ** fields in Dino's pci_bus structure.
 **
 ** Changes in the configuration *will* result in a different
 ** bus number for each dino.
 */
 #define is_card_dino(id)	((id)->hw_type == HPHW_A_DMA)
 #define is_cujo(id)		((id)->hversion == 0x682)
 #define DINO_IAR0		0x004
 #define DINO_IODC_ADDR		0x008
 #define DINO_IODC_DATA_0	0x008
 #define DINO_IODC_DATA_1	0x008
 #define DINO_IRR0		0x00C
 #define DINO_IAR1		0x010
 #define DINO_IRR1		0x014
 #define DINO_IMR		0x018
 #define DINO_IPR		0x01C
 #define DINO_TOC_ADDR		0x020
 #define DINO_ICR		0x024
 #define DINO_ILR		0x028
 #define DINO_IO_COMMAND		0x030
 #define DINO_IO_STATUS		0x034
 #define DINO_IO_CONTROL		0x038
 #define DINO_IO_GSC_ERR_RESP	0x040
 #define DINO_IO_ERR_INFO	0x044
 #define DINO_IO_PCI_ERR_RESP	0x048
 #define DINO_IO_FBB_EN		0x05c
 #define DINO_IO_ADDR_EN		0x060
 #define DINO_PCI_ADDR		0x064
 #define DINO_CONFIG_DATA	0x068
 #define DINO_IO_DATA		0x06c
 #define DINO_MEM_DATA		0x070	/* Dino 3.x only */
 #define DINO_GSC2X_CONFIG	0x7b4
 #define DINO_GMASK		0x800
 #define DINO_PAMR		0x804
 #define DINO_PAPR		0x808
 #define DINO_DAMODE		0x80c
 #define DINO_PCICMD		0x810
 #define DINO_PCISTS		0x814
 #define DINO_MLTIM		0x81c
 #define DINO_BRDG_FEAT		0x820
 #define DINO_PCIROR		0x824
 #define DINO_PCIWOR		0x828
 #define DINO_TLTIM		0x830
 #define DINO_IRQS 11		/* bits 0-10 are architected */
 #define DINO_IRR_MASK	0x5ff	/* only 10 bits are implemented */
 #define DINO_LOCAL_IRQS (DINO_IRQS+1)
 #define DINO_MASK_IRQ(x)	(1<<(x))
 #define PCIINTA   0x001
 #define PCIINTB   0x002
 #define PCIINTC   0x004
 #define PCIINTD   0x008
 #define PCIINTE   0x010
 #define PCIINTF   0x020
 #define GSCEXTINT 0x040
 /* #define xxx       0x080 - bit 7 is "default" */
 /* #define xxx    0x100 - bit 8 not used */
 /* #define xxx    0x200 - bit 9 not used */
 #define RS232INT  0x400
 struct dino_device
 {
 	struct pci_hba_data	hba;	/* 'C' inheritance - must be first */
 	spinlock_t		dinosaur_pen;
 	unsigned long		txn_addr; /* EIR addr to generate interrupt */
 	u32			txn_data; /* EIR data assign to each dino */
 	u32 			imr;	  /* IRQ's which are enabled */
 	int			global_irq[DINO_LOCAL_IRQS]; /* map IMR bit to global irq */
 #ifdef DINO_DEBUG
 	unsigned int		dino_irr0; /* save most recent IRQ line stat */
 #endif
 };
 /* Looks nice and keeps the compiler happy */
 #define DINO_DEV(d) ((struct dino_device *) d)
 /*
  * Dino Configuration Space Accessor Functions
  */
 #define DINO_CFG_TOK(bus,dfn,pos) ((u32) ((bus)<<16 | (dfn)<<8 | (pos)))
 /*
  * keep the current highest bus count to assist in allocating busses.  This
  * tries to keep a global bus count total so that when we discover an
  * entirely new bus, it can be given a unique bus number.
  */
 static int dino_current_bus = 0;
 static int dino_cfg_read(struct pci_bus *bus, unsigned int devfn, int where,
 		int size, u32 *val)
 {
 	struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
 	u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
 	u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
 	void __iomem *base_addr = d->hba.base_addr;
 	unsigned long flags;
 	DBG("%s: %p, %d, %d, %d\n", __FUNCTION__, base_addr, devfn, where,
 									size);
 	spin_lock_irqsave(&d->dinosaur_pen, flags);
 	/* tell HW which CFG address */
 	__raw_writel(v, base_addr + DINO_PCI_ADDR);
 	/* generate cfg read cycle */
 	if (size == 1) {
 		*val = readb(base_addr + DINO_CONFIG_DATA + (where & 3));
 	} else if (size == 2) {
 		*val = readw(base_addr + DINO_CONFIG_DATA + (where & 2));
 	} else if (size == 4) {
 		*val = readl(base_addr + DINO_CONFIG_DATA);
 	}
 	spin_unlock_irqrestore(&d->dinosaur_pen, flags);
 	return 0;
 }
 /*
  * Dino address stepping "feature":
  * When address stepping, Dino attempts to drive the bus one cycle too soon
  * even though the type of cycle (config vs. MMIO) might be different.
  * The read of Ven/Prod ID is harmless and avoids Dino's address stepping.
  */
 static int dino_cfg_write(struct pci_bus *bus, unsigned int devfn, int where,
 	int size, u32 val)
 {
 	struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
 	u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
 	u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
 	void __iomem *base_addr = d->hba.base_addr;
 	unsigned long flags;
 	DBG("%s: %p, %d, %d, %d\n", __FUNCTION__, base_addr, devfn, where,
 									size);
 	spin_lock_irqsave(&d->dinosaur_pen, flags);
 	/* avoid address stepping feature */
 	__raw_writel(v & 0xffffff00, base_addr + DINO_PCI_ADDR);
 	__raw_readl(base_addr + DINO_CONFIG_DATA);
 	/* tell HW which CFG address */
 	__raw_writel(v, base_addr + DINO_PCI_ADDR);
 	/* generate cfg read cycle */
 	if (size == 1) {
 		writeb(val, base_addr + DINO_CONFIG_DATA + (where & 3));
 	} else if (size == 2) {
 		writew(val, base_addr + DINO_CONFIG_DATA + (where & 2));
 	} else if (size == 4) {
 		writel(val, base_addr + DINO_CONFIG_DATA);
 	}
 	spin_unlock_irqrestore(&d->dinosaur_pen, flags);
 	return 0;
 }
 static struct pci_ops dino_cfg_ops = {
 	.read =		dino_cfg_read,
 	.write =	dino_cfg_write,
 };
 /*
  * Dino "I/O Port" Space Accessor Functions
  *
  * Many PCI devices don't require use of I/O port space (eg Tulip,
  * NCR720) since they export the same registers to both MMIO and
  * I/O port space.  Performance is going to stink if drivers use
  * I/O port instead of MMIO.
  */
 #define DINO_PORT_IN(type, size, mask) \
 static u##size dino_in##size (struct pci_hba_data *d, u16 addr) \
 { \
 	u##size v; \
 	unsigned long flags; \
 	spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
 	/* tell HW which IO Port address */ \
 	__raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
 	/* generate I/O PORT read cycle */ \
 	v = read##type(d->base_addr+DINO_IO_DATA+(addr&mask)); \
 	spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
 	return v; \
 }
 DINO_PORT_IN(b,  8, 3)
 DINO_PORT_IN(w, 16, 2)
 DINO_PORT_IN(l, 32, 0)
 #define DINO_PORT_OUT(type, size, mask) \
 static void dino_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
 { \
 	unsigned long flags; \
 	spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
 	/* tell HW which IO port address */ \
 	__raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
 	/* generate cfg write cycle */ \
 	write##type(val, d->base_addr+DINO_IO_DATA+(addr&mask)); \
 	spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
 }
 DINO_PORT_OUT(b,  8, 3)
 DINO_PORT_OUT(w, 16, 2)
 DINO_PORT_OUT(l, 32, 0)
 struct pci_port_ops dino_port_ops = {
 	.inb	= dino_in8,
 	.inw	= dino_in16,
 	.inl	= dino_in32,
 	.outb	= dino_out8,
 	.outw	= dino_out16,
 	.outl	= dino_out32
 };
 static void dino_disable_irq(unsigned int irq)
 {
 	struct dino_device *dino_dev = irq_desc[irq].handler_data;
 	int local_irq = gsc_find_local_irq(irq, dino_dev->global_irq, DINO_LOCAL_IRQS);
 	DBG(KERN_WARNING "%s(0x%p, %d)\n", __FUNCTION__, dino_dev, irq);
 	/* Clear the matching bit in the IMR register */
 	dino_dev->imr &= ~(DINO_MASK_IRQ(local_irq));
 	__raw_writel(dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
 }
 static void dino_enable_irq(unsigned int irq)
 {
 	struct dino_device *dino_dev = irq_desc[irq].handler_data;
 	int local_irq = gsc_find_local_irq(irq, dino_dev->global_irq, DINO_LOCAL_IRQS);
 	u32 tmp;
 	DBG(KERN_WARNING "%s(0x%p, %d)\n", __FUNCTION__, dino_dev, irq);
 	/*
 	** clear pending IRQ bits
 	**
 	** This does NOT change ILR state!
 	** See comment below for ILR usage.
 	*/
 	__raw_readl(dino_dev->hba.base_addr+DINO_IPR);
 	/* set the matching bit in the IMR register */
 	dino_dev->imr |= DINO_MASK_IRQ(local_irq);	/* used in dino_isr() */
 	__raw_writel( dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
 	/* Emulate "Level Triggered" Interrupt
 	** Basically, a driver is blowing it if the IRQ line is asserted
 	** while the IRQ is disabled.  But tulip.c seems to do that....
 	** Give 'em a kluge award and a nice round of applause!
 	**
 	** The gsc_write will generate an interrupt which invokes dino_isr().
 	** dino_isr() will read IPR and find nothing. But then catch this
 	** when it also checks ILR.
 	*/
 	tmp = __raw_readl(dino_dev->hba.base_addr+DINO_ILR);
 	if (tmp & DINO_MASK_IRQ(local_irq)) {
 		DBG(KERN_WARNING "%s(): IRQ asserted! (ILR 0x%x)\n",
 				__FUNCTION__, tmp);
 		gsc_writel(dino_dev->txn_data, dino_dev->txn_addr);
 	}
 }
 static unsigned int dino_startup_irq(unsigned int irq)
 {
 	dino_enable_irq(irq);
 	return 0;
 }
 static struct hw_interrupt_type dino_interrupt_type = {
 	.typename	= "GSC-PCI",
 	.startup	= dino_startup_irq,
 	.shutdown	= dino_disable_irq,
 	.enable		= dino_enable_irq,
 	.disable	= dino_disable_irq,
 	.ack		= no_ack_irq,
 	.end		= no_end_irq,
 };
 /*
  * Handle a Processor interrupt generated by Dino.
  *
  * ilr_loop counter is a kluge to prevent a "stuck" IRQ line from
  * wedging the CPU. Could be removed or made optional at some point.
  */
 static irqreturn_t
 dino_isr(int irq, void *intr_dev, struct pt_regs *regs)
 {
 	struct dino_device *dino_dev = intr_dev;
 	u32 mask;
 	int ilr_loop = 100;
 	/* read and acknowledge pending interrupts */
 #ifdef DINO_DEBUG
 	dino_dev->dino_irr0 =
 #endif
 	mask = __raw_readl(dino_dev->hba.base_addr+DINO_IRR0) & DINO_IRR_MASK;
 	if (mask == 0)
 		return IRQ_NONE;
 ilr_again:
 	do {
 		int local_irq = __ffs(mask);
 		int irq = dino_dev->global_irq[local_irq];
 		DBG(KERN_DEBUG "%s(%d, %p) mask 0x%x\n",
 			__FUNCTION__, irq, intr_dev, mask);
 		__do_IRQ(irq, regs);
 		mask &= ~(1 << local_irq);
 	} while (mask);
 	/* Support for level triggered IRQ lines.
 	**
 	** Dropping this support would make this routine *much* faster.
 	** But since PCI requires level triggered IRQ line to share lines...
 	** device drivers may assume lines are level triggered (and not
 	** edge triggered like EISA/ISA can be).
 	*/
 	mask = __raw_readl(dino_dev->hba.base_addr+DINO_ILR) & dino_dev->imr;
 	if (mask) {
 		if (--ilr_loop > 0)
 			goto ilr_again;
 		printk(KERN_ERR "Dino 0x%p: stuck interrupt %d\n",
 		       dino_dev->hba.base_addr, mask);
 		return IRQ_NONE;
 	}
 	return IRQ_HANDLED;
 }
 static void dino_assign_irq(struct dino_device *dino, int local_irq, int *irqp)
 {
 	int irq = gsc_assign_irq(&dino_interrupt_type, dino);
 	if (irq == NO_IRQ)
 		return;
 	*irqp = irq;
 	dino->global_irq[local_irq] = irq;
 }
 static void dino_choose_irq(struct parisc_device *dev, void *ctrl)
 {
 	int irq;
 	struct dino_device *dino = ctrl;
 	switch (dev->id.sversion) {
 		case 0x00084:	irq =  8; break; /* PS/2 */
 		case 0x0008c:	irq = 10; break; /* RS232 */
 		case 0x00096:	irq =  8; break; /* PS/2 */
 		default:	return;		 /* Unknown */
 	}
 	dino_assign_irq(dino, irq, &dev->irq);
 }
 /*
  * Cirrus 6832 Cardbus reports wrong irq on RDI Tadpole PARISC Laptop (deller@gmx.de)
  * (the irqs are off-by-one, not sure yet if this is a cirrus, dino-hardware or dino-driver problem...)
  */
 static void __devinit quirk_cirrus_cardbus(struct pci_dev *dev)
 {
 	u8 new_irq = dev->irq - 1;
 	printk(KERN_INFO "PCI: Cirrus Cardbus IRQ fixup for %s, from %d to %d\n",
 			pci_name(dev), dev->irq, new_irq);
 	dev->irq = new_irq;
 }
 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6832, quirk_cirrus_cardbus );
 static void __init
 dino_bios_init(void)
 {
 	DBG("dino_bios_init\n");
 }
 /*
  * dino_card_setup - Set up the memory space for a Dino in card mode.
  * @bus: the bus under this dino
  *
  * Claim an 8MB chunk of unused IO space and call the generic PCI routines
  * to set up the addresses of the devices on this bus.
  */
 #define _8MB 0x00800000UL
 static void __init
 dino_card_setup(struct pci_bus *bus, void __iomem *base_addr)
 {
 	int i;
 	struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge));
 	struct resource *res;
 	char name[128];
 	int size;
 	res = &dino_dev->hba.lmmio_space;
 	res->flags = IORESOURCE_MEM;
 	size = scnprintf(name, sizeof(name), "Dino LMMIO (%s)",
 			 bus->bridge->bus_id);
 	res->name = kmalloc(size+1, GFP_KERNEL);
 	if(res->name)
 		strcpy((char *)res->name, name);
 	else
 		res->name = dino_dev->hba.lmmio_space.name;
 	if (ccio_allocate_resource(dino_dev->hba.dev, res, _8MB,
 				F_EXTEND(0xf0000000UL) | _8MB,
 				F_EXTEND(0xffffffffUL) &~ _8MB, _8MB) < 0) {
 		struct list_head *ln, *tmp_ln;
 		printk(KERN_ERR "Dino: cannot attach bus %s\n",
 		       bus->bridge->bus_id);
 		/* kill the bus, we can't do anything with it */
 		list_for_each_safe(ln, tmp_ln, &bus->devices) {
 			struct pci_dev *dev = pci_dev_b(ln);
 			list_del(&dev->global_list);
 			list_del(&dev->bus_list);
 		}
 		return;
 	}
 	bus->resource[1] = res;
 	bus->resource[0] = &(dino_dev->hba.io_space);
 	/* Now tell dino what range it has */
 	for (i = 1; i < 31; i++) {
 		if (res->start == F_EXTEND(0xf0000000UL | (i * _8MB)))
 			break;
 	}
 	DBG("DINO GSC WRITE i=%d, start=%lx, dino addr = %p\n",
 	    i, res->start, base_addr + DINO_IO_ADDR_EN);
 	__raw_writel(1 << i, base_addr + DINO_IO_ADDR_EN);
 }
 static void __init
 dino_card_fixup(struct pci_dev *dev)
 {
 	u32 irq_pin;
 	/*
 	** REVISIT: card-mode PCI-PCI expansion chassis do exist.
 	**         Not sure they were ever productized.
 	**         Die here since we'll die later in dino_inb() anyway.
 	*/
 	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
 		panic("Card-Mode Dino: PCI-PCI Bridge not supported\n");
 	}
 	/*
 	** Set Latency Timer to 0xff (not a shared bus)
 	** Set CACHELINE_SIZE.
 	*/
 	dino_cfg_write(dev->bus, dev->devfn,
 		       PCI_CACHE_LINE_SIZE, 2, 0xff00 | L1_CACHE_BYTES/4);
 	/*
 	** Program INT_LINE for card-mode devices.
 	** The cards are hardwired according to this algorithm.
 	** And it doesn't matter if PPB's are present or not since
 	** the IRQ lines bypass the PPB.
 	**
 	** "-1" converts INTA-D (1-4) to PCIINTA-D (0-3) range.
 	** The additional "-1" adjusts for skewing the IRQ<->slot.
 	*/
 	dino_cfg_read(dev->bus, dev->devfn, PCI_INTERRUPT_PIN, 1, &irq_pin);
 	dev->irq = (irq_pin + PCI_SLOT(dev->devfn) - 1) % 4 ;
 	/* Shouldn't really need to do this but it's in case someone tries
 	** to bypass PCI services and look at the card themselves.
 	*/
 	dino_cfg_write(dev->bus, dev->devfn, PCI_INTERRUPT_LINE, 1, dev->irq);
 }
 /* The alignment contraints for PCI bridges under dino */
 #define DINO_BRIDGE_ALIGN 0x100000
 static void __init
 dino_fixup_bus(struct pci_bus *bus)
 {
 	struct list_head *ln;
         struct pci_dev *dev;
         struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge));
 	int port_base = HBA_PORT_BASE(dino_dev->hba.hba_num);
 	DBG(KERN_WARNING "%s(0x%p) bus %d platform_data 0x%p\n",
 	    __FUNCTION__, bus, bus->secondary,
 	    bus->bridge->platform_data);
 	/* Firmware doesn't set up card-mode dino, so we have to */
 	if (is_card_dino(&dino_dev->hba.dev->id)) {
 		dino_card_setup(bus, dino_dev->hba.base_addr);
 	} else if(bus->parent == NULL) {
 		/* must have a dino above it, reparent the resources
 		 * into the dino window */
 		int i;
 		struct resource *res = &dino_dev->hba.lmmio_space;
 		bus->resource[0] = &(dino_dev->hba.io_space);
 		for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) {
 			if(res[i].flags == 0)
 				break;
 			bus->resource[i+1] = &res[i];
 		}
 	} else if(bus->self) {
 		int i;
 		pci_read_bridge_bases(bus);
 		for(i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
 			if((bus->self->resource[i].flags &
 			    (IORESOURCE_IO | IORESOURCE_MEM)) == 0)
 				continue;
 			if(bus->self->resource[i].flags & IORESOURCE_MEM) {
 				/* There's a quirk to alignment of
 				 * bridge memory resources: the start
 				 * is the alignment and start-end is
 				 * the size.  However, firmware will
 				 * have assigned start and end, so we
 				 * need to take this into account */
 				bus->self->resource[i].end = bus->self->resource[i].end - bus->self->resource[i].start + DINO_BRIDGE_ALIGN;
 				bus->self->resource[i].start = DINO_BRIDGE_ALIGN;
 			}
 			DBG("DEBUG %s assigning %d [0x%lx,0x%lx]\n",
 			    bus->self->dev.bus_id, i,
 			    bus->self->resource[i].start,
 			    bus->self->resource[i].end);
 			pci_assign_resource(bus->self, i);
 			DBG("DEBUG %s after assign %d [0x%lx,0x%lx]\n",
 			    bus->self->dev.bus_id, i,
 			    bus->self->resource[i].start,
 			    bus->self->resource[i].end);
 		}
 	}
 	list_for_each(ln, &bus->devices) {
 		int i;
 		dev = pci_dev_b(ln);
 		if (is_card_dino(&dino_dev->hba.dev->id))
 			dino_card_fixup(dev);
 		/*
 		** P2PB's only have 2 BARs, no IRQs.
 		** I'd like to just ignore them for now.
 		*/
 		if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
 			continue;
 		/* Adjust the I/O Port space addresses */
 		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 			struct resource *res = &dev->resource[i];
 			if (res->flags & IORESOURCE_IO) {
 				res->start |= port_base;
 				res->end |= port_base;
 			}
 #ifdef __LP64__
 			/* Sign Extend MMIO addresses */
 			else if (res->flags & IORESOURCE_MEM) {
 				res->start |= F_EXTEND(0UL);
 				res->end   |= F_EXTEND(0UL);
 			}
 #endif
 		}
 		/* null out the ROM resource if there is one (we don't
 		 * care about an expansion rom on parisc, since it
 		 * usually contains (x86) bios code) */
 		dev->resource[PCI_ROM_RESOURCE].flags = 0;
 		if(dev->irq == 255) {
 #define DINO_FIX_UNASSIGNED_INTERRUPTS
 #ifdef DINO_FIX_UNASSIGNED_INTERRUPTS
 			/* This code tries to assign an unassigned
 			 * interrupt.  Leave it disabled unless you
 			 * *really* know what you're doing since the
 			 * pin<->interrupt line mapping varies by bus
 			 * and machine */
 			u32 irq_pin;
 			dino_cfg_read(dev->bus, dev->devfn,
 				      PCI_INTERRUPT_PIN, 1, &irq_pin);
 			irq_pin = (irq_pin + PCI_SLOT(dev->devfn) - 1) % 4 ;
 			printk(KERN_WARNING "Device %s has undefined IRQ, "
 					"setting to %d\n", pci_name(dev), irq_pin);
 			dino_cfg_write(dev->bus, dev->devfn,
 				       PCI_INTERRUPT_LINE, 1, irq_pin);
 			dino_assign_irq(dino_dev, irq_pin, &dev->irq);
 #else
 			dev->irq = 65535;
 			printk(KERN_WARNING "Device %s has unassigned IRQ\n", pci_name(dev));
 #endif
 		} else {
 			/* Adjust INT_LINE for that busses region */
 			dino_assign_irq(dino_dev, dev->irq, &dev->irq);
 		}
 	}
 }
 struct pci_bios_ops dino_bios_ops = {
 	.init		= dino_bios_init,
 	.fixup_bus	= dino_fixup_bus
 };
 /*
  *	Initialise a DINO controller chip
  */
 static void __init
 dino_card_init(struct dino_device *dino_dev)
 {
 	u32 brdg_feat = 0x00784e05;
 	unsigned long status;
 	status = __raw_readl(dino_dev->hba.base_addr+DINO_IO_STATUS);
 	if (status & 0x0000ff80) {
 		__raw_writel(0x00000005,
 				dino_dev->hba.base_addr+DINO_IO_COMMAND);
 		udelay(1);
 	}
 	__raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_GMASK);
 	__raw_writel(0x00000001, dino_dev->hba.base_addr+DINO_IO_FBB_EN);
 	__raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_ICR);
 #if 1
 /* REVISIT - should be a runtime check (eg if (CPU_IS_PCX_L) ...) */
 	/*
 	** PCX-L processors don't support XQL like Dino wants it.
 	** PCX-L2 ignore XQL signal and it doesn't matter.
 	*/
 	brdg_feat &= ~0x4;	/* UXQL */
 #endif
 	__raw_writel( brdg_feat, dino_dev->hba.base_addr+DINO_BRDG_FEAT);
 	/*
 	** Don't enable address decoding until we know which I/O range
 	** currently is available from the host. Only affects MMIO
 	** and not I/O port space.
 	*/
 	__raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_IO_ADDR_EN);
 	__raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_DAMODE);
 	__raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIROR);
 	__raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIWOR);
 	__raw_writel(0x00000040, dino_dev->hba.base_addr+DINO_MLTIM);
 	__raw_writel(0x00000080, dino_dev->hba.base_addr+DINO_IO_CONTROL);
 	__raw_writel(0x0000008c, dino_dev->hba.base_addr+DINO_TLTIM);
 	/* Disable PAMR before writing PAPR */
 	__raw_writel(0x0000007e, dino_dev->hba.base_addr+DINO_PAMR);
 	__raw_writel(0x0000007f, dino_dev->hba.base_addr+DINO_PAPR);
 	__raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_PAMR);
 	/*
 	** Dino ERS encourages enabling FBB (0x6f).
 	** We can't until we know *all* devices below us can support it.
 	** (Something in device configuration header tells us).
 	*/
 	__raw_writel(0x0000004f, dino_dev->hba.base_addr+DINO_PCICMD);
 	/* Somewhere, the PCI spec says give devices 1 second
 	** to recover from the #RESET being de-asserted.
 	** Experience shows most devices only need 10ms.
 	** This short-cut speeds up booting significantly.
 	*/
 	mdelay(pci_post_reset_delay);
 }
 static int __init
 dino_bridge_init(struct dino_device *dino_dev, const char *name)
 {
 	unsigned long io_addr;
 	int result, i, count=0;
 	struct resource *res, *prevres = NULL;
 	/*
 	 * Decoding IO_ADDR_EN only works for Built-in Dino
 	 * since PDC has already initialized this.
 	 */
 	io_addr = __raw_readl(dino_dev->hba.base_addr + DINO_IO_ADDR_EN);
 	if (io_addr == 0) {
 		printk(KERN_WARNING "%s: No PCI devices enabled.\n", name);
 		return -ENODEV;
 	}
 	res = &dino_dev->hba.lmmio_space;
 	for (i = 0; i < 32; i++) {
 		unsigned long start, end;
 		if((io_addr & (1 << i)) == 0)
 			continue;
-		start = (unsigned long)(signed int)(0xf0000000 | (i << 23));
+		start = F_EXTEND(0xf0000000UL) | (i << 23);
 		end = start + 8 * 1024 * 1024 - 1;
 		DBG("DINO RANGE %d is at 0x%lx-0x%lx\n", count,
 		    start, end);
 		if(prevres && prevres->end + 1 == start) {
 			prevres->end = end;
 		} else {
 			if(count >= DINO_MAX_LMMIO_RESOURCES) {
 				printk(KERN_ERR "%s is out of resource windows for range %d (0x%lx-0x%lx)\n", name, count, start, end);
 				break;
 			}
 			prevres = res;
 			res->start = start;
 			res->end = end;
 			res->flags = IORESOURCE_MEM;
 			res->name = kmalloc(64, GFP_KERNEL);
 			if(res->name)
 				snprintf((char *)res->name, 64, "%s LMMIO %d",
 					 name, count);
 			res++;
 			count++;
 		}
 	}
 	res = &dino_dev->hba.lmmio_space;
 	for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) {
 		if(res[i].flags == 0)
 			break;
 		result = ccio_request_resource(dino_dev->hba.dev, &res[i]);
 		if (result < 0) {
 			printk(KERN_ERR "%s: failed to claim PCI Bus address space %d (0x%lx-0x%lx)!\n", name, i, res[i].start, res[i].end);
 			return result;
 		}
 	}
 	return 0;
 }
 static int __init dino_common_init(struct parisc_device *dev,
 		struct dino_device *dino_dev, const char *name)
 {
 	int status;
 	u32 eim;
 	struct gsc_irq gsc_irq;
 	struct resource *res;
 	pcibios_register_hba(&dino_dev->hba);
 	pci_bios = &dino_bios_ops;   /* used by pci_scan_bus() */
 	pci_port = &dino_port_ops;
 	/*
 	** Note: SMP systems can make use of IRR1/IAR1 registers
 	**   But it won't buy much performance except in very
 	**   specific applications/configurations. Note Dino
 	**   still only has 11 IRQ input lines - just map some of them
 	**   to a different processor.
 	*/
 	dev->irq = gsc_alloc_irq(&gsc_irq);
 	dino_dev->txn_addr = gsc_irq.txn_addr;
 	dino_dev->txn_data = gsc_irq.txn_data;
 	eim = ((u32) gsc_irq.txn_addr) | gsc_irq.txn_data;
 	/*
 	** Dino needs a PA "IRQ" to get a processor's attention.
 	** arch/parisc/kernel/irq.c returns an EIRR bit.
 	*/
 	if (dev->irq < 0) {
 		printk(KERN_WARNING "%s: gsc_alloc_irq() failed\n", name);
 		return 1;
 	}
 	status = request_irq(dev->irq, dino_isr, 0, name, dino_dev);
 	if (status) {
 		printk(KERN_WARNING "%s: request_irq() failed with %d\n",
 			name, status);
 		return 1;
 	}
 	/* Support the serial port which is sometimes attached on built-in
 	 * Dino / Cujo chips.
 	 */
 	gsc_fixup_irqs(dev, dino_dev, dino_choose_irq);
 	/*
 	** This enables DINO to generate interrupts when it sees
 	** any of its inputs *change*. Just asserting an IRQ
 	** before it's enabled (ie unmasked) isn't good enough.
 	*/
 	__raw_writel(eim, dino_dev->hba.base_addr+DINO_IAR0);
 	/*
 	** Some platforms don't clear Dino's IRR0 register at boot time.
 	** Reading will clear it now.
 	*/
 	__raw_readl(dino_dev->hba.base_addr+DINO_IRR0);
 	/* allocate I/O Port resource region */
 	res = &dino_dev->hba.io_space;
 	if (!is_cujo(&dev->id)) {
 		res->name = "Dino I/O Port";
 	} else {
 		res->name = "Cujo I/O Port";
 	}
 	res->start = HBA_PORT_BASE(dino_dev->hba.hba_num);
 	res->end = res->start + (HBA_PORT_SPACE_SIZE - 1);
 	res->flags = IORESOURCE_IO; /* do not mark it busy ! */
 	if (request_resource(&ioport_resource, res) < 0) {
 		printk(KERN_ERR "%s: request I/O Port region failed "
 		       "0x%lx/%lx (hpa 0x%p)\n",
 		       name, res->start, res->end, dino_dev->hba.base_addr);
 		return 1;
 	}
 	return 0;
 }
 #define CUJO_RAVEN_ADDR		F_EXTEND(0xf1000000UL)
 #define CUJO_FIREHAWK_ADDR	F_EXTEND(0xf1604000UL)
 #define CUJO_RAVEN_BADPAGE	0x01003000UL
 #define CUJO_FIREHAWK_BADPAGE	0x01607000UL
 static const char *dino_vers[] = {
 	"2.0",
 	"2.1",
 	"3.0",
 	"3.1"
 };
 static const char *cujo_vers[] = {
 	"1.0",
 	"2.0"
 };
 void ccio_cujo20_fixup(struct parisc_device *dev, u32 iovp);
 /*
 ** Determine if dino should claim this chip (return 0) or not (return 1).
 ** If so, initialize the chip appropriately (card-mode vs bridge mode).
 ** Much of the initialization is common though.
 */
 static int __init dino_probe(struct parisc_device *dev)
 {
 	struct dino_device *dino_dev;	// Dino specific control struct
 	const char *version = "unknown";
 	char *name;
 	int is_cujo = 0;
 	struct pci_bus *bus;
 	unsigned long hpa = dev->hpa.start;
 	name = "Dino";
 	if (is_card_dino(&dev->id)) {
 		version = "3.x (card mode)";
 	} else {
 		if (!is_cujo(&dev->id)) {
 			if (dev->id.hversion_rev < 4) {
 				version = dino_vers[dev->id.hversion_rev];
 			}
 		} else {
 			name = "Cujo";
 			is_cujo = 1;
 			if (dev->id.hversion_rev < 2) {
 				version = cujo_vers[dev->id.hversion_rev];
 			}
 		}
 	}
 	printk("%s version %s found at 0x%lx\n", name, version, hpa);
 	if (!request_mem_region(hpa, PAGE_SIZE, name)) {
 		printk(KERN_ERR "DINO: Hey! Someone took my MMIO space (0x%ld)!\n",
 			hpa);
 		return 1;
 	}
 	/* Check for bugs */
 	if (is_cujo && dev->id.hversion_rev == 1) {
 #ifdef CONFIG_IOMMU_CCIO
 		printk(KERN_WARNING "Enabling Cujo 2.0 bug workaround\n");
 		if (hpa == (unsigned long)CUJO_RAVEN_ADDR) {
 			ccio_cujo20_fixup(dev, CUJO_RAVEN_BADPAGE);
 		} else if (hpa == (unsigned long)CUJO_FIREHAWK_ADDR) {
 			ccio_cujo20_fixup(dev, CUJO_FIREHAWK_BADPAGE);
 		} else {
 			printk("Don't recognise Cujo at address 0x%lx, not enabling workaround\n", hpa);
 		}
 #endif
 	} else if (!is_cujo && !is_card_dino(&dev->id) &&
 			dev->id.hversion_rev < 3) {
 		printk(KERN_WARNING
 "The GSCtoPCI (Dino hrev %d) bus converter found may exhibit\n"
 "data corruption.  See Service Note Numbers: A4190A-01, A4191A-01.\n"
 "Systems shipped after Aug 20, 1997 will not exhibit this problem.\n"
 "Models affected: C180, C160, C160L, B160L, and B132L workstations.\n\n",
 			dev->id.hversion_rev);
 /* REVISIT: why are C200/C240 listed in the README table but not
 **   "Models affected"? Could be an omission in the original literature.
 */
 	}
 	dino_dev = kzalloc(sizeof(struct dino_device), GFP_KERNEL);
 	if (!dino_dev) {
 		printk("dino_init_chip - couldn't alloc dino_device\n");
 		return 1;
 	}
 	dino_dev->hba.dev = dev;
-	dino_dev->hba.base_addr = ioremap(hpa, 4096);
+	dino_dev->hba.base_addr = ioremap_nocache(hpa, 4096);
 	dino_dev->hba.lmmio_space_offset = 0;	/* CPU addrs == bus addrs */
 	spin_lock_init(&dino_dev->dinosaur_pen);
 	dino_dev->hba.iommu = ccio_get_iommu(dev);
 	if (is_card_dino(&dev->id)) {
 		dino_card_init(dino_dev);
 	} else {
 		dino_bridge_init(dino_dev, name);
 	}
 	if (dino_common_init(dev, dino_dev, name))
 		return 1;
 	dev->dev.platform_data = dino_dev;
 	/*
 	** It's not used to avoid chicken/egg problems
 	** with configuration accessor functions.
 	*/
 	bus = pci_scan_bus_parented(&dev->dev, dino_current_bus,
 				    &dino_cfg_ops, NULL);
 	if(bus) {
 		pci_bus_add_devices(bus);
 		/* This code *depends* on scanning being single threaded
 		 * if it isn't, this global bus number count will fail
 		 */
 		dino_current_bus = bus->subordinate + 1;
 		pci_bus_assign_resources(bus);
 	} else {
 		printk(KERN_ERR "ERROR: failed to scan PCI bus on %s (probably duplicate bus number %d)\n", dev->dev.bus_id, dino_current_bus);
 		/* increment the bus number in case of duplicates */
 		dino_current_bus++;
 	}
 	dino_dev->hba.hba_bus = bus;
 	return 0;
 }
 /*
  * Normally, we would just test sversion.  But the Elroy PCI adapter has
  * the same sversion as Dino, so we have to check hversion as well.
  * Unfortunately, the J2240 PDC reports the wrong hversion for the first
  * Dino, so we have to test for Dino, Cujo and Dino-in-a-J2240.
  * For card-mode Dino, most machines report an sversion of 9D.  But 715
  * and 725 firmware misreport it as 0x08080 for no adequately explained
  * reason.
  */
 static struct parisc_device_id dino_tbl[] = {
 	{ HPHW_A_DMA, HVERSION_REV_ANY_ID, 0x004, 0x0009D },/* Card-mode Dino */
 	{ HPHW_A_DMA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x08080 }, /* XXX */
 	{ HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x680, 0xa }, /* Bridge-mode Dino */
 	{ HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x682, 0xa }, /* Bridge-mode Cujo */
 	{ HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x05d, 0xa }, /* Dino in a J2240 */
 	{ 0, }
 };
 static struct parisc_driver dino_driver = {
 	.name =		"dino",
 	.id_table =	dino_tbl,
 	.probe =	dino_probe,
 };
 /*
  * One time initialization to let the world know Dino is here.
  * This is the only routine which is NOT static.
  * Must be called exactly once before pci_init().
  */
 int __init dino_init(void)
 {
 	register_parisc_driver(&dino_driver);
 	return 0;
 }

drivers/parisc/eisa.c

Diff comments View file @ 5076c15

1	/*	1	/*
2	* eisa.c - provide support for EISA adapters in PA-RISC machines	2	* eisa.c - provide support for EISA adapters in PA-RISC machines
3	*	3	*
4	* This program is free software; you can redistribute it and/or	4	* This program is free software; you can redistribute it and/or
5	* modify it under the terms of the GNU General Public License	5	* modify it under the terms of the GNU General Public License
6	* as published by the Free Software Foundation; either version	6	* as published by the Free Software Foundation; either version
7	* 2 of the License, or (at your option) any later version.	7	* 2 of the License, or (at your option) any later version.
8	*	8	*
9	* Copyright (c) 2001 Matthew Wilcox for Hewlett Packard	9	* Copyright (c) 2001 Matthew Wilcox for Hewlett Packard
10	* Copyright (c) 2001 Daniel Engstrom <5116@telia.com>	10	* Copyright (c) 2001 Daniel Engstrom <5116@telia.com>
11	*	11	*
12	* There are two distinct EISA adapters. Mongoose is found in machines	12	* There are two distinct EISA adapters. Mongoose is found in machines
13	* before the 712; then the Wax ASIC is used. To complicate matters, the	13	* before the 712; then the Wax ASIC is used. To complicate matters, the
14	* Wax ASIC also includes a PS/2 and RS-232 controller, but those are	14	* Wax ASIC also includes a PS/2 and RS-232 controller, but those are
15	* dealt with elsewhere; this file is concerned only with the EISA portions	15	* dealt with elsewhere; this file is concerned only with the EISA portions
16	* of Wax.	16	* of Wax.
17	*	17	*
18	*	18	*
19	* HINT:	19	* HINT:
20	* -----	20	* -----
21	* To allow an ISA card to work properly in the EISA slot you need to	21	* To allow an ISA card to work properly in the EISA slot you need to
22	* set an edge trigger level. This may be done on the palo command line	22	* set an edge trigger level. This may be done on the palo command line
23	* by adding the kernel parameter "eisa_irq_edge=n,n2,[...]]", with	23	* by adding the kernel parameter "eisa_irq_edge=n,n2,[...]]", with
24	* n and n2 as the irq levels you want to use.	24	* n and n2 as the irq levels you want to use.
25	*	25	*
26	* Example: "eisa_irq_edge=10,11" allows ISA cards to operate at	26	* Example: "eisa_irq_edge=10,11" allows ISA cards to operate at
27	* irq levels 10 and 11.	27	* irq levels 10 and 11.
28	*/	28	*/
29		29
30	#include <linux/init.h>	30	#include <linux/init.h>
31	#include <linux/ioport.h>	31	#include <linux/ioport.h>
32	#include <linux/interrupt.h>	32	#include <linux/interrupt.h>
33	#include <linux/kernel.h>	33	#include <linux/kernel.h>
34	#include <linux/module.h>	34	#include <linux/module.h>
35	#include <linux/pci.h>	35	#include <linux/pci.h>
36	#include <linux/sched.h>	36	#include <linux/sched.h>
37	#include <linux/spinlock.h>	37	#include <linux/spinlock.h>
38	#include <linux/eisa.h>	38	#include <linux/eisa.h>
39		39
40	#include <asm/byteorder.h>	40	#include <asm/byteorder.h>
41	#include <asm/io.h>	41	#include <asm/io.h>
42	#include <asm/hardware.h>	42	#include <asm/hardware.h>
43	#include <asm/processor.h>	43	#include <asm/processor.h>
44	#include <asm/parisc-device.h>	44	#include <asm/parisc-device.h>
45	#include <asm/delay.h>	45	#include <asm/delay.h>
46	#include <asm/eisa_bus.h>	46	#include <asm/eisa_bus.h>
47	#include <asm/eisa_eeprom.h>	47	#include <asm/eisa_eeprom.h>
48		48
49	#if 0	49	#if 0
50	#define EISA_DBG(msg, arg... ) printk(KERN_DEBUG "eisa: " msg , ## arg )	50	#define EISA_DBG(msg, arg... ) printk(KERN_DEBUG "eisa: " msg , ## arg )
51	#else	51	#else
52	#define EISA_DBG(msg, arg... )	52	#define EISA_DBG(msg, arg... )
53	#endif	53	#endif
54		54
55	#define SNAKES_EEPROM_BASE_ADDR 0xF0810400	55	#define SNAKES_EEPROM_BASE_ADDR 0xF0810400
56	#define MIRAGE_EEPROM_BASE_ADDR 0xF00C0400	56	#define MIRAGE_EEPROM_BASE_ADDR 0xF00C0400
57		57
58	static DEFINE_SPINLOCK(eisa_irq_lock);	58	static DEFINE_SPINLOCK(eisa_irq_lock);
59		59
60	void __iomem *eisa_eeprom_addr __read_mostly;	60	void __iomem *eisa_eeprom_addr __read_mostly;
61		61
62	/* We can only have one EISA adapter in the system because neither	62	/* We can only have one EISA adapter in the system because neither
63	* implementation can be flexed.	63	* implementation can be flexed.
64	*/	64	*/
65	static struct eisa_ba {	65	static struct eisa_ba {
66	struct pci_hba_data hba;	66	struct pci_hba_data hba;
67	unsigned long eeprom_addr;	67	unsigned long eeprom_addr;
68	struct eisa_root_device root;	68	struct eisa_root_device root;
69	} eisa_dev;	69	} eisa_dev;
70		70
71	/* Port ops */	71	/* Port ops */
72		72
73	static inline unsigned long eisa_permute(unsigned short port)	73	static inline unsigned long eisa_permute(unsigned short port)
74	{	74	{
75	if (port & 0x300) {	75	if (port & 0x300) {
76	return 0xfc000000 \| ((port & 0xfc00) >> 6)	76	return 0xfc000000 \| ((port & 0xfc00) >> 6)
77	\| ((port & 0x3f8) << 9) \| (port & 7);	77	\| ((port & 0x3f8) << 9) \| (port & 7);
78	} else {	78	} else {
79	return 0xfc000000 \| port;	79	return 0xfc000000 \| port;
80	}	80	}
81	}	81	}
82		82
83	unsigned char eisa_in8(unsigned short port)	83	unsigned char eisa_in8(unsigned short port)
84	{	84	{
85	if (EISA_bus)	85	if (EISA_bus)
86	return gsc_readb(eisa_permute(port));	86	return gsc_readb(eisa_permute(port));
87	return 0xff;	87	return 0xff;
88	}	88	}
89		89
90	unsigned short eisa_in16(unsigned short port)	90	unsigned short eisa_in16(unsigned short port)
91	{	91	{
92	if (EISA_bus)	92	if (EISA_bus)
93	return le16_to_cpu(gsc_readw(eisa_permute(port)));	93	return le16_to_cpu(gsc_readw(eisa_permute(port)));
94	return 0xffff;	94	return 0xffff;
95	}	95	}
96		96
97	unsigned int eisa_in32(unsigned short port)	97	unsigned int eisa_in32(unsigned short port)
98	{	98	{
99	if (EISA_bus)	99	if (EISA_bus)
100	return le32_to_cpu(gsc_readl(eisa_permute(port)));	100	return le32_to_cpu(gsc_readl(eisa_permute(port)));
101	return 0xffffffff;	101	return 0xffffffff;
102	}	102	}
103		103
104	void eisa_out8(unsigned char data, unsigned short port)	104	void eisa_out8(unsigned char data, unsigned short port)
105	{	105	{
106	if (EISA_bus)	106	if (EISA_bus)
107	gsc_writeb(data, eisa_permute(port));	107	gsc_writeb(data, eisa_permute(port));
108	}	108	}
109		109
110	void eisa_out16(unsigned short data, unsigned short port)	110	void eisa_out16(unsigned short data, unsigned short port)
111	{	111	{
112	if (EISA_bus)	112	if (EISA_bus)
113	gsc_writew(cpu_to_le16(data), eisa_permute(port));	113	gsc_writew(cpu_to_le16(data), eisa_permute(port));
114	}	114	}
115		115
116	void eisa_out32(unsigned int data, unsigned short port)	116	void eisa_out32(unsigned int data, unsigned short port)
117	{	117	{
118	if (EISA_bus)	118	if (EISA_bus)
119	gsc_writel(cpu_to_le32(data), eisa_permute(port));	119	gsc_writel(cpu_to_le32(data), eisa_permute(port));
120	}	120	}
121		121
122	#ifndef CONFIG_PCI	122	#ifndef CONFIG_PCI
123	/* We call these directly without PCI. See asm/io.h. */	123	/* We call these directly without PCI. See asm/io.h. */
124	EXPORT_SYMBOL(eisa_in8);	124	EXPORT_SYMBOL(eisa_in8);
125	EXPORT_SYMBOL(eisa_in16);	125	EXPORT_SYMBOL(eisa_in16);
126	EXPORT_SYMBOL(eisa_in32);	126	EXPORT_SYMBOL(eisa_in32);
127	EXPORT_SYMBOL(eisa_out8);	127	EXPORT_SYMBOL(eisa_out8);
128	EXPORT_SYMBOL(eisa_out16);	128	EXPORT_SYMBOL(eisa_out16);
129	EXPORT_SYMBOL(eisa_out32);	129	EXPORT_SYMBOL(eisa_out32);
130	#endif	130	#endif
131		131
132	/* Interrupt handling */	132	/* Interrupt handling */
133		133
134	/* cached interrupt mask registers */	134	/* cached interrupt mask registers */
135	static int master_mask;	135	static int master_mask;
136	static int slave_mask;	136	static int slave_mask;
137		137
138	/* the trig level can be set with the	138	/* the trig level can be set with the
139	* eisa_irq_edge=n,n,n commandline parameter	139	* eisa_irq_edge=n,n,n commandline parameter
140	* We should really read this from the EEPROM	140	* We should really read this from the EEPROM
141	* in the furure.	141	* in the furure.
142	*/	142	*/
143	/* irq 13,8,2,1,0 must be edge */	143	/* irq 13,8,2,1,0 must be edge */
144	static unsigned int eisa_irq_level __read_mostly; /* default to edge triggered */	144	static unsigned int eisa_irq_level __read_mostly; /* default to edge triggered */
145		145
146		146
147	/* called by free irq */	147	/* called by free irq */
148	static void eisa_disable_irq(unsigned int irq)	148	static void eisa_disable_irq(unsigned int irq)
149	{	149	{
150	unsigned long flags;	150	unsigned long flags;
151		151
152	EISA_DBG("disable irq %d\n", irq);	152	EISA_DBG("disable irq %d\n", irq);
153	/* just mask for now */	153	/* just mask for now */
154	spin_lock_irqsave(&eisa_irq_lock, flags);	154	spin_lock_irqsave(&eisa_irq_lock, flags);
155	if (irq & 8) {	155	if (irq & 8) {
156	slave_mask \|= (1 << (irq&7));	156	slave_mask \|= (1 << (irq&7));
157	eisa_out8(slave_mask, 0xa1);	157	eisa_out8(slave_mask, 0xa1);
158	} else {	158	} else {
159	master_mask \|= (1 << (irq&7));	159	master_mask \|= (1 << (irq&7));
160	eisa_out8(master_mask, 0x21);	160	eisa_out8(master_mask, 0x21);
161	}	161	}
162	spin_unlock_irqrestore(&eisa_irq_lock, flags);	162	spin_unlock_irqrestore(&eisa_irq_lock, flags);
163	EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));	163	EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
164	EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));	164	EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
165	}	165	}
166		166
167	/* called by request irq */	167	/* called by request irq */
168	static void eisa_enable_irq(unsigned int irq)	168	static void eisa_enable_irq(unsigned int irq)
169	{	169	{
170	unsigned long flags;	170	unsigned long flags;
171	EISA_DBG("enable irq %d\n", irq);	171	EISA_DBG("enable irq %d\n", irq);
172		172
173	spin_lock_irqsave(&eisa_irq_lock, flags);	173	spin_lock_irqsave(&eisa_irq_lock, flags);
174	if (irq & 8) {	174	if (irq & 8) {
175	slave_mask &= ~(1 << (irq&7));	175	slave_mask &= ~(1 << (irq&7));
176	eisa_out8(slave_mask, 0xa1);	176	eisa_out8(slave_mask, 0xa1);
177	} else {	177	} else {
178	master_mask &= ~(1 << (irq&7));	178	master_mask &= ~(1 << (irq&7));
179	eisa_out8(master_mask, 0x21);	179	eisa_out8(master_mask, 0x21);
180	}	180	}
181	spin_unlock_irqrestore(&eisa_irq_lock, flags);	181	spin_unlock_irqrestore(&eisa_irq_lock, flags);
182	EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));	182	EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
183	EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));	183	EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
184	}	184	}
185		185
186	static unsigned int eisa_startup_irq(unsigned int irq)	186	static unsigned int eisa_startup_irq(unsigned int irq)
187	{	187	{
188	eisa_enable_irq(irq);	188	eisa_enable_irq(irq);
189	return 0;	189	return 0;
190	}	190	}
191		191
192	static struct hw_interrupt_type eisa_interrupt_type = {	192	static struct hw_interrupt_type eisa_interrupt_type = {
193	.typename = "EISA",	193	.typename = "EISA",
194	.startup = eisa_startup_irq,	194	.startup = eisa_startup_irq,
195	.shutdown = eisa_disable_irq,	195	.shutdown = eisa_disable_irq,
196	.enable = eisa_enable_irq,	196	.enable = eisa_enable_irq,
197	.disable = eisa_disable_irq,	197	.disable = eisa_disable_irq,
198	.ack = no_ack_irq,	198	.ack = no_ack_irq,
199	.end = no_end_irq,	199	.end = no_end_irq,
200	};	200	};
201		201
202	static irqreturn_t eisa_irq(int wax_irq, void intr_dev, struct pt_regs regs)	202	static irqreturn_t eisa_irq(int wax_irq, void intr_dev, struct pt_regs regs)
203	{	203	{
204	int irq = gsc_readb(0xfc01f000); /* EISA supports 16 irqs */	204	int irq = gsc_readb(0xfc01f000); /* EISA supports 16 irqs */
205	unsigned long flags;	205	unsigned long flags;
206		206
207	spin_lock_irqsave(&eisa_irq_lock, flags);	207	spin_lock_irqsave(&eisa_irq_lock, flags);
208	/* read IRR command */	208	/* read IRR command */
209	eisa_out8(0x0a, 0x20);	209	eisa_out8(0x0a, 0x20);
210	eisa_out8(0x0a, 0xa0);	210	eisa_out8(0x0a, 0xa0);
211		211
212	EISA_DBG("irq IAR %02x 8259-1 irr %02x 8259-2 irr %02x\n",	212	EISA_DBG("irq IAR %02x 8259-1 irr %02x 8259-2 irr %02x\n",
213	irq, eisa_in8(0x20), eisa_in8(0xa0));	213	irq, eisa_in8(0x20), eisa_in8(0xa0));
214		214
215	/* read ISR command */	215	/* read ISR command */
216	eisa_out8(0x0a, 0x20);	216	eisa_out8(0x0a, 0x20);
217	eisa_out8(0x0a, 0xa0);	217	eisa_out8(0x0a, 0xa0);
218	EISA_DBG("irq 8259-1 isr %02x imr %02x 8259-2 isr %02x imr %02x\n",	218	EISA_DBG("irq 8259-1 isr %02x imr %02x 8259-2 isr %02x imr %02x\n",
219	eisa_in8(0x20), eisa_in8(0x21), eisa_in8(0xa0), eisa_in8(0xa1));	219	eisa_in8(0x20), eisa_in8(0x21), eisa_in8(0xa0), eisa_in8(0xa1));
220		220
221	irq &= 0xf;	221	irq &= 0xf;
222		222
223	/* mask irq and write eoi */	223	/* mask irq and write eoi */
224	if (irq & 8) {	224	if (irq & 8) {
225	slave_mask \|= (1 << (irq&7));	225	slave_mask \|= (1 << (irq&7));
226	eisa_out8(slave_mask, 0xa1);	226	eisa_out8(slave_mask, 0xa1);
227	eisa_out8(0x60 \| (irq&7),0xa0);/* 'Specific EOI' to slave */	227	eisa_out8(0x60 \| (irq&7),0xa0);/* 'Specific EOI' to slave */
228	eisa_out8(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */	228	eisa_out8(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */
229		229
230	} else {	230	} else {
231	master_mask \|= (1 << (irq&7));	231	master_mask \|= (1 << (irq&7));
232	eisa_out8(master_mask, 0x21);	232	eisa_out8(master_mask, 0x21);
233	eisa_out8(0x60\|irq,0x20); /* 'Specific EOI' to master */	233	eisa_out8(0x60\|irq,0x20); /* 'Specific EOI' to master */
234	}	234	}
235	spin_unlock_irqrestore(&eisa_irq_lock, flags);	235	spin_unlock_irqrestore(&eisa_irq_lock, flags);
236		236
237	__do_IRQ(irq, regs);	237	__do_IRQ(irq, regs);
238		238
239	spin_lock_irqsave(&eisa_irq_lock, flags);	239	spin_lock_irqsave(&eisa_irq_lock, flags);
240	/* unmask */	240	/* unmask */
241	if (irq & 8) {	241	if (irq & 8) {
242	slave_mask &= ~(1 << (irq&7));	242	slave_mask &= ~(1 << (irq&7));
243	eisa_out8(slave_mask, 0xa1);	243	eisa_out8(slave_mask, 0xa1);
244	} else {	244	} else {
245	master_mask &= ~(1 << (irq&7));	245	master_mask &= ~(1 << (irq&7));
246	eisa_out8(master_mask, 0x21);	246	eisa_out8(master_mask, 0x21);
247	}	247	}
248	spin_unlock_irqrestore(&eisa_irq_lock, flags);	248	spin_unlock_irqrestore(&eisa_irq_lock, flags);
249	return IRQ_HANDLED;	249	return IRQ_HANDLED;
250	}	250	}
251		251
252	static irqreturn_t dummy_irq2_handler(int _, void dev, struct pt_regs regs)	252	static irqreturn_t dummy_irq2_handler(int _, void dev, struct pt_regs regs)
253	{	253	{
254	printk(KERN_ALERT "eisa: uhh, irq2?\n");	254	printk(KERN_ALERT "eisa: uhh, irq2?\n");
255	return IRQ_HANDLED;	255	return IRQ_HANDLED;
256	}	256	}
257		257
258	static struct irqaction irq2_action = {	258	static struct irqaction irq2_action = {
259	.handler = dummy_irq2_handler,	259	.handler = dummy_irq2_handler,
260	.name = "cascade",	260	.name = "cascade",
261	};	261	};
262		262
263	static void init_eisa_pic(void)	263	static void init_eisa_pic(void)
264	{	264	{
265	unsigned long flags;	265	unsigned long flags;
266		266
267	spin_lock_irqsave(&eisa_irq_lock, flags);	267	spin_lock_irqsave(&eisa_irq_lock, flags);
268		268
269	eisa_out8(0xff, 0x21); /* mask during init */	269	eisa_out8(0xff, 0x21); /* mask during init */
270	eisa_out8(0xff, 0xa1); /* mask during init */	270	eisa_out8(0xff, 0xa1); /* mask during init */
271		271
272	/* master pic */	272	/* master pic */
273	eisa_out8(0x11,0x20); /* ICW1 */	273	eisa_out8(0x11,0x20); /* ICW1 */
274	eisa_out8(0x00,0x21); /* ICW2 */	274	eisa_out8(0x00,0x21); /* ICW2 */
275	eisa_out8(0x04,0x21); /* ICW3 */	275	eisa_out8(0x04,0x21); /* ICW3 */
276	eisa_out8(0x01,0x21); /* ICW4 */	276	eisa_out8(0x01,0x21); /* ICW4 */
277	eisa_out8(0x40,0x20); /* OCW2 */	277	eisa_out8(0x40,0x20); /* OCW2 */
278		278
279	/* slave pic */	279	/* slave pic */
280	eisa_out8(0x11,0xa0); /* ICW1 */	280	eisa_out8(0x11,0xa0); /* ICW1 */
281	eisa_out8(0x08,0xa1); /* ICW2 */	281	eisa_out8(0x08,0xa1); /* ICW2 */
282	eisa_out8(0x02,0xa1); /* ICW3 */	282	eisa_out8(0x02,0xa1); /* ICW3 */
283	eisa_out8(0x01,0xa1); /* ICW4 */	283	eisa_out8(0x01,0xa1); /* ICW4 */
284	eisa_out8(0x40,0xa0); /* OCW2 */	284	eisa_out8(0x40,0xa0); /* OCW2 */
285		285
286	udelay(100);	286	udelay(100);
287		287
288	slave_mask = 0xff;	288	slave_mask = 0xff;
289	master_mask = 0xfb;	289	master_mask = 0xfb;
290	eisa_out8(slave_mask, 0xa1); /* OCW1 */	290	eisa_out8(slave_mask, 0xa1); /* OCW1 */
291	eisa_out8(master_mask, 0x21); /* OCW1 */	291	eisa_out8(master_mask, 0x21); /* OCW1 */
292		292
293	/* setup trig level */	293	/* setup trig level */
294	EISA_DBG("EISA edge/level %04x\n", eisa_irq_level);	294	EISA_DBG("EISA edge/level %04x\n", eisa_irq_level);
295		295
296	eisa_out8(eisa_irq_level&0xff, 0x4d0); /* Set all irq's to edge */	296	eisa_out8(eisa_irq_level&0xff, 0x4d0); /* Set all irq's to edge */
297	eisa_out8((eisa_irq_level >> 8) & 0xff, 0x4d1);	297	eisa_out8((eisa_irq_level >> 8) & 0xff, 0x4d1);
298		298
299	EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));	299	EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
300	EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));	300	EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
301	EISA_DBG("pic0 edge/level %02x\n", eisa_in8(0x4d0));	301	EISA_DBG("pic0 edge/level %02x\n", eisa_in8(0x4d0));
302	EISA_DBG("pic1 edge/level %02x\n", eisa_in8(0x4d1));	302	EISA_DBG("pic1 edge/level %02x\n", eisa_in8(0x4d1));
303		303
304	spin_unlock_irqrestore(&eisa_irq_lock, flags);	304	spin_unlock_irqrestore(&eisa_irq_lock, flags);
305	}	305	}
306		306
307	/* Device initialisation */	307	/* Device initialisation */
308		308
309	#define is_mongoose(dev) (dev->id.sversion == 0x00076)	309	#define is_mongoose(dev) (dev->id.sversion == 0x00076)
310		310
311	static int __devinit eisa_probe(struct parisc_device *dev)	311	static int __devinit eisa_probe(struct parisc_device *dev)
312	{	312	{
313	int i, result;	313	int i, result;
314		314
315	char *name = is_mongoose(dev) ? "Mongoose" : "Wax";	315	char *name = is_mongoose(dev) ? "Mongoose" : "Wax";
316		316
317	printk(KERN_INFO "%s EISA Adapter found at 0x%08lx\n",	317	printk(KERN_INFO "%s EISA Adapter found at 0x%08lx\n",
318	name, dev->hpa.start);	318	name, dev->hpa.start);
319		319
320	eisa_dev.hba.dev = dev;	320	eisa_dev.hba.dev = dev;
321	eisa_dev.hba.iommu = ccio_get_iommu(dev);	321	eisa_dev.hba.iommu = ccio_get_iommu(dev);
322		322
323	eisa_dev.hba.lmmio_space.name = "EISA";	323	eisa_dev.hba.lmmio_space.name = "EISA";
324	eisa_dev.hba.lmmio_space.start = F_EXTEND(0xfc000000);	324	eisa_dev.hba.lmmio_space.start = F_EXTEND(0xfc000000);
325	eisa_dev.hba.lmmio_space.end = F_EXTEND(0xffbfffff);	325	eisa_dev.hba.lmmio_space.end = F_EXTEND(0xffbfffff);
326	eisa_dev.hba.lmmio_space.flags = IORESOURCE_MEM;	326	eisa_dev.hba.lmmio_space.flags = IORESOURCE_MEM;
327	result = ccio_request_resource(dev, &eisa_dev.hba.lmmio_space);	327	result = ccio_request_resource(dev, &eisa_dev.hba.lmmio_space);
328	if (result < 0) {	328	if (result < 0) {
329	printk(KERN_ERR "EISA: failed to claim EISA Bus address space!\n");	329	printk(KERN_ERR "EISA: failed to claim EISA Bus address space!\n");
330	return result;	330	return result;
331	}	331	}
332	eisa_dev.hba.io_space.name = "EISA";	332	eisa_dev.hba.io_space.name = "EISA";
333	eisa_dev.hba.io_space.start = 0;	333	eisa_dev.hba.io_space.start = 0;
334	eisa_dev.hba.io_space.end = 0xffff;	334	eisa_dev.hba.io_space.end = 0xffff;
335	eisa_dev.hba.lmmio_space.flags = IORESOURCE_IO;	335	eisa_dev.hba.lmmio_space.flags = IORESOURCE_IO;
336	result = request_resource(&ioport_resource, &eisa_dev.hba.io_space);	336	result = request_resource(&ioport_resource, &eisa_dev.hba.io_space);
337	if (result < 0) {	337	if (result < 0) {
338	printk(KERN_ERR "EISA: failed to claim EISA Bus port space!\n");	338	printk(KERN_ERR "EISA: failed to claim EISA Bus port space!\n");
339	return result;	339	return result;
340	}	340	}
341	pcibios_register_hba(&eisa_dev.hba);	341	pcibios_register_hba(&eisa_dev.hba);
342		342
343	result = request_irq(dev->irq, eisa_irq, SA_SHIRQ, "EISA", &eisa_dev);	343	result = request_irq(dev->irq, eisa_irq, SA_SHIRQ, "EISA", &eisa_dev);
344	if (result) {	344	if (result) {
345	printk(KERN_ERR "EISA: request_irq failed!\n");	345	printk(KERN_ERR "EISA: request_irq failed!\n");
346	return result;	346	return result;
347	}	347	}
348		348
349	/* Reserve IRQ2 */	349	/* Reserve IRQ2 */
350	irq_desc[2].action = &irq2_action;	350	irq_desc[2].action = &irq2_action;
351		351
352	for (i = 0; i < 16; i++) {	352	for (i = 0; i < 16; i++) {
353	irq_desc[i].handler = &eisa_interrupt_type;	353	irq_desc[i].handler = &eisa_interrupt_type;
354	}	354	}
355		355
356	EISA_bus = 1;	356	EISA_bus = 1;
357		357
358	if (dev->num_addrs) {	358	if (dev->num_addrs) {
359	/* newer firmware hand out the eeprom address */	359	/* newer firmware hand out the eeprom address */
360	eisa_dev.eeprom_addr = dev->addr[0];	360	eisa_dev.eeprom_addr = dev->addr[0];
361	} else {	361	} else {
362	/* old firmware, need to figure out the box */	362	/* old firmware, need to figure out the box */
363	if (is_mongoose(dev)) {	363	if (is_mongoose(dev)) {
364	eisa_dev.eeprom_addr = SNAKES_EEPROM_BASE_ADDR;	364	eisa_dev.eeprom_addr = SNAKES_EEPROM_BASE_ADDR;
365	} else {	365	} else {
366	eisa_dev.eeprom_addr = MIRAGE_EEPROM_BASE_ADDR;	366	eisa_dev.eeprom_addr = MIRAGE_EEPROM_BASE_ADDR;
367	}	367	}
368	}	368	}
369	eisa_eeprom_addr = ioremap(eisa_dev.eeprom_addr, HPEE_MAX_LENGTH);	369	eisa_eeprom_addr = ioremap_nocache(eisa_dev.eeprom_addr, HPEE_MAX_LENGTH);
370	result = eisa_enumerator(eisa_dev.eeprom_addr, &eisa_dev.hba.io_space,	370	result = eisa_enumerator(eisa_dev.eeprom_addr, &eisa_dev.hba.io_space,
371	&eisa_dev.hba.lmmio_space);	371	&eisa_dev.hba.lmmio_space);
372	init_eisa_pic();	372	init_eisa_pic();
373		373
374	if (result >= 0) {	374	if (result >= 0) {
375	/* FIXME : Don't enumerate the bus twice. */	375	/* FIXME : Don't enumerate the bus twice. */
376	eisa_dev.root.dev = &dev->dev;	376	eisa_dev.root.dev = &dev->dev;
377	dev->dev.driver_data = &eisa_dev.root;	377	dev->dev.driver_data = &eisa_dev.root;
378	eisa_dev.root.bus_base_addr = 0;	378	eisa_dev.root.bus_base_addr = 0;
379	eisa_dev.root.res = &eisa_dev.hba.io_space;	379	eisa_dev.root.res = &eisa_dev.hba.io_space;
380	eisa_dev.root.slots = result;	380	eisa_dev.root.slots = result;
381	eisa_dev.root.dma_mask = 0xffffffff; /* wild guess */	381	eisa_dev.root.dma_mask = 0xffffffff; /* wild guess */
382	if (eisa_root_register (&eisa_dev.root)) {	382	if (eisa_root_register (&eisa_dev.root)) {
383	printk(KERN_ERR "EISA: Failed to register EISA root\n");	383	printk(KERN_ERR "EISA: Failed to register EISA root\n");
384	return -1;	384	return -1;
385	}	385	}
386	}	386	}
387		387
388	return 0;	388	return 0;
389	}	389	}
390		390
391	static struct parisc_device_id eisa_tbl[] = {	391	static struct parisc_device_id eisa_tbl[] = {
392	{ HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00076 }, /* Mongoose */	392	{ HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00076 }, /* Mongoose */
393	{ HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00090 }, /* Wax EISA */	393	{ HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00090 }, /* Wax EISA */
394	{ 0, }	394	{ 0, }
395	};	395	};
396		396
397	MODULE_DEVICE_TABLE(parisc, eisa_tbl);	397	MODULE_DEVICE_TABLE(parisc, eisa_tbl);
398		398
399	static struct parisc_driver eisa_driver = {	399	static struct parisc_driver eisa_driver = {
400	.name = "eisa_ba",	400	.name = "eisa_ba",
401	.id_table = eisa_tbl,	401	.id_table = eisa_tbl,
402	.probe = eisa_probe,	402	.probe = eisa_probe,
403	};	403	};
404		404
405	void __init eisa_init(void)	405	void __init eisa_init(void)
406	{	406	{
407	register_parisc_driver(&eisa_driver);	407	register_parisc_driver(&eisa_driver);
408	}	408	}
409		409
410		410
411	static unsigned int eisa_irq_configured;	411	static unsigned int eisa_irq_configured;
412	void eisa_make_irq_level(int num)	412	void eisa_make_irq_level(int num)
413	{	413	{
414	if (eisa_irq_configured& (1<<num)) {	414	if (eisa_irq_configured& (1<<num)) {
415	printk(KERN_WARNING	415	printk(KERN_WARNING
416	"IRQ %d polarity configured twice (last to level)\n",	416	"IRQ %d polarity configured twice (last to level)\n",
417	num);	417	num);
418	}	418	}
419	eisa_irq_level \|= (1<<num); /* set the corresponding bit */	419	eisa_irq_level \|= (1<<num); /* set the corresponding bit */
420	eisa_irq_configured \|= (1<<num); /* set the corresponding bit */	420	eisa_irq_configured \|= (1<<num); /* set the corresponding bit */
421	}	421	}
422		422
423	void eisa_make_irq_edge(int num)	423	void eisa_make_irq_edge(int num)
424	{	424	{
425	if (eisa_irq_configured& (1<<num)) {	425	if (eisa_irq_configured& (1<<num)) {
426	printk(KERN_WARNING	426	printk(KERN_WARNING
427	"IRQ %d polarity configured twice (last to edge)\n",	427	"IRQ %d polarity configured twice (last to edge)\n",
428	num);	428	num);
429	}	429	}
430	eisa_irq_level &= ~(1<<num); /* clear the corresponding bit */	430	eisa_irq_level &= ~(1<<num); /* clear the corresponding bit */
431	eisa_irq_configured \|= (1<<num); /* set the corresponding bit */	431	eisa_irq_configured \|= (1<<num); /* set the corresponding bit */
432	}	432	}
433		433
434	static int __init eisa_irq_setup(char *str)	434	static int __init eisa_irq_setup(char *str)
435	{	435	{
436	char *cur = str;	436	char *cur = str;
437	int val;	437	int val;
438		438
439	EISA_DBG("IRQ setup\n");	439	EISA_DBG("IRQ setup\n");
440	while (cur != NULL) {	440	while (cur != NULL) {
441	char *pe;	441	char *pe;
442		442
443	val = (int) simple_strtoul(cur, &pe, 0);	443	val = (int) simple_strtoul(cur, &pe, 0);
444	if (val > 15 \|\| val < 0) {	444	if (val > 15 \|\| val < 0) {
445	printk(KERN_ERR "eisa: EISA irq value are 0-15\n");	445	printk(KERN_ERR "eisa: EISA irq value are 0-15\n");
446	continue;	446	continue;
447	}	447	}
448	if (val == 2) {	448	if (val == 2) {
449	val = 9;	449	val = 9;
450	}	450	}
451	eisa_make_irq_edge(val); /* clear the corresponding bit */	451	eisa_make_irq_edge(val); /* clear the corresponding bit */
452	EISA_DBG("setting IRQ %d to edge-triggered mode\n", val);	452	EISA_DBG("setting IRQ %d to edge-triggered mode\n", val);
453		453
454	if ((cur = strchr(cur, ','))) {	454	if ((cur = strchr(cur, ','))) {
455	cur++;	455	cur++;
456	} else {	456	} else {
457	break;	457	break;
458	}	458	}
459	}	459	}
460	return 1;	460	return 1;
461	}	461	}
462		462
463	__setup("eisa_irq_edge=", eisa_irq_setup);	463	__setup("eisa_irq_edge=", eisa_irq_setup);
464		464
465		465

drivers/parisc/iosapic.c

Diff comments View file @ 5076c15

drivers/parisc/lba_pci.c

Diff comments View file @ 5076c15

drivers/parisc/sba_iommu.c

Diff comments View file @ 5076c15

drivers/parisc/superio.c

Diff comments View file @ 5076c15

1	/* National Semiconductor NS87560UBD Super I/O controller used in	1	/* National Semiconductor NS87560UBD Super I/O controller used in
2	* HP [BCJ]x000 workstations.	2	* HP [BCJ]x000 workstations.
3	*	3	*
4	* This chip is a horrid piece of engineering, and National	4	* This chip is a horrid piece of engineering, and National
5	* denies any knowledge of its existence. Thus no datasheet is	5	* denies any knowledge of its existence. Thus no datasheet is
6	* available off www.national.com.	6	* available off www.national.com.
7	*	7	*
8	* (C) Copyright 2000 Linuxcare, Inc.	8	* (C) Copyright 2000 Linuxcare, Inc.
9	* (C) Copyright 2000 Linuxcare Canada, Inc.	9	* (C) Copyright 2000 Linuxcare Canada, Inc.
10	* (C) Copyright 2000 Martin K. Petersen <mkp@linuxcare.com>	10	* (C) Copyright 2000 Martin K. Petersen <mkp@linuxcare.com>
11	* (C) Copyright 2000 Alex deVries <alex@onefishtwo.ca>	11	* (C) Copyright 2000 Alex deVries <alex@onefishtwo.ca>
12	* (C) Copyright 2001 John Marvin <jsm fc hp com>	12	* (C) Copyright 2001 John Marvin <jsm fc hp com>
13	* (C) Copyright 2003 Grant Grundler <grundler parisc-linux org>	13	* (C) Copyright 2003 Grant Grundler <grundler parisc-linux org>
14	* (C) Copyright 2005 Kyle McMartin <kyle@parisc-linux.org>	14	* (C) Copyright 2005 Kyle McMartin <kyle@parisc-linux.org>
		15	* (C) Copyright 2006 Helge Deller <deller@gmx.de>
15	*	16	*
16	* This program is free software; you can redistribute it and/or	17	* This program is free software; you can redistribute it and/or
17	* modify it under the terms of the GNU General Public License as	18	* modify it under the terms of the GNU General Public License as
18	* published by the Free Software Foundation; either version 2 of	19	* published by the Free Software Foundation; either version 2 of
19	* the License, or (at your option) any later version.	20	* the License, or (at your option) any later version.
20	*	21	*
21	* The initial version of this is by Martin Peterson. Alex deVries	22	* The initial version of this is by Martin Peterson. Alex deVries
22	* has spent a bit of time trying to coax it into working.	23	* has spent a bit of time trying to coax it into working.
23	*	24	*
24	* Major changes to get basic interrupt infrastructure working to	25	* Major changes to get basic interrupt infrastructure working to
25	* hopefully be able to support all SuperIO devices. Currently	26	* hopefully be able to support all SuperIO devices. Currently
26	* works with serial. -- John Marvin <jsm@fc.hp.com>	27	* works with serial. -- John Marvin <jsm@fc.hp.com>
27	*	28	*
28	* Converted superio_init() to be a PCI_FIXUP_FINAL callee.	29	* Converted superio_init() to be a PCI_FIXUP_FINAL callee.
29	* -- Kyle McMartin <kyle@parisc-linux.org>	30	* -- Kyle McMartin <kyle@parisc-linux.org>
30	*/	31	*/
31		32
32		33
33	/* NOTES:	34	/* NOTES:
34	*	35	*
35	* Function 0 is an IDE controller. It is identical to a PC87415 IDE	36	* Function 0 is an IDE controller. It is identical to a PC87415 IDE
36	* controller (and identifies itself as such).	37	* controller (and identifies itself as such).
37	*	38	*
38	* Function 1 is a "Legacy I/O" controller. Under this function is a	39	* Function 1 is a "Legacy I/O" controller. Under this function is a
39	* whole mess of legacy I/O peripherals. Of course, HP hasn't enabled	40	* whole mess of legacy I/O peripherals. Of course, HP hasn't enabled
40	* all the functionality in hardware, but the following is available:	41	* all the functionality in hardware, but the following is available:
41	*	42	*
42	* Two 16550A compatible serial controllers	43	* Two 16550A compatible serial controllers
43	* An IEEE 1284 compatible parallel port	44	* An IEEE 1284 compatible parallel port
44	* A floppy disk controller	45	* A floppy disk controller
45	*	46	*
46	* Function 2 is a USB controller.	47	* Function 2 is a USB controller.
47	*	48	*
48	* We must be incredibly careful during initialization. Since all	49	* We must be incredibly careful during initialization. Since all
49	* interrupts are routed through function 1 (which is not allowed by	50	* interrupts are routed through function 1 (which is not allowed by
50	* the PCI spec), we need to program the PICs on the legacy I/O port	51	* the PCI spec), we need to program the PICs on the legacy I/O port
51	* before we attempt to set up IDE and USB. @#$!&	52	* before we attempt to set up IDE and USB. @#$!&
52	*	53	*
53	* According to HP, devices are only enabled by firmware if they have	54	* According to HP, devices are only enabled by firmware if they have
54	* a physical device connected.	55	* a physical device connected.
55	*	56	*
56	* Configuration register bits:	57	* Configuration register bits:
57	* 0x5A: FDC, SP1, IDE1, SP2, IDE2, PAR, Reserved, P92	58	* 0x5A: FDC, SP1, IDE1, SP2, IDE2, PAR, Reserved, P92
58	* 0x5B: RTC, 8259, 8254, DMA1, DMA2, KBC, P61, APM	59	* 0x5B: RTC, 8259, 8254, DMA1, DMA2, KBC, P61, APM
59	*	60	*
60	*/	61	*/
61		62
62	#include <linux/errno.h>	63	#include <linux/errno.h>
63	#include <linux/init.h>	64	#include <linux/init.h>
64	#include <linux/module.h>	65	#include <linux/module.h>
65	#include <linux/types.h>	66	#include <linux/types.h>
66	#include <linux/interrupt.h>	67	#include <linux/interrupt.h>
67	#include <linux/ioport.h>	68	#include <linux/ioport.h>
68	#include <linux/serial.h>	69	#include <linux/serial.h>
69	#include <linux/pci.h>	70	#include <linux/pci.h>
70	#include <linux/parport.h>	71	#include <linux/parport.h>
71	#include <linux/parport_pc.h>	72	#include <linux/parport_pc.h>
72	#include <linux/termios.h>	73	#include <linux/termios.h>
73	#include <linux/tty.h>	74	#include <linux/tty.h>
74	#include <linux/serial_core.h>	75	#include <linux/serial_core.h>
75	#include <linux/delay.h>	76	#include <linux/delay.h>
76		77
77	#include <asm/io.h>	78	#include <asm/io.h>
78	#include <asm/hardware.h>	79	#include <asm/hardware.h>
79	#include <asm/superio.h>	80	#include <asm/superio.h>
80		81
81	static struct superio_device sio_dev;	82	static struct superio_device sio_dev;
82		83
83		84
84	#undef DEBUG_SUPERIO_INIT	85	#undef DEBUG_SUPERIO_INIT
85		86
86	#ifdef DEBUG_SUPERIO_INIT	87	#ifdef DEBUG_SUPERIO_INIT
87	#define DBG_INIT(x...) printk(x)	88	#define DBG_INIT(x...) printk(x)
88	#else	89	#else
89	#define DBG_INIT(x...)	90	#define DBG_INIT(x...)
90	#endif	91	#endif
91		92
92	#define SUPERIO "SuperIO"	93	#define SUPERIO "SuperIO"
93	#define PFX SUPERIO ": "	94	#define PFX SUPERIO ": "
94		95
95	static irqreturn_t	96	static irqreturn_t
96	superio_interrupt(int parent_irq, void devp, struct pt_regs regs)	97	superio_interrupt(int parent_irq, void devp, struct pt_regs regs)
97	{	98	{
98	u8 results;	99	u8 results;
99	u8 local_irq;	100	u8 local_irq;
100		101
101	/* Poll the 8259 to see if there's an interrupt. */	102	/* Poll the 8259 to see if there's an interrupt. */
102	outb (OCW3_POLL,IC_PIC1+0);	103	outb (OCW3_POLL,IC_PIC1+0);
103		104
104	results = inb(IC_PIC1+0);	105	results = inb(IC_PIC1+0);
105		106
106	/*	107	/*
107	* Bit 7: 1 = active Interrupt; 0 = no Interrupt pending	108	* Bit 7: 1 = active Interrupt; 0 = no Interrupt pending
108	* Bits 6-3: zero	109	* Bits 6-3: zero
109	* Bits 2-0: highest priority, active requesting interrupt ID (0-7)	110	* Bits 2-0: highest priority, active requesting interrupt ID (0-7)
110	*/	111	*/
111	if ((results & 0x80) == 0) {	112	if ((results & 0x80) == 0) {
112	/* I suspect "spurious" interrupts are from unmasking an IRQ.	113	/* I suspect "spurious" interrupts are from unmasking an IRQ.
113	* We don't know if an interrupt was/is pending and thus	114	* We don't know if an interrupt was/is pending and thus
114	* just call the handler for that IRQ as if it were pending.	115	* just call the handler for that IRQ as if it were pending.
115	*/	116	*/
116	return IRQ_NONE;	117	return IRQ_NONE;
117	}	118	}
118		119
119	/* Check to see which device is interrupting */	120	/* Check to see which device is interrupting */
120	local_irq = results & 0x0f;	121	local_irq = results & 0x0f;
121		122
122	if (local_irq == 2 \|\| local_irq > 7) {	123	if (local_irq == 2 \|\| local_irq > 7) {
123	printk(KERN_ERR PFX "slave interrupted!\n");	124	printk(KERN_ERR PFX "slave interrupted!\n");
124	return IRQ_HANDLED;	125	return IRQ_HANDLED;
125	}	126	}
126		127
127	if (local_irq == 7) {	128	if (local_irq == 7) {
128		129
129	/* Could be spurious. Check in service bits */	130	/* Could be spurious. Check in service bits */
130		131
131	outb(OCW3_ISR,IC_PIC1+0);	132	outb(OCW3_ISR,IC_PIC1+0);
132	results = inb(IC_PIC1+0);	133	results = inb(IC_PIC1+0);
133	if ((results & 0x80) == 0) { /* if ISR7 not set: spurious */	134	if ((results & 0x80) == 0) { /* if ISR7 not set: spurious */
134	printk(KERN_WARNING PFX "spurious interrupt!\n");	135	printk(KERN_WARNING PFX "spurious interrupt!\n");
135	return IRQ_HANDLED;	136	return IRQ_HANDLED;
136	}	137	}
137	}	138	}
138		139
139	/* Call the appropriate device's interrupt */	140	/* Call the appropriate device's interrupt */
140	__do_IRQ(local_irq, regs);	141	__do_IRQ(local_irq, regs);
141		142
142	/* set EOI - forces a new interrupt if a lower priority device	143	/* set EOI - forces a new interrupt if a lower priority device
143	* still needs service.	144	* still needs service.
144	*/	145	*/
145	outb((OCW2_SEOI\|local_irq),IC_PIC1 + 0);	146	outb((OCW2_SEOI\|local_irq),IC_PIC1 + 0);
146	return IRQ_HANDLED;	147	return IRQ_HANDLED;
147	}	148	}
148		149
149	/* Initialize Super I/O device */	150	/* Initialize Super I/O device */
150	static void	151	static void
151	superio_init(struct pci_dev *pcidev)	152	superio_init(struct pci_dev *pcidev)
152	{	153	{
153	struct superio_device *sio = &sio_dev;	154	struct superio_device *sio = &sio_dev;
154	struct pci_dev *pdev = sio->lio_pdev;	155	struct pci_dev *pdev = sio->lio_pdev;
155	u16 word;	156	u16 word;
156		157
157	if (sio->suckyio_irq_enabled)	158	if (sio->suckyio_irq_enabled)
158	return;	159	return;
159		160
160	BUG_ON(!pdev);	161	BUG_ON(!pdev);
161	BUG_ON(!sio->usb_pdev);	162	BUG_ON(!sio->usb_pdev);
162		163
163	/* use the IRQ iosapic found for USB INT D... */	164	/* use the IRQ iosapic found for USB INT D... */
164	pdev->irq = sio->usb_pdev->irq;	165	pdev->irq = sio->usb_pdev->irq;
165		166
166	/* ...then properly fixup the USB to point at suckyio PIC */	167	/* ...then properly fixup the USB to point at suckyio PIC */
167	sio->usb_pdev->irq = superio_fixup_irq(sio->usb_pdev);	168	sio->usb_pdev->irq = superio_fixup_irq(sio->usb_pdev);
168		169
169	printk(KERN_INFO PFX "Found NS87560 Legacy I/O device at %s (IRQ %i) \n",	170	printk(KERN_INFO PFX "Found NS87560 Legacy I/O device at %s (IRQ %i) \n",
170	pci_name(pdev), pdev->irq);	171	pci_name(pdev), pdev->irq);
171		172
172	pci_read_config_dword (pdev, SIO_SP1BAR, &sio->sp1_base);	173	pci_read_config_dword (pdev, SIO_SP1BAR, &sio->sp1_base);
173	sio->sp1_base &= ~1;	174	sio->sp1_base &= ~1;
174	printk(KERN_INFO PFX "Serial port 1 at 0x%x\n", sio->sp1_base);	175	printk(KERN_INFO PFX "Serial port 1 at 0x%x\n", sio->sp1_base);
175		176
176	pci_read_config_dword (pdev, SIO_SP2BAR, &sio->sp2_base);	177	pci_read_config_dword (pdev, SIO_SP2BAR, &sio->sp2_base);
177	sio->sp2_base &= ~1;	178	sio->sp2_base &= ~1;
178	printk(KERN_INFO PFX "Serial port 2 at 0x%x\n", sio->sp2_base);	179	printk(KERN_INFO PFX "Serial port 2 at 0x%x\n", sio->sp2_base);
179		180
180	pci_read_config_dword (pdev, SIO_PPBAR, &sio->pp_base);	181	pci_read_config_dword (pdev, SIO_PPBAR, &sio->pp_base);
181	sio->pp_base &= ~1;	182	sio->pp_base &= ~1;
182	printk(KERN_INFO PFX "Parallel port at 0x%x\n", sio->pp_base);	183	printk(KERN_INFO PFX "Parallel port at 0x%x\n", sio->pp_base);
183		184
184	pci_read_config_dword (pdev, SIO_FDCBAR, &sio->fdc_base);	185	pci_read_config_dword (pdev, SIO_FDCBAR, &sio->fdc_base);
185	sio->fdc_base &= ~1;	186	sio->fdc_base &= ~1;
186	printk(KERN_INFO PFX "Floppy controller at 0x%x\n", sio->fdc_base);	187	printk(KERN_INFO PFX "Floppy controller at 0x%x\n", sio->fdc_base);
187	pci_read_config_dword (pdev, SIO_ACPIBAR, &sio->acpi_base);	188	pci_read_config_dword (pdev, SIO_ACPIBAR, &sio->acpi_base);
188	sio->acpi_base &= ~1;	189	sio->acpi_base &= ~1;
189	printk(KERN_INFO PFX "ACPI at 0x%x\n", sio->acpi_base);	190	printk(KERN_INFO PFX "ACPI at 0x%x\n", sio->acpi_base);
190		191
191	request_region (IC_PIC1, 0x1f, "pic1");	192	request_region (IC_PIC1, 0x1f, "pic1");
192	request_region (IC_PIC2, 0x1f, "pic2");	193	request_region (IC_PIC2, 0x1f, "pic2");
193	request_region (sio->acpi_base, 0x1f, "acpi");	194	request_region (sio->acpi_base, 0x1f, "acpi");
194		195
195	/* Enable the legacy I/O function */	196	/* Enable the legacy I/O function */
196	pci_read_config_word (pdev, PCI_COMMAND, &word);	197	pci_read_config_word (pdev, PCI_COMMAND, &word);
197	word \|= PCI_COMMAND_SERR \| PCI_COMMAND_PARITY \| PCI_COMMAND_IO;	198	word \|= PCI_COMMAND_SERR \| PCI_COMMAND_PARITY \| PCI_COMMAND_IO;
198	pci_write_config_word (pdev, PCI_COMMAND, word);	199	pci_write_config_word (pdev, PCI_COMMAND, word);
199		200
200	pci_set_master (pdev);	201	pci_set_master (pdev);
201	pci_enable_device(pdev);	202	pci_enable_device(pdev);
202		203
203	/*	204	/*
204	* Next project is programming the onboard interrupt controllers.	205	* Next project is programming the onboard interrupt controllers.
205	* PDC hasn't done this for us, since it's using polled I/O.	206	* PDC hasn't done this for us, since it's using polled I/O.
206	*	207	*
207	* XXX Use dword writes to avoid bugs in Elroy or Suckyio Config	208	* XXX Use dword writes to avoid bugs in Elroy or Suckyio Config
208	* space access. PCI is by nature a 32-bit bus and config	209	* space access. PCI is by nature a 32-bit bus and config
209	* space can be sensitive to that.	210	* space can be sensitive to that.
210	*/	211	*/
211		212
212	/* 0x64 - 0x67 :	213	/* 0x64 - 0x67 :
213	DMA Rtg 2	214	DMA Rtg 2
214	DMA Rtg 3	215	DMA Rtg 3
215	DMA Chan Ctl	216	DMA Chan Ctl
216	TRIGGER_1 == 0x82 USB & IDE level triggered, rest to edge	217	TRIGGER_1 == 0x82 USB & IDE level triggered, rest to edge
217	*/	218	*/
218	pci_write_config_dword (pdev, 0x64, 0x82000000U);	219	pci_write_config_dword (pdev, 0x64, 0x82000000U);
219		220
220	/* 0x68 - 0x6b :	221	/* 0x68 - 0x6b :
221	TRIGGER_2 == 0x00 all edge triggered (not used)	222	TRIGGER_2 == 0x00 all edge triggered (not used)
222	CFG_IR_SER == 0x43 SerPort1 = IRQ3, SerPort2 = IRQ4	223	CFG_IR_SER == 0x43 SerPort1 = IRQ3, SerPort2 = IRQ4
223	CFG_IR_PF == 0x65 ParPort = IRQ5, FloppyCtlr = IRQ6	224	CFG_IR_PF == 0x65 ParPort = IRQ5, FloppyCtlr = IRQ6
224	CFG_IR_IDE == 0x07 IDE1 = IRQ7, reserved	225	CFG_IR_IDE == 0x07 IDE1 = IRQ7, reserved
225	*/	226	*/
226	pci_write_config_dword (pdev, TRIGGER_2, 0x07654300U);	227	pci_write_config_dword (pdev, TRIGGER_2, 0x07654300U);
227		228
228	/* 0x6c - 0x6f :	229	/* 0x6c - 0x6f :
229	CFG_IR_INTAB == 0x00	230	CFG_IR_INTAB == 0x00
230	CFG_IR_INTCD == 0x10 USB = IRQ1	231	CFG_IR_INTCD == 0x10 USB = IRQ1
231	CFG_IR_PS2 == 0x00	232	CFG_IR_PS2 == 0x00
232	CFG_IR_FXBUS == 0x00	233	CFG_IR_FXBUS == 0x00
233	*/	234	*/
234	pci_write_config_dword (pdev, CFG_IR_INTAB, 0x00001000U);	235	pci_write_config_dword (pdev, CFG_IR_INTAB, 0x00001000U);
235		236
236	/* 0x70 - 0x73 :	237	/* 0x70 - 0x73 :
237	CFG_IR_USB == 0x00 not used. USB is connected to INTD.	238	CFG_IR_USB == 0x00 not used. USB is connected to INTD.
238	CFG_IR_ACPI == 0x00 not used.	239	CFG_IR_ACPI == 0x00 not used.
239	DMA Priority == 0x4c88 Power on default value. NFC.	240	DMA Priority == 0x4c88 Power on default value. NFC.
240	*/	241	*/
241	pci_write_config_dword (pdev, CFG_IR_USB, 0x4c880000U);	242	pci_write_config_dword (pdev, CFG_IR_USB, 0x4c880000U);
242		243
243	/* PIC1 Initialization Command Word register programming */	244	/* PIC1 Initialization Command Word register programming */
244	outb (0x11,IC_PIC1+0); /* ICW1: ICW4 write req \| ICW1 */	245	outb (0x11,IC_PIC1+0); /* ICW1: ICW4 write req \| ICW1 */
245	outb (0x00,IC_PIC1+1); /* ICW2: interrupt vector table - not used */	246	outb (0x00,IC_PIC1+1); /* ICW2: interrupt vector table - not used */
246	outb (0x04,IC_PIC1+1); /* ICW3: Cascade */	247	outb (0x04,IC_PIC1+1); /* ICW3: Cascade */
247	outb (0x01,IC_PIC1+1); /* ICW4: x86 mode */	248	outb (0x01,IC_PIC1+1); /* ICW4: x86 mode */
248		249
249	/* PIC1 Program Operational Control Words */	250	/* PIC1 Program Operational Control Words */
250	outb (0xff,IC_PIC1+1); /* OCW1: Mask all interrupts */	251	outb (0xff,IC_PIC1+1); /* OCW1: Mask all interrupts */
251	outb (0xc2,IC_PIC1+0); /* OCW2: priority (3-7,0-2) */	252	outb (0xc2,IC_PIC1+0); /* OCW2: priority (3-7,0-2) */
252		253
253	/* PIC2 Initialization Command Word register programming */	254	/* PIC2 Initialization Command Word register programming */
254	outb (0x11,IC_PIC2+0); /* ICW1: ICW4 write req \| ICW1 */	255	outb (0x11,IC_PIC2+0); /* ICW1: ICW4 write req \| ICW1 */
255	outb (0x00,IC_PIC2+1); /* ICW2: N/A */	256	outb (0x00,IC_PIC2+1); /* ICW2: N/A */
256	outb (0x02,IC_PIC2+1); /* ICW3: Slave ID code */	257	outb (0x02,IC_PIC2+1); /* ICW3: Slave ID code */
257	outb (0x01,IC_PIC2+1); /* ICW4: x86 mode */	258	outb (0x01,IC_PIC2+1); /* ICW4: x86 mode */
258		259
259	/* Program Operational Control Words */	260	/* Program Operational Control Words */
260	outb (0xff,IC_PIC1+1); /* OCW1: Mask all interrupts */	261	outb (0xff,IC_PIC1+1); /* OCW1: Mask all interrupts */
261	outb (0x68,IC_PIC1+0); /* OCW3: OCW3 select \| ESMM \| SMM */	262	outb (0x68,IC_PIC1+0); /* OCW3: OCW3 select \| ESMM \| SMM */
262		263
263	/* Write master mask reg */	264	/* Write master mask reg */
264	outb (0xff,IC_PIC1+1);	265	outb (0xff,IC_PIC1+1);
265		266
266	/* Setup USB power regulation */	267	/* Setup USB power regulation */
267	outb(1, sio->acpi_base + USB_REG_CR);	268	outb(1, sio->acpi_base + USB_REG_CR);
268	if (inb(sio->acpi_base + USB_REG_CR) & 1)	269	if (inb(sio->acpi_base + USB_REG_CR) & 1)
269	printk(KERN_INFO PFX "USB regulator enabled\n");	270	printk(KERN_INFO PFX "USB regulator enabled\n");
270	else	271	else
271	printk(KERN_ERR PFX "USB regulator not initialized!\n");	272	printk(KERN_ERR PFX "USB regulator not initialized!\n");
272		273
273	if (request_irq(pdev->irq, superio_interrupt, SA_INTERRUPT,	274	if (request_irq(pdev->irq, superio_interrupt, SA_INTERRUPT,
274	SUPERIO, (void *)sio)) {	275	SUPERIO, (void *)sio)) {
275		276
276	printk(KERN_ERR PFX "could not get irq\n");	277	printk(KERN_ERR PFX "could not get irq\n");
277	BUG();	278	BUG();
278	return;	279	return;
279	}	280	}
280		281
281	sio->suckyio_irq_enabled = 1;	282	sio->suckyio_irq_enabled = 1;
282	}	283	}
283	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87560_LIO, superio_init);	284	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87560_LIO, superio_init);
284		285
285	static void superio_disable_irq(unsigned int irq)	286	static void superio_disable_irq(unsigned int irq)
286	{	287	{
287	u8 r8;	288	u8 r8;
288		289
289	if ((irq < 1) \|\| (irq == 2) \|\| (irq > 7)) {	290	if ((irq < 1) \|\| (irq == 2) \|\| (irq > 7)) {
290	printk(KERN_ERR PFX "Illegal irq number.\n");	291	printk(KERN_ERR PFX "Illegal irq number.\n");
291	BUG();	292	BUG();
292	return;	293	return;
293	}	294	}
294		295
295	/* Mask interrupt */	296	/* Mask interrupt */
296		297
297	r8 = inb(IC_PIC1+1);	298	r8 = inb(IC_PIC1+1);
298	r8 \|= (1 << irq);	299	r8 \|= (1 << irq);
299	outb (r8,IC_PIC1+1);	300	outb (r8,IC_PIC1+1);
300	}	301	}
301		302
302	static void superio_enable_irq(unsigned int irq)	303	static void superio_enable_irq(unsigned int irq)
303	{	304	{
304	u8 r8;	305	u8 r8;
305		306
306	if ((irq < 1) \|\| (irq == 2) \|\| (irq > 7)) {	307	if ((irq < 1) \|\| (irq == 2) \|\| (irq > 7)) {
307	printk(KERN_ERR PFX "Illegal irq number (%d).\n", irq);	308	printk(KERN_ERR PFX "Illegal irq number (%d).\n", irq);
308	BUG();	309	BUG();
309	return;	310	return;
310	}	311	}
311		312
312	/* Unmask interrupt */	313	/* Unmask interrupt */
313	r8 = inb(IC_PIC1+1);	314	r8 = inb(IC_PIC1+1);
314	r8 &= ~(1 << irq);	315	r8 &= ~(1 << irq);
315	outb (r8,IC_PIC1+1);	316	outb (r8,IC_PIC1+1);
316	}	317	}
317		318
318	static unsigned int superio_startup_irq(unsigned int irq)	319	static unsigned int superio_startup_irq(unsigned int irq)
319	{	320	{
320	superio_enable_irq(irq);	321	superio_enable_irq(irq);
321	return 0;	322	return 0;
322	}	323	}
323		324
324	static struct hw_interrupt_type superio_interrupt_type = {	325	static struct hw_interrupt_type superio_interrupt_type = {
325	.typename = SUPERIO,	326	.typename = SUPERIO,
326	.startup = superio_startup_irq,	327	.startup = superio_startup_irq,
327	.shutdown = superio_disable_irq,	328	.shutdown = superio_disable_irq,
328	.enable = superio_enable_irq,	329	.enable = superio_enable_irq,
329	.disable = superio_disable_irq,	330	.disable = superio_disable_irq,
330	.ack = no_ack_irq,	331	.ack = no_ack_irq,
331	.end = no_end_irq,	332	.end = no_end_irq,
332	};	333	};
333		334
334	#ifdef DEBUG_SUPERIO_INIT	335	#ifdef DEBUG_SUPERIO_INIT
335	static unsigned short expected_device[3] = {	336	static unsigned short expected_device[3] = {
336	PCI_DEVICE_ID_NS_87415,	337	PCI_DEVICE_ID_NS_87415,
337	PCI_DEVICE_ID_NS_87560_LIO,	338	PCI_DEVICE_ID_NS_87560_LIO,
338	PCI_DEVICE_ID_NS_87560_USB	339	PCI_DEVICE_ID_NS_87560_USB
339	};	340	};
340	#endif	341	#endif
341		342
342	int superio_fixup_irq(struct pci_dev *pcidev)	343	int superio_fixup_irq(struct pci_dev *pcidev)
343	{	344	{
344	int local_irq, i;	345	int local_irq, i;
345		346
346	#ifdef DEBUG_SUPERIO_INIT	347	#ifdef DEBUG_SUPERIO_INIT
347	int fn;	348	int fn;
348	fn = PCI_FUNC(pcidev->devfn);	349	fn = PCI_FUNC(pcidev->devfn);
349		350
350	/* Verify the function number matches the expected device id. */	351	/* Verify the function number matches the expected device id. */
351	if (expected_device[fn] != pcidev->device) {	352	if (expected_device[fn] != pcidev->device) {
352	BUG();	353	BUG();
353	return -1;	354	return -1;
354	}	355	}
355	printk("superio_fixup_irq(%s) ven 0x%x dev 0x%x from %p\n",	356	printk("superio_fixup_irq(%s) ven 0x%x dev 0x%x from %p\n",
356	pci_name(pcidev),	357	pci_name(pcidev),
357	pcidev->vendor, pcidev->device,	358	pcidev->vendor, pcidev->device,
358	__builtin_return_address(0));	359	__builtin_return_address(0));
359	#endif	360	#endif
360		361
361	for (i = 0; i < 16; i++) {	362	for (i = 0; i < 16; i++) {
362	irq_desc[i].handler = &superio_interrupt_type;	363	irq_desc[i].handler = &superio_interrupt_type;
363	}	364	}
364		365
365	/*	366	/*
366	* We don't allocate a SuperIO irq for the legacy IO function,	367	* We don't allocate a SuperIO irq for the legacy IO function,
367	* since it is a "bridge". Instead, we will allocate irq's for	368	* since it is a "bridge". Instead, we will allocate irq's for
368	* each legacy device as they are initialized.	369	* each legacy device as they are initialized.
369	*/	370	*/
370		371
371	switch(pcidev->device) {	372	switch(pcidev->device) {
372	case PCI_DEVICE_ID_NS_87415: /* Function 0 */	373	case PCI_DEVICE_ID_NS_87415: /* Function 0 */
373	local_irq = IDE_IRQ;	374	local_irq = IDE_IRQ;
374	break;	375	break;
375	case PCI_DEVICE_ID_NS_87560_LIO: /* Function 1 */	376	case PCI_DEVICE_ID_NS_87560_LIO: /* Function 1 */
376	sio_dev.lio_pdev = pcidev; /* save for superio_init() */	377	sio_dev.lio_pdev = pcidev; /* save for superio_init() */
377	return -1;	378	return -1;
378	case PCI_DEVICE_ID_NS_87560_USB: /* Function 2 */	379	case PCI_DEVICE_ID_NS_87560_USB: /* Function 2 */
379	sio_dev.usb_pdev = pcidev; /* save for superio_init() */	380	sio_dev.usb_pdev = pcidev; /* save for superio_init() */
380	local_irq = USB_IRQ;	381	local_irq = USB_IRQ;
381	break;	382	break;
382	default:	383	default:
383	local_irq = -1;	384	local_irq = -1;
384	BUG();	385	BUG();
385	break;	386	break;
386	}	387	}
387		388
388	return local_irq;	389	return local_irq;
389	}	390	}
390		391
391	static struct uart_port serial[] = {
392	{
393	.iotype = UPIO_PORT,
394	.line = 0,
395	.type = PORT_16550A,
396	.uartclk = 115200*16,
397	.fifosize = 16,
398	},
399	{
400	.iotype = UPIO_PORT,
401	.line = 1,
402	.type = PORT_16550A,
403	.uartclk = 115200*16,
404	.fifosize = 16,
405	}
406	};
407
408	static void __devinit superio_serial_init(void)	392	static void __devinit superio_serial_init(void)
409	{	393	{
410	#ifdef CONFIG_SERIAL_8250	394	#ifdef CONFIG_SERIAL_8250
411	int retval;	395	int retval;
412		396	struct uart_port serial_port;
413	serial[0].iobase = sio_dev.sp1_base;
414	serial[0].irq = SP1_IRQ;
415	spin_lock_init(&serial[0].lock);
416		397
417	retval = early_serial_setup(&serial[0]);	398	memset(&serial_port, 0, sizeof(serial_port));
		399	serial_port.iotype = UPIO_PORT;
		400	serial_port.type = PORT_16550A;
		401	serial_port.uartclk = 115200*16;
		402	serial_port.fifosize = 16;
		403	spin_lock_init(&serial_port.lock);
		404
		405	/* serial port #1 */
		406	serial_port.iobase = sio_dev.sp1_base;
		407	serial_port.irq = SP1_IRQ;
		408	serial_port.line = 0;
		409	retval = early_serial_setup(&serial_port);
418	if (retval < 0) {	410	if (retval < 0) {
419	printk(KERN_WARNING PFX "Register Serial #0 failed.\n");	411	printk(KERN_WARNING PFX "Register Serial #0 failed.\n");
420	return;	412	return;
421	}	413	}
422		414
423	serial[1].iobase = sio_dev.sp2_base;	415	/* serial port #2 */
424	serial[1].irq = SP2_IRQ;	416	serial_port.iobase = sio_dev.sp2_base;
425	spin_lock_init(&serial[1].lock);	417	serial_port.irq = SP2_IRQ;
426	retval = early_serial_setup(&serial[1]);	418	serial_port.line = 1;
427		419	retval = early_serial_setup(&serial_port);
428	if (retval < 0)	420	if (retval < 0)
429	printk(KERN_WARNING PFX "Register Serial #1 failed.\n");	421	printk(KERN_WARNING PFX "Register Serial #1 failed.\n");
430	#endif /* CONFIG_SERIAL_8250 */	422	#endif /* CONFIG_SERIAL_8250 */
431	}	423	}
432		424
433		425
434	static void __devinit superio_parport_init(void)	426	static void __devinit superio_parport_init(void)
435	{	427	{
436	#ifdef CONFIG_PARPORT_PC	428	#ifdef CONFIG_PARPORT_PC
437	if (!parport_pc_probe_port(sio_dev.pp_base,	429	if (!parport_pc_probe_port(sio_dev.pp_base,
438	0 /base_hi/,	430	0 /base_hi/,
439	PAR_IRQ,	431	PAR_IRQ,
440	PARPORT_DMA_NONE /* dma */,	432	PARPORT_DMA_NONE /* dma */,
441	NULL /struct pci_dev */) )	433	NULL /struct pci_dev */) )
442		434
443	printk(KERN_WARNING PFX "Probing parallel port failed.\n");	435	printk(KERN_WARNING PFX "Probing parallel port failed.\n");
444	#endif /* CONFIG_PARPORT_PC */	436	#endif /* CONFIG_PARPORT_PC */
445	}	437	}
446		438
447		439
448	static void superio_fixup_pci(struct pci_dev *pdev)	440	static void superio_fixup_pci(struct pci_dev *pdev)
449	{	441	{
450	u8 prog;	442	u8 prog;
451		443
452	pdev->class \|= 0x5;	444	pdev->class \|= 0x5;
453	pci_write_config_byte(pdev, PCI_CLASS_PROG, pdev->class);	445	pci_write_config_byte(pdev, PCI_CLASS_PROG, pdev->class);
454		446
455	pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);	447	pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
456	printk("PCI: Enabled native mode for NS87415 (pif=0x%x)\n", prog);	448	printk("PCI: Enabled native mode for NS87415 (pif=0x%x)\n", prog);
457	}	449	}
458	DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87415, superio_fixup_pci);	450	DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87415, superio_fixup_pci);
459		451
460		452
461	static int __devinit	453	static int __devinit
462	superio_probe(struct pci_dev dev, const struct pci_device_id id)	454	superio_probe(struct pci_dev dev, const struct pci_device_id id)
463	{	455	{
464	struct superio_device *sio = &sio_dev;	456	struct superio_device *sio = &sio_dev;
465		457
466	/*	458	/*
467	** superio_probe(00:0e.0) ven 0x100b dev 0x2 sv 0x0 sd 0x0 class 0x1018a	459	** superio_probe(00:0e.0) ven 0x100b dev 0x2 sv 0x0 sd 0x0 class 0x1018a
468	** superio_probe(00:0e.1) ven 0x100b dev 0xe sv 0x0 sd 0x0 class 0x68000	460	** superio_probe(00:0e.1) ven 0x100b dev 0xe sv 0x0 sd 0x0 class 0x68000
469	** superio_probe(00:0e.2) ven 0x100b dev 0x12 sv 0x0 sd 0x0 class 0xc0310	461	** superio_probe(00:0e.2) ven 0x100b dev 0x12 sv 0x0 sd 0x0 class 0xc0310
470	*/	462	*/
471	DBG_INIT("superio_probe(%s) ven 0x%x dev 0x%x sv 0x%x sd 0x%x class 0x%x\n",	463	DBG_INIT("superio_probe(%s) ven 0x%x dev 0x%x sv 0x%x sd 0x%x class 0x%x\n",
472	pci_name(dev),	464	pci_name(dev),
473	dev->vendor, dev->device,	465	dev->vendor, dev->device,
474	dev->subsystem_vendor, dev->subsystem_device,	466	dev->subsystem_vendor, dev->subsystem_device,
475	dev->class);	467	dev->class);
476		468
477	BUG_ON(!sio->suckyio_irq_enabled); /* Enabled by PCI_FIXUP_FINAL */	469	BUG_ON(!sio->suckyio_irq_enabled); /* Enabled by PCI_FIXUP_FINAL */
478		470
479	if (dev->device == PCI_DEVICE_ID_NS_87560_LIO) { /* Function 1 */	471	if (dev->device == PCI_DEVICE_ID_NS_87560_LIO) { /* Function 1 */
480	superio_parport_init();	472	superio_parport_init();
481	superio_serial_init();	473	superio_serial_init();
482	/* REVISIT XXX : superio_fdc_init() ? */	474	/* REVISIT XXX : superio_fdc_init() ? */
483	return 0;	475	return 0;
484	} else if (dev->device == PCI_DEVICE_ID_NS_87415) { /* Function 0 */	476	} else if (dev->device == PCI_DEVICE_ID_NS_87415) { /* Function 0 */
485	DBG_INIT("superio_probe: ignoring IDE 87415\n");	477	DBG_INIT("superio_probe: ignoring IDE 87415\n");
486	} else if (dev->device == PCI_DEVICE_ID_NS_87560_USB) { /* Function 2 */	478	} else if (dev->device == PCI_DEVICE_ID_NS_87560_USB) { /* Function 2 */
487	DBG_INIT("superio_probe: ignoring USB OHCI controller\n");	479	DBG_INIT("superio_probe: ignoring USB OHCI controller\n");
488	} else {	480	} else {
489	DBG_INIT("superio_probe: WTF? Fire Extinguisher?\n");	481	DBG_INIT("superio_probe: WTF? Fire Extinguisher?\n");
490	}	482	}
491		483
492	/* Let appropriate other driver claim this device. */	484	/* Let appropriate other driver claim this device. */
493	return -ENODEV;	485	return -ENODEV;
494	}	486	}
495		487
496	static struct pci_device_id superio_tbl[] = {	488	static struct pci_device_id superio_tbl[] = {
497	{ PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87560_LIO) },	489	{ PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87560_LIO) },
498	{ PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87560_USB) },	490	{ PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87560_USB) },
499	{ PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87415) },	491	{ PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87415) },
500	{ 0, }	492	{ 0, }
501	};	493	};
502		494
503	static struct pci_driver superio_driver = {	495	static struct pci_driver superio_driver = {
504	.name = SUPERIO,	496	.name = SUPERIO,
505	.id_table = superio_tbl,	497	.id_table = superio_tbl,
506	.probe = superio_probe,	498	.probe = superio_probe,
507	};	499	};
508		500
509	static int __init superio_modinit(void)	501	static int __init superio_modinit(void)

drivers/scsi/lasi700.c

Diff comments View file @ 5076c15

1	/* -- mode: c; c-basic-offset: 8 -- */	1	/* -- mode: c; c-basic-offset: 8 -- */
2		2
3	/* PARISC LASI driver for the 53c700 chip	3	/* PARISC LASI driver for the 53c700 chip
4	*	4	*
5	* Copyright (C) 2001 by James.Bottomley@HansenPartnership.com	5	* Copyright (C) 2001 by James.Bottomley@HansenPartnership.com
6	**-----------------------------------------------------------------------------	6	**-----------------------------------------------------------------------------
7	**	7	**
8	** This program is free software; you can redistribute it and/or modify	8	** This program is free software; you can redistribute it and/or modify
9	** it under the terms of the GNU General Public License as published by	9	** it under the terms of the GNU General Public License as published by
10	** the Free Software Foundation; either version 2 of the License, or	10	** the Free Software Foundation; either version 2 of the License, or
11	** (at your option) any later version.	11	** (at your option) any later version.
12	**	12	**
13	** This program is distributed in the hope that it will be useful,	13	** This program is distributed in the hope that it will be useful,
14	** but WITHOUT ANY WARRANTY; without even the implied warranty of	14	** but WITHOUT ANY WARRANTY; without even the implied warranty of
15	** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	15	** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16	** GNU General Public License for more details.	16	** GNU General Public License for more details.
17	**	17	**
18	** You should have received a copy of the GNU General Public License	18	** You should have received a copy of the GNU General Public License
19	** along with this program; if not, write to the Free Software	19	** along with this program; if not, write to the Free Software
20	** Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.	20	** Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21	**	21	**
22	**-----------------------------------------------------------------------------	22	**-----------------------------------------------------------------------------
23	*/	23	*/
24		24
25	/*	25	/*
26	* Many thanks to Richard Hirst <rhirst@linuxcare.com> for patiently	26	* Many thanks to Richard Hirst <rhirst@linuxcare.com> for patiently
27	* debugging this driver on the parisc architecture and suggesting	27	* debugging this driver on the parisc architecture and suggesting
28	* many improvements and bug fixes.	28	* many improvements and bug fixes.
29	*	29	*
30	* Thanks also go to Linuxcare Inc. for providing several PARISC	30	* Thanks also go to Linuxcare Inc. for providing several PARISC
31	* machines for me to debug the driver on.	31	* machines for me to debug the driver on.
32	*/	32	*/
33		33
34	#include <linux/kernel.h>	34	#include <linux/kernel.h>
35	#include <linux/module.h>	35	#include <linux/module.h>
36	#include <linux/init.h>	36	#include <linux/init.h>
37	#include <linux/types.h>	37	#include <linux/types.h>
38	#include <linux/stat.h>	38	#include <linux/stat.h>
39	#include <linux/mm.h>	39	#include <linux/mm.h>
40	#include <linux/blkdev.h>	40	#include <linux/blkdev.h>
41	#include <linux/sched.h>	41	#include <linux/sched.h>
42	#include <linux/ioport.h>	42	#include <linux/ioport.h>
43	#include <linux/dma-mapping.h>	43	#include <linux/dma-mapping.h>
44		44
45	#include <asm/page.h>	45	#include <asm/page.h>
46	#include <asm/pgtable.h>	46	#include <asm/pgtable.h>
47	#include <asm/irq.h>	47	#include <asm/irq.h>
48	#include <asm/hardware.h>	48	#include <asm/hardware.h>
49	#include <asm/parisc-device.h>	49	#include <asm/parisc-device.h>
50	#include <asm/delay.h>	50	#include <asm/delay.h>
51		51
52	#include <scsi/scsi_host.h>	52	#include <scsi/scsi_host.h>
53	#include <scsi/scsi_device.h>	53	#include <scsi/scsi_device.h>
54	#include <scsi/scsi_transport.h>	54	#include <scsi/scsi_transport.h>
55	#include <scsi/scsi_transport_spi.h>	55	#include <scsi/scsi_transport_spi.h>
56		56
57	#include "53c700.h"	57	#include "53c700.h"
58		58
59	MODULE_AUTHOR("James Bottomley");	59	MODULE_AUTHOR("James Bottomley");
60	MODULE_DESCRIPTION("lasi700 SCSI Driver");	60	MODULE_DESCRIPTION("lasi700 SCSI Driver");
61	MODULE_LICENSE("GPL");	61	MODULE_LICENSE("GPL");
62		62
63	#define LASI_700_SVERSION 0x00071	63	#define LASI_700_SVERSION 0x00071
64	#define LASI_710_SVERSION 0x00082	64	#define LASI_710_SVERSION 0x00082
65		65
66	#define LASI700_ID_TABLE { \	66	#define LASI700_ID_TABLE { \
67	.hw_type = HPHW_FIO, \	67	.hw_type = HPHW_FIO, \
68	.sversion = LASI_700_SVERSION, \	68	.sversion = LASI_700_SVERSION, \
69	.hversion = HVERSION_ANY_ID, \	69	.hversion = HVERSION_ANY_ID, \
70	.hversion_rev = HVERSION_REV_ANY_ID, \	70	.hversion_rev = HVERSION_REV_ANY_ID, \
71	}	71	}
72		72
73	#define LASI710_ID_TABLE { \	73	#define LASI710_ID_TABLE { \
74	.hw_type = HPHW_FIO, \	74	.hw_type = HPHW_FIO, \
75	.sversion = LASI_710_SVERSION, \	75	.sversion = LASI_710_SVERSION, \
76	.hversion = HVERSION_ANY_ID, \	76	.hversion = HVERSION_ANY_ID, \
77	.hversion_rev = HVERSION_REV_ANY_ID, \	77	.hversion_rev = HVERSION_REV_ANY_ID, \
78	}	78	}
79		79
80	#define LASI700_CLOCK 25	80	#define LASI700_CLOCK 25
81	#define LASI710_CLOCK 40	81	#define LASI710_CLOCK 40
82	#define LASI_SCSI_CORE_OFFSET 0x100	82	#define LASI_SCSI_CORE_OFFSET 0x100
83		83
84	static struct parisc_device_id lasi700_ids[] = {	84	static struct parisc_device_id lasi700_ids[] = {
85	LASI700_ID_TABLE,	85	LASI700_ID_TABLE,
86	LASI710_ID_TABLE,	86	LASI710_ID_TABLE,
87	{ 0 }	87	{ 0 }
88	};	88	};
89		89
90	static struct scsi_host_template lasi700_template = {	90	static struct scsi_host_template lasi700_template = {
91	.name = "LASI SCSI 53c700",	91	.name = "LASI SCSI 53c700",
92	.proc_name = "lasi700",	92	.proc_name = "lasi700",
93	.this_id = 7,	93	.this_id = 7,
94	.module = THIS_MODULE,	94	.module = THIS_MODULE,
95	};	95	};
96	MODULE_DEVICE_TABLE(parisc, lasi700_ids);	96	MODULE_DEVICE_TABLE(parisc, lasi700_ids);
97		97
98	static int __init	98	static int __init
99	lasi700_probe(struct parisc_device *dev)	99	lasi700_probe(struct parisc_device *dev)
100	{	100	{
101	unsigned long base = dev->hpa.start + LASI_SCSI_CORE_OFFSET;	101	unsigned long base = dev->hpa.start + LASI_SCSI_CORE_OFFSET;
102	struct NCR_700_Host_Parameters *hostdata;	102	struct NCR_700_Host_Parameters *hostdata;
103	struct Scsi_Host *host;	103	struct Scsi_Host *host;
104		104
105	hostdata = kmalloc(sizeof(*hostdata), GFP_KERNEL);	105	hostdata = kmalloc(sizeof(*hostdata), GFP_KERNEL);
106	if (!hostdata) {	106	if (!hostdata) {
107	printk(KERN_ERR "%s: Failed to allocate host data\n",	107	printk(KERN_ERR "%s: Failed to allocate host data\n",
108	dev->dev.bus_id);	108	dev->dev.bus_id);
109	return -ENOMEM;	109	return -ENOMEM;
110	}	110	}
111	memset(hostdata, 0, sizeof(struct NCR_700_Host_Parameters));	111	memset(hostdata, 0, sizeof(struct NCR_700_Host_Parameters));
112		112
113	hostdata->dev = &dev->dev;	113	hostdata->dev = &dev->dev;
114	dma_set_mask(&dev->dev, DMA_32BIT_MASK);	114	dma_set_mask(&dev->dev, DMA_32BIT_MASK);
115	hostdata->base = ioremap(base, 0x100);	115	hostdata->base = ioremap_nocache(base, 0x100);
116	hostdata->differential = 0;	116	hostdata->differential = 0;
117		117
118	if (dev->id.sversion == LASI_700_SVERSION) {	118	if (dev->id.sversion == LASI_700_SVERSION) {
119	hostdata->clock = LASI700_CLOCK;	119	hostdata->clock = LASI700_CLOCK;
120	hostdata->force_le_on_be = 1;	120	hostdata->force_le_on_be = 1;
121	} else {	121	} else {
122	hostdata->clock = LASI710_CLOCK;	122	hostdata->clock = LASI710_CLOCK;
123	hostdata->force_le_on_be = 0;	123	hostdata->force_le_on_be = 0;
124	hostdata->chip710 = 1;	124	hostdata->chip710 = 1;
125	hostdata->dmode_extra = DMODE_FC2;	125	hostdata->dmode_extra = DMODE_FC2;
126	}	126	}
127		127
128	host = NCR_700_detect(&lasi700_template, hostdata, &dev->dev);	128	host = NCR_700_detect(&lasi700_template, hostdata, &dev->dev);
129	if (!host)	129	if (!host)
130	goto out_kfree;	130	goto out_kfree;
131	host->this_id = 7;	131	host->this_id = 7;
132	host->base = base;	132	host->base = base;
133	host->irq = dev->irq;	133	host->irq = dev->irq;
134	if(request_irq(dev->irq, NCR_700_intr, SA_SHIRQ, "lasi700", host)) {	134	if(request_irq(dev->irq, NCR_700_intr, SA_SHIRQ, "lasi700", host)) {
135	printk(KERN_ERR "lasi700: request_irq failed!\n");	135	printk(KERN_ERR "lasi700: request_irq failed!\n");
136	goto out_put_host;	136	goto out_put_host;
137	}	137	}
138		138
139	dev_set_drvdata(&dev->dev, host);	139	dev_set_drvdata(&dev->dev, host);
140	scsi_scan_host(host);	140	scsi_scan_host(host);
141		141
142	return 0;	142	return 0;
143		143
144	out_put_host:	144	out_put_host:
145	scsi_host_put(host);	145	scsi_host_put(host);
146	out_kfree:	146	out_kfree:
147	iounmap(hostdata->base);	147	iounmap(hostdata->base);
148	kfree(hostdata);	148	kfree(hostdata);
149	return -ENODEV;	149	return -ENODEV;
150	}	150	}
151		151
152	static int __exit	152	static int __exit
153	lasi700_driver_remove(struct parisc_device *dev)	153	lasi700_driver_remove(struct parisc_device *dev)
154	{	154	{
155	struct Scsi_Host *host = dev_get_drvdata(&dev->dev);	155	struct Scsi_Host *host = dev_get_drvdata(&dev->dev);
156	struct NCR_700_Host_Parameters *hostdata =	156	struct NCR_700_Host_Parameters *hostdata =
157	(struct NCR_700_Host_Parameters *)host->hostdata[0];	157	(struct NCR_700_Host_Parameters *)host->hostdata[0];
158		158
159	scsi_remove_host(host);	159	scsi_remove_host(host);
160	NCR_700_release(host);	160	NCR_700_release(host);
161	free_irq(host->irq, host);	161	free_irq(host->irq, host);
162	iounmap(hostdata->base);	162	iounmap(hostdata->base);
163	kfree(hostdata);	163	kfree(hostdata);
164		164
165	return 0;	165	return 0;
166	}	166	}
167		167
168	static struct parisc_driver lasi700_driver = {	168	static struct parisc_driver lasi700_driver = {
169	.name = "lasi_scsi",	169	.name = "lasi_scsi",
170	.id_table = lasi700_ids,	170	.id_table = lasi700_ids,
171	.probe = lasi700_probe,	171	.probe = lasi700_probe,
172	.remove = __devexit_p(lasi700_driver_remove),	172	.remove = __devexit_p(lasi700_driver_remove),
173	};	173	};
174		174
175	static int __init	175	static int __init
176	lasi700_init(void)	176	lasi700_init(void)
177	{	177	{
178	return register_parisc_driver(&lasi700_driver);	178	return register_parisc_driver(&lasi700_driver);
179	}	179	}
180		180
181	static void __exit	181	static void __exit
182	lasi700_exit(void)	182	lasi700_exit(void)
183	{	183	{
184	unregister_parisc_driver(&lasi700_driver);	184	unregister_parisc_driver(&lasi700_driver);
185	}	185	}
186		186
187	module_init(lasi700_init);	187	module_init(lasi700_init);
188	module_exit(lasi700_exit);	188	module_exit(lasi700_exit);
189		189

drivers/scsi/zalon.c

Diff comments View file @ 5076c15

1	/*	1	/*
2	* Zalon 53c7xx device driver.	2	* Zalon 53c7xx device driver.
3	* By Richard Hirst (rhirst@linuxcare.com)	3	* By Richard Hirst (rhirst@linuxcare.com)
4	*/	4	*/
5		5
6	#include <linux/init.h>	6	#include <linux/init.h>
7	#include <linux/interrupt.h>	7	#include <linux/interrupt.h>
8	#include <linux/module.h>	8	#include <linux/module.h>
9	#include <linux/types.h>	9	#include <linux/types.h>
10	#include <asm/hardware.h>	10	#include <asm/hardware.h>
11	#include <asm/io.h>	11	#include <asm/io.h>
12		12
13	#include "../parisc/gsc.h"	13	#include "../parisc/gsc.h"
14		14
15	#include "ncr53c8xx.h"	15	#include "ncr53c8xx.h"
16		16
17	MODULE_AUTHOR("Richard Hirst");	17	MODULE_AUTHOR("Richard Hirst");
18	MODULE_DESCRIPTION("Bluefish/Zalon 720 SCSI Driver");	18	MODULE_DESCRIPTION("Bluefish/Zalon 720 SCSI Driver");
19	MODULE_LICENSE("GPL");	19	MODULE_LICENSE("GPL");
20		20
21	#define GSC_SCSI_ZALON_OFFSET 0x800	21	#define GSC_SCSI_ZALON_OFFSET 0x800
22		22
23	#define IO_MODULE_EIM (1*4)	23	#define IO_MODULE_EIM (1*4)
24	#define IO_MODULE_DC_ADATA (2*4)	24	#define IO_MODULE_DC_ADATA (2*4)
25	#define IO_MODULE_II_CDATA (3*4)	25	#define IO_MODULE_II_CDATA (3*4)
26	#define IO_MODULE_IO_COMMAND (12*4)	26	#define IO_MODULE_IO_COMMAND (12*4)
27	#define IO_MODULE_IO_STATUS (13*4)	27	#define IO_MODULE_IO_STATUS (13*4)
28		28
29	#define IOSTATUS_RY 0x40	29	#define IOSTATUS_RY 0x40
30	#define IOSTATUS_FE 0x80	30	#define IOSTATUS_FE 0x80
31	#define IOIIDATA_SMINT5L 0x40000000	31	#define IOIIDATA_SMINT5L 0x40000000
32	#define IOIIDATA_MINT5EN 0x20000000	32	#define IOIIDATA_MINT5EN 0x20000000
33	#define IOIIDATA_PACKEN 0x10000000	33	#define IOIIDATA_PACKEN 0x10000000
34	#define IOIIDATA_PREFETCHEN 0x08000000	34	#define IOIIDATA_PREFETCHEN 0x08000000
35	#define IOIIDATA_IOII 0x00000020	35	#define IOIIDATA_IOII 0x00000020
36		36
37	#define CMD_RESET 5	37	#define CMD_RESET 5
38		38
39	static struct ncr_chip zalon720_chip __initdata = {	39	static struct ncr_chip zalon720_chip __initdata = {
40	.revision_id = 0x0f,	40	.revision_id = 0x0f,
41	.burst_max = 3,	41	.burst_max = 3,
42	.offset_max = 8,	42	.offset_max = 8,
43	.nr_divisor = 4,	43	.nr_divisor = 4,
44	.features = FE_WIDE \| FE_DIFF \| FE_EHP\| FE_MUX \| FE_EA,	44	.features = FE_WIDE \| FE_DIFF \| FE_EHP\| FE_MUX \| FE_EA,
45	};	45	};
46		46
47		47
48		48
49	#if 0	49	#if 0
50	/* FIXME:	50	/* FIXME:
51	* Is this function dead code? or is someone planning on using it in the	51	* Is this function dead code? or is someone planning on using it in the
52	* future. The clock = (int) pdc_result[16] does not look correct to	52	* future. The clock = (int) pdc_result[16] does not look correct to
53	* me ... I think it should be iodc_data[16]. Since this cause a compile	53	* me ... I think it should be iodc_data[16]. Since this cause a compile
54	* error with the new encapsulated PDC, I'm not compiling in this function.	54	* error with the new encapsulated PDC, I'm not compiling in this function.
55	* - RB	55	* - RB
56	*/	56	*/
57	/* poke SCSI clock out of iodc data */	57	/* poke SCSI clock out of iodc data */
58		58
59	static u8 iodc_data[32] __attribute__ ((aligned (64)));	59	static u8 iodc_data[32] __attribute__ ((aligned (64)));
60	static unsigned long pdc_result[32] __attribute__ ((aligned (16))) ={0,0,0,0};	60	static unsigned long pdc_result[32] __attribute__ ((aligned (16))) ={0,0,0,0};
61		61
62	static int	62	static int
63	lasi_scsi_clock(void * hpa, int defaultclock)	63	lasi_scsi_clock(void * hpa, int defaultclock)
64	{	64	{
65	int clock, status;	65	int clock, status;
66		66
67	status = pdc_iodc_read(&pdc_result, hpa, 0, &iodc_data, 32 );	67	status = pdc_iodc_read(&pdc_result, hpa, 0, &iodc_data, 32 );
68	if (status == PDC_RET_OK) {	68	if (status == PDC_RET_OK) {
69	clock = (int) pdc_result[16];	69	clock = (int) pdc_result[16];
70	} else {	70	} else {
71	printk(KERN_WARNING "%s: pdc_iodc_read returned %d\n", __FUNCTION__, status);	71	printk(KERN_WARNING "%s: pdc_iodc_read returned %d\n", __FUNCTION__, status);
72	clock = defaultclock;	72	clock = defaultclock;
73	}	73	}
74		74
75	printk(KERN_DEBUG "%s: SCSI clock %d\n", __FUNCTION__, clock);	75	printk(KERN_DEBUG "%s: SCSI clock %d\n", __FUNCTION__, clock);
76	return clock;	76	return clock;
77	}	77	}
78	#endif	78	#endif
79		79
80	static struct scsi_host_template zalon7xx_template = {	80	static struct scsi_host_template zalon7xx_template = {
81	.module = THIS_MODULE,	81	.module = THIS_MODULE,
82	.proc_name = "zalon7xx",	82	.proc_name = "zalon7xx",
83	};	83	};
84		84
85	static int __init	85	static int __init
86	zalon_probe(struct parisc_device *dev)	86	zalon_probe(struct parisc_device *dev)
87	{	87	{
88	struct gsc_irq gsc_irq;	88	struct gsc_irq gsc_irq;
89	u32 zalon_vers;	89	u32 zalon_vers;
90	int error = -ENODEV;	90	int error = -ENODEV;
91	void __iomem *zalon = ioremap(dev->hpa.start, 4096);	91	void __iomem *zalon = ioremap_nocache(dev->hpa.start, 4096);
92	void __iomem *io_port = zalon + GSC_SCSI_ZALON_OFFSET;	92	void __iomem *io_port = zalon + GSC_SCSI_ZALON_OFFSET;
93	static int unit = 0;	93	static int unit = 0;
94	struct Scsi_Host *host;	94	struct Scsi_Host *host;
95	struct ncr_device device;	95	struct ncr_device device;
96		96
97	__raw_writel(CMD_RESET, zalon + IO_MODULE_IO_COMMAND);	97	__raw_writel(CMD_RESET, zalon + IO_MODULE_IO_COMMAND);
98	while (!(__raw_readl(zalon + IO_MODULE_IO_STATUS) & IOSTATUS_RY))	98	while (!(__raw_readl(zalon + IO_MODULE_IO_STATUS) & IOSTATUS_RY))
99	cpu_relax();	99	cpu_relax();
100	__raw_writel(IOIIDATA_MINT5EN \| IOIIDATA_PACKEN \| IOIIDATA_PREFETCHEN,	100	__raw_writel(IOIIDATA_MINT5EN \| IOIIDATA_PACKEN \| IOIIDATA_PREFETCHEN,
101	zalon + IO_MODULE_II_CDATA);	101	zalon + IO_MODULE_II_CDATA);
102		102
103	/* XXX: Save the Zalon version for bug workarounds? */	103	/* XXX: Save the Zalon version for bug workarounds? */
104	zalon_vers = (__raw_readl(zalon + IO_MODULE_II_CDATA) >> 24) & 0x07;	104	zalon_vers = (__raw_readl(zalon + IO_MODULE_II_CDATA) >> 24) & 0x07;
105		105
106	/* Setup the interrupts first.	106	/* Setup the interrupts first.
107	** Later on request_irq() will register the handler.	107	** Later on request_irq() will register the handler.
108	*/	108	*/
109	dev->irq = gsc_alloc_irq(&gsc_irq);	109	dev->irq = gsc_alloc_irq(&gsc_irq);
110		110
111	printk(KERN_INFO "%s: Zalon version %d, IRQ %d\n", __FUNCTION__,	111	printk(KERN_INFO "%s: Zalon version %d, IRQ %d\n", __FUNCTION__,
112	zalon_vers, dev->irq);	112	zalon_vers, dev->irq);
113		113
114	__raw_writel(gsc_irq.txn_addr \| gsc_irq.txn_data, zalon + IO_MODULE_EIM);	114	__raw_writel(gsc_irq.txn_addr \| gsc_irq.txn_data, zalon + IO_MODULE_EIM);
115		115
116	if (zalon_vers == 0)	116	if (zalon_vers == 0)
117	printk(KERN_WARNING "%s: Zalon 1.1 or earlier\n", __FUNCTION__);	117	printk(KERN_WARNING "%s: Zalon 1.1 or earlier\n", __FUNCTION__);
118		118
119	memset(&device, 0, sizeof(struct ncr_device));	119	memset(&device, 0, sizeof(struct ncr_device));
120		120
121	/* The following three are needed before any other access. */	121	/* The following three are needed before any other access. */
122	__raw_writeb(0x20, io_port + 0x38); /* DCNTL_REG, EA */	122	__raw_writeb(0x20, io_port + 0x38); /* DCNTL_REG, EA */
123	__raw_writeb(0x04, io_port + 0x1b); /* CTEST0_REG, EHP */	123	__raw_writeb(0x04, io_port + 0x1b); /* CTEST0_REG, EHP */
124	__raw_writeb(0x80, io_port + 0x22); /* CTEST4_REG, MUX */	124	__raw_writeb(0x80, io_port + 0x22); /* CTEST4_REG, MUX */
125		125
126	/* Initialise ncr_device structure with items required by ncr_attach. */	126	/* Initialise ncr_device structure with items required by ncr_attach. */
127	device.chip = zalon720_chip;	127	device.chip = zalon720_chip;
128	device.host_id = 7;	128	device.host_id = 7;
129	device.dev = &dev->dev;	129	device.dev = &dev->dev;
130	device.slot.base = dev->hpa.start + GSC_SCSI_ZALON_OFFSET;	130	device.slot.base = dev->hpa.start + GSC_SCSI_ZALON_OFFSET;
131	device.slot.base_v = io_port;	131	device.slot.base_v = io_port;
132	device.slot.irq = dev->irq;	132	device.slot.irq = dev->irq;
133	device.differential = 2;	133	device.differential = 2;
134		134
135	host = ncr_attach(&zalon7xx_template, unit, &device);	135	host = ncr_attach(&zalon7xx_template, unit, &device);
136	if (!host)	136	if (!host)
137	goto fail;	137	goto fail;
138		138
139	if (request_irq(dev->irq, ncr53c8xx_intr, SA_SHIRQ, "zalon", host)) {	139	if (request_irq(dev->irq, ncr53c8xx_intr, SA_SHIRQ, "zalon", host)) {
140	printk(KERN_ERR "%s: irq problem with %d, detaching\n ",	140	printk(KERN_ERR "%s: irq problem with %d, detaching\n ",
141	dev->dev.bus_id, dev->irq);	141	dev->dev.bus_id, dev->irq);
142	goto fail;	142	goto fail;
143	}	143	}
144		144
145	unit++;	145	unit++;
146		146
147	dev_set_drvdata(&dev->dev, host);	147	dev_set_drvdata(&dev->dev, host);
148		148
149	error = scsi_add_host(host, &dev->dev);	149	error = scsi_add_host(host, &dev->dev);
150	if (error)	150	if (error)
151	goto fail_free_irq;	151	goto fail_free_irq;
152		152
153	scsi_scan_host(host);	153	scsi_scan_host(host);
154	return 0;	154	return 0;
155		155
156	fail_free_irq:	156	fail_free_irq:
157	free_irq(dev->irq, host);	157	free_irq(dev->irq, host);
158	fail:	158	fail:
159	ncr53c8xx_release(host);	159	ncr53c8xx_release(host);
160	return error;	160	return error;
161	}	161	}
162		162
163	static struct parisc_device_id zalon_tbl[] = {	163	static struct parisc_device_id zalon_tbl[] = {
164	{ HPHW_A_DMA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00089 },	164	{ HPHW_A_DMA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00089 },
165	{ 0, }	165	{ 0, }
166	};	166	};
167		167
168	MODULE_DEVICE_TABLE(parisc, zalon_tbl);	168	MODULE_DEVICE_TABLE(parisc, zalon_tbl);
169		169
170	static int __exit zalon_remove(struct parisc_device *dev)	170	static int __exit zalon_remove(struct parisc_device *dev)
171	{	171	{
172	struct Scsi_Host *host = dev_get_drvdata(&dev->dev);	172	struct Scsi_Host *host = dev_get_drvdata(&dev->dev);
173		173
174	scsi_remove_host(host);	174	scsi_remove_host(host);
175	ncr53c8xx_release(host);	175	ncr53c8xx_release(host);
176	free_irq(dev->irq, host);	176	free_irq(dev->irq, host);
177		177
178	return 0;	178	return 0;
179	}	179	}
180		180
181	static struct parisc_driver zalon_driver = {	181	static struct parisc_driver zalon_driver = {
182	.name = "zalon",	182	.name = "zalon",
183	.id_table = zalon_tbl,	183	.id_table = zalon_tbl,
184	.probe = zalon_probe,	184	.probe = zalon_probe,
185	.remove = __devexit_p(zalon_remove),	185	.remove = __devexit_p(zalon_remove),
186	};	186	};
187		187
188	static int __init zalon7xx_init(void)	188	static int __init zalon7xx_init(void)
189	{	189	{
190	int ret = ncr53c8xx_init();	190	int ret = ncr53c8xx_init();
191	if (!ret)	191	if (!ret)
192	ret = register_parisc_driver(&zalon_driver);	192	ret = register_parisc_driver(&zalon_driver);
193	if (ret)	193	if (ret)
194	ncr53c8xx_exit();	194	ncr53c8xx_exit();
195	return ret;	195	return ret;
196	}	196	}
197		197
198	static void __exit zalon7xx_exit(void)	198	static void __exit zalon7xx_exit(void)
199	{	199	{
200	unregister_parisc_driver(&zalon_driver);	200	unregister_parisc_driver(&zalon_driver);
201	ncr53c8xx_exit();	201	ncr53c8xx_exit();
202	}	202	}
203		203
204	module_init(zalon7xx_init);	204	module_init(zalon7xx_init);
205	module_exit(zalon7xx_exit);	205	module_exit(zalon7xx_exit);
206		206

drivers/serial/8250_gsc.c

Diff comments View file @ 5076c15

 /*
  *	Serial Device Initialisation for Lasi/Asp/Wax/Dino
  *
  *	(c) Copyright Matthew Wilcox <willy@debian.org> 2001-2002
  *
  *	This program is free software; you can redistribute it and/or modify
  *	it under the terms of the GNU General Public License as published by
  *      the Free Software Foundation; either version 2 of the License, or
  *      (at your option) any later version.
  */
 #include <linux/errno.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/module.h>
 #include <linux/serial_core.h>
 #include <linux/signal.h>
 #include <linux/slab.h>
 #include <linux/types.h>
 #include <asm/hardware.h>
 #include <asm/parisc-device.h>
 #include <asm/io.h>
 #include <asm/serial.h> /* for LASI_BASE_BAUD */
 #include "8250.h"
 static int __init
 serial_init_chip(struct parisc_device *dev)
 {
 	struct uart_port port;
 	unsigned long address;
 	int err;
 	if (!dev->irq) {
 		/* We find some unattached serial ports by walking native
 		 * busses.  These should be silently ignored.  Otherwise,
 		 * what we have here is a missing parent device, so tell
 		 * the user what they're missing.
 		 */
 		if (parisc_parent(dev)->id.hw_type != HPHW_IOA) {
 			printk(KERN_INFO "Serial: device 0x%lx not configured.\n"
 				"Enable support for Wax, Lasi, Asp or Dino.\n",
 				dev->hpa.start);
 		}
 		return -ENODEV;
 	}
 	address = dev->hpa.start;
 	if (dev->id.sversion != 0x8d) {
 		address += 0x800;
 	}
-	memset(&port, 0, sizeof(struct uart_port));
+	memset(&port, 0, sizeof(port));
-	port.mapbase = address;
+	port.iotype	= UPIO_MEM;
-	port.irq = dev->irq;
+	port.uartclk	= LASI_BASE_BAUD * 16;
-	port.iotype = UPIO_MEM;
+	port.mapbase	= address;
-	port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
+	port.membase	= ioremap_nocache(address, 16);
-	port.uartclk = LASI_BASE_BAUD * 16;
+	port.irq	= dev->irq;
-	port.dev = &dev->dev;
+	port.flags	= UPF_BOOT_AUTOCONF;
+	port.dev	= &dev->dev;
 	err = serial8250_register_port(&port);
 	if (err < 0) {
 		printk(KERN_WARNING "serial8250_register_port returned error %d\n", err);
 		return err;
 	}
 	return 0;
 }
 static struct parisc_device_id serial_tbl[] = {
 	{ HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00075 },
 	{ HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x0008c },
 	{ HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x0008d },
 	{ 0 }
 };
 /* Hack.  Some machines have SERIAL_0 attached to Lasi and SERIAL_1
  * attached to Dino.  Unfortunately, Dino appears before Lasi in the device
  * tree.  To ensure that ttyS0 == SERIAL_0, we register two drivers; one
  * which only knows about Lasi and then a second which will find all the
  * other serial ports.  HPUX ignores this problem.
  */
 static struct parisc_device_id lasi_tbl[] = {
 	{ HPHW_FIO, HVERSION_REV_ANY_ID, 0x03B, 0x0008C }, /* C1xx/C1xxL */
 	{ HPHW_FIO, HVERSION_REV_ANY_ID, 0x03C, 0x0008C }, /* B132L */
 	{ HPHW_FIO, HVERSION_REV_ANY_ID, 0x03D, 0x0008C }, /* B160L */
 	{ HPHW_FIO, HVERSION_REV_ANY_ID, 0x03E, 0x0008C }, /* B132L+ */
 	{ HPHW_FIO, HVERSION_REV_ANY_ID, 0x03F, 0x0008C }, /* B180L+ */
 	{ HPHW_FIO, HVERSION_REV_ANY_ID, 0x046, 0x0008C }, /* Rocky2 120 */
 	{ HPHW_FIO, HVERSION_REV_ANY_ID, 0x047, 0x0008C }, /* Rocky2 150 */
 	{ HPHW_FIO, HVERSION_REV_ANY_ID, 0x04E, 0x0008C }, /* Kiji L2 132 */
 	{ HPHW_FIO, HVERSION_REV_ANY_ID, 0x056, 0x0008C }, /* Raven+ */
 	{ 0 }
 };
 MODULE_DEVICE_TABLE(parisc, serial_tbl);
 static struct parisc_driver lasi_driver = {
 	.name		= "serial_1",
 	.id_table	= lasi_tbl,
 	.probe		= serial_init_chip,
 };
 static struct parisc_driver serial_driver = {
 	.name		= "serial",
 	.id_table	= serial_tbl,
 	.probe		= serial_init_chip,
 };
 int __init probe_serial_gsc(void)
 {
 	register_parisc_driver(&lasi_driver);
 	register_parisc_driver(&serial_driver);
 	return 0;
 }
 module_init(probe_serial_gsc);

drivers/serial/mux.c

Diff comments View file @ 5076c15

1	/*	1	/*
2	** mux.c:	2	** mux.c:
3	** serial driver for the Mux console found in some PA-RISC servers.	3	** serial driver for the Mux console found in some PA-RISC servers.
4	**	4	**
5	** (c) Copyright 2002 Ryan Bradetich	5	** (c) Copyright 2002 Ryan Bradetich
6	** (c) Copyright 2002 Hewlett-Packard Company	6	** (c) Copyright 2002 Hewlett-Packard Company
7	**	7	**
8	** This program is free software; you can redistribute it and/or modify	8	** This program is free software; you can redistribute it and/or modify
9	** it under the terms of the GNU General Public License as published by	9	** it under the terms of the GNU General Public License as published by
10	** the Free Software Foundation; either version 2 of the License, or	10	** the Free Software Foundation; either version 2 of the License, or
11	** (at your option) any later version.	11	** (at your option) any later version.
12	**	12	**
13	** This Driver currently only supports the console (port 0) on the MUX.	13	** This Driver currently only supports the console (port 0) on the MUX.
14	** Additional work will be needed on this driver to enable the full	14	** Additional work will be needed on this driver to enable the full
15	** functionality of the MUX.	15	** functionality of the MUX.
16	**	16	**
17	*/	17	*/
18		18
19	#include <linux/config.h>	19	#include <linux/config.h>
20	#include <linux/module.h>	20	#include <linux/module.h>
21	#include <linux/tty.h>	21	#include <linux/tty.h>
22	#include <linux/ioport.h>	22	#include <linux/ioport.h>
23	#include <linux/init.h>	23	#include <linux/init.h>
24	#include <linux/serial.h>	24	#include <linux/serial.h>
25	#include <linux/console.h>	25	#include <linux/console.h>
26	#include <linux/slab.h>	26	#include <linux/slab.h>
27	#include <linux/delay.h> /* for udelay */	27	#include <linux/delay.h> /* for udelay */
28	#include <linux/device.h>	28	#include <linux/device.h>
29	#include <asm/io.h>	29	#include <asm/io.h>
30	#include <asm/irq.h>	30	#include <asm/irq.h>
31	#include <asm/parisc-device.h>	31	#include <asm/parisc-device.h>
32		32
33	#ifdef CONFIG_MAGIC_SYSRQ	33	#ifdef CONFIG_MAGIC_SYSRQ
34	#include <linux/sysrq.h>	34	#include <linux/sysrq.h>
35	#define SUPPORT_SYSRQ	35	#define SUPPORT_SYSRQ
36	#endif	36	#endif
37		37
38	#include <linux/serial_core.h>	38	#include <linux/serial_core.h>
39		39
40	#define MUX_OFFSET 0x800	40	#define MUX_OFFSET 0x800
41	#define MUX_LINE_OFFSET 0x80	41	#define MUX_LINE_OFFSET 0x80
42		42
43	#define MUX_FIFO_SIZE 255	43	#define MUX_FIFO_SIZE 255
44	#define MUX_POLL_DELAY (30 * HZ / 1000)	44	#define MUX_POLL_DELAY (30 * HZ / 1000)
45		45
46	#define IO_DATA_REG_OFFSET 0x3c	46	#define IO_DATA_REG_OFFSET 0x3c
47	#define IO_DCOUNT_REG_OFFSET 0x40	47	#define IO_DCOUNT_REG_OFFSET 0x40
48		48
49	#define MUX_EOFIFO(status) ((status & 0xF000) == 0xF000)	49	#define MUX_EOFIFO(status) ((status & 0xF000) == 0xF000)
50	#define MUX_STATUS(status) ((status & 0xF000) == 0x8000)	50	#define MUX_STATUS(status) ((status & 0xF000) == 0x8000)
51	#define MUX_BREAK(status) ((status & 0xF000) == 0x2000)	51	#define MUX_BREAK(status) ((status & 0xF000) == 0x2000)
52		52
53	#define MUX_NR 256	53	#define MUX_NR 256
54	static unsigned int port_cnt = 0;	54	static unsigned int port_cnt __read_mostly;
55	static struct uart_port mux_ports[MUX_NR];	55	static struct uart_port mux_ports[MUX_NR];
56		56
57	static struct uart_driver mux_driver = {	57	static struct uart_driver mux_driver = {
58	.owner = THIS_MODULE,	58	.owner = THIS_MODULE,
59	.driver_name = "ttyB",	59	.driver_name = "ttyB",
60	.dev_name = "ttyB",	60	.dev_name = "ttyB",
61	.major = MUX_MAJOR,	61	.major = MUX_MAJOR,
62	.minor = 0,	62	.minor = 0,
63	.nr = MUX_NR,	63	.nr = MUX_NR,
64	};	64	};
65		65
66	static struct timer_list mux_timer;	66	static struct timer_list mux_timer;
67		67
68	#define UART_PUT_CHAR(p, c) __raw_writel((c), (p)->membase + IO_DATA_REG_OFFSET)	68	#define UART_PUT_CHAR(p, c) __raw_writel((c), (p)->membase + IO_DATA_REG_OFFSET)
69	#define UART_GET_FIFO_CNT(p) __raw_readl((p)->membase + IO_DCOUNT_REG_OFFSET)	69	#define UART_GET_FIFO_CNT(p) __raw_readl((p)->membase + IO_DCOUNT_REG_OFFSET)
70	#define GET_MUX_PORTS(iodc_data) ((((iodc_data)[4] & 0xf0) >> 4) * 8) + 8	70	#define GET_MUX_PORTS(iodc_data) ((((iodc_data)[4] & 0xf0) >> 4) * 8) + 8
71		71
72	/**	72	/**
73	* mux_tx_empty - Check if the transmitter fifo is empty.	73	* mux_tx_empty - Check if the transmitter fifo is empty.
74	* @port: Ptr to the uart_port.	74	* @port: Ptr to the uart_port.
75	*	75	*
76	* This function test if the transmitter fifo for the port	76	* This function test if the transmitter fifo for the port
77	* described by 'port' is empty. If it is empty, this function	77	* described by 'port' is empty. If it is empty, this function
78	* should return TIOCSER_TEMT, otherwise return 0.	78	* should return TIOCSER_TEMT, otherwise return 0.
79	*/	79	*/
80	static unsigned int mux_tx_empty(struct uart_port *port)	80	static unsigned int mux_tx_empty(struct uart_port *port)
81	{	81	{
82	return UART_GET_FIFO_CNT(port) ? 0 : TIOCSER_TEMT;	82	return UART_GET_FIFO_CNT(port) ? 0 : TIOCSER_TEMT;
83	}	83	}
84		84
85	/**	85	/**
86	* mux_set_mctrl - Set the current state of the modem control inputs.	86	* mux_set_mctrl - Set the current state of the modem control inputs.
87	* @ports: Ptr to the uart_port.	87	* @ports: Ptr to the uart_port.
88	* @mctrl: Modem control bits.	88	* @mctrl: Modem control bits.
89	*	89	*
90	* The Serial MUX does not support CTS, DCD or DSR so this function	90	* The Serial MUX does not support CTS, DCD or DSR so this function
91	* is ignored.	91	* is ignored.
92	*/	92	*/
93	static void mux_set_mctrl(struct uart_port *port, unsigned int mctrl)	93	static void mux_set_mctrl(struct uart_port *port, unsigned int mctrl)
94	{	94	{
95	}	95	}
96		96
97	/**	97	/**
98	* mux_get_mctrl - Returns the current state of modem control inputs.	98	* mux_get_mctrl - Returns the current state of modem control inputs.
99	* @port: Ptr to the uart_port.	99	* @port: Ptr to the uart_port.
100	*	100	*
101	* The Serial MUX does not support CTS, DCD or DSR so these lines are	101	* The Serial MUX does not support CTS, DCD or DSR so these lines are
102	* treated as permanently active.	102	* treated as permanently active.
103	*/	103	*/
104	static unsigned int mux_get_mctrl(struct uart_port *port)	104	static unsigned int mux_get_mctrl(struct uart_port *port)
105	{	105	{
106	return TIOCM_CAR \| TIOCM_DSR \| TIOCM_CTS;	106	return TIOCM_CAR \| TIOCM_DSR \| TIOCM_CTS;
107	}	107	}
108		108
109	/**	109	/**
110	* mux_stop_tx - Stop transmitting characters.	110	* mux_stop_tx - Stop transmitting characters.
111	* @port: Ptr to the uart_port.	111	* @port: Ptr to the uart_port.
112	*	112	*
113	* The Serial MUX does not support this function.	113	* The Serial MUX does not support this function.
114	*/	114	*/
115	static void mux_stop_tx(struct uart_port *port)	115	static void mux_stop_tx(struct uart_port *port)
116	{	116	{
117	}	117	}
118		118
119	/**	119	/**
120	* mux_start_tx - Start transmitting characters.	120	* mux_start_tx - Start transmitting characters.
121	* @port: Ptr to the uart_port.	121	* @port: Ptr to the uart_port.
122	*	122	*
123	* The Serial Mux does not support this function.	123	* The Serial Mux does not support this function.
124	*/	124	*/
125	static void mux_start_tx(struct uart_port *port)	125	static void mux_start_tx(struct uart_port *port)
126	{	126	{
127	}	127	}
128		128
129	/**	129	/**
130	* mux_stop_rx - Stop receiving characters.	130	* mux_stop_rx - Stop receiving characters.
131	* @port: Ptr to the uart_port.	131	* @port: Ptr to the uart_port.
132	*	132	*
133	* The Serial Mux does not support this function.	133	* The Serial Mux does not support this function.
134	*/	134	*/
135	static void mux_stop_rx(struct uart_port *port)	135	static void mux_stop_rx(struct uart_port *port)
136	{	136	{
137	}	137	}
138		138
139	/**	139	/**
140	* mux_enable_ms - Enable modum status interrupts.	140	* mux_enable_ms - Enable modum status interrupts.
141	* @port: Ptr to the uart_port.	141	* @port: Ptr to the uart_port.
142	*	142	*
143	* The Serial Mux does not support this function.	143	* The Serial Mux does not support this function.
144	*/	144	*/
145	static void mux_enable_ms(struct uart_port *port)	145	static void mux_enable_ms(struct uart_port *port)
146	{	146	{
147	}	147	}
148		148
149	/**	149	/**
150	* mux_break_ctl - Control the transmitssion of a break signal.	150	* mux_break_ctl - Control the transmitssion of a break signal.
151	* @port: Ptr to the uart_port.	151	* @port: Ptr to the uart_port.
152	* @break_state: Raise/Lower the break signal.	152	* @break_state: Raise/Lower the break signal.
153	*	153	*
154	* The Serial Mux does not support this function.	154	* The Serial Mux does not support this function.
155	*/	155	*/
156	static void mux_break_ctl(struct uart_port *port, int break_state)	156	static void mux_break_ctl(struct uart_port *port, int break_state)
157	{	157	{
158	}	158	}
159		159
160	/**	160	/**
161	* mux_write - Write chars to the mux fifo.	161	* mux_write - Write chars to the mux fifo.
162	* @port: Ptr to the uart_port.	162	* @port: Ptr to the uart_port.
163	*	163	*
164	* This function writes all the data from the uart buffer to	164	* This function writes all the data from the uart buffer to
165	* the mux fifo.	165	* the mux fifo.
166	*/	166	*/
167	static void mux_write(struct uart_port *port)	167	static void mux_write(struct uart_port *port)
168	{	168	{
169	int count;	169	int count;
170	struct circ_buf *xmit = &port->info->xmit;	170	struct circ_buf *xmit = &port->info->xmit;
171		171
172	if(port->x_char) {	172	if(port->x_char) {
173	UART_PUT_CHAR(port, port->x_char);	173	UART_PUT_CHAR(port, port->x_char);
174	port->icount.tx++;	174	port->icount.tx++;
175	port->x_char = 0;	175	port->x_char = 0;
176	return;	176	return;
177	}	177	}
178		178
179	if(uart_circ_empty(xmit) \|\| uart_tx_stopped(port)) {	179	if(uart_circ_empty(xmit) \|\| uart_tx_stopped(port)) {
180	mux_stop_tx(port);	180	mux_stop_tx(port);
181	return;	181	return;
182	}	182	}
183		183
184	count = (port->fifosize) - UART_GET_FIFO_CNT(port);	184	count = (port->fifosize) - UART_GET_FIFO_CNT(port);
185	do {	185	do {
186	UART_PUT_CHAR(port, xmit->buf[xmit->tail]);	186	UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
187	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);	187	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
188	port->icount.tx++;	188	port->icount.tx++;
189	if(uart_circ_empty(xmit))	189	if(uart_circ_empty(xmit))
190	break;	190	break;
191		191
192	} while(--count > 0);	192	} while(--count > 0);
193		193
194	while(UART_GET_FIFO_CNT(port))	194	while(UART_GET_FIFO_CNT(port))
195	udelay(1);	195	udelay(1);
196		196
197	if(uart_circ_chars_pending(xmit) < WAKEUP_CHARS)	197	if(uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
198	uart_write_wakeup(port);	198	uart_write_wakeup(port);
199		199
200	if (uart_circ_empty(xmit))	200	if (uart_circ_empty(xmit))
201	mux_stop_tx(port);	201	mux_stop_tx(port);
202	}	202	}
203		203
204	/**	204	/**
205	* mux_read - Read chars from the mux fifo.	205	* mux_read - Read chars from the mux fifo.
206	* @port: Ptr to the uart_port.	206	* @port: Ptr to the uart_port.
207	*	207	*
208	* This reads all available data from the mux's fifo and pushes	208	* This reads all available data from the mux's fifo and pushes
209	* the data to the tty layer.	209	* the data to the tty layer.
210	*/	210	*/
211	static void mux_read(struct uart_port *port)	211	static void mux_read(struct uart_port *port)
212	{	212	{
213	int data;	213	int data;
214	struct tty_struct *tty = port->info->tty;	214	struct tty_struct *tty = port->info->tty;
215	__u32 start_count = port->icount.rx;	215	__u32 start_count = port->icount.rx;
216		216
217	while(1) {	217	while(1) {
218	data = __raw_readl(port->membase + IO_DATA_REG_OFFSET);	218	data = __raw_readl(port->membase + IO_DATA_REG_OFFSET);
219		219
220	if (MUX_STATUS(data))	220	if (MUX_STATUS(data))
221	continue;	221	continue;
222		222
223	if (MUX_EOFIFO(data))	223	if (MUX_EOFIFO(data))
224	break;	224	break;
225		225
226	port->icount.rx++;	226	port->icount.rx++;
227		227
228	if (MUX_BREAK(data)) {	228	if (MUX_BREAK(data)) {
229	port->icount.brk++;	229	port->icount.brk++;
230	if(uart_handle_break(port))	230	if(uart_handle_break(port))
231	continue;	231	continue;
232	}	232	}
233		233
234	if (uart_handle_sysrq_char(port, data & 0xffu, NULL))	234	if (uart_handle_sysrq_char(port, data & 0xffu, NULL))
235	continue;	235	continue;
236		236
237	tty_insert_flip_char(tty, data & 0xFF, TTY_NORMAL);	237	tty_insert_flip_char(tty, data & 0xFF, TTY_NORMAL);
238	}	238	}
239		239
240	if (start_count != port->icount.rx) {	240	if (start_count != port->icount.rx) {
241	tty_flip_buffer_push(tty);	241	tty_flip_buffer_push(tty);
242	}	242	}
243	}	243	}
244		244
245	/**	245	/**
246	* mux_startup - Initialize the port.	246	* mux_startup - Initialize the port.
247	* @port: Ptr to the uart_port.	247	* @port: Ptr to the uart_port.
248	*	248	*
249	* Grab any resources needed for this port and start the	249	* Grab any resources needed for this port and start the
250	* mux timer.	250	* mux timer.
251	*/	251	*/
252	static int mux_startup(struct uart_port *port)	252	static int mux_startup(struct uart_port *port)
253	{	253	{
254	mod_timer(&mux_timer, jiffies + MUX_POLL_DELAY);	254	mod_timer(&mux_timer, jiffies + MUX_POLL_DELAY);
255	return 0;	255	return 0;
256	}	256	}
257		257
258	/**	258	/**
259	* mux_shutdown - Disable the port.	259	* mux_shutdown - Disable the port.
260	* @port: Ptr to the uart_port.	260	* @port: Ptr to the uart_port.
261	*	261	*
262	* Release any resources needed for the port.	262	* Release any resources needed for the port.
263	*/	263	*/
264	static void mux_shutdown(struct uart_port *port)	264	static void mux_shutdown(struct uart_port *port)
265	{	265	{
266	}	266	}
267		267
268	/**	268	/**
269	* mux_set_termios - Chane port parameters.	269	* mux_set_termios - Chane port parameters.
270	* @port: Ptr to the uart_port.	270	* @port: Ptr to the uart_port.
271	* @termios: new termios settings.	271	* @termios: new termios settings.
272	* @old: old termios settings.	272	* @old: old termios settings.
273	*	273	*
274	* The Serial Mux does not support this function.	274	* The Serial Mux does not support this function.
275	*/	275	*/
276	static void	276	static void
277	mux_set_termios(struct uart_port port, struct termios termios,	277	mux_set_termios(struct uart_port port, struct termios termios,
278	struct termios *old)	278	struct termios *old)
279	{	279	{
280	}	280	}
281		281
282	/**	282	/**
283	* mux_type - Describe the port.	283	* mux_type - Describe the port.
284	* @port: Ptr to the uart_port.	284	* @port: Ptr to the uart_port.
285	*	285	*
286	* Return a pointer to a string constant describing the	286	* Return a pointer to a string constant describing the
287	* specified port.	287	* specified port.
288	*/	288	*/
289	static const char mux_type(struct uart_port port)	289	static const char mux_type(struct uart_port port)
290	{	290	{
291	return "Mux";	291	return "Mux";
292	}	292	}
293		293
294	/**	294	/**
295	* mux_release_port - Release memory and IO regions.	295	* mux_release_port - Release memory and IO regions.
296	* @port: Ptr to the uart_port.	296	* @port: Ptr to the uart_port.
297	*	297	*
298	* Release any memory and IO region resources currently in use by	298	* Release any memory and IO region resources currently in use by
299	* the port.	299	* the port.
300	*/	300	*/
301	static void mux_release_port(struct uart_port *port)	301	static void mux_release_port(struct uart_port *port)
302	{	302	{
303	}	303	}
304		304
305	/**	305	/**
306	* mux_request_port - Request memory and IO regions.	306	* mux_request_port - Request memory and IO regions.
307	* @port: Ptr to the uart_port.	307	* @port: Ptr to the uart_port.
308	*	308	*
309	* Request any memory and IO region resources required by the port.	309	* Request any memory and IO region resources required by the port.
310	* If any fail, no resources should be registered when this function	310	* If any fail, no resources should be registered when this function
311	* returns, and it should return -EBUSY on failure.	311	* returns, and it should return -EBUSY on failure.
312	*/	312	*/
313	static int mux_request_port(struct uart_port *port)	313	static int mux_request_port(struct uart_port *port)
314	{	314	{
315	return 0;	315	return 0;
316	}	316	}
317		317
318	/**	318	/**
319	* mux_config_port - Perform port autoconfiguration.	319	* mux_config_port - Perform port autoconfiguration.
320	* @port: Ptr to the uart_port.	320	* @port: Ptr to the uart_port.
321	* @type: Bitmask of required configurations.	321	* @type: Bitmask of required configurations.
322	*	322	*
323	* Perform any autoconfiguration steps for the port. This functino is	323	* Perform any autoconfiguration steps for the port. This functino is
324	* called if the UPF_BOOT_AUTOCONF flag is specified for the port.	324	* called if the UPF_BOOT_AUTOCONF flag is specified for the port.
325	* [Note: This is required for now because of a bug in the Serial core.	325	* [Note: This is required for now because of a bug in the Serial core.
326	* rmk has already submitted a patch to linus, should be available for	326	* rmk has already submitted a patch to linus, should be available for
327	* 2.5.47.]	327	* 2.5.47.]
328	*/	328	*/
329	static void mux_config_port(struct uart_port *port, int type)	329	static void mux_config_port(struct uart_port *port, int type)
330	{	330	{
331	port->type = PORT_MUX;	331	port->type = PORT_MUX;
332	}	332	}
333		333
334	/**	334	/**
335	* mux_verify_port - Verify the port information.	335	* mux_verify_port - Verify the port information.
336	* @port: Ptr to the uart_port.	336	* @port: Ptr to the uart_port.
337	* @ser: Ptr to the serial information.	337	* @ser: Ptr to the serial information.
338	*	338	*
339	* Verify the new serial port information contained within serinfo is	339	* Verify the new serial port information contained within serinfo is
340	* suitable for this port type.	340	* suitable for this port type.
341	*/	341	*/
342	static int mux_verify_port(struct uart_port port, struct serial_struct ser)	342	static int mux_verify_port(struct uart_port port, struct serial_struct ser)
343	{	343	{
344	if(port->membase == NULL)	344	if(port->membase == NULL)
345	return -EINVAL;	345	return -EINVAL;
346		346
347	return 0;	347	return 0;
348	}	348	}
349		349
350	/**	350	/**
351	* mux_drv_poll - Mux poll function.	351	* mux_drv_poll - Mux poll function.
352	* @unused: Unused variable	352	* @unused: Unused variable
353	*	353	*
354	* This function periodically polls the Serial MUX to check for new data.	354	* This function periodically polls the Serial MUX to check for new data.
355	*/	355	*/
356	static void mux_poll(unsigned long unused)	356	static void mux_poll(unsigned long unused)
357	{	357	{
358	int i;	358	int i;
359		359
360	for(i = 0; i < port_cnt; ++i) {	360	for(i = 0; i < port_cnt; ++i) {
361	if(!mux_ports[i].info)	361	if(!mux_ports[i].info)
362	continue;	362	continue;
363		363
364	mux_read(&mux_ports[i]);	364	mux_read(&mux_ports[i]);
365	mux_write(&mux_ports[i]);	365	mux_write(&mux_ports[i]);
366	}	366	}
367		367
368	mod_timer(&mux_timer, jiffies + MUX_POLL_DELAY);	368	mod_timer(&mux_timer, jiffies + MUX_POLL_DELAY);
369	}	369	}
370		370
371		371
372	#ifdef CONFIG_SERIAL_MUX_CONSOLE	372	#ifdef CONFIG_SERIAL_MUX_CONSOLE
373	static void mux_console_write(struct console co, const char s, unsigned count)	373	static void mux_console_write(struct console co, const char s, unsigned count)
374	{	374	{
375	while(count--)	375	while(count--)
376	pdc_iodc_putc(*s++);	376	pdc_iodc_putc(*s++);
377	}	377	}
378		378
379	static int mux_console_setup(struct console co, char options)	379	static int mux_console_setup(struct console co, char options)
380	{	380	{
381	return 0;	381	return 0;
382	}	382	}
383		383
384	struct tty_driver mux_console_device(struct console co, int *index)	384	struct tty_driver mux_console_device(struct console co, int *index)
385	{	385	{
386	*index = co->index;	386	*index = co->index;
387	return mux_driver.tty_driver;	387	return mux_driver.tty_driver;
388	}	388	}
389		389
390	static struct console mux_console = {	390	static struct console mux_console = {
391	.name = "ttyB",	391	.name = "ttyB",
392	.write = mux_console_write,	392	.write = mux_console_write,
393	.device = mux_console_device,	393	.device = mux_console_device,
394	.setup = mux_console_setup,	394	.setup = mux_console_setup,
395	.flags = CON_ENABLED \| CON_PRINTBUFFER,	395	.flags = CON_ENABLED \| CON_PRINTBUFFER,
396	.index = 0,	396	.index = 0,
397	};	397	};
398		398
399	#define MUX_CONSOLE &mux_console	399	#define MUX_CONSOLE &mux_console
400	#else	400	#else
401	#define MUX_CONSOLE NULL	401	#define MUX_CONSOLE NULL
402	#endif	402	#endif
403		403
404	static struct uart_ops mux_pops = {	404	static struct uart_ops mux_pops = {
405	.tx_empty = mux_tx_empty,	405	.tx_empty = mux_tx_empty,
406	.set_mctrl = mux_set_mctrl,	406	.set_mctrl = mux_set_mctrl,
407	.get_mctrl = mux_get_mctrl,	407	.get_mctrl = mux_get_mctrl,
408	.stop_tx = mux_stop_tx,	408	.stop_tx = mux_stop_tx,
409	.start_tx = mux_start_tx,	409	.start_tx = mux_start_tx,
410	.stop_rx = mux_stop_rx,	410	.stop_rx = mux_stop_rx,
411	.enable_ms = mux_enable_ms,	411	.enable_ms = mux_enable_ms,
412	.break_ctl = mux_break_ctl,	412	.break_ctl = mux_break_ctl,
413	.startup = mux_startup,	413	.startup = mux_startup,
414	.shutdown = mux_shutdown,	414	.shutdown = mux_shutdown,
415	.set_termios = mux_set_termios,	415	.set_termios = mux_set_termios,
416	.type = mux_type,	416	.type = mux_type,
417	.release_port = mux_release_port,	417	.release_port = mux_release_port,
418	.request_port = mux_request_port,	418	.request_port = mux_request_port,
419	.config_port = mux_config_port,	419	.config_port = mux_config_port,
420	.verify_port = mux_verify_port,	420	.verify_port = mux_verify_port,
421	};	421	};
422		422
423	/**	423	/**
424	* mux_probe - Determine if the Serial Mux should claim this device.	424	* mux_probe - Determine if the Serial Mux should claim this device.
425	* @dev: The parisc device.	425	* @dev: The parisc device.
426	*	426	*
427	* Deterimine if the Serial Mux should claim this chip (return 0)	427	* Deterimine if the Serial Mux should claim this chip (return 0)
428	* or not (return 1).	428	* or not (return 1).
429	*/	429	*/
430	static int __init mux_probe(struct parisc_device *dev)	430	static int __init mux_probe(struct parisc_device *dev)
431	{	431	{
432	int i, status, ports;	432	int i, status, ports;
433	u8 iodc_data[32];	433	u8 iodc_data[32];
434	unsigned long bytecnt;	434	unsigned long bytecnt;
435	struct uart_port *port;	435	struct uart_port *port;
436		436
437	status = pdc_iodc_read(&bytecnt, dev->hpa.start, 0, iodc_data, 32);	437	status = pdc_iodc_read(&bytecnt, dev->hpa.start, 0, iodc_data, 32);
438	if(status != PDC_OK) {	438	if(status != PDC_OK) {
439	printk(KERN_ERR "Serial mux: Unable to read IODC.\n");	439	printk(KERN_ERR "Serial mux: Unable to read IODC.\n");
440	return 1;	440	return 1;
441	}	441	}
442		442
443	ports = GET_MUX_PORTS(iodc_data);	443	ports = GET_MUX_PORTS(iodc_data);
444	printk(KERN_INFO "Serial mux driver (%d ports) Revision: 0.3\n", ports);	444	printk(KERN_INFO "Serial mux driver (%d ports) Revision: 0.3\n", ports);
445		445
446	if(!port_cnt) {	446	if(!port_cnt) {
447	mux_driver.cons = MUX_CONSOLE;	447	mux_driver.cons = MUX_CONSOLE;
448		448
449	status = uart_register_driver(&mux_driver);	449	status = uart_register_driver(&mux_driver);
450	if(status) {	450	if(status) {
451	printk(KERN_ERR "Serial mux: Unable to register driver.\n");	451	printk(KERN_ERR "Serial mux: Unable to register driver.\n");
452	return 1;	452	return 1;
453	}	453	}
454		454
455	init_timer(&mux_timer);	455	init_timer(&mux_timer);
456	mux_timer.function = mux_poll;	456	mux_timer.function = mux_poll;
457	}	457	}
458		458
459	for(i = 0; i < ports; ++i, ++port_cnt) {	459	for(i = 0; i < ports; ++i, ++port_cnt) {
460	port = &mux_ports[port_cnt];	460	port = &mux_ports[port_cnt];
461	port->iobase = 0;	461	port->iobase = 0;
462	port->mapbase = dev->hpa.start + MUX_OFFSET +	462	port->mapbase = dev->hpa.start + MUX_OFFSET +
463	(i * MUX_LINE_OFFSET);	463	(i * MUX_LINE_OFFSET);
464	port->membase = ioremap(port->mapbase, MUX_LINE_OFFSET);	464	port->membase = ioremap_nocache(port->mapbase, MUX_LINE_OFFSET);
465	port->iotype = UPIO_MEM;	465	port->iotype = UPIO_MEM;
466	port->type = PORT_MUX;	466	port->type = PORT_MUX;
467	port->irq = NO_IRQ;	467	port->irq = NO_IRQ;
468	port->uartclk = 0;	468	port->uartclk = 0;
469	port->fifosize = MUX_FIFO_SIZE;	469	port->fifosize = MUX_FIFO_SIZE;
470	port->ops = &mux_pops;	470	port->ops = &mux_pops;
471	port->flags = UPF_BOOT_AUTOCONF;	471	port->flags = UPF_BOOT_AUTOCONF;
472	port->line = port_cnt;	472	port->line = port_cnt;
473		473
474	/* The port->timeout needs to match what is present in	474	/* The port->timeout needs to match what is present in
475	* uart_wait_until_sent in serial_core.c. Otherwise	475	* uart_wait_until_sent in serial_core.c. Otherwise
476	* the time spent in msleep_interruptable will be very	476	* the time spent in msleep_interruptable will be very
477	* long, causing the appearance of a console hang.	477	* long, causing the appearance of a console hang.
478	*/	478	*/
479	port->timeout = HZ / 50;	479	port->timeout = HZ / 50;
480	spin_lock_init(&port->lock);	480	spin_lock_init(&port->lock);
481	status = uart_add_one_port(&mux_driver, port);	481	status = uart_add_one_port(&mux_driver, port);
482	BUG_ON(status);	482	BUG_ON(status);
483	}	483	}
484		484
485	#ifdef CONFIG_SERIAL_MUX_CONSOLE	485	#ifdef CONFIG_SERIAL_MUX_CONSOLE
486	register_console(&mux_console);	486	register_console(&mux_console);
487	#endif	487	#endif
488	return 0;	488	return 0;
489	}	489	}
490		490
491	static struct parisc_device_id mux_tbl[] = {	491	static struct parisc_device_id mux_tbl[] = {
492	{ HPHW_A_DIRECT, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x0000D },	492	{ HPHW_A_DIRECT, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x0000D },
493	{ 0, }	493	{ 0, }
494	};	494	};
495		495
496	MODULE_DEVICE_TABLE(parisc, mux_tbl);	496	MODULE_DEVICE_TABLE(parisc, mux_tbl);
497		497
498	static struct parisc_driver serial_mux_driver = {	498	static struct parisc_driver serial_mux_driver = {
499	.name = "serial_mux",	499	.name = "serial_mux",
500	.id_table = mux_tbl,	500	.id_table = mux_tbl,
501	.probe = mux_probe,	501	.probe = mux_probe,
502	};	502	};
503		503
504	/**	504	/**
505	* mux_init - Serial MUX initalization procedure.	505	* mux_init - Serial MUX initalization procedure.
506	*	506	*
507	* Register the Serial MUX driver.	507	* Register the Serial MUX driver.
508	*/	508	*/
509	static int __init mux_init(void)	509	static int __init mux_init(void)
510	{	510	{
511	return register_parisc_driver(&serial_mux_driver);	511	return register_parisc_driver(&serial_mux_driver);
512	}	512	}
513		513
514	/**	514	/**
515	* mux_exit - Serial MUX cleanup procedure.	515	* mux_exit - Serial MUX cleanup procedure.
516	*	516	*
517	* Unregister the Serial MUX driver from the tty layer.	517	* Unregister the Serial MUX driver from the tty layer.
518	*/	518	*/
519	static void __exit mux_exit(void)	519	static void __exit mux_exit(void)
520	{	520	{
521	int i;	521	int i;
522		522
523	for (i = 0; i < port_cnt; i++) {	523	for (i = 0; i < port_cnt; i++) {
524	uart_remove_one_port(&mux_driver, &mux_ports[i]);	524	uart_remove_one_port(&mux_driver, &mux_ports[i]);
525	}	525	}
526		526
527	uart_unregister_driver(&mux_driver);	527	uart_unregister_driver(&mux_driver);
528	}	528	}
529		529
530	module_init(mux_init);	530	module_init(mux_init);
531	module_exit(mux_exit);	531	module_exit(mux_exit);
532		532
533	MODULE_AUTHOR("Ryan Bradetich");	533	MODULE_AUTHOR("Ryan Bradetich");
534	MODULE_DESCRIPTION("Serial MUX driver");	534	MODULE_DESCRIPTION("Serial MUX driver");
535	MODULE_LICENSE("GPL");	535	MODULE_LICENSE("GPL");
536	MODULE_ALIAS_CHARDEV_MAJOR(MUX_MAJOR);	536	MODULE_ALIAS_CHARDEV_MAJOR(MUX_MAJOR);
537		537

1	/*	1	/*
2	** ccio-dma.c:	2	** ccio-dma.c:
3	** DMA management routines for first generation cache-coherent machines.	3	** DMA management routines for first generation cache-coherent machines.
4	** Program U2/Uturn in "Virtual Mode" and use the I/O MMU.	4	** Program U2/Uturn in "Virtual Mode" and use the I/O MMU.
5	**	5	**
6	** (c) Copyright 2000 Grant Grundler	6	** (c) Copyright 2000 Grant Grundler
7	** (c) Copyright 2000 Ryan Bradetich	7	** (c) Copyright 2000 Ryan Bradetich
8	** (c) Copyright 2000 Hewlett-Packard Company	8	** (c) Copyright 2000 Hewlett-Packard Company
9	**	9	**
10	** This program is free software; you can redistribute it and/or modify	10	** This program is free software; you can redistribute it and/or modify
11	** it under the terms of the GNU General Public License as published by	11	** it under the terms of the GNU General Public License as published by
12	** the Free Software Foundation; either version 2 of the License, or	12	** the Free Software Foundation; either version 2 of the License, or
13	** (at your option) any later version.	13	** (at your option) any later version.
14	**	14	**
15	**	15	**
16	** "Real Mode" operation refers to U2/Uturn chip operation.	16	** "Real Mode" operation refers to U2/Uturn chip operation.
17	** U2/Uturn were designed to perform coherency checks w/o using	17	** U2/Uturn were designed to perform coherency checks w/o using
18	** the I/O MMU - basically what x86 does.	18	** the I/O MMU - basically what x86 does.
19	**	19	**
20	** Philipp Rumpf has a "Real Mode" driver for PCX-W machines at:	20	** Philipp Rumpf has a "Real Mode" driver for PCX-W machines at:
21	** CVSROOT=:pserver:anonymous@198.186.203.37:/cvsroot/linux-parisc	21	** CVSROOT=:pserver:anonymous@198.186.203.37:/cvsroot/linux-parisc
22	** cvs -z3 co linux/arch/parisc/kernel/dma-rm.c	22	** cvs -z3 co linux/arch/parisc/kernel/dma-rm.c
23	**	23	**
24	** I've rewritten his code to work under TPG's tree. See ccio-rm-dma.c.	24	** I've rewritten his code to work under TPG's tree. See ccio-rm-dma.c.
25	**	25	**
26	** Drawbacks of using Real Mode are:	26	** Drawbacks of using Real Mode are:
27	** o outbound DMA is slower - U2 won't prefetch data (GSC+ XQL signal).	27	** o outbound DMA is slower - U2 won't prefetch data (GSC+ XQL signal).
28	** o Inbound DMA less efficient - U2 can't use DMA_FAST attribute.	28	** o Inbound DMA less efficient - U2 can't use DMA_FAST attribute.
29	** o Ability to do scatter/gather in HW is lost.	29	** o Ability to do scatter/gather in HW is lost.
30	** o Doesn't work under PCX-U/U+ machines since they didn't follow	30	** o Doesn't work under PCX-U/U+ machines since they didn't follow
31	** the coherency design originally worked out. Only PCX-W does.	31	** the coherency design originally worked out. Only PCX-W does.
32	*/	32	*/
33		33
34	#include <linux/config.h>	34	#include <linux/config.h>
35	#include <linux/types.h>	35	#include <linux/types.h>
36	#include <linux/init.h>	36	#include <linux/init.h>
37	#include <linux/mm.h>	37	#include <linux/mm.h>
38	#include <linux/spinlock.h>	38	#include <linux/spinlock.h>
39	#include <linux/slab.h>	39	#include <linux/slab.h>
40	#include <linux/string.h>	40	#include <linux/string.h>

1	/*	1	/*
2	** System Bus Adapter (SBA) I/O MMU manager	2	** System Bus Adapter (SBA) I/O MMU manager
3	**	3	**
4	** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org>	4	** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org>
5	** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com>	5	** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com>
6	** (c) Copyright 2000-2004 Hewlett-Packard Company	6	** (c) Copyright 2000-2004 Hewlett-Packard Company
7	**	7	**
8	** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)	8	** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
9	**	9	**
10	** This program is free software; you can redistribute it and/or modify	10	** This program is free software; you can redistribute it and/or modify
11	** it under the terms of the GNU General Public License as published by	11	** it under the terms of the GNU General Public License as published by
12	** the Free Software Foundation; either version 2 of the License, or	12	** the Free Software Foundation; either version 2 of the License, or
13	** (at your option) any later version.	13	** (at your option) any later version.
14	**	14	**
15	**	15	**
16	** This module initializes the IOC (I/O Controller) found on B1000/C3000/	16	** This module initializes the IOC (I/O Controller) found on B1000/C3000/
17	** J5000/J7000/N-class/L-class machines and their successors.	17	** J5000/J7000/N-class/L-class machines and their successors.
18	**	18	**
19	** FIXME: add DMA hint support programming in both sba and lba modules.	19	** FIXME: add DMA hint support programming in both sba and lba modules.
20	*/	20	*/
21		21
22	#include <linux/config.h>	22	#include <linux/config.h>
23	#include <linux/types.h>	23	#include <linux/types.h>
24	#include <linux/kernel.h>	24	#include <linux/kernel.h>
25	#include <linux/spinlock.h>	25	#include <linux/spinlock.h>
26	#include <linux/slab.h>	26	#include <linux/slab.h>
27	#include <linux/init.h>	27	#include <linux/init.h>
28		28
29	#include <linux/mm.h>	29	#include <linux/mm.h>
30	#include <linux/string.h>	30	#include <linux/string.h>
31	#include <linux/pci.h>	31	#include <linux/pci.h>
32		32
33	#include <asm/byteorder.h>	33	#include <asm/byteorder.h>
34	#include <asm/io.h>	34	#include <asm/io.h>
35	#include <asm/dma.h> /* for DMA_CHUNK_SIZE */	35	#include <asm/dma.h> /* for DMA_CHUNK_SIZE */
36		36
37	#include <asm/hardware.h> /* for register_parisc_driver() stuff */	37	#include <asm/hardware.h> /* for register_parisc_driver() stuff */
38		38
39	#include <linux/proc_fs.h>	39	#include <linux/proc_fs.h>
40	#include <linux/seq_file.h>	40	#include <linux/seq_file.h>