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Commit 519b371dcd3b175bcffa97bc88a7122e41afd318

Authored by Stephen Boyd
Committed by David Brown
1 parent f98cf83d0c
Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch imx_3.14.28_1.0.0_ga

msm_serial: Use devm_clk_get() and properly return errors 

Clocks are not clk_put() in this driver's error paths during
probe. The code that checks for clock errors also fails to
properly return the error code from the pclk member if it turns
out to be the failing clock, leading to potentially confusing
error values if the clk member is not an error pointer. Fix these
problems with devm_clk_get() and proper error checking.

Removing the clk_put() in msm_serial_remove() also points out
that msm_port is unused. Furthermore, msm_port is the wrong type
and so the clk_put() would be using the wrong pointer. Replace it
with the proper type and call uart_remove_one_port() to do the
proper cleanup.

Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: David Brown <davidb@codeaurora.org>

Showing 1 changed file with 12 additions and 9 deletions Inline Diff

drivers/tty/serial/msm_serial.c
Diff comments   View file @ 519b371
1 /* 1 /*
2 * Driver for msm7k serial device and console 2 * Driver for msm7k serial device and console
3 * 3 *
4 * Copyright (C) 2007 Google, Inc. 4 * Copyright (C) 2007 Google, Inc.
5 * Author: Robert Love <rlove@google.com> 5 * Author: Robert Love <rlove@google.com>
6 * Copyright (c) 2011, Code Aurora Forum. All rights reserved. 6 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
7 * 7 *
8 * This software is licensed under the terms of the GNU General Public 8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and 9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms. 10 * may be copied, distributed, and modified under those terms.
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 */ 16 */
17 17
18 #if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 18 #if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19 # define SUPPORT_SYSRQ 19 # define SUPPORT_SYSRQ
20 #endif 20 #endif
21 21
22 #include <linux/atomic.h> 22 #include <linux/atomic.h>
23 #include <linux/hrtimer.h> 23 #include <linux/hrtimer.h>
24 #include <linux/module.h> 24 #include <linux/module.h>
25 #include <linux/io.h> 25 #include <linux/io.h>
26 #include <linux/ioport.h> 26 #include <linux/ioport.h>
27 #include <linux/irq.h> 27 #include <linux/irq.h>
28 #include <linux/init.h> 28 #include <linux/init.h>
29 #include <linux/console.h> 29 #include <linux/console.h>
30 #include <linux/tty.h> 30 #include <linux/tty.h>
31 #include <linux/tty_flip.h> 31 #include <linux/tty_flip.h>
32 #include <linux/serial_core.h> 32 #include <linux/serial_core.h>
33 #include <linux/serial.h> 33 #include <linux/serial.h>
34 #include <linux/clk.h> 34 #include <linux/clk.h>
35 #include <linux/platform_device.h> 35 #include <linux/platform_device.h>
36 #include <linux/delay.h> 36 #include <linux/delay.h>
37 #include <linux/of.h> 37 #include <linux/of.h>
38 #include <linux/of_device.h> 38 #include <linux/of_device.h>
39 39
40 #include "msm_serial.h" 40 #include "msm_serial.h"
41 41
42 struct msm_port { 42 struct msm_port {
43 struct uart_port uart; 43 struct uart_port uart;
44 char name[16]; 44 char name[16];
45 struct clk *clk; 45 struct clk *clk;
46 struct clk *pclk; 46 struct clk *pclk;
47 unsigned int imr; 47 unsigned int imr;
48 unsigned int *gsbi_base; 48 unsigned int *gsbi_base;
49 int is_uartdm; 49 int is_uartdm;
50 unsigned int old_snap_state; 50 unsigned int old_snap_state;
51 }; 51 };
52 52
53 static inline void wait_for_xmitr(struct uart_port *port, int bits) 53 static inline void wait_for_xmitr(struct uart_port *port, int bits)
54 { 54 {
55 if (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) 55 if (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY))
56 while ((msm_read(port, UART_ISR) & bits) != bits) 56 while ((msm_read(port, UART_ISR) & bits) != bits)
57 cpu_relax(); 57 cpu_relax();
58 } 58 }
59 59
60 static void msm_stop_tx(struct uart_port *port) 60 static void msm_stop_tx(struct uart_port *port)
61 { 61 {
62 struct msm_port *msm_port = UART_TO_MSM(port); 62 struct msm_port *msm_port = UART_TO_MSM(port);
63 63
64 msm_port->imr &= ~UART_IMR_TXLEV; 64 msm_port->imr &= ~UART_IMR_TXLEV;
65 msm_write(port, msm_port->imr, UART_IMR); 65 msm_write(port, msm_port->imr, UART_IMR);
66 } 66 }
67 67
68 static void msm_start_tx(struct uart_port *port) 68 static void msm_start_tx(struct uart_port *port)
69 { 69 {
70 struct msm_port *msm_port = UART_TO_MSM(port); 70 struct msm_port *msm_port = UART_TO_MSM(port);
71 71
72 msm_port->imr |= UART_IMR_TXLEV; 72 msm_port->imr |= UART_IMR_TXLEV;
73 msm_write(port, msm_port->imr, UART_IMR); 73 msm_write(port, msm_port->imr, UART_IMR);
74 } 74 }
75 75
76 static void msm_stop_rx(struct uart_port *port) 76 static void msm_stop_rx(struct uart_port *port)
77 { 77 {
78 struct msm_port *msm_port = UART_TO_MSM(port); 78 struct msm_port *msm_port = UART_TO_MSM(port);
79 79
80 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE); 80 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
81 msm_write(port, msm_port->imr, UART_IMR); 81 msm_write(port, msm_port->imr, UART_IMR);
82 } 82 }
83 83
84 static void msm_enable_ms(struct uart_port *port) 84 static void msm_enable_ms(struct uart_port *port)
85 { 85 {
86 struct msm_port *msm_port = UART_TO_MSM(port); 86 struct msm_port *msm_port = UART_TO_MSM(port);
87 87
88 msm_port->imr |= UART_IMR_DELTA_CTS; 88 msm_port->imr |= UART_IMR_DELTA_CTS;
89 msm_write(port, msm_port->imr, UART_IMR); 89 msm_write(port, msm_port->imr, UART_IMR);
90 } 90 }
91 91
92 static void handle_rx_dm(struct uart_port *port, unsigned int misr) 92 static void handle_rx_dm(struct uart_port *port, unsigned int misr)
93 { 93 {
94 struct tty_port *tport = &port->state->port; 94 struct tty_port *tport = &port->state->port;
95 unsigned int sr; 95 unsigned int sr;
96 int count = 0; 96 int count = 0;
97 struct msm_port *msm_port = UART_TO_MSM(port); 97 struct msm_port *msm_port = UART_TO_MSM(port);
98 98
99 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) { 99 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
100 port->icount.overrun++; 100 port->icount.overrun++;
101 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 101 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
102 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 102 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
103 } 103 }
104 104
105 if (misr & UART_IMR_RXSTALE) { 105 if (misr & UART_IMR_RXSTALE) {
106 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) - 106 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
107 msm_port->old_snap_state; 107 msm_port->old_snap_state;
108 msm_port->old_snap_state = 0; 108 msm_port->old_snap_state = 0;
109 } else { 109 } else {
110 count = 4 * (msm_read(port, UART_RFWR)); 110 count = 4 * (msm_read(port, UART_RFWR));
111 msm_port->old_snap_state += count; 111 msm_port->old_snap_state += count;
112 } 112 }
113 113
114 /* TODO: Precise error reporting */ 114 /* TODO: Precise error reporting */
115 115
116 port->icount.rx += count; 116 port->icount.rx += count;
117 117
118 while (count > 0) { 118 while (count > 0) {
119 unsigned int c; 119 unsigned int c;
120 120
121 sr = msm_read(port, UART_SR); 121 sr = msm_read(port, UART_SR);
122 if ((sr & UART_SR_RX_READY) == 0) { 122 if ((sr & UART_SR_RX_READY) == 0) {
123 msm_port->old_snap_state -= count; 123 msm_port->old_snap_state -= count;
124 break; 124 break;
125 } 125 }
126 c = msm_read(port, UARTDM_RF); 126 c = msm_read(port, UARTDM_RF);
127 if (sr & UART_SR_RX_BREAK) { 127 if (sr & UART_SR_RX_BREAK) {
128 port->icount.brk++; 128 port->icount.brk++;
129 if (uart_handle_break(port)) 129 if (uart_handle_break(port))
130 continue; 130 continue;
131 } else if (sr & UART_SR_PAR_FRAME_ERR) 131 } else if (sr & UART_SR_PAR_FRAME_ERR)
132 port->icount.frame++; 132 port->icount.frame++;
133 133
134 /* TODO: handle sysrq */ 134 /* TODO: handle sysrq */
135 tty_insert_flip_string(tport, (char *)&c, 135 tty_insert_flip_string(tport, (char *)&c,
136 (count > 4) ? 4 : count); 136 (count > 4) ? 4 : count);
137 count -= 4; 137 count -= 4;
138 } 138 }
139 139
140 tty_flip_buffer_push(tport); 140 tty_flip_buffer_push(tport);
141 if (misr & (UART_IMR_RXSTALE)) 141 if (misr & (UART_IMR_RXSTALE))
142 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); 142 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
143 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 143 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
144 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); 144 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
145 } 145 }
146 146
147 static void handle_rx(struct uart_port *port) 147 static void handle_rx(struct uart_port *port)
148 { 148 {
149 struct tty_port *tport = &port->state->port; 149 struct tty_port *tport = &port->state->port;
150 unsigned int sr; 150 unsigned int sr;
151 151
152 /* 152 /*
153 * Handle overrun. My understanding of the hardware is that overrun 153 * Handle overrun. My understanding of the hardware is that overrun
154 * is not tied to the RX buffer, so we handle the case out of band. 154 * is not tied to the RX buffer, so we handle the case out of band.
155 */ 155 */
156 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) { 156 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
157 port->icount.overrun++; 157 port->icount.overrun++;
158 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 158 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
159 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 159 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
160 } 160 }
161 161
162 /* and now the main RX loop */ 162 /* and now the main RX loop */
163 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) { 163 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
164 unsigned int c; 164 unsigned int c;
165 char flag = TTY_NORMAL; 165 char flag = TTY_NORMAL;
166 166
167 c = msm_read(port, UART_RF); 167 c = msm_read(port, UART_RF);
168 168
169 if (sr & UART_SR_RX_BREAK) { 169 if (sr & UART_SR_RX_BREAK) {
170 port->icount.brk++; 170 port->icount.brk++;
171 if (uart_handle_break(port)) 171 if (uart_handle_break(port))
172 continue; 172 continue;
173 } else if (sr & UART_SR_PAR_FRAME_ERR) { 173 } else if (sr & UART_SR_PAR_FRAME_ERR) {
174 port->icount.frame++; 174 port->icount.frame++;
175 } else { 175 } else {
176 port->icount.rx++; 176 port->icount.rx++;
177 } 177 }
178 178
179 /* Mask conditions we're ignorning. */ 179 /* Mask conditions we're ignorning. */
180 sr &= port->read_status_mask; 180 sr &= port->read_status_mask;
181 181
182 if (sr & UART_SR_RX_BREAK) { 182 if (sr & UART_SR_RX_BREAK) {
183 flag = TTY_BREAK; 183 flag = TTY_BREAK;
184 } else if (sr & UART_SR_PAR_FRAME_ERR) { 184 } else if (sr & UART_SR_PAR_FRAME_ERR) {
185 flag = TTY_FRAME; 185 flag = TTY_FRAME;
186 } 186 }
187 187
188 if (!uart_handle_sysrq_char(port, c)) 188 if (!uart_handle_sysrq_char(port, c))
189 tty_insert_flip_char(tport, c, flag); 189 tty_insert_flip_char(tport, c, flag);
190 } 190 }
191 191
192 tty_flip_buffer_push(tport); 192 tty_flip_buffer_push(tport);
193 } 193 }
194 194
195 static void reset_dm_count(struct uart_port *port) 195 static void reset_dm_count(struct uart_port *port)
196 { 196 {
197 wait_for_xmitr(port, UART_ISR_TX_READY); 197 wait_for_xmitr(port, UART_ISR_TX_READY);
198 msm_write(port, 1, UARTDM_NCF_TX); 198 msm_write(port, 1, UARTDM_NCF_TX);
199 } 199 }
200 200
201 static void handle_tx(struct uart_port *port) 201 static void handle_tx(struct uart_port *port)
202 { 202 {
203 struct circ_buf *xmit = &port->state->xmit; 203 struct circ_buf *xmit = &port->state->xmit;
204 struct msm_port *msm_port = UART_TO_MSM(port); 204 struct msm_port *msm_port = UART_TO_MSM(port);
205 int sent_tx; 205 int sent_tx;
206 206
207 if (port->x_char) { 207 if (port->x_char) {
208 if (msm_port->is_uartdm) 208 if (msm_port->is_uartdm)
209 reset_dm_count(port); 209 reset_dm_count(port);
210 210
211 msm_write(port, port->x_char, 211 msm_write(port, port->x_char,
212 msm_port->is_uartdm ? UARTDM_TF : UART_TF); 212 msm_port->is_uartdm ? UARTDM_TF : UART_TF);
213 port->icount.tx++; 213 port->icount.tx++;
214 port->x_char = 0; 214 port->x_char = 0;
215 } 215 }
216 216
217 if (msm_port->is_uartdm) 217 if (msm_port->is_uartdm)
218 reset_dm_count(port); 218 reset_dm_count(port);
219 219
220 while (msm_read(port, UART_SR) & UART_SR_TX_READY) { 220 while (msm_read(port, UART_SR) & UART_SR_TX_READY) {
221 if (uart_circ_empty(xmit)) { 221 if (uart_circ_empty(xmit)) {
222 /* disable tx interrupts */ 222 /* disable tx interrupts */
223 msm_port->imr &= ~UART_IMR_TXLEV; 223 msm_port->imr &= ~UART_IMR_TXLEV;
224 msm_write(port, msm_port->imr, UART_IMR); 224 msm_write(port, msm_port->imr, UART_IMR);
225 break; 225 break;
226 } 226 }
227 msm_write(port, xmit->buf[xmit->tail], 227 msm_write(port, xmit->buf[xmit->tail],
228 msm_port->is_uartdm ? UARTDM_TF : UART_TF); 228 msm_port->is_uartdm ? UARTDM_TF : UART_TF);
229 229
230 if (msm_port->is_uartdm) 230 if (msm_port->is_uartdm)
231 reset_dm_count(port); 231 reset_dm_count(port);
232 232
233 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 233 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
234 port->icount.tx++; 234 port->icount.tx++;
235 sent_tx = 1; 235 sent_tx = 1;
236 } 236 }
237 237
238 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 238 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
239 uart_write_wakeup(port); 239 uart_write_wakeup(port);
240 } 240 }
241 241
242 static void handle_delta_cts(struct uart_port *port) 242 static void handle_delta_cts(struct uart_port *port)
243 { 243 {
244 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR); 244 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
245 port->icount.cts++; 245 port->icount.cts++;
246 wake_up_interruptible(&port->state->port.delta_msr_wait); 246 wake_up_interruptible(&port->state->port.delta_msr_wait);
247 } 247 }
248 248
249 static irqreturn_t msm_irq(int irq, void *dev_id) 249 static irqreturn_t msm_irq(int irq, void *dev_id)
250 { 250 {
251 struct uart_port *port = dev_id; 251 struct uart_port *port = dev_id;
252 struct msm_port *msm_port = UART_TO_MSM(port); 252 struct msm_port *msm_port = UART_TO_MSM(port);
253 unsigned int misr; 253 unsigned int misr;
254 254
255 spin_lock(&port->lock); 255 spin_lock(&port->lock);
256 misr = msm_read(port, UART_MISR); 256 misr = msm_read(port, UART_MISR);
257 msm_write(port, 0, UART_IMR); /* disable interrupt */ 257 msm_write(port, 0, UART_IMR); /* disable interrupt */
258 258
259 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) { 259 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
260 if (msm_port->is_uartdm) 260 if (msm_port->is_uartdm)
261 handle_rx_dm(port, misr); 261 handle_rx_dm(port, misr);
262 else 262 else
263 handle_rx(port); 263 handle_rx(port);
264 } 264 }
265 if (misr & UART_IMR_TXLEV) 265 if (misr & UART_IMR_TXLEV)
266 handle_tx(port); 266 handle_tx(port);
267 if (misr & UART_IMR_DELTA_CTS) 267 if (misr & UART_IMR_DELTA_CTS)
268 handle_delta_cts(port); 268 handle_delta_cts(port);
269 269
270 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */ 270 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
271 spin_unlock(&port->lock); 271 spin_unlock(&port->lock);
272 272
273 return IRQ_HANDLED; 273 return IRQ_HANDLED;
274 } 274 }
275 275
276 static unsigned int msm_tx_empty(struct uart_port *port) 276 static unsigned int msm_tx_empty(struct uart_port *port)
277 { 277 {
278 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0; 278 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
279 } 279 }
280 280
281 static unsigned int msm_get_mctrl(struct uart_port *port) 281 static unsigned int msm_get_mctrl(struct uart_port *port)
282 { 282 {
283 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS; 283 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
284 } 284 }
285 285
286 286
287 static void msm_reset(struct uart_port *port) 287 static void msm_reset(struct uart_port *port)
288 { 288 {
289 /* reset everything */ 289 /* reset everything */
290 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR); 290 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
291 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR); 291 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
292 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 292 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
293 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR); 293 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
294 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR); 294 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
295 msm_write(port, UART_CR_CMD_SET_RFR, UART_CR); 295 msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
296 } 296 }
297 297
298 void msm_set_mctrl(struct uart_port *port, unsigned int mctrl) 298 void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
299 { 299 {
300 unsigned int mr; 300 unsigned int mr;
301 mr = msm_read(port, UART_MR1); 301 mr = msm_read(port, UART_MR1);
302 302
303 if (!(mctrl & TIOCM_RTS)) { 303 if (!(mctrl & TIOCM_RTS)) {
304 mr &= ~UART_MR1_RX_RDY_CTL; 304 mr &= ~UART_MR1_RX_RDY_CTL;
305 msm_write(port, mr, UART_MR1); 305 msm_write(port, mr, UART_MR1);
306 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR); 306 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
307 } else { 307 } else {
308 mr |= UART_MR1_RX_RDY_CTL; 308 mr |= UART_MR1_RX_RDY_CTL;
309 msm_write(port, mr, UART_MR1); 309 msm_write(port, mr, UART_MR1);
310 } 310 }
311 } 311 }
312 312
313 static void msm_break_ctl(struct uart_port *port, int break_ctl) 313 static void msm_break_ctl(struct uart_port *port, int break_ctl)
314 { 314 {
315 if (break_ctl) 315 if (break_ctl)
316 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR); 316 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
317 else 317 else
318 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR); 318 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
319 } 319 }
320 320
321 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud) 321 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
322 { 322 {
323 unsigned int baud_code, rxstale, watermark; 323 unsigned int baud_code, rxstale, watermark;
324 struct msm_port *msm_port = UART_TO_MSM(port); 324 struct msm_port *msm_port = UART_TO_MSM(port);
325 325
326 switch (baud) { 326 switch (baud) {
327 case 300: 327 case 300:
328 baud_code = UART_CSR_300; 328 baud_code = UART_CSR_300;
329 rxstale = 1; 329 rxstale = 1;
330 break; 330 break;
331 case 600: 331 case 600:
332 baud_code = UART_CSR_600; 332 baud_code = UART_CSR_600;
333 rxstale = 1; 333 rxstale = 1;
334 break; 334 break;
335 case 1200: 335 case 1200:
336 baud_code = UART_CSR_1200; 336 baud_code = UART_CSR_1200;
337 rxstale = 1; 337 rxstale = 1;
338 break; 338 break;
339 case 2400: 339 case 2400:
340 baud_code = UART_CSR_2400; 340 baud_code = UART_CSR_2400;
341 rxstale = 1; 341 rxstale = 1;
342 break; 342 break;
343 case 4800: 343 case 4800:
344 baud_code = UART_CSR_4800; 344 baud_code = UART_CSR_4800;
345 rxstale = 1; 345 rxstale = 1;
346 break; 346 break;
347 case 9600: 347 case 9600:
348 baud_code = UART_CSR_9600; 348 baud_code = UART_CSR_9600;
349 rxstale = 2; 349 rxstale = 2;
350 break; 350 break;
351 case 14400: 351 case 14400:
352 baud_code = UART_CSR_14400; 352 baud_code = UART_CSR_14400;
353 rxstale = 3; 353 rxstale = 3;
354 break; 354 break;
355 case 19200: 355 case 19200:
356 baud_code = UART_CSR_19200; 356 baud_code = UART_CSR_19200;
357 rxstale = 4; 357 rxstale = 4;
358 break; 358 break;
359 case 28800: 359 case 28800:
360 baud_code = UART_CSR_28800; 360 baud_code = UART_CSR_28800;
361 rxstale = 6; 361 rxstale = 6;
362 break; 362 break;
363 case 38400: 363 case 38400:
364 baud_code = UART_CSR_38400; 364 baud_code = UART_CSR_38400;
365 rxstale = 8; 365 rxstale = 8;
366 break; 366 break;
367 case 57600: 367 case 57600:
368 baud_code = UART_CSR_57600; 368 baud_code = UART_CSR_57600;
369 rxstale = 16; 369 rxstale = 16;
370 break; 370 break;
371 case 115200: 371 case 115200:
372 default: 372 default:
373 baud_code = UART_CSR_115200; 373 baud_code = UART_CSR_115200;
374 baud = 115200; 374 baud = 115200;
375 rxstale = 31; 375 rxstale = 31;
376 break; 376 break;
377 } 377 }
378 378
379 if (msm_port->is_uartdm) 379 if (msm_port->is_uartdm)
380 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR); 380 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
381 381
382 msm_write(port, baud_code, UART_CSR); 382 msm_write(port, baud_code, UART_CSR);
383 383
384 /* RX stale watermark */ 384 /* RX stale watermark */
385 watermark = UART_IPR_STALE_LSB & rxstale; 385 watermark = UART_IPR_STALE_LSB & rxstale;
386 watermark |= UART_IPR_RXSTALE_LAST; 386 watermark |= UART_IPR_RXSTALE_LAST;
387 watermark |= UART_IPR_STALE_TIMEOUT_MSB & (rxstale << 2); 387 watermark |= UART_IPR_STALE_TIMEOUT_MSB & (rxstale << 2);
388 msm_write(port, watermark, UART_IPR); 388 msm_write(port, watermark, UART_IPR);
389 389
390 /* set RX watermark */ 390 /* set RX watermark */
391 watermark = (port->fifosize * 3) / 4; 391 watermark = (port->fifosize * 3) / 4;
392 msm_write(port, watermark, UART_RFWR); 392 msm_write(port, watermark, UART_RFWR);
393 393
394 /* set TX watermark */ 394 /* set TX watermark */
395 msm_write(port, 10, UART_TFWR); 395 msm_write(port, 10, UART_TFWR);
396 396
397 if (msm_port->is_uartdm) { 397 if (msm_port->is_uartdm) {
398 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); 398 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
399 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 399 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
400 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); 400 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
401 } 401 }
402 402
403 return baud; 403 return baud;
404 } 404 }
405 405
406 406
407 static void msm_init_clock(struct uart_port *port) 407 static void msm_init_clock(struct uart_port *port)
408 { 408 {
409 struct msm_port *msm_port = UART_TO_MSM(port); 409 struct msm_port *msm_port = UART_TO_MSM(port);
410 410
411 clk_prepare_enable(msm_port->clk); 411 clk_prepare_enable(msm_port->clk);
412 if (!IS_ERR(msm_port->pclk)) 412 if (!IS_ERR(msm_port->pclk))
413 clk_prepare_enable(msm_port->pclk); 413 clk_prepare_enable(msm_port->pclk);
414 msm_serial_set_mnd_regs(port); 414 msm_serial_set_mnd_regs(port);
415 } 415 }
416 416
417 static int msm_startup(struct uart_port *port) 417 static int msm_startup(struct uart_port *port)
418 { 418 {
419 struct msm_port *msm_port = UART_TO_MSM(port); 419 struct msm_port *msm_port = UART_TO_MSM(port);
420 unsigned int data, rfr_level; 420 unsigned int data, rfr_level;
421 int ret; 421 int ret;
422 422
423 snprintf(msm_port->name, sizeof(msm_port->name), 423 snprintf(msm_port->name, sizeof(msm_port->name),
424 "msm_serial%d", port->line); 424 "msm_serial%d", port->line);
425 425
426 ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH, 426 ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH,
427 msm_port->name, port); 427 msm_port->name, port);
428 if (unlikely(ret)) 428 if (unlikely(ret))
429 return ret; 429 return ret;
430 430
431 msm_init_clock(port); 431 msm_init_clock(port);
432 432
433 if (likely(port->fifosize > 12)) 433 if (likely(port->fifosize > 12))
434 rfr_level = port->fifosize - 12; 434 rfr_level = port->fifosize - 12;
435 else 435 else
436 rfr_level = port->fifosize; 436 rfr_level = port->fifosize;
437 437
438 /* set automatic RFR level */ 438 /* set automatic RFR level */
439 data = msm_read(port, UART_MR1); 439 data = msm_read(port, UART_MR1);
440 data &= ~UART_MR1_AUTO_RFR_LEVEL1; 440 data &= ~UART_MR1_AUTO_RFR_LEVEL1;
441 data &= ~UART_MR1_AUTO_RFR_LEVEL0; 441 data &= ~UART_MR1_AUTO_RFR_LEVEL0;
442 data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2); 442 data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2);
443 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level; 443 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
444 msm_write(port, data, UART_MR1); 444 msm_write(port, data, UART_MR1);
445 445
446 /* make sure that RXSTALE count is non-zero */ 446 /* make sure that RXSTALE count is non-zero */
447 data = msm_read(port, UART_IPR); 447 data = msm_read(port, UART_IPR);
448 if (unlikely(!data)) { 448 if (unlikely(!data)) {
449 data |= UART_IPR_RXSTALE_LAST; 449 data |= UART_IPR_RXSTALE_LAST;
450 data |= UART_IPR_STALE_LSB; 450 data |= UART_IPR_STALE_LSB;
451 msm_write(port, data, UART_IPR); 451 msm_write(port, data, UART_IPR);
452 } 452 }
453 453
454 data = 0; 454 data = 0;
455 if (!port->cons || (port->cons && !(port->cons->flags & CON_ENABLED))) { 455 if (!port->cons || (port->cons && !(port->cons->flags & CON_ENABLED))) {
456 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR); 456 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
457 msm_reset(port); 457 msm_reset(port);
458 data = UART_CR_TX_ENABLE; 458 data = UART_CR_TX_ENABLE;
459 } 459 }
460 460
461 data |= UART_CR_RX_ENABLE; 461 data |= UART_CR_RX_ENABLE;
462 msm_write(port, data, UART_CR); /* enable TX & RX */ 462 msm_write(port, data, UART_CR); /* enable TX & RX */
463 463
464 /* Make sure IPR is not 0 to start with*/ 464 /* Make sure IPR is not 0 to start with*/
465 if (msm_port->is_uartdm) 465 if (msm_port->is_uartdm)
466 msm_write(port, UART_IPR_STALE_LSB, UART_IPR); 466 msm_write(port, UART_IPR_STALE_LSB, UART_IPR);
467 467
468 /* turn on RX and CTS interrupts */ 468 /* turn on RX and CTS interrupts */
469 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE | 469 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
470 UART_IMR_CURRENT_CTS; 470 UART_IMR_CURRENT_CTS;
471 471
472 if (msm_port->is_uartdm) { 472 if (msm_port->is_uartdm) {
473 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 473 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
474 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); 474 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
475 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); 475 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
476 } 476 }
477 477
478 msm_write(port, msm_port->imr, UART_IMR); 478 msm_write(port, msm_port->imr, UART_IMR);
479 return 0; 479 return 0;
480 } 480 }
481 481
482 static void msm_shutdown(struct uart_port *port) 482 static void msm_shutdown(struct uart_port *port)
483 { 483 {
484 struct msm_port *msm_port = UART_TO_MSM(port); 484 struct msm_port *msm_port = UART_TO_MSM(port);
485 485
486 msm_port->imr = 0; 486 msm_port->imr = 0;
487 msm_write(port, 0, UART_IMR); /* disable interrupts */ 487 msm_write(port, 0, UART_IMR); /* disable interrupts */
488 488
489 clk_disable_unprepare(msm_port->clk); 489 clk_disable_unprepare(msm_port->clk);
490 490
491 free_irq(port->irq, port); 491 free_irq(port->irq, port);
492 } 492 }
493 493
494 static void msm_set_termios(struct uart_port *port, struct ktermios *termios, 494 static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
495 struct ktermios *old) 495 struct ktermios *old)
496 { 496 {
497 unsigned long flags; 497 unsigned long flags;
498 unsigned int baud, mr; 498 unsigned int baud, mr;
499 499
500 spin_lock_irqsave(&port->lock, flags); 500 spin_lock_irqsave(&port->lock, flags);
501 501
502 /* calculate and set baud rate */ 502 /* calculate and set baud rate */
503 baud = uart_get_baud_rate(port, termios, old, 300, 115200); 503 baud = uart_get_baud_rate(port, termios, old, 300, 115200);
504 baud = msm_set_baud_rate(port, baud); 504 baud = msm_set_baud_rate(port, baud);
505 if (tty_termios_baud_rate(termios)) 505 if (tty_termios_baud_rate(termios))
506 tty_termios_encode_baud_rate(termios, baud, baud); 506 tty_termios_encode_baud_rate(termios, baud, baud);
507 507
508 /* calculate parity */ 508 /* calculate parity */
509 mr = msm_read(port, UART_MR2); 509 mr = msm_read(port, UART_MR2);
510 mr &= ~UART_MR2_PARITY_MODE; 510 mr &= ~UART_MR2_PARITY_MODE;
511 if (termios->c_cflag & PARENB) { 511 if (termios->c_cflag & PARENB) {
512 if (termios->c_cflag & PARODD) 512 if (termios->c_cflag & PARODD)
513 mr |= UART_MR2_PARITY_MODE_ODD; 513 mr |= UART_MR2_PARITY_MODE_ODD;
514 else if (termios->c_cflag & CMSPAR) 514 else if (termios->c_cflag & CMSPAR)
515 mr |= UART_MR2_PARITY_MODE_SPACE; 515 mr |= UART_MR2_PARITY_MODE_SPACE;
516 else 516 else
517 mr |= UART_MR2_PARITY_MODE_EVEN; 517 mr |= UART_MR2_PARITY_MODE_EVEN;
518 } 518 }
519 519
520 /* calculate bits per char */ 520 /* calculate bits per char */
521 mr &= ~UART_MR2_BITS_PER_CHAR; 521 mr &= ~UART_MR2_BITS_PER_CHAR;
522 switch (termios->c_cflag & CSIZE) { 522 switch (termios->c_cflag & CSIZE) {
523 case CS5: 523 case CS5:
524 mr |= UART_MR2_BITS_PER_CHAR_5; 524 mr |= UART_MR2_BITS_PER_CHAR_5;
525 break; 525 break;
526 case CS6: 526 case CS6:
527 mr |= UART_MR2_BITS_PER_CHAR_6; 527 mr |= UART_MR2_BITS_PER_CHAR_6;
528 break; 528 break;
529 case CS7: 529 case CS7:
530 mr |= UART_MR2_BITS_PER_CHAR_7; 530 mr |= UART_MR2_BITS_PER_CHAR_7;
531 break; 531 break;
532 case CS8: 532 case CS8:
533 default: 533 default:
534 mr |= UART_MR2_BITS_PER_CHAR_8; 534 mr |= UART_MR2_BITS_PER_CHAR_8;
535 break; 535 break;
536 } 536 }
537 537
538 /* calculate stop bits */ 538 /* calculate stop bits */
539 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO); 539 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
540 if (termios->c_cflag & CSTOPB) 540 if (termios->c_cflag & CSTOPB)
541 mr |= UART_MR2_STOP_BIT_LEN_TWO; 541 mr |= UART_MR2_STOP_BIT_LEN_TWO;
542 else 542 else
543 mr |= UART_MR2_STOP_BIT_LEN_ONE; 543 mr |= UART_MR2_STOP_BIT_LEN_ONE;
544 544
545 /* set parity, bits per char, and stop bit */ 545 /* set parity, bits per char, and stop bit */
546 msm_write(port, mr, UART_MR2); 546 msm_write(port, mr, UART_MR2);
547 547
548 /* calculate and set hardware flow control */ 548 /* calculate and set hardware flow control */
549 mr = msm_read(port, UART_MR1); 549 mr = msm_read(port, UART_MR1);
550 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL); 550 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
551 if (termios->c_cflag & CRTSCTS) { 551 if (termios->c_cflag & CRTSCTS) {
552 mr |= UART_MR1_CTS_CTL; 552 mr |= UART_MR1_CTS_CTL;
553 mr |= UART_MR1_RX_RDY_CTL; 553 mr |= UART_MR1_RX_RDY_CTL;
554 } 554 }
555 msm_write(port, mr, UART_MR1); 555 msm_write(port, mr, UART_MR1);
556 556
557 /* Configure status bits to ignore based on termio flags. */ 557 /* Configure status bits to ignore based on termio flags. */
558 port->read_status_mask = 0; 558 port->read_status_mask = 0;
559 if (termios->c_iflag & INPCK) 559 if (termios->c_iflag & INPCK)
560 port->read_status_mask |= UART_SR_PAR_FRAME_ERR; 560 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
561 if (termios->c_iflag & (BRKINT | PARMRK)) 561 if (termios->c_iflag & (BRKINT | PARMRK))
562 port->read_status_mask |= UART_SR_RX_BREAK; 562 port->read_status_mask |= UART_SR_RX_BREAK;
563 563
564 uart_update_timeout(port, termios->c_cflag, baud); 564 uart_update_timeout(port, termios->c_cflag, baud);
565 565
566 spin_unlock_irqrestore(&port->lock, flags); 566 spin_unlock_irqrestore(&port->lock, flags);
567 } 567 }
568 568
569 static const char *msm_type(struct uart_port *port) 569 static const char *msm_type(struct uart_port *port)
570 { 570 {
571 return "MSM"; 571 return "MSM";
572 } 572 }
573 573
574 static void msm_release_port(struct uart_port *port) 574 static void msm_release_port(struct uart_port *port)
575 { 575 {
576 struct platform_device *pdev = to_platform_device(port->dev); 576 struct platform_device *pdev = to_platform_device(port->dev);
577 struct msm_port *msm_port = UART_TO_MSM(port); 577 struct msm_port *msm_port = UART_TO_MSM(port);
578 struct resource *uart_resource; 578 struct resource *uart_resource;
579 struct resource *gsbi_resource; 579 struct resource *gsbi_resource;
580 resource_size_t size; 580 resource_size_t size;
581 581
582 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 582 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
583 if (unlikely(!uart_resource)) 583 if (unlikely(!uart_resource))
584 return; 584 return;
585 size = resource_size(uart_resource); 585 size = resource_size(uart_resource);
586 586
587 release_mem_region(port->mapbase, size); 587 release_mem_region(port->mapbase, size);
588 iounmap(port->membase); 588 iounmap(port->membase);
589 port->membase = NULL; 589 port->membase = NULL;
590 590
591 if (msm_port->gsbi_base) { 591 if (msm_port->gsbi_base) {
592 iowrite32(GSBI_PROTOCOL_IDLE, msm_port->gsbi_base + 592 iowrite32(GSBI_PROTOCOL_IDLE, msm_port->gsbi_base +
593 GSBI_CONTROL); 593 GSBI_CONTROL);
594 594
595 gsbi_resource = platform_get_resource(pdev, 595 gsbi_resource = platform_get_resource(pdev,
596 IORESOURCE_MEM, 1); 596 IORESOURCE_MEM, 1);
597 597
598 if (unlikely(!gsbi_resource)) 598 if (unlikely(!gsbi_resource))
599 return; 599 return;
600 600
601 size = resource_size(gsbi_resource); 601 size = resource_size(gsbi_resource);
602 release_mem_region(gsbi_resource->start, size); 602 release_mem_region(gsbi_resource->start, size);
603 iounmap(msm_port->gsbi_base); 603 iounmap(msm_port->gsbi_base);
604 msm_port->gsbi_base = NULL; 604 msm_port->gsbi_base = NULL;
605 } 605 }
606 } 606 }
607 607
608 static int msm_request_port(struct uart_port *port) 608 static int msm_request_port(struct uart_port *port)
609 { 609 {
610 struct msm_port *msm_port = UART_TO_MSM(port); 610 struct msm_port *msm_port = UART_TO_MSM(port);
611 struct platform_device *pdev = to_platform_device(port->dev); 611 struct platform_device *pdev = to_platform_device(port->dev);
612 struct resource *uart_resource; 612 struct resource *uart_resource;
613 struct resource *gsbi_resource; 613 struct resource *gsbi_resource;
614 resource_size_t size; 614 resource_size_t size;
615 int ret; 615 int ret;
616 616
617 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 617 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
618 if (unlikely(!uart_resource)) 618 if (unlikely(!uart_resource))
619 return -ENXIO; 619 return -ENXIO;
620 620
621 size = resource_size(uart_resource); 621 size = resource_size(uart_resource);
622 622
623 if (!request_mem_region(port->mapbase, size, "msm_serial")) 623 if (!request_mem_region(port->mapbase, size, "msm_serial"))
624 return -EBUSY; 624 return -EBUSY;
625 625
626 port->membase = ioremap(port->mapbase, size); 626 port->membase = ioremap(port->mapbase, size);
627 if (!port->membase) { 627 if (!port->membase) {
628 ret = -EBUSY; 628 ret = -EBUSY;
629 goto fail_release_port; 629 goto fail_release_port;
630 } 630 }
631 631
632 gsbi_resource = platform_get_resource(pdev, IORESOURCE_MEM, 1); 632 gsbi_resource = platform_get_resource(pdev, IORESOURCE_MEM, 1);
633 /* Is this a GSBI-based port? */ 633 /* Is this a GSBI-based port? */
634 if (gsbi_resource) { 634 if (gsbi_resource) {
635 size = resource_size(gsbi_resource); 635 size = resource_size(gsbi_resource);
636 636
637 if (!request_mem_region(gsbi_resource->start, size, 637 if (!request_mem_region(gsbi_resource->start, size,
638 "msm_serial")) { 638 "msm_serial")) {
639 ret = -EBUSY; 639 ret = -EBUSY;
640 goto fail_release_port; 640 goto fail_release_port;
641 } 641 }
642 642
643 msm_port->gsbi_base = ioremap(gsbi_resource->start, size); 643 msm_port->gsbi_base = ioremap(gsbi_resource->start, size);
644 if (!msm_port->gsbi_base) { 644 if (!msm_port->gsbi_base) {
645 ret = -EBUSY; 645 ret = -EBUSY;
646 goto fail_release_gsbi; 646 goto fail_release_gsbi;
647 } 647 }
648 } 648 }
649 649
650 return 0; 650 return 0;
651 651
652 fail_release_gsbi: 652 fail_release_gsbi:
653 release_mem_region(gsbi_resource->start, size); 653 release_mem_region(gsbi_resource->start, size);
654 fail_release_port: 654 fail_release_port:
655 release_mem_region(port->mapbase, size); 655 release_mem_region(port->mapbase, size);
656 return ret; 656 return ret;
657 } 657 }
658 658
659 static void msm_config_port(struct uart_port *port, int flags) 659 static void msm_config_port(struct uart_port *port, int flags)
660 { 660 {
661 struct msm_port *msm_port = UART_TO_MSM(port); 661 struct msm_port *msm_port = UART_TO_MSM(port);
662 int ret; 662 int ret;
663 if (flags & UART_CONFIG_TYPE) { 663 if (flags & UART_CONFIG_TYPE) {
664 port->type = PORT_MSM; 664 port->type = PORT_MSM;
665 ret = msm_request_port(port); 665 ret = msm_request_port(port);
666 if (ret) 666 if (ret)
667 return; 667 return;
668 } 668 }
669 669
670 if (msm_port->is_uartdm) 670 if (msm_port->is_uartdm)
671 iowrite32(GSBI_PROTOCOL_UART, msm_port->gsbi_base + 671 iowrite32(GSBI_PROTOCOL_UART, msm_port->gsbi_base +
672 GSBI_CONTROL); 672 GSBI_CONTROL);
673 } 673 }
674 674
675 static int msm_verify_port(struct uart_port *port, struct serial_struct *ser) 675 static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
676 { 676 {
677 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM)) 677 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
678 return -EINVAL; 678 return -EINVAL;
679 if (unlikely(port->irq != ser->irq)) 679 if (unlikely(port->irq != ser->irq))
680 return -EINVAL; 680 return -EINVAL;
681 return 0; 681 return 0;
682 } 682 }
683 683
684 static void msm_power(struct uart_port *port, unsigned int state, 684 static void msm_power(struct uart_port *port, unsigned int state,
685 unsigned int oldstate) 685 unsigned int oldstate)
686 { 686 {
687 struct msm_port *msm_port = UART_TO_MSM(port); 687 struct msm_port *msm_port = UART_TO_MSM(port);
688 688
689 switch (state) { 689 switch (state) {
690 case 0: 690 case 0:
691 clk_prepare_enable(msm_port->clk); 691 clk_prepare_enable(msm_port->clk);
692 if (!IS_ERR(msm_port->pclk)) 692 if (!IS_ERR(msm_port->pclk))
693 clk_prepare_enable(msm_port->pclk); 693 clk_prepare_enable(msm_port->pclk);
694 break; 694 break;
695 case 3: 695 case 3:
696 clk_disable_unprepare(msm_port->clk); 696 clk_disable_unprepare(msm_port->clk);
697 if (!IS_ERR(msm_port->pclk)) 697 if (!IS_ERR(msm_port->pclk))
698 clk_disable_unprepare(msm_port->pclk); 698 clk_disable_unprepare(msm_port->pclk);
699 break; 699 break;
700 default: 700 default:
701 printk(KERN_ERR "msm_serial: Unknown PM state %d\n", state); 701 printk(KERN_ERR "msm_serial: Unknown PM state %d\n", state);
702 } 702 }
703 } 703 }
704 704
705 static struct uart_ops msm_uart_pops = { 705 static struct uart_ops msm_uart_pops = {
706 .tx_empty = msm_tx_empty, 706 .tx_empty = msm_tx_empty,
707 .set_mctrl = msm_set_mctrl, 707 .set_mctrl = msm_set_mctrl,
708 .get_mctrl = msm_get_mctrl, 708 .get_mctrl = msm_get_mctrl,
709 .stop_tx = msm_stop_tx, 709 .stop_tx = msm_stop_tx,
710 .start_tx = msm_start_tx, 710 .start_tx = msm_start_tx,
711 .stop_rx = msm_stop_rx, 711 .stop_rx = msm_stop_rx,
712 .enable_ms = msm_enable_ms, 712 .enable_ms = msm_enable_ms,
713 .break_ctl = msm_break_ctl, 713 .break_ctl = msm_break_ctl,
714 .startup = msm_startup, 714 .startup = msm_startup,
715 .shutdown = msm_shutdown, 715 .shutdown = msm_shutdown,
716 .set_termios = msm_set_termios, 716 .set_termios = msm_set_termios,
717 .type = msm_type, 717 .type = msm_type,
718 .release_port = msm_release_port, 718 .release_port = msm_release_port,
719 .request_port = msm_request_port, 719 .request_port = msm_request_port,
720 .config_port = msm_config_port, 720 .config_port = msm_config_port,
721 .verify_port = msm_verify_port, 721 .verify_port = msm_verify_port,
722 .pm = msm_power, 722 .pm = msm_power,
723 }; 723 };
724 724
725 static struct msm_port msm_uart_ports[] = { 725 static struct msm_port msm_uart_ports[] = {
726 { 726 {
727 .uart = { 727 .uart = {
728 .iotype = UPIO_MEM, 728 .iotype = UPIO_MEM,
729 .ops = &msm_uart_pops, 729 .ops = &msm_uart_pops,
730 .flags = UPF_BOOT_AUTOCONF, 730 .flags = UPF_BOOT_AUTOCONF,
731 .fifosize = 64, 731 .fifosize = 64,
732 .line = 0, 732 .line = 0,
733 }, 733 },
734 }, 734 },
735 { 735 {
736 .uart = { 736 .uart = {
737 .iotype = UPIO_MEM, 737 .iotype = UPIO_MEM,
738 .ops = &msm_uart_pops, 738 .ops = &msm_uart_pops,
739 .flags = UPF_BOOT_AUTOCONF, 739 .flags = UPF_BOOT_AUTOCONF,
740 .fifosize = 64, 740 .fifosize = 64,
741 .line = 1, 741 .line = 1,
742 }, 742 },
743 }, 743 },
744 { 744 {
745 .uart = { 745 .uart = {
746 .iotype = UPIO_MEM, 746 .iotype = UPIO_MEM,
747 .ops = &msm_uart_pops, 747 .ops = &msm_uart_pops,
748 .flags = UPF_BOOT_AUTOCONF, 748 .flags = UPF_BOOT_AUTOCONF,
749 .fifosize = 64, 749 .fifosize = 64,
750 .line = 2, 750 .line = 2,
751 }, 751 },
752 }, 752 },
753 }; 753 };
754 754
755 #define UART_NR ARRAY_SIZE(msm_uart_ports) 755 #define UART_NR ARRAY_SIZE(msm_uart_ports)
756 756
757 static inline struct uart_port *get_port_from_line(unsigned int line) 757 static inline struct uart_port *get_port_from_line(unsigned int line)
758 { 758 {
759 return &msm_uart_ports[line].uart; 759 return &msm_uart_ports[line].uart;
760 } 760 }
761 761
762 #ifdef CONFIG_SERIAL_MSM_CONSOLE 762 #ifdef CONFIG_SERIAL_MSM_CONSOLE
763 763
764 static void msm_console_putchar(struct uart_port *port, int c) 764 static void msm_console_putchar(struct uart_port *port, int c)
765 { 765 {
766 struct msm_port *msm_port = UART_TO_MSM(port); 766 struct msm_port *msm_port = UART_TO_MSM(port);
767 767
768 if (msm_port->is_uartdm) 768 if (msm_port->is_uartdm)
769 reset_dm_count(port); 769 reset_dm_count(port);
770 770
771 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) 771 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
772 ; 772 ;
773 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF); 773 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
774 } 774 }
775 775
776 static void msm_console_write(struct console *co, const char *s, 776 static void msm_console_write(struct console *co, const char *s,
777 unsigned int count) 777 unsigned int count)
778 { 778 {
779 struct uart_port *port; 779 struct uart_port *port;
780 struct msm_port *msm_port; 780 struct msm_port *msm_port;
781 781
782 BUG_ON(co->index < 0 || co->index >= UART_NR); 782 BUG_ON(co->index < 0 || co->index >= UART_NR);
783 783
784 port = get_port_from_line(co->index); 784 port = get_port_from_line(co->index);
785 msm_port = UART_TO_MSM(port); 785 msm_port = UART_TO_MSM(port);
786 786
787 spin_lock(&port->lock); 787 spin_lock(&port->lock);
788 uart_console_write(port, s, count, msm_console_putchar); 788 uart_console_write(port, s, count, msm_console_putchar);
789 spin_unlock(&port->lock); 789 spin_unlock(&port->lock);
790 } 790 }
791 791
792 static int __init msm_console_setup(struct console *co, char *options) 792 static int __init msm_console_setup(struct console *co, char *options)
793 { 793 {
794 struct uart_port *port; 794 struct uart_port *port;
795 struct msm_port *msm_port; 795 struct msm_port *msm_port;
796 int baud, flow, bits, parity; 796 int baud, flow, bits, parity;
797 797
798 if (unlikely(co->index >= UART_NR || co->index < 0)) 798 if (unlikely(co->index >= UART_NR || co->index < 0))
799 return -ENXIO; 799 return -ENXIO;
800 800
801 port = get_port_from_line(co->index); 801 port = get_port_from_line(co->index);
802 msm_port = UART_TO_MSM(port); 802 msm_port = UART_TO_MSM(port);
803 803
804 if (unlikely(!port->membase)) 804 if (unlikely(!port->membase))
805 return -ENXIO; 805 return -ENXIO;
806 806
807 msm_init_clock(port); 807 msm_init_clock(port);
808 808
809 if (options) 809 if (options)
810 uart_parse_options(options, &baud, &parity, &bits, &flow); 810 uart_parse_options(options, &baud, &parity, &bits, &flow);
811 811
812 bits = 8; 812 bits = 8;
813 parity = 'n'; 813 parity = 'n';
814 flow = 'n'; 814 flow = 'n';
815 msm_write(port, UART_MR2_BITS_PER_CHAR_8 | UART_MR2_STOP_BIT_LEN_ONE, 815 msm_write(port, UART_MR2_BITS_PER_CHAR_8 | UART_MR2_STOP_BIT_LEN_ONE,
816 UART_MR2); /* 8N1 */ 816 UART_MR2); /* 8N1 */
817 817
818 if (baud < 300 || baud > 115200) 818 if (baud < 300 || baud > 115200)
819 baud = 115200; 819 baud = 115200;
820 msm_set_baud_rate(port, baud); 820 msm_set_baud_rate(port, baud);
821 821
822 msm_reset(port); 822 msm_reset(port);
823 823
824 if (msm_port->is_uartdm) { 824 if (msm_port->is_uartdm) {
825 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR); 825 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
826 msm_write(port, UART_CR_TX_ENABLE, UART_CR); 826 msm_write(port, UART_CR_TX_ENABLE, UART_CR);
827 } 827 }
828 828
829 printk(KERN_INFO "msm_serial: console setup on port #%d\n", port->line); 829 printk(KERN_INFO "msm_serial: console setup on port #%d\n", port->line);
830 830
831 return uart_set_options(port, co, baud, parity, bits, flow); 831 return uart_set_options(port, co, baud, parity, bits, flow);
832 } 832 }
833 833
834 static struct uart_driver msm_uart_driver; 834 static struct uart_driver msm_uart_driver;
835 835
836 static struct console msm_console = { 836 static struct console msm_console = {
837 .name = "ttyMSM", 837 .name = "ttyMSM",
838 .write = msm_console_write, 838 .write = msm_console_write,
839 .device = uart_console_device, 839 .device = uart_console_device,
840 .setup = msm_console_setup, 840 .setup = msm_console_setup,
841 .flags = CON_PRINTBUFFER, 841 .flags = CON_PRINTBUFFER,
842 .index = -1, 842 .index = -1,
843 .data = &msm_uart_driver, 843 .data = &msm_uart_driver,
844 }; 844 };
845 845
846 #define MSM_CONSOLE (&msm_console) 846 #define MSM_CONSOLE (&msm_console)
847 847
848 #else 848 #else
849 #define MSM_CONSOLE NULL 849 #define MSM_CONSOLE NULL
850 #endif 850 #endif
851 851
852 static struct uart_driver msm_uart_driver = { 852 static struct uart_driver msm_uart_driver = {
853 .owner = THIS_MODULE, 853 .owner = THIS_MODULE,
854 .driver_name = "msm_serial", 854 .driver_name = "msm_serial",
855 .dev_name = "ttyMSM", 855 .dev_name = "ttyMSM",
856 .nr = UART_NR, 856 .nr = UART_NR,
857 .cons = MSM_CONSOLE, 857 .cons = MSM_CONSOLE,
858 }; 858 };
859 859
860 static atomic_t msm_uart_next_id = ATOMIC_INIT(0); 860 static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
861 861
862 static int __init msm_serial_probe(struct platform_device *pdev) 862 static int __init msm_serial_probe(struct platform_device *pdev)
863 { 863 {
864 struct msm_port *msm_port; 864 struct msm_port *msm_port;
865 struct resource *resource; 865 struct resource *resource;
866 struct uart_port *port; 866 struct uart_port *port;
867 int irq; 867 int irq;
868 868
869 if (pdev->id == -1) 869 if (pdev->id == -1)
870 pdev->id = atomic_inc_return(&msm_uart_next_id) - 1; 870 pdev->id = atomic_inc_return(&msm_uart_next_id) - 1;
871 871
872 if (unlikely(pdev->id < 0 || pdev->id >= UART_NR)) 872 if (unlikely(pdev->id < 0 || pdev->id >= UART_NR))
873 return -ENXIO; 873 return -ENXIO;
874 874
875 printk(KERN_INFO "msm_serial: detected port #%d\n", pdev->id); 875 printk(KERN_INFO "msm_serial: detected port #%d\n", pdev->id);
876 876
877 port = get_port_from_line(pdev->id); 877 port = get_port_from_line(pdev->id);
878 port->dev = &pdev->dev; 878 port->dev = &pdev->dev;
879 msm_port = UART_TO_MSM(port); 879 msm_port = UART_TO_MSM(port);
880 880
881 if (platform_get_resource(pdev, IORESOURCE_MEM, 1)) 881 if (platform_get_resource(pdev, IORESOURCE_MEM, 1))
882 msm_port->is_uartdm = 1; 882 msm_port->is_uartdm = 1;
883 else 883 else
884 msm_port->is_uartdm = 0; 884 msm_port->is_uartdm = 0;
885 885
886 if (msm_port->is_uartdm) { 886 if (msm_port->is_uartdm) {
887 msm_port->clk = clk_get(&pdev->dev, "gsbi_uart_clk"); 887 msm_port->clk = devm_clk_get(&pdev->dev, "gsbi_uart_clk");
888 msm_port->pclk = clk_get(&pdev->dev, "gsbi_pclk"); 888 msm_port->pclk = devm_clk_get(&pdev->dev, "gsbi_pclk");
889 } else { 889 } else {
890 msm_port->clk = clk_get(&pdev->dev, "uart_clk"); 890 msm_port->clk = devm_clk_get(&pdev->dev, "uart_clk");
891 msm_port->pclk = ERR_PTR(-ENOENT); 891 msm_port->pclk = ERR_PTR(-ENOENT);
892 } 892 }
893 893
894 if (unlikely(IS_ERR(msm_port->clk) || (IS_ERR(msm_port->pclk) && 894 if (IS_ERR(msm_port->clk))
895 msm_port->is_uartdm))) 895 return PTR_ERR(msm_port->clk);
896 return PTR_ERR(msm_port->clk);
897 896
898 if (msm_port->is_uartdm) 897 if (msm_port->is_uartdm) {
898 if (IS_ERR(msm_port->pclk))
899 return PTR_ERR(msm_port->pclk);
900
899 clk_set_rate(msm_port->clk, 1843200); 901 clk_set_rate(msm_port->clk, 1843200);
902 }
900 903
901 port->uartclk = clk_get_rate(msm_port->clk); 904 port->uartclk = clk_get_rate(msm_port->clk);
902 printk(KERN_INFO "uartclk = %d\n", port->uartclk); 905 printk(KERN_INFO "uartclk = %d\n", port->uartclk);
903 906
904 907
905 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 908 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
906 if (unlikely(!resource)) 909 if (unlikely(!resource))
907 return -ENXIO; 910 return -ENXIO;
908 port->mapbase = resource->start; 911 port->mapbase = resource->start;
909 912
910 irq = platform_get_irq(pdev, 0); 913 irq = platform_get_irq(pdev, 0);
911 if (unlikely(irq < 0)) 914 if (unlikely(irq < 0))
912 return -ENXIO; 915 return -ENXIO;
913 port->irq = irq; 916 port->irq = irq;
914 917
915 platform_set_drvdata(pdev, port); 918 platform_set_drvdata(pdev, port);
916 919
917 return uart_add_one_port(&msm_uart_driver, port); 920 return uart_add_one_port(&msm_uart_driver, port);
918 } 921 }
919 922
920 static int msm_serial_remove(struct platform_device *pdev) 923 static int msm_serial_remove(struct platform_device *pdev)
921 { 924 {
922 struct msm_port *msm_port = platform_get_drvdata(pdev); 925 struct uart_port *port = platform_get_drvdata(pdev);
923 926
924 clk_put(msm_port->clk); 927 uart_remove_one_port(&msm_uart_driver, port);
925 928
926 return 0; 929 return 0;
927 } 930 }
928 931
929 static struct of_device_id msm_match_table[] = { 932 static struct of_device_id msm_match_table[] = {
930 { .compatible = "qcom,msm-uart" }, 933 { .compatible = "qcom,msm-uart" },
931 {} 934 {}
932 }; 935 };
933 936
934 static struct platform_driver msm_platform_driver = { 937 static struct platform_driver msm_platform_driver = {
935 .remove = msm_serial_remove, 938 .remove = msm_serial_remove,
936 .driver = { 939 .driver = {
937 .name = "msm_serial", 940 .name = "msm_serial",
938 .owner = THIS_MODULE, 941 .owner = THIS_MODULE,
939 .of_match_table = msm_match_table, 942 .of_match_table = msm_match_table,
940 }, 943 },
941 }; 944 };
942 945
943 static int __init msm_serial_init(void) 946 static int __init msm_serial_init(void)
944 { 947 {
945 int ret; 948 int ret;
946 949
947 ret = uart_register_driver(&msm_uart_driver); 950 ret = uart_register_driver(&msm_uart_driver);
948 if (unlikely(ret)) 951 if (unlikely(ret))
949 return ret; 952 return ret;
950 953
951 ret = platform_driver_probe(&msm_platform_driver, msm_serial_probe); 954 ret = platform_driver_probe(&msm_platform_driver, msm_serial_probe);
952 if (unlikely(ret)) 955 if (unlikely(ret))
953 uart_unregister_driver(&msm_uart_driver); 956 uart_unregister_driver(&msm_uart_driver);
954 957
955 printk(KERN_INFO "msm_serial: driver initialized\n"); 958 printk(KERN_INFO "msm_serial: driver initialized\n");
956 959
957 return ret; 960 return ret;
958 } 961 }
959 962
960 static void __exit msm_serial_exit(void) 963 static void __exit msm_serial_exit(void)
961 { 964 {
962 #ifdef CONFIG_SERIAL_MSM_CONSOLE 965 #ifdef CONFIG_SERIAL_MSM_CONSOLE
963 unregister_console(&msm_console); 966 unregister_console(&msm_console);
964 #endif 967 #endif
965 platform_driver_unregister(&msm_platform_driver); 968 platform_driver_unregister(&msm_platform_driver);
966 uart_unregister_driver(&msm_uart_driver); 969 uart_unregister_driver(&msm_uart_driver);
967 } 970 }
968 971
969 module_init(msm_serial_init); 972 module_init(msm_serial_init);
970 module_exit(msm_serial_exit); 973 module_exit(msm_serial_exit);
971 974
972 MODULE_AUTHOR("Robert Love <rlove@google.com>"); 975 MODULE_AUTHOR("Robert Love <rlove@google.com>");
973 MODULE_DESCRIPTION("Driver for msm7x serial device"); 976 MODULE_DESCRIPTION("Driver for msm7x serial device");
974 MODULE_LICENSE("GPL"); 977 MODULE_LICENSE("GPL");