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Commit 52c0eee3329b08dfd912a59e0246e21026308301

Authored by Mark Brown
1 parent 8b5eae137b
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

ASoC: wm8962: Don't duplicate bias level management in resume 

The core will bring the bias level up for us since we use idle_bias_off,
duplicating this may be harmful.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

Showing 1 changed file with 0 additions and 15 deletions Inline Diff

sound/soc/codecs/wm8962.c
Diff comments   View file @ 52c0eee
1 /* 1 /*
2 * wm8962.c -- WM8962 ALSA SoC Audio driver 2 * wm8962.c -- WM8962 ALSA SoC Audio driver
3 * 3 *
4 * Copyright 2010-2 Wolfson Microelectronics plc 4 * Copyright 2010-2 Wolfson Microelectronics plc
5 * 5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 * 7 *
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 */ 12 */
13 13
14 #include <linux/module.h> 14 #include <linux/module.h>
15 #include <linux/moduleparam.h> 15 #include <linux/moduleparam.h>
16 #include <linux/init.h> 16 #include <linux/init.h>
17 #include <linux/delay.h> 17 #include <linux/delay.h>
18 #include <linux/pm.h> 18 #include <linux/pm.h>
19 #include <linux/gcd.h> 19 #include <linux/gcd.h>
20 #include <linux/gpio.h> 20 #include <linux/gpio.h>
21 #include <linux/i2c.h> 21 #include <linux/i2c.h>
22 #include <linux/input.h> 22 #include <linux/input.h>
23 #include <linux/pm_runtime.h> 23 #include <linux/pm_runtime.h>
24 #include <linux/regmap.h> 24 #include <linux/regmap.h>
25 #include <linux/regulator/consumer.h> 25 #include <linux/regulator/consumer.h>
26 #include <linux/slab.h> 26 #include <linux/slab.h>
27 #include <linux/workqueue.h> 27 #include <linux/workqueue.h>
28 #include <sound/core.h> 28 #include <sound/core.h>
29 #include <sound/jack.h> 29 #include <sound/jack.h>
30 #include <sound/pcm.h> 30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h> 31 #include <sound/pcm_params.h>
32 #include <sound/soc.h> 32 #include <sound/soc.h>
33 #include <sound/initval.h> 33 #include <sound/initval.h>
34 #include <sound/tlv.h> 34 #include <sound/tlv.h>
35 #include <sound/wm8962.h> 35 #include <sound/wm8962.h>
36 #include <trace/events/asoc.h> 36 #include <trace/events/asoc.h>
37 37
38 #include "wm8962.h" 38 #include "wm8962.h"
39 39
40 #define WM8962_NUM_SUPPLIES 8 40 #define WM8962_NUM_SUPPLIES 8
41 static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = { 41 static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = {
42 "DCVDD", 42 "DCVDD",
43 "DBVDD", 43 "DBVDD",
44 "AVDD", 44 "AVDD",
45 "CPVDD", 45 "CPVDD",
46 "MICVDD", 46 "MICVDD",
47 "PLLVDD", 47 "PLLVDD",
48 "SPKVDD1", 48 "SPKVDD1",
49 "SPKVDD2", 49 "SPKVDD2",
50 }; 50 };
51 51
52 /* codec private data */ 52 /* codec private data */
53 struct wm8962_priv { 53 struct wm8962_priv {
54 struct regmap *regmap; 54 struct regmap *regmap;
55 struct snd_soc_codec *codec; 55 struct snd_soc_codec *codec;
56 56
57 int sysclk; 57 int sysclk;
58 int sysclk_rate; 58 int sysclk_rate;
59 59
60 int bclk; /* Desired BCLK */ 60 int bclk; /* Desired BCLK */
61 int lrclk; 61 int lrclk;
62 62
63 struct completion fll_lock; 63 struct completion fll_lock;
64 int fll_src; 64 int fll_src;
65 int fll_fref; 65 int fll_fref;
66 int fll_fout; 66 int fll_fout;
67 67
68 u16 dsp2_ena; 68 u16 dsp2_ena;
69 69
70 struct delayed_work mic_work; 70 struct delayed_work mic_work;
71 struct snd_soc_jack *jack; 71 struct snd_soc_jack *jack;
72 72
73 struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES]; 73 struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES];
74 struct notifier_block disable_nb[WM8962_NUM_SUPPLIES]; 74 struct notifier_block disable_nb[WM8962_NUM_SUPPLIES];
75 75
76 #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE) 76 #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
77 struct input_dev *beep; 77 struct input_dev *beep;
78 struct work_struct beep_work; 78 struct work_struct beep_work;
79 int beep_rate; 79 int beep_rate;
80 #endif 80 #endif
81 81
82 #ifdef CONFIG_GPIOLIB 82 #ifdef CONFIG_GPIOLIB
83 struct gpio_chip gpio_chip; 83 struct gpio_chip gpio_chip;
84 #endif 84 #endif
85 85
86 int irq; 86 int irq;
87 }; 87 };
88 88
89 /* We can't use the same notifier block for more than one supply and 89 /* We can't use the same notifier block for more than one supply and
90 * there's no way I can see to get from a callback to the caller 90 * there's no way I can see to get from a callback to the caller
91 * except container_of(). 91 * except container_of().
92 */ 92 */
93 #define WM8962_REGULATOR_EVENT(n) \ 93 #define WM8962_REGULATOR_EVENT(n) \
94 static int wm8962_regulator_event_##n(struct notifier_block *nb, \ 94 static int wm8962_regulator_event_##n(struct notifier_block *nb, \
95 unsigned long event, void *data) \ 95 unsigned long event, void *data) \
96 { \ 96 { \
97 struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \ 97 struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \
98 disable_nb[n]); \ 98 disable_nb[n]); \
99 if (event & REGULATOR_EVENT_DISABLE) { \ 99 if (event & REGULATOR_EVENT_DISABLE) { \
100 regcache_mark_dirty(wm8962->regmap); \ 100 regcache_mark_dirty(wm8962->regmap); \
101 } \ 101 } \
102 return 0; \ 102 return 0; \
103 } 103 }
104 104
105 WM8962_REGULATOR_EVENT(0) 105 WM8962_REGULATOR_EVENT(0)
106 WM8962_REGULATOR_EVENT(1) 106 WM8962_REGULATOR_EVENT(1)
107 WM8962_REGULATOR_EVENT(2) 107 WM8962_REGULATOR_EVENT(2)
108 WM8962_REGULATOR_EVENT(3) 108 WM8962_REGULATOR_EVENT(3)
109 WM8962_REGULATOR_EVENT(4) 109 WM8962_REGULATOR_EVENT(4)
110 WM8962_REGULATOR_EVENT(5) 110 WM8962_REGULATOR_EVENT(5)
111 WM8962_REGULATOR_EVENT(6) 111 WM8962_REGULATOR_EVENT(6)
112 WM8962_REGULATOR_EVENT(7) 112 WM8962_REGULATOR_EVENT(7)
113 113
114 static struct reg_default wm8962_reg[] = { 114 static struct reg_default wm8962_reg[] = {
115 { 0, 0x009F }, /* R0 - Left Input volume */ 115 { 0, 0x009F }, /* R0 - Left Input volume */
116 { 1, 0x049F }, /* R1 - Right Input volume */ 116 { 1, 0x049F }, /* R1 - Right Input volume */
117 { 2, 0x0000 }, /* R2 - HPOUTL volume */ 117 { 2, 0x0000 }, /* R2 - HPOUTL volume */
118 { 3, 0x0000 }, /* R3 - HPOUTR volume */ 118 { 3, 0x0000 }, /* R3 - HPOUTR volume */
119 119
120 { 5, 0x0018 }, /* R5 - ADC & DAC Control 1 */ 120 { 5, 0x0018 }, /* R5 - ADC & DAC Control 1 */
121 { 6, 0x2008 }, /* R6 - ADC & DAC Control 2 */ 121 { 6, 0x2008 }, /* R6 - ADC & DAC Control 2 */
122 { 7, 0x000A }, /* R7 - Audio Interface 0 */ 122 { 7, 0x000A }, /* R7 - Audio Interface 0 */
123 123
124 { 9, 0x0300 }, /* R9 - Audio Interface 1 */ 124 { 9, 0x0300 }, /* R9 - Audio Interface 1 */
125 { 10, 0x00C0 }, /* R10 - Left DAC volume */ 125 { 10, 0x00C0 }, /* R10 - Left DAC volume */
126 { 11, 0x00C0 }, /* R11 - Right DAC volume */ 126 { 11, 0x00C0 }, /* R11 - Right DAC volume */
127 127
128 { 14, 0x0040 }, /* R14 - Audio Interface 2 */ 128 { 14, 0x0040 }, /* R14 - Audio Interface 2 */
129 { 15, 0x6243 }, /* R15 - Software Reset */ 129 { 15, 0x6243 }, /* R15 - Software Reset */
130 130
131 { 17, 0x007B }, /* R17 - ALC1 */ 131 { 17, 0x007B }, /* R17 - ALC1 */
132 132
133 { 19, 0x1C32 }, /* R19 - ALC3 */ 133 { 19, 0x1C32 }, /* R19 - ALC3 */
134 { 20, 0x3200 }, /* R20 - Noise Gate */ 134 { 20, 0x3200 }, /* R20 - Noise Gate */
135 { 21, 0x00C0 }, /* R21 - Left ADC volume */ 135 { 21, 0x00C0 }, /* R21 - Left ADC volume */
136 { 22, 0x00C0 }, /* R22 - Right ADC volume */ 136 { 22, 0x00C0 }, /* R22 - Right ADC volume */
137 { 23, 0x0160 }, /* R23 - Additional control(1) */ 137 { 23, 0x0160 }, /* R23 - Additional control(1) */
138 { 24, 0x0000 }, /* R24 - Additional control(2) */ 138 { 24, 0x0000 }, /* R24 - Additional control(2) */
139 { 25, 0x0000 }, /* R25 - Pwr Mgmt (1) */ 139 { 25, 0x0000 }, /* R25 - Pwr Mgmt (1) */
140 { 26, 0x0000 }, /* R26 - Pwr Mgmt (2) */ 140 { 26, 0x0000 }, /* R26 - Pwr Mgmt (2) */
141 { 27, 0x0010 }, /* R27 - Additional Control (3) */ 141 { 27, 0x0010 }, /* R27 - Additional Control (3) */
142 { 28, 0x0000 }, /* R28 - Anti-pop */ 142 { 28, 0x0000 }, /* R28 - Anti-pop */
143 143
144 { 30, 0x005E }, /* R30 - Clocking 3 */ 144 { 30, 0x005E }, /* R30 - Clocking 3 */
145 { 31, 0x0000 }, /* R31 - Input mixer control (1) */ 145 { 31, 0x0000 }, /* R31 - Input mixer control (1) */
146 { 32, 0x0145 }, /* R32 - Left input mixer volume */ 146 { 32, 0x0145 }, /* R32 - Left input mixer volume */
147 { 33, 0x0145 }, /* R33 - Right input mixer volume */ 147 { 33, 0x0145 }, /* R33 - Right input mixer volume */
148 { 34, 0x0009 }, /* R34 - Input mixer control (2) */ 148 { 34, 0x0009 }, /* R34 - Input mixer control (2) */
149 { 35, 0x0003 }, /* R35 - Input bias control */ 149 { 35, 0x0003 }, /* R35 - Input bias control */
150 { 37, 0x0008 }, /* R37 - Left input PGA control */ 150 { 37, 0x0008 }, /* R37 - Left input PGA control */
151 { 38, 0x0008 }, /* R38 - Right input PGA control */ 151 { 38, 0x0008 }, /* R38 - Right input PGA control */
152 152
153 { 40, 0x0000 }, /* R40 - SPKOUTL volume */ 153 { 40, 0x0000 }, /* R40 - SPKOUTL volume */
154 { 41, 0x0000 }, /* R41 - SPKOUTR volume */ 154 { 41, 0x0000 }, /* R41 - SPKOUTR volume */
155 155
156 { 51, 0x0003 }, /* R51 - Class D Control 2 */ 156 { 51, 0x0003 }, /* R51 - Class D Control 2 */
157 157
158 { 56, 0x0506 }, /* R56 - Clocking 4 */ 158 { 56, 0x0506 }, /* R56 - Clocking 4 */
159 { 57, 0x0000 }, /* R57 - DAC DSP Mixing (1) */ 159 { 57, 0x0000 }, /* R57 - DAC DSP Mixing (1) */
160 { 58, 0x0000 }, /* R58 - DAC DSP Mixing (2) */ 160 { 58, 0x0000 }, /* R58 - DAC DSP Mixing (2) */
161 161
162 { 60, 0x0300 }, /* R60 - DC Servo 0 */ 162 { 60, 0x0300 }, /* R60 - DC Servo 0 */
163 { 61, 0x0300 }, /* R61 - DC Servo 1 */ 163 { 61, 0x0300 }, /* R61 - DC Servo 1 */
164 164
165 { 64, 0x0810 }, /* R64 - DC Servo 4 */ 165 { 64, 0x0810 }, /* R64 - DC Servo 4 */
166 166
167 { 68, 0x001B }, /* R68 - Analogue PGA Bias */ 167 { 68, 0x001B }, /* R68 - Analogue PGA Bias */
168 { 69, 0x0000 }, /* R69 - Analogue HP 0 */ 168 { 69, 0x0000 }, /* R69 - Analogue HP 0 */
169 169
170 { 71, 0x01FB }, /* R71 - Analogue HP 2 */ 170 { 71, 0x01FB }, /* R71 - Analogue HP 2 */
171 { 72, 0x0000 }, /* R72 - Charge Pump 1 */ 171 { 72, 0x0000 }, /* R72 - Charge Pump 1 */
172 172
173 { 82, 0x0004 }, /* R82 - Charge Pump B */ 173 { 82, 0x0004 }, /* R82 - Charge Pump B */
174 174
175 { 87, 0x0000 }, /* R87 - Write Sequencer Control 1 */ 175 { 87, 0x0000 }, /* R87 - Write Sequencer Control 1 */
176 176
177 { 90, 0x0000 }, /* R90 - Write Sequencer Control 2 */ 177 { 90, 0x0000 }, /* R90 - Write Sequencer Control 2 */
178 178
179 { 93, 0x0000 }, /* R93 - Write Sequencer Control 3 */ 179 { 93, 0x0000 }, /* R93 - Write Sequencer Control 3 */
180 { 94, 0x0000 }, /* R94 - Control Interface */ 180 { 94, 0x0000 }, /* R94 - Control Interface */
181 181
182 { 99, 0x0000 }, /* R99 - Mixer Enables */ 182 { 99, 0x0000 }, /* R99 - Mixer Enables */
183 { 100, 0x0000 }, /* R100 - Headphone Mixer (1) */ 183 { 100, 0x0000 }, /* R100 - Headphone Mixer (1) */
184 { 101, 0x0000 }, /* R101 - Headphone Mixer (2) */ 184 { 101, 0x0000 }, /* R101 - Headphone Mixer (2) */
185 { 102, 0x013F }, /* R102 - Headphone Mixer (3) */ 185 { 102, 0x013F }, /* R102 - Headphone Mixer (3) */
186 { 103, 0x013F }, /* R103 - Headphone Mixer (4) */ 186 { 103, 0x013F }, /* R103 - Headphone Mixer (4) */
187 187
188 { 105, 0x0000 }, /* R105 - Speaker Mixer (1) */ 188 { 105, 0x0000 }, /* R105 - Speaker Mixer (1) */
189 { 106, 0x0000 }, /* R106 - Speaker Mixer (2) */ 189 { 106, 0x0000 }, /* R106 - Speaker Mixer (2) */
190 { 107, 0x013F }, /* R107 - Speaker Mixer (3) */ 190 { 107, 0x013F }, /* R107 - Speaker Mixer (3) */
191 { 108, 0x013F }, /* R108 - Speaker Mixer (4) */ 191 { 108, 0x013F }, /* R108 - Speaker Mixer (4) */
192 { 109, 0x0003 }, /* R109 - Speaker Mixer (5) */ 192 { 109, 0x0003 }, /* R109 - Speaker Mixer (5) */
193 { 110, 0x0002 }, /* R110 - Beep Generator (1) */ 193 { 110, 0x0002 }, /* R110 - Beep Generator (1) */
194 194
195 { 115, 0x0006 }, /* R115 - Oscillator Trim (3) */ 195 { 115, 0x0006 }, /* R115 - Oscillator Trim (3) */
196 { 116, 0x0026 }, /* R116 - Oscillator Trim (4) */ 196 { 116, 0x0026 }, /* R116 - Oscillator Trim (4) */
197 197
198 { 119, 0x0000 }, /* R119 - Oscillator Trim (7) */ 198 { 119, 0x0000 }, /* R119 - Oscillator Trim (7) */
199 199
200 { 124, 0x0011 }, /* R124 - Analogue Clocking1 */ 200 { 124, 0x0011 }, /* R124 - Analogue Clocking1 */
201 { 125, 0x004B }, /* R125 - Analogue Clocking2 */ 201 { 125, 0x004B }, /* R125 - Analogue Clocking2 */
202 { 126, 0x000D }, /* R126 - Analogue Clocking3 */ 202 { 126, 0x000D }, /* R126 - Analogue Clocking3 */
203 { 127, 0x0000 }, /* R127 - PLL Software Reset */ 203 { 127, 0x0000 }, /* R127 - PLL Software Reset */
204 204
205 { 131, 0x0000 }, /* R131 - PLL 4 */ 205 { 131, 0x0000 }, /* R131 - PLL 4 */
206 206
207 { 136, 0x0067 }, /* R136 - PLL 9 */ 207 { 136, 0x0067 }, /* R136 - PLL 9 */
208 { 137, 0x001C }, /* R137 - PLL 10 */ 208 { 137, 0x001C }, /* R137 - PLL 10 */
209 { 138, 0x0071 }, /* R138 - PLL 11 */ 209 { 138, 0x0071 }, /* R138 - PLL 11 */
210 { 139, 0x00C7 }, /* R139 - PLL 12 */ 210 { 139, 0x00C7 }, /* R139 - PLL 12 */
211 { 140, 0x0067 }, /* R140 - PLL 13 */ 211 { 140, 0x0067 }, /* R140 - PLL 13 */
212 { 141, 0x0048 }, /* R141 - PLL 14 */ 212 { 141, 0x0048 }, /* R141 - PLL 14 */
213 { 142, 0x0022 }, /* R142 - PLL 15 */ 213 { 142, 0x0022 }, /* R142 - PLL 15 */
214 { 143, 0x0097 }, /* R143 - PLL 16 */ 214 { 143, 0x0097 }, /* R143 - PLL 16 */
215 215
216 { 155, 0x000C }, /* R155 - FLL Control (1) */ 216 { 155, 0x000C }, /* R155 - FLL Control (1) */
217 { 156, 0x0039 }, /* R156 - FLL Control (2) */ 217 { 156, 0x0039 }, /* R156 - FLL Control (2) */
218 { 157, 0x0180 }, /* R157 - FLL Control (3) */ 218 { 157, 0x0180 }, /* R157 - FLL Control (3) */
219 219
220 { 159, 0x0032 }, /* R159 - FLL Control (5) */ 220 { 159, 0x0032 }, /* R159 - FLL Control (5) */
221 { 160, 0x0018 }, /* R160 - FLL Control (6) */ 221 { 160, 0x0018 }, /* R160 - FLL Control (6) */
222 { 161, 0x007D }, /* R161 - FLL Control (7) */ 222 { 161, 0x007D }, /* R161 - FLL Control (7) */
223 { 162, 0x0008 }, /* R162 - FLL Control (8) */ 223 { 162, 0x0008 }, /* R162 - FLL Control (8) */
224 224
225 { 252, 0x0005 }, /* R252 - General test 1 */ 225 { 252, 0x0005 }, /* R252 - General test 1 */
226 226
227 { 256, 0x0000 }, /* R256 - DF1 */ 227 { 256, 0x0000 }, /* R256 - DF1 */
228 { 257, 0x0000 }, /* R257 - DF2 */ 228 { 257, 0x0000 }, /* R257 - DF2 */
229 { 258, 0x0000 }, /* R258 - DF3 */ 229 { 258, 0x0000 }, /* R258 - DF3 */
230 { 259, 0x0000 }, /* R259 - DF4 */ 230 { 259, 0x0000 }, /* R259 - DF4 */
231 { 260, 0x0000 }, /* R260 - DF5 */ 231 { 260, 0x0000 }, /* R260 - DF5 */
232 { 261, 0x0000 }, /* R261 - DF6 */ 232 { 261, 0x0000 }, /* R261 - DF6 */
233 { 262, 0x0000 }, /* R262 - DF7 */ 233 { 262, 0x0000 }, /* R262 - DF7 */
234 234
235 { 264, 0x0000 }, /* R264 - LHPF1 */ 235 { 264, 0x0000 }, /* R264 - LHPF1 */
236 { 265, 0x0000 }, /* R265 - LHPF2 */ 236 { 265, 0x0000 }, /* R265 - LHPF2 */
237 237
238 { 268, 0x0000 }, /* R268 - THREED1 */ 238 { 268, 0x0000 }, /* R268 - THREED1 */
239 { 269, 0x0000 }, /* R269 - THREED2 */ 239 { 269, 0x0000 }, /* R269 - THREED2 */
240 { 270, 0x0000 }, /* R270 - THREED3 */ 240 { 270, 0x0000 }, /* R270 - THREED3 */
241 { 271, 0x0000 }, /* R271 - THREED4 */ 241 { 271, 0x0000 }, /* R271 - THREED4 */
242 242
243 { 276, 0x000C }, /* R276 - DRC 1 */ 243 { 276, 0x000C }, /* R276 - DRC 1 */
244 { 277, 0x0925 }, /* R277 - DRC 2 */ 244 { 277, 0x0925 }, /* R277 - DRC 2 */
245 { 278, 0x0000 }, /* R278 - DRC 3 */ 245 { 278, 0x0000 }, /* R278 - DRC 3 */
246 { 279, 0x0000 }, /* R279 - DRC 4 */ 246 { 279, 0x0000 }, /* R279 - DRC 4 */
247 { 280, 0x0000 }, /* R280 - DRC 5 */ 247 { 280, 0x0000 }, /* R280 - DRC 5 */
248 248
249 { 285, 0x0000 }, /* R285 - Tloopback */ 249 { 285, 0x0000 }, /* R285 - Tloopback */
250 250
251 { 335, 0x0004 }, /* R335 - EQ1 */ 251 { 335, 0x0004 }, /* R335 - EQ1 */
252 { 336, 0x6318 }, /* R336 - EQ2 */ 252 { 336, 0x6318 }, /* R336 - EQ2 */
253 { 337, 0x6300 }, /* R337 - EQ3 */ 253 { 337, 0x6300 }, /* R337 - EQ3 */
254 { 338, 0x0FCA }, /* R338 - EQ4 */ 254 { 338, 0x0FCA }, /* R338 - EQ4 */
255 { 339, 0x0400 }, /* R339 - EQ5 */ 255 { 339, 0x0400 }, /* R339 - EQ5 */
256 { 340, 0x00D8 }, /* R340 - EQ6 */ 256 { 340, 0x00D8 }, /* R340 - EQ6 */
257 { 341, 0x1EB5 }, /* R341 - EQ7 */ 257 { 341, 0x1EB5 }, /* R341 - EQ7 */
258 { 342, 0xF145 }, /* R342 - EQ8 */ 258 { 342, 0xF145 }, /* R342 - EQ8 */
259 { 343, 0x0B75 }, /* R343 - EQ9 */ 259 { 343, 0x0B75 }, /* R343 - EQ9 */
260 { 344, 0x01C5 }, /* R344 - EQ10 */ 260 { 344, 0x01C5 }, /* R344 - EQ10 */
261 { 345, 0x1C58 }, /* R345 - EQ11 */ 261 { 345, 0x1C58 }, /* R345 - EQ11 */
262 { 346, 0xF373 }, /* R346 - EQ12 */ 262 { 346, 0xF373 }, /* R346 - EQ12 */
263 { 347, 0x0A54 }, /* R347 - EQ13 */ 263 { 347, 0x0A54 }, /* R347 - EQ13 */
264 { 348, 0x0558 }, /* R348 - EQ14 */ 264 { 348, 0x0558 }, /* R348 - EQ14 */
265 { 349, 0x168E }, /* R349 - EQ15 */ 265 { 349, 0x168E }, /* R349 - EQ15 */
266 { 350, 0xF829 }, /* R350 - EQ16 */ 266 { 350, 0xF829 }, /* R350 - EQ16 */
267 { 351, 0x07AD }, /* R351 - EQ17 */ 267 { 351, 0x07AD }, /* R351 - EQ17 */
268 { 352, 0x1103 }, /* R352 - EQ18 */ 268 { 352, 0x1103 }, /* R352 - EQ18 */
269 { 353, 0x0564 }, /* R353 - EQ19 */ 269 { 353, 0x0564 }, /* R353 - EQ19 */
270 { 354, 0x0559 }, /* R354 - EQ20 */ 270 { 354, 0x0559 }, /* R354 - EQ20 */
271 { 355, 0x4000 }, /* R355 - EQ21 */ 271 { 355, 0x4000 }, /* R355 - EQ21 */
272 { 356, 0x6318 }, /* R356 - EQ22 */ 272 { 356, 0x6318 }, /* R356 - EQ22 */
273 { 357, 0x6300 }, /* R357 - EQ23 */ 273 { 357, 0x6300 }, /* R357 - EQ23 */
274 { 358, 0x0FCA }, /* R358 - EQ24 */ 274 { 358, 0x0FCA }, /* R358 - EQ24 */
275 { 359, 0x0400 }, /* R359 - EQ25 */ 275 { 359, 0x0400 }, /* R359 - EQ25 */
276 { 360, 0x00D8 }, /* R360 - EQ26 */ 276 { 360, 0x00D8 }, /* R360 - EQ26 */
277 { 361, 0x1EB5 }, /* R361 - EQ27 */ 277 { 361, 0x1EB5 }, /* R361 - EQ27 */
278 { 362, 0xF145 }, /* R362 - EQ28 */ 278 { 362, 0xF145 }, /* R362 - EQ28 */
279 { 363, 0x0B75 }, /* R363 - EQ29 */ 279 { 363, 0x0B75 }, /* R363 - EQ29 */
280 { 364, 0x01C5 }, /* R364 - EQ30 */ 280 { 364, 0x01C5 }, /* R364 - EQ30 */
281 { 365, 0x1C58 }, /* R365 - EQ31 */ 281 { 365, 0x1C58 }, /* R365 - EQ31 */
282 { 366, 0xF373 }, /* R366 - EQ32 */ 282 { 366, 0xF373 }, /* R366 - EQ32 */
283 { 367, 0x0A54 }, /* R367 - EQ33 */ 283 { 367, 0x0A54 }, /* R367 - EQ33 */
284 { 368, 0x0558 }, /* R368 - EQ34 */ 284 { 368, 0x0558 }, /* R368 - EQ34 */
285 { 369, 0x168E }, /* R369 - EQ35 */ 285 { 369, 0x168E }, /* R369 - EQ35 */
286 { 370, 0xF829 }, /* R370 - EQ36 */ 286 { 370, 0xF829 }, /* R370 - EQ36 */
287 { 371, 0x07AD }, /* R371 - EQ37 */ 287 { 371, 0x07AD }, /* R371 - EQ37 */
288 { 372, 0x1103 }, /* R372 - EQ38 */ 288 { 372, 0x1103 }, /* R372 - EQ38 */
289 { 373, 0x0564 }, /* R373 - EQ39 */ 289 { 373, 0x0564 }, /* R373 - EQ39 */
290 { 374, 0x0559 }, /* R374 - EQ40 */ 290 { 374, 0x0559 }, /* R374 - EQ40 */
291 { 375, 0x4000 }, /* R375 - EQ41 */ 291 { 375, 0x4000 }, /* R375 - EQ41 */
292 292
293 { 513, 0x0000 }, /* R513 - GPIO 2 */ 293 { 513, 0x0000 }, /* R513 - GPIO 2 */
294 { 514, 0x0000 }, /* R514 - GPIO 3 */ 294 { 514, 0x0000 }, /* R514 - GPIO 3 */
295 295
296 { 516, 0x8100 }, /* R516 - GPIO 5 */ 296 { 516, 0x8100 }, /* R516 - GPIO 5 */
297 { 517, 0x8100 }, /* R517 - GPIO 6 */ 297 { 517, 0x8100 }, /* R517 - GPIO 6 */
298 298
299 { 568, 0x0030 }, /* R568 - Interrupt Status 1 Mask */ 299 { 568, 0x0030 }, /* R568 - Interrupt Status 1 Mask */
300 { 569, 0xFFED }, /* R569 - Interrupt Status 2 Mask */ 300 { 569, 0xFFED }, /* R569 - Interrupt Status 2 Mask */
301 301
302 { 576, 0x0000 }, /* R576 - Interrupt Control */ 302 { 576, 0x0000 }, /* R576 - Interrupt Control */
303 303
304 { 584, 0x002D }, /* R584 - IRQ Debounce */ 304 { 584, 0x002D }, /* R584 - IRQ Debounce */
305 305
306 { 586, 0x0000 }, /* R586 - MICINT Source Pol */ 306 { 586, 0x0000 }, /* R586 - MICINT Source Pol */
307 307
308 { 768, 0x1C00 }, /* R768 - DSP2 Power Management */ 308 { 768, 0x1C00 }, /* R768 - DSP2 Power Management */
309 309
310 { 8192, 0x0000 }, /* R8192 - DSP2 Instruction RAM 0 */ 310 { 8192, 0x0000 }, /* R8192 - DSP2 Instruction RAM 0 */
311 311
312 { 9216, 0x0030 }, /* R9216 - DSP2 Address RAM 2 */ 312 { 9216, 0x0030 }, /* R9216 - DSP2 Address RAM 2 */
313 { 9217, 0x0000 }, /* R9217 - DSP2 Address RAM 1 */ 313 { 9217, 0x0000 }, /* R9217 - DSP2 Address RAM 1 */
314 { 9218, 0x0000 }, /* R9218 - DSP2 Address RAM 0 */ 314 { 9218, 0x0000 }, /* R9218 - DSP2 Address RAM 0 */
315 315
316 { 12288, 0x0000 }, /* R12288 - DSP2 Data1 RAM 1 */ 316 { 12288, 0x0000 }, /* R12288 - DSP2 Data1 RAM 1 */
317 { 12289, 0x0000 }, /* R12289 - DSP2 Data1 RAM 0 */ 317 { 12289, 0x0000 }, /* R12289 - DSP2 Data1 RAM 0 */
318 318
319 { 13312, 0x0000 }, /* R13312 - DSP2 Data2 RAM 1 */ 319 { 13312, 0x0000 }, /* R13312 - DSP2 Data2 RAM 1 */
320 { 13313, 0x0000 }, /* R13313 - DSP2 Data2 RAM 0 */ 320 { 13313, 0x0000 }, /* R13313 - DSP2 Data2 RAM 0 */
321 321
322 { 14336, 0x0000 }, /* R14336 - DSP2 Data3 RAM 1 */ 322 { 14336, 0x0000 }, /* R14336 - DSP2 Data3 RAM 1 */
323 { 14337, 0x0000 }, /* R14337 - DSP2 Data3 RAM 0 */ 323 { 14337, 0x0000 }, /* R14337 - DSP2 Data3 RAM 0 */
324 324
325 { 15360, 0x000A }, /* R15360 - DSP2 Coeff RAM 0 */ 325 { 15360, 0x000A }, /* R15360 - DSP2 Coeff RAM 0 */
326 326
327 { 16384, 0x0000 }, /* R16384 - RETUNEADC_SHARED_COEFF_1 */ 327 { 16384, 0x0000 }, /* R16384 - RETUNEADC_SHARED_COEFF_1 */
328 { 16385, 0x0000 }, /* R16385 - RETUNEADC_SHARED_COEFF_0 */ 328 { 16385, 0x0000 }, /* R16385 - RETUNEADC_SHARED_COEFF_0 */
329 { 16386, 0x0000 }, /* R16386 - RETUNEDAC_SHARED_COEFF_1 */ 329 { 16386, 0x0000 }, /* R16386 - RETUNEDAC_SHARED_COEFF_1 */
330 { 16387, 0x0000 }, /* R16387 - RETUNEDAC_SHARED_COEFF_0 */ 330 { 16387, 0x0000 }, /* R16387 - RETUNEDAC_SHARED_COEFF_0 */
331 { 16388, 0x0000 }, /* R16388 - SOUNDSTAGE_ENABLES_1 */ 331 { 16388, 0x0000 }, /* R16388 - SOUNDSTAGE_ENABLES_1 */
332 { 16389, 0x0000 }, /* R16389 - SOUNDSTAGE_ENABLES_0 */ 332 { 16389, 0x0000 }, /* R16389 - SOUNDSTAGE_ENABLES_0 */
333 333
334 { 16896, 0x0002 }, /* R16896 - HDBASS_AI_1 */ 334 { 16896, 0x0002 }, /* R16896 - HDBASS_AI_1 */
335 { 16897, 0xBD12 }, /* R16897 - HDBASS_AI_0 */ 335 { 16897, 0xBD12 }, /* R16897 - HDBASS_AI_0 */
336 { 16898, 0x007C }, /* R16898 - HDBASS_AR_1 */ 336 { 16898, 0x007C }, /* R16898 - HDBASS_AR_1 */
337 { 16899, 0x586C }, /* R16899 - HDBASS_AR_0 */ 337 { 16899, 0x586C }, /* R16899 - HDBASS_AR_0 */
338 { 16900, 0x0053 }, /* R16900 - HDBASS_B_1 */ 338 { 16900, 0x0053 }, /* R16900 - HDBASS_B_1 */
339 { 16901, 0x8121 }, /* R16901 - HDBASS_B_0 */ 339 { 16901, 0x8121 }, /* R16901 - HDBASS_B_0 */
340 { 16902, 0x003F }, /* R16902 - HDBASS_K_1 */ 340 { 16902, 0x003F }, /* R16902 - HDBASS_K_1 */
341 { 16903, 0x8BD8 }, /* R16903 - HDBASS_K_0 */ 341 { 16903, 0x8BD8 }, /* R16903 - HDBASS_K_0 */
342 { 16904, 0x0032 }, /* R16904 - HDBASS_N1_1 */ 342 { 16904, 0x0032 }, /* R16904 - HDBASS_N1_1 */
343 { 16905, 0xF52D }, /* R16905 - HDBASS_N1_0 */ 343 { 16905, 0xF52D }, /* R16905 - HDBASS_N1_0 */
344 { 16906, 0x0065 }, /* R16906 - HDBASS_N2_1 */ 344 { 16906, 0x0065 }, /* R16906 - HDBASS_N2_1 */
345 { 16907, 0xAC8C }, /* R16907 - HDBASS_N2_0 */ 345 { 16907, 0xAC8C }, /* R16907 - HDBASS_N2_0 */
346 { 16908, 0x006B }, /* R16908 - HDBASS_N3_1 */ 346 { 16908, 0x006B }, /* R16908 - HDBASS_N3_1 */
347 { 16909, 0xE087 }, /* R16909 - HDBASS_N3_0 */ 347 { 16909, 0xE087 }, /* R16909 - HDBASS_N3_0 */
348 { 16910, 0x0072 }, /* R16910 - HDBASS_N4_1 */ 348 { 16910, 0x0072 }, /* R16910 - HDBASS_N4_1 */
349 { 16911, 0x1483 }, /* R16911 - HDBASS_N4_0 */ 349 { 16911, 0x1483 }, /* R16911 - HDBASS_N4_0 */
350 { 16912, 0x0072 }, /* R16912 - HDBASS_N5_1 */ 350 { 16912, 0x0072 }, /* R16912 - HDBASS_N5_1 */
351 { 16913, 0x1483 }, /* R16913 - HDBASS_N5_0 */ 351 { 16913, 0x1483 }, /* R16913 - HDBASS_N5_0 */
352 { 16914, 0x0043 }, /* R16914 - HDBASS_X1_1 */ 352 { 16914, 0x0043 }, /* R16914 - HDBASS_X1_1 */
353 { 16915, 0x3525 }, /* R16915 - HDBASS_X1_0 */ 353 { 16915, 0x3525 }, /* R16915 - HDBASS_X1_0 */
354 { 16916, 0x0006 }, /* R16916 - HDBASS_X2_1 */ 354 { 16916, 0x0006 }, /* R16916 - HDBASS_X2_1 */
355 { 16917, 0x6A4A }, /* R16917 - HDBASS_X2_0 */ 355 { 16917, 0x6A4A }, /* R16917 - HDBASS_X2_0 */
356 { 16918, 0x0043 }, /* R16918 - HDBASS_X3_1 */ 356 { 16918, 0x0043 }, /* R16918 - HDBASS_X3_1 */
357 { 16919, 0x6079 }, /* R16919 - HDBASS_X3_0 */ 357 { 16919, 0x6079 }, /* R16919 - HDBASS_X3_0 */
358 { 16920, 0x0008 }, /* R16920 - HDBASS_ATK_1 */ 358 { 16920, 0x0008 }, /* R16920 - HDBASS_ATK_1 */
359 { 16921, 0x0000 }, /* R16921 - HDBASS_ATK_0 */ 359 { 16921, 0x0000 }, /* R16921 - HDBASS_ATK_0 */
360 { 16922, 0x0001 }, /* R16922 - HDBASS_DCY_1 */ 360 { 16922, 0x0001 }, /* R16922 - HDBASS_DCY_1 */
361 { 16923, 0x0000 }, /* R16923 - HDBASS_DCY_0 */ 361 { 16923, 0x0000 }, /* R16923 - HDBASS_DCY_0 */
362 { 16924, 0x0059 }, /* R16924 - HDBASS_PG_1 */ 362 { 16924, 0x0059 }, /* R16924 - HDBASS_PG_1 */
363 { 16925, 0x999A }, /* R16925 - HDBASS_PG_0 */ 363 { 16925, 0x999A }, /* R16925 - HDBASS_PG_0 */
364 364
365 { 17048, 0x0083 }, /* R17408 - HPF_C_1 */ 365 { 17048, 0x0083 }, /* R17408 - HPF_C_1 */
366 { 17049, 0x98AD }, /* R17409 - HPF_C_0 */ 366 { 17049, 0x98AD }, /* R17409 - HPF_C_0 */
367 367
368 { 17920, 0x007F }, /* R17920 - ADCL_RETUNE_C1_1 */ 368 { 17920, 0x007F }, /* R17920 - ADCL_RETUNE_C1_1 */
369 { 17921, 0xFFFF }, /* R17921 - ADCL_RETUNE_C1_0 */ 369 { 17921, 0xFFFF }, /* R17921 - ADCL_RETUNE_C1_0 */
370 { 17922, 0x0000 }, /* R17922 - ADCL_RETUNE_C2_1 */ 370 { 17922, 0x0000 }, /* R17922 - ADCL_RETUNE_C2_1 */
371 { 17923, 0x0000 }, /* R17923 - ADCL_RETUNE_C2_0 */ 371 { 17923, 0x0000 }, /* R17923 - ADCL_RETUNE_C2_0 */
372 { 17924, 0x0000 }, /* R17924 - ADCL_RETUNE_C3_1 */ 372 { 17924, 0x0000 }, /* R17924 - ADCL_RETUNE_C3_1 */
373 { 17925, 0x0000 }, /* R17925 - ADCL_RETUNE_C3_0 */ 373 { 17925, 0x0000 }, /* R17925 - ADCL_RETUNE_C3_0 */
374 { 17926, 0x0000 }, /* R17926 - ADCL_RETUNE_C4_1 */ 374 { 17926, 0x0000 }, /* R17926 - ADCL_RETUNE_C4_1 */
375 { 17927, 0x0000 }, /* R17927 - ADCL_RETUNE_C4_0 */ 375 { 17927, 0x0000 }, /* R17927 - ADCL_RETUNE_C4_0 */
376 { 17928, 0x0000 }, /* R17928 - ADCL_RETUNE_C5_1 */ 376 { 17928, 0x0000 }, /* R17928 - ADCL_RETUNE_C5_1 */
377 { 17929, 0x0000 }, /* R17929 - ADCL_RETUNE_C5_0 */ 377 { 17929, 0x0000 }, /* R17929 - ADCL_RETUNE_C5_0 */
378 { 17930, 0x0000 }, /* R17930 - ADCL_RETUNE_C6_1 */ 378 { 17930, 0x0000 }, /* R17930 - ADCL_RETUNE_C6_1 */
379 { 17931, 0x0000 }, /* R17931 - ADCL_RETUNE_C6_0 */ 379 { 17931, 0x0000 }, /* R17931 - ADCL_RETUNE_C6_0 */
380 { 17932, 0x0000 }, /* R17932 - ADCL_RETUNE_C7_1 */ 380 { 17932, 0x0000 }, /* R17932 - ADCL_RETUNE_C7_1 */
381 { 17933, 0x0000 }, /* R17933 - ADCL_RETUNE_C7_0 */ 381 { 17933, 0x0000 }, /* R17933 - ADCL_RETUNE_C7_0 */
382 { 17934, 0x0000 }, /* R17934 - ADCL_RETUNE_C8_1 */ 382 { 17934, 0x0000 }, /* R17934 - ADCL_RETUNE_C8_1 */
383 { 17935, 0x0000 }, /* R17935 - ADCL_RETUNE_C8_0 */ 383 { 17935, 0x0000 }, /* R17935 - ADCL_RETUNE_C8_0 */
384 { 17936, 0x0000 }, /* R17936 - ADCL_RETUNE_C9_1 */ 384 { 17936, 0x0000 }, /* R17936 - ADCL_RETUNE_C9_1 */
385 { 17937, 0x0000 }, /* R17937 - ADCL_RETUNE_C9_0 */ 385 { 17937, 0x0000 }, /* R17937 - ADCL_RETUNE_C9_0 */
386 { 17938, 0x0000 }, /* R17938 - ADCL_RETUNE_C10_1 */ 386 { 17938, 0x0000 }, /* R17938 - ADCL_RETUNE_C10_1 */
387 { 17939, 0x0000 }, /* R17939 - ADCL_RETUNE_C10_0 */ 387 { 17939, 0x0000 }, /* R17939 - ADCL_RETUNE_C10_0 */
388 { 17940, 0x0000 }, /* R17940 - ADCL_RETUNE_C11_1 */ 388 { 17940, 0x0000 }, /* R17940 - ADCL_RETUNE_C11_1 */
389 { 17941, 0x0000 }, /* R17941 - ADCL_RETUNE_C11_0 */ 389 { 17941, 0x0000 }, /* R17941 - ADCL_RETUNE_C11_0 */
390 { 17942, 0x0000 }, /* R17942 - ADCL_RETUNE_C12_1 */ 390 { 17942, 0x0000 }, /* R17942 - ADCL_RETUNE_C12_1 */
391 { 17943, 0x0000 }, /* R17943 - ADCL_RETUNE_C12_0 */ 391 { 17943, 0x0000 }, /* R17943 - ADCL_RETUNE_C12_0 */
392 { 17944, 0x0000 }, /* R17944 - ADCL_RETUNE_C13_1 */ 392 { 17944, 0x0000 }, /* R17944 - ADCL_RETUNE_C13_1 */
393 { 17945, 0x0000 }, /* R17945 - ADCL_RETUNE_C13_0 */ 393 { 17945, 0x0000 }, /* R17945 - ADCL_RETUNE_C13_0 */
394 { 17946, 0x0000 }, /* R17946 - ADCL_RETUNE_C14_1 */ 394 { 17946, 0x0000 }, /* R17946 - ADCL_RETUNE_C14_1 */
395 { 17947, 0x0000 }, /* R17947 - ADCL_RETUNE_C14_0 */ 395 { 17947, 0x0000 }, /* R17947 - ADCL_RETUNE_C14_0 */
396 { 17948, 0x0000 }, /* R17948 - ADCL_RETUNE_C15_1 */ 396 { 17948, 0x0000 }, /* R17948 - ADCL_RETUNE_C15_1 */
397 { 17949, 0x0000 }, /* R17949 - ADCL_RETUNE_C15_0 */ 397 { 17949, 0x0000 }, /* R17949 - ADCL_RETUNE_C15_0 */
398 { 17950, 0x0000 }, /* R17950 - ADCL_RETUNE_C16_1 */ 398 { 17950, 0x0000 }, /* R17950 - ADCL_RETUNE_C16_1 */
399 { 17951, 0x0000 }, /* R17951 - ADCL_RETUNE_C16_0 */ 399 { 17951, 0x0000 }, /* R17951 - ADCL_RETUNE_C16_0 */
400 { 17952, 0x0000 }, /* R17952 - ADCL_RETUNE_C17_1 */ 400 { 17952, 0x0000 }, /* R17952 - ADCL_RETUNE_C17_1 */
401 { 17953, 0x0000 }, /* R17953 - ADCL_RETUNE_C17_0 */ 401 { 17953, 0x0000 }, /* R17953 - ADCL_RETUNE_C17_0 */
402 { 17954, 0x0000 }, /* R17954 - ADCL_RETUNE_C18_1 */ 402 { 17954, 0x0000 }, /* R17954 - ADCL_RETUNE_C18_1 */
403 { 17955, 0x0000 }, /* R17955 - ADCL_RETUNE_C18_0 */ 403 { 17955, 0x0000 }, /* R17955 - ADCL_RETUNE_C18_0 */
404 { 17956, 0x0000 }, /* R17956 - ADCL_RETUNE_C19_1 */ 404 { 17956, 0x0000 }, /* R17956 - ADCL_RETUNE_C19_1 */
405 { 17957, 0x0000 }, /* R17957 - ADCL_RETUNE_C19_0 */ 405 { 17957, 0x0000 }, /* R17957 - ADCL_RETUNE_C19_0 */
406 { 17958, 0x0000 }, /* R17958 - ADCL_RETUNE_C20_1 */ 406 { 17958, 0x0000 }, /* R17958 - ADCL_RETUNE_C20_1 */
407 { 17959, 0x0000 }, /* R17959 - ADCL_RETUNE_C20_0 */ 407 { 17959, 0x0000 }, /* R17959 - ADCL_RETUNE_C20_0 */
408 { 17960, 0x0000 }, /* R17960 - ADCL_RETUNE_C21_1 */ 408 { 17960, 0x0000 }, /* R17960 - ADCL_RETUNE_C21_1 */
409 { 17961, 0x0000 }, /* R17961 - ADCL_RETUNE_C21_0 */ 409 { 17961, 0x0000 }, /* R17961 - ADCL_RETUNE_C21_0 */
410 { 17962, 0x0000 }, /* R17962 - ADCL_RETUNE_C22_1 */ 410 { 17962, 0x0000 }, /* R17962 - ADCL_RETUNE_C22_1 */
411 { 17963, 0x0000 }, /* R17963 - ADCL_RETUNE_C22_0 */ 411 { 17963, 0x0000 }, /* R17963 - ADCL_RETUNE_C22_0 */
412 { 17964, 0x0000 }, /* R17964 - ADCL_RETUNE_C23_1 */ 412 { 17964, 0x0000 }, /* R17964 - ADCL_RETUNE_C23_1 */
413 { 17965, 0x0000 }, /* R17965 - ADCL_RETUNE_C23_0 */ 413 { 17965, 0x0000 }, /* R17965 - ADCL_RETUNE_C23_0 */
414 { 17966, 0x0000 }, /* R17966 - ADCL_RETUNE_C24_1 */ 414 { 17966, 0x0000 }, /* R17966 - ADCL_RETUNE_C24_1 */
415 { 17967, 0x0000 }, /* R17967 - ADCL_RETUNE_C24_0 */ 415 { 17967, 0x0000 }, /* R17967 - ADCL_RETUNE_C24_0 */
416 { 17968, 0x0000 }, /* R17968 - ADCL_RETUNE_C25_1 */ 416 { 17968, 0x0000 }, /* R17968 - ADCL_RETUNE_C25_1 */
417 { 17969, 0x0000 }, /* R17969 - ADCL_RETUNE_C25_0 */ 417 { 17969, 0x0000 }, /* R17969 - ADCL_RETUNE_C25_0 */
418 { 17970, 0x0000 }, /* R17970 - ADCL_RETUNE_C26_1 */ 418 { 17970, 0x0000 }, /* R17970 - ADCL_RETUNE_C26_1 */
419 { 17971, 0x0000 }, /* R17971 - ADCL_RETUNE_C26_0 */ 419 { 17971, 0x0000 }, /* R17971 - ADCL_RETUNE_C26_0 */
420 { 17972, 0x0000 }, /* R17972 - ADCL_RETUNE_C27_1 */ 420 { 17972, 0x0000 }, /* R17972 - ADCL_RETUNE_C27_1 */
421 { 17973, 0x0000 }, /* R17973 - ADCL_RETUNE_C27_0 */ 421 { 17973, 0x0000 }, /* R17973 - ADCL_RETUNE_C27_0 */
422 { 17974, 0x0000 }, /* R17974 - ADCL_RETUNE_C28_1 */ 422 { 17974, 0x0000 }, /* R17974 - ADCL_RETUNE_C28_1 */
423 { 17975, 0x0000 }, /* R17975 - ADCL_RETUNE_C28_0 */ 423 { 17975, 0x0000 }, /* R17975 - ADCL_RETUNE_C28_0 */
424 { 17976, 0x0000 }, /* R17976 - ADCL_RETUNE_C29_1 */ 424 { 17976, 0x0000 }, /* R17976 - ADCL_RETUNE_C29_1 */
425 { 17977, 0x0000 }, /* R17977 - ADCL_RETUNE_C29_0 */ 425 { 17977, 0x0000 }, /* R17977 - ADCL_RETUNE_C29_0 */
426 { 17978, 0x0000 }, /* R17978 - ADCL_RETUNE_C30_1 */ 426 { 17978, 0x0000 }, /* R17978 - ADCL_RETUNE_C30_1 */
427 { 17979, 0x0000 }, /* R17979 - ADCL_RETUNE_C30_0 */ 427 { 17979, 0x0000 }, /* R17979 - ADCL_RETUNE_C30_0 */
428 { 17980, 0x0000 }, /* R17980 - ADCL_RETUNE_C31_1 */ 428 { 17980, 0x0000 }, /* R17980 - ADCL_RETUNE_C31_1 */
429 { 17981, 0x0000 }, /* R17981 - ADCL_RETUNE_C31_0 */ 429 { 17981, 0x0000 }, /* R17981 - ADCL_RETUNE_C31_0 */
430 { 17982, 0x0000 }, /* R17982 - ADCL_RETUNE_C32_1 */ 430 { 17982, 0x0000 }, /* R17982 - ADCL_RETUNE_C32_1 */
431 { 17983, 0x0000 }, /* R17983 - ADCL_RETUNE_C32_0 */ 431 { 17983, 0x0000 }, /* R17983 - ADCL_RETUNE_C32_0 */
432 432
433 { 18432, 0x0020 }, /* R18432 - RETUNEADC_PG2_1 */ 433 { 18432, 0x0020 }, /* R18432 - RETUNEADC_PG2_1 */
434 { 18433, 0x0000 }, /* R18433 - RETUNEADC_PG2_0 */ 434 { 18433, 0x0000 }, /* R18433 - RETUNEADC_PG2_0 */
435 { 18434, 0x0040 }, /* R18434 - RETUNEADC_PG_1 */ 435 { 18434, 0x0040 }, /* R18434 - RETUNEADC_PG_1 */
436 { 18435, 0x0000 }, /* R18435 - RETUNEADC_PG_0 */ 436 { 18435, 0x0000 }, /* R18435 - RETUNEADC_PG_0 */
437 437
438 { 18944, 0x007F }, /* R18944 - ADCR_RETUNE_C1_1 */ 438 { 18944, 0x007F }, /* R18944 - ADCR_RETUNE_C1_1 */
439 { 18945, 0xFFFF }, /* R18945 - ADCR_RETUNE_C1_0 */ 439 { 18945, 0xFFFF }, /* R18945 - ADCR_RETUNE_C1_0 */
440 { 18946, 0x0000 }, /* R18946 - ADCR_RETUNE_C2_1 */ 440 { 18946, 0x0000 }, /* R18946 - ADCR_RETUNE_C2_1 */
441 { 18947, 0x0000 }, /* R18947 - ADCR_RETUNE_C2_0 */ 441 { 18947, 0x0000 }, /* R18947 - ADCR_RETUNE_C2_0 */
442 { 18948, 0x0000 }, /* R18948 - ADCR_RETUNE_C3_1 */ 442 { 18948, 0x0000 }, /* R18948 - ADCR_RETUNE_C3_1 */
443 { 18949, 0x0000 }, /* R18949 - ADCR_RETUNE_C3_0 */ 443 { 18949, 0x0000 }, /* R18949 - ADCR_RETUNE_C3_0 */
444 { 18950, 0x0000 }, /* R18950 - ADCR_RETUNE_C4_1 */ 444 { 18950, 0x0000 }, /* R18950 - ADCR_RETUNE_C4_1 */
445 { 18951, 0x0000 }, /* R18951 - ADCR_RETUNE_C4_0 */ 445 { 18951, 0x0000 }, /* R18951 - ADCR_RETUNE_C4_0 */
446 { 18952, 0x0000 }, /* R18952 - ADCR_RETUNE_C5_1 */ 446 { 18952, 0x0000 }, /* R18952 - ADCR_RETUNE_C5_1 */
447 { 18953, 0x0000 }, /* R18953 - ADCR_RETUNE_C5_0 */ 447 { 18953, 0x0000 }, /* R18953 - ADCR_RETUNE_C5_0 */
448 { 18954, 0x0000 }, /* R18954 - ADCR_RETUNE_C6_1 */ 448 { 18954, 0x0000 }, /* R18954 - ADCR_RETUNE_C6_1 */
449 { 18955, 0x0000 }, /* R18955 - ADCR_RETUNE_C6_0 */ 449 { 18955, 0x0000 }, /* R18955 - ADCR_RETUNE_C6_0 */
450 { 18956, 0x0000 }, /* R18956 - ADCR_RETUNE_C7_1 */ 450 { 18956, 0x0000 }, /* R18956 - ADCR_RETUNE_C7_1 */
451 { 18957, 0x0000 }, /* R18957 - ADCR_RETUNE_C7_0 */ 451 { 18957, 0x0000 }, /* R18957 - ADCR_RETUNE_C7_0 */
452 { 18958, 0x0000 }, /* R18958 - ADCR_RETUNE_C8_1 */ 452 { 18958, 0x0000 }, /* R18958 - ADCR_RETUNE_C8_1 */
453 { 18959, 0x0000 }, /* R18959 - ADCR_RETUNE_C8_0 */ 453 { 18959, 0x0000 }, /* R18959 - ADCR_RETUNE_C8_0 */
454 { 18960, 0x0000 }, /* R18960 - ADCR_RETUNE_C9_1 */ 454 { 18960, 0x0000 }, /* R18960 - ADCR_RETUNE_C9_1 */
455 { 18961, 0x0000 }, /* R18961 - ADCR_RETUNE_C9_0 */ 455 { 18961, 0x0000 }, /* R18961 - ADCR_RETUNE_C9_0 */
456 { 18962, 0x0000 }, /* R18962 - ADCR_RETUNE_C10_1 */ 456 { 18962, 0x0000 }, /* R18962 - ADCR_RETUNE_C10_1 */
457 { 18963, 0x0000 }, /* R18963 - ADCR_RETUNE_C10_0 */ 457 { 18963, 0x0000 }, /* R18963 - ADCR_RETUNE_C10_0 */
458 { 18964, 0x0000 }, /* R18964 - ADCR_RETUNE_C11_1 */ 458 { 18964, 0x0000 }, /* R18964 - ADCR_RETUNE_C11_1 */
459 { 18965, 0x0000 }, /* R18965 - ADCR_RETUNE_C11_0 */ 459 { 18965, 0x0000 }, /* R18965 - ADCR_RETUNE_C11_0 */
460 { 18966, 0x0000 }, /* R18966 - ADCR_RETUNE_C12_1 */ 460 { 18966, 0x0000 }, /* R18966 - ADCR_RETUNE_C12_1 */
461 { 18967, 0x0000 }, /* R18967 - ADCR_RETUNE_C12_0 */ 461 { 18967, 0x0000 }, /* R18967 - ADCR_RETUNE_C12_0 */
462 { 18968, 0x0000 }, /* R18968 - ADCR_RETUNE_C13_1 */ 462 { 18968, 0x0000 }, /* R18968 - ADCR_RETUNE_C13_1 */
463 { 18969, 0x0000 }, /* R18969 - ADCR_RETUNE_C13_0 */ 463 { 18969, 0x0000 }, /* R18969 - ADCR_RETUNE_C13_0 */
464 { 18970, 0x0000 }, /* R18970 - ADCR_RETUNE_C14_1 */ 464 { 18970, 0x0000 }, /* R18970 - ADCR_RETUNE_C14_1 */
465 { 18971, 0x0000 }, /* R18971 - ADCR_RETUNE_C14_0 */ 465 { 18971, 0x0000 }, /* R18971 - ADCR_RETUNE_C14_0 */
466 { 18972, 0x0000 }, /* R18972 - ADCR_RETUNE_C15_1 */ 466 { 18972, 0x0000 }, /* R18972 - ADCR_RETUNE_C15_1 */
467 { 18973, 0x0000 }, /* R18973 - ADCR_RETUNE_C15_0 */ 467 { 18973, 0x0000 }, /* R18973 - ADCR_RETUNE_C15_0 */
468 { 18974, 0x0000 }, /* R18974 - ADCR_RETUNE_C16_1 */ 468 { 18974, 0x0000 }, /* R18974 - ADCR_RETUNE_C16_1 */
469 { 18975, 0x0000 }, /* R18975 - ADCR_RETUNE_C16_0 */ 469 { 18975, 0x0000 }, /* R18975 - ADCR_RETUNE_C16_0 */
470 { 18976, 0x0000 }, /* R18976 - ADCR_RETUNE_C17_1 */ 470 { 18976, 0x0000 }, /* R18976 - ADCR_RETUNE_C17_1 */
471 { 18977, 0x0000 }, /* R18977 - ADCR_RETUNE_C17_0 */ 471 { 18977, 0x0000 }, /* R18977 - ADCR_RETUNE_C17_0 */
472 { 18978, 0x0000 }, /* R18978 - ADCR_RETUNE_C18_1 */ 472 { 18978, 0x0000 }, /* R18978 - ADCR_RETUNE_C18_1 */
473 { 18979, 0x0000 }, /* R18979 - ADCR_RETUNE_C18_0 */ 473 { 18979, 0x0000 }, /* R18979 - ADCR_RETUNE_C18_0 */
474 { 18980, 0x0000 }, /* R18980 - ADCR_RETUNE_C19_1 */ 474 { 18980, 0x0000 }, /* R18980 - ADCR_RETUNE_C19_1 */
475 { 18981, 0x0000 }, /* R18981 - ADCR_RETUNE_C19_0 */ 475 { 18981, 0x0000 }, /* R18981 - ADCR_RETUNE_C19_0 */
476 { 18982, 0x0000 }, /* R18982 - ADCR_RETUNE_C20_1 */ 476 { 18982, 0x0000 }, /* R18982 - ADCR_RETUNE_C20_1 */
477 { 18983, 0x0000 }, /* R18983 - ADCR_RETUNE_C20_0 */ 477 { 18983, 0x0000 }, /* R18983 - ADCR_RETUNE_C20_0 */
478 { 18984, 0x0000 }, /* R18984 - ADCR_RETUNE_C21_1 */ 478 { 18984, 0x0000 }, /* R18984 - ADCR_RETUNE_C21_1 */
479 { 18985, 0x0000 }, /* R18985 - ADCR_RETUNE_C21_0 */ 479 { 18985, 0x0000 }, /* R18985 - ADCR_RETUNE_C21_0 */
480 { 18986, 0x0000 }, /* R18986 - ADCR_RETUNE_C22_1 */ 480 { 18986, 0x0000 }, /* R18986 - ADCR_RETUNE_C22_1 */
481 { 18987, 0x0000 }, /* R18987 - ADCR_RETUNE_C22_0 */ 481 { 18987, 0x0000 }, /* R18987 - ADCR_RETUNE_C22_0 */
482 { 18988, 0x0000 }, /* R18988 - ADCR_RETUNE_C23_1 */ 482 { 18988, 0x0000 }, /* R18988 - ADCR_RETUNE_C23_1 */
483 { 18989, 0x0000 }, /* R18989 - ADCR_RETUNE_C23_0 */ 483 { 18989, 0x0000 }, /* R18989 - ADCR_RETUNE_C23_0 */
484 { 18990, 0x0000 }, /* R18990 - ADCR_RETUNE_C24_1 */ 484 { 18990, 0x0000 }, /* R18990 - ADCR_RETUNE_C24_1 */
485 { 18991, 0x0000 }, /* R18991 - ADCR_RETUNE_C24_0 */ 485 { 18991, 0x0000 }, /* R18991 - ADCR_RETUNE_C24_0 */
486 { 18992, 0x0000 }, /* R18992 - ADCR_RETUNE_C25_1 */ 486 { 18992, 0x0000 }, /* R18992 - ADCR_RETUNE_C25_1 */
487 { 18993, 0x0000 }, /* R18993 - ADCR_RETUNE_C25_0 */ 487 { 18993, 0x0000 }, /* R18993 - ADCR_RETUNE_C25_0 */
488 { 18994, 0x0000 }, /* R18994 - ADCR_RETUNE_C26_1 */ 488 { 18994, 0x0000 }, /* R18994 - ADCR_RETUNE_C26_1 */
489 { 18995, 0x0000 }, /* R18995 - ADCR_RETUNE_C26_0 */ 489 { 18995, 0x0000 }, /* R18995 - ADCR_RETUNE_C26_0 */
490 { 18996, 0x0000 }, /* R18996 - ADCR_RETUNE_C27_1 */ 490 { 18996, 0x0000 }, /* R18996 - ADCR_RETUNE_C27_1 */
491 { 18997, 0x0000 }, /* R18997 - ADCR_RETUNE_C27_0 */ 491 { 18997, 0x0000 }, /* R18997 - ADCR_RETUNE_C27_0 */
492 { 18998, 0x0000 }, /* R18998 - ADCR_RETUNE_C28_1 */ 492 { 18998, 0x0000 }, /* R18998 - ADCR_RETUNE_C28_1 */
493 { 18999, 0x0000 }, /* R18999 - ADCR_RETUNE_C28_0 */ 493 { 18999, 0x0000 }, /* R18999 - ADCR_RETUNE_C28_0 */
494 { 19000, 0x0000 }, /* R19000 - ADCR_RETUNE_C29_1 */ 494 { 19000, 0x0000 }, /* R19000 - ADCR_RETUNE_C29_1 */
495 { 19001, 0x0000 }, /* R19001 - ADCR_RETUNE_C29_0 */ 495 { 19001, 0x0000 }, /* R19001 - ADCR_RETUNE_C29_0 */
496 { 19002, 0x0000 }, /* R19002 - ADCR_RETUNE_C30_1 */ 496 { 19002, 0x0000 }, /* R19002 - ADCR_RETUNE_C30_1 */
497 { 19003, 0x0000 }, /* R19003 - ADCR_RETUNE_C30_0 */ 497 { 19003, 0x0000 }, /* R19003 - ADCR_RETUNE_C30_0 */
498 { 19004, 0x0000 }, /* R19004 - ADCR_RETUNE_C31_1 */ 498 { 19004, 0x0000 }, /* R19004 - ADCR_RETUNE_C31_1 */
499 { 19005, 0x0000 }, /* R19005 - ADCR_RETUNE_C31_0 */ 499 { 19005, 0x0000 }, /* R19005 - ADCR_RETUNE_C31_0 */
500 { 19006, 0x0000 }, /* R19006 - ADCR_RETUNE_C32_1 */ 500 { 19006, 0x0000 }, /* R19006 - ADCR_RETUNE_C32_1 */
501 { 19007, 0x0000 }, /* R19007 - ADCR_RETUNE_C32_0 */ 501 { 19007, 0x0000 }, /* R19007 - ADCR_RETUNE_C32_0 */
502 502
503 { 19456, 0x007F }, /* R19456 - DACL_RETUNE_C1_1 */ 503 { 19456, 0x007F }, /* R19456 - DACL_RETUNE_C1_1 */
504 { 19457, 0xFFFF }, /* R19457 - DACL_RETUNE_C1_0 */ 504 { 19457, 0xFFFF }, /* R19457 - DACL_RETUNE_C1_0 */
505 { 19458, 0x0000 }, /* R19458 - DACL_RETUNE_C2_1 */ 505 { 19458, 0x0000 }, /* R19458 - DACL_RETUNE_C2_1 */
506 { 19459, 0x0000 }, /* R19459 - DACL_RETUNE_C2_0 */ 506 { 19459, 0x0000 }, /* R19459 - DACL_RETUNE_C2_0 */
507 { 19460, 0x0000 }, /* R19460 - DACL_RETUNE_C3_1 */ 507 { 19460, 0x0000 }, /* R19460 - DACL_RETUNE_C3_1 */
508 { 19461, 0x0000 }, /* R19461 - DACL_RETUNE_C3_0 */ 508 { 19461, 0x0000 }, /* R19461 - DACL_RETUNE_C3_0 */
509 { 19462, 0x0000 }, /* R19462 - DACL_RETUNE_C4_1 */ 509 { 19462, 0x0000 }, /* R19462 - DACL_RETUNE_C4_1 */
510 { 19463, 0x0000 }, /* R19463 - DACL_RETUNE_C4_0 */ 510 { 19463, 0x0000 }, /* R19463 - DACL_RETUNE_C4_0 */
511 { 19464, 0x0000 }, /* R19464 - DACL_RETUNE_C5_1 */ 511 { 19464, 0x0000 }, /* R19464 - DACL_RETUNE_C5_1 */
512 { 19465, 0x0000 }, /* R19465 - DACL_RETUNE_C5_0 */ 512 { 19465, 0x0000 }, /* R19465 - DACL_RETUNE_C5_0 */
513 { 19466, 0x0000 }, /* R19466 - DACL_RETUNE_C6_1 */ 513 { 19466, 0x0000 }, /* R19466 - DACL_RETUNE_C6_1 */
514 { 19467, 0x0000 }, /* R19467 - DACL_RETUNE_C6_0 */ 514 { 19467, 0x0000 }, /* R19467 - DACL_RETUNE_C6_0 */
515 { 19468, 0x0000 }, /* R19468 - DACL_RETUNE_C7_1 */ 515 { 19468, 0x0000 }, /* R19468 - DACL_RETUNE_C7_1 */
516 { 19469, 0x0000 }, /* R19469 - DACL_RETUNE_C7_0 */ 516 { 19469, 0x0000 }, /* R19469 - DACL_RETUNE_C7_0 */
517 { 19470, 0x0000 }, /* R19470 - DACL_RETUNE_C8_1 */ 517 { 19470, 0x0000 }, /* R19470 - DACL_RETUNE_C8_1 */
518 { 19471, 0x0000 }, /* R19471 - DACL_RETUNE_C8_0 */ 518 { 19471, 0x0000 }, /* R19471 - DACL_RETUNE_C8_0 */
519 { 19472, 0x0000 }, /* R19472 - DACL_RETUNE_C9_1 */ 519 { 19472, 0x0000 }, /* R19472 - DACL_RETUNE_C9_1 */
520 { 19473, 0x0000 }, /* R19473 - DACL_RETUNE_C9_0 */ 520 { 19473, 0x0000 }, /* R19473 - DACL_RETUNE_C9_0 */
521 { 19474, 0x0000 }, /* R19474 - DACL_RETUNE_C10_1 */ 521 { 19474, 0x0000 }, /* R19474 - DACL_RETUNE_C10_1 */
522 { 19475, 0x0000 }, /* R19475 - DACL_RETUNE_C10_0 */ 522 { 19475, 0x0000 }, /* R19475 - DACL_RETUNE_C10_0 */
523 { 19476, 0x0000 }, /* R19476 - DACL_RETUNE_C11_1 */ 523 { 19476, 0x0000 }, /* R19476 - DACL_RETUNE_C11_1 */
524 { 19477, 0x0000 }, /* R19477 - DACL_RETUNE_C11_0 */ 524 { 19477, 0x0000 }, /* R19477 - DACL_RETUNE_C11_0 */
525 { 19478, 0x0000 }, /* R19478 - DACL_RETUNE_C12_1 */ 525 { 19478, 0x0000 }, /* R19478 - DACL_RETUNE_C12_1 */
526 { 19479, 0x0000 }, /* R19479 - DACL_RETUNE_C12_0 */ 526 { 19479, 0x0000 }, /* R19479 - DACL_RETUNE_C12_0 */
527 { 19480, 0x0000 }, /* R19480 - DACL_RETUNE_C13_1 */ 527 { 19480, 0x0000 }, /* R19480 - DACL_RETUNE_C13_1 */
528 { 19481, 0x0000 }, /* R19481 - DACL_RETUNE_C13_0 */ 528 { 19481, 0x0000 }, /* R19481 - DACL_RETUNE_C13_0 */
529 { 19482, 0x0000 }, /* R19482 - DACL_RETUNE_C14_1 */ 529 { 19482, 0x0000 }, /* R19482 - DACL_RETUNE_C14_1 */
530 { 19483, 0x0000 }, /* R19483 - DACL_RETUNE_C14_0 */ 530 { 19483, 0x0000 }, /* R19483 - DACL_RETUNE_C14_0 */
531 { 19484, 0x0000 }, /* R19484 - DACL_RETUNE_C15_1 */ 531 { 19484, 0x0000 }, /* R19484 - DACL_RETUNE_C15_1 */
532 { 19485, 0x0000 }, /* R19485 - DACL_RETUNE_C15_0 */ 532 { 19485, 0x0000 }, /* R19485 - DACL_RETUNE_C15_0 */
533 { 19486, 0x0000 }, /* R19486 - DACL_RETUNE_C16_1 */ 533 { 19486, 0x0000 }, /* R19486 - DACL_RETUNE_C16_1 */
534 { 19487, 0x0000 }, /* R19487 - DACL_RETUNE_C16_0 */ 534 { 19487, 0x0000 }, /* R19487 - DACL_RETUNE_C16_0 */
535 { 19488, 0x0000 }, /* R19488 - DACL_RETUNE_C17_1 */ 535 { 19488, 0x0000 }, /* R19488 - DACL_RETUNE_C17_1 */
536 { 19489, 0x0000 }, /* R19489 - DACL_RETUNE_C17_0 */ 536 { 19489, 0x0000 }, /* R19489 - DACL_RETUNE_C17_0 */
537 { 19490, 0x0000 }, /* R19490 - DACL_RETUNE_C18_1 */ 537 { 19490, 0x0000 }, /* R19490 - DACL_RETUNE_C18_1 */
538 { 19491, 0x0000 }, /* R19491 - DACL_RETUNE_C18_0 */ 538 { 19491, 0x0000 }, /* R19491 - DACL_RETUNE_C18_0 */
539 { 19492, 0x0000 }, /* R19492 - DACL_RETUNE_C19_1 */ 539 { 19492, 0x0000 }, /* R19492 - DACL_RETUNE_C19_1 */
540 { 19493, 0x0000 }, /* R19493 - DACL_RETUNE_C19_0 */ 540 { 19493, 0x0000 }, /* R19493 - DACL_RETUNE_C19_0 */
541 { 19494, 0x0000 }, /* R19494 - DACL_RETUNE_C20_1 */ 541 { 19494, 0x0000 }, /* R19494 - DACL_RETUNE_C20_1 */
542 { 19495, 0x0000 }, /* R19495 - DACL_RETUNE_C20_0 */ 542 { 19495, 0x0000 }, /* R19495 - DACL_RETUNE_C20_0 */
543 { 19496, 0x0000 }, /* R19496 - DACL_RETUNE_C21_1 */ 543 { 19496, 0x0000 }, /* R19496 - DACL_RETUNE_C21_1 */
544 { 19497, 0x0000 }, /* R19497 - DACL_RETUNE_C21_0 */ 544 { 19497, 0x0000 }, /* R19497 - DACL_RETUNE_C21_0 */
545 { 19498, 0x0000 }, /* R19498 - DACL_RETUNE_C22_1 */ 545 { 19498, 0x0000 }, /* R19498 - DACL_RETUNE_C22_1 */
546 { 19499, 0x0000 }, /* R19499 - DACL_RETUNE_C22_0 */ 546 { 19499, 0x0000 }, /* R19499 - DACL_RETUNE_C22_0 */
547 { 19500, 0x0000 }, /* R19500 - DACL_RETUNE_C23_1 */ 547 { 19500, 0x0000 }, /* R19500 - DACL_RETUNE_C23_1 */
548 { 19501, 0x0000 }, /* R19501 - DACL_RETUNE_C23_0 */ 548 { 19501, 0x0000 }, /* R19501 - DACL_RETUNE_C23_0 */
549 { 19502, 0x0000 }, /* R19502 - DACL_RETUNE_C24_1 */ 549 { 19502, 0x0000 }, /* R19502 - DACL_RETUNE_C24_1 */
550 { 19503, 0x0000 }, /* R19503 - DACL_RETUNE_C24_0 */ 550 { 19503, 0x0000 }, /* R19503 - DACL_RETUNE_C24_0 */
551 { 19504, 0x0000 }, /* R19504 - DACL_RETUNE_C25_1 */ 551 { 19504, 0x0000 }, /* R19504 - DACL_RETUNE_C25_1 */
552 { 19505, 0x0000 }, /* R19505 - DACL_RETUNE_C25_0 */ 552 { 19505, 0x0000 }, /* R19505 - DACL_RETUNE_C25_0 */
553 { 19506, 0x0000 }, /* R19506 - DACL_RETUNE_C26_1 */ 553 { 19506, 0x0000 }, /* R19506 - DACL_RETUNE_C26_1 */
554 { 19507, 0x0000 }, /* R19507 - DACL_RETUNE_C26_0 */ 554 { 19507, 0x0000 }, /* R19507 - DACL_RETUNE_C26_0 */
555 { 19508, 0x0000 }, /* R19508 - DACL_RETUNE_C27_1 */ 555 { 19508, 0x0000 }, /* R19508 - DACL_RETUNE_C27_1 */
556 { 19509, 0x0000 }, /* R19509 - DACL_RETUNE_C27_0 */ 556 { 19509, 0x0000 }, /* R19509 - DACL_RETUNE_C27_0 */
557 { 19510, 0x0000 }, /* R19510 - DACL_RETUNE_C28_1 */ 557 { 19510, 0x0000 }, /* R19510 - DACL_RETUNE_C28_1 */
558 { 19511, 0x0000 }, /* R19511 - DACL_RETUNE_C28_0 */ 558 { 19511, 0x0000 }, /* R19511 - DACL_RETUNE_C28_0 */
559 { 19512, 0x0000 }, /* R19512 - DACL_RETUNE_C29_1 */ 559 { 19512, 0x0000 }, /* R19512 - DACL_RETUNE_C29_1 */
560 { 19513, 0x0000 }, /* R19513 - DACL_RETUNE_C29_0 */ 560 { 19513, 0x0000 }, /* R19513 - DACL_RETUNE_C29_0 */
561 { 19514, 0x0000 }, /* R19514 - DACL_RETUNE_C30_1 */ 561 { 19514, 0x0000 }, /* R19514 - DACL_RETUNE_C30_1 */
562 { 19515, 0x0000 }, /* R19515 - DACL_RETUNE_C30_0 */ 562 { 19515, 0x0000 }, /* R19515 - DACL_RETUNE_C30_0 */
563 { 19516, 0x0000 }, /* R19516 - DACL_RETUNE_C31_1 */ 563 { 19516, 0x0000 }, /* R19516 - DACL_RETUNE_C31_1 */
564 { 19517, 0x0000 }, /* R19517 - DACL_RETUNE_C31_0 */ 564 { 19517, 0x0000 }, /* R19517 - DACL_RETUNE_C31_0 */
565 { 19518, 0x0000 }, /* R19518 - DACL_RETUNE_C32_1 */ 565 { 19518, 0x0000 }, /* R19518 - DACL_RETUNE_C32_1 */
566 { 19519, 0x0000 }, /* R19519 - DACL_RETUNE_C32_0 */ 566 { 19519, 0x0000 }, /* R19519 - DACL_RETUNE_C32_0 */
567 567
568 { 19968, 0x0020 }, /* R19968 - RETUNEDAC_PG2_1 */ 568 { 19968, 0x0020 }, /* R19968 - RETUNEDAC_PG2_1 */
569 { 19969, 0x0000 }, /* R19969 - RETUNEDAC_PG2_0 */ 569 { 19969, 0x0000 }, /* R19969 - RETUNEDAC_PG2_0 */
570 { 19970, 0x0040 }, /* R19970 - RETUNEDAC_PG_1 */ 570 { 19970, 0x0040 }, /* R19970 - RETUNEDAC_PG_1 */
571 { 19971, 0x0000 }, /* R19971 - RETUNEDAC_PG_0 */ 571 { 19971, 0x0000 }, /* R19971 - RETUNEDAC_PG_0 */
572 572
573 { 20480, 0x007F }, /* R20480 - DACR_RETUNE_C1_1 */ 573 { 20480, 0x007F }, /* R20480 - DACR_RETUNE_C1_1 */
574 { 20481, 0xFFFF }, /* R20481 - DACR_RETUNE_C1_0 */ 574 { 20481, 0xFFFF }, /* R20481 - DACR_RETUNE_C1_0 */
575 { 20482, 0x0000 }, /* R20482 - DACR_RETUNE_C2_1 */ 575 { 20482, 0x0000 }, /* R20482 - DACR_RETUNE_C2_1 */
576 { 20483, 0x0000 }, /* R20483 - DACR_RETUNE_C2_0 */ 576 { 20483, 0x0000 }, /* R20483 - DACR_RETUNE_C2_0 */
577 { 20484, 0x0000 }, /* R20484 - DACR_RETUNE_C3_1 */ 577 { 20484, 0x0000 }, /* R20484 - DACR_RETUNE_C3_1 */
578 { 20485, 0x0000 }, /* R20485 - DACR_RETUNE_C3_0 */ 578 { 20485, 0x0000 }, /* R20485 - DACR_RETUNE_C3_0 */
579 { 20486, 0x0000 }, /* R20486 - DACR_RETUNE_C4_1 */ 579 { 20486, 0x0000 }, /* R20486 - DACR_RETUNE_C4_1 */
580 { 20487, 0x0000 }, /* R20487 - DACR_RETUNE_C4_0 */ 580 { 20487, 0x0000 }, /* R20487 - DACR_RETUNE_C4_0 */
581 { 20488, 0x0000 }, /* R20488 - DACR_RETUNE_C5_1 */ 581 { 20488, 0x0000 }, /* R20488 - DACR_RETUNE_C5_1 */
582 { 20489, 0x0000 }, /* R20489 - DACR_RETUNE_C5_0 */ 582 { 20489, 0x0000 }, /* R20489 - DACR_RETUNE_C5_0 */
583 { 20490, 0x0000 }, /* R20490 - DACR_RETUNE_C6_1 */ 583 { 20490, 0x0000 }, /* R20490 - DACR_RETUNE_C6_1 */
584 { 20491, 0x0000 }, /* R20491 - DACR_RETUNE_C6_0 */ 584 { 20491, 0x0000 }, /* R20491 - DACR_RETUNE_C6_0 */
585 { 20492, 0x0000 }, /* R20492 - DACR_RETUNE_C7_1 */ 585 { 20492, 0x0000 }, /* R20492 - DACR_RETUNE_C7_1 */
586 { 20493, 0x0000 }, /* R20493 - DACR_RETUNE_C7_0 */ 586 { 20493, 0x0000 }, /* R20493 - DACR_RETUNE_C7_0 */
587 { 20494, 0x0000 }, /* R20494 - DACR_RETUNE_C8_1 */ 587 { 20494, 0x0000 }, /* R20494 - DACR_RETUNE_C8_1 */
588 { 20495, 0x0000 }, /* R20495 - DACR_RETUNE_C8_0 */ 588 { 20495, 0x0000 }, /* R20495 - DACR_RETUNE_C8_0 */
589 { 20496, 0x0000 }, /* R20496 - DACR_RETUNE_C9_1 */ 589 { 20496, 0x0000 }, /* R20496 - DACR_RETUNE_C9_1 */
590 { 20497, 0x0000 }, /* R20497 - DACR_RETUNE_C9_0 */ 590 { 20497, 0x0000 }, /* R20497 - DACR_RETUNE_C9_0 */
591 { 20498, 0x0000 }, /* R20498 - DACR_RETUNE_C10_1 */ 591 { 20498, 0x0000 }, /* R20498 - DACR_RETUNE_C10_1 */
592 { 20499, 0x0000 }, /* R20499 - DACR_RETUNE_C10_0 */ 592 { 20499, 0x0000 }, /* R20499 - DACR_RETUNE_C10_0 */
593 { 20500, 0x0000 }, /* R20500 - DACR_RETUNE_C11_1 */ 593 { 20500, 0x0000 }, /* R20500 - DACR_RETUNE_C11_1 */
594 { 20501, 0x0000 }, /* R20501 - DACR_RETUNE_C11_0 */ 594 { 20501, 0x0000 }, /* R20501 - DACR_RETUNE_C11_0 */
595 { 20502, 0x0000 }, /* R20502 - DACR_RETUNE_C12_1 */ 595 { 20502, 0x0000 }, /* R20502 - DACR_RETUNE_C12_1 */
596 { 20503, 0x0000 }, /* R20503 - DACR_RETUNE_C12_0 */ 596 { 20503, 0x0000 }, /* R20503 - DACR_RETUNE_C12_0 */
597 { 20504, 0x0000 }, /* R20504 - DACR_RETUNE_C13_1 */ 597 { 20504, 0x0000 }, /* R20504 - DACR_RETUNE_C13_1 */
598 { 20505, 0x0000 }, /* R20505 - DACR_RETUNE_C13_0 */ 598 { 20505, 0x0000 }, /* R20505 - DACR_RETUNE_C13_0 */
599 { 20506, 0x0000 }, /* R20506 - DACR_RETUNE_C14_1 */ 599 { 20506, 0x0000 }, /* R20506 - DACR_RETUNE_C14_1 */
600 { 20507, 0x0000 }, /* R20507 - DACR_RETUNE_C14_0 */ 600 { 20507, 0x0000 }, /* R20507 - DACR_RETUNE_C14_0 */
601 { 20508, 0x0000 }, /* R20508 - DACR_RETUNE_C15_1 */ 601 { 20508, 0x0000 }, /* R20508 - DACR_RETUNE_C15_1 */
602 { 20509, 0x0000 }, /* R20509 - DACR_RETUNE_C15_0 */ 602 { 20509, 0x0000 }, /* R20509 - DACR_RETUNE_C15_0 */
603 { 20510, 0x0000 }, /* R20510 - DACR_RETUNE_C16_1 */ 603 { 20510, 0x0000 }, /* R20510 - DACR_RETUNE_C16_1 */
604 { 20511, 0x0000 }, /* R20511 - DACR_RETUNE_C16_0 */ 604 { 20511, 0x0000 }, /* R20511 - DACR_RETUNE_C16_0 */
605 { 20512, 0x0000 }, /* R20512 - DACR_RETUNE_C17_1 */ 605 { 20512, 0x0000 }, /* R20512 - DACR_RETUNE_C17_1 */
606 { 20513, 0x0000 }, /* R20513 - DACR_RETUNE_C17_0 */ 606 { 20513, 0x0000 }, /* R20513 - DACR_RETUNE_C17_0 */
607 { 20514, 0x0000 }, /* R20514 - DACR_RETUNE_C18_1 */ 607 { 20514, 0x0000 }, /* R20514 - DACR_RETUNE_C18_1 */
608 { 20515, 0x0000 }, /* R20515 - DACR_RETUNE_C18_0 */ 608 { 20515, 0x0000 }, /* R20515 - DACR_RETUNE_C18_0 */
609 { 20516, 0x0000 }, /* R20516 - DACR_RETUNE_C19_1 */ 609 { 20516, 0x0000 }, /* R20516 - DACR_RETUNE_C19_1 */
610 { 20517, 0x0000 }, /* R20517 - DACR_RETUNE_C19_0 */ 610 { 20517, 0x0000 }, /* R20517 - DACR_RETUNE_C19_0 */
611 { 20518, 0x0000 }, /* R20518 - DACR_RETUNE_C20_1 */ 611 { 20518, 0x0000 }, /* R20518 - DACR_RETUNE_C20_1 */
612 { 20519, 0x0000 }, /* R20519 - DACR_RETUNE_C20_0 */ 612 { 20519, 0x0000 }, /* R20519 - DACR_RETUNE_C20_0 */
613 { 20520, 0x0000 }, /* R20520 - DACR_RETUNE_C21_1 */ 613 { 20520, 0x0000 }, /* R20520 - DACR_RETUNE_C21_1 */
614 { 20521, 0x0000 }, /* R20521 - DACR_RETUNE_C21_0 */ 614 { 20521, 0x0000 }, /* R20521 - DACR_RETUNE_C21_0 */
615 { 20522, 0x0000 }, /* R20522 - DACR_RETUNE_C22_1 */ 615 { 20522, 0x0000 }, /* R20522 - DACR_RETUNE_C22_1 */
616 { 20523, 0x0000 }, /* R20523 - DACR_RETUNE_C22_0 */ 616 { 20523, 0x0000 }, /* R20523 - DACR_RETUNE_C22_0 */
617 { 20524, 0x0000 }, /* R20524 - DACR_RETUNE_C23_1 */ 617 { 20524, 0x0000 }, /* R20524 - DACR_RETUNE_C23_1 */
618 { 20525, 0x0000 }, /* R20525 - DACR_RETUNE_C23_0 */ 618 { 20525, 0x0000 }, /* R20525 - DACR_RETUNE_C23_0 */
619 { 20526, 0x0000 }, /* R20526 - DACR_RETUNE_C24_1 */ 619 { 20526, 0x0000 }, /* R20526 - DACR_RETUNE_C24_1 */
620 { 20527, 0x0000 }, /* R20527 - DACR_RETUNE_C24_0 */ 620 { 20527, 0x0000 }, /* R20527 - DACR_RETUNE_C24_0 */
621 { 20528, 0x0000 }, /* R20528 - DACR_RETUNE_C25_1 */ 621 { 20528, 0x0000 }, /* R20528 - DACR_RETUNE_C25_1 */
622 { 20529, 0x0000 }, /* R20529 - DACR_RETUNE_C25_0 */ 622 { 20529, 0x0000 }, /* R20529 - DACR_RETUNE_C25_0 */
623 { 20530, 0x0000 }, /* R20530 - DACR_RETUNE_C26_1 */ 623 { 20530, 0x0000 }, /* R20530 - DACR_RETUNE_C26_1 */
624 { 20531, 0x0000 }, /* R20531 - DACR_RETUNE_C26_0 */ 624 { 20531, 0x0000 }, /* R20531 - DACR_RETUNE_C26_0 */
625 { 20532, 0x0000 }, /* R20532 - DACR_RETUNE_C27_1 */ 625 { 20532, 0x0000 }, /* R20532 - DACR_RETUNE_C27_1 */
626 { 20533, 0x0000 }, /* R20533 - DACR_RETUNE_C27_0 */ 626 { 20533, 0x0000 }, /* R20533 - DACR_RETUNE_C27_0 */
627 { 20534, 0x0000 }, /* R20534 - DACR_RETUNE_C28_1 */ 627 { 20534, 0x0000 }, /* R20534 - DACR_RETUNE_C28_1 */
628 { 20535, 0x0000 }, /* R20535 - DACR_RETUNE_C28_0 */ 628 { 20535, 0x0000 }, /* R20535 - DACR_RETUNE_C28_0 */
629 { 20536, 0x0000 }, /* R20536 - DACR_RETUNE_C29_1 */ 629 { 20536, 0x0000 }, /* R20536 - DACR_RETUNE_C29_1 */
630 { 20537, 0x0000 }, /* R20537 - DACR_RETUNE_C29_0 */ 630 { 20537, 0x0000 }, /* R20537 - DACR_RETUNE_C29_0 */
631 { 20538, 0x0000 }, /* R20538 - DACR_RETUNE_C30_1 */ 631 { 20538, 0x0000 }, /* R20538 - DACR_RETUNE_C30_1 */
632 { 20539, 0x0000 }, /* R20539 - DACR_RETUNE_C30_0 */ 632 { 20539, 0x0000 }, /* R20539 - DACR_RETUNE_C30_0 */
633 { 20540, 0x0000 }, /* R20540 - DACR_RETUNE_C31_1 */ 633 { 20540, 0x0000 }, /* R20540 - DACR_RETUNE_C31_1 */
634 { 20541, 0x0000 }, /* R20541 - DACR_RETUNE_C31_0 */ 634 { 20541, 0x0000 }, /* R20541 - DACR_RETUNE_C31_0 */
635 { 20542, 0x0000 }, /* R20542 - DACR_RETUNE_C32_1 */ 635 { 20542, 0x0000 }, /* R20542 - DACR_RETUNE_C32_1 */
636 { 20543, 0x0000 }, /* R20543 - DACR_RETUNE_C32_0 */ 636 { 20543, 0x0000 }, /* R20543 - DACR_RETUNE_C32_0 */
637 637
638 { 20992, 0x008C }, /* R20992 - VSS_XHD2_1 */ 638 { 20992, 0x008C }, /* R20992 - VSS_XHD2_1 */
639 { 20993, 0x0200 }, /* R20993 - VSS_XHD2_0 */ 639 { 20993, 0x0200 }, /* R20993 - VSS_XHD2_0 */
640 { 20994, 0x0035 }, /* R20994 - VSS_XHD3_1 */ 640 { 20994, 0x0035 }, /* R20994 - VSS_XHD3_1 */
641 { 20995, 0x0700 }, /* R20995 - VSS_XHD3_0 */ 641 { 20995, 0x0700 }, /* R20995 - VSS_XHD3_0 */
642 { 20996, 0x003A }, /* R20996 - VSS_XHN1_1 */ 642 { 20996, 0x003A }, /* R20996 - VSS_XHN1_1 */
643 { 20997, 0x4100 }, /* R20997 - VSS_XHN1_0 */ 643 { 20997, 0x4100 }, /* R20997 - VSS_XHN1_0 */
644 { 20998, 0x008B }, /* R20998 - VSS_XHN2_1 */ 644 { 20998, 0x008B }, /* R20998 - VSS_XHN2_1 */
645 { 20999, 0x7D00 }, /* R20999 - VSS_XHN2_0 */ 645 { 20999, 0x7D00 }, /* R20999 - VSS_XHN2_0 */
646 { 21000, 0x003A }, /* R21000 - VSS_XHN3_1 */ 646 { 21000, 0x003A }, /* R21000 - VSS_XHN3_1 */
647 { 21001, 0x4100 }, /* R21001 - VSS_XHN3_0 */ 647 { 21001, 0x4100 }, /* R21001 - VSS_XHN3_0 */
648 { 21002, 0x008C }, /* R21002 - VSS_XLA_1 */ 648 { 21002, 0x008C }, /* R21002 - VSS_XLA_1 */
649 { 21003, 0xFEE8 }, /* R21003 - VSS_XLA_0 */ 649 { 21003, 0xFEE8 }, /* R21003 - VSS_XLA_0 */
650 { 21004, 0x0078 }, /* R21004 - VSS_XLB_1 */ 650 { 21004, 0x0078 }, /* R21004 - VSS_XLB_1 */
651 { 21005, 0x0000 }, /* R21005 - VSS_XLB_0 */ 651 { 21005, 0x0000 }, /* R21005 - VSS_XLB_0 */
652 { 21006, 0x003F }, /* R21006 - VSS_XLG_1 */ 652 { 21006, 0x003F }, /* R21006 - VSS_XLG_1 */
653 { 21007, 0xB260 }, /* R21007 - VSS_XLG_0 */ 653 { 21007, 0xB260 }, /* R21007 - VSS_XLG_0 */
654 { 21008, 0x002D }, /* R21008 - VSS_PG2_1 */ 654 { 21008, 0x002D }, /* R21008 - VSS_PG2_1 */
655 { 21009, 0x1818 }, /* R21009 - VSS_PG2_0 */ 655 { 21009, 0x1818 }, /* R21009 - VSS_PG2_0 */
656 { 21010, 0x0020 }, /* R21010 - VSS_PG_1 */ 656 { 21010, 0x0020 }, /* R21010 - VSS_PG_1 */
657 { 21011, 0x0000 }, /* R21011 - VSS_PG_0 */ 657 { 21011, 0x0000 }, /* R21011 - VSS_PG_0 */
658 { 21012, 0x00F1 }, /* R21012 - VSS_XTD1_1 */ 658 { 21012, 0x00F1 }, /* R21012 - VSS_XTD1_1 */
659 { 21013, 0x8340 }, /* R21013 - VSS_XTD1_0 */ 659 { 21013, 0x8340 }, /* R21013 - VSS_XTD1_0 */
660 { 21014, 0x00FB }, /* R21014 - VSS_XTD2_1 */ 660 { 21014, 0x00FB }, /* R21014 - VSS_XTD2_1 */
661 { 21015, 0x8300 }, /* R21015 - VSS_XTD2_0 */ 661 { 21015, 0x8300 }, /* R21015 - VSS_XTD2_0 */
662 { 21016, 0x00EE }, /* R21016 - VSS_XTD3_1 */ 662 { 21016, 0x00EE }, /* R21016 - VSS_XTD3_1 */
663 { 21017, 0xAEC0 }, /* R21017 - VSS_XTD3_0 */ 663 { 21017, 0xAEC0 }, /* R21017 - VSS_XTD3_0 */
664 { 21018, 0x00FB }, /* R21018 - VSS_XTD4_1 */ 664 { 21018, 0x00FB }, /* R21018 - VSS_XTD4_1 */
665 { 21019, 0xAC40 }, /* R21019 - VSS_XTD4_0 */ 665 { 21019, 0xAC40 }, /* R21019 - VSS_XTD4_0 */
666 { 21020, 0x00F1 }, /* R21020 - VSS_XTD5_1 */ 666 { 21020, 0x00F1 }, /* R21020 - VSS_XTD5_1 */
667 { 21021, 0x7F80 }, /* R21021 - VSS_XTD5_0 */ 667 { 21021, 0x7F80 }, /* R21021 - VSS_XTD5_0 */
668 { 21022, 0x00F4 }, /* R21022 - VSS_XTD6_1 */ 668 { 21022, 0x00F4 }, /* R21022 - VSS_XTD6_1 */
669 { 21023, 0x3B40 }, /* R21023 - VSS_XTD6_0 */ 669 { 21023, 0x3B40 }, /* R21023 - VSS_XTD6_0 */
670 { 21024, 0x00F5 }, /* R21024 - VSS_XTD7_1 */ 670 { 21024, 0x00F5 }, /* R21024 - VSS_XTD7_1 */
671 { 21025, 0xFB00 }, /* R21025 - VSS_XTD7_0 */ 671 { 21025, 0xFB00 }, /* R21025 - VSS_XTD7_0 */
672 { 21026, 0x00EA }, /* R21026 - VSS_XTD8_1 */ 672 { 21026, 0x00EA }, /* R21026 - VSS_XTD8_1 */
673 { 21027, 0x10C0 }, /* R21027 - VSS_XTD8_0 */ 673 { 21027, 0x10C0 }, /* R21027 - VSS_XTD8_0 */
674 { 21028, 0x00FC }, /* R21028 - VSS_XTD9_1 */ 674 { 21028, 0x00FC }, /* R21028 - VSS_XTD9_1 */
675 { 21029, 0xC580 }, /* R21029 - VSS_XTD9_0 */ 675 { 21029, 0xC580 }, /* R21029 - VSS_XTD9_0 */
676 { 21030, 0x00E2 }, /* R21030 - VSS_XTD10_1 */ 676 { 21030, 0x00E2 }, /* R21030 - VSS_XTD10_1 */
677 { 21031, 0x75C0 }, /* R21031 - VSS_XTD10_0 */ 677 { 21031, 0x75C0 }, /* R21031 - VSS_XTD10_0 */
678 { 21032, 0x0004 }, /* R21032 - VSS_XTD11_1 */ 678 { 21032, 0x0004 }, /* R21032 - VSS_XTD11_1 */
679 { 21033, 0xB480 }, /* R21033 - VSS_XTD11_0 */ 679 { 21033, 0xB480 }, /* R21033 - VSS_XTD11_0 */
680 { 21034, 0x00D4 }, /* R21034 - VSS_XTD12_1 */ 680 { 21034, 0x00D4 }, /* R21034 - VSS_XTD12_1 */
681 { 21035, 0xF980 }, /* R21035 - VSS_XTD12_0 */ 681 { 21035, 0xF980 }, /* R21035 - VSS_XTD12_0 */
682 { 21036, 0x0004 }, /* R21036 - VSS_XTD13_1 */ 682 { 21036, 0x0004 }, /* R21036 - VSS_XTD13_1 */
683 { 21037, 0x9140 }, /* R21037 - VSS_XTD13_0 */ 683 { 21037, 0x9140 }, /* R21037 - VSS_XTD13_0 */
684 { 21038, 0x00D8 }, /* R21038 - VSS_XTD14_1 */ 684 { 21038, 0x00D8 }, /* R21038 - VSS_XTD14_1 */
685 { 21039, 0xA480 }, /* R21039 - VSS_XTD14_0 */ 685 { 21039, 0xA480 }, /* R21039 - VSS_XTD14_0 */
686 { 21040, 0x0002 }, /* R21040 - VSS_XTD15_1 */ 686 { 21040, 0x0002 }, /* R21040 - VSS_XTD15_1 */
687 { 21041, 0x3DC0 }, /* R21041 - VSS_XTD15_0 */ 687 { 21041, 0x3DC0 }, /* R21041 - VSS_XTD15_0 */
688 { 21042, 0x00CF }, /* R21042 - VSS_XTD16_1 */ 688 { 21042, 0x00CF }, /* R21042 - VSS_XTD16_1 */
689 { 21043, 0x7A80 }, /* R21043 - VSS_XTD16_0 */ 689 { 21043, 0x7A80 }, /* R21043 - VSS_XTD16_0 */
690 { 21044, 0x00DC }, /* R21044 - VSS_XTD17_1 */ 690 { 21044, 0x00DC }, /* R21044 - VSS_XTD17_1 */
691 { 21045, 0x0600 }, /* R21045 - VSS_XTD17_0 */ 691 { 21045, 0x0600 }, /* R21045 - VSS_XTD17_0 */
692 { 21046, 0x00F2 }, /* R21046 - VSS_XTD18_1 */ 692 { 21046, 0x00F2 }, /* R21046 - VSS_XTD18_1 */
693 { 21047, 0xDAC0 }, /* R21047 - VSS_XTD18_0 */ 693 { 21047, 0xDAC0 }, /* R21047 - VSS_XTD18_0 */
694 { 21048, 0x00BA }, /* R21048 - VSS_XTD19_1 */ 694 { 21048, 0x00BA }, /* R21048 - VSS_XTD19_1 */
695 { 21049, 0xF340 }, /* R21049 - VSS_XTD19_0 */ 695 { 21049, 0xF340 }, /* R21049 - VSS_XTD19_0 */
696 { 21050, 0x000A }, /* R21050 - VSS_XTD20_1 */ 696 { 21050, 0x000A }, /* R21050 - VSS_XTD20_1 */
697 { 21051, 0x7940 }, /* R21051 - VSS_XTD20_0 */ 697 { 21051, 0x7940 }, /* R21051 - VSS_XTD20_0 */
698 { 21052, 0x001C }, /* R21052 - VSS_XTD21_1 */ 698 { 21052, 0x001C }, /* R21052 - VSS_XTD21_1 */
699 { 21053, 0x0680 }, /* R21053 - VSS_XTD21_0 */ 699 { 21053, 0x0680 }, /* R21053 - VSS_XTD21_0 */
700 { 21054, 0x00FD }, /* R21054 - VSS_XTD22_1 */ 700 { 21054, 0x00FD }, /* R21054 - VSS_XTD22_1 */
701 { 21055, 0x2D00 }, /* R21055 - VSS_XTD22_0 */ 701 { 21055, 0x2D00 }, /* R21055 - VSS_XTD22_0 */
702 { 21056, 0x001C }, /* R21056 - VSS_XTD23_1 */ 702 { 21056, 0x001C }, /* R21056 - VSS_XTD23_1 */
703 { 21057, 0xE840 }, /* R21057 - VSS_XTD23_0 */ 703 { 21057, 0xE840 }, /* R21057 - VSS_XTD23_0 */
704 { 21058, 0x000D }, /* R21058 - VSS_XTD24_1 */ 704 { 21058, 0x000D }, /* R21058 - VSS_XTD24_1 */
705 { 21059, 0xDC40 }, /* R21059 - VSS_XTD24_0 */ 705 { 21059, 0xDC40 }, /* R21059 - VSS_XTD24_0 */
706 { 21060, 0x00FC }, /* R21060 - VSS_XTD25_1 */ 706 { 21060, 0x00FC }, /* R21060 - VSS_XTD25_1 */
707 { 21061, 0x9D00 }, /* R21061 - VSS_XTD25_0 */ 707 { 21061, 0x9D00 }, /* R21061 - VSS_XTD25_0 */
708 { 21062, 0x0009 }, /* R21062 - VSS_XTD26_1 */ 708 { 21062, 0x0009 }, /* R21062 - VSS_XTD26_1 */
709 { 21063, 0x5580 }, /* R21063 - VSS_XTD26_0 */ 709 { 21063, 0x5580 }, /* R21063 - VSS_XTD26_0 */
710 { 21064, 0x00FE }, /* R21064 - VSS_XTD27_1 */ 710 { 21064, 0x00FE }, /* R21064 - VSS_XTD27_1 */
711 { 21065, 0x7E80 }, /* R21065 - VSS_XTD27_0 */ 711 { 21065, 0x7E80 }, /* R21065 - VSS_XTD27_0 */
712 { 21066, 0x000E }, /* R21066 - VSS_XTD28_1 */ 712 { 21066, 0x000E }, /* R21066 - VSS_XTD28_1 */
713 { 21067, 0xAB40 }, /* R21067 - VSS_XTD28_0 */ 713 { 21067, 0xAB40 }, /* R21067 - VSS_XTD28_0 */
714 { 21068, 0x00F9 }, /* R21068 - VSS_XTD29_1 */ 714 { 21068, 0x00F9 }, /* R21068 - VSS_XTD29_1 */
715 { 21069, 0x9880 }, /* R21069 - VSS_XTD29_0 */ 715 { 21069, 0x9880 }, /* R21069 - VSS_XTD29_0 */
716 { 21070, 0x0009 }, /* R21070 - VSS_XTD30_1 */ 716 { 21070, 0x0009 }, /* R21070 - VSS_XTD30_1 */
717 { 21071, 0x87C0 }, /* R21071 - VSS_XTD30_0 */ 717 { 21071, 0x87C0 }, /* R21071 - VSS_XTD30_0 */
718 { 21072, 0x00FD }, /* R21072 - VSS_XTD31_1 */ 718 { 21072, 0x00FD }, /* R21072 - VSS_XTD31_1 */
719 { 21073, 0x2C40 }, /* R21073 - VSS_XTD31_0 */ 719 { 21073, 0x2C40 }, /* R21073 - VSS_XTD31_0 */
720 { 21074, 0x0009 }, /* R21074 - VSS_XTD32_1 */ 720 { 21074, 0x0009 }, /* R21074 - VSS_XTD32_1 */
721 { 21075, 0x4800 }, /* R21075 - VSS_XTD32_0 */ 721 { 21075, 0x4800 }, /* R21075 - VSS_XTD32_0 */
722 { 21076, 0x0003 }, /* R21076 - VSS_XTS1_1 */ 722 { 21076, 0x0003 }, /* R21076 - VSS_XTS1_1 */
723 { 21077, 0x5F40 }, /* R21077 - VSS_XTS1_0 */ 723 { 21077, 0x5F40 }, /* R21077 - VSS_XTS1_0 */
724 { 21078, 0x0000 }, /* R21078 - VSS_XTS2_1 */ 724 { 21078, 0x0000 }, /* R21078 - VSS_XTS2_1 */
725 { 21079, 0x8700 }, /* R21079 - VSS_XTS2_0 */ 725 { 21079, 0x8700 }, /* R21079 - VSS_XTS2_0 */
726 { 21080, 0x00FA }, /* R21080 - VSS_XTS3_1 */ 726 { 21080, 0x00FA }, /* R21080 - VSS_XTS3_1 */
727 { 21081, 0xE4C0 }, /* R21081 - VSS_XTS3_0 */ 727 { 21081, 0xE4C0 }, /* R21081 - VSS_XTS3_0 */
728 { 21082, 0x0000 }, /* R21082 - VSS_XTS4_1 */ 728 { 21082, 0x0000 }, /* R21082 - VSS_XTS4_1 */
729 { 21083, 0x0B40 }, /* R21083 - VSS_XTS4_0 */ 729 { 21083, 0x0B40 }, /* R21083 - VSS_XTS4_0 */
730 { 21084, 0x0004 }, /* R21084 - VSS_XTS5_1 */ 730 { 21084, 0x0004 }, /* R21084 - VSS_XTS5_1 */
731 { 21085, 0xE180 }, /* R21085 - VSS_XTS5_0 */ 731 { 21085, 0xE180 }, /* R21085 - VSS_XTS5_0 */
732 { 21086, 0x0001 }, /* R21086 - VSS_XTS6_1 */ 732 { 21086, 0x0001 }, /* R21086 - VSS_XTS6_1 */
733 { 21087, 0x1F40 }, /* R21087 - VSS_XTS6_0 */ 733 { 21087, 0x1F40 }, /* R21087 - VSS_XTS6_0 */
734 { 21088, 0x00F8 }, /* R21088 - VSS_XTS7_1 */ 734 { 21088, 0x00F8 }, /* R21088 - VSS_XTS7_1 */
735 { 21089, 0xB000 }, /* R21089 - VSS_XTS7_0 */ 735 { 21089, 0xB000 }, /* R21089 - VSS_XTS7_0 */
736 { 21090, 0x00FB }, /* R21090 - VSS_XTS8_1 */ 736 { 21090, 0x00FB }, /* R21090 - VSS_XTS8_1 */
737 { 21091, 0xCBC0 }, /* R21091 - VSS_XTS8_0 */ 737 { 21091, 0xCBC0 }, /* R21091 - VSS_XTS8_0 */
738 { 21092, 0x0004 }, /* R21092 - VSS_XTS9_1 */ 738 { 21092, 0x0004 }, /* R21092 - VSS_XTS9_1 */
739 { 21093, 0xF380 }, /* R21093 - VSS_XTS9_0 */ 739 { 21093, 0xF380 }, /* R21093 - VSS_XTS9_0 */
740 { 21094, 0x0007 }, /* R21094 - VSS_XTS10_1 */ 740 { 21094, 0x0007 }, /* R21094 - VSS_XTS10_1 */
741 { 21095, 0xDF40 }, /* R21095 - VSS_XTS10_0 */ 741 { 21095, 0xDF40 }, /* R21095 - VSS_XTS10_0 */
742 { 21096, 0x00FF }, /* R21096 - VSS_XTS11_1 */ 742 { 21096, 0x00FF }, /* R21096 - VSS_XTS11_1 */
743 { 21097, 0x0700 }, /* R21097 - VSS_XTS11_0 */ 743 { 21097, 0x0700 }, /* R21097 - VSS_XTS11_0 */
744 { 21098, 0x00EF }, /* R21098 - VSS_XTS12_1 */ 744 { 21098, 0x00EF }, /* R21098 - VSS_XTS12_1 */
745 { 21099, 0xD700 }, /* R21099 - VSS_XTS12_0 */ 745 { 21099, 0xD700 }, /* R21099 - VSS_XTS12_0 */
746 { 21100, 0x00FB }, /* R21100 - VSS_XTS13_1 */ 746 { 21100, 0x00FB }, /* R21100 - VSS_XTS13_1 */
747 { 21101, 0xAF40 }, /* R21101 - VSS_XTS13_0 */ 747 { 21101, 0xAF40 }, /* R21101 - VSS_XTS13_0 */
748 { 21102, 0x0010 }, /* R21102 - VSS_XTS14_1 */ 748 { 21102, 0x0010 }, /* R21102 - VSS_XTS14_1 */
749 { 21103, 0x8A80 }, /* R21103 - VSS_XTS14_0 */ 749 { 21103, 0x8A80 }, /* R21103 - VSS_XTS14_0 */
750 { 21104, 0x0011 }, /* R21104 - VSS_XTS15_1 */ 750 { 21104, 0x0011 }, /* R21104 - VSS_XTS15_1 */
751 { 21105, 0x07C0 }, /* R21105 - VSS_XTS15_0 */ 751 { 21105, 0x07C0 }, /* R21105 - VSS_XTS15_0 */
752 { 21106, 0x00E0 }, /* R21106 - VSS_XTS16_1 */ 752 { 21106, 0x00E0 }, /* R21106 - VSS_XTS16_1 */
753 { 21107, 0x0800 }, /* R21107 - VSS_XTS16_0 */ 753 { 21107, 0x0800 }, /* R21107 - VSS_XTS16_0 */
754 { 21108, 0x00D2 }, /* R21108 - VSS_XTS17_1 */ 754 { 21108, 0x00D2 }, /* R21108 - VSS_XTS17_1 */
755 { 21109, 0x7600 }, /* R21109 - VSS_XTS17_0 */ 755 { 21109, 0x7600 }, /* R21109 - VSS_XTS17_0 */
756 { 21110, 0x0020 }, /* R21110 - VSS_XTS18_1 */ 756 { 21110, 0x0020 }, /* R21110 - VSS_XTS18_1 */
757 { 21111, 0xCF40 }, /* R21111 - VSS_XTS18_0 */ 757 { 21111, 0xCF40 }, /* R21111 - VSS_XTS18_0 */
758 { 21112, 0x0030 }, /* R21112 - VSS_XTS19_1 */ 758 { 21112, 0x0030 }, /* R21112 - VSS_XTS19_1 */
759 { 21113, 0x2340 }, /* R21113 - VSS_XTS19_0 */ 759 { 21113, 0x2340 }, /* R21113 - VSS_XTS19_0 */
760 { 21114, 0x00FD }, /* R21114 - VSS_XTS20_1 */ 760 { 21114, 0x00FD }, /* R21114 - VSS_XTS20_1 */
761 { 21115, 0x69C0 }, /* R21115 - VSS_XTS20_0 */ 761 { 21115, 0x69C0 }, /* R21115 - VSS_XTS20_0 */
762 { 21116, 0x0028 }, /* R21116 - VSS_XTS21_1 */ 762 { 21116, 0x0028 }, /* R21116 - VSS_XTS21_1 */
763 { 21117, 0x3500 }, /* R21117 - VSS_XTS21_0 */ 763 { 21117, 0x3500 }, /* R21117 - VSS_XTS21_0 */
764 { 21118, 0x0006 }, /* R21118 - VSS_XTS22_1 */ 764 { 21118, 0x0006 }, /* R21118 - VSS_XTS22_1 */
765 { 21119, 0x3300 }, /* R21119 - VSS_XTS22_0 */ 765 { 21119, 0x3300 }, /* R21119 - VSS_XTS22_0 */
766 { 21120, 0x00D9 }, /* R21120 - VSS_XTS23_1 */ 766 { 21120, 0x00D9 }, /* R21120 - VSS_XTS23_1 */
767 { 21121, 0xF6C0 }, /* R21121 - VSS_XTS23_0 */ 767 { 21121, 0xF6C0 }, /* R21121 - VSS_XTS23_0 */
768 { 21122, 0x00F3 }, /* R21122 - VSS_XTS24_1 */ 768 { 21122, 0x00F3 }, /* R21122 - VSS_XTS24_1 */
769 { 21123, 0x3340 }, /* R21123 - VSS_XTS24_0 */ 769 { 21123, 0x3340 }, /* R21123 - VSS_XTS24_0 */
770 { 21124, 0x000F }, /* R21124 - VSS_XTS25_1 */ 770 { 21124, 0x000F }, /* R21124 - VSS_XTS25_1 */
771 { 21125, 0x4200 }, /* R21125 - VSS_XTS25_0 */ 771 { 21125, 0x4200 }, /* R21125 - VSS_XTS25_0 */
772 { 21126, 0x0004 }, /* R21126 - VSS_XTS26_1 */ 772 { 21126, 0x0004 }, /* R21126 - VSS_XTS26_1 */
773 { 21127, 0x0C80 }, /* R21127 - VSS_XTS26_0 */ 773 { 21127, 0x0C80 }, /* R21127 - VSS_XTS26_0 */
774 { 21128, 0x00FB }, /* R21128 - VSS_XTS27_1 */ 774 { 21128, 0x00FB }, /* R21128 - VSS_XTS27_1 */
775 { 21129, 0x3F80 }, /* R21129 - VSS_XTS27_0 */ 775 { 21129, 0x3F80 }, /* R21129 - VSS_XTS27_0 */
776 { 21130, 0x00F7 }, /* R21130 - VSS_XTS28_1 */ 776 { 21130, 0x00F7 }, /* R21130 - VSS_XTS28_1 */
777 { 21131, 0x57C0 }, /* R21131 - VSS_XTS28_0 */ 777 { 21131, 0x57C0 }, /* R21131 - VSS_XTS28_0 */
778 { 21132, 0x0003 }, /* R21132 - VSS_XTS29_1 */ 778 { 21132, 0x0003 }, /* R21132 - VSS_XTS29_1 */
779 { 21133, 0x5400 }, /* R21133 - VSS_XTS29_0 */ 779 { 21133, 0x5400 }, /* R21133 - VSS_XTS29_0 */
780 { 21134, 0x0000 }, /* R21134 - VSS_XTS30_1 */ 780 { 21134, 0x0000 }, /* R21134 - VSS_XTS30_1 */
781 { 21135, 0xC6C0 }, /* R21135 - VSS_XTS30_0 */ 781 { 21135, 0xC6C0 }, /* R21135 - VSS_XTS30_0 */
782 { 21136, 0x0003 }, /* R21136 - VSS_XTS31_1 */ 782 { 21136, 0x0003 }, /* R21136 - VSS_XTS31_1 */
783 { 21137, 0x12C0 }, /* R21137 - VSS_XTS31_0 */ 783 { 21137, 0x12C0 }, /* R21137 - VSS_XTS31_0 */
784 { 21138, 0x00FD }, /* R21138 - VSS_XTS32_1 */ 784 { 21138, 0x00FD }, /* R21138 - VSS_XTS32_1 */
785 { 21139, 0x8580 }, /* R21139 - VSS_XTS32_0 */ 785 { 21139, 0x8580 }, /* R21139 - VSS_XTS32_0 */
786 }; 786 };
787 787
788 static bool wm8962_volatile_register(struct device *dev, unsigned int reg) 788 static bool wm8962_volatile_register(struct device *dev, unsigned int reg)
789 { 789 {
790 switch (reg) { 790 switch (reg) {
791 case WM8962_CLOCKING1: 791 case WM8962_CLOCKING1:
792 case WM8962_CLOCKING2: 792 case WM8962_CLOCKING2:
793 case WM8962_SOFTWARE_RESET: 793 case WM8962_SOFTWARE_RESET:
794 case WM8962_ALC2: 794 case WM8962_ALC2:
795 case WM8962_THERMAL_SHUTDOWN_STATUS: 795 case WM8962_THERMAL_SHUTDOWN_STATUS:
796 case WM8962_ADDITIONAL_CONTROL_4: 796 case WM8962_ADDITIONAL_CONTROL_4:
797 case WM8962_CLASS_D_CONTROL_1: 797 case WM8962_CLASS_D_CONTROL_1:
798 case WM8962_DC_SERVO_6: 798 case WM8962_DC_SERVO_6:
799 case WM8962_INTERRUPT_STATUS_1: 799 case WM8962_INTERRUPT_STATUS_1:
800 case WM8962_INTERRUPT_STATUS_2: 800 case WM8962_INTERRUPT_STATUS_2:
801 case WM8962_DSP2_EXECCONTROL: 801 case WM8962_DSP2_EXECCONTROL:
802 return true; 802 return true;
803 default: 803 default:
804 return false; 804 return false;
805 } 805 }
806 } 806 }
807 807
808 static bool wm8962_readable_register(struct device *dev, unsigned int reg) 808 static bool wm8962_readable_register(struct device *dev, unsigned int reg)
809 { 809 {
810 switch (reg) { 810 switch (reg) {
811 case WM8962_LEFT_INPUT_VOLUME: 811 case WM8962_LEFT_INPUT_VOLUME:
812 case WM8962_RIGHT_INPUT_VOLUME: 812 case WM8962_RIGHT_INPUT_VOLUME:
813 case WM8962_HPOUTL_VOLUME: 813 case WM8962_HPOUTL_VOLUME:
814 case WM8962_HPOUTR_VOLUME: 814 case WM8962_HPOUTR_VOLUME:
815 case WM8962_CLOCKING1: 815 case WM8962_CLOCKING1:
816 case WM8962_ADC_DAC_CONTROL_1: 816 case WM8962_ADC_DAC_CONTROL_1:
817 case WM8962_ADC_DAC_CONTROL_2: 817 case WM8962_ADC_DAC_CONTROL_2:
818 case WM8962_AUDIO_INTERFACE_0: 818 case WM8962_AUDIO_INTERFACE_0:
819 case WM8962_CLOCKING2: 819 case WM8962_CLOCKING2:
820 case WM8962_AUDIO_INTERFACE_1: 820 case WM8962_AUDIO_INTERFACE_1:
821 case WM8962_LEFT_DAC_VOLUME: 821 case WM8962_LEFT_DAC_VOLUME:
822 case WM8962_RIGHT_DAC_VOLUME: 822 case WM8962_RIGHT_DAC_VOLUME:
823 case WM8962_AUDIO_INTERFACE_2: 823 case WM8962_AUDIO_INTERFACE_2:
824 case WM8962_SOFTWARE_RESET: 824 case WM8962_SOFTWARE_RESET:
825 case WM8962_ALC1: 825 case WM8962_ALC1:
826 case WM8962_ALC2: 826 case WM8962_ALC2:
827 case WM8962_ALC3: 827 case WM8962_ALC3:
828 case WM8962_NOISE_GATE: 828 case WM8962_NOISE_GATE:
829 case WM8962_LEFT_ADC_VOLUME: 829 case WM8962_LEFT_ADC_VOLUME:
830 case WM8962_RIGHT_ADC_VOLUME: 830 case WM8962_RIGHT_ADC_VOLUME:
831 case WM8962_ADDITIONAL_CONTROL_1: 831 case WM8962_ADDITIONAL_CONTROL_1:
832 case WM8962_ADDITIONAL_CONTROL_2: 832 case WM8962_ADDITIONAL_CONTROL_2:
833 case WM8962_PWR_MGMT_1: 833 case WM8962_PWR_MGMT_1:
834 case WM8962_PWR_MGMT_2: 834 case WM8962_PWR_MGMT_2:
835 case WM8962_ADDITIONAL_CONTROL_3: 835 case WM8962_ADDITIONAL_CONTROL_3:
836 case WM8962_ANTI_POP: 836 case WM8962_ANTI_POP:
837 case WM8962_CLOCKING_3: 837 case WM8962_CLOCKING_3:
838 case WM8962_INPUT_MIXER_CONTROL_1: 838 case WM8962_INPUT_MIXER_CONTROL_1:
839 case WM8962_LEFT_INPUT_MIXER_VOLUME: 839 case WM8962_LEFT_INPUT_MIXER_VOLUME:
840 case WM8962_RIGHT_INPUT_MIXER_VOLUME: 840 case WM8962_RIGHT_INPUT_MIXER_VOLUME:
841 case WM8962_INPUT_MIXER_CONTROL_2: 841 case WM8962_INPUT_MIXER_CONTROL_2:
842 case WM8962_INPUT_BIAS_CONTROL: 842 case WM8962_INPUT_BIAS_CONTROL:
843 case WM8962_LEFT_INPUT_PGA_CONTROL: 843 case WM8962_LEFT_INPUT_PGA_CONTROL:
844 case WM8962_RIGHT_INPUT_PGA_CONTROL: 844 case WM8962_RIGHT_INPUT_PGA_CONTROL:
845 case WM8962_SPKOUTL_VOLUME: 845 case WM8962_SPKOUTL_VOLUME:
846 case WM8962_SPKOUTR_VOLUME: 846 case WM8962_SPKOUTR_VOLUME:
847 case WM8962_THERMAL_SHUTDOWN_STATUS: 847 case WM8962_THERMAL_SHUTDOWN_STATUS:
848 case WM8962_ADDITIONAL_CONTROL_4: 848 case WM8962_ADDITIONAL_CONTROL_4:
849 case WM8962_CLASS_D_CONTROL_1: 849 case WM8962_CLASS_D_CONTROL_1:
850 case WM8962_CLASS_D_CONTROL_2: 850 case WM8962_CLASS_D_CONTROL_2:
851 case WM8962_CLOCKING_4: 851 case WM8962_CLOCKING_4:
852 case WM8962_DAC_DSP_MIXING_1: 852 case WM8962_DAC_DSP_MIXING_1:
853 case WM8962_DAC_DSP_MIXING_2: 853 case WM8962_DAC_DSP_MIXING_2:
854 case WM8962_DC_SERVO_0: 854 case WM8962_DC_SERVO_0:
855 case WM8962_DC_SERVO_1: 855 case WM8962_DC_SERVO_1:
856 case WM8962_DC_SERVO_4: 856 case WM8962_DC_SERVO_4:
857 case WM8962_DC_SERVO_6: 857 case WM8962_DC_SERVO_6:
858 case WM8962_ANALOGUE_PGA_BIAS: 858 case WM8962_ANALOGUE_PGA_BIAS:
859 case WM8962_ANALOGUE_HP_0: 859 case WM8962_ANALOGUE_HP_0:
860 case WM8962_ANALOGUE_HP_2: 860 case WM8962_ANALOGUE_HP_2:
861 case WM8962_CHARGE_PUMP_1: 861 case WM8962_CHARGE_PUMP_1:
862 case WM8962_CHARGE_PUMP_B: 862 case WM8962_CHARGE_PUMP_B:
863 case WM8962_WRITE_SEQUENCER_CONTROL_1: 863 case WM8962_WRITE_SEQUENCER_CONTROL_1:
864 case WM8962_WRITE_SEQUENCER_CONTROL_2: 864 case WM8962_WRITE_SEQUENCER_CONTROL_2:
865 case WM8962_WRITE_SEQUENCER_CONTROL_3: 865 case WM8962_WRITE_SEQUENCER_CONTROL_3:
866 case WM8962_CONTROL_INTERFACE: 866 case WM8962_CONTROL_INTERFACE:
867 case WM8962_MIXER_ENABLES: 867 case WM8962_MIXER_ENABLES:
868 case WM8962_HEADPHONE_MIXER_1: 868 case WM8962_HEADPHONE_MIXER_1:
869 case WM8962_HEADPHONE_MIXER_2: 869 case WM8962_HEADPHONE_MIXER_2:
870 case WM8962_HEADPHONE_MIXER_3: 870 case WM8962_HEADPHONE_MIXER_3:
871 case WM8962_HEADPHONE_MIXER_4: 871 case WM8962_HEADPHONE_MIXER_4:
872 case WM8962_SPEAKER_MIXER_1: 872 case WM8962_SPEAKER_MIXER_1:
873 case WM8962_SPEAKER_MIXER_2: 873 case WM8962_SPEAKER_MIXER_2:
874 case WM8962_SPEAKER_MIXER_3: 874 case WM8962_SPEAKER_MIXER_3:
875 case WM8962_SPEAKER_MIXER_4: 875 case WM8962_SPEAKER_MIXER_4:
876 case WM8962_SPEAKER_MIXER_5: 876 case WM8962_SPEAKER_MIXER_5:
877 case WM8962_BEEP_GENERATOR_1: 877 case WM8962_BEEP_GENERATOR_1:
878 case WM8962_OSCILLATOR_TRIM_3: 878 case WM8962_OSCILLATOR_TRIM_3:
879 case WM8962_OSCILLATOR_TRIM_4: 879 case WM8962_OSCILLATOR_TRIM_4:
880 case WM8962_OSCILLATOR_TRIM_7: 880 case WM8962_OSCILLATOR_TRIM_7:
881 case WM8962_ANALOGUE_CLOCKING1: 881 case WM8962_ANALOGUE_CLOCKING1:
882 case WM8962_ANALOGUE_CLOCKING2: 882 case WM8962_ANALOGUE_CLOCKING2:
883 case WM8962_ANALOGUE_CLOCKING3: 883 case WM8962_ANALOGUE_CLOCKING3:
884 case WM8962_PLL_SOFTWARE_RESET: 884 case WM8962_PLL_SOFTWARE_RESET:
885 case WM8962_PLL2: 885 case WM8962_PLL2:
886 case WM8962_PLL_4: 886 case WM8962_PLL_4:
887 case WM8962_PLL_9: 887 case WM8962_PLL_9:
888 case WM8962_PLL_10: 888 case WM8962_PLL_10:
889 case WM8962_PLL_11: 889 case WM8962_PLL_11:
890 case WM8962_PLL_12: 890 case WM8962_PLL_12:
891 case WM8962_PLL_13: 891 case WM8962_PLL_13:
892 case WM8962_PLL_14: 892 case WM8962_PLL_14:
893 case WM8962_PLL_15: 893 case WM8962_PLL_15:
894 case WM8962_PLL_16: 894 case WM8962_PLL_16:
895 case WM8962_FLL_CONTROL_1: 895 case WM8962_FLL_CONTROL_1:
896 case WM8962_FLL_CONTROL_2: 896 case WM8962_FLL_CONTROL_2:
897 case WM8962_FLL_CONTROL_3: 897 case WM8962_FLL_CONTROL_3:
898 case WM8962_FLL_CONTROL_5: 898 case WM8962_FLL_CONTROL_5:
899 case WM8962_FLL_CONTROL_6: 899 case WM8962_FLL_CONTROL_6:
900 case WM8962_FLL_CONTROL_7: 900 case WM8962_FLL_CONTROL_7:
901 case WM8962_FLL_CONTROL_8: 901 case WM8962_FLL_CONTROL_8:
902 case WM8962_GENERAL_TEST_1: 902 case WM8962_GENERAL_TEST_1:
903 case WM8962_DF1: 903 case WM8962_DF1:
904 case WM8962_DF2: 904 case WM8962_DF2:
905 case WM8962_DF3: 905 case WM8962_DF3:
906 case WM8962_DF4: 906 case WM8962_DF4:
907 case WM8962_DF5: 907 case WM8962_DF5:
908 case WM8962_DF6: 908 case WM8962_DF6:
909 case WM8962_DF7: 909 case WM8962_DF7:
910 case WM8962_LHPF1: 910 case WM8962_LHPF1:
911 case WM8962_LHPF2: 911 case WM8962_LHPF2:
912 case WM8962_THREED1: 912 case WM8962_THREED1:
913 case WM8962_THREED2: 913 case WM8962_THREED2:
914 case WM8962_THREED3: 914 case WM8962_THREED3:
915 case WM8962_THREED4: 915 case WM8962_THREED4:
916 case WM8962_DRC_1: 916 case WM8962_DRC_1:
917 case WM8962_DRC_2: 917 case WM8962_DRC_2:
918 case WM8962_DRC_3: 918 case WM8962_DRC_3:
919 case WM8962_DRC_4: 919 case WM8962_DRC_4:
920 case WM8962_DRC_5: 920 case WM8962_DRC_5:
921 case WM8962_TLOOPBACK: 921 case WM8962_TLOOPBACK:
922 case WM8962_EQ1: 922 case WM8962_EQ1:
923 case WM8962_EQ2: 923 case WM8962_EQ2:
924 case WM8962_EQ3: 924 case WM8962_EQ3:
925 case WM8962_EQ4: 925 case WM8962_EQ4:
926 case WM8962_EQ5: 926 case WM8962_EQ5:
927 case WM8962_EQ6: 927 case WM8962_EQ6:
928 case WM8962_EQ7: 928 case WM8962_EQ7:
929 case WM8962_EQ8: 929 case WM8962_EQ8:
930 case WM8962_EQ9: 930 case WM8962_EQ9:
931 case WM8962_EQ10: 931 case WM8962_EQ10:
932 case WM8962_EQ11: 932 case WM8962_EQ11:
933 case WM8962_EQ12: 933 case WM8962_EQ12:
934 case WM8962_EQ13: 934 case WM8962_EQ13:
935 case WM8962_EQ14: 935 case WM8962_EQ14:
936 case WM8962_EQ15: 936 case WM8962_EQ15:
937 case WM8962_EQ16: 937 case WM8962_EQ16:
938 case WM8962_EQ17: 938 case WM8962_EQ17:
939 case WM8962_EQ18: 939 case WM8962_EQ18:
940 case WM8962_EQ19: 940 case WM8962_EQ19:
941 case WM8962_EQ20: 941 case WM8962_EQ20:
942 case WM8962_EQ21: 942 case WM8962_EQ21:
943 case WM8962_EQ22: 943 case WM8962_EQ22:
944 case WM8962_EQ23: 944 case WM8962_EQ23:
945 case WM8962_EQ24: 945 case WM8962_EQ24:
946 case WM8962_EQ25: 946 case WM8962_EQ25:
947 case WM8962_EQ26: 947 case WM8962_EQ26:
948 case WM8962_EQ27: 948 case WM8962_EQ27:
949 case WM8962_EQ28: 949 case WM8962_EQ28:
950 case WM8962_EQ29: 950 case WM8962_EQ29:
951 case WM8962_EQ30: 951 case WM8962_EQ30:
952 case WM8962_EQ31: 952 case WM8962_EQ31:
953 case WM8962_EQ32: 953 case WM8962_EQ32:
954 case WM8962_EQ33: 954 case WM8962_EQ33:
955 case WM8962_EQ34: 955 case WM8962_EQ34:
956 case WM8962_EQ35: 956 case WM8962_EQ35:
957 case WM8962_EQ36: 957 case WM8962_EQ36:
958 case WM8962_EQ37: 958 case WM8962_EQ37:
959 case WM8962_EQ38: 959 case WM8962_EQ38:
960 case WM8962_EQ39: 960 case WM8962_EQ39:
961 case WM8962_EQ40: 961 case WM8962_EQ40:
962 case WM8962_EQ41: 962 case WM8962_EQ41:
963 case WM8962_GPIO_BASE: 963 case WM8962_GPIO_BASE:
964 case WM8962_GPIO_2: 964 case WM8962_GPIO_2:
965 case WM8962_GPIO_3: 965 case WM8962_GPIO_3:
966 case WM8962_GPIO_5: 966 case WM8962_GPIO_5:
967 case WM8962_GPIO_6: 967 case WM8962_GPIO_6:
968 case WM8962_INTERRUPT_STATUS_1: 968 case WM8962_INTERRUPT_STATUS_1:
969 case WM8962_INTERRUPT_STATUS_2: 969 case WM8962_INTERRUPT_STATUS_2:
970 case WM8962_INTERRUPT_STATUS_1_MASK: 970 case WM8962_INTERRUPT_STATUS_1_MASK:
971 case WM8962_INTERRUPT_STATUS_2_MASK: 971 case WM8962_INTERRUPT_STATUS_2_MASK:
972 case WM8962_INTERRUPT_CONTROL: 972 case WM8962_INTERRUPT_CONTROL:
973 case WM8962_IRQ_DEBOUNCE: 973 case WM8962_IRQ_DEBOUNCE:
974 case WM8962_MICINT_SOURCE_POL: 974 case WM8962_MICINT_SOURCE_POL:
975 case WM8962_DSP2_POWER_MANAGEMENT: 975 case WM8962_DSP2_POWER_MANAGEMENT:
976 case WM8962_DSP2_EXECCONTROL: 976 case WM8962_DSP2_EXECCONTROL:
977 case WM8962_DSP2_INSTRUCTION_RAM_0: 977 case WM8962_DSP2_INSTRUCTION_RAM_0:
978 case WM8962_DSP2_ADDRESS_RAM_2: 978 case WM8962_DSP2_ADDRESS_RAM_2:
979 case WM8962_DSP2_ADDRESS_RAM_1: 979 case WM8962_DSP2_ADDRESS_RAM_1:
980 case WM8962_DSP2_ADDRESS_RAM_0: 980 case WM8962_DSP2_ADDRESS_RAM_0:
981 case WM8962_DSP2_DATA1_RAM_1: 981 case WM8962_DSP2_DATA1_RAM_1:
982 case WM8962_DSP2_DATA1_RAM_0: 982 case WM8962_DSP2_DATA1_RAM_0:
983 case WM8962_DSP2_DATA2_RAM_1: 983 case WM8962_DSP2_DATA2_RAM_1:
984 case WM8962_DSP2_DATA2_RAM_0: 984 case WM8962_DSP2_DATA2_RAM_0:
985 case WM8962_DSP2_DATA3_RAM_1: 985 case WM8962_DSP2_DATA3_RAM_1:
986 case WM8962_DSP2_DATA3_RAM_0: 986 case WM8962_DSP2_DATA3_RAM_0:
987 case WM8962_DSP2_COEFF_RAM_0: 987 case WM8962_DSP2_COEFF_RAM_0:
988 case WM8962_RETUNEADC_SHARED_COEFF_1: 988 case WM8962_RETUNEADC_SHARED_COEFF_1:
989 case WM8962_RETUNEADC_SHARED_COEFF_0: 989 case WM8962_RETUNEADC_SHARED_COEFF_0:
990 case WM8962_RETUNEDAC_SHARED_COEFF_1: 990 case WM8962_RETUNEDAC_SHARED_COEFF_1:
991 case WM8962_RETUNEDAC_SHARED_COEFF_0: 991 case WM8962_RETUNEDAC_SHARED_COEFF_0:
992 case WM8962_SOUNDSTAGE_ENABLES_1: 992 case WM8962_SOUNDSTAGE_ENABLES_1:
993 case WM8962_SOUNDSTAGE_ENABLES_0: 993 case WM8962_SOUNDSTAGE_ENABLES_0:
994 case WM8962_HDBASS_AI_1: 994 case WM8962_HDBASS_AI_1:
995 case WM8962_HDBASS_AI_0: 995 case WM8962_HDBASS_AI_0:
996 case WM8962_HDBASS_AR_1: 996 case WM8962_HDBASS_AR_1:
997 case WM8962_HDBASS_AR_0: 997 case WM8962_HDBASS_AR_0:
998 case WM8962_HDBASS_B_1: 998 case WM8962_HDBASS_B_1:
999 case WM8962_HDBASS_B_0: 999 case WM8962_HDBASS_B_0:
1000 case WM8962_HDBASS_K_1: 1000 case WM8962_HDBASS_K_1:
1001 case WM8962_HDBASS_K_0: 1001 case WM8962_HDBASS_K_0:
1002 case WM8962_HDBASS_N1_1: 1002 case WM8962_HDBASS_N1_1:
1003 case WM8962_HDBASS_N1_0: 1003 case WM8962_HDBASS_N1_0:
1004 case WM8962_HDBASS_N2_1: 1004 case WM8962_HDBASS_N2_1:
1005 case WM8962_HDBASS_N2_0: 1005 case WM8962_HDBASS_N2_0:
1006 case WM8962_HDBASS_N3_1: 1006 case WM8962_HDBASS_N3_1:
1007 case WM8962_HDBASS_N3_0: 1007 case WM8962_HDBASS_N3_0:
1008 case WM8962_HDBASS_N4_1: 1008 case WM8962_HDBASS_N4_1:
1009 case WM8962_HDBASS_N4_0: 1009 case WM8962_HDBASS_N4_0:
1010 case WM8962_HDBASS_N5_1: 1010 case WM8962_HDBASS_N5_1:
1011 case WM8962_HDBASS_N5_0: 1011 case WM8962_HDBASS_N5_0:
1012 case WM8962_HDBASS_X1_1: 1012 case WM8962_HDBASS_X1_1:
1013 case WM8962_HDBASS_X1_0: 1013 case WM8962_HDBASS_X1_0:
1014 case WM8962_HDBASS_X2_1: 1014 case WM8962_HDBASS_X2_1:
1015 case WM8962_HDBASS_X2_0: 1015 case WM8962_HDBASS_X2_0:
1016 case WM8962_HDBASS_X3_1: 1016 case WM8962_HDBASS_X3_1:
1017 case WM8962_HDBASS_X3_0: 1017 case WM8962_HDBASS_X3_0:
1018 case WM8962_HDBASS_ATK_1: 1018 case WM8962_HDBASS_ATK_1:
1019 case WM8962_HDBASS_ATK_0: 1019 case WM8962_HDBASS_ATK_0:
1020 case WM8962_HDBASS_DCY_1: 1020 case WM8962_HDBASS_DCY_1:
1021 case WM8962_HDBASS_DCY_0: 1021 case WM8962_HDBASS_DCY_0:
1022 case WM8962_HDBASS_PG_1: 1022 case WM8962_HDBASS_PG_1:
1023 case WM8962_HDBASS_PG_0: 1023 case WM8962_HDBASS_PG_0:
1024 case WM8962_HPF_C_1: 1024 case WM8962_HPF_C_1:
1025 case WM8962_HPF_C_0: 1025 case WM8962_HPF_C_0:
1026 case WM8962_ADCL_RETUNE_C1_1: 1026 case WM8962_ADCL_RETUNE_C1_1:
1027 case WM8962_ADCL_RETUNE_C1_0: 1027 case WM8962_ADCL_RETUNE_C1_0:
1028 case WM8962_ADCL_RETUNE_C2_1: 1028 case WM8962_ADCL_RETUNE_C2_1:
1029 case WM8962_ADCL_RETUNE_C2_0: 1029 case WM8962_ADCL_RETUNE_C2_0:
1030 case WM8962_ADCL_RETUNE_C3_1: 1030 case WM8962_ADCL_RETUNE_C3_1:
1031 case WM8962_ADCL_RETUNE_C3_0: 1031 case WM8962_ADCL_RETUNE_C3_0:
1032 case WM8962_ADCL_RETUNE_C4_1: 1032 case WM8962_ADCL_RETUNE_C4_1:
1033 case WM8962_ADCL_RETUNE_C4_0: 1033 case WM8962_ADCL_RETUNE_C4_0:
1034 case WM8962_ADCL_RETUNE_C5_1: 1034 case WM8962_ADCL_RETUNE_C5_1:
1035 case WM8962_ADCL_RETUNE_C5_0: 1035 case WM8962_ADCL_RETUNE_C5_0:
1036 case WM8962_ADCL_RETUNE_C6_1: 1036 case WM8962_ADCL_RETUNE_C6_1:
1037 case WM8962_ADCL_RETUNE_C6_0: 1037 case WM8962_ADCL_RETUNE_C6_0:
1038 case WM8962_ADCL_RETUNE_C7_1: 1038 case WM8962_ADCL_RETUNE_C7_1:
1039 case WM8962_ADCL_RETUNE_C7_0: 1039 case WM8962_ADCL_RETUNE_C7_0:
1040 case WM8962_ADCL_RETUNE_C8_1: 1040 case WM8962_ADCL_RETUNE_C8_1:
1041 case WM8962_ADCL_RETUNE_C8_0: 1041 case WM8962_ADCL_RETUNE_C8_0:
1042 case WM8962_ADCL_RETUNE_C9_1: 1042 case WM8962_ADCL_RETUNE_C9_1:
1043 case WM8962_ADCL_RETUNE_C9_0: 1043 case WM8962_ADCL_RETUNE_C9_0:
1044 case WM8962_ADCL_RETUNE_C10_1: 1044 case WM8962_ADCL_RETUNE_C10_1:
1045 case WM8962_ADCL_RETUNE_C10_0: 1045 case WM8962_ADCL_RETUNE_C10_0:
1046 case WM8962_ADCL_RETUNE_C11_1: 1046 case WM8962_ADCL_RETUNE_C11_1:
1047 case WM8962_ADCL_RETUNE_C11_0: 1047 case WM8962_ADCL_RETUNE_C11_0:
1048 case WM8962_ADCL_RETUNE_C12_1: 1048 case WM8962_ADCL_RETUNE_C12_1:
1049 case WM8962_ADCL_RETUNE_C12_0: 1049 case WM8962_ADCL_RETUNE_C12_0:
1050 case WM8962_ADCL_RETUNE_C13_1: 1050 case WM8962_ADCL_RETUNE_C13_1:
1051 case WM8962_ADCL_RETUNE_C13_0: 1051 case WM8962_ADCL_RETUNE_C13_0:
1052 case WM8962_ADCL_RETUNE_C14_1: 1052 case WM8962_ADCL_RETUNE_C14_1:
1053 case WM8962_ADCL_RETUNE_C14_0: 1053 case WM8962_ADCL_RETUNE_C14_0:
1054 case WM8962_ADCL_RETUNE_C15_1: 1054 case WM8962_ADCL_RETUNE_C15_1:
1055 case WM8962_ADCL_RETUNE_C15_0: 1055 case WM8962_ADCL_RETUNE_C15_0:
1056 case WM8962_ADCL_RETUNE_C16_1: 1056 case WM8962_ADCL_RETUNE_C16_1:
1057 case WM8962_ADCL_RETUNE_C16_0: 1057 case WM8962_ADCL_RETUNE_C16_0:
1058 case WM8962_ADCL_RETUNE_C17_1: 1058 case WM8962_ADCL_RETUNE_C17_1:
1059 case WM8962_ADCL_RETUNE_C17_0: 1059 case WM8962_ADCL_RETUNE_C17_0:
1060 case WM8962_ADCL_RETUNE_C18_1: 1060 case WM8962_ADCL_RETUNE_C18_1:
1061 case WM8962_ADCL_RETUNE_C18_0: 1061 case WM8962_ADCL_RETUNE_C18_0:
1062 case WM8962_ADCL_RETUNE_C19_1: 1062 case WM8962_ADCL_RETUNE_C19_1:
1063 case WM8962_ADCL_RETUNE_C19_0: 1063 case WM8962_ADCL_RETUNE_C19_0:
1064 case WM8962_ADCL_RETUNE_C20_1: 1064 case WM8962_ADCL_RETUNE_C20_1:
1065 case WM8962_ADCL_RETUNE_C20_0: 1065 case WM8962_ADCL_RETUNE_C20_0:
1066 case WM8962_ADCL_RETUNE_C21_1: 1066 case WM8962_ADCL_RETUNE_C21_1:
1067 case WM8962_ADCL_RETUNE_C21_0: 1067 case WM8962_ADCL_RETUNE_C21_0:
1068 case WM8962_ADCL_RETUNE_C22_1: 1068 case WM8962_ADCL_RETUNE_C22_1:
1069 case WM8962_ADCL_RETUNE_C22_0: 1069 case WM8962_ADCL_RETUNE_C22_0:
1070 case WM8962_ADCL_RETUNE_C23_1: 1070 case WM8962_ADCL_RETUNE_C23_1:
1071 case WM8962_ADCL_RETUNE_C23_0: 1071 case WM8962_ADCL_RETUNE_C23_0:
1072 case WM8962_ADCL_RETUNE_C24_1: 1072 case WM8962_ADCL_RETUNE_C24_1:
1073 case WM8962_ADCL_RETUNE_C24_0: 1073 case WM8962_ADCL_RETUNE_C24_0:
1074 case WM8962_ADCL_RETUNE_C25_1: 1074 case WM8962_ADCL_RETUNE_C25_1:
1075 case WM8962_ADCL_RETUNE_C25_0: 1075 case WM8962_ADCL_RETUNE_C25_0:
1076 case WM8962_ADCL_RETUNE_C26_1: 1076 case WM8962_ADCL_RETUNE_C26_1:
1077 case WM8962_ADCL_RETUNE_C26_0: 1077 case WM8962_ADCL_RETUNE_C26_0:
1078 case WM8962_ADCL_RETUNE_C27_1: 1078 case WM8962_ADCL_RETUNE_C27_1:
1079 case WM8962_ADCL_RETUNE_C27_0: 1079 case WM8962_ADCL_RETUNE_C27_0:
1080 case WM8962_ADCL_RETUNE_C28_1: 1080 case WM8962_ADCL_RETUNE_C28_1:
1081 case WM8962_ADCL_RETUNE_C28_0: 1081 case WM8962_ADCL_RETUNE_C28_0:
1082 case WM8962_ADCL_RETUNE_C29_1: 1082 case WM8962_ADCL_RETUNE_C29_1:
1083 case WM8962_ADCL_RETUNE_C29_0: 1083 case WM8962_ADCL_RETUNE_C29_0:
1084 case WM8962_ADCL_RETUNE_C30_1: 1084 case WM8962_ADCL_RETUNE_C30_1:
1085 case WM8962_ADCL_RETUNE_C30_0: 1085 case WM8962_ADCL_RETUNE_C30_0:
1086 case WM8962_ADCL_RETUNE_C31_1: 1086 case WM8962_ADCL_RETUNE_C31_1:
1087 case WM8962_ADCL_RETUNE_C31_0: 1087 case WM8962_ADCL_RETUNE_C31_0:
1088 case WM8962_ADCL_RETUNE_C32_1: 1088 case WM8962_ADCL_RETUNE_C32_1:
1089 case WM8962_ADCL_RETUNE_C32_0: 1089 case WM8962_ADCL_RETUNE_C32_0:
1090 case WM8962_RETUNEADC_PG2_1: 1090 case WM8962_RETUNEADC_PG2_1:
1091 case WM8962_RETUNEADC_PG2_0: 1091 case WM8962_RETUNEADC_PG2_0:
1092 case WM8962_RETUNEADC_PG_1: 1092 case WM8962_RETUNEADC_PG_1:
1093 case WM8962_RETUNEADC_PG_0: 1093 case WM8962_RETUNEADC_PG_0:
1094 case WM8962_ADCR_RETUNE_C1_1: 1094 case WM8962_ADCR_RETUNE_C1_1:
1095 case WM8962_ADCR_RETUNE_C1_0: 1095 case WM8962_ADCR_RETUNE_C1_0:
1096 case WM8962_ADCR_RETUNE_C2_1: 1096 case WM8962_ADCR_RETUNE_C2_1:
1097 case WM8962_ADCR_RETUNE_C2_0: 1097 case WM8962_ADCR_RETUNE_C2_0:
1098 case WM8962_ADCR_RETUNE_C3_1: 1098 case WM8962_ADCR_RETUNE_C3_1:
1099 case WM8962_ADCR_RETUNE_C3_0: 1099 case WM8962_ADCR_RETUNE_C3_0:
1100 case WM8962_ADCR_RETUNE_C4_1: 1100 case WM8962_ADCR_RETUNE_C4_1:
1101 case WM8962_ADCR_RETUNE_C4_0: 1101 case WM8962_ADCR_RETUNE_C4_0:
1102 case WM8962_ADCR_RETUNE_C5_1: 1102 case WM8962_ADCR_RETUNE_C5_1:
1103 case WM8962_ADCR_RETUNE_C5_0: 1103 case WM8962_ADCR_RETUNE_C5_0:
1104 case WM8962_ADCR_RETUNE_C6_1: 1104 case WM8962_ADCR_RETUNE_C6_1:
1105 case WM8962_ADCR_RETUNE_C6_0: 1105 case WM8962_ADCR_RETUNE_C6_0:
1106 case WM8962_ADCR_RETUNE_C7_1: 1106 case WM8962_ADCR_RETUNE_C7_1:
1107 case WM8962_ADCR_RETUNE_C7_0: 1107 case WM8962_ADCR_RETUNE_C7_0:
1108 case WM8962_ADCR_RETUNE_C8_1: 1108 case WM8962_ADCR_RETUNE_C8_1:
1109 case WM8962_ADCR_RETUNE_C8_0: 1109 case WM8962_ADCR_RETUNE_C8_0:
1110 case WM8962_ADCR_RETUNE_C9_1: 1110 case WM8962_ADCR_RETUNE_C9_1:
1111 case WM8962_ADCR_RETUNE_C9_0: 1111 case WM8962_ADCR_RETUNE_C9_0:
1112 case WM8962_ADCR_RETUNE_C10_1: 1112 case WM8962_ADCR_RETUNE_C10_1:
1113 case WM8962_ADCR_RETUNE_C10_0: 1113 case WM8962_ADCR_RETUNE_C10_0:
1114 case WM8962_ADCR_RETUNE_C11_1: 1114 case WM8962_ADCR_RETUNE_C11_1:
1115 case WM8962_ADCR_RETUNE_C11_0: 1115 case WM8962_ADCR_RETUNE_C11_0:
1116 case WM8962_ADCR_RETUNE_C12_1: 1116 case WM8962_ADCR_RETUNE_C12_1:
1117 case WM8962_ADCR_RETUNE_C12_0: 1117 case WM8962_ADCR_RETUNE_C12_0:
1118 case WM8962_ADCR_RETUNE_C13_1: 1118 case WM8962_ADCR_RETUNE_C13_1:
1119 case WM8962_ADCR_RETUNE_C13_0: 1119 case WM8962_ADCR_RETUNE_C13_0:
1120 case WM8962_ADCR_RETUNE_C14_1: 1120 case WM8962_ADCR_RETUNE_C14_1:
1121 case WM8962_ADCR_RETUNE_C14_0: 1121 case WM8962_ADCR_RETUNE_C14_0:
1122 case WM8962_ADCR_RETUNE_C15_1: 1122 case WM8962_ADCR_RETUNE_C15_1:
1123 case WM8962_ADCR_RETUNE_C15_0: 1123 case WM8962_ADCR_RETUNE_C15_0:
1124 case WM8962_ADCR_RETUNE_C16_1: 1124 case WM8962_ADCR_RETUNE_C16_1:
1125 case WM8962_ADCR_RETUNE_C16_0: 1125 case WM8962_ADCR_RETUNE_C16_0:
1126 case WM8962_ADCR_RETUNE_C17_1: 1126 case WM8962_ADCR_RETUNE_C17_1:
1127 case WM8962_ADCR_RETUNE_C17_0: 1127 case WM8962_ADCR_RETUNE_C17_0:
1128 case WM8962_ADCR_RETUNE_C18_1: 1128 case WM8962_ADCR_RETUNE_C18_1:
1129 case WM8962_ADCR_RETUNE_C18_0: 1129 case WM8962_ADCR_RETUNE_C18_0:
1130 case WM8962_ADCR_RETUNE_C19_1: 1130 case WM8962_ADCR_RETUNE_C19_1:
1131 case WM8962_ADCR_RETUNE_C19_0: 1131 case WM8962_ADCR_RETUNE_C19_0:
1132 case WM8962_ADCR_RETUNE_C20_1: 1132 case WM8962_ADCR_RETUNE_C20_1:
1133 case WM8962_ADCR_RETUNE_C20_0: 1133 case WM8962_ADCR_RETUNE_C20_0:
1134 case WM8962_ADCR_RETUNE_C21_1: 1134 case WM8962_ADCR_RETUNE_C21_1:
1135 case WM8962_ADCR_RETUNE_C21_0: 1135 case WM8962_ADCR_RETUNE_C21_0:
1136 case WM8962_ADCR_RETUNE_C22_1: 1136 case WM8962_ADCR_RETUNE_C22_1:
1137 case WM8962_ADCR_RETUNE_C22_0: 1137 case WM8962_ADCR_RETUNE_C22_0:
1138 case WM8962_ADCR_RETUNE_C23_1: 1138 case WM8962_ADCR_RETUNE_C23_1:
1139 case WM8962_ADCR_RETUNE_C23_0: 1139 case WM8962_ADCR_RETUNE_C23_0:
1140 case WM8962_ADCR_RETUNE_C24_1: 1140 case WM8962_ADCR_RETUNE_C24_1:
1141 case WM8962_ADCR_RETUNE_C24_0: 1141 case WM8962_ADCR_RETUNE_C24_0:
1142 case WM8962_ADCR_RETUNE_C25_1: 1142 case WM8962_ADCR_RETUNE_C25_1:
1143 case WM8962_ADCR_RETUNE_C25_0: 1143 case WM8962_ADCR_RETUNE_C25_0:
1144 case WM8962_ADCR_RETUNE_C26_1: 1144 case WM8962_ADCR_RETUNE_C26_1:
1145 case WM8962_ADCR_RETUNE_C26_0: 1145 case WM8962_ADCR_RETUNE_C26_0:
1146 case WM8962_ADCR_RETUNE_C27_1: 1146 case WM8962_ADCR_RETUNE_C27_1:
1147 case WM8962_ADCR_RETUNE_C27_0: 1147 case WM8962_ADCR_RETUNE_C27_0:
1148 case WM8962_ADCR_RETUNE_C28_1: 1148 case WM8962_ADCR_RETUNE_C28_1:
1149 case WM8962_ADCR_RETUNE_C28_0: 1149 case WM8962_ADCR_RETUNE_C28_0:
1150 case WM8962_ADCR_RETUNE_C29_1: 1150 case WM8962_ADCR_RETUNE_C29_1:
1151 case WM8962_ADCR_RETUNE_C29_0: 1151 case WM8962_ADCR_RETUNE_C29_0:
1152 case WM8962_ADCR_RETUNE_C30_1: 1152 case WM8962_ADCR_RETUNE_C30_1:
1153 case WM8962_ADCR_RETUNE_C30_0: 1153 case WM8962_ADCR_RETUNE_C30_0:
1154 case WM8962_ADCR_RETUNE_C31_1: 1154 case WM8962_ADCR_RETUNE_C31_1:
1155 case WM8962_ADCR_RETUNE_C31_0: 1155 case WM8962_ADCR_RETUNE_C31_0:
1156 case WM8962_ADCR_RETUNE_C32_1: 1156 case WM8962_ADCR_RETUNE_C32_1:
1157 case WM8962_ADCR_RETUNE_C32_0: 1157 case WM8962_ADCR_RETUNE_C32_0:
1158 case WM8962_DACL_RETUNE_C1_1: 1158 case WM8962_DACL_RETUNE_C1_1:
1159 case WM8962_DACL_RETUNE_C1_0: 1159 case WM8962_DACL_RETUNE_C1_0:
1160 case WM8962_DACL_RETUNE_C2_1: 1160 case WM8962_DACL_RETUNE_C2_1:
1161 case WM8962_DACL_RETUNE_C2_0: 1161 case WM8962_DACL_RETUNE_C2_0:
1162 case WM8962_DACL_RETUNE_C3_1: 1162 case WM8962_DACL_RETUNE_C3_1:
1163 case WM8962_DACL_RETUNE_C3_0: 1163 case WM8962_DACL_RETUNE_C3_0:
1164 case WM8962_DACL_RETUNE_C4_1: 1164 case WM8962_DACL_RETUNE_C4_1:
1165 case WM8962_DACL_RETUNE_C4_0: 1165 case WM8962_DACL_RETUNE_C4_0:
1166 case WM8962_DACL_RETUNE_C5_1: 1166 case WM8962_DACL_RETUNE_C5_1:
1167 case WM8962_DACL_RETUNE_C5_0: 1167 case WM8962_DACL_RETUNE_C5_0:
1168 case WM8962_DACL_RETUNE_C6_1: 1168 case WM8962_DACL_RETUNE_C6_1:
1169 case WM8962_DACL_RETUNE_C6_0: 1169 case WM8962_DACL_RETUNE_C6_0:
1170 case WM8962_DACL_RETUNE_C7_1: 1170 case WM8962_DACL_RETUNE_C7_1:
1171 case WM8962_DACL_RETUNE_C7_0: 1171 case WM8962_DACL_RETUNE_C7_0:
1172 case WM8962_DACL_RETUNE_C8_1: 1172 case WM8962_DACL_RETUNE_C8_1:
1173 case WM8962_DACL_RETUNE_C8_0: 1173 case WM8962_DACL_RETUNE_C8_0:
1174 case WM8962_DACL_RETUNE_C9_1: 1174 case WM8962_DACL_RETUNE_C9_1:
1175 case WM8962_DACL_RETUNE_C9_0: 1175 case WM8962_DACL_RETUNE_C9_0:
1176 case WM8962_DACL_RETUNE_C10_1: 1176 case WM8962_DACL_RETUNE_C10_1:
1177 case WM8962_DACL_RETUNE_C10_0: 1177 case WM8962_DACL_RETUNE_C10_0:
1178 case WM8962_DACL_RETUNE_C11_1: 1178 case WM8962_DACL_RETUNE_C11_1:
1179 case WM8962_DACL_RETUNE_C11_0: 1179 case WM8962_DACL_RETUNE_C11_0:
1180 case WM8962_DACL_RETUNE_C12_1: 1180 case WM8962_DACL_RETUNE_C12_1:
1181 case WM8962_DACL_RETUNE_C12_0: 1181 case WM8962_DACL_RETUNE_C12_0:
1182 case WM8962_DACL_RETUNE_C13_1: 1182 case WM8962_DACL_RETUNE_C13_1:
1183 case WM8962_DACL_RETUNE_C13_0: 1183 case WM8962_DACL_RETUNE_C13_0:
1184 case WM8962_DACL_RETUNE_C14_1: 1184 case WM8962_DACL_RETUNE_C14_1:
1185 case WM8962_DACL_RETUNE_C14_0: 1185 case WM8962_DACL_RETUNE_C14_0:
1186 case WM8962_DACL_RETUNE_C15_1: 1186 case WM8962_DACL_RETUNE_C15_1:
1187 case WM8962_DACL_RETUNE_C15_0: 1187 case WM8962_DACL_RETUNE_C15_0:
1188 case WM8962_DACL_RETUNE_C16_1: 1188 case WM8962_DACL_RETUNE_C16_1:
1189 case WM8962_DACL_RETUNE_C16_0: 1189 case WM8962_DACL_RETUNE_C16_0:
1190 case WM8962_DACL_RETUNE_C17_1: 1190 case WM8962_DACL_RETUNE_C17_1:
1191 case WM8962_DACL_RETUNE_C17_0: 1191 case WM8962_DACL_RETUNE_C17_0:
1192 case WM8962_DACL_RETUNE_C18_1: 1192 case WM8962_DACL_RETUNE_C18_1:
1193 case WM8962_DACL_RETUNE_C18_0: 1193 case WM8962_DACL_RETUNE_C18_0:
1194 case WM8962_DACL_RETUNE_C19_1: 1194 case WM8962_DACL_RETUNE_C19_1:
1195 case WM8962_DACL_RETUNE_C19_0: 1195 case WM8962_DACL_RETUNE_C19_0:
1196 case WM8962_DACL_RETUNE_C20_1: 1196 case WM8962_DACL_RETUNE_C20_1:
1197 case WM8962_DACL_RETUNE_C20_0: 1197 case WM8962_DACL_RETUNE_C20_0:
1198 case WM8962_DACL_RETUNE_C21_1: 1198 case WM8962_DACL_RETUNE_C21_1:
1199 case WM8962_DACL_RETUNE_C21_0: 1199 case WM8962_DACL_RETUNE_C21_0:
1200 case WM8962_DACL_RETUNE_C22_1: 1200 case WM8962_DACL_RETUNE_C22_1:
1201 case WM8962_DACL_RETUNE_C22_0: 1201 case WM8962_DACL_RETUNE_C22_0:
1202 case WM8962_DACL_RETUNE_C23_1: 1202 case WM8962_DACL_RETUNE_C23_1:
1203 case WM8962_DACL_RETUNE_C23_0: 1203 case WM8962_DACL_RETUNE_C23_0:
1204 case WM8962_DACL_RETUNE_C24_1: 1204 case WM8962_DACL_RETUNE_C24_1:
1205 case WM8962_DACL_RETUNE_C24_0: 1205 case WM8962_DACL_RETUNE_C24_0:
1206 case WM8962_DACL_RETUNE_C25_1: 1206 case WM8962_DACL_RETUNE_C25_1:
1207 case WM8962_DACL_RETUNE_C25_0: 1207 case WM8962_DACL_RETUNE_C25_0:
1208 case WM8962_DACL_RETUNE_C26_1: 1208 case WM8962_DACL_RETUNE_C26_1:
1209 case WM8962_DACL_RETUNE_C26_0: 1209 case WM8962_DACL_RETUNE_C26_0:
1210 case WM8962_DACL_RETUNE_C27_1: 1210 case WM8962_DACL_RETUNE_C27_1:
1211 case WM8962_DACL_RETUNE_C27_0: 1211 case WM8962_DACL_RETUNE_C27_0:
1212 case WM8962_DACL_RETUNE_C28_1: 1212 case WM8962_DACL_RETUNE_C28_1:
1213 case WM8962_DACL_RETUNE_C28_0: 1213 case WM8962_DACL_RETUNE_C28_0:
1214 case WM8962_DACL_RETUNE_C29_1: 1214 case WM8962_DACL_RETUNE_C29_1:
1215 case WM8962_DACL_RETUNE_C29_0: 1215 case WM8962_DACL_RETUNE_C29_0:
1216 case WM8962_DACL_RETUNE_C30_1: 1216 case WM8962_DACL_RETUNE_C30_1:
1217 case WM8962_DACL_RETUNE_C30_0: 1217 case WM8962_DACL_RETUNE_C30_0:
1218 case WM8962_DACL_RETUNE_C31_1: 1218 case WM8962_DACL_RETUNE_C31_1:
1219 case WM8962_DACL_RETUNE_C31_0: 1219 case WM8962_DACL_RETUNE_C31_0:
1220 case WM8962_DACL_RETUNE_C32_1: 1220 case WM8962_DACL_RETUNE_C32_1:
1221 case WM8962_DACL_RETUNE_C32_0: 1221 case WM8962_DACL_RETUNE_C32_0:
1222 case WM8962_RETUNEDAC_PG2_1: 1222 case WM8962_RETUNEDAC_PG2_1:
1223 case WM8962_RETUNEDAC_PG2_0: 1223 case WM8962_RETUNEDAC_PG2_0:
1224 case WM8962_RETUNEDAC_PG_1: 1224 case WM8962_RETUNEDAC_PG_1:
1225 case WM8962_RETUNEDAC_PG_0: 1225 case WM8962_RETUNEDAC_PG_0:
1226 case WM8962_DACR_RETUNE_C1_1: 1226 case WM8962_DACR_RETUNE_C1_1:
1227 case WM8962_DACR_RETUNE_C1_0: 1227 case WM8962_DACR_RETUNE_C1_0:
1228 case WM8962_DACR_RETUNE_C2_1: 1228 case WM8962_DACR_RETUNE_C2_1:
1229 case WM8962_DACR_RETUNE_C2_0: 1229 case WM8962_DACR_RETUNE_C2_0:
1230 case WM8962_DACR_RETUNE_C3_1: 1230 case WM8962_DACR_RETUNE_C3_1:
1231 case WM8962_DACR_RETUNE_C3_0: 1231 case WM8962_DACR_RETUNE_C3_0:
1232 case WM8962_DACR_RETUNE_C4_1: 1232 case WM8962_DACR_RETUNE_C4_1:
1233 case WM8962_DACR_RETUNE_C4_0: 1233 case WM8962_DACR_RETUNE_C4_0:
1234 case WM8962_DACR_RETUNE_C5_1: 1234 case WM8962_DACR_RETUNE_C5_1:
1235 case WM8962_DACR_RETUNE_C5_0: 1235 case WM8962_DACR_RETUNE_C5_0:
1236 case WM8962_DACR_RETUNE_C6_1: 1236 case WM8962_DACR_RETUNE_C6_1:
1237 case WM8962_DACR_RETUNE_C6_0: 1237 case WM8962_DACR_RETUNE_C6_0:
1238 case WM8962_DACR_RETUNE_C7_1: 1238 case WM8962_DACR_RETUNE_C7_1:
1239 case WM8962_DACR_RETUNE_C7_0: 1239 case WM8962_DACR_RETUNE_C7_0:
1240 case WM8962_DACR_RETUNE_C8_1: 1240 case WM8962_DACR_RETUNE_C8_1:
1241 case WM8962_DACR_RETUNE_C8_0: 1241 case WM8962_DACR_RETUNE_C8_0:
1242 case WM8962_DACR_RETUNE_C9_1: 1242 case WM8962_DACR_RETUNE_C9_1:
1243 case WM8962_DACR_RETUNE_C9_0: 1243 case WM8962_DACR_RETUNE_C9_0:
1244 case WM8962_DACR_RETUNE_C10_1: 1244 case WM8962_DACR_RETUNE_C10_1:
1245 case WM8962_DACR_RETUNE_C10_0: 1245 case WM8962_DACR_RETUNE_C10_0:
1246 case WM8962_DACR_RETUNE_C11_1: 1246 case WM8962_DACR_RETUNE_C11_1:
1247 case WM8962_DACR_RETUNE_C11_0: 1247 case WM8962_DACR_RETUNE_C11_0:
1248 case WM8962_DACR_RETUNE_C12_1: 1248 case WM8962_DACR_RETUNE_C12_1:
1249 case WM8962_DACR_RETUNE_C12_0: 1249 case WM8962_DACR_RETUNE_C12_0:
1250 case WM8962_DACR_RETUNE_C13_1: 1250 case WM8962_DACR_RETUNE_C13_1:
1251 case WM8962_DACR_RETUNE_C13_0: 1251 case WM8962_DACR_RETUNE_C13_0:
1252 case WM8962_DACR_RETUNE_C14_1: 1252 case WM8962_DACR_RETUNE_C14_1:
1253 case WM8962_DACR_RETUNE_C14_0: 1253 case WM8962_DACR_RETUNE_C14_0:
1254 case WM8962_DACR_RETUNE_C15_1: 1254 case WM8962_DACR_RETUNE_C15_1:
1255 case WM8962_DACR_RETUNE_C15_0: 1255 case WM8962_DACR_RETUNE_C15_0:
1256 case WM8962_DACR_RETUNE_C16_1: 1256 case WM8962_DACR_RETUNE_C16_1:
1257 case WM8962_DACR_RETUNE_C16_0: 1257 case WM8962_DACR_RETUNE_C16_0:
1258 case WM8962_DACR_RETUNE_C17_1: 1258 case WM8962_DACR_RETUNE_C17_1:
1259 case WM8962_DACR_RETUNE_C17_0: 1259 case WM8962_DACR_RETUNE_C17_0:
1260 case WM8962_DACR_RETUNE_C18_1: 1260 case WM8962_DACR_RETUNE_C18_1:
1261 case WM8962_DACR_RETUNE_C18_0: 1261 case WM8962_DACR_RETUNE_C18_0:
1262 case WM8962_DACR_RETUNE_C19_1: 1262 case WM8962_DACR_RETUNE_C19_1:
1263 case WM8962_DACR_RETUNE_C19_0: 1263 case WM8962_DACR_RETUNE_C19_0:
1264 case WM8962_DACR_RETUNE_C20_1: 1264 case WM8962_DACR_RETUNE_C20_1:
1265 case WM8962_DACR_RETUNE_C20_0: 1265 case WM8962_DACR_RETUNE_C20_0:
1266 case WM8962_DACR_RETUNE_C21_1: 1266 case WM8962_DACR_RETUNE_C21_1:
1267 case WM8962_DACR_RETUNE_C21_0: 1267 case WM8962_DACR_RETUNE_C21_0:
1268 case WM8962_DACR_RETUNE_C22_1: 1268 case WM8962_DACR_RETUNE_C22_1:
1269 case WM8962_DACR_RETUNE_C22_0: 1269 case WM8962_DACR_RETUNE_C22_0:
1270 case WM8962_DACR_RETUNE_C23_1: 1270 case WM8962_DACR_RETUNE_C23_1:
1271 case WM8962_DACR_RETUNE_C23_0: 1271 case WM8962_DACR_RETUNE_C23_0:
1272 case WM8962_DACR_RETUNE_C24_1: 1272 case WM8962_DACR_RETUNE_C24_1:
1273 case WM8962_DACR_RETUNE_C24_0: 1273 case WM8962_DACR_RETUNE_C24_0:
1274 case WM8962_DACR_RETUNE_C25_1: 1274 case WM8962_DACR_RETUNE_C25_1:
1275 case WM8962_DACR_RETUNE_C25_0: 1275 case WM8962_DACR_RETUNE_C25_0:
1276 case WM8962_DACR_RETUNE_C26_1: 1276 case WM8962_DACR_RETUNE_C26_1:
1277 case WM8962_DACR_RETUNE_C26_0: 1277 case WM8962_DACR_RETUNE_C26_0:
1278 case WM8962_DACR_RETUNE_C27_1: 1278 case WM8962_DACR_RETUNE_C27_1:
1279 case WM8962_DACR_RETUNE_C27_0: 1279 case WM8962_DACR_RETUNE_C27_0:
1280 case WM8962_DACR_RETUNE_C28_1: 1280 case WM8962_DACR_RETUNE_C28_1:
1281 case WM8962_DACR_RETUNE_C28_0: 1281 case WM8962_DACR_RETUNE_C28_0:
1282 case WM8962_DACR_RETUNE_C29_1: 1282 case WM8962_DACR_RETUNE_C29_1:
1283 case WM8962_DACR_RETUNE_C29_0: 1283 case WM8962_DACR_RETUNE_C29_0:
1284 case WM8962_DACR_RETUNE_C30_1: 1284 case WM8962_DACR_RETUNE_C30_1:
1285 case WM8962_DACR_RETUNE_C30_0: 1285 case WM8962_DACR_RETUNE_C30_0:
1286 case WM8962_DACR_RETUNE_C31_1: 1286 case WM8962_DACR_RETUNE_C31_1:
1287 case WM8962_DACR_RETUNE_C31_0: 1287 case WM8962_DACR_RETUNE_C31_0:
1288 case WM8962_DACR_RETUNE_C32_1: 1288 case WM8962_DACR_RETUNE_C32_1:
1289 case WM8962_DACR_RETUNE_C32_0: 1289 case WM8962_DACR_RETUNE_C32_0:
1290 case WM8962_VSS_XHD2_1: 1290 case WM8962_VSS_XHD2_1:
1291 case WM8962_VSS_XHD2_0: 1291 case WM8962_VSS_XHD2_0:
1292 case WM8962_VSS_XHD3_1: 1292 case WM8962_VSS_XHD3_1:
1293 case WM8962_VSS_XHD3_0: 1293 case WM8962_VSS_XHD3_0:
1294 case WM8962_VSS_XHN1_1: 1294 case WM8962_VSS_XHN1_1:
1295 case WM8962_VSS_XHN1_0: 1295 case WM8962_VSS_XHN1_0:
1296 case WM8962_VSS_XHN2_1: 1296 case WM8962_VSS_XHN2_1:
1297 case WM8962_VSS_XHN2_0: 1297 case WM8962_VSS_XHN2_0:
1298 case WM8962_VSS_XHN3_1: 1298 case WM8962_VSS_XHN3_1:
1299 case WM8962_VSS_XHN3_0: 1299 case WM8962_VSS_XHN3_0:
1300 case WM8962_VSS_XLA_1: 1300 case WM8962_VSS_XLA_1:
1301 case WM8962_VSS_XLA_0: 1301 case WM8962_VSS_XLA_0:
1302 case WM8962_VSS_XLB_1: 1302 case WM8962_VSS_XLB_1:
1303 case WM8962_VSS_XLB_0: 1303 case WM8962_VSS_XLB_0:
1304 case WM8962_VSS_XLG_1: 1304 case WM8962_VSS_XLG_1:
1305 case WM8962_VSS_XLG_0: 1305 case WM8962_VSS_XLG_0:
1306 case WM8962_VSS_PG2_1: 1306 case WM8962_VSS_PG2_1:
1307 case WM8962_VSS_PG2_0: 1307 case WM8962_VSS_PG2_0:
1308 case WM8962_VSS_PG_1: 1308 case WM8962_VSS_PG_1:
1309 case WM8962_VSS_PG_0: 1309 case WM8962_VSS_PG_0:
1310 case WM8962_VSS_XTD1_1: 1310 case WM8962_VSS_XTD1_1:
1311 case WM8962_VSS_XTD1_0: 1311 case WM8962_VSS_XTD1_0:
1312 case WM8962_VSS_XTD2_1: 1312 case WM8962_VSS_XTD2_1:
1313 case WM8962_VSS_XTD2_0: 1313 case WM8962_VSS_XTD2_0:
1314 case WM8962_VSS_XTD3_1: 1314 case WM8962_VSS_XTD3_1:
1315 case WM8962_VSS_XTD3_0: 1315 case WM8962_VSS_XTD3_0:
1316 case WM8962_VSS_XTD4_1: 1316 case WM8962_VSS_XTD4_1:
1317 case WM8962_VSS_XTD4_0: 1317 case WM8962_VSS_XTD4_0:
1318 case WM8962_VSS_XTD5_1: 1318 case WM8962_VSS_XTD5_1:
1319 case WM8962_VSS_XTD5_0: 1319 case WM8962_VSS_XTD5_0:
1320 case WM8962_VSS_XTD6_1: 1320 case WM8962_VSS_XTD6_1:
1321 case WM8962_VSS_XTD6_0: 1321 case WM8962_VSS_XTD6_0:
1322 case WM8962_VSS_XTD7_1: 1322 case WM8962_VSS_XTD7_1:
1323 case WM8962_VSS_XTD7_0: 1323 case WM8962_VSS_XTD7_0:
1324 case WM8962_VSS_XTD8_1: 1324 case WM8962_VSS_XTD8_1:
1325 case WM8962_VSS_XTD8_0: 1325 case WM8962_VSS_XTD8_0:
1326 case WM8962_VSS_XTD9_1: 1326 case WM8962_VSS_XTD9_1:
1327 case WM8962_VSS_XTD9_0: 1327 case WM8962_VSS_XTD9_0:
1328 case WM8962_VSS_XTD10_1: 1328 case WM8962_VSS_XTD10_1:
1329 case WM8962_VSS_XTD10_0: 1329 case WM8962_VSS_XTD10_0:
1330 case WM8962_VSS_XTD11_1: 1330 case WM8962_VSS_XTD11_1:
1331 case WM8962_VSS_XTD11_0: 1331 case WM8962_VSS_XTD11_0:
1332 case WM8962_VSS_XTD12_1: 1332 case WM8962_VSS_XTD12_1:
1333 case WM8962_VSS_XTD12_0: 1333 case WM8962_VSS_XTD12_0:
1334 case WM8962_VSS_XTD13_1: 1334 case WM8962_VSS_XTD13_1:
1335 case WM8962_VSS_XTD13_0: 1335 case WM8962_VSS_XTD13_0:
1336 case WM8962_VSS_XTD14_1: 1336 case WM8962_VSS_XTD14_1:
1337 case WM8962_VSS_XTD14_0: 1337 case WM8962_VSS_XTD14_0:
1338 case WM8962_VSS_XTD15_1: 1338 case WM8962_VSS_XTD15_1:
1339 case WM8962_VSS_XTD15_0: 1339 case WM8962_VSS_XTD15_0:
1340 case WM8962_VSS_XTD16_1: 1340 case WM8962_VSS_XTD16_1:
1341 case WM8962_VSS_XTD16_0: 1341 case WM8962_VSS_XTD16_0:
1342 case WM8962_VSS_XTD17_1: 1342 case WM8962_VSS_XTD17_1:
1343 case WM8962_VSS_XTD17_0: 1343 case WM8962_VSS_XTD17_0:
1344 case WM8962_VSS_XTD18_1: 1344 case WM8962_VSS_XTD18_1:
1345 case WM8962_VSS_XTD18_0: 1345 case WM8962_VSS_XTD18_0:
1346 case WM8962_VSS_XTD19_1: 1346 case WM8962_VSS_XTD19_1:
1347 case WM8962_VSS_XTD19_0: 1347 case WM8962_VSS_XTD19_0:
1348 case WM8962_VSS_XTD20_1: 1348 case WM8962_VSS_XTD20_1:
1349 case WM8962_VSS_XTD20_0: 1349 case WM8962_VSS_XTD20_0:
1350 case WM8962_VSS_XTD21_1: 1350 case WM8962_VSS_XTD21_1:
1351 case WM8962_VSS_XTD21_0: 1351 case WM8962_VSS_XTD21_0:
1352 case WM8962_VSS_XTD22_1: 1352 case WM8962_VSS_XTD22_1:
1353 case WM8962_VSS_XTD22_0: 1353 case WM8962_VSS_XTD22_0:
1354 case WM8962_VSS_XTD23_1: 1354 case WM8962_VSS_XTD23_1:
1355 case WM8962_VSS_XTD23_0: 1355 case WM8962_VSS_XTD23_0:
1356 case WM8962_VSS_XTD24_1: 1356 case WM8962_VSS_XTD24_1:
1357 case WM8962_VSS_XTD24_0: 1357 case WM8962_VSS_XTD24_0:
1358 case WM8962_VSS_XTD25_1: 1358 case WM8962_VSS_XTD25_1:
1359 case WM8962_VSS_XTD25_0: 1359 case WM8962_VSS_XTD25_0:
1360 case WM8962_VSS_XTD26_1: 1360 case WM8962_VSS_XTD26_1:
1361 case WM8962_VSS_XTD26_0: 1361 case WM8962_VSS_XTD26_0:
1362 case WM8962_VSS_XTD27_1: 1362 case WM8962_VSS_XTD27_1:
1363 case WM8962_VSS_XTD27_0: 1363 case WM8962_VSS_XTD27_0:
1364 case WM8962_VSS_XTD28_1: 1364 case WM8962_VSS_XTD28_1:
1365 case WM8962_VSS_XTD28_0: 1365 case WM8962_VSS_XTD28_0:
1366 case WM8962_VSS_XTD29_1: 1366 case WM8962_VSS_XTD29_1:
1367 case WM8962_VSS_XTD29_0: 1367 case WM8962_VSS_XTD29_0:
1368 case WM8962_VSS_XTD30_1: 1368 case WM8962_VSS_XTD30_1:
1369 case WM8962_VSS_XTD30_0: 1369 case WM8962_VSS_XTD30_0:
1370 case WM8962_VSS_XTD31_1: 1370 case WM8962_VSS_XTD31_1:
1371 case WM8962_VSS_XTD31_0: 1371 case WM8962_VSS_XTD31_0:
1372 case WM8962_VSS_XTD32_1: 1372 case WM8962_VSS_XTD32_1:
1373 case WM8962_VSS_XTD32_0: 1373 case WM8962_VSS_XTD32_0:
1374 case WM8962_VSS_XTS1_1: 1374 case WM8962_VSS_XTS1_1:
1375 case WM8962_VSS_XTS1_0: 1375 case WM8962_VSS_XTS1_0:
1376 case WM8962_VSS_XTS2_1: 1376 case WM8962_VSS_XTS2_1:
1377 case WM8962_VSS_XTS2_0: 1377 case WM8962_VSS_XTS2_0:
1378 case WM8962_VSS_XTS3_1: 1378 case WM8962_VSS_XTS3_1:
1379 case WM8962_VSS_XTS3_0: 1379 case WM8962_VSS_XTS3_0:
1380 case WM8962_VSS_XTS4_1: 1380 case WM8962_VSS_XTS4_1:
1381 case WM8962_VSS_XTS4_0: 1381 case WM8962_VSS_XTS4_0:
1382 case WM8962_VSS_XTS5_1: 1382 case WM8962_VSS_XTS5_1:
1383 case WM8962_VSS_XTS5_0: 1383 case WM8962_VSS_XTS5_0:
1384 case WM8962_VSS_XTS6_1: 1384 case WM8962_VSS_XTS6_1:
1385 case WM8962_VSS_XTS6_0: 1385 case WM8962_VSS_XTS6_0:
1386 case WM8962_VSS_XTS7_1: 1386 case WM8962_VSS_XTS7_1:
1387 case WM8962_VSS_XTS7_0: 1387 case WM8962_VSS_XTS7_0:
1388 case WM8962_VSS_XTS8_1: 1388 case WM8962_VSS_XTS8_1:
1389 case WM8962_VSS_XTS8_0: 1389 case WM8962_VSS_XTS8_0:
1390 case WM8962_VSS_XTS9_1: 1390 case WM8962_VSS_XTS9_1:
1391 case WM8962_VSS_XTS9_0: 1391 case WM8962_VSS_XTS9_0:
1392 case WM8962_VSS_XTS10_1: 1392 case WM8962_VSS_XTS10_1:
1393 case WM8962_VSS_XTS10_0: 1393 case WM8962_VSS_XTS10_0:
1394 case WM8962_VSS_XTS11_1: 1394 case WM8962_VSS_XTS11_1:
1395 case WM8962_VSS_XTS11_0: 1395 case WM8962_VSS_XTS11_0:
1396 case WM8962_VSS_XTS12_1: 1396 case WM8962_VSS_XTS12_1:
1397 case WM8962_VSS_XTS12_0: 1397 case WM8962_VSS_XTS12_0:
1398 case WM8962_VSS_XTS13_1: 1398 case WM8962_VSS_XTS13_1:
1399 case WM8962_VSS_XTS13_0: 1399 case WM8962_VSS_XTS13_0:
1400 case WM8962_VSS_XTS14_1: 1400 case WM8962_VSS_XTS14_1:
1401 case WM8962_VSS_XTS14_0: 1401 case WM8962_VSS_XTS14_0:
1402 case WM8962_VSS_XTS15_1: 1402 case WM8962_VSS_XTS15_1:
1403 case WM8962_VSS_XTS15_0: 1403 case WM8962_VSS_XTS15_0:
1404 case WM8962_VSS_XTS16_1: 1404 case WM8962_VSS_XTS16_1:
1405 case WM8962_VSS_XTS16_0: 1405 case WM8962_VSS_XTS16_0:
1406 case WM8962_VSS_XTS17_1: 1406 case WM8962_VSS_XTS17_1:
1407 case WM8962_VSS_XTS17_0: 1407 case WM8962_VSS_XTS17_0:
1408 case WM8962_VSS_XTS18_1: 1408 case WM8962_VSS_XTS18_1:
1409 case WM8962_VSS_XTS18_0: 1409 case WM8962_VSS_XTS18_0:
1410 case WM8962_VSS_XTS19_1: 1410 case WM8962_VSS_XTS19_1:
1411 case WM8962_VSS_XTS19_0: 1411 case WM8962_VSS_XTS19_0:
1412 case WM8962_VSS_XTS20_1: 1412 case WM8962_VSS_XTS20_1:
1413 case WM8962_VSS_XTS20_0: 1413 case WM8962_VSS_XTS20_0:
1414 case WM8962_VSS_XTS21_1: 1414 case WM8962_VSS_XTS21_1:
1415 case WM8962_VSS_XTS21_0: 1415 case WM8962_VSS_XTS21_0:
1416 case WM8962_VSS_XTS22_1: 1416 case WM8962_VSS_XTS22_1:
1417 case WM8962_VSS_XTS22_0: 1417 case WM8962_VSS_XTS22_0:
1418 case WM8962_VSS_XTS23_1: 1418 case WM8962_VSS_XTS23_1:
1419 case WM8962_VSS_XTS23_0: 1419 case WM8962_VSS_XTS23_0:
1420 case WM8962_VSS_XTS24_1: 1420 case WM8962_VSS_XTS24_1:
1421 case WM8962_VSS_XTS24_0: 1421 case WM8962_VSS_XTS24_0:
1422 case WM8962_VSS_XTS25_1: 1422 case WM8962_VSS_XTS25_1:
1423 case WM8962_VSS_XTS25_0: 1423 case WM8962_VSS_XTS25_0:
1424 case WM8962_VSS_XTS26_1: 1424 case WM8962_VSS_XTS26_1:
1425 case WM8962_VSS_XTS26_0: 1425 case WM8962_VSS_XTS26_0:
1426 case WM8962_VSS_XTS27_1: 1426 case WM8962_VSS_XTS27_1:
1427 case WM8962_VSS_XTS27_0: 1427 case WM8962_VSS_XTS27_0:
1428 case WM8962_VSS_XTS28_1: 1428 case WM8962_VSS_XTS28_1:
1429 case WM8962_VSS_XTS28_0: 1429 case WM8962_VSS_XTS28_0:
1430 case WM8962_VSS_XTS29_1: 1430 case WM8962_VSS_XTS29_1:
1431 case WM8962_VSS_XTS29_0: 1431 case WM8962_VSS_XTS29_0:
1432 case WM8962_VSS_XTS30_1: 1432 case WM8962_VSS_XTS30_1:
1433 case WM8962_VSS_XTS30_0: 1433 case WM8962_VSS_XTS30_0:
1434 case WM8962_VSS_XTS31_1: 1434 case WM8962_VSS_XTS31_1:
1435 case WM8962_VSS_XTS31_0: 1435 case WM8962_VSS_XTS31_0:
1436 case WM8962_VSS_XTS32_1: 1436 case WM8962_VSS_XTS32_1:
1437 case WM8962_VSS_XTS32_0: 1437 case WM8962_VSS_XTS32_0:
1438 return true; 1438 return true;
1439 default: 1439 default:
1440 return false; 1440 return false;
1441 } 1441 }
1442 } 1442 }
1443 1443
1444 static int wm8962_reset(struct wm8962_priv *wm8962) 1444 static int wm8962_reset(struct wm8962_priv *wm8962)
1445 { 1445 {
1446 int ret; 1446 int ret;
1447 1447
1448 ret = regmap_write(wm8962->regmap, WM8962_SOFTWARE_RESET, 0x6243); 1448 ret = regmap_write(wm8962->regmap, WM8962_SOFTWARE_RESET, 0x6243);
1449 if (ret != 0) 1449 if (ret != 0)
1450 return ret; 1450 return ret;
1451 1451
1452 return regmap_write(wm8962->regmap, WM8962_PLL_SOFTWARE_RESET, 0); 1452 return regmap_write(wm8962->regmap, WM8962_PLL_SOFTWARE_RESET, 0);
1453 } 1453 }
1454 1454
1455 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0); 1455 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
1456 static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0); 1456 static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0);
1457 static const unsigned int mixinpga_tlv[] = { 1457 static const unsigned int mixinpga_tlv[] = {
1458 TLV_DB_RANGE_HEAD(5), 1458 TLV_DB_RANGE_HEAD(5),
1459 0, 1, TLV_DB_SCALE_ITEM(0, 600, 0), 1459 0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
1460 2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0), 1460 2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0),
1461 3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0), 1461 3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0),
1462 5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0), 1462 5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0),
1463 6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0), 1463 6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0),
1464 }; 1464 };
1465 static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1); 1465 static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1);
1466 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 1466 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
1467 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0); 1467 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
1468 static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0); 1468 static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0);
1469 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0); 1469 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
1470 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1); 1470 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
1471 static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0); 1471 static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0);
1472 static const unsigned int classd_tlv[] = { 1472 static const unsigned int classd_tlv[] = {
1473 TLV_DB_RANGE_HEAD(2), 1473 TLV_DB_RANGE_HEAD(2),
1474 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0), 1474 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
1475 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0), 1475 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0),
1476 }; 1476 };
1477 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 1477 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1478 1478
1479 static int wm8962_dsp2_write_config(struct snd_soc_codec *codec) 1479 static int wm8962_dsp2_write_config(struct snd_soc_codec *codec)
1480 { 1480 {
1481 return regcache_sync_region(codec->control_data, 1481 return regcache_sync_region(codec->control_data,
1482 WM8962_HDBASS_AI_1, WM8962_MAX_REGISTER); 1482 WM8962_HDBASS_AI_1, WM8962_MAX_REGISTER);
1483 } 1483 }
1484 1484
1485 static int wm8962_dsp2_set_enable(struct snd_soc_codec *codec, u16 val) 1485 static int wm8962_dsp2_set_enable(struct snd_soc_codec *codec, u16 val)
1486 { 1486 {
1487 u16 adcl = snd_soc_read(codec, WM8962_LEFT_ADC_VOLUME); 1487 u16 adcl = snd_soc_read(codec, WM8962_LEFT_ADC_VOLUME);
1488 u16 adcr = snd_soc_read(codec, WM8962_RIGHT_ADC_VOLUME); 1488 u16 adcr = snd_soc_read(codec, WM8962_RIGHT_ADC_VOLUME);
1489 u16 dac = snd_soc_read(codec, WM8962_ADC_DAC_CONTROL_1); 1489 u16 dac = snd_soc_read(codec, WM8962_ADC_DAC_CONTROL_1);
1490 1490
1491 /* Mute the ADCs and DACs */ 1491 /* Mute the ADCs and DACs */
1492 snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, 0); 1492 snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, 0);
1493 snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, WM8962_ADC_VU); 1493 snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, WM8962_ADC_VU);
1494 snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1, 1494 snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
1495 WM8962_DAC_MUTE, WM8962_DAC_MUTE); 1495 WM8962_DAC_MUTE, WM8962_DAC_MUTE);
1496 1496
1497 snd_soc_write(codec, WM8962_SOUNDSTAGE_ENABLES_0, val); 1497 snd_soc_write(codec, WM8962_SOUNDSTAGE_ENABLES_0, val);
1498 1498
1499 /* Restore the ADCs and DACs */ 1499 /* Restore the ADCs and DACs */
1500 snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, adcl); 1500 snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, adcl);
1501 snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, adcr); 1501 snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, adcr);
1502 snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1, 1502 snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
1503 WM8962_DAC_MUTE, dac); 1503 WM8962_DAC_MUTE, dac);
1504 1504
1505 return 0; 1505 return 0;
1506 } 1506 }
1507 1507
1508 static int wm8962_dsp2_start(struct snd_soc_codec *codec) 1508 static int wm8962_dsp2_start(struct snd_soc_codec *codec)
1509 { 1509 {
1510 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 1510 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1511 1511
1512 wm8962_dsp2_write_config(codec); 1512 wm8962_dsp2_write_config(codec);
1513 1513
1514 snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_RUNR); 1514 snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_RUNR);
1515 1515
1516 wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena); 1516 wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena);
1517 1517
1518 return 0; 1518 return 0;
1519 } 1519 }
1520 1520
1521 static int wm8962_dsp2_stop(struct snd_soc_codec *codec) 1521 static int wm8962_dsp2_stop(struct snd_soc_codec *codec)
1522 { 1522 {
1523 wm8962_dsp2_set_enable(codec, 0); 1523 wm8962_dsp2_set_enable(codec, 0);
1524 1524
1525 snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_STOP); 1525 snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_STOP);
1526 1526
1527 return 0; 1527 return 0;
1528 } 1528 }
1529 1529
1530 #define WM8962_DSP2_ENABLE(xname, xshift) \ 1530 #define WM8962_DSP2_ENABLE(xname, xshift) \
1531 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1531 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1532 .info = wm8962_dsp2_ena_info, \ 1532 .info = wm8962_dsp2_ena_info, \
1533 .get = wm8962_dsp2_ena_get, .put = wm8962_dsp2_ena_put, \ 1533 .get = wm8962_dsp2_ena_get, .put = wm8962_dsp2_ena_put, \
1534 .private_value = xshift } 1534 .private_value = xshift }
1535 1535
1536 static int wm8962_dsp2_ena_info(struct snd_kcontrol *kcontrol, 1536 static int wm8962_dsp2_ena_info(struct snd_kcontrol *kcontrol,
1537 struct snd_ctl_elem_info *uinfo) 1537 struct snd_ctl_elem_info *uinfo)
1538 { 1538 {
1539 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 1539 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1540 1540
1541 uinfo->count = 1; 1541 uinfo->count = 1;
1542 uinfo->value.integer.min = 0; 1542 uinfo->value.integer.min = 0;
1543 uinfo->value.integer.max = 1; 1543 uinfo->value.integer.max = 1;
1544 1544
1545 return 0; 1545 return 0;
1546 } 1546 }
1547 1547
1548 static int wm8962_dsp2_ena_get(struct snd_kcontrol *kcontrol, 1548 static int wm8962_dsp2_ena_get(struct snd_kcontrol *kcontrol,
1549 struct snd_ctl_elem_value *ucontrol) 1549 struct snd_ctl_elem_value *ucontrol)
1550 { 1550 {
1551 int shift = kcontrol->private_value; 1551 int shift = kcontrol->private_value;
1552 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1552 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1553 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 1553 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1554 1554
1555 ucontrol->value.integer.value[0] = !!(wm8962->dsp2_ena & 1 << shift); 1555 ucontrol->value.integer.value[0] = !!(wm8962->dsp2_ena & 1 << shift);
1556 1556
1557 return 0; 1557 return 0;
1558 } 1558 }
1559 1559
1560 static int wm8962_dsp2_ena_put(struct snd_kcontrol *kcontrol, 1560 static int wm8962_dsp2_ena_put(struct snd_kcontrol *kcontrol,
1561 struct snd_ctl_elem_value *ucontrol) 1561 struct snd_ctl_elem_value *ucontrol)
1562 { 1562 {
1563 int shift = kcontrol->private_value; 1563 int shift = kcontrol->private_value;
1564 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1564 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1565 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 1565 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1566 int old = wm8962->dsp2_ena; 1566 int old = wm8962->dsp2_ena;
1567 int ret = 0; 1567 int ret = 0;
1568 int dsp2_running = snd_soc_read(codec, WM8962_DSP2_POWER_MANAGEMENT) & 1568 int dsp2_running = snd_soc_read(codec, WM8962_DSP2_POWER_MANAGEMENT) &
1569 WM8962_DSP2_ENA; 1569 WM8962_DSP2_ENA;
1570 1570
1571 mutex_lock(&codec->mutex); 1571 mutex_lock(&codec->mutex);
1572 1572
1573 if (ucontrol->value.integer.value[0]) 1573 if (ucontrol->value.integer.value[0])
1574 wm8962->dsp2_ena |= 1 << shift; 1574 wm8962->dsp2_ena |= 1 << shift;
1575 else 1575 else
1576 wm8962->dsp2_ena &= ~(1 << shift); 1576 wm8962->dsp2_ena &= ~(1 << shift);
1577 1577
1578 if (wm8962->dsp2_ena == old) 1578 if (wm8962->dsp2_ena == old)
1579 goto out; 1579 goto out;
1580 1580
1581 ret = 1; 1581 ret = 1;
1582 1582
1583 if (dsp2_running) { 1583 if (dsp2_running) {
1584 if (wm8962->dsp2_ena) 1584 if (wm8962->dsp2_ena)
1585 wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena); 1585 wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena);
1586 else 1586 else
1587 wm8962_dsp2_stop(codec); 1587 wm8962_dsp2_stop(codec);
1588 } 1588 }
1589 1589
1590 out: 1590 out:
1591 mutex_unlock(&codec->mutex); 1591 mutex_unlock(&codec->mutex);
1592 1592
1593 return ret; 1593 return ret;
1594 } 1594 }
1595 1595
1596 /* The VU bits for the headphones are in a different register to the mute 1596 /* The VU bits for the headphones are in a different register to the mute
1597 * bits and only take effect on the PGA if it is actually powered. 1597 * bits and only take effect on the PGA if it is actually powered.
1598 */ 1598 */
1599 static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol, 1599 static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
1600 struct snd_ctl_elem_value *ucontrol) 1600 struct snd_ctl_elem_value *ucontrol)
1601 { 1601 {
1602 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1602 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1603 u16 *reg_cache = codec->reg_cache; 1603 u16 *reg_cache = codec->reg_cache;
1604 int ret; 1604 int ret;
1605 1605
1606 /* Apply the update (if any) */ 1606 /* Apply the update (if any) */
1607 ret = snd_soc_put_volsw(kcontrol, ucontrol); 1607 ret = snd_soc_put_volsw(kcontrol, ucontrol);
1608 if (ret == 0) 1608 if (ret == 0)
1609 return 0; 1609 return 0;
1610 1610
1611 /* If the left PGA is enabled hit that VU bit... */ 1611 /* If the left PGA is enabled hit that VU bit... */
1612 if (snd_soc_read(codec, WM8962_PWR_MGMT_2) & WM8962_HPOUTL_PGA_ENA) 1612 if (snd_soc_read(codec, WM8962_PWR_MGMT_2) & WM8962_HPOUTL_PGA_ENA)
1613 return snd_soc_write(codec, WM8962_HPOUTL_VOLUME, 1613 return snd_soc_write(codec, WM8962_HPOUTL_VOLUME,
1614 reg_cache[WM8962_HPOUTL_VOLUME]); 1614 reg_cache[WM8962_HPOUTL_VOLUME]);
1615 1615
1616 /* ...otherwise the right. The VU is stereo. */ 1616 /* ...otherwise the right. The VU is stereo. */
1617 if (snd_soc_read(codec, WM8962_PWR_MGMT_2) & WM8962_HPOUTR_PGA_ENA) 1617 if (snd_soc_read(codec, WM8962_PWR_MGMT_2) & WM8962_HPOUTR_PGA_ENA)
1618 return snd_soc_write(codec, WM8962_HPOUTR_VOLUME, 1618 return snd_soc_write(codec, WM8962_HPOUTR_VOLUME,
1619 reg_cache[WM8962_HPOUTR_VOLUME]); 1619 reg_cache[WM8962_HPOUTR_VOLUME]);
1620 1620
1621 return 0; 1621 return 0;
1622 } 1622 }
1623 1623
1624 /* The VU bits for the speakers are in a different register to the mute 1624 /* The VU bits for the speakers are in a different register to the mute
1625 * bits and only take effect on the PGA if it is actually powered. 1625 * bits and only take effect on the PGA if it is actually powered.
1626 */ 1626 */
1627 static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol, 1627 static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
1628 struct snd_ctl_elem_value *ucontrol) 1628 struct snd_ctl_elem_value *ucontrol)
1629 { 1629 {
1630 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1630 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1631 int ret; 1631 int ret;
1632 1632
1633 /* Apply the update (if any) */ 1633 /* Apply the update (if any) */
1634 ret = snd_soc_put_volsw(kcontrol, ucontrol); 1634 ret = snd_soc_put_volsw(kcontrol, ucontrol);
1635 if (ret == 0) 1635 if (ret == 0)
1636 return 0; 1636 return 0;
1637 1637
1638 /* If the left PGA is enabled hit that VU bit... */ 1638 /* If the left PGA is enabled hit that VU bit... */
1639 ret = snd_soc_read(codec, WM8962_PWR_MGMT_2); 1639 ret = snd_soc_read(codec, WM8962_PWR_MGMT_2);
1640 if (ret & WM8962_SPKOUTL_PGA_ENA) { 1640 if (ret & WM8962_SPKOUTL_PGA_ENA) {
1641 snd_soc_write(codec, WM8962_SPKOUTL_VOLUME, 1641 snd_soc_write(codec, WM8962_SPKOUTL_VOLUME,
1642 snd_soc_read(codec, WM8962_SPKOUTL_VOLUME)); 1642 snd_soc_read(codec, WM8962_SPKOUTL_VOLUME));
1643 return 1; 1643 return 1;
1644 } 1644 }
1645 1645
1646 /* ...otherwise the right. The VU is stereo. */ 1646 /* ...otherwise the right. The VU is stereo. */
1647 if (ret & WM8962_SPKOUTR_PGA_ENA) 1647 if (ret & WM8962_SPKOUTR_PGA_ENA)
1648 snd_soc_write(codec, WM8962_SPKOUTR_VOLUME, 1648 snd_soc_write(codec, WM8962_SPKOUTR_VOLUME,
1649 snd_soc_read(codec, WM8962_SPKOUTR_VOLUME)); 1649 snd_soc_read(codec, WM8962_SPKOUTR_VOLUME));
1650 1650
1651 return 1; 1651 return 1;
1652 } 1652 }
1653 1653
1654 static const char *cap_hpf_mode_text[] = { 1654 static const char *cap_hpf_mode_text[] = {
1655 "Hi-fi", "Application" 1655 "Hi-fi", "Application"
1656 }; 1656 };
1657 1657
1658 static const struct soc_enum cap_hpf_mode = 1658 static const struct soc_enum cap_hpf_mode =
1659 SOC_ENUM_SINGLE(WM8962_ADC_DAC_CONTROL_2, 10, 2, cap_hpf_mode_text); 1659 SOC_ENUM_SINGLE(WM8962_ADC_DAC_CONTROL_2, 10, 2, cap_hpf_mode_text);
1660 1660
1661 1661
1662 static const char *cap_lhpf_mode_text[] = { 1662 static const char *cap_lhpf_mode_text[] = {
1663 "LPF", "HPF" 1663 "LPF", "HPF"
1664 }; 1664 };
1665 1665
1666 static const struct soc_enum cap_lhpf_mode = 1666 static const struct soc_enum cap_lhpf_mode =
1667 SOC_ENUM_SINGLE(WM8962_LHPF1, 1, 2, cap_lhpf_mode_text); 1667 SOC_ENUM_SINGLE(WM8962_LHPF1, 1, 2, cap_lhpf_mode_text);
1668 1668
1669 static const struct snd_kcontrol_new wm8962_snd_controls[] = { 1669 static const struct snd_kcontrol_new wm8962_snd_controls[] = {
1670 SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1), 1670 SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1),
1671 1671
1672 SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0, 1672 SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0,
1673 mixin_tlv), 1673 mixin_tlv),
1674 SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0, 1674 SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0,
1675 mixinpga_tlv), 1675 mixinpga_tlv),
1676 SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0, 1676 SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0,
1677 mixin_tlv), 1677 mixin_tlv),
1678 1678
1679 SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0, 1679 SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0,
1680 mixin_tlv), 1680 mixin_tlv),
1681 SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0, 1681 SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0,
1682 mixinpga_tlv), 1682 mixinpga_tlv),
1683 SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0, 1683 SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0,
1684 mixin_tlv), 1684 mixin_tlv),
1685 1685
1686 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME, 1686 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME,
1687 WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv), 1687 WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv),
1688 SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME, 1688 SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME,
1689 WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv), 1689 WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv),
1690 SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME, 1690 SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME,
1691 WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1), 1691 WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1),
1692 SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME, 1692 SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME,
1693 WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1), 1693 WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1),
1694 SOC_SINGLE("Capture HPF Switch", WM8962_ADC_DAC_CONTROL_1, 0, 1, 1), 1694 SOC_SINGLE("Capture HPF Switch", WM8962_ADC_DAC_CONTROL_1, 0, 1, 1),
1695 SOC_ENUM("Capture HPF Mode", cap_hpf_mode), 1695 SOC_ENUM("Capture HPF Mode", cap_hpf_mode),
1696 SOC_SINGLE("Capture HPF Cutoff", WM8962_ADC_DAC_CONTROL_2, 7, 7, 0), 1696 SOC_SINGLE("Capture HPF Cutoff", WM8962_ADC_DAC_CONTROL_2, 7, 7, 0),
1697 SOC_SINGLE("Capture LHPF Switch", WM8962_LHPF1, 0, 1, 0), 1697 SOC_SINGLE("Capture LHPF Switch", WM8962_LHPF1, 0, 1, 0),
1698 SOC_ENUM("Capture LHPF Mode", cap_lhpf_mode), 1698 SOC_ENUM("Capture LHPF Mode", cap_lhpf_mode),
1699 1699
1700 SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1, 1700 SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1,
1701 WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv), 1701 WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv),
1702 1702
1703 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME, 1703 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME,
1704 WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv), 1704 WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv),
1705 SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0), 1705 SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0),
1706 SOC_SINGLE("DAC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 5, 1, 0), 1706 SOC_SINGLE("DAC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 5, 1, 0),
1707 SOC_SINGLE("ADC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 8, 1, 0), 1707 SOC_SINGLE("ADC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 8, 1, 0),
1708 1708
1709 SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1, 1709 SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1,
1710 5, 1, 0), 1710 5, 1, 0),
1711 1711
1712 SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv), 1712 SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv),
1713 1713
1714 SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME, 1714 SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME,
1715 WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv), 1715 WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv),
1716 SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1, 1716 SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1,
1717 snd_soc_get_volsw, wm8962_put_hp_sw), 1717 snd_soc_get_volsw, wm8962_put_hp_sw),
1718 SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME, 1718 SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME,
1719 7, 1, 0), 1719 7, 1, 0),
1720 SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0, 1720 SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0,
1721 hp_tlv), 1721 hp_tlv),
1722 1722
1723 SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3, 1723 SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3,
1724 WM8962_HEADPHONE_MIXER_4, 8, 1, 1), 1724 WM8962_HEADPHONE_MIXER_4, 8, 1, 1),
1725 1725
1726 SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3, 1726 SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3,
1727 3, 7, 0, bypass_tlv), 1727 3, 7, 0, bypass_tlv),
1728 SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3, 1728 SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3,
1729 0, 7, 0, bypass_tlv), 1729 0, 7, 0, bypass_tlv),
1730 SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3, 1730 SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3,
1731 7, 1, 1, inmix_tlv), 1731 7, 1, 1, inmix_tlv),
1732 SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3, 1732 SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3,
1733 6, 1, 1, inmix_tlv), 1733 6, 1, 1, inmix_tlv),
1734 1734
1735 SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4, 1735 SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4,
1736 3, 7, 0, bypass_tlv), 1736 3, 7, 0, bypass_tlv),
1737 SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4, 1737 SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4,
1738 0, 7, 0, bypass_tlv), 1738 0, 7, 0, bypass_tlv),
1739 SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4, 1739 SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4,
1740 7, 1, 1, inmix_tlv), 1740 7, 1, 1, inmix_tlv),
1741 SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4, 1741 SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4,
1742 6, 1, 1, inmix_tlv), 1742 6, 1, 1, inmix_tlv),
1743 1743
1744 SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0, 1744 SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0,
1745 classd_tlv), 1745 classd_tlv),
1746 1746
1747 SOC_SINGLE("EQ Switch", WM8962_EQ1, WM8962_EQ_ENA_SHIFT, 1, 0), 1747 SOC_SINGLE("EQ Switch", WM8962_EQ1, WM8962_EQ_ENA_SHIFT, 1, 0),
1748 SOC_DOUBLE_R_TLV("EQ1 Volume", WM8962_EQ2, WM8962_EQ22, 1748 SOC_DOUBLE_R_TLV("EQ1 Volume", WM8962_EQ2, WM8962_EQ22,
1749 WM8962_EQL_B1_GAIN_SHIFT, 31, 0, eq_tlv), 1749 WM8962_EQL_B1_GAIN_SHIFT, 31, 0, eq_tlv),
1750 SOC_DOUBLE_R_TLV("EQ2 Volume", WM8962_EQ2, WM8962_EQ22, 1750 SOC_DOUBLE_R_TLV("EQ2 Volume", WM8962_EQ2, WM8962_EQ22,
1751 WM8962_EQL_B2_GAIN_SHIFT, 31, 0, eq_tlv), 1751 WM8962_EQL_B2_GAIN_SHIFT, 31, 0, eq_tlv),
1752 SOC_DOUBLE_R_TLV("EQ3 Volume", WM8962_EQ2, WM8962_EQ22, 1752 SOC_DOUBLE_R_TLV("EQ3 Volume", WM8962_EQ2, WM8962_EQ22,
1753 WM8962_EQL_B3_GAIN_SHIFT, 31, 0, eq_tlv), 1753 WM8962_EQL_B3_GAIN_SHIFT, 31, 0, eq_tlv),
1754 SOC_DOUBLE_R_TLV("EQ4 Volume", WM8962_EQ3, WM8962_EQ23, 1754 SOC_DOUBLE_R_TLV("EQ4 Volume", WM8962_EQ3, WM8962_EQ23,
1755 WM8962_EQL_B4_GAIN_SHIFT, 31, 0, eq_tlv), 1755 WM8962_EQL_B4_GAIN_SHIFT, 31, 0, eq_tlv),
1756 SOC_DOUBLE_R_TLV("EQ5 Volume", WM8962_EQ3, WM8962_EQ23, 1756 SOC_DOUBLE_R_TLV("EQ5 Volume", WM8962_EQ3, WM8962_EQ23,
1757 WM8962_EQL_B5_GAIN_SHIFT, 31, 0, eq_tlv), 1757 WM8962_EQL_B5_GAIN_SHIFT, 31, 0, eq_tlv),
1758 1758
1759 SOC_SINGLE("3D Switch", WM8962_THREED1, 0, 1, 0), 1759 SOC_SINGLE("3D Switch", WM8962_THREED1, 0, 1, 0),
1760 SND_SOC_BYTES_MASK("3D Coefficients", WM8962_THREED1, 4, WM8962_THREED_ENA), 1760 SND_SOC_BYTES_MASK("3D Coefficients", WM8962_THREED1, 4, WM8962_THREED_ENA),
1761 1761
1762 SOC_SINGLE("DF1 Switch", WM8962_DF1, 0, 1, 0), 1762 SOC_SINGLE("DF1 Switch", WM8962_DF1, 0, 1, 0),
1763 SND_SOC_BYTES_MASK("DF1 Coefficients", WM8962_DF1, 7, WM8962_DF1_ENA), 1763 SND_SOC_BYTES_MASK("DF1 Coefficients", WM8962_DF1, 7, WM8962_DF1_ENA),
1764 1764
1765 SOC_SINGLE("DRC Switch", WM8962_DRC_1, 0, 1, 0), 1765 SOC_SINGLE("DRC Switch", WM8962_DRC_1, 0, 1, 0),
1766 SND_SOC_BYTES_MASK("DRC Coefficients", WM8962_DRC_1, 5, WM8962_DRC_ENA), 1766 SND_SOC_BYTES_MASK("DRC Coefficients", WM8962_DRC_1, 5, WM8962_DRC_ENA),
1767 1767
1768 WM8962_DSP2_ENABLE("VSS Switch", WM8962_VSS_ENA_SHIFT), 1768 WM8962_DSP2_ENABLE("VSS Switch", WM8962_VSS_ENA_SHIFT),
1769 SND_SOC_BYTES("VSS Coefficients", WM8962_VSS_XHD2_1, 148), 1769 SND_SOC_BYTES("VSS Coefficients", WM8962_VSS_XHD2_1, 148),
1770 WM8962_DSP2_ENABLE("HPF1 Switch", WM8962_HPF1_ENA_SHIFT), 1770 WM8962_DSP2_ENABLE("HPF1 Switch", WM8962_HPF1_ENA_SHIFT),
1771 WM8962_DSP2_ENABLE("HPF2 Switch", WM8962_HPF2_ENA_SHIFT), 1771 WM8962_DSP2_ENABLE("HPF2 Switch", WM8962_HPF2_ENA_SHIFT),
1772 SND_SOC_BYTES("HPF Coefficients", WM8962_LHPF2, 1), 1772 SND_SOC_BYTES("HPF Coefficients", WM8962_LHPF2, 1),
1773 WM8962_DSP2_ENABLE("HD Bass Switch", WM8962_HDBASS_ENA_SHIFT), 1773 WM8962_DSP2_ENABLE("HD Bass Switch", WM8962_HDBASS_ENA_SHIFT),
1774 SND_SOC_BYTES("HD Bass Coefficients", WM8962_HDBASS_AI_1, 30), 1774 SND_SOC_BYTES("HD Bass Coefficients", WM8962_HDBASS_AI_1, 30),
1775 }; 1775 };
1776 1776
1777 static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = { 1777 static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = {
1778 SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv), 1778 SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv),
1779 SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1, 1779 SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1,
1780 snd_soc_get_volsw, wm8962_put_spk_sw), 1780 snd_soc_get_volsw, wm8962_put_spk_sw),
1781 SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0), 1781 SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0),
1782 1782
1783 SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1), 1783 SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1),
1784 SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3, 1784 SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1785 3, 7, 0, bypass_tlv), 1785 3, 7, 0, bypass_tlv),
1786 SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3, 1786 SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1787 0, 7, 0, bypass_tlv), 1787 0, 7, 0, bypass_tlv),
1788 SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3, 1788 SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1789 7, 1, 1, inmix_tlv), 1789 7, 1, 1, inmix_tlv),
1790 SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3, 1790 SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1791 6, 1, 1, inmix_tlv), 1791 6, 1, 1, inmix_tlv),
1792 SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5, 1792 SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1793 7, 1, 0, inmix_tlv), 1793 7, 1, 0, inmix_tlv),
1794 SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5, 1794 SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1795 6, 1, 0, inmix_tlv), 1795 6, 1, 0, inmix_tlv),
1796 }; 1796 };
1797 1797
1798 static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = { 1798 static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = {
1799 SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 1799 SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME,
1800 WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv), 1800 WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv),
1801 SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1, 1801 SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1,
1802 snd_soc_get_volsw, wm8962_put_spk_sw), 1802 snd_soc_get_volsw, wm8962_put_spk_sw),
1803 SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME, 1803 SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME,
1804 7, 1, 0), 1804 7, 1, 0),
1805 1805
1806 SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 1806 SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3,
1807 WM8962_SPEAKER_MIXER_4, 8, 1, 1), 1807 WM8962_SPEAKER_MIXER_4, 8, 1, 1),
1808 1808
1809 SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3, 1809 SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1810 3, 7, 0, bypass_tlv), 1810 3, 7, 0, bypass_tlv),
1811 SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3, 1811 SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1812 0, 7, 0, bypass_tlv), 1812 0, 7, 0, bypass_tlv),
1813 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3, 1813 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1814 7, 1, 1, inmix_tlv), 1814 7, 1, 1, inmix_tlv),
1815 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3, 1815 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1816 6, 1, 1, inmix_tlv), 1816 6, 1, 1, inmix_tlv),
1817 SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5, 1817 SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1818 7, 1, 0, inmix_tlv), 1818 7, 1, 0, inmix_tlv),
1819 SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5, 1819 SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1820 6, 1, 0, inmix_tlv), 1820 6, 1, 0, inmix_tlv),
1821 1821
1822 SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4, 1822 SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4,
1823 3, 7, 0, bypass_tlv), 1823 3, 7, 0, bypass_tlv),
1824 SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4, 1824 SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4,
1825 0, 7, 0, bypass_tlv), 1825 0, 7, 0, bypass_tlv),
1826 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4, 1826 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4,
1827 7, 1, 1, inmix_tlv), 1827 7, 1, 1, inmix_tlv),
1828 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4, 1828 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4,
1829 6, 1, 1, inmix_tlv), 1829 6, 1, 1, inmix_tlv),
1830 SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5, 1830 SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1831 5, 1, 0, inmix_tlv), 1831 5, 1, 0, inmix_tlv),
1832 SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5, 1832 SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1833 4, 1, 0, inmix_tlv), 1833 4, 1, 0, inmix_tlv),
1834 }; 1834 };
1835 1835
1836 static int cp_event(struct snd_soc_dapm_widget *w, 1836 static int cp_event(struct snd_soc_dapm_widget *w,
1837 struct snd_kcontrol *kcontrol, int event) 1837 struct snd_kcontrol *kcontrol, int event)
1838 { 1838 {
1839 switch (event) { 1839 switch (event) {
1840 case SND_SOC_DAPM_POST_PMU: 1840 case SND_SOC_DAPM_POST_PMU:
1841 msleep(5); 1841 msleep(5);
1842 break; 1842 break;
1843 1843
1844 default: 1844 default:
1845 BUG(); 1845 BUG();
1846 return -EINVAL; 1846 return -EINVAL;
1847 } 1847 }
1848 1848
1849 return 0; 1849 return 0;
1850 } 1850 }
1851 1851
1852 static int hp_event(struct snd_soc_dapm_widget *w, 1852 static int hp_event(struct snd_soc_dapm_widget *w,
1853 struct snd_kcontrol *kcontrol, int event) 1853 struct snd_kcontrol *kcontrol, int event)
1854 { 1854 {
1855 struct snd_soc_codec *codec = w->codec; 1855 struct snd_soc_codec *codec = w->codec;
1856 int timeout; 1856 int timeout;
1857 int reg; 1857 int reg;
1858 int expected = (WM8962_DCS_STARTUP_DONE_HP1L | 1858 int expected = (WM8962_DCS_STARTUP_DONE_HP1L |
1859 WM8962_DCS_STARTUP_DONE_HP1R); 1859 WM8962_DCS_STARTUP_DONE_HP1R);
1860 1860
1861 switch (event) { 1861 switch (event) {
1862 case SND_SOC_DAPM_POST_PMU: 1862 case SND_SOC_DAPM_POST_PMU:
1863 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, 1863 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1864 WM8962_HP1L_ENA | WM8962_HP1R_ENA, 1864 WM8962_HP1L_ENA | WM8962_HP1R_ENA,
1865 WM8962_HP1L_ENA | WM8962_HP1R_ENA); 1865 WM8962_HP1L_ENA | WM8962_HP1R_ENA);
1866 udelay(20); 1866 udelay(20);
1867 1867
1868 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, 1868 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1869 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY, 1869 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY,
1870 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY); 1870 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY);
1871 1871
1872 /* Start the DC servo */ 1872 /* Start the DC servo */
1873 snd_soc_update_bits(codec, WM8962_DC_SERVO_1, 1873 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
1874 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA | 1874 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1875 WM8962_HP1L_DCS_STARTUP | 1875 WM8962_HP1L_DCS_STARTUP |
1876 WM8962_HP1R_DCS_STARTUP, 1876 WM8962_HP1R_DCS_STARTUP,
1877 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA | 1877 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1878 WM8962_HP1L_DCS_STARTUP | 1878 WM8962_HP1L_DCS_STARTUP |
1879 WM8962_HP1R_DCS_STARTUP); 1879 WM8962_HP1R_DCS_STARTUP);
1880 1880
1881 /* Wait for it to complete, should be well under 100ms */ 1881 /* Wait for it to complete, should be well under 100ms */
1882 timeout = 0; 1882 timeout = 0;
1883 do { 1883 do {
1884 msleep(1); 1884 msleep(1);
1885 reg = snd_soc_read(codec, WM8962_DC_SERVO_6); 1885 reg = snd_soc_read(codec, WM8962_DC_SERVO_6);
1886 if (reg < 0) { 1886 if (reg < 0) {
1887 dev_err(codec->dev, 1887 dev_err(codec->dev,
1888 "Failed to read DCS status: %d\n", 1888 "Failed to read DCS status: %d\n",
1889 reg); 1889 reg);
1890 continue; 1890 continue;
1891 } 1891 }
1892 dev_dbg(codec->dev, "DCS status: %x\n", reg); 1892 dev_dbg(codec->dev, "DCS status: %x\n", reg);
1893 } while (++timeout < 200 && (reg & expected) != expected); 1893 } while (++timeout < 200 && (reg & expected) != expected);
1894 1894
1895 if ((reg & expected) != expected) 1895 if ((reg & expected) != expected)
1896 dev_err(codec->dev, "DC servo timed out\n"); 1896 dev_err(codec->dev, "DC servo timed out\n");
1897 else 1897 else
1898 dev_dbg(codec->dev, "DC servo complete after %dms\n", 1898 dev_dbg(codec->dev, "DC servo complete after %dms\n",
1899 timeout); 1899 timeout);
1900 1900
1901 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, 1901 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1902 WM8962_HP1L_ENA_OUTP | 1902 WM8962_HP1L_ENA_OUTP |
1903 WM8962_HP1R_ENA_OUTP, 1903 WM8962_HP1R_ENA_OUTP,
1904 WM8962_HP1L_ENA_OUTP | 1904 WM8962_HP1L_ENA_OUTP |
1905 WM8962_HP1R_ENA_OUTP); 1905 WM8962_HP1R_ENA_OUTP);
1906 udelay(20); 1906 udelay(20);
1907 1907
1908 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, 1908 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1909 WM8962_HP1L_RMV_SHORT | 1909 WM8962_HP1L_RMV_SHORT |
1910 WM8962_HP1R_RMV_SHORT, 1910 WM8962_HP1R_RMV_SHORT,
1911 WM8962_HP1L_RMV_SHORT | 1911 WM8962_HP1L_RMV_SHORT |
1912 WM8962_HP1R_RMV_SHORT); 1912 WM8962_HP1R_RMV_SHORT);
1913 break; 1913 break;
1914 1914
1915 case SND_SOC_DAPM_PRE_PMD: 1915 case SND_SOC_DAPM_PRE_PMD:
1916 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, 1916 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1917 WM8962_HP1L_RMV_SHORT | 1917 WM8962_HP1L_RMV_SHORT |
1918 WM8962_HP1R_RMV_SHORT, 0); 1918 WM8962_HP1R_RMV_SHORT, 0);
1919 1919
1920 udelay(20); 1920 udelay(20);
1921 1921
1922 snd_soc_update_bits(codec, WM8962_DC_SERVO_1, 1922 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
1923 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA | 1923 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1924 WM8962_HP1L_DCS_STARTUP | 1924 WM8962_HP1L_DCS_STARTUP |
1925 WM8962_HP1R_DCS_STARTUP, 1925 WM8962_HP1R_DCS_STARTUP,
1926 0); 1926 0);
1927 1927
1928 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, 1928 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1929 WM8962_HP1L_ENA | WM8962_HP1R_ENA | 1929 WM8962_HP1L_ENA | WM8962_HP1R_ENA |
1930 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY | 1930 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY |
1931 WM8962_HP1L_ENA_OUTP | 1931 WM8962_HP1L_ENA_OUTP |
1932 WM8962_HP1R_ENA_OUTP, 0); 1932 WM8962_HP1R_ENA_OUTP, 0);
1933 1933
1934 break; 1934 break;
1935 1935
1936 default: 1936 default:
1937 BUG(); 1937 BUG();
1938 return -EINVAL; 1938 return -EINVAL;
1939 1939
1940 } 1940 }
1941 1941
1942 return 0; 1942 return 0;
1943 } 1943 }
1944 1944
1945 /* VU bits for the output PGAs only take effect while the PGA is powered */ 1945 /* VU bits for the output PGAs only take effect while the PGA is powered */
1946 static int out_pga_event(struct snd_soc_dapm_widget *w, 1946 static int out_pga_event(struct snd_soc_dapm_widget *w,
1947 struct snd_kcontrol *kcontrol, int event) 1947 struct snd_kcontrol *kcontrol, int event)
1948 { 1948 {
1949 struct snd_soc_codec *codec = w->codec; 1949 struct snd_soc_codec *codec = w->codec;
1950 int reg; 1950 int reg;
1951 1951
1952 switch (w->shift) { 1952 switch (w->shift) {
1953 case WM8962_HPOUTR_PGA_ENA_SHIFT: 1953 case WM8962_HPOUTR_PGA_ENA_SHIFT:
1954 reg = WM8962_HPOUTR_VOLUME; 1954 reg = WM8962_HPOUTR_VOLUME;
1955 break; 1955 break;
1956 case WM8962_HPOUTL_PGA_ENA_SHIFT: 1956 case WM8962_HPOUTL_PGA_ENA_SHIFT:
1957 reg = WM8962_HPOUTL_VOLUME; 1957 reg = WM8962_HPOUTL_VOLUME;
1958 break; 1958 break;
1959 case WM8962_SPKOUTR_PGA_ENA_SHIFT: 1959 case WM8962_SPKOUTR_PGA_ENA_SHIFT:
1960 reg = WM8962_SPKOUTR_VOLUME; 1960 reg = WM8962_SPKOUTR_VOLUME;
1961 break; 1961 break;
1962 case WM8962_SPKOUTL_PGA_ENA_SHIFT: 1962 case WM8962_SPKOUTL_PGA_ENA_SHIFT:
1963 reg = WM8962_SPKOUTL_VOLUME; 1963 reg = WM8962_SPKOUTL_VOLUME;
1964 break; 1964 break;
1965 default: 1965 default:
1966 BUG(); 1966 BUG();
1967 return -EINVAL; 1967 return -EINVAL;
1968 } 1968 }
1969 1969
1970 switch (event) { 1970 switch (event) {
1971 case SND_SOC_DAPM_POST_PMU: 1971 case SND_SOC_DAPM_POST_PMU:
1972 return snd_soc_write(codec, reg, snd_soc_read(codec, reg)); 1972 return snd_soc_write(codec, reg, snd_soc_read(codec, reg));
1973 default: 1973 default:
1974 BUG(); 1974 BUG();
1975 return -EINVAL; 1975 return -EINVAL;
1976 } 1976 }
1977 } 1977 }
1978 1978
1979 static int dsp2_event(struct snd_soc_dapm_widget *w, 1979 static int dsp2_event(struct snd_soc_dapm_widget *w,
1980 struct snd_kcontrol *kcontrol, int event) 1980 struct snd_kcontrol *kcontrol, int event)
1981 { 1981 {
1982 struct snd_soc_codec *codec = w->codec; 1982 struct snd_soc_codec *codec = w->codec;
1983 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 1983 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1984 1984
1985 switch (event) { 1985 switch (event) {
1986 case SND_SOC_DAPM_POST_PMU: 1986 case SND_SOC_DAPM_POST_PMU:
1987 if (wm8962->dsp2_ena) 1987 if (wm8962->dsp2_ena)
1988 wm8962_dsp2_start(codec); 1988 wm8962_dsp2_start(codec);
1989 break; 1989 break;
1990 1990
1991 case SND_SOC_DAPM_PRE_PMD: 1991 case SND_SOC_DAPM_PRE_PMD:
1992 if (wm8962->dsp2_ena) 1992 if (wm8962->dsp2_ena)
1993 wm8962_dsp2_stop(codec); 1993 wm8962_dsp2_stop(codec);
1994 break; 1994 break;
1995 1995
1996 default: 1996 default:
1997 BUG(); 1997 BUG();
1998 return -EINVAL; 1998 return -EINVAL;
1999 } 1999 }
2000 2000
2001 return 0; 2001 return 0;
2002 } 2002 }
2003 2003
2004 static const char *st_text[] = { "None", "Left", "Right" }; 2004 static const char *st_text[] = { "None", "Left", "Right" };
2005 2005
2006 static const struct soc_enum str_enum = 2006 static const struct soc_enum str_enum =
2007 SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_1, 2, 3, st_text); 2007 SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_1, 2, 3, st_text);
2008 2008
2009 static const struct snd_kcontrol_new str_mux = 2009 static const struct snd_kcontrol_new str_mux =
2010 SOC_DAPM_ENUM("Right Sidetone", str_enum); 2010 SOC_DAPM_ENUM("Right Sidetone", str_enum);
2011 2011
2012 static const struct soc_enum stl_enum = 2012 static const struct soc_enum stl_enum =
2013 SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_2, 2, 3, st_text); 2013 SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_2, 2, 3, st_text);
2014 2014
2015 static const struct snd_kcontrol_new stl_mux = 2015 static const struct snd_kcontrol_new stl_mux =
2016 SOC_DAPM_ENUM("Left Sidetone", stl_enum); 2016 SOC_DAPM_ENUM("Left Sidetone", stl_enum);
2017 2017
2018 static const char *outmux_text[] = { "DAC", "Mixer" }; 2018 static const char *outmux_text[] = { "DAC", "Mixer" };
2019 2019
2020 static const struct soc_enum spkoutr_enum = 2020 static const struct soc_enum spkoutr_enum =
2021 SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_2, 7, 2, outmux_text); 2021 SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_2, 7, 2, outmux_text);
2022 2022
2023 static const struct snd_kcontrol_new spkoutr_mux = 2023 static const struct snd_kcontrol_new spkoutr_mux =
2024 SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum); 2024 SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum);
2025 2025
2026 static const struct soc_enum spkoutl_enum = 2026 static const struct soc_enum spkoutl_enum =
2027 SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_1, 7, 2, outmux_text); 2027 SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_1, 7, 2, outmux_text);
2028 2028
2029 static const struct snd_kcontrol_new spkoutl_mux = 2029 static const struct snd_kcontrol_new spkoutl_mux =
2030 SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum); 2030 SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum);
2031 2031
2032 static const struct soc_enum hpoutr_enum = 2032 static const struct soc_enum hpoutr_enum =
2033 SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_2, 7, 2, outmux_text); 2033 SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_2, 7, 2, outmux_text);
2034 2034
2035 static const struct snd_kcontrol_new hpoutr_mux = 2035 static const struct snd_kcontrol_new hpoutr_mux =
2036 SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum); 2036 SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum);
2037 2037
2038 static const struct soc_enum hpoutl_enum = 2038 static const struct soc_enum hpoutl_enum =
2039 SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_1, 7, 2, outmux_text); 2039 SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_1, 7, 2, outmux_text);
2040 2040
2041 static const struct snd_kcontrol_new hpoutl_mux = 2041 static const struct snd_kcontrol_new hpoutl_mux =
2042 SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum); 2042 SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum);
2043 2043
2044 static const struct snd_kcontrol_new inpgal[] = { 2044 static const struct snd_kcontrol_new inpgal[] = {
2045 SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0), 2045 SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0),
2046 SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0), 2046 SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0),
2047 SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0), 2047 SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0),
2048 SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0), 2048 SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0),
2049 }; 2049 };
2050 2050
2051 static const struct snd_kcontrol_new inpgar[] = { 2051 static const struct snd_kcontrol_new inpgar[] = {
2052 SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0), 2052 SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0),
2053 SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0), 2053 SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0),
2054 SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0), 2054 SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0),
2055 SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0), 2055 SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0),
2056 }; 2056 };
2057 2057
2058 static const struct snd_kcontrol_new mixinl[] = { 2058 static const struct snd_kcontrol_new mixinl[] = {
2059 SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0), 2059 SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0),
2060 SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0), 2060 SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0),
2061 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0), 2061 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0),
2062 }; 2062 };
2063 2063
2064 static const struct snd_kcontrol_new mixinr[] = { 2064 static const struct snd_kcontrol_new mixinr[] = {
2065 SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0), 2065 SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0),
2066 SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0), 2066 SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0),
2067 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0), 2067 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0),
2068 }; 2068 };
2069 2069
2070 static const struct snd_kcontrol_new hpmixl[] = { 2070 static const struct snd_kcontrol_new hpmixl[] = {
2071 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0), 2071 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0),
2072 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0), 2072 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0),
2073 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0), 2073 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0),
2074 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0), 2074 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0),
2075 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0), 2075 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0),
2076 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0), 2076 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0),
2077 }; 2077 };
2078 2078
2079 static const struct snd_kcontrol_new hpmixr[] = { 2079 static const struct snd_kcontrol_new hpmixr[] = {
2080 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0), 2080 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0),
2081 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0), 2081 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0),
2082 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0), 2082 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0),
2083 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0), 2083 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0),
2084 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0), 2084 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0),
2085 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0), 2085 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0),
2086 }; 2086 };
2087 2087
2088 static const struct snd_kcontrol_new spkmixl[] = { 2088 static const struct snd_kcontrol_new spkmixl[] = {
2089 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0), 2089 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0),
2090 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0), 2090 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0),
2091 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0), 2091 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0),
2092 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0), 2092 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0),
2093 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0), 2093 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0),
2094 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0), 2094 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0),
2095 }; 2095 };
2096 2096
2097 static const struct snd_kcontrol_new spkmixr[] = { 2097 static const struct snd_kcontrol_new spkmixr[] = {
2098 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0), 2098 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0),
2099 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0), 2099 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0),
2100 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0), 2100 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0),
2101 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0), 2101 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0),
2102 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0), 2102 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0),
2103 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0), 2103 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0),
2104 }; 2104 };
2105 2105
2106 static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = { 2106 static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = {
2107 SND_SOC_DAPM_INPUT("IN1L"), 2107 SND_SOC_DAPM_INPUT("IN1L"),
2108 SND_SOC_DAPM_INPUT("IN1R"), 2108 SND_SOC_DAPM_INPUT("IN1R"),
2109 SND_SOC_DAPM_INPUT("IN2L"), 2109 SND_SOC_DAPM_INPUT("IN2L"),
2110 SND_SOC_DAPM_INPUT("IN2R"), 2110 SND_SOC_DAPM_INPUT("IN2R"),
2111 SND_SOC_DAPM_INPUT("IN3L"), 2111 SND_SOC_DAPM_INPUT("IN3L"),
2112 SND_SOC_DAPM_INPUT("IN3R"), 2112 SND_SOC_DAPM_INPUT("IN3R"),
2113 SND_SOC_DAPM_INPUT("IN4L"), 2113 SND_SOC_DAPM_INPUT("IN4L"),
2114 SND_SOC_DAPM_INPUT("IN4R"), 2114 SND_SOC_DAPM_INPUT("IN4R"),
2115 SND_SOC_DAPM_SIGGEN("Beep"), 2115 SND_SOC_DAPM_SIGGEN("Beep"),
2116 SND_SOC_DAPM_INPUT("DMICDAT"), 2116 SND_SOC_DAPM_INPUT("DMICDAT"),
2117 2117
2118 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8962_PWR_MGMT_1, 1, 0, NULL, 0), 2118 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8962_PWR_MGMT_1, 1, 0, NULL, 0),
2119 2119
2120 SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0), 2120 SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0),
2121 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, NULL, 0), 2121 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, NULL, 0),
2122 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event, 2122 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event,
2123 SND_SOC_DAPM_POST_PMU), 2123 SND_SOC_DAPM_POST_PMU),
2124 SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0), 2124 SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0),
2125 SND_SOC_DAPM_SUPPLY_S("DSP2", 1, WM8962_DSP2_POWER_MANAGEMENT, 2125 SND_SOC_DAPM_SUPPLY_S("DSP2", 1, WM8962_DSP2_POWER_MANAGEMENT,
2126 WM8962_DSP2_ENA_SHIFT, 0, dsp2_event, 2126 WM8962_DSP2_ENA_SHIFT, 0, dsp2_event,
2127 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2127 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2128 SND_SOC_DAPM_SUPPLY("TEMP_HP", WM8962_ADDITIONAL_CONTROL_4, 2, 0, NULL, 0), 2128 SND_SOC_DAPM_SUPPLY("TEMP_HP", WM8962_ADDITIONAL_CONTROL_4, 2, 0, NULL, 0),
2129 SND_SOC_DAPM_SUPPLY("TEMP_SPK", WM8962_ADDITIONAL_CONTROL_4, 1, 0, NULL, 0), 2129 SND_SOC_DAPM_SUPPLY("TEMP_SPK", WM8962_ADDITIONAL_CONTROL_4, 1, 0, NULL, 0),
2130 2130
2131 SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0, 2131 SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0,
2132 inpgal, ARRAY_SIZE(inpgal)), 2132 inpgal, ARRAY_SIZE(inpgal)),
2133 SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0, 2133 SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0,
2134 inpgar, ARRAY_SIZE(inpgar)), 2134 inpgar, ARRAY_SIZE(inpgar)),
2135 SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0, 2135 SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0,
2136 mixinl, ARRAY_SIZE(mixinl)), 2136 mixinl, ARRAY_SIZE(mixinl)),
2137 SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0, 2137 SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0,
2138 mixinr, ARRAY_SIZE(mixinr)), 2138 mixinr, ARRAY_SIZE(mixinr)),
2139 2139
2140 SND_SOC_DAPM_AIF_IN("DMIC_ENA", NULL, 0, WM8962_PWR_MGMT_1, 10, 0), 2140 SND_SOC_DAPM_AIF_IN("DMIC_ENA", NULL, 0, WM8962_PWR_MGMT_1, 10, 0),
2141 2141
2142 SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0), 2142 SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0),
2143 SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0), 2143 SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0),
2144 2144
2145 SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux), 2145 SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux),
2146 SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux), 2146 SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux),
2147 2147
2148 SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0), 2148 SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0),
2149 SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0), 2149 SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0),
2150 2150
2151 SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), 2151 SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2152 SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), 2152 SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2153 2153
2154 SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0, 2154 SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0,
2155 hpmixl, ARRAY_SIZE(hpmixl)), 2155 hpmixl, ARRAY_SIZE(hpmixl)),
2156 SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0, 2156 SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0,
2157 hpmixr, ARRAY_SIZE(hpmixr)), 2157 hpmixr, ARRAY_SIZE(hpmixr)),
2158 2158
2159 SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux, 2159 SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux,
2160 out_pga_event, SND_SOC_DAPM_POST_PMU), 2160 out_pga_event, SND_SOC_DAPM_POST_PMU),
2161 SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux, 2161 SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux,
2162 out_pga_event, SND_SOC_DAPM_POST_PMU), 2162 out_pga_event, SND_SOC_DAPM_POST_PMU),
2163 2163
2164 SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event, 2164 SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event,
2165 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2165 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2166 2166
2167 SND_SOC_DAPM_OUTPUT("HPOUTL"), 2167 SND_SOC_DAPM_OUTPUT("HPOUTL"),
2168 SND_SOC_DAPM_OUTPUT("HPOUTR"), 2168 SND_SOC_DAPM_OUTPUT("HPOUTR"),
2169 }; 2169 };
2170 2170
2171 static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = { 2171 static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = {
2172 SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0, 2172 SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0,
2173 spkmixl, ARRAY_SIZE(spkmixl)), 2173 spkmixl, ARRAY_SIZE(spkmixl)),
2174 SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux, 2174 SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2175 out_pga_event, SND_SOC_DAPM_POST_PMU), 2175 out_pga_event, SND_SOC_DAPM_POST_PMU),
2176 SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0), 2176 SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2177 SND_SOC_DAPM_OUTPUT("SPKOUT"), 2177 SND_SOC_DAPM_OUTPUT("SPKOUT"),
2178 }; 2178 };
2179 2179
2180 static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = { 2180 static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = {
2181 SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0, 2181 SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0,
2182 spkmixl, ARRAY_SIZE(spkmixl)), 2182 spkmixl, ARRAY_SIZE(spkmixl)),
2183 SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0, 2183 SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0,
2184 spkmixr, ARRAY_SIZE(spkmixr)), 2184 spkmixr, ARRAY_SIZE(spkmixr)),
2185 2185
2186 SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux, 2186 SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2187 out_pga_event, SND_SOC_DAPM_POST_PMU), 2187 out_pga_event, SND_SOC_DAPM_POST_PMU),
2188 SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux, 2188 SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux,
2189 out_pga_event, SND_SOC_DAPM_POST_PMU), 2189 out_pga_event, SND_SOC_DAPM_POST_PMU),
2190 2190
2191 SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0), 2191 SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2192 SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0), 2192 SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0),
2193 2193
2194 SND_SOC_DAPM_OUTPUT("SPKOUTL"), 2194 SND_SOC_DAPM_OUTPUT("SPKOUTL"),
2195 SND_SOC_DAPM_OUTPUT("SPKOUTR"), 2195 SND_SOC_DAPM_OUTPUT("SPKOUTR"),
2196 }; 2196 };
2197 2197
2198 static const struct snd_soc_dapm_route wm8962_intercon[] = { 2198 static const struct snd_soc_dapm_route wm8962_intercon[] = {
2199 { "INPGAL", "IN1L Switch", "IN1L" }, 2199 { "INPGAL", "IN1L Switch", "IN1L" },
2200 { "INPGAL", "IN2L Switch", "IN2L" }, 2200 { "INPGAL", "IN2L Switch", "IN2L" },
2201 { "INPGAL", "IN3L Switch", "IN3L" }, 2201 { "INPGAL", "IN3L Switch", "IN3L" },
2202 { "INPGAL", "IN4L Switch", "IN4L" }, 2202 { "INPGAL", "IN4L Switch", "IN4L" },
2203 2203
2204 { "INPGAR", "IN1R Switch", "IN1R" }, 2204 { "INPGAR", "IN1R Switch", "IN1R" },
2205 { "INPGAR", "IN2R Switch", "IN2R" }, 2205 { "INPGAR", "IN2R Switch", "IN2R" },
2206 { "INPGAR", "IN3R Switch", "IN3R" }, 2206 { "INPGAR", "IN3R Switch", "IN3R" },
2207 { "INPGAR", "IN4R Switch", "IN4R" }, 2207 { "INPGAR", "IN4R Switch", "IN4R" },
2208 2208
2209 { "MIXINL", "IN2L Switch", "IN2L" }, 2209 { "MIXINL", "IN2L Switch", "IN2L" },
2210 { "MIXINL", "IN3L Switch", "IN3L" }, 2210 { "MIXINL", "IN3L Switch", "IN3L" },
2211 { "MIXINL", "PGA Switch", "INPGAL" }, 2211 { "MIXINL", "PGA Switch", "INPGAL" },
2212 2212
2213 { "MIXINR", "IN2R Switch", "IN2R" }, 2213 { "MIXINR", "IN2R Switch", "IN2R" },
2214 { "MIXINR", "IN3R Switch", "IN3R" }, 2214 { "MIXINR", "IN3R Switch", "IN3R" },
2215 { "MIXINR", "PGA Switch", "INPGAR" }, 2215 { "MIXINR", "PGA Switch", "INPGAR" },
2216 2216
2217 { "MICBIAS", NULL, "SYSCLK" }, 2217 { "MICBIAS", NULL, "SYSCLK" },
2218 2218
2219 { "DMIC_ENA", NULL, "DMICDAT" }, 2219 { "DMIC_ENA", NULL, "DMICDAT" },
2220 2220
2221 { "ADCL", NULL, "SYSCLK" }, 2221 { "ADCL", NULL, "SYSCLK" },
2222 { "ADCL", NULL, "TOCLK" }, 2222 { "ADCL", NULL, "TOCLK" },
2223 { "ADCL", NULL, "MIXINL" }, 2223 { "ADCL", NULL, "MIXINL" },
2224 { "ADCL", NULL, "DMIC_ENA" }, 2224 { "ADCL", NULL, "DMIC_ENA" },
2225 { "ADCL", NULL, "DSP2" }, 2225 { "ADCL", NULL, "DSP2" },
2226 2226
2227 { "ADCR", NULL, "SYSCLK" }, 2227 { "ADCR", NULL, "SYSCLK" },
2228 { "ADCR", NULL, "TOCLK" }, 2228 { "ADCR", NULL, "TOCLK" },
2229 { "ADCR", NULL, "MIXINR" }, 2229 { "ADCR", NULL, "MIXINR" },
2230 { "ADCR", NULL, "DMIC_ENA" }, 2230 { "ADCR", NULL, "DMIC_ENA" },
2231 { "ADCR", NULL, "DSP2" }, 2231 { "ADCR", NULL, "DSP2" },
2232 2232
2233 { "STL", "Left", "ADCL" }, 2233 { "STL", "Left", "ADCL" },
2234 { "STL", "Right", "ADCR" }, 2234 { "STL", "Right", "ADCR" },
2235 { "STL", NULL, "Class G" }, 2235 { "STL", NULL, "Class G" },
2236 2236
2237 { "STR", "Left", "ADCL" }, 2237 { "STR", "Left", "ADCL" },
2238 { "STR", "Right", "ADCR" }, 2238 { "STR", "Right", "ADCR" },
2239 { "STR", NULL, "Class G" }, 2239 { "STR", NULL, "Class G" },
2240 2240
2241 { "DACL", NULL, "SYSCLK" }, 2241 { "DACL", NULL, "SYSCLK" },
2242 { "DACL", NULL, "TOCLK" }, 2242 { "DACL", NULL, "TOCLK" },
2243 { "DACL", NULL, "Beep" }, 2243 { "DACL", NULL, "Beep" },
2244 { "DACL", NULL, "STL" }, 2244 { "DACL", NULL, "STL" },
2245 { "DACL", NULL, "DSP2" }, 2245 { "DACL", NULL, "DSP2" },
2246 2246
2247 { "DACR", NULL, "SYSCLK" }, 2247 { "DACR", NULL, "SYSCLK" },
2248 { "DACR", NULL, "TOCLK" }, 2248 { "DACR", NULL, "TOCLK" },
2249 { "DACR", NULL, "Beep" }, 2249 { "DACR", NULL, "Beep" },
2250 { "DACR", NULL, "STR" }, 2250 { "DACR", NULL, "STR" },
2251 { "DACR", NULL, "DSP2" }, 2251 { "DACR", NULL, "DSP2" },
2252 2252
2253 { "HPMIXL", "IN4L Switch", "IN4L" }, 2253 { "HPMIXL", "IN4L Switch", "IN4L" },
2254 { "HPMIXL", "IN4R Switch", "IN4R" }, 2254 { "HPMIXL", "IN4R Switch", "IN4R" },
2255 { "HPMIXL", "DACL Switch", "DACL" }, 2255 { "HPMIXL", "DACL Switch", "DACL" },
2256 { "HPMIXL", "DACR Switch", "DACR" }, 2256 { "HPMIXL", "DACR Switch", "DACR" },
2257 { "HPMIXL", "MIXINL Switch", "MIXINL" }, 2257 { "HPMIXL", "MIXINL Switch", "MIXINL" },
2258 { "HPMIXL", "MIXINR Switch", "MIXINR" }, 2258 { "HPMIXL", "MIXINR Switch", "MIXINR" },
2259 2259
2260 { "HPMIXR", "IN4L Switch", "IN4L" }, 2260 { "HPMIXR", "IN4L Switch", "IN4L" },
2261 { "HPMIXR", "IN4R Switch", "IN4R" }, 2261 { "HPMIXR", "IN4R Switch", "IN4R" },
2262 { "HPMIXR", "DACL Switch", "DACL" }, 2262 { "HPMIXR", "DACL Switch", "DACL" },
2263 { "HPMIXR", "DACR Switch", "DACR" }, 2263 { "HPMIXR", "DACR Switch", "DACR" },
2264 { "HPMIXR", "MIXINL Switch", "MIXINL" }, 2264 { "HPMIXR", "MIXINL Switch", "MIXINL" },
2265 { "HPMIXR", "MIXINR Switch", "MIXINR" }, 2265 { "HPMIXR", "MIXINR Switch", "MIXINR" },
2266 2266
2267 { "Left Bypass", NULL, "HPMIXL" }, 2267 { "Left Bypass", NULL, "HPMIXL" },
2268 { "Left Bypass", NULL, "Class G" }, 2268 { "Left Bypass", NULL, "Class G" },
2269 2269
2270 { "Right Bypass", NULL, "HPMIXR" }, 2270 { "Right Bypass", NULL, "HPMIXR" },
2271 { "Right Bypass", NULL, "Class G" }, 2271 { "Right Bypass", NULL, "Class G" },
2272 2272
2273 { "HPOUTL PGA", "Mixer", "Left Bypass" }, 2273 { "HPOUTL PGA", "Mixer", "Left Bypass" },
2274 { "HPOUTL PGA", "DAC", "DACL" }, 2274 { "HPOUTL PGA", "DAC", "DACL" },
2275 2275
2276 { "HPOUTR PGA", "Mixer", "Right Bypass" }, 2276 { "HPOUTR PGA", "Mixer", "Right Bypass" },
2277 { "HPOUTR PGA", "DAC", "DACR" }, 2277 { "HPOUTR PGA", "DAC", "DACR" },
2278 2278
2279 { "HPOUT", NULL, "HPOUTL PGA" }, 2279 { "HPOUT", NULL, "HPOUTL PGA" },
2280 { "HPOUT", NULL, "HPOUTR PGA" }, 2280 { "HPOUT", NULL, "HPOUTR PGA" },
2281 { "HPOUT", NULL, "Charge Pump" }, 2281 { "HPOUT", NULL, "Charge Pump" },
2282 { "HPOUT", NULL, "SYSCLK" }, 2282 { "HPOUT", NULL, "SYSCLK" },
2283 { "HPOUT", NULL, "TOCLK" }, 2283 { "HPOUT", NULL, "TOCLK" },
2284 2284
2285 { "HPOUTL", NULL, "HPOUT" }, 2285 { "HPOUTL", NULL, "HPOUT" },
2286 { "HPOUTR", NULL, "HPOUT" }, 2286 { "HPOUTR", NULL, "HPOUT" },
2287 2287
2288 { "HPOUTL", NULL, "TEMP_HP" }, 2288 { "HPOUTL", NULL, "TEMP_HP" },
2289 { "HPOUTR", NULL, "TEMP_HP" }, 2289 { "HPOUTR", NULL, "TEMP_HP" },
2290 }; 2290 };
2291 2291
2292 static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = { 2292 static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = {
2293 { "Speaker Mixer", "IN4L Switch", "IN4L" }, 2293 { "Speaker Mixer", "IN4L Switch", "IN4L" },
2294 { "Speaker Mixer", "IN4R Switch", "IN4R" }, 2294 { "Speaker Mixer", "IN4R Switch", "IN4R" },
2295 { "Speaker Mixer", "DACL Switch", "DACL" }, 2295 { "Speaker Mixer", "DACL Switch", "DACL" },
2296 { "Speaker Mixer", "DACR Switch", "DACR" }, 2296 { "Speaker Mixer", "DACR Switch", "DACR" },
2297 { "Speaker Mixer", "MIXINL Switch", "MIXINL" }, 2297 { "Speaker Mixer", "MIXINL Switch", "MIXINL" },
2298 { "Speaker Mixer", "MIXINR Switch", "MIXINR" }, 2298 { "Speaker Mixer", "MIXINR Switch", "MIXINR" },
2299 2299
2300 { "Speaker PGA", "Mixer", "Speaker Mixer" }, 2300 { "Speaker PGA", "Mixer", "Speaker Mixer" },
2301 { "Speaker PGA", "DAC", "DACL" }, 2301 { "Speaker PGA", "DAC", "DACL" },
2302 2302
2303 { "Speaker Output", NULL, "Speaker PGA" }, 2303 { "Speaker Output", NULL, "Speaker PGA" },
2304 { "Speaker Output", NULL, "SYSCLK" }, 2304 { "Speaker Output", NULL, "SYSCLK" },
2305 { "Speaker Output", NULL, "TOCLK" }, 2305 { "Speaker Output", NULL, "TOCLK" },
2306 { "Speaker Output", NULL, "TEMP_SPK" }, 2306 { "Speaker Output", NULL, "TEMP_SPK" },
2307 2307
2308 { "SPKOUT", NULL, "Speaker Output" }, 2308 { "SPKOUT", NULL, "Speaker Output" },
2309 }; 2309 };
2310 2310
2311 static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = { 2311 static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = {
2312 { "SPKOUTL Mixer", "IN4L Switch", "IN4L" }, 2312 { "SPKOUTL Mixer", "IN4L Switch", "IN4L" },
2313 { "SPKOUTL Mixer", "IN4R Switch", "IN4R" }, 2313 { "SPKOUTL Mixer", "IN4R Switch", "IN4R" },
2314 { "SPKOUTL Mixer", "DACL Switch", "DACL" }, 2314 { "SPKOUTL Mixer", "DACL Switch", "DACL" },
2315 { "SPKOUTL Mixer", "DACR Switch", "DACR" }, 2315 { "SPKOUTL Mixer", "DACR Switch", "DACR" },
2316 { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" }, 2316 { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" },
2317 { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" }, 2317 { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" },
2318 2318
2319 { "SPKOUTR Mixer", "IN4L Switch", "IN4L" }, 2319 { "SPKOUTR Mixer", "IN4L Switch", "IN4L" },
2320 { "SPKOUTR Mixer", "IN4R Switch", "IN4R" }, 2320 { "SPKOUTR Mixer", "IN4R Switch", "IN4R" },
2321 { "SPKOUTR Mixer", "DACL Switch", "DACL" }, 2321 { "SPKOUTR Mixer", "DACL Switch", "DACL" },
2322 { "SPKOUTR Mixer", "DACR Switch", "DACR" }, 2322 { "SPKOUTR Mixer", "DACR Switch", "DACR" },
2323 { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" }, 2323 { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" },
2324 { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" }, 2324 { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" },
2325 2325
2326 { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" }, 2326 { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" },
2327 { "SPKOUTL PGA", "DAC", "DACL" }, 2327 { "SPKOUTL PGA", "DAC", "DACL" },
2328 2328
2329 { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" }, 2329 { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" },
2330 { "SPKOUTR PGA", "DAC", "DACR" }, 2330 { "SPKOUTR PGA", "DAC", "DACR" },
2331 2331
2332 { "SPKOUTL Output", NULL, "SPKOUTL PGA" }, 2332 { "SPKOUTL Output", NULL, "SPKOUTL PGA" },
2333 { "SPKOUTL Output", NULL, "SYSCLK" }, 2333 { "SPKOUTL Output", NULL, "SYSCLK" },
2334 { "SPKOUTL Output", NULL, "TOCLK" }, 2334 { "SPKOUTL Output", NULL, "TOCLK" },
2335 { "SPKOUTL Output", NULL, "TEMP_SPK" }, 2335 { "SPKOUTL Output", NULL, "TEMP_SPK" },
2336 2336
2337 { "SPKOUTR Output", NULL, "SPKOUTR PGA" }, 2337 { "SPKOUTR Output", NULL, "SPKOUTR PGA" },
2338 { "SPKOUTR Output", NULL, "SYSCLK" }, 2338 { "SPKOUTR Output", NULL, "SYSCLK" },
2339 { "SPKOUTR Output", NULL, "TOCLK" }, 2339 { "SPKOUTR Output", NULL, "TOCLK" },
2340 { "SPKOUTR Output", NULL, "TEMP_SPK" }, 2340 { "SPKOUTR Output", NULL, "TEMP_SPK" },
2341 2341
2342 { "SPKOUTL", NULL, "SPKOUTL Output" }, 2342 { "SPKOUTL", NULL, "SPKOUTL Output" },
2343 { "SPKOUTR", NULL, "SPKOUTR Output" }, 2343 { "SPKOUTR", NULL, "SPKOUTR Output" },
2344 }; 2344 };
2345 2345
2346 static int wm8962_add_widgets(struct snd_soc_codec *codec) 2346 static int wm8962_add_widgets(struct snd_soc_codec *codec)
2347 { 2347 {
2348 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev); 2348 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
2349 struct snd_soc_dapm_context *dapm = &codec->dapm; 2349 struct snd_soc_dapm_context *dapm = &codec->dapm;
2350 2350
2351 snd_soc_add_codec_controls(codec, wm8962_snd_controls, 2351 snd_soc_add_codec_controls(codec, wm8962_snd_controls,
2352 ARRAY_SIZE(wm8962_snd_controls)); 2352 ARRAY_SIZE(wm8962_snd_controls));
2353 if (pdata && pdata->spk_mono) 2353 if (pdata && pdata->spk_mono)
2354 snd_soc_add_codec_controls(codec, wm8962_spk_mono_controls, 2354 snd_soc_add_codec_controls(codec, wm8962_spk_mono_controls,
2355 ARRAY_SIZE(wm8962_spk_mono_controls)); 2355 ARRAY_SIZE(wm8962_spk_mono_controls));
2356 else 2356 else
2357 snd_soc_add_codec_controls(codec, wm8962_spk_stereo_controls, 2357 snd_soc_add_codec_controls(codec, wm8962_spk_stereo_controls,
2358 ARRAY_SIZE(wm8962_spk_stereo_controls)); 2358 ARRAY_SIZE(wm8962_spk_stereo_controls));
2359 2359
2360 2360
2361 snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets, 2361 snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets,
2362 ARRAY_SIZE(wm8962_dapm_widgets)); 2362 ARRAY_SIZE(wm8962_dapm_widgets));
2363 if (pdata && pdata->spk_mono) 2363 if (pdata && pdata->spk_mono)
2364 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets, 2364 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets,
2365 ARRAY_SIZE(wm8962_dapm_spk_mono_widgets)); 2365 ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
2366 else 2366 else
2367 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_stereo_widgets, 2367 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_stereo_widgets,
2368 ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets)); 2368 ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets));
2369 2369
2370 snd_soc_dapm_add_routes(dapm, wm8962_intercon, 2370 snd_soc_dapm_add_routes(dapm, wm8962_intercon,
2371 ARRAY_SIZE(wm8962_intercon)); 2371 ARRAY_SIZE(wm8962_intercon));
2372 if (pdata && pdata->spk_mono) 2372 if (pdata && pdata->spk_mono)
2373 snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon, 2373 snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon,
2374 ARRAY_SIZE(wm8962_spk_mono_intercon)); 2374 ARRAY_SIZE(wm8962_spk_mono_intercon));
2375 else 2375 else
2376 snd_soc_dapm_add_routes(dapm, wm8962_spk_stereo_intercon, 2376 snd_soc_dapm_add_routes(dapm, wm8962_spk_stereo_intercon,
2377 ARRAY_SIZE(wm8962_spk_stereo_intercon)); 2377 ARRAY_SIZE(wm8962_spk_stereo_intercon));
2378 2378
2379 2379
2380 snd_soc_dapm_disable_pin(dapm, "Beep"); 2380 snd_soc_dapm_disable_pin(dapm, "Beep");
2381 2381
2382 return 0; 2382 return 0;
2383 } 2383 }
2384 2384
2385 /* -1 for reserved values */ 2385 /* -1 for reserved values */
2386 static const int bclk_divs[] = { 2386 static const int bclk_divs[] = {
2387 1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32 2387 1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32
2388 }; 2388 };
2389 2389
2390 static const int sysclk_rates[] = { 2390 static const int sysclk_rates[] = {
2391 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536, 3072, 6144 2391 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536, 3072, 6144
2392 }; 2392 };
2393 2393
2394 static void wm8962_configure_bclk(struct snd_soc_codec *codec) 2394 static void wm8962_configure_bclk(struct snd_soc_codec *codec)
2395 { 2395 {
2396 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 2396 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2397 int dspclk, i; 2397 int dspclk, i;
2398 int clocking2 = 0; 2398 int clocking2 = 0;
2399 int clocking4 = 0; 2399 int clocking4 = 0;
2400 int aif2 = 0; 2400 int aif2 = 0;
2401 2401
2402 if (!wm8962->sysclk_rate) { 2402 if (!wm8962->sysclk_rate) {
2403 dev_dbg(codec->dev, "No SYSCLK configured\n"); 2403 dev_dbg(codec->dev, "No SYSCLK configured\n");
2404 return; 2404 return;
2405 } 2405 }
2406 2406
2407 if (!wm8962->bclk || !wm8962->lrclk) { 2407 if (!wm8962->bclk || !wm8962->lrclk) {
2408 dev_dbg(codec->dev, "No audio clocks configured\n"); 2408 dev_dbg(codec->dev, "No audio clocks configured\n");
2409 return; 2409 return;
2410 } 2410 }
2411 2411
2412 for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) { 2412 for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) {
2413 if (sysclk_rates[i] == wm8962->sysclk_rate / wm8962->lrclk) { 2413 if (sysclk_rates[i] == wm8962->sysclk_rate / wm8962->lrclk) {
2414 clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT; 2414 clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT;
2415 break; 2415 break;
2416 } 2416 }
2417 } 2417 }
2418 2418
2419 if (i == ARRAY_SIZE(sysclk_rates)) { 2419 if (i == ARRAY_SIZE(sysclk_rates)) {
2420 dev_err(codec->dev, "Unsupported sysclk ratio %d\n", 2420 dev_err(codec->dev, "Unsupported sysclk ratio %d\n",
2421 wm8962->sysclk_rate / wm8962->lrclk); 2421 wm8962->sysclk_rate / wm8962->lrclk);
2422 return; 2422 return;
2423 } 2423 }
2424 2424
2425 dev_dbg(codec->dev, "Selected sysclk ratio %d\n", sysclk_rates[i]); 2425 dev_dbg(codec->dev, "Selected sysclk ratio %d\n", sysclk_rates[i]);
2426 2426
2427 snd_soc_update_bits(codec, WM8962_CLOCKING_4, 2427 snd_soc_update_bits(codec, WM8962_CLOCKING_4,
2428 WM8962_SYSCLK_RATE_MASK, clocking4); 2428 WM8962_SYSCLK_RATE_MASK, clocking4);
2429 2429
2430 dspclk = snd_soc_read(codec, WM8962_CLOCKING1); 2430 dspclk = snd_soc_read(codec, WM8962_CLOCKING1);
2431 if (dspclk < 0) { 2431 if (dspclk < 0) {
2432 dev_err(codec->dev, "Failed to read DSPCLK: %d\n", dspclk); 2432 dev_err(codec->dev, "Failed to read DSPCLK: %d\n", dspclk);
2433 return; 2433 return;
2434 } 2434 }
2435 2435
2436 dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT; 2436 dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT;
2437 switch (dspclk) { 2437 switch (dspclk) {
2438 case 0: 2438 case 0:
2439 dspclk = wm8962->sysclk_rate; 2439 dspclk = wm8962->sysclk_rate;
2440 break; 2440 break;
2441 case 1: 2441 case 1:
2442 dspclk = wm8962->sysclk_rate / 2; 2442 dspclk = wm8962->sysclk_rate / 2;
2443 break; 2443 break;
2444 case 2: 2444 case 2:
2445 dspclk = wm8962->sysclk_rate / 4; 2445 dspclk = wm8962->sysclk_rate / 4;
2446 break; 2446 break;
2447 default: 2447 default:
2448 dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n"); 2448 dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n");
2449 dspclk = wm8962->sysclk; 2449 dspclk = wm8962->sysclk;
2450 } 2450 }
2451 2451
2452 dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk); 2452 dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);
2453 2453
2454 /* We're expecting an exact match */ 2454 /* We're expecting an exact match */
2455 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 2455 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2456 if (bclk_divs[i] < 0) 2456 if (bclk_divs[i] < 0)
2457 continue; 2457 continue;
2458 2458
2459 if (dspclk / bclk_divs[i] == wm8962->bclk) { 2459 if (dspclk / bclk_divs[i] == wm8962->bclk) {
2460 dev_dbg(codec->dev, "Selected BCLK_DIV %d for %dHz\n", 2460 dev_dbg(codec->dev, "Selected BCLK_DIV %d for %dHz\n",
2461 bclk_divs[i], wm8962->bclk); 2461 bclk_divs[i], wm8962->bclk);
2462 clocking2 |= i; 2462 clocking2 |= i;
2463 break; 2463 break;
2464 } 2464 }
2465 } 2465 }
2466 if (i == ARRAY_SIZE(bclk_divs)) { 2466 if (i == ARRAY_SIZE(bclk_divs)) {
2467 dev_err(codec->dev, "Unsupported BCLK ratio %d\n", 2467 dev_err(codec->dev, "Unsupported BCLK ratio %d\n",
2468 dspclk / wm8962->bclk); 2468 dspclk / wm8962->bclk);
2469 return; 2469 return;
2470 } 2470 }
2471 2471
2472 aif2 |= wm8962->bclk / wm8962->lrclk; 2472 aif2 |= wm8962->bclk / wm8962->lrclk;
2473 dev_dbg(codec->dev, "Selected LRCLK divisor %d for %dHz\n", 2473 dev_dbg(codec->dev, "Selected LRCLK divisor %d for %dHz\n",
2474 wm8962->bclk / wm8962->lrclk, wm8962->lrclk); 2474 wm8962->bclk / wm8962->lrclk, wm8962->lrclk);
2475 2475
2476 snd_soc_update_bits(codec, WM8962_CLOCKING2, 2476 snd_soc_update_bits(codec, WM8962_CLOCKING2,
2477 WM8962_BCLK_DIV_MASK, clocking2); 2477 WM8962_BCLK_DIV_MASK, clocking2);
2478 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_2, 2478 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_2,
2479 WM8962_AIF_RATE_MASK, aif2); 2479 WM8962_AIF_RATE_MASK, aif2);
2480 } 2480 }
2481 2481
2482 static int wm8962_set_bias_level(struct snd_soc_codec *codec, 2482 static int wm8962_set_bias_level(struct snd_soc_codec *codec,
2483 enum snd_soc_bias_level level) 2483 enum snd_soc_bias_level level)
2484 { 2484 {
2485 if (level == codec->dapm.bias_level) 2485 if (level == codec->dapm.bias_level)
2486 return 0; 2486 return 0;
2487 2487
2488 switch (level) { 2488 switch (level) {
2489 case SND_SOC_BIAS_ON: 2489 case SND_SOC_BIAS_ON:
2490 break; 2490 break;
2491 2491
2492 case SND_SOC_BIAS_PREPARE: 2492 case SND_SOC_BIAS_PREPARE:
2493 /* VMID 2*50k */ 2493 /* VMID 2*50k */
2494 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1, 2494 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2495 WM8962_VMID_SEL_MASK, 0x80); 2495 WM8962_VMID_SEL_MASK, 0x80);
2496 2496
2497 wm8962_configure_bclk(codec); 2497 wm8962_configure_bclk(codec);
2498 break; 2498 break;
2499 2499
2500 case SND_SOC_BIAS_STANDBY: 2500 case SND_SOC_BIAS_STANDBY:
2501 /* VMID 2*250k */ 2501 /* VMID 2*250k */
2502 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1, 2502 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2503 WM8962_VMID_SEL_MASK, 0x100); 2503 WM8962_VMID_SEL_MASK, 0x100);
2504 2504
2505 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) 2505 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
2506 msleep(100); 2506 msleep(100);
2507 break; 2507 break;
2508 2508
2509 case SND_SOC_BIAS_OFF: 2509 case SND_SOC_BIAS_OFF:
2510 break; 2510 break;
2511 } 2511 }
2512 2512
2513 codec->dapm.bias_level = level; 2513 codec->dapm.bias_level = level;
2514 return 0; 2514 return 0;
2515 } 2515 }
2516 2516
2517 static const struct { 2517 static const struct {
2518 int rate; 2518 int rate;
2519 int reg; 2519 int reg;
2520 } sr_vals[] = { 2520 } sr_vals[] = {
2521 { 48000, 0 }, 2521 { 48000, 0 },
2522 { 44100, 0 }, 2522 { 44100, 0 },
2523 { 32000, 1 }, 2523 { 32000, 1 },
2524 { 22050, 2 }, 2524 { 22050, 2 },
2525 { 24000, 2 }, 2525 { 24000, 2 },
2526 { 16000, 3 }, 2526 { 16000, 3 },
2527 { 11025, 4 }, 2527 { 11025, 4 },
2528 { 12000, 4 }, 2528 { 12000, 4 },
2529 { 8000, 5 }, 2529 { 8000, 5 },
2530 { 88200, 6 }, 2530 { 88200, 6 },
2531 { 96000, 6 }, 2531 { 96000, 6 },
2532 }; 2532 };
2533 2533
2534 static int wm8962_hw_params(struct snd_pcm_substream *substream, 2534 static int wm8962_hw_params(struct snd_pcm_substream *substream,
2535 struct snd_pcm_hw_params *params, 2535 struct snd_pcm_hw_params *params,
2536 struct snd_soc_dai *dai) 2536 struct snd_soc_dai *dai)
2537 { 2537 {
2538 struct snd_soc_codec *codec = dai->codec; 2538 struct snd_soc_codec *codec = dai->codec;
2539 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 2539 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2540 int i; 2540 int i;
2541 int aif0 = 0; 2541 int aif0 = 0;
2542 int adctl3 = 0; 2542 int adctl3 = 0;
2543 2543
2544 wm8962->bclk = snd_soc_params_to_bclk(params); 2544 wm8962->bclk = snd_soc_params_to_bclk(params);
2545 if (params_channels(params) == 1) 2545 if (params_channels(params) == 1)
2546 wm8962->bclk *= 2; 2546 wm8962->bclk *= 2;
2547 2547
2548 wm8962->lrclk = params_rate(params); 2548 wm8962->lrclk = params_rate(params);
2549 2549
2550 for (i = 0; i < ARRAY_SIZE(sr_vals); i++) { 2550 for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
2551 if (sr_vals[i].rate == wm8962->lrclk) { 2551 if (sr_vals[i].rate == wm8962->lrclk) {
2552 adctl3 |= sr_vals[i].reg; 2552 adctl3 |= sr_vals[i].reg;
2553 break; 2553 break;
2554 } 2554 }
2555 } 2555 }
2556 if (i == ARRAY_SIZE(sr_vals)) { 2556 if (i == ARRAY_SIZE(sr_vals)) {
2557 dev_err(codec->dev, "Unsupported rate %dHz\n", wm8962->lrclk); 2557 dev_err(codec->dev, "Unsupported rate %dHz\n", wm8962->lrclk);
2558 return -EINVAL; 2558 return -EINVAL;
2559 } 2559 }
2560 2560
2561 if (wm8962->lrclk % 8000 == 0) 2561 if (wm8962->lrclk % 8000 == 0)
2562 adctl3 |= WM8962_SAMPLE_RATE_INT_MODE; 2562 adctl3 |= WM8962_SAMPLE_RATE_INT_MODE;
2563 2563
2564 switch (params_format(params)) { 2564 switch (params_format(params)) {
2565 case SNDRV_PCM_FORMAT_S16_LE: 2565 case SNDRV_PCM_FORMAT_S16_LE:
2566 break; 2566 break;
2567 case SNDRV_PCM_FORMAT_S20_3LE: 2567 case SNDRV_PCM_FORMAT_S20_3LE:
2568 aif0 |= 0x4; 2568 aif0 |= 0x4;
2569 break; 2569 break;
2570 case SNDRV_PCM_FORMAT_S24_LE: 2570 case SNDRV_PCM_FORMAT_S24_LE:
2571 aif0 |= 0x8; 2571 aif0 |= 0x8;
2572 break; 2572 break;
2573 case SNDRV_PCM_FORMAT_S32_LE: 2573 case SNDRV_PCM_FORMAT_S32_LE:
2574 aif0 |= 0xc; 2574 aif0 |= 0xc;
2575 break; 2575 break;
2576 default: 2576 default:
2577 return -EINVAL; 2577 return -EINVAL;
2578 } 2578 }
2579 2579
2580 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0, 2580 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
2581 WM8962_WL_MASK, aif0); 2581 WM8962_WL_MASK, aif0);
2582 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_3, 2582 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_3,
2583 WM8962_SAMPLE_RATE_INT_MODE | 2583 WM8962_SAMPLE_RATE_INT_MODE |
2584 WM8962_SAMPLE_RATE_MASK, adctl3); 2584 WM8962_SAMPLE_RATE_MASK, adctl3);
2585 2585
2586 dev_dbg(codec->dev, "hw_params set BCLK %dHz LRCLK %dHz\n", 2586 dev_dbg(codec->dev, "hw_params set BCLK %dHz LRCLK %dHz\n",
2587 wm8962->bclk, wm8962->lrclk); 2587 wm8962->bclk, wm8962->lrclk);
2588 2588
2589 if (codec->dapm.bias_level == SND_SOC_BIAS_ON) 2589 if (codec->dapm.bias_level == SND_SOC_BIAS_ON)
2590 wm8962_configure_bclk(codec); 2590 wm8962_configure_bclk(codec);
2591 2591
2592 return 0; 2592 return 0;
2593 } 2593 }
2594 2594
2595 static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, 2595 static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2596 unsigned int freq, int dir) 2596 unsigned int freq, int dir)
2597 { 2597 {
2598 struct snd_soc_codec *codec = dai->codec; 2598 struct snd_soc_codec *codec = dai->codec;
2599 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 2599 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2600 int src; 2600 int src;
2601 2601
2602 switch (clk_id) { 2602 switch (clk_id) {
2603 case WM8962_SYSCLK_MCLK: 2603 case WM8962_SYSCLK_MCLK:
2604 wm8962->sysclk = WM8962_SYSCLK_MCLK; 2604 wm8962->sysclk = WM8962_SYSCLK_MCLK;
2605 src = 0; 2605 src = 0;
2606 break; 2606 break;
2607 case WM8962_SYSCLK_FLL: 2607 case WM8962_SYSCLK_FLL:
2608 wm8962->sysclk = WM8962_SYSCLK_FLL; 2608 wm8962->sysclk = WM8962_SYSCLK_FLL;
2609 src = 1 << WM8962_SYSCLK_SRC_SHIFT; 2609 src = 1 << WM8962_SYSCLK_SRC_SHIFT;
2610 break; 2610 break;
2611 default: 2611 default:
2612 return -EINVAL; 2612 return -EINVAL;
2613 } 2613 }
2614 2614
2615 snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK, 2615 snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK,
2616 src); 2616 src);
2617 2617
2618 wm8962->sysclk_rate = freq; 2618 wm8962->sysclk_rate = freq;
2619 2619
2620 wm8962_configure_bclk(codec); 2620 wm8962_configure_bclk(codec);
2621 2621
2622 return 0; 2622 return 0;
2623 } 2623 }
2624 2624
2625 static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2625 static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2626 { 2626 {
2627 struct snd_soc_codec *codec = dai->codec; 2627 struct snd_soc_codec *codec = dai->codec;
2628 int aif0 = 0; 2628 int aif0 = 0;
2629 2629
2630 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2630 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2631 case SND_SOC_DAIFMT_DSP_B: 2631 case SND_SOC_DAIFMT_DSP_B:
2632 aif0 |= WM8962_LRCLK_INV | 3; 2632 aif0 |= WM8962_LRCLK_INV | 3;
2633 case SND_SOC_DAIFMT_DSP_A: 2633 case SND_SOC_DAIFMT_DSP_A:
2634 aif0 |= 3; 2634 aif0 |= 3;
2635 2635
2636 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2636 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2637 case SND_SOC_DAIFMT_NB_NF: 2637 case SND_SOC_DAIFMT_NB_NF:
2638 case SND_SOC_DAIFMT_IB_NF: 2638 case SND_SOC_DAIFMT_IB_NF:
2639 break; 2639 break;
2640 default: 2640 default:
2641 return -EINVAL; 2641 return -EINVAL;
2642 } 2642 }
2643 break; 2643 break;
2644 2644
2645 case SND_SOC_DAIFMT_RIGHT_J: 2645 case SND_SOC_DAIFMT_RIGHT_J:
2646 break; 2646 break;
2647 case SND_SOC_DAIFMT_LEFT_J: 2647 case SND_SOC_DAIFMT_LEFT_J:
2648 aif0 |= 1; 2648 aif0 |= 1;
2649 break; 2649 break;
2650 case SND_SOC_DAIFMT_I2S: 2650 case SND_SOC_DAIFMT_I2S:
2651 aif0 |= 2; 2651 aif0 |= 2;
2652 break; 2652 break;
2653 default: 2653 default:
2654 return -EINVAL; 2654 return -EINVAL;
2655 } 2655 }
2656 2656
2657 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2657 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2658 case SND_SOC_DAIFMT_NB_NF: 2658 case SND_SOC_DAIFMT_NB_NF:
2659 break; 2659 break;
2660 case SND_SOC_DAIFMT_IB_NF: 2660 case SND_SOC_DAIFMT_IB_NF:
2661 aif0 |= WM8962_BCLK_INV; 2661 aif0 |= WM8962_BCLK_INV;
2662 break; 2662 break;
2663 case SND_SOC_DAIFMT_NB_IF: 2663 case SND_SOC_DAIFMT_NB_IF:
2664 aif0 |= WM8962_LRCLK_INV; 2664 aif0 |= WM8962_LRCLK_INV;
2665 break; 2665 break;
2666 case SND_SOC_DAIFMT_IB_IF: 2666 case SND_SOC_DAIFMT_IB_IF:
2667 aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV; 2667 aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV;
2668 break; 2668 break;
2669 default: 2669 default:
2670 return -EINVAL; 2670 return -EINVAL;
2671 } 2671 }
2672 2672
2673 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2673 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2674 case SND_SOC_DAIFMT_CBM_CFM: 2674 case SND_SOC_DAIFMT_CBM_CFM:
2675 aif0 |= WM8962_MSTR; 2675 aif0 |= WM8962_MSTR;
2676 break; 2676 break;
2677 case SND_SOC_DAIFMT_CBS_CFS: 2677 case SND_SOC_DAIFMT_CBS_CFS:
2678 break; 2678 break;
2679 default: 2679 default:
2680 return -EINVAL; 2680 return -EINVAL;
2681 } 2681 }
2682 2682
2683 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0, 2683 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
2684 WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR | 2684 WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR |
2685 WM8962_LRCLK_INV, aif0); 2685 WM8962_LRCLK_INV, aif0);
2686 2686
2687 return 0; 2687 return 0;
2688 } 2688 }
2689 2689
2690 struct _fll_div { 2690 struct _fll_div {
2691 u16 fll_fratio; 2691 u16 fll_fratio;
2692 u16 fll_outdiv; 2692 u16 fll_outdiv;
2693 u16 fll_refclk_div; 2693 u16 fll_refclk_div;
2694 u16 n; 2694 u16 n;
2695 u16 theta; 2695 u16 theta;
2696 u16 lambda; 2696 u16 lambda;
2697 }; 2697 };
2698 2698
2699 /* The size in bits of the FLL divide multiplied by 10 2699 /* The size in bits of the FLL divide multiplied by 10
2700 * to allow rounding later */ 2700 * to allow rounding later */
2701 #define FIXED_FLL_SIZE ((1 << 16) * 10) 2701 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2702 2702
2703 static struct { 2703 static struct {
2704 unsigned int min; 2704 unsigned int min;
2705 unsigned int max; 2705 unsigned int max;
2706 u16 fll_fratio; 2706 u16 fll_fratio;
2707 int ratio; 2707 int ratio;
2708 } fll_fratios[] = { 2708 } fll_fratios[] = {
2709 { 0, 64000, 4, 16 }, 2709 { 0, 64000, 4, 16 },
2710 { 64000, 128000, 3, 8 }, 2710 { 64000, 128000, 3, 8 },
2711 { 128000, 256000, 2, 4 }, 2711 { 128000, 256000, 2, 4 },
2712 { 256000, 1000000, 1, 2 }, 2712 { 256000, 1000000, 1, 2 },
2713 { 1000000, 13500000, 0, 1 }, 2713 { 1000000, 13500000, 0, 1 },
2714 }; 2714 };
2715 2715
2716 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, 2716 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
2717 unsigned int Fout) 2717 unsigned int Fout)
2718 { 2718 {
2719 unsigned int target; 2719 unsigned int target;
2720 unsigned int div; 2720 unsigned int div;
2721 unsigned int fratio, gcd_fll; 2721 unsigned int fratio, gcd_fll;
2722 int i; 2722 int i;
2723 2723
2724 /* Fref must be <=13.5MHz */ 2724 /* Fref must be <=13.5MHz */
2725 div = 1; 2725 div = 1;
2726 fll_div->fll_refclk_div = 0; 2726 fll_div->fll_refclk_div = 0;
2727 while ((Fref / div) > 13500000) { 2727 while ((Fref / div) > 13500000) {
2728 div *= 2; 2728 div *= 2;
2729 fll_div->fll_refclk_div++; 2729 fll_div->fll_refclk_div++;
2730 2730
2731 if (div > 4) { 2731 if (div > 4) {
2732 pr_err("Can't scale %dMHz input down to <=13.5MHz\n", 2732 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
2733 Fref); 2733 Fref);
2734 return -EINVAL; 2734 return -EINVAL;
2735 } 2735 }
2736 } 2736 }
2737 2737
2738 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout); 2738 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
2739 2739
2740 /* Apply the division for our remaining calculations */ 2740 /* Apply the division for our remaining calculations */
2741 Fref /= div; 2741 Fref /= div;
2742 2742
2743 /* Fvco should be 90-100MHz; don't check the upper bound */ 2743 /* Fvco should be 90-100MHz; don't check the upper bound */
2744 div = 2; 2744 div = 2;
2745 while (Fout * div < 90000000) { 2745 while (Fout * div < 90000000) {
2746 div++; 2746 div++;
2747 if (div > 64) { 2747 if (div > 64) {
2748 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", 2748 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
2749 Fout); 2749 Fout);
2750 return -EINVAL; 2750 return -EINVAL;
2751 } 2751 }
2752 } 2752 }
2753 target = Fout * div; 2753 target = Fout * div;
2754 fll_div->fll_outdiv = div - 1; 2754 fll_div->fll_outdiv = div - 1;
2755 2755
2756 pr_debug("FLL Fvco=%dHz\n", target); 2756 pr_debug("FLL Fvco=%dHz\n", target);
2757 2757
2758 /* Find an appropriate FLL_FRATIO and factor it out of the target */ 2758 /* Find an appropriate FLL_FRATIO and factor it out of the target */
2759 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { 2759 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
2760 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { 2760 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
2761 fll_div->fll_fratio = fll_fratios[i].fll_fratio; 2761 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
2762 fratio = fll_fratios[i].ratio; 2762 fratio = fll_fratios[i].ratio;
2763 break; 2763 break;
2764 } 2764 }
2765 } 2765 }
2766 if (i == ARRAY_SIZE(fll_fratios)) { 2766 if (i == ARRAY_SIZE(fll_fratios)) {
2767 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); 2767 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
2768 return -EINVAL; 2768 return -EINVAL;
2769 } 2769 }
2770 2770
2771 fll_div->n = target / (fratio * Fref); 2771 fll_div->n = target / (fratio * Fref);
2772 2772
2773 if (target % Fref == 0) { 2773 if (target % Fref == 0) {
2774 fll_div->theta = 0; 2774 fll_div->theta = 0;
2775 fll_div->lambda = 0; 2775 fll_div->lambda = 0;
2776 } else { 2776 } else {
2777 gcd_fll = gcd(target, fratio * Fref); 2777 gcd_fll = gcd(target, fratio * Fref);
2778 2778
2779 fll_div->theta = (target - (fll_div->n * fratio * Fref)) 2779 fll_div->theta = (target - (fll_div->n * fratio * Fref))
2780 / gcd_fll; 2780 / gcd_fll;
2781 fll_div->lambda = (fratio * Fref) / gcd_fll; 2781 fll_div->lambda = (fratio * Fref) / gcd_fll;
2782 } 2782 }
2783 2783
2784 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n", 2784 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
2785 fll_div->n, fll_div->theta, fll_div->lambda); 2785 fll_div->n, fll_div->theta, fll_div->lambda);
2786 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n", 2786 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2787 fll_div->fll_fratio, fll_div->fll_outdiv, 2787 fll_div->fll_fratio, fll_div->fll_outdiv,
2788 fll_div->fll_refclk_div); 2788 fll_div->fll_refclk_div);
2789 2789
2790 return 0; 2790 return 0;
2791 } 2791 }
2792 2792
2793 static int wm8962_set_fll(struct snd_soc_codec *codec, int fll_id, int source, 2793 static int wm8962_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
2794 unsigned int Fref, unsigned int Fout) 2794 unsigned int Fref, unsigned int Fout)
2795 { 2795 {
2796 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 2796 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2797 struct _fll_div fll_div; 2797 struct _fll_div fll_div;
2798 unsigned long timeout; 2798 unsigned long timeout;
2799 int ret; 2799 int ret;
2800 int fll1 = 0; 2800 int fll1 = 0;
2801 2801
2802 /* Any change? */ 2802 /* Any change? */
2803 if (source == wm8962->fll_src && Fref == wm8962->fll_fref && 2803 if (source == wm8962->fll_src && Fref == wm8962->fll_fref &&
2804 Fout == wm8962->fll_fout) 2804 Fout == wm8962->fll_fout)
2805 return 0; 2805 return 0;
2806 2806
2807 if (Fout == 0) { 2807 if (Fout == 0) {
2808 dev_dbg(codec->dev, "FLL disabled\n"); 2808 dev_dbg(codec->dev, "FLL disabled\n");
2809 2809
2810 wm8962->fll_fref = 0; 2810 wm8962->fll_fref = 0;
2811 wm8962->fll_fout = 0; 2811 wm8962->fll_fout = 0;
2812 2812
2813 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, 2813 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2814 WM8962_FLL_ENA, 0); 2814 WM8962_FLL_ENA, 0);
2815 2815
2816 pm_runtime_put(codec->dev); 2816 pm_runtime_put(codec->dev);
2817 2817
2818 return 0; 2818 return 0;
2819 } 2819 }
2820 2820
2821 ret = fll_factors(&fll_div, Fref, Fout); 2821 ret = fll_factors(&fll_div, Fref, Fout);
2822 if (ret != 0) 2822 if (ret != 0)
2823 return ret; 2823 return ret;
2824 2824
2825 /* Parameters good, disable so we can reprogram */ 2825 /* Parameters good, disable so we can reprogram */
2826 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0); 2826 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2827 2827
2828 switch (fll_id) { 2828 switch (fll_id) {
2829 case WM8962_FLL_MCLK: 2829 case WM8962_FLL_MCLK:
2830 case WM8962_FLL_BCLK: 2830 case WM8962_FLL_BCLK:
2831 case WM8962_FLL_OSC: 2831 case WM8962_FLL_OSC:
2832 fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT; 2832 fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT;
2833 break; 2833 break;
2834 case WM8962_FLL_INT: 2834 case WM8962_FLL_INT:
2835 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, 2835 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2836 WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA); 2836 WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA);
2837 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_5, 2837 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_5,
2838 WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO); 2838 WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO);
2839 break; 2839 break;
2840 default: 2840 default:
2841 dev_err(codec->dev, "Unknown FLL source %d\n", ret); 2841 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2842 return -EINVAL; 2842 return -EINVAL;
2843 } 2843 }
2844 2844
2845 if (fll_div.theta || fll_div.lambda) 2845 if (fll_div.theta || fll_div.lambda)
2846 fll1 |= WM8962_FLL_FRAC; 2846 fll1 |= WM8962_FLL_FRAC;
2847 2847
2848 /* Stop the FLL while we reconfigure */ 2848 /* Stop the FLL while we reconfigure */
2849 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0); 2849 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2850 2850
2851 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_2, 2851 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_2,
2852 WM8962_FLL_OUTDIV_MASK | 2852 WM8962_FLL_OUTDIV_MASK |
2853 WM8962_FLL_REFCLK_DIV_MASK, 2853 WM8962_FLL_REFCLK_DIV_MASK,
2854 (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) | 2854 (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) |
2855 (fll_div.fll_refclk_div)); 2855 (fll_div.fll_refclk_div));
2856 2856
2857 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_3, 2857 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_3,
2858 WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio); 2858 WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio);
2859 2859
2860 snd_soc_write(codec, WM8962_FLL_CONTROL_6, fll_div.theta); 2860 snd_soc_write(codec, WM8962_FLL_CONTROL_6, fll_div.theta);
2861 snd_soc_write(codec, WM8962_FLL_CONTROL_7, fll_div.lambda); 2861 snd_soc_write(codec, WM8962_FLL_CONTROL_7, fll_div.lambda);
2862 snd_soc_write(codec, WM8962_FLL_CONTROL_8, fll_div.n); 2862 snd_soc_write(codec, WM8962_FLL_CONTROL_8, fll_div.n);
2863 2863
2864 try_wait_for_completion(&wm8962->fll_lock); 2864 try_wait_for_completion(&wm8962->fll_lock);
2865 2865
2866 pm_runtime_get_sync(codec->dev); 2866 pm_runtime_get_sync(codec->dev);
2867 2867
2868 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, 2868 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2869 WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK | 2869 WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK |
2870 WM8962_FLL_ENA, fll1 | WM8962_FLL_ENA); 2870 WM8962_FLL_ENA, fll1 | WM8962_FLL_ENA);
2871 2871
2872 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); 2872 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2873 2873
2874 ret = 0; 2874 ret = 0;
2875 2875
2876 if (fll1 & WM8962_FLL_ENA) { 2876 if (fll1 & WM8962_FLL_ENA) {
2877 /* This should be a massive overestimate but go even 2877 /* This should be a massive overestimate but go even
2878 * higher if we'll error out 2878 * higher if we'll error out
2879 */ 2879 */
2880 if (wm8962->irq) 2880 if (wm8962->irq)
2881 timeout = msecs_to_jiffies(5); 2881 timeout = msecs_to_jiffies(5);
2882 else 2882 else
2883 timeout = msecs_to_jiffies(1); 2883 timeout = msecs_to_jiffies(1);
2884 2884
2885 timeout = wait_for_completion_timeout(&wm8962->fll_lock, 2885 timeout = wait_for_completion_timeout(&wm8962->fll_lock,
2886 timeout); 2886 timeout);
2887 2887
2888 if (timeout == 0 && wm8962->irq) { 2888 if (timeout == 0 && wm8962->irq) {
2889 dev_err(codec->dev, "FLL lock timed out"); 2889 dev_err(codec->dev, "FLL lock timed out");
2890 ret = -ETIMEDOUT; 2890 ret = -ETIMEDOUT;
2891 } 2891 }
2892 } 2892 }
2893 2893
2894 wm8962->fll_fref = Fref; 2894 wm8962->fll_fref = Fref;
2895 wm8962->fll_fout = Fout; 2895 wm8962->fll_fout = Fout;
2896 wm8962->fll_src = source; 2896 wm8962->fll_src = source;
2897 2897
2898 return ret; 2898 return ret;
2899 } 2899 }
2900 2900
2901 static int wm8962_mute(struct snd_soc_dai *dai, int mute) 2901 static int wm8962_mute(struct snd_soc_dai *dai, int mute)
2902 { 2902 {
2903 struct snd_soc_codec *codec = dai->codec; 2903 struct snd_soc_codec *codec = dai->codec;
2904 int val; 2904 int val;
2905 2905
2906 if (mute) 2906 if (mute)
2907 val = WM8962_DAC_MUTE; 2907 val = WM8962_DAC_MUTE;
2908 else 2908 else
2909 val = 0; 2909 val = 0;
2910 2910
2911 return snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1, 2911 return snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
2912 WM8962_DAC_MUTE, val); 2912 WM8962_DAC_MUTE, val);
2913 } 2913 }
2914 2914
2915 #define WM8962_RATES SNDRV_PCM_RATE_8000_96000 2915 #define WM8962_RATES SNDRV_PCM_RATE_8000_96000
2916 2916
2917 #define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 2917 #define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2918 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 2918 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2919 2919
2920 static const struct snd_soc_dai_ops wm8962_dai_ops = { 2920 static const struct snd_soc_dai_ops wm8962_dai_ops = {
2921 .hw_params = wm8962_hw_params, 2921 .hw_params = wm8962_hw_params,
2922 .set_sysclk = wm8962_set_dai_sysclk, 2922 .set_sysclk = wm8962_set_dai_sysclk,
2923 .set_fmt = wm8962_set_dai_fmt, 2923 .set_fmt = wm8962_set_dai_fmt,
2924 .digital_mute = wm8962_mute, 2924 .digital_mute = wm8962_mute,
2925 }; 2925 };
2926 2926
2927 static struct snd_soc_dai_driver wm8962_dai = { 2927 static struct snd_soc_dai_driver wm8962_dai = {
2928 .name = "wm8962", 2928 .name = "wm8962",
2929 .playback = { 2929 .playback = {
2930 .stream_name = "Playback", 2930 .stream_name = "Playback",
2931 .channels_min = 1, 2931 .channels_min = 1,
2932 .channels_max = 2, 2932 .channels_max = 2,
2933 .rates = WM8962_RATES, 2933 .rates = WM8962_RATES,
2934 .formats = WM8962_FORMATS, 2934 .formats = WM8962_FORMATS,
2935 }, 2935 },
2936 .capture = { 2936 .capture = {
2937 .stream_name = "Capture", 2937 .stream_name = "Capture",
2938 .channels_min = 1, 2938 .channels_min = 1,
2939 .channels_max = 2, 2939 .channels_max = 2,
2940 .rates = WM8962_RATES, 2940 .rates = WM8962_RATES,
2941 .formats = WM8962_FORMATS, 2941 .formats = WM8962_FORMATS,
2942 }, 2942 },
2943 .ops = &wm8962_dai_ops, 2943 .ops = &wm8962_dai_ops,
2944 .symmetric_rates = 1, 2944 .symmetric_rates = 1,
2945 }; 2945 };
2946 2946
2947 static void wm8962_mic_work(struct work_struct *work) 2947 static void wm8962_mic_work(struct work_struct *work)
2948 { 2948 {
2949 struct wm8962_priv *wm8962 = container_of(work, 2949 struct wm8962_priv *wm8962 = container_of(work,
2950 struct wm8962_priv, 2950 struct wm8962_priv,
2951 mic_work.work); 2951 mic_work.work);
2952 struct snd_soc_codec *codec = wm8962->codec; 2952 struct snd_soc_codec *codec = wm8962->codec;
2953 int status = 0; 2953 int status = 0;
2954 int irq_pol = 0; 2954 int irq_pol = 0;
2955 int reg; 2955 int reg;
2956 2956
2957 reg = snd_soc_read(codec, WM8962_ADDITIONAL_CONTROL_4); 2957 reg = snd_soc_read(codec, WM8962_ADDITIONAL_CONTROL_4);
2958 2958
2959 if (reg & WM8962_MICDET_STS) { 2959 if (reg & WM8962_MICDET_STS) {
2960 status |= SND_JACK_MICROPHONE; 2960 status |= SND_JACK_MICROPHONE;
2961 irq_pol |= WM8962_MICD_IRQ_POL; 2961 irq_pol |= WM8962_MICD_IRQ_POL;
2962 } 2962 }
2963 2963
2964 if (reg & WM8962_MICSHORT_STS) { 2964 if (reg & WM8962_MICSHORT_STS) {
2965 status |= SND_JACK_BTN_0; 2965 status |= SND_JACK_BTN_0;
2966 irq_pol |= WM8962_MICSCD_IRQ_POL; 2966 irq_pol |= WM8962_MICSCD_IRQ_POL;
2967 } 2967 }
2968 2968
2969 snd_soc_jack_report(wm8962->jack, status, 2969 snd_soc_jack_report(wm8962->jack, status,
2970 SND_JACK_MICROPHONE | SND_JACK_BTN_0); 2970 SND_JACK_MICROPHONE | SND_JACK_BTN_0);
2971 2971
2972 snd_soc_update_bits(codec, WM8962_MICINT_SOURCE_POL, 2972 snd_soc_update_bits(codec, WM8962_MICINT_SOURCE_POL,
2973 WM8962_MICSCD_IRQ_POL | 2973 WM8962_MICSCD_IRQ_POL |
2974 WM8962_MICD_IRQ_POL, irq_pol); 2974 WM8962_MICD_IRQ_POL, irq_pol);
2975 } 2975 }
2976 2976
2977 static irqreturn_t wm8962_irq(int irq, void *data) 2977 static irqreturn_t wm8962_irq(int irq, void *data)
2978 { 2978 {
2979 struct device *dev = data; 2979 struct device *dev = data;
2980 struct wm8962_priv *wm8962 = dev_get_drvdata(dev); 2980 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
2981 unsigned int mask; 2981 unsigned int mask;
2982 unsigned int active; 2982 unsigned int active;
2983 int reg, ret; 2983 int reg, ret;
2984 2984
2985 ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2_MASK, 2985 ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2_MASK,
2986 &mask); 2986 &mask);
2987 if (ret != 0) { 2987 if (ret != 0) {
2988 dev_err(dev, "Failed to read interrupt mask: %d\n", 2988 dev_err(dev, "Failed to read interrupt mask: %d\n",
2989 ret); 2989 ret);
2990 return IRQ_NONE; 2990 return IRQ_NONE;
2991 } 2991 }
2992 2992
2993 ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, &active); 2993 ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, &active);
2994 if (ret != 0) { 2994 if (ret != 0) {
2995 dev_err(dev, "Failed to read interrupt: %d\n", ret); 2995 dev_err(dev, "Failed to read interrupt: %d\n", ret);
2996 return IRQ_NONE; 2996 return IRQ_NONE;
2997 } 2997 }
2998 2998
2999 active &= ~mask; 2999 active &= ~mask;
3000 3000
3001 if (!active) 3001 if (!active)
3002 return IRQ_NONE; 3002 return IRQ_NONE;
3003 3003
3004 /* Acknowledge the interrupts */ 3004 /* Acknowledge the interrupts */
3005 ret = regmap_write(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, active); 3005 ret = regmap_write(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, active);
3006 if (ret != 0) 3006 if (ret != 0)
3007 dev_warn(dev, "Failed to ack interrupt: %d\n", ret); 3007 dev_warn(dev, "Failed to ack interrupt: %d\n", ret);
3008 3008
3009 if (active & WM8962_FLL_LOCK_EINT) { 3009 if (active & WM8962_FLL_LOCK_EINT) {
3010 dev_dbg(dev, "FLL locked\n"); 3010 dev_dbg(dev, "FLL locked\n");
3011 complete(&wm8962->fll_lock); 3011 complete(&wm8962->fll_lock);
3012 } 3012 }
3013 3013
3014 if (active & WM8962_FIFOS_ERR_EINT) 3014 if (active & WM8962_FIFOS_ERR_EINT)
3015 dev_err(dev, "FIFO error\n"); 3015 dev_err(dev, "FIFO error\n");
3016 3016
3017 if (active & WM8962_TEMP_SHUT_EINT) { 3017 if (active & WM8962_TEMP_SHUT_EINT) {
3018 dev_crit(dev, "Thermal shutdown\n"); 3018 dev_crit(dev, "Thermal shutdown\n");
3019 3019
3020 ret = regmap_read(wm8962->regmap, 3020 ret = regmap_read(wm8962->regmap,
3021 WM8962_THERMAL_SHUTDOWN_STATUS, &reg); 3021 WM8962_THERMAL_SHUTDOWN_STATUS, &reg);
3022 if (ret != 0) { 3022 if (ret != 0) {
3023 dev_warn(dev, "Failed to read thermal status: %d\n", 3023 dev_warn(dev, "Failed to read thermal status: %d\n",
3024 ret); 3024 ret);
3025 reg = 0; 3025 reg = 0;
3026 } 3026 }
3027 3027
3028 if (reg & WM8962_TEMP_ERR_HP) 3028 if (reg & WM8962_TEMP_ERR_HP)
3029 dev_crit(dev, "Headphone thermal error\n"); 3029 dev_crit(dev, "Headphone thermal error\n");
3030 if (reg & WM8962_TEMP_WARN_HP) 3030 if (reg & WM8962_TEMP_WARN_HP)
3031 dev_crit(dev, "Headphone thermal warning\n"); 3031 dev_crit(dev, "Headphone thermal warning\n");
3032 if (reg & WM8962_TEMP_ERR_SPK) 3032 if (reg & WM8962_TEMP_ERR_SPK)
3033 dev_crit(dev, "Speaker thermal error\n"); 3033 dev_crit(dev, "Speaker thermal error\n");
3034 if (reg & WM8962_TEMP_WARN_SPK) 3034 if (reg & WM8962_TEMP_WARN_SPK)
3035 dev_crit(dev, "Speaker thermal warning\n"); 3035 dev_crit(dev, "Speaker thermal warning\n");
3036 } 3036 }
3037 3037
3038 if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) { 3038 if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) {
3039 dev_dbg(dev, "Microphone event detected\n"); 3039 dev_dbg(dev, "Microphone event detected\n");
3040 3040
3041 #ifndef CONFIG_SND_SOC_WM8962_MODULE 3041 #ifndef CONFIG_SND_SOC_WM8962_MODULE
3042 trace_snd_soc_jack_irq(dev_name(dev)); 3042 trace_snd_soc_jack_irq(dev_name(dev));
3043 #endif 3043 #endif
3044 3044
3045 pm_wakeup_event(dev, 300); 3045 pm_wakeup_event(dev, 300);
3046 3046
3047 schedule_delayed_work(&wm8962->mic_work, 3047 schedule_delayed_work(&wm8962->mic_work,
3048 msecs_to_jiffies(250)); 3048 msecs_to_jiffies(250));
3049 } 3049 }
3050 3050
3051 return IRQ_HANDLED; 3051 return IRQ_HANDLED;
3052 } 3052 }
3053 3053
3054 /** 3054 /**
3055 * wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ 3055 * wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ
3056 * 3056 *
3057 * @codec: WM8962 codec 3057 * @codec: WM8962 codec
3058 * @jack: jack to report detection events on 3058 * @jack: jack to report detection events on
3059 * 3059 *
3060 * Enable microphone detection via IRQ on the WM8962. If GPIOs are 3060 * Enable microphone detection via IRQ on the WM8962. If GPIOs are
3061 * being used to bring out signals to the processor then only platform 3061 * being used to bring out signals to the processor then only platform
3062 * data configuration is needed for WM8962 and processor GPIOs should 3062 * data configuration is needed for WM8962 and processor GPIOs should
3063 * be configured using snd_soc_jack_add_gpios() instead. 3063 * be configured using snd_soc_jack_add_gpios() instead.
3064 * 3064 *
3065 * If no jack is supplied detection will be disabled. 3065 * If no jack is supplied detection will be disabled.
3066 */ 3066 */
3067 int wm8962_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack) 3067 int wm8962_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
3068 { 3068 {
3069 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 3069 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3070 int irq_mask, enable; 3070 int irq_mask, enable;
3071 3071
3072 wm8962->jack = jack; 3072 wm8962->jack = jack;
3073 if (jack) { 3073 if (jack) {
3074 irq_mask = 0; 3074 irq_mask = 0;
3075 enable = WM8962_MICDET_ENA; 3075 enable = WM8962_MICDET_ENA;
3076 } else { 3076 } else {
3077 irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT; 3077 irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT;
3078 enable = 0; 3078 enable = 0;
3079 } 3079 }
3080 3080
3081 snd_soc_update_bits(codec, WM8962_INTERRUPT_STATUS_2_MASK, 3081 snd_soc_update_bits(codec, WM8962_INTERRUPT_STATUS_2_MASK,
3082 WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask); 3082 WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask);
3083 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4, 3083 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
3084 WM8962_MICDET_ENA, enable); 3084 WM8962_MICDET_ENA, enable);
3085 3085
3086 /* Send an initial empty report */ 3086 /* Send an initial empty report */
3087 snd_soc_jack_report(wm8962->jack, 0, 3087 snd_soc_jack_report(wm8962->jack, 0,
3088 SND_JACK_MICROPHONE | SND_JACK_BTN_0); 3088 SND_JACK_MICROPHONE | SND_JACK_BTN_0);
3089 3089
3090 if (jack) { 3090 if (jack) {
3091 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK"); 3091 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
3092 snd_soc_dapm_force_enable_pin(&codec->dapm, "MICBIAS"); 3092 snd_soc_dapm_force_enable_pin(&codec->dapm, "MICBIAS");
3093 } else { 3093 } else {
3094 snd_soc_dapm_disable_pin(&codec->dapm, "SYSCLK"); 3094 snd_soc_dapm_disable_pin(&codec->dapm, "SYSCLK");
3095 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS"); 3095 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS");
3096 } 3096 }
3097 3097
3098 return 0; 3098 return 0;
3099 } 3099 }
3100 EXPORT_SYMBOL_GPL(wm8962_mic_detect); 3100 EXPORT_SYMBOL_GPL(wm8962_mic_detect);
3101 3101
3102 #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE) 3102 #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
3103 static int beep_rates[] = { 3103 static int beep_rates[] = {
3104 500, 1000, 2000, 4000, 3104 500, 1000, 2000, 4000,
3105 }; 3105 };
3106 3106
3107 static void wm8962_beep_work(struct work_struct *work) 3107 static void wm8962_beep_work(struct work_struct *work)
3108 { 3108 {
3109 struct wm8962_priv *wm8962 = 3109 struct wm8962_priv *wm8962 =
3110 container_of(work, struct wm8962_priv, beep_work); 3110 container_of(work, struct wm8962_priv, beep_work);
3111 struct snd_soc_codec *codec = wm8962->codec; 3111 struct snd_soc_codec *codec = wm8962->codec;
3112 struct snd_soc_dapm_context *dapm = &codec->dapm; 3112 struct snd_soc_dapm_context *dapm = &codec->dapm;
3113 int i; 3113 int i;
3114 int reg = 0; 3114 int reg = 0;
3115 int best = 0; 3115 int best = 0;
3116 3116
3117 if (wm8962->beep_rate) { 3117 if (wm8962->beep_rate) {
3118 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) { 3118 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
3119 if (abs(wm8962->beep_rate - beep_rates[i]) < 3119 if (abs(wm8962->beep_rate - beep_rates[i]) <
3120 abs(wm8962->beep_rate - beep_rates[best])) 3120 abs(wm8962->beep_rate - beep_rates[best]))
3121 best = i; 3121 best = i;
3122 } 3122 }
3123 3123
3124 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n", 3124 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
3125 beep_rates[best], wm8962->beep_rate); 3125 beep_rates[best], wm8962->beep_rate);
3126 3126
3127 reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT); 3127 reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT);
3128 3128
3129 snd_soc_dapm_enable_pin(dapm, "Beep"); 3129 snd_soc_dapm_enable_pin(dapm, "Beep");
3130 } else { 3130 } else {
3131 dev_dbg(codec->dev, "Disabling beep\n"); 3131 dev_dbg(codec->dev, "Disabling beep\n");
3132 snd_soc_dapm_disable_pin(dapm, "Beep"); 3132 snd_soc_dapm_disable_pin(dapm, "Beep");
3133 } 3133 }
3134 3134
3135 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, 3135 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1,
3136 WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg); 3136 WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg);
3137 3137
3138 snd_soc_dapm_sync(dapm); 3138 snd_soc_dapm_sync(dapm);
3139 } 3139 }
3140 3140
3141 /* For usability define a way of injecting beep events for the device - 3141 /* For usability define a way of injecting beep events for the device -
3142 * many systems will not have a keyboard. 3142 * many systems will not have a keyboard.
3143 */ 3143 */
3144 static int wm8962_beep_event(struct input_dev *dev, unsigned int type, 3144 static int wm8962_beep_event(struct input_dev *dev, unsigned int type,
3145 unsigned int code, int hz) 3145 unsigned int code, int hz)
3146 { 3146 {
3147 struct snd_soc_codec *codec = input_get_drvdata(dev); 3147 struct snd_soc_codec *codec = input_get_drvdata(dev);
3148 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 3148 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3149 3149
3150 dev_dbg(codec->dev, "Beep event %x %x\n", code, hz); 3150 dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
3151 3151
3152 switch (code) { 3152 switch (code) {
3153 case SND_BELL: 3153 case SND_BELL:
3154 if (hz) 3154 if (hz)
3155 hz = 1000; 3155 hz = 1000;
3156 case SND_TONE: 3156 case SND_TONE:
3157 break; 3157 break;
3158 default: 3158 default:
3159 return -1; 3159 return -1;
3160 } 3160 }
3161 3161
3162 /* Kick the beep from a workqueue */ 3162 /* Kick the beep from a workqueue */
3163 wm8962->beep_rate = hz; 3163 wm8962->beep_rate = hz;
3164 schedule_work(&wm8962->beep_work); 3164 schedule_work(&wm8962->beep_work);
3165 return 0; 3165 return 0;
3166 } 3166 }
3167 3167
3168 static ssize_t wm8962_beep_set(struct device *dev, 3168 static ssize_t wm8962_beep_set(struct device *dev,
3169 struct device_attribute *attr, 3169 struct device_attribute *attr,
3170 const char *buf, size_t count) 3170 const char *buf, size_t count)
3171 { 3171 {
3172 struct wm8962_priv *wm8962 = dev_get_drvdata(dev); 3172 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3173 long int time; 3173 long int time;
3174 int ret; 3174 int ret;
3175 3175
3176 ret = strict_strtol(buf, 10, &time); 3176 ret = strict_strtol(buf, 10, &time);
3177 if (ret != 0) 3177 if (ret != 0)
3178 return ret; 3178 return ret;
3179 3179
3180 input_event(wm8962->beep, EV_SND, SND_TONE, time); 3180 input_event(wm8962->beep, EV_SND, SND_TONE, time);
3181 3181
3182 return count; 3182 return count;
3183 } 3183 }
3184 3184
3185 static DEVICE_ATTR(beep, 0200, NULL, wm8962_beep_set); 3185 static DEVICE_ATTR(beep, 0200, NULL, wm8962_beep_set);
3186 3186
3187 static void wm8962_init_beep(struct snd_soc_codec *codec) 3187 static void wm8962_init_beep(struct snd_soc_codec *codec)
3188 { 3188 {
3189 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 3189 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3190 int ret; 3190 int ret;
3191 3191
3192 wm8962->beep = input_allocate_device(); 3192 wm8962->beep = input_allocate_device();
3193 if (!wm8962->beep) { 3193 if (!wm8962->beep) {
3194 dev_err(codec->dev, "Failed to allocate beep device\n"); 3194 dev_err(codec->dev, "Failed to allocate beep device\n");
3195 return; 3195 return;
3196 } 3196 }
3197 3197
3198 INIT_WORK(&wm8962->beep_work, wm8962_beep_work); 3198 INIT_WORK(&wm8962->beep_work, wm8962_beep_work);
3199 wm8962->beep_rate = 0; 3199 wm8962->beep_rate = 0;
3200 3200
3201 wm8962->beep->name = "WM8962 Beep Generator"; 3201 wm8962->beep->name = "WM8962 Beep Generator";
3202 wm8962->beep->phys = dev_name(codec->dev); 3202 wm8962->beep->phys = dev_name(codec->dev);
3203 wm8962->beep->id.bustype = BUS_I2C; 3203 wm8962->beep->id.bustype = BUS_I2C;
3204 3204
3205 wm8962->beep->evbit[0] = BIT_MASK(EV_SND); 3205 wm8962->beep->evbit[0] = BIT_MASK(EV_SND);
3206 wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE); 3206 wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
3207 wm8962->beep->event = wm8962_beep_event; 3207 wm8962->beep->event = wm8962_beep_event;
3208 wm8962->beep->dev.parent = codec->dev; 3208 wm8962->beep->dev.parent = codec->dev;
3209 input_set_drvdata(wm8962->beep, codec); 3209 input_set_drvdata(wm8962->beep, codec);
3210 3210
3211 ret = input_register_device(wm8962->beep); 3211 ret = input_register_device(wm8962->beep);
3212 if (ret != 0) { 3212 if (ret != 0) {
3213 input_free_device(wm8962->beep); 3213 input_free_device(wm8962->beep);
3214 wm8962->beep = NULL; 3214 wm8962->beep = NULL;
3215 dev_err(codec->dev, "Failed to register beep device\n"); 3215 dev_err(codec->dev, "Failed to register beep device\n");
3216 } 3216 }
3217 3217
3218 ret = device_create_file(codec->dev, &dev_attr_beep); 3218 ret = device_create_file(codec->dev, &dev_attr_beep);
3219 if (ret != 0) { 3219 if (ret != 0) {
3220 dev_err(codec->dev, "Failed to create keyclick file: %d\n", 3220 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
3221 ret); 3221 ret);
3222 } 3222 }
3223 } 3223 }
3224 3224
3225 static void wm8962_free_beep(struct snd_soc_codec *codec) 3225 static void wm8962_free_beep(struct snd_soc_codec *codec)
3226 { 3226 {
3227 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 3227 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3228 3228
3229 device_remove_file(codec->dev, &dev_attr_beep); 3229 device_remove_file(codec->dev, &dev_attr_beep);
3230 input_unregister_device(wm8962->beep); 3230 input_unregister_device(wm8962->beep);
3231 cancel_work_sync(&wm8962->beep_work); 3231 cancel_work_sync(&wm8962->beep_work);
3232 wm8962->beep = NULL; 3232 wm8962->beep = NULL;
3233 3233
3234 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0); 3234 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0);
3235 } 3235 }
3236 #else 3236 #else
3237 static void wm8962_init_beep(struct snd_soc_codec *codec) 3237 static void wm8962_init_beep(struct snd_soc_codec *codec)
3238 { 3238 {
3239 } 3239 }
3240 3240
3241 static void wm8962_free_beep(struct snd_soc_codec *codec) 3241 static void wm8962_free_beep(struct snd_soc_codec *codec)
3242 { 3242 {
3243 } 3243 }
3244 #endif 3244 #endif
3245 3245
3246 static void wm8962_set_gpio_mode(struct snd_soc_codec *codec, int gpio) 3246 static void wm8962_set_gpio_mode(struct snd_soc_codec *codec, int gpio)
3247 { 3247 {
3248 int mask = 0; 3248 int mask = 0;
3249 int val = 0; 3249 int val = 0;
3250 3250
3251 /* Some of the GPIOs are behind MFP configuration and need to 3251 /* Some of the GPIOs are behind MFP configuration and need to
3252 * be put into GPIO mode. */ 3252 * be put into GPIO mode. */
3253 switch (gpio) { 3253 switch (gpio) {
3254 case 2: 3254 case 2:
3255 mask = WM8962_CLKOUT2_SEL_MASK; 3255 mask = WM8962_CLKOUT2_SEL_MASK;
3256 val = 1 << WM8962_CLKOUT2_SEL_SHIFT; 3256 val = 1 << WM8962_CLKOUT2_SEL_SHIFT;
3257 break; 3257 break;
3258 case 3: 3258 case 3:
3259 mask = WM8962_CLKOUT3_SEL_MASK; 3259 mask = WM8962_CLKOUT3_SEL_MASK;
3260 val = 1 << WM8962_CLKOUT3_SEL_SHIFT; 3260 val = 1 << WM8962_CLKOUT3_SEL_SHIFT;
3261 break; 3261 break;
3262 default: 3262 default:
3263 break; 3263 break;
3264 } 3264 }
3265 3265
3266 if (mask) 3266 if (mask)
3267 snd_soc_update_bits(codec, WM8962_ANALOGUE_CLOCKING1, 3267 snd_soc_update_bits(codec, WM8962_ANALOGUE_CLOCKING1,
3268 mask, val); 3268 mask, val);
3269 } 3269 }
3270 3270
3271 #ifdef CONFIG_GPIOLIB 3271 #ifdef CONFIG_GPIOLIB
3272 static inline struct wm8962_priv *gpio_to_wm8962(struct gpio_chip *chip) 3272 static inline struct wm8962_priv *gpio_to_wm8962(struct gpio_chip *chip)
3273 { 3273 {
3274 return container_of(chip, struct wm8962_priv, gpio_chip); 3274 return container_of(chip, struct wm8962_priv, gpio_chip);
3275 } 3275 }
3276 3276
3277 static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset) 3277 static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset)
3278 { 3278 {
3279 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip); 3279 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3280 struct snd_soc_codec *codec = wm8962->codec; 3280 struct snd_soc_codec *codec = wm8962->codec;
3281 3281
3282 /* The WM8962 GPIOs aren't linearly numbered. For simplicity 3282 /* The WM8962 GPIOs aren't linearly numbered. For simplicity
3283 * we export linear numbers and error out if the unsupported 3283 * we export linear numbers and error out if the unsupported
3284 * ones are requsted. 3284 * ones are requsted.
3285 */ 3285 */
3286 switch (offset + 1) { 3286 switch (offset + 1) {
3287 case 2: 3287 case 2:
3288 case 3: 3288 case 3:
3289 case 5: 3289 case 5:
3290 case 6: 3290 case 6:
3291 break; 3291 break;
3292 default: 3292 default:
3293 return -EINVAL; 3293 return -EINVAL;
3294 } 3294 }
3295 3295
3296 wm8962_set_gpio_mode(codec, offset + 1); 3296 wm8962_set_gpio_mode(codec, offset + 1);
3297 3297
3298 return 0; 3298 return 0;
3299 } 3299 }
3300 3300
3301 static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 3301 static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3302 { 3302 {
3303 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip); 3303 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3304 struct snd_soc_codec *codec = wm8962->codec; 3304 struct snd_soc_codec *codec = wm8962->codec;
3305 3305
3306 snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset, 3306 snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
3307 WM8962_GP2_LVL, !!value << WM8962_GP2_LVL_SHIFT); 3307 WM8962_GP2_LVL, !!value << WM8962_GP2_LVL_SHIFT);
3308 } 3308 }
3309 3309
3310 static int wm8962_gpio_direction_out(struct gpio_chip *chip, 3310 static int wm8962_gpio_direction_out(struct gpio_chip *chip,
3311 unsigned offset, int value) 3311 unsigned offset, int value)
3312 { 3312 {
3313 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip); 3313 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3314 struct snd_soc_codec *codec = wm8962->codec; 3314 struct snd_soc_codec *codec = wm8962->codec;
3315 int ret, val; 3315 int ret, val;
3316 3316
3317 /* Force function 1 (logic output) */ 3317 /* Force function 1 (logic output) */
3318 val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT); 3318 val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT);
3319 3319
3320 ret = snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset, 3320 ret = snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
3321 WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val); 3321 WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val);
3322 if (ret < 0) 3322 if (ret < 0)
3323 return ret; 3323 return ret;
3324 3324
3325 return 0; 3325 return 0;
3326 } 3326 }
3327 3327
3328 static struct gpio_chip wm8962_template_chip = { 3328 static struct gpio_chip wm8962_template_chip = {
3329 .label = "wm8962", 3329 .label = "wm8962",
3330 .owner = THIS_MODULE, 3330 .owner = THIS_MODULE,
3331 .request = wm8962_gpio_request, 3331 .request = wm8962_gpio_request,
3332 .direction_output = wm8962_gpio_direction_out, 3332 .direction_output = wm8962_gpio_direction_out,
3333 .set = wm8962_gpio_set, 3333 .set = wm8962_gpio_set,
3334 .can_sleep = 1, 3334 .can_sleep = 1,
3335 }; 3335 };
3336 3336
3337 static void wm8962_init_gpio(struct snd_soc_codec *codec) 3337 static void wm8962_init_gpio(struct snd_soc_codec *codec)
3338 { 3338 {
3339 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 3339 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3340 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev); 3340 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
3341 int ret; 3341 int ret;
3342 3342
3343 wm8962->gpio_chip = wm8962_template_chip; 3343 wm8962->gpio_chip = wm8962_template_chip;
3344 wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO; 3344 wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO;
3345 wm8962->gpio_chip.dev = codec->dev; 3345 wm8962->gpio_chip.dev = codec->dev;
3346 3346
3347 if (pdata && pdata->gpio_base) 3347 if (pdata && pdata->gpio_base)
3348 wm8962->gpio_chip.base = pdata->gpio_base; 3348 wm8962->gpio_chip.base = pdata->gpio_base;
3349 else 3349 else
3350 wm8962->gpio_chip.base = -1; 3350 wm8962->gpio_chip.base = -1;
3351 3351
3352 ret = gpiochip_add(&wm8962->gpio_chip); 3352 ret = gpiochip_add(&wm8962->gpio_chip);
3353 if (ret != 0) 3353 if (ret != 0)
3354 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret); 3354 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
3355 } 3355 }
3356 3356
3357 static void wm8962_free_gpio(struct snd_soc_codec *codec) 3357 static void wm8962_free_gpio(struct snd_soc_codec *codec)
3358 { 3358 {
3359 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 3359 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3360 int ret; 3360 int ret;
3361 3361
3362 ret = gpiochip_remove(&wm8962->gpio_chip); 3362 ret = gpiochip_remove(&wm8962->gpio_chip);
3363 if (ret != 0) 3363 if (ret != 0)
3364 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret); 3364 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
3365 } 3365 }
3366 #else 3366 #else
3367 static void wm8962_init_gpio(struct snd_soc_codec *codec) 3367 static void wm8962_init_gpio(struct snd_soc_codec *codec)
3368 { 3368 {
3369 } 3369 }
3370 3370
3371 static void wm8962_free_gpio(struct snd_soc_codec *codec) 3371 static void wm8962_free_gpio(struct snd_soc_codec *codec)
3372 { 3372 {
3373 } 3373 }
3374 #endif 3374 #endif
3375 3375
3376 static int wm8962_probe(struct snd_soc_codec *codec) 3376 static int wm8962_probe(struct snd_soc_codec *codec)
3377 { 3377 {
3378 int ret; 3378 int ret;
3379 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 3379 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3380 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev); 3380 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
3381 u16 *reg_cache = codec->reg_cache; 3381 u16 *reg_cache = codec->reg_cache;
3382 int i, trigger, irq_pol; 3382 int i, trigger, irq_pol;
3383 bool dmicclk, dmicdat; 3383 bool dmicclk, dmicdat;
3384 3384
3385 wm8962->codec = codec; 3385 wm8962->codec = codec;
3386 codec->control_data = wm8962->regmap; 3386 codec->control_data = wm8962->regmap;
3387 3387
3388 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP); 3388 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
3389 if (ret != 0) { 3389 if (ret != 0) {
3390 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 3390 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
3391 return ret; 3391 return ret;
3392 } 3392 }
3393 3393
3394 wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0; 3394 wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0;
3395 wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1; 3395 wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1;
3396 wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2; 3396 wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2;
3397 wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3; 3397 wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3;
3398 wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4; 3398 wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4;
3399 wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5; 3399 wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5;
3400 wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6; 3400 wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6;
3401 wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7; 3401 wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7;
3402 3402
3403 /* This should really be moved into the regulator core */ 3403 /* This should really be moved into the regulator core */
3404 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) { 3404 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) {
3405 ret = regulator_register_notifier(wm8962->supplies[i].consumer, 3405 ret = regulator_register_notifier(wm8962->supplies[i].consumer,
3406 &wm8962->disable_nb[i]); 3406 &wm8962->disable_nb[i]);
3407 if (ret != 0) { 3407 if (ret != 0) {
3408 dev_err(codec->dev, 3408 dev_err(codec->dev,
3409 "Failed to register regulator notifier: %d\n", 3409 "Failed to register regulator notifier: %d\n",
3410 ret); 3410 ret);
3411 } 3411 }
3412 } 3412 }
3413 3413
3414 /* SYSCLK defaults to on; make sure it is off so we can safely 3414 /* SYSCLK defaults to on; make sure it is off so we can safely
3415 * write to registers if the device is declocked. 3415 * write to registers if the device is declocked.
3416 */ 3416 */
3417 snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_ENA, 0); 3417 snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_ENA, 0);
3418 3418
3419 /* Ensure we have soft control over all registers */ 3419 /* Ensure we have soft control over all registers */
3420 snd_soc_update_bits(codec, WM8962_CLOCKING2, 3420 snd_soc_update_bits(codec, WM8962_CLOCKING2,
3421 WM8962_CLKREG_OVD, WM8962_CLKREG_OVD); 3421 WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
3422 3422
3423 /* Ensure that the oscillator and PLLs are disabled */ 3423 /* Ensure that the oscillator and PLLs are disabled */
3424 snd_soc_update_bits(codec, WM8962_PLL2, 3424 snd_soc_update_bits(codec, WM8962_PLL2,
3425 WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA, 3425 WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
3426 0); 3426 0);
3427 3427
3428 if (pdata) { 3428 if (pdata) {
3429 /* Apply static configuration for GPIOs */ 3429 /* Apply static configuration for GPIOs */
3430 for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++) 3430 for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++)
3431 if (pdata->gpio_init[i]) { 3431 if (pdata->gpio_init[i]) {
3432 wm8962_set_gpio_mode(codec, i + 1); 3432 wm8962_set_gpio_mode(codec, i + 1);
3433 snd_soc_write(codec, 0x200 + i, 3433 snd_soc_write(codec, 0x200 + i,
3434 pdata->gpio_init[i] & 0xffff); 3434 pdata->gpio_init[i] & 0xffff);
3435 } 3435 }
3436 3436
3437 /* Put the speakers into mono mode? */ 3437 /* Put the speakers into mono mode? */
3438 if (pdata->spk_mono) 3438 if (pdata->spk_mono)
3439 reg_cache[WM8962_CLASS_D_CONTROL_2] 3439 reg_cache[WM8962_CLASS_D_CONTROL_2]
3440 |= WM8962_SPK_MONO; 3440 |= WM8962_SPK_MONO;
3441 3441
3442 /* Micbias setup, detection enable and detection 3442 /* Micbias setup, detection enable and detection
3443 * threasholds. */ 3443 * threasholds. */
3444 if (pdata->mic_cfg) 3444 if (pdata->mic_cfg)
3445 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4, 3445 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
3446 WM8962_MICDET_ENA | 3446 WM8962_MICDET_ENA |
3447 WM8962_MICDET_THR_MASK | 3447 WM8962_MICDET_THR_MASK |
3448 WM8962_MICSHORT_THR_MASK | 3448 WM8962_MICSHORT_THR_MASK |
3449 WM8962_MICBIAS_LVL, 3449 WM8962_MICBIAS_LVL,
3450 pdata->mic_cfg); 3450 pdata->mic_cfg);
3451 } 3451 }
3452 3452
3453 /* Latch volume update bits */ 3453 /* Latch volume update bits */
3454 snd_soc_update_bits(codec, WM8962_LEFT_INPUT_VOLUME, 3454 snd_soc_update_bits(codec, WM8962_LEFT_INPUT_VOLUME,
3455 WM8962_IN_VU, WM8962_IN_VU); 3455 WM8962_IN_VU, WM8962_IN_VU);
3456 snd_soc_update_bits(codec, WM8962_RIGHT_INPUT_VOLUME, 3456 snd_soc_update_bits(codec, WM8962_RIGHT_INPUT_VOLUME,
3457 WM8962_IN_VU, WM8962_IN_VU); 3457 WM8962_IN_VU, WM8962_IN_VU);
3458 snd_soc_update_bits(codec, WM8962_LEFT_ADC_VOLUME, 3458 snd_soc_update_bits(codec, WM8962_LEFT_ADC_VOLUME,
3459 WM8962_ADC_VU, WM8962_ADC_VU); 3459 WM8962_ADC_VU, WM8962_ADC_VU);
3460 snd_soc_update_bits(codec, WM8962_RIGHT_ADC_VOLUME, 3460 snd_soc_update_bits(codec, WM8962_RIGHT_ADC_VOLUME,
3461 WM8962_ADC_VU, WM8962_ADC_VU); 3461 WM8962_ADC_VU, WM8962_ADC_VU);
3462 snd_soc_update_bits(codec, WM8962_LEFT_DAC_VOLUME, 3462 snd_soc_update_bits(codec, WM8962_LEFT_DAC_VOLUME,
3463 WM8962_DAC_VU, WM8962_DAC_VU); 3463 WM8962_DAC_VU, WM8962_DAC_VU);
3464 snd_soc_update_bits(codec, WM8962_RIGHT_DAC_VOLUME, 3464 snd_soc_update_bits(codec, WM8962_RIGHT_DAC_VOLUME,
3465 WM8962_DAC_VU, WM8962_DAC_VU); 3465 WM8962_DAC_VU, WM8962_DAC_VU);
3466 snd_soc_update_bits(codec, WM8962_SPKOUTL_VOLUME, 3466 snd_soc_update_bits(codec, WM8962_SPKOUTL_VOLUME,
3467 WM8962_SPKOUT_VU, WM8962_SPKOUT_VU); 3467 WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3468 snd_soc_update_bits(codec, WM8962_SPKOUTR_VOLUME, 3468 snd_soc_update_bits(codec, WM8962_SPKOUTR_VOLUME,
3469 WM8962_SPKOUT_VU, WM8962_SPKOUT_VU); 3469 WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3470 snd_soc_update_bits(codec, WM8962_HPOUTL_VOLUME, 3470 snd_soc_update_bits(codec, WM8962_HPOUTL_VOLUME,
3471 WM8962_HPOUT_VU, WM8962_HPOUT_VU); 3471 WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3472 snd_soc_update_bits(codec, WM8962_HPOUTR_VOLUME, 3472 snd_soc_update_bits(codec, WM8962_HPOUTR_VOLUME,
3473 WM8962_HPOUT_VU, WM8962_HPOUT_VU); 3473 WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3474 3474
3475 /* Stereo control for EQ */ 3475 /* Stereo control for EQ */
3476 snd_soc_update_bits(codec, WM8962_EQ1, WM8962_EQ_SHARED_COEFF, 0); 3476 snd_soc_update_bits(codec, WM8962_EQ1, WM8962_EQ_SHARED_COEFF, 0);
3477 3477
3478 /* Don't debouce interrupts so we don't need SYSCLK */ 3478 /* Don't debouce interrupts so we don't need SYSCLK */
3479 snd_soc_update_bits(codec, WM8962_IRQ_DEBOUNCE, 3479 snd_soc_update_bits(codec, WM8962_IRQ_DEBOUNCE,
3480 WM8962_FLL_LOCK_DB | WM8962_PLL3_LOCK_DB | 3480 WM8962_FLL_LOCK_DB | WM8962_PLL3_LOCK_DB |
3481 WM8962_PLL2_LOCK_DB | WM8962_TEMP_SHUT_DB, 3481 WM8962_PLL2_LOCK_DB | WM8962_TEMP_SHUT_DB,
3482 0); 3482 0);
3483 3483
3484 wm8962_add_widgets(codec); 3484 wm8962_add_widgets(codec);
3485 3485
3486 /* Save boards having to disable DMIC when not in use */ 3486 /* Save boards having to disable DMIC when not in use */
3487 dmicclk = false; 3487 dmicclk = false;
3488 dmicdat = false; 3488 dmicdat = false;
3489 for (i = 0; i < WM8962_MAX_GPIO; i++) { 3489 for (i = 0; i < WM8962_MAX_GPIO; i++) {
3490 switch (snd_soc_read(codec, WM8962_GPIO_BASE + i) 3490 switch (snd_soc_read(codec, WM8962_GPIO_BASE + i)
3491 & WM8962_GP2_FN_MASK) { 3491 & WM8962_GP2_FN_MASK) {
3492 case WM8962_GPIO_FN_DMICCLK: 3492 case WM8962_GPIO_FN_DMICCLK:
3493 dmicclk = true; 3493 dmicclk = true;
3494 break; 3494 break;
3495 case WM8962_GPIO_FN_DMICDAT: 3495 case WM8962_GPIO_FN_DMICDAT:
3496 dmicdat = true; 3496 dmicdat = true;
3497 break; 3497 break;
3498 default: 3498 default:
3499 break; 3499 break;
3500 } 3500 }
3501 } 3501 }
3502 if (!dmicclk || !dmicdat) { 3502 if (!dmicclk || !dmicdat) {
3503 dev_dbg(codec->dev, "DMIC not in use, disabling\n"); 3503 dev_dbg(codec->dev, "DMIC not in use, disabling\n");
3504 snd_soc_dapm_nc_pin(&codec->dapm, "DMICDAT"); 3504 snd_soc_dapm_nc_pin(&codec->dapm, "DMICDAT");
3505 } 3505 }
3506 if (dmicclk != dmicdat) 3506 if (dmicclk != dmicdat)
3507 dev_warn(codec->dev, "DMIC GPIOs partially configured\n"); 3507 dev_warn(codec->dev, "DMIC GPIOs partially configured\n");
3508 3508
3509 wm8962_init_beep(codec); 3509 wm8962_init_beep(codec);
3510 wm8962_init_gpio(codec); 3510 wm8962_init_gpio(codec);
3511 3511
3512 if (wm8962->irq) { 3512 if (wm8962->irq) {
3513 if (pdata && pdata->irq_active_low) { 3513 if (pdata && pdata->irq_active_low) {
3514 trigger = IRQF_TRIGGER_LOW; 3514 trigger = IRQF_TRIGGER_LOW;
3515 irq_pol = WM8962_IRQ_POL; 3515 irq_pol = WM8962_IRQ_POL;
3516 } else { 3516 } else {
3517 trigger = IRQF_TRIGGER_HIGH; 3517 trigger = IRQF_TRIGGER_HIGH;
3518 irq_pol = 0; 3518 irq_pol = 0;
3519 } 3519 }
3520 3520
3521 snd_soc_update_bits(codec, WM8962_INTERRUPT_CONTROL, 3521 snd_soc_update_bits(codec, WM8962_INTERRUPT_CONTROL,
3522 WM8962_IRQ_POL, irq_pol); 3522 WM8962_IRQ_POL, irq_pol);
3523 3523
3524 ret = request_threaded_irq(wm8962->irq, NULL, wm8962_irq, 3524 ret = request_threaded_irq(wm8962->irq, NULL, wm8962_irq,
3525 trigger | IRQF_ONESHOT, 3525 trigger | IRQF_ONESHOT,
3526 "wm8962", codec->dev); 3526 "wm8962", codec->dev);
3527 if (ret != 0) { 3527 if (ret != 0) {
3528 dev_err(codec->dev, "Failed to request IRQ %d: %d\n", 3528 dev_err(codec->dev, "Failed to request IRQ %d: %d\n",
3529 wm8962->irq, ret); 3529 wm8962->irq, ret);
3530 wm8962->irq = 0; 3530 wm8962->irq = 0;
3531 /* Non-fatal */ 3531 /* Non-fatal */
3532 } else { 3532 } else {
3533 /* Enable some IRQs by default */ 3533 /* Enable some IRQs by default */
3534 snd_soc_update_bits(codec, 3534 snd_soc_update_bits(codec,
3535 WM8962_INTERRUPT_STATUS_2_MASK, 3535 WM8962_INTERRUPT_STATUS_2_MASK,
3536 WM8962_FLL_LOCK_EINT | 3536 WM8962_FLL_LOCK_EINT |
3537 WM8962_TEMP_SHUT_EINT | 3537 WM8962_TEMP_SHUT_EINT |
3538 WM8962_FIFOS_ERR_EINT, 0); 3538 WM8962_FIFOS_ERR_EINT, 0);
3539 } 3539 }
3540 } 3540 }
3541 3541
3542 return 0; 3542 return 0;
3543 } 3543 }
3544 3544
3545 static int wm8962_remove(struct snd_soc_codec *codec) 3545 static int wm8962_remove(struct snd_soc_codec *codec)
3546 { 3546 {
3547 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 3547 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3548 int i; 3548 int i;
3549 3549
3550 if (wm8962->irq) 3550 if (wm8962->irq)
3551 free_irq(wm8962->irq, codec); 3551 free_irq(wm8962->irq, codec);
3552 3552
3553 cancel_delayed_work_sync(&wm8962->mic_work); 3553 cancel_delayed_work_sync(&wm8962->mic_work);
3554 3554
3555 wm8962_free_gpio(codec); 3555 wm8962_free_gpio(codec);
3556 wm8962_free_beep(codec); 3556 wm8962_free_beep(codec);
3557 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) 3557 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3558 regulator_unregister_notifier(wm8962->supplies[i].consumer, 3558 regulator_unregister_notifier(wm8962->supplies[i].consumer,
3559 &wm8962->disable_nb[i]); 3559 &wm8962->disable_nb[i]);
3560 3560
3561 return 0; 3561 return 0;
3562 } 3562 }
3563 3563
3564 static struct snd_soc_codec_driver soc_codec_dev_wm8962 = { 3564 static struct snd_soc_codec_driver soc_codec_dev_wm8962 = {
3565 .probe = wm8962_probe, 3565 .probe = wm8962_probe,
3566 .remove = wm8962_remove, 3566 .remove = wm8962_remove,
3567 .set_bias_level = wm8962_set_bias_level, 3567 .set_bias_level = wm8962_set_bias_level,
3568 .set_pll = wm8962_set_fll, 3568 .set_pll = wm8962_set_fll,
3569 .idle_bias_off = true, 3569 .idle_bias_off = true,
3570 }; 3570 };
3571 3571
3572 /* Improve power consumption for IN4 DC measurement mode */ 3572 /* Improve power consumption for IN4 DC measurement mode */
3573 static const struct reg_default wm8962_dc_measure[] = { 3573 static const struct reg_default wm8962_dc_measure[] = {
3574 { 0xfd, 0x1 }, 3574 { 0xfd, 0x1 },
3575 { 0xcc, 0x40 }, 3575 { 0xcc, 0x40 },
3576 { 0xfd, 0 }, 3576 { 0xfd, 0 },
3577 }; 3577 };
3578 3578
3579 static const struct regmap_config wm8962_regmap = { 3579 static const struct regmap_config wm8962_regmap = {
3580 .reg_bits = 16, 3580 .reg_bits = 16,
3581 .val_bits = 16, 3581 .val_bits = 16,
3582 3582
3583 .max_register = WM8962_MAX_REGISTER, 3583 .max_register = WM8962_MAX_REGISTER,
3584 .reg_defaults = wm8962_reg, 3584 .reg_defaults = wm8962_reg,
3585 .num_reg_defaults = ARRAY_SIZE(wm8962_reg), 3585 .num_reg_defaults = ARRAY_SIZE(wm8962_reg),
3586 .volatile_reg = wm8962_volatile_register, 3586 .volatile_reg = wm8962_volatile_register,
3587 .readable_reg = wm8962_readable_register, 3587 .readable_reg = wm8962_readable_register,
3588 .cache_type = REGCACHE_RBTREE, 3588 .cache_type = REGCACHE_RBTREE,
3589 }; 3589 };
3590 3590
3591 static __devinit int wm8962_i2c_probe(struct i2c_client *i2c, 3591 static __devinit int wm8962_i2c_probe(struct i2c_client *i2c,
3592 const struct i2c_device_id *id) 3592 const struct i2c_device_id *id)
3593 { 3593 {
3594 struct wm8962_pdata *pdata = dev_get_platdata(&i2c->dev); 3594 struct wm8962_pdata *pdata = dev_get_platdata(&i2c->dev);
3595 struct wm8962_priv *wm8962; 3595 struct wm8962_priv *wm8962;
3596 unsigned int reg; 3596 unsigned int reg;
3597 int ret, i; 3597 int ret, i;
3598 3598
3599 wm8962 = devm_kzalloc(&i2c->dev, sizeof(struct wm8962_priv), 3599 wm8962 = devm_kzalloc(&i2c->dev, sizeof(struct wm8962_priv),
3600 GFP_KERNEL); 3600 GFP_KERNEL);
3601 if (wm8962 == NULL) 3601 if (wm8962 == NULL)
3602 return -ENOMEM; 3602 return -ENOMEM;
3603 3603
3604 i2c_set_clientdata(i2c, wm8962); 3604 i2c_set_clientdata(i2c, wm8962);
3605 3605
3606 INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work); 3606 INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work);
3607 init_completion(&wm8962->fll_lock); 3607 init_completion(&wm8962->fll_lock);
3608 wm8962->irq = i2c->irq; 3608 wm8962->irq = i2c->irq;
3609 3609
3610 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) 3610 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3611 wm8962->supplies[i].supply = wm8962_supply_names[i]; 3611 wm8962->supplies[i].supply = wm8962_supply_names[i];
3612 3612
3613 ret = regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8962->supplies), 3613 ret = regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8962->supplies),
3614 wm8962->supplies); 3614 wm8962->supplies);
3615 if (ret != 0) { 3615 if (ret != 0) {
3616 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 3616 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3617 goto err; 3617 goto err;
3618 } 3618 }
3619 3619
3620 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies), 3620 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3621 wm8962->supplies); 3621 wm8962->supplies);
3622 if (ret != 0) { 3622 if (ret != 0) {
3623 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 3623 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3624 goto err_get; 3624 goto err_get;
3625 } 3625 }
3626 3626
3627 wm8962->regmap = regmap_init_i2c(i2c, &wm8962_regmap); 3627 wm8962->regmap = regmap_init_i2c(i2c, &wm8962_regmap);
3628 if (IS_ERR(wm8962->regmap)) { 3628 if (IS_ERR(wm8962->regmap)) {
3629 ret = PTR_ERR(wm8962->regmap); 3629 ret = PTR_ERR(wm8962->regmap);
3630 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); 3630 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
3631 goto err_enable; 3631 goto err_enable;
3632 } 3632 }
3633 3633
3634 /* 3634 /*
3635 * We haven't marked the chip revision as volatile due to 3635 * We haven't marked the chip revision as volatile due to
3636 * sharing a register with the right input volume; explicitly 3636 * sharing a register with the right input volume; explicitly
3637 * bypass the cache to read it. 3637 * bypass the cache to read it.
3638 */ 3638 */
3639 regcache_cache_bypass(wm8962->regmap, true); 3639 regcache_cache_bypass(wm8962->regmap, true);
3640 3640
3641 ret = regmap_read(wm8962->regmap, WM8962_SOFTWARE_RESET, &reg); 3641 ret = regmap_read(wm8962->regmap, WM8962_SOFTWARE_RESET, &reg);
3642 if (ret < 0) { 3642 if (ret < 0) {
3643 dev_err(&i2c->dev, "Failed to read ID register\n"); 3643 dev_err(&i2c->dev, "Failed to read ID register\n");
3644 goto err_regmap; 3644 goto err_regmap;
3645 } 3645 }
3646 if (reg != 0x6243) { 3646 if (reg != 0x6243) {
3647 dev_err(&i2c->dev, 3647 dev_err(&i2c->dev,
3648 "Device is not a WM8962, ID %x != 0x6243\n", reg); 3648 "Device is not a WM8962, ID %x != 0x6243\n", reg);
3649 ret = -EINVAL; 3649 ret = -EINVAL;
3650 goto err_regmap; 3650 goto err_regmap;
3651 } 3651 }
3652 3652
3653 ret = regmap_read(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, &reg); 3653 ret = regmap_read(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, &reg);
3654 if (ret < 0) { 3654 if (ret < 0) {
3655 dev_err(&i2c->dev, "Failed to read device revision: %d\n", 3655 dev_err(&i2c->dev, "Failed to read device revision: %d\n",
3656 ret); 3656 ret);
3657 goto err_regmap; 3657 goto err_regmap;
3658 } 3658 }
3659 3659
3660 dev_info(&i2c->dev, "customer id %x revision %c\n", 3660 dev_info(&i2c->dev, "customer id %x revision %c\n",
3661 (reg & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT, 3661 (reg & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT,
3662 ((reg & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT) 3662 ((reg & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT)
3663 + 'A'); 3663 + 'A');
3664 3664
3665 regcache_cache_bypass(wm8962->regmap, false); 3665 regcache_cache_bypass(wm8962->regmap, false);
3666 3666
3667 ret = wm8962_reset(wm8962); 3667 ret = wm8962_reset(wm8962);
3668 if (ret < 0) { 3668 if (ret < 0) {
3669 dev_err(&i2c->dev, "Failed to issue reset\n"); 3669 dev_err(&i2c->dev, "Failed to issue reset\n");
3670 goto err_regmap; 3670 goto err_regmap;
3671 } 3671 }
3672 3672
3673 if (pdata && pdata->in4_dc_measure) { 3673 if (pdata && pdata->in4_dc_measure) {
3674 ret = regmap_register_patch(wm8962->regmap, 3674 ret = regmap_register_patch(wm8962->regmap,
3675 wm8962_dc_measure, 3675 wm8962_dc_measure,
3676 ARRAY_SIZE(wm8962_dc_measure)); 3676 ARRAY_SIZE(wm8962_dc_measure));
3677 if (ret != 0) 3677 if (ret != 0)
3678 dev_err(&i2c->dev, 3678 dev_err(&i2c->dev,
3679 "Failed to configure for DC mesurement: %d\n", 3679 "Failed to configure for DC mesurement: %d\n",
3680 ret); 3680 ret);
3681 } 3681 }
3682 3682
3683 pm_runtime_enable(&i2c->dev); 3683 pm_runtime_enable(&i2c->dev);
3684 pm_request_idle(&i2c->dev); 3684 pm_request_idle(&i2c->dev);
3685 3685
3686 ret = snd_soc_register_codec(&i2c->dev, 3686 ret = snd_soc_register_codec(&i2c->dev,
3687 &soc_codec_dev_wm8962, &wm8962_dai, 1); 3687 &soc_codec_dev_wm8962, &wm8962_dai, 1);
3688 if (ret < 0) 3688 if (ret < 0)
3689 goto err_regmap; 3689 goto err_regmap;
3690 3690
3691 /* The drivers should power up as needed */ 3691 /* The drivers should power up as needed */
3692 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies); 3692 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3693 3693
3694 return 0; 3694 return 0;
3695 3695
3696 err_regmap: 3696 err_regmap:
3697 regmap_exit(wm8962->regmap); 3697 regmap_exit(wm8962->regmap);
3698 err_enable: 3698 err_enable:
3699 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies); 3699 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3700 err_get: 3700 err_get:
3701 regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies); 3701 regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3702 err: 3702 err:
3703 return ret; 3703 return ret;
3704 } 3704 }
3705 3705
3706 static __devexit int wm8962_i2c_remove(struct i2c_client *client) 3706 static __devexit int wm8962_i2c_remove(struct i2c_client *client)
3707 { 3707 {
3708 struct wm8962_priv *wm8962 = dev_get_drvdata(&client->dev); 3708 struct wm8962_priv *wm8962 = dev_get_drvdata(&client->dev);
3709 3709
3710 snd_soc_unregister_codec(&client->dev); 3710 snd_soc_unregister_codec(&client->dev);
3711 regmap_exit(wm8962->regmap); 3711 regmap_exit(wm8962->regmap);
3712 regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies); 3712 regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3713 return 0; 3713 return 0;
3714 } 3714 }
3715 3715
3716 #ifdef CONFIG_PM_RUNTIME 3716 #ifdef CONFIG_PM_RUNTIME
3717 static int wm8962_runtime_resume(struct device *dev) 3717 static int wm8962_runtime_resume(struct device *dev)
3718 { 3718 {
3719 struct wm8962_priv *wm8962 = dev_get_drvdata(dev); 3719 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3720 int ret; 3720 int ret;
3721 3721
3722 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies), 3722 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3723 wm8962->supplies); 3723 wm8962->supplies);
3724 if (ret != 0) { 3724 if (ret != 0) {
3725 dev_err(dev, 3725 dev_err(dev,
3726 "Failed to enable supplies: %d\n", ret); 3726 "Failed to enable supplies: %d\n", ret);
3727 return ret; 3727 return ret;
3728 } 3728 }
3729 3729
3730 regcache_cache_only(wm8962->regmap, false); 3730 regcache_cache_only(wm8962->regmap, false);
3731 3731
3732 wm8962_reset(wm8962); 3732 wm8962_reset(wm8962);
3733 3733
3734 regcache_sync(wm8962->regmap); 3734 regcache_sync(wm8962->regmap);
3735 3735
3736 regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
3737 WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA,
3738 WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA);
3739
3740 /* Bias enable at 2*50k for ramp */
3741 regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3742 WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA,
3743 WM8962_BIAS_ENA | 0x180);
3744
3745 msleep(5);
3746
3747 /* VMID back to 2x250k for standby */
3748 regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3749 WM8962_VMID_SEL_MASK, 0x100);
3750
3751 return 0; 3736 return 0;
3752 } 3737 }
3753 3738
3754 static int wm8962_runtime_suspend(struct device *dev) 3739 static int wm8962_runtime_suspend(struct device *dev)
3755 { 3740 {
3756 struct wm8962_priv *wm8962 = dev_get_drvdata(dev); 3741 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3757 3742
3758 regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1, 3743 regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3759 WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0); 3744 WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0);
3760 3745
3761 regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP, 3746 regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
3762 WM8962_STARTUP_BIAS_ENA | 3747 WM8962_STARTUP_BIAS_ENA |
3763 WM8962_VMID_BUF_ENA, 0); 3748 WM8962_VMID_BUF_ENA, 0);
3764 3749
3765 regcache_cache_only(wm8962->regmap, true); 3750 regcache_cache_only(wm8962->regmap, true);
3766 3751
3767 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), 3752 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
3768 wm8962->supplies); 3753 wm8962->supplies);
3769 3754
3770 return 0; 3755 return 0;
3771 } 3756 }
3772 #endif 3757 #endif
3773 3758
3774 static struct dev_pm_ops wm8962_pm = { 3759 static struct dev_pm_ops wm8962_pm = {
3775 SET_RUNTIME_PM_OPS(wm8962_runtime_suspend, wm8962_runtime_resume, NULL) 3760 SET_RUNTIME_PM_OPS(wm8962_runtime_suspend, wm8962_runtime_resume, NULL)
3776 }; 3761 };
3777 3762
3778 static const struct i2c_device_id wm8962_i2c_id[] = { 3763 static const struct i2c_device_id wm8962_i2c_id[] = {
3779 { "wm8962", 0 }, 3764 { "wm8962", 0 },
3780 { } 3765 { }
3781 }; 3766 };
3782 MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id); 3767 MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id);
3783 3768
3784 static struct i2c_driver wm8962_i2c_driver = { 3769 static struct i2c_driver wm8962_i2c_driver = {
3785 .driver = { 3770 .driver = {
3786 .name = "wm8962", 3771 .name = "wm8962",
3787 .owner = THIS_MODULE, 3772 .owner = THIS_MODULE,
3788 .pm = &wm8962_pm, 3773 .pm = &wm8962_pm,
3789 }, 3774 },
3790 .probe = wm8962_i2c_probe, 3775 .probe = wm8962_i2c_probe,
3791 .remove = __devexit_p(wm8962_i2c_remove), 3776 .remove = __devexit_p(wm8962_i2c_remove),
3792 .id_table = wm8962_i2c_id, 3777 .id_table = wm8962_i2c_id,
3793 }; 3778 };
3794 3779
3795 module_i2c_driver(wm8962_i2c_driver); 3780 module_i2c_driver(wm8962_i2c_driver);
3796 3781
3797 MODULE_DESCRIPTION("ASoC WM8962 driver"); 3782 MODULE_DESCRIPTION("ASoC WM8962 driver");
3798 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 3783 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3799 MODULE_LICENSE("GPL"); 3784 MODULE_LICENSE("GPL");
3800 3785