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Commit 533462fba545d271e087c3c632cf62ff04808e40

Authored by Russell King
Committed by Russell King
1 parent f79299ca85
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

[ARM] pxa: omit PXA25x or PXA27x standby/sleep code as appropriate 

There's no point building standby/sleep code for processors which
aren't configured.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Showing 3 changed files with 10 additions and 7 deletions Inline Diff

arch/arm/mach-pxa/Makefile
Diff comments   View file @ 533462f
1 # 1 #
2 # Makefile for the linux kernel. 2 # Makefile for the linux kernel.
3 # 3 #
4 4
5 # Common support (must be linked before board specific support) 5 # Common support (must be linked before board specific support)
6 obj-y += clock.o devices.o generic.o irq.o dma.o time.o 6 obj-y += clock.o devices.o generic.o irq.o dma.o time.o
7 obj-$(CONFIG_PXA25x) += pxa25x.o 7 obj-$(CONFIG_PXA25x) += pxa25x.o
8 obj-$(CONFIG_PXA27x) += pxa27x.o 8 obj-$(CONFIG_PXA27x) += pxa27x.o
9 obj-$(CONFIG_PXA3xx) += pxa3xx.o mfp.o 9 obj-$(CONFIG_PXA3xx) += pxa3xx.o mfp.o
10 obj-$(CONFIG_CPU_PXA300) += pxa300.o 10 obj-$(CONFIG_CPU_PXA300) += pxa300.o
11 obj-$(CONFIG_CPU_PXA320) += pxa320.o 11 obj-$(CONFIG_CPU_PXA320) += pxa320.o
12 12
13 # Specific board support 13 # Specific board support
14 obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o 14 obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o
15 obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o 15 obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o
16 obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o 16 obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o
17 obj-$(CONFIG_ARCH_PXA_IDP) += idp.o 17 obj-$(CONFIG_ARCH_PXA_IDP) += idp.o
18 obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o 18 obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o
19 obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o corgi_pm.o 19 obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o corgi_pm.o
20 obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o spitz_pm.o 20 obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o spitz_pm.o
21 obj-$(CONFIG_MACH_AKITA) += akita-ioexp.o 21 obj-$(CONFIG_MACH_AKITA) += akita-ioexp.o
22 obj-$(CONFIG_MACH_POODLE) += poodle.o corgi_ssp.o 22 obj-$(CONFIG_MACH_POODLE) += poodle.o corgi_ssp.o
23 obj-$(CONFIG_MACH_TOSA) += tosa.o 23 obj-$(CONFIG_MACH_TOSA) += tosa.o
24 obj-$(CONFIG_MACH_EM_X270) += em-x270.o 24 obj-$(CONFIG_MACH_EM_X270) += em-x270.o
25 25
26 ifeq ($(CONFIG_MACH_ZYLONITE),y) 26 ifeq ($(CONFIG_MACH_ZYLONITE),y)
27 obj-y += zylonite.o 27 obj-y += zylonite.o
28 obj-$(CONFIG_CPU_PXA300) += zylonite_pxa300.o 28 obj-$(CONFIG_CPU_PXA300) += zylonite_pxa300.o
29 obj-$(CONFIG_CPU_PXA320) += zylonite_pxa320.o 29 obj-$(CONFIG_CPU_PXA320) += zylonite_pxa320.o
30 endif 30 endif
31 31
32 obj-$(CONFIG_MACH_ARMCORE) += cm-x270.o 32 obj-$(CONFIG_MACH_ARMCORE) += cm-x270.o
33 33
34 # Support for blinky lights 34 # Support for blinky lights
35 led-y := leds.o 35 led-y := leds.o
36 led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o 36 led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o
37 led-$(CONFIG_MACH_MAINSTONE) += leds-mainstone.o 37 led-$(CONFIG_MACH_MAINSTONE) += leds-mainstone.o
38 led-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o 38 led-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o
39 led-$(CONFIG_MACH_TRIZEPS4) += leds-trizeps4.o 39 led-$(CONFIG_MACH_TRIZEPS4) += leds-trizeps4.o
40 40
41 obj-$(CONFIG_LEDS) += $(led-y) 41 obj-$(CONFIG_LEDS) += $(led-y)
42 42
43 # Misc features 43 # Misc features
44 obj-$(CONFIG_PM) += pm.o sleep.o 44 obj-$(CONFIG_PM) += pm.o sleep.o standby.o
45 obj-$(CONFIG_CPU_FREQ) += cpu-pxa.o 45 obj-$(CONFIG_CPU_FREQ) += cpu-pxa.o
46 obj-$(CONFIG_PXA_SSP) += ssp.o 46 obj-$(CONFIG_PXA_SSP) += ssp.o
47
48 ifeq ($(CONFIG_PXA27x),y)
49 obj-$(CONFIG_PM) += standby.o
50 endif
51 47
52 ifeq ($(CONFIG_PCI),y) 48 ifeq ($(CONFIG_PCI),y)
53 obj-$(CONFIG_MACH_ARMCORE) += cm-x270-pci.o 49 obj-$(CONFIG_MACH_ARMCORE) += cm-x270-pci.o
54 endif 50 endif
55 51
arch/arm/mach-pxa/sleep.S
Diff comments   View file @ 533462f
1 /* 1 /*
2 * Low-level PXA250/210 sleep/wakeUp support 2 * Low-level PXA250/210 sleep/wakeUp support
3 * 3 *
4 * Initial SA1110 code: 4 * Initial SA1110 code:
5 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com> 5 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
6 * 6 *
7 * Adapted for PXA by Nicolas Pitre: 7 * Adapted for PXA by Nicolas Pitre:
8 * Copyright (c) 2002 Monta Vista Software, Inc. 8 * Copyright (c) 2002 Monta Vista Software, Inc.
9 * 9 *
10 * This program is free software; you can redistribute it and/or 10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License. 11 * modify it under the terms of the GNU General Public License.
12 */ 12 */
13 13
14 #include <linux/linkage.h> 14 #include <linux/linkage.h>
15 #include <asm/assembler.h> 15 #include <asm/assembler.h>
16 #include <asm/hardware.h> 16 #include <asm/hardware.h>
17 17
18 #include <asm/arch/pxa-regs.h> 18 #include <asm/arch/pxa-regs.h>
19 #include <asm/arch/pxa2xx-regs.h> 19 #include <asm/arch/pxa2xx-regs.h>
20 20
21 #define MDREFR_KDIV 0x200a4000 // all banks 21 #define MDREFR_KDIV 0x200a4000 // all banks
22 #define CCCR_SLEEP 0x00000107 // L=7 2N=2 A=0 PPDIS=0 CPDIS=0 22 #define CCCR_SLEEP 0x00000107 // L=7 2N=2 A=0 PPDIS=0 CPDIS=0
23 23
24 .text 24 .text
25 25
26 pxa_cpu_save_cp: 26 pxa_cpu_save_cp:
27 @ get coprocessor registers 27 @ get coprocessor registers
28 mrc p14, 0, r3, c6, c0, 0 @ clock configuration, for turbo mode 28 mrc p14, 0, r3, c6, c0, 0 @ clock configuration, for turbo mode
29 mrc p15, 0, r4, c15, c1, 0 @ CP access reg 29 mrc p15, 0, r4, c15, c1, 0 @ CP access reg
30 mrc p15, 0, r5, c13, c0, 0 @ PID 30 mrc p15, 0, r5, c13, c0, 0 @ PID
31 mrc p15, 0, r6, c3, c0, 0 @ domain ID 31 mrc p15, 0, r6, c3, c0, 0 @ domain ID
32 mrc p15, 0, r7, c2, c0, 0 @ translation table base addr 32 mrc p15, 0, r7, c2, c0, 0 @ translation table base addr
33 mrc p15, 0, r8, c1, c1, 0 @ auxiliary control reg 33 mrc p15, 0, r8, c1, c1, 0 @ auxiliary control reg
34 mrc p15, 0, r9, c1, c0, 0 @ control reg 34 mrc p15, 0, r9, c1, c0, 0 @ control reg
35 35
36 bic r3, r3, #2 @ clear frequency change bit 36 bic r3, r3, #2 @ clear frequency change bit
37 37
38 @ store them plus current virtual stack ptr on stack 38 @ store them plus current virtual stack ptr on stack
39 mov r10, sp 39 mov r10, sp
40 stmfd sp!, {r3 - r10} 40 stmfd sp!, {r3 - r10}
41 41
42 mov pc, lr 42 mov pc, lr
43 43
44 pxa_cpu_save_sp: 44 pxa_cpu_save_sp:
45 @ preserve phys address of stack 45 @ preserve phys address of stack
46 mov r0, sp 46 mov r0, sp
47 str lr, [sp, #-4]! 47 str lr, [sp, #-4]!
48 bl sleep_phys_sp 48 bl sleep_phys_sp
49 ldr r1, =sleep_save_sp 49 ldr r1, =sleep_save_sp
50 str r0, [r1] 50 str r0, [r1]
51 ldr pc, [sp], #4 51 ldr pc, [sp], #4
52 52
53 #ifdef CONFIG_PXA27x
53 /* 54 /*
54 * pxa27x_cpu_suspend() 55 * pxa27x_cpu_suspend()
55 * 56 *
56 * Forces CPU into sleep state. 57 * Forces CPU into sleep state.
57 * 58 *
58 * r0 = value for PWRMODE M field for desired sleep state 59 * r0 = value for PWRMODE M field for desired sleep state
59 */ 60 */
60 61
61 ENTRY(pxa27x_cpu_suspend) 62 ENTRY(pxa27x_cpu_suspend)
62 63
63 #ifndef CONFIG_IWMMXT 64 #ifndef CONFIG_IWMMXT
64 mra r2, r3, acc0 65 mra r2, r3, acc0
65 #endif 66 #endif
66 stmfd sp!, {r2 - r12, lr} @ save registers on stack 67 stmfd sp!, {r2 - r12, lr} @ save registers on stack
67 68
68 bl pxa_cpu_save_cp 69 bl pxa_cpu_save_cp
69 70
70 mov r5, r0 @ save sleep mode 71 mov r5, r0 @ save sleep mode
71 bl pxa_cpu_save_sp 72 bl pxa_cpu_save_sp
72 73
73 @ clean data cache 74 @ clean data cache
74 bl xscale_flush_kern_cache_all 75 bl xscale_flush_kern_cache_all
75 76
76 @ Put the processor to sleep 77 @ Put the processor to sleep
77 @ (also workaround for sighting 28071) 78 @ (also workaround for sighting 28071)
78 79
79 @ prepare value for sleep mode 80 @ prepare value for sleep mode
80 mov r1, r5 @ sleep mode 81 mov r1, r5 @ sleep mode
81 82
82 @ prepare pointer to physical address 0 (virtual mapping in generic.c) 83 @ prepare pointer to physical address 0 (virtual mapping in generic.c)
83 mov r2, #UNCACHED_PHYS_0 84 mov r2, #UNCACHED_PHYS_0
84 85
85 @ prepare SDRAM refresh settings 86 @ prepare SDRAM refresh settings
86 ldr r4, =MDREFR 87 ldr r4, =MDREFR
87 ldr r5, [r4] 88 ldr r5, [r4]
88 89
89 @ enable SDRAM self-refresh mode 90 @ enable SDRAM self-refresh mode
90 orr r5, r5, #MDREFR_SLFRSH 91 orr r5, r5, #MDREFR_SLFRSH
91 92
92 @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50) 93 @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50)
93 ldr r6, =MDREFR_KDIV 94 ldr r6, =MDREFR_KDIV
94 orr r5, r5, r6 95 orr r5, r5, r6
95 96
96 @ Intel PXA270 Specification Update notes problems sleeping 97 @ Intel PXA270 Specification Update notes problems sleeping
97 @ with core operating above 91 MHz 98 @ with core operating above 91 MHz
98 @ (see Errata 50, ...processor does not exit from sleep...) 99 @ (see Errata 50, ...processor does not exit from sleep...)
99 100
100 ldr r6, =CCCR 101 ldr r6, =CCCR
101 ldr r8, [r6] @ keep original value for resume 102 ldr r8, [r6] @ keep original value for resume
102 103
103 ldr r7, =CCCR_SLEEP @ prepare CCCR sleep value 104 ldr r7, =CCCR_SLEEP @ prepare CCCR sleep value
104 mov r0, #0x2 @ prepare value for CLKCFG 105 mov r0, #0x2 @ prepare value for CLKCFG
105 106
106 @ align execution to a cache line 107 @ align execution to a cache line
107 b pxa_cpu_do_suspend 108 b pxa_cpu_do_suspend
109 #endif
108 110
111 #ifdef CONFIG_PXA25x
109 /* 112 /*
110 * pxa27x_cpu_suspend() 113 * pxa25x_cpu_suspend()
111 * 114 *
112 * Forces CPU into sleep state. 115 * Forces CPU into sleep state.
113 * 116 *
114 * r0 = value for PWRMODE M field for desired sleep state 117 * r0 = value for PWRMODE M field for desired sleep state
115 */ 118 */
116 119
117 ENTRY(pxa25x_cpu_suspend) 120 ENTRY(pxa25x_cpu_suspend)
118 stmfd sp!, {r2 - r12, lr} @ save registers on stack 121 stmfd sp!, {r2 - r12, lr} @ save registers on stack
119 122
120 bl pxa_cpu_save_cp 123 bl pxa_cpu_save_cp
121 124
122 mov r5, r0 @ save sleep mode 125 mov r5, r0 @ save sleep mode
123 bl pxa_cpu_save_sp 126 bl pxa_cpu_save_sp
124 127
125 @ clean data cache 128 @ clean data cache
126 bl xscale_flush_kern_cache_all 129 bl xscale_flush_kern_cache_all
127 130
128 @ prepare value for sleep mode 131 @ prepare value for sleep mode
129 mov r1, r5 @ sleep mode 132 mov r1, r5 @ sleep mode
130 133
131 @ prepare pointer to physical address 0 (virtual mapping in generic.c) 134 @ prepare pointer to physical address 0 (virtual mapping in generic.c)
132 mov r2, #UNCACHED_PHYS_0 135 mov r2, #UNCACHED_PHYS_0
133 136
134 @ prepare SDRAM refresh settings 137 @ prepare SDRAM refresh settings
135 ldr r4, =MDREFR 138 ldr r4, =MDREFR
136 ldr r5, [r4] 139 ldr r5, [r4]
137 140
138 @ enable SDRAM self-refresh mode 141 @ enable SDRAM self-refresh mode
139 orr r5, r5, #MDREFR_SLFRSH 142 orr r5, r5, #MDREFR_SLFRSH
140 143
141 @ Intel PXA255 Specification Update notes problems 144 @ Intel PXA255 Specification Update notes problems
142 @ about suspending with PXBus operating above 133MHz 145 @ about suspending with PXBus operating above 133MHz
143 @ (see Errata 31, GPIO output signals, ... unpredictable in sleep 146 @ (see Errata 31, GPIO output signals, ... unpredictable in sleep
144 @ 147 @
145 @ We keep the change-down close to the actual suspend on SDRAM 148 @ We keep the change-down close to the actual suspend on SDRAM
146 @ as possible to eliminate messing about with the refresh clock 149 @ as possible to eliminate messing about with the refresh clock
147 @ as the system will restore with the original speed settings 150 @ as the system will restore with the original speed settings
148 @ 151 @
149 @ Ben Dooks, 13-Sep-2004 152 @ Ben Dooks, 13-Sep-2004
150 153
151 ldr r6, =CCCR 154 ldr r6, =CCCR
152 ldr r8, [r6] @ keep original value for resume 155 ldr r8, [r6] @ keep original value for resume
153 156
154 @ ensure x1 for run and turbo mode with memory clock 157 @ ensure x1 for run and turbo mode with memory clock
155 bic r7, r8, #CCCR_M_MASK | CCCR_N_MASK 158 bic r7, r8, #CCCR_M_MASK | CCCR_N_MASK
156 orr r7, r7, #(1<<5) | (2<<7) 159 orr r7, r7, #(1<<5) | (2<<7)
157 160
158 @ check that the memory frequency is within limits 161 @ check that the memory frequency is within limits
159 and r14, r7, #CCCR_L_MASK 162 and r14, r7, #CCCR_L_MASK
160 teq r14, #1 163 teq r14, #1
161 bicne r7, r7, #CCCR_L_MASK 164 bicne r7, r7, #CCCR_L_MASK
162 orrne r7, r7, #1 @@ 99.53MHz 165 orrne r7, r7, #1 @@ 99.53MHz
163 166
164 @ get ready for the change 167 @ get ready for the change
165 168
166 @ note, turbo is not preserved over sleep so there is no 169 @ note, turbo is not preserved over sleep so there is no
167 @ point in preserving it here. we save it on the stack with the 170 @ point in preserving it here. we save it on the stack with the
168 @ other CP registers instead. 171 @ other CP registers instead.
169 mov r0, #0 172 mov r0, #0
170 mcr p14, 0, r0, c6, c0, 0 173 mcr p14, 0, r0, c6, c0, 0
171 orr r0, r0, #2 @ initiate change bit 174 orr r0, r0, #2 @ initiate change bit
172 b pxa_cpu_do_suspend 175 b pxa_cpu_do_suspend
176 #endif
173 177
174 .ltorg 178 .ltorg
175 .align 5 179 .align 5
176 pxa_cpu_do_suspend: 180 pxa_cpu_do_suspend:
177 181
178 @ All needed values are now in registers. 182 @ All needed values are now in registers.
179 @ These last instructions should be in cache 183 @ These last instructions should be in cache
180 184
181 @ initiate the frequency change... 185 @ initiate the frequency change...
182 str r7, [r6] 186 str r7, [r6]
183 mcr p14, 0, r0, c6, c0, 0 187 mcr p14, 0, r0, c6, c0, 0
184 188
185 @ restore the original cpu speed value for resume 189 @ restore the original cpu speed value for resume
186 str r8, [r6] 190 str r8, [r6]
187 191
188 @ need 6 13-MHz cycles before changing PWRMODE 192 @ need 6 13-MHz cycles before changing PWRMODE
189 @ just set frequency to 91-MHz... 6*91/13 = 42 193 @ just set frequency to 91-MHz... 6*91/13 = 42
190 194
191 mov r0, #42 195 mov r0, #42
192 10: subs r0, r0, #1 196 10: subs r0, r0, #1
193 bne 10b 197 bne 10b
194 198
195 @ Do not reorder... 199 @ Do not reorder...
196 @ Intel PXA270 Specification Update notes problems performing 200 @ Intel PXA270 Specification Update notes problems performing
197 @ external accesses after SDRAM is put in self-refresh mode 201 @ external accesses after SDRAM is put in self-refresh mode
198 @ (see Errata 39 ...hangs when entering self-refresh mode) 202 @ (see Errata 39 ...hangs when entering self-refresh mode)
199 203
200 @ force address lines low by reading at physical address 0 204 @ force address lines low by reading at physical address 0
201 ldr r3, [r2] 205 ldr r3, [r2]
202 206
203 @ put SDRAM into self-refresh 207 @ put SDRAM into self-refresh
204 str r5, [r4] 208 str r5, [r4]
205 209
206 @ enter sleep mode 210 @ enter sleep mode
207 mcr p14, 0, r1, c7, c0, 0 @ PWRMODE 211 mcr p14, 0, r1, c7, c0, 0 @ PWRMODE
208 212
209 20: b 20b @ loop waiting for sleep 213 20: b 20b @ loop waiting for sleep
210 214
211 /* 215 /*
212 * cpu_pxa_resume() 216 * pxa_cpu_resume()
213 * 217 *
214 * entry point from bootloader into kernel during resume 218 * entry point from bootloader into kernel during resume
215 * 219 *
216 * Note: Yes, part of the following code is located into the .data section. 220 * Note: Yes, part of the following code is located into the .data section.
217 * This is to allow sleep_save_sp to be accessed with a relative load 221 * This is to allow sleep_save_sp to be accessed with a relative load
218 * while we can't rely on any MMU translation. We could have put 222 * while we can't rely on any MMU translation. We could have put
219 * sleep_save_sp in the .text section as well, but some setups might 223 * sleep_save_sp in the .text section as well, but some setups might
220 * insist on it to be truly read-only. 224 * insist on it to be truly read-only.
221 */ 225 */
222 226
223 .data 227 .data
224 .align 5 228 .align 5
225 ENTRY(pxa_cpu_resume) 229 ENTRY(pxa_cpu_resume)
226 mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE @ set SVC, irqs off 230 mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE @ set SVC, irqs off
227 msr cpsr_c, r0 231 msr cpsr_c, r0
228 232
229 ldr r0, sleep_save_sp @ stack phys addr 233 ldr r0, sleep_save_sp @ stack phys addr
230 ldr r2, =resume_after_mmu @ its absolute virtual address 234 ldr r2, =resume_after_mmu @ its absolute virtual address
231 ldmfd r0, {r3 - r9, sp} @ CP regs + virt stack ptr 235 ldmfd r0, {r3 - r9, sp} @ CP regs + virt stack ptr
232 236
233 mov r1, #0 237 mov r1, #0
234 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 238 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
235 mcr p15, 0, r1, c7, c7, 0 @ invalidate I & D caches, BTB 239 mcr p15, 0, r1, c7, c7, 0 @ invalidate I & D caches, BTB
236 240
237 #ifdef CONFIG_XSCALE_CACHE_ERRATA 241 #ifdef CONFIG_XSCALE_CACHE_ERRATA
238 bic r9, r9, #0x0004 @ see cpu_xscale_proc_init 242 bic r9, r9, #0x0004 @ see cpu_xscale_proc_init
239 #endif 243 #endif
240 244
241 mcr p14, 0, r3, c6, c0, 0 @ clock configuration, turbo mode. 245 mcr p14, 0, r3, c6, c0, 0 @ clock configuration, turbo mode.
242 mcr p15, 0, r4, c15, c1, 0 @ CP access reg 246 mcr p15, 0, r4, c15, c1, 0 @ CP access reg
243 mcr p15, 0, r5, c13, c0, 0 @ PID 247 mcr p15, 0, r5, c13, c0, 0 @ PID
244 mcr p15, 0, r6, c3, c0, 0 @ domain ID 248 mcr p15, 0, r6, c3, c0, 0 @ domain ID
245 mcr p15, 0, r7, c2, c0, 0 @ translation table base addr 249 mcr p15, 0, r7, c2, c0, 0 @ translation table base addr
246 mcr p15, 0, r8, c1, c1, 0 @ auxiliary control reg 250 mcr p15, 0, r8, c1, c1, 0 @ auxiliary control reg
247 b resume_turn_on_mmu @ cache align execution 251 b resume_turn_on_mmu @ cache align execution
248 252
249 .align 5 253 .align 5
250 resume_turn_on_mmu: 254 resume_turn_on_mmu:
251 mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, caches, etc. 255 mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, caches, etc.
252 256
253 @ Let us ensure we jump to resume_after_mmu only when the mcr above 257 @ Let us ensure we jump to resume_after_mmu only when the mcr above
254 @ actually took effect. They call it the "cpwait" operation. 258 @ actually took effect. They call it the "cpwait" operation.
255 mrc p15, 0, r1, c2, c0, 0 @ queue a dependency on CP15 259 mrc p15, 0, r1, c2, c0, 0 @ queue a dependency on CP15
256 sub pc, r2, r1, lsr #32 @ jump to virtual addr 260 sub pc, r2, r1, lsr #32 @ jump to virtual addr
257 nop 261 nop
258 nop 262 nop
259 nop 263 nop
260 264
261 sleep_save_sp: 265 sleep_save_sp:
262 .word 0 @ preserve stack phys ptr here 266 .word 0 @ preserve stack phys ptr here
263 267
264 .text 268 .text
265 resume_after_mmu: 269 resume_after_mmu:
266 #ifdef CONFIG_XSCALE_CACHE_ERRATA 270 #ifdef CONFIG_XSCALE_CACHE_ERRATA
267 bl cpu_xscale_proc_init 271 bl cpu_xscale_proc_init
268 #endif 272 #endif
269 ldmfd sp!, {r2, r3} 273 ldmfd sp!, {r2, r3}
270 #ifndef CONFIG_IWMMXT 274 #ifndef CONFIG_IWMMXT
271 mar acc0, r2, r3 275 mar acc0, r2, r3
272 #endif 276 #endif
273 ldmfd sp!, {r4 - r12, pc} @ return to caller 277 ldmfd sp!, {r4 - r12, pc} @ return to caller
274 278
arch/arm/mach-pxa/standby.S
Diff comments   View file @ 533462f
1 /* 1 /*
2 * PXA27x standby mode 2 * PXA27x standby mode
3 * 3 *
4 * Author: David Burrage 4 * Author: David Burrage
5 * 5 *
6 * 2005 (c) MontaVista Software, Inc. This file is licensed under 6 * 2005 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program 7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express 8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied. 9 * or implied.
10 */ 10 */
11 11
12 #include <linux/linkage.h> 12 #include <linux/linkage.h>
13 #include <asm/assembler.h> 13 #include <asm/assembler.h>
14 #include <asm/hardware.h> 14 #include <asm/hardware.h>
15 15
16 #include <asm/arch/pxa-regs.h> 16 #include <asm/arch/pxa-regs.h>
17 17
18 .text 18 .text
19 19
20 #ifdef CONFIG_PXA27x
20 ENTRY(pxa_cpu_standby) 21 ENTRY(pxa_cpu_standby)
21 ldr r0, =PSSR 22 ldr r0, =PSSR
22 mov r1, #(PSSR_PH | PSSR_STS) 23 mov r1, #(PSSR_PH | PSSR_STS)
23 mov r2, #PWRMODE_STANDBY 24 mov r2, #PWRMODE_STANDBY
24 mov r3, #UNCACHED_PHYS_0 @ Read mem context in. 25 mov r3, #UNCACHED_PHYS_0 @ Read mem context in.
25 ldr ip, [r3] 26 ldr ip, [r3]
26 b 1f 27 b 1f
27 28
28 .align 5 29 .align 5
29 1: mcr p14, 0, r2, c7, c0, 0 @ put the system into Standby 30 1: mcr p14, 0, r2, c7, c0, 0 @ put the system into Standby
30 str r1, [r0] @ make sure PSSR_PH/STS are clear 31 str r1, [r0] @ make sure PSSR_PH/STS are clear
31 mov pc, lr 32 mov pc, lr
33
34 #endif
32 35