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Commit 58a09b38cfcd700b796ea07ae3d2e0efbb28b561

Authored by Shane Huang
Committed by Jeff Garzik
1 parent 7654db1a92
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

[libata] ahci: Restore SB600 SATA controller 64 bit DMA 

Community reported one SB600 SATA issue(BZ #9412), which led to 64 bit
DMA disablement for all SB600 revisions by driver maintainers with
commits c7a42156d99bcea7f8173ba7a6034bbaa2ecb77c and
4cde32fc4b32e96a99063af3183acdfd54c563f0.

But the root cause is ASUS M2A-VM system BIOS bug in old revisions
like 0901, while forcing into 32bit DMA happens to work as workaround.
Now it's time to withdraw 4cde32fc4b32e96a99063af3183acdfd54c563f0
so as to restore the SB600 SATA 64bit DMA capability.
This patch is also adding the workaround for M2A-VM old BIOS revisions,
but users are suggested to upgrade their system BIOS to the latest one
if they meet this issue.

Signed-off-by: Shane Huang <shane.huang@amd.com>
Cc: Tejun Heo <tj@kernel.org>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>

Showing 2 changed files with 51 additions and 2 deletions Inline Diff

1 /* 1 /*
2 * ahci.c - AHCI SATA support 2 * ahci.c - AHCI SATA support
3 * 3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org 5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails. 6 * on emails.
7 * 7 *
8 * Copyright 2004-2005 Red Hat, Inc. 8 * Copyright 2004-2005 Red Hat, Inc.
9 * 9 *
10 * 10 *
11 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by 12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option) 13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version. 14 * any later version.
15 * 15 *
16 * This program is distributed in the hope that it will be useful, 16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details. 19 * GNU General Public License for more details.
20 * 20 *
21 * You should have received a copy of the GNU General Public License 21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to 22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 * 24 *
25 * 25 *
26 * libata documentation is available via 'make {ps|pdf}docs', 26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.* 27 * as Documentation/DocBook/libata.*
28 * 28 *
29 * AHCI hardware documentation: 29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 * 32 *
33 */ 33 */
34 34
35 #include <linux/kernel.h> 35 #include <linux/kernel.h>
36 #include <linux/module.h> 36 #include <linux/module.h>
37 #include <linux/pci.h> 37 #include <linux/pci.h>
38 #include <linux/init.h> 38 #include <linux/init.h>
39 #include <linux/blkdev.h> 39 #include <linux/blkdev.h>
40 #include <linux/delay.h> 40 #include <linux/delay.h>
41 #include <linux/interrupt.h> 41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h> 42 #include <linux/dma-mapping.h>
43 #include <linux/device.h> 43 #include <linux/device.h>
44 #include <linux/dmi.h> 44 #include <linux/dmi.h>
45 #include <scsi/scsi_host.h> 45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h> 46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h> 47 #include <linux/libata.h>
48 48
49 #define DRV_NAME "ahci" 49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "3.0" 50 #define DRV_VERSION "3.0"
51 51
52 /* Enclosure Management Control */ 52 /* Enclosure Management Control */
53 #define EM_CTRL_MSG_TYPE 0x000f0000 53 #define EM_CTRL_MSG_TYPE 0x000f0000
54 54
55 /* Enclosure Management LED Message Type */ 55 /* Enclosure Management LED Message Type */
56 #define EM_MSG_LED_HBA_PORT 0x0000000f 56 #define EM_MSG_LED_HBA_PORT 0x0000000f
57 #define EM_MSG_LED_PMP_SLOT 0x0000ff00 57 #define EM_MSG_LED_PMP_SLOT 0x0000ff00
58 #define EM_MSG_LED_VALUE 0xffff0000 58 #define EM_MSG_LED_VALUE 0xffff0000
59 #define EM_MSG_LED_VALUE_ACTIVITY 0x00070000 59 #define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
60 #define EM_MSG_LED_VALUE_OFF 0xfff80000 60 #define EM_MSG_LED_VALUE_OFF 0xfff80000
61 #define EM_MSG_LED_VALUE_ON 0x00010000 61 #define EM_MSG_LED_VALUE_ON 0x00010000
62 62
63 static int ahci_skip_host_reset; 63 static int ahci_skip_host_reset;
64 static int ahci_ignore_sss; 64 static int ahci_ignore_sss;
65 65
66 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); 66 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
67 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); 67 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
68 68
69 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444); 69 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
70 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)"); 70 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
71 71
72 static int ahci_enable_alpm(struct ata_port *ap, 72 static int ahci_enable_alpm(struct ata_port *ap,
73 enum link_pm policy); 73 enum link_pm policy);
74 static void ahci_disable_alpm(struct ata_port *ap); 74 static void ahci_disable_alpm(struct ata_port *ap);
75 static ssize_t ahci_led_show(struct ata_port *ap, char *buf); 75 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
76 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 76 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
77 size_t size); 77 size_t size);
78 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 78 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
79 ssize_t size); 79 ssize_t size);
80 80
81 enum { 81 enum {
82 AHCI_PCI_BAR = 5, 82 AHCI_PCI_BAR = 5,
83 AHCI_MAX_PORTS = 32, 83 AHCI_MAX_PORTS = 32,
84 AHCI_MAX_SG = 168, /* hardware max is 64K */ 84 AHCI_MAX_SG = 168, /* hardware max is 64K */
85 AHCI_DMA_BOUNDARY = 0xffffffff, 85 AHCI_DMA_BOUNDARY = 0xffffffff,
86 AHCI_MAX_CMDS = 32, 86 AHCI_MAX_CMDS = 32,
87 AHCI_CMD_SZ = 32, 87 AHCI_CMD_SZ = 32,
88 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, 88 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
89 AHCI_RX_FIS_SZ = 256, 89 AHCI_RX_FIS_SZ = 256,
90 AHCI_CMD_TBL_CDB = 0x40, 90 AHCI_CMD_TBL_CDB = 0x40,
91 AHCI_CMD_TBL_HDR_SZ = 0x80, 91 AHCI_CMD_TBL_HDR_SZ = 0x80,
92 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), 92 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
93 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, 93 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
94 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + 94 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
95 AHCI_RX_FIS_SZ, 95 AHCI_RX_FIS_SZ,
96 AHCI_IRQ_ON_SG = (1 << 31), 96 AHCI_IRQ_ON_SG = (1 << 31),
97 AHCI_CMD_ATAPI = (1 << 5), 97 AHCI_CMD_ATAPI = (1 << 5),
98 AHCI_CMD_WRITE = (1 << 6), 98 AHCI_CMD_WRITE = (1 << 6),
99 AHCI_CMD_PREFETCH = (1 << 7), 99 AHCI_CMD_PREFETCH = (1 << 7),
100 AHCI_CMD_RESET = (1 << 8), 100 AHCI_CMD_RESET = (1 << 8),
101 AHCI_CMD_CLR_BUSY = (1 << 10), 101 AHCI_CMD_CLR_BUSY = (1 << 10),
102 102
103 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ 103 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
104 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ 104 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
105 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ 105 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
106 106
107 board_ahci = 0, 107 board_ahci = 0,
108 board_ahci_vt8251 = 1, 108 board_ahci_vt8251 = 1,
109 board_ahci_ign_iferr = 2, 109 board_ahci_ign_iferr = 2,
110 board_ahci_sb600 = 3, 110 board_ahci_sb600 = 3,
111 board_ahci_mv = 4, 111 board_ahci_mv = 4,
112 board_ahci_sb700 = 5, /* for SB700 and SB800 */ 112 board_ahci_sb700 = 5, /* for SB700 and SB800 */
113 board_ahci_mcp65 = 6, 113 board_ahci_mcp65 = 6,
114 board_ahci_nopmp = 7, 114 board_ahci_nopmp = 7,
115 board_ahci_yesncq = 8, 115 board_ahci_yesncq = 8,
116 116
117 /* global controller registers */ 117 /* global controller registers */
118 HOST_CAP = 0x00, /* host capabilities */ 118 HOST_CAP = 0x00, /* host capabilities */
119 HOST_CTL = 0x04, /* global host control */ 119 HOST_CTL = 0x04, /* global host control */
120 HOST_IRQ_STAT = 0x08, /* interrupt status */ 120 HOST_IRQ_STAT = 0x08, /* interrupt status */
121 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ 121 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
122 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ 122 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
123 HOST_EM_LOC = 0x1c, /* Enclosure Management location */ 123 HOST_EM_LOC = 0x1c, /* Enclosure Management location */
124 HOST_EM_CTL = 0x20, /* Enclosure Management Control */ 124 HOST_EM_CTL = 0x20, /* Enclosure Management Control */
125 125
126 /* HOST_CTL bits */ 126 /* HOST_CTL bits */
127 HOST_RESET = (1 << 0), /* reset controller; self-clear */ 127 HOST_RESET = (1 << 0), /* reset controller; self-clear */
128 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ 128 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
129 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ 129 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
130 130
131 /* HOST_CAP bits */ 131 /* HOST_CAP bits */
132 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */ 132 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
133 HOST_CAP_SSC = (1 << 14), /* Slumber capable */ 133 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
134 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */ 134 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
135 HOST_CAP_CLO = (1 << 24), /* Command List Override support */ 135 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
136 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */ 136 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
137 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ 137 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
138 HOST_CAP_SNTF = (1 << 29), /* SNotification register */ 138 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
139 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ 139 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
140 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ 140 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
141 141
142 /* registers for each SATA port */ 142 /* registers for each SATA port */
143 PORT_LST_ADDR = 0x00, /* command list DMA addr */ 143 PORT_LST_ADDR = 0x00, /* command list DMA addr */
144 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ 144 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
145 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ 145 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
146 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ 146 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
147 PORT_IRQ_STAT = 0x10, /* interrupt status */ 147 PORT_IRQ_STAT = 0x10, /* interrupt status */
148 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ 148 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
149 PORT_CMD = 0x18, /* port command */ 149 PORT_CMD = 0x18, /* port command */
150 PORT_TFDATA = 0x20, /* taskfile data */ 150 PORT_TFDATA = 0x20, /* taskfile data */
151 PORT_SIG = 0x24, /* device TF signature */ 151 PORT_SIG = 0x24, /* device TF signature */
152 PORT_CMD_ISSUE = 0x38, /* command issue */ 152 PORT_CMD_ISSUE = 0x38, /* command issue */
153 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ 153 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
154 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ 154 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
155 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ 155 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
156 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ 156 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
157 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */ 157 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
158 158
159 /* PORT_IRQ_{STAT,MASK} bits */ 159 /* PORT_IRQ_{STAT,MASK} bits */
160 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ 160 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
161 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ 161 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
162 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ 162 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
163 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ 163 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
164 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ 164 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
165 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ 165 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
166 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ 166 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
167 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ 167 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
168 168
169 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ 169 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
170 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ 170 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
171 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ 171 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
172 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ 172 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
173 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ 173 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
174 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ 174 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
175 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ 175 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
176 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ 176 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
177 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ 177 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
178 178
179 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | 179 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
180 PORT_IRQ_IF_ERR | 180 PORT_IRQ_IF_ERR |
181 PORT_IRQ_CONNECT | 181 PORT_IRQ_CONNECT |
182 PORT_IRQ_PHYRDY | 182 PORT_IRQ_PHYRDY |
183 PORT_IRQ_UNK_FIS | 183 PORT_IRQ_UNK_FIS |
184 PORT_IRQ_BAD_PMP, 184 PORT_IRQ_BAD_PMP,
185 PORT_IRQ_ERROR = PORT_IRQ_FREEZE | 185 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
186 PORT_IRQ_TF_ERR | 186 PORT_IRQ_TF_ERR |
187 PORT_IRQ_HBUS_DATA_ERR, 187 PORT_IRQ_HBUS_DATA_ERR,
188 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | 188 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
189 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | 189 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
190 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, 190 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
191 191
192 /* PORT_CMD bits */ 192 /* PORT_CMD bits */
193 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ 193 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
194 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ 194 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
195 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ 195 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
196 PORT_CMD_PMP = (1 << 17), /* PMP attached */ 196 PORT_CMD_PMP = (1 << 17), /* PMP attached */
197 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ 197 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
198 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ 198 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
199 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ 199 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
200 PORT_CMD_CLO = (1 << 3), /* Command list override */ 200 PORT_CMD_CLO = (1 << 3), /* Command list override */
201 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ 201 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
202 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ 202 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
203 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ 203 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
204 204
205 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ 205 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
206 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ 206 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
207 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ 207 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
208 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ 208 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
209 209
210 /* hpriv->flags bits */ 210 /* hpriv->flags bits */
211 AHCI_HFLAG_NO_NCQ = (1 << 0), 211 AHCI_HFLAG_NO_NCQ = (1 << 0),
212 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */ 212 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
213 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */ 213 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
214 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */ 214 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
215 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */ 215 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
216 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */ 216 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
217 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */ 217 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
218 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */ 218 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
219 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */ 219 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
220 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */ 220 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
221 AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */ 221 AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */
222 222
223 /* ap->flags bits */ 223 /* ap->flags bits */
224 224
225 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 225 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
226 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | 226 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
227 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN | 227 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
228 ATA_FLAG_IPM, 228 ATA_FLAG_IPM,
229 229
230 ICH_MAP = 0x90, /* ICH MAP register */ 230 ICH_MAP = 0x90, /* ICH MAP register */
231 231
232 /* em constants */ 232 /* em constants */
233 EM_MAX_SLOTS = 8, 233 EM_MAX_SLOTS = 8,
234 EM_MAX_RETRY = 5, 234 EM_MAX_RETRY = 5,
235 235
236 /* em_ctl bits */ 236 /* em_ctl bits */
237 EM_CTL_RST = (1 << 9), /* Reset */ 237 EM_CTL_RST = (1 << 9), /* Reset */
238 EM_CTL_TM = (1 << 8), /* Transmit Message */ 238 EM_CTL_TM = (1 << 8), /* Transmit Message */
239 EM_CTL_ALHD = (1 << 26), /* Activity LED */ 239 EM_CTL_ALHD = (1 << 26), /* Activity LED */
240 }; 240 };
241 241
242 struct ahci_cmd_hdr { 242 struct ahci_cmd_hdr {
243 __le32 opts; 243 __le32 opts;
244 __le32 status; 244 __le32 status;
245 __le32 tbl_addr; 245 __le32 tbl_addr;
246 __le32 tbl_addr_hi; 246 __le32 tbl_addr_hi;
247 __le32 reserved[4]; 247 __le32 reserved[4];
248 }; 248 };
249 249
250 struct ahci_sg { 250 struct ahci_sg {
251 __le32 addr; 251 __le32 addr;
252 __le32 addr_hi; 252 __le32 addr_hi;
253 __le32 reserved; 253 __le32 reserved;
254 __le32 flags_size; 254 __le32 flags_size;
255 }; 255 };
256 256
257 struct ahci_em_priv { 257 struct ahci_em_priv {
258 enum sw_activity blink_policy; 258 enum sw_activity blink_policy;
259 struct timer_list timer; 259 struct timer_list timer;
260 unsigned long saved_activity; 260 unsigned long saved_activity;
261 unsigned long activity; 261 unsigned long activity;
262 unsigned long led_state; 262 unsigned long led_state;
263 }; 263 };
264 264
265 struct ahci_host_priv { 265 struct ahci_host_priv {
266 unsigned int flags; /* AHCI_HFLAG_* */ 266 unsigned int flags; /* AHCI_HFLAG_* */
267 u32 cap; /* cap to use */ 267 u32 cap; /* cap to use */
268 u32 port_map; /* port map to use */ 268 u32 port_map; /* port map to use */
269 u32 saved_cap; /* saved initial cap */ 269 u32 saved_cap; /* saved initial cap */
270 u32 saved_port_map; /* saved initial port_map */ 270 u32 saved_port_map; /* saved initial port_map */
271 u32 em_loc; /* enclosure management location */ 271 u32 em_loc; /* enclosure management location */
272 }; 272 };
273 273
274 struct ahci_port_priv { 274 struct ahci_port_priv {
275 struct ata_link *active_link; 275 struct ata_link *active_link;
276 struct ahci_cmd_hdr *cmd_slot; 276 struct ahci_cmd_hdr *cmd_slot;
277 dma_addr_t cmd_slot_dma; 277 dma_addr_t cmd_slot_dma;
278 void *cmd_tbl; 278 void *cmd_tbl;
279 dma_addr_t cmd_tbl_dma; 279 dma_addr_t cmd_tbl_dma;
280 void *rx_fis; 280 void *rx_fis;
281 dma_addr_t rx_fis_dma; 281 dma_addr_t rx_fis_dma;
282 /* for NCQ spurious interrupt analysis */ 282 /* for NCQ spurious interrupt analysis */
283 unsigned int ncq_saw_d2h:1; 283 unsigned int ncq_saw_d2h:1;
284 unsigned int ncq_saw_dmas:1; 284 unsigned int ncq_saw_dmas:1;
285 unsigned int ncq_saw_sdb:1; 285 unsigned int ncq_saw_sdb:1;
286 u32 intr_mask; /* interrupts to enable */ 286 u32 intr_mask; /* interrupts to enable */
287 /* enclosure management info per PM slot */ 287 /* enclosure management info per PM slot */
288 struct ahci_em_priv em_priv[EM_MAX_SLOTS]; 288 struct ahci_em_priv em_priv[EM_MAX_SLOTS];
289 }; 289 };
290 290
291 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 291 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
292 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 292 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
293 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 293 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
294 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); 294 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
295 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc); 295 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
296 static int ahci_port_start(struct ata_port *ap); 296 static int ahci_port_start(struct ata_port *ap);
297 static void ahci_port_stop(struct ata_port *ap); 297 static void ahci_port_stop(struct ata_port *ap);
298 static void ahci_qc_prep(struct ata_queued_cmd *qc); 298 static void ahci_qc_prep(struct ata_queued_cmd *qc);
299 static void ahci_freeze(struct ata_port *ap); 299 static void ahci_freeze(struct ata_port *ap);
300 static void ahci_thaw(struct ata_port *ap); 300 static void ahci_thaw(struct ata_port *ap);
301 static void ahci_pmp_attach(struct ata_port *ap); 301 static void ahci_pmp_attach(struct ata_port *ap);
302 static void ahci_pmp_detach(struct ata_port *ap); 302 static void ahci_pmp_detach(struct ata_port *ap);
303 static int ahci_softreset(struct ata_link *link, unsigned int *class, 303 static int ahci_softreset(struct ata_link *link, unsigned int *class,
304 unsigned long deadline); 304 unsigned long deadline);
305 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class, 305 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
306 unsigned long deadline); 306 unsigned long deadline);
307 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 307 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
308 unsigned long deadline); 308 unsigned long deadline);
309 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 309 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
310 unsigned long deadline); 310 unsigned long deadline);
311 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 311 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
312 unsigned long deadline); 312 unsigned long deadline);
313 static void ahci_postreset(struct ata_link *link, unsigned int *class); 313 static void ahci_postreset(struct ata_link *link, unsigned int *class);
314 static void ahci_error_handler(struct ata_port *ap); 314 static void ahci_error_handler(struct ata_port *ap);
315 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); 315 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
316 static int ahci_port_resume(struct ata_port *ap); 316 static int ahci_port_resume(struct ata_port *ap);
317 static void ahci_dev_config(struct ata_device *dev); 317 static void ahci_dev_config(struct ata_device *dev);
318 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 318 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
319 u32 opts); 319 u32 opts);
320 #ifdef CONFIG_PM 320 #ifdef CONFIG_PM
321 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); 321 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
322 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); 322 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
323 static int ahci_pci_device_resume(struct pci_dev *pdev); 323 static int ahci_pci_device_resume(struct pci_dev *pdev);
324 #endif 324 #endif
325 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf); 325 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
326 static ssize_t ahci_activity_store(struct ata_device *dev, 326 static ssize_t ahci_activity_store(struct ata_device *dev,
327 enum sw_activity val); 327 enum sw_activity val);
328 static void ahci_init_sw_activity(struct ata_link *link); 328 static void ahci_init_sw_activity(struct ata_link *link);
329 329
330 static struct device_attribute *ahci_shost_attrs[] = { 330 static struct device_attribute *ahci_shost_attrs[] = {
331 &dev_attr_link_power_management_policy, 331 &dev_attr_link_power_management_policy,
332 &dev_attr_em_message_type, 332 &dev_attr_em_message_type,
333 &dev_attr_em_message, 333 &dev_attr_em_message,
334 NULL 334 NULL
335 }; 335 };
336 336
337 static struct device_attribute *ahci_sdev_attrs[] = { 337 static struct device_attribute *ahci_sdev_attrs[] = {
338 &dev_attr_sw_activity, 338 &dev_attr_sw_activity,
339 &dev_attr_unload_heads, 339 &dev_attr_unload_heads,
340 NULL 340 NULL
341 }; 341 };
342 342
343 static struct scsi_host_template ahci_sht = { 343 static struct scsi_host_template ahci_sht = {
344 ATA_NCQ_SHT(DRV_NAME), 344 ATA_NCQ_SHT(DRV_NAME),
345 .can_queue = AHCI_MAX_CMDS - 1, 345 .can_queue = AHCI_MAX_CMDS - 1,
346 .sg_tablesize = AHCI_MAX_SG, 346 .sg_tablesize = AHCI_MAX_SG,
347 .dma_boundary = AHCI_DMA_BOUNDARY, 347 .dma_boundary = AHCI_DMA_BOUNDARY,
348 .shost_attrs = ahci_shost_attrs, 348 .shost_attrs = ahci_shost_attrs,
349 .sdev_attrs = ahci_sdev_attrs, 349 .sdev_attrs = ahci_sdev_attrs,
350 }; 350 };
351 351
352 static struct ata_port_operations ahci_ops = { 352 static struct ata_port_operations ahci_ops = {
353 .inherits = &sata_pmp_port_ops, 353 .inherits = &sata_pmp_port_ops,
354 354
355 .qc_defer = sata_pmp_qc_defer_cmd_switch, 355 .qc_defer = sata_pmp_qc_defer_cmd_switch,
356 .qc_prep = ahci_qc_prep, 356 .qc_prep = ahci_qc_prep,
357 .qc_issue = ahci_qc_issue, 357 .qc_issue = ahci_qc_issue,
358 .qc_fill_rtf = ahci_qc_fill_rtf, 358 .qc_fill_rtf = ahci_qc_fill_rtf,
359 359
360 .freeze = ahci_freeze, 360 .freeze = ahci_freeze,
361 .thaw = ahci_thaw, 361 .thaw = ahci_thaw,
362 .softreset = ahci_softreset, 362 .softreset = ahci_softreset,
363 .hardreset = ahci_hardreset, 363 .hardreset = ahci_hardreset,
364 .postreset = ahci_postreset, 364 .postreset = ahci_postreset,
365 .pmp_softreset = ahci_softreset, 365 .pmp_softreset = ahci_softreset,
366 .error_handler = ahci_error_handler, 366 .error_handler = ahci_error_handler,
367 .post_internal_cmd = ahci_post_internal_cmd, 367 .post_internal_cmd = ahci_post_internal_cmd,
368 .dev_config = ahci_dev_config, 368 .dev_config = ahci_dev_config,
369 369
370 .scr_read = ahci_scr_read, 370 .scr_read = ahci_scr_read,
371 .scr_write = ahci_scr_write, 371 .scr_write = ahci_scr_write,
372 .pmp_attach = ahci_pmp_attach, 372 .pmp_attach = ahci_pmp_attach,
373 .pmp_detach = ahci_pmp_detach, 373 .pmp_detach = ahci_pmp_detach,
374 374
375 .enable_pm = ahci_enable_alpm, 375 .enable_pm = ahci_enable_alpm,
376 .disable_pm = ahci_disable_alpm, 376 .disable_pm = ahci_disable_alpm,
377 .em_show = ahci_led_show, 377 .em_show = ahci_led_show,
378 .em_store = ahci_led_store, 378 .em_store = ahci_led_store,
379 .sw_activity_show = ahci_activity_show, 379 .sw_activity_show = ahci_activity_show,
380 .sw_activity_store = ahci_activity_store, 380 .sw_activity_store = ahci_activity_store,
381 #ifdef CONFIG_PM 381 #ifdef CONFIG_PM
382 .port_suspend = ahci_port_suspend, 382 .port_suspend = ahci_port_suspend,
383 .port_resume = ahci_port_resume, 383 .port_resume = ahci_port_resume,
384 #endif 384 #endif
385 .port_start = ahci_port_start, 385 .port_start = ahci_port_start,
386 .port_stop = ahci_port_stop, 386 .port_stop = ahci_port_stop,
387 }; 387 };
388 388
389 static struct ata_port_operations ahci_vt8251_ops = { 389 static struct ata_port_operations ahci_vt8251_ops = {
390 .inherits = &ahci_ops, 390 .inherits = &ahci_ops,
391 .hardreset = ahci_vt8251_hardreset, 391 .hardreset = ahci_vt8251_hardreset,
392 }; 392 };
393 393
394 static struct ata_port_operations ahci_p5wdh_ops = { 394 static struct ata_port_operations ahci_p5wdh_ops = {
395 .inherits = &ahci_ops, 395 .inherits = &ahci_ops,
396 .hardreset = ahci_p5wdh_hardreset, 396 .hardreset = ahci_p5wdh_hardreset,
397 }; 397 };
398 398
399 static struct ata_port_operations ahci_sb600_ops = { 399 static struct ata_port_operations ahci_sb600_ops = {
400 .inherits = &ahci_ops, 400 .inherits = &ahci_ops,
401 .softreset = ahci_sb600_softreset, 401 .softreset = ahci_sb600_softreset,
402 .pmp_softreset = ahci_sb600_softreset, 402 .pmp_softreset = ahci_sb600_softreset,
403 }; 403 };
404 404
405 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags) 405 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
406 406
407 static const struct ata_port_info ahci_port_info[] = { 407 static const struct ata_port_info ahci_port_info[] = {
408 [board_ahci] = 408 [board_ahci] =
409 { 409 {
410 .flags = AHCI_FLAG_COMMON, 410 .flags = AHCI_FLAG_COMMON,
411 .pio_mask = ATA_PIO4, 411 .pio_mask = ATA_PIO4,
412 .udma_mask = ATA_UDMA6, 412 .udma_mask = ATA_UDMA6,
413 .port_ops = &ahci_ops, 413 .port_ops = &ahci_ops,
414 }, 414 },
415 [board_ahci_vt8251] = 415 [board_ahci_vt8251] =
416 { 416 {
417 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), 417 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
418 .flags = AHCI_FLAG_COMMON, 418 .flags = AHCI_FLAG_COMMON,
419 .pio_mask = ATA_PIO4, 419 .pio_mask = ATA_PIO4,
420 .udma_mask = ATA_UDMA6, 420 .udma_mask = ATA_UDMA6,
421 .port_ops = &ahci_vt8251_ops, 421 .port_ops = &ahci_vt8251_ops,
422 }, 422 },
423 [board_ahci_ign_iferr] = 423 [board_ahci_ign_iferr] =
424 { 424 {
425 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), 425 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
426 .flags = AHCI_FLAG_COMMON, 426 .flags = AHCI_FLAG_COMMON,
427 .pio_mask = ATA_PIO4, 427 .pio_mask = ATA_PIO4,
428 .udma_mask = ATA_UDMA6, 428 .udma_mask = ATA_UDMA6,
429 .port_ops = &ahci_ops, 429 .port_ops = &ahci_ops,
430 }, 430 },
431 [board_ahci_sb600] = 431 [board_ahci_sb600] =
432 { 432 {
433 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | 433 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
434 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI | 434 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255),
435 AHCI_HFLAG_SECT255),
436 .flags = AHCI_FLAG_COMMON, 435 .flags = AHCI_FLAG_COMMON,
437 .pio_mask = ATA_PIO4, 436 .pio_mask = ATA_PIO4,
438 .udma_mask = ATA_UDMA6, 437 .udma_mask = ATA_UDMA6,
439 .port_ops = &ahci_sb600_ops, 438 .port_ops = &ahci_sb600_ops,
440 }, 439 },
441 [board_ahci_mv] = 440 [board_ahci_mv] =
442 { 441 {
443 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | 442 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
444 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), 443 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
445 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 444 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
446 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA, 445 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
447 .pio_mask = ATA_PIO4, 446 .pio_mask = ATA_PIO4,
448 .udma_mask = ATA_UDMA6, 447 .udma_mask = ATA_UDMA6,
449 .port_ops = &ahci_ops, 448 .port_ops = &ahci_ops,
450 }, 449 },
451 [board_ahci_sb700] = /* for SB700 and SB800 */ 450 [board_ahci_sb700] = /* for SB700 and SB800 */
452 { 451 {
453 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), 452 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
454 .flags = AHCI_FLAG_COMMON, 453 .flags = AHCI_FLAG_COMMON,
455 .pio_mask = ATA_PIO4, 454 .pio_mask = ATA_PIO4,
456 .udma_mask = ATA_UDMA6, 455 .udma_mask = ATA_UDMA6,
457 .port_ops = &ahci_sb600_ops, 456 .port_ops = &ahci_sb600_ops,
458 }, 457 },
459 [board_ahci_mcp65] = 458 [board_ahci_mcp65] =
460 { 459 {
461 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ), 460 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
462 .flags = AHCI_FLAG_COMMON, 461 .flags = AHCI_FLAG_COMMON,
463 .pio_mask = ATA_PIO4, 462 .pio_mask = ATA_PIO4,
464 .udma_mask = ATA_UDMA6, 463 .udma_mask = ATA_UDMA6,
465 .port_ops = &ahci_ops, 464 .port_ops = &ahci_ops,
466 }, 465 },
467 [board_ahci_nopmp] = 466 [board_ahci_nopmp] =
468 { 467 {
469 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP), 468 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
470 .flags = AHCI_FLAG_COMMON, 469 .flags = AHCI_FLAG_COMMON,
471 .pio_mask = ATA_PIO4, 470 .pio_mask = ATA_PIO4,
472 .udma_mask = ATA_UDMA6, 471 .udma_mask = ATA_UDMA6,
473 .port_ops = &ahci_ops, 472 .port_ops = &ahci_ops,
474 }, 473 },
475 /* board_ahci_yesncq */ 474 /* board_ahci_yesncq */
476 { 475 {
477 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ), 476 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
478 .flags = AHCI_FLAG_COMMON, 477 .flags = AHCI_FLAG_COMMON,
479 .pio_mask = ATA_PIO4, 478 .pio_mask = ATA_PIO4,
480 .udma_mask = ATA_UDMA6, 479 .udma_mask = ATA_UDMA6,
481 .port_ops = &ahci_ops, 480 .port_ops = &ahci_ops,
482 }, 481 },
483 }; 482 };
484 483
485 static const struct pci_device_id ahci_pci_tbl[] = { 484 static const struct pci_device_id ahci_pci_tbl[] = {
486 /* Intel */ 485 /* Intel */
487 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ 486 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
488 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ 487 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
489 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ 488 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
490 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ 489 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
491 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ 490 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
492 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ 491 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
493 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ 492 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
494 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ 493 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
495 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ 494 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
496 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ 495 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
497 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ 496 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
498 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */ 497 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
499 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ 498 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
500 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ 499 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
501 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ 500 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
502 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ 501 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
503 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ 502 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
504 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ 503 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
505 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ 504 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
506 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ 505 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
507 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */ 506 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
508 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */ 507 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
509 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */ 508 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
510 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */ 509 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
511 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */ 510 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
512 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ 511 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
513 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */ 512 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
514 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ 513 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
515 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ 514 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
516 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ 515 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
517 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ 516 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
518 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ 517 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
519 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ 518 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
520 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ 519 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
521 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */ 520 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
522 521
523 /* JMicron 360/1/3/5/6, match class to avoid IDE function */ 522 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
524 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 523 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
525 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, 524 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
526 525
527 /* ATI */ 526 /* ATI */
528 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ 527 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
529 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ 528 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
530 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ 529 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
531 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ 530 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
532 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ 531 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
533 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ 532 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
534 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ 533 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
535 534
536 /* VIA */ 535 /* VIA */
537 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ 536 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
538 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ 537 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
539 538
540 /* NVIDIA */ 539 /* NVIDIA */
541 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ 540 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
542 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ 541 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
543 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ 542 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
544 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ 543 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
545 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ 544 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
546 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ 545 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
547 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ 546 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
548 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ 547 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
549 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_yesncq }, /* MCP67 */ 548 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_yesncq }, /* MCP67 */
550 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_yesncq }, /* MCP67 */ 549 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_yesncq }, /* MCP67 */
551 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_yesncq }, /* MCP67 */ 550 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_yesncq }, /* MCP67 */
552 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_yesncq }, /* MCP67 */ 551 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_yesncq }, /* MCP67 */
553 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_yesncq }, /* MCP67 */ 552 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_yesncq }, /* MCP67 */
554 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_yesncq }, /* MCP67 */ 553 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_yesncq }, /* MCP67 */
555 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_yesncq }, /* MCP67 */ 554 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_yesncq }, /* MCP67 */
556 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_yesncq }, /* MCP67 */ 555 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_yesncq }, /* MCP67 */
557 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_yesncq }, /* MCP67 */ 556 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_yesncq }, /* MCP67 */
558 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_yesncq }, /* MCP67 */ 557 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_yesncq }, /* MCP67 */
559 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_yesncq }, /* MCP67 */ 558 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_yesncq }, /* MCP67 */
560 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_yesncq }, /* MCP67 */ 559 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_yesncq }, /* MCP67 */
561 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_yesncq }, /* MCP73 */ 560 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_yesncq }, /* MCP73 */
562 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_yesncq }, /* MCP73 */ 561 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_yesncq }, /* MCP73 */
563 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_yesncq }, /* MCP73 */ 562 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_yesncq }, /* MCP73 */
564 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_yesncq }, /* MCP73 */ 563 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_yesncq }, /* MCP73 */
565 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_yesncq }, /* MCP73 */ 564 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_yesncq }, /* MCP73 */
566 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_yesncq }, /* MCP73 */ 565 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_yesncq }, /* MCP73 */
567 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_yesncq }, /* MCP73 */ 566 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_yesncq }, /* MCP73 */
568 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_yesncq }, /* MCP73 */ 567 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_yesncq }, /* MCP73 */
569 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_yesncq }, /* MCP73 */ 568 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_yesncq }, /* MCP73 */
570 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_yesncq }, /* MCP73 */ 569 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_yesncq }, /* MCP73 */
571 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_yesncq }, /* MCP73 */ 570 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_yesncq }, /* MCP73 */
572 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_yesncq }, /* MCP73 */ 571 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_yesncq }, /* MCP73 */
573 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */ 572 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
574 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */ 573 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
575 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */ 574 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
576 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */ 575 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
577 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */ 576 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
578 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */ 577 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
579 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */ 578 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
580 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */ 579 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
581 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */ 580 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
582 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */ 581 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
583 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */ 582 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
584 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */ 583 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
585 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */ 584 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
586 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */ 585 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
587 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */ 586 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
588 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */ 587 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
589 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */ 588 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
590 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */ 589 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
591 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */ 590 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
592 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */ 591 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
593 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */ 592 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
594 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */ 593 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
595 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */ 594 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
596 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */ 595 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
597 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci }, /* MCP89 */ 596 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci }, /* MCP89 */
598 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci }, /* MCP89 */ 597 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci }, /* MCP89 */
599 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci }, /* MCP89 */ 598 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci }, /* MCP89 */
600 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci }, /* MCP89 */ 599 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci }, /* MCP89 */
601 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci }, /* MCP89 */ 600 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci }, /* MCP89 */
602 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci }, /* MCP89 */ 601 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci }, /* MCP89 */
603 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci }, /* MCP89 */ 602 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci }, /* MCP89 */
604 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci }, /* MCP89 */ 603 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci }, /* MCP89 */
605 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci }, /* MCP89 */ 604 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci }, /* MCP89 */
606 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci }, /* MCP89 */ 605 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci }, /* MCP89 */
607 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci }, /* MCP89 */ 606 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci }, /* MCP89 */
608 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci }, /* MCP89 */ 607 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci }, /* MCP89 */
609 608
610 /* SiS */ 609 /* SiS */
611 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ 610 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
612 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ 611 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
613 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ 612 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
614 613
615 /* Marvell */ 614 /* Marvell */
616 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ 615 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
617 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ 616 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
618 617
619 /* Promise */ 618 /* Promise */
620 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ 619 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
621 620
622 /* Generic, PCI class code for AHCI */ 621 /* Generic, PCI class code for AHCI */
623 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 622 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
624 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, 623 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
625 624
626 { } /* terminate list */ 625 { } /* terminate list */
627 }; 626 };
628 627
629 628
630 static struct pci_driver ahci_pci_driver = { 629 static struct pci_driver ahci_pci_driver = {
631 .name = DRV_NAME, 630 .name = DRV_NAME,
632 .id_table = ahci_pci_tbl, 631 .id_table = ahci_pci_tbl,
633 .probe = ahci_init_one, 632 .probe = ahci_init_one,
634 .remove = ata_pci_remove_one, 633 .remove = ata_pci_remove_one,
635 #ifdef CONFIG_PM 634 #ifdef CONFIG_PM
636 .suspend = ahci_pci_device_suspend, 635 .suspend = ahci_pci_device_suspend,
637 .resume = ahci_pci_device_resume, 636 .resume = ahci_pci_device_resume,
638 #endif 637 #endif
639 }; 638 };
640 639
641 static int ahci_em_messages = 1; 640 static int ahci_em_messages = 1;
642 module_param(ahci_em_messages, int, 0444); 641 module_param(ahci_em_messages, int, 0444);
643 /* add other LED protocol types when they become supported */ 642 /* add other LED protocol types when they become supported */
644 MODULE_PARM_DESC(ahci_em_messages, 643 MODULE_PARM_DESC(ahci_em_messages,
645 "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED"); 644 "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
646 645
647 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE) 646 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
648 static int marvell_enable; 647 static int marvell_enable;
649 #else 648 #else
650 static int marvell_enable = 1; 649 static int marvell_enable = 1;
651 #endif 650 #endif
652 module_param(marvell_enable, int, 0644); 651 module_param(marvell_enable, int, 0644);
653 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); 652 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
654 653
655 654
656 static inline int ahci_nr_ports(u32 cap) 655 static inline int ahci_nr_ports(u32 cap)
657 { 656 {
658 return (cap & 0x1f) + 1; 657 return (cap & 0x1f) + 1;
659 } 658 }
660 659
661 static inline void __iomem *__ahci_port_base(struct ata_host *host, 660 static inline void __iomem *__ahci_port_base(struct ata_host *host,
662 unsigned int port_no) 661 unsigned int port_no)
663 { 662 {
664 void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; 663 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
665 664
666 return mmio + 0x100 + (port_no * 0x80); 665 return mmio + 0x100 + (port_no * 0x80);
667 } 666 }
668 667
669 static inline void __iomem *ahci_port_base(struct ata_port *ap) 668 static inline void __iomem *ahci_port_base(struct ata_port *ap)
670 { 669 {
671 return __ahci_port_base(ap->host, ap->port_no); 670 return __ahci_port_base(ap->host, ap->port_no);
672 } 671 }
673 672
674 static void ahci_enable_ahci(void __iomem *mmio) 673 static void ahci_enable_ahci(void __iomem *mmio)
675 { 674 {
676 int i; 675 int i;
677 u32 tmp; 676 u32 tmp;
678 677
679 /* turn on AHCI_EN */ 678 /* turn on AHCI_EN */
680 tmp = readl(mmio + HOST_CTL); 679 tmp = readl(mmio + HOST_CTL);
681 if (tmp & HOST_AHCI_EN) 680 if (tmp & HOST_AHCI_EN)
682 return; 681 return;
683 682
684 /* Some controllers need AHCI_EN to be written multiple times. 683 /* Some controllers need AHCI_EN to be written multiple times.
685 * Try a few times before giving up. 684 * Try a few times before giving up.
686 */ 685 */
687 for (i = 0; i < 5; i++) { 686 for (i = 0; i < 5; i++) {
688 tmp |= HOST_AHCI_EN; 687 tmp |= HOST_AHCI_EN;
689 writel(tmp, mmio + HOST_CTL); 688 writel(tmp, mmio + HOST_CTL);
690 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ 689 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
691 if (tmp & HOST_AHCI_EN) 690 if (tmp & HOST_AHCI_EN)
692 return; 691 return;
693 msleep(10); 692 msleep(10);
694 } 693 }
695 694
696 WARN_ON(1); 695 WARN_ON(1);
697 } 696 }
698 697
699 /** 698 /**
700 * ahci_save_initial_config - Save and fixup initial config values 699 * ahci_save_initial_config - Save and fixup initial config values
701 * @pdev: target PCI device 700 * @pdev: target PCI device
702 * @hpriv: host private area to store config values 701 * @hpriv: host private area to store config values
703 * 702 *
704 * Some registers containing configuration info might be setup by 703 * Some registers containing configuration info might be setup by
705 * BIOS and might be cleared on reset. This function saves the 704 * BIOS and might be cleared on reset. This function saves the
706 * initial values of those registers into @hpriv such that they 705 * initial values of those registers into @hpriv such that they
707 * can be restored after controller reset. 706 * can be restored after controller reset.
708 * 707 *
709 * If inconsistent, config values are fixed up by this function. 708 * If inconsistent, config values are fixed up by this function.
710 * 709 *
711 * LOCKING: 710 * LOCKING:
712 * None. 711 * None.
713 */ 712 */
714 static void ahci_save_initial_config(struct pci_dev *pdev, 713 static void ahci_save_initial_config(struct pci_dev *pdev,
715 struct ahci_host_priv *hpriv) 714 struct ahci_host_priv *hpriv)
716 { 715 {
717 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; 716 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
718 u32 cap, port_map; 717 u32 cap, port_map;
719 int i; 718 int i;
720 int mv; 719 int mv;
721 720
722 /* make sure AHCI mode is enabled before accessing CAP */ 721 /* make sure AHCI mode is enabled before accessing CAP */
723 ahci_enable_ahci(mmio); 722 ahci_enable_ahci(mmio);
724 723
725 /* Values prefixed with saved_ are written back to host after 724 /* Values prefixed with saved_ are written back to host after
726 * reset. Values without are used for driver operation. 725 * reset. Values without are used for driver operation.
727 */ 726 */
728 hpriv->saved_cap = cap = readl(mmio + HOST_CAP); 727 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
729 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); 728 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
730 729
731 /* some chips have errata preventing 64bit use */ 730 /* some chips have errata preventing 64bit use */
732 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { 731 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
733 dev_printk(KERN_INFO, &pdev->dev, 732 dev_printk(KERN_INFO, &pdev->dev,
734 "controller can't do 64bit DMA, forcing 32bit\n"); 733 "controller can't do 64bit DMA, forcing 32bit\n");
735 cap &= ~HOST_CAP_64; 734 cap &= ~HOST_CAP_64;
736 } 735 }
737 736
738 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { 737 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
739 dev_printk(KERN_INFO, &pdev->dev, 738 dev_printk(KERN_INFO, &pdev->dev,
740 "controller can't do NCQ, turning off CAP_NCQ\n"); 739 "controller can't do NCQ, turning off CAP_NCQ\n");
741 cap &= ~HOST_CAP_NCQ; 740 cap &= ~HOST_CAP_NCQ;
742 } 741 }
743 742
744 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) { 743 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
745 dev_printk(KERN_INFO, &pdev->dev, 744 dev_printk(KERN_INFO, &pdev->dev,
746 "controller can do NCQ, turning on CAP_NCQ\n"); 745 "controller can do NCQ, turning on CAP_NCQ\n");
747 cap |= HOST_CAP_NCQ; 746 cap |= HOST_CAP_NCQ;
748 } 747 }
749 748
750 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { 749 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
751 dev_printk(KERN_INFO, &pdev->dev, 750 dev_printk(KERN_INFO, &pdev->dev,
752 "controller can't do PMP, turning off CAP_PMP\n"); 751 "controller can't do PMP, turning off CAP_PMP\n");
753 cap &= ~HOST_CAP_PMP; 752 cap &= ~HOST_CAP_PMP;
754 } 753 }
755 754
756 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 && 755 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
757 port_map != 1) { 756 port_map != 1) {
758 dev_printk(KERN_INFO, &pdev->dev, 757 dev_printk(KERN_INFO, &pdev->dev,
759 "JMB361 has only one port, port_map 0x%x -> 0x%x\n", 758 "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
760 port_map, 1); 759 port_map, 1);
761 port_map = 1; 760 port_map = 1;
762 } 761 }
763 762
764 /* 763 /*
765 * Temporary Marvell 6145 hack: PATA port presence 764 * Temporary Marvell 6145 hack: PATA port presence
766 * is asserted through the standard AHCI port 765 * is asserted through the standard AHCI port
767 * presence register, as bit 4 (counting from 0) 766 * presence register, as bit 4 (counting from 0)
768 */ 767 */
769 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 768 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
770 if (pdev->device == 0x6121) 769 if (pdev->device == 0x6121)
771 mv = 0x3; 770 mv = 0x3;
772 else 771 else
773 mv = 0xf; 772 mv = 0xf;
774 dev_printk(KERN_ERR, &pdev->dev, 773 dev_printk(KERN_ERR, &pdev->dev,
775 "MV_AHCI HACK: port_map %x -> %x\n", 774 "MV_AHCI HACK: port_map %x -> %x\n",
776 port_map, 775 port_map,
777 port_map & mv); 776 port_map & mv);
778 dev_printk(KERN_ERR, &pdev->dev, 777 dev_printk(KERN_ERR, &pdev->dev,
779 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); 778 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
780 779
781 port_map &= mv; 780 port_map &= mv;
782 } 781 }
783 782
784 /* cross check port_map and cap.n_ports */ 783 /* cross check port_map and cap.n_ports */
785 if (port_map) { 784 if (port_map) {
786 int map_ports = 0; 785 int map_ports = 0;
787 786
788 for (i = 0; i < AHCI_MAX_PORTS; i++) 787 for (i = 0; i < AHCI_MAX_PORTS; i++)
789 if (port_map & (1 << i)) 788 if (port_map & (1 << i))
790 map_ports++; 789 map_ports++;
791 790
792 /* If PI has more ports than n_ports, whine, clear 791 /* If PI has more ports than n_ports, whine, clear
793 * port_map and let it be generated from n_ports. 792 * port_map and let it be generated from n_ports.
794 */ 793 */
795 if (map_ports > ahci_nr_ports(cap)) { 794 if (map_ports > ahci_nr_ports(cap)) {
796 dev_printk(KERN_WARNING, &pdev->dev, 795 dev_printk(KERN_WARNING, &pdev->dev,
797 "implemented port map (0x%x) contains more " 796 "implemented port map (0x%x) contains more "
798 "ports than nr_ports (%u), using nr_ports\n", 797 "ports than nr_ports (%u), using nr_ports\n",
799 port_map, ahci_nr_ports(cap)); 798 port_map, ahci_nr_ports(cap));
800 port_map = 0; 799 port_map = 0;
801 } 800 }
802 } 801 }
803 802
804 /* fabricate port_map from cap.nr_ports */ 803 /* fabricate port_map from cap.nr_ports */
805 if (!port_map) { 804 if (!port_map) {
806 port_map = (1 << ahci_nr_ports(cap)) - 1; 805 port_map = (1 << ahci_nr_ports(cap)) - 1;
807 dev_printk(KERN_WARNING, &pdev->dev, 806 dev_printk(KERN_WARNING, &pdev->dev,
808 "forcing PORTS_IMPL to 0x%x\n", port_map); 807 "forcing PORTS_IMPL to 0x%x\n", port_map);
809 808
810 /* write the fixed up value to the PI register */ 809 /* write the fixed up value to the PI register */
811 hpriv->saved_port_map = port_map; 810 hpriv->saved_port_map = port_map;
812 } 811 }
813 812
814 /* record values to use during operation */ 813 /* record values to use during operation */
815 hpriv->cap = cap; 814 hpriv->cap = cap;
816 hpriv->port_map = port_map; 815 hpriv->port_map = port_map;
817 } 816 }
818 817
819 /** 818 /**
820 * ahci_restore_initial_config - Restore initial config 819 * ahci_restore_initial_config - Restore initial config
821 * @host: target ATA host 820 * @host: target ATA host
822 * 821 *
823 * Restore initial config stored by ahci_save_initial_config(). 822 * Restore initial config stored by ahci_save_initial_config().
824 * 823 *
825 * LOCKING: 824 * LOCKING:
826 * None. 825 * None.
827 */ 826 */
828 static void ahci_restore_initial_config(struct ata_host *host) 827 static void ahci_restore_initial_config(struct ata_host *host)
829 { 828 {
830 struct ahci_host_priv *hpriv = host->private_data; 829 struct ahci_host_priv *hpriv = host->private_data;
831 void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; 830 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
832 831
833 writel(hpriv->saved_cap, mmio + HOST_CAP); 832 writel(hpriv->saved_cap, mmio + HOST_CAP);
834 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); 833 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
835 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ 834 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
836 } 835 }
837 836
838 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) 837 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
839 { 838 {
840 static const int offset[] = { 839 static const int offset[] = {
841 [SCR_STATUS] = PORT_SCR_STAT, 840 [SCR_STATUS] = PORT_SCR_STAT,
842 [SCR_CONTROL] = PORT_SCR_CTL, 841 [SCR_CONTROL] = PORT_SCR_CTL,
843 [SCR_ERROR] = PORT_SCR_ERR, 842 [SCR_ERROR] = PORT_SCR_ERR,
844 [SCR_ACTIVE] = PORT_SCR_ACT, 843 [SCR_ACTIVE] = PORT_SCR_ACT,
845 [SCR_NOTIFICATION] = PORT_SCR_NTF, 844 [SCR_NOTIFICATION] = PORT_SCR_NTF,
846 }; 845 };
847 struct ahci_host_priv *hpriv = ap->host->private_data; 846 struct ahci_host_priv *hpriv = ap->host->private_data;
848 847
849 if (sc_reg < ARRAY_SIZE(offset) && 848 if (sc_reg < ARRAY_SIZE(offset) &&
850 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) 849 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
851 return offset[sc_reg]; 850 return offset[sc_reg];
852 return 0; 851 return 0;
853 } 852 }
854 853
855 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) 854 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
856 { 855 {
857 void __iomem *port_mmio = ahci_port_base(link->ap); 856 void __iomem *port_mmio = ahci_port_base(link->ap);
858 int offset = ahci_scr_offset(link->ap, sc_reg); 857 int offset = ahci_scr_offset(link->ap, sc_reg);
859 858
860 if (offset) { 859 if (offset) {
861 *val = readl(port_mmio + offset); 860 *val = readl(port_mmio + offset);
862 return 0; 861 return 0;
863 } 862 }
864 return -EINVAL; 863 return -EINVAL;
865 } 864 }
866 865
867 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) 866 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
868 { 867 {
869 void __iomem *port_mmio = ahci_port_base(link->ap); 868 void __iomem *port_mmio = ahci_port_base(link->ap);
870 int offset = ahci_scr_offset(link->ap, sc_reg); 869 int offset = ahci_scr_offset(link->ap, sc_reg);
871 870
872 if (offset) { 871 if (offset) {
873 writel(val, port_mmio + offset); 872 writel(val, port_mmio + offset);
874 return 0; 873 return 0;
875 } 874 }
876 return -EINVAL; 875 return -EINVAL;
877 } 876 }
878 877
879 static void ahci_start_engine(struct ata_port *ap) 878 static void ahci_start_engine(struct ata_port *ap)
880 { 879 {
881 void __iomem *port_mmio = ahci_port_base(ap); 880 void __iomem *port_mmio = ahci_port_base(ap);
882 u32 tmp; 881 u32 tmp;
883 882
884 /* start DMA */ 883 /* start DMA */
885 tmp = readl(port_mmio + PORT_CMD); 884 tmp = readl(port_mmio + PORT_CMD);
886 tmp |= PORT_CMD_START; 885 tmp |= PORT_CMD_START;
887 writel(tmp, port_mmio + PORT_CMD); 886 writel(tmp, port_mmio + PORT_CMD);
888 readl(port_mmio + PORT_CMD); /* flush */ 887 readl(port_mmio + PORT_CMD); /* flush */
889 } 888 }
890 889
891 static int ahci_stop_engine(struct ata_port *ap) 890 static int ahci_stop_engine(struct ata_port *ap)
892 { 891 {
893 void __iomem *port_mmio = ahci_port_base(ap); 892 void __iomem *port_mmio = ahci_port_base(ap);
894 u32 tmp; 893 u32 tmp;
895 894
896 tmp = readl(port_mmio + PORT_CMD); 895 tmp = readl(port_mmio + PORT_CMD);
897 896
898 /* check if the HBA is idle */ 897 /* check if the HBA is idle */
899 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) 898 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
900 return 0; 899 return 0;
901 900
902 /* setting HBA to idle */ 901 /* setting HBA to idle */
903 tmp &= ~PORT_CMD_START; 902 tmp &= ~PORT_CMD_START;
904 writel(tmp, port_mmio + PORT_CMD); 903 writel(tmp, port_mmio + PORT_CMD);
905 904
906 /* wait for engine to stop. This could be as long as 500 msec */ 905 /* wait for engine to stop. This could be as long as 500 msec */
907 tmp = ata_wait_register(port_mmio + PORT_CMD, 906 tmp = ata_wait_register(port_mmio + PORT_CMD,
908 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); 907 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
909 if (tmp & PORT_CMD_LIST_ON) 908 if (tmp & PORT_CMD_LIST_ON)
910 return -EIO; 909 return -EIO;
911 910
912 return 0; 911 return 0;
913 } 912 }
914 913
915 static void ahci_start_fis_rx(struct ata_port *ap) 914 static void ahci_start_fis_rx(struct ata_port *ap)
916 { 915 {
917 void __iomem *port_mmio = ahci_port_base(ap); 916 void __iomem *port_mmio = ahci_port_base(ap);
918 struct ahci_host_priv *hpriv = ap->host->private_data; 917 struct ahci_host_priv *hpriv = ap->host->private_data;
919 struct ahci_port_priv *pp = ap->private_data; 918 struct ahci_port_priv *pp = ap->private_data;
920 u32 tmp; 919 u32 tmp;
921 920
922 /* set FIS registers */ 921 /* set FIS registers */
923 if (hpriv->cap & HOST_CAP_64) 922 if (hpriv->cap & HOST_CAP_64)
924 writel((pp->cmd_slot_dma >> 16) >> 16, 923 writel((pp->cmd_slot_dma >> 16) >> 16,
925 port_mmio + PORT_LST_ADDR_HI); 924 port_mmio + PORT_LST_ADDR_HI);
926 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); 925 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
927 926
928 if (hpriv->cap & HOST_CAP_64) 927 if (hpriv->cap & HOST_CAP_64)
929 writel((pp->rx_fis_dma >> 16) >> 16, 928 writel((pp->rx_fis_dma >> 16) >> 16,
930 port_mmio + PORT_FIS_ADDR_HI); 929 port_mmio + PORT_FIS_ADDR_HI);
931 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); 930 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
932 931
933 /* enable FIS reception */ 932 /* enable FIS reception */
934 tmp = readl(port_mmio + PORT_CMD); 933 tmp = readl(port_mmio + PORT_CMD);
935 tmp |= PORT_CMD_FIS_RX; 934 tmp |= PORT_CMD_FIS_RX;
936 writel(tmp, port_mmio + PORT_CMD); 935 writel(tmp, port_mmio + PORT_CMD);
937 936
938 /* flush */ 937 /* flush */
939 readl(port_mmio + PORT_CMD); 938 readl(port_mmio + PORT_CMD);
940 } 939 }
941 940
942 static int ahci_stop_fis_rx(struct ata_port *ap) 941 static int ahci_stop_fis_rx(struct ata_port *ap)
943 { 942 {
944 void __iomem *port_mmio = ahci_port_base(ap); 943 void __iomem *port_mmio = ahci_port_base(ap);
945 u32 tmp; 944 u32 tmp;
946 945
947 /* disable FIS reception */ 946 /* disable FIS reception */
948 tmp = readl(port_mmio + PORT_CMD); 947 tmp = readl(port_mmio + PORT_CMD);
949 tmp &= ~PORT_CMD_FIS_RX; 948 tmp &= ~PORT_CMD_FIS_RX;
950 writel(tmp, port_mmio + PORT_CMD); 949 writel(tmp, port_mmio + PORT_CMD);
951 950
952 /* wait for completion, spec says 500ms, give it 1000 */ 951 /* wait for completion, spec says 500ms, give it 1000 */
953 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, 952 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
954 PORT_CMD_FIS_ON, 10, 1000); 953 PORT_CMD_FIS_ON, 10, 1000);
955 if (tmp & PORT_CMD_FIS_ON) 954 if (tmp & PORT_CMD_FIS_ON)
956 return -EBUSY; 955 return -EBUSY;
957 956
958 return 0; 957 return 0;
959 } 958 }
960 959
961 static void ahci_power_up(struct ata_port *ap) 960 static void ahci_power_up(struct ata_port *ap)
962 { 961 {
963 struct ahci_host_priv *hpriv = ap->host->private_data; 962 struct ahci_host_priv *hpriv = ap->host->private_data;
964 void __iomem *port_mmio = ahci_port_base(ap); 963 void __iomem *port_mmio = ahci_port_base(ap);
965 u32 cmd; 964 u32 cmd;
966 965
967 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 966 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
968 967
969 /* spin up device */ 968 /* spin up device */
970 if (hpriv->cap & HOST_CAP_SSS) { 969 if (hpriv->cap & HOST_CAP_SSS) {
971 cmd |= PORT_CMD_SPIN_UP; 970 cmd |= PORT_CMD_SPIN_UP;
972 writel(cmd, port_mmio + PORT_CMD); 971 writel(cmd, port_mmio + PORT_CMD);
973 } 972 }
974 973
975 /* wake up link */ 974 /* wake up link */
976 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); 975 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
977 } 976 }
978 977
979 static void ahci_disable_alpm(struct ata_port *ap) 978 static void ahci_disable_alpm(struct ata_port *ap)
980 { 979 {
981 struct ahci_host_priv *hpriv = ap->host->private_data; 980 struct ahci_host_priv *hpriv = ap->host->private_data;
982 void __iomem *port_mmio = ahci_port_base(ap); 981 void __iomem *port_mmio = ahci_port_base(ap);
983 u32 cmd; 982 u32 cmd;
984 struct ahci_port_priv *pp = ap->private_data; 983 struct ahci_port_priv *pp = ap->private_data;
985 984
986 /* IPM bits should be disabled by libata-core */ 985 /* IPM bits should be disabled by libata-core */
987 /* get the existing command bits */ 986 /* get the existing command bits */
988 cmd = readl(port_mmio + PORT_CMD); 987 cmd = readl(port_mmio + PORT_CMD);
989 988
990 /* disable ALPM and ASP */ 989 /* disable ALPM and ASP */
991 cmd &= ~PORT_CMD_ASP; 990 cmd &= ~PORT_CMD_ASP;
992 cmd &= ~PORT_CMD_ALPE; 991 cmd &= ~PORT_CMD_ALPE;
993 992
994 /* force the interface back to active */ 993 /* force the interface back to active */
995 cmd |= PORT_CMD_ICC_ACTIVE; 994 cmd |= PORT_CMD_ICC_ACTIVE;
996 995
997 /* write out new cmd value */ 996 /* write out new cmd value */
998 writel(cmd, port_mmio + PORT_CMD); 997 writel(cmd, port_mmio + PORT_CMD);
999 cmd = readl(port_mmio + PORT_CMD); 998 cmd = readl(port_mmio + PORT_CMD);
1000 999
1001 /* wait 10ms to be sure we've come out of any low power state */ 1000 /* wait 10ms to be sure we've come out of any low power state */
1002 msleep(10); 1001 msleep(10);
1003 1002
1004 /* clear out any PhyRdy stuff from interrupt status */ 1003 /* clear out any PhyRdy stuff from interrupt status */
1005 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT); 1004 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
1006 1005
1007 /* go ahead and clean out PhyRdy Change from Serror too */ 1006 /* go ahead and clean out PhyRdy Change from Serror too */
1008 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18))); 1007 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
1009 1008
1010 /* 1009 /*
1011 * Clear flag to indicate that we should ignore all PhyRdy 1010 * Clear flag to indicate that we should ignore all PhyRdy
1012 * state changes 1011 * state changes
1013 */ 1012 */
1014 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG; 1013 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
1015 1014
1016 /* 1015 /*
1017 * Enable interrupts on Phy Ready. 1016 * Enable interrupts on Phy Ready.
1018 */ 1017 */
1019 pp->intr_mask |= PORT_IRQ_PHYRDY; 1018 pp->intr_mask |= PORT_IRQ_PHYRDY;
1020 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 1019 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1021 1020
1022 /* 1021 /*
1023 * don't change the link pm policy - we can be called 1022 * don't change the link pm policy - we can be called
1024 * just to turn of link pm temporarily 1023 * just to turn of link pm temporarily
1025 */ 1024 */
1026 } 1025 }
1027 1026
1028 static int ahci_enable_alpm(struct ata_port *ap, 1027 static int ahci_enable_alpm(struct ata_port *ap,
1029 enum link_pm policy) 1028 enum link_pm policy)
1030 { 1029 {
1031 struct ahci_host_priv *hpriv = ap->host->private_data; 1030 struct ahci_host_priv *hpriv = ap->host->private_data;
1032 void __iomem *port_mmio = ahci_port_base(ap); 1031 void __iomem *port_mmio = ahci_port_base(ap);
1033 u32 cmd; 1032 u32 cmd;
1034 struct ahci_port_priv *pp = ap->private_data; 1033 struct ahci_port_priv *pp = ap->private_data;
1035 u32 asp; 1034 u32 asp;
1036 1035
1037 /* Make sure the host is capable of link power management */ 1036 /* Make sure the host is capable of link power management */
1038 if (!(hpriv->cap & HOST_CAP_ALPM)) 1037 if (!(hpriv->cap & HOST_CAP_ALPM))
1039 return -EINVAL; 1038 return -EINVAL;
1040 1039
1041 switch (policy) { 1040 switch (policy) {
1042 case MAX_PERFORMANCE: 1041 case MAX_PERFORMANCE:
1043 case NOT_AVAILABLE: 1042 case NOT_AVAILABLE:
1044 /* 1043 /*
1045 * if we came here with NOT_AVAILABLE, 1044 * if we came here with NOT_AVAILABLE,
1046 * it just means this is the first time we 1045 * it just means this is the first time we
1047 * have tried to enable - default to max performance, 1046 * have tried to enable - default to max performance,
1048 * and let the user go to lower power modes on request. 1047 * and let the user go to lower power modes on request.
1049 */ 1048 */
1050 ahci_disable_alpm(ap); 1049 ahci_disable_alpm(ap);
1051 return 0; 1050 return 0;
1052 case MIN_POWER: 1051 case MIN_POWER:
1053 /* configure HBA to enter SLUMBER */ 1052 /* configure HBA to enter SLUMBER */
1054 asp = PORT_CMD_ASP; 1053 asp = PORT_CMD_ASP;
1055 break; 1054 break;
1056 case MEDIUM_POWER: 1055 case MEDIUM_POWER:
1057 /* configure HBA to enter PARTIAL */ 1056 /* configure HBA to enter PARTIAL */
1058 asp = 0; 1057 asp = 0;
1059 break; 1058 break;
1060 default: 1059 default:
1061 return -EINVAL; 1060 return -EINVAL;
1062 } 1061 }
1063 1062
1064 /* 1063 /*
1065 * Disable interrupts on Phy Ready. This keeps us from 1064 * Disable interrupts on Phy Ready. This keeps us from
1066 * getting woken up due to spurious phy ready interrupts 1065 * getting woken up due to spurious phy ready interrupts
1067 * TBD - Hot plug should be done via polling now, is 1066 * TBD - Hot plug should be done via polling now, is
1068 * that even supported? 1067 * that even supported?
1069 */ 1068 */
1070 pp->intr_mask &= ~PORT_IRQ_PHYRDY; 1069 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
1071 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 1070 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1072 1071
1073 /* 1072 /*
1074 * Set a flag to indicate that we should ignore all PhyRdy 1073 * Set a flag to indicate that we should ignore all PhyRdy
1075 * state changes since these can happen now whenever we 1074 * state changes since these can happen now whenever we
1076 * change link state 1075 * change link state
1077 */ 1076 */
1078 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG; 1077 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1079 1078
1080 /* get the existing command bits */ 1079 /* get the existing command bits */
1081 cmd = readl(port_mmio + PORT_CMD); 1080 cmd = readl(port_mmio + PORT_CMD);
1082 1081
1083 /* 1082 /*
1084 * Set ASP based on Policy 1083 * Set ASP based on Policy
1085 */ 1084 */
1086 cmd |= asp; 1085 cmd |= asp;
1087 1086
1088 /* 1087 /*
1089 * Setting this bit will instruct the HBA to aggressively 1088 * Setting this bit will instruct the HBA to aggressively
1090 * enter a lower power link state when it's appropriate and 1089 * enter a lower power link state when it's appropriate and
1091 * based on the value set above for ASP 1090 * based on the value set above for ASP
1092 */ 1091 */
1093 cmd |= PORT_CMD_ALPE; 1092 cmd |= PORT_CMD_ALPE;
1094 1093
1095 /* write out new cmd value */ 1094 /* write out new cmd value */
1096 writel(cmd, port_mmio + PORT_CMD); 1095 writel(cmd, port_mmio + PORT_CMD);
1097 cmd = readl(port_mmio + PORT_CMD); 1096 cmd = readl(port_mmio + PORT_CMD);
1098 1097
1099 /* IPM bits should be set by libata-core */ 1098 /* IPM bits should be set by libata-core */
1100 return 0; 1099 return 0;
1101 } 1100 }
1102 1101
1103 #ifdef CONFIG_PM 1102 #ifdef CONFIG_PM
1104 static void ahci_power_down(struct ata_port *ap) 1103 static void ahci_power_down(struct ata_port *ap)
1105 { 1104 {
1106 struct ahci_host_priv *hpriv = ap->host->private_data; 1105 struct ahci_host_priv *hpriv = ap->host->private_data;
1107 void __iomem *port_mmio = ahci_port_base(ap); 1106 void __iomem *port_mmio = ahci_port_base(ap);
1108 u32 cmd, scontrol; 1107 u32 cmd, scontrol;
1109 1108
1110 if (!(hpriv->cap & HOST_CAP_SSS)) 1109 if (!(hpriv->cap & HOST_CAP_SSS))
1111 return; 1110 return;
1112 1111
1113 /* put device into listen mode, first set PxSCTL.DET to 0 */ 1112 /* put device into listen mode, first set PxSCTL.DET to 0 */
1114 scontrol = readl(port_mmio + PORT_SCR_CTL); 1113 scontrol = readl(port_mmio + PORT_SCR_CTL);
1115 scontrol &= ~0xf; 1114 scontrol &= ~0xf;
1116 writel(scontrol, port_mmio + PORT_SCR_CTL); 1115 writel(scontrol, port_mmio + PORT_SCR_CTL);
1117 1116
1118 /* then set PxCMD.SUD to 0 */ 1117 /* then set PxCMD.SUD to 0 */
1119 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 1118 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1120 cmd &= ~PORT_CMD_SPIN_UP; 1119 cmd &= ~PORT_CMD_SPIN_UP;
1121 writel(cmd, port_mmio + PORT_CMD); 1120 writel(cmd, port_mmio + PORT_CMD);
1122 } 1121 }
1123 #endif 1122 #endif
1124 1123
1125 static void ahci_start_port(struct ata_port *ap) 1124 static void ahci_start_port(struct ata_port *ap)
1126 { 1125 {
1127 struct ahci_port_priv *pp = ap->private_data; 1126 struct ahci_port_priv *pp = ap->private_data;
1128 struct ata_link *link; 1127 struct ata_link *link;
1129 struct ahci_em_priv *emp; 1128 struct ahci_em_priv *emp;
1130 ssize_t rc; 1129 ssize_t rc;
1131 int i; 1130 int i;
1132 1131
1133 /* enable FIS reception */ 1132 /* enable FIS reception */
1134 ahci_start_fis_rx(ap); 1133 ahci_start_fis_rx(ap);
1135 1134
1136 /* enable DMA */ 1135 /* enable DMA */
1137 ahci_start_engine(ap); 1136 ahci_start_engine(ap);
1138 1137
1139 /* turn on LEDs */ 1138 /* turn on LEDs */
1140 if (ap->flags & ATA_FLAG_EM) { 1139 if (ap->flags & ATA_FLAG_EM) {
1141 ata_for_each_link(link, ap, EDGE) { 1140 ata_for_each_link(link, ap, EDGE) {
1142 emp = &pp->em_priv[link->pmp]; 1141 emp = &pp->em_priv[link->pmp];
1143 1142
1144 /* EM Transmit bit maybe busy during init */ 1143 /* EM Transmit bit maybe busy during init */
1145 for (i = 0; i < EM_MAX_RETRY; i++) { 1144 for (i = 0; i < EM_MAX_RETRY; i++) {
1146 rc = ahci_transmit_led_message(ap, 1145 rc = ahci_transmit_led_message(ap,
1147 emp->led_state, 1146 emp->led_state,
1148 4); 1147 4);
1149 if (rc == -EBUSY) 1148 if (rc == -EBUSY)
1150 msleep(1); 1149 msleep(1);
1151 else 1150 else
1152 break; 1151 break;
1153 } 1152 }
1154 } 1153 }
1155 } 1154 }
1156 1155
1157 if (ap->flags & ATA_FLAG_SW_ACTIVITY) 1156 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
1158 ata_for_each_link(link, ap, EDGE) 1157 ata_for_each_link(link, ap, EDGE)
1159 ahci_init_sw_activity(link); 1158 ahci_init_sw_activity(link);
1160 1159
1161 } 1160 }
1162 1161
1163 static int ahci_deinit_port(struct ata_port *ap, const char **emsg) 1162 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
1164 { 1163 {
1165 int rc; 1164 int rc;
1166 1165
1167 /* disable DMA */ 1166 /* disable DMA */
1168 rc = ahci_stop_engine(ap); 1167 rc = ahci_stop_engine(ap);
1169 if (rc) { 1168 if (rc) {
1170 *emsg = "failed to stop engine"; 1169 *emsg = "failed to stop engine";
1171 return rc; 1170 return rc;
1172 } 1171 }
1173 1172
1174 /* disable FIS reception */ 1173 /* disable FIS reception */
1175 rc = ahci_stop_fis_rx(ap); 1174 rc = ahci_stop_fis_rx(ap);
1176 if (rc) { 1175 if (rc) {
1177 *emsg = "failed stop FIS RX"; 1176 *emsg = "failed stop FIS RX";
1178 return rc; 1177 return rc;
1179 } 1178 }
1180 1179
1181 return 0; 1180 return 0;
1182 } 1181 }
1183 1182
1184 static int ahci_reset_controller(struct ata_host *host) 1183 static int ahci_reset_controller(struct ata_host *host)
1185 { 1184 {
1186 struct pci_dev *pdev = to_pci_dev(host->dev); 1185 struct pci_dev *pdev = to_pci_dev(host->dev);
1187 struct ahci_host_priv *hpriv = host->private_data; 1186 struct ahci_host_priv *hpriv = host->private_data;
1188 void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; 1187 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1189 u32 tmp; 1188 u32 tmp;
1190 1189
1191 /* we must be in AHCI mode, before using anything 1190 /* we must be in AHCI mode, before using anything
1192 * AHCI-specific, such as HOST_RESET. 1191 * AHCI-specific, such as HOST_RESET.
1193 */ 1192 */
1194 ahci_enable_ahci(mmio); 1193 ahci_enable_ahci(mmio);
1195 1194
1196 /* global controller reset */ 1195 /* global controller reset */
1197 if (!ahci_skip_host_reset) { 1196 if (!ahci_skip_host_reset) {
1198 tmp = readl(mmio + HOST_CTL); 1197 tmp = readl(mmio + HOST_CTL);
1199 if ((tmp & HOST_RESET) == 0) { 1198 if ((tmp & HOST_RESET) == 0) {
1200 writel(tmp | HOST_RESET, mmio + HOST_CTL); 1199 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1201 readl(mmio + HOST_CTL); /* flush */ 1200 readl(mmio + HOST_CTL); /* flush */
1202 } 1201 }
1203 1202
1204 /* 1203 /*
1205 * to perform host reset, OS should set HOST_RESET 1204 * to perform host reset, OS should set HOST_RESET
1206 * and poll until this bit is read to be "0". 1205 * and poll until this bit is read to be "0".
1207 * reset must complete within 1 second, or 1206 * reset must complete within 1 second, or
1208 * the hardware should be considered fried. 1207 * the hardware should be considered fried.
1209 */ 1208 */
1210 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET, 1209 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
1211 HOST_RESET, 10, 1000); 1210 HOST_RESET, 10, 1000);
1212 1211
1213 if (tmp & HOST_RESET) { 1212 if (tmp & HOST_RESET) {
1214 dev_printk(KERN_ERR, host->dev, 1213 dev_printk(KERN_ERR, host->dev,
1215 "controller reset failed (0x%x)\n", tmp); 1214 "controller reset failed (0x%x)\n", tmp);
1216 return -EIO; 1215 return -EIO;
1217 } 1216 }
1218 1217
1219 /* turn on AHCI mode */ 1218 /* turn on AHCI mode */
1220 ahci_enable_ahci(mmio); 1219 ahci_enable_ahci(mmio);
1221 1220
1222 /* Some registers might be cleared on reset. Restore 1221 /* Some registers might be cleared on reset. Restore
1223 * initial values. 1222 * initial values.
1224 */ 1223 */
1225 ahci_restore_initial_config(host); 1224 ahci_restore_initial_config(host);
1226 } else 1225 } else
1227 dev_printk(KERN_INFO, host->dev, 1226 dev_printk(KERN_INFO, host->dev,
1228 "skipping global host reset\n"); 1227 "skipping global host reset\n");
1229 1228
1230 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 1229 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1231 u16 tmp16; 1230 u16 tmp16;
1232 1231
1233 /* configure PCS */ 1232 /* configure PCS */
1234 pci_read_config_word(pdev, 0x92, &tmp16); 1233 pci_read_config_word(pdev, 0x92, &tmp16);
1235 if ((tmp16 & hpriv->port_map) != hpriv->port_map) { 1234 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1236 tmp16 |= hpriv->port_map; 1235 tmp16 |= hpriv->port_map;
1237 pci_write_config_word(pdev, 0x92, tmp16); 1236 pci_write_config_word(pdev, 0x92, tmp16);
1238 } 1237 }
1239 } 1238 }
1240 1239
1241 return 0; 1240 return 0;
1242 } 1241 }
1243 1242
1244 static void ahci_sw_activity(struct ata_link *link) 1243 static void ahci_sw_activity(struct ata_link *link)
1245 { 1244 {
1246 struct ata_port *ap = link->ap; 1245 struct ata_port *ap = link->ap;
1247 struct ahci_port_priv *pp = ap->private_data; 1246 struct ahci_port_priv *pp = ap->private_data;
1248 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1247 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1249 1248
1250 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY)) 1249 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1251 return; 1250 return;
1252 1251
1253 emp->activity++; 1252 emp->activity++;
1254 if (!timer_pending(&emp->timer)) 1253 if (!timer_pending(&emp->timer))
1255 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10)); 1254 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1256 } 1255 }
1257 1256
1258 static void ahci_sw_activity_blink(unsigned long arg) 1257 static void ahci_sw_activity_blink(unsigned long arg)
1259 { 1258 {
1260 struct ata_link *link = (struct ata_link *)arg; 1259 struct ata_link *link = (struct ata_link *)arg;
1261 struct ata_port *ap = link->ap; 1260 struct ata_port *ap = link->ap;
1262 struct ahci_port_priv *pp = ap->private_data; 1261 struct ahci_port_priv *pp = ap->private_data;
1263 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1262 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1264 unsigned long led_message = emp->led_state; 1263 unsigned long led_message = emp->led_state;
1265 u32 activity_led_state; 1264 u32 activity_led_state;
1266 unsigned long flags; 1265 unsigned long flags;
1267 1266
1268 led_message &= EM_MSG_LED_VALUE; 1267 led_message &= EM_MSG_LED_VALUE;
1269 led_message |= ap->port_no | (link->pmp << 8); 1268 led_message |= ap->port_no | (link->pmp << 8);
1270 1269
1271 /* check to see if we've had activity. If so, 1270 /* check to see if we've had activity. If so,
1272 * toggle state of LED and reset timer. If not, 1271 * toggle state of LED and reset timer. If not,
1273 * turn LED to desired idle state. 1272 * turn LED to desired idle state.
1274 */ 1273 */
1275 spin_lock_irqsave(ap->lock, flags); 1274 spin_lock_irqsave(ap->lock, flags);
1276 if (emp->saved_activity != emp->activity) { 1275 if (emp->saved_activity != emp->activity) {
1277 emp->saved_activity = emp->activity; 1276 emp->saved_activity = emp->activity;
1278 /* get the current LED state */ 1277 /* get the current LED state */
1279 activity_led_state = led_message & EM_MSG_LED_VALUE_ON; 1278 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
1280 1279
1281 if (activity_led_state) 1280 if (activity_led_state)
1282 activity_led_state = 0; 1281 activity_led_state = 0;
1283 else 1282 else
1284 activity_led_state = 1; 1283 activity_led_state = 1;
1285 1284
1286 /* clear old state */ 1285 /* clear old state */
1287 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 1286 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1288 1287
1289 /* toggle state */ 1288 /* toggle state */
1290 led_message |= (activity_led_state << 16); 1289 led_message |= (activity_led_state << 16);
1291 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100)); 1290 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1292 } else { 1291 } else {
1293 /* switch to idle */ 1292 /* switch to idle */
1294 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 1293 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1295 if (emp->blink_policy == BLINK_OFF) 1294 if (emp->blink_policy == BLINK_OFF)
1296 led_message |= (1 << 16); 1295 led_message |= (1 << 16);
1297 } 1296 }
1298 spin_unlock_irqrestore(ap->lock, flags); 1297 spin_unlock_irqrestore(ap->lock, flags);
1299 ahci_transmit_led_message(ap, led_message, 4); 1298 ahci_transmit_led_message(ap, led_message, 4);
1300 } 1299 }
1301 1300
1302 static void ahci_init_sw_activity(struct ata_link *link) 1301 static void ahci_init_sw_activity(struct ata_link *link)
1303 { 1302 {
1304 struct ata_port *ap = link->ap; 1303 struct ata_port *ap = link->ap;
1305 struct ahci_port_priv *pp = ap->private_data; 1304 struct ahci_port_priv *pp = ap->private_data;
1306 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1305 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1307 1306
1308 /* init activity stats, setup timer */ 1307 /* init activity stats, setup timer */
1309 emp->saved_activity = emp->activity = 0; 1308 emp->saved_activity = emp->activity = 0;
1310 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link); 1309 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1311 1310
1312 /* check our blink policy and set flag for link if it's enabled */ 1311 /* check our blink policy and set flag for link if it's enabled */
1313 if (emp->blink_policy) 1312 if (emp->blink_policy)
1314 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1313 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1315 } 1314 }
1316 1315
1317 static int ahci_reset_em(struct ata_host *host) 1316 static int ahci_reset_em(struct ata_host *host)
1318 { 1317 {
1319 void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; 1318 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1320 u32 em_ctl; 1319 u32 em_ctl;
1321 1320
1322 em_ctl = readl(mmio + HOST_EM_CTL); 1321 em_ctl = readl(mmio + HOST_EM_CTL);
1323 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST)) 1322 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1324 return -EINVAL; 1323 return -EINVAL;
1325 1324
1326 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL); 1325 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1327 return 0; 1326 return 0;
1328 } 1327 }
1329 1328
1330 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 1329 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1331 ssize_t size) 1330 ssize_t size)
1332 { 1331 {
1333 struct ahci_host_priv *hpriv = ap->host->private_data; 1332 struct ahci_host_priv *hpriv = ap->host->private_data;
1334 struct ahci_port_priv *pp = ap->private_data; 1333 struct ahci_port_priv *pp = ap->private_data;
1335 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; 1334 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1336 u32 em_ctl; 1335 u32 em_ctl;
1337 u32 message[] = {0, 0}; 1336 u32 message[] = {0, 0};
1338 unsigned long flags; 1337 unsigned long flags;
1339 int pmp; 1338 int pmp;
1340 struct ahci_em_priv *emp; 1339 struct ahci_em_priv *emp;
1341 1340
1342 /* get the slot number from the message */ 1341 /* get the slot number from the message */
1343 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1342 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1344 if (pmp < EM_MAX_SLOTS) 1343 if (pmp < EM_MAX_SLOTS)
1345 emp = &pp->em_priv[pmp]; 1344 emp = &pp->em_priv[pmp];
1346 else 1345 else
1347 return -EINVAL; 1346 return -EINVAL;
1348 1347
1349 spin_lock_irqsave(ap->lock, flags); 1348 spin_lock_irqsave(ap->lock, flags);
1350 1349
1351 /* 1350 /*
1352 * if we are still busy transmitting a previous message, 1351 * if we are still busy transmitting a previous message,
1353 * do not allow 1352 * do not allow
1354 */ 1353 */
1355 em_ctl = readl(mmio + HOST_EM_CTL); 1354 em_ctl = readl(mmio + HOST_EM_CTL);
1356 if (em_ctl & EM_CTL_TM) { 1355 if (em_ctl & EM_CTL_TM) {
1357 spin_unlock_irqrestore(ap->lock, flags); 1356 spin_unlock_irqrestore(ap->lock, flags);
1358 return -EBUSY; 1357 return -EBUSY;
1359 } 1358 }
1360 1359
1361 /* 1360 /*
1362 * create message header - this is all zero except for 1361 * create message header - this is all zero except for
1363 * the message size, which is 4 bytes. 1362 * the message size, which is 4 bytes.
1364 */ 1363 */
1365 message[0] |= (4 << 8); 1364 message[0] |= (4 << 8);
1366 1365
1367 /* ignore 0:4 of byte zero, fill in port info yourself */ 1366 /* ignore 0:4 of byte zero, fill in port info yourself */
1368 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); 1367 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1369 1368
1370 /* write message to EM_LOC */ 1369 /* write message to EM_LOC */
1371 writel(message[0], mmio + hpriv->em_loc); 1370 writel(message[0], mmio + hpriv->em_loc);
1372 writel(message[1], mmio + hpriv->em_loc+4); 1371 writel(message[1], mmio + hpriv->em_loc+4);
1373 1372
1374 /* save off new led state for port/slot */ 1373 /* save off new led state for port/slot */
1375 emp->led_state = state; 1374 emp->led_state = state;
1376 1375
1377 /* 1376 /*
1378 * tell hardware to transmit the message 1377 * tell hardware to transmit the message
1379 */ 1378 */
1380 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 1379 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1381 1380
1382 spin_unlock_irqrestore(ap->lock, flags); 1381 spin_unlock_irqrestore(ap->lock, flags);
1383 return size; 1382 return size;
1384 } 1383 }
1385 1384
1386 static ssize_t ahci_led_show(struct ata_port *ap, char *buf) 1385 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1387 { 1386 {
1388 struct ahci_port_priv *pp = ap->private_data; 1387 struct ahci_port_priv *pp = ap->private_data;
1389 struct ata_link *link; 1388 struct ata_link *link;
1390 struct ahci_em_priv *emp; 1389 struct ahci_em_priv *emp;
1391 int rc = 0; 1390 int rc = 0;
1392 1391
1393 ata_for_each_link(link, ap, EDGE) { 1392 ata_for_each_link(link, ap, EDGE) {
1394 emp = &pp->em_priv[link->pmp]; 1393 emp = &pp->em_priv[link->pmp];
1395 rc += sprintf(buf, "%lx\n", emp->led_state); 1394 rc += sprintf(buf, "%lx\n", emp->led_state);
1396 } 1395 }
1397 return rc; 1396 return rc;
1398 } 1397 }
1399 1398
1400 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 1399 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1401 size_t size) 1400 size_t size)
1402 { 1401 {
1403 int state; 1402 int state;
1404 int pmp; 1403 int pmp;
1405 struct ahci_port_priv *pp = ap->private_data; 1404 struct ahci_port_priv *pp = ap->private_data;
1406 struct ahci_em_priv *emp; 1405 struct ahci_em_priv *emp;
1407 1406
1408 state = simple_strtoul(buf, NULL, 0); 1407 state = simple_strtoul(buf, NULL, 0);
1409 1408
1410 /* get the slot number from the message */ 1409 /* get the slot number from the message */
1411 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1410 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1412 if (pmp < EM_MAX_SLOTS) 1411 if (pmp < EM_MAX_SLOTS)
1413 emp = &pp->em_priv[pmp]; 1412 emp = &pp->em_priv[pmp];
1414 else 1413 else
1415 return -EINVAL; 1414 return -EINVAL;
1416 1415
1417 /* mask off the activity bits if we are in sw_activity 1416 /* mask off the activity bits if we are in sw_activity
1418 * mode, user should turn off sw_activity before setting 1417 * mode, user should turn off sw_activity before setting
1419 * activity led through em_message 1418 * activity led through em_message
1420 */ 1419 */
1421 if (emp->blink_policy) 1420 if (emp->blink_policy)
1422 state &= ~EM_MSG_LED_VALUE_ACTIVITY; 1421 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1423 1422
1424 return ahci_transmit_led_message(ap, state, size); 1423 return ahci_transmit_led_message(ap, state, size);
1425 } 1424 }
1426 1425
1427 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) 1426 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1428 { 1427 {
1429 struct ata_link *link = dev->link; 1428 struct ata_link *link = dev->link;
1430 struct ata_port *ap = link->ap; 1429 struct ata_port *ap = link->ap;
1431 struct ahci_port_priv *pp = ap->private_data; 1430 struct ahci_port_priv *pp = ap->private_data;
1432 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1431 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1433 u32 port_led_state = emp->led_state; 1432 u32 port_led_state = emp->led_state;
1434 1433
1435 /* save the desired Activity LED behavior */ 1434 /* save the desired Activity LED behavior */
1436 if (val == OFF) { 1435 if (val == OFF) {
1437 /* clear LFLAG */ 1436 /* clear LFLAG */
1438 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY); 1437 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1439 1438
1440 /* set the LED to OFF */ 1439 /* set the LED to OFF */
1441 port_led_state &= EM_MSG_LED_VALUE_OFF; 1440 port_led_state &= EM_MSG_LED_VALUE_OFF;
1442 port_led_state |= (ap->port_no | (link->pmp << 8)); 1441 port_led_state |= (ap->port_no | (link->pmp << 8));
1443 ahci_transmit_led_message(ap, port_led_state, 4); 1442 ahci_transmit_led_message(ap, port_led_state, 4);
1444 } else { 1443 } else {
1445 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1444 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1446 if (val == BLINK_OFF) { 1445 if (val == BLINK_OFF) {
1447 /* set LED to ON for idle */ 1446 /* set LED to ON for idle */
1448 port_led_state &= EM_MSG_LED_VALUE_OFF; 1447 port_led_state &= EM_MSG_LED_VALUE_OFF;
1449 port_led_state |= (ap->port_no | (link->pmp << 8)); 1448 port_led_state |= (ap->port_no | (link->pmp << 8));
1450 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */ 1449 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1451 ahci_transmit_led_message(ap, port_led_state, 4); 1450 ahci_transmit_led_message(ap, port_led_state, 4);
1452 } 1451 }
1453 } 1452 }
1454 emp->blink_policy = val; 1453 emp->blink_policy = val;
1455 return 0; 1454 return 0;
1456 } 1455 }
1457 1456
1458 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) 1457 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1459 { 1458 {
1460 struct ata_link *link = dev->link; 1459 struct ata_link *link = dev->link;
1461 struct ata_port *ap = link->ap; 1460 struct ata_port *ap = link->ap;
1462 struct ahci_port_priv *pp = ap->private_data; 1461 struct ahci_port_priv *pp = ap->private_data;
1463 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1462 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1464 1463
1465 /* display the saved value of activity behavior for this 1464 /* display the saved value of activity behavior for this
1466 * disk. 1465 * disk.
1467 */ 1466 */
1468 return sprintf(buf, "%d\n", emp->blink_policy); 1467 return sprintf(buf, "%d\n", emp->blink_policy);
1469 } 1468 }
1470 1469
1471 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap, 1470 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1472 int port_no, void __iomem *mmio, 1471 int port_no, void __iomem *mmio,
1473 void __iomem *port_mmio) 1472 void __iomem *port_mmio)
1474 { 1473 {
1475 const char *emsg = NULL; 1474 const char *emsg = NULL;
1476 int rc; 1475 int rc;
1477 u32 tmp; 1476 u32 tmp;
1478 1477
1479 /* make sure port is not active */ 1478 /* make sure port is not active */
1480 rc = ahci_deinit_port(ap, &emsg); 1479 rc = ahci_deinit_port(ap, &emsg);
1481 if (rc) 1480 if (rc)
1482 dev_printk(KERN_WARNING, &pdev->dev, 1481 dev_printk(KERN_WARNING, &pdev->dev,
1483 "%s (%d)\n", emsg, rc); 1482 "%s (%d)\n", emsg, rc);
1484 1483
1485 /* clear SError */ 1484 /* clear SError */
1486 tmp = readl(port_mmio + PORT_SCR_ERR); 1485 tmp = readl(port_mmio + PORT_SCR_ERR);
1487 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); 1486 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1488 writel(tmp, port_mmio + PORT_SCR_ERR); 1487 writel(tmp, port_mmio + PORT_SCR_ERR);
1489 1488
1490 /* clear port IRQ */ 1489 /* clear port IRQ */
1491 tmp = readl(port_mmio + PORT_IRQ_STAT); 1490 tmp = readl(port_mmio + PORT_IRQ_STAT);
1492 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 1491 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1493 if (tmp) 1492 if (tmp)
1494 writel(tmp, port_mmio + PORT_IRQ_STAT); 1493 writel(tmp, port_mmio + PORT_IRQ_STAT);
1495 1494
1496 writel(1 << port_no, mmio + HOST_IRQ_STAT); 1495 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1497 } 1496 }
1498 1497
1499 static void ahci_init_controller(struct ata_host *host) 1498 static void ahci_init_controller(struct ata_host *host)
1500 { 1499 {
1501 struct ahci_host_priv *hpriv = host->private_data; 1500 struct ahci_host_priv *hpriv = host->private_data;
1502 struct pci_dev *pdev = to_pci_dev(host->dev); 1501 struct pci_dev *pdev = to_pci_dev(host->dev);
1503 void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; 1502 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1504 int i; 1503 int i;
1505 void __iomem *port_mmio; 1504 void __iomem *port_mmio;
1506 u32 tmp; 1505 u32 tmp;
1507 int mv; 1506 int mv;
1508 1507
1509 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 1508 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1510 if (pdev->device == 0x6121) 1509 if (pdev->device == 0x6121)
1511 mv = 2; 1510 mv = 2;
1512 else 1511 else
1513 mv = 4; 1512 mv = 4;
1514 port_mmio = __ahci_port_base(host, mv); 1513 port_mmio = __ahci_port_base(host, mv);
1515 1514
1516 writel(0, port_mmio + PORT_IRQ_MASK); 1515 writel(0, port_mmio + PORT_IRQ_MASK);
1517 1516
1518 /* clear port IRQ */ 1517 /* clear port IRQ */
1519 tmp = readl(port_mmio + PORT_IRQ_STAT); 1518 tmp = readl(port_mmio + PORT_IRQ_STAT);
1520 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 1519 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1521 if (tmp) 1520 if (tmp)
1522 writel(tmp, port_mmio + PORT_IRQ_STAT); 1521 writel(tmp, port_mmio + PORT_IRQ_STAT);
1523 } 1522 }
1524 1523
1525 for (i = 0; i < host->n_ports; i++) { 1524 for (i = 0; i < host->n_ports; i++) {
1526 struct ata_port *ap = host->ports[i]; 1525 struct ata_port *ap = host->ports[i];
1527 1526
1528 port_mmio = ahci_port_base(ap); 1527 port_mmio = ahci_port_base(ap);
1529 if (ata_port_is_dummy(ap)) 1528 if (ata_port_is_dummy(ap))
1530 continue; 1529 continue;
1531 1530
1532 ahci_port_init(pdev, ap, i, mmio, port_mmio); 1531 ahci_port_init(pdev, ap, i, mmio, port_mmio);
1533 } 1532 }
1534 1533
1535 tmp = readl(mmio + HOST_CTL); 1534 tmp = readl(mmio + HOST_CTL);
1536 VPRINTK("HOST_CTL 0x%x\n", tmp); 1535 VPRINTK("HOST_CTL 0x%x\n", tmp);
1537 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 1536 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1538 tmp = readl(mmio + HOST_CTL); 1537 tmp = readl(mmio + HOST_CTL);
1539 VPRINTK("HOST_CTL 0x%x\n", tmp); 1538 VPRINTK("HOST_CTL 0x%x\n", tmp);
1540 } 1539 }
1541 1540
1542 static void ahci_dev_config(struct ata_device *dev) 1541 static void ahci_dev_config(struct ata_device *dev)
1543 { 1542 {
1544 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; 1543 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1545 1544
1546 if (hpriv->flags & AHCI_HFLAG_SECT255) { 1545 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1547 dev->max_sectors = 255; 1546 dev->max_sectors = 255;
1548 ata_dev_printk(dev, KERN_INFO, 1547 ata_dev_printk(dev, KERN_INFO,
1549 "SB600 AHCI: limiting to 255 sectors per cmd\n"); 1548 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1550 } 1549 }
1551 } 1550 }
1552 1551
1553 static unsigned int ahci_dev_classify(struct ata_port *ap) 1552 static unsigned int ahci_dev_classify(struct ata_port *ap)
1554 { 1553 {
1555 void __iomem *port_mmio = ahci_port_base(ap); 1554 void __iomem *port_mmio = ahci_port_base(ap);
1556 struct ata_taskfile tf; 1555 struct ata_taskfile tf;
1557 u32 tmp; 1556 u32 tmp;
1558 1557
1559 tmp = readl(port_mmio + PORT_SIG); 1558 tmp = readl(port_mmio + PORT_SIG);
1560 tf.lbah = (tmp >> 24) & 0xff; 1559 tf.lbah = (tmp >> 24) & 0xff;
1561 tf.lbam = (tmp >> 16) & 0xff; 1560 tf.lbam = (tmp >> 16) & 0xff;
1562 tf.lbal = (tmp >> 8) & 0xff; 1561 tf.lbal = (tmp >> 8) & 0xff;
1563 tf.nsect = (tmp) & 0xff; 1562 tf.nsect = (tmp) & 0xff;
1564 1563
1565 return ata_dev_classify(&tf); 1564 return ata_dev_classify(&tf);
1566 } 1565 }
1567 1566
1568 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 1567 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1569 u32 opts) 1568 u32 opts)
1570 { 1569 {
1571 dma_addr_t cmd_tbl_dma; 1570 dma_addr_t cmd_tbl_dma;
1572 1571
1573 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; 1572 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1574 1573
1575 pp->cmd_slot[tag].opts = cpu_to_le32(opts); 1574 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1576 pp->cmd_slot[tag].status = 0; 1575 pp->cmd_slot[tag].status = 0;
1577 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); 1576 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1578 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); 1577 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1579 } 1578 }
1580 1579
1581 static int ahci_kick_engine(struct ata_port *ap, int force_restart) 1580 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
1582 { 1581 {
1583 void __iomem *port_mmio = ahci_port_base(ap); 1582 void __iomem *port_mmio = ahci_port_base(ap);
1584 struct ahci_host_priv *hpriv = ap->host->private_data; 1583 struct ahci_host_priv *hpriv = ap->host->private_data;
1585 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1584 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1586 u32 tmp; 1585 u32 tmp;
1587 int busy, rc; 1586 int busy, rc;
1588 1587
1589 /* do we need to kick the port? */ 1588 /* do we need to kick the port? */
1590 busy = status & (ATA_BUSY | ATA_DRQ); 1589 busy = status & (ATA_BUSY | ATA_DRQ);
1591 if (!busy && !force_restart) 1590 if (!busy && !force_restart)
1592 return 0; 1591 return 0;
1593 1592
1594 /* stop engine */ 1593 /* stop engine */
1595 rc = ahci_stop_engine(ap); 1594 rc = ahci_stop_engine(ap);
1596 if (rc) 1595 if (rc)
1597 goto out_restart; 1596 goto out_restart;
1598 1597
1599 /* need to do CLO? */ 1598 /* need to do CLO? */
1600 if (!busy) { 1599 if (!busy) {
1601 rc = 0; 1600 rc = 0;
1602 goto out_restart; 1601 goto out_restart;
1603 } 1602 }
1604 1603
1605 if (!(hpriv->cap & HOST_CAP_CLO)) { 1604 if (!(hpriv->cap & HOST_CAP_CLO)) {
1606 rc = -EOPNOTSUPP; 1605 rc = -EOPNOTSUPP;
1607 goto out_restart; 1606 goto out_restart;
1608 } 1607 }
1609 1608
1610 /* perform CLO */ 1609 /* perform CLO */
1611 tmp = readl(port_mmio + PORT_CMD); 1610 tmp = readl(port_mmio + PORT_CMD);
1612 tmp |= PORT_CMD_CLO; 1611 tmp |= PORT_CMD_CLO;
1613 writel(tmp, port_mmio + PORT_CMD); 1612 writel(tmp, port_mmio + PORT_CMD);
1614 1613
1615 rc = 0; 1614 rc = 0;
1616 tmp = ata_wait_register(port_mmio + PORT_CMD, 1615 tmp = ata_wait_register(port_mmio + PORT_CMD,
1617 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); 1616 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1618 if (tmp & PORT_CMD_CLO) 1617 if (tmp & PORT_CMD_CLO)
1619 rc = -EIO; 1618 rc = -EIO;
1620 1619
1621 /* restart engine */ 1620 /* restart engine */
1622 out_restart: 1621 out_restart:
1623 ahci_start_engine(ap); 1622 ahci_start_engine(ap);
1624 return rc; 1623 return rc;
1625 } 1624 }
1626 1625
1627 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, 1626 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1628 struct ata_taskfile *tf, int is_cmd, u16 flags, 1627 struct ata_taskfile *tf, int is_cmd, u16 flags,
1629 unsigned long timeout_msec) 1628 unsigned long timeout_msec)
1630 { 1629 {
1631 const u32 cmd_fis_len = 5; /* five dwords */ 1630 const u32 cmd_fis_len = 5; /* five dwords */
1632 struct ahci_port_priv *pp = ap->private_data; 1631 struct ahci_port_priv *pp = ap->private_data;
1633 void __iomem *port_mmio = ahci_port_base(ap); 1632 void __iomem *port_mmio = ahci_port_base(ap);
1634 u8 *fis = pp->cmd_tbl; 1633 u8 *fis = pp->cmd_tbl;
1635 u32 tmp; 1634 u32 tmp;
1636 1635
1637 /* prep the command */ 1636 /* prep the command */
1638 ata_tf_to_fis(tf, pmp, is_cmd, fis); 1637 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1639 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); 1638 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1640 1639
1641 /* issue & wait */ 1640 /* issue & wait */
1642 writel(1, port_mmio + PORT_CMD_ISSUE); 1641 writel(1, port_mmio + PORT_CMD_ISSUE);
1643 1642
1644 if (timeout_msec) { 1643 if (timeout_msec) {
1645 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1644 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1646 1, timeout_msec); 1645 1, timeout_msec);
1647 if (tmp & 0x1) { 1646 if (tmp & 0x1) {
1648 ahci_kick_engine(ap, 1); 1647 ahci_kick_engine(ap, 1);
1649 return -EBUSY; 1648 return -EBUSY;
1650 } 1649 }
1651 } else 1650 } else
1652 readl(port_mmio + PORT_CMD_ISSUE); /* flush */ 1651 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1653 1652
1654 return 0; 1653 return 0;
1655 } 1654 }
1656 1655
1657 static int ahci_do_softreset(struct ata_link *link, unsigned int *class, 1656 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1658 int pmp, unsigned long deadline, 1657 int pmp, unsigned long deadline,
1659 int (*check_ready)(struct ata_link *link)) 1658 int (*check_ready)(struct ata_link *link))
1660 { 1659 {
1661 struct ata_port *ap = link->ap; 1660 struct ata_port *ap = link->ap;
1662 const char *reason = NULL; 1661 const char *reason = NULL;
1663 unsigned long now, msecs; 1662 unsigned long now, msecs;
1664 struct ata_taskfile tf; 1663 struct ata_taskfile tf;
1665 int rc; 1664 int rc;
1666 1665
1667 DPRINTK("ENTER\n"); 1666 DPRINTK("ENTER\n");
1668 1667
1669 /* prepare for SRST (AHCI-1.1 10.4.1) */ 1668 /* prepare for SRST (AHCI-1.1 10.4.1) */
1670 rc = ahci_kick_engine(ap, 1); 1669 rc = ahci_kick_engine(ap, 1);
1671 if (rc && rc != -EOPNOTSUPP) 1670 if (rc && rc != -EOPNOTSUPP)
1672 ata_link_printk(link, KERN_WARNING, 1671 ata_link_printk(link, KERN_WARNING,
1673 "failed to reset engine (errno=%d)\n", rc); 1672 "failed to reset engine (errno=%d)\n", rc);
1674 1673
1675 ata_tf_init(link->device, &tf); 1674 ata_tf_init(link->device, &tf);
1676 1675
1677 /* issue the first D2H Register FIS */ 1676 /* issue the first D2H Register FIS */
1678 msecs = 0; 1677 msecs = 0;
1679 now = jiffies; 1678 now = jiffies;
1680 if (time_after(now, deadline)) 1679 if (time_after(now, deadline))
1681 msecs = jiffies_to_msecs(deadline - now); 1680 msecs = jiffies_to_msecs(deadline - now);
1682 1681
1683 tf.ctl |= ATA_SRST; 1682 tf.ctl |= ATA_SRST;
1684 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, 1683 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1685 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { 1684 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1686 rc = -EIO; 1685 rc = -EIO;
1687 reason = "1st FIS failed"; 1686 reason = "1st FIS failed";
1688 goto fail; 1687 goto fail;
1689 } 1688 }
1690 1689
1691 /* spec says at least 5us, but be generous and sleep for 1ms */ 1690 /* spec says at least 5us, but be generous and sleep for 1ms */
1692 msleep(1); 1691 msleep(1);
1693 1692
1694 /* issue the second D2H Register FIS */ 1693 /* issue the second D2H Register FIS */
1695 tf.ctl &= ~ATA_SRST; 1694 tf.ctl &= ~ATA_SRST;
1696 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); 1695 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1697 1696
1698 /* wait for link to become ready */ 1697 /* wait for link to become ready */
1699 rc = ata_wait_after_reset(link, deadline, check_ready); 1698 rc = ata_wait_after_reset(link, deadline, check_ready);
1700 /* link occupied, -ENODEV too is an error */ 1699 /* link occupied, -ENODEV too is an error */
1701 if (rc) { 1700 if (rc) {
1702 reason = "device not ready"; 1701 reason = "device not ready";
1703 goto fail; 1702 goto fail;
1704 } 1703 }
1705 *class = ahci_dev_classify(ap); 1704 *class = ahci_dev_classify(ap);
1706 1705
1707 DPRINTK("EXIT, class=%u\n", *class); 1706 DPRINTK("EXIT, class=%u\n", *class);
1708 return 0; 1707 return 0;
1709 1708
1710 fail: 1709 fail:
1711 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason); 1710 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1712 return rc; 1711 return rc;
1713 } 1712 }
1714 1713
1715 static int ahci_check_ready(struct ata_link *link) 1714 static int ahci_check_ready(struct ata_link *link)
1716 { 1715 {
1717 void __iomem *port_mmio = ahci_port_base(link->ap); 1716 void __iomem *port_mmio = ahci_port_base(link->ap);
1718 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1717 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1719 1718
1720 return ata_check_ready(status); 1719 return ata_check_ready(status);
1721 } 1720 }
1722 1721
1723 static int ahci_softreset(struct ata_link *link, unsigned int *class, 1722 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1724 unsigned long deadline) 1723 unsigned long deadline)
1725 { 1724 {
1726 int pmp = sata_srst_pmp(link); 1725 int pmp = sata_srst_pmp(link);
1727 1726
1728 DPRINTK("ENTER\n"); 1727 DPRINTK("ENTER\n");
1729 1728
1730 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); 1729 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1731 } 1730 }
1732 1731
1733 static int ahci_sb600_check_ready(struct ata_link *link) 1732 static int ahci_sb600_check_ready(struct ata_link *link)
1734 { 1733 {
1735 void __iomem *port_mmio = ahci_port_base(link->ap); 1734 void __iomem *port_mmio = ahci_port_base(link->ap);
1736 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1735 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1737 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT); 1736 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1738 1737
1739 /* 1738 /*
1740 * There is no need to check TFDATA if BAD PMP is found due to HW bug, 1739 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1741 * which can save timeout delay. 1740 * which can save timeout delay.
1742 */ 1741 */
1743 if (irq_status & PORT_IRQ_BAD_PMP) 1742 if (irq_status & PORT_IRQ_BAD_PMP)
1744 return -EIO; 1743 return -EIO;
1745 1744
1746 return ata_check_ready(status); 1745 return ata_check_ready(status);
1747 } 1746 }
1748 1747
1749 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class, 1748 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
1750 unsigned long deadline) 1749 unsigned long deadline)
1751 { 1750 {
1752 struct ata_port *ap = link->ap; 1751 struct ata_port *ap = link->ap;
1753 void __iomem *port_mmio = ahci_port_base(ap); 1752 void __iomem *port_mmio = ahci_port_base(ap);
1754 int pmp = sata_srst_pmp(link); 1753 int pmp = sata_srst_pmp(link);
1755 int rc; 1754 int rc;
1756 u32 irq_sts; 1755 u32 irq_sts;
1757 1756
1758 DPRINTK("ENTER\n"); 1757 DPRINTK("ENTER\n");
1759 1758
1760 rc = ahci_do_softreset(link, class, pmp, deadline, 1759 rc = ahci_do_softreset(link, class, pmp, deadline,
1761 ahci_sb600_check_ready); 1760 ahci_sb600_check_ready);
1762 1761
1763 /* 1762 /*
1764 * Soft reset fails on some ATI chips with IPMS set when PMP 1763 * Soft reset fails on some ATI chips with IPMS set when PMP
1765 * is enabled but SATA HDD/ODD is connected to SATA port, 1764 * is enabled but SATA HDD/ODD is connected to SATA port,
1766 * do soft reset again to port 0. 1765 * do soft reset again to port 0.
1767 */ 1766 */
1768 if (rc == -EIO) { 1767 if (rc == -EIO) {
1769 irq_sts = readl(port_mmio + PORT_IRQ_STAT); 1768 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1770 if (irq_sts & PORT_IRQ_BAD_PMP) { 1769 if (irq_sts & PORT_IRQ_BAD_PMP) {
1771 ata_link_printk(link, KERN_WARNING, 1770 ata_link_printk(link, KERN_WARNING,
1772 "failed due to HW bug, retry pmp=0\n"); 1771 "failed due to HW bug, retry pmp=0\n");
1773 rc = ahci_do_softreset(link, class, 0, deadline, 1772 rc = ahci_do_softreset(link, class, 0, deadline,
1774 ahci_check_ready); 1773 ahci_check_ready);
1775 } 1774 }
1776 } 1775 }
1777 1776
1778 return rc; 1777 return rc;
1779 } 1778 }
1780 1779
1781 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 1780 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1782 unsigned long deadline) 1781 unsigned long deadline)
1783 { 1782 {
1784 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 1783 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1785 struct ata_port *ap = link->ap; 1784 struct ata_port *ap = link->ap;
1786 struct ahci_port_priv *pp = ap->private_data; 1785 struct ahci_port_priv *pp = ap->private_data;
1787 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 1786 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1788 struct ata_taskfile tf; 1787 struct ata_taskfile tf;
1789 bool online; 1788 bool online;
1790 int rc; 1789 int rc;
1791 1790
1792 DPRINTK("ENTER\n"); 1791 DPRINTK("ENTER\n");
1793 1792
1794 ahci_stop_engine(ap); 1793 ahci_stop_engine(ap);
1795 1794
1796 /* clear D2H reception area to properly wait for D2H FIS */ 1795 /* clear D2H reception area to properly wait for D2H FIS */
1797 ata_tf_init(link->device, &tf); 1796 ata_tf_init(link->device, &tf);
1798 tf.command = 0x80; 1797 tf.command = 0x80;
1799 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 1798 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1800 1799
1801 rc = sata_link_hardreset(link, timing, deadline, &online, 1800 rc = sata_link_hardreset(link, timing, deadline, &online,
1802 ahci_check_ready); 1801 ahci_check_ready);
1803 1802
1804 ahci_start_engine(ap); 1803 ahci_start_engine(ap);
1805 1804
1806 if (online) 1805 if (online)
1807 *class = ahci_dev_classify(ap); 1806 *class = ahci_dev_classify(ap);
1808 1807
1809 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 1808 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1810 return rc; 1809 return rc;
1811 } 1810 }
1812 1811
1813 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 1812 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1814 unsigned long deadline) 1813 unsigned long deadline)
1815 { 1814 {
1816 struct ata_port *ap = link->ap; 1815 struct ata_port *ap = link->ap;
1817 bool online; 1816 bool online;
1818 int rc; 1817 int rc;
1819 1818
1820 DPRINTK("ENTER\n"); 1819 DPRINTK("ENTER\n");
1821 1820
1822 ahci_stop_engine(ap); 1821 ahci_stop_engine(ap);
1823 1822
1824 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 1823 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1825 deadline, &online, NULL); 1824 deadline, &online, NULL);
1826 1825
1827 ahci_start_engine(ap); 1826 ahci_start_engine(ap);
1828 1827
1829 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 1828 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1830 1829
1831 /* vt8251 doesn't clear BSY on signature FIS reception, 1830 /* vt8251 doesn't clear BSY on signature FIS reception,
1832 * request follow-up softreset. 1831 * request follow-up softreset.
1833 */ 1832 */
1834 return online ? -EAGAIN : rc; 1833 return online ? -EAGAIN : rc;
1835 } 1834 }
1836 1835
1837 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 1836 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1838 unsigned long deadline) 1837 unsigned long deadline)
1839 { 1838 {
1840 struct ata_port *ap = link->ap; 1839 struct ata_port *ap = link->ap;
1841 struct ahci_port_priv *pp = ap->private_data; 1840 struct ahci_port_priv *pp = ap->private_data;
1842 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 1841 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1843 struct ata_taskfile tf; 1842 struct ata_taskfile tf;
1844 bool online; 1843 bool online;
1845 int rc; 1844 int rc;
1846 1845
1847 ahci_stop_engine(ap); 1846 ahci_stop_engine(ap);
1848 1847
1849 /* clear D2H reception area to properly wait for D2H FIS */ 1848 /* clear D2H reception area to properly wait for D2H FIS */
1850 ata_tf_init(link->device, &tf); 1849 ata_tf_init(link->device, &tf);
1851 tf.command = 0x80; 1850 tf.command = 0x80;
1852 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 1851 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1853 1852
1854 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 1853 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1855 deadline, &online, NULL); 1854 deadline, &online, NULL);
1856 1855
1857 ahci_start_engine(ap); 1856 ahci_start_engine(ap);
1858 1857
1859 /* The pseudo configuration device on SIMG4726 attached to 1858 /* The pseudo configuration device on SIMG4726 attached to
1860 * ASUS P5W-DH Deluxe doesn't send signature FIS after 1859 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1861 * hardreset if no device is attached to the first downstream 1860 * hardreset if no device is attached to the first downstream
1862 * port && the pseudo device locks up on SRST w/ PMP==0. To 1861 * port && the pseudo device locks up on SRST w/ PMP==0. To
1863 * work around this, wait for !BSY only briefly. If BSY isn't 1862 * work around this, wait for !BSY only briefly. If BSY isn't
1864 * cleared, perform CLO and proceed to IDENTIFY (achieved by 1863 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1865 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). 1864 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1866 * 1865 *
1867 * Wait for two seconds. Devices attached to downstream port 1866 * Wait for two seconds. Devices attached to downstream port
1868 * which can't process the following IDENTIFY after this will 1867 * which can't process the following IDENTIFY after this will
1869 * have to be reset again. For most cases, this should 1868 * have to be reset again. For most cases, this should
1870 * suffice while making probing snappish enough. 1869 * suffice while making probing snappish enough.
1871 */ 1870 */
1872 if (online) { 1871 if (online) {
1873 rc = ata_wait_after_reset(link, jiffies + 2 * HZ, 1872 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
1874 ahci_check_ready); 1873 ahci_check_ready);
1875 if (rc) 1874 if (rc)
1876 ahci_kick_engine(ap, 0); 1875 ahci_kick_engine(ap, 0);
1877 } 1876 }
1878 return rc; 1877 return rc;
1879 } 1878 }
1880 1879
1881 static void ahci_postreset(struct ata_link *link, unsigned int *class) 1880 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1882 { 1881 {
1883 struct ata_port *ap = link->ap; 1882 struct ata_port *ap = link->ap;
1884 void __iomem *port_mmio = ahci_port_base(ap); 1883 void __iomem *port_mmio = ahci_port_base(ap);
1885 u32 new_tmp, tmp; 1884 u32 new_tmp, tmp;
1886 1885
1887 ata_std_postreset(link, class); 1886 ata_std_postreset(link, class);
1888 1887
1889 /* Make sure port's ATAPI bit is set appropriately */ 1888 /* Make sure port's ATAPI bit is set appropriately */
1890 new_tmp = tmp = readl(port_mmio + PORT_CMD); 1889 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1891 if (*class == ATA_DEV_ATAPI) 1890 if (*class == ATA_DEV_ATAPI)
1892 new_tmp |= PORT_CMD_ATAPI; 1891 new_tmp |= PORT_CMD_ATAPI;
1893 else 1892 else
1894 new_tmp &= ~PORT_CMD_ATAPI; 1893 new_tmp &= ~PORT_CMD_ATAPI;
1895 if (new_tmp != tmp) { 1894 if (new_tmp != tmp) {
1896 writel(new_tmp, port_mmio + PORT_CMD); 1895 writel(new_tmp, port_mmio + PORT_CMD);
1897 readl(port_mmio + PORT_CMD); /* flush */ 1896 readl(port_mmio + PORT_CMD); /* flush */
1898 } 1897 }
1899 } 1898 }
1900 1899
1901 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) 1900 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1902 { 1901 {
1903 struct scatterlist *sg; 1902 struct scatterlist *sg;
1904 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; 1903 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1905 unsigned int si; 1904 unsigned int si;
1906 1905
1907 VPRINTK("ENTER\n"); 1906 VPRINTK("ENTER\n");
1908 1907
1909 /* 1908 /*
1910 * Next, the S/G list. 1909 * Next, the S/G list.
1911 */ 1910 */
1912 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1911 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1913 dma_addr_t addr = sg_dma_address(sg); 1912 dma_addr_t addr = sg_dma_address(sg);
1914 u32 sg_len = sg_dma_len(sg); 1913 u32 sg_len = sg_dma_len(sg);
1915 1914
1916 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); 1915 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1917 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); 1916 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1918 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); 1917 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1919 } 1918 }
1920 1919
1921 return si; 1920 return si;
1922 } 1921 }
1923 1922
1924 static void ahci_qc_prep(struct ata_queued_cmd *qc) 1923 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1925 { 1924 {
1926 struct ata_port *ap = qc->ap; 1925 struct ata_port *ap = qc->ap;
1927 struct ahci_port_priv *pp = ap->private_data; 1926 struct ahci_port_priv *pp = ap->private_data;
1928 int is_atapi = ata_is_atapi(qc->tf.protocol); 1927 int is_atapi = ata_is_atapi(qc->tf.protocol);
1929 void *cmd_tbl; 1928 void *cmd_tbl;
1930 u32 opts; 1929 u32 opts;
1931 const u32 cmd_fis_len = 5; /* five dwords */ 1930 const u32 cmd_fis_len = 5; /* five dwords */
1932 unsigned int n_elem; 1931 unsigned int n_elem;
1933 1932
1934 /* 1933 /*
1935 * Fill in command table information. First, the header, 1934 * Fill in command table information. First, the header,
1936 * a SATA Register - Host to Device command FIS. 1935 * a SATA Register - Host to Device command FIS.
1937 */ 1936 */
1938 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; 1937 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1939 1938
1940 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); 1939 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1941 if (is_atapi) { 1940 if (is_atapi) {
1942 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); 1941 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1943 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); 1942 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1944 } 1943 }
1945 1944
1946 n_elem = 0; 1945 n_elem = 0;
1947 if (qc->flags & ATA_QCFLAG_DMAMAP) 1946 if (qc->flags & ATA_QCFLAG_DMAMAP)
1948 n_elem = ahci_fill_sg(qc, cmd_tbl); 1947 n_elem = ahci_fill_sg(qc, cmd_tbl);
1949 1948
1950 /* 1949 /*
1951 * Fill in command slot information. 1950 * Fill in command slot information.
1952 */ 1951 */
1953 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); 1952 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1954 if (qc->tf.flags & ATA_TFLAG_WRITE) 1953 if (qc->tf.flags & ATA_TFLAG_WRITE)
1955 opts |= AHCI_CMD_WRITE; 1954 opts |= AHCI_CMD_WRITE;
1956 if (is_atapi) 1955 if (is_atapi)
1957 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; 1956 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1958 1957
1959 ahci_fill_cmd_slot(pp, qc->tag, opts); 1958 ahci_fill_cmd_slot(pp, qc->tag, opts);
1960 } 1959 }
1961 1960
1962 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) 1961 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1963 { 1962 {
1964 struct ahci_host_priv *hpriv = ap->host->private_data; 1963 struct ahci_host_priv *hpriv = ap->host->private_data;
1965 struct ahci_port_priv *pp = ap->private_data; 1964 struct ahci_port_priv *pp = ap->private_data;
1966 struct ata_eh_info *host_ehi = &ap->link.eh_info; 1965 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1967 struct ata_link *link = NULL; 1966 struct ata_link *link = NULL;
1968 struct ata_queued_cmd *active_qc; 1967 struct ata_queued_cmd *active_qc;
1969 struct ata_eh_info *active_ehi; 1968 struct ata_eh_info *active_ehi;
1970 u32 serror; 1969 u32 serror;
1971 1970
1972 /* determine active link */ 1971 /* determine active link */
1973 ata_for_each_link(link, ap, EDGE) 1972 ata_for_each_link(link, ap, EDGE)
1974 if (ata_link_active(link)) 1973 if (ata_link_active(link))
1975 break; 1974 break;
1976 if (!link) 1975 if (!link)
1977 link = &ap->link; 1976 link = &ap->link;
1978 1977
1979 active_qc = ata_qc_from_tag(ap, link->active_tag); 1978 active_qc = ata_qc_from_tag(ap, link->active_tag);
1980 active_ehi = &link->eh_info; 1979 active_ehi = &link->eh_info;
1981 1980
1982 /* record irq stat */ 1981 /* record irq stat */
1983 ata_ehi_clear_desc(host_ehi); 1982 ata_ehi_clear_desc(host_ehi);
1984 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); 1983 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1985 1984
1986 /* AHCI needs SError cleared; otherwise, it might lock up */ 1985 /* AHCI needs SError cleared; otherwise, it might lock up */
1987 ahci_scr_read(&ap->link, SCR_ERROR, &serror); 1986 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1988 ahci_scr_write(&ap->link, SCR_ERROR, serror); 1987 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1989 host_ehi->serror |= serror; 1988 host_ehi->serror |= serror;
1990 1989
1991 /* some controllers set IRQ_IF_ERR on device errors, ignore it */ 1990 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1992 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) 1991 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1993 irq_stat &= ~PORT_IRQ_IF_ERR; 1992 irq_stat &= ~PORT_IRQ_IF_ERR;
1994 1993
1995 if (irq_stat & PORT_IRQ_TF_ERR) { 1994 if (irq_stat & PORT_IRQ_TF_ERR) {
1996 /* If qc is active, charge it; otherwise, the active 1995 /* If qc is active, charge it; otherwise, the active
1997 * link. There's no active qc on NCQ errors. It will 1996 * link. There's no active qc on NCQ errors. It will
1998 * be determined by EH by reading log page 10h. 1997 * be determined by EH by reading log page 10h.
1999 */ 1998 */
2000 if (active_qc) 1999 if (active_qc)
2001 active_qc->err_mask |= AC_ERR_DEV; 2000 active_qc->err_mask |= AC_ERR_DEV;
2002 else 2001 else
2003 active_ehi->err_mask |= AC_ERR_DEV; 2002 active_ehi->err_mask |= AC_ERR_DEV;
2004 2003
2005 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) 2004 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
2006 host_ehi->serror &= ~SERR_INTERNAL; 2005 host_ehi->serror &= ~SERR_INTERNAL;
2007 } 2006 }
2008 2007
2009 if (irq_stat & PORT_IRQ_UNK_FIS) { 2008 if (irq_stat & PORT_IRQ_UNK_FIS) {
2010 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); 2009 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
2011 2010
2012 active_ehi->err_mask |= AC_ERR_HSM; 2011 active_ehi->err_mask |= AC_ERR_HSM;
2013 active_ehi->action |= ATA_EH_RESET; 2012 active_ehi->action |= ATA_EH_RESET;
2014 ata_ehi_push_desc(active_ehi, 2013 ata_ehi_push_desc(active_ehi,
2015 "unknown FIS %08x %08x %08x %08x" , 2014 "unknown FIS %08x %08x %08x %08x" ,
2016 unk[0], unk[1], unk[2], unk[3]); 2015 unk[0], unk[1], unk[2], unk[3]);
2017 } 2016 }
2018 2017
2019 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) { 2018 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
2020 active_ehi->err_mask |= AC_ERR_HSM; 2019 active_ehi->err_mask |= AC_ERR_HSM;
2021 active_ehi->action |= ATA_EH_RESET; 2020 active_ehi->action |= ATA_EH_RESET;
2022 ata_ehi_push_desc(active_ehi, "incorrect PMP"); 2021 ata_ehi_push_desc(active_ehi, "incorrect PMP");
2023 } 2022 }
2024 2023
2025 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { 2024 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
2026 host_ehi->err_mask |= AC_ERR_HOST_BUS; 2025 host_ehi->err_mask |= AC_ERR_HOST_BUS;
2027 host_ehi->action |= ATA_EH_RESET; 2026 host_ehi->action |= ATA_EH_RESET;
2028 ata_ehi_push_desc(host_ehi, "host bus error"); 2027 ata_ehi_push_desc(host_ehi, "host bus error");
2029 } 2028 }
2030 2029
2031 if (irq_stat & PORT_IRQ_IF_ERR) { 2030 if (irq_stat & PORT_IRQ_IF_ERR) {
2032 host_ehi->err_mask |= AC_ERR_ATA_BUS; 2031 host_ehi->err_mask |= AC_ERR_ATA_BUS;
2033 host_ehi->action |= ATA_EH_RESET; 2032 host_ehi->action |= ATA_EH_RESET;
2034 ata_ehi_push_desc(host_ehi, "interface fatal error"); 2033 ata_ehi_push_desc(host_ehi, "interface fatal error");
2035 } 2034 }
2036 2035
2037 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { 2036 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
2038 ata_ehi_hotplugged(host_ehi); 2037 ata_ehi_hotplugged(host_ehi);
2039 ata_ehi_push_desc(host_ehi, "%s", 2038 ata_ehi_push_desc(host_ehi, "%s",
2040 irq_stat & PORT_IRQ_CONNECT ? 2039 irq_stat & PORT_IRQ_CONNECT ?
2041 "connection status changed" : "PHY RDY changed"); 2040 "connection status changed" : "PHY RDY changed");
2042 } 2041 }
2043 2042
2044 /* okay, let's hand over to EH */ 2043 /* okay, let's hand over to EH */
2045 2044
2046 if (irq_stat & PORT_IRQ_FREEZE) 2045 if (irq_stat & PORT_IRQ_FREEZE)
2047 ata_port_freeze(ap); 2046 ata_port_freeze(ap);
2048 else 2047 else
2049 ata_port_abort(ap); 2048 ata_port_abort(ap);
2050 } 2049 }
2051 2050
2052 static void ahci_port_intr(struct ata_port *ap) 2051 static void ahci_port_intr(struct ata_port *ap)
2053 { 2052 {
2054 void __iomem *port_mmio = ahci_port_base(ap); 2053 void __iomem *port_mmio = ahci_port_base(ap);
2055 struct ata_eh_info *ehi = &ap->link.eh_info; 2054 struct ata_eh_info *ehi = &ap->link.eh_info;
2056 struct ahci_port_priv *pp = ap->private_data; 2055 struct ahci_port_priv *pp = ap->private_data;
2057 struct ahci_host_priv *hpriv = ap->host->private_data; 2056 struct ahci_host_priv *hpriv = ap->host->private_data;
2058 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); 2057 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
2059 u32 status, qc_active; 2058 u32 status, qc_active;
2060 int rc; 2059 int rc;
2061 2060
2062 status = readl(port_mmio + PORT_IRQ_STAT); 2061 status = readl(port_mmio + PORT_IRQ_STAT);
2063 writel(status, port_mmio + PORT_IRQ_STAT); 2062 writel(status, port_mmio + PORT_IRQ_STAT);
2064 2063
2065 /* ignore BAD_PMP while resetting */ 2064 /* ignore BAD_PMP while resetting */
2066 if (unlikely(resetting)) 2065 if (unlikely(resetting))
2067 status &= ~PORT_IRQ_BAD_PMP; 2066 status &= ~PORT_IRQ_BAD_PMP;
2068 2067
2069 /* If we are getting PhyRdy, this is 2068 /* If we are getting PhyRdy, this is
2070 * just a power state change, we should 2069 * just a power state change, we should
2071 * clear out this, plus the PhyRdy/Comm 2070 * clear out this, plus the PhyRdy/Comm
2072 * Wake bits from Serror 2071 * Wake bits from Serror
2073 */ 2072 */
2074 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) && 2073 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
2075 (status & PORT_IRQ_PHYRDY)) { 2074 (status & PORT_IRQ_PHYRDY)) {
2076 status &= ~PORT_IRQ_PHYRDY; 2075 status &= ~PORT_IRQ_PHYRDY;
2077 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18))); 2076 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
2078 } 2077 }
2079 2078
2080 if (unlikely(status & PORT_IRQ_ERROR)) { 2079 if (unlikely(status & PORT_IRQ_ERROR)) {
2081 ahci_error_intr(ap, status); 2080 ahci_error_intr(ap, status);
2082 return; 2081 return;
2083 } 2082 }
2084 2083
2085 if (status & PORT_IRQ_SDB_FIS) { 2084 if (status & PORT_IRQ_SDB_FIS) {
2086 /* If SNotification is available, leave notification 2085 /* If SNotification is available, leave notification
2087 * handling to sata_async_notification(). If not, 2086 * handling to sata_async_notification(). If not,
2088 * emulate it by snooping SDB FIS RX area. 2087 * emulate it by snooping SDB FIS RX area.
2089 * 2088 *
2090 * Snooping FIS RX area is probably cheaper than 2089 * Snooping FIS RX area is probably cheaper than
2091 * poking SNotification but some constrollers which 2090 * poking SNotification but some constrollers which
2092 * implement SNotification, ICH9 for example, don't 2091 * implement SNotification, ICH9 for example, don't
2093 * store AN SDB FIS into receive area. 2092 * store AN SDB FIS into receive area.
2094 */ 2093 */
2095 if (hpriv->cap & HOST_CAP_SNTF) 2094 if (hpriv->cap & HOST_CAP_SNTF)
2096 sata_async_notification(ap); 2095 sata_async_notification(ap);
2097 else { 2096 else {
2098 /* If the 'N' bit in word 0 of the FIS is set, 2097 /* If the 'N' bit in word 0 of the FIS is set,
2099 * we just received asynchronous notification. 2098 * we just received asynchronous notification.
2100 * Tell libata about it. 2099 * Tell libata about it.
2101 */ 2100 */
2102 const __le32 *f = pp->rx_fis + RX_FIS_SDB; 2101 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
2103 u32 f0 = le32_to_cpu(f[0]); 2102 u32 f0 = le32_to_cpu(f[0]);
2104 2103
2105 if (f0 & (1 << 15)) 2104 if (f0 & (1 << 15))
2106 sata_async_notification(ap); 2105 sata_async_notification(ap);
2107 } 2106 }
2108 } 2107 }
2109 2108
2110 /* pp->active_link is valid iff any command is in flight */ 2109 /* pp->active_link is valid iff any command is in flight */
2111 if (ap->qc_active && pp->active_link->sactive) 2110 if (ap->qc_active && pp->active_link->sactive)
2112 qc_active = readl(port_mmio + PORT_SCR_ACT); 2111 qc_active = readl(port_mmio + PORT_SCR_ACT);
2113 else 2112 else
2114 qc_active = readl(port_mmio + PORT_CMD_ISSUE); 2113 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
2115 2114
2116 rc = ata_qc_complete_multiple(ap, qc_active); 2115 rc = ata_qc_complete_multiple(ap, qc_active);
2117 2116
2118 /* while resetting, invalid completions are expected */ 2117 /* while resetting, invalid completions are expected */
2119 if (unlikely(rc < 0 && !resetting)) { 2118 if (unlikely(rc < 0 && !resetting)) {
2120 ehi->err_mask |= AC_ERR_HSM; 2119 ehi->err_mask |= AC_ERR_HSM;
2121 ehi->action |= ATA_EH_RESET; 2120 ehi->action |= ATA_EH_RESET;
2122 ata_port_freeze(ap); 2121 ata_port_freeze(ap);
2123 } 2122 }
2124 } 2123 }
2125 2124
2126 static irqreturn_t ahci_interrupt(int irq, void *dev_instance) 2125 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
2127 { 2126 {
2128 struct ata_host *host = dev_instance; 2127 struct ata_host *host = dev_instance;
2129 struct ahci_host_priv *hpriv; 2128 struct ahci_host_priv *hpriv;
2130 unsigned int i, handled = 0; 2129 unsigned int i, handled = 0;
2131 void __iomem *mmio; 2130 void __iomem *mmio;
2132 u32 irq_stat, irq_masked; 2131 u32 irq_stat, irq_masked;
2133 2132
2134 VPRINTK("ENTER\n"); 2133 VPRINTK("ENTER\n");
2135 2134
2136 hpriv = host->private_data; 2135 hpriv = host->private_data;
2137 mmio = host->iomap[AHCI_PCI_BAR]; 2136 mmio = host->iomap[AHCI_PCI_BAR];
2138 2137
2139 /* sigh. 0xffffffff is a valid return from h/w */ 2138 /* sigh. 0xffffffff is a valid return from h/w */
2140 irq_stat = readl(mmio + HOST_IRQ_STAT); 2139 irq_stat = readl(mmio + HOST_IRQ_STAT);
2141 if (!irq_stat) 2140 if (!irq_stat)
2142 return IRQ_NONE; 2141 return IRQ_NONE;
2143 2142
2144 irq_masked = irq_stat & hpriv->port_map; 2143 irq_masked = irq_stat & hpriv->port_map;
2145 2144
2146 spin_lock(&host->lock); 2145 spin_lock(&host->lock);
2147 2146
2148 for (i = 0; i < host->n_ports; i++) { 2147 for (i = 0; i < host->n_ports; i++) {
2149 struct ata_port *ap; 2148 struct ata_port *ap;
2150 2149
2151 if (!(irq_masked & (1 << i))) 2150 if (!(irq_masked & (1 << i)))
2152 continue; 2151 continue;
2153 2152
2154 ap = host->ports[i]; 2153 ap = host->ports[i];
2155 if (ap) { 2154 if (ap) {
2156 ahci_port_intr(ap); 2155 ahci_port_intr(ap);
2157 VPRINTK("port %u\n", i); 2156 VPRINTK("port %u\n", i);
2158 } else { 2157 } else {
2159 VPRINTK("port %u (no irq)\n", i); 2158 VPRINTK("port %u (no irq)\n", i);
2160 if (ata_ratelimit()) 2159 if (ata_ratelimit())
2161 dev_printk(KERN_WARNING, host->dev, 2160 dev_printk(KERN_WARNING, host->dev,
2162 "interrupt on disabled port %u\n", i); 2161 "interrupt on disabled port %u\n", i);
2163 } 2162 }
2164 2163
2165 handled = 1; 2164 handled = 1;
2166 } 2165 }
2167 2166
2168 /* HOST_IRQ_STAT behaves as level triggered latch meaning that 2167 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
2169 * it should be cleared after all the port events are cleared; 2168 * it should be cleared after all the port events are cleared;
2170 * otherwise, it will raise a spurious interrupt after each 2169 * otherwise, it will raise a spurious interrupt after each
2171 * valid one. Please read section 10.6.2 of ahci 1.1 for more 2170 * valid one. Please read section 10.6.2 of ahci 1.1 for more
2172 * information. 2171 * information.
2173 * 2172 *
2174 * Also, use the unmasked value to clear interrupt as spurious 2173 * Also, use the unmasked value to clear interrupt as spurious
2175 * pending event on a dummy port might cause screaming IRQ. 2174 * pending event on a dummy port might cause screaming IRQ.
2176 */ 2175 */
2177 writel(irq_stat, mmio + HOST_IRQ_STAT); 2176 writel(irq_stat, mmio + HOST_IRQ_STAT);
2178 2177
2179 spin_unlock(&host->lock); 2178 spin_unlock(&host->lock);
2180 2179
2181 VPRINTK("EXIT\n"); 2180 VPRINTK("EXIT\n");
2182 2181
2183 return IRQ_RETVAL(handled); 2182 return IRQ_RETVAL(handled);
2184 } 2183 }
2185 2184
2186 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) 2185 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
2187 { 2186 {
2188 struct ata_port *ap = qc->ap; 2187 struct ata_port *ap = qc->ap;
2189 void __iomem *port_mmio = ahci_port_base(ap); 2188 void __iomem *port_mmio = ahci_port_base(ap);
2190 struct ahci_port_priv *pp = ap->private_data; 2189 struct ahci_port_priv *pp = ap->private_data;
2191 2190
2192 /* Keep track of the currently active link. It will be used 2191 /* Keep track of the currently active link. It will be used
2193 * in completion path to determine whether NCQ phase is in 2192 * in completion path to determine whether NCQ phase is in
2194 * progress. 2193 * progress.
2195 */ 2194 */
2196 pp->active_link = qc->dev->link; 2195 pp->active_link = qc->dev->link;
2197 2196
2198 if (qc->tf.protocol == ATA_PROT_NCQ) 2197 if (qc->tf.protocol == ATA_PROT_NCQ)
2199 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); 2198 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2200 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); 2199 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
2201 2200
2202 ahci_sw_activity(qc->dev->link); 2201 ahci_sw_activity(qc->dev->link);
2203 2202
2204 return 0; 2203 return 0;
2205 } 2204 }
2206 2205
2207 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc) 2206 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2208 { 2207 {
2209 struct ahci_port_priv *pp = qc->ap->private_data; 2208 struct ahci_port_priv *pp = qc->ap->private_data;
2210 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 2209 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
2211 2210
2212 ata_tf_from_fis(d2h_fis, &qc->result_tf); 2211 ata_tf_from_fis(d2h_fis, &qc->result_tf);
2213 return true; 2212 return true;
2214 } 2213 }
2215 2214
2216 static void ahci_freeze(struct ata_port *ap) 2215 static void ahci_freeze(struct ata_port *ap)
2217 { 2216 {
2218 void __iomem *port_mmio = ahci_port_base(ap); 2217 void __iomem *port_mmio = ahci_port_base(ap);
2219 2218
2220 /* turn IRQ off */ 2219 /* turn IRQ off */
2221 writel(0, port_mmio + PORT_IRQ_MASK); 2220 writel(0, port_mmio + PORT_IRQ_MASK);
2222 } 2221 }
2223 2222
2224 static void ahci_thaw(struct ata_port *ap) 2223 static void ahci_thaw(struct ata_port *ap)
2225 { 2224 {
2226 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; 2225 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
2227 void __iomem *port_mmio = ahci_port_base(ap); 2226 void __iomem *port_mmio = ahci_port_base(ap);
2228 u32 tmp; 2227 u32 tmp;
2229 struct ahci_port_priv *pp = ap->private_data; 2228 struct ahci_port_priv *pp = ap->private_data;
2230 2229
2231 /* clear IRQ */ 2230 /* clear IRQ */
2232 tmp = readl(port_mmio + PORT_IRQ_STAT); 2231 tmp = readl(port_mmio + PORT_IRQ_STAT);
2233 writel(tmp, port_mmio + PORT_IRQ_STAT); 2232 writel(tmp, port_mmio + PORT_IRQ_STAT);
2234 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); 2233 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2235 2234
2236 /* turn IRQ back on */ 2235 /* turn IRQ back on */
2237 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2236 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2238 } 2237 }
2239 2238
2240 static void ahci_error_handler(struct ata_port *ap) 2239 static void ahci_error_handler(struct ata_port *ap)
2241 { 2240 {
2242 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 2241 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2243 /* restart engine */ 2242 /* restart engine */
2244 ahci_stop_engine(ap); 2243 ahci_stop_engine(ap);
2245 ahci_start_engine(ap); 2244 ahci_start_engine(ap);
2246 } 2245 }
2247 2246
2248 sata_pmp_error_handler(ap); 2247 sata_pmp_error_handler(ap);
2249 } 2248 }
2250 2249
2251 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) 2250 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2252 { 2251 {
2253 struct ata_port *ap = qc->ap; 2252 struct ata_port *ap = qc->ap;
2254 2253
2255 /* make DMA engine forget about the failed command */ 2254 /* make DMA engine forget about the failed command */
2256 if (qc->flags & ATA_QCFLAG_FAILED) 2255 if (qc->flags & ATA_QCFLAG_FAILED)
2257 ahci_kick_engine(ap, 1); 2256 ahci_kick_engine(ap, 1);
2258 } 2257 }
2259 2258
2260 static void ahci_pmp_attach(struct ata_port *ap) 2259 static void ahci_pmp_attach(struct ata_port *ap)
2261 { 2260 {
2262 void __iomem *port_mmio = ahci_port_base(ap); 2261 void __iomem *port_mmio = ahci_port_base(ap);
2263 struct ahci_port_priv *pp = ap->private_data; 2262 struct ahci_port_priv *pp = ap->private_data;
2264 u32 cmd; 2263 u32 cmd;
2265 2264
2266 cmd = readl(port_mmio + PORT_CMD); 2265 cmd = readl(port_mmio + PORT_CMD);
2267 cmd |= PORT_CMD_PMP; 2266 cmd |= PORT_CMD_PMP;
2268 writel(cmd, port_mmio + PORT_CMD); 2267 writel(cmd, port_mmio + PORT_CMD);
2269 2268
2270 pp->intr_mask |= PORT_IRQ_BAD_PMP; 2269 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2271 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2270 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2272 } 2271 }
2273 2272
2274 static void ahci_pmp_detach(struct ata_port *ap) 2273 static void ahci_pmp_detach(struct ata_port *ap)
2275 { 2274 {
2276 void __iomem *port_mmio = ahci_port_base(ap); 2275 void __iomem *port_mmio = ahci_port_base(ap);
2277 struct ahci_port_priv *pp = ap->private_data; 2276 struct ahci_port_priv *pp = ap->private_data;
2278 u32 cmd; 2277 u32 cmd;
2279 2278
2280 cmd = readl(port_mmio + PORT_CMD); 2279 cmd = readl(port_mmio + PORT_CMD);
2281 cmd &= ~PORT_CMD_PMP; 2280 cmd &= ~PORT_CMD_PMP;
2282 writel(cmd, port_mmio + PORT_CMD); 2281 writel(cmd, port_mmio + PORT_CMD);
2283 2282
2284 pp->intr_mask &= ~PORT_IRQ_BAD_PMP; 2283 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2285 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2284 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2286 } 2285 }
2287 2286
2288 static int ahci_port_resume(struct ata_port *ap) 2287 static int ahci_port_resume(struct ata_port *ap)
2289 { 2288 {
2290 ahci_power_up(ap); 2289 ahci_power_up(ap);
2291 ahci_start_port(ap); 2290 ahci_start_port(ap);
2292 2291
2293 if (sata_pmp_attached(ap)) 2292 if (sata_pmp_attached(ap))
2294 ahci_pmp_attach(ap); 2293 ahci_pmp_attach(ap);
2295 else 2294 else
2296 ahci_pmp_detach(ap); 2295 ahci_pmp_detach(ap);
2297 2296
2298 return 0; 2297 return 0;
2299 } 2298 }
2300 2299
2301 #ifdef CONFIG_PM 2300 #ifdef CONFIG_PM
2302 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) 2301 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2303 { 2302 {
2304 const char *emsg = NULL; 2303 const char *emsg = NULL;
2305 int rc; 2304 int rc;
2306 2305
2307 rc = ahci_deinit_port(ap, &emsg); 2306 rc = ahci_deinit_port(ap, &emsg);
2308 if (rc == 0) 2307 if (rc == 0)
2309 ahci_power_down(ap); 2308 ahci_power_down(ap);
2310 else { 2309 else {
2311 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); 2310 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
2312 ahci_start_port(ap); 2311 ahci_start_port(ap);
2313 } 2312 }
2314 2313
2315 return rc; 2314 return rc;
2316 } 2315 }
2317 2316
2318 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) 2317 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
2319 { 2318 {
2320 struct ata_host *host = dev_get_drvdata(&pdev->dev); 2319 struct ata_host *host = dev_get_drvdata(&pdev->dev);
2321 struct ahci_host_priv *hpriv = host->private_data; 2320 struct ahci_host_priv *hpriv = host->private_data;
2322 void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; 2321 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2323 u32 ctl; 2322 u32 ctl;
2324 2323
2325 if (mesg.event & PM_EVENT_SUSPEND && 2324 if (mesg.event & PM_EVENT_SUSPEND &&
2326 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { 2325 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
2327 dev_printk(KERN_ERR, &pdev->dev, 2326 dev_printk(KERN_ERR, &pdev->dev,
2328 "BIOS update required for suspend/resume\n"); 2327 "BIOS update required for suspend/resume\n");
2329 return -EIO; 2328 return -EIO;
2330 } 2329 }
2331 2330
2332 if (mesg.event & PM_EVENT_SLEEP) { 2331 if (mesg.event & PM_EVENT_SLEEP) {
2333 /* AHCI spec rev1.1 section 8.3.3: 2332 /* AHCI spec rev1.1 section 8.3.3:
2334 * Software must disable interrupts prior to requesting a 2333 * Software must disable interrupts prior to requesting a
2335 * transition of the HBA to D3 state. 2334 * transition of the HBA to D3 state.
2336 */ 2335 */
2337 ctl = readl(mmio + HOST_CTL); 2336 ctl = readl(mmio + HOST_CTL);
2338 ctl &= ~HOST_IRQ_EN; 2337 ctl &= ~HOST_IRQ_EN;
2339 writel(ctl, mmio + HOST_CTL); 2338 writel(ctl, mmio + HOST_CTL);
2340 readl(mmio + HOST_CTL); /* flush */ 2339 readl(mmio + HOST_CTL); /* flush */
2341 } 2340 }
2342 2341
2343 return ata_pci_device_suspend(pdev, mesg); 2342 return ata_pci_device_suspend(pdev, mesg);
2344 } 2343 }
2345 2344
2346 static int ahci_pci_device_resume(struct pci_dev *pdev) 2345 static int ahci_pci_device_resume(struct pci_dev *pdev)
2347 { 2346 {
2348 struct ata_host *host = dev_get_drvdata(&pdev->dev); 2347 struct ata_host *host = dev_get_drvdata(&pdev->dev);
2349 int rc; 2348 int rc;
2350 2349
2351 rc = ata_pci_device_do_resume(pdev); 2350 rc = ata_pci_device_do_resume(pdev);
2352 if (rc) 2351 if (rc)
2353 return rc; 2352 return rc;
2354 2353
2355 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 2354 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
2356 rc = ahci_reset_controller(host); 2355 rc = ahci_reset_controller(host);
2357 if (rc) 2356 if (rc)
2358 return rc; 2357 return rc;
2359 2358
2360 ahci_init_controller(host); 2359 ahci_init_controller(host);
2361 } 2360 }
2362 2361
2363 ata_host_resume(host); 2362 ata_host_resume(host);
2364 2363
2365 return 0; 2364 return 0;
2366 } 2365 }
2367 #endif 2366 #endif
2368 2367
2369 static int ahci_port_start(struct ata_port *ap) 2368 static int ahci_port_start(struct ata_port *ap)
2370 { 2369 {
2371 struct device *dev = ap->host->dev; 2370 struct device *dev = ap->host->dev;
2372 struct ahci_port_priv *pp; 2371 struct ahci_port_priv *pp;
2373 void *mem; 2372 void *mem;
2374 dma_addr_t mem_dma; 2373 dma_addr_t mem_dma;
2375 2374
2376 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 2375 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2377 if (!pp) 2376 if (!pp)
2378 return -ENOMEM; 2377 return -ENOMEM;
2379 2378
2380 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, 2379 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2381 GFP_KERNEL); 2380 GFP_KERNEL);
2382 if (!mem) 2381 if (!mem)
2383 return -ENOMEM; 2382 return -ENOMEM;
2384 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); 2383 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2385 2384
2386 /* 2385 /*
2387 * First item in chunk of DMA memory: 32-slot command table, 2386 * First item in chunk of DMA memory: 32-slot command table,
2388 * 32 bytes each in size 2387 * 32 bytes each in size
2389 */ 2388 */
2390 pp->cmd_slot = mem; 2389 pp->cmd_slot = mem;
2391 pp->cmd_slot_dma = mem_dma; 2390 pp->cmd_slot_dma = mem_dma;
2392 2391
2393 mem += AHCI_CMD_SLOT_SZ; 2392 mem += AHCI_CMD_SLOT_SZ;
2394 mem_dma += AHCI_CMD_SLOT_SZ; 2393 mem_dma += AHCI_CMD_SLOT_SZ;
2395 2394
2396 /* 2395 /*
2397 * Second item: Received-FIS area 2396 * Second item: Received-FIS area
2398 */ 2397 */
2399 pp->rx_fis = mem; 2398 pp->rx_fis = mem;
2400 pp->rx_fis_dma = mem_dma; 2399 pp->rx_fis_dma = mem_dma;
2401 2400
2402 mem += AHCI_RX_FIS_SZ; 2401 mem += AHCI_RX_FIS_SZ;
2403 mem_dma += AHCI_RX_FIS_SZ; 2402 mem_dma += AHCI_RX_FIS_SZ;
2404 2403
2405 /* 2404 /*
2406 * Third item: data area for storing a single command 2405 * Third item: data area for storing a single command
2407 * and its scatter-gather table 2406 * and its scatter-gather table
2408 */ 2407 */
2409 pp->cmd_tbl = mem; 2408 pp->cmd_tbl = mem;
2410 pp->cmd_tbl_dma = mem_dma; 2409 pp->cmd_tbl_dma = mem_dma;
2411 2410
2412 /* 2411 /*
2413 * Save off initial list of interrupts to be enabled. 2412 * Save off initial list of interrupts to be enabled.
2414 * This could be changed later 2413 * This could be changed later
2415 */ 2414 */
2416 pp->intr_mask = DEF_PORT_IRQ; 2415 pp->intr_mask = DEF_PORT_IRQ;
2417 2416
2418 ap->private_data = pp; 2417 ap->private_data = pp;
2419 2418
2420 /* engage engines, captain */ 2419 /* engage engines, captain */
2421 return ahci_port_resume(ap); 2420 return ahci_port_resume(ap);
2422 } 2421 }
2423 2422
2424 static void ahci_port_stop(struct ata_port *ap) 2423 static void ahci_port_stop(struct ata_port *ap)
2425 { 2424 {
2426 const char *emsg = NULL; 2425 const char *emsg = NULL;
2427 int rc; 2426 int rc;
2428 2427
2429 /* de-initialize port */ 2428 /* de-initialize port */
2430 rc = ahci_deinit_port(ap, &emsg); 2429 rc = ahci_deinit_port(ap, &emsg);
2431 if (rc) 2430 if (rc)
2432 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); 2431 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2433 } 2432 }
2434 2433
2435 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) 2434 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
2436 { 2435 {
2437 int rc; 2436 int rc;
2438 2437
2439 if (using_dac && 2438 if (using_dac &&
2440 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 2439 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2441 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 2440 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
2442 if (rc) { 2441 if (rc) {
2443 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 2442 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2444 if (rc) { 2443 if (rc) {
2445 dev_printk(KERN_ERR, &pdev->dev, 2444 dev_printk(KERN_ERR, &pdev->dev,
2446 "64-bit DMA enable failed\n"); 2445 "64-bit DMA enable failed\n");
2447 return rc; 2446 return rc;
2448 } 2447 }
2449 } 2448 }
2450 } else { 2449 } else {
2451 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 2450 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2452 if (rc) { 2451 if (rc) {
2453 dev_printk(KERN_ERR, &pdev->dev, 2452 dev_printk(KERN_ERR, &pdev->dev,
2454 "32-bit DMA enable failed\n"); 2453 "32-bit DMA enable failed\n");
2455 return rc; 2454 return rc;
2456 } 2455 }
2457 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 2456 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2458 if (rc) { 2457 if (rc) {
2459 dev_printk(KERN_ERR, &pdev->dev, 2458 dev_printk(KERN_ERR, &pdev->dev,
2460 "32-bit consistent DMA enable failed\n"); 2459 "32-bit consistent DMA enable failed\n");
2461 return rc; 2460 return rc;
2462 } 2461 }
2463 } 2462 }
2464 return 0; 2463 return 0;
2465 } 2464 }
2466 2465
2467 static void ahci_print_info(struct ata_host *host) 2466 static void ahci_print_info(struct ata_host *host)
2468 { 2467 {
2469 struct ahci_host_priv *hpriv = host->private_data; 2468 struct ahci_host_priv *hpriv = host->private_data;
2470 struct pci_dev *pdev = to_pci_dev(host->dev); 2469 struct pci_dev *pdev = to_pci_dev(host->dev);
2471 void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; 2470 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2472 u32 vers, cap, impl, speed; 2471 u32 vers, cap, impl, speed;
2473 const char *speed_s; 2472 const char *speed_s;
2474 u16 cc; 2473 u16 cc;
2475 const char *scc_s; 2474 const char *scc_s;
2476 2475
2477 vers = readl(mmio + HOST_VERSION); 2476 vers = readl(mmio + HOST_VERSION);
2478 cap = hpriv->cap; 2477 cap = hpriv->cap;
2479 impl = hpriv->port_map; 2478 impl = hpriv->port_map;
2480 2479
2481 speed = (cap >> 20) & 0xf; 2480 speed = (cap >> 20) & 0xf;
2482 if (speed == 1) 2481 if (speed == 1)
2483 speed_s = "1.5"; 2482 speed_s = "1.5";
2484 else if (speed == 2) 2483 else if (speed == 2)
2485 speed_s = "3"; 2484 speed_s = "3";
2486 else if (speed == 3) 2485 else if (speed == 3)
2487 speed_s = "6"; 2486 speed_s = "6";
2488 else 2487 else
2489 speed_s = "?"; 2488 speed_s = "?";
2490 2489
2491 pci_read_config_word(pdev, 0x0a, &cc); 2490 pci_read_config_word(pdev, 0x0a, &cc);
2492 if (cc == PCI_CLASS_STORAGE_IDE) 2491 if (cc == PCI_CLASS_STORAGE_IDE)
2493 scc_s = "IDE"; 2492 scc_s = "IDE";
2494 else if (cc == PCI_CLASS_STORAGE_SATA) 2493 else if (cc == PCI_CLASS_STORAGE_SATA)
2495 scc_s = "SATA"; 2494 scc_s = "SATA";
2496 else if (cc == PCI_CLASS_STORAGE_RAID) 2495 else if (cc == PCI_CLASS_STORAGE_RAID)
2497 scc_s = "RAID"; 2496 scc_s = "RAID";
2498 else 2497 else
2499 scc_s = "unknown"; 2498 scc_s = "unknown";
2500 2499
2501 dev_printk(KERN_INFO, &pdev->dev, 2500 dev_printk(KERN_INFO, &pdev->dev,
2502 "AHCI %02x%02x.%02x%02x " 2501 "AHCI %02x%02x.%02x%02x "
2503 "%u slots %u ports %s Gbps 0x%x impl %s mode\n" 2502 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2504 , 2503 ,
2505 2504
2506 (vers >> 24) & 0xff, 2505 (vers >> 24) & 0xff,
2507 (vers >> 16) & 0xff, 2506 (vers >> 16) & 0xff,
2508 (vers >> 8) & 0xff, 2507 (vers >> 8) & 0xff,
2509 vers & 0xff, 2508 vers & 0xff,
2510 2509
2511 ((cap >> 8) & 0x1f) + 1, 2510 ((cap >> 8) & 0x1f) + 1,
2512 (cap & 0x1f) + 1, 2511 (cap & 0x1f) + 1,
2513 speed_s, 2512 speed_s,
2514 impl, 2513 impl,
2515 scc_s); 2514 scc_s);
2516 2515
2517 dev_printk(KERN_INFO, &pdev->dev, 2516 dev_printk(KERN_INFO, &pdev->dev,
2518 "flags: " 2517 "flags: "
2519 "%s%s%s%s%s%s%s" 2518 "%s%s%s%s%s%s%s"
2520 "%s%s%s%s%s%s%s" 2519 "%s%s%s%s%s%s%s"
2521 "%s\n" 2520 "%s\n"
2522 , 2521 ,
2523 2522
2524 cap & (1 << 31) ? "64bit " : "", 2523 cap & (1 << 31) ? "64bit " : "",
2525 cap & (1 << 30) ? "ncq " : "", 2524 cap & (1 << 30) ? "ncq " : "",
2526 cap & (1 << 29) ? "sntf " : "", 2525 cap & (1 << 29) ? "sntf " : "",
2527 cap & (1 << 28) ? "ilck " : "", 2526 cap & (1 << 28) ? "ilck " : "",
2528 cap & (1 << 27) ? "stag " : "", 2527 cap & (1 << 27) ? "stag " : "",
2529 cap & (1 << 26) ? "pm " : "", 2528 cap & (1 << 26) ? "pm " : "",
2530 cap & (1 << 25) ? "led " : "", 2529 cap & (1 << 25) ? "led " : "",
2531 2530
2532 cap & (1 << 24) ? "clo " : "", 2531 cap & (1 << 24) ? "clo " : "",
2533 cap & (1 << 19) ? "nz " : "", 2532 cap & (1 << 19) ? "nz " : "",
2534 cap & (1 << 18) ? "only " : "", 2533 cap & (1 << 18) ? "only " : "",
2535 cap & (1 << 17) ? "pmp " : "", 2534 cap & (1 << 17) ? "pmp " : "",
2536 cap & (1 << 15) ? "pio " : "", 2535 cap & (1 << 15) ? "pio " : "",
2537 cap & (1 << 14) ? "slum " : "", 2536 cap & (1 << 14) ? "slum " : "",
2538 cap & (1 << 13) ? "part " : "", 2537 cap & (1 << 13) ? "part " : "",
2539 cap & (1 << 6) ? "ems ": "" 2538 cap & (1 << 6) ? "ems ": ""
2540 ); 2539 );
2541 } 2540 }
2542 2541
2543 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is 2542 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2544 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't 2543 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2545 * support PMP and the 4726 either directly exports the device 2544 * support PMP and the 4726 either directly exports the device
2546 * attached to the first downstream port or acts as a hardware storage 2545 * attached to the first downstream port or acts as a hardware storage
2547 * controller and emulate a single ATA device (can be RAID 0/1 or some 2546 * controller and emulate a single ATA device (can be RAID 0/1 or some
2548 * other configuration). 2547 * other configuration).
2549 * 2548 *
2550 * When there's no device attached to the first downstream port of the 2549 * When there's no device attached to the first downstream port of the
2551 * 4726, "Config Disk" appears, which is a pseudo ATA device to 2550 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2552 * configure the 4726. However, ATA emulation of the device is very 2551 * configure the 4726. However, ATA emulation of the device is very
2553 * lame. It doesn't send signature D2H Reg FIS after the initial 2552 * lame. It doesn't send signature D2H Reg FIS after the initial
2554 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. 2553 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2555 * 2554 *
2556 * The following function works around the problem by always using 2555 * The following function works around the problem by always using
2557 * hardreset on the port and not depending on receiving signature FIS 2556 * hardreset on the port and not depending on receiving signature FIS
2558 * afterward. If signature FIS isn't received soon, ATA class is 2557 * afterward. If signature FIS isn't received soon, ATA class is
2559 * assumed without follow-up softreset. 2558 * assumed without follow-up softreset.
2560 */ 2559 */
2561 static void ahci_p5wdh_workaround(struct ata_host *host) 2560 static void ahci_p5wdh_workaround(struct ata_host *host)
2562 { 2561 {
2563 static struct dmi_system_id sysids[] = { 2562 static struct dmi_system_id sysids[] = {
2564 { 2563 {
2565 .ident = "P5W DH Deluxe", 2564 .ident = "P5W DH Deluxe",
2566 .matches = { 2565 .matches = {
2567 DMI_MATCH(DMI_SYS_VENDOR, 2566 DMI_MATCH(DMI_SYS_VENDOR,
2568 "ASUSTEK COMPUTER INC"), 2567 "ASUSTEK COMPUTER INC"),
2569 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), 2568 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2570 }, 2569 },
2571 }, 2570 },
2572 { } 2571 { }
2573 }; 2572 };
2574 struct pci_dev *pdev = to_pci_dev(host->dev); 2573 struct pci_dev *pdev = to_pci_dev(host->dev);
2575 2574
2576 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && 2575 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2577 dmi_check_system(sysids)) { 2576 dmi_check_system(sysids)) {
2578 struct ata_port *ap = host->ports[1]; 2577 struct ata_port *ap = host->ports[1];
2579 2578
2580 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH " 2579 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2581 "Deluxe on-board SIMG4726 workaround\n"); 2580 "Deluxe on-board SIMG4726 workaround\n");
2582 2581
2583 ap->ops = &ahci_p5wdh_ops; 2582 ap->ops = &ahci_p5wdh_ops;
2584 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; 2583 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2585 } 2584 }
2586 } 2585 }
2587 2586
2587 /*
2588 * SB600 ahci controller on ASUS M2A-VM can't do 64bit DMA with older
2589 * BIOS. The oldest version known to be broken is 0901 and working is
2590 * 1501 which was released on 2007-10-26. Force 32bit DMA on anything
2591 * older than 1501. Please read bko#9412 for more info.
2592 */
2593 static bool ahci_asus_m2a_vm_32bit_only(struct pci_dev *pdev)
2594 {
2595 static const struct dmi_system_id sysids[] = {
2596 {
2597 .ident = "ASUS M2A-VM",
2598 .matches = {
2599 DMI_MATCH(DMI_BOARD_VENDOR,
2600 "ASUSTeK Computer INC."),
2601 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
2602 },
2603 },
2604 { }
2605 };
2606 const char *cutoff_mmdd = "10/26";
2607 const char *date;
2608 int year;
2609
2610 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
2611 !dmi_check_system(sysids))
2612 return false;
2613
2614 /*
2615 * Argh.... both version and date are free form strings.
2616 * Let's hope they're using the same date format across
2617 * different versions.
2618 */
2619 date = dmi_get_system_info(DMI_BIOS_DATE);
2620 year = dmi_get_year(DMI_BIOS_DATE);
2621 if (date && strlen(date) >= 10 && date[2] == '/' && date[5] == '/' &&
2622 (year > 2007 ||
2623 (year == 2007 && strncmp(date, cutoff_mmdd, 5) >= 0)))
2624 return false;
2625
2626 dev_printk(KERN_WARNING, &pdev->dev, "ASUS M2A-VM: BIOS too old, "
2627 "forcing 32bit DMA, update BIOS\n");
2628
2629 return true;
2630 }
2631
2588 static bool ahci_broken_system_poweroff(struct pci_dev *pdev) 2632 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
2589 { 2633 {
2590 static const struct dmi_system_id broken_systems[] = { 2634 static const struct dmi_system_id broken_systems[] = {
2591 { 2635 {
2592 .ident = "HP Compaq nx6310", 2636 .ident = "HP Compaq nx6310",
2593 .matches = { 2637 .matches = {
2594 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 2638 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2595 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), 2639 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
2596 }, 2640 },
2597 /* PCI slot number of the controller */ 2641 /* PCI slot number of the controller */
2598 .driver_data = (void *)0x1FUL, 2642 .driver_data = (void *)0x1FUL,
2599 }, 2643 },
2600 { 2644 {
2601 .ident = "HP Compaq 6720s", 2645 .ident = "HP Compaq 6720s",
2602 .matches = { 2646 .matches = {
2603 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 2647 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2604 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), 2648 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
2605 }, 2649 },
2606 /* PCI slot number of the controller */ 2650 /* PCI slot number of the controller */
2607 .driver_data = (void *)0x1FUL, 2651 .driver_data = (void *)0x1FUL,
2608 }, 2652 },
2609 2653
2610 { } /* terminate list */ 2654 { } /* terminate list */
2611 }; 2655 };
2612 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 2656 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
2613 2657
2614 if (dmi) { 2658 if (dmi) {
2615 unsigned long slot = (unsigned long)dmi->driver_data; 2659 unsigned long slot = (unsigned long)dmi->driver_data;
2616 /* apply the quirk only to on-board controllers */ 2660 /* apply the quirk only to on-board controllers */
2617 return slot == PCI_SLOT(pdev->devfn); 2661 return slot == PCI_SLOT(pdev->devfn);
2618 } 2662 }
2619 2663
2620 return false; 2664 return false;
2621 } 2665 }
2622 2666
2623 static bool ahci_broken_suspend(struct pci_dev *pdev) 2667 static bool ahci_broken_suspend(struct pci_dev *pdev)
2624 { 2668 {
2625 static const struct dmi_system_id sysids[] = { 2669 static const struct dmi_system_id sysids[] = {
2626 /* 2670 /*
2627 * On HP dv[4-6] and HDX18 with earlier BIOSen, link 2671 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
2628 * to the harddisk doesn't become online after 2672 * to the harddisk doesn't become online after
2629 * resuming from STR. Warn and fail suspend. 2673 * resuming from STR. Warn and fail suspend.
2630 */ 2674 */
2631 { 2675 {
2632 .ident = "dv4", 2676 .ident = "dv4",
2633 .matches = { 2677 .matches = {
2634 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 2678 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2635 DMI_MATCH(DMI_PRODUCT_NAME, 2679 DMI_MATCH(DMI_PRODUCT_NAME,
2636 "HP Pavilion dv4 Notebook PC"), 2680 "HP Pavilion dv4 Notebook PC"),
2637 }, 2681 },
2638 .driver_data = "F.30", /* cutoff BIOS version */ 2682 .driver_data = "F.30", /* cutoff BIOS version */
2639 }, 2683 },
2640 { 2684 {
2641 .ident = "dv5", 2685 .ident = "dv5",
2642 .matches = { 2686 .matches = {
2643 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 2687 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2644 DMI_MATCH(DMI_PRODUCT_NAME, 2688 DMI_MATCH(DMI_PRODUCT_NAME,
2645 "HP Pavilion dv5 Notebook PC"), 2689 "HP Pavilion dv5 Notebook PC"),
2646 }, 2690 },
2647 .driver_data = "F.16", /* cutoff BIOS version */ 2691 .driver_data = "F.16", /* cutoff BIOS version */
2648 }, 2692 },
2649 { 2693 {
2650 .ident = "dv6", 2694 .ident = "dv6",
2651 .matches = { 2695 .matches = {
2652 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 2696 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2653 DMI_MATCH(DMI_PRODUCT_NAME, 2697 DMI_MATCH(DMI_PRODUCT_NAME,
2654 "HP Pavilion dv6 Notebook PC"), 2698 "HP Pavilion dv6 Notebook PC"),
2655 }, 2699 },
2656 .driver_data = "F.21", /* cutoff BIOS version */ 2700 .driver_data = "F.21", /* cutoff BIOS version */
2657 }, 2701 },
2658 { 2702 {
2659 .ident = "HDX18", 2703 .ident = "HDX18",
2660 .matches = { 2704 .matches = {
2661 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 2705 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2662 DMI_MATCH(DMI_PRODUCT_NAME, 2706 DMI_MATCH(DMI_PRODUCT_NAME,
2663 "HP HDX18 Notebook PC"), 2707 "HP HDX18 Notebook PC"),
2664 }, 2708 },
2665 .driver_data = "F.23", /* cutoff BIOS version */ 2709 .driver_data = "F.23", /* cutoff BIOS version */
2666 }, 2710 },
2667 { } /* terminate list */ 2711 { } /* terminate list */
2668 }; 2712 };
2669 const struct dmi_system_id *dmi = dmi_first_match(sysids); 2713 const struct dmi_system_id *dmi = dmi_first_match(sysids);
2670 const char *ver; 2714 const char *ver;
2671 2715
2672 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) 2716 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
2673 return false; 2717 return false;
2674 2718
2675 ver = dmi_get_system_info(DMI_BIOS_VERSION); 2719 ver = dmi_get_system_info(DMI_BIOS_VERSION);
2676 2720
2677 return !ver || strcmp(ver, dmi->driver_data) < 0; 2721 return !ver || strcmp(ver, dmi->driver_data) < 0;
2678 } 2722 }
2679 2723
2680 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 2724 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2681 { 2725 {
2682 static int printed_version; 2726 static int printed_version;
2683 unsigned int board_id = ent->driver_data; 2727 unsigned int board_id = ent->driver_data;
2684 struct ata_port_info pi = ahci_port_info[board_id]; 2728 struct ata_port_info pi = ahci_port_info[board_id];
2685 const struct ata_port_info *ppi[] = { &pi, NULL }; 2729 const struct ata_port_info *ppi[] = { &pi, NULL };
2686 struct device *dev = &pdev->dev; 2730 struct device *dev = &pdev->dev;
2687 struct ahci_host_priv *hpriv; 2731 struct ahci_host_priv *hpriv;
2688 struct ata_host *host; 2732 struct ata_host *host;
2689 int n_ports, i, rc; 2733 int n_ports, i, rc;
2690 2734
2691 VPRINTK("ENTER\n"); 2735 VPRINTK("ENTER\n");
2692 2736
2693 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS); 2737 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2694 2738
2695 if (!printed_version++) 2739 if (!printed_version++)
2696 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 2740 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
2697 2741
2698 /* The AHCI driver can only drive the SATA ports, the PATA driver 2742 /* The AHCI driver can only drive the SATA ports, the PATA driver
2699 can drive them all so if both drivers are selected make sure 2743 can drive them all so if both drivers are selected make sure
2700 AHCI stays out of the way */ 2744 AHCI stays out of the way */
2701 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) 2745 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
2702 return -ENODEV; 2746 return -ENODEV;
2703 2747
2704 /* acquire resources */ 2748 /* acquire resources */
2705 rc = pcim_enable_device(pdev); 2749 rc = pcim_enable_device(pdev);
2706 if (rc) 2750 if (rc)
2707 return rc; 2751 return rc;
2708 2752
2709 /* AHCI controllers often implement SFF compatible interface. 2753 /* AHCI controllers often implement SFF compatible interface.
2710 * Grab all PCI BARs just in case. 2754 * Grab all PCI BARs just in case.
2711 */ 2755 */
2712 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME); 2756 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
2713 if (rc == -EBUSY) 2757 if (rc == -EBUSY)
2714 pcim_pin_device(pdev); 2758 pcim_pin_device(pdev);
2715 if (rc) 2759 if (rc)
2716 return rc; 2760 return rc;
2717 2761
2718 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 2762 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2719 (pdev->device == 0x2652 || pdev->device == 0x2653)) { 2763 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2720 u8 map; 2764 u8 map;
2721 2765
2722 /* ICH6s share the same PCI ID for both piix and ahci 2766 /* ICH6s share the same PCI ID for both piix and ahci
2723 * modes. Enabling ahci mode while MAP indicates 2767 * modes. Enabling ahci mode while MAP indicates
2724 * combined mode is a bad idea. Yield to ata_piix. 2768 * combined mode is a bad idea. Yield to ata_piix.
2725 */ 2769 */
2726 pci_read_config_byte(pdev, ICH_MAP, &map); 2770 pci_read_config_byte(pdev, ICH_MAP, &map);
2727 if (map & 0x3) { 2771 if (map & 0x3) {
2728 dev_printk(KERN_INFO, &pdev->dev, "controller is in " 2772 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2729 "combined mode, can't enable AHCI mode\n"); 2773 "combined mode, can't enable AHCI mode\n");
2730 return -ENODEV; 2774 return -ENODEV;
2731 } 2775 }
2732 } 2776 }
2733 2777
2734 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 2778 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2735 if (!hpriv) 2779 if (!hpriv)
2736 return -ENOMEM; 2780 return -ENOMEM;
2737 hpriv->flags |= (unsigned long)pi.private_data; 2781 hpriv->flags |= (unsigned long)pi.private_data;
2738 2782
2739 /* MCP65 revision A1 and A2 can't do MSI */ 2783 /* MCP65 revision A1 and A2 can't do MSI */
2740 if (board_id == board_ahci_mcp65 && 2784 if (board_id == board_ahci_mcp65 &&
2741 (pdev->revision == 0xa1 || pdev->revision == 0xa2)) 2785 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
2742 hpriv->flags |= AHCI_HFLAG_NO_MSI; 2786 hpriv->flags |= AHCI_HFLAG_NO_MSI;
2743 2787
2744 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ 2788 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
2745 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) 2789 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
2746 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; 2790 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
2791
2792 /* apply ASUS M2A_VM quirk */
2793 if (ahci_asus_m2a_vm_32bit_only(pdev))
2794 hpriv->flags |= AHCI_HFLAG_32BIT_ONLY;
2747 2795
2748 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) 2796 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI))
2749 pci_enable_msi(pdev); 2797 pci_enable_msi(pdev);
2750 2798
2751 /* save initial config */ 2799 /* save initial config */
2752 ahci_save_initial_config(pdev, hpriv); 2800 ahci_save_initial_config(pdev, hpriv);
2753 2801
2754 /* prepare host */ 2802 /* prepare host */
2755 if (hpriv->cap & HOST_CAP_NCQ) 2803 if (hpriv->cap & HOST_CAP_NCQ)
2756 pi.flags |= ATA_FLAG_NCQ; 2804 pi.flags |= ATA_FLAG_NCQ;
2757 2805
2758 if (hpriv->cap & HOST_CAP_PMP) 2806 if (hpriv->cap & HOST_CAP_PMP)
2759 pi.flags |= ATA_FLAG_PMP; 2807 pi.flags |= ATA_FLAG_PMP;
2760 2808
2761 if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) { 2809 if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) {
2762 u8 messages; 2810 u8 messages;
2763 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; 2811 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
2764 u32 em_loc = readl(mmio + HOST_EM_LOC); 2812 u32 em_loc = readl(mmio + HOST_EM_LOC);
2765 u32 em_ctl = readl(mmio + HOST_EM_CTL); 2813 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2766 2814
2767 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16; 2815 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2768 2816
2769 /* we only support LED message type right now */ 2817 /* we only support LED message type right now */
2770 if ((messages & 0x01) && (ahci_em_messages == 1)) { 2818 if ((messages & 0x01) && (ahci_em_messages == 1)) {
2771 /* store em_loc */ 2819 /* store em_loc */
2772 hpriv->em_loc = ((em_loc >> 16) * 4); 2820 hpriv->em_loc = ((em_loc >> 16) * 4);
2773 pi.flags |= ATA_FLAG_EM; 2821 pi.flags |= ATA_FLAG_EM;
2774 if (!(em_ctl & EM_CTL_ALHD)) 2822 if (!(em_ctl & EM_CTL_ALHD))
2775 pi.flags |= ATA_FLAG_SW_ACTIVITY; 2823 pi.flags |= ATA_FLAG_SW_ACTIVITY;
2776 } 2824 }
2777 } 2825 }
2778 2826
2779 if (ahci_broken_system_poweroff(pdev)) { 2827 if (ahci_broken_system_poweroff(pdev)) {
2780 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; 2828 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
2781 dev_info(&pdev->dev, 2829 dev_info(&pdev->dev,
2782 "quirky BIOS, skipping spindown on poweroff\n"); 2830 "quirky BIOS, skipping spindown on poweroff\n");
2783 } 2831 }
2784 2832
2785 if (ahci_broken_suspend(pdev)) { 2833 if (ahci_broken_suspend(pdev)) {
2786 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; 2834 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
2787 dev_printk(KERN_WARNING, &pdev->dev, 2835 dev_printk(KERN_WARNING, &pdev->dev,
2788 "BIOS update required for suspend/resume\n"); 2836 "BIOS update required for suspend/resume\n");
2789 } 2837 }
2790 2838
2791 /* CAP.NP sometimes indicate the index of the last enabled 2839 /* CAP.NP sometimes indicate the index of the last enabled
2792 * port, at other times, that of the last possible port, so 2840 * port, at other times, that of the last possible port, so
2793 * determining the maximum port number requires looking at 2841 * determining the maximum port number requires looking at
2794 * both CAP.NP and port_map. 2842 * both CAP.NP and port_map.
2795 */ 2843 */
2796 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); 2844 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2797 2845
2798 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 2846 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2799 if (!host) 2847 if (!host)
2800 return -ENOMEM; 2848 return -ENOMEM;
2801 host->iomap = pcim_iomap_table(pdev); 2849 host->iomap = pcim_iomap_table(pdev);
2802 host->private_data = hpriv; 2850 host->private_data = hpriv;
2803 2851
2804 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) 2852 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
2805 host->flags |= ATA_HOST_PARALLEL_SCAN; 2853 host->flags |= ATA_HOST_PARALLEL_SCAN;
2806 else 2854 else
2807 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n"); 2855 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
2808 2856
2809 if (pi.flags & ATA_FLAG_EM) 2857 if (pi.flags & ATA_FLAG_EM)
2810 ahci_reset_em(host); 2858 ahci_reset_em(host);
2811 2859
2812 for (i = 0; i < host->n_ports; i++) { 2860 for (i = 0; i < host->n_ports; i++) {
2813 struct ata_port *ap = host->ports[i]; 2861 struct ata_port *ap = host->ports[i];
2814 2862
2815 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar"); 2863 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2816 ata_port_pbar_desc(ap, AHCI_PCI_BAR, 2864 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2817 0x100 + ap->port_no * 0x80, "port"); 2865 0x100 + ap->port_no * 0x80, "port");
2818 2866
2819 /* set initial link pm policy */ 2867 /* set initial link pm policy */
2820 ap->pm_policy = NOT_AVAILABLE; 2868 ap->pm_policy = NOT_AVAILABLE;
2821 2869
2822 /* set enclosure management message type */ 2870 /* set enclosure management message type */
2823 if (ap->flags & ATA_FLAG_EM) 2871 if (ap->flags & ATA_FLAG_EM)
2824 ap->em_message_type = ahci_em_messages; 2872 ap->em_message_type = ahci_em_messages;
2825 2873
2826 2874
2827 /* disabled/not-implemented port */ 2875 /* disabled/not-implemented port */
2828 if (!(hpriv->port_map & (1 << i))) 2876 if (!(hpriv->port_map & (1 << i)))
2829 ap->ops = &ata_dummy_port_ops; 2877 ap->ops = &ata_dummy_port_ops;
2830 } 2878 }
2831 2879
2832 /* apply workaround for ASUS P5W DH Deluxe mainboard */ 2880 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2833 ahci_p5wdh_workaround(host); 2881 ahci_p5wdh_workaround(host);
2834 2882
2835 /* initialize adapter */ 2883 /* initialize adapter */
2836 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); 2884 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
2837 if (rc) 2885 if (rc)
2838 return rc; 2886 return rc;
2839 2887
2840 rc = ahci_reset_controller(host); 2888 rc = ahci_reset_controller(host);
2841 if (rc) 2889 if (rc)
2842 return rc; 2890 return rc;
2843 2891
2844 ahci_init_controller(host); 2892 ahci_init_controller(host);
2845 ahci_print_info(host); 2893 ahci_print_info(host);
2846 2894
2847 pci_set_master(pdev); 2895 pci_set_master(pdev);
2848 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED, 2896 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2849 &ahci_sht); 2897 &ahci_sht);
2850 } 2898 }
2851 2899
2852 static int __init ahci_init(void) 2900 static int __init ahci_init(void)
2853 { 2901 {
2854 return pci_register_driver(&ahci_pci_driver); 2902 return pci_register_driver(&ahci_pci_driver);
2855 } 2903 }
2856 2904
2857 static void __exit ahci_exit(void) 2905 static void __exit ahci_exit(void)
2858 { 2906 {
2859 pci_unregister_driver(&ahci_pci_driver); 2907 pci_unregister_driver(&ahci_pci_driver);
2860 } 2908 }
2861 2909
2862 2910
2863 MODULE_AUTHOR("Jeff Garzik"); 2911 MODULE_AUTHOR("Jeff Garzik");
2864 MODULE_DESCRIPTION("AHCI SATA low-level driver"); 2912 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2865 MODULE_LICENSE("GPL"); 2913 MODULE_LICENSE("GPL");
2866 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); 2914 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2867 MODULE_VERSION(DRV_VERSION); 2915 MODULE_VERSION(DRV_VERSION);
2868 2916
2869 module_init(ahci_init); 2917 module_init(ahci_init);
2870 module_exit(ahci_exit); 2918 module_exit(ahci_exit);
drivers/firmware/dmi_scan.c
Diff comments   View file @ 58a09b3
1 #include <linux/types.h> 1 #include <linux/types.h>
2 #include <linux/string.h> 2 #include <linux/string.h>
3 #include <linux/init.h> 3 #include <linux/init.h>
4 #include <linux/module.h> 4 #include <linux/module.h>
5 #include <linux/dmi.h> 5 #include <linux/dmi.h>
6 #include <linux/efi.h> 6 #include <linux/efi.h>
7 #include <linux/bootmem.h> 7 #include <linux/bootmem.h>
8 #include <linux/slab.h> 8 #include <linux/slab.h>
9 #include <asm/dmi.h> 9 #include <asm/dmi.h>
10 10
11 /* 11 /*
12 * DMI stands for "Desktop Management Interface". It is part 12 * DMI stands for "Desktop Management Interface". It is part
13 * of and an antecedent to, SMBIOS, which stands for System 13 * of and an antecedent to, SMBIOS, which stands for System
14 * Management BIOS. See further: http://www.dmtf.org/standards 14 * Management BIOS. See further: http://www.dmtf.org/standards
15 */ 15 */
16 static char dmi_empty_string[] = " "; 16 static char dmi_empty_string[] = " ";
17 17
18 /* 18 /*
19 * Catch too early calls to dmi_check_system(): 19 * Catch too early calls to dmi_check_system():
20 */ 20 */
21 static int dmi_initialized; 21 static int dmi_initialized;
22 22
23 static const char * __init dmi_string_nosave(const struct dmi_header *dm, u8 s) 23 static const char * __init dmi_string_nosave(const struct dmi_header *dm, u8 s)
24 { 24 {
25 const u8 *bp = ((u8 *) dm) + dm->length; 25 const u8 *bp = ((u8 *) dm) + dm->length;
26 26
27 if (s) { 27 if (s) {
28 s--; 28 s--;
29 while (s > 0 && *bp) { 29 while (s > 0 && *bp) {
30 bp += strlen(bp) + 1; 30 bp += strlen(bp) + 1;
31 s--; 31 s--;
32 } 32 }
33 33
34 if (*bp != 0) { 34 if (*bp != 0) {
35 size_t len = strlen(bp)+1; 35 size_t len = strlen(bp)+1;
36 size_t cmp_len = len > 8 ? 8 : len; 36 size_t cmp_len = len > 8 ? 8 : len;
37 37
38 if (!memcmp(bp, dmi_empty_string, cmp_len)) 38 if (!memcmp(bp, dmi_empty_string, cmp_len))
39 return dmi_empty_string; 39 return dmi_empty_string;
40 return bp; 40 return bp;
41 } 41 }
42 } 42 }
43 43
44 return ""; 44 return "";
45 } 45 }
46 46
47 static char * __init dmi_string(const struct dmi_header *dm, u8 s) 47 static char * __init dmi_string(const struct dmi_header *dm, u8 s)
48 { 48 {
49 const char *bp = dmi_string_nosave(dm, s); 49 const char *bp = dmi_string_nosave(dm, s);
50 char *str; 50 char *str;
51 size_t len; 51 size_t len;
52 52
53 if (bp == dmi_empty_string) 53 if (bp == dmi_empty_string)
54 return dmi_empty_string; 54 return dmi_empty_string;
55 55
56 len = strlen(bp) + 1; 56 len = strlen(bp) + 1;
57 str = dmi_alloc(len); 57 str = dmi_alloc(len);
58 if (str != NULL) 58 if (str != NULL)
59 strcpy(str, bp); 59 strcpy(str, bp);
60 else 60 else
61 printk(KERN_ERR "dmi_string: cannot allocate %Zu bytes.\n", len); 61 printk(KERN_ERR "dmi_string: cannot allocate %Zu bytes.\n", len);
62 62
63 return str; 63 return str;
64 } 64 }
65 65
66 /* 66 /*
67 * We have to be cautious here. We have seen BIOSes with DMI pointers 67 * We have to be cautious here. We have seen BIOSes with DMI pointers
68 * pointing to completely the wrong place for example 68 * pointing to completely the wrong place for example
69 */ 69 */
70 static void dmi_table(u8 *buf, int len, int num, 70 static void dmi_table(u8 *buf, int len, int num,
71 void (*decode)(const struct dmi_header *, void *), 71 void (*decode)(const struct dmi_header *, void *),
72 void *private_data) 72 void *private_data)
73 { 73 {
74 u8 *data = buf; 74 u8 *data = buf;
75 int i = 0; 75 int i = 0;
76 76
77 /* 77 /*
78 * Stop when we see all the items the table claimed to have 78 * Stop when we see all the items the table claimed to have
79 * OR we run off the end of the table (also happens) 79 * OR we run off the end of the table (also happens)
80 */ 80 */
81 while ((i < num) && (data - buf + sizeof(struct dmi_header)) <= len) { 81 while ((i < num) && (data - buf + sizeof(struct dmi_header)) <= len) {
82 const struct dmi_header *dm = (const struct dmi_header *)data; 82 const struct dmi_header *dm = (const struct dmi_header *)data;
83 83
84 /* 84 /*
85 * We want to know the total length (formatted area and 85 * We want to know the total length (formatted area and
86 * strings) before decoding to make sure we won't run off the 86 * strings) before decoding to make sure we won't run off the
87 * table in dmi_decode or dmi_string 87 * table in dmi_decode or dmi_string
88 */ 88 */
89 data += dm->length; 89 data += dm->length;
90 while ((data - buf < len - 1) && (data[0] || data[1])) 90 while ((data - buf < len - 1) && (data[0] || data[1]))
91 data++; 91 data++;
92 if (data - buf < len - 1) 92 if (data - buf < len - 1)
93 decode(dm, private_data); 93 decode(dm, private_data);
94 data += 2; 94 data += 2;
95 i++; 95 i++;
96 } 96 }
97 } 97 }
98 98
99 static u32 dmi_base; 99 static u32 dmi_base;
100 static u16 dmi_len; 100 static u16 dmi_len;
101 static u16 dmi_num; 101 static u16 dmi_num;
102 102
103 static int __init dmi_walk_early(void (*decode)(const struct dmi_header *, 103 static int __init dmi_walk_early(void (*decode)(const struct dmi_header *,
104 void *)) 104 void *))
105 { 105 {
106 u8 *buf; 106 u8 *buf;
107 107
108 buf = dmi_ioremap(dmi_base, dmi_len); 108 buf = dmi_ioremap(dmi_base, dmi_len);
109 if (buf == NULL) 109 if (buf == NULL)
110 return -1; 110 return -1;
111 111
112 dmi_table(buf, dmi_len, dmi_num, decode, NULL); 112 dmi_table(buf, dmi_len, dmi_num, decode, NULL);
113 113
114 dmi_iounmap(buf, dmi_len); 114 dmi_iounmap(buf, dmi_len);
115 return 0; 115 return 0;
116 } 116 }
117 117
118 static int __init dmi_checksum(const u8 *buf) 118 static int __init dmi_checksum(const u8 *buf)
119 { 119 {
120 u8 sum = 0; 120 u8 sum = 0;
121 int a; 121 int a;
122 122
123 for (a = 0; a < 15; a++) 123 for (a = 0; a < 15; a++)
124 sum += buf[a]; 124 sum += buf[a];
125 125
126 return sum == 0; 126 return sum == 0;
127 } 127 }
128 128
129 static char *dmi_ident[DMI_STRING_MAX]; 129 static char *dmi_ident[DMI_STRING_MAX];
130 static LIST_HEAD(dmi_devices); 130 static LIST_HEAD(dmi_devices);
131 int dmi_available; 131 int dmi_available;
132 132
133 /* 133 /*
134 * Save a DMI string 134 * Save a DMI string
135 */ 135 */
136 static void __init dmi_save_ident(const struct dmi_header *dm, int slot, int string) 136 static void __init dmi_save_ident(const struct dmi_header *dm, int slot, int string)
137 { 137 {
138 const char *d = (const char*) dm; 138 const char *d = (const char*) dm;
139 char *p; 139 char *p;
140 140
141 if (dmi_ident[slot]) 141 if (dmi_ident[slot])
142 return; 142 return;
143 143
144 p = dmi_string(dm, d[string]); 144 p = dmi_string(dm, d[string]);
145 if (p == NULL) 145 if (p == NULL)
146 return; 146 return;
147 147
148 dmi_ident[slot] = p; 148 dmi_ident[slot] = p;
149 } 149 }
150 150
151 static void __init dmi_save_uuid(const struct dmi_header *dm, int slot, int index) 151 static void __init dmi_save_uuid(const struct dmi_header *dm, int slot, int index)
152 { 152 {
153 const u8 *d = (u8*) dm + index; 153 const u8 *d = (u8*) dm + index;
154 char *s; 154 char *s;
155 int is_ff = 1, is_00 = 1, i; 155 int is_ff = 1, is_00 = 1, i;
156 156
157 if (dmi_ident[slot]) 157 if (dmi_ident[slot])
158 return; 158 return;
159 159
160 for (i = 0; i < 16 && (is_ff || is_00); i++) { 160 for (i = 0; i < 16 && (is_ff || is_00); i++) {
161 if(d[i] != 0x00) is_ff = 0; 161 if(d[i] != 0x00) is_ff = 0;
162 if(d[i] != 0xFF) is_00 = 0; 162 if(d[i] != 0xFF) is_00 = 0;
163 } 163 }
164 164
165 if (is_ff || is_00) 165 if (is_ff || is_00)
166 return; 166 return;
167 167
168 s = dmi_alloc(16*2+4+1); 168 s = dmi_alloc(16*2+4+1);
169 if (!s) 169 if (!s)
170 return; 170 return;
171 171
172 sprintf(s, 172 sprintf(s,
173 "%02X%02X%02X%02X-%02X%02X-%02X%02X-%02X%02X-%02X%02X%02X%02X%02X%02X", 173 "%02X%02X%02X%02X-%02X%02X-%02X%02X-%02X%02X-%02X%02X%02X%02X%02X%02X",
174 d[0], d[1], d[2], d[3], d[4], d[5], d[6], d[7], 174 d[0], d[1], d[2], d[3], d[4], d[5], d[6], d[7],
175 d[8], d[9], d[10], d[11], d[12], d[13], d[14], d[15]); 175 d[8], d[9], d[10], d[11], d[12], d[13], d[14], d[15]);
176 176
177 dmi_ident[slot] = s; 177 dmi_ident[slot] = s;
178 } 178 }
179 179
180 static void __init dmi_save_type(const struct dmi_header *dm, int slot, int index) 180 static void __init dmi_save_type(const struct dmi_header *dm, int slot, int index)
181 { 181 {
182 const u8 *d = (u8*) dm + index; 182 const u8 *d = (u8*) dm + index;
183 char *s; 183 char *s;
184 184
185 if (dmi_ident[slot]) 185 if (dmi_ident[slot])
186 return; 186 return;
187 187
188 s = dmi_alloc(4); 188 s = dmi_alloc(4);
189 if (!s) 189 if (!s)
190 return; 190 return;
191 191
192 sprintf(s, "%u", *d & 0x7F); 192 sprintf(s, "%u", *d & 0x7F);
193 dmi_ident[slot] = s; 193 dmi_ident[slot] = s;
194 } 194 }
195 195
196 static void __init dmi_save_one_device(int type, const char *name) 196 static void __init dmi_save_one_device(int type, const char *name)
197 { 197 {
198 struct dmi_device *dev; 198 struct dmi_device *dev;
199 199
200 /* No duplicate device */ 200 /* No duplicate device */
201 if (dmi_find_device(type, name, NULL)) 201 if (dmi_find_device(type, name, NULL))
202 return; 202 return;
203 203
204 dev = dmi_alloc(sizeof(*dev) + strlen(name) + 1); 204 dev = dmi_alloc(sizeof(*dev) + strlen(name) + 1);
205 if (!dev) { 205 if (!dev) {
206 printk(KERN_ERR "dmi_save_one_device: out of memory.\n"); 206 printk(KERN_ERR "dmi_save_one_device: out of memory.\n");
207 return; 207 return;
208 } 208 }
209 209
210 dev->type = type; 210 dev->type = type;
211 strcpy((char *)(dev + 1), name); 211 strcpy((char *)(dev + 1), name);
212 dev->name = (char *)(dev + 1); 212 dev->name = (char *)(dev + 1);
213 dev->device_data = NULL; 213 dev->device_data = NULL;
214 list_add(&dev->list, &dmi_devices); 214 list_add(&dev->list, &dmi_devices);
215 } 215 }
216 216
217 static void __init dmi_save_devices(const struct dmi_header *dm) 217 static void __init dmi_save_devices(const struct dmi_header *dm)
218 { 218 {
219 int i, count = (dm->length - sizeof(struct dmi_header)) / 2; 219 int i, count = (dm->length - sizeof(struct dmi_header)) / 2;
220 220
221 for (i = 0; i < count; i++) { 221 for (i = 0; i < count; i++) {
222 const char *d = (char *)(dm + 1) + (i * 2); 222 const char *d = (char *)(dm + 1) + (i * 2);
223 223
224 /* Skip disabled device */ 224 /* Skip disabled device */
225 if ((*d & 0x80) == 0) 225 if ((*d & 0x80) == 0)
226 continue; 226 continue;
227 227
228 dmi_save_one_device(*d & 0x7f, dmi_string_nosave(dm, *(d + 1))); 228 dmi_save_one_device(*d & 0x7f, dmi_string_nosave(dm, *(d + 1)));
229 } 229 }
230 } 230 }
231 231
232 static void __init dmi_save_oem_strings_devices(const struct dmi_header *dm) 232 static void __init dmi_save_oem_strings_devices(const struct dmi_header *dm)
233 { 233 {
234 int i, count = *(u8 *)(dm + 1); 234 int i, count = *(u8 *)(dm + 1);
235 struct dmi_device *dev; 235 struct dmi_device *dev;
236 236
237 for (i = 1; i <= count; i++) { 237 for (i = 1; i <= count; i++) {
238 char *devname = dmi_string(dm, i); 238 char *devname = dmi_string(dm, i);
239 239
240 if (devname == dmi_empty_string) 240 if (devname == dmi_empty_string)
241 continue; 241 continue;
242 242
243 dev = dmi_alloc(sizeof(*dev)); 243 dev = dmi_alloc(sizeof(*dev));
244 if (!dev) { 244 if (!dev) {
245 printk(KERN_ERR 245 printk(KERN_ERR
246 "dmi_save_oem_strings_devices: out of memory.\n"); 246 "dmi_save_oem_strings_devices: out of memory.\n");
247 break; 247 break;
248 } 248 }
249 249
250 dev->type = DMI_DEV_TYPE_OEM_STRING; 250 dev->type = DMI_DEV_TYPE_OEM_STRING;
251 dev->name = devname; 251 dev->name = devname;
252 dev->device_data = NULL; 252 dev->device_data = NULL;
253 253
254 list_add(&dev->list, &dmi_devices); 254 list_add(&dev->list, &dmi_devices);
255 } 255 }
256 } 256 }
257 257
258 static void __init dmi_save_ipmi_device(const struct dmi_header *dm) 258 static void __init dmi_save_ipmi_device(const struct dmi_header *dm)
259 { 259 {
260 struct dmi_device *dev; 260 struct dmi_device *dev;
261 void * data; 261 void * data;
262 262
263 data = dmi_alloc(dm->length); 263 data = dmi_alloc(dm->length);
264 if (data == NULL) { 264 if (data == NULL) {
265 printk(KERN_ERR "dmi_save_ipmi_device: out of memory.\n"); 265 printk(KERN_ERR "dmi_save_ipmi_device: out of memory.\n");
266 return; 266 return;
267 } 267 }
268 268
269 memcpy(data, dm, dm->length); 269 memcpy(data, dm, dm->length);
270 270
271 dev = dmi_alloc(sizeof(*dev)); 271 dev = dmi_alloc(sizeof(*dev));
272 if (!dev) { 272 if (!dev) {
273 printk(KERN_ERR "dmi_save_ipmi_device: out of memory.\n"); 273 printk(KERN_ERR "dmi_save_ipmi_device: out of memory.\n");
274 return; 274 return;
275 } 275 }
276 276
277 dev->type = DMI_DEV_TYPE_IPMI; 277 dev->type = DMI_DEV_TYPE_IPMI;
278 dev->name = "IPMI controller"; 278 dev->name = "IPMI controller";
279 dev->device_data = data; 279 dev->device_data = data;
280 280
281 list_add_tail(&dev->list, &dmi_devices); 281 list_add_tail(&dev->list, &dmi_devices);
282 } 282 }
283 283
284 static void __init dmi_save_extended_devices(const struct dmi_header *dm) 284 static void __init dmi_save_extended_devices(const struct dmi_header *dm)
285 { 285 {
286 const u8 *d = (u8*) dm + 5; 286 const u8 *d = (u8*) dm + 5;
287 287
288 /* Skip disabled device */ 288 /* Skip disabled device */
289 if ((*d & 0x80) == 0) 289 if ((*d & 0x80) == 0)
290 return; 290 return;
291 291
292 dmi_save_one_device(*d & 0x7f, dmi_string_nosave(dm, *(d - 1))); 292 dmi_save_one_device(*d & 0x7f, dmi_string_nosave(dm, *(d - 1)));
293 } 293 }
294 294
295 /* 295 /*
296 * Process a DMI table entry. Right now all we care about are the BIOS 296 * Process a DMI table entry. Right now all we care about are the BIOS
297 * and machine entries. For 2.5 we should pull the smbus controller info 297 * and machine entries. For 2.5 we should pull the smbus controller info
298 * out of here. 298 * out of here.
299 */ 299 */
300 static void __init dmi_decode(const struct dmi_header *dm, void *dummy) 300 static void __init dmi_decode(const struct dmi_header *dm, void *dummy)
301 { 301 {
302 switch(dm->type) { 302 switch(dm->type) {
303 case 0: /* BIOS Information */ 303 case 0: /* BIOS Information */
304 dmi_save_ident(dm, DMI_BIOS_VENDOR, 4); 304 dmi_save_ident(dm, DMI_BIOS_VENDOR, 4);
305 dmi_save_ident(dm, DMI_BIOS_VERSION, 5); 305 dmi_save_ident(dm, DMI_BIOS_VERSION, 5);
306 dmi_save_ident(dm, DMI_BIOS_DATE, 8); 306 dmi_save_ident(dm, DMI_BIOS_DATE, 8);
307 break; 307 break;
308 case 1: /* System Information */ 308 case 1: /* System Information */
309 dmi_save_ident(dm, DMI_SYS_VENDOR, 4); 309 dmi_save_ident(dm, DMI_SYS_VENDOR, 4);
310 dmi_save_ident(dm, DMI_PRODUCT_NAME, 5); 310 dmi_save_ident(dm, DMI_PRODUCT_NAME, 5);
311 dmi_save_ident(dm, DMI_PRODUCT_VERSION, 6); 311 dmi_save_ident(dm, DMI_PRODUCT_VERSION, 6);
312 dmi_save_ident(dm, DMI_PRODUCT_SERIAL, 7); 312 dmi_save_ident(dm, DMI_PRODUCT_SERIAL, 7);
313 dmi_save_uuid(dm, DMI_PRODUCT_UUID, 8); 313 dmi_save_uuid(dm, DMI_PRODUCT_UUID, 8);
314 break; 314 break;
315 case 2: /* Base Board Information */ 315 case 2: /* Base Board Information */
316 dmi_save_ident(dm, DMI_BOARD_VENDOR, 4); 316 dmi_save_ident(dm, DMI_BOARD_VENDOR, 4);
317 dmi_save_ident(dm, DMI_BOARD_NAME, 5); 317 dmi_save_ident(dm, DMI_BOARD_NAME, 5);
318 dmi_save_ident(dm, DMI_BOARD_VERSION, 6); 318 dmi_save_ident(dm, DMI_BOARD_VERSION, 6);
319 dmi_save_ident(dm, DMI_BOARD_SERIAL, 7); 319 dmi_save_ident(dm, DMI_BOARD_SERIAL, 7);
320 dmi_save_ident(dm, DMI_BOARD_ASSET_TAG, 8); 320 dmi_save_ident(dm, DMI_BOARD_ASSET_TAG, 8);
321 break; 321 break;
322 case 3: /* Chassis Information */ 322 case 3: /* Chassis Information */
323 dmi_save_ident(dm, DMI_CHASSIS_VENDOR, 4); 323 dmi_save_ident(dm, DMI_CHASSIS_VENDOR, 4);
324 dmi_save_type(dm, DMI_CHASSIS_TYPE, 5); 324 dmi_save_type(dm, DMI_CHASSIS_TYPE, 5);
325 dmi_save_ident(dm, DMI_CHASSIS_VERSION, 6); 325 dmi_save_ident(dm, DMI_CHASSIS_VERSION, 6);
326 dmi_save_ident(dm, DMI_CHASSIS_SERIAL, 7); 326 dmi_save_ident(dm, DMI_CHASSIS_SERIAL, 7);
327 dmi_save_ident(dm, DMI_CHASSIS_ASSET_TAG, 8); 327 dmi_save_ident(dm, DMI_CHASSIS_ASSET_TAG, 8);
328 break; 328 break;
329 case 10: /* Onboard Devices Information */ 329 case 10: /* Onboard Devices Information */
330 dmi_save_devices(dm); 330 dmi_save_devices(dm);
331 break; 331 break;
332 case 11: /* OEM Strings */ 332 case 11: /* OEM Strings */
333 dmi_save_oem_strings_devices(dm); 333 dmi_save_oem_strings_devices(dm);
334 break; 334 break;
335 case 38: /* IPMI Device Information */ 335 case 38: /* IPMI Device Information */
336 dmi_save_ipmi_device(dm); 336 dmi_save_ipmi_device(dm);
337 break; 337 break;
338 case 41: /* Onboard Devices Extended Information */ 338 case 41: /* Onboard Devices Extended Information */
339 dmi_save_extended_devices(dm); 339 dmi_save_extended_devices(dm);
340 } 340 }
341 } 341 }
342 342
343 static int __init dmi_present(const char __iomem *p) 343 static int __init dmi_present(const char __iomem *p)
344 { 344 {
345 u8 buf[15]; 345 u8 buf[15];
346 346
347 memcpy_fromio(buf, p, 15); 347 memcpy_fromio(buf, p, 15);
348 if ((memcmp(buf, "_DMI_", 5) == 0) && dmi_checksum(buf)) { 348 if ((memcmp(buf, "_DMI_", 5) == 0) && dmi_checksum(buf)) {
349 dmi_num = (buf[13] << 8) | buf[12]; 349 dmi_num = (buf[13] << 8) | buf[12];
350 dmi_len = (buf[7] << 8) | buf[6]; 350 dmi_len = (buf[7] << 8) | buf[6];
351 dmi_base = (buf[11] << 24) | (buf[10] << 16) | 351 dmi_base = (buf[11] << 24) | (buf[10] << 16) |
352 (buf[9] << 8) | buf[8]; 352 (buf[9] << 8) | buf[8];
353 353
354 /* 354 /*
355 * DMI version 0.0 means that the real version is taken from 355 * DMI version 0.0 means that the real version is taken from
356 * the SMBIOS version, which we don't know at this point. 356 * the SMBIOS version, which we don't know at this point.
357 */ 357 */
358 if (buf[14] != 0) 358 if (buf[14] != 0)
359 printk(KERN_INFO "DMI %d.%d present.\n", 359 printk(KERN_INFO "DMI %d.%d present.\n",
360 buf[14] >> 4, buf[14] & 0xF); 360 buf[14] >> 4, buf[14] & 0xF);
361 else 361 else
362 printk(KERN_INFO "DMI present.\n"); 362 printk(KERN_INFO "DMI present.\n");
363 if (dmi_walk_early(dmi_decode) == 0) 363 if (dmi_walk_early(dmi_decode) == 0)
364 return 0; 364 return 0;
365 } 365 }
366 return 1; 366 return 1;
367 } 367 }
368 368
369 void __init dmi_scan_machine(void) 369 void __init dmi_scan_machine(void)
370 { 370 {
371 char __iomem *p, *q; 371 char __iomem *p, *q;
372 int rc; 372 int rc;
373 373
374 if (efi_enabled) { 374 if (efi_enabled) {
375 if (efi.smbios == EFI_INVALID_TABLE_ADDR) 375 if (efi.smbios == EFI_INVALID_TABLE_ADDR)
376 goto error; 376 goto error;
377 377
378 /* This is called as a core_initcall() because it isn't 378 /* This is called as a core_initcall() because it isn't
379 * needed during early boot. This also means we can 379 * needed during early boot. This also means we can
380 * iounmap the space when we're done with it. 380 * iounmap the space when we're done with it.
381 */ 381 */
382 p = dmi_ioremap(efi.smbios, 32); 382 p = dmi_ioremap(efi.smbios, 32);
383 if (p == NULL) 383 if (p == NULL)
384 goto error; 384 goto error;
385 385
386 rc = dmi_present(p + 0x10); /* offset of _DMI_ string */ 386 rc = dmi_present(p + 0x10); /* offset of _DMI_ string */
387 dmi_iounmap(p, 32); 387 dmi_iounmap(p, 32);
388 if (!rc) { 388 if (!rc) {
389 dmi_available = 1; 389 dmi_available = 1;
390 goto out; 390 goto out;
391 } 391 }
392 } 392 }
393 else { 393 else {
394 /* 394 /*
395 * no iounmap() for that ioremap(); it would be a no-op, but 395 * no iounmap() for that ioremap(); it would be a no-op, but
396 * it's so early in setup that sucker gets confused into doing 396 * it's so early in setup that sucker gets confused into doing
397 * what it shouldn't if we actually call it. 397 * what it shouldn't if we actually call it.
398 */ 398 */
399 p = dmi_ioremap(0xF0000, 0x10000); 399 p = dmi_ioremap(0xF0000, 0x10000);
400 if (p == NULL) 400 if (p == NULL)
401 goto error; 401 goto error;
402 402
403 for (q = p; q < p + 0x10000; q += 16) { 403 for (q = p; q < p + 0x10000; q += 16) {
404 rc = dmi_present(q); 404 rc = dmi_present(q);
405 if (!rc) { 405 if (!rc) {
406 dmi_available = 1; 406 dmi_available = 1;
407 dmi_iounmap(p, 0x10000); 407 dmi_iounmap(p, 0x10000);
408 goto out; 408 goto out;
409 } 409 }
410 } 410 }
411 dmi_iounmap(p, 0x10000); 411 dmi_iounmap(p, 0x10000);
412 } 412 }
413 error: 413 error:
414 printk(KERN_INFO "DMI not present or invalid.\n"); 414 printk(KERN_INFO "DMI not present or invalid.\n");
415 out: 415 out:
416 dmi_initialized = 1; 416 dmi_initialized = 1;
417 } 417 }
418 418
419 /** 419 /**
420 * dmi_matches - check if dmi_system_id structure matches system DMI data 420 * dmi_matches - check if dmi_system_id structure matches system DMI data
421 * @dmi: pointer to the dmi_system_id structure to check 421 * @dmi: pointer to the dmi_system_id structure to check
422 */ 422 */
423 static bool dmi_matches(const struct dmi_system_id *dmi) 423 static bool dmi_matches(const struct dmi_system_id *dmi)
424 { 424 {
425 int i; 425 int i;
426 426
427 WARN(!dmi_initialized, KERN_ERR "dmi check: not initialized yet.\n"); 427 WARN(!dmi_initialized, KERN_ERR "dmi check: not initialized yet.\n");
428 428
429 for (i = 0; i < ARRAY_SIZE(dmi->matches); i++) { 429 for (i = 0; i < ARRAY_SIZE(dmi->matches); i++) {
430 int s = dmi->matches[i].slot; 430 int s = dmi->matches[i].slot;
431 if (s == DMI_NONE) 431 if (s == DMI_NONE)
432 continue; 432 continue;
433 if (dmi_ident[s] 433 if (dmi_ident[s]
434 && strstr(dmi_ident[s], dmi->matches[i].substr)) 434 && strstr(dmi_ident[s], dmi->matches[i].substr))
435 continue; 435 continue;
436 /* No match */ 436 /* No match */
437 return false; 437 return false;
438 } 438 }
439 return true; 439 return true;
440 } 440 }
441 441
442 /** 442 /**
443 * dmi_check_system - check system DMI data 443 * dmi_check_system - check system DMI data
444 * @list: array of dmi_system_id structures to match against 444 * @list: array of dmi_system_id structures to match against
445 * All non-null elements of the list must match 445 * All non-null elements of the list must match
446 * their slot's (field index's) data (i.e., each 446 * their slot's (field index's) data (i.e., each
447 * list string must be a substring of the specified 447 * list string must be a substring of the specified
448 * DMI slot's string data) to be considered a 448 * DMI slot's string data) to be considered a
449 * successful match. 449 * successful match.
450 * 450 *
451 * Walk the blacklist table running matching functions until someone 451 * Walk the blacklist table running matching functions until someone
452 * returns non zero or we hit the end. Callback function is called for 452 * returns non zero or we hit the end. Callback function is called for
453 * each successful match. Returns the number of matches. 453 * each successful match. Returns the number of matches.
454 */ 454 */
455 int dmi_check_system(const struct dmi_system_id *list) 455 int dmi_check_system(const struct dmi_system_id *list)
456 { 456 {
457 int count = 0; 457 int count = 0;
458 const struct dmi_system_id *d; 458 const struct dmi_system_id *d;
459 459
460 for (d = list; d->ident; d++) 460 for (d = list; d->ident; d++)
461 if (dmi_matches(d)) { 461 if (dmi_matches(d)) {
462 count++; 462 count++;
463 if (d->callback && d->callback(d)) 463 if (d->callback && d->callback(d))
464 break; 464 break;
465 } 465 }
466 466
467 return count; 467 return count;
468 } 468 }
469 EXPORT_SYMBOL(dmi_check_system); 469 EXPORT_SYMBOL(dmi_check_system);
470 470
471 /** 471 /**
472 * dmi_first_match - find dmi_system_id structure matching system DMI data 472 * dmi_first_match - find dmi_system_id structure matching system DMI data
473 * @list: array of dmi_system_id structures to match against 473 * @list: array of dmi_system_id structures to match against
474 * All non-null elements of the list must match 474 * All non-null elements of the list must match
475 * their slot's (field index's) data (i.e., each 475 * their slot's (field index's) data (i.e., each
476 * list string must be a substring of the specified 476 * list string must be a substring of the specified
477 * DMI slot's string data) to be considered a 477 * DMI slot's string data) to be considered a
478 * successful match. 478 * successful match.
479 * 479 *
480 * Walk the blacklist table until the first match is found. Return the 480 * Walk the blacklist table until the first match is found. Return the
481 * pointer to the matching entry or NULL if there's no match. 481 * pointer to the matching entry or NULL if there's no match.
482 */ 482 */
483 const struct dmi_system_id *dmi_first_match(const struct dmi_system_id *list) 483 const struct dmi_system_id *dmi_first_match(const struct dmi_system_id *list)
484 { 484 {
485 const struct dmi_system_id *d; 485 const struct dmi_system_id *d;
486 486
487 for (d = list; d->ident; d++) 487 for (d = list; d->ident; d++)
488 if (dmi_matches(d)) 488 if (dmi_matches(d))
489 return d; 489 return d;
490 490
491 return NULL; 491 return NULL;
492 } 492 }
493 EXPORT_SYMBOL(dmi_first_match); 493 EXPORT_SYMBOL(dmi_first_match);
494 494
495 /** 495 /**
496 * dmi_get_system_info - return DMI data value 496 * dmi_get_system_info - return DMI data value
497 * @field: data index (see enum dmi_field) 497 * @field: data index (see enum dmi_field)
498 * 498 *
499 * Returns one DMI data value, can be used to perform 499 * Returns one DMI data value, can be used to perform
500 * complex DMI data checks. 500 * complex DMI data checks.
501 */ 501 */
502 const char *dmi_get_system_info(int field) 502 const char *dmi_get_system_info(int field)
503 { 503 {
504 return dmi_ident[field]; 504 return dmi_ident[field];
505 } 505 }
506 EXPORT_SYMBOL(dmi_get_system_info); 506 EXPORT_SYMBOL(dmi_get_system_info);
507 507
508 /** 508 /**
509 * dmi_name_in_serial - Check if string is in the DMI product serial information 509 * dmi_name_in_serial - Check if string is in the DMI product serial information
510 * @str: string to check for 510 * @str: string to check for
511 */ 511 */
512 int dmi_name_in_serial(const char *str) 512 int dmi_name_in_serial(const char *str)
513 { 513 {
514 int f = DMI_PRODUCT_SERIAL; 514 int f = DMI_PRODUCT_SERIAL;
515 if (dmi_ident[f] && strstr(dmi_ident[f], str)) 515 if (dmi_ident[f] && strstr(dmi_ident[f], str))
516 return 1; 516 return 1;
517 return 0; 517 return 0;
518 } 518 }
519 519
520 /** 520 /**
521 * dmi_name_in_vendors - Check if string is anywhere in the DMI vendor information. 521 * dmi_name_in_vendors - Check if string is anywhere in the DMI vendor information.
522 * @str: Case sensitive Name 522 * @str: Case sensitive Name
523 */ 523 */
524 int dmi_name_in_vendors(const char *str) 524 int dmi_name_in_vendors(const char *str)
525 { 525 {
526 static int fields[] = { DMI_BIOS_VENDOR, DMI_BIOS_VERSION, DMI_SYS_VENDOR, 526 static int fields[] = { DMI_BIOS_VENDOR, DMI_BIOS_VERSION, DMI_SYS_VENDOR,
527 DMI_PRODUCT_NAME, DMI_PRODUCT_VERSION, DMI_BOARD_VENDOR, 527 DMI_PRODUCT_NAME, DMI_PRODUCT_VERSION, DMI_BOARD_VENDOR,
528 DMI_BOARD_NAME, DMI_BOARD_VERSION, DMI_NONE }; 528 DMI_BOARD_NAME, DMI_BOARD_VERSION, DMI_NONE };
529 int i; 529 int i;
530 for (i = 0; fields[i] != DMI_NONE; i++) { 530 for (i = 0; fields[i] != DMI_NONE; i++) {
531 int f = fields[i]; 531 int f = fields[i];
532 if (dmi_ident[f] && strstr(dmi_ident[f], str)) 532 if (dmi_ident[f] && strstr(dmi_ident[f], str))
533 return 1; 533 return 1;
534 } 534 }
535 return 0; 535 return 0;
536 } 536 }
537 EXPORT_SYMBOL(dmi_name_in_vendors); 537 EXPORT_SYMBOL(dmi_name_in_vendors);
538 538
539 /** 539 /**
540 * dmi_find_device - find onboard device by type/name 540 * dmi_find_device - find onboard device by type/name
541 * @type: device type or %DMI_DEV_TYPE_ANY to match all device types 541 * @type: device type or %DMI_DEV_TYPE_ANY to match all device types
542 * @name: device name string or %NULL to match all 542 * @name: device name string or %NULL to match all
543 * @from: previous device found in search, or %NULL for new search. 543 * @from: previous device found in search, or %NULL for new search.
544 * 544 *
545 * Iterates through the list of known onboard devices. If a device is 545 * Iterates through the list of known onboard devices. If a device is
546 * found with a matching @vendor and @device, a pointer to its device 546 * found with a matching @vendor and @device, a pointer to its device
547 * structure is returned. Otherwise, %NULL is returned. 547 * structure is returned. Otherwise, %NULL is returned.
548 * A new search is initiated by passing %NULL as the @from argument. 548 * A new search is initiated by passing %NULL as the @from argument.
549 * If @from is not %NULL, searches continue from next device. 549 * If @from is not %NULL, searches continue from next device.
550 */ 550 */
551 const struct dmi_device * dmi_find_device(int type, const char *name, 551 const struct dmi_device * dmi_find_device(int type, const char *name,
552 const struct dmi_device *from) 552 const struct dmi_device *from)
553 { 553 {
554 const struct list_head *head = from ? &from->list : &dmi_devices; 554 const struct list_head *head = from ? &from->list : &dmi_devices;
555 struct list_head *d; 555 struct list_head *d;
556 556
557 for(d = head->next; d != &dmi_devices; d = d->next) { 557 for(d = head->next; d != &dmi_devices; d = d->next) {
558 const struct dmi_device *dev = 558 const struct dmi_device *dev =
559 list_entry(d, struct dmi_device, list); 559 list_entry(d, struct dmi_device, list);
560 560
561 if (((type == DMI_DEV_TYPE_ANY) || (dev->type == type)) && 561 if (((type == DMI_DEV_TYPE_ANY) || (dev->type == type)) &&
562 ((name == NULL) || (strcmp(dev->name, name) == 0))) 562 ((name == NULL) || (strcmp(dev->name, name) == 0)))
563 return dev; 563 return dev;
564 } 564 }
565 565
566 return NULL; 566 return NULL;
567 } 567 }
568 EXPORT_SYMBOL(dmi_find_device); 568 EXPORT_SYMBOL(dmi_find_device);
569 569
570 /** 570 /**
571 * dmi_get_year - Return year of a DMI date 571 * dmi_get_year - Return year of a DMI date
572 * @field: data index (like dmi_get_system_info) 572 * @field: data index (like dmi_get_system_info)
573 * 573 *
574 * Returns -1 when the field doesn't exist. 0 when it is broken. 574 * Returns -1 when the field doesn't exist. 0 when it is broken.
575 */ 575 */
576 int dmi_get_year(int field) 576 int dmi_get_year(int field)
577 { 577 {
578 int year; 578 int year;
579 const char *s = dmi_get_system_info(field); 579 const char *s = dmi_get_system_info(field);
580 580
581 if (!s) 581 if (!s)
582 return -1; 582 return -1;
583 if (*s == '\0') 583 if (*s == '\0')
584 return 0; 584 return 0;
585 s = strrchr(s, '/'); 585 s = strrchr(s, '/');
586 if (!s) 586 if (!s)
587 return 0; 587 return 0;
588 588
589 s += 1; 589 s += 1;
590 year = simple_strtoul(s, NULL, 0); 590 year = simple_strtoul(s, NULL, 0);
591 if (year && year < 100) { /* 2-digit year */ 591 if (year && year < 100) { /* 2-digit year */
592 year += 1900; 592 year += 1900;
593 if (year < 1996) /* no dates < spec 1.0 */ 593 if (year < 1996) /* no dates < spec 1.0 */
594 year += 100; 594 year += 100;
595 } 595 }
596 596
597 return year; 597 return year;
598 } 598 }
599 EXPORT_SYMBOL(dmi_get_year);
599 600
600 /** 601 /**
601 * dmi_walk - Walk the DMI table and get called back for every record 602 * dmi_walk - Walk the DMI table and get called back for every record
602 * @decode: Callback function 603 * @decode: Callback function
603 * @private_data: Private data to be passed to the callback function 604 * @private_data: Private data to be passed to the callback function
604 * 605 *
605 * Returns -1 when the DMI table can't be reached, 0 on success. 606 * Returns -1 when the DMI table can't be reached, 0 on success.
606 */ 607 */
607 int dmi_walk(void (*decode)(const struct dmi_header *, void *), 608 int dmi_walk(void (*decode)(const struct dmi_header *, void *),
608 void *private_data) 609 void *private_data)
609 { 610 {
610 u8 *buf; 611 u8 *buf;
611 612
612 if (!dmi_available) 613 if (!dmi_available)
613 return -1; 614 return -1;
614 615
615 buf = ioremap(dmi_base, dmi_len); 616 buf = ioremap(dmi_base, dmi_len);
616 if (buf == NULL) 617 if (buf == NULL)
617 return -1; 618 return -1;
618 619
619 dmi_table(buf, dmi_len, dmi_num, decode, private_data); 620 dmi_table(buf, dmi_len, dmi_num, decode, private_data);
620 621
621 iounmap(buf); 622 iounmap(buf);
622 return 0; 623 return 0;
623 } 624 }
624 EXPORT_SYMBOL_GPL(dmi_walk); 625 EXPORT_SYMBOL_GPL(dmi_walk);
625 626
626 /** 627 /**
627 * dmi_match - compare a string to the dmi field (if exists) 628 * dmi_match - compare a string to the dmi field (if exists)
628 * @f: DMI field identifier 629 * @f: DMI field identifier
629 * @str: string to compare the DMI field to 630 * @str: string to compare the DMI field to
630 * 631 *
631 * Returns true if the requested field equals to the str (including NULL). 632 * Returns true if the requested field equals to the str (including NULL).
632 */ 633 */
633 bool dmi_match(enum dmi_field f, const char *str) 634 bool dmi_match(enum dmi_field f, const char *str)
634 { 635 {
635 const char *info = dmi_get_system_info(f); 636 const char *info = dmi_get_system_info(f);
636 637
637 if (info == NULL || str == NULL) 638 if (info == NULL || str == NULL)
638 return info == str; 639 return info == str;
639 640
640 return !strcmp(info, str); 641 return !strcmp(info, str);
641 } 642 }
642 EXPORT_SYMBOL_GPL(dmi_match); 643 EXPORT_SYMBOL_GPL(dmi_match);
643 644