Doug / smarc-fsl-linux-kernel

1

/* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $

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/* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $

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* sungem.c: Sun GEM ethernet driver.

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* sungem.c: Sun GEM ethernet driver.

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*

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*

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*

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*

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* Support for Apple GMAC and assorted PHYs, WOL, Power Management

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* Support for Apple GMAC and assorted PHYs, WOL, Power Management

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*

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*

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* NAPI and NETPOLL support

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* NAPI and NETPOLL support

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*

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*

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*/

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*/

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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

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#include <linux/module.h>

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#include <linux/module.h>

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#include <linux/kernel.h>

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#include <linux/kernel.h>

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#include <linux/types.h>

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#include <linux/types.h>

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#include <linux/fcntl.h>

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#include <linux/fcntl.h>

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#include <linux/interrupt.h>

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#include <linux/interrupt.h>

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#include <linux/ioport.h>

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#include <linux/ioport.h>

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#include <linux/in.h>

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#include <linux/in.h>

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#include <linux/sched.h>

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#include <linux/sched.h>

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#include <linux/string.h>

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#include <linux/string.h>

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#include <linux/delay.h>

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#include <linux/delay.h>

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#include <linux/init.h>

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#include <linux/init.h>

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#include <linux/errno.h>

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#include <linux/errno.h>

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#include <linux/pci.h>

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#include <linux/pci.h>

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#include <linux/dma-mapping.h>

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#include <linux/dma-mapping.h>

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#include <linux/netdevice.h>

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#include <linux/netdevice.h>

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#include <linux/etherdevice.h>

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#include <linux/etherdevice.h>

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#include <linux/skbuff.h>

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#include <linux/skbuff.h>

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#include <linux/mii.h>

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#include <linux/mii.h>

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#include <linux/ethtool.h>

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#include <linux/ethtool.h>

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#include <linux/crc32.h>

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#include <linux/crc32.h>

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#include <linux/random.h>

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#include <linux/random.h>

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#include <linux/workqueue.h>

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#include <linux/workqueue.h>

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#include <linux/if_vlan.h>

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#include <linux/if_vlan.h>

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#include <linux/bitops.h>

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#include <linux/bitops.h>

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#include <linux/mm.h>

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#include <linux/mm.h>

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#include <linux/gfp.h>

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#include <linux/gfp.h>

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#include <asm/system.h>

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#include <asm/system.h>

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#include <asm/io.h>

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#include <asm/io.h>

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#include <asm/byteorder.h>

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#include <asm/byteorder.h>

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#include <asm/uaccess.h>

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#include <asm/uaccess.h>

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#include <asm/irq.h>

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#include <asm/irq.h>

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#include <asm/prom.h>

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#ifdef CONFIG_SPARC

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#ifdef CONFIG_SPARC

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#include <asm/idprom.h>

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#include <asm/idprom.h>

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#include <asm/prom.h>

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#endif

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#endif

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#ifdef CONFIG_PPC_PMAC

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#ifdef CONFIG_PPC_PMAC

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#include <asm/pci-bridge.h>

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#include <asm/pci-bridge.h>

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#include <asm/prom.h>

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#include <asm/machdep.h>

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#include <asm/machdep.h>

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#include <asm/pmac_feature.h>

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#include <asm/pmac_feature.h>

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#endif

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#endif

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#include "sungem_phy.h"

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#include "sungem_phy.h"

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#include "sungem.h"

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#include "sungem.h"

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/* Stripping FCS is causing problems, disabled for now */

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/* Stripping FCS is causing problems, disabled for now */

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#undef STRIP_FCS

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#undef STRIP_FCS

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#define DEFAULT_MSG (NETIF_MSG_DRV | \

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#define DEFAULT_MSG (NETIF_MSG_DRV | \

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NETIF_MSG_PROBE | \

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NETIF_MSG_PROBE | \

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NETIF_MSG_LINK)

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NETIF_MSG_LINK)

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#define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \

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#define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \

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SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \

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SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \

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SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | \

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SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | \

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SUPPORTED_Pause | SUPPORTED_Autoneg)

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SUPPORTED_Pause | SUPPORTED_Autoneg)

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#define DRV_NAME "sungem"

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#define DRV_NAME "sungem"

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#define DRV_VERSION "1.0"

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#define DRV_VERSION "1.0"

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#define DRV_AUTHOR "David S. Miller <davem@redhat.com>"

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#define DRV_AUTHOR "David S. Miller <davem@redhat.com>"

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static char version[] __devinitdata =

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static char version[] __devinitdata =

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DRV_NAME ".c:v" DRV_VERSION " " DRV_AUTHOR "\n";

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DRV_NAME ".c:v" DRV_VERSION " " DRV_AUTHOR "\n";

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MODULE_AUTHOR(DRV_AUTHOR);

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MODULE_AUTHOR(DRV_AUTHOR);

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MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");

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MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");

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MODULE_LICENSE("GPL");

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MODULE_LICENSE("GPL");

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#define GEM_MODULE_NAME "gem"

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#define GEM_MODULE_NAME "gem"

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static DEFINE_PCI_DEVICE_TABLE(gem_pci_tbl) = {

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static DEFINE_PCI_DEVICE_TABLE(gem_pci_tbl) = {

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{ PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,

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{ PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,

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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

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/* These models only differ from the original GEM in

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/* These models only differ from the original GEM in

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* that their tx/rx fifos are of a different size and

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* that their tx/rx fifos are of a different size and

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* they only support 10/100 speeds. -DaveM

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* they only support 10/100 speeds. -DaveM

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*

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*

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* Apple's GMAC does support gigabit on machines with

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* Apple's GMAC does support gigabit on machines with

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* the BCM54xx PHYs. -BenH

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* the BCM54xx PHYs. -BenH

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*/

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*/

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{ PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,

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{ PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,

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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

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{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,

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{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,

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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

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{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,

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{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,

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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

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{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,

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{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,

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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

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{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC,

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{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC,

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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

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{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_SUNGEM,

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{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_SUNGEM,

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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

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{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_GMAC,

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{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_GMAC,

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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

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{0, }

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{0, }

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};

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};

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MODULE_DEVICE_TABLE(pci, gem_pci_tbl);

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MODULE_DEVICE_TABLE(pci, gem_pci_tbl);

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static u16 __phy_read(struct gem *gp, int phy_addr, int reg)

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static u16 __phy_read(struct gem *gp, int phy_addr, int reg)

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{

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{

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u32 cmd;

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u32 cmd;

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int limit = 10000;

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int limit = 10000;

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cmd = (1 << 30);

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cmd = (1 << 30);

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cmd |= (2 << 28);

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cmd |= (2 << 28);

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cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;

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cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;

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cmd |= (reg << 18) & MIF_FRAME_REGAD;

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cmd |= (reg << 18) & MIF_FRAME_REGAD;

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cmd |= (MIF_FRAME_TAMSB);

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cmd |= (MIF_FRAME_TAMSB);

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writel(cmd, gp->regs + MIF_FRAME);

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writel(cmd, gp->regs + MIF_FRAME);

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while (--limit) {

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while (--limit) {

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cmd = readl(gp->regs + MIF_FRAME);

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cmd = readl(gp->regs + MIF_FRAME);

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if (cmd & MIF_FRAME_TALSB)

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if (cmd & MIF_FRAME_TALSB)

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break;

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break;

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udelay(10);

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udelay(10);

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}

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}

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if (!limit)

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if (!limit)

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cmd = 0xffff;

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cmd = 0xffff;

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return cmd & MIF_FRAME_DATA;

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return cmd & MIF_FRAME_DATA;

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}

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}

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static inline int _phy_read(struct net_device *dev, int mii_id, int reg)

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static inline int _phy_read(struct net_device *dev, int mii_id, int reg)

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{

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{

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struct gem *gp = netdev_priv(dev);

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struct gem *gp = netdev_priv(dev);

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return __phy_read(gp, mii_id, reg);

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return __phy_read(gp, mii_id, reg);

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}

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}

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static inline u16 phy_read(struct gem *gp, int reg)

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static inline u16 phy_read(struct gem *gp, int reg)

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{

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{

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return __phy_read(gp, gp->mii_phy_addr, reg);

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return __phy_read(gp, gp->mii_phy_addr, reg);

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}

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}

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static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val)

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static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val)

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{

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{

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u32 cmd;

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u32 cmd;

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int limit = 10000;

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int limit = 10000;

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cmd = (1 << 30);

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cmd = (1 << 30);

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cmd |= (1 << 28);

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cmd |= (1 << 28);

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cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;

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cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;

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cmd |= (reg << 18) & MIF_FRAME_REGAD;

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cmd |= (reg << 18) & MIF_FRAME_REGAD;

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cmd |= (MIF_FRAME_TAMSB);

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cmd |= (MIF_FRAME_TAMSB);

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cmd |= (val & MIF_FRAME_DATA);

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cmd |= (val & MIF_FRAME_DATA);

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writel(cmd, gp->regs + MIF_FRAME);

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writel(cmd, gp->regs + MIF_FRAME);

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while (limit--) {

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while (limit--) {

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cmd = readl(gp->regs + MIF_FRAME);

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cmd = readl(gp->regs + MIF_FRAME);

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if (cmd & MIF_FRAME_TALSB)

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if (cmd & MIF_FRAME_TALSB)

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break;

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break;

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udelay(10);

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udelay(10);

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}

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}

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}

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}

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static inline void _phy_write(struct net_device *dev, int mii_id, int reg, int val)

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static inline void _phy_write(struct net_device *dev, int mii_id, int reg, int val)

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{

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{

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struct gem *gp = netdev_priv(dev);

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struct gem *gp = netdev_priv(dev);

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__phy_write(gp, mii_id, reg, val & 0xffff);

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__phy_write(gp, mii_id, reg, val & 0xffff);

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}

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}

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static inline void phy_write(struct gem *gp, int reg, u16 val)

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static inline void phy_write(struct gem *gp, int reg, u16 val)

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{

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{

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__phy_write(gp, gp->mii_phy_addr, reg, val);

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__phy_write(gp, gp->mii_phy_addr, reg, val);

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}

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}

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static inline void gem_enable_ints(struct gem *gp)

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static inline void gem_enable_ints(struct gem *gp)

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{

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{

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/* Enable all interrupts but TXDONE */

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/* Enable all interrupts but TXDONE */

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writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);

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writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);

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}

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}

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static inline void gem_disable_ints(struct gem *gp)

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static inline void gem_disable_ints(struct gem *gp)

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{

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{

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/* Disable all interrupts, including TXDONE */

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/* Disable all interrupts, including TXDONE */

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writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK);

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writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK);

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(void)readl(gp->regs + GREG_IMASK); /* write posting */

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(void)readl(gp->regs + GREG_IMASK); /* write posting */

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}

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}

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static void gem_get_cell(struct gem *gp)

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static void gem_get_cell(struct gem *gp)

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{

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{

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BUG_ON(gp->cell_enabled < 0);

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BUG_ON(gp->cell_enabled < 0);

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gp->cell_enabled++;

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gp->cell_enabled++;

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#ifdef CONFIG_PPC_PMAC

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#ifdef CONFIG_PPC_PMAC

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if (gp->cell_enabled == 1) {

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if (gp->cell_enabled == 1) {

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mb();

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mb();

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pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);

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pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);

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udelay(10);

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udelay(10);

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}

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}

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#endif /* CONFIG_PPC_PMAC */

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#endif /* CONFIG_PPC_PMAC */

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}

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}

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/* Turn off the chip's clock */

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/* Turn off the chip's clock */

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static void gem_put_cell(struct gem *gp)

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static void gem_put_cell(struct gem *gp)

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{

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{

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BUG_ON(gp->cell_enabled <= 0);

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BUG_ON(gp->cell_enabled <= 0);

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gp->cell_enabled--;

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gp->cell_enabled--;

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#ifdef CONFIG_PPC_PMAC

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#ifdef CONFIG_PPC_PMAC

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if (gp->cell_enabled == 0) {

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if (gp->cell_enabled == 0) {

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mb();

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mb();

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pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);

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pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);

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udelay(10);

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udelay(10);

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}

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}

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#endif /* CONFIG_PPC_PMAC */

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#endif /* CONFIG_PPC_PMAC */

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}

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}

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static inline void gem_netif_stop(struct gem *gp)

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static inline void gem_netif_stop(struct gem *gp)

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{

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{

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gp->dev->trans_start = jiffies; /* prevent tx timeout */

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gp->dev->trans_start = jiffies; /* prevent tx timeout */

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napi_disable(&gp->napi);

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napi_disable(&gp->napi);

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netif_tx_disable(gp->dev);

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netif_tx_disable(gp->dev);

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}

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}

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static inline void gem_netif_start(struct gem *gp)

237

static inline void gem_netif_start(struct gem *gp)

237

{

238

{

238

/* NOTE: unconditional netif_wake_queue is only

239

/* NOTE: unconditional netif_wake_queue is only

239

* appropriate so long as all callers are assured to

240

* appropriate so long as all callers are assured to

240

* have free tx slots.

241

* have free tx slots.

241

*/

242

*/

242

netif_wake_queue(gp->dev);

243

netif_wake_queue(gp->dev);

243

napi_enable(&gp->napi);

244

napi_enable(&gp->napi);

244

}

245

}

245

246

static void gem_schedule_reset(struct gem *gp)

247

static void gem_schedule_reset(struct gem *gp)

247

{

248

{

248

gp->reset_task_pending = 1;

249

gp->reset_task_pending = 1;

249

schedule_work(&gp->reset_task);

250

schedule_work(&gp->reset_task);

250

}

251

}

251

252

static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)

253

static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)

253

{

254

{

254

if (netif_msg_intr(gp))

255

if (netif_msg_intr(gp))

255

printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);

256

printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);

256

}

257

}

257

258

static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)

259

static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)

259

{

260

{

260

u32 pcs_istat = readl(gp->regs + PCS_ISTAT);

261

u32 pcs_istat = readl(gp->regs + PCS_ISTAT);

261

u32 pcs_miistat;

262

u32 pcs_miistat;

262

263

if (netif_msg_intr(gp))

264

if (netif_msg_intr(gp))

264

printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n",

265

printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n",

265

gp->dev->name, pcs_istat);

266

gp->dev->name, pcs_istat);

266

267

if (!(pcs_istat & PCS_ISTAT_LSC)) {

268

if (!(pcs_istat & PCS_ISTAT_LSC)) {

268

netdev_err(dev, "PCS irq but no link status change???\n");

269

netdev_err(dev, "PCS irq but no link status change???\n");

269

return 0;

270

return 0;

270

}

271

}

271

272

/* The link status bit latches on zero, so you must

273

/* The link status bit latches on zero, so you must

273

* read it twice in such a case to see a transition

274

* read it twice in such a case to see a transition

274

* to the link being up.

275

* to the link being up.

275

*/

276

*/

276

pcs_miistat = readl(gp->regs + PCS_MIISTAT);

277

pcs_miistat = readl(gp->regs + PCS_MIISTAT);

277

if (!(pcs_miistat & PCS_MIISTAT_LS))

278

if (!(pcs_miistat & PCS_MIISTAT_LS))

278

pcs_miistat |=

279

pcs_miistat |=

279

(readl(gp->regs + PCS_MIISTAT) &

280

(readl(gp->regs + PCS_MIISTAT) &

280

PCS_MIISTAT_LS);

281

PCS_MIISTAT_LS);

281

282

if (pcs_miistat & PCS_MIISTAT_ANC) {

283

if (pcs_miistat & PCS_MIISTAT_ANC) {

283

/* The remote-fault indication is only valid

284

/* The remote-fault indication is only valid

284

* when autoneg has completed.

285

* when autoneg has completed.

285

*/

286

*/

286

if (pcs_miistat & PCS_MIISTAT_RF)

287

if (pcs_miistat & PCS_MIISTAT_RF)

287

netdev_info(dev, "PCS AutoNEG complete, RemoteFault\n");

288

netdev_info(dev, "PCS AutoNEG complete, RemoteFault\n");

288

else

289

else

289

netdev_info(dev, "PCS AutoNEG complete\n");

290

netdev_info(dev, "PCS AutoNEG complete\n");

290

}

291

}

291

292

if (pcs_miistat & PCS_MIISTAT_LS) {

293

if (pcs_miistat & PCS_MIISTAT_LS) {

293

netdev_info(dev, "PCS link is now up\n");

294

netdev_info(dev, "PCS link is now up\n");

294

netif_carrier_on(gp->dev);

295

netif_carrier_on(gp->dev);

295

} else {

296

} else {

296

netdev_info(dev, "PCS link is now down\n");

297

netdev_info(dev, "PCS link is now down\n");

297

netif_carrier_off(gp->dev);

298

netif_carrier_off(gp->dev);

298

/* If this happens and the link timer is not running,

299

/* If this happens and the link timer is not running,

299

* reset so we re-negotiate.

300

* reset so we re-negotiate.

300

*/

301

*/

301

if (!timer_pending(&gp->link_timer))

302

if (!timer_pending(&gp->link_timer))

302

return 1;

303

return 1;

303

}

304

}

304

305

return 0;

306

return 0;

306

}

307

}

307

308

static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)

309

static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)

309

{

310

{

310

u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);

311

u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);

311

312

if (netif_msg_intr(gp))

313

if (netif_msg_intr(gp))

313

printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",

314

printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",

314

gp->dev->name, txmac_stat);

315

gp->dev->name, txmac_stat);

315

316

/* Defer timer expiration is quite normal,

317

/* Defer timer expiration is quite normal,

317

* don't even log the event.

318

* don't even log the event.

318

*/

319

*/

319

if ((txmac_stat & MAC_TXSTAT_DTE) &&

320

if ((txmac_stat & MAC_TXSTAT_DTE) &&

320

!(txmac_stat & ~MAC_TXSTAT_DTE))

321

!(txmac_stat & ~MAC_TXSTAT_DTE))

321

return 0;

322

return 0;

322

323

if (txmac_stat & MAC_TXSTAT_URUN) {

324

if (txmac_stat & MAC_TXSTAT_URUN) {

324

netdev_err(dev, "TX MAC xmit underrun\n");

325

netdev_err(dev, "TX MAC xmit underrun\n");

325

dev->stats.tx_fifo_errors++;

326

dev->stats.tx_fifo_errors++;

326

}

327

}

327

328

if (txmac_stat & MAC_TXSTAT_MPE) {

329

if (txmac_stat & MAC_TXSTAT_MPE) {

329

netdev_err(dev, "TX MAC max packet size error\n");

330

netdev_err(dev, "TX MAC max packet size error\n");

330

dev->stats.tx_errors++;

331

dev->stats.tx_errors++;

331

}

332

}

332

333

/* The rest are all cases of one of the 16-bit TX

334

/* The rest are all cases of one of the 16-bit TX

334

* counters expiring.

335

* counters expiring.

335

*/

336

*/

336

if (txmac_stat & MAC_TXSTAT_NCE)

337

if (txmac_stat & MAC_TXSTAT_NCE)

337

dev->stats.collisions += 0x10000;

338

dev->stats.collisions += 0x10000;

338

339

if (txmac_stat & MAC_TXSTAT_ECE) {

340

if (txmac_stat & MAC_TXSTAT_ECE) {

340

dev->stats.tx_aborted_errors += 0x10000;

341

dev->stats.tx_aborted_errors += 0x10000;

341

dev->stats.collisions += 0x10000;

342

dev->stats.collisions += 0x10000;

342

}

343

}

343

344

if (txmac_stat & MAC_TXSTAT_LCE) {

345

if (txmac_stat & MAC_TXSTAT_LCE) {

345

dev->stats.tx_aborted_errors += 0x10000;

346

dev->stats.tx_aborted_errors += 0x10000;

346

dev->stats.collisions += 0x10000;

347

dev->stats.collisions += 0x10000;

347

}

348

}

348

349

/* We do not keep track of MAC_TXSTAT_FCE and

350

/* We do not keep track of MAC_TXSTAT_FCE and

350

* MAC_TXSTAT_PCE events.

351

* MAC_TXSTAT_PCE events.

351

*/

352

*/

352

return 0;

353

return 0;

353

}

354

}

354

355

/* When we get a RX fifo overflow, the RX unit in GEM is probably hung

356

/* When we get a RX fifo overflow, the RX unit in GEM is probably hung

356

* so we do the following.

357

* so we do the following.

357

*

358

*

358

* If any part of the reset goes wrong, we return 1 and that causes the

359

* If any part of the reset goes wrong, we return 1 and that causes the

359

* whole chip to be reset.

360

* whole chip to be reset.

360

*/

361

*/

361

static int gem_rxmac_reset(struct gem *gp)

362

static int gem_rxmac_reset(struct gem *gp)

362

{

363

{

363

struct net_device *dev = gp->dev;

364

struct net_device *dev = gp->dev;

364

int limit, i;

365

int limit, i;

365

u64 desc_dma;

366

u64 desc_dma;

366

u32 val;

367

u32 val;

367

368

/* First, reset & disable MAC RX. */

369

/* First, reset & disable MAC RX. */

369

writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);

370

writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);

370

for (limit = 0; limit < 5000; limit++) {

371

for (limit = 0; limit < 5000; limit++) {

371

if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))

372

if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))

372

break;

373

break;

373

udelay(10);

374

udelay(10);

374

}

375

}

375

if (limit == 5000) {

376

if (limit == 5000) {

376

netdev_err(dev, "RX MAC will not reset, resetting whole chip\n");

377

netdev_err(dev, "RX MAC will not reset, resetting whole chip\n");

377

return 1;

378

return 1;

378

}

379

}

379

380

writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,

381

writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,

381

gp->regs + MAC_RXCFG);

382

gp->regs + MAC_RXCFG);

382

for (limit = 0; limit < 5000; limit++) {

383

for (limit = 0; limit < 5000; limit++) {

383

if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))

384

if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))

384

break;

385

break;

385

udelay(10);

386

udelay(10);

386

}

387

}

387

if (limit == 5000) {

388

if (limit == 5000) {

388

netdev_err(dev, "RX MAC will not disable, resetting whole chip\n");

389

netdev_err(dev, "RX MAC will not disable, resetting whole chip\n");

389

return 1;

390

return 1;

390

}

391

}

391

392

/* Second, disable RX DMA. */

393

/* Second, disable RX DMA. */

393

writel(0, gp->regs + RXDMA_CFG);

394

writel(0, gp->regs + RXDMA_CFG);

394

for (limit = 0; limit < 5000; limit++) {

395

for (limit = 0; limit < 5000; limit++) {

395

if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))

396

if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))

396

break;

397

break;

397

udelay(10);

398

udelay(10);

398

}

399

}

399

if (limit == 5000) {

400

if (limit == 5000) {

400

netdev_err(dev, "RX DMA will not disable, resetting whole chip\n");

401

netdev_err(dev, "RX DMA will not disable, resetting whole chip\n");

401

return 1;

402

return 1;

402

}

403

}

403

404

udelay(5000);

405

udelay(5000);

405

406

/* Execute RX reset command. */

407

/* Execute RX reset command. */

407

writel(gp->swrst_base | GREG_SWRST_RXRST,

408

writel(gp->swrst_base | GREG_SWRST_RXRST,

408

gp->regs + GREG_SWRST);

409

gp->regs + GREG_SWRST);

409

for (limit = 0; limit < 5000; limit++) {

410

for (limit = 0; limit < 5000; limit++) {

410

if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))

411

if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))

411

break;

412

break;

412

udelay(10);

413

udelay(10);

413

}

414

}

414

if (limit == 5000) {

415

if (limit == 5000) {

415

netdev_err(dev, "RX reset command will not execute, resetting whole chip\n");

416

netdev_err(dev, "RX reset command will not execute, resetting whole chip\n");

416

return 1;

417

return 1;

417

}

418

}

418

419

/* Refresh the RX ring. */

420

/* Refresh the RX ring. */

420

for (i = 0; i < RX_RING_SIZE; i++) {

421

for (i = 0; i < RX_RING_SIZE; i++) {

421

struct gem_rxd *rxd = &gp->init_block->rxd[i];

422

struct gem_rxd *rxd = &gp->init_block->rxd[i];

422

423

if (gp->rx_skbs[i] == NULL) {

424

if (gp->rx_skbs[i] == NULL) {

424

netdev_err(dev, "Parts of RX ring empty, resetting whole chip\n");

425

netdev_err(dev, "Parts of RX ring empty, resetting whole chip\n");

425

return 1;

426

return 1;

426

}

427

}

427

428

rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));

429

rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));

429

}

430

}

430

gp->rx_new = gp->rx_old = 0;

431

gp->rx_new = gp->rx_old = 0;

431

432

/* Now we must reprogram the rest of RX unit. */

433

/* Now we must reprogram the rest of RX unit. */

433

desc_dma = (u64) gp->gblock_dvma;

434

desc_dma = (u64) gp->gblock_dvma;

434

desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));

435

desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));

435

writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);

436

writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);

436

writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);

437

writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);

437

writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);

438

writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);

438

val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |

439

val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |

439

((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);

440

((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);

440

writel(val, gp->regs + RXDMA_CFG);

441

writel(val, gp->regs + RXDMA_CFG);

441

if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)

442

if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)

442

writel(((5 & RXDMA_BLANK_IPKTS) |

443

writel(((5 & RXDMA_BLANK_IPKTS) |

443

((8 << 12) & RXDMA_BLANK_ITIME)),

444

((8 << 12) & RXDMA_BLANK_ITIME)),

444

gp->regs + RXDMA_BLANK);

445

gp->regs + RXDMA_BLANK);

445

else

446

else

446

writel(((5 & RXDMA_BLANK_IPKTS) |

447

writel(((5 & RXDMA_BLANK_IPKTS) |

447

((4 << 12) & RXDMA_BLANK_ITIME)),

448

((4 << 12) & RXDMA_BLANK_ITIME)),

448

gp->regs + RXDMA_BLANK);

449

gp->regs + RXDMA_BLANK);

449

val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);

450

val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);

450

val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);

451

val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);

451

writel(val, gp->regs + RXDMA_PTHRESH);

452

writel(val, gp->regs + RXDMA_PTHRESH);

452

val = readl(gp->regs + RXDMA_CFG);

453

val = readl(gp->regs + RXDMA_CFG);

453

writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);

454

writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);

454

writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);

455

writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);

455

val = readl(gp->regs + MAC_RXCFG);

456

val = readl(gp->regs + MAC_RXCFG);

456

writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);

457

writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);

457

458

return 0;

459

return 0;

459

}

460

}

460

461

static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)

462

static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)

462

{

463

{

463

u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);

464

u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);

464

int ret = 0;

465

int ret = 0;

465

466

if (netif_msg_intr(gp))

467

if (netif_msg_intr(gp))

467

printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n",

468

printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n",

468

gp->dev->name, rxmac_stat);

469

gp->dev->name, rxmac_stat);

469

470

if (rxmac_stat & MAC_RXSTAT_OFLW) {

471

if (rxmac_stat & MAC_RXSTAT_OFLW) {

471

u32 smac = readl(gp->regs + MAC_SMACHINE);

472

u32 smac = readl(gp->regs + MAC_SMACHINE);

472

473

netdev_err(dev, "RX MAC fifo overflow smac[%08x]\n", smac);

474

netdev_err(dev, "RX MAC fifo overflow smac[%08x]\n", smac);

474

dev->stats.rx_over_errors++;

475

dev->stats.rx_over_errors++;

475

dev->stats.rx_fifo_errors++;

476

dev->stats.rx_fifo_errors++;

476

477

ret = gem_rxmac_reset(gp);

478

ret = gem_rxmac_reset(gp);

478

}

479

}

479

480

if (rxmac_stat & MAC_RXSTAT_ACE)

481

if (rxmac_stat & MAC_RXSTAT_ACE)

481

dev->stats.rx_frame_errors += 0x10000;

482

dev->stats.rx_frame_errors += 0x10000;

482

483

if (rxmac_stat & MAC_RXSTAT_CCE)

484

if (rxmac_stat & MAC_RXSTAT_CCE)

484

dev->stats.rx_crc_errors += 0x10000;

485

dev->stats.rx_crc_errors += 0x10000;

485

486

if (rxmac_stat & MAC_RXSTAT_LCE)

487

if (rxmac_stat & MAC_RXSTAT_LCE)

487

dev->stats.rx_length_errors += 0x10000;

488

dev->stats.rx_length_errors += 0x10000;

488

489

/* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE

490

/* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE

490

* events.

491

* events.

491

*/

492

*/

492

return ret;

493

return ret;

493

}

494

}

494

495

static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)

496

static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)

496

{

497

{

497

u32 mac_cstat = readl(gp->regs + MAC_CSTAT);

498

u32 mac_cstat = readl(gp->regs + MAC_CSTAT);

498

499

if (netif_msg_intr(gp))

500

if (netif_msg_intr(gp))

500

printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n",

501

printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n",

501

gp->dev->name, mac_cstat);

502

gp->dev->name, mac_cstat);

502

503

/* This interrupt is just for pause frame and pause

504

/* This interrupt is just for pause frame and pause

504

* tracking. It is useful for diagnostics and debug

505

* tracking. It is useful for diagnostics and debug

505

* but probably by default we will mask these events.

506

* but probably by default we will mask these events.

506

*/

507

*/

507

if (mac_cstat & MAC_CSTAT_PS)

508

if (mac_cstat & MAC_CSTAT_PS)

508

gp->pause_entered++;

509

gp->pause_entered++;

509

510

if (mac_cstat & MAC_CSTAT_PRCV)

511

if (mac_cstat & MAC_CSTAT_PRCV)

511

gp->pause_last_time_recvd = (mac_cstat >> 16);

512

gp->pause_last_time_recvd = (mac_cstat >> 16);

512

513

return 0;

514

return 0;

514

}

515

}

515

516

static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)

517

static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)

517

{

518

{

518

u32 mif_status = readl(gp->regs + MIF_STATUS);

519

u32 mif_status = readl(gp->regs + MIF_STATUS);

519

u32 reg_val, changed_bits;

520

u32 reg_val, changed_bits;

520

521

reg_val = (mif_status & MIF_STATUS_DATA) >> 16;

522

reg_val = (mif_status & MIF_STATUS_DATA) >> 16;

522

changed_bits = (mif_status & MIF_STATUS_STAT);

523

changed_bits = (mif_status & MIF_STATUS_STAT);

523

524

gem_handle_mif_event(gp, reg_val, changed_bits);

525

gem_handle_mif_event(gp, reg_val, changed_bits);

525

526

return 0;

527

return 0;

527

}

528

}

528

529

static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)

530

static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)

530

{

531

{

531

u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);

532

u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);

532

533

if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&

534

if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&

534

gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {

535

gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {

535

netdev_err(dev, "PCI error [%04x]", pci_estat);

536

netdev_err(dev, "PCI error [%04x]", pci_estat);

536

537

if (pci_estat & GREG_PCIESTAT_BADACK)

538

if (pci_estat & GREG_PCIESTAT_BADACK)

538

pr_cont(" <No ACK64# during ABS64 cycle>");

539

pr_cont(" <No ACK64# during ABS64 cycle>");

539

if (pci_estat & GREG_PCIESTAT_DTRTO)

540

if (pci_estat & GREG_PCIESTAT_DTRTO)

540

pr_cont(" <Delayed transaction timeout>");

541

pr_cont(" <Delayed transaction timeout>");

541

if (pci_estat & GREG_PCIESTAT_OTHER)

542

if (pci_estat & GREG_PCIESTAT_OTHER)

542

pr_cont(" <other>");

543

pr_cont(" <other>");

543

pr_cont("\n");

544

pr_cont("\n");

544

} else {

545

} else {

545

pci_estat |= GREG_PCIESTAT_OTHER;

546

pci_estat |= GREG_PCIESTAT_OTHER;

546

netdev_err(dev, "PCI error\n");

547

netdev_err(dev, "PCI error\n");

547

}

548

}

548

549

if (pci_estat & GREG_PCIESTAT_OTHER) {

550

if (pci_estat & GREG_PCIESTAT_OTHER) {

550

u16 pci_cfg_stat;

551

u16 pci_cfg_stat;

551

552

/* Interrogate PCI config space for the

553

/* Interrogate PCI config space for the

553

* true cause.

554

* true cause.

554

*/

555

*/

555

pci_read_config_word(gp->pdev, PCI_STATUS,

556

pci_read_config_word(gp->pdev, PCI_STATUS,

556

&pci_cfg_stat);

557

&pci_cfg_stat);

557

netdev_err(dev, "Read PCI cfg space status [%04x]\n",

558

netdev_err(dev, "Read PCI cfg space status [%04x]\n",

558

pci_cfg_stat);

559

pci_cfg_stat);

559

if (pci_cfg_stat & PCI_STATUS_PARITY)

560

if (pci_cfg_stat & PCI_STATUS_PARITY)

560

netdev_err(dev, "PCI parity error detected\n");

561

netdev_err(dev, "PCI parity error detected\n");

561

if (pci_cfg_stat & PCI_STATUS_SIG_TARGET_ABORT)

562

if (pci_cfg_stat & PCI_STATUS_SIG_TARGET_ABORT)

562

netdev_err(dev, "PCI target abort\n");

563

netdev_err(dev, "PCI target abort\n");

563

if (pci_cfg_stat & PCI_STATUS_REC_TARGET_ABORT)

564

if (pci_cfg_stat & PCI_STATUS_REC_TARGET_ABORT)

564

netdev_err(dev, "PCI master acks target abort\n");

565

netdev_err(dev, "PCI master acks target abort\n");

565

if (pci_cfg_stat & PCI_STATUS_REC_MASTER_ABORT)

566

if (pci_cfg_stat & PCI_STATUS_REC_MASTER_ABORT)

566

netdev_err(dev, "PCI master abort\n");

567

netdev_err(dev, "PCI master abort\n");

567

if (pci_cfg_stat & PCI_STATUS_SIG_SYSTEM_ERROR)

568

if (pci_cfg_stat & PCI_STATUS_SIG_SYSTEM_ERROR)

568

netdev_err(dev, "PCI system error SERR#\n");

569

netdev_err(dev, "PCI system error SERR#\n");

569

if (pci_cfg_stat & PCI_STATUS_DETECTED_PARITY)

570

if (pci_cfg_stat & PCI_STATUS_DETECTED_PARITY)

570

netdev_err(dev, "PCI parity error\n");

571

netdev_err(dev, "PCI parity error\n");

571

572

/* Write the error bits back to clear them. */

573

/* Write the error bits back to clear them. */

573

pci_cfg_stat &= (PCI_STATUS_PARITY |

574

pci_cfg_stat &= (PCI_STATUS_PARITY |

574

PCI_STATUS_SIG_TARGET_ABORT |

575

PCI_STATUS_SIG_TARGET_ABORT |

575

PCI_STATUS_REC_TARGET_ABORT |

576

PCI_STATUS_REC_TARGET_ABORT |

576

PCI_STATUS_REC_MASTER_ABORT |

577

PCI_STATUS_REC_MASTER_ABORT |

577

PCI_STATUS_SIG_SYSTEM_ERROR |

578

PCI_STATUS_SIG_SYSTEM_ERROR |

578

PCI_STATUS_DETECTED_PARITY);

579

PCI_STATUS_DETECTED_PARITY);

579

pci_write_config_word(gp->pdev,

580

pci_write_config_word(gp->pdev,

580

PCI_STATUS, pci_cfg_stat);

581

PCI_STATUS, pci_cfg_stat);

581

}

582

}

582

583

/* For all PCI errors, we should reset the chip. */

584

/* For all PCI errors, we should reset the chip. */

584

return 1;

585

return 1;

585

}

586

}

586

587

/* All non-normal interrupt conditions get serviced here.

588

/* All non-normal interrupt conditions get serviced here.

588

* Returns non-zero if we should just exit the interrupt

589

* Returns non-zero if we should just exit the interrupt

589

* handler right now (ie. if we reset the card which invalidates

590

* handler right now (ie. if we reset the card which invalidates

590

* all of the other original irq status bits).

591

* all of the other original irq status bits).

591

*/

592

*/

592

static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)

593

static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)

593

{

594

{

594

if (gem_status & GREG_STAT_RXNOBUF) {

595

if (gem_status & GREG_STAT_RXNOBUF) {

595

/* Frame arrived, no free RX buffers available. */

596

/* Frame arrived, no free RX buffers available. */

596

if (netif_msg_rx_err(gp))

597

if (netif_msg_rx_err(gp))

597

printk(KERN_DEBUG "%s: no buffer for rx frame\n",

598

printk(KERN_DEBUG "%s: no buffer for rx frame\n",

598

gp->dev->name);

599

gp->dev->name);

599

dev->stats.rx_dropped++;

600

dev->stats.rx_dropped++;

600

}

601

}

601

602

if (gem_status & GREG_STAT_RXTAGERR) {

603

if (gem_status & GREG_STAT_RXTAGERR) {

603

/* corrupt RX tag framing */

604

/* corrupt RX tag framing */

604

if (netif_msg_rx_err(gp))

605

if (netif_msg_rx_err(gp))

605

printk(KERN_DEBUG "%s: corrupt rx tag framing\n",

606

printk(KERN_DEBUG "%s: corrupt rx tag framing\n",

606

gp->dev->name);

607

gp->dev->name);

607

dev->stats.rx_errors++;

608

dev->stats.rx_errors++;

608

609

return 1;

610

return 1;

610

}

611

}

611

612

if (gem_status & GREG_STAT_PCS) {

613

if (gem_status & GREG_STAT_PCS) {

613

if (gem_pcs_interrupt(dev, gp, gem_status))

614

if (gem_pcs_interrupt(dev, gp, gem_status))

614

return 1;

615

return 1;

615

}

616

}

616

617

if (gem_status & GREG_STAT_TXMAC) {

618

if (gem_status & GREG_STAT_TXMAC) {

618

if (gem_txmac_interrupt(dev, gp, gem_status))

619

if (gem_txmac_interrupt(dev, gp, gem_status))

619

return 1;

620

return 1;

620

}

621

}

621

622

if (gem_status & GREG_STAT_RXMAC) {

623

if (gem_status & GREG_STAT_RXMAC) {

623

if (gem_rxmac_interrupt(dev, gp, gem_status))

624

if (gem_rxmac_interrupt(dev, gp, gem_status))

624

return 1;

625

return 1;

625

}

626

}

626

627

if (gem_status & GREG_STAT_MAC) {

628

if (gem_status & GREG_STAT_MAC) {

628

if (gem_mac_interrupt(dev, gp, gem_status))

629

if (gem_mac_interrupt(dev, gp, gem_status))

629

return 1;

630

return 1;

630

}

631

}

631

632

if (gem_status & GREG_STAT_MIF) {

633

if (gem_status & GREG_STAT_MIF) {

633

if (gem_mif_interrupt(dev, gp, gem_status))

634

if (gem_mif_interrupt(dev, gp, gem_status))

634

return 1;

635

return 1;

635

}

636

}

636

637

if (gem_status & GREG_STAT_PCIERR) {

638

if (gem_status & GREG_STAT_PCIERR) {

638

if (gem_pci_interrupt(dev, gp, gem_status))

639

if (gem_pci_interrupt(dev, gp, gem_status))

639

return 1;

640

return 1;

640

}

641

}

641

642

return 0;

643

return 0;

643

}

644

}

644

645

static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)

646

static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)

646

{

647

{

647

int entry, limit;

648

int entry, limit;

648

649

entry = gp->tx_old;

650

entry = gp->tx_old;

650

limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);

651

limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);

651

while (entry != limit) {

652

while (entry != limit) {

652

struct sk_buff *skb;

653

struct sk_buff *skb;

653

struct gem_txd *txd;

654

struct gem_txd *txd;

654

dma_addr_t dma_addr;

655

dma_addr_t dma_addr;

655

u32 dma_len;

656

u32 dma_len;

656

int frag;

657

int frag;

657

658

if (netif_msg_tx_done(gp))

659

if (netif_msg_tx_done(gp))

659

printk(KERN_DEBUG "%s: tx done, slot %d\n",

660

printk(KERN_DEBUG "%s: tx done, slot %d\n",

660

gp->dev->name, entry);

661

gp->dev->name, entry);

661

skb = gp->tx_skbs[entry];

662

skb = gp->tx_skbs[entry];

662

if (skb_shinfo(skb)->nr_frags) {

663

if (skb_shinfo(skb)->nr_frags) {

663

int last = entry + skb_shinfo(skb)->nr_frags;

664

int last = entry + skb_shinfo(skb)->nr_frags;

664

int walk = entry;

665

int walk = entry;

665

int incomplete = 0;

666

int incomplete = 0;

666

667

last &= (TX_RING_SIZE - 1);

668

last &= (TX_RING_SIZE - 1);

668

for (;;) {

669

for (;;) {

669

walk = NEXT_TX(walk);

670

walk = NEXT_TX(walk);

670

if (walk == limit)

671

if (walk == limit)

671

incomplete = 1;

672

incomplete = 1;

672

if (walk == last)

673

if (walk == last)

673

break;

674

break;

674

}

675

}

675

if (incomplete)

676

if (incomplete)

676

break;

677

break;

677

}

678

}

678

gp->tx_skbs[entry] = NULL;

679

gp->tx_skbs[entry] = NULL;

679

dev->stats.tx_bytes += skb->len;

680

dev->stats.tx_bytes += skb->len;

680

681

for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {

682

for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {

682

txd = &gp->init_block->txd[entry];

683

txd = &gp->init_block->txd[entry];

683

684

dma_addr = le64_to_cpu(txd->buffer);

685

dma_addr = le64_to_cpu(txd->buffer);

685

dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;

686

dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;

686

687

pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);

688

pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);

688

entry = NEXT_TX(entry);

689

entry = NEXT_TX(entry);

689

}

690

}

690

691

dev->stats.tx_packets++;

692

dev->stats.tx_packets++;

692

dev_kfree_skb(skb);

693

dev_kfree_skb(skb);

693

}

694

}

694

gp->tx_old = entry;

695

gp->tx_old = entry;

695

696

/* Need to make the tx_old update visible to gem_start_xmit()

697

/* Need to make the tx_old update visible to gem_start_xmit()

697

* before checking for netif_queue_stopped(). Without the

698

* before checking for netif_queue_stopped(). Without the

698

* memory barrier, there is a small possibility that gem_start_xmit()

699

* memory barrier, there is a small possibility that gem_start_xmit()

699

* will miss it and cause the queue to be stopped forever.

700

* will miss it and cause the queue to be stopped forever.

700

*/

701

*/

701

smp_mb();

702

smp_mb();

702

703

if (unlikely(netif_queue_stopped(dev) &&

704

if (unlikely(netif_queue_stopped(dev) &&

704

TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))) {

705

TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))) {

705

struct netdev_queue *txq = netdev_get_tx_queue(dev, 0);

706

struct netdev_queue *txq = netdev_get_tx_queue(dev, 0);

706

707

__netif_tx_lock(txq, smp_processor_id());

708

__netif_tx_lock(txq, smp_processor_id());

708

if (netif_queue_stopped(dev) &&

709

if (netif_queue_stopped(dev) &&

709

TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))

710

TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))

710

netif_wake_queue(dev);

711

netif_wake_queue(dev);

711

__netif_tx_unlock(txq);

712

__netif_tx_unlock(txq);

712

}

713

}

713

}

714

}

714

715

static __inline__ void gem_post_rxds(struct gem *gp, int limit)

716

static __inline__ void gem_post_rxds(struct gem *gp, int limit)

716

{

717

{

717

int cluster_start, curr, count, kick;

718

int cluster_start, curr, count, kick;

718

719

cluster_start = curr = (gp->rx_new & ~(4 - 1));

720

cluster_start = curr = (gp->rx_new & ~(4 - 1));

720

count = 0;

721

count = 0;

721

kick = -1;

722

kick = -1;

722

wmb();

723

wmb();

723

while (curr != limit) {

724

while (curr != limit) {

724

curr = NEXT_RX(curr);

725

curr = NEXT_RX(curr);

725

if (++count == 4) {

726

if (++count == 4) {

726

struct gem_rxd *rxd =

727

struct gem_rxd *rxd =

727

&gp->init_block->rxd[cluster_start];

728

&gp->init_block->rxd[cluster_start];

728

for (;;) {

729

for (;;) {

729

rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));

730

rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));

730

rxd++;

731

rxd++;

731

cluster_start = NEXT_RX(cluster_start);

732

cluster_start = NEXT_RX(cluster_start);

732

if (cluster_start == curr)

733

if (cluster_start == curr)

733

break;

734

break;

734

}

735

}

735

kick = curr;

736

kick = curr;

736

count = 0;

737

count = 0;

737

}

738

}

738

}

739

}

739

if (kick >= 0) {

740

if (kick >= 0) {

740

mb();

741

mb();

741

writel(kick, gp->regs + RXDMA_KICK);

742

writel(kick, gp->regs + RXDMA_KICK);

742

}

743

}

743

}

744

}

744

745

#define ALIGNED_RX_SKB_ADDR(addr) \

746

#define ALIGNED_RX_SKB_ADDR(addr) \

746

((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))

747

((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))

747

static __inline__ struct sk_buff *gem_alloc_skb(struct net_device *dev, int size,

748

static __inline__ struct sk_buff *gem_alloc_skb(struct net_device *dev, int size,

748

gfp_t gfp_flags)

749

gfp_t gfp_flags)

749

{

750

{

750

struct sk_buff *skb = alloc_skb(size + 64, gfp_flags);

751

struct sk_buff *skb = alloc_skb(size + 64, gfp_flags);

751

752

if (likely(skb)) {

753

if (likely(skb)) {

753

unsigned long offset = ALIGNED_RX_SKB_ADDR(skb->data);

754

unsigned long offset = ALIGNED_RX_SKB_ADDR(skb->data);

754

skb_reserve(skb, offset);

755

skb_reserve(skb, offset);

755

skb->dev = dev;

756

skb->dev = dev;

756

}

757

}

757

return skb;

758

return skb;

758

}

759

}

759

760

static int gem_rx(struct gem *gp, int work_to_do)

761

static int gem_rx(struct gem *gp, int work_to_do)

761

{

762

{

762

struct net_device *dev = gp->dev;

763

struct net_device *dev = gp->dev;

763

int entry, drops, work_done = 0;

764

int entry, drops, work_done = 0;

764

u32 done;

765

u32 done;

765

__sum16 csum;

766

__sum16 csum;

766

767

if (netif_msg_rx_status(gp))

768

if (netif_msg_rx_status(gp))

768

printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n",

769

printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n",

769

gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);

770

gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);

770

771

entry = gp->rx_new;

772

entry = gp->rx_new;

772

drops = 0;

773

drops = 0;

773

done = readl(gp->regs + RXDMA_DONE);

774

done = readl(gp->regs + RXDMA_DONE);

774

for (;;) {

775

for (;;) {

775

struct gem_rxd *rxd = &gp->init_block->rxd[entry];

776

struct gem_rxd *rxd = &gp->init_block->rxd[entry];

776

struct sk_buff *skb;

777

struct sk_buff *skb;

777

u64 status = le64_to_cpu(rxd->status_word);

778

u64 status = le64_to_cpu(rxd->status_word);

778

dma_addr_t dma_addr;

779

dma_addr_t dma_addr;

779

int len;

780

int len;

780

781

if ((status & RXDCTRL_OWN) != 0)

782

if ((status & RXDCTRL_OWN) != 0)

782

break;

783

break;

783

784

if (work_done >= RX_RING_SIZE || work_done >= work_to_do)

785

if (work_done >= RX_RING_SIZE || work_done >= work_to_do)

785

break;

786

break;

786

787

/* When writing back RX descriptor, GEM writes status

788

/* When writing back RX descriptor, GEM writes status

788

* then buffer address, possibly in separate transactions.

789

* then buffer address, possibly in separate transactions.

789

* If we don't wait for the chip to write both, we could

790

* If we don't wait for the chip to write both, we could

790

* post a new buffer to this descriptor then have GEM spam

791

* post a new buffer to this descriptor then have GEM spam

791

* on the buffer address. We sync on the RX completion

792

* on the buffer address. We sync on the RX completion

792

* register to prevent this from happening.

793

* register to prevent this from happening.

793

*/

794

*/

794

if (entry == done) {

795

if (entry == done) {

795

done = readl(gp->regs + RXDMA_DONE);

796

done = readl(gp->regs + RXDMA_DONE);

796

if (entry == done)

797

if (entry == done)

797

break;

798

break;

798

}

799

}

799

800

/* We can now account for the work we're about to do */

801

/* We can now account for the work we're about to do */

801

work_done++;

802

work_done++;

802

803

skb = gp->rx_skbs[entry];

804

skb = gp->rx_skbs[entry];

804

805

len = (status & RXDCTRL_BUFSZ) >> 16;

806

len = (status & RXDCTRL_BUFSZ) >> 16;

806

if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {

807

if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {

807

dev->stats.rx_errors++;

808

dev->stats.rx_errors++;

808

if (len < ETH_ZLEN)

809

if (len < ETH_ZLEN)

809

dev->stats.rx_length_errors++;

810

dev->stats.rx_length_errors++;

810

if (len & RXDCTRL_BAD)

811

if (len & RXDCTRL_BAD)

811

dev->stats.rx_crc_errors++;

812

dev->stats.rx_crc_errors++;

812

813

/* We'll just return it to GEM. */

814

/* We'll just return it to GEM. */

814

drop_it:

815

drop_it:

815

dev->stats.rx_dropped++;

816

dev->stats.rx_dropped++;

816

goto next;

817

goto next;

817

}

818

}

818

819

dma_addr = le64_to_cpu(rxd->buffer);

820

dma_addr = le64_to_cpu(rxd->buffer);

820

if (len > RX_COPY_THRESHOLD) {

821

if (len > RX_COPY_THRESHOLD) {

821

struct sk_buff *new_skb;

822

struct sk_buff *new_skb;

822

823

new_skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);

824

new_skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);

824

if (new_skb == NULL) {

825

if (new_skb == NULL) {

825

drops++;

826

drops++;

826

goto drop_it;

827

goto drop_it;

827

}

828

}

828

pci_unmap_page(gp->pdev, dma_addr,

829

pci_unmap_page(gp->pdev, dma_addr,

829

RX_BUF_ALLOC_SIZE(gp),

830

RX_BUF_ALLOC_SIZE(gp),

830

PCI_DMA_FROMDEVICE);

831

PCI_DMA_FROMDEVICE);

831

gp->rx_skbs[entry] = new_skb;

832

gp->rx_skbs[entry] = new_skb;

832

skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET));

833

skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET));

833

rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev,

834

rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev,

834

virt_to_page(new_skb->data),

835

virt_to_page(new_skb->data),

835

offset_in_page(new_skb->data),

836

offset_in_page(new_skb->data),

836

RX_BUF_ALLOC_SIZE(gp),

837

RX_BUF_ALLOC_SIZE(gp),

837

PCI_DMA_FROMDEVICE));

838

PCI_DMA_FROMDEVICE));

838

skb_reserve(new_skb, RX_OFFSET);

839

skb_reserve(new_skb, RX_OFFSET);

839

840

/* Trim the original skb for the netif. */

841

/* Trim the original skb for the netif. */

841

skb_trim(skb, len);

842

skb_trim(skb, len);

842

} else {

843

} else {

843

struct sk_buff *copy_skb = netdev_alloc_skb(dev, len + 2);

844

struct sk_buff *copy_skb = netdev_alloc_skb(dev, len + 2);

844

845

if (copy_skb == NULL) {

846

if (copy_skb == NULL) {

846

drops++;

847

drops++;

847

goto drop_it;

848

goto drop_it;

848

}

849

}

849

850

skb_reserve(copy_skb, 2);

851

skb_reserve(copy_skb, 2);

851

skb_put(copy_skb, len);

852

skb_put(copy_skb, len);

852

pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);

853

pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);

853

skb_copy_from_linear_data(skb, copy_skb->data, len);

854

skb_copy_from_linear_data(skb, copy_skb->data, len);

854

pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);

855

pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);

855

856

/* We'll reuse the original ring buffer. */

857

/* We'll reuse the original ring buffer. */

857

skb = copy_skb;

858

skb = copy_skb;

858

}

859

}

859

860

csum = (__force __sum16)htons((status & RXDCTRL_TCPCSUM) ^ 0xffff);

861

csum = (__force __sum16)htons((status & RXDCTRL_TCPCSUM) ^ 0xffff);

861

skb->csum = csum_unfold(csum);

862

skb->csum = csum_unfold(csum);

862

skb->ip_summed = CHECKSUM_COMPLETE;

863

skb->ip_summed = CHECKSUM_COMPLETE;

863

skb->protocol = eth_type_trans(skb, gp->dev);

864

skb->protocol = eth_type_trans(skb, gp->dev);

864

865

napi_gro_receive(&gp->napi, skb);

866

napi_gro_receive(&gp->napi, skb);

866

867

dev->stats.rx_packets++;

868

dev->stats.rx_packets++;

868

dev->stats.rx_bytes += len;

869

dev->stats.rx_bytes += len;

869

870

entry = NEXT_RX(entry);

872

entry = NEXT_RX(entry);

872

}

873

}

873

874

gem_post_rxds(gp, entry);

875

gem_post_rxds(gp, entry);

875

876

gp->rx_new = entry;

877

gp->rx_new = entry;

877

878

if (drops)

879

if (drops)

879

netdev_info(gp->dev, "Memory squeeze, deferring packet\n");

880

netdev_info(gp->dev, "Memory squeeze, deferring packet\n");

880

881

return work_done;

882

return work_done;

882

}

883

}

883

884

static int gem_poll(struct napi_struct *napi, int budget)

885

static int gem_poll(struct napi_struct *napi, int budget)

885

{

886

{

886

struct gem *gp = container_of(napi, struct gem, napi);

887

struct gem *gp = container_of(napi, struct gem, napi);

887

struct net_device *dev = gp->dev;

888

struct net_device *dev = gp->dev;

888

int work_done;

889

int work_done;

889

890

work_done = 0;

891

work_done = 0;

891

do {

892

do {

892

/* Handle anomalies */

893

/* Handle anomalies */

893

if (unlikely(gp->status & GREG_STAT_ABNORMAL)) {

894

if (unlikely(gp->status & GREG_STAT_ABNORMAL)) {

894

struct netdev_queue *txq = netdev_get_tx_queue(dev, 0);

895

struct netdev_queue *txq = netdev_get_tx_queue(dev, 0);

895

int reset;

896

int reset;

896

897

/* We run the abnormal interrupt handling code with

898

/* We run the abnormal interrupt handling code with

898

* the Tx lock. It only resets the Rx portion of the

899

* the Tx lock. It only resets the Rx portion of the

899

* chip, but we need to guard it against DMA being

900

* chip, but we need to guard it against DMA being

900

* restarted by the link poll timer

901

* restarted by the link poll timer

901

*/

902

*/

902

__netif_tx_lock(txq, smp_processor_id());

903

__netif_tx_lock(txq, smp_processor_id());

903

reset = gem_abnormal_irq(dev, gp, gp->status);

904

reset = gem_abnormal_irq(dev, gp, gp->status);

904

__netif_tx_unlock(txq);

905

__netif_tx_unlock(txq);

905

if (reset) {

906

if (reset) {

906

gem_schedule_reset(gp);

907

gem_schedule_reset(gp);

907

napi_complete(napi);

908

napi_complete(napi);

908

return work_done;

909

return work_done;

909

}

910

}

910

}

911

}

911

912

/* Run TX completion thread */

913

/* Run TX completion thread */

913

gem_tx(dev, gp, gp->status);

914

gem_tx(dev, gp, gp->status);

914

915

/* Run RX thread. We don't use any locking here,

916

/* Run RX thread. We don't use any locking here,

916

* code willing to do bad things - like cleaning the

917

* code willing to do bad things - like cleaning the

917

* rx ring - must call napi_disable(), which

918

* rx ring - must call napi_disable(), which

918

* schedule_timeout()'s if polling is already disabled.

919

* schedule_timeout()'s if polling is already disabled.

919

*/

920

*/

920

work_done += gem_rx(gp, budget - work_done);

921

work_done += gem_rx(gp, budget - work_done);

921

922

if (work_done >= budget)

923

if (work_done >= budget)

923

return work_done;

924

return work_done;

924

925

gp->status = readl(gp->regs + GREG_STAT);

926

gp->status = readl(gp->regs + GREG_STAT);

926

} while (gp->status & GREG_STAT_NAPI);

927

} while (gp->status & GREG_STAT_NAPI);

927

928

napi_complete(napi);

929

napi_complete(napi);

929

gem_enable_ints(gp);

930

gem_enable_ints(gp);

930

931

return work_done;

932

return work_done;

932

}

933

}

933

934

static irqreturn_t gem_interrupt(int irq, void *dev_id)

935

static irqreturn_t gem_interrupt(int irq, void *dev_id)

935

{

936

{

936

struct net_device *dev = dev_id;

937

struct net_device *dev = dev_id;

937

struct gem *gp = netdev_priv(dev);

938

struct gem *gp = netdev_priv(dev);

938

939

if (napi_schedule_prep(&gp->napi)) {

940

if (napi_schedule_prep(&gp->napi)) {

940

u32 gem_status = readl(gp->regs + GREG_STAT);

941

u32 gem_status = readl(gp->regs + GREG_STAT);

941

942

if (unlikely(gem_status == 0)) {

943

if (unlikely(gem_status == 0)) {

943

napi_enable(&gp->napi);

944

napi_enable(&gp->napi);

944

return IRQ_NONE;

945

return IRQ_NONE;

945

}

946

}

946

if (netif_msg_intr(gp))

947

if (netif_msg_intr(gp))

947

printk(KERN_DEBUG "%s: gem_interrupt() gem_status: 0x%x\n",

948

printk(KERN_DEBUG "%s: gem_interrupt() gem_status: 0x%x\n",

948

gp->dev->name, gem_status);

949

gp->dev->name, gem_status);

949

950

gp->status = gem_status;

951

gp->status = gem_status;

951

gem_disable_ints(gp);

952

gem_disable_ints(gp);

952

__napi_schedule(&gp->napi);

953

__napi_schedule(&gp->napi);

953

}

954

}

954

955

/* If polling was disabled at the time we received that

956

/* If polling was disabled at the time we received that

956

* interrupt, we may return IRQ_HANDLED here while we

957

* interrupt, we may return IRQ_HANDLED here while we

957

* should return IRQ_NONE. No big deal...

958

* should return IRQ_NONE. No big deal...

958

*/

959

*/

959

return IRQ_HANDLED;

960

return IRQ_HANDLED;

960

}

961

}

961

962

#ifdef CONFIG_NET_POLL_CONTROLLER

963

#ifdef CONFIG_NET_POLL_CONTROLLER

963

static void gem_poll_controller(struct net_device *dev)

964

static void gem_poll_controller(struct net_device *dev)

964

{

965

{

965

struct gem *gp = netdev_priv(dev);

966

struct gem *gp = netdev_priv(dev);

966

967

disable_irq(gp->pdev->irq);

968

disable_irq(gp->pdev->irq);

968

gem_interrupt(gp->pdev->irq, dev);

969

gem_interrupt(gp->pdev->irq, dev);

969

enable_irq(gp->pdev->irq);

970

enable_irq(gp->pdev->irq);

970

}

971

}

971

#endif

972

#endif

972

973

static void gem_tx_timeout(struct net_device *dev)

974

static void gem_tx_timeout(struct net_device *dev)

974

{

975

{

975

struct gem *gp = netdev_priv(dev);

976

struct gem *gp = netdev_priv(dev);

976

977

netdev_err(dev, "transmit timed out, resetting\n");

978

netdev_err(dev, "transmit timed out, resetting\n");

978

979

netdev_err(dev, "TX_STATE[%08x:%08x:%08x]\n",

980

netdev_err(dev, "TX_STATE[%08x:%08x:%08x]\n",

980

readl(gp->regs + TXDMA_CFG),

981

readl(gp->regs + TXDMA_CFG),

981

readl(gp->regs + MAC_TXSTAT),

982

readl(gp->regs + MAC_TXSTAT),

982

readl(gp->regs + MAC_TXCFG));

983

readl(gp->regs + MAC_TXCFG));

983

netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n",

984

netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n",

984

readl(gp->regs + RXDMA_CFG),

985

readl(gp->regs + RXDMA_CFG),

985

readl(gp->regs + MAC_RXSTAT),

986

readl(gp->regs + MAC_RXSTAT),

986

readl(gp->regs + MAC_RXCFG));

987

readl(gp->regs + MAC_RXCFG));

987

988

gem_schedule_reset(gp);

989

gem_schedule_reset(gp);

989

}

990

}

990

991

static __inline__ int gem_intme(int entry)

992

static __inline__ int gem_intme(int entry)

992

{

993

{

993

/* Algorithm: IRQ every 1/2 of descriptors. */

994

/* Algorithm: IRQ every 1/2 of descriptors. */

994

if (!(entry & ((TX_RING_SIZE>>1)-1)))

995

if (!(entry & ((TX_RING_SIZE>>1)-1)))

995

return 1;

996

return 1;

996

997

return 0;

998

return 0;

998

}

999

}

999

1000

static netdev_tx_t gem_start_xmit(struct sk_buff *skb,

1001

static netdev_tx_t gem_start_xmit(struct sk_buff *skb,

1001

struct net_device *dev)

1002

struct net_device *dev)

1002

{

1003

{

1003

struct gem *gp = netdev_priv(dev);

1004

struct gem *gp = netdev_priv(dev);

1004

int entry;

1005

int entry;

1005

u64 ctrl;

1006

u64 ctrl;

1006

1007

ctrl = 0;

1008

ctrl = 0;

1008

if (skb->ip_summed == CHECKSUM_PARTIAL) {

1009

if (skb->ip_summed == CHECKSUM_PARTIAL) {

1009

const u64 csum_start_off = skb_checksum_start_offset(skb);

1010

const u64 csum_start_off = skb_checksum_start_offset(skb);

1010

const u64 csum_stuff_off = csum_start_off + skb->csum_offset;

1011

const u64 csum_stuff_off = csum_start_off + skb->csum_offset;

1011

1012

ctrl = (TXDCTRL_CENAB |

1013

ctrl = (TXDCTRL_CENAB |

1013

(csum_start_off << 15) |

1014

(csum_start_off << 15) |

1014

(csum_stuff_off << 21));

1015

(csum_stuff_off << 21));

1015

}

1016

}

1016

1017

if (unlikely(TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1))) {

1018

if (unlikely(TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1))) {

1018

/* This is a hard error, log it. */

1019

/* This is a hard error, log it. */

1019

if (!netif_queue_stopped(dev)) {

1020

if (!netif_queue_stopped(dev)) {

1020

netif_stop_queue(dev);

1021

netif_stop_queue(dev);

1021

netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");

1022

netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");

1022

}

1023

}

1023

return NETDEV_TX_BUSY;

1024

return NETDEV_TX_BUSY;

1024

}

1025

}

1025

1026

entry = gp->tx_new;

1027

entry = gp->tx_new;

1027

gp->tx_skbs[entry] = skb;

1028

gp->tx_skbs[entry] = skb;

1028

1029

if (skb_shinfo(skb)->nr_frags == 0) {

1030

if (skb_shinfo(skb)->nr_frags == 0) {

1030

struct gem_txd *txd = &gp->init_block->txd[entry];

1031

struct gem_txd *txd = &gp->init_block->txd[entry];

1031

dma_addr_t mapping;

1032

dma_addr_t mapping;

1032

u32 len;

1033

u32 len;

1033

1034

len = skb->len;

1035

len = skb->len;

1035

mapping = pci_map_page(gp->pdev,

1036

mapping = pci_map_page(gp->pdev,

1036

virt_to_page(skb->data),

1037

virt_to_page(skb->data),

1037

offset_in_page(skb->data),

1038

offset_in_page(skb->data),

1038

len, PCI_DMA_TODEVICE);

1039

len, PCI_DMA_TODEVICE);

1039

ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;

1040

ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;

1040

if (gem_intme(entry))

1041

if (gem_intme(entry))

1041

ctrl |= TXDCTRL_INTME;

1042

ctrl |= TXDCTRL_INTME;

1042

txd->buffer = cpu_to_le64(mapping);

1043

txd->buffer = cpu_to_le64(mapping);

1043

wmb();

1044

wmb();

1044

txd->control_word = cpu_to_le64(ctrl);

1045

txd->control_word = cpu_to_le64(ctrl);

1045

entry = NEXT_TX(entry);

1046

entry = NEXT_TX(entry);

1046

} else {

1047

} else {

1047

struct gem_txd *txd;

1048

struct gem_txd *txd;

1048

u32 first_len;

1049

u32 first_len;

1049

u64 intme;

1050

u64 intme;

1050

dma_addr_t first_mapping;

1051

dma_addr_t first_mapping;

1051

int frag, first_entry = entry;

1052

int frag, first_entry = entry;

1052

1053

intme = 0;

1054

intme = 0;

1054

if (gem_intme(entry))

1055

if (gem_intme(entry))

1055

intme |= TXDCTRL_INTME;

1056

intme |= TXDCTRL_INTME;

1056

1057

/* We must give this initial chunk to the device last.

1058

/* We must give this initial chunk to the device last.

1058

* Otherwise we could race with the device.

1059

* Otherwise we could race with the device.

1059

*/

1060

*/

1060

first_len = skb_headlen(skb);

1061

first_len = skb_headlen(skb);

1061

first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data),

1062

first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data),

1062

offset_in_page(skb->data),

1063

offset_in_page(skb->data),

1063

first_len, PCI_DMA_TODEVICE);

1064

first_len, PCI_DMA_TODEVICE);

1064

entry = NEXT_TX(entry);

1065

entry = NEXT_TX(entry);

1065

1066

for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {

1067

for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {

1067

skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];

1068

skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];

1068

u32 len;

1069

u32 len;

1069

dma_addr_t mapping;

1070

dma_addr_t mapping;

1070

u64 this_ctrl;

1071

u64 this_ctrl;

1071

1072

len = this_frag->size;

1073

len = this_frag->size;

1073

mapping = pci_map_page(gp->pdev,

1074

mapping = pci_map_page(gp->pdev,

1074

this_frag->page,

1075

this_frag->page,

1075

this_frag->page_offset,

1076

this_frag->page_offset,

1076

len, PCI_DMA_TODEVICE);

1077

len, PCI_DMA_TODEVICE);

1077

this_ctrl = ctrl;

1078

this_ctrl = ctrl;

1078

if (frag == skb_shinfo(skb)->nr_frags - 1)

1079

if (frag == skb_shinfo(skb)->nr_frags - 1)

1079

this_ctrl |= TXDCTRL_EOF;

1080

this_ctrl |= TXDCTRL_EOF;

1080

1081

txd = &gp->init_block->txd[entry];

1082

txd = &gp->init_block->txd[entry];

1082

txd->buffer = cpu_to_le64(mapping);

1083

txd->buffer = cpu_to_le64(mapping);

1083

wmb();

1084

wmb();

1084

txd->control_word = cpu_to_le64(this_ctrl | len);

1085

txd->control_word = cpu_to_le64(this_ctrl | len);

1085

1086

if (gem_intme(entry))

1087

if (gem_intme(entry))

1087

intme |= TXDCTRL_INTME;

1088

intme |= TXDCTRL_INTME;

1088

1089

entry = NEXT_TX(entry);

1090

entry = NEXT_TX(entry);

1090

}

1091

}

1091

txd = &gp->init_block->txd[first_entry];

1092

txd = &gp->init_block->txd[first_entry];

1092

txd->buffer = cpu_to_le64(first_mapping);

1093

txd->buffer = cpu_to_le64(first_mapping);

1093

wmb();

1094

wmb();

1094

txd->control_word =

1095

txd->control_word =

1095

cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len);

1096

cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len);

1096

}

1097

}

1097

1098

gp->tx_new = entry;

1099

gp->tx_new = entry;

1099

if (unlikely(TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))) {

1100

if (unlikely(TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))) {

1100

netif_stop_queue(dev);

1101

netif_stop_queue(dev);

1101

1102

/* netif_stop_queue() must be done before checking

1103

/* netif_stop_queue() must be done before checking

1103

* checking tx index in TX_BUFFS_AVAIL() below, because

1104

* checking tx index in TX_BUFFS_AVAIL() below, because

1104

* in gem_tx(), we update tx_old before checking for

1105

* in gem_tx(), we update tx_old before checking for

1105

* netif_queue_stopped().

1106

* netif_queue_stopped().

1106

*/

1107

*/

1107

smp_mb();

1108

smp_mb();

1108

if (TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))

1109

if (TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))

1109

netif_wake_queue(dev);

1110

netif_wake_queue(dev);

1110

}

1111

}

1111

if (netif_msg_tx_queued(gp))

1112

if (netif_msg_tx_queued(gp))

1112

printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",

1113

printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",

1113

dev->name, entry, skb->len);

1114

dev->name, entry, skb->len);

1114

mb();

1115

mb();

1115

writel(gp->tx_new, gp->regs + TXDMA_KICK);

1116

writel(gp->tx_new, gp->regs + TXDMA_KICK);

1116

1117

return NETDEV_TX_OK;

1118

return NETDEV_TX_OK;

1118

}

1119

}

1119

1120

static void gem_pcs_reset(struct gem *gp)

1121

static void gem_pcs_reset(struct gem *gp)

1121

{

1122

{

1122

int limit;

1123

int limit;

1123

u32 val;

1124

u32 val;

1124

1125

/* Reset PCS unit. */

1126

/* Reset PCS unit. */

1126

val = readl(gp->regs + PCS_MIICTRL);

1127

val = readl(gp->regs + PCS_MIICTRL);

1127

val |= PCS_MIICTRL_RST;

1128

val |= PCS_MIICTRL_RST;

1128

writel(val, gp->regs + PCS_MIICTRL);

1129

writel(val, gp->regs + PCS_MIICTRL);

1129

1130

limit = 32;

1131

limit = 32;

1131

while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {

1132

while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {

1132

udelay(100);

1133

udelay(100);

1133

if (limit-- <= 0)

1134

if (limit-- <= 0)

1134

break;

1135

break;

1135

}

1136

}

1136

if (limit < 0)

1137

if (limit < 0)

1137

netdev_warn(gp->dev, "PCS reset bit would not clear\n");

1138

netdev_warn(gp->dev, "PCS reset bit would not clear\n");

1138

}

1139

}

1139

1140

static void gem_pcs_reinit_adv(struct gem *gp)

1141

static void gem_pcs_reinit_adv(struct gem *gp)

1141

{

1142

{

1142

u32 val;

1143

u32 val;

1143

1144

/* Make sure PCS is disabled while changing advertisement

1145

/* Make sure PCS is disabled while changing advertisement

1145

* configuration.

1146

* configuration.

1146

*/

1147

*/

1147

val = readl(gp->regs + PCS_CFG);

1148

val = readl(gp->regs + PCS_CFG);

1148

val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);

1149

val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);

1149

writel(val, gp->regs + PCS_CFG);

1150

writel(val, gp->regs + PCS_CFG);

1150

1151

/* Advertise all capabilities except asymmetric

1152

/* Advertise all capabilities except asymmetric

1152

* pause.

1153

* pause.

1153

*/

1154

*/

1154

val = readl(gp->regs + PCS_MIIADV);

1155

val = readl(gp->regs + PCS_MIIADV);

1155

val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |

1156

val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |

1156

PCS_MIIADV_SP | PCS_MIIADV_AP);

1157

PCS_MIIADV_SP | PCS_MIIADV_AP);

1157

writel(val, gp->regs + PCS_MIIADV);

1158

writel(val, gp->regs + PCS_MIIADV);

1158

1159

/* Enable and restart auto-negotiation, disable wrapback/loopback,

1160

/* Enable and restart auto-negotiation, disable wrapback/loopback,

1160

* and re-enable PCS.

1161

* and re-enable PCS.

1161

*/

1162

*/

1162

val = readl(gp->regs + PCS_MIICTRL);

1163

val = readl(gp->regs + PCS_MIICTRL);

1163

val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);

1164

val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);

1164

val &= ~PCS_MIICTRL_WB;

1165

val &= ~PCS_MIICTRL_WB;

1165

writel(val, gp->regs + PCS_MIICTRL);

1166

writel(val, gp->regs + PCS_MIICTRL);

1166

1167

val = readl(gp->regs + PCS_CFG);

1168

val = readl(gp->regs + PCS_CFG);

1168

val |= PCS_CFG_ENABLE;

1169

val |= PCS_CFG_ENABLE;

1169

writel(val, gp->regs + PCS_CFG);

1170

writel(val, gp->regs + PCS_CFG);

1170

1171

/* Make sure serialink loopback is off. The meaning

1172

/* Make sure serialink loopback is off. The meaning

1172

* of this bit is logically inverted based upon whether

1173

* of this bit is logically inverted based upon whether

1173

* you are in Serialink or SERDES mode.

1174

* you are in Serialink or SERDES mode.

1174

*/

1175

*/

1175

val = readl(gp->regs + PCS_SCTRL);

1176

val = readl(gp->regs + PCS_SCTRL);

1176

if (gp->phy_type == phy_serialink)

1177

if (gp->phy_type == phy_serialink)

1177

val &= ~PCS_SCTRL_LOOP;

1178

val &= ~PCS_SCTRL_LOOP;

1178

else

1179

else

1179

val |= PCS_SCTRL_LOOP;

1180

val |= PCS_SCTRL_LOOP;

1180

writel(val, gp->regs + PCS_SCTRL);

1181

writel(val, gp->regs + PCS_SCTRL);

1181

}

1182

}

1182

1183

#define STOP_TRIES 32

1184

#define STOP_TRIES 32

1184

1185

static void gem_reset(struct gem *gp)

1186

static void gem_reset(struct gem *gp)

1186

{

1187

{

1187

int limit;

1188

int limit;

1188

u32 val;

1189

u32 val;

1189

1190

/* Make sure we won't get any more interrupts */

1191

/* Make sure we won't get any more interrupts */

1191

writel(0xffffffff, gp->regs + GREG_IMASK);

1192

writel(0xffffffff, gp->regs + GREG_IMASK);

1192

1193

/* Reset the chip */

1194

/* Reset the chip */

1194

writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,

1195

writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,

1195

gp->regs + GREG_SWRST);

1196

gp->regs + GREG_SWRST);

1196

1197

limit = STOP_TRIES;

1198

limit = STOP_TRIES;

1198

1199

do {

1200

do {

1200

udelay(20);

1201

udelay(20);

1201

val = readl(gp->regs + GREG_SWRST);

1202

val = readl(gp->regs + GREG_SWRST);

1202

if (limit-- <= 0)

1203

if (limit-- <= 0)

1203

break;

1204

break;

1204

} while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));

1205

} while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));

1205

1206

if (limit < 0)

1207

if (limit < 0)

1207

netdev_err(gp->dev, "SW reset is ghetto\n");

1208

netdev_err(gp->dev, "SW reset is ghetto\n");

1208

1209

if (gp->phy_type == phy_serialink || gp->phy_type == phy_serdes)

1210

if (gp->phy_type == phy_serialink || gp->phy_type == phy_serdes)

1210

gem_pcs_reinit_adv(gp);

1211

gem_pcs_reinit_adv(gp);

1211

}

1212

}

1212

1213

static void gem_start_dma(struct gem *gp)

1214

static void gem_start_dma(struct gem *gp)

1214

{

1215

{

1215

u32 val;

1216

u32 val;

1216

1217

/* We are ready to rock, turn everything on. */

1218

/* We are ready to rock, turn everything on. */

1218

val = readl(gp->regs + TXDMA_CFG);

1219

val = readl(gp->regs + TXDMA_CFG);

1219

writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);

1220

writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);

1220

val = readl(gp->regs + RXDMA_CFG);

1221

val = readl(gp->regs + RXDMA_CFG);

1221

writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);

1222

writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);

1222

val = readl(gp->regs + MAC_TXCFG);

1223

val = readl(gp->regs + MAC_TXCFG);

1223

writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);

1224

writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);

1224

val = readl(gp->regs + MAC_RXCFG);

1225

val = readl(gp->regs + MAC_RXCFG);

1225

writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);

1226

writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);

1226

1227

(void) readl(gp->regs + MAC_RXCFG);

1228

(void) readl(gp->regs + MAC_RXCFG);

1228

udelay(100);

1229

udelay(100);

1229

1230

gem_enable_ints(gp);

1231

gem_enable_ints(gp);

1231

1232

writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);

1233

writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);

1233

}

1234

}

1234

1235

/* DMA won't be actually stopped before about 4ms tho ...

1236

/* DMA won't be actually stopped before about 4ms tho ...

1236

*/

1237

*/

1237

static void gem_stop_dma(struct gem *gp)

1238

static void gem_stop_dma(struct gem *gp)

1238

{

1239

{

1239

u32 val;

1240

u32 val;

1240

1241

/* We are done rocking, turn everything off. */

1242

/* We are done rocking, turn everything off. */

1242

val = readl(gp->regs + TXDMA_CFG);

1243

val = readl(gp->regs + TXDMA_CFG);

1243

writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);

1244

writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);

1244

val = readl(gp->regs + RXDMA_CFG);

1245

val = readl(gp->regs + RXDMA_CFG);

1245

writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);

1246

writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);

1246

val = readl(gp->regs + MAC_TXCFG);

1247

val = readl(gp->regs + MAC_TXCFG);

1247

writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);

1248

writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);

1248

val = readl(gp->regs + MAC_RXCFG);

1249

val = readl(gp->regs + MAC_RXCFG);

1249

writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);

1250

writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);

1250

1251

(void) readl(gp->regs + MAC_RXCFG);

1252

(void) readl(gp->regs + MAC_RXCFG);

1252

1253

/* Need to wait a bit ... done by the caller */

1254

/* Need to wait a bit ... done by the caller */

1254

}

1255

}

1255

1256

1257

// XXX dbl check what that function should do when called on PCS PHY

1258

// XXX dbl check what that function should do when called on PCS PHY

1258

static void gem_begin_auto_negotiation(struct gem *gp, struct ethtool_cmd *ep)

1259

static void gem_begin_auto_negotiation(struct gem *gp, struct ethtool_cmd *ep)

1259

{

1260

{

1260

u32 advertise, features;

1261

u32 advertise, features;

1261

int autoneg;

1262

int autoneg;

1262

int speed;

1263

int speed;

1263

int duplex;

1264

int duplex;

1264

1265

if (gp->phy_type != phy_mii_mdio0 &&

1266

if (gp->phy_type != phy_mii_mdio0 &&

1266

gp->phy_type != phy_mii_mdio1)

1267

gp->phy_type != phy_mii_mdio1)

1267

goto non_mii;

1268

goto non_mii;

1268

1269

/* Setup advertise */

1270

/* Setup advertise */

1270

if (found_mii_phy(gp))

1271

if (found_mii_phy(gp))

1271

features = gp->phy_mii.def->features;

1272

features = gp->phy_mii.def->features;

1272

else

1273

else

1273

features = 0;

1274

features = 0;

1274

1275

advertise = features & ADVERTISE_MASK;

1276

advertise = features & ADVERTISE_MASK;

1276

if (gp->phy_mii.advertising != 0)

1277

if (gp->phy_mii.advertising != 0)

1277

advertise &= gp->phy_mii.advertising;

1278

advertise &= gp->phy_mii.advertising;

1278

1279

autoneg = gp->want_autoneg;

1280

autoneg = gp->want_autoneg;

1280

speed = gp->phy_mii.speed;

1281

speed = gp->phy_mii.speed;

1281

duplex = gp->phy_mii.duplex;

1282

duplex = gp->phy_mii.duplex;

1282

1283

/* Setup link parameters */

1284

/* Setup link parameters */

1284

if (!ep)

1285

if (!ep)

1285

goto start_aneg;

1286

goto start_aneg;

1286

if (ep->autoneg == AUTONEG_ENABLE) {

1287

if (ep->autoneg == AUTONEG_ENABLE) {

1287

advertise = ep->advertising;

1288

advertise = ep->advertising;

1288

autoneg = 1;

1289

autoneg = 1;

1289

} else {

1290

} else {

1290

autoneg = 0;

1291

autoneg = 0;

1291

speed = ethtool_cmd_speed(ep);

1292

speed = ethtool_cmd_speed(ep);

1292

duplex = ep->duplex;

1293

duplex = ep->duplex;

1293

}

1294

}

1294

1295

start_aneg:

1296

start_aneg:

1296

/* Sanitize settings based on PHY capabilities */

1297

/* Sanitize settings based on PHY capabilities */

1297

if ((features & SUPPORTED_Autoneg) == 0)

1298

if ((features & SUPPORTED_Autoneg) == 0)

1298

autoneg = 0;

1299

autoneg = 0;

1299

if (speed == SPEED_1000 &&

1300

if (speed == SPEED_1000 &&

1300

!(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))

1301

!(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))

1301

speed = SPEED_100;

1302

speed = SPEED_100;

1302

if (speed == SPEED_100 &&

1303

if (speed == SPEED_100 &&

1303

!(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))

1304

!(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))

1304

speed = SPEED_10;

1305

speed = SPEED_10;

1305

if (duplex == DUPLEX_FULL &&

1306

if (duplex == DUPLEX_FULL &&

1306

!(features & (SUPPORTED_1000baseT_Full |

1307

!(features & (SUPPORTED_1000baseT_Full |

1307

SUPPORTED_100baseT_Full |

1308

SUPPORTED_100baseT_Full |

1308

SUPPORTED_10baseT_Full)))

1309

SUPPORTED_10baseT_Full)))

1309

duplex = DUPLEX_HALF;

1310

duplex = DUPLEX_HALF;

1310

if (speed == 0)

1311

if (speed == 0)

1311

speed = SPEED_10;

1312

speed = SPEED_10;

1312

1313

/* If we are asleep, we don't try to actually setup the PHY, we

1314

/* If we are asleep, we don't try to actually setup the PHY, we

1314

* just store the settings

1315

* just store the settings

1315

*/

1316

*/

1316

if (!netif_device_present(gp->dev)) {

1317

if (!netif_device_present(gp->dev)) {

1317

gp->phy_mii.autoneg = gp->want_autoneg = autoneg;

1318

gp->phy_mii.autoneg = gp->want_autoneg = autoneg;

1318

gp->phy_mii.speed = speed;

1319

gp->phy_mii.speed = speed;

1319

gp->phy_mii.duplex = duplex;

1320

gp->phy_mii.duplex = duplex;

1320

return;

1321

return;

1321

}

1322

}

1322

1323

/* Configure PHY & start aneg */

1324

/* Configure PHY & start aneg */

1324

gp->want_autoneg = autoneg;

1325

gp->want_autoneg = autoneg;

1325

if (autoneg) {

1326

if (autoneg) {

1326

if (found_mii_phy(gp))

1327

if (found_mii_phy(gp))

1327

gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);

1328

gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);

1328

gp->lstate = link_aneg;

1329

gp->lstate = link_aneg;

1329

} else {

1330

} else {

1330

if (found_mii_phy(gp))

1331

if (found_mii_phy(gp))

1331

gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);

1332

gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);

1332

gp->lstate = link_force_ok;

1333

gp->lstate = link_force_ok;

1333

}

1334

}

1334

1335

non_mii:

1336

non_mii:

1336

gp->timer_ticks = 0;

1337

gp->timer_ticks = 0;

1337

mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));

1338

mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));

1338

}

1339

}

1339

1340

/* A link-up condition has occurred, initialize and enable the

1341

/* A link-up condition has occurred, initialize and enable the

1341

* rest of the chip.

1342

* rest of the chip.

1342

*/

1343

*/

1343

static int gem_set_link_modes(struct gem *gp)

1344

static int gem_set_link_modes(struct gem *gp)

1344

{

1345

{

1345

struct netdev_queue *txq = netdev_get_tx_queue(gp->dev, 0);

1346

struct netdev_queue *txq = netdev_get_tx_queue(gp->dev, 0);

1346

int full_duplex, speed, pause;

1347

int full_duplex, speed, pause;

1347

u32 val;

1348

u32 val;

1348

1349

full_duplex = 0;

1350

full_duplex = 0;

1350

speed = SPEED_10;

1351

speed = SPEED_10;

1351

pause = 0;

1352

pause = 0;

1352

1353

if (found_mii_phy(gp)) {

1354

if (found_mii_phy(gp)) {

1354

if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))

1355

if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))

1355

return 1;

1356

return 1;

1356

full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);

1357

full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);

1357

speed = gp->phy_mii.speed;

1358

speed = gp->phy_mii.speed;

1358

pause = gp->phy_mii.pause;

1359

pause = gp->phy_mii.pause;

1359

} else if (gp->phy_type == phy_serialink ||

1360

} else if (gp->phy_type == phy_serialink ||

1360

gp->phy_type == phy_serdes) {

1361

gp->phy_type == phy_serdes) {

1361

u32 pcs_lpa = readl(gp->regs + PCS_MIILP);

1362

u32 pcs_lpa = readl(gp->regs + PCS_MIILP);

1362

1363

if ((pcs_lpa & PCS_MIIADV_FD) || gp->phy_type == phy_serdes)

1364

if ((pcs_lpa & PCS_MIIADV_FD) || gp->phy_type == phy_serdes)

1364

full_duplex = 1;

1365

full_duplex = 1;

1365

speed = SPEED_1000;

1366

speed = SPEED_1000;

1366

}

1367

}

1367

1368

netif_info(gp, link, gp->dev, "Link is up at %d Mbps, %s-duplex\n",

1369

netif_info(gp, link, gp->dev, "Link is up at %d Mbps, %s-duplex\n",

1369

speed, (full_duplex ? "full" : "half"));

1370

speed, (full_duplex ? "full" : "half"));

1370

1371

1372

/* We take the tx queue lock to avoid collisions between

1373

/* We take the tx queue lock to avoid collisions between

1373

* this code, the tx path and the NAPI-driven error path

1374

* this code, the tx path and the NAPI-driven error path

1374

*/

1375

*/

1375

__netif_tx_lock(txq, smp_processor_id());

1376

__netif_tx_lock(txq, smp_processor_id());

1376

1377

val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);

1378

val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);

1378

if (full_duplex) {

1379

if (full_duplex) {

1379

val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);

1380

val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);

1380

} else {

1381

} else {

1381

/* MAC_TXCFG_NBO must be zero. */

1382

/* MAC_TXCFG_NBO must be zero. */

1382

}

1383

}

1383

writel(val, gp->regs + MAC_TXCFG);

1384

writel(val, gp->regs + MAC_TXCFG);

1384

1385

val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);

1386

val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);

1386

if (!full_duplex &&

1387

if (!full_duplex &&

1387

(gp->phy_type == phy_mii_mdio0 ||

1388

(gp->phy_type == phy_mii_mdio0 ||

1388

gp->phy_type == phy_mii_mdio1)) {

1389

gp->phy_type == phy_mii_mdio1)) {

1389

val |= MAC_XIFCFG_DISE;

1390

val |= MAC_XIFCFG_DISE;

1390

} else if (full_duplex) {

1391

} else if (full_duplex) {

1391

val |= MAC_XIFCFG_FLED;

1392

val |= MAC_XIFCFG_FLED;

1392

}

1393

}

1393

1394

if (speed == SPEED_1000)

1395

if (speed == SPEED_1000)

1395

val |= (MAC_XIFCFG_GMII);

1396

val |= (MAC_XIFCFG_GMII);

1396

1397

writel(val, gp->regs + MAC_XIFCFG);

1398

writel(val, gp->regs + MAC_XIFCFG);

1398

1399

/* If gigabit and half-duplex, enable carrier extension

1400

/* If gigabit and half-duplex, enable carrier extension

1400

* mode. Else, disable it.

1401

* mode. Else, disable it.

1401

*/

1402

*/

1402

if (speed == SPEED_1000 && !full_duplex) {

1403

if (speed == SPEED_1000 && !full_duplex) {

1403

val = readl(gp->regs + MAC_TXCFG);

1404

val = readl(gp->regs + MAC_TXCFG);

1404

writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);

1405

writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);

1405

1406

val = readl(gp->regs + MAC_RXCFG);

1407

val = readl(gp->regs + MAC_RXCFG);

1407

writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);

1408

writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);

1408

} else {

1409

} else {

1409

val = readl(gp->regs + MAC_TXCFG);

1410

val = readl(gp->regs + MAC_TXCFG);

1410

writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);

1411

writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);

1411

1412

val = readl(gp->regs + MAC_RXCFG);

1413

val = readl(gp->regs + MAC_RXCFG);

1413

writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);

1414

writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);

1414

}

1415

}

1415

1416

if (gp->phy_type == phy_serialink ||

1417

if (gp->phy_type == phy_serialink ||

1417

gp->phy_type == phy_serdes) {

1418

gp->phy_type == phy_serdes) {

1418

u32 pcs_lpa = readl(gp->regs + PCS_MIILP);

1419

u32 pcs_lpa = readl(gp->regs + PCS_MIILP);

1419

1420

if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))

1421

if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))

1421

pause = 1;

1422

pause = 1;

1422

}

1423

}

1423

1424

if (!full_duplex)

1425

if (!full_duplex)

1425

writel(512, gp->regs + MAC_STIME);

1426

writel(512, gp->regs + MAC_STIME);

1426

else

1427

else

1427

writel(64, gp->regs + MAC_STIME);

1428

writel(64, gp->regs + MAC_STIME);

1428

val = readl(gp->regs + MAC_MCCFG);

1429

val = readl(gp->regs + MAC_MCCFG);

1429

if (pause)

1430

if (pause)

1430

val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);

1431

val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);

1431

else

1432

else

1432

val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);

1433

val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);

1433

writel(val, gp->regs + MAC_MCCFG);

1434

writel(val, gp->regs + MAC_MCCFG);

1434

1435

gem_start_dma(gp);

1436

gem_start_dma(gp);

1436

1437

__netif_tx_unlock(txq);

1438

__netif_tx_unlock(txq);

1438

1439

if (netif_msg_link(gp)) {

1440

if (netif_msg_link(gp)) {

1440

if (pause) {

1441

if (pause) {

1441

netdev_info(gp->dev,

1442

netdev_info(gp->dev,

1442

"Pause is enabled (rxfifo: %d off: %d on: %d)\n",

1443

"Pause is enabled (rxfifo: %d off: %d on: %d)\n",

1443

gp->rx_fifo_sz,

1444

gp->rx_fifo_sz,

1444

gp->rx_pause_off,

1445

gp->rx_pause_off,

1445

gp->rx_pause_on);

1446

gp->rx_pause_on);

1446

} else {

1447

} else {

1447

netdev_info(gp->dev, "Pause is disabled\n");

1448

netdev_info(gp->dev, "Pause is disabled\n");

1448

}

1449

}

1449

}

1450

}

1450

1451

return 0;

1452

return 0;

1452

}

1453

}

1453

1454

static int gem_mdio_link_not_up(struct gem *gp)

1455

static int gem_mdio_link_not_up(struct gem *gp)

1455

{

1456

{

1456

switch (gp->lstate) {

1457

switch (gp->lstate) {

1457

case link_force_ret:

1458

case link_force_ret:

1458

netif_info(gp, link, gp->dev,

1459

netif_info(gp, link, gp->dev,

1459

"Autoneg failed again, keeping forced mode\n");

1460

"Autoneg failed again, keeping forced mode\n");

1460

gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,

1461

gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,

1461

gp->last_forced_speed, DUPLEX_HALF);

1462

gp->last_forced_speed, DUPLEX_HALF);

1462

gp->timer_ticks = 5;

1463

gp->timer_ticks = 5;

1463

gp->lstate = link_force_ok;

1464

gp->lstate = link_force_ok;

1464

return 0;

1465

return 0;

1465

case link_aneg:

1466

case link_aneg:

1466

/* We try forced modes after a failed aneg only on PHYs that don't

1467

/* We try forced modes after a failed aneg only on PHYs that don't

1467

* have "magic_aneg" bit set, which means they internally do the

1468

* have "magic_aneg" bit set, which means they internally do the

1468

* while forced-mode thingy. On these, we just restart aneg

1469

* while forced-mode thingy. On these, we just restart aneg

1469

*/

1470

*/

1470

if (gp->phy_mii.def->magic_aneg)

1471

if (gp->phy_mii.def->magic_aneg)

1471

return 1;

1472

return 1;

1472

netif_info(gp, link, gp->dev, "switching to forced 100bt\n");

1473

netif_info(gp, link, gp->dev, "switching to forced 100bt\n");

1473

/* Try forced modes. */

1474

/* Try forced modes. */

1474

gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,

1475

gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,

1475

DUPLEX_HALF);

1476

DUPLEX_HALF);

1476

gp->timer_ticks = 5;

1477

gp->timer_ticks = 5;

1477

gp->lstate = link_force_try;

1478

gp->lstate = link_force_try;

1478

return 0;

1479

return 0;

1479

case link_force_try:

1480

case link_force_try:

1480

/* Downgrade from 100 to 10 Mbps if necessary.

1481

/* Downgrade from 100 to 10 Mbps if necessary.

1481

* If already at 10Mbps, warn user about the

1482

* If already at 10Mbps, warn user about the

1482

* situation every 10 ticks.

1483

* situation every 10 ticks.

1483

*/

1484

*/

1484

if (gp->phy_mii.speed == SPEED_100) {

1485

if (gp->phy_mii.speed == SPEED_100) {

1485

gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,

1486

gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,

1486

DUPLEX_HALF);

1487

DUPLEX_HALF);

1487

gp->timer_ticks = 5;

1488

gp->timer_ticks = 5;

1488

netif_info(gp, link, gp->dev,

1489

netif_info(gp, link, gp->dev,

1489

"switching to forced 10bt\n");

1490

"switching to forced 10bt\n");

1490

return 0;

1491

return 0;

1491

} else

1492

} else

1492

return 1;

1493

return 1;

1493

default:

1494

default:

1494

return 0;

1495

return 0;

1495

}

1496

}

1496

}

1497

}

1497

1498

static void gem_link_timer(unsigned long data)

1499

static void gem_link_timer(unsigned long data)

1499

{

1500

{

1500

struct gem *gp = (struct gem *) data;

1501

struct gem *gp = (struct gem *) data;

1501

struct net_device *dev = gp->dev;

1502

struct net_device *dev = gp->dev;

1502

int restart_aneg = 0;

1503

int restart_aneg = 0;

1503

1504

/* There's no point doing anything if we're going to be reset */

1505

/* There's no point doing anything if we're going to be reset */

1505

if (gp->reset_task_pending)

1506

if (gp->reset_task_pending)

1506

return;

1507

return;

1507

1508

if (gp->phy_type == phy_serialink ||

1509

if (gp->phy_type == phy_serialink ||

1509

gp->phy_type == phy_serdes) {

1510

gp->phy_type == phy_serdes) {

1510

u32 val = readl(gp->regs + PCS_MIISTAT);

1511

u32 val = readl(gp->regs + PCS_MIISTAT);

1511

1512

if (!(val & PCS_MIISTAT_LS))

1513

if (!(val & PCS_MIISTAT_LS))

1513

val = readl(gp->regs + PCS_MIISTAT);

1514

val = readl(gp->regs + PCS_MIISTAT);

1514

1515

if ((val & PCS_MIISTAT_LS) != 0) {

1516

if ((val & PCS_MIISTAT_LS) != 0) {

1516

if (gp->lstate == link_up)

1517

if (gp->lstate == link_up)

1517

goto restart;

1518

goto restart;

1518

1519

gp->lstate = link_up;

1520

gp->lstate = link_up;

1520

netif_carrier_on(dev);

1521

netif_carrier_on(dev);

1521

(void)gem_set_link_modes(gp);

1522

(void)gem_set_link_modes(gp);

1522

}

1523

}

1523

goto restart;

1524

goto restart;

1524

}

1525

}

1525

if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {

1526

if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {

1526

/* Ok, here we got a link. If we had it due to a forced

1527

/* Ok, here we got a link. If we had it due to a forced

1527

* fallback, and we were configured for autoneg, we do

1528

* fallback, and we were configured for autoneg, we do

1528

* retry a short autoneg pass. If you know your hub is

1529

* retry a short autoneg pass. If you know your hub is

1529

* broken, use ethtool ;)

1530

* broken, use ethtool ;)

1530

*/

1531

*/

1531

if (gp->lstate == link_force_try && gp->want_autoneg) {

1532

if (gp->lstate == link_force_try && gp->want_autoneg) {

1532

gp->lstate = link_force_ret;

1533

gp->lstate = link_force_ret;

1533

gp->last_forced_speed = gp->phy_mii.speed;

1534

gp->last_forced_speed = gp->phy_mii.speed;

1534

gp->timer_ticks = 5;

1535

gp->timer_ticks = 5;

1535

if (netif_msg_link(gp))

1536

if (netif_msg_link(gp))

1536

netdev_info(dev,

1537

netdev_info(dev,

1537

"Got link after fallback, retrying autoneg once...\n");

1538

"Got link after fallback, retrying autoneg once...\n");

1538

gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);

1539

gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);

1539

} else if (gp->lstate != link_up) {

1540

} else if (gp->lstate != link_up) {

1540

gp->lstate = link_up;

1541

gp->lstate = link_up;

1541

netif_carrier_on(dev);

1542

netif_carrier_on(dev);

1542

if (gem_set_link_modes(gp))

1543

if (gem_set_link_modes(gp))

1543

restart_aneg = 1;

1544

restart_aneg = 1;

1544

}

1545

}

1545

} else {

1546

} else {

1546

/* If the link was previously up, we restart the

1547

/* If the link was previously up, we restart the

1547

* whole process

1548

* whole process

1548

*/

1549

*/

1549

if (gp->lstate == link_up) {

1550

if (gp->lstate == link_up) {

1550

gp->lstate = link_down;

1551

gp->lstate = link_down;

1551

netif_info(gp, link, dev, "Link down\n");

1552

netif_info(gp, link, dev, "Link down\n");

1552

netif_carrier_off(dev);

1553

netif_carrier_off(dev);

1553

gem_schedule_reset(gp);

1554

gem_schedule_reset(gp);

1554

/* The reset task will restart the timer */

1555

/* The reset task will restart the timer */

1555

return;

1556

return;

1556

} else if (++gp->timer_ticks > 10) {

1557

} else if (++gp->timer_ticks > 10) {

1557

if (found_mii_phy(gp))

1558

if (found_mii_phy(gp))

1558

restart_aneg = gem_mdio_link_not_up(gp);

1559

restart_aneg = gem_mdio_link_not_up(gp);

1559

else

1560

else

1560

restart_aneg = 1;

1561

restart_aneg = 1;

1561

}

1562

}

1562

}

1563

}

1563

if (restart_aneg) {

1564

if (restart_aneg) {

1564

gem_begin_auto_negotiation(gp, NULL);

1565

gem_begin_auto_negotiation(gp, NULL);

1565

return;

1566

return;

1566

}

1567

}

1567

restart:

1568

restart:

1568

mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));

1569

mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));

1569

}

1570

}

1570

1571

static void gem_clean_rings(struct gem *gp)

1572

static void gem_clean_rings(struct gem *gp)

1572

{

1573

{

1573

struct gem_init_block *gb = gp->init_block;

1574

struct gem_init_block *gb = gp->init_block;

1574

struct sk_buff *skb;

1575

struct sk_buff *skb;

1575

int i;

1576

int i;

1576

dma_addr_t dma_addr;

1577

dma_addr_t dma_addr;

1577

1578

for (i = 0; i < RX_RING_SIZE; i++) {

1579

for (i = 0; i < RX_RING_SIZE; i++) {

1579

struct gem_rxd *rxd;

1580

struct gem_rxd *rxd;

1580

1581

rxd = &gb->rxd[i];

1582

rxd = &gb->rxd[i];

1582

if (gp->rx_skbs[i] != NULL) {

1583

if (gp->rx_skbs[i] != NULL) {

1583

skb = gp->rx_skbs[i];

1584

skb = gp->rx_skbs[i];

1584

dma_addr = le64_to_cpu(rxd->buffer);

1585

dma_addr = le64_to_cpu(rxd->buffer);

1585

pci_unmap_page(gp->pdev, dma_addr,

1586

pci_unmap_page(gp->pdev, dma_addr,

1586

RX_BUF_ALLOC_SIZE(gp),

1587

RX_BUF_ALLOC_SIZE(gp),

1587

PCI_DMA_FROMDEVICE);

1588

PCI_DMA_FROMDEVICE);

1588

dev_kfree_skb_any(skb);

1589

dev_kfree_skb_any(skb);

1589

gp->rx_skbs[i] = NULL;

1590

gp->rx_skbs[i] = NULL;

1590

}

1591

}

1591

rxd->status_word = 0;

1592

rxd->status_word = 0;

1592

wmb();

1593

wmb();

1593

rxd->buffer = 0;

1594

rxd->buffer = 0;

1594

}

1595

}

1595

1596

for (i = 0; i < TX_RING_SIZE; i++) {

1597

for (i = 0; i < TX_RING_SIZE; i++) {

1597

if (gp->tx_skbs[i] != NULL) {

1598

if (gp->tx_skbs[i] != NULL) {

1598

struct gem_txd *txd;

1599

struct gem_txd *txd;

1599

int frag;

1600

int frag;

1600

1601

skb = gp->tx_skbs[i];

1602

skb = gp->tx_skbs[i];

1602

gp->tx_skbs[i] = NULL;

1603

gp->tx_skbs[i] = NULL;

1603

1604

for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {

1605

for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {

1605

int ent = i & (TX_RING_SIZE - 1);

1606

int ent = i & (TX_RING_SIZE - 1);

1606

1607

txd = &gb->txd[ent];

1608

txd = &gb->txd[ent];

1608

dma_addr = le64_to_cpu(txd->buffer);

1609

dma_addr = le64_to_cpu(txd->buffer);

1609

pci_unmap_page(gp->pdev, dma_addr,

1610

pci_unmap_page(gp->pdev, dma_addr,

1610

le64_to_cpu(txd->control_word) &

1611

le64_to_cpu(txd->control_word) &

1611

TXDCTRL_BUFSZ, PCI_DMA_TODEVICE);

1612

TXDCTRL_BUFSZ, PCI_DMA_TODEVICE);

1612

1613

if (frag != skb_shinfo(skb)->nr_frags)

1614

if (frag != skb_shinfo(skb)->nr_frags)

1614

i++;

1615

i++;

1615

}

1616

}

1616

dev_kfree_skb_any(skb);

1617

dev_kfree_skb_any(skb);

1617

}

1618

}

1618

}

1619

}

1619

}

1620

}

1620

1621

static void gem_init_rings(struct gem *gp)

1622

static void gem_init_rings(struct gem *gp)

1622

{

1623

{

1623

struct gem_init_block *gb = gp->init_block;

1624

struct gem_init_block *gb = gp->init_block;

1624

struct net_device *dev = gp->dev;

1625

struct net_device *dev = gp->dev;

1625

int i;

1626

int i;

1626

dma_addr_t dma_addr;

1627

dma_addr_t dma_addr;

1627

1628

gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;

1629

gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;

1629

1630

gem_clean_rings(gp);

1631

gem_clean_rings(gp);

1631

1632

gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN,

1633

gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN,

1633

(unsigned)VLAN_ETH_FRAME_LEN);

1634

(unsigned)VLAN_ETH_FRAME_LEN);

1634

1635

for (i = 0; i < RX_RING_SIZE; i++) {

1636

for (i = 0; i < RX_RING_SIZE; i++) {

1636

struct sk_buff *skb;

1637

struct sk_buff *skb;

1637

struct gem_rxd *rxd = &gb->rxd[i];

1638

struct gem_rxd *rxd = &gb->rxd[i];

1638

1639

skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_KERNEL);

1640

skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_KERNEL);

1640

if (!skb) {

1641

if (!skb) {

1641

rxd->buffer = 0;

1642

rxd->buffer = 0;

1642

rxd->status_word = 0;

1643

rxd->status_word = 0;

1643

continue;

1644

continue;

1644

}

1645

}

1645

1646

gp->rx_skbs[i] = skb;

1647

gp->rx_skbs[i] = skb;

1647

skb_put(skb, (gp->rx_buf_sz + RX_OFFSET));

1648

skb_put(skb, (gp->rx_buf_sz + RX_OFFSET));

1648

dma_addr = pci_map_page(gp->pdev,

1649

dma_addr = pci_map_page(gp->pdev,

1649

virt_to_page(skb->data),

1650

virt_to_page(skb->data),

1650

offset_in_page(skb->data),

1651

offset_in_page(skb->data),

1651

RX_BUF_ALLOC_SIZE(gp),

1652

RX_BUF_ALLOC_SIZE(gp),

1652

PCI_DMA_FROMDEVICE);

1653

PCI_DMA_FROMDEVICE);

1653

rxd->buffer = cpu_to_le64(dma_addr);

1654

rxd->buffer = cpu_to_le64(dma_addr);

1654

wmb();

1655

wmb();

1655

rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));

1656

rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));

1656

skb_reserve(skb, RX_OFFSET);

1657

skb_reserve(skb, RX_OFFSET);

1657

}

1658

}

1658

1659

for (i = 0; i < TX_RING_SIZE; i++) {

1660

for (i = 0; i < TX_RING_SIZE; i++) {

1660

struct gem_txd *txd = &gb->txd[i];

1661

struct gem_txd *txd = &gb->txd[i];

1661

1662

txd->control_word = 0;

1663

txd->control_word = 0;

1663

wmb();

1664

wmb();

1664

txd->buffer = 0;

1665

txd->buffer = 0;

1665

}

1666

}

1666

wmb();

1667

wmb();

1667

}

1668

}

1668

1669

/* Init PHY interface and start link poll state machine */

1670

/* Init PHY interface and start link poll state machine */

1670

static void gem_init_phy(struct gem *gp)

1671

static void gem_init_phy(struct gem *gp)

1671

{

1672

{

1672

u32 mifcfg;

1673

u32 mifcfg;

1673

1674

/* Revert MIF CFG setting done on stop_phy */

1675

/* Revert MIF CFG setting done on stop_phy */

1675

mifcfg = readl(gp->regs + MIF_CFG);

1676

mifcfg = readl(gp->regs + MIF_CFG);

1676

mifcfg &= ~MIF_CFG_BBMODE;

1677

mifcfg &= ~MIF_CFG_BBMODE;

1677

writel(mifcfg, gp->regs + MIF_CFG);

1678

writel(mifcfg, gp->regs + MIF_CFG);

1678

1679

if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {

1680

if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {

1680

int i;

1681

int i;

1681

1682

/* Those delay sucks, the HW seem to love them though, I'll

1683

/* Those delay sucks, the HW seem to love them though, I'll

1683

* serisouly consider breaking some locks here to be able

1684

* serisouly consider breaking some locks here to be able

1684

* to schedule instead

1685

* to schedule instead

1685

*/

1686

*/

1686

for (i = 0; i < 3; i++) {

1687

for (i = 0; i < 3; i++) {

1687

#ifdef CONFIG_PPC_PMAC

1688

#ifdef CONFIG_PPC_PMAC

1688

pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);

1689

pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);

1689

msleep(20);

1690

msleep(20);

1690

#endif

1691

#endif

1691

/* Some PHYs used by apple have problem getting back to us,

1692

/* Some PHYs used by apple have problem getting back to us,

1692

* we do an additional reset here

1693

* we do an additional reset here

1693

*/

1694

*/

1694

phy_write(gp, MII_BMCR, BMCR_RESET);

1695

phy_write(gp, MII_BMCR, BMCR_RESET);

1695

msleep(20);

1696

msleep(20);

1696

if (phy_read(gp, MII_BMCR) != 0xffff)

1697

if (phy_read(gp, MII_BMCR) != 0xffff)

1697

break;

1698

break;

1698

if (i == 2)

1699

if (i == 2)

1699

netdev_warn(gp->dev, "GMAC PHY not responding !\n");

1700

netdev_warn(gp->dev, "GMAC PHY not responding !\n");

1700

}

1701

}

1701

}

1702

}

1702

1703

if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&

1704

if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&

1704

gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {

1705

gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {

1705

u32 val;

1706

u32 val;

1706

1707

/* Init datapath mode register. */

1708

/* Init datapath mode register. */

1708

if (gp->phy_type == phy_mii_mdio0 ||

1709

if (gp->phy_type == phy_mii_mdio0 ||

1709

gp->phy_type == phy_mii_mdio1) {

1710

gp->phy_type == phy_mii_mdio1) {

1710

val = PCS_DMODE_MGM;

1711

val = PCS_DMODE_MGM;

1711

} else if (gp->phy_type == phy_serialink) {

1712

} else if (gp->phy_type == phy_serialink) {

1712

val = PCS_DMODE_SM | PCS_DMODE_GMOE;

1713

val = PCS_DMODE_SM | PCS_DMODE_GMOE;

1713

} else {

1714

} else {

1714

val = PCS_DMODE_ESM;

1715

val = PCS_DMODE_ESM;

1715

}

1716

}

1716

1717

writel(val, gp->regs + PCS_DMODE);

1718

writel(val, gp->regs + PCS_DMODE);

1718

}

1719

}

1719

1720

if (gp->phy_type == phy_mii_mdio0 ||

1721

if (gp->phy_type == phy_mii_mdio0 ||

1721

gp->phy_type == phy_mii_mdio1) {

1722

gp->phy_type == phy_mii_mdio1) {

1722

/* Reset and detect MII PHY */

1723

/* Reset and detect MII PHY */

1723

mii_phy_probe(&gp->phy_mii, gp->mii_phy_addr);

1724

mii_phy_probe(&gp->phy_mii, gp->mii_phy_addr);

1724

1725

/* Init PHY */

1726

/* Init PHY */

1726

if (gp->phy_mii.def && gp->phy_mii.def->ops->init)

1727

if (gp->phy_mii.def && gp->phy_mii.def->ops->init)

1727

gp->phy_mii.def->ops->init(&gp->phy_mii);

1728

gp->phy_mii.def->ops->init(&gp->phy_mii);

1728

} else {

1729

} else {

1729

gem_pcs_reset(gp);

1730

gem_pcs_reset(gp);

1730

gem_pcs_reinit_adv(gp);

1731

gem_pcs_reinit_adv(gp);

1731

}

1732

}

1732

1733

/* Default aneg parameters */

1734

/* Default aneg parameters */

1734

gp->timer_ticks = 0;

1735

gp->timer_ticks = 0;

1735

gp->lstate = link_down;

1736

gp->lstate = link_down;

1736

netif_carrier_off(gp->dev);

1737

netif_carrier_off(gp->dev);

1737

1738

/* Print things out */

1739

/* Print things out */

1739

if (gp->phy_type == phy_mii_mdio0 ||

1740

if (gp->phy_type == phy_mii_mdio0 ||

1740

gp->phy_type == phy_mii_mdio1)

1741

gp->phy_type == phy_mii_mdio1)

1741

netdev_info(gp->dev, "Found %s PHY\n",

1742

netdev_info(gp->dev, "Found %s PHY\n",

1742

gp->phy_mii.def ? gp->phy_mii.def->name : "no");

1743

gp->phy_mii.def ? gp->phy_mii.def->name : "no");

1743

1744

gem_begin_auto_negotiation(gp, NULL);

1745

gem_begin_auto_negotiation(gp, NULL);

1745

}

1746

}

1746

1747

static void gem_init_dma(struct gem *gp)

1748

static void gem_init_dma(struct gem *gp)

1748

{

1749

{

1749

u64 desc_dma = (u64) gp->gblock_dvma;

1750

u64 desc_dma = (u64) gp->gblock_dvma;

1750

u32 val;

1751

u32 val;

1751

1752

val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);

1753

val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);

1753

writel(val, gp->regs + TXDMA_CFG);

1754

writel(val, gp->regs + TXDMA_CFG);

1754

1755

writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);

1756

writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);

1756

writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);

1757

writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);

1757

desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));

1758

desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));

1758

1759

writel(0, gp->regs + TXDMA_KICK);

1760

writel(0, gp->regs + TXDMA_KICK);

1760

1761

val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |

1762

val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |

1762

((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);

1763

((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);

1763

writel(val, gp->regs + RXDMA_CFG);

1764

writel(val, gp->regs + RXDMA_CFG);

1764

1765

writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);

1766

writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);

1766

writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);

1767

writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);

1767

1768

writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);

1769

writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);

1769

1770

val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);

1771

val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);

1771

val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);

1772

val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);

1772

writel(val, gp->regs + RXDMA_PTHRESH);

1773

writel(val, gp->regs + RXDMA_PTHRESH);

1773

1774

if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)

1775

if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)

1775

writel(((5 & RXDMA_BLANK_IPKTS) |

1776

writel(((5 & RXDMA_BLANK_IPKTS) |

1776

((8 << 12) & RXDMA_BLANK_ITIME)),

1777

((8 << 12) & RXDMA_BLANK_ITIME)),

1777

gp->regs + RXDMA_BLANK);

1778

gp->regs + RXDMA_BLANK);

1778

else

1779

else

1779

writel(((5 & RXDMA_BLANK_IPKTS) |

1780

writel(((5 & RXDMA_BLANK_IPKTS) |

1780

((4 << 12) & RXDMA_BLANK_ITIME)),

1781

((4 << 12) & RXDMA_BLANK_ITIME)),

1781

gp->regs + RXDMA_BLANK);

1782

gp->regs + RXDMA_BLANK);

1782

}

1783

}

1783

1784

static u32 gem_setup_multicast(struct gem *gp)

1785

static u32 gem_setup_multicast(struct gem *gp)

1785

{

1786

{

1786

u32 rxcfg = 0;

1787

u32 rxcfg = 0;

1787

int i;

1788

int i;

1788

1789

if ((gp->dev->flags & IFF_ALLMULTI) ||

1790

if ((gp->dev->flags & IFF_ALLMULTI) ||

1790

(netdev_mc_count(gp->dev) > 256)) {

1791

(netdev_mc_count(gp->dev) > 256)) {

1791

for (i=0; i<16; i++)

1792

for (i=0; i<16; i++)

1792

writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));

1793

writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));

1793

rxcfg |= MAC_RXCFG_HFE;

1794

rxcfg |= MAC_RXCFG_HFE;

1794

} else if (gp->dev->flags & IFF_PROMISC) {

1795

} else if (gp->dev->flags & IFF_PROMISC) {

1795

rxcfg |= MAC_RXCFG_PROM;

1796

rxcfg |= MAC_RXCFG_PROM;

1796

} else {

1797

} else {

1797

u16 hash_table[16];

1798

u16 hash_table[16];

1798

u32 crc;

1799

u32 crc;

1799

struct netdev_hw_addr *ha;

1800

struct netdev_hw_addr *ha;

1800

int i;

1801

int i;

1801

1802

memset(hash_table, 0, sizeof(hash_table));

1803

memset(hash_table, 0, sizeof(hash_table));

1803

netdev_for_each_mc_addr(ha, gp->dev) {

1804

netdev_for_each_mc_addr(ha, gp->dev) {

1804

crc = ether_crc_le(6, ha->addr);

1805

crc = ether_crc_le(6, ha->addr);

1805

crc >>= 24;

1806

crc >>= 24;

1806

hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));

1807

hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));

1807

}

1808

}

1808

for (i=0; i<16; i++)

1809

for (i=0; i<16; i++)

1809

writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));

1810

writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));

1810

rxcfg |= MAC_RXCFG_HFE;

1811

rxcfg |= MAC_RXCFG_HFE;

1811

}

1812

}

1812

1813

return rxcfg;

1814

return rxcfg;

1814

}

1815

}

1815

1816

static void gem_init_mac(struct gem *gp)

1817

static void gem_init_mac(struct gem *gp)

1817

{

1818

{

1818

unsigned char *e = &gp->dev->dev_addr[0];

1819

unsigned char *e = &gp->dev->dev_addr[0];

1819

1820

writel(0x1bf0, gp->regs + MAC_SNDPAUSE);

1821

writel(0x1bf0, gp->regs + MAC_SNDPAUSE);

1821

1822

writel(0x00, gp->regs + MAC_IPG0);

1823

writel(0x00, gp->regs + MAC_IPG0);

1823

writel(0x08, gp->regs + MAC_IPG1);

1824

writel(0x08, gp->regs + MAC_IPG1);

1824

writel(0x04, gp->regs + MAC_IPG2);

1825

writel(0x04, gp->regs + MAC_IPG2);

1825

writel(0x40, gp->regs + MAC_STIME);

1826

writel(0x40, gp->regs + MAC_STIME);

1826

writel(0x40, gp->regs + MAC_MINFSZ);

1827

writel(0x40, gp->regs + MAC_MINFSZ);

1827

1828

/* Ethernet payload + header + FCS + optional VLAN tag. */

1829

/* Ethernet payload + header + FCS + optional VLAN tag. */

1829

writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);

1830

writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);

1830

1831

writel(0x07, gp->regs + MAC_PASIZE);

1832

writel(0x07, gp->regs + MAC_PASIZE);

1832

writel(0x04, gp->regs + MAC_JAMSIZE);

1833

writel(0x04, gp->regs + MAC_JAMSIZE);

1833

writel(0x10, gp->regs + MAC_ATTLIM);

1834

writel(0x10, gp->regs + MAC_ATTLIM);

1834

writel(0x8808, gp->regs + MAC_MCTYPE);

1835

writel(0x8808, gp->regs + MAC_MCTYPE);

1835

1836

writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);

1837

writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);

1837

1838

writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);

1839

writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);

1839

writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);

1840

writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);

1840

writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);

1841

writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);

1841

1842

writel(0, gp->regs + MAC_ADDR3);

1843

writel(0, gp->regs + MAC_ADDR3);

1843

writel(0, gp->regs + MAC_ADDR4);

1844

writel(0, gp->regs + MAC_ADDR4);

1844

writel(0, gp->regs + MAC_ADDR5);

1845

writel(0, gp->regs + MAC_ADDR5);

1845

1846

writel(0x0001, gp->regs + MAC_ADDR6);

1847

writel(0x0001, gp->regs + MAC_ADDR6);

1847

writel(0xc200, gp->regs + MAC_ADDR7);

1848

writel(0xc200, gp->regs + MAC_ADDR7);

1848

writel(0x0180, gp->regs + MAC_ADDR8);

1849

writel(0x0180, gp->regs + MAC_ADDR8);

1849

1850

writel(0, gp->regs + MAC_AFILT0);

1851

writel(0, gp->regs + MAC_AFILT0);

1851

writel(0, gp->regs + MAC_AFILT1);

1852

writel(0, gp->regs + MAC_AFILT1);

1852

writel(0, gp->regs + MAC_AFILT2);

1853

writel(0, gp->regs + MAC_AFILT2);

1853

writel(0, gp->regs + MAC_AF21MSK);

1854

writel(0, gp->regs + MAC_AF21MSK);

1854

writel(0, gp->regs + MAC_AF0MSK);

1855

writel(0, gp->regs + MAC_AF0MSK);

1855

1856

gp->mac_rx_cfg = gem_setup_multicast(gp);

1857

gp->mac_rx_cfg = gem_setup_multicast(gp);

1857

#ifdef STRIP_FCS

1858

#ifdef STRIP_FCS

1858

gp->mac_rx_cfg |= MAC_RXCFG_SFCS;

1859

gp->mac_rx_cfg |= MAC_RXCFG_SFCS;

1859

#endif

1860

#endif

1860

writel(0, gp->regs + MAC_NCOLL);

1861

writel(0, gp->regs + MAC_NCOLL);

1861

writel(0, gp->regs + MAC_FASUCC);

1862

writel(0, gp->regs + MAC_FASUCC);

1862

writel(0, gp->regs + MAC_ECOLL);

1863

writel(0, gp->regs + MAC_ECOLL);

1863

writel(0, gp->regs + MAC_LCOLL);

1864

writel(0, gp->regs + MAC_LCOLL);

1864

writel(0, gp->regs + MAC_DTIMER);

1865

writel(0, gp->regs + MAC_DTIMER);

1865

writel(0, gp->regs + MAC_PATMPS);

1866

writel(0, gp->regs + MAC_PATMPS);

1866

writel(0, gp->regs + MAC_RFCTR);

1867

writel(0, gp->regs + MAC_RFCTR);

1867

writel(0, gp->regs + MAC_LERR);

1868

writel(0, gp->regs + MAC_LERR);

1868

writel(0, gp->regs + MAC_AERR);

1869

writel(0, gp->regs + MAC_AERR);

1869

writel(0, gp->regs + MAC_FCSERR);

1870

writel(0, gp->regs + MAC_FCSERR);

1870

writel(0, gp->regs + MAC_RXCVERR);

1871

writel(0, gp->regs + MAC_RXCVERR);

1871

1872

/* Clear RX/TX/MAC/XIF config, we will set these up and enable

1873

/* Clear RX/TX/MAC/XIF config, we will set these up and enable

1873

* them once a link is established.

1874

* them once a link is established.

1874

*/

1875

*/

1875

writel(0, gp->regs + MAC_TXCFG);

1876

writel(0, gp->regs + MAC_TXCFG);

1876

writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);

1877

writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);

1877

writel(0, gp->regs + MAC_MCCFG);

1878

writel(0, gp->regs + MAC_MCCFG);

1878

writel(0, gp->regs + MAC_XIFCFG);

1879

writel(0, gp->regs + MAC_XIFCFG);

1879

1880

/* Setup MAC interrupts. We want to get all of the interesting

1881

/* Setup MAC interrupts. We want to get all of the interesting

1881

* counter expiration events, but we do not want to hear about

1882

* counter expiration events, but we do not want to hear about

1882

* normal rx/tx as the DMA engine tells us that.

1883

* normal rx/tx as the DMA engine tells us that.

1883

*/

1884

*/

1884

writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);

1885

writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);

1885

writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);

1886

writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);

1886

1887

/* Don't enable even the PAUSE interrupts for now, we

1888

/* Don't enable even the PAUSE interrupts for now, we

1888

* make no use of those events other than to record them.

1889

* make no use of those events other than to record them.

1889

*/

1890

*/

1890

writel(0xffffffff, gp->regs + MAC_MCMASK);

1891

writel(0xffffffff, gp->regs + MAC_MCMASK);

1891

1892

/* Don't enable GEM's WOL in normal operations

1893

/* Don't enable GEM's WOL in normal operations

1893

*/

1894

*/

1894

if (gp->has_wol)

1895

if (gp->has_wol)

1895

writel(0, gp->regs + WOL_WAKECSR);

1896

writel(0, gp->regs + WOL_WAKECSR);

1896

}

1897

}

1897

1898

static void gem_init_pause_thresholds(struct gem *gp)

1899

static void gem_init_pause_thresholds(struct gem *gp)

1899

{

1900

{

1900

u32 cfg;

1901

u32 cfg;

1901

1902

/* Calculate pause thresholds. Setting the OFF threshold to the

1903

/* Calculate pause thresholds. Setting the OFF threshold to the

1903

* full RX fifo size effectively disables PAUSE generation which

1904

* full RX fifo size effectively disables PAUSE generation which

1904

* is what we do for 10/100 only GEMs which have FIFOs too small

1905

* is what we do for 10/100 only GEMs which have FIFOs too small

1905

* to make real gains from PAUSE.

1906

* to make real gains from PAUSE.

1906

*/

1907

*/

1907

if (gp->rx_fifo_sz <= (2 * 1024)) {

1908

if (gp->rx_fifo_sz <= (2 * 1024)) {

1908

gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;

1909

gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;

1909

} else {

1910

} else {

1910

int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63;

1911

int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63;

1911

int off = (gp->rx_fifo_sz - (max_frame * 2));

1912

int off = (gp->rx_fifo_sz - (max_frame * 2));

1912

int on = off - max_frame;

1913

int on = off - max_frame;

1913

1914

gp->rx_pause_off = off;

1915

gp->rx_pause_off = off;

1915

gp->rx_pause_on = on;

1916

gp->rx_pause_on = on;

1916

}

1917

}

1917

1918

1919

/* Configure the chip "burst" DMA mode & enable some

1920

/* Configure the chip "burst" DMA mode & enable some

1920

* HW bug fixes on Apple version

1921

* HW bug fixes on Apple version

1921

*/

1922

*/

1922

cfg = 0;

1923

cfg = 0;

1923

if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)

1924

if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)

1924

cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX;

1925

cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX;

1925

#if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)

1926

#if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)

1926

cfg |= GREG_CFG_IBURST;

1927

cfg |= GREG_CFG_IBURST;

1927

#endif

1928

#endif

1928

cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);

1929

cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);

1929

cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);

1930

cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);

1930

writel(cfg, gp->regs + GREG_CFG);

1931

writel(cfg, gp->regs + GREG_CFG);

1931

1932

/* If Infinite Burst didn't stick, then use different

1933

/* If Infinite Burst didn't stick, then use different

1933

* thresholds (and Apple bug fixes don't exist)

1934

* thresholds (and Apple bug fixes don't exist)

1934

*/

1935

*/

1935

if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {

1936

if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {

1936

cfg = ((2 << 1) & GREG_CFG_TXDMALIM);

1937

cfg = ((2 << 1) & GREG_CFG_TXDMALIM);

1937

cfg |= ((8 << 6) & GREG_CFG_RXDMALIM);

1938

cfg |= ((8 << 6) & GREG_CFG_RXDMALIM);

1938

writel(cfg, gp->regs + GREG_CFG);

1939

writel(cfg, gp->regs + GREG_CFG);

1939

}

1940

}

1940

}

1941

}

1941

1942

static int gem_check_invariants(struct gem *gp)

1943

static int gem_check_invariants(struct gem *gp)

1943

{

1944

{

1944

struct pci_dev *pdev = gp->pdev;

1945

struct pci_dev *pdev = gp->pdev;

1945

u32 mif_cfg;

1946

u32 mif_cfg;

1946

1947

/* On Apple's sungem, we can't rely on registers as the chip

1948

/* On Apple's sungem, we can't rely on registers as the chip

1948

* was been powered down by the firmware. The PHY is looked

1949

* was been powered down by the firmware. The PHY is looked

1949

* up later on.

1950

* up later on.

1950

*/

1951

*/

1951

if (pdev->vendor == PCI_VENDOR_ID_APPLE) {

1952

if (pdev->vendor == PCI_VENDOR_ID_APPLE) {

1952

gp->phy_type = phy_mii_mdio0;

1953

gp->phy_type = phy_mii_mdio0;

1953

gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;

1954

gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;

1954

gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;

1955

gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;

1955

gp->swrst_base = 0;

1956

gp->swrst_base = 0;

1956

1957

mif_cfg = readl(gp->regs + MIF_CFG);

1958

mif_cfg = readl(gp->regs + MIF_CFG);

1958

mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);

1959

mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);

1959

mif_cfg |= MIF_CFG_MDI0;

1960

mif_cfg |= MIF_CFG_MDI0;

1960

writel(mif_cfg, gp->regs + MIF_CFG);

1961

writel(mif_cfg, gp->regs + MIF_CFG);

1961

writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);

1962

writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);

1962

writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);

1963

writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);

1963

1964

/* We hard-code the PHY address so we can properly bring it out of

1965

/* We hard-code the PHY address so we can properly bring it out of

1965

* reset later on, we can't really probe it at this point, though

1966

* reset later on, we can't really probe it at this point, though

1966

* that isn't an issue.

1967

* that isn't an issue.

1967

*/

1968

*/

1968

if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC)

1969

if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC)

1969

gp->mii_phy_addr = 1;

1970

gp->mii_phy_addr = 1;

1970

else

1971

else

1971

gp->mii_phy_addr = 0;

1972

gp->mii_phy_addr = 0;

1972

1973

return 0;

1974

return 0;

1974

}

1975

}

1975

1976

mif_cfg = readl(gp->regs + MIF_CFG);

1977

mif_cfg = readl(gp->regs + MIF_CFG);

1977

1978

if (pdev->vendor == PCI_VENDOR_ID_SUN &&

1979

if (pdev->vendor == PCI_VENDOR_ID_SUN &&

1979

pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {

1980

pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {

1980

/* One of the MII PHYs _must_ be present

1981

/* One of the MII PHYs _must_ be present

1981

* as this chip has no gigabit PHY.

1982

* as this chip has no gigabit PHY.

1982

*/

1983

*/

1983

if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {

1984

if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {

1984

pr_err("RIO GEM lacks MII phy, mif_cfg[%08x]\n",

1985

pr_err("RIO GEM lacks MII phy, mif_cfg[%08x]\n",

1985

mif_cfg);

1986

mif_cfg);

1986

return -1;

1987

return -1;

1987

}

1988

}

1988

}

1989

}

1989

1990

/* Determine initial PHY interface type guess. MDIO1 is the

1991

/* Determine initial PHY interface type guess. MDIO1 is the

1991

* external PHY and thus takes precedence over MDIO0.

1992

* external PHY and thus takes precedence over MDIO0.

1992

*/

1993

*/

1993

1994

if (mif_cfg & MIF_CFG_MDI1) {

1995

if (mif_cfg & MIF_CFG_MDI1) {

1995

gp->phy_type = phy_mii_mdio1;

1996

gp->phy_type = phy_mii_mdio1;

1996

mif_cfg |= MIF_CFG_PSELECT;

1997

mif_cfg |= MIF_CFG_PSELECT;

1997

writel(mif_cfg, gp->regs + MIF_CFG);

1998

writel(mif_cfg, gp->regs + MIF_CFG);

1998

} else if (mif_cfg & MIF_CFG_MDI0) {

1999

} else if (mif_cfg & MIF_CFG_MDI0) {

1999

gp->phy_type = phy_mii_mdio0;

2000

gp->phy_type = phy_mii_mdio0;

2000

mif_cfg &= ~MIF_CFG_PSELECT;

2001

mif_cfg &= ~MIF_CFG_PSELECT;

2001

writel(mif_cfg, gp->regs + MIF_CFG);

2002

writel(mif_cfg, gp->regs + MIF_CFG);

2002

} else {

2003

} else {

2003

#ifdef CONFIG_SPARC

2004

#ifdef CONFIG_SPARC

2004

const char *p;

2005

const char *p;

2005

2006

p = of_get_property(gp->of_node, "shared-pins", NULL);

2007

p = of_get_property(gp->of_node, "shared-pins", NULL);

2007

if (p && !strcmp(p, "serdes"))

2008

if (p && !strcmp(p, "serdes"))

2008

gp->phy_type = phy_serdes;

2009

gp->phy_type = phy_serdes;

2009

else

2010

else

2010

#endif

2011

#endif

2011

gp->phy_type = phy_serialink;

2012

gp->phy_type = phy_serialink;

2012

}

2013

}

2013

if (gp->phy_type == phy_mii_mdio1 ||

2014

if (gp->phy_type == phy_mii_mdio1 ||

2014

gp->phy_type == phy_mii_mdio0) {

2015

gp->phy_type == phy_mii_mdio0) {

2015

int i;

2016

int i;

2016

2017

for (i = 0; i < 32; i++) {

2018

for (i = 0; i < 32; i++) {

2018

gp->mii_phy_addr = i;

2019

gp->mii_phy_addr = i;

2019

if (phy_read(gp, MII_BMCR) != 0xffff)

2020

if (phy_read(gp, MII_BMCR) != 0xffff)

2020

break;

2021

break;

2021

}

2022

}

2022

if (i == 32) {

2023

if (i == 32) {

2023

if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {

2024

if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {

2024

pr_err("RIO MII phy will not respond\n");

2025

pr_err("RIO MII phy will not respond\n");

2025

return -1;

2026

return -1;

2026

}

2027

}

2027

gp->phy_type = phy_serdes;

2028

gp->phy_type = phy_serdes;

2028

}

2029

}

2029

}

2030

}

2030

2031

/* Fetch the FIFO configurations now too. */

2032

/* Fetch the FIFO configurations now too. */

2032

gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;

2033

gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;

2033

gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;

2034

gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;

2034

2035

if (pdev->vendor == PCI_VENDOR_ID_SUN) {

2036

if (pdev->vendor == PCI_VENDOR_ID_SUN) {

2036

if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {

2037

if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {

2037

if (gp->tx_fifo_sz != (9 * 1024) ||

2038

if (gp->tx_fifo_sz != (9 * 1024) ||

2038

gp->rx_fifo_sz != (20 * 1024)) {

2039

gp->rx_fifo_sz != (20 * 1024)) {

2039

pr_err("GEM has bogus fifo sizes tx(%d) rx(%d)\n",

2040

pr_err("GEM has bogus fifo sizes tx(%d) rx(%d)\n",

2040

gp->tx_fifo_sz, gp->rx_fifo_sz);

2041

gp->tx_fifo_sz, gp->rx_fifo_sz);

2041

return -1;

2042

return -1;

2042

}

2043

}

2043

gp->swrst_base = 0;

2044

gp->swrst_base = 0;

2044

} else {

2045

} else {

2045

if (gp->tx_fifo_sz != (2 * 1024) ||

2046

if (gp->tx_fifo_sz != (2 * 1024) ||

2046

gp->rx_fifo_sz != (2 * 1024)) {

2047

gp->rx_fifo_sz != (2 * 1024)) {

2047

pr_err("RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",

2048

pr_err("RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",

2048

gp->tx_fifo_sz, gp->rx_fifo_sz);

2049

gp->tx_fifo_sz, gp->rx_fifo_sz);

2049

return -1;

2050

return -1;

2050

}

2051

}

2051

gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;

2052

gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;

2052

}

2053

}

2053

}

2054

}

2054

2055

return 0;

2056

return 0;

2056

}

2057

}

2057

2058

static void gem_reinit_chip(struct gem *gp)

2059

static void gem_reinit_chip(struct gem *gp)

2059

{

2060

{

2060

/* Reset the chip */

2061

/* Reset the chip */

2061

gem_reset(gp);

2062

gem_reset(gp);

2062

2063

/* Make sure ints are disabled */

2064

/* Make sure ints are disabled */

2064

gem_disable_ints(gp);

2065

gem_disable_ints(gp);

2065

2066

/* Allocate & setup ring buffers */

2067

/* Allocate & setup ring buffers */

2067

gem_init_rings(gp);

2068

gem_init_rings(gp);

2068

2069

/* Configure pause thresholds */

2070

/* Configure pause thresholds */

2070

gem_init_pause_thresholds(gp);

2071

gem_init_pause_thresholds(gp);

2071

2072

/* Init DMA & MAC engines */

2073

/* Init DMA & MAC engines */

2073

gem_init_dma(gp);

2074

gem_init_dma(gp);

2074

gem_init_mac(gp);

2075

gem_init_mac(gp);

2075

}

2076

}

2076

2077

2078

static void gem_stop_phy(struct gem *gp, int wol)

2079

static void gem_stop_phy(struct gem *gp, int wol)

2079

{

2080

{

2080

u32 mifcfg;

2081

u32 mifcfg;

2081

2082

/* Let the chip settle down a bit, it seems that helps

2083

/* Let the chip settle down a bit, it seems that helps

2083

* for sleep mode on some models

2084

* for sleep mode on some models

2084

*/

2085

*/

2085

msleep(10);

2086

msleep(10);

2086

2087

/* Make sure we aren't polling PHY status change. We

2088

/* Make sure we aren't polling PHY status change. We

2088

* don't currently use that feature though

2089

* don't currently use that feature though

2089

*/

2090

*/

2090

mifcfg = readl(gp->regs + MIF_CFG);

2091

mifcfg = readl(gp->regs + MIF_CFG);

2091

mifcfg &= ~MIF_CFG_POLL;

2092

mifcfg &= ~MIF_CFG_POLL;

2092

writel(mifcfg, gp->regs + MIF_CFG);

2093

writel(mifcfg, gp->regs + MIF_CFG);

2093

2094

if (wol && gp->has_wol) {

2095

if (wol && gp->has_wol) {

2095

unsigned char *e = &gp->dev->dev_addr[0];

2096

unsigned char *e = &gp->dev->dev_addr[0];

2096

u32 csr;

2097

u32 csr;

2097

2098

/* Setup wake-on-lan for MAGIC packet */

2099

/* Setup wake-on-lan for MAGIC packet */

2099

writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB,

2100

writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB,

2100

gp->regs + MAC_RXCFG);

2101

gp->regs + MAC_RXCFG);

2101

writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0);

2102

writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0);

2102

writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1);

2103

writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1);

2103

writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2);

2104

writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2);

2104

2105

writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT);

2106

writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT);

2106

csr = WOL_WAKECSR_ENABLE;

2107

csr = WOL_WAKECSR_ENABLE;

2107

if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0)

2108

if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0)

2108

csr |= WOL_WAKECSR_MII;

2109

csr |= WOL_WAKECSR_MII;

2109

writel(csr, gp->regs + WOL_WAKECSR);

2110

writel(csr, gp->regs + WOL_WAKECSR);

2110

} else {

2111

} else {

2111

writel(0, gp->regs + MAC_RXCFG);

2112

writel(0, gp->regs + MAC_RXCFG);

2112

(void)readl(gp->regs + MAC_RXCFG);

2113

(void)readl(gp->regs + MAC_RXCFG);

2113

/* Machine sleep will die in strange ways if we

2114

/* Machine sleep will die in strange ways if we

2114

* dont wait a bit here, looks like the chip takes

2115

* dont wait a bit here, looks like the chip takes

2115

* some time to really shut down

2116

* some time to really shut down

2116

*/

2117

*/

2117

msleep(10);

2118

msleep(10);

2118

}

2119

}

2119

2120

writel(0, gp->regs + MAC_TXCFG);

2121

writel(0, gp->regs + MAC_TXCFG);

2121

writel(0, gp->regs + MAC_XIFCFG);

2122

writel(0, gp->regs + MAC_XIFCFG);

2122

writel(0, gp->regs + TXDMA_CFG);

2123

writel(0, gp->regs + TXDMA_CFG);

2123

writel(0, gp->regs + RXDMA_CFG);

2124

writel(0, gp->regs + RXDMA_CFG);

2124

2125

if (!wol) {

2126

if (!wol) {

2126

gem_reset(gp);

2127

gem_reset(gp);

2127

writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);

2128

writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);

2128

writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);

2129

writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);

2129

2130

if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)

2131

if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)

2131

gp->phy_mii.def->ops->suspend(&gp->phy_mii);

2132

gp->phy_mii.def->ops->suspend(&gp->phy_mii);

2132

2133

/* According to Apple, we must set the MDIO pins to this begnign

2134

/* According to Apple, we must set the MDIO pins to this begnign

2134

* state or we may 1) eat more current, 2) damage some PHYs

2135

* state or we may 1) eat more current, 2) damage some PHYs

2135

*/

2136

*/

2136

writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);

2137

writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);

2137

writel(0, gp->regs + MIF_BBCLK);

2138

writel(0, gp->regs + MIF_BBCLK);

2138

writel(0, gp->regs + MIF_BBDATA);

2139

writel(0, gp->regs + MIF_BBDATA);

2139

writel(0, gp->regs + MIF_BBOENAB);

2140

writel(0, gp->regs + MIF_BBOENAB);

2140

writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);

2141

writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);

2141

(void) readl(gp->regs + MAC_XIFCFG);

2142

(void) readl(gp->regs + MAC_XIFCFG);

2142

}

2143

}

2143

}

2144

}

2144

2145

static int gem_do_start(struct net_device *dev)

2146

static int gem_do_start(struct net_device *dev)

2146

{

2147

{

2147

struct gem *gp = netdev_priv(dev);

2148

struct gem *gp = netdev_priv(dev);

2148

int rc;

2149

int rc;

2149

2150

/* Enable the cell */

2151

/* Enable the cell */

2151

gem_get_cell(gp);

2152

gem_get_cell(gp);

2152

2153

/* Make sure PCI access and bus master are enabled */

2154

/* Make sure PCI access and bus master are enabled */

2154

rc = pci_enable_device(gp->pdev);

2155

rc = pci_enable_device(gp->pdev);

2155

if (rc) {

2156

if (rc) {

2156

netdev_err(dev, "Failed to enable chip on PCI bus !\n");

2157

netdev_err(dev, "Failed to enable chip on PCI bus !\n");

2157

2158

/* Put cell and forget it for now, it will be considered as

2159

/* Put cell and forget it for now, it will be considered as

2159

* still asleep, a new sleep cycle may bring it back

2160

* still asleep, a new sleep cycle may bring it back

2160

*/

2161

*/

2161

gem_put_cell(gp);

2162

gem_put_cell(gp);

2162

return -ENXIO;

2163

return -ENXIO;

2163

}

2164

}

2164

pci_set_master(gp->pdev);

2165

pci_set_master(gp->pdev);

2165

2166

/* Init & setup chip hardware */

2167

/* Init & setup chip hardware */

2167

gem_reinit_chip(gp);

2168

gem_reinit_chip(gp);

2168

2169

/* An interrupt might come in handy */

2170

/* An interrupt might come in handy */

2170

rc = request_irq(gp->pdev->irq, gem_interrupt,

2171

rc = request_irq(gp->pdev->irq, gem_interrupt,

2171

IRQF_SHARED, dev->name, (void *)dev);

2172

IRQF_SHARED, dev->name, (void *)dev);

2172

if (rc) {

2173

if (rc) {

2173

netdev_err(dev, "failed to request irq !\n");

2174

netdev_err(dev, "failed to request irq !\n");

2174

2175

gem_reset(gp);

2176

gem_reset(gp);

2176

gem_clean_rings(gp);

2177

gem_clean_rings(gp);

2177

gem_put_cell(gp);

2178

gem_put_cell(gp);

2178

return rc;

2179

return rc;

2179

}

2180

}

2180

2181

/* Mark us as attached again if we come from resume(), this has

2182

/* Mark us as attached again if we come from resume(), this has

2182

* no effect if we weren't detatched and needs to be done now.

2183

* no effect if we weren't detatched and needs to be done now.

2183

*/

2184

*/

2184

netif_device_attach(dev);

2185

netif_device_attach(dev);

2185

2186

/* Restart NAPI & queues */

2187

/* Restart NAPI & queues */

2187

gem_netif_start(gp);

2188

gem_netif_start(gp);

2188

2189

/* Detect & init PHY, start autoneg etc... this will

2190

/* Detect & init PHY, start autoneg etc... this will

2190

* eventually result in starting DMA operations when

2191

* eventually result in starting DMA operations when

2191

* the link is up

2192

* the link is up

2192

*/

2193

*/

2193

gem_init_phy(gp);

2194

gem_init_phy(gp);

2194

2195

return 0;

2196

return 0;

2196

}

2197

}

2197

2198

static void gem_do_stop(struct net_device *dev, int wol)

2199

static void gem_do_stop(struct net_device *dev, int wol)

2199

{

2200

{

2200

struct gem *gp = netdev_priv(dev);

2201

struct gem *gp = netdev_priv(dev);

2201

2202

/* Stop NAPI and stop tx queue */

2203

/* Stop NAPI and stop tx queue */

2203

gem_netif_stop(gp);

2204

gem_netif_stop(gp);

2204

2205

/* Make sure ints are disabled. We don't care about

2206

/* Make sure ints are disabled. We don't care about

2206

* synchronizing as NAPI is disabled, thus a stray

2207

* synchronizing as NAPI is disabled, thus a stray

2207

* interrupt will do nothing bad (our irq handler

2208

* interrupt will do nothing bad (our irq handler

2208

* just schedules NAPI)

2209

* just schedules NAPI)

2209

*/

2210

*/

2210

gem_disable_ints(gp);

2211

gem_disable_ints(gp);

2211

2212

/* Stop the link timer */

2213

/* Stop the link timer */

2213

del_timer_sync(&gp->link_timer);

2214

del_timer_sync(&gp->link_timer);

2214

2215

/* We cannot cancel the reset task while holding the

2216

/* We cannot cancel the reset task while holding the

2216

* rtnl lock, we'd get an A->B / B->A deadlock stituation

2217

* rtnl lock, we'd get an A->B / B->A deadlock stituation

2217

* if we did. This is not an issue however as the reset

2218

* if we did. This is not an issue however as the reset

2218

* task is synchronized vs. us (rtnl_lock) and will do

2219

* task is synchronized vs. us (rtnl_lock) and will do

2219

* nothing if the device is down or suspended. We do

2220

* nothing if the device is down or suspended. We do

2220

* still clear reset_task_pending to avoid a spurrious

2221

* still clear reset_task_pending to avoid a spurrious

2221

* reset later on in case we do resume before it gets

2222

* reset later on in case we do resume before it gets

2222

* scheduled.

2223

* scheduled.

2223

*/

2224

*/

2224

gp->reset_task_pending = 0;

2225

gp->reset_task_pending = 0;

2225

2226

/* If we are going to sleep with WOL */

2227

/* If we are going to sleep with WOL */

2227

gem_stop_dma(gp);

2228

gem_stop_dma(gp);

2228

msleep(10);

2229

msleep(10);

2229

if (!wol)

2230

if (!wol)

2230

gem_reset(gp);

2231

gem_reset(gp);

2231

msleep(10);

2232

msleep(10);

2232

2233

/* Get rid of rings */

2234

/* Get rid of rings */

2234

gem_clean_rings(gp);

2235

gem_clean_rings(gp);

2235

2236

/* No irq needed anymore */

2237

/* No irq needed anymore */

2237

free_irq(gp->pdev->irq, (void *) dev);

2238

free_irq(gp->pdev->irq, (void *) dev);

2238

2239

/* Shut the PHY down eventually and setup WOL */

2240

/* Shut the PHY down eventually and setup WOL */

2240

gem_stop_phy(gp, wol);

2241

gem_stop_phy(gp, wol);

2241

2242

/* Make sure bus master is disabled */

2243

/* Make sure bus master is disabled */

2243

pci_disable_device(gp->pdev);

2244

pci_disable_device(gp->pdev);

2244

2245

/* Cell not needed neither if no WOL */

2246

/* Cell not needed neither if no WOL */

2246

if (!wol)

2247

if (!wol)

2247

gem_put_cell(gp);

2248

gem_put_cell(gp);

2248

}

2249

}

2249

2250

static void gem_reset_task(struct work_struct *work)

2251

static void gem_reset_task(struct work_struct *work)

2251

{

2252

{

2252

struct gem *gp = container_of(work, struct gem, reset_task);

2253

struct gem *gp = container_of(work, struct gem, reset_task);

2253

2254

/* Lock out the network stack (essentially shield ourselves

2255

/* Lock out the network stack (essentially shield ourselves

2255

* against a racing open, close, control call, or suspend

2256

* against a racing open, close, control call, or suspend

2256

*/

2257

*/

2257

rtnl_lock();

2258

rtnl_lock();

2258

2259

/* Skip the reset task if suspended or closed, or if it's

2260

/* Skip the reset task if suspended or closed, or if it's

2260

* been cancelled by gem_do_stop (see comment there)

2261

* been cancelled by gem_do_stop (see comment there)

2261

*/

2262

*/

2262

if (!netif_device_present(gp->dev) ||

2263

if (!netif_device_present(gp->dev) ||

2263

!netif_running(gp->dev) ||

2264

!netif_running(gp->dev) ||

2264

!gp->reset_task_pending) {

2265

!gp->reset_task_pending) {

2265

rtnl_unlock();

2266

rtnl_unlock();

2266

return;

2267

return;

2267

}

2268

}

2268

2269

/* Stop the link timer */

2270

/* Stop the link timer */

2270

del_timer_sync(&gp->link_timer);

2271

del_timer_sync(&gp->link_timer);

2271

2272

/* Stop NAPI and tx */

2273

/* Stop NAPI and tx */

2273

gem_netif_stop(gp);

2274

gem_netif_stop(gp);

2274

2275

/* Reset the chip & rings */

2276

/* Reset the chip & rings */

2276

gem_reinit_chip(gp);

2277

gem_reinit_chip(gp);

2277

if (gp->lstate == link_up)

2278

if (gp->lstate == link_up)

2278

gem_set_link_modes(gp);

2279

gem_set_link_modes(gp);

2279

2280

/* Restart NAPI and Tx */

2281

/* Restart NAPI and Tx */

2281

gem_netif_start(gp);

2282

gem_netif_start(gp);

2282

2283

/* We are back ! */

2284

/* We are back ! */

2284

gp->reset_task_pending = 0;

2285

gp->reset_task_pending = 0;

2285

2286

/* If the link is not up, restart autoneg, else restart the

2287

/* If the link is not up, restart autoneg, else restart the

2287

* polling timer

2288

* polling timer

2288

*/

2289

*/

2289

if (gp->lstate != link_up)

2290

if (gp->lstate != link_up)

2290

gem_begin_auto_negotiation(gp, NULL);

2291

gem_begin_auto_negotiation(gp, NULL);

2291

else

2292

else

2292

mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));

2293

mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));

2293

2294

rtnl_unlock();

2295

rtnl_unlock();

2295

}

2296

}

2296

2297

static int gem_open(struct net_device *dev)

2298

static int gem_open(struct net_device *dev)

2298

{

2299

{

2299

/* We allow open while suspended, we just do nothing,

2300

/* We allow open while suspended, we just do nothing,

2300

* the chip will be initialized in resume()

2301

* the chip will be initialized in resume()

2301

*/

2302

*/

2302

if (netif_device_present(dev))

2303

if (netif_device_present(dev))

2303

return gem_do_start(dev);

2304

return gem_do_start(dev);

2304

return 0;

2305

return 0;

2305

}

2306

}

2306

2307

static int gem_close(struct net_device *dev)

2308

static int gem_close(struct net_device *dev)

2308

{

2309

{

2309

if (netif_device_present(dev))

2310

if (netif_device_present(dev))

2310

gem_do_stop(dev, 0);

2311

gem_do_stop(dev, 0);

2311

2312

return 0;

2313

return 0;

2313

}

2314

}

2314

2315

#ifdef CONFIG_PM

2316

#ifdef CONFIG_PM

2316

static int gem_suspend(struct pci_dev *pdev, pm_message_t state)

2317

static int gem_suspend(struct pci_dev *pdev, pm_message_t state)

2317

{

2318

{

2318

struct net_device *dev = pci_get_drvdata(pdev);

2319

struct net_device *dev = pci_get_drvdata(pdev);

2319

struct gem *gp = netdev_priv(dev);

2320

struct gem *gp = netdev_priv(dev);

2320

2321

/* Lock the network stack first to avoid racing with open/close,

2322

/* Lock the network stack first to avoid racing with open/close,

2322

* reset task and setting calls

2323

* reset task and setting calls

2323

*/

2324

*/

2324

rtnl_lock();

2325

rtnl_lock();

2325

2326

/* Not running, mark ourselves non-present, no need for

2327

/* Not running, mark ourselves non-present, no need for

2327

* a lock here

2328

* a lock here

2328

*/

2329

*/

2329

if (!netif_running(dev)) {

2330

if (!netif_running(dev)) {

2330

netif_device_detach(dev);

2331

netif_device_detach(dev);

2331

rtnl_unlock();

2332

rtnl_unlock();

2332

return 0;

2333

return 0;

2333

}

2334

}

2334

netdev_info(dev, "suspending, WakeOnLan %s\n",

2335

netdev_info(dev, "suspending, WakeOnLan %s\n",

2335

(gp->wake_on_lan && netif_running(dev)) ?

2336

(gp->wake_on_lan && netif_running(dev)) ?

2336

"enabled" : "disabled");

2337

"enabled" : "disabled");

2337

2338

/* Tell the network stack we're gone. gem_do_stop() below will

2339

/* Tell the network stack we're gone. gem_do_stop() below will

2339

* synchronize with TX, stop NAPI etc...

2340

* synchronize with TX, stop NAPI etc...

2340

*/

2341

*/

2341

netif_device_detach(dev);

2342

netif_device_detach(dev);

2342

2343

/* Switch off chip, remember WOL setting */

2344

/* Switch off chip, remember WOL setting */

2344

gp->asleep_wol = gp->wake_on_lan;

2345

gp->asleep_wol = gp->wake_on_lan;

2345

gem_do_stop(dev, gp->asleep_wol);

2346

gem_do_stop(dev, gp->asleep_wol);

2346

2347

/* Unlock the network stack */

2348

/* Unlock the network stack */

2348

rtnl_unlock();

2349

rtnl_unlock();

2349

2350

return 0;

2351

return 0;

2351

}

2352

}

2352

2353

static int gem_resume(struct pci_dev *pdev)

2354

static int gem_resume(struct pci_dev *pdev)

2354

{

2355

{

2355

struct net_device *dev = pci_get_drvdata(pdev);

2356

struct net_device *dev = pci_get_drvdata(pdev);

2356

struct gem *gp = netdev_priv(dev);

2357

struct gem *gp = netdev_priv(dev);

2357

2358

/* See locking comment in gem_suspend */

2359

/* See locking comment in gem_suspend */

2359

rtnl_lock();

2360

rtnl_lock();

2360

2361

/* Not running, mark ourselves present, no need for

2362

/* Not running, mark ourselves present, no need for

2362

* a lock here

2363

* a lock here

2363

*/

2364

*/

2364

if (!netif_running(dev)) {

2365

if (!netif_running(dev)) {

2365

netif_device_attach(dev);

2366

netif_device_attach(dev);

2366

rtnl_unlock();

2367

rtnl_unlock();

2367

return 0;

2368

return 0;

2368

}

2369

}

2369

2370

/* Restart chip. If that fails there isn't much we can do, we

2371

/* Restart chip. If that fails there isn't much we can do, we

2371

* leave things stopped.

2372

* leave things stopped.

2372

*/

2373

*/

2373

gem_do_start(dev);

2374

gem_do_start(dev);

2374

2375

/* If we had WOL enabled, the cell clock was never turned off during

2376

/* If we had WOL enabled, the cell clock was never turned off during

2376

* sleep, so we end up beeing unbalanced. Fix that here

2377

* sleep, so we end up beeing unbalanced. Fix that here

2377

*/

2378

*/

2378

if (gp->asleep_wol)

2379

if (gp->asleep_wol)

2379

gem_put_cell(gp);

2380

gem_put_cell(gp);

2380

2381

/* Unlock the network stack */

2382

/* Unlock the network stack */

2382

rtnl_unlock();

2383

rtnl_unlock();

2383

2384

return 0;

2385

return 0;

2385

}

2386

}

2386

#endif /* CONFIG_PM */

2387

#endif /* CONFIG_PM */

2387

2388

static struct net_device_stats *gem_get_stats(struct net_device *dev)

2389

static struct net_device_stats *gem_get_stats(struct net_device *dev)

2389

{

2390

{

2390

struct gem *gp = netdev_priv(dev);

2391

struct gem *gp = netdev_priv(dev);

2391

2392

/* I have seen this being called while the PM was in progress,

2393

/* I have seen this being called while the PM was in progress,

2393

* so we shield against this. Let's also not poke at registers

2394

* so we shield against this. Let's also not poke at registers

2394

* while the reset task is going on.

2395

* while the reset task is going on.

2395

*

2396

*

2396

* TODO: Move stats collection elsewhere (link timer ?) and

2397

* TODO: Move stats collection elsewhere (link timer ?) and

2397

* make this a nop to avoid all those synchro issues

2398

* make this a nop to avoid all those synchro issues

2398

*/

2399

*/

2399

if (!netif_device_present(dev) || !netif_running(dev))

2400

if (!netif_device_present(dev) || !netif_running(dev))

2400

goto bail;

2401

goto bail;

2401

2402

/* Better safe than sorry... */

2403

/* Better safe than sorry... */

2403

if (WARN_ON(!gp->cell_enabled))

2404

if (WARN_ON(!gp->cell_enabled))

2404

goto bail;

2405

goto bail;

2405

2406

dev->stats.rx_crc_errors += readl(gp->regs + MAC_FCSERR);

2407

dev->stats.rx_crc_errors += readl(gp->regs + MAC_FCSERR);

2407

writel(0, gp->regs + MAC_FCSERR);

2408

writel(0, gp->regs + MAC_FCSERR);

2408

2409

dev->stats.rx_frame_errors += readl(gp->regs + MAC_AERR);

2410

dev->stats.rx_frame_errors += readl(gp->regs + MAC_AERR);

2410

writel(0, gp->regs + MAC_AERR);

2411

writel(0, gp->regs + MAC_AERR);

2411

2412

dev->stats.rx_length_errors += readl(gp->regs + MAC_LERR);

2413

dev->stats.rx_length_errors += readl(gp->regs + MAC_LERR);

2413

writel(0, gp->regs + MAC_LERR);

2414

writel(0, gp->regs + MAC_LERR);

2414

2415

dev->stats.tx_aborted_errors += readl(gp->regs + MAC_ECOLL);

2416

dev->stats.tx_aborted_errors += readl(gp->regs + MAC_ECOLL);

2416

dev->stats.collisions +=

2417

dev->stats.collisions +=

2417

(readl(gp->regs + MAC_ECOLL) + readl(gp->regs + MAC_LCOLL));

2418

(readl(gp->regs + MAC_ECOLL) + readl(gp->regs + MAC_LCOLL));

2418

writel(0, gp->regs + MAC_ECOLL);

2419

writel(0, gp->regs + MAC_ECOLL);

2419

writel(0, gp->regs + MAC_LCOLL);

2420

writel(0, gp->regs + MAC_LCOLL);

2420

bail:

2421

bail:

2421

return &dev->stats;

2422

return &dev->stats;

2422

}

2423

}

2423

2424

static int gem_set_mac_address(struct net_device *dev, void *addr)

2425

static int gem_set_mac_address(struct net_device *dev, void *addr)

2425

{

2426

{

2426

struct sockaddr *macaddr = (struct sockaddr *) addr;

2427

struct sockaddr *macaddr = (struct sockaddr *) addr;

2427

struct gem *gp = netdev_priv(dev);

2428

struct gem *gp = netdev_priv(dev);

2428

unsigned char *e = &dev->dev_addr[0];

2429

unsigned char *e = &dev->dev_addr[0];

2429

2430

if (!is_valid_ether_addr(macaddr->sa_data))

2431

if (!is_valid_ether_addr(macaddr->sa_data))

2431

return -EADDRNOTAVAIL;

2432

return -EADDRNOTAVAIL;

2432

2433

memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len);

2434

memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len);

2434

2435

/* We'll just catch it later when the device is up'd or resumed */

2436

/* We'll just catch it later when the device is up'd or resumed */

2436

if (!netif_running(dev) || !netif_device_present(dev))

2437

if (!netif_running(dev) || !netif_device_present(dev))

2437

return 0;

2438

return 0;

2438

2439

/* Better safe than sorry... */

2440

/* Better safe than sorry... */

2440

if (WARN_ON(!gp->cell_enabled))

2441

if (WARN_ON(!gp->cell_enabled))

2441

return 0;

2442

return 0;

2442

2443

writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);

2444

writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);

2444

writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);

2445

writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);

2445

writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);

2446

writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);

2446

2447

return 0;

2448

return 0;

2448

}

2449

}

2449

2450

static void gem_set_multicast(struct net_device *dev)

2451

static void gem_set_multicast(struct net_device *dev)

2451

{

2452

{

2452

struct gem *gp = netdev_priv(dev);

2453

struct gem *gp = netdev_priv(dev);

2453

u32 rxcfg, rxcfg_new;

2454

u32 rxcfg, rxcfg_new;

2454

int limit = 10000;

2455

int limit = 10000;

2455

2456

if (!netif_running(dev) || !netif_device_present(dev))

2457

if (!netif_running(dev) || !netif_device_present(dev))

2457

return;

2458

return;

2458

2459

/* Better safe than sorry... */

2460

/* Better safe than sorry... */

2460

if (gp->reset_task_pending || WARN_ON(!gp->cell_enabled))

2461

if (gp->reset_task_pending || WARN_ON(!gp->cell_enabled))

2461

return;

2462

return;

2462

2463

rxcfg = readl(gp->regs + MAC_RXCFG);

2464

rxcfg = readl(gp->regs + MAC_RXCFG);

2464

rxcfg_new = gem_setup_multicast(gp);

2465

rxcfg_new = gem_setup_multicast(gp);

2465

#ifdef STRIP_FCS

2466

#ifdef STRIP_FCS

2466

rxcfg_new |= MAC_RXCFG_SFCS;

2467

rxcfg_new |= MAC_RXCFG_SFCS;

2467

#endif

2468

#endif

2468

gp->mac_rx_cfg = rxcfg_new;

2469

gp->mac_rx_cfg = rxcfg_new;

2469

2470

writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);

2471

writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);

2471

while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {

2472

while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {

2472

if (!limit--)

2473

if (!limit--)

2473

break;

2474

break;

2474

udelay(10);

2475

udelay(10);

2475

}

2476

}

2476

2477

rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);

2478

rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);

2478

rxcfg |= rxcfg_new;

2479

rxcfg |= rxcfg_new;

2479

2480

writel(rxcfg, gp->regs + MAC_RXCFG);

2481

writel(rxcfg, gp->regs + MAC_RXCFG);

2481

}

2482

}

2482

2483

/* Jumbo-grams don't seem to work :-( */

2484

/* Jumbo-grams don't seem to work :-( */

2484

#define GEM_MIN_MTU 68

2485

#define GEM_MIN_MTU 68

2485

#if 1

2486

#if 1

2486

#define GEM_MAX_MTU 1500

2487

#define GEM_MAX_MTU 1500

2487

#else

2488

#else

2488

#define GEM_MAX_MTU 9000

2489

#define GEM_MAX_MTU 9000

2489

#endif

2490

#endif

2490

2491

static int gem_change_mtu(struct net_device *dev, int new_mtu)

2492

static int gem_change_mtu(struct net_device *dev, int new_mtu)

2492

{

2493

{

2493

struct gem *gp = netdev_priv(dev);

2494

struct gem *gp = netdev_priv(dev);

2494

2495

if (new_mtu < GEM_MIN_MTU || new_mtu > GEM_MAX_MTU)

2496

if (new_mtu < GEM_MIN_MTU || new_mtu > GEM_MAX_MTU)

2496

return -EINVAL;

2497

return -EINVAL;

2497

2498

dev->mtu = new_mtu;

2499

dev->mtu = new_mtu;

2499

2500

/* We'll just catch it later when the device is up'd or resumed */

2501

/* We'll just catch it later when the device is up'd or resumed */

2501

if (!netif_running(dev) || !netif_device_present(dev))

2502

if (!netif_running(dev) || !netif_device_present(dev))

2502

return 0;

2503

return 0;

2503

2504

/* Better safe than sorry... */

2505

/* Better safe than sorry... */

2505

if (WARN_ON(!gp->cell_enabled))

2506

if (WARN_ON(!gp->cell_enabled))

2506

return 0;

2507

return 0;

2507

2508

gem_netif_stop(gp);

2509

gem_netif_stop(gp);

2509

gem_reinit_chip(gp);

2510

gem_reinit_chip(gp);

2510

if (gp->lstate == link_up)

2511

if (gp->lstate == link_up)

2511

gem_set_link_modes(gp);

2512

gem_set_link_modes(gp);

2512

gem_netif_start(gp);

2513

gem_netif_start(gp);

2513

2514

return 0;

2515

return 0;

2515

}

2516

}

2516

2517

static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)

2518

static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)

2518

{

2519

{

2519

struct gem *gp = netdev_priv(dev);

2520

struct gem *gp = netdev_priv(dev);

2520

2521

strcpy(info->driver, DRV_NAME);

2522

strcpy(info->driver, DRV_NAME);

2522

strcpy(info->version, DRV_VERSION);

2523

strcpy(info->version, DRV_VERSION);

2523

strcpy(info->bus_info, pci_name(gp->pdev));

2524

strcpy(info->bus_info, pci_name(gp->pdev));

2524

}

2525

}

2525

2526

static int gem_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)

2527

static int gem_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)

2527

{

2528

{

2528

struct gem *gp = netdev_priv(dev);

2529

struct gem *gp = netdev_priv(dev);

2529

2530

if (gp->phy_type == phy_mii_mdio0 ||

2531

if (gp->phy_type == phy_mii_mdio0 ||

2531

gp->phy_type == phy_mii_mdio1) {

2532

gp->phy_type == phy_mii_mdio1) {

2532

if (gp->phy_mii.def)

2533

if (gp->phy_mii.def)

2533

cmd->supported = gp->phy_mii.def->features;

2534

cmd->supported = gp->phy_mii.def->features;

2534

else

2535

else

2535

cmd->supported = (SUPPORTED_10baseT_Half |

2536

cmd->supported = (SUPPORTED_10baseT_Half |

2536

SUPPORTED_10baseT_Full);

2537

SUPPORTED_10baseT_Full);

2537

2538

/* XXX hardcoded stuff for now */

2539

/* XXX hardcoded stuff for now */

2539

cmd->port = PORT_MII;

2540

cmd->port = PORT_MII;

2540

cmd->transceiver = XCVR_EXTERNAL;

2541

cmd->transceiver = XCVR_EXTERNAL;

2541

cmd->phy_address = 0; /* XXX fixed PHYAD */

2542

cmd->phy_address = 0; /* XXX fixed PHYAD */

2542

2543

/* Return current PHY settings */

2544

/* Return current PHY settings */

2544

cmd->autoneg = gp->want_autoneg;

2545

cmd->autoneg = gp->want_autoneg;

2545

ethtool_cmd_speed_set(cmd, gp->phy_mii.speed);

2546

ethtool_cmd_speed_set(cmd, gp->phy_mii.speed);

2546

cmd->duplex = gp->phy_mii.duplex;

2547

cmd->duplex = gp->phy_mii.duplex;

2547

cmd->advertising = gp->phy_mii.advertising;

2548

cmd->advertising = gp->phy_mii.advertising;

2548

2549

/* If we started with a forced mode, we don't have a default

2550

/* If we started with a forced mode, we don't have a default

2550

* advertise set, we need to return something sensible so

2551

* advertise set, we need to return something sensible so

2551

* userland can re-enable autoneg properly.

2552

* userland can re-enable autoneg properly.

2552

*/

2553

*/

2553

if (cmd->advertising == 0)

2554

if (cmd->advertising == 0)

2554

cmd->advertising = cmd->supported;

2555

cmd->advertising = cmd->supported;

2555

} else { // XXX PCS ?

2556

} else { // XXX PCS ?

2556

cmd->supported =

2557

cmd->supported =

2557

(SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |

2558

(SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |

2558

SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |

2559

SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |

2559

SUPPORTED_Autoneg);

2560

SUPPORTED_Autoneg);

2560

cmd->advertising = cmd->supported;

2561

cmd->advertising = cmd->supported;

2561

ethtool_cmd_speed_set(cmd, 0);

2562

ethtool_cmd_speed_set(cmd, 0);

2562

cmd->duplex = cmd->port = cmd->phy_address =

2563

cmd->duplex = cmd->port = cmd->phy_address =

2563

cmd->transceiver = cmd->autoneg = 0;

2564

cmd->transceiver = cmd->autoneg = 0;

2564

2565

/* serdes means usually a Fibre connector, with most fixed */

2566

/* serdes means usually a Fibre connector, with most fixed */

2566

if (gp->phy_type == phy_serdes) {

2567

if (gp->phy_type == phy_serdes) {

2567

cmd->port = PORT_FIBRE;

2568

cmd->port = PORT_FIBRE;

2568

cmd->supported = (SUPPORTED_1000baseT_Half |

2569

cmd->supported = (SUPPORTED_1000baseT_Half |

2569

SUPPORTED_1000baseT_Full |

2570

SUPPORTED_1000baseT_Full |

2570

SUPPORTED_FIBRE | SUPPORTED_Autoneg |

2571

SUPPORTED_FIBRE | SUPPORTED_Autoneg |

2571

SUPPORTED_Pause | SUPPORTED_Asym_Pause);

2572

SUPPORTED_Pause | SUPPORTED_Asym_Pause);

2572

cmd->advertising = cmd->supported;

2573

cmd->advertising = cmd->supported;

2573

cmd->transceiver = XCVR_INTERNAL;

2574

cmd->transceiver = XCVR_INTERNAL;

2574

if (gp->lstate == link_up)

2575

if (gp->lstate == link_up)

2575

ethtool_cmd_speed_set(cmd, SPEED_1000);

2576

ethtool_cmd_speed_set(cmd, SPEED_1000);

2576

cmd->duplex = DUPLEX_FULL;

2577

cmd->duplex = DUPLEX_FULL;

2577

cmd->autoneg = 1;

2578

cmd->autoneg = 1;

2578

}

2579

}

2579

}

2580

}

2580

cmd->maxtxpkt = cmd->maxrxpkt = 0;

2581

cmd->maxtxpkt = cmd->maxrxpkt = 0;

2581

2582

return 0;

2583

return 0;

2583

}

2584

}

2584

2585

static int gem_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)

2586

static int gem_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)

2586

{

2587

{

2587

struct gem *gp = netdev_priv(dev);

2588

struct gem *gp = netdev_priv(dev);

2588

u32 speed = ethtool_cmd_speed(cmd);

2589

u32 speed = ethtool_cmd_speed(cmd);

2589

2590

/* Verify the settings we care about. */

2591

/* Verify the settings we care about. */

2591

if (cmd->autoneg != AUTONEG_ENABLE &&

2592

if (cmd->autoneg != AUTONEG_ENABLE &&

2592

cmd->autoneg != AUTONEG_DISABLE)

2593

cmd->autoneg != AUTONEG_DISABLE)

2593

return -EINVAL;

2594

return -EINVAL;

2594

2595

if (cmd->autoneg == AUTONEG_ENABLE &&

2596

if (cmd->autoneg == AUTONEG_ENABLE &&

2596

cmd->advertising == 0)

2597

cmd->advertising == 0)

2597

return -EINVAL;

2598

return -EINVAL;

2598

2599

if (cmd->autoneg == AUTONEG_DISABLE &&

2600

if (cmd->autoneg == AUTONEG_DISABLE &&

2600

((speed != SPEED_1000 &&

2601

((speed != SPEED_1000 &&

2601

speed != SPEED_100 &&

2602

speed != SPEED_100 &&

2602

speed != SPEED_10) ||

2603

speed != SPEED_10) ||

2603

(cmd->duplex != DUPLEX_HALF &&

2604

(cmd->duplex != DUPLEX_HALF &&

2604

cmd->duplex != DUPLEX_FULL)))

2605

cmd->duplex != DUPLEX_FULL)))

2605

return -EINVAL;

2606

return -EINVAL;

2606

2607

/* Apply settings and restart link process. */

2608

/* Apply settings and restart link process. */

2608

if (netif_device_present(gp->dev)) {

2609

if (netif_device_present(gp->dev)) {

2609

del_timer_sync(&gp->link_timer);

2610

del_timer_sync(&gp->link_timer);

2610

gem_begin_auto_negotiation(gp, cmd);

2611

gem_begin_auto_negotiation(gp, cmd);

2611

}

2612

}

2612

2613

return 0;

2614

return 0;

2614

}

2615

}

2615

2616

static int gem_nway_reset(struct net_device *dev)

2617

static int gem_nway_reset(struct net_device *dev)

2617

{

2618

{

2618

struct gem *gp = netdev_priv(dev);

2619

struct gem *gp = netdev_priv(dev);

2619

2620

if (!gp->want_autoneg)

2621

if (!gp->want_autoneg)

2621

return -EINVAL;

2622

return -EINVAL;

2622

2623

/* Restart link process */

2624

/* Restart link process */

2624

if (netif_device_present(gp->dev)) {

2625

if (netif_device_present(gp->dev)) {

2625

del_timer_sync(&gp->link_timer);

2626

del_timer_sync(&gp->link_timer);

2626

gem_begin_auto_negotiation(gp, NULL);

2627

gem_begin_auto_negotiation(gp, NULL);

2627

}

2628

}

2628

2629

return 0;

2630

return 0;

2630

}

2631

}

2631

2632

static u32 gem_get_msglevel(struct net_device *dev)

2633

static u32 gem_get_msglevel(struct net_device *dev)

2633

{

2634

{

2634

struct gem *gp = netdev_priv(dev);

2635

struct gem *gp = netdev_priv(dev);

2635

return gp->msg_enable;

2636

return gp->msg_enable;

2636

}

2637

}

2637

2638

static void gem_set_msglevel(struct net_device *dev, u32 value)

2639

static void gem_set_msglevel(struct net_device *dev, u32 value)

2639

{

2640

{

2640

struct gem *gp = netdev_priv(dev);

2641

struct gem *gp = netdev_priv(dev);

2641

gp->msg_enable = value;

2642

gp->msg_enable = value;

2642

}

2643

}

2643

2644

2645

/* Add more when I understand how to program the chip */

2646

/* Add more when I understand how to program the chip */

2646

/* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */

2647

/* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */

2647

2648

#define WOL_SUPPORTED_MASK (WAKE_MAGIC)

2649

#define WOL_SUPPORTED_MASK (WAKE_MAGIC)

2649

2650

static void gem_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)

2651

static void gem_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)

2651

{

2652

{

2652

struct gem *gp = netdev_priv(dev);

2653

struct gem *gp = netdev_priv(dev);

2653

2654

/* Add more when I understand how to program the chip */

2655

/* Add more when I understand how to program the chip */

2655

if (gp->has_wol) {

2656

if (gp->has_wol) {

2656

wol->supported = WOL_SUPPORTED_MASK;

2657

wol->supported = WOL_SUPPORTED_MASK;

2657

wol->wolopts = gp->wake_on_lan;

2658

wol->wolopts = gp->wake_on_lan;

2658

} else {

2659

} else {

2659

wol->supported = 0;

2660

wol->supported = 0;

2660

wol->wolopts = 0;

2661

wol->wolopts = 0;

2661

}

2662

}

2662

}

2663

}

2663

2664

static int gem_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)

2665

static int gem_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)

2665

{

2666

{

2666

struct gem *gp = netdev_priv(dev);

2667

struct gem *gp = netdev_priv(dev);

2667

2668

if (!gp->has_wol)

2669

if (!gp->has_wol)

2669

return -EOPNOTSUPP;

2670

return -EOPNOTSUPP;

2670

gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK;

2671

gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK;

2671

return 0;

2672

return 0;

2672

}

2673

}

2673

2674

static const struct ethtool_ops gem_ethtool_ops = {

2675

static const struct ethtool_ops gem_ethtool_ops = {

2675

.get_drvinfo = gem_get_drvinfo,

2676

.get_drvinfo = gem_get_drvinfo,

2676

.get_link = ethtool_op_get_link,

2677

.get_link = ethtool_op_get_link,

2677

.get_settings = gem_get_settings,

2678

.get_settings = gem_get_settings,

2678

.set_settings = gem_set_settings,

2679

.set_settings = gem_set_settings,

2679

.nway_reset = gem_nway_reset,

2680

.nway_reset = gem_nway_reset,

2680

.get_msglevel = gem_get_msglevel,

2681

.get_msglevel = gem_get_msglevel,

2681

.set_msglevel = gem_set_msglevel,

2682

.set_msglevel = gem_set_msglevel,

2682

.get_wol = gem_get_wol,

2683

.get_wol = gem_get_wol,

2683

.set_wol = gem_set_wol,

2684

.set_wol = gem_set_wol,

2684

};

2685

};

2685

2686

static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)

2687

static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)

2687

{

2688

{

2688

struct gem *gp = netdev_priv(dev);

2689

struct gem *gp = netdev_priv(dev);

2689

struct mii_ioctl_data *data = if_mii(ifr);

2690

struct mii_ioctl_data *data = if_mii(ifr);

2690

int rc = -EOPNOTSUPP;

2691

int rc = -EOPNOTSUPP;

2691

2692

/* For SIOCGMIIREG and SIOCSMIIREG the core checks for us that

2693

/* For SIOCGMIIREG and SIOCSMIIREG the core checks for us that

2693

* netif_device_present() is true and holds rtnl_lock for us

2694

* netif_device_present() is true and holds rtnl_lock for us

2694

* so we have nothing to worry about

2695

* so we have nothing to worry about

2695

*/

2696

*/

2696

2697

switch (cmd) {

2698

switch (cmd) {

2698

case SIOCGMIIPHY: /* Get address of MII PHY in use. */

2699

case SIOCGMIIPHY: /* Get address of MII PHY in use. */

2699

data->phy_id = gp->mii_phy_addr;

2700

data->phy_id = gp->mii_phy_addr;

2700

/* Fallthrough... */

2701

/* Fallthrough... */

2701

2702

case SIOCGMIIREG: /* Read MII PHY register. */

2703

case SIOCGMIIREG: /* Read MII PHY register. */

2703

data->val_out = __phy_read(gp, data->phy_id & 0x1f,

2704

data->val_out = __phy_read(gp, data->phy_id & 0x1f,

2704

data->reg_num & 0x1f);

2705

data->reg_num & 0x1f);

2705

rc = 0;

2706

rc = 0;

2706

break;

2707

break;

2707

2708

case SIOCSMIIREG: /* Write MII PHY register. */

2709

case SIOCSMIIREG: /* Write MII PHY register. */

2709

__phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,

2710

__phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,

2710

data->val_in);

2711

data->val_in);

2711

rc = 0;

2712

rc = 0;

2712

break;

2713

break;

2713

}

2714

}

2714

return rc;

2715

return rc;

2715

}

2716

}

2716

2717

#if (!defined(CONFIG_SPARC) && !defined(CONFIG_PPC_PMAC))

2718

#if (!defined(CONFIG_SPARC) && !defined(CONFIG_PPC_PMAC))

2718

/* Fetch MAC address from vital product data of PCI ROM. */

2719

/* Fetch MAC address from vital product data of PCI ROM. */

2719

static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, unsigned char *dev_addr)

2720

static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, unsigned char *dev_addr)

2720

{

2721

{

2721

int this_offset;

2722

int this_offset;

2722

2723

for (this_offset = 0x20; this_offset < len; this_offset++) {

2724

for (this_offset = 0x20; this_offset < len; this_offset++) {

2724

void __iomem *p = rom_base + this_offset;

2725

void __iomem *p = rom_base + this_offset;

2725

int i;

2726

int i;

2726

2727

if (readb(p + 0) != 0x90 ||

2728

if (readb(p + 0) != 0x90 ||

2728

readb(p + 1) != 0x00 ||

2729

readb(p + 1) != 0x00 ||

2729

readb(p + 2) != 0x09 ||

2730

readb(p + 2) != 0x09 ||

2730

readb(p + 3) != 0x4e ||

2731

readb(p + 3) != 0x4e ||

2731

readb(p + 4) != 0x41 ||

2732

readb(p + 4) != 0x41 ||

2732

readb(p + 5) != 0x06)

2733

readb(p + 5) != 0x06)

2733

continue;

2734

continue;

2734

2735

this_offset += 6;

2736

this_offset += 6;

2736

p += 6;

2737

p += 6;

2737

2738

for (i = 0; i < 6; i++)

2739

for (i = 0; i < 6; i++)

2739

dev_addr[i] = readb(p + i);

2740

dev_addr[i] = readb(p + i);

2740

return 1;

2741

return 1;

2741

}

2742

}

2742

return 0;

2743

return 0;

2743

}

2744

}

2744

2745

static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr)

2746

static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr)

2746

{

2747

{

2747

size_t size;

2748

size_t size;

2748

void __iomem *p = pci_map_rom(pdev, &size);

2749

void __iomem *p = pci_map_rom(pdev, &size);

2749

2750

if (p) {

2751

if (p) {

2751

int found;

2752

int found;

2752

2753

found = readb(p) == 0x55 &&

2754

found = readb(p) == 0x55 &&

2754

readb(p + 1) == 0xaa &&

2755

readb(p + 1) == 0xaa &&

2755

find_eth_addr_in_vpd(p, (64 * 1024), dev_addr);

2756

find_eth_addr_in_vpd(p, (64 * 1024), dev_addr);

2756

pci_unmap_rom(pdev, p);

2757

pci_unmap_rom(pdev, p);

2757

if (found)

2758

if (found)

2758

return;

2759

return;

2759

}

2760

}

2760

2761

/* Sun MAC prefix then 3 random bytes. */

2762

/* Sun MAC prefix then 3 random bytes. */

2762

dev_addr[0] = 0x08;

2763

dev_addr[0] = 0x08;

2763

dev_addr[1] = 0x00;

2764

dev_addr[1] = 0x00;

2764

dev_addr[2] = 0x20;

2765

dev_addr[2] = 0x20;

2765

get_random_bytes(dev_addr + 3, 3);

2766

get_random_bytes(dev_addr + 3, 3);

2766

}

2767

}

2767

#endif /* not Sparc and not PPC */

2768

#endif /* not Sparc and not PPC */

2768

2769

static int __devinit gem_get_device_address(struct gem *gp)

2770

static int __devinit gem_get_device_address(struct gem *gp)

2770

{

2771

{

2771

#if defined(CONFIG_SPARC) || defined(CONFIG_PPC_PMAC)

2772

#if defined(CONFIG_SPARC) || defined(CONFIG_PPC_PMAC)

2772

struct net_device *dev = gp->dev;

2773

struct net_device *dev = gp->dev;

2773

const unsigned char *addr;

2774

const unsigned char *addr;

2774

2775

addr = of_get_property(gp->of_node, "local-mac-address", NULL);

2776

addr = of_get_property(gp->of_node, "local-mac-address", NULL);

2776

if (addr == NULL) {

2777

if (addr == NULL) {

2777

#ifdef CONFIG_SPARC

2778

#ifdef CONFIG_SPARC

2778

addr = idprom->id_ethaddr;

2779

addr = idprom->id_ethaddr;

2779

#else

2780

#else

2780

printk("\n");

2781

printk("\n");

2781

pr_err("%s: can't get mac-address\n", dev->name);

2782

pr_err("%s: can't get mac-address\n", dev->name);

2782

return -1;

2783

return -1;

2783

#endif

2784

#endif

2784

}

2785

}

2785

memcpy(dev->dev_addr, addr, 6);

2786

memcpy(dev->dev_addr, addr, 6);

2786

#else

2787

#else

2787

get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr);

2788

get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr);

2788

#endif

2789

#endif

2789

return 0;

2790

return 0;

2790

}

2791

}

2791

2792

static void gem_remove_one(struct pci_dev *pdev)

2793

static void gem_remove_one(struct pci_dev *pdev)

2793

{

2794

{

2794

struct net_device *dev = pci_get_drvdata(pdev);

2795

struct net_device *dev = pci_get_drvdata(pdev);

2795

2796

if (dev) {

2797

if (dev) {

2797

struct gem *gp = netdev_priv(dev);

2798

struct gem *gp = netdev_priv(dev);

2798

2799

unregister_netdev(dev);

2800

unregister_netdev(dev);

2800

2801

/* Ensure reset task is truely gone */

2802

/* Ensure reset task is truely gone */

2802

cancel_work_sync(&gp->reset_task);

2803

cancel_work_sync(&gp->reset_task);

2803

2804

/* Free resources */

2805

/* Free resources */

2805

pci_free_consistent(pdev,

2806

pci_free_consistent(pdev,

2806

sizeof(struct gem_init_block),

2807

sizeof(struct gem_init_block),

2807

gp->init_block,

2808

gp->init_block,

2808

gp->gblock_dvma);

2809

gp->gblock_dvma);

2809

iounmap(gp->regs);

2810

iounmap(gp->regs);

2810

pci_release_regions(pdev);

2811

pci_release_regions(pdev);

2811

free_netdev(dev);

2812

free_netdev(dev);

2812

2813

pci_set_drvdata(pdev, NULL);

2814

pci_set_drvdata(pdev, NULL);

2814

}

2815

}

2815

}

2816

}

2816

2817

static const struct net_device_ops gem_netdev_ops = {

2818

static const struct net_device_ops gem_netdev_ops = {

2818

.ndo_open = gem_open,

2819

.ndo_open = gem_open,

2819

.ndo_stop = gem_close,

2820

.ndo_stop = gem_close,

2820

.ndo_start_xmit = gem_start_xmit,

2821

.ndo_start_xmit = gem_start_xmit,

2821

.ndo_get_stats = gem_get_stats,

2822

.ndo_get_stats = gem_get_stats,

2822

.ndo_set_multicast_list = gem_set_multicast,

2823

.ndo_set_multicast_list = gem_set_multicast,

2823

.ndo_do_ioctl = gem_ioctl,

2824

.ndo_do_ioctl = gem_ioctl,

2824

.ndo_tx_timeout = gem_tx_timeout,

2825

.ndo_tx_timeout = gem_tx_timeout,

2825

.ndo_change_mtu = gem_change_mtu,

2826

.ndo_change_mtu = gem_change_mtu,

2826

.ndo_validate_addr = eth_validate_addr,

2827

.ndo_validate_addr = eth_validate_addr,

2827

.ndo_set_mac_address = gem_set_mac_address,

2828

.ndo_set_mac_address = gem_set_mac_address,

2828

#ifdef CONFIG_NET_POLL_CONTROLLER

2829

#ifdef CONFIG_NET_POLL_CONTROLLER

2829

.ndo_poll_controller = gem_poll_controller,

2830

.ndo_poll_controller = gem_poll_controller,

2830

#endif

2831

#endif

2831

};

2832

};

2832

2833

static int __devinit gem_init_one(struct pci_dev *pdev,

2834

static int __devinit gem_init_one(struct pci_dev *pdev,

2834

const struct pci_device_id *ent)

2835

const struct pci_device_id *ent)

2835

{

2836

{

2836

unsigned long gemreg_base, gemreg_len;

2837

unsigned long gemreg_base, gemreg_len;

2837

struct net_device *dev;

2838

struct net_device *dev;

2838

struct gem *gp;

2839

struct gem *gp;

2839

int err, pci_using_dac;

2840

int err, pci_using_dac;

2840

2841

printk_once(KERN_INFO "%s", version);

2842

printk_once(KERN_INFO "%s", version);

2842

2843

/* Apple gmac note: during probe, the chip is powered up by

2844

/* Apple gmac note: during probe, the chip is powered up by

2844

* the arch code to allow the code below to work (and to let

2845

* the arch code to allow the code below to work (and to let

2845

* the chip be probed on the config space. It won't stay powered

2846

* the chip be probed on the config space. It won't stay powered

2846

* up until the interface is brought up however, so we can't rely

2847

* up until the interface is brought up however, so we can't rely

2847

* on register configuration done at this point.

2848

* on register configuration done at this point.

2848

*/

2849

*/

2849

err = pci_enable_device(pdev);

2850

err = pci_enable_device(pdev);

2850

if (err) {

2851

if (err) {

2851

pr_err("Cannot enable MMIO operation, aborting\n");

2852

pr_err("Cannot enable MMIO operation, aborting\n");

2852

return err;

2853

return err;

2853

}

2854

}

2854

pci_set_master(pdev);

2855

pci_set_master(pdev);

2855

2856

/* Configure DMA attributes. */

2857

/* Configure DMA attributes. */

2857

2858

/* All of the GEM documentation states that 64-bit DMA addressing

2859

/* All of the GEM documentation states that 64-bit DMA addressing

2859

* is fully supported and should work just fine. However the

2860

* is fully supported and should work just fine. However the

2860

* front end for RIO based GEMs is different and only supports

2861

* front end for RIO based GEMs is different and only supports

2861

* 32-bit addressing.

2862

* 32-bit addressing.

2862

*

2863

*

2863

* For now we assume the various PPC GEMs are 32-bit only as well.

2864

* For now we assume the various PPC GEMs are 32-bit only as well.

2864

*/

2865

*/

2865

if (pdev->vendor == PCI_VENDOR_ID_SUN &&

2866

if (pdev->vendor == PCI_VENDOR_ID_SUN &&

2866

pdev->device == PCI_DEVICE_ID_SUN_GEM &&

2867

pdev->device == PCI_DEVICE_ID_SUN_GEM &&

2867

!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {

2868

!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {

2868

pci_using_dac = 1;

2869

pci_using_dac = 1;

2869

} else {

2870

} else {

2870

err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));

2871

err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));

2871

if (err) {

2872

if (err) {

2872

pr_err("No usable DMA configuration, aborting\n");

2873

pr_err("No usable DMA configuration, aborting\n");

2873

goto err_disable_device;

2874

goto err_disable_device;

2874

}

2875

}

2875

pci_using_dac = 0;

2876

pci_using_dac = 0;

2876

}

2877

}

2877

2878

gemreg_base = pci_resource_start(pdev, 0);

2879

gemreg_base = pci_resource_start(pdev, 0);

2879

gemreg_len = pci_resource_len(pdev, 0);

2880

gemreg_len = pci_resource_len(pdev, 0);

2880

2881

if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {

2882

if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {

2882

pr_err("Cannot find proper PCI device base address, aborting\n");

2883

pr_err("Cannot find proper PCI device base address, aborting\n");

2883

err = -ENODEV;

2884

err = -ENODEV;

2884

goto err_disable_device;

2885

goto err_disable_device;

2885

}

2886

}

2886

2887

dev = alloc_etherdev(sizeof(*gp));

2888

dev = alloc_etherdev(sizeof(*gp));

2888

if (!dev) {

2889

if (!dev) {

2889

pr_err("Etherdev alloc failed, aborting\n");

2890

pr_err("Etherdev alloc failed, aborting\n");

2890

err = -ENOMEM;

2891

err = -ENOMEM;

2891

goto err_disable_device;

2892

goto err_disable_device;

2892

}

2893

}

2893

SET_NETDEV_DEV(dev, &pdev->dev);

2894

SET_NETDEV_DEV(dev, &pdev->dev);

2894

2895

gp = netdev_priv(dev);

2896

gp = netdev_priv(dev);

2896

2897

err = pci_request_regions(pdev, DRV_NAME);

2898

err = pci_request_regions(pdev, DRV_NAME);

2898

if (err) {

2899

if (err) {

2899

pr_err("Cannot obtain PCI resources, aborting\n");

2900

pr_err("Cannot obtain PCI resources, aborting\n");

2900

goto err_out_free_netdev;

2901

goto err_out_free_netdev;

2901

}

2902

}

2902

2903

gp->pdev = pdev;

2904

gp->pdev = pdev;

2904

dev->base_addr = (long) pdev;

2905

dev->base_addr = (long) pdev;

2905

gp->dev = dev;

2906

gp->dev = dev;

2906

2907

gp->msg_enable = DEFAULT_MSG;

2908

gp->msg_enable = DEFAULT_MSG;

2908

2909

init_timer(&gp->link_timer);

2910

init_timer(&gp->link_timer);

2910

gp->link_timer.function = gem_link_timer;

2911

gp->link_timer.function = gem_link_timer;

2911

gp->link_timer.data = (unsigned long) gp;

2912

gp->link_timer.data = (unsigned long) gp;

2912

2913

INIT_WORK(&gp->reset_task, gem_reset_task);

2914

INIT_WORK(&gp->reset_task, gem_reset_task);

2914

2915

gp->lstate = link_down;

2916

gp->lstate = link_down;

2916

gp->timer_ticks = 0;

2917

gp->timer_ticks = 0;

2917

netif_carrier_off(dev);

2918

netif_carrier_off(dev);

2918

2919

gp->regs = ioremap(gemreg_base, gemreg_len);

2920

gp->regs = ioremap(gemreg_base, gemreg_len);

2920

if (!gp->regs) {

2921

if (!gp->regs) {

2921

pr_err("Cannot map device registers, aborting\n");

2922

pr_err("Cannot map device registers, aborting\n");

2922

err = -EIO;

2923

err = -EIO;

2923

goto err_out_free_res;

2924

goto err_out_free_res;

2924

}

2925

}

2925

2926

/* On Apple, we want a reference to the Open Firmware device-tree

2927

/* On Apple, we want a reference to the Open Firmware device-tree

2927

* node. We use it for clock control.

2928

* node. We use it for clock control.

2928

*/

2929

*/

2929

#if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC)

2930

#if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC)

2930

gp->of_node = pci_device_to_OF_node(pdev);

2931

gp->of_node = pci_device_to_OF_node(pdev);

2931

#endif

2932

#endif

2932

2933

/* Only Apple version supports WOL afaik */

2934

/* Only Apple version supports WOL afaik */

2934

if (pdev->vendor == PCI_VENDOR_ID_APPLE)

2935

if (pdev->vendor == PCI_VENDOR_ID_APPLE)

2935

gp->has_wol = 1;

2936

gp->has_wol = 1;

2936

2937

/* Make sure cell is enabled */

2938

/* Make sure cell is enabled */

2938

gem_get_cell(gp);

2939

gem_get_cell(gp);

2939

2940

/* Make sure everything is stopped and in init state */

2941

/* Make sure everything is stopped and in init state */

2941

gem_reset(gp);

2942

gem_reset(gp);

2942

2943

/* Fill up the mii_phy structure (even if we won't use it) */

2944

/* Fill up the mii_phy structure (even if we won't use it) */

2944

gp->phy_mii.dev = dev;

2945

gp->phy_mii.dev = dev;

2945

gp->phy_mii.mdio_read = _phy_read;

2946

gp->phy_mii.mdio_read = _phy_read;

2946

gp->phy_mii.mdio_write = _phy_write;

2947

gp->phy_mii.mdio_write = _phy_write;

2947

#ifdef CONFIG_PPC_PMAC

2948

#ifdef CONFIG_PPC_PMAC

2948

gp->phy_mii.platform_data = gp->of_node;

2949

gp->phy_mii.platform_data = gp->of_node;

2949

#endif

2950

#endif

2950

/* By default, we start with autoneg */

2951

/* By default, we start with autoneg */

2951

gp->want_autoneg = 1;

2952

gp->want_autoneg = 1;

2952

2953

/* Check fifo sizes, PHY type, etc... */

2954

/* Check fifo sizes, PHY type, etc... */

2954

if (gem_check_invariants(gp)) {

2955

if (gem_check_invariants(gp)) {

2955

err = -ENODEV;

2956

err = -ENODEV;

2956

goto err_out_iounmap;

2957

goto err_out_iounmap;

2957

}

2958

}

2958

2959

/* It is guaranteed that the returned buffer will be at least

2960

/* It is guaranteed that the returned buffer will be at least

2960

* PAGE_SIZE aligned.

2961

* PAGE_SIZE aligned.

2961

*/

2962

*/

2962

gp->init_block = (struct gem_init_block *)

2963

gp->init_block = (struct gem_init_block *)

2963

pci_alloc_consistent(pdev, sizeof(struct gem_init_block),

2964

pci_alloc_consistent(pdev, sizeof(struct gem_init_block),

2964

&gp->gblock_dvma);

2965

&gp->gblock_dvma);

2965

if (!gp->init_block) {

2966

if (!gp->init_block) {

2966

pr_err("Cannot allocate init block, aborting\n");

2967

pr_err("Cannot allocate init block, aborting\n");

2967

err = -ENOMEM;

2968

err = -ENOMEM;

2968

goto err_out_iounmap;

2969

goto err_out_iounmap;

2969

}

2970

}

2970

2971

if (gem_get_device_address(gp))

2972

if (gem_get_device_address(gp))

2972

goto err_out_free_consistent;

2973

goto err_out_free_consistent;

2973

2974

dev->netdev_ops = &gem_netdev_ops;

2975

dev->netdev_ops = &gem_netdev_ops;

2975

netif_napi_add(dev, &gp->napi, gem_poll, 64);

2976

netif_napi_add(dev, &gp->napi, gem_poll, 64);

2976

dev->ethtool_ops = &gem_ethtool_ops;

2977

dev->ethtool_ops = &gem_ethtool_ops;

2977

dev->watchdog_timeo = 5 * HZ;

2978

dev->watchdog_timeo = 5 * HZ;

2978

dev->irq = pdev->irq;

2979

dev->irq = pdev->irq;

2979

dev->dma = 0;

2980

dev->dma = 0;

2980

2981

/* Set that now, in case PM kicks in now */

2982

/* Set that now, in case PM kicks in now */

2982

pci_set_drvdata(pdev, dev);

2983

pci_set_drvdata(pdev, dev);

2983

2984

/* We can do scatter/gather and HW checksum */

2985

/* We can do scatter/gather and HW checksum */

2985

dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM;

2986

dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM;

2986

dev->features |= dev->hw_features | NETIF_F_RXCSUM;

2987

dev->features |= dev->hw_features | NETIF_F_RXCSUM;

2987

if (pci_using_dac)

2988

if (pci_using_dac)

2988

dev->features |= NETIF_F_HIGHDMA;

2989

dev->features |= NETIF_F_HIGHDMA;

2989

2990

/* Register with kernel */

2991

/* Register with kernel */

2991

if (register_netdev(dev)) {

2992

if (register_netdev(dev)) {

2992

pr_err("Cannot register net device, aborting\n");

2993

pr_err("Cannot register net device, aborting\n");

2993

err = -ENOMEM;

2994

err = -ENOMEM;

2994

goto err_out_free_consistent;

2995

goto err_out_free_consistent;

2995

}

2996

}

2996

2997

/* Undo the get_cell with appropriate locking (we could use

2998

/* Undo the get_cell with appropriate locking (we could use

2998

* ndo_init/uninit but that would be even more clumsy imho)

2999

* ndo_init/uninit but that would be even more clumsy imho)

2999

*/

3000

*/

3000

rtnl_lock();

3001

rtnl_lock();

3001

gem_put_cell(gp);

3002

gem_put_cell(gp);

3002

rtnl_unlock();

3003

rtnl_unlock();

3003

3004

netdev_info(dev, "Sun GEM (PCI) 10/100/1000BaseT Ethernet %pM\n",

3005

netdev_info(dev, "Sun GEM (PCI) 10/100/1000BaseT Ethernet %pM\n",

3005

dev->dev_addr);

3006

dev->dev_addr);

3006

return 0;

3007

return 0;

3007

3008

err_out_free_consistent:

3009

err_out_free_consistent:

3009

gem_remove_one(pdev);

3010

gem_remove_one(pdev);

3010

err_out_iounmap:

3011

err_out_iounmap:

3011

gem_put_cell(gp);

3012

gem_put_cell(gp);

3012

iounmap(gp->regs);

3013

iounmap(gp->regs);

3013

3014

err_out_free_res:

3015

err_out_free_res:

3015

pci_release_regions(pdev);

3016

pci_release_regions(pdev);

3016

3017

err_out_free_netdev:

3018

err_out_free_netdev:

3018

free_netdev(dev);

3019

free_netdev(dev);

3019

err_disable_device:

3020

err_disable_device:

3020

pci_disable_device(pdev);

3021

pci_disable_device(pdev);

3021

return err;

3022

return err;

3022

3023

}

3024

}

3024

3025

3026

static struct pci_driver gem_driver = {

3027

static struct pci_driver gem_driver = {

3027

.name = GEM_MODULE_NAME,

3028

.name = GEM_MODULE_NAME,

3028

.id_table = gem_pci_tbl,

3029

.id_table = gem_pci_tbl,

3029

.probe = gem_init_one,

3030

.probe = gem_init_one,

3030

.remove = gem_remove_one,

3031

.remove = gem_remove_one,

3031

#ifdef CONFIG_PM

3032

#ifdef CONFIG_PM

3032

.suspend = gem_suspend,

3033

.suspend = gem_suspend,

3033

.resume = gem_resume,

3034

.resume = gem_resume,

3034

#endif /* CONFIG_PM */

3035

#endif /* CONFIG_PM */

3035

};

3036

};

3036

3037

static int __init gem_init(void)

3038

static int __init gem_init(void)

3038

{

3039

{

3039

return pci_register_driver(&gem_driver);

3040

return pci_register_driver(&gem_driver);

3040

}

3041

}

3041

3042

static void __exit gem_cleanup(void)

3043

static void __exit gem_cleanup(void)

3043

{

3044

{

3044

pci_unregister_driver(&gem_driver);

3045

pci_unregister_driver(&gem_driver);

3045

}

3046

}

3046

3047

module_init(gem_init);

3048

module_init(gem_init);

3048

module_exit(gem_cleanup);

3049

module_exit(gem_cleanup);

GITLAB

sungem: fix compile failure caused by trivial #include consolidation

 /* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
  * sungem.c: Sun GEM ethernet driver.
  *
  * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
  *
  * Support for Apple GMAC and assorted PHYs, WOL, Power Management
  * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org)
  * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp.
  *
  * NAPI and NETPOLL support
  * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com)
  *
  */
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/types.h>
 #include <linux/fcntl.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/in.h>
 #include <linux/sched.h>
 #include <linux/string.h>
 #include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/pci.h>
 #include <linux/dma-mapping.h>
 #include <linux/netdevice.h>
 #include <linux/etherdevice.h>
 #include <linux/skbuff.h>
 #include <linux/mii.h>
 #include <linux/ethtool.h>
 #include <linux/crc32.h>
 #include <linux/random.h>
 #include <linux/workqueue.h>
 #include <linux/if_vlan.h>
 #include <linux/bitops.h>
 #include <linux/mm.h>
 #include <linux/gfp.h>
 #include <asm/system.h>
 #include <asm/io.h>
 #include <asm/byteorder.h>
 #include <asm/uaccess.h>
 #include <asm/irq.h>
-#include <asm/prom.h>
 #ifdef CONFIG_SPARC
 #include <asm/idprom.h>
+#include <asm/prom.h>
 #endif
 #ifdef CONFIG_PPC_PMAC
 #include <asm/pci-bridge.h>
+#include <asm/prom.h>
 #include <asm/machdep.h>
 #include <asm/pmac_feature.h>
 #endif
 #include "sungem_phy.h"
 #include "sungem.h"
 /* Stripping FCS is causing problems, disabled for now */
 #undef STRIP_FCS
 #define DEFAULT_MSG	(NETIF_MSG_DRV		| \
 			 NETIF_MSG_PROBE	| \
 			 NETIF_MSG_LINK)
 #define ADVERTISE_MASK	(SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
 			 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
 			 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | \
 			 SUPPORTED_Pause | SUPPORTED_Autoneg)
 #define DRV_NAME	"sungem"
 #define DRV_VERSION	"1.0"
 #define DRV_AUTHOR	"David S. Miller <davem@redhat.com>"
 static char version[] __devinitdata =
         DRV_NAME ".c:v" DRV_VERSION " " DRV_AUTHOR "\n";
 MODULE_AUTHOR(DRV_AUTHOR);
 MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
 MODULE_LICENSE("GPL");
 #define GEM_MODULE_NAME	"gem"
 static DEFINE_PCI_DEVICE_TABLE(gem_pci_tbl) = {
 	{ PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,
 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 	/* These models only differ from the original GEM in
 	 * that their tx/rx fifos are of a different size and
 	 * they only support 10/100 speeds. -DaveM
 	 *
 	 * Apple's GMAC does support gigabit on machines with
 	 * the BCM54xx PHYs. -BenH
 	 */
 	{ PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,
 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 	{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,
 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 	{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,
 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 	{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,
 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 	{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC,
 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 	{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_SUNGEM,
 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 	{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_GMAC,
 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 	{0, }
 };
 MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
 static u16 __phy_read(struct gem *gp, int phy_addr, int reg)
 {
 	u32 cmd;
 	int limit = 10000;
 	cmd  = (1 << 30);
 	cmd |= (2 << 28);
 	cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
 	cmd |= (reg << 18) & MIF_FRAME_REGAD;
 	cmd |= (MIF_FRAME_TAMSB);
 	writel(cmd, gp->regs + MIF_FRAME);
 	while (--limit) {
 		cmd = readl(gp->regs + MIF_FRAME);
 		if (cmd & MIF_FRAME_TALSB)
 			break;
 		udelay(10);
 	}
 	if (!limit)
 		cmd = 0xffff;
 	return cmd & MIF_FRAME_DATA;
 }
 static inline int _phy_read(struct net_device *dev, int mii_id, int reg)
 {
 	struct gem *gp = netdev_priv(dev);
 	return __phy_read(gp, mii_id, reg);
 }
 static inline u16 phy_read(struct gem *gp, int reg)
 {
 	return __phy_read(gp, gp->mii_phy_addr, reg);
 }
 static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
 {
 	u32 cmd;
 	int limit = 10000;
 	cmd  = (1 << 30);
 	cmd |= (1 << 28);
 	cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
 	cmd |= (reg << 18) & MIF_FRAME_REGAD;
 	cmd |= (MIF_FRAME_TAMSB);
 	cmd |= (val & MIF_FRAME_DATA);
 	writel(cmd, gp->regs + MIF_FRAME);
 	while (limit--) {
 		cmd = readl(gp->regs + MIF_FRAME);
 		if (cmd & MIF_FRAME_TALSB)
 			break;
 		udelay(10);
 	}
 }
 static inline void _phy_write(struct net_device *dev, int mii_id, int reg, int val)
 {
 	struct gem *gp = netdev_priv(dev);
 	__phy_write(gp, mii_id, reg, val & 0xffff);
 }
 static inline void phy_write(struct gem *gp, int reg, u16 val)
 {
 	__phy_write(gp, gp->mii_phy_addr, reg, val);
 }
 static inline void gem_enable_ints(struct gem *gp)
 {
 	/* Enable all interrupts but TXDONE */
 	writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
 }
 static inline void gem_disable_ints(struct gem *gp)
 {
 	/* Disable all interrupts, including TXDONE */
 	writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
 	(void)readl(gp->regs + GREG_IMASK); /* write posting */
 }
 static void gem_get_cell(struct gem *gp)
 {
 	BUG_ON(gp->cell_enabled < 0);
 	gp->cell_enabled++;
 #ifdef CONFIG_PPC_PMAC
 	if (gp->cell_enabled == 1) {
 		mb();
 		pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);
 		udelay(10);
 	}
 #endif /* CONFIG_PPC_PMAC */
 }
 /* Turn off the chip's clock */
 static void gem_put_cell(struct gem *gp)
 {
 	BUG_ON(gp->cell_enabled <= 0);
 	gp->cell_enabled--;
 #ifdef CONFIG_PPC_PMAC
 	if (gp->cell_enabled == 0) {
 		mb();
 		pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);
 		udelay(10);
 	}
 #endif /* CONFIG_PPC_PMAC */
 }
 static inline void gem_netif_stop(struct gem *gp)
 {
 	gp->dev->trans_start = jiffies;	/* prevent tx timeout */
 	napi_disable(&gp->napi);
 	netif_tx_disable(gp->dev);
 }
 static inline void gem_netif_start(struct gem *gp)
 {
 	/* NOTE: unconditional netif_wake_queue is only
 	 * appropriate so long as all callers are assured to
 	 * have free tx slots.
 	 */
 	netif_wake_queue(gp->dev);
 	napi_enable(&gp->napi);
 }
 static void gem_schedule_reset(struct gem *gp)
 {
 	gp->reset_task_pending = 1;
 	schedule_work(&gp->reset_task);
 }
 static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)
 {
 	if (netif_msg_intr(gp))
 		printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);
 }
 static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
 {
 	u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
 	u32 pcs_miistat;
 	if (netif_msg_intr(gp))
 		printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n",
 			gp->dev->name, pcs_istat);
 	if (!(pcs_istat & PCS_ISTAT_LSC)) {
 		netdev_err(dev, "PCS irq but no link status change???\n");
 		return 0;
 	}
 	/* The link status bit latches on zero, so you must
 	 * read it twice in such a case to see a transition
 	 * to the link being up.
 	 */
 	pcs_miistat = readl(gp->regs + PCS_MIISTAT);
 	if (!(pcs_miistat & PCS_MIISTAT_LS))
 		pcs_miistat |=
 			(readl(gp->regs + PCS_MIISTAT) &
 			 PCS_MIISTAT_LS);
 	if (pcs_miistat & PCS_MIISTAT_ANC) {
 		/* The remote-fault indication is only valid
 		 * when autoneg has completed.
 		 */
 		if (pcs_miistat & PCS_MIISTAT_RF)
 			netdev_info(dev, "PCS AutoNEG complete, RemoteFault\n");
 		else
 			netdev_info(dev, "PCS AutoNEG complete\n");
 	}
 	if (pcs_miistat & PCS_MIISTAT_LS) {
 		netdev_info(dev, "PCS link is now up\n");
 		netif_carrier_on(gp->dev);
 	} else {
 		netdev_info(dev, "PCS link is now down\n");
 		netif_carrier_off(gp->dev);
 		/* If this happens and the link timer is not running,
 		 * reset so we re-negotiate.
 		 */
 		if (!timer_pending(&gp->link_timer))
 			return 1;
 	}
 	return 0;
 }
 static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
 {
 	u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
 	if (netif_msg_intr(gp))
 		printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
 			gp->dev->name, txmac_stat);
 	/* Defer timer expiration is quite normal,
 	 * don't even log the event.
 	 */
 	if ((txmac_stat & MAC_TXSTAT_DTE) &&
 	    !(txmac_stat & ~MAC_TXSTAT_DTE))
 		return 0;
 	if (txmac_stat & MAC_TXSTAT_URUN) {
 		netdev_err(dev, "TX MAC xmit underrun\n");
 		dev->stats.tx_fifo_errors++;
 	}
 	if (txmac_stat & MAC_TXSTAT_MPE) {
 		netdev_err(dev, "TX MAC max packet size error\n");
 		dev->stats.tx_errors++;
 	}
 	/* The rest are all cases of one of the 16-bit TX
 	 * counters expiring.
 	 */
 	if (txmac_stat & MAC_TXSTAT_NCE)
 		dev->stats.collisions += 0x10000;
 	if (txmac_stat & MAC_TXSTAT_ECE) {
 		dev->stats.tx_aborted_errors += 0x10000;
 		dev->stats.collisions += 0x10000;
 	}
 	if (txmac_stat & MAC_TXSTAT_LCE) {
 		dev->stats.tx_aborted_errors += 0x10000;
 		dev->stats.collisions += 0x10000;
 	}
 	/* We do not keep track of MAC_TXSTAT_FCE and
 	 * MAC_TXSTAT_PCE events.
 	 */
 	return 0;
 }
 /* When we get a RX fifo overflow, the RX unit in GEM is probably hung
  * so we do the following.
  *
  * If any part of the reset goes wrong, we return 1 and that causes the
  * whole chip to be reset.
  */
 static int gem_rxmac_reset(struct gem *gp)
 {
 	struct net_device *dev = gp->dev;
 	int limit, i;
 	u64 desc_dma;
 	u32 val;
 	/* First, reset & disable MAC RX. */
 	writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
 	for (limit = 0; limit < 5000; limit++) {
 		if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))
 			break;
 		udelay(10);
 	}
 	if (limit == 5000) {
 		netdev_err(dev, "RX MAC will not reset, resetting whole chip\n");
 		return 1;
 	}
 	writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,
 	       gp->regs + MAC_RXCFG);
 	for (limit = 0; limit < 5000; limit++) {
 		if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
 			break;
 		udelay(10);
 	}
 	if (limit == 5000) {
 		netdev_err(dev, "RX MAC will not disable, resetting whole chip\n");
 		return 1;
 	}
 	/* Second, disable RX DMA. */
 	writel(0, gp->regs + RXDMA_CFG);
 	for (limit = 0; limit < 5000; limit++) {
 		if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
 			break;
 		udelay(10);
 	}
 	if (limit == 5000) {
 		netdev_err(dev, "RX DMA will not disable, resetting whole chip\n");
 		return 1;
 	}
 	udelay(5000);
 	/* Execute RX reset command. */
 	writel(gp->swrst_base | GREG_SWRST_RXRST,
 	       gp->regs + GREG_SWRST);
 	for (limit = 0; limit < 5000; limit++) {
 		if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))
 			break;
 		udelay(10);
 	}
 	if (limit == 5000) {
 		netdev_err(dev, "RX reset command will not execute, resetting whole chip\n");
 		return 1;
 	}
 	/* Refresh the RX ring. */
 	for (i = 0; i < RX_RING_SIZE; i++) {
 		struct gem_rxd *rxd = &gp->init_block->rxd[i];
 		if (gp->rx_skbs[i] == NULL) {
 			netdev_err(dev, "Parts of RX ring empty, resetting whole chip\n");
 			return 1;
 		}
 		rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
 	}
 	gp->rx_new = gp->rx_old = 0;
 	/* Now we must reprogram the rest of RX unit. */
 	desc_dma = (u64) gp->gblock_dvma;
 	desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
 	writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
 	writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
 	writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
 	val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
 	       ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
 	writel(val, gp->regs + RXDMA_CFG);
 	if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
 		writel(((5 & RXDMA_BLANK_IPKTS) |
 			((8 << 12) & RXDMA_BLANK_ITIME)),
 		       gp->regs + RXDMA_BLANK);
 	else
 		writel(((5 & RXDMA_BLANK_IPKTS) |
 			((4 << 12) & RXDMA_BLANK_ITIME)),
 		       gp->regs + RXDMA_BLANK);
 	val  = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
 	val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
 	writel(val, gp->regs + RXDMA_PTHRESH);
 	val = readl(gp->regs + RXDMA_CFG);
 	writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
 	writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
 	val = readl(gp->regs + MAC_RXCFG);
 	writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
 	return 0;
 }
 static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
 {
 	u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
 	int ret = 0;
 	if (netif_msg_intr(gp))
 		printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n",
 			gp->dev->name, rxmac_stat);
 	if (rxmac_stat & MAC_RXSTAT_OFLW) {
 		u32 smac = readl(gp->regs + MAC_SMACHINE);
 		netdev_err(dev, "RX MAC fifo overflow smac[%08x]\n", smac);
 		dev->stats.rx_over_errors++;
 		dev->stats.rx_fifo_errors++;
 		ret = gem_rxmac_reset(gp);
 	}
 	if (rxmac_stat & MAC_RXSTAT_ACE)
 		dev->stats.rx_frame_errors += 0x10000;
 	if (rxmac_stat & MAC_RXSTAT_CCE)
 		dev->stats.rx_crc_errors += 0x10000;
 	if (rxmac_stat & MAC_RXSTAT_LCE)
 		dev->stats.rx_length_errors += 0x10000;
 	/* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
 	 * events.
 	 */
 	return ret;
 }
 static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
 {
 	u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
 	if (netif_msg_intr(gp))
 		printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n",
 			gp->dev->name, mac_cstat);
 	/* This interrupt is just for pause frame and pause
 	 * tracking.  It is useful for diagnostics and debug
 	 * but probably by default we will mask these events.
 	 */
 	if (mac_cstat & MAC_CSTAT_PS)
 		gp->pause_entered++;
 	if (mac_cstat & MAC_CSTAT_PRCV)
 		gp->pause_last_time_recvd = (mac_cstat >> 16);
 	return 0;
 }
 static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
 {
 	u32 mif_status = readl(gp->regs + MIF_STATUS);
 	u32 reg_val, changed_bits;
 	reg_val = (mif_status & MIF_STATUS_DATA) >> 16;
 	changed_bits = (mif_status & MIF_STATUS_STAT);
 	gem_handle_mif_event(gp, reg_val, changed_bits);
 	return 0;
 }
 static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
 {
 	u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
 	if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
 	    gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
 		netdev_err(dev, "PCI error [%04x]", pci_estat);
 		if (pci_estat & GREG_PCIESTAT_BADACK)
 			pr_cont(" <No ACK64# during ABS64 cycle>");
 		if (pci_estat & GREG_PCIESTAT_DTRTO)
 			pr_cont(" <Delayed transaction timeout>");
 		if (pci_estat & GREG_PCIESTAT_OTHER)
 			pr_cont(" <other>");
 		pr_cont("\n");
 	} else {
 		pci_estat |= GREG_PCIESTAT_OTHER;
 		netdev_err(dev, "PCI error\n");
 	}
 	if (pci_estat & GREG_PCIESTAT_OTHER) {
 		u16 pci_cfg_stat;
 		/* Interrogate PCI config space for the
 		 * true cause.
 		 */
 		pci_read_config_word(gp->pdev, PCI_STATUS,
 				     &pci_cfg_stat);
 		netdev_err(dev, "Read PCI cfg space status [%04x]\n",
 			   pci_cfg_stat);
 		if (pci_cfg_stat & PCI_STATUS_PARITY)
 			netdev_err(dev, "PCI parity error detected\n");
 		if (pci_cfg_stat & PCI_STATUS_SIG_TARGET_ABORT)
 			netdev_err(dev, "PCI target abort\n");
 		if (pci_cfg_stat & PCI_STATUS_REC_TARGET_ABORT)
 			netdev_err(dev, "PCI master acks target abort\n");
 		if (pci_cfg_stat & PCI_STATUS_REC_MASTER_ABORT)
 			netdev_err(dev, "PCI master abort\n");
 		if (pci_cfg_stat & PCI_STATUS_SIG_SYSTEM_ERROR)
 			netdev_err(dev, "PCI system error SERR#\n");
 		if (pci_cfg_stat & PCI_STATUS_DETECTED_PARITY)
 			netdev_err(dev, "PCI parity error\n");
 		/* Write the error bits back to clear them. */
 		pci_cfg_stat &= (PCI_STATUS_PARITY |
 				 PCI_STATUS_SIG_TARGET_ABORT |
 				 PCI_STATUS_REC_TARGET_ABORT |
 				 PCI_STATUS_REC_MASTER_ABORT |
 				 PCI_STATUS_SIG_SYSTEM_ERROR |
 				 PCI_STATUS_DETECTED_PARITY);
 		pci_write_config_word(gp->pdev,
 				      PCI_STATUS, pci_cfg_stat);
 	}
 	/* For all PCI errors, we should reset the chip. */
 	return 1;
 }
 /* All non-normal interrupt conditions get serviced here.
  * Returns non-zero if we should just exit the interrupt
  * handler right now (ie. if we reset the card which invalidates
  * all of the other original irq status bits).
  */
 static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)
 {
 	if (gem_status & GREG_STAT_RXNOBUF) {
 		/* Frame arrived, no free RX buffers available. */
 		if (netif_msg_rx_err(gp))
 			printk(KERN_DEBUG "%s: no buffer for rx frame\n",
 				gp->dev->name);
 		dev->stats.rx_dropped++;
 	}
 	if (gem_status & GREG_STAT_RXTAGERR) {
 		/* corrupt RX tag framing */
 		if (netif_msg_rx_err(gp))
 			printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
 				gp->dev->name);
 		dev->stats.rx_errors++;
 		return 1;
 	}
 	if (gem_status & GREG_STAT_PCS) {
 		if (gem_pcs_interrupt(dev, gp, gem_status))
 			return 1;
 	}
 	if (gem_status & GREG_STAT_TXMAC) {
 		if (gem_txmac_interrupt(dev, gp, gem_status))
 			return 1;
 	}
 	if (gem_status & GREG_STAT_RXMAC) {
 		if (gem_rxmac_interrupt(dev, gp, gem_status))
 			return 1;
 	}
 	if (gem_status & GREG_STAT_MAC) {
 		if (gem_mac_interrupt(dev, gp, gem_status))
 			return 1;
 	}
 	if (gem_status & GREG_STAT_MIF) {
 		if (gem_mif_interrupt(dev, gp, gem_status))
 			return 1;
 	}
 	if (gem_status & GREG_STAT_PCIERR) {
 		if (gem_pci_interrupt(dev, gp, gem_status))
 			return 1;
 	}
 	return 0;
 }
 static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)
 {
 	int entry, limit;
 	entry = gp->tx_old;
 	limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);
 	while (entry != limit) {
 		struct sk_buff *skb;
 		struct gem_txd *txd;
 		dma_addr_t dma_addr;
 		u32 dma_len;
 		int frag;
 		if (netif_msg_tx_done(gp))
 			printk(KERN_DEBUG "%s: tx done, slot %d\n",
 				gp->dev->name, entry);
 		skb = gp->tx_skbs[entry];
 		if (skb_shinfo(skb)->nr_frags) {
 			int last = entry + skb_shinfo(skb)->nr_frags;
 			int walk = entry;
 			int incomplete = 0;
 			last &= (TX_RING_SIZE - 1);
 			for (;;) {
 				walk = NEXT_TX(walk);
 				if (walk == limit)
 					incomplete = 1;
 				if (walk == last)
 					break;
 			}
 			if (incomplete)
 				break;
 		}
 		gp->tx_skbs[entry] = NULL;
 		dev->stats.tx_bytes += skb->len;
 		for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
 			txd = &gp->init_block->txd[entry];
 			dma_addr = le64_to_cpu(txd->buffer);
 			dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;
 			pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
 			entry = NEXT_TX(entry);
 		}
 		dev->stats.tx_packets++;
 		dev_kfree_skb(skb);
 	}
 	gp->tx_old = entry;
 	/* Need to make the tx_old update visible to gem_start_xmit()
 	 * before checking for netif_queue_stopped().  Without the
 	 * memory barrier, there is a small possibility that gem_start_xmit()
 	 * will miss it and cause the queue to be stopped forever.
 	 */
 	smp_mb();
 	if (unlikely(netif_queue_stopped(dev) &&
 		     TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))) {
 		struct netdev_queue *txq = netdev_get_tx_queue(dev, 0);
 		__netif_tx_lock(txq, smp_processor_id());
 		if (netif_queue_stopped(dev) &&
 		    TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
 			netif_wake_queue(dev);
 		__netif_tx_unlock(txq);
 	}
 }
 static __inline__ void gem_post_rxds(struct gem *gp, int limit)
 {
 	int cluster_start, curr, count, kick;
 	cluster_start = curr = (gp->rx_new & ~(4 - 1));
 	count = 0;
 	kick = -1;
 	wmb();
 	while (curr != limit) {
 		curr = NEXT_RX(curr);
 		if (++count == 4) {
 			struct gem_rxd *rxd =
 				&gp->init_block->rxd[cluster_start];
 			for (;;) {
 				rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
 				rxd++;
 				cluster_start = NEXT_RX(cluster_start);
 				if (cluster_start == curr)
 					break;
 			}
 			kick = curr;
 			count = 0;
 		}
 	}
 	if (kick >= 0) {
 		mb();
 		writel(kick, gp->regs + RXDMA_KICK);
 	}
 }
 #define ALIGNED_RX_SKB_ADDR(addr) \
         ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))
 static __inline__ struct sk_buff *gem_alloc_skb(struct net_device *dev, int size,
 						gfp_t gfp_flags)
 {
 	struct sk_buff *skb = alloc_skb(size + 64, gfp_flags);
 	if (likely(skb)) {
 		unsigned long offset = ALIGNED_RX_SKB_ADDR(skb->data);
 		skb_reserve(skb, offset);
 		skb->dev = dev;
 	}
 	return skb;
 }
 static int gem_rx(struct gem *gp, int work_to_do)
 {
 	struct net_device *dev = gp->dev;
 	int entry, drops, work_done = 0;
 	u32 done;
 	__sum16 csum;
 	if (netif_msg_rx_status(gp))
 		printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n",
 			gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);
 	entry = gp->rx_new;
 	drops = 0;
 	done = readl(gp->regs + RXDMA_DONE);
 	for (;;) {
 		struct gem_rxd *rxd = &gp->init_block->rxd[entry];
 		struct sk_buff *skb;
 		u64 status = le64_to_cpu(rxd->status_word);
 		dma_addr_t dma_addr;
 		int len;
 		if ((status & RXDCTRL_OWN) != 0)
 			break;
 		if (work_done >= RX_RING_SIZE || work_done >= work_to_do)
 			break;
 		/* When writing back RX descriptor, GEM writes status
 		 * then buffer address, possibly in separate transactions.
 		 * If we don't wait for the chip to write both, we could
 		 * post a new buffer to this descriptor then have GEM spam
 		 * on the buffer address.  We sync on the RX completion
 		 * register to prevent this from happening.
 		 */
 		if (entry == done) {
 			done = readl(gp->regs + RXDMA_DONE);
 			if (entry == done)
 				break;
 		}
 		/* We can now account for the work we're about to do */
 		work_done++;
 		skb = gp->rx_skbs[entry];
 		len = (status & RXDCTRL_BUFSZ) >> 16;
 		if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {
 			dev->stats.rx_errors++;
 			if (len < ETH_ZLEN)
 				dev->stats.rx_length_errors++;
 			if (len & RXDCTRL_BAD)
 				dev->stats.rx_crc_errors++;
 			/* We'll just return it to GEM. */
 		drop_it:
 			dev->stats.rx_dropped++;
 			goto next;
 		}
 		dma_addr = le64_to_cpu(rxd->buffer);
 		if (len > RX_COPY_THRESHOLD) {
 			struct sk_buff *new_skb;
 			new_skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
 			if (new_skb == NULL) {
 				drops++;
 				goto drop_it;
 			}
 			pci_unmap_page(gp->pdev, dma_addr,
 				       RX_BUF_ALLOC_SIZE(gp),
 				       PCI_DMA_FROMDEVICE);
 			gp->rx_skbs[entry] = new_skb;
 			skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET));
 			rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev,
 							       virt_to_page(new_skb->data),
 							       offset_in_page(new_skb->data),
 							       RX_BUF_ALLOC_SIZE(gp),
 							       PCI_DMA_FROMDEVICE));
 			skb_reserve(new_skb, RX_OFFSET);
 			/* Trim the original skb for the netif. */
 			skb_trim(skb, len);
 		} else {
 			struct sk_buff *copy_skb = netdev_alloc_skb(dev, len + 2);
 			if (copy_skb == NULL) {
 				drops++;
 				goto drop_it;
 			}
 			skb_reserve(copy_skb, 2);
 			skb_put(copy_skb, len);
 			pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
 			skb_copy_from_linear_data(skb, copy_skb->data, len);
 			pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
 			/* We'll reuse the original ring buffer. */
 			skb = copy_skb;
 		}
 		csum = (__force __sum16)htons((status & RXDCTRL_TCPCSUM) ^ 0xffff);
 		skb->csum = csum_unfold(csum);
 		skb->ip_summed = CHECKSUM_COMPLETE;
 		skb->protocol = eth_type_trans(skb, gp->dev);
 		napi_gro_receive(&gp->napi, skb);
 		dev->stats.rx_packets++;
 		dev->stats.rx_bytes += len;
 	next:
 		entry = NEXT_RX(entry);
 	}
 	gem_post_rxds(gp, entry);
 	gp->rx_new = entry;
 	if (drops)
 		netdev_info(gp->dev, "Memory squeeze, deferring packet\n");
 	return work_done;
 }
 static int gem_poll(struct napi_struct *napi, int budget)
 {
 	struct gem *gp = container_of(napi, struct gem, napi);
 	struct net_device *dev = gp->dev;
 	int work_done;
 	work_done = 0;
 	do {
 		/* Handle anomalies */
 		if (unlikely(gp->status & GREG_STAT_ABNORMAL)) {
 			struct netdev_queue *txq = netdev_get_tx_queue(dev, 0);
 			int reset;
 			/* We run the abnormal interrupt handling code with
 			 * the Tx lock. It only resets the Rx portion of the
 			 * chip, but we need to guard it against DMA being
 			 * restarted by the link poll timer
 			 */
 			__netif_tx_lock(txq, smp_processor_id());
 			reset = gem_abnormal_irq(dev, gp, gp->status);
 			__netif_tx_unlock(txq);
 			if (reset) {
 				gem_schedule_reset(gp);
 				napi_complete(napi);
 				return work_done;
 			}
 		}
 		/* Run TX completion thread */
 		gem_tx(dev, gp, gp->status);
 		/* Run RX thread. We don't use any locking here,
 		 * code willing to do bad things - like cleaning the
 		 * rx ring - must call napi_disable(), which
 		 * schedule_timeout()'s if polling is already disabled.
 		 */
 		work_done += gem_rx(gp, budget - work_done);
 		if (work_done >= budget)
 			return work_done;
 		gp->status = readl(gp->regs + GREG_STAT);
 	} while (gp->status & GREG_STAT_NAPI);
 	napi_complete(napi);
 	gem_enable_ints(gp);
 	return work_done;
 }
 static irqreturn_t gem_interrupt(int irq, void *dev_id)
 {
 	struct net_device *dev = dev_id;
 	struct gem *gp = netdev_priv(dev);
 	if (napi_schedule_prep(&gp->napi)) {
 		u32 gem_status = readl(gp->regs + GREG_STAT);
 		if (unlikely(gem_status == 0)) {
 			napi_enable(&gp->napi);
 			return IRQ_NONE;
 		}
 		if (netif_msg_intr(gp))
 			printk(KERN_DEBUG "%s: gem_interrupt() gem_status: 0x%x\n",
 			       gp->dev->name, gem_status);
 		gp->status = gem_status;
 		gem_disable_ints(gp);
 		__napi_schedule(&gp->napi);
 	}
 	/* If polling was disabled at the time we received that
 	 * interrupt, we may return IRQ_HANDLED here while we
 	 * should return IRQ_NONE. No big deal...
 	 */
 	return IRQ_HANDLED;
 }
 #ifdef CONFIG_NET_POLL_CONTROLLER
 static void gem_poll_controller(struct net_device *dev)
 {
 	struct gem *gp = netdev_priv(dev);
 	disable_irq(gp->pdev->irq);
 	gem_interrupt(gp->pdev->irq, dev);
 	enable_irq(gp->pdev->irq);
 }
 #endif
 static void gem_tx_timeout(struct net_device *dev)
 {
 	struct gem *gp = netdev_priv(dev);
 	netdev_err(dev, "transmit timed out, resetting\n");
 	netdev_err(dev, "TX_STATE[%08x:%08x:%08x]\n",
 		   readl(gp->regs + TXDMA_CFG),
 		   readl(gp->regs + MAC_TXSTAT),
 		   readl(gp->regs + MAC_TXCFG));
 	netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n",
 		   readl(gp->regs + RXDMA_CFG),
 		   readl(gp->regs + MAC_RXSTAT),
 		   readl(gp->regs + MAC_RXCFG));
 	gem_schedule_reset(gp);
 }
 static __inline__ int gem_intme(int entry)
 {
 	/* Algorithm: IRQ every 1/2 of descriptors. */
 	if (!(entry & ((TX_RING_SIZE>>1)-1)))
 		return 1;
 	return 0;
 }
 static netdev_tx_t gem_start_xmit(struct sk_buff *skb,
 				  struct net_device *dev)
 {
 	struct gem *gp = netdev_priv(dev);
 	int entry;
 	u64 ctrl;
 	ctrl = 0;
 	if (skb->ip_summed == CHECKSUM_PARTIAL) {
 		const u64 csum_start_off = skb_checksum_start_offset(skb);
 		const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
 		ctrl = (TXDCTRL_CENAB |
 			(csum_start_off << 15) |
 			(csum_stuff_off << 21));
 	}
 	if (unlikely(TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1))) {
 		/* This is a hard error, log it. */
 		if (!netif_queue_stopped(dev)) {
 			netif_stop_queue(dev);
 			netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
 		}
 		return NETDEV_TX_BUSY;
 	}
 	entry = gp->tx_new;
 	gp->tx_skbs[entry] = skb;
 	if (skb_shinfo(skb)->nr_frags == 0) {
 		struct gem_txd *txd = &gp->init_block->txd[entry];
 		dma_addr_t mapping;
 		u32 len;
 		len = skb->len;
 		mapping = pci_map_page(gp->pdev,
 				       virt_to_page(skb->data),
 				       offset_in_page(skb->data),
 				       len, PCI_DMA_TODEVICE);
 		ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;
 		if (gem_intme(entry))
 			ctrl |= TXDCTRL_INTME;
 		txd->buffer = cpu_to_le64(mapping);
 		wmb();
 		txd->control_word = cpu_to_le64(ctrl);
 		entry = NEXT_TX(entry);
 	} else {
 		struct gem_txd *txd;
 		u32 first_len;
 		u64 intme;
 		dma_addr_t first_mapping;
 		int frag, first_entry = entry;
 		intme = 0;
 		if (gem_intme(entry))
 			intme |= TXDCTRL_INTME;
 		/* We must give this initial chunk to the device last.
 		 * Otherwise we could race with the device.
 		 */
 		first_len = skb_headlen(skb);
 		first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data),
 					     offset_in_page(skb->data),
 					     first_len, PCI_DMA_TODEVICE);
 		entry = NEXT_TX(entry);
 		for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
 			skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
 			u32 len;
 			dma_addr_t mapping;
 			u64 this_ctrl;
 			len = this_frag->size;
 			mapping = pci_map_page(gp->pdev,
 					       this_frag->page,
 					       this_frag->page_offset,
 					       len, PCI_DMA_TODEVICE);
 			this_ctrl = ctrl;
 			if (frag == skb_shinfo(skb)->nr_frags - 1)
 				this_ctrl |= TXDCTRL_EOF;
 			txd = &gp->init_block->txd[entry];
 			txd->buffer = cpu_to_le64(mapping);
 			wmb();
 			txd->control_word = cpu_to_le64(this_ctrl | len);
 			if (gem_intme(entry))
 				intme |= TXDCTRL_INTME;
 			entry = NEXT_TX(entry);
 		}
 		txd = &gp->init_block->txd[first_entry];
 		txd->buffer = cpu_to_le64(first_mapping);
 		wmb();
 		txd->control_word =
 			cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len);
 	}
 	gp->tx_new = entry;
 	if (unlikely(TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))) {
 		netif_stop_queue(dev);
 		/* netif_stop_queue() must be done before checking
 		 * checking tx index in TX_BUFFS_AVAIL() below, because
 		 * in gem_tx(), we update tx_old before checking for
 		 * netif_queue_stopped().
 		 */
 		smp_mb();
 		if (TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
 			netif_wake_queue(dev);
 	}
 	if (netif_msg_tx_queued(gp))
 		printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
 		       dev->name, entry, skb->len);
 	mb();
 	writel(gp->tx_new, gp->regs + TXDMA_KICK);
 	return NETDEV_TX_OK;
 }
 static void gem_pcs_reset(struct gem *gp)
 {
 	int limit;
 	u32 val;
 	/* Reset PCS unit. */
 	val = readl(gp->regs + PCS_MIICTRL);
 	val |= PCS_MIICTRL_RST;
 	writel(val, gp->regs + PCS_MIICTRL);
 	limit = 32;
 	while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
 		udelay(100);
 		if (limit-- <= 0)
 			break;
 	}
 	if (limit < 0)
 		netdev_warn(gp->dev, "PCS reset bit would not clear\n");
 }
 static void gem_pcs_reinit_adv(struct gem *gp)
 {
 	u32 val;
 	/* Make sure PCS is disabled while changing advertisement
 	 * configuration.
 	 */
 	val = readl(gp->regs + PCS_CFG);
 	val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
 	writel(val, gp->regs + PCS_CFG);
 	/* Advertise all capabilities except asymmetric
 	 * pause.
 	 */
 	val = readl(gp->regs + PCS_MIIADV);
 	val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
 		PCS_MIIADV_SP | PCS_MIIADV_AP);
 	writel(val, gp->regs + PCS_MIIADV);
 	/* Enable and restart auto-negotiation, disable wrapback/loopback,
 	 * and re-enable PCS.
 	 */
 	val = readl(gp->regs + PCS_MIICTRL);
 	val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
 	val &= ~PCS_MIICTRL_WB;
 	writel(val, gp->regs + PCS_MIICTRL);
 	val = readl(gp->regs + PCS_CFG);
 	val |= PCS_CFG_ENABLE;
 	writel(val, gp->regs + PCS_CFG);
 	/* Make sure serialink loopback is off.  The meaning
 	 * of this bit is logically inverted based upon whether
 	 * you are in Serialink or SERDES mode.
 	 */
 	val = readl(gp->regs + PCS_SCTRL);
 	if (gp->phy_type == phy_serialink)
 		val &= ~PCS_SCTRL_LOOP;
 	else
 		val |= PCS_SCTRL_LOOP;
 	writel(val, gp->regs + PCS_SCTRL);
 }
 #define STOP_TRIES 32
 static void gem_reset(struct gem *gp)
 {
 	int limit;
 	u32 val;
 	/* Make sure we won't get any more interrupts */
 	writel(0xffffffff, gp->regs + GREG_IMASK);
 	/* Reset the chip */
 	writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,
 	       gp->regs + GREG_SWRST);
 	limit = STOP_TRIES;
 	do {
 		udelay(20);
 		val = readl(gp->regs + GREG_SWRST);
 		if (limit-- <= 0)
 			break;
 	} while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));
 	if (limit < 0)
 		netdev_err(gp->dev, "SW reset is ghetto\n");
 	if (gp->phy_type == phy_serialink || gp->phy_type == phy_serdes)
 		gem_pcs_reinit_adv(gp);
 }
 static void gem_start_dma(struct gem *gp)
 {
 	u32 val;
 	/* We are ready to rock, turn everything on. */
 	val = readl(gp->regs + TXDMA_CFG);
 	writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
 	val = readl(gp->regs + RXDMA_CFG);
 	writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
 	val = readl(gp->regs + MAC_TXCFG);
 	writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
 	val = readl(gp->regs + MAC_RXCFG);
 	writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
 	(void) readl(gp->regs + MAC_RXCFG);
 	udelay(100);
 	gem_enable_ints(gp);
 	writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
 }
 /* DMA won't be actually stopped before about 4ms tho ...
  */
 static void gem_stop_dma(struct gem *gp)
 {
 	u32 val;
 	/* We are done rocking, turn everything off. */
 	val = readl(gp->regs + TXDMA_CFG);
 	writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
 	val = readl(gp->regs + RXDMA_CFG);
 	writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
 	val = readl(gp->regs + MAC_TXCFG);
 	writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
 	val = readl(gp->regs + MAC_RXCFG);
 	writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
 	(void) readl(gp->regs + MAC_RXCFG);
 	/* Need to wait a bit ... done by the caller */
 }
 // XXX dbl check what that function should do when called on PCS PHY
 static void gem_begin_auto_negotiation(struct gem *gp, struct ethtool_cmd *ep)
 {
 	u32 advertise, features;
 	int autoneg;
 	int speed;
 	int duplex;
 	if (gp->phy_type != phy_mii_mdio0 &&
      	    gp->phy_type != phy_mii_mdio1)
      	    	goto non_mii;
 	/* Setup advertise */
 	if (found_mii_phy(gp))
 		features = gp->phy_mii.def->features;
 	else
 		features = 0;
 	advertise = features & ADVERTISE_MASK;
 	if (gp->phy_mii.advertising != 0)
 		advertise &= gp->phy_mii.advertising;
 	autoneg = gp->want_autoneg;
 	speed = gp->phy_mii.speed;
 	duplex = gp->phy_mii.duplex;
 	/* Setup link parameters */
 	if (!ep)
 		goto start_aneg;
 	if (ep->autoneg == AUTONEG_ENABLE) {
 		advertise = ep->advertising;
 		autoneg = 1;
 	} else {
 		autoneg = 0;
 		speed = ethtool_cmd_speed(ep);
 		duplex = ep->duplex;
 	}
 start_aneg:
 	/* Sanitize settings based on PHY capabilities */
 	if ((features & SUPPORTED_Autoneg) == 0)
 		autoneg = 0;
 	if (speed == SPEED_1000 &&
 	    !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))
 		speed = SPEED_100;
 	if (speed == SPEED_100 &&
 	    !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))
 		speed = SPEED_10;
 	if (duplex == DUPLEX_FULL &&
 	    !(features & (SUPPORTED_1000baseT_Full |
 	    		  SUPPORTED_100baseT_Full |
 	    		  SUPPORTED_10baseT_Full)))
 	    	duplex = DUPLEX_HALF;
 	if (speed == 0)
 		speed = SPEED_10;
 	/* If we are asleep, we don't try to actually setup the PHY, we
 	 * just store the settings
 	 */
 	if (!netif_device_present(gp->dev)) {
 		gp->phy_mii.autoneg = gp->want_autoneg = autoneg;
 		gp->phy_mii.speed = speed;
 		gp->phy_mii.duplex = duplex;
 		return;
 	}
 	/* Configure PHY & start aneg */
 	gp->want_autoneg = autoneg;
 	if (autoneg) {
 		if (found_mii_phy(gp))
 			gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);
 		gp->lstate = link_aneg;
 	} else {
 		if (found_mii_phy(gp))
 			gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);
 		gp->lstate = link_force_ok;
 	}
 non_mii:
 	gp->timer_ticks = 0;
 	mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
 }
 /* A link-up condition has occurred, initialize and enable the
  * rest of the chip.
  */
 static int gem_set_link_modes(struct gem *gp)
 {
 	struct netdev_queue *txq = netdev_get_tx_queue(gp->dev, 0);
 	int full_duplex, speed, pause;
 	u32 val;
 	full_duplex = 0;
 	speed = SPEED_10;
 	pause = 0;
 	if (found_mii_phy(gp)) {
 	    	if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))
 	    		return 1;
 		full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);
 		speed = gp->phy_mii.speed;
 		pause = gp->phy_mii.pause;
 	} else if (gp->phy_type == phy_serialink ||
 	    	   gp->phy_type == phy_serdes) {
 		u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
 		if ((pcs_lpa & PCS_MIIADV_FD) || gp->phy_type == phy_serdes)
 			full_duplex = 1;
 		speed = SPEED_1000;
 	}
 	netif_info(gp, link, gp->dev, "Link is up at %d Mbps, %s-duplex\n",
 		   speed, (full_duplex ? "full" : "half"));
 	/* We take the tx queue lock to avoid collisions between
 	 * this code, the tx path and the NAPI-driven error path
 	 */
 	__netif_tx_lock(txq, smp_processor_id());
 	val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);
 	if (full_duplex) {
 		val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);
 	} else {
 		/* MAC_TXCFG_NBO must be zero. */
 	}
 	writel(val, gp->regs + MAC_TXCFG);
 	val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);
 	if (!full_duplex &&
 	    (gp->phy_type == phy_mii_mdio0 ||
 	     gp->phy_type == phy_mii_mdio1)) {
 		val |= MAC_XIFCFG_DISE;
 	} else if (full_duplex) {
 		val |= MAC_XIFCFG_FLED;
 	}
 	if (speed == SPEED_1000)
 		val |= (MAC_XIFCFG_GMII);
 	writel(val, gp->regs + MAC_XIFCFG);
 	/* If gigabit and half-duplex, enable carrier extension
 	 * mode.  Else, disable it.
 	 */
 	if (speed == SPEED_1000 && !full_duplex) {
 		val = readl(gp->regs + MAC_TXCFG);
 		writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
 		val = readl(gp->regs + MAC_RXCFG);
 		writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
 	} else {
 		val = readl(gp->regs + MAC_TXCFG);
 		writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
 		val = readl(gp->regs + MAC_RXCFG);
 		writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
 	}
 	if (gp->phy_type == phy_serialink ||
 	    gp->phy_type == phy_serdes) {
  		u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
 		if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))
 			pause = 1;
 	}
 	if (!full_duplex)
 		writel(512, gp->regs + MAC_STIME);
 	else
 		writel(64, gp->regs + MAC_STIME);
 	val = readl(gp->regs + MAC_MCCFG);
 	if (pause)
 		val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);
 	else
 		val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);
 	writel(val, gp->regs + MAC_MCCFG);
 	gem_start_dma(gp);
 	__netif_tx_unlock(txq);
 	if (netif_msg_link(gp)) {
 		if (pause) {
 			netdev_info(gp->dev,
 				    "Pause is enabled (rxfifo: %d off: %d on: %d)\n",
 				    gp->rx_fifo_sz,
 				    gp->rx_pause_off,
 				    gp->rx_pause_on);
 		} else {
 			netdev_info(gp->dev, "Pause is disabled\n");
 		}
 	}
 	return 0;
 }
 static int gem_mdio_link_not_up(struct gem *gp)
 {
 	switch (gp->lstate) {
 	case link_force_ret:
 		netif_info(gp, link, gp->dev,
 			   "Autoneg failed again, keeping forced mode\n");
 		gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,
 			gp->last_forced_speed, DUPLEX_HALF);
 		gp->timer_ticks = 5;
 		gp->lstate = link_force_ok;
 		return 0;
 	case link_aneg:
 		/* We try forced modes after a failed aneg only on PHYs that don't
 		 * have "magic_aneg" bit set, which means they internally do the
 		 * while forced-mode thingy. On these, we just restart aneg
 		 */
 		if (gp->phy_mii.def->magic_aneg)
 			return 1;
 		netif_info(gp, link, gp->dev, "switching to forced 100bt\n");
 		/* Try forced modes. */
 		gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,
 			DUPLEX_HALF);
 		gp->timer_ticks = 5;
 		gp->lstate = link_force_try;
 		return 0;
 	case link_force_try:
 		/* Downgrade from 100 to 10 Mbps if necessary.
 		 * If already at 10Mbps, warn user about the
 		 * situation every 10 ticks.
 		 */
 		if (gp->phy_mii.speed == SPEED_100) {
 			gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,
 				DUPLEX_HALF);
 			gp->timer_ticks = 5;
 			netif_info(gp, link, gp->dev,
 				   "switching to forced 10bt\n");
 			return 0;
 		} else
 			return 1;
 	default:
 		return 0;
 	}
 }
 static void gem_link_timer(unsigned long data)
 {
 	struct gem *gp = (struct gem *) data;
 	struct net_device *dev = gp->dev;
 	int restart_aneg = 0;
 	/* There's no point doing anything if we're going to be reset */
 	if (gp->reset_task_pending)
 		return;
 	if (gp->phy_type == phy_serialink ||
 	    gp->phy_type == phy_serdes) {
 		u32 val = readl(gp->regs + PCS_MIISTAT);
 		if (!(val & PCS_MIISTAT_LS))
 			val = readl(gp->regs + PCS_MIISTAT);
 		if ((val & PCS_MIISTAT_LS) != 0) {
 			if (gp->lstate == link_up)
 				goto restart;
 			gp->lstate = link_up;
 			netif_carrier_on(dev);
 			(void)gem_set_link_modes(gp);
 		}
 		goto restart;
 	}
 	if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {
 		/* Ok, here we got a link. If we had it due to a forced
 		 * fallback, and we were configured for autoneg, we do
 		 * retry a short autoneg pass. If you know your hub is
 		 * broken, use ethtool ;)
 		 */
 		if (gp->lstate == link_force_try && gp->want_autoneg) {
 			gp->lstate = link_force_ret;
 			gp->last_forced_speed = gp->phy_mii.speed;
 			gp->timer_ticks = 5;
 			if (netif_msg_link(gp))
 				netdev_info(dev,
 					    "Got link after fallback, retrying autoneg once...\n");
 			gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);
 		} else if (gp->lstate != link_up) {
 			gp->lstate = link_up;
 			netif_carrier_on(dev);
 			if (gem_set_link_modes(gp))
 				restart_aneg = 1;
 		}
 	} else {
 		/* If the link was previously up, we restart the
 		 * whole process
 		 */
 		if (gp->lstate == link_up) {
 			gp->lstate = link_down;
 			netif_info(gp, link, dev, "Link down\n");
 			netif_carrier_off(dev);
 			gem_schedule_reset(gp);
 			/* The reset task will restart the timer */
 			return;
 		} else if (++gp->timer_ticks > 10) {
 			if (found_mii_phy(gp))
 				restart_aneg = gem_mdio_link_not_up(gp);
 			else
 				restart_aneg = 1;
 		}
 	}
 	if (restart_aneg) {
 		gem_begin_auto_negotiation(gp, NULL);
 		return;
 	}
 restart:
 	mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
 }
 static void gem_clean_rings(struct gem *gp)
 {
 	struct gem_init_block *gb = gp->init_block;
 	struct sk_buff *skb;
 	int i;
 	dma_addr_t dma_addr;
 	for (i = 0; i < RX_RING_SIZE; i++) {
 		struct gem_rxd *rxd;
 		rxd = &gb->rxd[i];
 		if (gp->rx_skbs[i] != NULL) {
 			skb = gp->rx_skbs[i];
 			dma_addr = le64_to_cpu(rxd->buffer);
 			pci_unmap_page(gp->pdev, dma_addr,
 				       RX_BUF_ALLOC_SIZE(gp),
 				       PCI_DMA_FROMDEVICE);
 			dev_kfree_skb_any(skb);
 			gp->rx_skbs[i] = NULL;
 		}
 		rxd->status_word = 0;
 		wmb();
 		rxd->buffer = 0;
 	}
 	for (i = 0; i < TX_RING_SIZE; i++) {
 		if (gp->tx_skbs[i] != NULL) {
 			struct gem_txd *txd;
 			int frag;
 			skb = gp->tx_skbs[i];
 			gp->tx_skbs[i] = NULL;
 			for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
 				int ent = i & (TX_RING_SIZE - 1);
 				txd = &gb->txd[ent];
 				dma_addr = le64_to_cpu(txd->buffer);
 				pci_unmap_page(gp->pdev, dma_addr,
 					       le64_to_cpu(txd->control_word) &
 					       TXDCTRL_BUFSZ, PCI_DMA_TODEVICE);
 				if (frag != skb_shinfo(skb)->nr_frags)
 					i++;
 			}
 			dev_kfree_skb_any(skb);
 		}
 	}
 }
 static void gem_init_rings(struct gem *gp)
 {
 	struct gem_init_block *gb = gp->init_block;
 	struct net_device *dev = gp->dev;
 	int i;
 	dma_addr_t dma_addr;
 	gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;
 	gem_clean_rings(gp);
 	gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN,
 			    (unsigned)VLAN_ETH_FRAME_LEN);
 	for (i = 0; i < RX_RING_SIZE; i++) {
 		struct sk_buff *skb;
 		struct gem_rxd *rxd = &gb->rxd[i];
 		skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_KERNEL);
 		if (!skb) {
 			rxd->buffer = 0;
 			rxd->status_word = 0;
 			continue;
 		}
 		gp->rx_skbs[i] = skb;
 		skb_put(skb, (gp->rx_buf_sz + RX_OFFSET));
 		dma_addr = pci_map_page(gp->pdev,
 					virt_to_page(skb->data),
 					offset_in_page(skb->data),
 					RX_BUF_ALLOC_SIZE(gp),
 					PCI_DMA_FROMDEVICE);
 		rxd->buffer = cpu_to_le64(dma_addr);
 		wmb();
 		rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
 		skb_reserve(skb, RX_OFFSET);
 	}
 	for (i = 0; i < TX_RING_SIZE; i++) {
 		struct gem_txd *txd = &gb->txd[i];
 		txd->control_word = 0;
 		wmb();
 		txd->buffer = 0;
 	}
 	wmb();
 }
 /* Init PHY interface and start link poll state machine */
 static void gem_init_phy(struct gem *gp)
 {
 	u32 mifcfg;
 	/* Revert MIF CFG setting done on stop_phy */
 	mifcfg = readl(gp->regs + MIF_CFG);
 	mifcfg &= ~MIF_CFG_BBMODE;
 	writel(mifcfg, gp->regs + MIF_CFG);
 	if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
 		int i;
 		/* Those delay sucks, the HW seem to love them though, I'll
 		 * serisouly consider breaking some locks here to be able
 		 * to schedule instead
 		 */
 		for (i = 0; i < 3; i++) {
 #ifdef CONFIG_PPC_PMAC
 			pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
 			msleep(20);
 #endif
 			/* Some PHYs used by apple have problem getting back to us,
 			 * we do an additional reset here
 			 */
 			phy_write(gp, MII_BMCR, BMCR_RESET);
 			msleep(20);
 			if (phy_read(gp, MII_BMCR) != 0xffff)
 				break;
 			if (i == 2)
 				netdev_warn(gp->dev, "GMAC PHY not responding !\n");
 		}
 	}
 	if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
 	    gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
 		u32 val;
 		/* Init datapath mode register. */
 		if (gp->phy_type == phy_mii_mdio0 ||
 		    gp->phy_type == phy_mii_mdio1) {
 			val = PCS_DMODE_MGM;
 		} else if (gp->phy_type == phy_serialink) {
 			val = PCS_DMODE_SM | PCS_DMODE_GMOE;
 		} else {
 			val = PCS_DMODE_ESM;
 		}
 		writel(val, gp->regs + PCS_DMODE);
 	}
 	if (gp->phy_type == phy_mii_mdio0 ||
 	    gp->phy_type == phy_mii_mdio1) {
 		/* Reset and detect MII PHY */
 		mii_phy_probe(&gp->phy_mii, gp->mii_phy_addr);
 		/* Init PHY */
 		if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
 			gp->phy_mii.def->ops->init(&gp->phy_mii);
 	} else {
 		gem_pcs_reset(gp);
 		gem_pcs_reinit_adv(gp);
 	}
 	/* Default aneg parameters */
 	gp->timer_ticks = 0;
 	gp->lstate = link_down;
 	netif_carrier_off(gp->dev);
 	/* Print things out */
 	if (gp->phy_type == phy_mii_mdio0 ||
 	    gp->phy_type == phy_mii_mdio1)
 		netdev_info(gp->dev, "Found %s PHY\n",
 			    gp->phy_mii.def ? gp->phy_mii.def->name : "no");
 	gem_begin_auto_negotiation(gp, NULL);
 }
 static void gem_init_dma(struct gem *gp)
 {
 	u64 desc_dma = (u64) gp->gblock_dvma;
 	u32 val;
 	val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);
 	writel(val, gp->regs + TXDMA_CFG);
 	writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
 	writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
 	desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
 	writel(0, gp->regs + TXDMA_KICK);
 	val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
 	       ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
 	writel(val, gp->regs + RXDMA_CFG);
 	writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
 	writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
 	writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
 	val  = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
 	val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
 	writel(val, gp->regs + RXDMA_PTHRESH);
 	if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
 		writel(((5 & RXDMA_BLANK_IPKTS) |
 			((8 << 12) & RXDMA_BLANK_ITIME)),
 		       gp->regs + RXDMA_BLANK);
 	else
 		writel(((5 & RXDMA_BLANK_IPKTS) |
 			((4 << 12) & RXDMA_BLANK_ITIME)),
 		       gp->regs + RXDMA_BLANK);
 }
 static u32 gem_setup_multicast(struct gem *gp)
 {
 	u32 rxcfg = 0;
 	int i;
 	if ((gp->dev->flags & IFF_ALLMULTI) ||
 	    (netdev_mc_count(gp->dev) > 256)) {
 	    	for (i=0; i<16; i++)
 			writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
 		rxcfg |= MAC_RXCFG_HFE;
 	} else if (gp->dev->flags & IFF_PROMISC) {
 		rxcfg |= MAC_RXCFG_PROM;
 	} else {
 		u16 hash_table[16];
 		u32 crc;
 		struct netdev_hw_addr *ha;
 		int i;
 		memset(hash_table, 0, sizeof(hash_table));
 		netdev_for_each_mc_addr(ha, gp->dev) {
 			crc = ether_crc_le(6, ha->addr);
 			crc >>= 24;
 			hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
 		}
 	    	for (i=0; i<16; i++)
 			writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
 		rxcfg |= MAC_RXCFG_HFE;
 	}
 	return rxcfg;
 }
 static void gem_init_mac(struct gem *gp)
 {
 	unsigned char *e = &gp->dev->dev_addr[0];
 	writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
 	writel(0x00, gp->regs + MAC_IPG0);
 	writel(0x08, gp->regs + MAC_IPG1);
 	writel(0x04, gp->regs + MAC_IPG2);
 	writel(0x40, gp->regs + MAC_STIME);
 	writel(0x40, gp->regs + MAC_MINFSZ);
 	/* Ethernet payload + header + FCS + optional VLAN tag. */
 	writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);
 	writel(0x07, gp->regs + MAC_PASIZE);
 	writel(0x04, gp->regs + MAC_JAMSIZE);
 	writel(0x10, gp->regs + MAC_ATTLIM);
 	writel(0x8808, gp->regs + MAC_MCTYPE);
 	writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
 	writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
 	writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
 	writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
 	writel(0, gp->regs + MAC_ADDR3);
 	writel(0, gp->regs + MAC_ADDR4);
 	writel(0, gp->regs + MAC_ADDR5);
 	writel(0x0001, gp->regs + MAC_ADDR6);
 	writel(0xc200, gp->regs + MAC_ADDR7);
 	writel(0x0180, gp->regs + MAC_ADDR8);
 	writel(0, gp->regs + MAC_AFILT0);
 	writel(0, gp->regs + MAC_AFILT1);
 	writel(0, gp->regs + MAC_AFILT2);
 	writel(0, gp->regs + MAC_AF21MSK);
 	writel(0, gp->regs + MAC_AF0MSK);
 	gp->mac_rx_cfg = gem_setup_multicast(gp);
 #ifdef STRIP_FCS
 	gp->mac_rx_cfg |= MAC_RXCFG_SFCS;
 #endif
 	writel(0, gp->regs + MAC_NCOLL);
 	writel(0, gp->regs + MAC_FASUCC);
 	writel(0, gp->regs + MAC_ECOLL);
 	writel(0, gp->regs + MAC_LCOLL);
 	writel(0, gp->regs + MAC_DTIMER);
 	writel(0, gp->regs + MAC_PATMPS);
 	writel(0, gp->regs + MAC_RFCTR);
 	writel(0, gp->regs + MAC_LERR);
 	writel(0, gp->regs + MAC_AERR);
 	writel(0, gp->regs + MAC_FCSERR);
 	writel(0, gp->regs + MAC_RXCVERR);
 	/* Clear RX/TX/MAC/XIF config, we will set these up and enable
 	 * them once a link is established.
 	 */
 	writel(0, gp->regs + MAC_TXCFG);
 	writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
 	writel(0, gp->regs + MAC_MCCFG);
 	writel(0, gp->regs + MAC_XIFCFG);
 	/* Setup MAC interrupts.  We want to get all of the interesting
 	 * counter expiration events, but we do not want to hear about
 	 * normal rx/tx as the DMA engine tells us that.
 	 */
 	writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
 	writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
 	/* Don't enable even the PAUSE interrupts for now, we
 	 * make no use of those events other than to record them.
 	 */
 	writel(0xffffffff, gp->regs + MAC_MCMASK);
 	/* Don't enable GEM's WOL in normal operations
 	 */
 	if (gp->has_wol)
 		writel(0, gp->regs + WOL_WAKECSR);
 }
 static void gem_init_pause_thresholds(struct gem *gp)
 {
        	u32 cfg;
 	/* Calculate pause thresholds.  Setting the OFF threshold to the
 	 * full RX fifo size effectively disables PAUSE generation which
 	 * is what we do for 10/100 only GEMs which have FIFOs too small
 	 * to make real gains from PAUSE.
 	 */
 	if (gp->rx_fifo_sz <= (2 * 1024)) {
 		gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;
 	} else {
 		int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63;
 		int off = (gp->rx_fifo_sz - (max_frame * 2));
 		int on = off - max_frame;
 		gp->rx_pause_off = off;
 		gp->rx_pause_on = on;
 	}
 	/* Configure the chip "burst" DMA mode & enable some
 	 * HW bug fixes on Apple version
 	 */
        	cfg  = 0;
        	if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
 		cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX;
 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
        	cfg |= GREG_CFG_IBURST;
 #endif
        	cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);
        	cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);
        	writel(cfg, gp->regs + GREG_CFG);
 	/* If Infinite Burst didn't stick, then use different
 	 * thresholds (and Apple bug fixes don't exist)
 	 */
 	if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {
 		cfg = ((2 << 1) & GREG_CFG_TXDMALIM);
 		cfg |= ((8 << 6) & GREG_CFG_RXDMALIM);
 		writel(cfg, gp->regs + GREG_CFG);
 	}
 }
 static int gem_check_invariants(struct gem *gp)
 {
 	struct pci_dev *pdev = gp->pdev;
 	u32 mif_cfg;
 	/* On Apple's sungem, we can't rely on registers as the chip
 	 * was been powered down by the firmware. The PHY is looked
 	 * up later on.
 	 */
 	if (pdev->vendor == PCI_VENDOR_ID_APPLE) {
 		gp->phy_type = phy_mii_mdio0;
 		gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
 		gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
 		gp->swrst_base = 0;
 		mif_cfg = readl(gp->regs + MIF_CFG);
 		mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
 		mif_cfg |= MIF_CFG_MDI0;
 		writel(mif_cfg, gp->regs + MIF_CFG);
 		writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
 		writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
 		/* We hard-code the PHY address so we can properly bring it out of
 		 * reset later on, we can't really probe it at this point, though
 		 * that isn't an issue.
 		 */
 		if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC)
 			gp->mii_phy_addr = 1;
 		else
 			gp->mii_phy_addr = 0;
 		return 0;
 	}
 	mif_cfg = readl(gp->regs + MIF_CFG);
 	if (pdev->vendor == PCI_VENDOR_ID_SUN &&
 	    pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {
 		/* One of the MII PHYs _must_ be present
 		 * as this chip has no gigabit PHY.
 		 */
 		if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {
 			pr_err("RIO GEM lacks MII phy, mif_cfg[%08x]\n",
 			       mif_cfg);
 			return -1;
 		}
 	}
 	/* Determine initial PHY interface type guess.  MDIO1 is the
 	 * external PHY and thus takes precedence over MDIO0.
 	 */
 	if (mif_cfg & MIF_CFG_MDI1) {
 		gp->phy_type = phy_mii_mdio1;
 		mif_cfg |= MIF_CFG_PSELECT;
 		writel(mif_cfg, gp->regs + MIF_CFG);
 	} else if (mif_cfg & MIF_CFG_MDI0) {
 		gp->phy_type = phy_mii_mdio0;
 		mif_cfg &= ~MIF_CFG_PSELECT;
 		writel(mif_cfg, gp->regs + MIF_CFG);
 	} else {
 #ifdef CONFIG_SPARC
 		const char *p;
 		p = of_get_property(gp->of_node, "shared-pins", NULL);
 		if (p && !strcmp(p, "serdes"))
 			gp->phy_type = phy_serdes;
 		else
 #endif
 			gp->phy_type = phy_serialink;
 	}
 	if (gp->phy_type == phy_mii_mdio1 ||
 	    gp->phy_type == phy_mii_mdio0) {
 		int i;
 		for (i = 0; i < 32; i++) {
 			gp->mii_phy_addr = i;
 			if (phy_read(gp, MII_BMCR) != 0xffff)
 				break;
 		}
 		if (i == 32) {
 			if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {
 				pr_err("RIO MII phy will not respond\n");
 				return -1;
 			}
 			gp->phy_type = phy_serdes;
 		}
 	}
 	/* Fetch the FIFO configurations now too. */
 	gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
 	gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
 	if (pdev->vendor == PCI_VENDOR_ID_SUN) {
 		if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {
 			if (gp->tx_fifo_sz != (9 * 1024) ||
 			    gp->rx_fifo_sz != (20 * 1024)) {
 				pr_err("GEM has bogus fifo sizes tx(%d) rx(%d)\n",
 				       gp->tx_fifo_sz, gp->rx_fifo_sz);
 				return -1;
 			}
 			gp->swrst_base = 0;
 		} else {
 			if (gp->tx_fifo_sz != (2 * 1024) ||
 			    gp->rx_fifo_sz != (2 * 1024)) {
 				pr_err("RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
 				       gp->tx_fifo_sz, gp->rx_fifo_sz);
 				return -1;
 			}
 			gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;
 		}
 	}
 	return 0;
 }
 static void gem_reinit_chip(struct gem *gp)
 {
 	/* Reset the chip */
 	gem_reset(gp);
 	/* Make sure ints are disabled */
 	gem_disable_ints(gp);
 	/* Allocate & setup ring buffers */
 	gem_init_rings(gp);
 	/* Configure pause thresholds */
 	gem_init_pause_thresholds(gp);
 	/* Init DMA & MAC engines */
 	gem_init_dma(gp);
 	gem_init_mac(gp);
 }
 static void gem_stop_phy(struct gem *gp, int wol)
 {
 	u32 mifcfg;
 	/* Let the chip settle down a bit, it seems that helps
 	 * for sleep mode on some models
 	 */
 	msleep(10);
 	/* Make sure we aren't polling PHY status change. We
 	 * don't currently use that feature though
 	 */
 	mifcfg = readl(gp->regs + MIF_CFG);
 	mifcfg &= ~MIF_CFG_POLL;
 	writel(mifcfg, gp->regs + MIF_CFG);
 	if (wol && gp->has_wol) {
 		unsigned char *e = &gp->dev->dev_addr[0];
 		u32 csr;
 		/* Setup wake-on-lan for MAGIC packet */
 		writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB,
 		       gp->regs + MAC_RXCFG);
 		writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0);
 		writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1);
 		writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2);
 		writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT);
 		csr = WOL_WAKECSR_ENABLE;
 		if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0)
 			csr |= WOL_WAKECSR_MII;
 		writel(csr, gp->regs + WOL_WAKECSR);
 	} else {
 		writel(0, gp->regs + MAC_RXCFG);
 		(void)readl(gp->regs + MAC_RXCFG);
 		/* Machine sleep will die in strange ways if we
 		 * dont wait a bit here, looks like the chip takes
 		 * some time to really shut down
 		 */
 		msleep(10);
 	}
 	writel(0, gp->regs + MAC_TXCFG);
 	writel(0, gp->regs + MAC_XIFCFG);
 	writel(0, gp->regs + TXDMA_CFG);
 	writel(0, gp->regs + RXDMA_CFG);
 	if (!wol) {
 		gem_reset(gp);
 		writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
 		writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
 		if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)
 			gp->phy_mii.def->ops->suspend(&gp->phy_mii);
 		/* According to Apple, we must set the MDIO pins to this begnign
 		 * state or we may 1) eat more current, 2) damage some PHYs
 		 */
 		writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
 		writel(0, gp->regs + MIF_BBCLK);
 		writel(0, gp->regs + MIF_BBDATA);
 		writel(0, gp->regs + MIF_BBOENAB);
 		writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
 		(void) readl(gp->regs + MAC_XIFCFG);
 	}
 }
 static int gem_do_start(struct net_device *dev)
 {
 	struct gem *gp = netdev_priv(dev);
 	int rc;
 	/* Enable the cell */
 	gem_get_cell(gp);
 	/* Make sure PCI access and bus master are enabled */
 	rc = pci_enable_device(gp->pdev);
 	if (rc) {
 		netdev_err(dev, "Failed to enable chip on PCI bus !\n");
 		/* Put cell and forget it for now, it will be considered as
 		 * still asleep, a new sleep cycle may bring it back
 		 */
 		gem_put_cell(gp);
 		return -ENXIO;
 	}
 	pci_set_master(gp->pdev);
 	/* Init & setup chip hardware */
 	gem_reinit_chip(gp);
 	/* An interrupt might come in handy */
 	rc = request_irq(gp->pdev->irq, gem_interrupt,
 			 IRQF_SHARED, dev->name, (void *)dev);
 	if (rc) {
 		netdev_err(dev, "failed to request irq !\n");
 		gem_reset(gp);
 		gem_clean_rings(gp);
 		gem_put_cell(gp);
 		return rc;
 	}
 	/* Mark us as attached again if we come from resume(), this has
 	 * no effect if we weren't detatched and needs to be done now.
 	 */
 	netif_device_attach(dev);
 	/* Restart NAPI & queues */
 	gem_netif_start(gp);
 	/* Detect & init PHY, start autoneg etc... this will
 	 * eventually result in starting DMA operations when
 	 * the link is up
 	 */
 	gem_init_phy(gp);
 	return 0;
 }
 static void gem_do_stop(struct net_device *dev, int wol)
 {
 	struct gem *gp = netdev_priv(dev);
 	/* Stop NAPI and stop tx queue */
 	gem_netif_stop(gp);
 	/* Make sure ints are disabled. We don't care about
 	 * synchronizing as NAPI is disabled, thus a stray
 	 * interrupt will do nothing bad (our irq handler
 	 * just schedules NAPI)
 	 */
 	gem_disable_ints(gp);
 	/* Stop the link timer */
 	del_timer_sync(&gp->link_timer);
 	/* We cannot cancel the reset task while holding the
 	 * rtnl lock, we'd get an A->B / B->A deadlock stituation
 	 * if we did. This is not an issue however as the reset
 	 * task is synchronized vs. us (rtnl_lock) and will do
 	 * nothing if the device is down or suspended. We do
 	 * still clear reset_task_pending to avoid a spurrious
 	 * reset later on in case we do resume before it gets
 	 * scheduled.
 	 */
 	gp->reset_task_pending = 0;
 	/* If we are going to sleep with WOL */
 	gem_stop_dma(gp);
 	msleep(10);
 	if (!wol)
 		gem_reset(gp);
 	msleep(10);
 	/* Get rid of rings */
 	gem_clean_rings(gp);
 	/* No irq needed anymore */
 	free_irq(gp->pdev->irq, (void *) dev);
 	/* Shut the PHY down eventually and setup WOL */
 	gem_stop_phy(gp, wol);
 	/* Make sure bus master is disabled */
 	pci_disable_device(gp->pdev);
 	/* Cell not needed neither if no WOL */
 	if (!wol)
 		gem_put_cell(gp);
 }
 static void gem_reset_task(struct work_struct *work)
 {
 	struct gem *gp = container_of(work, struct gem, reset_task);
 	/* Lock out the network stack (essentially shield ourselves
 	 * against a racing open, close, control call, or suspend
 	 */
 	rtnl_lock();
 	/* Skip the reset task if suspended or closed, or if it's
 	 * been cancelled by gem_do_stop (see comment there)
 	 */
 	if (!netif_device_present(gp->dev) ||
 	    !netif_running(gp->dev) ||
 	    !gp->reset_task_pending) {
 		rtnl_unlock();
 		return;
 	}
 	/* Stop the link timer */
 	del_timer_sync(&gp->link_timer);
 	/* Stop NAPI and tx */
 	gem_netif_stop(gp);
 	/* Reset the chip & rings */
 	gem_reinit_chip(gp);
 	if (gp->lstate == link_up)
 		gem_set_link_modes(gp);
 	/* Restart NAPI and Tx */
 	gem_netif_start(gp);
 	/* We are back ! */
 	gp->reset_task_pending = 0;
 	/* If the link is not up, restart autoneg, else restart the
 	 * polling timer
 	 */
 	if (gp->lstate != link_up)
 		gem_begin_auto_negotiation(gp, NULL);
 	else
 		mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
 	rtnl_unlock();
 }
 static int gem_open(struct net_device *dev)
 {
 	/* We allow open while suspended, we just do nothing,
 	 * the chip will be initialized in resume()
 	 */
 	if (netif_device_present(dev))
 		return gem_do_start(dev);
 	return 0;
 }
 static int gem_close(struct net_device *dev)
 {
 	if (netif_device_present(dev))
 		gem_do_stop(dev, 0);
 	return 0;
 }
 #ifdef CONFIG_PM
 static int gem_suspend(struct pci_dev *pdev, pm_message_t state)
 {
 	struct net_device *dev = pci_get_drvdata(pdev);
 	struct gem *gp = netdev_priv(dev);
 	/* Lock the network stack first to avoid racing with open/close,
 	 * reset task and setting calls
 	 */
 	rtnl_lock();
 	/* Not running, mark ourselves non-present, no need for
 	 * a lock here
 	 */
 	if (!netif_running(dev)) {
 		netif_device_detach(dev);
 		rtnl_unlock();
 		return 0;
 	}
 	netdev_info(dev, "suspending, WakeOnLan %s\n",
 		    (gp->wake_on_lan && netif_running(dev)) ?
 		    "enabled" : "disabled");
 	/* Tell the network stack we're gone. gem_do_stop() below will
 	 * synchronize with TX, stop NAPI etc...
 	 */
 	netif_device_detach(dev);
 	/* Switch off chip, remember WOL setting */
 	gp->asleep_wol = gp->wake_on_lan;
 	gem_do_stop(dev, gp->asleep_wol);
 	/* Unlock the network stack */
 	rtnl_unlock();
 	return 0;
 }
 static int gem_resume(struct pci_dev *pdev)
 {
 	struct net_device *dev = pci_get_drvdata(pdev);
 	struct gem *gp = netdev_priv(dev);
 	/* See locking comment in gem_suspend */
 	rtnl_lock();
 	/* Not running, mark ourselves present, no need for
 	 * a lock here
 	 */
 	if (!netif_running(dev)) {
 		netif_device_attach(dev);
 		rtnl_unlock();
 		return 0;
 	}
 	/* Restart chip. If that fails there isn't much we can do, we
 	 * leave things stopped.
 	 */
 	gem_do_start(dev);
 	/* If we had WOL enabled, the cell clock was never turned off during
 	 * sleep, so we end up beeing unbalanced. Fix that here
 	 */
 	if (gp->asleep_wol)
 		gem_put_cell(gp);
 	/* Unlock the network stack */
 	rtnl_unlock();
 	return 0;
 }
 #endif /* CONFIG_PM */
 static struct net_device_stats *gem_get_stats(struct net_device *dev)
 {
 	struct gem *gp = netdev_priv(dev);
 	/* I have seen this being called while the PM was in progress,
 	 * so we shield against this. Let's also not poke at registers
 	 * while the reset task is going on.
 	 *
 	 * TODO: Move stats collection elsewhere (link timer ?) and
 	 * make this a nop to avoid all those synchro issues
 	 */
 	if (!netif_device_present(dev) || !netif_running(dev))
 		goto bail;
 	/* Better safe than sorry... */
 	if (WARN_ON(!gp->cell_enabled))
 		goto bail;
 	dev->stats.rx_crc_errors += readl(gp->regs + MAC_FCSERR);
 	writel(0, gp->regs + MAC_FCSERR);
 	dev->stats.rx_frame_errors += readl(gp->regs + MAC_AERR);
 	writel(0, gp->regs + MAC_AERR);
 	dev->stats.rx_length_errors += readl(gp->regs + MAC_LERR);
 	writel(0, gp->regs + MAC_LERR);
 	dev->stats.tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
 	dev->stats.collisions +=
 		(readl(gp->regs + MAC_ECOLL) + readl(gp->regs + MAC_LCOLL));
 	writel(0, gp->regs + MAC_ECOLL);
 	writel(0, gp->regs + MAC_LCOLL);
  bail:
 	return &dev->stats;
 }
 static int gem_set_mac_address(struct net_device *dev, void *addr)
 {
 	struct sockaddr *macaddr = (struct sockaddr *) addr;
 	struct gem *gp = netdev_priv(dev);
 	unsigned char *e = &dev->dev_addr[0];
 	if (!is_valid_ether_addr(macaddr->sa_data))
 		return -EADDRNOTAVAIL;
 	memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len);
 	/* We'll just catch it later when the device is up'd or resumed */
 	if (!netif_running(dev) || !netif_device_present(dev))
 		return 0;
 	/* Better safe than sorry... */
 	if (WARN_ON(!gp->cell_enabled))
 		return 0;
 	writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
 	writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
 	writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
 	return 0;
 }
 static void gem_set_multicast(struct net_device *dev)
 {
 	struct gem *gp = netdev_priv(dev);
 	u32 rxcfg, rxcfg_new;
 	int limit = 10000;
 	if (!netif_running(dev) || !netif_device_present(dev))
 		return;
 	/* Better safe than sorry... */
 	if (gp->reset_task_pending || WARN_ON(!gp->cell_enabled))
 		return;
 	rxcfg = readl(gp->regs + MAC_RXCFG);
 	rxcfg_new = gem_setup_multicast(gp);
 #ifdef STRIP_FCS
 	rxcfg_new |= MAC_RXCFG_SFCS;
 #endif
 	gp->mac_rx_cfg = rxcfg_new;
 	writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
 	while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
 		if (!limit--)
 			break;
 		udelay(10);
 	}
 	rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);
 	rxcfg |= rxcfg_new;
 	writel(rxcfg, gp->regs + MAC_RXCFG);
 }
 /* Jumbo-grams don't seem to work :-( */
 #define GEM_MIN_MTU	68
 #if 1
 #define GEM_MAX_MTU	1500
 #else
 #define GEM_MAX_MTU	9000
 #endif
 static int gem_change_mtu(struct net_device *dev, int new_mtu)
 {
 	struct gem *gp = netdev_priv(dev);
 	if (new_mtu < GEM_MIN_MTU || new_mtu > GEM_MAX_MTU)
 		return -EINVAL;
 	dev->mtu = new_mtu;
 	/* We'll just catch it later when the device is up'd or resumed */
 	if (!netif_running(dev) || !netif_device_present(dev))
 		return 0;
 	/* Better safe than sorry... */
 	if (WARN_ON(!gp->cell_enabled))
 		return 0;
 	gem_netif_stop(gp);
 	gem_reinit_chip(gp);
 	if (gp->lstate == link_up)
 		gem_set_link_modes(gp);
 	gem_netif_start(gp);
 	return 0;
 }
 static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
 {
 	struct gem *gp = netdev_priv(dev);
 	strcpy(info->driver, DRV_NAME);
 	strcpy(info->version, DRV_VERSION);
 	strcpy(info->bus_info, pci_name(gp->pdev));
 }
 static int gem_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 {
 	struct gem *gp = netdev_priv(dev);
 	if (gp->phy_type == phy_mii_mdio0 ||
 	    gp->phy_type == phy_mii_mdio1) {
 		if (gp->phy_mii.def)
 			cmd->supported = gp->phy_mii.def->features;
 		else
 			cmd->supported = (SUPPORTED_10baseT_Half |
 					  SUPPORTED_10baseT_Full);
 		/* XXX hardcoded stuff for now */
 		cmd->port = PORT_MII;
 		cmd->transceiver = XCVR_EXTERNAL;
 		cmd->phy_address = 0; /* XXX fixed PHYAD */
 		/* Return current PHY settings */
 		cmd->autoneg = gp->want_autoneg;
 		ethtool_cmd_speed_set(cmd, gp->phy_mii.speed);
 		cmd->duplex = gp->phy_mii.duplex;
 		cmd->advertising = gp->phy_mii.advertising;
 		/* If we started with a forced mode, we don't have a default
 		 * advertise set, we need to return something sensible so
 		 * userland can re-enable autoneg properly.
 		 */
 		if (cmd->advertising == 0)
 			cmd->advertising = cmd->supported;
 	} else { // XXX PCS ?
 		cmd->supported =
 			(SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
 			 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
 			 SUPPORTED_Autoneg);
 		cmd->advertising = cmd->supported;
 		ethtool_cmd_speed_set(cmd, 0);
 		cmd->duplex = cmd->port = cmd->phy_address =
 			cmd->transceiver = cmd->autoneg = 0;
 		/* serdes means usually a Fibre connector, with most fixed */
 		if (gp->phy_type == phy_serdes) {
 			cmd->port = PORT_FIBRE;
 			cmd->supported = (SUPPORTED_1000baseT_Half |
 				SUPPORTED_1000baseT_Full |
 				SUPPORTED_FIBRE | SUPPORTED_Autoneg |
 				SUPPORTED_Pause | SUPPORTED_Asym_Pause);
 			cmd->advertising = cmd->supported;
 			cmd->transceiver = XCVR_INTERNAL;
 			if (gp->lstate == link_up)
 				ethtool_cmd_speed_set(cmd, SPEED_1000);
 			cmd->duplex = DUPLEX_FULL;
 			cmd->autoneg = 1;
 		}
 	}
 	cmd->maxtxpkt = cmd->maxrxpkt = 0;
 	return 0;
 }
 static int gem_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 {
 	struct gem *gp = netdev_priv(dev);
 	u32 speed = ethtool_cmd_speed(cmd);
 	/* Verify the settings we care about. */
 	if (cmd->autoneg != AUTONEG_ENABLE &&
 	    cmd->autoneg != AUTONEG_DISABLE)
 		return -EINVAL;
 	if (cmd->autoneg == AUTONEG_ENABLE &&
 	    cmd->advertising == 0)
 		return -EINVAL;
 	if (cmd->autoneg == AUTONEG_DISABLE &&
 	    ((speed != SPEED_1000 &&
 	      speed != SPEED_100 &&
 	      speed != SPEED_10) ||
 	     (cmd->duplex != DUPLEX_HALF &&
 	      cmd->duplex != DUPLEX_FULL)))
 		return -EINVAL;
 	/* Apply settings and restart link process. */
 	if (netif_device_present(gp->dev)) {
 		del_timer_sync(&gp->link_timer);
 		gem_begin_auto_negotiation(gp, cmd);
 	}
 	return 0;
 }
 static int gem_nway_reset(struct net_device *dev)
 {
 	struct gem *gp = netdev_priv(dev);
 	if (!gp->want_autoneg)
 		return -EINVAL;
 	/* Restart link process  */
 	if (netif_device_present(gp->dev)) {
 		del_timer_sync(&gp->link_timer);
 		gem_begin_auto_negotiation(gp, NULL);
 	}
 	return 0;
 }
 static u32 gem_get_msglevel(struct net_device *dev)
 {
 	struct gem *gp = netdev_priv(dev);
 	return gp->msg_enable;
 }
 static void gem_set_msglevel(struct net_device *dev, u32 value)
 {
 	struct gem *gp = netdev_priv(dev);
 	gp->msg_enable = value;
 }
 /* Add more when I understand how to program the chip */
 /* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */
 #define WOL_SUPPORTED_MASK	(WAKE_MAGIC)
 static void gem_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 {
 	struct gem *gp = netdev_priv(dev);
 	/* Add more when I understand how to program the chip */
 	if (gp->has_wol) {
 		wol->supported = WOL_SUPPORTED_MASK;
 		wol->wolopts = gp->wake_on_lan;
 	} else {
 		wol->supported = 0;
 		wol->wolopts = 0;
 	}
 }
 static int gem_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 {
 	struct gem *gp = netdev_priv(dev);
 	if (!gp->has_wol)
 		return -EOPNOTSUPP;
 	gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK;
 	return 0;
 }
 static const struct ethtool_ops gem_ethtool_ops = {
 	.get_drvinfo		= gem_get_drvinfo,
 	.get_link		= ethtool_op_get_link,
 	.get_settings		= gem_get_settings,
 	.set_settings		= gem_set_settings,
 	.nway_reset		= gem_nway_reset,
 	.get_msglevel		= gem_get_msglevel,
 	.set_msglevel		= gem_set_msglevel,
 	.get_wol		= gem_get_wol,
 	.set_wol		= gem_set_wol,
 };
 static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 {
 	struct gem *gp = netdev_priv(dev);
 	struct mii_ioctl_data *data = if_mii(ifr);
 	int rc = -EOPNOTSUPP;
 	/* For SIOCGMIIREG and SIOCSMIIREG the core checks for us that
 	 * netif_device_present() is true and holds rtnl_lock for us
 	 * so we have nothing to worry about
 	 */
 	switch (cmd) {
 	case SIOCGMIIPHY:		/* Get address of MII PHY in use. */
 		data->phy_id = gp->mii_phy_addr;
 		/* Fallthrough... */
 	case SIOCGMIIREG:		/* Read MII PHY register. */
 		data->val_out = __phy_read(gp, data->phy_id & 0x1f,
 					   data->reg_num & 0x1f);
 		rc = 0;
 		break;
 	case SIOCSMIIREG:		/* Write MII PHY register. */
 		__phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,
 			    data->val_in);
 		rc = 0;
 		break;
 	}
 	return rc;
 }
 #if (!defined(CONFIG_SPARC) && !defined(CONFIG_PPC_PMAC))
 /* Fetch MAC address from vital product data of PCI ROM. */
 static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, unsigned char *dev_addr)
 {
 	int this_offset;
 	for (this_offset = 0x20; this_offset < len; this_offset++) {
 		void __iomem *p = rom_base + this_offset;
 		int i;
 		if (readb(p + 0) != 0x90 ||
 		    readb(p + 1) != 0x00 ||
 		    readb(p + 2) != 0x09 ||
 		    readb(p + 3) != 0x4e ||
 		    readb(p + 4) != 0x41 ||
 		    readb(p + 5) != 0x06)
 			continue;
 		this_offset += 6;
 		p += 6;
 		for (i = 0; i < 6; i++)
 			dev_addr[i] = readb(p + i);
 		return 1;
 	}
 	return 0;
 }
 static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr)
 {
 	size_t size;
 	void __iomem *p = pci_map_rom(pdev, &size);
 	if (p) {
 			int found;
 		found = readb(p) == 0x55 &&
 			readb(p + 1) == 0xaa &&
 			find_eth_addr_in_vpd(p, (64 * 1024), dev_addr);
 		pci_unmap_rom(pdev, p);
 		if (found)
 			return;
 	}
 	/* Sun MAC prefix then 3 random bytes. */
 	dev_addr[0] = 0x08;
 	dev_addr[1] = 0x00;
 	dev_addr[2] = 0x20;
 	get_random_bytes(dev_addr + 3, 3);
 }
 #endif /* not Sparc and not PPC */
 static int __devinit gem_get_device_address(struct gem *gp)
 {
 #if defined(CONFIG_SPARC) || defined(CONFIG_PPC_PMAC)
 	struct net_device *dev = gp->dev;
 	const unsigned char *addr;
 	addr = of_get_property(gp->of_node, "local-mac-address", NULL);
 	if (addr == NULL) {
 #ifdef CONFIG_SPARC
 		addr = idprom->id_ethaddr;
 #else
 		printk("\n");
 		pr_err("%s: can't get mac-address\n", dev->name);
 		return -1;
 #endif
 	}
 	memcpy(dev->dev_addr, addr, 6);
 #else
 	get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr);
 #endif
 	return 0;
 }
 static void gem_remove_one(struct pci_dev *pdev)
 {
 	struct net_device *dev = pci_get_drvdata(pdev);
 	if (dev) {
 		struct gem *gp = netdev_priv(dev);
 		unregister_netdev(dev);
 		/* Ensure reset task is truely gone */
 		cancel_work_sync(&gp->reset_task);
 		/* Free resources */
 		pci_free_consistent(pdev,
 				    sizeof(struct gem_init_block),
 				    gp->init_block,
 				    gp->gblock_dvma);
 		iounmap(gp->regs);
 		pci_release_regions(pdev);
 		free_netdev(dev);
 		pci_set_drvdata(pdev, NULL);
 	}
 }
 static const struct net_device_ops gem_netdev_ops = {
 	.ndo_open		= gem_open,
 	.ndo_stop		= gem_close,
 	.ndo_start_xmit		= gem_start_xmit,
 	.ndo_get_stats		= gem_get_stats,
 	.ndo_set_multicast_list = gem_set_multicast,
 	.ndo_do_ioctl		= gem_ioctl,
 	.ndo_tx_timeout		= gem_tx_timeout,
 	.ndo_change_mtu		= gem_change_mtu,
 	.ndo_validate_addr	= eth_validate_addr,
 	.ndo_set_mac_address    = gem_set_mac_address,
 #ifdef CONFIG_NET_POLL_CONTROLLER
 	.ndo_poll_controller    = gem_poll_controller,
 #endif
 };
 static int __devinit gem_init_one(struct pci_dev *pdev,
 				  const struct pci_device_id *ent)
 {
 	unsigned long gemreg_base, gemreg_len;
 	struct net_device *dev;
 	struct gem *gp;
 	int err, pci_using_dac;
 	printk_once(KERN_INFO "%s", version);
 	/* Apple gmac note: during probe, the chip is powered up by
 	 * the arch code to allow the code below to work (and to let
 	 * the chip be probed on the config space. It won't stay powered
 	 * up until the interface is brought up however, so we can't rely
 	 * on register configuration done at this point.
 	 */
 	err = pci_enable_device(pdev);
 	if (err) {
 		pr_err("Cannot enable MMIO operation, aborting\n");
 		return err;
 	}
 	pci_set_master(pdev);
 	/* Configure DMA attributes. */
 	/* All of the GEM documentation states that 64-bit DMA addressing
 	 * is fully supported and should work just fine.  However the
 	 * front end for RIO based GEMs is different and only supports
 	 * 32-bit addressing.
 	 *
 	 * For now we assume the various PPC GEMs are 32-bit only as well.
 	 */
 	if (pdev->vendor == PCI_VENDOR_ID_SUN &&
 	    pdev->device == PCI_DEVICE_ID_SUN_GEM &&
 	    !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
 		pci_using_dac = 1;
 	} else {
 		err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 		if (err) {
 			pr_err("No usable DMA configuration, aborting\n");
 			goto err_disable_device;
 		}
 		pci_using_dac = 0;
 	}
 	gemreg_base = pci_resource_start(pdev, 0);
 	gemreg_len = pci_resource_len(pdev, 0);
 	if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
 		pr_err("Cannot find proper PCI device base address, aborting\n");
 		err = -ENODEV;
 		goto err_disable_device;
 	}
 	dev = alloc_etherdev(sizeof(*gp));
 	if (!dev) {
 		pr_err("Etherdev alloc failed, aborting\n");
 		err = -ENOMEM;
 		goto err_disable_device;
 	}
 	SET_NETDEV_DEV(dev, &pdev->dev);
 	gp = netdev_priv(dev);
 	err = pci_request_regions(pdev, DRV_NAME);
 	if (err) {
 		pr_err("Cannot obtain PCI resources, aborting\n");
 		goto err_out_free_netdev;
 	}
 	gp->pdev = pdev;
 	dev->base_addr = (long) pdev;
 	gp->dev = dev;
 	gp->msg_enable = DEFAULT_MSG;
 	init_timer(&gp->link_timer);
 	gp->link_timer.function = gem_link_timer;
 	gp->link_timer.data = (unsigned long) gp;
 	INIT_WORK(&gp->reset_task, gem_reset_task);
 	gp->lstate = link_down;
 	gp->timer_ticks = 0;
 	netif_carrier_off(dev);
 	gp->regs = ioremap(gemreg_base, gemreg_len);
 	if (!gp->regs) {
 		pr_err("Cannot map device registers, aborting\n");
 		err = -EIO;
 		goto err_out_free_res;
 	}
 	/* On Apple, we want a reference to the Open Firmware device-tree
 	 * node. We use it for clock control.
 	 */
 #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC)
 	gp->of_node = pci_device_to_OF_node(pdev);
 #endif
 	/* Only Apple version supports WOL afaik */
 	if (pdev->vendor == PCI_VENDOR_ID_APPLE)
 		gp->has_wol = 1;
 	/* Make sure cell is enabled */
 	gem_get_cell(gp);
 	/* Make sure everything is stopped and in init state */
 	gem_reset(gp);
 	/* Fill up the mii_phy structure (even if we won't use it) */
 	gp->phy_mii.dev = dev;
 	gp->phy_mii.mdio_read = _phy_read;
 	gp->phy_mii.mdio_write = _phy_write;
 #ifdef CONFIG_PPC_PMAC
 	gp->phy_mii.platform_data = gp->of_node;
 #endif
 	/* By default, we start with autoneg */
 	gp->want_autoneg = 1;
 	/* Check fifo sizes, PHY type, etc... */
 	if (gem_check_invariants(gp)) {
 		err = -ENODEV;
 		goto err_out_iounmap;
 	}
 	/* It is guaranteed that the returned buffer will be at least
 	 * PAGE_SIZE aligned.
 	 */
 	gp->init_block = (struct gem_init_block *)
 		pci_alloc_consistent(pdev, sizeof(struct gem_init_block),
 				     &gp->gblock_dvma);
 	if (!gp->init_block) {
 		pr_err("Cannot allocate init block, aborting\n");
 		err = -ENOMEM;
 		goto err_out_iounmap;
 	}
 	if (gem_get_device_address(gp))
 		goto err_out_free_consistent;
 	dev->netdev_ops = &gem_netdev_ops;
 	netif_napi_add(dev, &gp->napi, gem_poll, 64);
 	dev->ethtool_ops = &gem_ethtool_ops;
 	dev->watchdog_timeo = 5 * HZ;
 	dev->irq = pdev->irq;
 	dev->dma = 0;
 	/* Set that now, in case PM kicks in now */
 	pci_set_drvdata(pdev, dev);
 	/* We can do scatter/gather and HW checksum */
 	dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM;
 	dev->features |= dev->hw_features | NETIF_F_RXCSUM;
 	if (pci_using_dac)
 		dev->features |= NETIF_F_HIGHDMA;
 	/* Register with kernel */
 	if (register_netdev(dev)) {
 		pr_err("Cannot register net device, aborting\n");
 		err = -ENOMEM;
 		goto err_out_free_consistent;
 	}
 	/* Undo the get_cell with appropriate locking (we could use
 	 * ndo_init/uninit but that would be even more clumsy imho)
 	 */
 	rtnl_lock();
 	gem_put_cell(gp);
 	rtnl_unlock();
 	netdev_info(dev, "Sun GEM (PCI) 10/100/1000BaseT Ethernet %pM\n",
 		    dev->dev_addr);
 	return 0;
 err_out_free_consistent:
 	gem_remove_one(pdev);
 err_out_iounmap:
 	gem_put_cell(gp);
 	iounmap(gp->regs);
 err_out_free_res:
 	pci_release_regions(pdev);
 err_out_free_netdev:
 	free_netdev(dev);
 err_disable_device:
 	pci_disable_device(pdev);
 	return err;
 }
 static struct pci_driver gem_driver = {
 	.name		= GEM_MODULE_NAME,
 	.id_table	= gem_pci_tbl,
 	.probe		= gem_init_one,
 	.remove		= gem_remove_one,
 #ifdef CONFIG_PM
 	.suspend	= gem_suspend,
 	.resume		= gem_resume,
 #endif /* CONFIG_PM */
 };
 static int __init gem_init(void)
 {
 	return pci_register_driver(&gem_driver);
 }
 static void __exit gem_cleanup(void)
 {
 	pci_unregister_driver(&gem_driver);
 }
 module_init(gem_init);
 module_exit(gem_cleanup);