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Commit 5e3bcf30d655c2e277c77b523347685d06bb9d31

Authored by Mike Frysinger
1 parent 9346dba556
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

Blackfin: dma: constify MMR pointer array 

The array of pointers is never written, so constify it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Showing 8 changed files with 8 additions and 8 deletions Inline Diff

arch/blackfin/include/asm/dma.h
Diff comments   View file @ 5e3bcf3
1 /* 1 /*
2 * dma.h - Blackfin DMA defines/structures/etc... 2 * dma.h - Blackfin DMA defines/structures/etc...
3 * 3 *
4 * Copyright 2004-2008 Analog Devices Inc. 4 * Copyright 2004-2008 Analog Devices Inc.
5 * Licensed under the GPL-2 or later. 5 * Licensed under the GPL-2 or later.
6 */ 6 */
7 7
8 #ifndef _BLACKFIN_DMA_H_ 8 #ifndef _BLACKFIN_DMA_H_
9 #define _BLACKFIN_DMA_H_ 9 #define _BLACKFIN_DMA_H_
10 10
11 #include <linux/interrupt.h> 11 #include <linux/interrupt.h>
12 #include <mach/dma.h> 12 #include <mach/dma.h>
13 #include <asm/atomic.h> 13 #include <asm/atomic.h>
14 #include <asm/blackfin.h> 14 #include <asm/blackfin.h>
15 #include <asm/page.h> 15 #include <asm/page.h>
16 #include <asm-generic/dma.h> 16 #include <asm-generic/dma.h>
17 #include <asm/bfin_dma.h> 17 #include <asm/bfin_dma.h>
18 18
19 /*------------------------- 19 /*-------------------------
20 * config reg bits value 20 * config reg bits value
21 *-------------------------*/ 21 *-------------------------*/
22 #define DATA_SIZE_8 0 22 #define DATA_SIZE_8 0
23 #define DATA_SIZE_16 1 23 #define DATA_SIZE_16 1
24 #define DATA_SIZE_32 2 24 #define DATA_SIZE_32 2
25 25
26 #define DMA_FLOW_STOP 0 26 #define DMA_FLOW_STOP 0
27 #define DMA_FLOW_AUTO 1 27 #define DMA_FLOW_AUTO 1
28 #define DMA_FLOW_ARRAY 4 28 #define DMA_FLOW_ARRAY 4
29 #define DMA_FLOW_SMALL 6 29 #define DMA_FLOW_SMALL 6
30 #define DMA_FLOW_LARGE 7 30 #define DMA_FLOW_LARGE 7
31 31
32 #define DIMENSION_LINEAR 0 32 #define DIMENSION_LINEAR 0
33 #define DIMENSION_2D 1 33 #define DIMENSION_2D 1
34 34
35 #define DIR_READ 0 35 #define DIR_READ 0
36 #define DIR_WRITE 1 36 #define DIR_WRITE 1
37 37
38 #define INTR_DISABLE 0 38 #define INTR_DISABLE 0
39 #define INTR_ON_BUF 2 39 #define INTR_ON_BUF 2
40 #define INTR_ON_ROW 3 40 #define INTR_ON_ROW 3
41 41
42 #define DMA_NOSYNC_KEEP_DMA_BUF 0 42 #define DMA_NOSYNC_KEEP_DMA_BUF 0
43 #define DMA_SYNC_RESTART 1 43 #define DMA_SYNC_RESTART 1
44 44
45 struct dmasg { 45 struct dmasg {
46 void *next_desc_addr; 46 void *next_desc_addr;
47 unsigned long start_addr; 47 unsigned long start_addr;
48 unsigned short cfg; 48 unsigned short cfg;
49 unsigned short x_count; 49 unsigned short x_count;
50 short x_modify; 50 short x_modify;
51 unsigned short y_count; 51 unsigned short y_count;
52 short y_modify; 52 short y_modify;
53 } __attribute__((packed)); 53 } __attribute__((packed));
54 54
55 struct dma_register { 55 struct dma_register {
56 void *next_desc_ptr; /* DMA Next Descriptor Pointer register */ 56 void *next_desc_ptr; /* DMA Next Descriptor Pointer register */
57 unsigned long start_addr; /* DMA Start address register */ 57 unsigned long start_addr; /* DMA Start address register */
58 58
59 unsigned short cfg; /* DMA Configuration register */ 59 unsigned short cfg; /* DMA Configuration register */
60 unsigned short dummy1; /* DMA Configuration register */ 60 unsigned short dummy1; /* DMA Configuration register */
61 61
62 unsigned long reserved; 62 unsigned long reserved;
63 63
64 unsigned short x_count; /* DMA x_count register */ 64 unsigned short x_count; /* DMA x_count register */
65 unsigned short dummy2; 65 unsigned short dummy2;
66 66
67 short x_modify; /* DMA x_modify register */ 67 short x_modify; /* DMA x_modify register */
68 unsigned short dummy3; 68 unsigned short dummy3;
69 69
70 unsigned short y_count; /* DMA y_count register */ 70 unsigned short y_count; /* DMA y_count register */
71 unsigned short dummy4; 71 unsigned short dummy4;
72 72
73 short y_modify; /* DMA y_modify register */ 73 short y_modify; /* DMA y_modify register */
74 unsigned short dummy5; 74 unsigned short dummy5;
75 75
76 void *curr_desc_ptr; /* DMA Current Descriptor Pointer 76 void *curr_desc_ptr; /* DMA Current Descriptor Pointer
77 register */ 77 register */
78 unsigned long curr_addr_ptr; /* DMA Current Address Pointer 78 unsigned long curr_addr_ptr; /* DMA Current Address Pointer
79 register */ 79 register */
80 unsigned short irq_status; /* DMA irq status register */ 80 unsigned short irq_status; /* DMA irq status register */
81 unsigned short dummy6; 81 unsigned short dummy6;
82 82
83 unsigned short peripheral_map; /* DMA peripheral map register */ 83 unsigned short peripheral_map; /* DMA peripheral map register */
84 unsigned short dummy7; 84 unsigned short dummy7;
85 85
86 unsigned short curr_x_count; /* DMA Current x-count register */ 86 unsigned short curr_x_count; /* DMA Current x-count register */
87 unsigned short dummy8; 87 unsigned short dummy8;
88 88
89 unsigned long reserved2; 89 unsigned long reserved2;
90 90
91 unsigned short curr_y_count; /* DMA Current y-count register */ 91 unsigned short curr_y_count; /* DMA Current y-count register */
92 unsigned short dummy9; 92 unsigned short dummy9;
93 93
94 unsigned long reserved3; 94 unsigned long reserved3;
95 95
96 }; 96 };
97 97
98 struct dma_channel { 98 struct dma_channel {
99 const char *device_id; 99 const char *device_id;
100 atomic_t chan_status; 100 atomic_t chan_status;
101 volatile struct dma_register *regs; 101 volatile struct dma_register *regs;
102 struct dmasg *sg; /* large mode descriptor */ 102 struct dmasg *sg; /* large mode descriptor */
103 unsigned int irq; 103 unsigned int irq;
104 void *data; 104 void *data;
105 #ifdef CONFIG_PM 105 #ifdef CONFIG_PM
106 unsigned short saved_peripheral_map; 106 unsigned short saved_peripheral_map;
107 #endif 107 #endif
108 }; 108 };
109 109
110 #ifdef CONFIG_PM 110 #ifdef CONFIG_PM
111 int blackfin_dma_suspend(void); 111 int blackfin_dma_suspend(void);
112 void blackfin_dma_resume(void); 112 void blackfin_dma_resume(void);
113 #endif 113 #endif
114 114
115 /******************************************************************************* 115 /*******************************************************************************
116 * DMA API's 116 * DMA API's
117 *******************************************************************************/ 117 *******************************************************************************/
118 extern struct dma_channel dma_ch[MAX_DMA_CHANNELS]; 118 extern struct dma_channel dma_ch[MAX_DMA_CHANNELS];
119 extern struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS]; 119 extern struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS];
120 extern int channel2irq(unsigned int channel); 120 extern int channel2irq(unsigned int channel);
121 121
122 static inline void set_dma_start_addr(unsigned int channel, unsigned long addr) 122 static inline void set_dma_start_addr(unsigned int channel, unsigned long addr)
123 { 123 {
124 dma_ch[channel].regs->start_addr = addr; 124 dma_ch[channel].regs->start_addr = addr;
125 } 125 }
126 static inline void set_dma_next_desc_addr(unsigned int channel, void *addr) 126 static inline void set_dma_next_desc_addr(unsigned int channel, void *addr)
127 { 127 {
128 dma_ch[channel].regs->next_desc_ptr = addr; 128 dma_ch[channel].regs->next_desc_ptr = addr;
129 } 129 }
130 static inline void set_dma_curr_desc_addr(unsigned int channel, void *addr) 130 static inline void set_dma_curr_desc_addr(unsigned int channel, void *addr)
131 { 131 {
132 dma_ch[channel].regs->curr_desc_ptr = addr; 132 dma_ch[channel].regs->curr_desc_ptr = addr;
133 } 133 }
134 static inline void set_dma_x_count(unsigned int channel, unsigned short x_count) 134 static inline void set_dma_x_count(unsigned int channel, unsigned short x_count)
135 { 135 {
136 dma_ch[channel].regs->x_count = x_count; 136 dma_ch[channel].regs->x_count = x_count;
137 } 137 }
138 static inline void set_dma_y_count(unsigned int channel, unsigned short y_count) 138 static inline void set_dma_y_count(unsigned int channel, unsigned short y_count)
139 { 139 {
140 dma_ch[channel].regs->y_count = y_count; 140 dma_ch[channel].regs->y_count = y_count;
141 } 141 }
142 static inline void set_dma_x_modify(unsigned int channel, short x_modify) 142 static inline void set_dma_x_modify(unsigned int channel, short x_modify)
143 { 143 {
144 dma_ch[channel].regs->x_modify = x_modify; 144 dma_ch[channel].regs->x_modify = x_modify;
145 } 145 }
146 static inline void set_dma_y_modify(unsigned int channel, short y_modify) 146 static inline void set_dma_y_modify(unsigned int channel, short y_modify)
147 { 147 {
148 dma_ch[channel].regs->y_modify = y_modify; 148 dma_ch[channel].regs->y_modify = y_modify;
149 } 149 }
150 static inline void set_dma_config(unsigned int channel, unsigned short config) 150 static inline void set_dma_config(unsigned int channel, unsigned short config)
151 { 151 {
152 dma_ch[channel].regs->cfg = config; 152 dma_ch[channel].regs->cfg = config;
153 } 153 }
154 static inline void set_dma_curr_addr(unsigned int channel, unsigned long addr) 154 static inline void set_dma_curr_addr(unsigned int channel, unsigned long addr)
155 { 155 {
156 dma_ch[channel].regs->curr_addr_ptr = addr; 156 dma_ch[channel].regs->curr_addr_ptr = addr;
157 } 157 }
158 158
159 static inline unsigned short 159 static inline unsigned short
160 set_bfin_dma_config(char direction, char flow_mode, 160 set_bfin_dma_config(char direction, char flow_mode,
161 char intr_mode, char dma_mode, char width, char syncmode) 161 char intr_mode, char dma_mode, char width, char syncmode)
162 { 162 {
163 return (direction << 1) | (width << 2) | (dma_mode << 4) | 163 return (direction << 1) | (width << 2) | (dma_mode << 4) |
164 (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5); 164 (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5);
165 } 165 }
166 166
167 static inline unsigned short get_dma_curr_irqstat(unsigned int channel) 167 static inline unsigned short get_dma_curr_irqstat(unsigned int channel)
168 { 168 {
169 return dma_ch[channel].regs->irq_status; 169 return dma_ch[channel].regs->irq_status;
170 } 170 }
171 static inline unsigned short get_dma_curr_xcount(unsigned int channel) 171 static inline unsigned short get_dma_curr_xcount(unsigned int channel)
172 { 172 {
173 return dma_ch[channel].regs->curr_x_count; 173 return dma_ch[channel].regs->curr_x_count;
174 } 174 }
175 static inline unsigned short get_dma_curr_ycount(unsigned int channel) 175 static inline unsigned short get_dma_curr_ycount(unsigned int channel)
176 { 176 {
177 return dma_ch[channel].regs->curr_y_count; 177 return dma_ch[channel].regs->curr_y_count;
178 } 178 }
179 static inline void *get_dma_next_desc_ptr(unsigned int channel) 179 static inline void *get_dma_next_desc_ptr(unsigned int channel)
180 { 180 {
181 return dma_ch[channel].regs->next_desc_ptr; 181 return dma_ch[channel].regs->next_desc_ptr;
182 } 182 }
183 static inline void *get_dma_curr_desc_ptr(unsigned int channel) 183 static inline void *get_dma_curr_desc_ptr(unsigned int channel)
184 { 184 {
185 return dma_ch[channel].regs->curr_desc_ptr; 185 return dma_ch[channel].regs->curr_desc_ptr;
186 } 186 }
187 static inline unsigned short get_dma_config(unsigned int channel) 187 static inline unsigned short get_dma_config(unsigned int channel)
188 { 188 {
189 return dma_ch[channel].regs->cfg; 189 return dma_ch[channel].regs->cfg;
190 } 190 }
191 static inline unsigned long get_dma_curr_addr(unsigned int channel) 191 static inline unsigned long get_dma_curr_addr(unsigned int channel)
192 { 192 {
193 return dma_ch[channel].regs->curr_addr_ptr; 193 return dma_ch[channel].regs->curr_addr_ptr;
194 } 194 }
195 195
196 static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize) 196 static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize)
197 { 197 {
198 /* Make sure the internal data buffers in the core are drained 198 /* Make sure the internal data buffers in the core are drained
199 * so that the DMA descriptors are completely written when the 199 * so that the DMA descriptors are completely written when the
200 * DMA engine goes to fetch them below. 200 * DMA engine goes to fetch them below.
201 */ 201 */
202 SSYNC(); 202 SSYNC();
203 203
204 dma_ch[channel].regs->next_desc_ptr = sg; 204 dma_ch[channel].regs->next_desc_ptr = sg;
205 dma_ch[channel].regs->cfg = 205 dma_ch[channel].regs->cfg =
206 (dma_ch[channel].regs->cfg & ~(0xf << 8)) | 206 (dma_ch[channel].regs->cfg & ~(0xf << 8)) |
207 ((ndsize & 0xf) << 8); 207 ((ndsize & 0xf) << 8);
208 } 208 }
209 209
210 static inline int dma_channel_active(unsigned int channel) 210 static inline int dma_channel_active(unsigned int channel)
211 { 211 {
212 return atomic_read(&dma_ch[channel].chan_status); 212 return atomic_read(&dma_ch[channel].chan_status);
213 } 213 }
214 214
215 static inline void disable_dma(unsigned int channel) 215 static inline void disable_dma(unsigned int channel)
216 { 216 {
217 dma_ch[channel].regs->cfg &= ~DMAEN; 217 dma_ch[channel].regs->cfg &= ~DMAEN;
218 SSYNC(); 218 SSYNC();
219 } 219 }
220 static inline void enable_dma(unsigned int channel) 220 static inline void enable_dma(unsigned int channel)
221 { 221 {
222 dma_ch[channel].regs->curr_x_count = 0; 222 dma_ch[channel].regs->curr_x_count = 0;
223 dma_ch[channel].regs->curr_y_count = 0; 223 dma_ch[channel].regs->curr_y_count = 0;
224 dma_ch[channel].regs->cfg |= DMAEN; 224 dma_ch[channel].regs->cfg |= DMAEN;
225 } 225 }
226 int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data); 226 int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data);
227 227
228 static inline void dma_disable_irq(unsigned int channel) 228 static inline void dma_disable_irq(unsigned int channel)
229 { 229 {
230 disable_irq(dma_ch[channel].irq); 230 disable_irq(dma_ch[channel].irq);
231 } 231 }
232 static inline void dma_disable_irq_nosync(unsigned int channel) 232 static inline void dma_disable_irq_nosync(unsigned int channel)
233 { 233 {
234 disable_irq_nosync(dma_ch[channel].irq); 234 disable_irq_nosync(dma_ch[channel].irq);
235 } 235 }
236 static inline void dma_enable_irq(unsigned int channel) 236 static inline void dma_enable_irq(unsigned int channel)
237 { 237 {
238 enable_irq(dma_ch[channel].irq); 238 enable_irq(dma_ch[channel].irq);
239 } 239 }
240 static inline void clear_dma_irqstat(unsigned int channel) 240 static inline void clear_dma_irqstat(unsigned int channel)
241 { 241 {
242 dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR; 242 dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR;
243 } 243 }
244 244
245 void *dma_memcpy(void *dest, const void *src, size_t count); 245 void *dma_memcpy(void *dest, const void *src, size_t count);
246 void *dma_memcpy_nocache(void *dest, const void *src, size_t count); 246 void *dma_memcpy_nocache(void *dest, const void *src, size_t count);
247 void *safe_dma_memcpy(void *dest, const void *src, size_t count); 247 void *safe_dma_memcpy(void *dest, const void *src, size_t count);
248 void blackfin_dma_early_init(void); 248 void blackfin_dma_early_init(void);
249 void early_dma_memcpy(void *dest, const void *src, size_t count); 249 void early_dma_memcpy(void *dest, const void *src, size_t count);
250 void early_dma_memcpy_done(void); 250 void early_dma_memcpy_done(void);
251 251
252 #endif 252 #endif
253 253
arch/blackfin/mach-bf518/dma.c
Diff comments   View file @ 5e3bcf3
1 /* 1 /*
2 * the simple DMA Implementation for Blackfin 2 * the simple DMA Implementation for Blackfin
3 * 3 *
4 * Copyright 2008 Analog Devices Inc. 4 * Copyright 2008 Analog Devices Inc.
5 * 5 *
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
9 #include <linux/module.h> 9 #include <linux/module.h>
10 10
11 #include <asm/blackfin.h> 11 #include <asm/blackfin.h>
12 #include <asm/dma.h> 12 #include <asm/dma.h>
13 13
14 struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { 14 struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
15 (struct dma_register *) DMA0_NEXT_DESC_PTR, 15 (struct dma_register *) DMA0_NEXT_DESC_PTR,
16 (struct dma_register *) DMA1_NEXT_DESC_PTR, 16 (struct dma_register *) DMA1_NEXT_DESC_PTR,
17 (struct dma_register *) DMA2_NEXT_DESC_PTR, 17 (struct dma_register *) DMA2_NEXT_DESC_PTR,
18 (struct dma_register *) DMA3_NEXT_DESC_PTR, 18 (struct dma_register *) DMA3_NEXT_DESC_PTR,
19 (struct dma_register *) DMA4_NEXT_DESC_PTR, 19 (struct dma_register *) DMA4_NEXT_DESC_PTR,
20 (struct dma_register *) DMA5_NEXT_DESC_PTR, 20 (struct dma_register *) DMA5_NEXT_DESC_PTR,
21 (struct dma_register *) DMA6_NEXT_DESC_PTR, 21 (struct dma_register *) DMA6_NEXT_DESC_PTR,
22 (struct dma_register *) DMA7_NEXT_DESC_PTR, 22 (struct dma_register *) DMA7_NEXT_DESC_PTR,
23 (struct dma_register *) DMA8_NEXT_DESC_PTR, 23 (struct dma_register *) DMA8_NEXT_DESC_PTR,
24 (struct dma_register *) DMA9_NEXT_DESC_PTR, 24 (struct dma_register *) DMA9_NEXT_DESC_PTR,
25 (struct dma_register *) DMA10_NEXT_DESC_PTR, 25 (struct dma_register *) DMA10_NEXT_DESC_PTR,
26 (struct dma_register *) DMA11_NEXT_DESC_PTR, 26 (struct dma_register *) DMA11_NEXT_DESC_PTR,
27 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR, 27 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
28 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR, 28 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
29 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, 29 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
30 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, 30 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
31 }; 31 };
32 EXPORT_SYMBOL(dma_io_base_addr); 32 EXPORT_SYMBOL(dma_io_base_addr);
33 33
34 int channel2irq(unsigned int channel) 34 int channel2irq(unsigned int channel)
35 { 35 {
36 int ret_irq = -1; 36 int ret_irq = -1;
37 37
38 switch (channel) { 38 switch (channel) {
39 case CH_PPI: 39 case CH_PPI:
40 ret_irq = IRQ_PPI; 40 ret_irq = IRQ_PPI;
41 break; 41 break;
42 42
43 case CH_EMAC_RX: 43 case CH_EMAC_RX:
44 ret_irq = IRQ_MAC_RX; 44 ret_irq = IRQ_MAC_RX;
45 break; 45 break;
46 46
47 case CH_EMAC_TX: 47 case CH_EMAC_TX:
48 ret_irq = IRQ_MAC_TX; 48 ret_irq = IRQ_MAC_TX;
49 break; 49 break;
50 50
51 case CH_UART1_RX: 51 case CH_UART1_RX:
52 ret_irq = IRQ_UART1_RX; 52 ret_irq = IRQ_UART1_RX;
53 break; 53 break;
54 54
55 case CH_UART1_TX: 55 case CH_UART1_TX:
56 ret_irq = IRQ_UART1_TX; 56 ret_irq = IRQ_UART1_TX;
57 break; 57 break;
58 58
59 case CH_SPORT0_RX: 59 case CH_SPORT0_RX:
60 ret_irq = IRQ_SPORT0_RX; 60 ret_irq = IRQ_SPORT0_RX;
61 break; 61 break;
62 62
63 case CH_SPORT0_TX: 63 case CH_SPORT0_TX:
64 ret_irq = IRQ_SPORT0_TX; 64 ret_irq = IRQ_SPORT0_TX;
65 break; 65 break;
66 66
67 case CH_SPORT1_RX: 67 case CH_SPORT1_RX:
68 ret_irq = IRQ_SPORT1_RX; 68 ret_irq = IRQ_SPORT1_RX;
69 break; 69 break;
70 70
71 case CH_SPORT1_TX: 71 case CH_SPORT1_TX:
72 ret_irq = IRQ_SPORT1_TX; 72 ret_irq = IRQ_SPORT1_TX;
73 break; 73 break;
74 74
75 case CH_SPI0: 75 case CH_SPI0:
76 ret_irq = IRQ_SPI0; 76 ret_irq = IRQ_SPI0;
77 break; 77 break;
78 78
79 case CH_UART0_RX: 79 case CH_UART0_RX:
80 ret_irq = IRQ_UART0_RX; 80 ret_irq = IRQ_UART0_RX;
81 break; 81 break;
82 82
83 case CH_UART0_TX: 83 case CH_UART0_TX:
84 ret_irq = IRQ_UART0_TX; 84 ret_irq = IRQ_UART0_TX;
85 break; 85 break;
86 86
87 case CH_MEM_STREAM0_SRC: 87 case CH_MEM_STREAM0_SRC:
88 case CH_MEM_STREAM0_DEST: 88 case CH_MEM_STREAM0_DEST:
89 ret_irq = IRQ_MEM_DMA0; 89 ret_irq = IRQ_MEM_DMA0;
90 break; 90 break;
91 91
92 case CH_MEM_STREAM1_SRC: 92 case CH_MEM_STREAM1_SRC:
93 case CH_MEM_STREAM1_DEST: 93 case CH_MEM_STREAM1_DEST:
94 ret_irq = IRQ_MEM_DMA1; 94 ret_irq = IRQ_MEM_DMA1;
95 break; 95 break;
96 } 96 }
97 return ret_irq; 97 return ret_irq;
98 } 98 }
99 99
arch/blackfin/mach-bf527/dma.c
Diff comments   View file @ 5e3bcf3
1 /* 1 /*
2 * This file contains the simple DMA Implementation for Blackfin 2 * This file contains the simple DMA Implementation for Blackfin
3 * 3 *
4 * Copyright 2007-2008 Analog Devices Inc. 4 * Copyright 2007-2008 Analog Devices Inc.
5 * 5 *
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
9 #include <linux/module.h> 9 #include <linux/module.h>
10 10
11 #include <asm/blackfin.h> 11 #include <asm/blackfin.h>
12 #include <asm/dma.h> 12 #include <asm/dma.h>
13 13
14 struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { 14 struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
15 (struct dma_register *) DMA0_NEXT_DESC_PTR, 15 (struct dma_register *) DMA0_NEXT_DESC_PTR,
16 (struct dma_register *) DMA1_NEXT_DESC_PTR, 16 (struct dma_register *) DMA1_NEXT_DESC_PTR,
17 (struct dma_register *) DMA2_NEXT_DESC_PTR, 17 (struct dma_register *) DMA2_NEXT_DESC_PTR,
18 (struct dma_register *) DMA3_NEXT_DESC_PTR, 18 (struct dma_register *) DMA3_NEXT_DESC_PTR,
19 (struct dma_register *) DMA4_NEXT_DESC_PTR, 19 (struct dma_register *) DMA4_NEXT_DESC_PTR,
20 (struct dma_register *) DMA5_NEXT_DESC_PTR, 20 (struct dma_register *) DMA5_NEXT_DESC_PTR,
21 (struct dma_register *) DMA6_NEXT_DESC_PTR, 21 (struct dma_register *) DMA6_NEXT_DESC_PTR,
22 (struct dma_register *) DMA7_NEXT_DESC_PTR, 22 (struct dma_register *) DMA7_NEXT_DESC_PTR,
23 (struct dma_register *) DMA8_NEXT_DESC_PTR, 23 (struct dma_register *) DMA8_NEXT_DESC_PTR,
24 (struct dma_register *) DMA9_NEXT_DESC_PTR, 24 (struct dma_register *) DMA9_NEXT_DESC_PTR,
25 (struct dma_register *) DMA10_NEXT_DESC_PTR, 25 (struct dma_register *) DMA10_NEXT_DESC_PTR,
26 (struct dma_register *) DMA11_NEXT_DESC_PTR, 26 (struct dma_register *) DMA11_NEXT_DESC_PTR,
27 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR, 27 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
28 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR, 28 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
29 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, 29 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
30 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, 30 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
31 }; 31 };
32 EXPORT_SYMBOL(dma_io_base_addr); 32 EXPORT_SYMBOL(dma_io_base_addr);
33 33
34 int channel2irq(unsigned int channel) 34 int channel2irq(unsigned int channel)
35 { 35 {
36 int ret_irq = -1; 36 int ret_irq = -1;
37 37
38 switch (channel) { 38 switch (channel) {
39 case CH_PPI: 39 case CH_PPI:
40 ret_irq = IRQ_PPI; 40 ret_irq = IRQ_PPI;
41 break; 41 break;
42 42
43 case CH_EMAC_RX: 43 case CH_EMAC_RX:
44 ret_irq = IRQ_MAC_RX; 44 ret_irq = IRQ_MAC_RX;
45 break; 45 break;
46 46
47 case CH_EMAC_TX: 47 case CH_EMAC_TX:
48 ret_irq = IRQ_MAC_TX; 48 ret_irq = IRQ_MAC_TX;
49 break; 49 break;
50 50
51 case CH_UART1_RX: 51 case CH_UART1_RX:
52 ret_irq = IRQ_UART1_RX; 52 ret_irq = IRQ_UART1_RX;
53 break; 53 break;
54 54
55 case CH_UART1_TX: 55 case CH_UART1_TX:
56 ret_irq = IRQ_UART1_TX; 56 ret_irq = IRQ_UART1_TX;
57 break; 57 break;
58 58
59 case CH_SPORT0_RX: 59 case CH_SPORT0_RX:
60 ret_irq = IRQ_SPORT0_RX; 60 ret_irq = IRQ_SPORT0_RX;
61 break; 61 break;
62 62
63 case CH_SPORT0_TX: 63 case CH_SPORT0_TX:
64 ret_irq = IRQ_SPORT0_TX; 64 ret_irq = IRQ_SPORT0_TX;
65 break; 65 break;
66 66
67 case CH_SPORT1_RX: 67 case CH_SPORT1_RX:
68 ret_irq = IRQ_SPORT1_RX; 68 ret_irq = IRQ_SPORT1_RX;
69 break; 69 break;
70 70
71 case CH_SPORT1_TX: 71 case CH_SPORT1_TX:
72 ret_irq = IRQ_SPORT1_TX; 72 ret_irq = IRQ_SPORT1_TX;
73 break; 73 break;
74 74
75 case CH_SPI: 75 case CH_SPI:
76 ret_irq = IRQ_SPI; 76 ret_irq = IRQ_SPI;
77 break; 77 break;
78 78
79 case CH_UART0_RX: 79 case CH_UART0_RX:
80 ret_irq = IRQ_UART0_RX; 80 ret_irq = IRQ_UART0_RX;
81 break; 81 break;
82 82
83 case CH_UART0_TX: 83 case CH_UART0_TX:
84 ret_irq = IRQ_UART0_TX; 84 ret_irq = IRQ_UART0_TX;
85 break; 85 break;
86 86
87 case CH_MEM_STREAM0_SRC: 87 case CH_MEM_STREAM0_SRC:
88 case CH_MEM_STREAM0_DEST: 88 case CH_MEM_STREAM0_DEST:
89 ret_irq = IRQ_MEM_DMA0; 89 ret_irq = IRQ_MEM_DMA0;
90 break; 90 break;
91 91
92 case CH_MEM_STREAM1_SRC: 92 case CH_MEM_STREAM1_SRC:
93 case CH_MEM_STREAM1_DEST: 93 case CH_MEM_STREAM1_DEST:
94 ret_irq = IRQ_MEM_DMA1; 94 ret_irq = IRQ_MEM_DMA1;
95 break; 95 break;
96 } 96 }
97 return ret_irq; 97 return ret_irq;
98 } 98 }
99 99
arch/blackfin/mach-bf533/dma.c
Diff comments   View file @ 5e3bcf3
1 /* 1 /*
2 * simple DMA Implementation for Blackfin 2 * simple DMA Implementation for Blackfin
3 * 3 *
4 * Copyright 2007-2009 Analog Devices Inc. 4 * Copyright 2007-2009 Analog Devices Inc.
5 * 5 *
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
9 #include <linux/module.h> 9 #include <linux/module.h>
10 10
11 #include <asm/blackfin.h> 11 #include <asm/blackfin.h>
12 #include <asm/dma.h> 12 #include <asm/dma.h>
13 13
14 struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { 14 struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
15 (struct dma_register *) DMA0_NEXT_DESC_PTR, 15 (struct dma_register *) DMA0_NEXT_DESC_PTR,
16 (struct dma_register *) DMA1_NEXT_DESC_PTR, 16 (struct dma_register *) DMA1_NEXT_DESC_PTR,
17 (struct dma_register *) DMA2_NEXT_DESC_PTR, 17 (struct dma_register *) DMA2_NEXT_DESC_PTR,
18 (struct dma_register *) DMA3_NEXT_DESC_PTR, 18 (struct dma_register *) DMA3_NEXT_DESC_PTR,
19 (struct dma_register *) DMA4_NEXT_DESC_PTR, 19 (struct dma_register *) DMA4_NEXT_DESC_PTR,
20 (struct dma_register *) DMA5_NEXT_DESC_PTR, 20 (struct dma_register *) DMA5_NEXT_DESC_PTR,
21 (struct dma_register *) DMA6_NEXT_DESC_PTR, 21 (struct dma_register *) DMA6_NEXT_DESC_PTR,
22 (struct dma_register *) DMA7_NEXT_DESC_PTR, 22 (struct dma_register *) DMA7_NEXT_DESC_PTR,
23 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR, 23 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
24 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR, 24 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
25 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, 25 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
26 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, 26 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
27 }; 27 };
28 EXPORT_SYMBOL(dma_io_base_addr); 28 EXPORT_SYMBOL(dma_io_base_addr);
29 29
30 int channel2irq(unsigned int channel) 30 int channel2irq(unsigned int channel)
31 { 31 {
32 int ret_irq = -1; 32 int ret_irq = -1;
33 33
34 switch (channel) { 34 switch (channel) {
35 case CH_PPI: 35 case CH_PPI:
36 ret_irq = IRQ_PPI; 36 ret_irq = IRQ_PPI;
37 break; 37 break;
38 38
39 case CH_SPORT0_RX: 39 case CH_SPORT0_RX:
40 ret_irq = IRQ_SPORT0_RX; 40 ret_irq = IRQ_SPORT0_RX;
41 break; 41 break;
42 42
43 case CH_SPORT0_TX: 43 case CH_SPORT0_TX:
44 ret_irq = IRQ_SPORT0_TX; 44 ret_irq = IRQ_SPORT0_TX;
45 break; 45 break;
46 46
47 case CH_SPORT1_RX: 47 case CH_SPORT1_RX:
48 ret_irq = IRQ_SPORT1_RX; 48 ret_irq = IRQ_SPORT1_RX;
49 break; 49 break;
50 50
51 case CH_SPORT1_TX: 51 case CH_SPORT1_TX:
52 ret_irq = IRQ_SPORT1_TX; 52 ret_irq = IRQ_SPORT1_TX;
53 break; 53 break;
54 54
55 case CH_SPI: 55 case CH_SPI:
56 ret_irq = IRQ_SPI; 56 ret_irq = IRQ_SPI;
57 break; 57 break;
58 58
59 case CH_UART0_RX: 59 case CH_UART0_RX:
60 ret_irq = IRQ_UART0_RX; 60 ret_irq = IRQ_UART0_RX;
61 break; 61 break;
62 62
63 case CH_UART0_TX: 63 case CH_UART0_TX:
64 ret_irq = IRQ_UART0_TX; 64 ret_irq = IRQ_UART0_TX;
65 break; 65 break;
66 66
67 case CH_MEM_STREAM0_SRC: 67 case CH_MEM_STREAM0_SRC:
68 case CH_MEM_STREAM0_DEST: 68 case CH_MEM_STREAM0_DEST:
69 ret_irq = IRQ_MEM_DMA0; 69 ret_irq = IRQ_MEM_DMA0;
70 break; 70 break;
71 71
72 case CH_MEM_STREAM1_SRC: 72 case CH_MEM_STREAM1_SRC:
73 case CH_MEM_STREAM1_DEST: 73 case CH_MEM_STREAM1_DEST:
74 ret_irq = IRQ_MEM_DMA1; 74 ret_irq = IRQ_MEM_DMA1;
75 break; 75 break;
76 } 76 }
77 return ret_irq; 77 return ret_irq;
78 } 78 }
79 79
arch/blackfin/mach-bf537/dma.c
Diff comments   View file @ 5e3bcf3
1 /* 1 /*
2 * Copyright 2007-2009 Analog Devices Inc. 2 * Copyright 2007-2009 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 * 5 *
6 * This file contains the simple DMA Implementation for Blackfin 6 * This file contains the simple DMA Implementation for Blackfin
7 */ 7 */
8 8
9 #include <linux/module.h> 9 #include <linux/module.h>
10 10
11 #include <asm/blackfin.h> 11 #include <asm/blackfin.h>
12 #include <asm/dma.h> 12 #include <asm/dma.h>
13 13
14 struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { 14 struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
15 (struct dma_register *) DMA0_NEXT_DESC_PTR, 15 (struct dma_register *) DMA0_NEXT_DESC_PTR,
16 (struct dma_register *) DMA1_NEXT_DESC_PTR, 16 (struct dma_register *) DMA1_NEXT_DESC_PTR,
17 (struct dma_register *) DMA2_NEXT_DESC_PTR, 17 (struct dma_register *) DMA2_NEXT_DESC_PTR,
18 (struct dma_register *) DMA3_NEXT_DESC_PTR, 18 (struct dma_register *) DMA3_NEXT_DESC_PTR,
19 (struct dma_register *) DMA4_NEXT_DESC_PTR, 19 (struct dma_register *) DMA4_NEXT_DESC_PTR,
20 (struct dma_register *) DMA5_NEXT_DESC_PTR, 20 (struct dma_register *) DMA5_NEXT_DESC_PTR,
21 (struct dma_register *) DMA6_NEXT_DESC_PTR, 21 (struct dma_register *) DMA6_NEXT_DESC_PTR,
22 (struct dma_register *) DMA7_NEXT_DESC_PTR, 22 (struct dma_register *) DMA7_NEXT_DESC_PTR,
23 (struct dma_register *) DMA8_NEXT_DESC_PTR, 23 (struct dma_register *) DMA8_NEXT_DESC_PTR,
24 (struct dma_register *) DMA9_NEXT_DESC_PTR, 24 (struct dma_register *) DMA9_NEXT_DESC_PTR,
25 (struct dma_register *) DMA10_NEXT_DESC_PTR, 25 (struct dma_register *) DMA10_NEXT_DESC_PTR,
26 (struct dma_register *) DMA11_NEXT_DESC_PTR, 26 (struct dma_register *) DMA11_NEXT_DESC_PTR,
27 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR, 27 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
28 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR, 28 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
29 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, 29 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
30 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, 30 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
31 }; 31 };
32 EXPORT_SYMBOL(dma_io_base_addr); 32 EXPORT_SYMBOL(dma_io_base_addr);
33 33
34 int channel2irq(unsigned int channel) 34 int channel2irq(unsigned int channel)
35 { 35 {
36 int ret_irq = -1; 36 int ret_irq = -1;
37 37
38 switch (channel) { 38 switch (channel) {
39 case CH_PPI: 39 case CH_PPI:
40 ret_irq = IRQ_PPI; 40 ret_irq = IRQ_PPI;
41 break; 41 break;
42 42
43 case CH_EMAC_RX: 43 case CH_EMAC_RX:
44 ret_irq = IRQ_MAC_RX; 44 ret_irq = IRQ_MAC_RX;
45 break; 45 break;
46 46
47 case CH_EMAC_TX: 47 case CH_EMAC_TX:
48 ret_irq = IRQ_MAC_TX; 48 ret_irq = IRQ_MAC_TX;
49 break; 49 break;
50 50
51 case CH_UART1_RX: 51 case CH_UART1_RX:
52 ret_irq = IRQ_UART1_RX; 52 ret_irq = IRQ_UART1_RX;
53 break; 53 break;
54 54
55 case CH_UART1_TX: 55 case CH_UART1_TX:
56 ret_irq = IRQ_UART1_TX; 56 ret_irq = IRQ_UART1_TX;
57 break; 57 break;
58 58
59 case CH_SPORT0_RX: 59 case CH_SPORT0_RX:
60 ret_irq = IRQ_SPORT0_RX; 60 ret_irq = IRQ_SPORT0_RX;
61 break; 61 break;
62 62
63 case CH_SPORT0_TX: 63 case CH_SPORT0_TX:
64 ret_irq = IRQ_SPORT0_TX; 64 ret_irq = IRQ_SPORT0_TX;
65 break; 65 break;
66 66
67 case CH_SPORT1_RX: 67 case CH_SPORT1_RX:
68 ret_irq = IRQ_SPORT1_RX; 68 ret_irq = IRQ_SPORT1_RX;
69 break; 69 break;
70 70
71 case CH_SPORT1_TX: 71 case CH_SPORT1_TX:
72 ret_irq = IRQ_SPORT1_TX; 72 ret_irq = IRQ_SPORT1_TX;
73 break; 73 break;
74 74
75 case CH_SPI: 75 case CH_SPI:
76 ret_irq = IRQ_SPI; 76 ret_irq = IRQ_SPI;
77 break; 77 break;
78 78
79 case CH_UART0_RX: 79 case CH_UART0_RX:
80 ret_irq = IRQ_UART0_RX; 80 ret_irq = IRQ_UART0_RX;
81 break; 81 break;
82 82
83 case CH_UART0_TX: 83 case CH_UART0_TX:
84 ret_irq = IRQ_UART0_TX; 84 ret_irq = IRQ_UART0_TX;
85 break; 85 break;
86 86
87 case CH_MEM_STREAM0_SRC: 87 case CH_MEM_STREAM0_SRC:
88 case CH_MEM_STREAM0_DEST: 88 case CH_MEM_STREAM0_DEST:
89 ret_irq = IRQ_MEM_DMA0; 89 ret_irq = IRQ_MEM_DMA0;
90 break; 90 break;
91 91
92 case CH_MEM_STREAM1_SRC: 92 case CH_MEM_STREAM1_SRC:
93 case CH_MEM_STREAM1_DEST: 93 case CH_MEM_STREAM1_DEST:
94 ret_irq = IRQ_MEM_DMA1; 94 ret_irq = IRQ_MEM_DMA1;
95 break; 95 break;
96 } 96 }
97 return ret_irq; 97 return ret_irq;
98 } 98 }
99 99
arch/blackfin/mach-bf538/dma.c
Diff comments   View file @ 5e3bcf3
1 /* 1 /*
2 * the simple DMA Implementation for Blackfin 2 * the simple DMA Implementation for Blackfin
3 * 3 *
4 * Copyright 2008 Analog Devices Inc. 4 * Copyright 2008 Analog Devices Inc.
5 * 5 *
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
9 #include <linux/module.h> 9 #include <linux/module.h>
10 10
11 #include <asm/blackfin.h> 11 #include <asm/blackfin.h>
12 #include <asm/dma.h> 12 #include <asm/dma.h>
13 13
14 struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { 14 struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
15 (struct dma_register *) DMA0_NEXT_DESC_PTR, 15 (struct dma_register *) DMA0_NEXT_DESC_PTR,
16 (struct dma_register *) DMA1_NEXT_DESC_PTR, 16 (struct dma_register *) DMA1_NEXT_DESC_PTR,
17 (struct dma_register *) DMA2_NEXT_DESC_PTR, 17 (struct dma_register *) DMA2_NEXT_DESC_PTR,
18 (struct dma_register *) DMA3_NEXT_DESC_PTR, 18 (struct dma_register *) DMA3_NEXT_DESC_PTR,
19 (struct dma_register *) DMA4_NEXT_DESC_PTR, 19 (struct dma_register *) DMA4_NEXT_DESC_PTR,
20 (struct dma_register *) DMA5_NEXT_DESC_PTR, 20 (struct dma_register *) DMA5_NEXT_DESC_PTR,
21 (struct dma_register *) DMA6_NEXT_DESC_PTR, 21 (struct dma_register *) DMA6_NEXT_DESC_PTR,
22 (struct dma_register *) DMA7_NEXT_DESC_PTR, 22 (struct dma_register *) DMA7_NEXT_DESC_PTR,
23 (struct dma_register *) DMA8_NEXT_DESC_PTR, 23 (struct dma_register *) DMA8_NEXT_DESC_PTR,
24 (struct dma_register *) DMA9_NEXT_DESC_PTR, 24 (struct dma_register *) DMA9_NEXT_DESC_PTR,
25 (struct dma_register *) DMA10_NEXT_DESC_PTR, 25 (struct dma_register *) DMA10_NEXT_DESC_PTR,
26 (struct dma_register *) DMA11_NEXT_DESC_PTR, 26 (struct dma_register *) DMA11_NEXT_DESC_PTR,
27 (struct dma_register *) DMA12_NEXT_DESC_PTR, 27 (struct dma_register *) DMA12_NEXT_DESC_PTR,
28 (struct dma_register *) DMA13_NEXT_DESC_PTR, 28 (struct dma_register *) DMA13_NEXT_DESC_PTR,
29 (struct dma_register *) DMA14_NEXT_DESC_PTR, 29 (struct dma_register *) DMA14_NEXT_DESC_PTR,
30 (struct dma_register *) DMA15_NEXT_DESC_PTR, 30 (struct dma_register *) DMA15_NEXT_DESC_PTR,
31 (struct dma_register *) DMA16_NEXT_DESC_PTR, 31 (struct dma_register *) DMA16_NEXT_DESC_PTR,
32 (struct dma_register *) DMA17_NEXT_DESC_PTR, 32 (struct dma_register *) DMA17_NEXT_DESC_PTR,
33 (struct dma_register *) DMA18_NEXT_DESC_PTR, 33 (struct dma_register *) DMA18_NEXT_DESC_PTR,
34 (struct dma_register *) DMA19_NEXT_DESC_PTR, 34 (struct dma_register *) DMA19_NEXT_DESC_PTR,
35 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR, 35 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
36 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR, 36 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
37 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, 37 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
38 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, 38 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
39 (struct dma_register *) MDMA_D2_NEXT_DESC_PTR, 39 (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
40 (struct dma_register *) MDMA_S2_NEXT_DESC_PTR, 40 (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
41 (struct dma_register *) MDMA_D3_NEXT_DESC_PTR, 41 (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
42 (struct dma_register *) MDMA_S3_NEXT_DESC_PTR, 42 (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
43 }; 43 };
44 EXPORT_SYMBOL(dma_io_base_addr); 44 EXPORT_SYMBOL(dma_io_base_addr);
45 45
46 int channel2irq(unsigned int channel) 46 int channel2irq(unsigned int channel)
47 { 47 {
48 int ret_irq = -1; 48 int ret_irq = -1;
49 49
50 switch (channel) { 50 switch (channel) {
51 case CH_PPI: 51 case CH_PPI:
52 ret_irq = IRQ_PPI; 52 ret_irq = IRQ_PPI;
53 break; 53 break;
54 54
55 case CH_UART0_RX: 55 case CH_UART0_RX:
56 ret_irq = IRQ_UART0_RX; 56 ret_irq = IRQ_UART0_RX;
57 break; 57 break;
58 58
59 case CH_UART0_TX: 59 case CH_UART0_TX:
60 ret_irq = IRQ_UART0_TX; 60 ret_irq = IRQ_UART0_TX;
61 break; 61 break;
62 62
63 case CH_UART1_RX: 63 case CH_UART1_RX:
64 ret_irq = IRQ_UART1_RX; 64 ret_irq = IRQ_UART1_RX;
65 break; 65 break;
66 66
67 case CH_UART1_TX: 67 case CH_UART1_TX:
68 ret_irq = IRQ_UART1_TX; 68 ret_irq = IRQ_UART1_TX;
69 break; 69 break;
70 70
71 case CH_UART2_RX: 71 case CH_UART2_RX:
72 ret_irq = IRQ_UART2_RX; 72 ret_irq = IRQ_UART2_RX;
73 break; 73 break;
74 74
75 case CH_UART2_TX: 75 case CH_UART2_TX:
76 ret_irq = IRQ_UART2_TX; 76 ret_irq = IRQ_UART2_TX;
77 break; 77 break;
78 78
79 case CH_SPORT0_RX: 79 case CH_SPORT0_RX:
80 ret_irq = IRQ_SPORT0_RX; 80 ret_irq = IRQ_SPORT0_RX;
81 break; 81 break;
82 82
83 case CH_SPORT0_TX: 83 case CH_SPORT0_TX:
84 ret_irq = IRQ_SPORT0_TX; 84 ret_irq = IRQ_SPORT0_TX;
85 break; 85 break;
86 86
87 case CH_SPORT1_RX: 87 case CH_SPORT1_RX:
88 ret_irq = IRQ_SPORT1_RX; 88 ret_irq = IRQ_SPORT1_RX;
89 break; 89 break;
90 90
91 case CH_SPORT1_TX: 91 case CH_SPORT1_TX:
92 ret_irq = IRQ_SPORT1_TX; 92 ret_irq = IRQ_SPORT1_TX;
93 break; 93 break;
94 94
95 case CH_SPORT2_RX: 95 case CH_SPORT2_RX:
96 ret_irq = IRQ_SPORT2_RX; 96 ret_irq = IRQ_SPORT2_RX;
97 break; 97 break;
98 98
99 case CH_SPORT2_TX: 99 case CH_SPORT2_TX:
100 ret_irq = IRQ_SPORT2_TX; 100 ret_irq = IRQ_SPORT2_TX;
101 break; 101 break;
102 102
103 case CH_SPORT3_RX: 103 case CH_SPORT3_RX:
104 ret_irq = IRQ_SPORT3_RX; 104 ret_irq = IRQ_SPORT3_RX;
105 break; 105 break;
106 106
107 case CH_SPORT3_TX: 107 case CH_SPORT3_TX:
108 ret_irq = IRQ_SPORT3_TX; 108 ret_irq = IRQ_SPORT3_TX;
109 break; 109 break;
110 110
111 case CH_SPI0: 111 case CH_SPI0:
112 ret_irq = IRQ_SPI0; 112 ret_irq = IRQ_SPI0;
113 break; 113 break;
114 114
115 case CH_SPI1: 115 case CH_SPI1:
116 ret_irq = IRQ_SPI1; 116 ret_irq = IRQ_SPI1;
117 break; 117 break;
118 118
119 case CH_SPI2: 119 case CH_SPI2:
120 ret_irq = IRQ_SPI2; 120 ret_irq = IRQ_SPI2;
121 break; 121 break;
122 122
123 case CH_MEM_STREAM0_SRC: 123 case CH_MEM_STREAM0_SRC:
124 case CH_MEM_STREAM0_DEST: 124 case CH_MEM_STREAM0_DEST:
125 ret_irq = IRQ_MEM0_DMA0; 125 ret_irq = IRQ_MEM0_DMA0;
126 break; 126 break;
127 case CH_MEM_STREAM1_SRC: 127 case CH_MEM_STREAM1_SRC:
128 case CH_MEM_STREAM1_DEST: 128 case CH_MEM_STREAM1_DEST:
129 ret_irq = IRQ_MEM0_DMA1; 129 ret_irq = IRQ_MEM0_DMA1;
130 break; 130 break;
131 case CH_MEM_STREAM2_SRC: 131 case CH_MEM_STREAM2_SRC:
132 case CH_MEM_STREAM2_DEST: 132 case CH_MEM_STREAM2_DEST:
133 ret_irq = IRQ_MEM1_DMA0; 133 ret_irq = IRQ_MEM1_DMA0;
134 break; 134 break;
135 case CH_MEM_STREAM3_SRC: 135 case CH_MEM_STREAM3_SRC:
136 case CH_MEM_STREAM3_DEST: 136 case CH_MEM_STREAM3_DEST:
137 ret_irq = IRQ_MEM1_DMA1; 137 ret_irq = IRQ_MEM1_DMA1;
138 break; 138 break;
139 } 139 }
140 return ret_irq; 140 return ret_irq;
141 } 141 }
142 142
arch/blackfin/mach-bf548/dma.c
Diff comments   View file @ 5e3bcf3
1 /* 1 /*
2 * the simple DMA Implementation for Blackfin 2 * the simple DMA Implementation for Blackfin
3 * 3 *
4 * Copyright 2007-2009 Analog Devices Inc. 4 * Copyright 2007-2009 Analog Devices Inc.
5 * 5 *
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
9 #include <linux/module.h> 9 #include <linux/module.h>
10 10
11 #include <asm/blackfin.h> 11 #include <asm/blackfin.h>
12 #include <asm/dma.h> 12 #include <asm/dma.h>
13 13
14 struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { 14 struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
15 (struct dma_register *) DMA0_NEXT_DESC_PTR, 15 (struct dma_register *) DMA0_NEXT_DESC_PTR,
16 (struct dma_register *) DMA1_NEXT_DESC_PTR, 16 (struct dma_register *) DMA1_NEXT_DESC_PTR,
17 (struct dma_register *) DMA2_NEXT_DESC_PTR, 17 (struct dma_register *) DMA2_NEXT_DESC_PTR,
18 (struct dma_register *) DMA3_NEXT_DESC_PTR, 18 (struct dma_register *) DMA3_NEXT_DESC_PTR,
19 (struct dma_register *) DMA4_NEXT_DESC_PTR, 19 (struct dma_register *) DMA4_NEXT_DESC_PTR,
20 (struct dma_register *) DMA5_NEXT_DESC_PTR, 20 (struct dma_register *) DMA5_NEXT_DESC_PTR,
21 (struct dma_register *) DMA6_NEXT_DESC_PTR, 21 (struct dma_register *) DMA6_NEXT_DESC_PTR,
22 (struct dma_register *) DMA7_NEXT_DESC_PTR, 22 (struct dma_register *) DMA7_NEXT_DESC_PTR,
23 (struct dma_register *) DMA8_NEXT_DESC_PTR, 23 (struct dma_register *) DMA8_NEXT_DESC_PTR,
24 (struct dma_register *) DMA9_NEXT_DESC_PTR, 24 (struct dma_register *) DMA9_NEXT_DESC_PTR,
25 (struct dma_register *) DMA10_NEXT_DESC_PTR, 25 (struct dma_register *) DMA10_NEXT_DESC_PTR,
26 (struct dma_register *) DMA11_NEXT_DESC_PTR, 26 (struct dma_register *) DMA11_NEXT_DESC_PTR,
27 (struct dma_register *) DMA12_NEXT_DESC_PTR, 27 (struct dma_register *) DMA12_NEXT_DESC_PTR,
28 (struct dma_register *) DMA13_NEXT_DESC_PTR, 28 (struct dma_register *) DMA13_NEXT_DESC_PTR,
29 (struct dma_register *) DMA14_NEXT_DESC_PTR, 29 (struct dma_register *) DMA14_NEXT_DESC_PTR,
30 (struct dma_register *) DMA15_NEXT_DESC_PTR, 30 (struct dma_register *) DMA15_NEXT_DESC_PTR,
31 (struct dma_register *) DMA16_NEXT_DESC_PTR, 31 (struct dma_register *) DMA16_NEXT_DESC_PTR,
32 (struct dma_register *) DMA17_NEXT_DESC_PTR, 32 (struct dma_register *) DMA17_NEXT_DESC_PTR,
33 (struct dma_register *) DMA18_NEXT_DESC_PTR, 33 (struct dma_register *) DMA18_NEXT_DESC_PTR,
34 (struct dma_register *) DMA19_NEXT_DESC_PTR, 34 (struct dma_register *) DMA19_NEXT_DESC_PTR,
35 (struct dma_register *) DMA20_NEXT_DESC_PTR, 35 (struct dma_register *) DMA20_NEXT_DESC_PTR,
36 (struct dma_register *) DMA21_NEXT_DESC_PTR, 36 (struct dma_register *) DMA21_NEXT_DESC_PTR,
37 (struct dma_register *) DMA22_NEXT_DESC_PTR, 37 (struct dma_register *) DMA22_NEXT_DESC_PTR,
38 (struct dma_register *) DMA23_NEXT_DESC_PTR, 38 (struct dma_register *) DMA23_NEXT_DESC_PTR,
39 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR, 39 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
40 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR, 40 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
41 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, 41 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
42 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, 42 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
43 (struct dma_register *) MDMA_D2_NEXT_DESC_PTR, 43 (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
44 (struct dma_register *) MDMA_S2_NEXT_DESC_PTR, 44 (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
45 (struct dma_register *) MDMA_D3_NEXT_DESC_PTR, 45 (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
46 (struct dma_register *) MDMA_S3_NEXT_DESC_PTR, 46 (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
47 }; 47 };
48 EXPORT_SYMBOL(dma_io_base_addr); 48 EXPORT_SYMBOL(dma_io_base_addr);
49 49
50 int channel2irq(unsigned int channel) 50 int channel2irq(unsigned int channel)
51 { 51 {
52 int ret_irq = -1; 52 int ret_irq = -1;
53 53
54 switch (channel) { 54 switch (channel) {
55 case CH_SPORT0_RX: 55 case CH_SPORT0_RX:
56 ret_irq = IRQ_SPORT0_RX; 56 ret_irq = IRQ_SPORT0_RX;
57 break; 57 break;
58 case CH_SPORT0_TX: 58 case CH_SPORT0_TX:
59 ret_irq = IRQ_SPORT0_TX; 59 ret_irq = IRQ_SPORT0_TX;
60 break; 60 break;
61 case CH_SPORT1_RX: 61 case CH_SPORT1_RX:
62 ret_irq = IRQ_SPORT1_RX; 62 ret_irq = IRQ_SPORT1_RX;
63 break; 63 break;
64 case CH_SPORT1_TX: 64 case CH_SPORT1_TX:
65 ret_irq = IRQ_SPORT1_TX; 65 ret_irq = IRQ_SPORT1_TX;
66 break; 66 break;
67 case CH_SPI0: 67 case CH_SPI0:
68 ret_irq = IRQ_SPI0; 68 ret_irq = IRQ_SPI0;
69 break; 69 break;
70 case CH_SPI1: 70 case CH_SPI1:
71 ret_irq = IRQ_SPI1; 71 ret_irq = IRQ_SPI1;
72 break; 72 break;
73 case CH_UART0_RX: 73 case CH_UART0_RX:
74 ret_irq = IRQ_UART0_RX; 74 ret_irq = IRQ_UART0_RX;
75 break; 75 break;
76 case CH_UART0_TX: 76 case CH_UART0_TX:
77 ret_irq = IRQ_UART0_TX; 77 ret_irq = IRQ_UART0_TX;
78 break; 78 break;
79 case CH_UART1_RX: 79 case CH_UART1_RX:
80 ret_irq = IRQ_UART1_RX; 80 ret_irq = IRQ_UART1_RX;
81 break; 81 break;
82 case CH_UART1_TX: 82 case CH_UART1_TX:
83 ret_irq = IRQ_UART1_TX; 83 ret_irq = IRQ_UART1_TX;
84 break; 84 break;
85 case CH_EPPI0: 85 case CH_EPPI0:
86 ret_irq = IRQ_EPPI0; 86 ret_irq = IRQ_EPPI0;
87 break; 87 break;
88 case CH_EPPI1: 88 case CH_EPPI1:
89 ret_irq = IRQ_EPPI1; 89 ret_irq = IRQ_EPPI1;
90 break; 90 break;
91 case CH_EPPI2: 91 case CH_EPPI2:
92 ret_irq = IRQ_EPPI2; 92 ret_irq = IRQ_EPPI2;
93 break; 93 break;
94 case CH_PIXC_IMAGE: 94 case CH_PIXC_IMAGE:
95 ret_irq = IRQ_PIXC_IN0; 95 ret_irq = IRQ_PIXC_IN0;
96 break; 96 break;
97 case CH_PIXC_OVERLAY: 97 case CH_PIXC_OVERLAY:
98 ret_irq = IRQ_PIXC_IN1; 98 ret_irq = IRQ_PIXC_IN1;
99 break; 99 break;
100 case CH_PIXC_OUTPUT: 100 case CH_PIXC_OUTPUT:
101 ret_irq = IRQ_PIXC_OUT; 101 ret_irq = IRQ_PIXC_OUT;
102 break; 102 break;
103 case CH_SPORT2_RX: 103 case CH_SPORT2_RX:
104 ret_irq = IRQ_SPORT2_RX; 104 ret_irq = IRQ_SPORT2_RX;
105 break; 105 break;
106 case CH_SPORT2_TX: 106 case CH_SPORT2_TX:
107 ret_irq = IRQ_SPORT2_TX; 107 ret_irq = IRQ_SPORT2_TX;
108 break; 108 break;
109 case CH_SPORT3_RX: 109 case CH_SPORT3_RX:
110 ret_irq = IRQ_SPORT3_RX; 110 ret_irq = IRQ_SPORT3_RX;
111 break; 111 break;
112 case CH_SPORT3_TX: 112 case CH_SPORT3_TX:
113 ret_irq = IRQ_SPORT3_TX; 113 ret_irq = IRQ_SPORT3_TX;
114 break; 114 break;
115 case CH_SDH: 115 case CH_SDH:
116 ret_irq = IRQ_SDH; 116 ret_irq = IRQ_SDH;
117 break; 117 break;
118 case CH_SPI2: 118 case CH_SPI2:
119 ret_irq = IRQ_SPI2; 119 ret_irq = IRQ_SPI2;
120 break; 120 break;
121 case CH_MEM_STREAM0_SRC: 121 case CH_MEM_STREAM0_SRC:
122 case CH_MEM_STREAM0_DEST: 122 case CH_MEM_STREAM0_DEST:
123 ret_irq = IRQ_MDMAS0; 123 ret_irq = IRQ_MDMAS0;
124 break; 124 break;
125 case CH_MEM_STREAM1_SRC: 125 case CH_MEM_STREAM1_SRC:
126 case CH_MEM_STREAM1_DEST: 126 case CH_MEM_STREAM1_DEST:
127 ret_irq = IRQ_MDMAS1; 127 ret_irq = IRQ_MDMAS1;
128 break; 128 break;
129 case CH_MEM_STREAM2_SRC: 129 case CH_MEM_STREAM2_SRC:
130 case CH_MEM_STREAM2_DEST: 130 case CH_MEM_STREAM2_DEST:
131 ret_irq = IRQ_MDMAS2; 131 ret_irq = IRQ_MDMAS2;
132 break; 132 break;
133 case CH_MEM_STREAM3_SRC: 133 case CH_MEM_STREAM3_SRC:
134 case CH_MEM_STREAM3_DEST: 134 case CH_MEM_STREAM3_DEST:
135 ret_irq = IRQ_MDMAS3; 135 ret_irq = IRQ_MDMAS3;
136 break; 136 break;
137 } 137 }
138 return ret_irq; 138 return ret_irq;
139 } 139 }
140 140
arch/blackfin/mach-bf561/dma.c
Diff comments   View file @ 5e3bcf3
1 /* 1 /*
2 * the simple DMA Implementation for Blackfin 2 * the simple DMA Implementation for Blackfin
3 * 3 *
4 * Copyright 2007-2008 Analog Devices Inc. 4 * Copyright 2007-2008 Analog Devices Inc.
5 * 5 *
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
9 #include <linux/module.h> 9 #include <linux/module.h>
10 10
11 #include <asm/blackfin.h> 11 #include <asm/blackfin.h>
12 #include <asm/dma.h> 12 #include <asm/dma.h>
13 13
14 struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { 14 struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
15 (struct dma_register *) DMA1_0_NEXT_DESC_PTR, 15 (struct dma_register *) DMA1_0_NEXT_DESC_PTR,
16 (struct dma_register *) DMA1_1_NEXT_DESC_PTR, 16 (struct dma_register *) DMA1_1_NEXT_DESC_PTR,
17 (struct dma_register *) DMA1_2_NEXT_DESC_PTR, 17 (struct dma_register *) DMA1_2_NEXT_DESC_PTR,
18 (struct dma_register *) DMA1_3_NEXT_DESC_PTR, 18 (struct dma_register *) DMA1_3_NEXT_DESC_PTR,
19 (struct dma_register *) DMA1_4_NEXT_DESC_PTR, 19 (struct dma_register *) DMA1_4_NEXT_DESC_PTR,
20 (struct dma_register *) DMA1_5_NEXT_DESC_PTR, 20 (struct dma_register *) DMA1_5_NEXT_DESC_PTR,
21 (struct dma_register *) DMA1_6_NEXT_DESC_PTR, 21 (struct dma_register *) DMA1_6_NEXT_DESC_PTR,
22 (struct dma_register *) DMA1_7_NEXT_DESC_PTR, 22 (struct dma_register *) DMA1_7_NEXT_DESC_PTR,
23 (struct dma_register *) DMA1_8_NEXT_DESC_PTR, 23 (struct dma_register *) DMA1_8_NEXT_DESC_PTR,
24 (struct dma_register *) DMA1_9_NEXT_DESC_PTR, 24 (struct dma_register *) DMA1_9_NEXT_DESC_PTR,
25 (struct dma_register *) DMA1_10_NEXT_DESC_PTR, 25 (struct dma_register *) DMA1_10_NEXT_DESC_PTR,
26 (struct dma_register *) DMA1_11_NEXT_DESC_PTR, 26 (struct dma_register *) DMA1_11_NEXT_DESC_PTR,
27 (struct dma_register *) DMA2_0_NEXT_DESC_PTR, 27 (struct dma_register *) DMA2_0_NEXT_DESC_PTR,
28 (struct dma_register *) DMA2_1_NEXT_DESC_PTR, 28 (struct dma_register *) DMA2_1_NEXT_DESC_PTR,
29 (struct dma_register *) DMA2_2_NEXT_DESC_PTR, 29 (struct dma_register *) DMA2_2_NEXT_DESC_PTR,
30 (struct dma_register *) DMA2_3_NEXT_DESC_PTR, 30 (struct dma_register *) DMA2_3_NEXT_DESC_PTR,
31 (struct dma_register *) DMA2_4_NEXT_DESC_PTR, 31 (struct dma_register *) DMA2_4_NEXT_DESC_PTR,
32 (struct dma_register *) DMA2_5_NEXT_DESC_PTR, 32 (struct dma_register *) DMA2_5_NEXT_DESC_PTR,
33 (struct dma_register *) DMA2_6_NEXT_DESC_PTR, 33 (struct dma_register *) DMA2_6_NEXT_DESC_PTR,
34 (struct dma_register *) DMA2_7_NEXT_DESC_PTR, 34 (struct dma_register *) DMA2_7_NEXT_DESC_PTR,
35 (struct dma_register *) DMA2_8_NEXT_DESC_PTR, 35 (struct dma_register *) DMA2_8_NEXT_DESC_PTR,
36 (struct dma_register *) DMA2_9_NEXT_DESC_PTR, 36 (struct dma_register *) DMA2_9_NEXT_DESC_PTR,
37 (struct dma_register *) DMA2_10_NEXT_DESC_PTR, 37 (struct dma_register *) DMA2_10_NEXT_DESC_PTR,
38 (struct dma_register *) DMA2_11_NEXT_DESC_PTR, 38 (struct dma_register *) DMA2_11_NEXT_DESC_PTR,
39 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR, 39 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
40 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR, 40 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
41 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, 41 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
42 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, 42 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
43 (struct dma_register *) MDMA_D2_NEXT_DESC_PTR, 43 (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
44 (struct dma_register *) MDMA_S2_NEXT_DESC_PTR, 44 (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
45 (struct dma_register *) MDMA_D3_NEXT_DESC_PTR, 45 (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
46 (struct dma_register *) MDMA_S3_NEXT_DESC_PTR, 46 (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
47 (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR, 47 (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
48 (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR, 48 (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
49 (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR, 49 (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
50 (struct dma_register *) IMDMA_S1_NEXT_DESC_PTR, 50 (struct dma_register *) IMDMA_S1_NEXT_DESC_PTR,
51 }; 51 };
52 EXPORT_SYMBOL(dma_io_base_addr); 52 EXPORT_SYMBOL(dma_io_base_addr);
53 53
54 int channel2irq(unsigned int channel) 54 int channel2irq(unsigned int channel)
55 { 55 {
56 int ret_irq = -1; 56 int ret_irq = -1;
57 57
58 switch (channel) { 58 switch (channel) {
59 case CH_PPI0: 59 case CH_PPI0:
60 ret_irq = IRQ_PPI0; 60 ret_irq = IRQ_PPI0;
61 break; 61 break;
62 case CH_PPI1: 62 case CH_PPI1:
63 ret_irq = IRQ_PPI1; 63 ret_irq = IRQ_PPI1;
64 break; 64 break;
65 case CH_SPORT0_RX: 65 case CH_SPORT0_RX:
66 ret_irq = IRQ_SPORT0_RX; 66 ret_irq = IRQ_SPORT0_RX;
67 break; 67 break;
68 case CH_SPORT0_TX: 68 case CH_SPORT0_TX:
69 ret_irq = IRQ_SPORT0_TX; 69 ret_irq = IRQ_SPORT0_TX;
70 break; 70 break;
71 case CH_SPORT1_RX: 71 case CH_SPORT1_RX:
72 ret_irq = IRQ_SPORT1_RX; 72 ret_irq = IRQ_SPORT1_RX;
73 break; 73 break;
74 case CH_SPORT1_TX: 74 case CH_SPORT1_TX:
75 ret_irq = IRQ_SPORT1_TX; 75 ret_irq = IRQ_SPORT1_TX;
76 break; 76 break;
77 case CH_SPI: 77 case CH_SPI:
78 ret_irq = IRQ_SPI; 78 ret_irq = IRQ_SPI;
79 break; 79 break;
80 case CH_UART_RX: 80 case CH_UART_RX:
81 ret_irq = IRQ_UART_RX; 81 ret_irq = IRQ_UART_RX;
82 break; 82 break;
83 case CH_UART_TX: 83 case CH_UART_TX:
84 ret_irq = IRQ_UART_TX; 84 ret_irq = IRQ_UART_TX;
85 break; 85 break;
86 86
87 case CH_MEM_STREAM0_SRC: 87 case CH_MEM_STREAM0_SRC:
88 case CH_MEM_STREAM0_DEST: 88 case CH_MEM_STREAM0_DEST:
89 ret_irq = IRQ_MEM_DMA0; 89 ret_irq = IRQ_MEM_DMA0;
90 break; 90 break;
91 case CH_MEM_STREAM1_SRC: 91 case CH_MEM_STREAM1_SRC:
92 case CH_MEM_STREAM1_DEST: 92 case CH_MEM_STREAM1_DEST:
93 ret_irq = IRQ_MEM_DMA1; 93 ret_irq = IRQ_MEM_DMA1;
94 break; 94 break;
95 case CH_MEM_STREAM2_SRC: 95 case CH_MEM_STREAM2_SRC:
96 case CH_MEM_STREAM2_DEST: 96 case CH_MEM_STREAM2_DEST:
97 ret_irq = IRQ_MEM_DMA2; 97 ret_irq = IRQ_MEM_DMA2;
98 break; 98 break;
99 case CH_MEM_STREAM3_SRC: 99 case CH_MEM_STREAM3_SRC:
100 case CH_MEM_STREAM3_DEST: 100 case CH_MEM_STREAM3_DEST:
101 ret_irq = IRQ_MEM_DMA3; 101 ret_irq = IRQ_MEM_DMA3;
102 break; 102 break;
103 103
104 case CH_IMEM_STREAM0_SRC: 104 case CH_IMEM_STREAM0_SRC:
105 case CH_IMEM_STREAM0_DEST: 105 case CH_IMEM_STREAM0_DEST:
106 ret_irq = IRQ_IMEM_DMA0; 106 ret_irq = IRQ_IMEM_DMA0;
107 break; 107 break;
108 case CH_IMEM_STREAM1_SRC: 108 case CH_IMEM_STREAM1_SRC:
109 case CH_IMEM_STREAM1_DEST: 109 case CH_IMEM_STREAM1_DEST:
110 ret_irq = IRQ_IMEM_DMA1; 110 ret_irq = IRQ_IMEM_DMA1;
111 break; 111 break;
112 } 112 }
113 return ret_irq; 113 return ret_irq;
114 } 114 }
115 115