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Commit 636752bcb5177a301d0266270661581de8624828

Authored by Daniel Kurtz
Committed by Jean Delvare
1 parent 6cad93c4bb
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

i2c-i801: Enable IRQ for SMBus transactions 

Add a new 'feature' to i2c-i801 to enable using PCI interrupts.
When the feature is enabled, then an isr is installed for the device's
PCI IRQ.

An I2C/SMBus transaction is always terminated by one of the following
interrupt sources: FAILED, BUS_ERR, DEV_ERR, or on success: INTR.

When the isr fires for one of these cases, it sets the ->status variable
and wakes up the waitq.  The waitq then saves off the status code, and
clears ->status (in preparation for some future transaction).
The SMBus controller generates an INTR irq at the end of each
transaction where INTREN was set in the HST_CNT register.

No locking is needed around accesses to priv->status since all writes to
it are serialized: it is only ever set once in the isr at the end of a
transaction, and cleared while no interrupts can occur.  In addition, the
I2C adapter lock guarantees that entire I2C transactions for a single
adapter are always serialized.

For this patch, the INTREN bit is set only for SMBus block, byte and word
transactions, but not for I2C reads or writes.  The use of the DS
(BYTE_DONE) interrupt with byte-by-byte I2C transactions is implemented in
a subsequent patch.

The interrupt feature has only been enabled for COUGARPOINT hardware.
In addition, it is disabled if SMBus is using the SMI# interrupt.

Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Jean Delvare <khali@linux-fr.org>

Showing 2 changed files with 105 additions and 7 deletions Inline Diff

Documentation/i2c/busses/i2c-i801
Diff comments   View file @ 636752b
1 Kernel driver i2c-i801 1 Kernel driver i2c-i801
2 2
3 Supported adapters: 3 Supported adapters:
4 * Intel 82801AA and 82801AB (ICH and ICH0 - part of the 4 * Intel 82801AA and 82801AB (ICH and ICH0 - part of the
5 '810' and '810E' chipsets) 5 '810' and '810E' chipsets)
6 * Intel 82801BA (ICH2 - part of the '815E' chipset) 6 * Intel 82801BA (ICH2 - part of the '815E' chipset)
7 * Intel 82801CA/CAM (ICH3) 7 * Intel 82801CA/CAM (ICH3)
8 * Intel 82801DB (ICH4) (HW PEC supported) 8 * Intel 82801DB (ICH4) (HW PEC supported)
9 * Intel 82801EB/ER (ICH5) (HW PEC supported) 9 * Intel 82801EB/ER (ICH5) (HW PEC supported)
10 * Intel 6300ESB 10 * Intel 6300ESB
11 * Intel 82801FB/FR/FW/FRW (ICH6) 11 * Intel 82801FB/FR/FW/FRW (ICH6)
12 * Intel 82801G (ICH7) 12 * Intel 82801G (ICH7)
13 * Intel 631xESB/632xESB (ESB2) 13 * Intel 631xESB/632xESB (ESB2)
14 * Intel 82801H (ICH8) 14 * Intel 82801H (ICH8)
15 * Intel 82801I (ICH9) 15 * Intel 82801I (ICH9)
16 * Intel EP80579 (Tolapai) 16 * Intel EP80579 (Tolapai)
17 * Intel 82801JI (ICH10) 17 * Intel 82801JI (ICH10)
18 * Intel 5/3400 Series (PCH) 18 * Intel 5/3400 Series (PCH)
19 * Intel 6 Series (PCH) 19 * Intel 6 Series (PCH)
20 * Intel Patsburg (PCH) 20 * Intel Patsburg (PCH)
21 * Intel DH89xxCC (PCH) 21 * Intel DH89xxCC (PCH)
22 * Intel Panther Point (PCH) 22 * Intel Panther Point (PCH)
23 * Intel Lynx Point (PCH) 23 * Intel Lynx Point (PCH)
24 Datasheets: Publicly available at the Intel website 24 Datasheets: Publicly available at the Intel website
25 25
26 On Intel Patsburg and later chipsets, both the normal host SMBus controller 26 On Intel Patsburg and later chipsets, both the normal host SMBus controller
27 and the additional 'Integrated Device Function' controllers are supported. 27 and the additional 'Integrated Device Function' controllers are supported.
28 28
29 Authors: 29 Authors:
30 Mark Studebaker <mdsxyz123@yahoo.com> 30 Mark Studebaker <mdsxyz123@yahoo.com>
31 Jean Delvare <khali@linux-fr.org> 31 Jean Delvare <khali@linux-fr.org>
32 32
33 33
34 Module Parameters 34 Module Parameters
35 ----------------- 35 -----------------
36 36
37 * disable_features (bit vector) 37 * disable_features (bit vector)
38 Disable selected features normally supported by the device. This makes it 38 Disable selected features normally supported by the device. This makes it
39 possible to work around possible driver or hardware bugs if the feature in 39 possible to work around possible driver or hardware bugs if the feature in
40 question doesn't work as intended for whatever reason. Bit values: 40 question doesn't work as intended for whatever reason. Bit values:
41 1 disable SMBus PEC 41 0x01 disable SMBus PEC
42 2 disable the block buffer 42 0x02 disable the block buffer
43 8 disable the I2C block read functionality 43 0x08 disable the I2C block read functionality
44 0x10 don't use interrupts
44 45
45 46
46 Description 47 Description
47 ----------- 48 -----------
48 49
49 The ICH (properly known as the 82801AA), ICH0 (82801AB), ICH2 (82801BA), 50 The ICH (properly known as the 82801AA), ICH0 (82801AB), ICH2 (82801BA),
50 ICH3 (82801CA/CAM) and later devices (PCH) are Intel chips that are a part of 51 ICH3 (82801CA/CAM) and later devices (PCH) are Intel chips that are a part of
51 Intel's '810' chipset for Celeron-based PCs, '810E' chipset for 52 Intel's '810' chipset for Celeron-based PCs, '810E' chipset for
52 Pentium-based PCs, '815E' chipset, and others. 53 Pentium-based PCs, '815E' chipset, and others.
53 54
54 The ICH chips contain at least SEVEN separate PCI functions in TWO logical 55 The ICH chips contain at least SEVEN separate PCI functions in TWO logical
55 PCI devices. An output of lspci will show something similar to the 56 PCI devices. An output of lspci will show something similar to the
56 following: 57 following:
57 58
58 00:1e.0 PCI bridge: Intel Corporation: Unknown device 2418 (rev 01) 59 00:1e.0 PCI bridge: Intel Corporation: Unknown device 2418 (rev 01)
59 00:1f.0 ISA bridge: Intel Corporation: Unknown device 2410 (rev 01) 60 00:1f.0 ISA bridge: Intel Corporation: Unknown device 2410 (rev 01)
60 00:1f.1 IDE interface: Intel Corporation: Unknown device 2411 (rev 01) 61 00:1f.1 IDE interface: Intel Corporation: Unknown device 2411 (rev 01)
61 00:1f.2 USB Controller: Intel Corporation: Unknown device 2412 (rev 01) 62 00:1f.2 USB Controller: Intel Corporation: Unknown device 2412 (rev 01)
62 00:1f.3 Unknown class [0c05]: Intel Corporation: Unknown device 2413 (rev 01) 63 00:1f.3 Unknown class [0c05]: Intel Corporation: Unknown device 2413 (rev 01)
63 64
64 The SMBus controller is function 3 in device 1f. Class 0c05 is SMBus Serial 65 The SMBus controller is function 3 in device 1f. Class 0c05 is SMBus Serial
65 Controller. 66 Controller.
66 67
67 The ICH chips are quite similar to Intel's PIIX4 chip, at least in the 68 The ICH chips are quite similar to Intel's PIIX4 chip, at least in the
68 SMBus controller. 69 SMBus controller.
69 70
70 71
71 Process Call Support 72 Process Call Support
72 -------------------- 73 --------------------
73 74
74 Not supported. 75 Not supported.
75 76
76 77
77 I2C Block Read Support 78 I2C Block Read Support
78 ---------------------- 79 ----------------------
79 80
80 I2C block read is supported on the 82801EB (ICH5) and later chips. 81 I2C block read is supported on the 82801EB (ICH5) and later chips.
81 82
82 83
83 SMBus 2.0 Support 84 SMBus 2.0 Support
84 ----------------- 85 -----------------
85 86
86 The 82801DB (ICH4) and later chips support several SMBus 2.0 features. 87 The 82801DB (ICH4) and later chips support several SMBus 2.0 features.
88
89
90 Interrupt Support
91 -----------------
92
93 PCI interrupt support is supported on the 82801EB (ICH5) and later chips.
87 94
88 95
89 Hidden ICH SMBus 96 Hidden ICH SMBus
90 ---------------- 97 ----------------
91 98
92 If your system has an Intel ICH south bridge, but you do NOT see the 99 If your system has an Intel ICH south bridge, but you do NOT see the
93 SMBus device at 00:1f.3 in lspci, and you can't figure out any way in the 100 SMBus device at 00:1f.3 in lspci, and you can't figure out any way in the
94 BIOS to enable it, it means it has been hidden by the BIOS code. Asus is 101 BIOS to enable it, it means it has been hidden by the BIOS code. Asus is
95 well known for first doing this on their P4B motherboard, and many other 102 well known for first doing this on their P4B motherboard, and many other
96 boards after that. Some vendor machines are affected as well. 103 boards after that. Some vendor machines are affected as well.
97 104
98 The first thing to try is the "i2c_ec" ACPI driver. It could be that the 105 The first thing to try is the "i2c_ec" ACPI driver. It could be that the
99 SMBus was hidden on purpose because it'll be driven by ACPI. If the 106 SMBus was hidden on purpose because it'll be driven by ACPI. If the
100 i2c_ec driver works for you, just forget about the i2c-i801 driver and 107 i2c_ec driver works for you, just forget about the i2c-i801 driver and
101 don't try to unhide the ICH SMBus. Even if i2c_ec doesn't work, you 108 don't try to unhide the ICH SMBus. Even if i2c_ec doesn't work, you
102 better make sure that the SMBus isn't used by the ACPI code. Try loading 109 better make sure that the SMBus isn't used by the ACPI code. Try loading
103 the "fan" and "thermal" drivers, and check in /proc/acpi/fan and 110 the "fan" and "thermal" drivers, and check in /proc/acpi/fan and
104 /proc/acpi/thermal_zone. If you find anything there, it's likely that 111 /proc/acpi/thermal_zone. If you find anything there, it's likely that
105 the ACPI is accessing the SMBus and it's safer not to unhide it. Only 112 the ACPI is accessing the SMBus and it's safer not to unhide it. Only
106 once you are certain that ACPI isn't using the SMBus, you can attempt 113 once you are certain that ACPI isn't using the SMBus, you can attempt
107 to unhide it. 114 to unhide it.
108 115
109 In order to unhide the SMBus, we need to change the value of a PCI 116 In order to unhide the SMBus, we need to change the value of a PCI
110 register before the kernel enumerates the PCI devices. This is done in 117 register before the kernel enumerates the PCI devices. This is done in
111 drivers/pci/quirks.c, where all affected boards must be listed (see 118 drivers/pci/quirks.c, where all affected boards must be listed (see
112 function asus_hides_smbus_hostbridge.) If the SMBus device is missing, 119 function asus_hides_smbus_hostbridge.) If the SMBus device is missing,
113 and you think there's something interesting on the SMBus (e.g. a 120 and you think there's something interesting on the SMBus (e.g. a
114 hardware monitoring chip), you need to add your board to the list. 121 hardware monitoring chip), you need to add your board to the list.
115 122
116 The motherboard is identified using the subvendor and subdevice IDs of the 123 The motherboard is identified using the subvendor and subdevice IDs of the
117 host bridge PCI device. Get yours with "lspci -n -v -s 00:00.0": 124 host bridge PCI device. Get yours with "lspci -n -v -s 00:00.0":
118 125
119 00:00.0 Class 0600: 8086:2570 (rev 02) 126 00:00.0 Class 0600: 8086:2570 (rev 02)
120 Subsystem: 1043:80f2 127 Subsystem: 1043:80f2
121 Flags: bus master, fast devsel, latency 0 128 Flags: bus master, fast devsel, latency 0
122 Memory at fc000000 (32-bit, prefetchable) [size=32M] 129 Memory at fc000000 (32-bit, prefetchable) [size=32M]
123 Capabilities: [e4] #09 [2106] 130 Capabilities: [e4] #09 [2106]
124 Capabilities: [a0] AGP version 3.0 131 Capabilities: [a0] AGP version 3.0
125 132
126 Here the host bridge ID is 2570 (82865G/PE/P), the subvendor ID is 1043 133 Here the host bridge ID is 2570 (82865G/PE/P), the subvendor ID is 1043
127 (Asus) and the subdevice ID is 80f2 (P4P800-X). You can find the symbolic 134 (Asus) and the subdevice ID is 80f2 (P4P800-X). You can find the symbolic
128 names for the bridge ID and the subvendor ID in include/linux/pci_ids.h, 135 names for the bridge ID and the subvendor ID in include/linux/pci_ids.h,
129 and then add a case for your subdevice ID at the right place in 136 and then add a case for your subdevice ID at the right place in
130 drivers/pci/quirks.c. Then please give it very good testing, to make sure 137 drivers/pci/quirks.c. Then please give it very good testing, to make sure
131 that the unhidden SMBus doesn't conflict with e.g. ACPI. 138 that the unhidden SMBus doesn't conflict with e.g. ACPI.
132 139
133 If it works, proves useful (i.e. there are usable chips on the SMBus) 140 If it works, proves useful (i.e. there are usable chips on the SMBus)
134 and seems safe, please submit a patch for inclusion into the kernel. 141 and seems safe, please submit a patch for inclusion into the kernel.
135 142
136 Note: There's a useful script in lm_sensors 2.10.2 and later, named 143 Note: There's a useful script in lm_sensors 2.10.2 and later, named
137 unhide_ICH_SMBus (in prog/hotplug), which uses the fakephp driver to 144 unhide_ICH_SMBus (in prog/hotplug), which uses the fakephp driver to
138 temporarily unhide the SMBus without having to patch and recompile your 145 temporarily unhide the SMBus without having to patch and recompile your
139 kernel. It's very convenient if you just want to check if there's 146 kernel. It's very convenient if you just want to check if there's
140 anything interesting on your hidden ICH SMBus. 147 anything interesting on your hidden ICH SMBus.
141 148
142 149
143 ********************** 150 **********************
144 The lm_sensors project gratefully acknowledges the support of Texas 151 The lm_sensors project gratefully acknowledges the support of Texas
145 Instruments in the initial development of this driver. 152 Instruments in the initial development of this driver.
146 153
147 The lm_sensors project gratefully acknowledges the support of Intel in the 154 The lm_sensors project gratefully acknowledges the support of Intel in the
148 development of SMBus 2.0 / ICH4 features of this driver. 155 development of SMBus 2.0 / ICH4 features of this driver.
149 156
drivers/i2c/busses/i2c-i801.c
Diff comments   View file @ 636752b
1 /* 1 /*
2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
4 <mdsxyz123@yahoo.com> 4 <mdsxyz123@yahoo.com>
5 Copyright (C) 2007 - 2012 Jean Delvare <khali@linux-fr.org> 5 Copyright (C) 2007 - 2012 Jean Delvare <khali@linux-fr.org>
6 Copyright (C) 2010 Intel Corporation, 6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org> 7 David Woodhouse <dwmw2@infradead.org>
8 8
9 This program is free software; you can redistribute it and/or modify 9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by 10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or 11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version. 12 (at your option) any later version.
13 13
14 This program is distributed in the hope that it will be useful, 14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details. 17 GNU General Public License for more details.
18 18
19 You should have received a copy of the GNU General Public License 19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software 20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */ 22 */
23 23
24 /* 24 /*
25 Supports the following Intel I/O Controller Hubs (ICH): 25 Supports the following Intel I/O Controller Hubs (ICH):
26 26
27 I/O Block I2C 27 I/O Block I2C
28 region SMBus Block proc. block 28 region SMBus Block proc. block
29 Chip name PCI ID size PEC buffer call read 29 Chip name PCI ID size PEC buffer call read
30 ---------------------------------------------------------------------- 30 ----------------------------------------------------------------------
31 82801AA (ICH) 0x2413 16 no no no no 31 82801AA (ICH) 0x2413 16 no no no no
32 82801AB (ICH0) 0x2423 16 no no no no 32 82801AB (ICH0) 0x2423 16 no no no no
33 82801BA (ICH2) 0x2443 16 no no no no 33 82801BA (ICH2) 0x2443 16 no no no no
34 82801CA (ICH3) 0x2483 32 soft no no no 34 82801CA (ICH3) 0x2483 32 soft no no no
35 82801DB (ICH4) 0x24c3 32 hard yes no no 35 82801DB (ICH4) 0x24c3 32 hard yes no no
36 82801E (ICH5) 0x24d3 32 hard yes yes yes 36 82801E (ICH5) 0x24d3 32 hard yes yes yes
37 6300ESB 0x25a4 32 hard yes yes yes 37 6300ESB 0x25a4 32 hard yes yes yes
38 82801F (ICH6) 0x266a 32 hard yes yes yes 38 82801F (ICH6) 0x266a 32 hard yes yes yes
39 6310ESB/6320ESB 0x269b 32 hard yes yes yes 39 6310ESB/6320ESB 0x269b 32 hard yes yes yes
40 82801G (ICH7) 0x27da 32 hard yes yes yes 40 82801G (ICH7) 0x27da 32 hard yes yes yes
41 82801H (ICH8) 0x283e 32 hard yes yes yes 41 82801H (ICH8) 0x283e 32 hard yes yes yes
42 82801I (ICH9) 0x2930 32 hard yes yes yes 42 82801I (ICH9) 0x2930 32 hard yes yes yes
43 EP80579 (Tolapai) 0x5032 32 hard yes yes yes 43 EP80579 (Tolapai) 0x5032 32 hard yes yes yes
44 ICH10 0x3a30 32 hard yes yes yes 44 ICH10 0x3a30 32 hard yes yes yes
45 ICH10 0x3a60 32 hard yes yes yes 45 ICH10 0x3a60 32 hard yes yes yes
46 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes 46 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
47 6 Series (PCH) 0x1c22 32 hard yes yes yes 47 6 Series (PCH) 0x1c22 32 hard yes yes yes
48 Patsburg (PCH) 0x1d22 32 hard yes yes yes 48 Patsburg (PCH) 0x1d22 32 hard yes yes yes
49 Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes 49 Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
50 Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes 50 Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
51 Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes 51 Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
52 DH89xxCC (PCH) 0x2330 32 hard yes yes yes 52 DH89xxCC (PCH) 0x2330 32 hard yes yes yes
53 Panther Point (PCH) 0x1e22 32 hard yes yes yes 53 Panther Point (PCH) 0x1e22 32 hard yes yes yes
54 Lynx Point (PCH) 0x8c22 32 hard yes yes yes 54 Lynx Point (PCH) 0x8c22 32 hard yes yes yes
55 55
56 Features supported by this driver: 56 Features supported by this driver:
57 Software PEC no 57 Software PEC no
58 Hardware PEC yes 58 Hardware PEC yes
59 Block buffer yes 59 Block buffer yes
60 Block process call transaction no 60 Block process call transaction no
61 I2C block read transaction yes (doesn't use the block buffer) 61 I2C block read transaction yes (doesn't use the block buffer)
62 Slave mode no 62 Slave mode no
63 Interrupt processing yes
63 64
64 See the file Documentation/i2c/busses/i2c-i801 for details. 65 See the file Documentation/i2c/busses/i2c-i801 for details.
65 */ 66 */
66 67
68 #include <linux/interrupt.h>
67 #include <linux/module.h> 69 #include <linux/module.h>
68 #include <linux/pci.h> 70 #include <linux/pci.h>
69 #include <linux/kernel.h> 71 #include <linux/kernel.h>
70 #include <linux/stddef.h> 72 #include <linux/stddef.h>
71 #include <linux/delay.h> 73 #include <linux/delay.h>
72 #include <linux/ioport.h> 74 #include <linux/ioport.h>
73 #include <linux/init.h> 75 #include <linux/init.h>
74 #include <linux/i2c.h> 76 #include <linux/i2c.h>
75 #include <linux/acpi.h> 77 #include <linux/acpi.h>
76 #include <linux/io.h> 78 #include <linux/io.h>
77 #include <linux/dmi.h> 79 #include <linux/dmi.h>
78 #include <linux/slab.h> 80 #include <linux/slab.h>
81 #include <linux/wait.h>
79 82
80 /* I801 SMBus address offsets */ 83 /* I801 SMBus address offsets */
81 #define SMBHSTSTS(p) (0 + (p)->smba) 84 #define SMBHSTSTS(p) (0 + (p)->smba)
82 #define SMBHSTCNT(p) (2 + (p)->smba) 85 #define SMBHSTCNT(p) (2 + (p)->smba)
83 #define SMBHSTCMD(p) (3 + (p)->smba) 86 #define SMBHSTCMD(p) (3 + (p)->smba)
84 #define SMBHSTADD(p) (4 + (p)->smba) 87 #define SMBHSTADD(p) (4 + (p)->smba)
85 #define SMBHSTDAT0(p) (5 + (p)->smba) 88 #define SMBHSTDAT0(p) (5 + (p)->smba)
86 #define SMBHSTDAT1(p) (6 + (p)->smba) 89 #define SMBHSTDAT1(p) (6 + (p)->smba)
87 #define SMBBLKDAT(p) (7 + (p)->smba) 90 #define SMBBLKDAT(p) (7 + (p)->smba)
88 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ 91 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
89 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ 92 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
90 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ 93 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
91 94
92 /* PCI Address Constants */ 95 /* PCI Address Constants */
93 #define SMBBAR 4 96 #define SMBBAR 4
97 #define SMBPCISTS 0x006
94 #define SMBHSTCFG 0x040 98 #define SMBHSTCFG 0x040
95 99
100 /* Host status bits for SMBPCISTS */
101 #define SMBPCISTS_INTS 0x08
102
96 /* Host configuration bits for SMBHSTCFG */ 103 /* Host configuration bits for SMBHSTCFG */
97 #define SMBHSTCFG_HST_EN 1 104 #define SMBHSTCFG_HST_EN 1
98 #define SMBHSTCFG_SMB_SMI_EN 2 105 #define SMBHSTCFG_SMB_SMI_EN 2
99 #define SMBHSTCFG_I2C_EN 4 106 #define SMBHSTCFG_I2C_EN 4
100 107
101 /* Auxiliary control register bits, ICH4+ only */ 108 /* Auxiliary control register bits, ICH4+ only */
102 #define SMBAUXCTL_CRC 1 109 #define SMBAUXCTL_CRC 1
103 #define SMBAUXCTL_E32B 2 110 #define SMBAUXCTL_E32B 2
104 111
105 /* Other settings */ 112 /* Other settings */
106 #define MAX_RETRIES 400 113 #define MAX_RETRIES 400
107 114
108 /* I801 command constants */ 115 /* I801 command constants */
109 #define I801_QUICK 0x00 116 #define I801_QUICK 0x00
110 #define I801_BYTE 0x04 117 #define I801_BYTE 0x04
111 #define I801_BYTE_DATA 0x08 118 #define I801_BYTE_DATA 0x08
112 #define I801_WORD_DATA 0x0C 119 #define I801_WORD_DATA 0x0C
113 #define I801_PROC_CALL 0x10 /* unimplemented */ 120 #define I801_PROC_CALL 0x10 /* unimplemented */
114 #define I801_BLOCK_DATA 0x14 121 #define I801_BLOCK_DATA 0x14
115 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 122 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
116 123
117 /* I801 Host Control register bits */ 124 /* I801 Host Control register bits */
118 #define SMBHSTCNT_INTREN 0x01 125 #define SMBHSTCNT_INTREN 0x01
119 #define SMBHSTCNT_KILL 0x02 126 #define SMBHSTCNT_KILL 0x02
120 #define SMBHSTCNT_LAST_BYTE 0x20 127 #define SMBHSTCNT_LAST_BYTE 0x20
121 #define SMBHSTCNT_START 0x40 128 #define SMBHSTCNT_START 0x40
122 #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */ 129 #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */
123 130
124 /* I801 Hosts Status register bits */ 131 /* I801 Hosts Status register bits */
125 #define SMBHSTSTS_BYTE_DONE 0x80 132 #define SMBHSTSTS_BYTE_DONE 0x80
126 #define SMBHSTSTS_INUSE_STS 0x40 133 #define SMBHSTSTS_INUSE_STS 0x40
127 #define SMBHSTSTS_SMBALERT_STS 0x20 134 #define SMBHSTSTS_SMBALERT_STS 0x20
128 #define SMBHSTSTS_FAILED 0x10 135 #define SMBHSTSTS_FAILED 0x10
129 #define SMBHSTSTS_BUS_ERR 0x08 136 #define SMBHSTSTS_BUS_ERR 0x08
130 #define SMBHSTSTS_DEV_ERR 0x04 137 #define SMBHSTSTS_DEV_ERR 0x04
131 #define SMBHSTSTS_INTR 0x02 138 #define SMBHSTSTS_INTR 0x02
132 #define SMBHSTSTS_HOST_BUSY 0x01 139 #define SMBHSTSTS_HOST_BUSY 0x01
133 140
134 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ 141 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
135 SMBHSTSTS_DEV_ERR) 142 SMBHSTSTS_DEV_ERR)
136 143
137 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ 144 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
138 STATUS_ERROR_FLAGS) 145 STATUS_ERROR_FLAGS)
139 146
140 /* Older devices have their ID defined in <linux/pci_ids.h> */ 147 /* Older devices have their ID defined in <linux/pci_ids.h> */
141 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 148 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
142 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 149 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
143 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ 150 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
144 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 151 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
145 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 152 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
146 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 153 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
147 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 154 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
148 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 155 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
149 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 156 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
150 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 157 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
151 158
152 struct i801_priv { 159 struct i801_priv {
153 struct i2c_adapter adapter; 160 struct i2c_adapter adapter;
154 unsigned long smba; 161 unsigned long smba;
155 unsigned char original_hstcfg; 162 unsigned char original_hstcfg;
156 struct pci_dev *pci_dev; 163 struct pci_dev *pci_dev;
157 unsigned int features; 164 unsigned int features;
165
166 /* isr processing */
167 wait_queue_head_t waitq;
168 u8 status;
158 }; 169 };
159 170
160 static struct pci_driver i801_driver; 171 static struct pci_driver i801_driver;
161 172
162 #define FEATURE_SMBUS_PEC (1 << 0) 173 #define FEATURE_SMBUS_PEC (1 << 0)
163 #define FEATURE_BLOCK_BUFFER (1 << 1) 174 #define FEATURE_BLOCK_BUFFER (1 << 1)
164 #define FEATURE_BLOCK_PROC (1 << 2) 175 #define FEATURE_BLOCK_PROC (1 << 2)
165 #define FEATURE_I2C_BLOCK_READ (1 << 3) 176 #define FEATURE_I2C_BLOCK_READ (1 << 3)
177 #define FEATURE_IRQ (1 << 4)
166 /* Not really a feature, but it's convenient to handle it as such */ 178 /* Not really a feature, but it's convenient to handle it as such */
167 #define FEATURE_IDF (1 << 15) 179 #define FEATURE_IDF (1 << 15)
168 180
169 static const char *i801_feature_names[] = { 181 static const char *i801_feature_names[] = {
170 "SMBus PEC", 182 "SMBus PEC",
171 "Block buffer", 183 "Block buffer",
172 "Block process call", 184 "Block process call",
173 "I2C block read", 185 "I2C block read",
186 "Interrupt",
174 }; 187 };
175 188
176 static unsigned int disable_features; 189 static unsigned int disable_features;
177 module_param(disable_features, uint, S_IRUGO | S_IWUSR); 190 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
178 MODULE_PARM_DESC(disable_features, "Disable selected driver features"); 191 MODULE_PARM_DESC(disable_features, "Disable selected driver features");
179 192
180 /* Make sure the SMBus host is ready to start transmitting. 193 /* Make sure the SMBus host is ready to start transmitting.
181 Return 0 if it is, -EBUSY if it is not. */ 194 Return 0 if it is, -EBUSY if it is not. */
182 static int i801_check_pre(struct i801_priv *priv) 195 static int i801_check_pre(struct i801_priv *priv)
183 { 196 {
184 int status; 197 int status;
185 198
186 status = inb_p(SMBHSTSTS(priv)); 199 status = inb_p(SMBHSTSTS(priv));
187 if (status & SMBHSTSTS_HOST_BUSY) { 200 if (status & SMBHSTSTS_HOST_BUSY) {
188 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); 201 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
189 return -EBUSY; 202 return -EBUSY;
190 } 203 }
191 204
192 status &= STATUS_FLAGS; 205 status &= STATUS_FLAGS;
193 if (status) { 206 if (status) {
194 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", 207 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
195 status); 208 status);
196 outb_p(status, SMBHSTSTS(priv)); 209 outb_p(status, SMBHSTSTS(priv));
197 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; 210 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
198 if (status) { 211 if (status) {
199 dev_err(&priv->pci_dev->dev, 212 dev_err(&priv->pci_dev->dev,
200 "Failed clearing status flags (%02x)\n", 213 "Failed clearing status flags (%02x)\n",
201 status); 214 status);
202 return -EBUSY; 215 return -EBUSY;
203 } 216 }
204 } 217 }
205 218
206 return 0; 219 return 0;
207 } 220 }
208 221
209 /* 222 /*
210 * Convert the status register to an error code, and clear it. 223 * Convert the status register to an error code, and clear it.
211 * Note that status only contains the bits we want to clear, not the 224 * Note that status only contains the bits we want to clear, not the
212 * actual register value. 225 * actual register value.
213 */ 226 */
214 static int i801_check_post(struct i801_priv *priv, int status) 227 static int i801_check_post(struct i801_priv *priv, int status)
215 { 228 {
216 int result = 0; 229 int result = 0;
217 230
218 /* If the SMBus is still busy, we give up */ 231 /*
232 * If the SMBus is still busy, we give up
233 * Note: This timeout condition only happens when using polling
234 * transactions. For interrupt operation, NAK/timeout is indicated by
235 * DEV_ERR.
236 */
219 if (unlikely(status < 0)) { 237 if (unlikely(status < 0)) {
220 dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); 238 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
221 /* try to stop the current command */ 239 /* try to stop the current command */
222 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); 240 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
223 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL, 241 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
224 SMBHSTCNT(priv)); 242 SMBHSTCNT(priv));
225 usleep_range(1000, 2000); 243 usleep_range(1000, 2000);
226 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL), 244 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
227 SMBHSTCNT(priv)); 245 SMBHSTCNT(priv));
228 246
229 /* Check if it worked */ 247 /* Check if it worked */
230 status = inb_p(SMBHSTSTS(priv)); 248 status = inb_p(SMBHSTSTS(priv));
231 if ((status & SMBHSTSTS_HOST_BUSY) || 249 if ((status & SMBHSTSTS_HOST_BUSY) ||
232 !(status & SMBHSTSTS_FAILED)) 250 !(status & SMBHSTSTS_FAILED))
233 dev_err(&priv->pci_dev->dev, 251 dev_err(&priv->pci_dev->dev,
234 "Failed terminating the transaction\n"); 252 "Failed terminating the transaction\n");
235 outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); 253 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
236 return -ETIMEDOUT; 254 return -ETIMEDOUT;
237 } 255 }
238 256
239 if (status & SMBHSTSTS_FAILED) { 257 if (status & SMBHSTSTS_FAILED) {
240 result = -EIO; 258 result = -EIO;
241 dev_err(&priv->pci_dev->dev, "Transaction failed\n"); 259 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
242 } 260 }
243 if (status & SMBHSTSTS_DEV_ERR) { 261 if (status & SMBHSTSTS_DEV_ERR) {
244 result = -ENXIO; 262 result = -ENXIO;
245 dev_dbg(&priv->pci_dev->dev, "No response\n"); 263 dev_dbg(&priv->pci_dev->dev, "No response\n");
246 } 264 }
247 if (status & SMBHSTSTS_BUS_ERR) { 265 if (status & SMBHSTSTS_BUS_ERR) {
248 result = -EAGAIN; 266 result = -EAGAIN;
249 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); 267 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
250 } 268 }
251 269
252 /* Clear status flags except BYTE_DONE, to be cleared by caller */ 270 /* Clear status flags except BYTE_DONE, to be cleared by caller */
253 outb_p(status, SMBHSTSTS(priv)); 271 outb_p(status, SMBHSTSTS(priv));
254 272
255 return result; 273 return result;
256 } 274 }
257 275
258 /* Wait for BUSY being cleared and either INTR or an error flag being set */ 276 /* Wait for BUSY being cleared and either INTR or an error flag being set */
259 static int i801_wait_intr(struct i801_priv *priv) 277 static int i801_wait_intr(struct i801_priv *priv)
260 { 278 {
261 int timeout = 0; 279 int timeout = 0;
262 int status; 280 int status;
263 281
264 /* We will always wait for a fraction of a second! */ 282 /* We will always wait for a fraction of a second! */
265 do { 283 do {
266 usleep_range(250, 500); 284 usleep_range(250, 500);
267 status = inb_p(SMBHSTSTS(priv)); 285 status = inb_p(SMBHSTSTS(priv));
268 } while (((status & SMBHSTSTS_HOST_BUSY) || 286 } while (((status & SMBHSTSTS_HOST_BUSY) ||
269 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && 287 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
270 (timeout++ < MAX_RETRIES)); 288 (timeout++ < MAX_RETRIES));
271 289
272 if (timeout > MAX_RETRIES) { 290 if (timeout > MAX_RETRIES) {
273 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n"); 291 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
274 return -ETIMEDOUT; 292 return -ETIMEDOUT;
275 } 293 }
276 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR); 294 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
277 } 295 }
278 296
279 /* Wait for either BYTE_DONE or an error flag being set */ 297 /* Wait for either BYTE_DONE or an error flag being set */
280 static int i801_wait_byte_done(struct i801_priv *priv) 298 static int i801_wait_byte_done(struct i801_priv *priv)
281 { 299 {
282 int timeout = 0; 300 int timeout = 0;
283 int status; 301 int status;
284 302
285 /* We will always wait for a fraction of a second! */ 303 /* We will always wait for a fraction of a second! */
286 do { 304 do {
287 usleep_range(250, 500); 305 usleep_range(250, 500);
288 status = inb_p(SMBHSTSTS(priv)); 306 status = inb_p(SMBHSTSTS(priv));
289 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && 307 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
290 (timeout++ < MAX_RETRIES)); 308 (timeout++ < MAX_RETRIES));
291 309
292 if (timeout > MAX_RETRIES) { 310 if (timeout > MAX_RETRIES) {
293 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n"); 311 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
294 return -ETIMEDOUT; 312 return -ETIMEDOUT;
295 } 313 }
296 return status & STATUS_ERROR_FLAGS; 314 return status & STATUS_ERROR_FLAGS;
297 } 315 }
298 316
299 static int i801_transaction(struct i801_priv *priv, int xact) 317 static int i801_transaction(struct i801_priv *priv, int xact)
300 { 318 {
301 int status; 319 int status;
302 int result; 320 int result;
303 321
304 result = i801_check_pre(priv); 322 result = i801_check_pre(priv);
305 if (result < 0) 323 if (result < 0)
306 return result; 324 return result;
307 325
326 if (priv->features & FEATURE_IRQ) {
327 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
328 SMBHSTCNT(priv));
329 wait_event(priv->waitq, (status = priv->status));
330 priv->status = 0;
331 return i801_check_post(priv, status);
332 }
333
308 /* the current contents of SMBHSTCNT can be overwritten, since PEC, 334 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
309 * SMBSCMD are passed in xact */ 335 * SMBSCMD are passed in xact */
310 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); 336 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
311 337
312 status = i801_wait_intr(priv); 338 status = i801_wait_intr(priv);
313 return i801_check_post(priv, status); 339 return i801_check_post(priv, status);
314 } 340 }
315 341
316 static int i801_block_transaction_by_block(struct i801_priv *priv, 342 static int i801_block_transaction_by_block(struct i801_priv *priv,
317 union i2c_smbus_data *data, 343 union i2c_smbus_data *data,
318 char read_write, int hwpec) 344 char read_write, int hwpec)
319 { 345 {
320 int i, len; 346 int i, len;
321 int status; 347 int status;
322 348
323 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 349 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
324 350
325 /* Use 32-byte buffer to process this transaction */ 351 /* Use 32-byte buffer to process this transaction */
326 if (read_write == I2C_SMBUS_WRITE) { 352 if (read_write == I2C_SMBUS_WRITE) {
327 len = data->block[0]; 353 len = data->block[0];
328 outb_p(len, SMBHSTDAT0(priv)); 354 outb_p(len, SMBHSTDAT0(priv));
329 for (i = 0; i < len; i++) 355 for (i = 0; i < len; i++)
330 outb_p(data->block[i+1], SMBBLKDAT(priv)); 356 outb_p(data->block[i+1], SMBBLKDAT(priv));
331 } 357 }
332 358
333 status = i801_transaction(priv, I801_BLOCK_DATA | 359 status = i801_transaction(priv, I801_BLOCK_DATA |
334 (hwpec ? SMBHSTCNT_PEC_EN : 0)); 360 (hwpec ? SMBHSTCNT_PEC_EN : 0));
335 if (status) 361 if (status)
336 return status; 362 return status;
337 363
338 if (read_write == I2C_SMBUS_READ) { 364 if (read_write == I2C_SMBUS_READ) {
339 len = inb_p(SMBHSTDAT0(priv)); 365 len = inb_p(SMBHSTDAT0(priv));
340 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) 366 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
341 return -EPROTO; 367 return -EPROTO;
342 368
343 data->block[0] = len; 369 data->block[0] = len;
344 for (i = 0; i < len; i++) 370 for (i = 0; i < len; i++)
345 data->block[i + 1] = inb_p(SMBBLKDAT(priv)); 371 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
346 } 372 }
347 return 0; 373 return 0;
348 } 374 }
349 375
350 /* 376 /*
377 * i801 signals transaction completion with one of these interrupts:
378 * INTR - Success
379 * DEV_ERR - Invalid command, NAK or communication timeout
380 * BUS_ERR - SMI# transaction collision
381 * FAILED - transaction was canceled due to a KILL request
382 * When any of these occur, update ->status and wake up the waitq.
383 * ->status must be cleared before kicking off the next transaction.
384 */
385 static irqreturn_t i801_isr(int irq, void *dev_id)
386 {
387 struct i801_priv *priv = dev_id;
388 u16 pcists;
389 u8 status;
390
391 /* Confirm this is our interrupt */
392 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
393 if (!(pcists & SMBPCISTS_INTS))
394 return IRQ_NONE;
395
396 status = inb_p(SMBHSTSTS(priv));
397 if (status != 0x42)
398 dev_dbg(&priv->pci_dev->dev, "irq: status = %02x\n", status);
399
400 /*
401 * Clear irq sources and report transaction result.
402 * ->status must be cleared before the next transaction is started.
403 */
404 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
405 if (status) {
406 outb_p(status, SMBHSTSTS(priv));
407 priv->status |= status;
408 wake_up(&priv->waitq);
409 }
410
411 return IRQ_HANDLED;
412 }
413
414 /*
351 * For "byte-by-byte" block transactions: 415 * For "byte-by-byte" block transactions:
352 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 416 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
353 * I2C read uses cmd=I801_I2C_BLOCK_DATA 417 * I2C read uses cmd=I801_I2C_BLOCK_DATA
354 */ 418 */
355 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 419 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
356 union i2c_smbus_data *data, 420 union i2c_smbus_data *data,
357 char read_write, int command, 421 char read_write, int command,
358 int hwpec) 422 int hwpec)
359 { 423 {
360 int i, len; 424 int i, len;
361 int smbcmd; 425 int smbcmd;
362 int status; 426 int status;
363 int result; 427 int result;
364 428
365 result = i801_check_pre(priv); 429 result = i801_check_pre(priv);
366 if (result < 0) 430 if (result < 0)
367 return result; 431 return result;
368 432
369 len = data->block[0]; 433 len = data->block[0];
370 434
371 if (read_write == I2C_SMBUS_WRITE) { 435 if (read_write == I2C_SMBUS_WRITE) {
372 outb_p(len, SMBHSTDAT0(priv)); 436 outb_p(len, SMBHSTDAT0(priv));
373 outb_p(data->block[1], SMBBLKDAT(priv)); 437 outb_p(data->block[1], SMBBLKDAT(priv));
374 } 438 }
375 439
376 if (command == I2C_SMBUS_I2C_BLOCK_DATA && 440 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
377 read_write == I2C_SMBUS_READ) 441 read_write == I2C_SMBUS_READ)
378 smbcmd = I801_I2C_BLOCK_DATA; 442 smbcmd = I801_I2C_BLOCK_DATA;
379 else 443 else
380 smbcmd = I801_BLOCK_DATA; 444 smbcmd = I801_BLOCK_DATA;
381 445
382 for (i = 1; i <= len; i++) { 446 for (i = 1; i <= len; i++) {
383 if (i == len && read_write == I2C_SMBUS_READ) 447 if (i == len && read_write == I2C_SMBUS_READ)
384 smbcmd |= SMBHSTCNT_LAST_BYTE; 448 smbcmd |= SMBHSTCNT_LAST_BYTE;
385 outb_p(smbcmd, SMBHSTCNT(priv)); 449 outb_p(smbcmd, SMBHSTCNT(priv));
386 450
387 if (i == 1) 451 if (i == 1)
388 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, 452 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
389 SMBHSTCNT(priv)); 453 SMBHSTCNT(priv));
390 454
391 status = i801_wait_byte_done(priv); 455 status = i801_wait_byte_done(priv);
392 if (status) 456 if (status)
393 goto exit; 457 goto exit;
394 458
395 if (i == 1 && read_write == I2C_SMBUS_READ 459 if (i == 1 && read_write == I2C_SMBUS_READ
396 && command != I2C_SMBUS_I2C_BLOCK_DATA) { 460 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
397 len = inb_p(SMBHSTDAT0(priv)); 461 len = inb_p(SMBHSTDAT0(priv));
398 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 462 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
399 dev_err(&priv->pci_dev->dev, 463 dev_err(&priv->pci_dev->dev,
400 "Illegal SMBus block read size %d\n", 464 "Illegal SMBus block read size %d\n",
401 len); 465 len);
402 /* Recover */ 466 /* Recover */
403 while (inb_p(SMBHSTSTS(priv)) & 467 while (inb_p(SMBHSTSTS(priv)) &
404 SMBHSTSTS_HOST_BUSY) 468 SMBHSTSTS_HOST_BUSY)
405 outb_p(SMBHSTSTS_BYTE_DONE, 469 outb_p(SMBHSTSTS_BYTE_DONE,
406 SMBHSTSTS(priv)); 470 SMBHSTSTS(priv));
407 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); 471 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
408 return -EPROTO; 472 return -EPROTO;
409 } 473 }
410 data->block[0] = len; 474 data->block[0] = len;
411 } 475 }
412 476
413 /* Retrieve/store value in SMBBLKDAT */ 477 /* Retrieve/store value in SMBBLKDAT */
414 if (read_write == I2C_SMBUS_READ) 478 if (read_write == I2C_SMBUS_READ)
415 data->block[i] = inb_p(SMBBLKDAT(priv)); 479 data->block[i] = inb_p(SMBBLKDAT(priv));
416 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 480 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
417 outb_p(data->block[i+1], SMBBLKDAT(priv)); 481 outb_p(data->block[i+1], SMBBLKDAT(priv));
418 482
419 /* signals SMBBLKDAT ready */ 483 /* signals SMBBLKDAT ready */
420 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 484 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
421 } 485 }
422 486
423 status = i801_wait_intr(priv); 487 status = i801_wait_intr(priv);
424 exit: 488 exit:
425 return i801_check_post(priv, status); 489 return i801_check_post(priv, status);
426 } 490 }
427 491
428 static int i801_set_block_buffer_mode(struct i801_priv *priv) 492 static int i801_set_block_buffer_mode(struct i801_priv *priv)
429 { 493 {
430 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); 494 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
431 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) 495 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
432 return -EIO; 496 return -EIO;
433 return 0; 497 return 0;
434 } 498 }
435 499
436 /* Block transaction function */ 500 /* Block transaction function */
437 static int i801_block_transaction(struct i801_priv *priv, 501 static int i801_block_transaction(struct i801_priv *priv,
438 union i2c_smbus_data *data, char read_write, 502 union i2c_smbus_data *data, char read_write,
439 int command, int hwpec) 503 int command, int hwpec)
440 { 504 {
441 int result = 0; 505 int result = 0;
442 unsigned char hostc; 506 unsigned char hostc;
443 507
444 if (command == I2C_SMBUS_I2C_BLOCK_DATA) { 508 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
445 if (read_write == I2C_SMBUS_WRITE) { 509 if (read_write == I2C_SMBUS_WRITE) {
446 /* set I2C_EN bit in configuration register */ 510 /* set I2C_EN bit in configuration register */
447 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); 511 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
448 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, 512 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
449 hostc | SMBHSTCFG_I2C_EN); 513 hostc | SMBHSTCFG_I2C_EN);
450 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { 514 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
451 dev_err(&priv->pci_dev->dev, 515 dev_err(&priv->pci_dev->dev,
452 "I2C block read is unsupported!\n"); 516 "I2C block read is unsupported!\n");
453 return -EOPNOTSUPP; 517 return -EOPNOTSUPP;
454 } 518 }
455 } 519 }
456 520
457 if (read_write == I2C_SMBUS_WRITE 521 if (read_write == I2C_SMBUS_WRITE
458 || command == I2C_SMBUS_I2C_BLOCK_DATA) { 522 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
459 if (data->block[0] < 1) 523 if (data->block[0] < 1)
460 data->block[0] = 1; 524 data->block[0] = 1;
461 if (data->block[0] > I2C_SMBUS_BLOCK_MAX) 525 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
462 data->block[0] = I2C_SMBUS_BLOCK_MAX; 526 data->block[0] = I2C_SMBUS_BLOCK_MAX;
463 } else { 527 } else {
464 data->block[0] = 32; /* max for SMBus block reads */ 528 data->block[0] = 32; /* max for SMBus block reads */
465 } 529 }
466 530
467 /* Experience has shown that the block buffer can only be used for 531 /* Experience has shown that the block buffer can only be used for
468 SMBus (not I2C) block transactions, even though the datasheet 532 SMBus (not I2C) block transactions, even though the datasheet
469 doesn't mention this limitation. */ 533 doesn't mention this limitation. */
470 if ((priv->features & FEATURE_BLOCK_BUFFER) 534 if ((priv->features & FEATURE_BLOCK_BUFFER)
471 && command != I2C_SMBUS_I2C_BLOCK_DATA 535 && command != I2C_SMBUS_I2C_BLOCK_DATA
472 && i801_set_block_buffer_mode(priv) == 0) 536 && i801_set_block_buffer_mode(priv) == 0)
473 result = i801_block_transaction_by_block(priv, data, 537 result = i801_block_transaction_by_block(priv, data,
474 read_write, hwpec); 538 read_write, hwpec);
475 else 539 else
476 result = i801_block_transaction_byte_by_byte(priv, data, 540 result = i801_block_transaction_byte_by_byte(priv, data,
477 read_write, 541 read_write,
478 command, hwpec); 542 command, hwpec);
479 543
480 if (command == I2C_SMBUS_I2C_BLOCK_DATA 544 if (command == I2C_SMBUS_I2C_BLOCK_DATA
481 && read_write == I2C_SMBUS_WRITE) { 545 && read_write == I2C_SMBUS_WRITE) {
482 /* restore saved configuration register value */ 546 /* restore saved configuration register value */
483 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); 547 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
484 } 548 }
485 return result; 549 return result;
486 } 550 }
487 551
488 /* Return negative errno on error. */ 552 /* Return negative errno on error. */
489 static s32 i801_access(struct i2c_adapter *adap, u16 addr, 553 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
490 unsigned short flags, char read_write, u8 command, 554 unsigned short flags, char read_write, u8 command,
491 int size, union i2c_smbus_data *data) 555 int size, union i2c_smbus_data *data)
492 { 556 {
493 int hwpec; 557 int hwpec;
494 int block = 0; 558 int block = 0;
495 int ret, xact = 0; 559 int ret, xact = 0;
496 struct i801_priv *priv = i2c_get_adapdata(adap); 560 struct i801_priv *priv = i2c_get_adapdata(adap);
497 561
498 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) 562 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
499 && size != I2C_SMBUS_QUICK 563 && size != I2C_SMBUS_QUICK
500 && size != I2C_SMBUS_I2C_BLOCK_DATA; 564 && size != I2C_SMBUS_I2C_BLOCK_DATA;
501 565
502 switch (size) { 566 switch (size) {
503 case I2C_SMBUS_QUICK: 567 case I2C_SMBUS_QUICK:
504 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 568 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
505 SMBHSTADD(priv)); 569 SMBHSTADD(priv));
506 xact = I801_QUICK; 570 xact = I801_QUICK;
507 break; 571 break;
508 case I2C_SMBUS_BYTE: 572 case I2C_SMBUS_BYTE:
509 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 573 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
510 SMBHSTADD(priv)); 574 SMBHSTADD(priv));
511 if (read_write == I2C_SMBUS_WRITE) 575 if (read_write == I2C_SMBUS_WRITE)
512 outb_p(command, SMBHSTCMD(priv)); 576 outb_p(command, SMBHSTCMD(priv));
513 xact = I801_BYTE; 577 xact = I801_BYTE;
514 break; 578 break;
515 case I2C_SMBUS_BYTE_DATA: 579 case I2C_SMBUS_BYTE_DATA:
516 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 580 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
517 SMBHSTADD(priv)); 581 SMBHSTADD(priv));
518 outb_p(command, SMBHSTCMD(priv)); 582 outb_p(command, SMBHSTCMD(priv));
519 if (read_write == I2C_SMBUS_WRITE) 583 if (read_write == I2C_SMBUS_WRITE)
520 outb_p(data->byte, SMBHSTDAT0(priv)); 584 outb_p(data->byte, SMBHSTDAT0(priv));
521 xact = I801_BYTE_DATA; 585 xact = I801_BYTE_DATA;
522 break; 586 break;
523 case I2C_SMBUS_WORD_DATA: 587 case I2C_SMBUS_WORD_DATA:
524 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 588 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
525 SMBHSTADD(priv)); 589 SMBHSTADD(priv));
526 outb_p(command, SMBHSTCMD(priv)); 590 outb_p(command, SMBHSTCMD(priv));
527 if (read_write == I2C_SMBUS_WRITE) { 591 if (read_write == I2C_SMBUS_WRITE) {
528 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 592 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
529 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 593 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
530 } 594 }
531 xact = I801_WORD_DATA; 595 xact = I801_WORD_DATA;
532 break; 596 break;
533 case I2C_SMBUS_BLOCK_DATA: 597 case I2C_SMBUS_BLOCK_DATA:
534 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 598 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
535 SMBHSTADD(priv)); 599 SMBHSTADD(priv));
536 outb_p(command, SMBHSTCMD(priv)); 600 outb_p(command, SMBHSTCMD(priv));
537 block = 1; 601 block = 1;
538 break; 602 break;
539 case I2C_SMBUS_I2C_BLOCK_DATA: 603 case I2C_SMBUS_I2C_BLOCK_DATA:
540 /* NB: page 240 of ICH5 datasheet shows that the R/#W 604 /* NB: page 240 of ICH5 datasheet shows that the R/#W
541 * bit should be cleared here, even when reading */ 605 * bit should be cleared here, even when reading */
542 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); 606 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
543 if (read_write == I2C_SMBUS_READ) { 607 if (read_write == I2C_SMBUS_READ) {
544 /* NB: page 240 of ICH5 datasheet also shows 608 /* NB: page 240 of ICH5 datasheet also shows
545 * that DATA1 is the cmd field when reading */ 609 * that DATA1 is the cmd field when reading */
546 outb_p(command, SMBHSTDAT1(priv)); 610 outb_p(command, SMBHSTDAT1(priv));
547 } else 611 } else
548 outb_p(command, SMBHSTCMD(priv)); 612 outb_p(command, SMBHSTCMD(priv));
549 block = 1; 613 block = 1;
550 break; 614 break;
551 default: 615 default:
552 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", 616 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
553 size); 617 size);
554 return -EOPNOTSUPP; 618 return -EOPNOTSUPP;
555 } 619 }
556 620
557 if (hwpec) /* enable/disable hardware PEC */ 621 if (hwpec) /* enable/disable hardware PEC */
558 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); 622 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
559 else 623 else
560 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), 624 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
561 SMBAUXCTL(priv)); 625 SMBAUXCTL(priv));
562 626
563 if (block) 627 if (block)
564 ret = i801_block_transaction(priv, data, read_write, size, 628 ret = i801_block_transaction(priv, data, read_write, size,
565 hwpec); 629 hwpec);
566 else 630 else
567 ret = i801_transaction(priv, xact); 631 ret = i801_transaction(priv, xact);
568 632
569 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 633 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
570 time, so we forcibly disable it after every transaction. Turn off 634 time, so we forcibly disable it after every transaction. Turn off
571 E32B for the same reason. */ 635 E32B for the same reason. */
572 if (hwpec || block) 636 if (hwpec || block)
573 outb_p(inb_p(SMBAUXCTL(priv)) & 637 outb_p(inb_p(SMBAUXCTL(priv)) &
574 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 638 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
575 639
576 if (block) 640 if (block)
577 return ret; 641 return ret;
578 if (ret) 642 if (ret)
579 return ret; 643 return ret;
580 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) 644 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
581 return 0; 645 return 0;
582 646
583 switch (xact & 0x7f) { 647 switch (xact & 0x7f) {
584 case I801_BYTE: /* Result put in SMBHSTDAT0 */ 648 case I801_BYTE: /* Result put in SMBHSTDAT0 */
585 case I801_BYTE_DATA: 649 case I801_BYTE_DATA:
586 data->byte = inb_p(SMBHSTDAT0(priv)); 650 data->byte = inb_p(SMBHSTDAT0(priv));
587 break; 651 break;
588 case I801_WORD_DATA: 652 case I801_WORD_DATA:
589 data->word = inb_p(SMBHSTDAT0(priv)) + 653 data->word = inb_p(SMBHSTDAT0(priv)) +
590 (inb_p(SMBHSTDAT1(priv)) << 8); 654 (inb_p(SMBHSTDAT1(priv)) << 8);
591 break; 655 break;
592 } 656 }
593 return 0; 657 return 0;
594 } 658 }
595 659
596 660
597 static u32 i801_func(struct i2c_adapter *adapter) 661 static u32 i801_func(struct i2c_adapter *adapter)
598 { 662 {
599 struct i801_priv *priv = i2c_get_adapdata(adapter); 663 struct i801_priv *priv = i2c_get_adapdata(adapter);
600 664
601 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 665 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
602 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 666 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
603 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | 667 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
604 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | 668 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
605 ((priv->features & FEATURE_I2C_BLOCK_READ) ? 669 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
606 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0); 670 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
607 } 671 }
608 672
609 static const struct i2c_algorithm smbus_algorithm = { 673 static const struct i2c_algorithm smbus_algorithm = {
610 .smbus_xfer = i801_access, 674 .smbus_xfer = i801_access,
611 .functionality = i801_func, 675 .functionality = i801_func,
612 }; 676 };
613 677
614 static DEFINE_PCI_DEVICE_TABLE(i801_ids) = { 678 static DEFINE_PCI_DEVICE_TABLE(i801_ids) = {
615 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, 679 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
616 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, 680 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
617 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, 681 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
618 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, 682 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
619 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, 683 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
620 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, 684 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
621 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, 685 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
622 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, 686 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
623 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, 687 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
624 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, 688 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
625 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, 689 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
626 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, 690 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
627 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, 691 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
628 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, 692 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
629 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, 693 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
630 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, 694 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
631 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, 695 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
632 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, 696 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
633 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, 697 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
634 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, 698 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
635 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, 699 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
636 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, 700 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
637 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, 701 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
638 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, 702 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
639 { 0, } 703 { 0, }
640 }; 704 };
641 705
642 MODULE_DEVICE_TABLE(pci, i801_ids); 706 MODULE_DEVICE_TABLE(pci, i801_ids);
643 707
644 #if defined CONFIG_X86 && defined CONFIG_DMI 708 #if defined CONFIG_X86 && defined CONFIG_DMI
645 static unsigned char apanel_addr; 709 static unsigned char apanel_addr;
646 710
647 /* Scan the system ROM for the signature "FJKEYINF" */ 711 /* Scan the system ROM for the signature "FJKEYINF" */
648 static __init const void __iomem *bios_signature(const void __iomem *bios) 712 static __init const void __iomem *bios_signature(const void __iomem *bios)
649 { 713 {
650 ssize_t offset; 714 ssize_t offset;
651 const unsigned char signature[] = "FJKEYINF"; 715 const unsigned char signature[] = "FJKEYINF";
652 716
653 for (offset = 0; offset < 0x10000; offset += 0x10) { 717 for (offset = 0; offset < 0x10000; offset += 0x10) {
654 if (check_signature(bios + offset, signature, 718 if (check_signature(bios + offset, signature,
655 sizeof(signature)-1)) 719 sizeof(signature)-1))
656 return bios + offset; 720 return bios + offset;
657 } 721 }
658 return NULL; 722 return NULL;
659 } 723 }
660 724
661 static void __init input_apanel_init(void) 725 static void __init input_apanel_init(void)
662 { 726 {
663 void __iomem *bios; 727 void __iomem *bios;
664 const void __iomem *p; 728 const void __iomem *p;
665 729
666 bios = ioremap(0xF0000, 0x10000); /* Can't fail */ 730 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
667 p = bios_signature(bios); 731 p = bios_signature(bios);
668 if (p) { 732 if (p) {
669 /* just use the first address */ 733 /* just use the first address */
670 apanel_addr = readb(p + 8 + 3) >> 1; 734 apanel_addr = readb(p + 8 + 3) >> 1;
671 } 735 }
672 iounmap(bios); 736 iounmap(bios);
673 } 737 }
674 738
675 struct dmi_onboard_device_info { 739 struct dmi_onboard_device_info {
676 const char *name; 740 const char *name;
677 u8 type; 741 u8 type;
678 unsigned short i2c_addr; 742 unsigned short i2c_addr;
679 const char *i2c_type; 743 const char *i2c_type;
680 }; 744 };
681 745
682 static struct dmi_onboard_device_info __devinitdata dmi_devices[] = { 746 static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
683 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, 747 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
684 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, 748 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
685 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, 749 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
686 }; 750 };
687 751
688 static void __devinit dmi_check_onboard_device(u8 type, const char *name, 752 static void __devinit dmi_check_onboard_device(u8 type, const char *name,
689 struct i2c_adapter *adap) 753 struct i2c_adapter *adap)
690 { 754 {
691 int i; 755 int i;
692 struct i2c_board_info info; 756 struct i2c_board_info info;
693 757
694 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { 758 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
695 /* & ~0x80, ignore enabled/disabled bit */ 759 /* & ~0x80, ignore enabled/disabled bit */
696 if ((type & ~0x80) != dmi_devices[i].type) 760 if ((type & ~0x80) != dmi_devices[i].type)
697 continue; 761 continue;
698 if (strcasecmp(name, dmi_devices[i].name)) 762 if (strcasecmp(name, dmi_devices[i].name))
699 continue; 763 continue;
700 764
701 memset(&info, 0, sizeof(struct i2c_board_info)); 765 memset(&info, 0, sizeof(struct i2c_board_info));
702 info.addr = dmi_devices[i].i2c_addr; 766 info.addr = dmi_devices[i].i2c_addr;
703 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); 767 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
704 i2c_new_device(adap, &info); 768 i2c_new_device(adap, &info);
705 break; 769 break;
706 } 770 }
707 } 771 }
708 772
709 /* We use our own function to check for onboard devices instead of 773 /* We use our own function to check for onboard devices instead of
710 dmi_find_device() as some buggy BIOS's have the devices we are interested 774 dmi_find_device() as some buggy BIOS's have the devices we are interested
711 in marked as disabled */ 775 in marked as disabled */
712 static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm, 776 static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
713 void *adap) 777 void *adap)
714 { 778 {
715 int i, count; 779 int i, count;
716 780
717 if (dm->type != 10) 781 if (dm->type != 10)
718 return; 782 return;
719 783
720 count = (dm->length - sizeof(struct dmi_header)) / 2; 784 count = (dm->length - sizeof(struct dmi_header)) / 2;
721 for (i = 0; i < count; i++) { 785 for (i = 0; i < count; i++) {
722 const u8 *d = (char *)(dm + 1) + (i * 2); 786 const u8 *d = (char *)(dm + 1) + (i * 2);
723 const char *name = ((char *) dm) + dm->length; 787 const char *name = ((char *) dm) + dm->length;
724 u8 type = d[0]; 788 u8 type = d[0];
725 u8 s = d[1]; 789 u8 s = d[1];
726 790
727 if (!s) 791 if (!s)
728 continue; 792 continue;
729 s--; 793 s--;
730 while (s > 0 && name[0]) { 794 while (s > 0 && name[0]) {
731 name += strlen(name) + 1; 795 name += strlen(name) + 1;
732 s--; 796 s--;
733 } 797 }
734 if (name[0] == 0) /* Bogus string reference */ 798 if (name[0] == 0) /* Bogus string reference */
735 continue; 799 continue;
736 800
737 dmi_check_onboard_device(type, name, adap); 801 dmi_check_onboard_device(type, name, adap);
738 } 802 }
739 } 803 }
740 804
741 /* Register optional slaves */ 805 /* Register optional slaves */
742 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) 806 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv)
743 { 807 {
744 /* Only register slaves on main SMBus channel */ 808 /* Only register slaves on main SMBus channel */
745 if (priv->features & FEATURE_IDF) 809 if (priv->features & FEATURE_IDF)
746 return; 810 return;
747 811
748 if (apanel_addr) { 812 if (apanel_addr) {
749 struct i2c_board_info info; 813 struct i2c_board_info info;
750 814
751 memset(&info, 0, sizeof(struct i2c_board_info)); 815 memset(&info, 0, sizeof(struct i2c_board_info));
752 info.addr = apanel_addr; 816 info.addr = apanel_addr;
753 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); 817 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
754 i2c_new_device(&priv->adapter, &info); 818 i2c_new_device(&priv->adapter, &info);
755 } 819 }
756 820
757 if (dmi_name_in_vendors("FUJITSU")) 821 if (dmi_name_in_vendors("FUJITSU"))
758 dmi_walk(dmi_check_onboard_devices, &priv->adapter); 822 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
759 } 823 }
760 #else 824 #else
761 static void __init input_apanel_init(void) {} 825 static void __init input_apanel_init(void) {}
762 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) {} 826 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) {}
763 #endif /* CONFIG_X86 && CONFIG_DMI */ 827 #endif /* CONFIG_X86 && CONFIG_DMI */
764 828
765 static int __devinit i801_probe(struct pci_dev *dev, 829 static int __devinit i801_probe(struct pci_dev *dev,
766 const struct pci_device_id *id) 830 const struct pci_device_id *id)
767 { 831 {
768 unsigned char temp; 832 unsigned char temp;
769 int err, i; 833 int err, i;
770 struct i801_priv *priv; 834 struct i801_priv *priv;
771 835
772 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 836 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
773 if (!priv) 837 if (!priv)
774 return -ENOMEM; 838 return -ENOMEM;
775 839
776 i2c_set_adapdata(&priv->adapter, priv); 840 i2c_set_adapdata(&priv->adapter, priv);
777 priv->adapter.owner = THIS_MODULE; 841 priv->adapter.owner = THIS_MODULE;
778 priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 842 priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
779 priv->adapter.algo = &smbus_algorithm; 843 priv->adapter.algo = &smbus_algorithm;
780 844
781 priv->pci_dev = dev; 845 priv->pci_dev = dev;
782 switch (dev->device) { 846 switch (dev->device) {
783 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: 847 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
784 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: 848 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
785 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: 849 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
786 priv->features |= FEATURE_IDF; 850 priv->features |= FEATURE_IDF;
787 /* fall through */ 851 /* fall through */
788 default: 852 default:
789 priv->features |= FEATURE_I2C_BLOCK_READ; 853 priv->features |= FEATURE_I2C_BLOCK_READ;
790 /* fall through */ 854 /* fall through */
791 case PCI_DEVICE_ID_INTEL_82801DB_3: 855 case PCI_DEVICE_ID_INTEL_82801DB_3:
792 priv->features |= FEATURE_SMBUS_PEC; 856 priv->features |= FEATURE_SMBUS_PEC;
793 priv->features |= FEATURE_BLOCK_BUFFER; 857 priv->features |= FEATURE_BLOCK_BUFFER;
794 /* fall through */ 858 /* fall through */
795 case PCI_DEVICE_ID_INTEL_82801CA_3: 859 case PCI_DEVICE_ID_INTEL_82801CA_3:
796 case PCI_DEVICE_ID_INTEL_82801BA_2: 860 case PCI_DEVICE_ID_INTEL_82801BA_2:
797 case PCI_DEVICE_ID_INTEL_82801AB_3: 861 case PCI_DEVICE_ID_INTEL_82801AB_3:
798 case PCI_DEVICE_ID_INTEL_82801AA_3: 862 case PCI_DEVICE_ID_INTEL_82801AA_3:
799 break; 863 break;
800 } 864 }
801 865
866 /* IRQ processing only tested on CougarPoint PCH */
867 if (dev->device == PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS)
868 priv->features |= FEATURE_IRQ;
869
802 /* Disable features on user request */ 870 /* Disable features on user request */
803 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { 871 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
804 if (priv->features & disable_features & (1 << i)) 872 if (priv->features & disable_features & (1 << i))
805 dev_notice(&dev->dev, "%s disabled by user\n", 873 dev_notice(&dev->dev, "%s disabled by user\n",
806 i801_feature_names[i]); 874 i801_feature_names[i]);
807 } 875 }
808 priv->features &= ~disable_features; 876 priv->features &= ~disable_features;
809 877
810 err = pci_enable_device(dev); 878 err = pci_enable_device(dev);
811 if (err) { 879 if (err) {
812 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 880 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
813 err); 881 err);
814 goto exit; 882 goto exit;
815 } 883 }
816 884
817 /* Determine the address of the SMBus area */ 885 /* Determine the address of the SMBus area */
818 priv->smba = pci_resource_start(dev, SMBBAR); 886 priv->smba = pci_resource_start(dev, SMBBAR);
819 if (!priv->smba) { 887 if (!priv->smba) {
820 dev_err(&dev->dev, "SMBus base address uninitialized, " 888 dev_err(&dev->dev, "SMBus base address uninitialized, "
821 "upgrade BIOS\n"); 889 "upgrade BIOS\n");
822 err = -ENODEV; 890 err = -ENODEV;
823 goto exit; 891 goto exit;
824 } 892 }
825 893
826 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]); 894 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
827 if (err) { 895 if (err) {
828 err = -ENODEV; 896 err = -ENODEV;
829 goto exit; 897 goto exit;
830 } 898 }
831 899
832 err = pci_request_region(dev, SMBBAR, i801_driver.name); 900 err = pci_request_region(dev, SMBBAR, i801_driver.name);
833 if (err) { 901 if (err) {
834 dev_err(&dev->dev, "Failed to request SMBus region " 902 dev_err(&dev->dev, "Failed to request SMBus region "
835 "0x%lx-0x%Lx\n", priv->smba, 903 "0x%lx-0x%Lx\n", priv->smba,
836 (unsigned long long)pci_resource_end(dev, SMBBAR)); 904 (unsigned long long)pci_resource_end(dev, SMBBAR));
837 goto exit; 905 goto exit;
838 } 906 }
839 907
840 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp); 908 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
841 priv->original_hstcfg = temp; 909 priv->original_hstcfg = temp;
842 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 910 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
843 if (!(temp & SMBHSTCFG_HST_EN)) { 911 if (!(temp & SMBHSTCFG_HST_EN)) {
844 dev_info(&dev->dev, "Enabling SMBus device\n"); 912 dev_info(&dev->dev, "Enabling SMBus device\n");
845 temp |= SMBHSTCFG_HST_EN; 913 temp |= SMBHSTCFG_HST_EN;
846 } 914 }
847 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp); 915 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
848 916
849 if (temp & SMBHSTCFG_SMB_SMI_EN) 917 if (temp & SMBHSTCFG_SMB_SMI_EN) {
850 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); 918 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
851 else 919 /* Disable SMBus interrupt feature if SMBus using SMI# */
920 priv->features &= ~FEATURE_IRQ;
921 } else {
852 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n"); 922 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
923 }
853 924
854 /* Clear special mode bits */ 925 /* Clear special mode bits */
855 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) 926 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
856 outb_p(inb_p(SMBAUXCTL(priv)) & 927 outb_p(inb_p(SMBAUXCTL(priv)) &
857 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 928 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
858 929
930 if (priv->features & FEATURE_IRQ) {
931 init_waitqueue_head(&priv->waitq);
932
933 err = request_irq(dev->irq, i801_isr, IRQF_SHARED,
934 i801_driver.name, priv);
935 if (err) {
936 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
937 dev->irq, err);
938 goto exit_release;
939 }
940 }
941
859 /* set up the sysfs linkage to our parent device */ 942 /* set up the sysfs linkage to our parent device */
860 priv->adapter.dev.parent = &dev->dev; 943 priv->adapter.dev.parent = &dev->dev;
861 944
862 /* Retry up to 3 times on lost arbitration */ 945 /* Retry up to 3 times on lost arbitration */
863 priv->adapter.retries = 3; 946 priv->adapter.retries = 3;
864 947
865 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 948 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
866 "SMBus I801 adapter at %04lx", priv->smba); 949 "SMBus I801 adapter at %04lx", priv->smba);
867 err = i2c_add_adapter(&priv->adapter); 950 err = i2c_add_adapter(&priv->adapter);
868 if (err) { 951 if (err) {
869 dev_err(&dev->dev, "Failed to add SMBus adapter\n"); 952 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
870 goto exit_release; 953 goto exit_free_irq;
871 } 954 }
872 955
873 i801_probe_optional_slaves(priv); 956 i801_probe_optional_slaves(priv);
874 957
875 pci_set_drvdata(dev, priv); 958 pci_set_drvdata(dev, priv);
959
876 return 0; 960 return 0;
877 961
962 exit_free_irq:
963 if (priv->features & FEATURE_IRQ)
964 free_irq(dev->irq, priv);
878 exit_release: 965 exit_release:
879 pci_release_region(dev, SMBBAR); 966 pci_release_region(dev, SMBBAR);
880 exit: 967 exit:
881 kfree(priv); 968 kfree(priv);
882 return err; 969 return err;
883 } 970 }
884 971
885 static void __devexit i801_remove(struct pci_dev *dev) 972 static void __devexit i801_remove(struct pci_dev *dev)
886 { 973 {
887 struct i801_priv *priv = pci_get_drvdata(dev); 974 struct i801_priv *priv = pci_get_drvdata(dev);
888 975
889 i2c_del_adapter(&priv->adapter); 976 i2c_del_adapter(&priv->adapter);
890 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 977 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
978
979 if (priv->features & FEATURE_IRQ)
980 free_irq(dev->irq, priv);
891 pci_release_region(dev, SMBBAR); 981 pci_release_region(dev, SMBBAR);
982
892 pci_set_drvdata(dev, NULL); 983 pci_set_drvdata(dev, NULL);
893 kfree(priv); 984 kfree(priv);
894 /* 985 /*
895 * do not call pci_disable_device(dev) since it can cause hard hangs on 986 * do not call pci_disable_device(dev) since it can cause hard hangs on
896 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 987 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
897 */ 988 */
898 } 989 }
899 990
900 #ifdef CONFIG_PM 991 #ifdef CONFIG_PM
901 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg) 992 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
902 { 993 {
903 struct i801_priv *priv = pci_get_drvdata(dev); 994 struct i801_priv *priv = pci_get_drvdata(dev);
904 995
905 pci_save_state(dev); 996 pci_save_state(dev);
906 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 997 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
907 pci_set_power_state(dev, pci_choose_state(dev, mesg)); 998 pci_set_power_state(dev, pci_choose_state(dev, mesg));
908 return 0; 999 return 0;
909 } 1000 }
910 1001
911 static int i801_resume(struct pci_dev *dev) 1002 static int i801_resume(struct pci_dev *dev)
912 { 1003 {
913 pci_set_power_state(dev, PCI_D0); 1004 pci_set_power_state(dev, PCI_D0);
914 pci_restore_state(dev); 1005 pci_restore_state(dev);
915 return pci_enable_device(dev); 1006 return pci_enable_device(dev);
916 } 1007 }
917 #else 1008 #else
918 #define i801_suspend NULL 1009 #define i801_suspend NULL
919 #define i801_resume NULL 1010 #define i801_resume NULL
920 #endif 1011 #endif
921 1012
922 static struct pci_driver i801_driver = { 1013 static struct pci_driver i801_driver = {
923 .name = "i801_smbus", 1014 .name = "i801_smbus",
924 .id_table = i801_ids, 1015 .id_table = i801_ids,
925 .probe = i801_probe, 1016 .probe = i801_probe,
926 .remove = __devexit_p(i801_remove), 1017 .remove = __devexit_p(i801_remove),
927 .suspend = i801_suspend, 1018 .suspend = i801_suspend,
928 .resume = i801_resume, 1019 .resume = i801_resume,
929 }; 1020 };
930 1021
931 static int __init i2c_i801_init(void) 1022 static int __init i2c_i801_init(void)
932 { 1023 {
933 if (dmi_name_in_vendors("FUJITSU")) 1024 if (dmi_name_in_vendors("FUJITSU"))
934 input_apanel_init(); 1025 input_apanel_init();
935 return pci_register_driver(&i801_driver); 1026 return pci_register_driver(&i801_driver);
936 } 1027 }
937 1028
938 static void __exit i2c_i801_exit(void) 1029 static void __exit i2c_i801_exit(void)
939 { 1030 {
940 pci_unregister_driver(&i801_driver); 1031 pci_unregister_driver(&i801_driver);
941 } 1032 }
942 1033
943 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, " 1034 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
944 "Jean Delvare <khali@linux-fr.org>"); 1035 "Jean Delvare <khali@linux-fr.org>");
945 MODULE_DESCRIPTION("I801 SMBus driver"); 1036 MODULE_DESCRIPTION("I801 SMBus driver");
946 MODULE_LICENSE("GPL"); 1037 MODULE_LICENSE("GPL");
947 1038
948 module_init(i2c_i801_init); 1039 module_init(i2c_i801_init);
949 module_exit(i2c_i801_exit); 1040 module_exit(i2c_i801_exit);
950 1041