Doug / smarc-fsl-linux-kernel

Download as
Browse Code ยป

Commit 6446221c14ef3bf58754cf1948631128dbe62700

Authored by Daniel Mack
Committed by Mark Brown
1 parent 1c459de1e6
Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch imx_3.14.28_1.0.0_ga

ARM: pxa: ssp: add pxa_ssp_request_of() 

Add a function to lookup ssp devices from device tree. This way, users
can reference the ssp devices in order to register to them.

Signed-off-by: Daniel Mack <zonque@gmail.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>

Showing 2 changed files with 36 additions and 0 deletions Inline Diff

arch/arm/plat-pxa/ssp.c
Diff comments   View file @ 6446221
1 /* 1 /*
2 * linux/arch/arm/mach-pxa/ssp.c 2 * linux/arch/arm/mach-pxa/ssp.c
3 * 3 *
4 * based on linux/arch/arm/mach-sa1100/ssp.c by Russell King 4 * based on linux/arch/arm/mach-sa1100/ssp.c by Russell King
5 * 5 *
6 * Copyright (C) 2003 Russell King. 6 * Copyright (C) 2003 Russell King.
7 * Copyright (C) 2003 Wolfson Microelectronics PLC 7 * Copyright (C) 2003 Wolfson Microelectronics PLC
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 * 12 *
13 * PXA2xx SSP driver. This provides the generic core for simple 13 * PXA2xx SSP driver. This provides the generic core for simple
14 * IO-based SSP applications and allows easy port setup for DMA access. 14 * IO-based SSP applications and allows easy port setup for DMA access.
15 * 15 *
16 * Author: Liam Girdwood <liam.girdwood@wolfsonmicro.com> 16 * Author: Liam Girdwood <liam.girdwood@wolfsonmicro.com>
17 */ 17 */
18 18
19 #include <linux/module.h> 19 #include <linux/module.h>
20 #include <linux/kernel.h> 20 #include <linux/kernel.h>
21 #include <linux/sched.h> 21 #include <linux/sched.h>
22 #include <linux/slab.h> 22 #include <linux/slab.h>
23 #include <linux/errno.h> 23 #include <linux/errno.h>
24 #include <linux/interrupt.h> 24 #include <linux/interrupt.h>
25 #include <linux/ioport.h> 25 #include <linux/ioport.h>
26 #include <linux/init.h> 26 #include <linux/init.h>
27 #include <linux/mutex.h> 27 #include <linux/mutex.h>
28 #include <linux/clk.h> 28 #include <linux/clk.h>
29 #include <linux/err.h> 29 #include <linux/err.h>
30 #include <linux/platform_device.h> 30 #include <linux/platform_device.h>
31 #include <linux/spi/pxa2xx_spi.h> 31 #include <linux/spi/pxa2xx_spi.h>
32 #include <linux/io.h> 32 #include <linux/io.h>
33 #include <linux/of.h> 33 #include <linux/of.h>
34 #include <linux/of_device.h> 34 #include <linux/of_device.h>
35 35
36 #include <asm/irq.h> 36 #include <asm/irq.h>
37 #include <mach/hardware.h> 37 #include <mach/hardware.h>
38 38
39 static DEFINE_MUTEX(ssp_lock); 39 static DEFINE_MUTEX(ssp_lock);
40 static LIST_HEAD(ssp_list); 40 static LIST_HEAD(ssp_list);
41 41
42 struct ssp_device *pxa_ssp_request(int port, const char *label) 42 struct ssp_device *pxa_ssp_request(int port, const char *label)
43 { 43 {
44 struct ssp_device *ssp = NULL; 44 struct ssp_device *ssp = NULL;
45 45
46 mutex_lock(&ssp_lock); 46 mutex_lock(&ssp_lock);
47 47
48 list_for_each_entry(ssp, &ssp_list, node) { 48 list_for_each_entry(ssp, &ssp_list, node) {
49 if (ssp->port_id == port && ssp->use_count == 0) { 49 if (ssp->port_id == port && ssp->use_count == 0) {
50 ssp->use_count++; 50 ssp->use_count++;
51 ssp->label = label; 51 ssp->label = label;
52 break; 52 break;
53 } 53 }
54 } 54 }
55 55
56 mutex_unlock(&ssp_lock); 56 mutex_unlock(&ssp_lock);
57 57
58 if (&ssp->node == &ssp_list) 58 if (&ssp->node == &ssp_list)
59 return NULL; 59 return NULL;
60 60
61 return ssp; 61 return ssp;
62 } 62 }
63 EXPORT_SYMBOL(pxa_ssp_request); 63 EXPORT_SYMBOL(pxa_ssp_request);
64 64
65 struct ssp_device *pxa_ssp_request_of(const struct device_node *of_node,
66 const char *label)
67 {
68 struct ssp_device *ssp = NULL;
69
70 mutex_lock(&ssp_lock);
71
72 list_for_each_entry(ssp, &ssp_list, node) {
73 if (ssp->of_node == of_node && ssp->use_count == 0) {
74 ssp->use_count++;
75 ssp->label = label;
76 break;
77 }
78 }
79
80 mutex_unlock(&ssp_lock);
81
82 if (&ssp->node == &ssp_list)
83 return NULL;
84
85 return ssp;
86 }
87 EXPORT_SYMBOL(pxa_ssp_request_of);
88
65 void pxa_ssp_free(struct ssp_device *ssp) 89 void pxa_ssp_free(struct ssp_device *ssp)
66 { 90 {
67 mutex_lock(&ssp_lock); 91 mutex_lock(&ssp_lock);
68 if (ssp->use_count) { 92 if (ssp->use_count) {
69 ssp->use_count--; 93 ssp->use_count--;
70 ssp->label = NULL; 94 ssp->label = NULL;
71 } else 95 } else
72 dev_err(&ssp->pdev->dev, "device already free\n"); 96 dev_err(&ssp->pdev->dev, "device already free\n");
73 mutex_unlock(&ssp_lock); 97 mutex_unlock(&ssp_lock);
74 } 98 }
75 EXPORT_SYMBOL(pxa_ssp_free); 99 EXPORT_SYMBOL(pxa_ssp_free);
76 100
77 #ifdef CONFIG_OF 101 #ifdef CONFIG_OF
78 static const struct of_device_id pxa_ssp_of_ids[] = { 102 static const struct of_device_id pxa_ssp_of_ids[] = {
79 { .compatible = "mrvl,pxa25x-ssp", .data = (void *) PXA25x_SSP }, 103 { .compatible = "mrvl,pxa25x-ssp", .data = (void *) PXA25x_SSP },
80 { .compatible = "mvrl,pxa25x-nssp", .data = (void *) PXA25x_NSSP }, 104 { .compatible = "mvrl,pxa25x-nssp", .data = (void *) PXA25x_NSSP },
81 { .compatible = "mrvl,pxa27x-ssp", .data = (void *) PXA27x_SSP }, 105 { .compatible = "mrvl,pxa27x-ssp", .data = (void *) PXA27x_SSP },
82 { .compatible = "mrvl,pxa3xx-ssp", .data = (void *) PXA3xx_SSP }, 106 { .compatible = "mrvl,pxa3xx-ssp", .data = (void *) PXA3xx_SSP },
83 { .compatible = "mvrl,pxa168-ssp", .data = (void *) PXA168_SSP }, 107 { .compatible = "mvrl,pxa168-ssp", .data = (void *) PXA168_SSP },
84 { .compatible = "mrvl,pxa910-ssp", .data = (void *) PXA910_SSP }, 108 { .compatible = "mrvl,pxa910-ssp", .data = (void *) PXA910_SSP },
85 { .compatible = "mrvl,ce4100-ssp", .data = (void *) CE4100_SSP }, 109 { .compatible = "mrvl,ce4100-ssp", .data = (void *) CE4100_SSP },
86 { .compatible = "mrvl,lpss-ssp", .data = (void *) LPSS_SSP }, 110 { .compatible = "mrvl,lpss-ssp", .data = (void *) LPSS_SSP },
87 { }, 111 { },
88 }; 112 };
89 MODULE_DEVICE_TABLE(of, pxa_ssp_of_ids); 113 MODULE_DEVICE_TABLE(of, pxa_ssp_of_ids);
90 #endif 114 #endif
91 115
92 static int pxa_ssp_probe(struct platform_device *pdev) 116 static int pxa_ssp_probe(struct platform_device *pdev)
93 { 117 {
94 struct resource *res; 118 struct resource *res;
95 struct ssp_device *ssp; 119 struct ssp_device *ssp;
96 struct device *dev = &pdev->dev; 120 struct device *dev = &pdev->dev;
97 121
98 ssp = devm_kzalloc(dev, sizeof(struct ssp_device), GFP_KERNEL); 122 ssp = devm_kzalloc(dev, sizeof(struct ssp_device), GFP_KERNEL);
99 if (ssp == NULL) 123 if (ssp == NULL)
100 return -ENOMEM; 124 return -ENOMEM;
101 125
102 ssp->pdev = pdev; 126 ssp->pdev = pdev;
103 127
104 ssp->clk = devm_clk_get(dev, NULL); 128 ssp->clk = devm_clk_get(dev, NULL);
105 if (IS_ERR(ssp->clk)) 129 if (IS_ERR(ssp->clk))
106 return PTR_ERR(ssp->clk); 130 return PTR_ERR(ssp->clk);
107 131
108 if (dev->of_node) { 132 if (dev->of_node) {
109 struct of_phandle_args dma_spec; 133 struct of_phandle_args dma_spec;
110 struct device_node *np = dev->of_node; 134 struct device_node *np = dev->of_node;
111 135
112 /* 136 /*
113 * FIXME: we should allocate the DMA channel from this 137 * FIXME: we should allocate the DMA channel from this
114 * context and pass the channel down to the ssp users. 138 * context and pass the channel down to the ssp users.
115 * For now, we lookup the rx and tx indices manually 139 * For now, we lookup the rx and tx indices manually
116 */ 140 */
117 141
118 /* rx */ 142 /* rx */
119 of_parse_phandle_with_args(np, "dmas", "#dma-cells", 143 of_parse_phandle_with_args(np, "dmas", "#dma-cells",
120 0, &dma_spec); 144 0, &dma_spec);
121 ssp->drcmr_rx = dma_spec.args[0]; 145 ssp->drcmr_rx = dma_spec.args[0];
122 of_node_put(dma_spec.np); 146 of_node_put(dma_spec.np);
123 147
124 /* tx */ 148 /* tx */
125 of_parse_phandle_with_args(np, "dmas", "#dma-cells", 149 of_parse_phandle_with_args(np, "dmas", "#dma-cells",
126 1, &dma_spec); 150 1, &dma_spec);
127 ssp->drcmr_tx = dma_spec.args[0]; 151 ssp->drcmr_tx = dma_spec.args[0];
128 of_node_put(dma_spec.np); 152 of_node_put(dma_spec.np);
129 } else { 153 } else {
130 res = platform_get_resource(pdev, IORESOURCE_DMA, 0); 154 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
131 if (res == NULL) { 155 if (res == NULL) {
132 dev_err(dev, "no SSP RX DRCMR defined\n"); 156 dev_err(dev, "no SSP RX DRCMR defined\n");
133 return -ENODEV; 157 return -ENODEV;
134 } 158 }
135 ssp->drcmr_rx = res->start; 159 ssp->drcmr_rx = res->start;
136 160
137 res = platform_get_resource(pdev, IORESOURCE_DMA, 1); 161 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
138 if (res == NULL) { 162 if (res == NULL) {
139 dev_err(dev, "no SSP TX DRCMR defined\n"); 163 dev_err(dev, "no SSP TX DRCMR defined\n");
140 return -ENODEV; 164 return -ENODEV;
141 } 165 }
142 ssp->drcmr_tx = res->start; 166 ssp->drcmr_tx = res->start;
143 } 167 }
144 168
145 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 169 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
146 if (res == NULL) { 170 if (res == NULL) {
147 dev_err(dev, "no memory resource defined\n"); 171 dev_err(dev, "no memory resource defined\n");
148 return -ENODEV; 172 return -ENODEV;
149 } 173 }
150 174
151 res = devm_request_mem_region(dev, res->start, resource_size(res), 175 res = devm_request_mem_region(dev, res->start, resource_size(res),
152 pdev->name); 176 pdev->name);
153 if (res == NULL) { 177 if (res == NULL) {
154 dev_err(dev, "failed to request memory resource\n"); 178 dev_err(dev, "failed to request memory resource\n");
155 return -EBUSY; 179 return -EBUSY;
156 } 180 }
157 181
158 ssp->phys_base = res->start; 182 ssp->phys_base = res->start;
159 183
160 ssp->mmio_base = devm_ioremap(dev, res->start, resource_size(res)); 184 ssp->mmio_base = devm_ioremap(dev, res->start, resource_size(res));
161 if (ssp->mmio_base == NULL) { 185 if (ssp->mmio_base == NULL) {
162 dev_err(dev, "failed to ioremap() registers\n"); 186 dev_err(dev, "failed to ioremap() registers\n");
163 return -ENODEV; 187 return -ENODEV;
164 } 188 }
165 189
166 ssp->irq = platform_get_irq(pdev, 0); 190 ssp->irq = platform_get_irq(pdev, 0);
167 if (ssp->irq < 0) { 191 if (ssp->irq < 0) {
168 dev_err(dev, "no IRQ resource defined\n"); 192 dev_err(dev, "no IRQ resource defined\n");
169 return -ENODEV; 193 return -ENODEV;
170 } 194 }
171 195
172 if (dev->of_node) { 196 if (dev->of_node) {
173 const struct of_device_id *id = 197 const struct of_device_id *id =
174 of_match_device(of_match_ptr(pxa_ssp_of_ids), dev); 198 of_match_device(of_match_ptr(pxa_ssp_of_ids), dev);
175 ssp->type = (int) id->data; 199 ssp->type = (int) id->data;
176 } else { 200 } else {
177 const struct platform_device_id *id = 201 const struct platform_device_id *id =
178 platform_get_device_id(pdev); 202 platform_get_device_id(pdev);
179 ssp->type = (int) id->driver_data; 203 ssp->type = (int) id->driver_data;
180 204
181 /* PXA2xx/3xx SSP ports starts from 1 and the internal pdev->id 205 /* PXA2xx/3xx SSP ports starts from 1 and the internal pdev->id
182 * starts from 0, do a translation here 206 * starts from 0, do a translation here
183 */ 207 */
184 ssp->port_id = pdev->id + 1; 208 ssp->port_id = pdev->id + 1;
185 } 209 }
186 210
187 ssp->use_count = 0; 211 ssp->use_count = 0;
212 ssp->of_node = dev->of_node;
188 213
189 mutex_lock(&ssp_lock); 214 mutex_lock(&ssp_lock);
190 list_add(&ssp->node, &ssp_list); 215 list_add(&ssp->node, &ssp_list);
191 mutex_unlock(&ssp_lock); 216 mutex_unlock(&ssp_lock);
192 217
193 platform_set_drvdata(pdev, ssp); 218 platform_set_drvdata(pdev, ssp);
194 219
195 return 0; 220 return 0;
196 } 221 }
197 222
198 static int pxa_ssp_remove(struct platform_device *pdev) 223 static int pxa_ssp_remove(struct platform_device *pdev)
199 { 224 {
200 struct resource *res; 225 struct resource *res;
201 struct ssp_device *ssp; 226 struct ssp_device *ssp;
202 227
203 ssp = platform_get_drvdata(pdev); 228 ssp = platform_get_drvdata(pdev);
204 if (ssp == NULL) 229 if (ssp == NULL)
205 return -ENODEV; 230 return -ENODEV;
206 231
207 iounmap(ssp->mmio_base); 232 iounmap(ssp->mmio_base);
208 233
209 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 234 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
210 release_mem_region(res->start, resource_size(res)); 235 release_mem_region(res->start, resource_size(res));
211 236
212 clk_put(ssp->clk); 237 clk_put(ssp->clk);
213 238
214 mutex_lock(&ssp_lock); 239 mutex_lock(&ssp_lock);
215 list_del(&ssp->node); 240 list_del(&ssp->node);
216 mutex_unlock(&ssp_lock); 241 mutex_unlock(&ssp_lock);
217 242
218 kfree(ssp); 243 kfree(ssp);
219 return 0; 244 return 0;
220 } 245 }
221 246
222 static const struct platform_device_id ssp_id_table[] = { 247 static const struct platform_device_id ssp_id_table[] = {
223 { "pxa25x-ssp", PXA25x_SSP }, 248 { "pxa25x-ssp", PXA25x_SSP },
224 { "pxa25x-nssp", PXA25x_NSSP }, 249 { "pxa25x-nssp", PXA25x_NSSP },
225 { "pxa27x-ssp", PXA27x_SSP }, 250 { "pxa27x-ssp", PXA27x_SSP },
226 { "pxa168-ssp", PXA168_SSP }, 251 { "pxa168-ssp", PXA168_SSP },
227 { "pxa910-ssp", PXA910_SSP }, 252 { "pxa910-ssp", PXA910_SSP },
228 { }, 253 { },
229 }; 254 };
230 255
231 static struct platform_driver pxa_ssp_driver = { 256 static struct platform_driver pxa_ssp_driver = {
232 .probe = pxa_ssp_probe, 257 .probe = pxa_ssp_probe,
233 .remove = pxa_ssp_remove, 258 .remove = pxa_ssp_remove,
234 .driver = { 259 .driver = {
235 .owner = THIS_MODULE, 260 .owner = THIS_MODULE,
236 .name = "pxa2xx-ssp", 261 .name = "pxa2xx-ssp",
237 .of_match_table = of_match_ptr(pxa_ssp_of_ids), 262 .of_match_table = of_match_ptr(pxa_ssp_of_ids),
238 }, 263 },
239 .id_table = ssp_id_table, 264 .id_table = ssp_id_table,
240 }; 265 };
241 266
242 static int __init pxa_ssp_init(void) 267 static int __init pxa_ssp_init(void)
243 { 268 {
244 return platform_driver_register(&pxa_ssp_driver); 269 return platform_driver_register(&pxa_ssp_driver);
245 } 270 }
246 271
247 static void __exit pxa_ssp_exit(void) 272 static void __exit pxa_ssp_exit(void)
248 { 273 {
249 platform_driver_unregister(&pxa_ssp_driver); 274 platform_driver_unregister(&pxa_ssp_driver);
250 } 275 }
251 276
252 arch_initcall(pxa_ssp_init); 277 arch_initcall(pxa_ssp_init);
253 module_exit(pxa_ssp_exit); 278 module_exit(pxa_ssp_exit);
254 279
255 MODULE_DESCRIPTION("PXA SSP driver"); 280 MODULE_DESCRIPTION("PXA SSP driver");
256 MODULE_AUTHOR("Liam Girdwood"); 281 MODULE_AUTHOR("Liam Girdwood");
257 MODULE_LICENSE("GPL"); 282 MODULE_LICENSE("GPL");
258 283
include/linux/pxa2xx_ssp.h
Diff comments   View file @ 6446221
1 /* 1 /*
2 * pxa2xx_ssp.h 2 * pxa2xx_ssp.h
3 * 3 *
4 * Copyright (C) 2003 Russell King, All Rights Reserved. 4 * Copyright (C) 2003 Russell King, All Rights Reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 * 9 *
10 * This driver supports the following PXA CPU/SSP ports:- 10 * This driver supports the following PXA CPU/SSP ports:-
11 * 11 *
12 * PXA250 SSP 12 * PXA250 SSP
13 * PXA255 SSP, NSSP 13 * PXA255 SSP, NSSP
14 * PXA26x SSP, NSSP, ASSP 14 * PXA26x SSP, NSSP, ASSP
15 * PXA27x SSP1, SSP2, SSP3 15 * PXA27x SSP1, SSP2, SSP3
16 * PXA3xx SSP1, SSP2, SSP3, SSP4 16 * PXA3xx SSP1, SSP2, SSP3, SSP4
17 */ 17 */
18 18
19 #ifndef __LINUX_SSP_H 19 #ifndef __LINUX_SSP_H
20 #define __LINUX_SSP_H 20 #define __LINUX_SSP_H
21 21
22 #include <linux/list.h> 22 #include <linux/list.h>
23 #include <linux/io.h> 23 #include <linux/io.h>
24 #include <linux/of.h>
24 25
26
25 /* 27 /*
26 * SSP Serial Port Registers 28 * SSP Serial Port Registers
27 * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different. 29 * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
28 * PXA255, PXA26x and PXA27x have extra ports, registers and bits. 30 * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
29 */ 31 */
30 32
31 #define SSCR0 (0x00) /* SSP Control Register 0 */ 33 #define SSCR0 (0x00) /* SSP Control Register 0 */
32 #define SSCR1 (0x04) /* SSP Control Register 1 */ 34 #define SSCR1 (0x04) /* SSP Control Register 1 */
33 #define SSSR (0x08) /* SSP Status Register */ 35 #define SSSR (0x08) /* SSP Status Register */
34 #define SSITR (0x0C) /* SSP Interrupt Test Register */ 36 #define SSITR (0x0C) /* SSP Interrupt Test Register */
35 #define SSDR (0x10) /* SSP Data Write/Data Read Register */ 37 #define SSDR (0x10) /* SSP Data Write/Data Read Register */
36 38
37 #define SSTO (0x28) /* SSP Time Out Register */ 39 #define SSTO (0x28) /* SSP Time Out Register */
38 #define SSPSP (0x2C) /* SSP Programmable Serial Protocol */ 40 #define SSPSP (0x2C) /* SSP Programmable Serial Protocol */
39 #define SSTSA (0x30) /* SSP Tx Timeslot Active */ 41 #define SSTSA (0x30) /* SSP Tx Timeslot Active */
40 #define SSRSA (0x34) /* SSP Rx Timeslot Active */ 42 #define SSRSA (0x34) /* SSP Rx Timeslot Active */
41 #define SSTSS (0x38) /* SSP Timeslot Status */ 43 #define SSTSS (0x38) /* SSP Timeslot Status */
42 #define SSACD (0x3C) /* SSP Audio Clock Divider */ 44 #define SSACD (0x3C) /* SSP Audio Clock Divider */
43 #define SSACDD (0x40) /* SSP Audio Clock Dither Divider */ 45 #define SSACDD (0x40) /* SSP Audio Clock Dither Divider */
44 46
45 /* Common PXA2xx bits first */ 47 /* Common PXA2xx bits first */
46 #define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */ 48 #define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
47 #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */ 49 #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
48 #define SSCR0_FRF (0x00000030) /* FRame Format (mask) */ 50 #define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
49 #define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */ 51 #define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
50 #define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */ 52 #define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
51 #define SSCR0_National (0x2 << 4) /* National Microwire */ 53 #define SSCR0_National (0x2 << 4) /* National Microwire */
52 #define SSCR0_ECS (1 << 6) /* External clock select */ 54 #define SSCR0_ECS (1 << 6) /* External clock select */
53 #define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */ 55 #define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
54 #define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */ 56 #define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */
55 57
56 /* PXA27x, PXA3xx */ 58 /* PXA27x, PXA3xx */
57 #define SSCR0_EDSS (1 << 20) /* Extended data size select */ 59 #define SSCR0_EDSS (1 << 20) /* Extended data size select */
58 #define SSCR0_NCS (1 << 21) /* Network clock select */ 60 #define SSCR0_NCS (1 << 21) /* Network clock select */
59 #define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */ 61 #define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
60 #define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */ 62 #define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
61 #define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */ 63 #define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
62 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */ 64 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
63 #define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */ 65 #define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */
64 #define SSCR0_ACS (1 << 30) /* Audio clock select */ 66 #define SSCR0_ACS (1 << 30) /* Audio clock select */
65 #define SSCR0_MOD (1 << 31) /* Mode (normal or network) */ 67 #define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
66 68
67 69
68 #define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ 70 #define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
69 #define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ 71 #define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
70 #define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ 72 #define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
71 #define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */ 73 #define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */
72 #define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ 74 #define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
73 #define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ 75 #define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
74 76
75 #define SSSR_ALT_FRM_MASK 3 /* Masks the SFRM signal number */ 77 #define SSSR_ALT_FRM_MASK 3 /* Masks the SFRM signal number */
76 #define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */ 78 #define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
77 #define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */ 79 #define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
78 #define SSSR_BSY (1 << 4) /* SSP Busy */ 80 #define SSSR_BSY (1 << 4) /* SSP Busy */
79 #define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */ 81 #define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
80 #define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ 82 #define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
81 #define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ 83 #define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
82 84
83 #ifdef CONFIG_ARCH_PXA 85 #ifdef CONFIG_ARCH_PXA
84 #define RX_THRESH_DFLT 8 86 #define RX_THRESH_DFLT 8
85 #define TX_THRESH_DFLT 8 87 #define TX_THRESH_DFLT 8
86 88
87 #define SSSR_TFL_MASK (0xf << 8) /* Transmit FIFO Level mask */ 89 #define SSSR_TFL_MASK (0xf << 8) /* Transmit FIFO Level mask */
88 #define SSSR_RFL_MASK (0xf << 12) /* Receive FIFO Level mask */ 90 #define SSSR_RFL_MASK (0xf << 12) /* Receive FIFO Level mask */
89 91
90 #define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */ 92 #define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
91 #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */ 93 #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
92 #define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */ 94 #define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
93 #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */ 95 #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
94 96
95 #else 97 #else
96 98
97 #define RX_THRESH_DFLT 2 99 #define RX_THRESH_DFLT 2
98 #define TX_THRESH_DFLT 2 100 #define TX_THRESH_DFLT 2
99 101
100 #define SSSR_TFL_MASK (0x3 << 8) /* Transmit FIFO Level mask */ 102 #define SSSR_TFL_MASK (0x3 << 8) /* Transmit FIFO Level mask */
101 #define SSSR_RFL_MASK (0x3 << 12) /* Receive FIFO Level mask */ 103 #define SSSR_RFL_MASK (0x3 << 12) /* Receive FIFO Level mask */
102 104
103 #define SSCR1_TFT (0x000000c0) /* Transmit FIFO Threshold (mask) */ 105 #define SSCR1_TFT (0x000000c0) /* Transmit FIFO Threshold (mask) */
104 #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..4] */ 106 #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..4] */
105 #define SSCR1_RFT (0x00000c00) /* Receive FIFO Threshold (mask) */ 107 #define SSCR1_RFT (0x00000c00) /* Receive FIFO Threshold (mask) */
106 #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */ 108 #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */
107 #endif 109 #endif
108 110
109 /* extra bits in PXA255, PXA26x and PXA27x SSP ports */ 111 /* extra bits in PXA255, PXA26x and PXA27x SSP ports */
110 #define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */ 112 #define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
111 #define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */ 113 #define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
112 #define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */ 114 #define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */
113 #define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */ 115 #define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */
114 #define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */ 116 #define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */
115 #define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */ 117 #define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */
116 #define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */ 118 #define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */
117 #define SSCR1_ECRB (1 << 26) /* Enable Clock request B */ 119 #define SSCR1_ECRB (1 << 26) /* Enable Clock request B */
118 #define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */ 120 #define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */
119 #define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */ 121 #define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */
120 #define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */ 122 #define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */
121 #define SSCR1_TRAIL (1 << 22) /* Trailing Byte */ 123 #define SSCR1_TRAIL (1 << 22) /* Trailing Byte */
122 #define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */ 124 #define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */
123 #define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */ 125 #define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */
124 #define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */ 126 #define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */
125 #define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interrupt Enable */ 127 #define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interrupt Enable */
126 #define SSCR1_IFS (1 << 16) /* Invert Frame Signal */ 128 #define SSCR1_IFS (1 << 16) /* Invert Frame Signal */
127 #define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */ 129 #define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */
128 #define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */ 130 #define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */
129 131
130 #define SSSR_BCE (1 << 23) /* Bit Count Error */ 132 #define SSSR_BCE (1 << 23) /* Bit Count Error */
131 #define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */ 133 #define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */
132 #define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */ 134 #define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */
133 #define SSSR_EOC (1 << 20) /* End Of Chain */ 135 #define SSSR_EOC (1 << 20) /* End Of Chain */
134 #define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ 136 #define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
135 #define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */ 137 #define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
136 138
137 139
138 #define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */ 140 #define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
139 #define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */ 141 #define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
140 #define SSPSP_ETDS (1 << 3) /* End of Transfer data State */ 142 #define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
141 #define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */ 143 #define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
142 #define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */ 144 #define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */
143 #define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */ 145 #define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
144 #define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */ 146 #define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
145 #define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */ 147 #define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
146 #define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */ 148 #define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */
147 149
148 /* PXA3xx */ 150 /* PXA3xx */
149 #define SSPSP_EDMYSTRT(x) ((x) << 26) /* Extended Dummy Start */ 151 #define SSPSP_EDMYSTRT(x) ((x) << 26) /* Extended Dummy Start */
150 #define SSPSP_EDMYSTOP(x) ((x) << 28) /* Extended Dummy Stop */ 152 #define SSPSP_EDMYSTOP(x) ((x) << 28) /* Extended Dummy Stop */
151 #define SSPSP_TIMING_MASK (0x7f8001f0) 153 #define SSPSP_TIMING_MASK (0x7f8001f0)
152 154
153 #define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */ 155 #define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
154 #define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */ 156 #define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
155 #define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */ 157 #define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
156 #define SSACD_SCDX8 (1 << 7) /* SYSCLK division ratio select */ 158 #define SSACD_SCDX8 (1 << 7) /* SYSCLK division ratio select */
157 159
158 /* LPSS SSP */ 160 /* LPSS SSP */
159 #define SSITF 0x44 /* TX FIFO trigger level */ 161 #define SSITF 0x44 /* TX FIFO trigger level */
160 #define SSITF_TxLoThresh(x) (((x) - 1) << 8) 162 #define SSITF_TxLoThresh(x) (((x) - 1) << 8)
161 #define SSITF_TxHiThresh(x) ((x) - 1) 163 #define SSITF_TxHiThresh(x) ((x) - 1)
162 164
163 #define SSIRF 0x48 /* RX FIFO trigger level */ 165 #define SSIRF 0x48 /* RX FIFO trigger level */
164 #define SSIRF_RxThresh(x) ((x) - 1) 166 #define SSIRF_RxThresh(x) ((x) - 1)
165 167
166 enum pxa_ssp_type { 168 enum pxa_ssp_type {
167 SSP_UNDEFINED = 0, 169 SSP_UNDEFINED = 0,
168 PXA25x_SSP, /* pxa 210, 250, 255, 26x */ 170 PXA25x_SSP, /* pxa 210, 250, 255, 26x */
169 PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */ 171 PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
170 PXA27x_SSP, 172 PXA27x_SSP,
171 PXA3xx_SSP, 173 PXA3xx_SSP,
172 PXA168_SSP, 174 PXA168_SSP,
173 PXA910_SSP, 175 PXA910_SSP,
174 CE4100_SSP, 176 CE4100_SSP,
175 LPSS_SSP, 177 LPSS_SSP,
176 }; 178 };
177 179
178 struct ssp_device { 180 struct ssp_device {
179 struct platform_device *pdev; 181 struct platform_device *pdev;
180 struct list_head node; 182 struct list_head node;
181 183
182 struct clk *clk; 184 struct clk *clk;
183 void __iomem *mmio_base; 185 void __iomem *mmio_base;
184 unsigned long phys_base; 186 unsigned long phys_base;
185 187
186 const char *label; 188 const char *label;
187 int port_id; 189 int port_id;
188 int type; 190 int type;
189 int use_count; 191 int use_count;
190 int irq; 192 int irq;
191 int drcmr_rx; 193 int drcmr_rx;
192 int drcmr_tx; 194 int drcmr_tx;
195
196 struct device_node *of_node;
193 }; 197 };
194 198
195 /** 199 /**
196 * pxa_ssp_write_reg - Write to a SSP register 200 * pxa_ssp_write_reg - Write to a SSP register
197 * 201 *
198 * @dev: SSP device to access 202 * @dev: SSP device to access
199 * @reg: Register to write to 203 * @reg: Register to write to
200 * @val: Value to be written. 204 * @val: Value to be written.
201 */ 205 */
202 static inline void pxa_ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val) 206 static inline void pxa_ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val)
203 { 207 {
204 __raw_writel(val, dev->mmio_base + reg); 208 __raw_writel(val, dev->mmio_base + reg);
205 } 209 }
206 210
207 /** 211 /**
208 * pxa_ssp_read_reg - Read from a SSP register 212 * pxa_ssp_read_reg - Read from a SSP register
209 * 213 *
210 * @dev: SSP device to access 214 * @dev: SSP device to access
211 * @reg: Register to read from 215 * @reg: Register to read from
212 */ 216 */
213 static inline u32 pxa_ssp_read_reg(struct ssp_device *dev, u32 reg) 217 static inline u32 pxa_ssp_read_reg(struct ssp_device *dev, u32 reg)
214 { 218 {
215 return __raw_readl(dev->mmio_base + reg); 219 return __raw_readl(dev->mmio_base + reg);
216 } 220 }
217 221
218 #ifdef CONFIG_ARCH_PXA 222 #ifdef CONFIG_ARCH_PXA
219 struct ssp_device *pxa_ssp_request(int port, const char *label); 223 struct ssp_device *pxa_ssp_request(int port, const char *label);
220 void pxa_ssp_free(struct ssp_device *); 224 void pxa_ssp_free(struct ssp_device *);
225 struct ssp_device *pxa_ssp_request_of(const struct device_node *of_node,
226 const char *label);
221 #else 227 #else
222 static inline struct ssp_device *pxa_ssp_request(int port, const char *label) 228 static inline struct ssp_device *pxa_ssp_request(int port, const char *label)
229 {
230 return NULL;
231 }
232 static inline struct ssp_device *pxa_ssp_request_of(const struct device_node *n,
233 const char *name)
223 { 234 {
224 return NULL; 235 return NULL;
225 } 236 }
226 static inline void pxa_ssp_free(struct ssp_device *ssp) {} 237 static inline void pxa_ssp_free(struct ssp_device *ssp) {}
227 #endif 238 #endif
228 239
229 #endif 240 #endif
230 241