Commit 6880e7cb35bfde5c8ef65cc846e0df54808f982f
Committed by
Jeff Garzik
Jeff Garzik
1 parent
c1b7151a5e
Exists in
master
and in
7 other branches
gianfar: remove orphan struct.
struct net_device_stats is no longer used in driver's private struct but in struct net_device. Cc: Li Yang <leoli@freescale.com> Signed-off-by: Sebastian Siewior <bigeasy@linutronix.de> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Showing 1 changed file with 0 additions and 1 deletions Inline Diff
drivers/net/gianfar.h
| 1 | /* | 1 | /* |
| 2 | * drivers/net/gianfar.h | 2 | * drivers/net/gianfar.h |
| 3 | * | 3 | * |
| 4 | * Gianfar Ethernet Driver | 4 | * Gianfar Ethernet Driver |
| 5 | * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560 | 5 | * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560 |
| 6 | * Based on 8260_io/fcc_enet.c | 6 | * Based on 8260_io/fcc_enet.c |
| 7 | * | 7 | * |
| 8 | * Author: Andy Fleming | 8 | * Author: Andy Fleming |
| 9 | * Maintainer: Kumar Gala | 9 | * Maintainer: Kumar Gala |
| 10 | * | 10 | * |
| 11 | * Copyright (c) 2002-2004 Freescale Semiconductor, Inc. | 11 | * Copyright (c) 2002-2004 Freescale Semiconductor, Inc. |
| 12 | * | 12 | * |
| 13 | * This program is free software; you can redistribute it and/or modify it | 13 | * This program is free software; you can redistribute it and/or modify it |
| 14 | * under the terms of the GNU General Public License as published by the | 14 | * under the terms of the GNU General Public License as published by the |
| 15 | * Free Software Foundation; either version 2 of the License, or (at your | 15 | * Free Software Foundation; either version 2 of the License, or (at your |
| 16 | * option) any later version. | 16 | * option) any later version. |
| 17 | * | 17 | * |
| 18 | * Still left to do: | 18 | * Still left to do: |
| 19 | * -Add support for module parameters | 19 | * -Add support for module parameters |
| 20 | * -Add patch for ethtool phys id | 20 | * -Add patch for ethtool phys id |
| 21 | */ | 21 | */ |
| 22 | #ifndef __GIANFAR_H | 22 | #ifndef __GIANFAR_H |
| 23 | #define __GIANFAR_H | 23 | #define __GIANFAR_H |
| 24 | 24 | ||
| 25 | #include <linux/kernel.h> | 25 | #include <linux/kernel.h> |
| 26 | #include <linux/sched.h> | 26 | #include <linux/sched.h> |
| 27 | #include <linux/string.h> | 27 | #include <linux/string.h> |
| 28 | #include <linux/errno.h> | 28 | #include <linux/errno.h> |
| 29 | #include <linux/slab.h> | 29 | #include <linux/slab.h> |
| 30 | #include <linux/interrupt.h> | 30 | #include <linux/interrupt.h> |
| 31 | #include <linux/init.h> | 31 | #include <linux/init.h> |
| 32 | #include <linux/delay.h> | 32 | #include <linux/delay.h> |
| 33 | #include <linux/netdevice.h> | 33 | #include <linux/netdevice.h> |
| 34 | #include <linux/etherdevice.h> | 34 | #include <linux/etherdevice.h> |
| 35 | #include <linux/skbuff.h> | 35 | #include <linux/skbuff.h> |
| 36 | #include <linux/spinlock.h> | 36 | #include <linux/spinlock.h> |
| 37 | #include <linux/mm.h> | 37 | #include <linux/mm.h> |
| 38 | #include <linux/mii.h> | 38 | #include <linux/mii.h> |
| 39 | #include <linux/phy.h> | 39 | #include <linux/phy.h> |
| 40 | 40 | ||
| 41 | #include <asm/io.h> | 41 | #include <asm/io.h> |
| 42 | #include <asm/irq.h> | 42 | #include <asm/irq.h> |
| 43 | #include <asm/uaccess.h> | 43 | #include <asm/uaccess.h> |
| 44 | #include <linux/module.h> | 44 | #include <linux/module.h> |
| 45 | #include <linux/crc32.h> | 45 | #include <linux/crc32.h> |
| 46 | #include <linux/workqueue.h> | 46 | #include <linux/workqueue.h> |
| 47 | #include <linux/ethtool.h> | 47 | #include <linux/ethtool.h> |
| 48 | #include <linux/fsl_devices.h> | 48 | #include <linux/fsl_devices.h> |
| 49 | #include "gianfar_mii.h" | 49 | #include "gianfar_mii.h" |
| 50 | 50 | ||
| 51 | /* The maximum number of packets to be handled in one call of gfar_poll */ | 51 | /* The maximum number of packets to be handled in one call of gfar_poll */ |
| 52 | #define GFAR_DEV_WEIGHT 64 | 52 | #define GFAR_DEV_WEIGHT 64 |
| 53 | 53 | ||
| 54 | /* Length for FCB */ | 54 | /* Length for FCB */ |
| 55 | #define GMAC_FCB_LEN 8 | 55 | #define GMAC_FCB_LEN 8 |
| 56 | 56 | ||
| 57 | /* Default padding amount */ | 57 | /* Default padding amount */ |
| 58 | #define DEFAULT_PADDING 2 | 58 | #define DEFAULT_PADDING 2 |
| 59 | 59 | ||
| 60 | /* Number of bytes to align the rx bufs to */ | 60 | /* Number of bytes to align the rx bufs to */ |
| 61 | #define RXBUF_ALIGNMENT 64 | 61 | #define RXBUF_ALIGNMENT 64 |
| 62 | 62 | ||
| 63 | /* The number of bytes which composes a unit for the purpose of | 63 | /* The number of bytes which composes a unit for the purpose of |
| 64 | * allocating data buffers. ie-for any given MTU, the data buffer | 64 | * allocating data buffers. ie-for any given MTU, the data buffer |
| 65 | * will be the next highest multiple of 512 bytes. */ | 65 | * will be the next highest multiple of 512 bytes. */ |
| 66 | #define INCREMENTAL_BUFFER_SIZE 512 | 66 | #define INCREMENTAL_BUFFER_SIZE 512 |
| 67 | 67 | ||
| 68 | 68 | ||
| 69 | #define MAC_ADDR_LEN 6 | 69 | #define MAC_ADDR_LEN 6 |
| 70 | 70 | ||
| 71 | #define PHY_INIT_TIMEOUT 100000 | 71 | #define PHY_INIT_TIMEOUT 100000 |
| 72 | #define GFAR_PHY_CHANGE_TIME 2 | 72 | #define GFAR_PHY_CHANGE_TIME 2 |
| 73 | 73 | ||
| 74 | #define DEVICE_NAME "%s: Gianfar Ethernet Controller Version 1.2, " | 74 | #define DEVICE_NAME "%s: Gianfar Ethernet Controller Version 1.2, " |
| 75 | #define DRV_NAME "gfar-enet" | 75 | #define DRV_NAME "gfar-enet" |
| 76 | extern const char gfar_driver_name[]; | 76 | extern const char gfar_driver_name[]; |
| 77 | extern const char gfar_driver_version[]; | 77 | extern const char gfar_driver_version[]; |
| 78 | 78 | ||
| 79 | /* These need to be powers of 2 for this driver */ | 79 | /* These need to be powers of 2 for this driver */ |
| 80 | #ifdef CONFIG_GFAR_NAPI | 80 | #ifdef CONFIG_GFAR_NAPI |
| 81 | #define DEFAULT_TX_RING_SIZE 256 | 81 | #define DEFAULT_TX_RING_SIZE 256 |
| 82 | #define DEFAULT_RX_RING_SIZE 256 | 82 | #define DEFAULT_RX_RING_SIZE 256 |
| 83 | #else | 83 | #else |
| 84 | #define DEFAULT_TX_RING_SIZE 64 | 84 | #define DEFAULT_TX_RING_SIZE 64 |
| 85 | #define DEFAULT_RX_RING_SIZE 64 | 85 | #define DEFAULT_RX_RING_SIZE 64 |
| 86 | #endif | 86 | #endif |
| 87 | 87 | ||
| 88 | #define GFAR_RX_MAX_RING_SIZE 256 | 88 | #define GFAR_RX_MAX_RING_SIZE 256 |
| 89 | #define GFAR_TX_MAX_RING_SIZE 256 | 89 | #define GFAR_TX_MAX_RING_SIZE 256 |
| 90 | 90 | ||
| 91 | #define GFAR_MAX_FIFO_THRESHOLD 511 | 91 | #define GFAR_MAX_FIFO_THRESHOLD 511 |
| 92 | #define GFAR_MAX_FIFO_STARVE 511 | 92 | #define GFAR_MAX_FIFO_STARVE 511 |
| 93 | #define GFAR_MAX_FIFO_STARVE_OFF 511 | 93 | #define GFAR_MAX_FIFO_STARVE_OFF 511 |
| 94 | 94 | ||
| 95 | #define DEFAULT_RX_BUFFER_SIZE 1536 | 95 | #define DEFAULT_RX_BUFFER_SIZE 1536 |
| 96 | #define TX_RING_MOD_MASK(size) (size-1) | 96 | #define TX_RING_MOD_MASK(size) (size-1) |
| 97 | #define RX_RING_MOD_MASK(size) (size-1) | 97 | #define RX_RING_MOD_MASK(size) (size-1) |
| 98 | #define JUMBO_BUFFER_SIZE 9728 | 98 | #define JUMBO_BUFFER_SIZE 9728 |
| 99 | #define JUMBO_FRAME_SIZE 9600 | 99 | #define JUMBO_FRAME_SIZE 9600 |
| 100 | 100 | ||
| 101 | #define DEFAULT_FIFO_TX_THR 0x100 | 101 | #define DEFAULT_FIFO_TX_THR 0x100 |
| 102 | #define DEFAULT_FIFO_TX_STARVE 0x40 | 102 | #define DEFAULT_FIFO_TX_STARVE 0x40 |
| 103 | #define DEFAULT_FIFO_TX_STARVE_OFF 0x80 | 103 | #define DEFAULT_FIFO_TX_STARVE_OFF 0x80 |
| 104 | #define DEFAULT_BD_STASH 1 | 104 | #define DEFAULT_BD_STASH 1 |
| 105 | #define DEFAULT_STASH_LENGTH 64 | 105 | #define DEFAULT_STASH_LENGTH 64 |
| 106 | #define DEFAULT_STASH_INDEX 0 | 106 | #define DEFAULT_STASH_INDEX 0 |
| 107 | 107 | ||
| 108 | /* The number of Exact Match registers */ | 108 | /* The number of Exact Match registers */ |
| 109 | #define GFAR_EM_NUM 15 | 109 | #define GFAR_EM_NUM 15 |
| 110 | 110 | ||
| 111 | /* Latency of interface clock in nanoseconds */ | 111 | /* Latency of interface clock in nanoseconds */ |
| 112 | /* Interface clock latency , in this case, means the | 112 | /* Interface clock latency , in this case, means the |
| 113 | * time described by a value of 1 in the interrupt | 113 | * time described by a value of 1 in the interrupt |
| 114 | * coalescing registers' time fields. Since those fields | 114 | * coalescing registers' time fields. Since those fields |
| 115 | * refer to the time it takes for 64 clocks to pass, the | 115 | * refer to the time it takes for 64 clocks to pass, the |
| 116 | * latencies are as such: | 116 | * latencies are as such: |
| 117 | * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick | 117 | * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick |
| 118 | * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick | 118 | * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick |
| 119 | * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick | 119 | * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick |
| 120 | */ | 120 | */ |
| 121 | #define GFAR_GBIT_TIME 512 | 121 | #define GFAR_GBIT_TIME 512 |
| 122 | #define GFAR_100_TIME 2560 | 122 | #define GFAR_100_TIME 2560 |
| 123 | #define GFAR_10_TIME 25600 | 123 | #define GFAR_10_TIME 25600 |
| 124 | 124 | ||
| 125 | #define DEFAULT_TX_COALESCE 1 | 125 | #define DEFAULT_TX_COALESCE 1 |
| 126 | #define DEFAULT_TXCOUNT 16 | 126 | #define DEFAULT_TXCOUNT 16 |
| 127 | #define DEFAULT_TXTIME 4 | 127 | #define DEFAULT_TXTIME 4 |
| 128 | 128 | ||
| 129 | #define DEFAULT_RX_COALESCE 1 | 129 | #define DEFAULT_RX_COALESCE 1 |
| 130 | #define DEFAULT_RXCOUNT 16 | 130 | #define DEFAULT_RXCOUNT 16 |
| 131 | #define DEFAULT_RXTIME 4 | 131 | #define DEFAULT_RXTIME 4 |
| 132 | 132 | ||
| 133 | #define TBIPA_VALUE 0x1f | 133 | #define TBIPA_VALUE 0x1f |
| 134 | #define MIIMCFG_INIT_VALUE 0x00000007 | 134 | #define MIIMCFG_INIT_VALUE 0x00000007 |
| 135 | #define MIIMCFG_RESET 0x80000000 | 135 | #define MIIMCFG_RESET 0x80000000 |
| 136 | #define MIIMIND_BUSY 0x00000001 | 136 | #define MIIMIND_BUSY 0x00000001 |
| 137 | 137 | ||
| 138 | /* TBI register addresses */ | 138 | /* TBI register addresses */ |
| 139 | #define MII_TBICON 0x11 | 139 | #define MII_TBICON 0x11 |
| 140 | 140 | ||
| 141 | /* TBICON register bit fields */ | 141 | /* TBICON register bit fields */ |
| 142 | #define TBICON_CLK_SELECT 0x0020 | 142 | #define TBICON_CLK_SELECT 0x0020 |
| 143 | 143 | ||
| 144 | /* MAC register bits */ | 144 | /* MAC register bits */ |
| 145 | #define MACCFG1_SOFT_RESET 0x80000000 | 145 | #define MACCFG1_SOFT_RESET 0x80000000 |
| 146 | #define MACCFG1_RESET_RX_MC 0x00080000 | 146 | #define MACCFG1_RESET_RX_MC 0x00080000 |
| 147 | #define MACCFG1_RESET_TX_MC 0x00040000 | 147 | #define MACCFG1_RESET_TX_MC 0x00040000 |
| 148 | #define MACCFG1_RESET_RX_FUN 0x00020000 | 148 | #define MACCFG1_RESET_RX_FUN 0x00020000 |
| 149 | #define MACCFG1_RESET_TX_FUN 0x00010000 | 149 | #define MACCFG1_RESET_TX_FUN 0x00010000 |
| 150 | #define MACCFG1_LOOPBACK 0x00000100 | 150 | #define MACCFG1_LOOPBACK 0x00000100 |
| 151 | #define MACCFG1_RX_FLOW 0x00000020 | 151 | #define MACCFG1_RX_FLOW 0x00000020 |
| 152 | #define MACCFG1_TX_FLOW 0x00000010 | 152 | #define MACCFG1_TX_FLOW 0x00000010 |
| 153 | #define MACCFG1_SYNCD_RX_EN 0x00000008 | 153 | #define MACCFG1_SYNCD_RX_EN 0x00000008 |
| 154 | #define MACCFG1_RX_EN 0x00000004 | 154 | #define MACCFG1_RX_EN 0x00000004 |
| 155 | #define MACCFG1_SYNCD_TX_EN 0x00000002 | 155 | #define MACCFG1_SYNCD_TX_EN 0x00000002 |
| 156 | #define MACCFG1_TX_EN 0x00000001 | 156 | #define MACCFG1_TX_EN 0x00000001 |
| 157 | 157 | ||
| 158 | #define MACCFG2_INIT_SETTINGS 0x00007205 | 158 | #define MACCFG2_INIT_SETTINGS 0x00007205 |
| 159 | #define MACCFG2_FULL_DUPLEX 0x00000001 | 159 | #define MACCFG2_FULL_DUPLEX 0x00000001 |
| 160 | #define MACCFG2_IF 0x00000300 | 160 | #define MACCFG2_IF 0x00000300 |
| 161 | #define MACCFG2_MII 0x00000100 | 161 | #define MACCFG2_MII 0x00000100 |
| 162 | #define MACCFG2_GMII 0x00000200 | 162 | #define MACCFG2_GMII 0x00000200 |
| 163 | #define MACCFG2_HUGEFRAME 0x00000020 | 163 | #define MACCFG2_HUGEFRAME 0x00000020 |
| 164 | #define MACCFG2_LENGTHCHECK 0x00000010 | 164 | #define MACCFG2_LENGTHCHECK 0x00000010 |
| 165 | 165 | ||
| 166 | #define ECNTRL_INIT_SETTINGS 0x00001000 | 166 | #define ECNTRL_INIT_SETTINGS 0x00001000 |
| 167 | #define ECNTRL_TBI_MODE 0x00000020 | 167 | #define ECNTRL_TBI_MODE 0x00000020 |
| 168 | #define ECNTRL_REDUCED_MODE 0x00000010 | 168 | #define ECNTRL_REDUCED_MODE 0x00000010 |
| 169 | #define ECNTRL_R100 0x00000008 | 169 | #define ECNTRL_R100 0x00000008 |
| 170 | #define ECNTRL_REDUCED_MII_MODE 0x00000004 | 170 | #define ECNTRL_REDUCED_MII_MODE 0x00000004 |
| 171 | #define ECNTRL_SGMII_MODE 0x00000002 | 171 | #define ECNTRL_SGMII_MODE 0x00000002 |
| 172 | 172 | ||
| 173 | #define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE | 173 | #define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE |
| 174 | 174 | ||
| 175 | #define MINFLR_INIT_SETTINGS 0x00000040 | 175 | #define MINFLR_INIT_SETTINGS 0x00000040 |
| 176 | 176 | ||
| 177 | /* Init to do tx snooping for buffers and descriptors */ | 177 | /* Init to do tx snooping for buffers and descriptors */ |
| 178 | #define DMACTRL_INIT_SETTINGS 0x000000c3 | 178 | #define DMACTRL_INIT_SETTINGS 0x000000c3 |
| 179 | #define DMACTRL_GRS 0x00000010 | 179 | #define DMACTRL_GRS 0x00000010 |
| 180 | #define DMACTRL_GTS 0x00000008 | 180 | #define DMACTRL_GTS 0x00000008 |
| 181 | 181 | ||
| 182 | #define TSTAT_CLEAR_THALT 0x80000000 | 182 | #define TSTAT_CLEAR_THALT 0x80000000 |
| 183 | 183 | ||
| 184 | /* Interrupt coalescing macros */ | 184 | /* Interrupt coalescing macros */ |
| 185 | #define IC_ICEN 0x80000000 | 185 | #define IC_ICEN 0x80000000 |
| 186 | #define IC_ICFT_MASK 0x1fe00000 | 186 | #define IC_ICFT_MASK 0x1fe00000 |
| 187 | #define IC_ICFT_SHIFT 21 | 187 | #define IC_ICFT_SHIFT 21 |
| 188 | #define mk_ic_icft(x) \ | 188 | #define mk_ic_icft(x) \ |
| 189 | (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK) | 189 | (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK) |
| 190 | #define IC_ICTT_MASK 0x0000ffff | 190 | #define IC_ICTT_MASK 0x0000ffff |
| 191 | #define mk_ic_ictt(x) (x&IC_ICTT_MASK) | 191 | #define mk_ic_ictt(x) (x&IC_ICTT_MASK) |
| 192 | 192 | ||
| 193 | #define mk_ic_value(count, time) (IC_ICEN | \ | 193 | #define mk_ic_value(count, time) (IC_ICEN | \ |
| 194 | mk_ic_icft(count) | \ | 194 | mk_ic_icft(count) | \ |
| 195 | mk_ic_ictt(time)) | 195 | mk_ic_ictt(time)) |
| 196 | 196 | ||
| 197 | #define RCTRL_PAL_MASK 0x001f0000 | 197 | #define RCTRL_PAL_MASK 0x001f0000 |
| 198 | #define RCTRL_VLEX 0x00002000 | 198 | #define RCTRL_VLEX 0x00002000 |
| 199 | #define RCTRL_FILREN 0x00001000 | 199 | #define RCTRL_FILREN 0x00001000 |
| 200 | #define RCTRL_GHTX 0x00000400 | 200 | #define RCTRL_GHTX 0x00000400 |
| 201 | #define RCTRL_IPCSEN 0x00000200 | 201 | #define RCTRL_IPCSEN 0x00000200 |
| 202 | #define RCTRL_TUCSEN 0x00000100 | 202 | #define RCTRL_TUCSEN 0x00000100 |
| 203 | #define RCTRL_PRSDEP_MASK 0x000000c0 | 203 | #define RCTRL_PRSDEP_MASK 0x000000c0 |
| 204 | #define RCTRL_PRSDEP_INIT 0x000000c0 | 204 | #define RCTRL_PRSDEP_INIT 0x000000c0 |
| 205 | #define RCTRL_PROM 0x00000008 | 205 | #define RCTRL_PROM 0x00000008 |
| 206 | #define RCTRL_EMEN 0x00000002 | 206 | #define RCTRL_EMEN 0x00000002 |
| 207 | #define RCTRL_CHECKSUMMING (RCTRL_IPCSEN \ | 207 | #define RCTRL_CHECKSUMMING (RCTRL_IPCSEN \ |
| 208 | | RCTRL_TUCSEN | RCTRL_PRSDEP_INIT) | 208 | | RCTRL_TUCSEN | RCTRL_PRSDEP_INIT) |
| 209 | #define RCTRL_EXTHASH (RCTRL_GHTX) | 209 | #define RCTRL_EXTHASH (RCTRL_GHTX) |
| 210 | #define RCTRL_VLAN (RCTRL_PRSDEP_INIT) | 210 | #define RCTRL_VLAN (RCTRL_PRSDEP_INIT) |
| 211 | #define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK) | 211 | #define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK) |
| 212 | 212 | ||
| 213 | 213 | ||
| 214 | #define RSTAT_CLEAR_RHALT 0x00800000 | 214 | #define RSTAT_CLEAR_RHALT 0x00800000 |
| 215 | 215 | ||
| 216 | #define TCTRL_IPCSEN 0x00004000 | 216 | #define TCTRL_IPCSEN 0x00004000 |
| 217 | #define TCTRL_TUCSEN 0x00002000 | 217 | #define TCTRL_TUCSEN 0x00002000 |
| 218 | #define TCTRL_VLINS 0x00001000 | 218 | #define TCTRL_VLINS 0x00001000 |
| 219 | #define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN) | 219 | #define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN) |
| 220 | 220 | ||
| 221 | #define IEVENT_INIT_CLEAR 0xffffffff | 221 | #define IEVENT_INIT_CLEAR 0xffffffff |
| 222 | #define IEVENT_BABR 0x80000000 | 222 | #define IEVENT_BABR 0x80000000 |
| 223 | #define IEVENT_RXC 0x40000000 | 223 | #define IEVENT_RXC 0x40000000 |
| 224 | #define IEVENT_BSY 0x20000000 | 224 | #define IEVENT_BSY 0x20000000 |
| 225 | #define IEVENT_EBERR 0x10000000 | 225 | #define IEVENT_EBERR 0x10000000 |
| 226 | #define IEVENT_MSRO 0x04000000 | 226 | #define IEVENT_MSRO 0x04000000 |
| 227 | #define IEVENT_GTSC 0x02000000 | 227 | #define IEVENT_GTSC 0x02000000 |
| 228 | #define IEVENT_BABT 0x01000000 | 228 | #define IEVENT_BABT 0x01000000 |
| 229 | #define IEVENT_TXC 0x00800000 | 229 | #define IEVENT_TXC 0x00800000 |
| 230 | #define IEVENT_TXE 0x00400000 | 230 | #define IEVENT_TXE 0x00400000 |
| 231 | #define IEVENT_TXB 0x00200000 | 231 | #define IEVENT_TXB 0x00200000 |
| 232 | #define IEVENT_TXF 0x00100000 | 232 | #define IEVENT_TXF 0x00100000 |
| 233 | #define IEVENT_LC 0x00040000 | 233 | #define IEVENT_LC 0x00040000 |
| 234 | #define IEVENT_CRL 0x00020000 | 234 | #define IEVENT_CRL 0x00020000 |
| 235 | #define IEVENT_XFUN 0x00010000 | 235 | #define IEVENT_XFUN 0x00010000 |
| 236 | #define IEVENT_RXB0 0x00008000 | 236 | #define IEVENT_RXB0 0x00008000 |
| 237 | #define IEVENT_GRSC 0x00000100 | 237 | #define IEVENT_GRSC 0x00000100 |
| 238 | #define IEVENT_RXF0 0x00000080 | 238 | #define IEVENT_RXF0 0x00000080 |
| 239 | #define IEVENT_FIR 0x00000008 | 239 | #define IEVENT_FIR 0x00000008 |
| 240 | #define IEVENT_FIQ 0x00000004 | 240 | #define IEVENT_FIQ 0x00000004 |
| 241 | #define IEVENT_DPE 0x00000002 | 241 | #define IEVENT_DPE 0x00000002 |
| 242 | #define IEVENT_PERR 0x00000001 | 242 | #define IEVENT_PERR 0x00000001 |
| 243 | #define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0) | 243 | #define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0) |
| 244 | #define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF) | 244 | #define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF) |
| 245 | #define IEVENT_ERR_MASK \ | 245 | #define IEVENT_ERR_MASK \ |
| 246 | (IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \ | 246 | (IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \ |
| 247 | IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \ | 247 | IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \ |
| 248 | | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR) | 248 | | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR) |
| 249 | 249 | ||
| 250 | #define IMASK_INIT_CLEAR 0x00000000 | 250 | #define IMASK_INIT_CLEAR 0x00000000 |
| 251 | #define IMASK_BABR 0x80000000 | 251 | #define IMASK_BABR 0x80000000 |
| 252 | #define IMASK_RXC 0x40000000 | 252 | #define IMASK_RXC 0x40000000 |
| 253 | #define IMASK_BSY 0x20000000 | 253 | #define IMASK_BSY 0x20000000 |
| 254 | #define IMASK_EBERR 0x10000000 | 254 | #define IMASK_EBERR 0x10000000 |
| 255 | #define IMASK_MSRO 0x04000000 | 255 | #define IMASK_MSRO 0x04000000 |
| 256 | #define IMASK_GRSC 0x02000000 | 256 | #define IMASK_GRSC 0x02000000 |
| 257 | #define IMASK_BABT 0x01000000 | 257 | #define IMASK_BABT 0x01000000 |
| 258 | #define IMASK_TXC 0x00800000 | 258 | #define IMASK_TXC 0x00800000 |
| 259 | #define IMASK_TXEEN 0x00400000 | 259 | #define IMASK_TXEEN 0x00400000 |
| 260 | #define IMASK_TXBEN 0x00200000 | 260 | #define IMASK_TXBEN 0x00200000 |
| 261 | #define IMASK_TXFEN 0x00100000 | 261 | #define IMASK_TXFEN 0x00100000 |
| 262 | #define IMASK_LC 0x00040000 | 262 | #define IMASK_LC 0x00040000 |
| 263 | #define IMASK_CRL 0x00020000 | 263 | #define IMASK_CRL 0x00020000 |
| 264 | #define IMASK_XFUN 0x00010000 | 264 | #define IMASK_XFUN 0x00010000 |
| 265 | #define IMASK_RXB0 0x00008000 | 265 | #define IMASK_RXB0 0x00008000 |
| 266 | #define IMASK_GTSC 0x00000100 | 266 | #define IMASK_GTSC 0x00000100 |
| 267 | #define IMASK_RXFEN0 0x00000080 | 267 | #define IMASK_RXFEN0 0x00000080 |
| 268 | #define IMASK_FIR 0x00000008 | 268 | #define IMASK_FIR 0x00000008 |
| 269 | #define IMASK_FIQ 0x00000004 | 269 | #define IMASK_FIQ 0x00000004 |
| 270 | #define IMASK_DPE 0x00000002 | 270 | #define IMASK_DPE 0x00000002 |
| 271 | #define IMASK_PERR 0x00000001 | 271 | #define IMASK_PERR 0x00000001 |
| 272 | #define IMASK_RX_DISABLED ~(IMASK_RXFEN0 | IMASK_BSY) | 272 | #define IMASK_RX_DISABLED ~(IMASK_RXFEN0 | IMASK_BSY) |
| 273 | #define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \ | 273 | #define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \ |
| 274 | IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \ | 274 | IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \ |
| 275 | IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \ | 275 | IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \ |
| 276 | | IMASK_PERR) | 276 | | IMASK_PERR) |
| 277 | 277 | ||
| 278 | /* Fifo management */ | 278 | /* Fifo management */ |
| 279 | #define FIFO_TX_THR_MASK 0x01ff | 279 | #define FIFO_TX_THR_MASK 0x01ff |
| 280 | #define FIFO_TX_STARVE_MASK 0x01ff | 280 | #define FIFO_TX_STARVE_MASK 0x01ff |
| 281 | #define FIFO_TX_STARVE_OFF_MASK 0x01ff | 281 | #define FIFO_TX_STARVE_OFF_MASK 0x01ff |
| 282 | 282 | ||
| 283 | /* Attribute fields */ | 283 | /* Attribute fields */ |
| 284 | 284 | ||
| 285 | /* This enables rx snooping for buffers and descriptors */ | 285 | /* This enables rx snooping for buffers and descriptors */ |
| 286 | #define ATTR_BDSTASH 0x00000800 | 286 | #define ATTR_BDSTASH 0x00000800 |
| 287 | 287 | ||
| 288 | #define ATTR_BUFSTASH 0x00004000 | 288 | #define ATTR_BUFSTASH 0x00004000 |
| 289 | 289 | ||
| 290 | #define ATTR_SNOOPING 0x000000c0 | 290 | #define ATTR_SNOOPING 0x000000c0 |
| 291 | #define ATTR_INIT_SETTINGS ATTR_SNOOPING | 291 | #define ATTR_INIT_SETTINGS ATTR_SNOOPING |
| 292 | 292 | ||
| 293 | #define ATTRELI_INIT_SETTINGS 0x0 | 293 | #define ATTRELI_INIT_SETTINGS 0x0 |
| 294 | #define ATTRELI_EL_MASK 0x3fff0000 | 294 | #define ATTRELI_EL_MASK 0x3fff0000 |
| 295 | #define ATTRELI_EL(x) (x << 16) | 295 | #define ATTRELI_EL(x) (x << 16) |
| 296 | #define ATTRELI_EI_MASK 0x00003fff | 296 | #define ATTRELI_EI_MASK 0x00003fff |
| 297 | #define ATTRELI_EI(x) (x) | 297 | #define ATTRELI_EI(x) (x) |
| 298 | 298 | ||
| 299 | 299 | ||
| 300 | /* TxBD status field bits */ | 300 | /* TxBD status field bits */ |
| 301 | #define TXBD_READY 0x8000 | 301 | #define TXBD_READY 0x8000 |
| 302 | #define TXBD_PADCRC 0x4000 | 302 | #define TXBD_PADCRC 0x4000 |
| 303 | #define TXBD_WRAP 0x2000 | 303 | #define TXBD_WRAP 0x2000 |
| 304 | #define TXBD_INTERRUPT 0x1000 | 304 | #define TXBD_INTERRUPT 0x1000 |
| 305 | #define TXBD_LAST 0x0800 | 305 | #define TXBD_LAST 0x0800 |
| 306 | #define TXBD_CRC 0x0400 | 306 | #define TXBD_CRC 0x0400 |
| 307 | #define TXBD_DEF 0x0200 | 307 | #define TXBD_DEF 0x0200 |
| 308 | #define TXBD_HUGEFRAME 0x0080 | 308 | #define TXBD_HUGEFRAME 0x0080 |
| 309 | #define TXBD_LATECOLLISION 0x0080 | 309 | #define TXBD_LATECOLLISION 0x0080 |
| 310 | #define TXBD_RETRYLIMIT 0x0040 | 310 | #define TXBD_RETRYLIMIT 0x0040 |
| 311 | #define TXBD_RETRYCOUNTMASK 0x003c | 311 | #define TXBD_RETRYCOUNTMASK 0x003c |
| 312 | #define TXBD_UNDERRUN 0x0002 | 312 | #define TXBD_UNDERRUN 0x0002 |
| 313 | #define TXBD_TOE 0x0002 | 313 | #define TXBD_TOE 0x0002 |
| 314 | 314 | ||
| 315 | /* Tx FCB param bits */ | 315 | /* Tx FCB param bits */ |
| 316 | #define TXFCB_VLN 0x80 | 316 | #define TXFCB_VLN 0x80 |
| 317 | #define TXFCB_IP 0x40 | 317 | #define TXFCB_IP 0x40 |
| 318 | #define TXFCB_IP6 0x20 | 318 | #define TXFCB_IP6 0x20 |
| 319 | #define TXFCB_TUP 0x10 | 319 | #define TXFCB_TUP 0x10 |
| 320 | #define TXFCB_UDP 0x08 | 320 | #define TXFCB_UDP 0x08 |
| 321 | #define TXFCB_CIP 0x04 | 321 | #define TXFCB_CIP 0x04 |
| 322 | #define TXFCB_CTU 0x02 | 322 | #define TXFCB_CTU 0x02 |
| 323 | #define TXFCB_NPH 0x01 | 323 | #define TXFCB_NPH 0x01 |
| 324 | #define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH) | 324 | #define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH) |
| 325 | 325 | ||
| 326 | /* RxBD status field bits */ | 326 | /* RxBD status field bits */ |
| 327 | #define RXBD_EMPTY 0x8000 | 327 | #define RXBD_EMPTY 0x8000 |
| 328 | #define RXBD_RO1 0x4000 | 328 | #define RXBD_RO1 0x4000 |
| 329 | #define RXBD_WRAP 0x2000 | 329 | #define RXBD_WRAP 0x2000 |
| 330 | #define RXBD_INTERRUPT 0x1000 | 330 | #define RXBD_INTERRUPT 0x1000 |
| 331 | #define RXBD_LAST 0x0800 | 331 | #define RXBD_LAST 0x0800 |
| 332 | #define RXBD_FIRST 0x0400 | 332 | #define RXBD_FIRST 0x0400 |
| 333 | #define RXBD_MISS 0x0100 | 333 | #define RXBD_MISS 0x0100 |
| 334 | #define RXBD_BROADCAST 0x0080 | 334 | #define RXBD_BROADCAST 0x0080 |
| 335 | #define RXBD_MULTICAST 0x0040 | 335 | #define RXBD_MULTICAST 0x0040 |
| 336 | #define RXBD_LARGE 0x0020 | 336 | #define RXBD_LARGE 0x0020 |
| 337 | #define RXBD_NONOCTET 0x0010 | 337 | #define RXBD_NONOCTET 0x0010 |
| 338 | #define RXBD_SHORT 0x0008 | 338 | #define RXBD_SHORT 0x0008 |
| 339 | #define RXBD_CRCERR 0x0004 | 339 | #define RXBD_CRCERR 0x0004 |
| 340 | #define RXBD_OVERRUN 0x0002 | 340 | #define RXBD_OVERRUN 0x0002 |
| 341 | #define RXBD_TRUNCATED 0x0001 | 341 | #define RXBD_TRUNCATED 0x0001 |
| 342 | #define RXBD_STATS 0x01ff | 342 | #define RXBD_STATS 0x01ff |
| 343 | 343 | ||
| 344 | /* Rx FCB status field bits */ | 344 | /* Rx FCB status field bits */ |
| 345 | #define RXFCB_VLN 0x8000 | 345 | #define RXFCB_VLN 0x8000 |
| 346 | #define RXFCB_IP 0x4000 | 346 | #define RXFCB_IP 0x4000 |
| 347 | #define RXFCB_IP6 0x2000 | 347 | #define RXFCB_IP6 0x2000 |
| 348 | #define RXFCB_TUP 0x1000 | 348 | #define RXFCB_TUP 0x1000 |
| 349 | #define RXFCB_CIP 0x0800 | 349 | #define RXFCB_CIP 0x0800 |
| 350 | #define RXFCB_CTU 0x0400 | 350 | #define RXFCB_CTU 0x0400 |
| 351 | #define RXFCB_EIP 0x0200 | 351 | #define RXFCB_EIP 0x0200 |
| 352 | #define RXFCB_ETU 0x0100 | 352 | #define RXFCB_ETU 0x0100 |
| 353 | #define RXFCB_CSUM_MASK 0x0f00 | 353 | #define RXFCB_CSUM_MASK 0x0f00 |
| 354 | #define RXFCB_PERR_MASK 0x000c | 354 | #define RXFCB_PERR_MASK 0x000c |
| 355 | #define RXFCB_PERR_BADL3 0x0008 | 355 | #define RXFCB_PERR_BADL3 0x0008 |
| 356 | 356 | ||
| 357 | struct txbd8 | 357 | struct txbd8 |
| 358 | { | 358 | { |
| 359 | u16 status; /* Status Fields */ | 359 | u16 status; /* Status Fields */ |
| 360 | u16 length; /* Buffer length */ | 360 | u16 length; /* Buffer length */ |
| 361 | u32 bufPtr; /* Buffer Pointer */ | 361 | u32 bufPtr; /* Buffer Pointer */ |
| 362 | }; | 362 | }; |
| 363 | 363 | ||
| 364 | struct txfcb { | 364 | struct txfcb { |
| 365 | u8 flags; | 365 | u8 flags; |
| 366 | u8 reserved; | 366 | u8 reserved; |
| 367 | u8 l4os; /* Level 4 Header Offset */ | 367 | u8 l4os; /* Level 4 Header Offset */ |
| 368 | u8 l3os; /* Level 3 Header Offset */ | 368 | u8 l3os; /* Level 3 Header Offset */ |
| 369 | u16 phcs; /* Pseudo-header Checksum */ | 369 | u16 phcs; /* Pseudo-header Checksum */ |
| 370 | u16 vlctl; /* VLAN control word */ | 370 | u16 vlctl; /* VLAN control word */ |
| 371 | }; | 371 | }; |
| 372 | 372 | ||
| 373 | struct rxbd8 | 373 | struct rxbd8 |
| 374 | { | 374 | { |
| 375 | u16 status; /* Status Fields */ | 375 | u16 status; /* Status Fields */ |
| 376 | u16 length; /* Buffer Length */ | 376 | u16 length; /* Buffer Length */ |
| 377 | u32 bufPtr; /* Buffer Pointer */ | 377 | u32 bufPtr; /* Buffer Pointer */ |
| 378 | }; | 378 | }; |
| 379 | 379 | ||
| 380 | struct rxfcb { | 380 | struct rxfcb { |
| 381 | u16 flags; | 381 | u16 flags; |
| 382 | u8 rq; /* Receive Queue index */ | 382 | u8 rq; /* Receive Queue index */ |
| 383 | u8 pro; /* Layer 4 Protocol */ | 383 | u8 pro; /* Layer 4 Protocol */ |
| 384 | u16 reserved; | 384 | u16 reserved; |
| 385 | u16 vlctl; /* VLAN control word */ | 385 | u16 vlctl; /* VLAN control word */ |
| 386 | }; | 386 | }; |
| 387 | 387 | ||
| 388 | struct rmon_mib | 388 | struct rmon_mib |
| 389 | { | 389 | { |
| 390 | u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */ | 390 | u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */ |
| 391 | u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */ | 391 | u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */ |
| 392 | u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */ | 392 | u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */ |
| 393 | u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */ | 393 | u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */ |
| 394 | u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */ | 394 | u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */ |
| 395 | u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */ | 395 | u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */ |
| 396 | u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */ | 396 | u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */ |
| 397 | u32 rbyt; /* 0x.69c - Receive Byte Counter */ | 397 | u32 rbyt; /* 0x.69c - Receive Byte Counter */ |
| 398 | u32 rpkt; /* 0x.6a0 - Receive Packet Counter */ | 398 | u32 rpkt; /* 0x.6a0 - Receive Packet Counter */ |
| 399 | u32 rfcs; /* 0x.6a4 - Receive FCS Error Counter */ | 399 | u32 rfcs; /* 0x.6a4 - Receive FCS Error Counter */ |
| 400 | u32 rmca; /* 0x.6a8 - Receive Multicast Packet Counter */ | 400 | u32 rmca; /* 0x.6a8 - Receive Multicast Packet Counter */ |
| 401 | u32 rbca; /* 0x.6ac - Receive Broadcast Packet Counter */ | 401 | u32 rbca; /* 0x.6ac - Receive Broadcast Packet Counter */ |
| 402 | u32 rxcf; /* 0x.6b0 - Receive Control Frame Packet Counter */ | 402 | u32 rxcf; /* 0x.6b0 - Receive Control Frame Packet Counter */ |
| 403 | u32 rxpf; /* 0x.6b4 - Receive Pause Frame Packet Counter */ | 403 | u32 rxpf; /* 0x.6b4 - Receive Pause Frame Packet Counter */ |
| 404 | u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */ | 404 | u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */ |
| 405 | u32 raln; /* 0x.6bc - Receive Alignment Error Counter */ | 405 | u32 raln; /* 0x.6bc - Receive Alignment Error Counter */ |
| 406 | u32 rflr; /* 0x.6c0 - Receive Frame Length Error Counter */ | 406 | u32 rflr; /* 0x.6c0 - Receive Frame Length Error Counter */ |
| 407 | u32 rcde; /* 0x.6c4 - Receive Code Error Counter */ | 407 | u32 rcde; /* 0x.6c4 - Receive Code Error Counter */ |
| 408 | u32 rcse; /* 0x.6c8 - Receive Carrier Sense Error Counter */ | 408 | u32 rcse; /* 0x.6c8 - Receive Carrier Sense Error Counter */ |
| 409 | u32 rund; /* 0x.6cc - Receive Undersize Packet Counter */ | 409 | u32 rund; /* 0x.6cc - Receive Undersize Packet Counter */ |
| 410 | u32 rovr; /* 0x.6d0 - Receive Oversize Packet Counter */ | 410 | u32 rovr; /* 0x.6d0 - Receive Oversize Packet Counter */ |
| 411 | u32 rfrg; /* 0x.6d4 - Receive Fragments Counter */ | 411 | u32 rfrg; /* 0x.6d4 - Receive Fragments Counter */ |
| 412 | u32 rjbr; /* 0x.6d8 - Receive Jabber Counter */ | 412 | u32 rjbr; /* 0x.6d8 - Receive Jabber Counter */ |
| 413 | u32 rdrp; /* 0x.6dc - Receive Drop Counter */ | 413 | u32 rdrp; /* 0x.6dc - Receive Drop Counter */ |
| 414 | u32 tbyt; /* 0x.6e0 - Transmit Byte Counter Counter */ | 414 | u32 tbyt; /* 0x.6e0 - Transmit Byte Counter Counter */ |
| 415 | u32 tpkt; /* 0x.6e4 - Transmit Packet Counter */ | 415 | u32 tpkt; /* 0x.6e4 - Transmit Packet Counter */ |
| 416 | u32 tmca; /* 0x.6e8 - Transmit Multicast Packet Counter */ | 416 | u32 tmca; /* 0x.6e8 - Transmit Multicast Packet Counter */ |
| 417 | u32 tbca; /* 0x.6ec - Transmit Broadcast Packet Counter */ | 417 | u32 tbca; /* 0x.6ec - Transmit Broadcast Packet Counter */ |
| 418 | u32 txpf; /* 0x.6f0 - Transmit Pause Control Frame Counter */ | 418 | u32 txpf; /* 0x.6f0 - Transmit Pause Control Frame Counter */ |
| 419 | u32 tdfr; /* 0x.6f4 - Transmit Deferral Packet Counter */ | 419 | u32 tdfr; /* 0x.6f4 - Transmit Deferral Packet Counter */ |
| 420 | u32 tedf; /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */ | 420 | u32 tedf; /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */ |
| 421 | u32 tscl; /* 0x.6fc - Transmit Single Collision Packet Counter */ | 421 | u32 tscl; /* 0x.6fc - Transmit Single Collision Packet Counter */ |
| 422 | u32 tmcl; /* 0x.700 - Transmit Multiple Collision Packet Counter */ | 422 | u32 tmcl; /* 0x.700 - Transmit Multiple Collision Packet Counter */ |
| 423 | u32 tlcl; /* 0x.704 - Transmit Late Collision Packet Counter */ | 423 | u32 tlcl; /* 0x.704 - Transmit Late Collision Packet Counter */ |
| 424 | u32 txcl; /* 0x.708 - Transmit Excessive Collision Packet Counter */ | 424 | u32 txcl; /* 0x.708 - Transmit Excessive Collision Packet Counter */ |
| 425 | u32 tncl; /* 0x.70c - Transmit Total Collision Counter */ | 425 | u32 tncl; /* 0x.70c - Transmit Total Collision Counter */ |
| 426 | u8 res1[4]; | 426 | u8 res1[4]; |
| 427 | u32 tdrp; /* 0x.714 - Transmit Drop Frame Counter */ | 427 | u32 tdrp; /* 0x.714 - Transmit Drop Frame Counter */ |
| 428 | u32 tjbr; /* 0x.718 - Transmit Jabber Frame Counter */ | 428 | u32 tjbr; /* 0x.718 - Transmit Jabber Frame Counter */ |
| 429 | u32 tfcs; /* 0x.71c - Transmit FCS Error Counter */ | 429 | u32 tfcs; /* 0x.71c - Transmit FCS Error Counter */ |
| 430 | u32 txcf; /* 0x.720 - Transmit Control Frame Counter */ | 430 | u32 txcf; /* 0x.720 - Transmit Control Frame Counter */ |
| 431 | u32 tovr; /* 0x.724 - Transmit Oversize Frame Counter */ | 431 | u32 tovr; /* 0x.724 - Transmit Oversize Frame Counter */ |
| 432 | u32 tund; /* 0x.728 - Transmit Undersize Frame Counter */ | 432 | u32 tund; /* 0x.728 - Transmit Undersize Frame Counter */ |
| 433 | u32 tfrg; /* 0x.72c - Transmit Fragments Frame Counter */ | 433 | u32 tfrg; /* 0x.72c - Transmit Fragments Frame Counter */ |
| 434 | u32 car1; /* 0x.730 - Carry Register One */ | 434 | u32 car1; /* 0x.730 - Carry Register One */ |
| 435 | u32 car2; /* 0x.734 - Carry Register Two */ | 435 | u32 car2; /* 0x.734 - Carry Register Two */ |
| 436 | u32 cam1; /* 0x.738 - Carry Mask Register One */ | 436 | u32 cam1; /* 0x.738 - Carry Mask Register One */ |
| 437 | u32 cam2; /* 0x.73c - Carry Mask Register Two */ | 437 | u32 cam2; /* 0x.73c - Carry Mask Register Two */ |
| 438 | }; | 438 | }; |
| 439 | 439 | ||
| 440 | struct gfar_extra_stats { | 440 | struct gfar_extra_stats { |
| 441 | u64 kernel_dropped; | 441 | u64 kernel_dropped; |
| 442 | u64 rx_large; | 442 | u64 rx_large; |
| 443 | u64 rx_short; | 443 | u64 rx_short; |
| 444 | u64 rx_nonoctet; | 444 | u64 rx_nonoctet; |
| 445 | u64 rx_crcerr; | 445 | u64 rx_crcerr; |
| 446 | u64 rx_overrun; | 446 | u64 rx_overrun; |
| 447 | u64 rx_bsy; | 447 | u64 rx_bsy; |
| 448 | u64 rx_babr; | 448 | u64 rx_babr; |
| 449 | u64 rx_trunc; | 449 | u64 rx_trunc; |
| 450 | u64 eberr; | 450 | u64 eberr; |
| 451 | u64 tx_babt; | 451 | u64 tx_babt; |
| 452 | u64 tx_underrun; | 452 | u64 tx_underrun; |
| 453 | u64 rx_skbmissing; | 453 | u64 rx_skbmissing; |
| 454 | u64 tx_timeout; | 454 | u64 tx_timeout; |
| 455 | }; | 455 | }; |
| 456 | 456 | ||
| 457 | #define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32)) | 457 | #define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32)) |
| 458 | #define GFAR_EXTRA_STATS_LEN (sizeof(struct gfar_extra_stats)/sizeof(u64)) | 458 | #define GFAR_EXTRA_STATS_LEN (sizeof(struct gfar_extra_stats)/sizeof(u64)) |
| 459 | 459 | ||
| 460 | /* Number of stats in the stats structure (ignore car and cam regs)*/ | 460 | /* Number of stats in the stats structure (ignore car and cam regs)*/ |
| 461 | #define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN) | 461 | #define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN) |
| 462 | 462 | ||
| 463 | #define GFAR_INFOSTR_LEN 32 | 463 | #define GFAR_INFOSTR_LEN 32 |
| 464 | 464 | ||
| 465 | struct gfar_stats { | 465 | struct gfar_stats { |
| 466 | u64 extra[GFAR_EXTRA_STATS_LEN]; | 466 | u64 extra[GFAR_EXTRA_STATS_LEN]; |
| 467 | u64 rmon[GFAR_RMON_LEN]; | 467 | u64 rmon[GFAR_RMON_LEN]; |
| 468 | }; | 468 | }; |
| 469 | 469 | ||
| 470 | 470 | ||
| 471 | struct gfar { | 471 | struct gfar { |
| 472 | u32 tsec_id; /* 0x.000 - Controller ID register */ | 472 | u32 tsec_id; /* 0x.000 - Controller ID register */ |
| 473 | u8 res1[12]; | 473 | u8 res1[12]; |
| 474 | u32 ievent; /* 0x.010 - Interrupt Event Register */ | 474 | u32 ievent; /* 0x.010 - Interrupt Event Register */ |
| 475 | u32 imask; /* 0x.014 - Interrupt Mask Register */ | 475 | u32 imask; /* 0x.014 - Interrupt Mask Register */ |
| 476 | u32 edis; /* 0x.018 - Error Disabled Register */ | 476 | u32 edis; /* 0x.018 - Error Disabled Register */ |
| 477 | u8 res2[4]; | 477 | u8 res2[4]; |
| 478 | u32 ecntrl; /* 0x.020 - Ethernet Control Register */ | 478 | u32 ecntrl; /* 0x.020 - Ethernet Control Register */ |
| 479 | u32 minflr; /* 0x.024 - Minimum Frame Length Register */ | 479 | u32 minflr; /* 0x.024 - Minimum Frame Length Register */ |
| 480 | u32 ptv; /* 0x.028 - Pause Time Value Register */ | 480 | u32 ptv; /* 0x.028 - Pause Time Value Register */ |
| 481 | u32 dmactrl; /* 0x.02c - DMA Control Register */ | 481 | u32 dmactrl; /* 0x.02c - DMA Control Register */ |
| 482 | u32 tbipa; /* 0x.030 - TBI PHY Address Register */ | 482 | u32 tbipa; /* 0x.030 - TBI PHY Address Register */ |
| 483 | u8 res3[88]; | 483 | u8 res3[88]; |
| 484 | u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */ | 484 | u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */ |
| 485 | u8 res4[8]; | 485 | u8 res4[8]; |
| 486 | u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */ | 486 | u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */ |
| 487 | u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */ | 487 | u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */ |
| 488 | u8 res5[4]; | 488 | u8 res5[4]; |
| 489 | u32 fifo_rx_pause; /* 0x.0a4 - FIFO receive pause threshold register */ | 489 | u32 fifo_rx_pause; /* 0x.0a4 - FIFO receive pause threshold register */ |
| 490 | u32 fifo_rx_alarm; /* 0x.0a8 - FIFO receive alarm threshold register */ | 490 | u32 fifo_rx_alarm; /* 0x.0a8 - FIFO receive alarm threshold register */ |
| 491 | u8 res6[84]; | 491 | u8 res6[84]; |
| 492 | u32 tctrl; /* 0x.100 - Transmit Control Register */ | 492 | u32 tctrl; /* 0x.100 - Transmit Control Register */ |
| 493 | u32 tstat; /* 0x.104 - Transmit Status Register */ | 493 | u32 tstat; /* 0x.104 - Transmit Status Register */ |
| 494 | u32 dfvlan; /* 0x.108 - Default VLAN Control word */ | 494 | u32 dfvlan; /* 0x.108 - Default VLAN Control word */ |
| 495 | u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */ | 495 | u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */ |
| 496 | u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */ | 496 | u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */ |
| 497 | u32 tqueue; /* 0x.114 - Transmit queue control register */ | 497 | u32 tqueue; /* 0x.114 - Transmit queue control register */ |
| 498 | u8 res7[40]; | 498 | u8 res7[40]; |
| 499 | u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */ | 499 | u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */ |
| 500 | u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */ | 500 | u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */ |
| 501 | u8 res8[52]; | 501 | u8 res8[52]; |
| 502 | u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */ | 502 | u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */ |
| 503 | u8 res9a[4]; | 503 | u8 res9a[4]; |
| 504 | u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */ | 504 | u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */ |
| 505 | u8 res9b[4]; | 505 | u8 res9b[4]; |
| 506 | u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */ | 506 | u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */ |
| 507 | u8 res9c[4]; | 507 | u8 res9c[4]; |
| 508 | u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */ | 508 | u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */ |
| 509 | u8 res9d[4]; | 509 | u8 res9d[4]; |
| 510 | u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */ | 510 | u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */ |
| 511 | u8 res9e[4]; | 511 | u8 res9e[4]; |
| 512 | u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */ | 512 | u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */ |
| 513 | u8 res9f[4]; | 513 | u8 res9f[4]; |
| 514 | u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */ | 514 | u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */ |
| 515 | u8 res9g[4]; | 515 | u8 res9g[4]; |
| 516 | u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */ | 516 | u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */ |
| 517 | u8 res9h[4]; | 517 | u8 res9h[4]; |
| 518 | u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */ | 518 | u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */ |
| 519 | u8 res9[64]; | 519 | u8 res9[64]; |
| 520 | u32 tbaseh; /* 0x.200 - TxBD base address high */ | 520 | u32 tbaseh; /* 0x.200 - TxBD base address high */ |
| 521 | u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */ | 521 | u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */ |
| 522 | u8 res10a[4]; | 522 | u8 res10a[4]; |
| 523 | u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */ | 523 | u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */ |
| 524 | u8 res10b[4]; | 524 | u8 res10b[4]; |
| 525 | u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */ | 525 | u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */ |
| 526 | u8 res10c[4]; | 526 | u8 res10c[4]; |
| 527 | u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */ | 527 | u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */ |
| 528 | u8 res10d[4]; | 528 | u8 res10d[4]; |
| 529 | u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */ | 529 | u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */ |
| 530 | u8 res10e[4]; | 530 | u8 res10e[4]; |
| 531 | u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */ | 531 | u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */ |
| 532 | u8 res10f[4]; | 532 | u8 res10f[4]; |
| 533 | u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */ | 533 | u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */ |
| 534 | u8 res10g[4]; | 534 | u8 res10g[4]; |
| 535 | u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */ | 535 | u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */ |
| 536 | u8 res10[192]; | 536 | u8 res10[192]; |
| 537 | u32 rctrl; /* 0x.300 - Receive Control Register */ | 537 | u32 rctrl; /* 0x.300 - Receive Control Register */ |
| 538 | u32 rstat; /* 0x.304 - Receive Status Register */ | 538 | u32 rstat; /* 0x.304 - Receive Status Register */ |
| 539 | u8 res12[8]; | 539 | u8 res12[8]; |
| 540 | u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */ | 540 | u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */ |
| 541 | u32 rqueue; /* 0x.314 - Receive queue control register */ | 541 | u32 rqueue; /* 0x.314 - Receive queue control register */ |
| 542 | u8 res13[24]; | 542 | u8 res13[24]; |
| 543 | u32 rbifx; /* 0x.330 - Receive bit field extract control register */ | 543 | u32 rbifx; /* 0x.330 - Receive bit field extract control register */ |
| 544 | u32 rqfar; /* 0x.334 - Receive queue filing table address register */ | 544 | u32 rqfar; /* 0x.334 - Receive queue filing table address register */ |
| 545 | u32 rqfcr; /* 0x.338 - Receive queue filing table control register */ | 545 | u32 rqfcr; /* 0x.338 - Receive queue filing table control register */ |
| 546 | u32 rqfpr; /* 0x.33c - Receive queue filing table property register */ | 546 | u32 rqfpr; /* 0x.33c - Receive queue filing table property register */ |
| 547 | u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */ | 547 | u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */ |
| 548 | u8 res14[56]; | 548 | u8 res14[56]; |
| 549 | u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */ | 549 | u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */ |
| 550 | u8 res15a[4]; | 550 | u8 res15a[4]; |
| 551 | u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */ | 551 | u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */ |
| 552 | u8 res15b[4]; | 552 | u8 res15b[4]; |
| 553 | u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */ | 553 | u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */ |
| 554 | u8 res15c[4]; | 554 | u8 res15c[4]; |
| 555 | u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */ | 555 | u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */ |
| 556 | u8 res15d[4]; | 556 | u8 res15d[4]; |
| 557 | u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */ | 557 | u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */ |
| 558 | u8 res15e[4]; | 558 | u8 res15e[4]; |
| 559 | u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */ | 559 | u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */ |
| 560 | u8 res15f[4]; | 560 | u8 res15f[4]; |
| 561 | u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */ | 561 | u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */ |
| 562 | u8 res15g[4]; | 562 | u8 res15g[4]; |
| 563 | u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */ | 563 | u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */ |
| 564 | u8 res15h[4]; | 564 | u8 res15h[4]; |
| 565 | u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */ | 565 | u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */ |
| 566 | u8 res16[64]; | 566 | u8 res16[64]; |
| 567 | u32 rbaseh; /* 0x.400 - RxBD base address high */ | 567 | u32 rbaseh; /* 0x.400 - RxBD base address high */ |
| 568 | u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */ | 568 | u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */ |
| 569 | u8 res17a[4]; | 569 | u8 res17a[4]; |
| 570 | u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */ | 570 | u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */ |
| 571 | u8 res17b[4]; | 571 | u8 res17b[4]; |
| 572 | u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */ | 572 | u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */ |
| 573 | u8 res17c[4]; | 573 | u8 res17c[4]; |
| 574 | u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */ | 574 | u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */ |
| 575 | u8 res17d[4]; | 575 | u8 res17d[4]; |
| 576 | u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */ | 576 | u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */ |
| 577 | u8 res17e[4]; | 577 | u8 res17e[4]; |
| 578 | u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */ | 578 | u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */ |
| 579 | u8 res17f[4]; | 579 | u8 res17f[4]; |
| 580 | u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */ | 580 | u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */ |
| 581 | u8 res17g[4]; | 581 | u8 res17g[4]; |
| 582 | u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */ | 582 | u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */ |
| 583 | u8 res17[192]; | 583 | u8 res17[192]; |
| 584 | u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */ | 584 | u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */ |
| 585 | u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */ | 585 | u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */ |
| 586 | u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */ | 586 | u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */ |
| 587 | u32 hafdup; /* 0x.50c - Half Duplex Register */ | 587 | u32 hafdup; /* 0x.50c - Half Duplex Register */ |
| 588 | u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */ | 588 | u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */ |
| 589 | u8 res18[12]; | 589 | u8 res18[12]; |
| 590 | u8 gfar_mii_regs[24]; /* See gianfar_phy.h */ | 590 | u8 gfar_mii_regs[24]; /* See gianfar_phy.h */ |
| 591 | u8 res19[4]; | 591 | u8 res19[4]; |
| 592 | u32 ifstat; /* 0x.53c - Interface Status Register */ | 592 | u32 ifstat; /* 0x.53c - Interface Status Register */ |
| 593 | u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */ | 593 | u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */ |
| 594 | u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */ | 594 | u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */ |
| 595 | u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */ | 595 | u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */ |
| 596 | u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */ | 596 | u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */ |
| 597 | u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */ | 597 | u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */ |
| 598 | u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */ | 598 | u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */ |
| 599 | u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */ | 599 | u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */ |
| 600 | u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */ | 600 | u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */ |
| 601 | u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */ | 601 | u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */ |
| 602 | u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */ | 602 | u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */ |
| 603 | u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */ | 603 | u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */ |
| 604 | u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */ | 604 | u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */ |
| 605 | u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */ | 605 | u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */ |
| 606 | u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */ | 606 | u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */ |
| 607 | u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */ | 607 | u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */ |
| 608 | u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */ | 608 | u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */ |
| 609 | u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */ | 609 | u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */ |
| 610 | u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */ | 610 | u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */ |
| 611 | u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */ | 611 | u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */ |
| 612 | u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */ | 612 | u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */ |
| 613 | u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/ | 613 | u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/ |
| 614 | u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/ | 614 | u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/ |
| 615 | u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/ | 615 | u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/ |
| 616 | u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/ | 616 | u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/ |
| 617 | u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/ | 617 | u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/ |
| 618 | u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/ | 618 | u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/ |
| 619 | u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/ | 619 | u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/ |
| 620 | u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/ | 620 | u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/ |
| 621 | u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/ | 621 | u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/ |
| 622 | u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/ | 622 | u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/ |
| 623 | u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/ | 623 | u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/ |
| 624 | u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/ | 624 | u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/ |
| 625 | u8 res20[192]; | 625 | u8 res20[192]; |
| 626 | struct rmon_mib rmon; /* 0x.680-0x.73c */ | 626 | struct rmon_mib rmon; /* 0x.680-0x.73c */ |
| 627 | u32 rrej; /* 0x.740 - Receive filer rejected packet counter */ | 627 | u32 rrej; /* 0x.740 - Receive filer rejected packet counter */ |
| 628 | u8 res21[188]; | 628 | u8 res21[188]; |
| 629 | u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/ | 629 | u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/ |
| 630 | u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/ | 630 | u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/ |
| 631 | u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/ | 631 | u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/ |
| 632 | u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/ | 632 | u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/ |
| 633 | u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/ | 633 | u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/ |
| 634 | u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/ | 634 | u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/ |
| 635 | u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/ | 635 | u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/ |
| 636 | u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/ | 636 | u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/ |
| 637 | u8 res22[96]; | 637 | u8 res22[96]; |
| 638 | u32 gaddr0; /* 0x.880 - Group address register 0 */ | 638 | u32 gaddr0; /* 0x.880 - Group address register 0 */ |
| 639 | u32 gaddr1; /* 0x.884 - Group address register 1 */ | 639 | u32 gaddr1; /* 0x.884 - Group address register 1 */ |
| 640 | u32 gaddr2; /* 0x.888 - Group address register 2 */ | 640 | u32 gaddr2; /* 0x.888 - Group address register 2 */ |
| 641 | u32 gaddr3; /* 0x.88c - Group address register 3 */ | 641 | u32 gaddr3; /* 0x.88c - Group address register 3 */ |
| 642 | u32 gaddr4; /* 0x.890 - Group address register 4 */ | 642 | u32 gaddr4; /* 0x.890 - Group address register 4 */ |
| 643 | u32 gaddr5; /* 0x.894 - Group address register 5 */ | 643 | u32 gaddr5; /* 0x.894 - Group address register 5 */ |
| 644 | u32 gaddr6; /* 0x.898 - Group address register 6 */ | 644 | u32 gaddr6; /* 0x.898 - Group address register 6 */ |
| 645 | u32 gaddr7; /* 0x.89c - Group address register 7 */ | 645 | u32 gaddr7; /* 0x.89c - Group address register 7 */ |
| 646 | u8 res23a[352]; | 646 | u8 res23a[352]; |
| 647 | u32 fifocfg; /* 0x.a00 - FIFO interface config register */ | 647 | u32 fifocfg; /* 0x.a00 - FIFO interface config register */ |
| 648 | u8 res23b[252]; | 648 | u8 res23b[252]; |
| 649 | u8 res23c[248]; | 649 | u8 res23c[248]; |
| 650 | u32 attr; /* 0x.bf8 - Attributes Register */ | 650 | u32 attr; /* 0x.bf8 - Attributes Register */ |
| 651 | u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */ | 651 | u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */ |
| 652 | u8 res24[1024]; | 652 | u8 res24[1024]; |
| 653 | 653 | ||
| 654 | }; | 654 | }; |
| 655 | 655 | ||
| 656 | /* Struct stolen almost completely (and shamelessly) from the FCC enet source | 656 | /* Struct stolen almost completely (and shamelessly) from the FCC enet source |
| 657 | * (Ok, that's not so true anymore, but there is a family resemblence) | 657 | * (Ok, that's not so true anymore, but there is a family resemblence) |
| 658 | * The GFAR buffer descriptors track the ring buffers. The rx_bd_base | 658 | * The GFAR buffer descriptors track the ring buffers. The rx_bd_base |
| 659 | * and tx_bd_base always point to the currently available buffer. | 659 | * and tx_bd_base always point to the currently available buffer. |
| 660 | * The dirty_tx tracks the current buffer that is being sent by the | 660 | * The dirty_tx tracks the current buffer that is being sent by the |
| 661 | * controller. The cur_tx and dirty_tx are equal under both completely | 661 | * controller. The cur_tx and dirty_tx are equal under both completely |
| 662 | * empty and completely full conditions. The empty/ready indicator in | 662 | * empty and completely full conditions. The empty/ready indicator in |
| 663 | * the buffer descriptor determines the actual condition. | 663 | * the buffer descriptor determines the actual condition. |
| 664 | */ | 664 | */ |
| 665 | struct gfar_private { | 665 | struct gfar_private { |
| 666 | /* Fields controlled by TX lock */ | 666 | /* Fields controlled by TX lock */ |
| 667 | spinlock_t txlock; | 667 | spinlock_t txlock; |
| 668 | 668 | ||
| 669 | /* Pointer to the array of skbuffs */ | 669 | /* Pointer to the array of skbuffs */ |
| 670 | struct sk_buff ** tx_skbuff; | 670 | struct sk_buff ** tx_skbuff; |
| 671 | 671 | ||
| 672 | /* next free skb in the array */ | 672 | /* next free skb in the array */ |
| 673 | u16 skb_curtx; | 673 | u16 skb_curtx; |
| 674 | 674 | ||
| 675 | /* First skb in line to be transmitted */ | 675 | /* First skb in line to be transmitted */ |
| 676 | u16 skb_dirtytx; | 676 | u16 skb_dirtytx; |
| 677 | 677 | ||
| 678 | /* Configuration info for the coalescing features */ | 678 | /* Configuration info for the coalescing features */ |
| 679 | unsigned char txcoalescing; | 679 | unsigned char txcoalescing; |
| 680 | unsigned short txcount; | 680 | unsigned short txcount; |
| 681 | unsigned short txtime; | 681 | unsigned short txtime; |
| 682 | 682 | ||
| 683 | /* Buffer descriptor pointers */ | 683 | /* Buffer descriptor pointers */ |
| 684 | struct txbd8 *tx_bd_base; /* First tx buffer descriptor */ | 684 | struct txbd8 *tx_bd_base; /* First tx buffer descriptor */ |
| 685 | struct txbd8 *cur_tx; /* Next free ring entry */ | 685 | struct txbd8 *cur_tx; /* Next free ring entry */ |
| 686 | struct txbd8 *dirty_tx; /* First buffer in line | 686 | struct txbd8 *dirty_tx; /* First buffer in line |
| 687 | to be transmitted */ | 687 | to be transmitted */ |
| 688 | unsigned int tx_ring_size; | 688 | unsigned int tx_ring_size; |
| 689 | 689 | ||
| 690 | /* RX Locked fields */ | 690 | /* RX Locked fields */ |
| 691 | spinlock_t rxlock; | 691 | spinlock_t rxlock; |
| 692 | 692 | ||
| 693 | struct net_device *dev; | 693 | struct net_device *dev; |
| 694 | struct napi_struct napi; | 694 | struct napi_struct napi; |
| 695 | 695 | ||
| 696 | /* skb array and index */ | 696 | /* skb array and index */ |
| 697 | struct sk_buff ** rx_skbuff; | 697 | struct sk_buff ** rx_skbuff; |
| 698 | u16 skb_currx; | 698 | u16 skb_currx; |
| 699 | 699 | ||
| 700 | /* RX Coalescing values */ | 700 | /* RX Coalescing values */ |
| 701 | unsigned char rxcoalescing; | 701 | unsigned char rxcoalescing; |
| 702 | unsigned short rxcount; | 702 | unsigned short rxcount; |
| 703 | unsigned short rxtime; | 703 | unsigned short rxtime; |
| 704 | 704 | ||
| 705 | struct rxbd8 *rx_bd_base; /* First Rx buffers */ | 705 | struct rxbd8 *rx_bd_base; /* First Rx buffers */ |
| 706 | struct rxbd8 *cur_rx; /* Next free rx ring entry */ | 706 | struct rxbd8 *cur_rx; /* Next free rx ring entry */ |
| 707 | 707 | ||
| 708 | /* RX parameters */ | 708 | /* RX parameters */ |
| 709 | unsigned int rx_ring_size; | 709 | unsigned int rx_ring_size; |
| 710 | unsigned int rx_buffer_size; | 710 | unsigned int rx_buffer_size; |
| 711 | unsigned int rx_stash_size; | 711 | unsigned int rx_stash_size; |
| 712 | unsigned int rx_stash_index; | 712 | unsigned int rx_stash_index; |
| 713 | 713 | ||
| 714 | struct vlan_group *vlgrp; | 714 | struct vlan_group *vlgrp; |
| 715 | 715 | ||
| 716 | /* Unprotected fields */ | 716 | /* Unprotected fields */ |
| 717 | /* Pointer to the GFAR memory mapped Registers */ | 717 | /* Pointer to the GFAR memory mapped Registers */ |
| 718 | struct gfar __iomem *regs; | 718 | struct gfar __iomem *regs; |
| 719 | 719 | ||
| 720 | /* Hash registers and their width */ | 720 | /* Hash registers and their width */ |
| 721 | u32 __iomem *hash_regs[16]; | 721 | u32 __iomem *hash_regs[16]; |
| 722 | int hash_width; | 722 | int hash_width; |
| 723 | 723 | ||
| 724 | /* global parameters */ | 724 | /* global parameters */ |
| 725 | unsigned int fifo_threshold; | 725 | unsigned int fifo_threshold; |
| 726 | unsigned int fifo_starve; | 726 | unsigned int fifo_starve; |
| 727 | unsigned int fifo_starve_off; | 727 | unsigned int fifo_starve_off; |
| 728 | 728 | ||
| 729 | unsigned char vlan_enable:1, | 729 | unsigned char vlan_enable:1, |
| 730 | rx_csum_enable:1, | 730 | rx_csum_enable:1, |
| 731 | extended_hash:1, | 731 | extended_hash:1, |
| 732 | bd_stash_en:1; | 732 | bd_stash_en:1; |
| 733 | unsigned short padding; | 733 | unsigned short padding; |
| 734 | 734 | ||
| 735 | unsigned int interruptTransmit; | 735 | unsigned int interruptTransmit; |
| 736 | unsigned int interruptReceive; | 736 | unsigned int interruptReceive; |
| 737 | unsigned int interruptError; | 737 | unsigned int interruptError; |
| 738 | 738 | ||
| 739 | /* info structure initialized by platform code */ | 739 | /* info structure initialized by platform code */ |
| 740 | struct gianfar_platform_data *einfo; | 740 | struct gianfar_platform_data *einfo; |
| 741 | 741 | ||
| 742 | /* PHY stuff */ | 742 | /* PHY stuff */ |
| 743 | struct phy_device *phydev; | 743 | struct phy_device *phydev; |
| 744 | struct mii_bus *mii_bus; | 744 | struct mii_bus *mii_bus; |
| 745 | int oldspeed; | 745 | int oldspeed; |
| 746 | int oldduplex; | 746 | int oldduplex; |
| 747 | int oldlink; | 747 | int oldlink; |
| 748 | 748 | ||
| 749 | uint32_t msg_enable; | 749 | uint32_t msg_enable; |
| 750 | 750 | ||
| 751 | /* Network Statistics */ | 751 | /* Network Statistics */ |
| 752 | struct net_device_stats stats; | ||
| 753 | struct gfar_extra_stats extra_stats; | 752 | struct gfar_extra_stats extra_stats; |
| 754 | }; | 753 | }; |
| 755 | 754 | ||
| 756 | static inline u32 gfar_read(volatile unsigned __iomem *addr) | 755 | static inline u32 gfar_read(volatile unsigned __iomem *addr) |
| 757 | { | 756 | { |
| 758 | u32 val; | 757 | u32 val; |
| 759 | val = in_be32(addr); | 758 | val = in_be32(addr); |
| 760 | return val; | 759 | return val; |
| 761 | } | 760 | } |
| 762 | 761 | ||
| 763 | static inline void gfar_write(volatile unsigned __iomem *addr, u32 val) | 762 | static inline void gfar_write(volatile unsigned __iomem *addr, u32 val) |
| 764 | { | 763 | { |
| 765 | out_be32(addr, val); | 764 | out_be32(addr, val); |
| 766 | } | 765 | } |
| 767 | 766 | ||
| 768 | extern irqreturn_t gfar_receive(int irq, void *dev_id); | 767 | extern irqreturn_t gfar_receive(int irq, void *dev_id); |
| 769 | extern int startup_gfar(struct net_device *dev); | 768 | extern int startup_gfar(struct net_device *dev); |
| 770 | extern void stop_gfar(struct net_device *dev); | 769 | extern void stop_gfar(struct net_device *dev); |
| 771 | extern void gfar_halt(struct net_device *dev); | 770 | extern void gfar_halt(struct net_device *dev); |
| 772 | extern void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev, | 771 | extern void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev, |
| 773 | int enable, u32 regnum, u32 read); | 772 | int enable, u32 regnum, u32 read); |
| 774 | void gfar_init_sysfs(struct net_device *dev); | 773 | void gfar_init_sysfs(struct net_device *dev); |
| 775 | 774 | ||
| 776 | #endif /* __GIANFAR_H */ | 775 | #endif /* __GIANFAR_H */ |
| 777 | 776 |