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Commit 6d53c3b71d32da665dc2742c1e8663741f27d3cd

Authored by Michal Simek
Committed by Greg Kroah-Hartman
1 parent 3240b48d49
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

tty: serial: uartlite: Support uartlite on big and little endian systems 

Use big and little endian accessors function to reflect system configuration.
Detection is done via control register in ulite_request_port.

Tested on Microblaze LE, BE, PPC440 and Arm zynq.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Showing 1 changed file with 79 additions and 22 deletions Inline Diff

drivers/tty/serial/uartlite.c
Diff comments   View file @ 6d53c3b
1 /* 1 /*
2 * uartlite.c: Serial driver for Xilinx uartlite serial controller 2 * uartlite.c: Serial driver for Xilinx uartlite serial controller
3 * 3 *
4 * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk> 4 * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk>
5 * Copyright (C) 2007 Secret Lab Technologies Ltd. 5 * Copyright (C) 2007 Secret Lab Technologies Ltd.
6 * 6 *
7 * This file is licensed under the terms of the GNU General Public License 7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any 8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied. 9 * kind, whether express or implied.
10 */ 10 */
11 11
12 #include <linux/platform_device.h> 12 #include <linux/platform_device.h>
13 #include <linux/module.h> 13 #include <linux/module.h>
14 #include <linux/console.h> 14 #include <linux/console.h>
15 #include <linux/serial.h> 15 #include <linux/serial.h>
16 #include <linux/serial_core.h> 16 #include <linux/serial_core.h>
17 #include <linux/tty.h> 17 #include <linux/tty.h>
18 #include <linux/tty_flip.h> 18 #include <linux/tty_flip.h>
19 #include <linux/delay.h> 19 #include <linux/delay.h>
20 #include <linux/interrupt.h> 20 #include <linux/interrupt.h>
21 #include <linux/init.h> 21 #include <linux/init.h>
22 #include <linux/io.h> 22 #include <linux/io.h>
23 #include <linux/of.h> 23 #include <linux/of.h>
24 #include <linux/of_address.h> 24 #include <linux/of_address.h>
25 #include <linux/of_device.h> 25 #include <linux/of_device.h>
26 #include <linux/of_platform.h> 26 #include <linux/of_platform.h>
27 27
28 #define ULITE_NAME "ttyUL" 28 #define ULITE_NAME "ttyUL"
29 #define ULITE_MAJOR 204 29 #define ULITE_MAJOR 204
30 #define ULITE_MINOR 187 30 #define ULITE_MINOR 187
31 #define ULITE_NR_UARTS 4 31 #define ULITE_NR_UARTS 4
32 32
33 /* --------------------------------------------------------------------- 33 /* ---------------------------------------------------------------------
34 * Register definitions 34 * Register definitions
35 * 35 *
36 * For register details see datasheet: 36 * For register details see datasheet:
37 * http://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf 37 * http://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf
38 */ 38 */
39 39
40 #define ULITE_RX 0x00 40 #define ULITE_RX 0x00
41 #define ULITE_TX 0x04 41 #define ULITE_TX 0x04
42 #define ULITE_STATUS 0x08 42 #define ULITE_STATUS 0x08
43 #define ULITE_CONTROL 0x0c 43 #define ULITE_CONTROL 0x0c
44 44
45 #define ULITE_REGION 16 45 #define ULITE_REGION 16
46 46
47 #define ULITE_STATUS_RXVALID 0x01 47 #define ULITE_STATUS_RXVALID 0x01
48 #define ULITE_STATUS_RXFULL 0x02 48 #define ULITE_STATUS_RXFULL 0x02
49 #define ULITE_STATUS_TXEMPTY 0x04 49 #define ULITE_STATUS_TXEMPTY 0x04
50 #define ULITE_STATUS_TXFULL 0x08 50 #define ULITE_STATUS_TXFULL 0x08
51 #define ULITE_STATUS_IE 0x10 51 #define ULITE_STATUS_IE 0x10
52 #define ULITE_STATUS_OVERRUN 0x20 52 #define ULITE_STATUS_OVERRUN 0x20
53 #define ULITE_STATUS_FRAME 0x40 53 #define ULITE_STATUS_FRAME 0x40
54 #define ULITE_STATUS_PARITY 0x80 54 #define ULITE_STATUS_PARITY 0x80
55 55
56 #define ULITE_CONTROL_RST_TX 0x01 56 #define ULITE_CONTROL_RST_TX 0x01
57 #define ULITE_CONTROL_RST_RX 0x02 57 #define ULITE_CONTROL_RST_RX 0x02
58 #define ULITE_CONTROL_IE 0x10 58 #define ULITE_CONTROL_IE 0x10
59 59
60 struct uartlite_reg_ops {
61 u32 (*in)(void __iomem *addr);
62 void (*out)(u32 val, void __iomem *addr);
63 };
60 64
65 static u32 uartlite_inbe32(void __iomem *addr)
66 {
67 return ioread32be(addr);
68 }
69
70 static void uartlite_outbe32(u32 val, void __iomem *addr)
71 {
72 iowrite32be(val, addr);
73 }
74
75 static struct uartlite_reg_ops uartlite_be = {
76 .in = uartlite_inbe32,
77 .out = uartlite_outbe32,
78 };
79
80 static u32 uartlite_inle32(void __iomem *addr)
81 {
82 return ioread32(addr);
83 }
84
85 static void uartlite_outle32(u32 val, void __iomem *addr)
86 {
87 iowrite32(val, addr);
88 }
89
90 static struct uartlite_reg_ops uartlite_le = {
91 .in = uartlite_inle32,
92 .out = uartlite_outle32,
93 };
94
95 static inline u32 uart_in32(u32 offset, struct uart_port *port)
96 {
97 struct uartlite_reg_ops *reg_ops = port->private_data;
98
99 return reg_ops->in(port->membase + offset);
100 }
101
102 static inline void uart_out32(u32 val, u32 offset, struct uart_port *port)
103 {
104 struct uartlite_reg_ops *reg_ops = port->private_data;
105
106 reg_ops->out(val, port->membase + offset);
107 }
108
61 static struct uart_port ulite_ports[ULITE_NR_UARTS]; 109 static struct uart_port ulite_ports[ULITE_NR_UARTS];
62 110
63 /* --------------------------------------------------------------------- 111 /* ---------------------------------------------------------------------
64 * Core UART driver operations 112 * Core UART driver operations
65 */ 113 */
66 114
67 static int ulite_receive(struct uart_port *port, int stat) 115 static int ulite_receive(struct uart_port *port, int stat)
68 { 116 {
69 struct tty_port *tport = &port->state->port; 117 struct tty_port *tport = &port->state->port;
70 unsigned char ch = 0; 118 unsigned char ch = 0;
71 char flag = TTY_NORMAL; 119 char flag = TTY_NORMAL;
72 120
73 if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN 121 if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
74 | ULITE_STATUS_FRAME)) == 0) 122 | ULITE_STATUS_FRAME)) == 0)
75 return 0; 123 return 0;
76 124
77 /* stats */ 125 /* stats */
78 if (stat & ULITE_STATUS_RXVALID) { 126 if (stat & ULITE_STATUS_RXVALID) {
79 port->icount.rx++; 127 port->icount.rx++;
80 ch = ioread32be(port->membase + ULITE_RX); 128 ch = uart_in32(ULITE_RX, port);
81 129
82 if (stat & ULITE_STATUS_PARITY) 130 if (stat & ULITE_STATUS_PARITY)
83 port->icount.parity++; 131 port->icount.parity++;
84 } 132 }
85 133
86 if (stat & ULITE_STATUS_OVERRUN) 134 if (stat & ULITE_STATUS_OVERRUN)
87 port->icount.overrun++; 135 port->icount.overrun++;
88 136
89 if (stat & ULITE_STATUS_FRAME) 137 if (stat & ULITE_STATUS_FRAME)
90 port->icount.frame++; 138 port->icount.frame++;
91 139
92 140
93 /* drop byte with parity error if IGNPAR specificed */ 141 /* drop byte with parity error if IGNPAR specificed */
94 if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY) 142 if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY)
95 stat &= ~ULITE_STATUS_RXVALID; 143 stat &= ~ULITE_STATUS_RXVALID;
96 144
97 stat &= port->read_status_mask; 145 stat &= port->read_status_mask;
98 146
99 if (stat & ULITE_STATUS_PARITY) 147 if (stat & ULITE_STATUS_PARITY)
100 flag = TTY_PARITY; 148 flag = TTY_PARITY;
101 149
102 150
103 stat &= ~port->ignore_status_mask; 151 stat &= ~port->ignore_status_mask;
104 152
105 if (stat & ULITE_STATUS_RXVALID) 153 if (stat & ULITE_STATUS_RXVALID)
106 tty_insert_flip_char(tport, ch, flag); 154 tty_insert_flip_char(tport, ch, flag);
107 155
108 if (stat & ULITE_STATUS_FRAME) 156 if (stat & ULITE_STATUS_FRAME)
109 tty_insert_flip_char(tport, 0, TTY_FRAME); 157 tty_insert_flip_char(tport, 0, TTY_FRAME);
110 158
111 if (stat & ULITE_STATUS_OVERRUN) 159 if (stat & ULITE_STATUS_OVERRUN)
112 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 160 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
113 161
114 return 1; 162 return 1;
115 } 163 }
116 164
117 static int ulite_transmit(struct uart_port *port, int stat) 165 static int ulite_transmit(struct uart_port *port, int stat)
118 { 166 {
119 struct circ_buf *xmit = &port->state->xmit; 167 struct circ_buf *xmit = &port->state->xmit;
120 168
121 if (stat & ULITE_STATUS_TXFULL) 169 if (stat & ULITE_STATUS_TXFULL)
122 return 0; 170 return 0;
123 171
124 if (port->x_char) { 172 if (port->x_char) {
125 iowrite32be(port->x_char, port->membase + ULITE_TX); 173 uart_out32(port->x_char, ULITE_TX, port);
126 port->x_char = 0; 174 port->x_char = 0;
127 port->icount.tx++; 175 port->icount.tx++;
128 return 1; 176 return 1;
129 } 177 }
130 178
131 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 179 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
132 return 0; 180 return 0;
133 181
134 iowrite32be(xmit->buf[xmit->tail], port->membase + ULITE_TX); 182 uart_out32(xmit->buf[xmit->tail], ULITE_TX, port);
135 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1); 183 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
136 port->icount.tx++; 184 port->icount.tx++;
137 185
138 /* wake up */ 186 /* wake up */
139 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 187 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
140 uart_write_wakeup(port); 188 uart_write_wakeup(port);
141 189
142 return 1; 190 return 1;
143 } 191 }
144 192
145 static irqreturn_t ulite_isr(int irq, void *dev_id) 193 static irqreturn_t ulite_isr(int irq, void *dev_id)
146 { 194 {
147 struct uart_port *port = dev_id; 195 struct uart_port *port = dev_id;
148 int busy, n = 0; 196 int busy, n = 0;
149 197
150 do { 198 do {
151 int stat = ioread32be(port->membase + ULITE_STATUS); 199 int stat = uart_in32(ULITE_STATUS, port);
152 busy = ulite_receive(port, stat); 200 busy = ulite_receive(port, stat);
153 busy |= ulite_transmit(port, stat); 201 busy |= ulite_transmit(port, stat);
154 n++; 202 n++;
155 } while (busy); 203 } while (busy);
156 204
157 /* work done? */ 205 /* work done? */
158 if (n > 1) { 206 if (n > 1) {
159 tty_flip_buffer_push(&port->state->port); 207 tty_flip_buffer_push(&port->state->port);
160 return IRQ_HANDLED; 208 return IRQ_HANDLED;
161 } else { 209 } else {
162 return IRQ_NONE; 210 return IRQ_NONE;
163 } 211 }
164 } 212 }
165 213
166 static unsigned int ulite_tx_empty(struct uart_port *port) 214 static unsigned int ulite_tx_empty(struct uart_port *port)
167 { 215 {
168 unsigned long flags; 216 unsigned long flags;
169 unsigned int ret; 217 unsigned int ret;
170 218
171 spin_lock_irqsave(&port->lock, flags); 219 spin_lock_irqsave(&port->lock, flags);
172 ret = ioread32be(port->membase + ULITE_STATUS); 220 ret = uart_in32(ULITE_STATUS, port);
173 spin_unlock_irqrestore(&port->lock, flags); 221 spin_unlock_irqrestore(&port->lock, flags);
174 222
175 return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0; 223 return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;
176 } 224 }
177 225
178 static unsigned int ulite_get_mctrl(struct uart_port *port) 226 static unsigned int ulite_get_mctrl(struct uart_port *port)
179 { 227 {
180 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 228 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
181 } 229 }
182 230
183 static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl) 231 static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl)
184 { 232 {
185 /* N/A */ 233 /* N/A */
186 } 234 }
187 235
188 static void ulite_stop_tx(struct uart_port *port) 236 static void ulite_stop_tx(struct uart_port *port)
189 { 237 {
190 /* N/A */ 238 /* N/A */
191 } 239 }
192 240
193 static void ulite_start_tx(struct uart_port *port) 241 static void ulite_start_tx(struct uart_port *port)
194 { 242 {
195 ulite_transmit(port, ioread32be(port->membase + ULITE_STATUS)); 243 ulite_transmit(port, uart_in32(ULITE_STATUS, port));
196 } 244 }
197 245
198 static void ulite_stop_rx(struct uart_port *port) 246 static void ulite_stop_rx(struct uart_port *port)
199 { 247 {
200 /* don't forward any more data (like !CREAD) */ 248 /* don't forward any more data (like !CREAD) */
201 port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY 249 port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
202 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; 250 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
203 } 251 }
204 252
205 static void ulite_enable_ms(struct uart_port *port) 253 static void ulite_enable_ms(struct uart_port *port)
206 { 254 {
207 /* N/A */ 255 /* N/A */
208 } 256 }
209 257
210 static void ulite_break_ctl(struct uart_port *port, int ctl) 258 static void ulite_break_ctl(struct uart_port *port, int ctl)
211 { 259 {
212 /* N/A */ 260 /* N/A */
213 } 261 }
214 262
215 static int ulite_startup(struct uart_port *port) 263 static int ulite_startup(struct uart_port *port)
216 { 264 {
217 int ret; 265 int ret;
218 266
219 ret = request_irq(port->irq, ulite_isr, IRQF_SHARED, "uartlite", port); 267 ret = request_irq(port->irq, ulite_isr, IRQF_SHARED, "uartlite", port);
220 if (ret) 268 if (ret)
221 return ret; 269 return ret;
222 270
223 iowrite32be(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX, 271 uart_out32(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX,
224 port->membase + ULITE_CONTROL); 272 ULITE_CONTROL, port);
225 iowrite32be(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL); 273 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port);
226 274
227 return 0; 275 return 0;
228 } 276 }
229 277
230 static void ulite_shutdown(struct uart_port *port) 278 static void ulite_shutdown(struct uart_port *port)
231 { 279 {
232 iowrite32be(0, port->membase + ULITE_CONTROL); 280 uart_out32(0, ULITE_CONTROL, port);
233 ioread32be(port->membase + ULITE_CONTROL); /* dummy */ 281 uart_in32(ULITE_CONTROL, port); /* dummy */
234 free_irq(port->irq, port); 282 free_irq(port->irq, port);
235 } 283 }
236 284
237 static void ulite_set_termios(struct uart_port *port, struct ktermios *termios, 285 static void ulite_set_termios(struct uart_port *port, struct ktermios *termios,
238 struct ktermios *old) 286 struct ktermios *old)
239 { 287 {
240 unsigned long flags; 288 unsigned long flags;
241 unsigned int baud; 289 unsigned int baud;
242 290
243 spin_lock_irqsave(&port->lock, flags); 291 spin_lock_irqsave(&port->lock, flags);
244 292
245 port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN 293 port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
246 | ULITE_STATUS_TXFULL; 294 | ULITE_STATUS_TXFULL;
247 295
248 if (termios->c_iflag & INPCK) 296 if (termios->c_iflag & INPCK)
249 port->read_status_mask |= 297 port->read_status_mask |=
250 ULITE_STATUS_PARITY | ULITE_STATUS_FRAME; 298 ULITE_STATUS_PARITY | ULITE_STATUS_FRAME;
251 299
252 port->ignore_status_mask = 0; 300 port->ignore_status_mask = 0;
253 if (termios->c_iflag & IGNPAR) 301 if (termios->c_iflag & IGNPAR)
254 port->ignore_status_mask |= ULITE_STATUS_PARITY 302 port->ignore_status_mask |= ULITE_STATUS_PARITY
255 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; 303 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
256 304
257 /* ignore all characters if CREAD is not set */ 305 /* ignore all characters if CREAD is not set */
258 if ((termios->c_cflag & CREAD) == 0) 306 if ((termios->c_cflag & CREAD) == 0)
259 port->ignore_status_mask |= 307 port->ignore_status_mask |=
260 ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY 308 ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
261 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; 309 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
262 310
263 /* update timeout */ 311 /* update timeout */
264 baud = uart_get_baud_rate(port, termios, old, 0, 460800); 312 baud = uart_get_baud_rate(port, termios, old, 0, 460800);
265 uart_update_timeout(port, termios->c_cflag, baud); 313 uart_update_timeout(port, termios->c_cflag, baud);
266 314
267 spin_unlock_irqrestore(&port->lock, flags); 315 spin_unlock_irqrestore(&port->lock, flags);
268 } 316 }
269 317
270 static const char *ulite_type(struct uart_port *port) 318 static const char *ulite_type(struct uart_port *port)
271 { 319 {
272 return port->type == PORT_UARTLITE ? "uartlite" : NULL; 320 return port->type == PORT_UARTLITE ? "uartlite" : NULL;
273 } 321 }
274 322
275 static void ulite_release_port(struct uart_port *port) 323 static void ulite_release_port(struct uart_port *port)
276 { 324 {
277 release_mem_region(port->mapbase, ULITE_REGION); 325 release_mem_region(port->mapbase, ULITE_REGION);
278 iounmap(port->membase); 326 iounmap(port->membase);
279 port->membase = NULL; 327 port->membase = NULL;
280 } 328 }
281 329
282 static int ulite_request_port(struct uart_port *port) 330 static int ulite_request_port(struct uart_port *port)
283 { 331 {
332 int ret;
333
284 pr_debug("ulite console: port=%p; port->mapbase=%llx\n", 334 pr_debug("ulite console: port=%p; port->mapbase=%llx\n",
285 port, (unsigned long long) port->mapbase); 335 port, (unsigned long long) port->mapbase);
286 336
287 if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) { 337 if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) {
288 dev_err(port->dev, "Memory region busy\n"); 338 dev_err(port->dev, "Memory region busy\n");
289 return -EBUSY; 339 return -EBUSY;
290 } 340 }
291 341
292 port->membase = ioremap(port->mapbase, ULITE_REGION); 342 port->membase = ioremap(port->mapbase, ULITE_REGION);
293 if (!port->membase) { 343 if (!port->membase) {
294 dev_err(port->dev, "Unable to map registers\n"); 344 dev_err(port->dev, "Unable to map registers\n");
295 release_mem_region(port->mapbase, ULITE_REGION); 345 release_mem_region(port->mapbase, ULITE_REGION);
296 return -EBUSY; 346 return -EBUSY;
297 } 347 }
298 348
349 port->private_data = &uartlite_be;
350 ret = uart_in32(ULITE_CONTROL, port);
351 uart_out32(ULITE_CONTROL_RST_TX, ULITE_CONTROL, port);
352 ret = uart_in32(ULITE_STATUS, port);
353 /* Endianess detection */
354 if ((ret & ULITE_STATUS_TXEMPTY) != ULITE_STATUS_TXEMPTY)
355 port->private_data = &uartlite_le;
356
299 return 0; 357 return 0;
300 } 358 }
301 359
302 static void ulite_config_port(struct uart_port *port, int flags) 360 static void ulite_config_port(struct uart_port *port, int flags)
303 { 361 {
304 if (!ulite_request_port(port)) 362 if (!ulite_request_port(port))
305 port->type = PORT_UARTLITE; 363 port->type = PORT_UARTLITE;
306 } 364 }
307 365
308 static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser) 366 static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser)
309 { 367 {
310 /* we don't want the core code to modify any port params */ 368 /* we don't want the core code to modify any port params */
311 return -EINVAL; 369 return -EINVAL;
312 } 370 }
313 371
314 #ifdef CONFIG_CONSOLE_POLL 372 #ifdef CONFIG_CONSOLE_POLL
315 static int ulite_get_poll_char(struct uart_port *port) 373 static int ulite_get_poll_char(struct uart_port *port)
316 { 374 {
317 if (!(ioread32be(port->membase + ULITE_STATUS) 375 if (!(uart_in32(ULITE_STATUS, port) & ULITE_STATUS_RXVALID))
318 & ULITE_STATUS_RXVALID))
319 return NO_POLL_CHAR; 376 return NO_POLL_CHAR;
320 377
321 return ioread32be(port->membase + ULITE_RX); 378 return uart_in32(ULITE_RX, port);
322 } 379 }
323 380
324 static void ulite_put_poll_char(struct uart_port *port, unsigned char ch) 381 static void ulite_put_poll_char(struct uart_port *port, unsigned char ch)
325 { 382 {
326 while (ioread32be(port->membase + ULITE_STATUS) & ULITE_STATUS_TXFULL) 383 while (uart_in32(ULITE_STATUS, port) & ULITE_STATUS_TXFULL)
327 cpu_relax(); 384 cpu_relax();
328 385
329 /* write char to device */ 386 /* write char to device */
330 iowrite32be(ch, port->membase + ULITE_TX); 387 uart_out32(ch, ULITE_TX, port);
331 } 388 }
332 #endif 389 #endif
333 390
334 static struct uart_ops ulite_ops = { 391 static struct uart_ops ulite_ops = {
335 .tx_empty = ulite_tx_empty, 392 .tx_empty = ulite_tx_empty,
336 .set_mctrl = ulite_set_mctrl, 393 .set_mctrl = ulite_set_mctrl,
337 .get_mctrl = ulite_get_mctrl, 394 .get_mctrl = ulite_get_mctrl,
338 .stop_tx = ulite_stop_tx, 395 .stop_tx = ulite_stop_tx,
339 .start_tx = ulite_start_tx, 396 .start_tx = ulite_start_tx,
340 .stop_rx = ulite_stop_rx, 397 .stop_rx = ulite_stop_rx,
341 .enable_ms = ulite_enable_ms, 398 .enable_ms = ulite_enable_ms,
342 .break_ctl = ulite_break_ctl, 399 .break_ctl = ulite_break_ctl,
343 .startup = ulite_startup, 400 .startup = ulite_startup,
344 .shutdown = ulite_shutdown, 401 .shutdown = ulite_shutdown,
345 .set_termios = ulite_set_termios, 402 .set_termios = ulite_set_termios,
346 .type = ulite_type, 403 .type = ulite_type,
347 .release_port = ulite_release_port, 404 .release_port = ulite_release_port,
348 .request_port = ulite_request_port, 405 .request_port = ulite_request_port,
349 .config_port = ulite_config_port, 406 .config_port = ulite_config_port,
350 .verify_port = ulite_verify_port, 407 .verify_port = ulite_verify_port,
351 #ifdef CONFIG_CONSOLE_POLL 408 #ifdef CONFIG_CONSOLE_POLL
352 .poll_get_char = ulite_get_poll_char, 409 .poll_get_char = ulite_get_poll_char,
353 .poll_put_char = ulite_put_poll_char, 410 .poll_put_char = ulite_put_poll_char,
354 #endif 411 #endif
355 }; 412 };
356 413
357 /* --------------------------------------------------------------------- 414 /* ---------------------------------------------------------------------
358 * Console driver operations 415 * Console driver operations
359 */ 416 */
360 417
361 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE 418 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
362 static void ulite_console_wait_tx(struct uart_port *port) 419 static void ulite_console_wait_tx(struct uart_port *port)
363 { 420 {
364 int i; 421 int i;
365 u8 val; 422 u8 val;
366 423
367 /* Spin waiting for TX fifo to have space available */ 424 /* Spin waiting for TX fifo to have space available */
368 for (i = 0; i < 100000; i++) { 425 for (i = 0; i < 100000; i++) {
369 val = ioread32be(port->membase + ULITE_STATUS); 426 val = uart_in32(ULITE_STATUS, port);
370 if ((val & ULITE_STATUS_TXFULL) == 0) 427 if ((val & ULITE_STATUS_TXFULL) == 0)
371 break; 428 break;
372 cpu_relax(); 429 cpu_relax();
373 } 430 }
374 } 431 }
375 432
376 static void ulite_console_putchar(struct uart_port *port, int ch) 433 static void ulite_console_putchar(struct uart_port *port, int ch)
377 { 434 {
378 ulite_console_wait_tx(port); 435 ulite_console_wait_tx(port);
379 iowrite32be(ch, port->membase + ULITE_TX); 436 uart_out32(ch, ULITE_TX, port);
380 } 437 }
381 438
382 static void ulite_console_write(struct console *co, const char *s, 439 static void ulite_console_write(struct console *co, const char *s,
383 unsigned int count) 440 unsigned int count)
384 { 441 {
385 struct uart_port *port = &ulite_ports[co->index]; 442 struct uart_port *port = &ulite_ports[co->index];
386 unsigned long flags; 443 unsigned long flags;
387 unsigned int ier; 444 unsigned int ier;
388 int locked = 1; 445 int locked = 1;
389 446
390 if (oops_in_progress) { 447 if (oops_in_progress) {
391 locked = spin_trylock_irqsave(&port->lock, flags); 448 locked = spin_trylock_irqsave(&port->lock, flags);
392 } else 449 } else
393 spin_lock_irqsave(&port->lock, flags); 450 spin_lock_irqsave(&port->lock, flags);
394 451
395 /* save and disable interrupt */ 452 /* save and disable interrupt */
396 ier = ioread32be(port->membase + ULITE_STATUS) & ULITE_STATUS_IE; 453 ier = uart_in32(ULITE_STATUS, port) & ULITE_STATUS_IE;
397 iowrite32be(0, port->membase + ULITE_CONTROL); 454 uart_out32(0, ULITE_CONTROL, port);
398 455
399 uart_console_write(port, s, count, ulite_console_putchar); 456 uart_console_write(port, s, count, ulite_console_putchar);
400 457
401 ulite_console_wait_tx(port); 458 ulite_console_wait_tx(port);
402 459
403 /* restore interrupt state */ 460 /* restore interrupt state */
404 if (ier) 461 if (ier)
405 iowrite32be(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL); 462 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port);
406 463
407 if (locked) 464 if (locked)
408 spin_unlock_irqrestore(&port->lock, flags); 465 spin_unlock_irqrestore(&port->lock, flags);
409 } 466 }
410 467
411 static int ulite_console_setup(struct console *co, char *options) 468 static int ulite_console_setup(struct console *co, char *options)
412 { 469 {
413 struct uart_port *port; 470 struct uart_port *port;
414 int baud = 9600; 471 int baud = 9600;
415 int bits = 8; 472 int bits = 8;
416 int parity = 'n'; 473 int parity = 'n';
417 int flow = 'n'; 474 int flow = 'n';
418 475
419 if (co->index < 0 || co->index >= ULITE_NR_UARTS) 476 if (co->index < 0 || co->index >= ULITE_NR_UARTS)
420 return -EINVAL; 477 return -EINVAL;
421 478
422 port = &ulite_ports[co->index]; 479 port = &ulite_ports[co->index];
423 480
424 /* Has the device been initialized yet? */ 481 /* Has the device been initialized yet? */
425 if (!port->mapbase) { 482 if (!port->mapbase) {
426 pr_debug("console on ttyUL%i not present\n", co->index); 483 pr_debug("console on ttyUL%i not present\n", co->index);
427 return -ENODEV; 484 return -ENODEV;
428 } 485 }
429 486
430 /* not initialized yet? */ 487 /* not initialized yet? */
431 if (!port->membase) { 488 if (!port->membase) {
432 if (ulite_request_port(port)) 489 if (ulite_request_port(port))
433 return -ENODEV; 490 return -ENODEV;
434 } 491 }
435 492
436 if (options) 493 if (options)
437 uart_parse_options(options, &baud, &parity, &bits, &flow); 494 uart_parse_options(options, &baud, &parity, &bits, &flow);
438 495
439 return uart_set_options(port, co, baud, parity, bits, flow); 496 return uart_set_options(port, co, baud, parity, bits, flow);
440 } 497 }
441 498
442 static struct uart_driver ulite_uart_driver; 499 static struct uart_driver ulite_uart_driver;
443 500
444 static struct console ulite_console = { 501 static struct console ulite_console = {
445 .name = ULITE_NAME, 502 .name = ULITE_NAME,
446 .write = ulite_console_write, 503 .write = ulite_console_write,
447 .device = uart_console_device, 504 .device = uart_console_device,
448 .setup = ulite_console_setup, 505 .setup = ulite_console_setup,
449 .flags = CON_PRINTBUFFER, 506 .flags = CON_PRINTBUFFER,
450 .index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */ 507 .index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */
451 .data = &ulite_uart_driver, 508 .data = &ulite_uart_driver,
452 }; 509 };
453 510
454 static int __init ulite_console_init(void) 511 static int __init ulite_console_init(void)
455 { 512 {
456 register_console(&ulite_console); 513 register_console(&ulite_console);
457 return 0; 514 return 0;
458 } 515 }
459 516
460 console_initcall(ulite_console_init); 517 console_initcall(ulite_console_init);
461 518
462 #endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */ 519 #endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */
463 520
464 static struct uart_driver ulite_uart_driver = { 521 static struct uart_driver ulite_uart_driver = {
465 .owner = THIS_MODULE, 522 .owner = THIS_MODULE,
466 .driver_name = "uartlite", 523 .driver_name = "uartlite",
467 .dev_name = ULITE_NAME, 524 .dev_name = ULITE_NAME,
468 .major = ULITE_MAJOR, 525 .major = ULITE_MAJOR,
469 .minor = ULITE_MINOR, 526 .minor = ULITE_MINOR,
470 .nr = ULITE_NR_UARTS, 527 .nr = ULITE_NR_UARTS,
471 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE 528 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
472 .cons = &ulite_console, 529 .cons = &ulite_console,
473 #endif 530 #endif
474 }; 531 };
475 532
476 /* --------------------------------------------------------------------- 533 /* ---------------------------------------------------------------------
477 * Port assignment functions (mapping devices to uart_port structures) 534 * Port assignment functions (mapping devices to uart_port structures)
478 */ 535 */
479 536
480 /** ulite_assign: register a uartlite device with the driver 537 /** ulite_assign: register a uartlite device with the driver
481 * 538 *
482 * @dev: pointer to device structure 539 * @dev: pointer to device structure
483 * @id: requested id number. Pass -1 for automatic port assignment 540 * @id: requested id number. Pass -1 for automatic port assignment
484 * @base: base address of uartlite registers 541 * @base: base address of uartlite registers
485 * @irq: irq number for uartlite 542 * @irq: irq number for uartlite
486 * 543 *
487 * Returns: 0 on success, <0 otherwise 544 * Returns: 0 on success, <0 otherwise
488 */ 545 */
489 static int ulite_assign(struct device *dev, int id, u32 base, int irq) 546 static int ulite_assign(struct device *dev, int id, u32 base, int irq)
490 { 547 {
491 struct uart_port *port; 548 struct uart_port *port;
492 int rc; 549 int rc;
493 550
494 /* if id = -1; then scan for a free id and use that */ 551 /* if id = -1; then scan for a free id and use that */
495 if (id < 0) { 552 if (id < 0) {
496 for (id = 0; id < ULITE_NR_UARTS; id++) 553 for (id = 0; id < ULITE_NR_UARTS; id++)
497 if (ulite_ports[id].mapbase == 0) 554 if (ulite_ports[id].mapbase == 0)
498 break; 555 break;
499 } 556 }
500 if (id < 0 || id >= ULITE_NR_UARTS) { 557 if (id < 0 || id >= ULITE_NR_UARTS) {
501 dev_err(dev, "%s%i too large\n", ULITE_NAME, id); 558 dev_err(dev, "%s%i too large\n", ULITE_NAME, id);
502 return -EINVAL; 559 return -EINVAL;
503 } 560 }
504 561
505 if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) { 562 if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) {
506 dev_err(dev, "cannot assign to %s%i; it is already in use\n", 563 dev_err(dev, "cannot assign to %s%i; it is already in use\n",
507 ULITE_NAME, id); 564 ULITE_NAME, id);
508 return -EBUSY; 565 return -EBUSY;
509 } 566 }
510 567
511 port = &ulite_ports[id]; 568 port = &ulite_ports[id];
512 569
513 spin_lock_init(&port->lock); 570 spin_lock_init(&port->lock);
514 port->fifosize = 16; 571 port->fifosize = 16;
515 port->regshift = 2; 572 port->regshift = 2;
516 port->iotype = UPIO_MEM; 573 port->iotype = UPIO_MEM;
517 port->iobase = 1; /* mark port in use */ 574 port->iobase = 1; /* mark port in use */
518 port->mapbase = base; 575 port->mapbase = base;
519 port->membase = NULL; 576 port->membase = NULL;
520 port->ops = &ulite_ops; 577 port->ops = &ulite_ops;
521 port->irq = irq; 578 port->irq = irq;
522 port->flags = UPF_BOOT_AUTOCONF; 579 port->flags = UPF_BOOT_AUTOCONF;
523 port->dev = dev; 580 port->dev = dev;
524 port->type = PORT_UNKNOWN; 581 port->type = PORT_UNKNOWN;
525 port->line = id; 582 port->line = id;
526 583
527 dev_set_drvdata(dev, port); 584 dev_set_drvdata(dev, port);
528 585
529 /* Register the port */ 586 /* Register the port */
530 rc = uart_add_one_port(&ulite_uart_driver, port); 587 rc = uart_add_one_port(&ulite_uart_driver, port);
531 if (rc) { 588 if (rc) {
532 dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc); 589 dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc);
533 port->mapbase = 0; 590 port->mapbase = 0;
534 dev_set_drvdata(dev, NULL); 591 dev_set_drvdata(dev, NULL);
535 return rc; 592 return rc;
536 } 593 }
537 594
538 return 0; 595 return 0;
539 } 596 }
540 597
541 /** ulite_release: register a uartlite device with the driver 598 /** ulite_release: register a uartlite device with the driver
542 * 599 *
543 * @dev: pointer to device structure 600 * @dev: pointer to device structure
544 */ 601 */
545 static int ulite_release(struct device *dev) 602 static int ulite_release(struct device *dev)
546 { 603 {
547 struct uart_port *port = dev_get_drvdata(dev); 604 struct uart_port *port = dev_get_drvdata(dev);
548 int rc = 0; 605 int rc = 0;
549 606
550 if (port) { 607 if (port) {
551 rc = uart_remove_one_port(&ulite_uart_driver, port); 608 rc = uart_remove_one_port(&ulite_uart_driver, port);
552 dev_set_drvdata(dev, NULL); 609 dev_set_drvdata(dev, NULL);
553 port->mapbase = 0; 610 port->mapbase = 0;
554 } 611 }
555 612
556 return rc; 613 return rc;
557 } 614 }
558 615
559 /* --------------------------------------------------------------------- 616 /* ---------------------------------------------------------------------
560 * Platform bus binding 617 * Platform bus binding
561 */ 618 */
562 619
563 #if defined(CONFIG_OF) 620 #if defined(CONFIG_OF)
564 /* Match table for of_platform binding */ 621 /* Match table for of_platform binding */
565 static struct of_device_id ulite_of_match[] = { 622 static struct of_device_id ulite_of_match[] = {
566 { .compatible = "xlnx,opb-uartlite-1.00.b", }, 623 { .compatible = "xlnx,opb-uartlite-1.00.b", },
567 { .compatible = "xlnx,xps-uartlite-1.00.a", }, 624 { .compatible = "xlnx,xps-uartlite-1.00.a", },
568 {} 625 {}
569 }; 626 };
570 MODULE_DEVICE_TABLE(of, ulite_of_match); 627 MODULE_DEVICE_TABLE(of, ulite_of_match);
571 #endif /* CONFIG_OF */ 628 #endif /* CONFIG_OF */
572 629
573 static int ulite_probe(struct platform_device *pdev) 630 static int ulite_probe(struct platform_device *pdev)
574 { 631 {
575 struct resource *res, *res2; 632 struct resource *res, *res2;
576 int id = pdev->id; 633 int id = pdev->id;
577 #ifdef CONFIG_OF 634 #ifdef CONFIG_OF
578 const __be32 *prop; 635 const __be32 *prop;
579 636
580 prop = of_get_property(pdev->dev.of_node, "port-number", NULL); 637 prop = of_get_property(pdev->dev.of_node, "port-number", NULL);
581 if (prop) 638 if (prop)
582 id = be32_to_cpup(prop); 639 id = be32_to_cpup(prop);
583 #endif 640 #endif
584 641
585 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 642 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
586 if (!res) 643 if (!res)
587 return -ENODEV; 644 return -ENODEV;
588 645
589 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 646 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
590 if (!res2) 647 if (!res2)
591 return -ENODEV; 648 return -ENODEV;
592 649
593 return ulite_assign(&pdev->dev, id, res->start, res2->start); 650 return ulite_assign(&pdev->dev, id, res->start, res2->start);
594 } 651 }
595 652
596 static int ulite_remove(struct platform_device *pdev) 653 static int ulite_remove(struct platform_device *pdev)
597 { 654 {
598 return ulite_release(&pdev->dev); 655 return ulite_release(&pdev->dev);
599 } 656 }
600 657
601 /* work with hotplug and coldplug */ 658 /* work with hotplug and coldplug */
602 MODULE_ALIAS("platform:uartlite"); 659 MODULE_ALIAS("platform:uartlite");
603 660
604 static struct platform_driver ulite_platform_driver = { 661 static struct platform_driver ulite_platform_driver = {
605 .probe = ulite_probe, 662 .probe = ulite_probe,
606 .remove = ulite_remove, 663 .remove = ulite_remove,
607 .driver = { 664 .driver = {
608 .owner = THIS_MODULE, 665 .owner = THIS_MODULE,
609 .name = "uartlite", 666 .name = "uartlite",
610 .of_match_table = of_match_ptr(ulite_of_match), 667 .of_match_table = of_match_ptr(ulite_of_match),
611 }, 668 },
612 }; 669 };
613 670
614 /* --------------------------------------------------------------------- 671 /* ---------------------------------------------------------------------
615 * Module setup/teardown 672 * Module setup/teardown
616 */ 673 */
617 674
618 static int __init ulite_init(void) 675 static int __init ulite_init(void)
619 { 676 {
620 int ret; 677 int ret;
621 678
622 pr_debug("uartlite: calling uart_register_driver()\n"); 679 pr_debug("uartlite: calling uart_register_driver()\n");
623 ret = uart_register_driver(&ulite_uart_driver); 680 ret = uart_register_driver(&ulite_uart_driver);
624 if (ret) 681 if (ret)
625 goto err_uart; 682 goto err_uart;
626 683
627 pr_debug("uartlite: calling platform_driver_register()\n"); 684 pr_debug("uartlite: calling platform_driver_register()\n");
628 ret = platform_driver_register(&ulite_platform_driver); 685 ret = platform_driver_register(&ulite_platform_driver);
629 if (ret) 686 if (ret)
630 goto err_plat; 687 goto err_plat;
631 688
632 return 0; 689 return 0;
633 690
634 err_plat: 691 err_plat:
635 uart_unregister_driver(&ulite_uart_driver); 692 uart_unregister_driver(&ulite_uart_driver);
636 err_uart: 693 err_uart:
637 pr_err("registering uartlite driver failed: err=%i", ret); 694 pr_err("registering uartlite driver failed: err=%i", ret);
638 return ret; 695 return ret;
639 } 696 }
640 697
641 static void __exit ulite_exit(void) 698 static void __exit ulite_exit(void)
642 { 699 {
643 platform_driver_unregister(&ulite_platform_driver); 700 platform_driver_unregister(&ulite_platform_driver);
644 uart_unregister_driver(&ulite_uart_driver); 701 uart_unregister_driver(&ulite_uart_driver);
645 } 702 }
646 703
647 module_init(ulite_init); 704 module_init(ulite_init);
648 module_exit(ulite_exit); 705 module_exit(ulite_exit);
649 706
650 MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>"); 707 MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
651 MODULE_DESCRIPTION("Xilinx uartlite serial driver"); 708 MODULE_DESCRIPTION("Xilinx uartlite serial driver");
652 MODULE_LICENSE("GPL"); 709 MODULE_LICENSE("GPL");