Doug / smarc-fsl-linux-kernel

Download as
Browse Code ยป

Commit 701c73aa89032f2551cdc73725cb881c0886d86f

Authored by Sachin Kamat
Committed by Mark Brown
1 parent f722406faa
Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch imx_3.14.28_1.0.0_ga

ASoC: ep93xx: Remove redundant platform_set_drvdata() 

Commit 0998d06310 (device-core: Ensure drvdata = NULL when no
driver is bound) removes the need to set driver data field to
NULL.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

Showing 1 changed file with 0 additions and 2 deletions Inline Diff

sound/soc/cirrus/ep93xx-ac97.c
Diff comments   View file @ 701c73a
1 /* 1 /*
2 * ASoC driver for Cirrus Logic EP93xx AC97 controller. 2 * ASoC driver for Cirrus Logic EP93xx AC97 controller.
3 * 3 *
4 * Copyright (c) 2010 Mika Westerberg 4 * Copyright (c) 2010 Mika Westerberg
5 * 5 *
6 * Based on s3c-ac97 ASoC driver by Jaswinder Singh. 6 * Based on s3c-ac97 ASoC driver by Jaswinder Singh.
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 */ 11 */
12 12
13 #include <linux/delay.h> 13 #include <linux/delay.h>
14 #include <linux/err.h> 14 #include <linux/err.h>
15 #include <linux/io.h> 15 #include <linux/io.h>
16 #include <linux/init.h> 16 #include <linux/init.h>
17 #include <linux/module.h> 17 #include <linux/module.h>
18 #include <linux/platform_device.h> 18 #include <linux/platform_device.h>
19 #include <linux/slab.h> 19 #include <linux/slab.h>
20 20
21 #include <sound/core.h> 21 #include <sound/core.h>
22 #include <sound/ac97_codec.h> 22 #include <sound/ac97_codec.h>
23 #include <sound/soc.h> 23 #include <sound/soc.h>
24 24
25 #include <linux/platform_data/dma-ep93xx.h> 25 #include <linux/platform_data/dma-ep93xx.h>
26 26
27 /* 27 /*
28 * Per channel (1-4) registers. 28 * Per channel (1-4) registers.
29 */ 29 */
30 #define AC97CH(n) (((n) - 1) * 0x20) 30 #define AC97CH(n) (((n) - 1) * 0x20)
31 31
32 #define AC97DR(n) (AC97CH(n) + 0x0000) 32 #define AC97DR(n) (AC97CH(n) + 0x0000)
33 33
34 #define AC97RXCR(n) (AC97CH(n) + 0x0004) 34 #define AC97RXCR(n) (AC97CH(n) + 0x0004)
35 #define AC97RXCR_REN BIT(0) 35 #define AC97RXCR_REN BIT(0)
36 #define AC97RXCR_RX3 BIT(3) 36 #define AC97RXCR_RX3 BIT(3)
37 #define AC97RXCR_RX4 BIT(4) 37 #define AC97RXCR_RX4 BIT(4)
38 #define AC97RXCR_CM BIT(15) 38 #define AC97RXCR_CM BIT(15)
39 39
40 #define AC97TXCR(n) (AC97CH(n) + 0x0008) 40 #define AC97TXCR(n) (AC97CH(n) + 0x0008)
41 #define AC97TXCR_TEN BIT(0) 41 #define AC97TXCR_TEN BIT(0)
42 #define AC97TXCR_TX3 BIT(3) 42 #define AC97TXCR_TX3 BIT(3)
43 #define AC97TXCR_TX4 BIT(4) 43 #define AC97TXCR_TX4 BIT(4)
44 #define AC97TXCR_CM BIT(15) 44 #define AC97TXCR_CM BIT(15)
45 45
46 #define AC97SR(n) (AC97CH(n) + 0x000c) 46 #define AC97SR(n) (AC97CH(n) + 0x000c)
47 #define AC97SR_TXFE BIT(1) 47 #define AC97SR_TXFE BIT(1)
48 #define AC97SR_TXUE BIT(6) 48 #define AC97SR_TXUE BIT(6)
49 49
50 #define AC97RISR(n) (AC97CH(n) + 0x0010) 50 #define AC97RISR(n) (AC97CH(n) + 0x0010)
51 #define AC97ISR(n) (AC97CH(n) + 0x0014) 51 #define AC97ISR(n) (AC97CH(n) + 0x0014)
52 #define AC97IE(n) (AC97CH(n) + 0x0018) 52 #define AC97IE(n) (AC97CH(n) + 0x0018)
53 53
54 /* 54 /*
55 * Global AC97 controller registers. 55 * Global AC97 controller registers.
56 */ 56 */
57 #define AC97S1DATA 0x0080 57 #define AC97S1DATA 0x0080
58 #define AC97S2DATA 0x0084 58 #define AC97S2DATA 0x0084
59 #define AC97S12DATA 0x0088 59 #define AC97S12DATA 0x0088
60 60
61 #define AC97RGIS 0x008c 61 #define AC97RGIS 0x008c
62 #define AC97GIS 0x0090 62 #define AC97GIS 0x0090
63 #define AC97IM 0x0094 63 #define AC97IM 0x0094
64 /* 64 /*
65 * Common bits for RGIS, GIS and IM registers. 65 * Common bits for RGIS, GIS and IM registers.
66 */ 66 */
67 #define AC97_SLOT2RXVALID BIT(1) 67 #define AC97_SLOT2RXVALID BIT(1)
68 #define AC97_CODECREADY BIT(5) 68 #define AC97_CODECREADY BIT(5)
69 #define AC97_SLOT2TXCOMPLETE BIT(6) 69 #define AC97_SLOT2TXCOMPLETE BIT(6)
70 70
71 #define AC97EOI 0x0098 71 #define AC97EOI 0x0098
72 #define AC97EOI_WINT BIT(0) 72 #define AC97EOI_WINT BIT(0)
73 #define AC97EOI_CODECREADY BIT(1) 73 #define AC97EOI_CODECREADY BIT(1)
74 74
75 #define AC97GCR 0x009c 75 #define AC97GCR 0x009c
76 #define AC97GCR_AC97IFE BIT(0) 76 #define AC97GCR_AC97IFE BIT(0)
77 77
78 #define AC97RESET 0x00a0 78 #define AC97RESET 0x00a0
79 #define AC97RESET_TIMEDRESET BIT(0) 79 #define AC97RESET_TIMEDRESET BIT(0)
80 80
81 #define AC97SYNC 0x00a4 81 #define AC97SYNC 0x00a4
82 #define AC97SYNC_TIMEDSYNC BIT(0) 82 #define AC97SYNC_TIMEDSYNC BIT(0)
83 83
84 #define AC97_TIMEOUT msecs_to_jiffies(5) 84 #define AC97_TIMEOUT msecs_to_jiffies(5)
85 85
86 /** 86 /**
87 * struct ep93xx_ac97_info - EP93xx AC97 controller info structure 87 * struct ep93xx_ac97_info - EP93xx AC97 controller info structure
88 * @lock: mutex serializing access to the bus (slot 1 & 2 ops) 88 * @lock: mutex serializing access to the bus (slot 1 & 2 ops)
89 * @dev: pointer to the platform device dev structure 89 * @dev: pointer to the platform device dev structure
90 * @regs: mapped AC97 controller registers 90 * @regs: mapped AC97 controller registers
91 * @done: bus ops wait here for an interrupt 91 * @done: bus ops wait here for an interrupt
92 */ 92 */
93 struct ep93xx_ac97_info { 93 struct ep93xx_ac97_info {
94 struct mutex lock; 94 struct mutex lock;
95 struct device *dev; 95 struct device *dev;
96 void __iomem *regs; 96 void __iomem *regs;
97 struct completion done; 97 struct completion done;
98 }; 98 };
99 99
100 /* currently ALSA only supports a single AC97 device */ 100 /* currently ALSA only supports a single AC97 device */
101 static struct ep93xx_ac97_info *ep93xx_ac97_info; 101 static struct ep93xx_ac97_info *ep93xx_ac97_info;
102 102
103 static struct ep93xx_dma_data ep93xx_ac97_pcm_out = { 103 static struct ep93xx_dma_data ep93xx_ac97_pcm_out = {
104 .name = "ac97-pcm-out", 104 .name = "ac97-pcm-out",
105 .dma_port = EP93XX_DMA_AAC1, 105 .dma_port = EP93XX_DMA_AAC1,
106 .direction = DMA_MEM_TO_DEV, 106 .direction = DMA_MEM_TO_DEV,
107 }; 107 };
108 108
109 static struct ep93xx_dma_data ep93xx_ac97_pcm_in = { 109 static struct ep93xx_dma_data ep93xx_ac97_pcm_in = {
110 .name = "ac97-pcm-in", 110 .name = "ac97-pcm-in",
111 .dma_port = EP93XX_DMA_AAC1, 111 .dma_port = EP93XX_DMA_AAC1,
112 .direction = DMA_DEV_TO_MEM, 112 .direction = DMA_DEV_TO_MEM,
113 }; 113 };
114 114
115 static inline unsigned ep93xx_ac97_read_reg(struct ep93xx_ac97_info *info, 115 static inline unsigned ep93xx_ac97_read_reg(struct ep93xx_ac97_info *info,
116 unsigned reg) 116 unsigned reg)
117 { 117 {
118 return __raw_readl(info->regs + reg); 118 return __raw_readl(info->regs + reg);
119 } 119 }
120 120
121 static inline void ep93xx_ac97_write_reg(struct ep93xx_ac97_info *info, 121 static inline void ep93xx_ac97_write_reg(struct ep93xx_ac97_info *info,
122 unsigned reg, unsigned val) 122 unsigned reg, unsigned val)
123 { 123 {
124 __raw_writel(val, info->regs + reg); 124 __raw_writel(val, info->regs + reg);
125 } 125 }
126 126
127 static unsigned short ep93xx_ac97_read(struct snd_ac97 *ac97, 127 static unsigned short ep93xx_ac97_read(struct snd_ac97 *ac97,
128 unsigned short reg) 128 unsigned short reg)
129 { 129 {
130 struct ep93xx_ac97_info *info = ep93xx_ac97_info; 130 struct ep93xx_ac97_info *info = ep93xx_ac97_info;
131 unsigned short val; 131 unsigned short val;
132 132
133 mutex_lock(&info->lock); 133 mutex_lock(&info->lock);
134 134
135 ep93xx_ac97_write_reg(info, AC97S1DATA, reg); 135 ep93xx_ac97_write_reg(info, AC97S1DATA, reg);
136 ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2RXVALID); 136 ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2RXVALID);
137 if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT)) { 137 if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT)) {
138 dev_warn(info->dev, "timeout reading register %x\n", reg); 138 dev_warn(info->dev, "timeout reading register %x\n", reg);
139 mutex_unlock(&info->lock); 139 mutex_unlock(&info->lock);
140 return -ETIMEDOUT; 140 return -ETIMEDOUT;
141 } 141 }
142 val = (unsigned short)ep93xx_ac97_read_reg(info, AC97S2DATA); 142 val = (unsigned short)ep93xx_ac97_read_reg(info, AC97S2DATA);
143 143
144 mutex_unlock(&info->lock); 144 mutex_unlock(&info->lock);
145 return val; 145 return val;
146 } 146 }
147 147
148 static void ep93xx_ac97_write(struct snd_ac97 *ac97, 148 static void ep93xx_ac97_write(struct snd_ac97 *ac97,
149 unsigned short reg, 149 unsigned short reg,
150 unsigned short val) 150 unsigned short val)
151 { 151 {
152 struct ep93xx_ac97_info *info = ep93xx_ac97_info; 152 struct ep93xx_ac97_info *info = ep93xx_ac97_info;
153 153
154 mutex_lock(&info->lock); 154 mutex_lock(&info->lock);
155 155
156 /* 156 /*
157 * Writes to the codec need to be done so that slot 2 is filled in 157 * Writes to the codec need to be done so that slot 2 is filled in
158 * before slot 1. 158 * before slot 1.
159 */ 159 */
160 ep93xx_ac97_write_reg(info, AC97S2DATA, val); 160 ep93xx_ac97_write_reg(info, AC97S2DATA, val);
161 ep93xx_ac97_write_reg(info, AC97S1DATA, reg); 161 ep93xx_ac97_write_reg(info, AC97S1DATA, reg);
162 162
163 ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2TXCOMPLETE); 163 ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2TXCOMPLETE);
164 if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT)) 164 if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
165 dev_warn(info->dev, "timeout writing register %x\n", reg); 165 dev_warn(info->dev, "timeout writing register %x\n", reg);
166 166
167 mutex_unlock(&info->lock); 167 mutex_unlock(&info->lock);
168 } 168 }
169 169
170 static void ep93xx_ac97_warm_reset(struct snd_ac97 *ac97) 170 static void ep93xx_ac97_warm_reset(struct snd_ac97 *ac97)
171 { 171 {
172 struct ep93xx_ac97_info *info = ep93xx_ac97_info; 172 struct ep93xx_ac97_info *info = ep93xx_ac97_info;
173 173
174 mutex_lock(&info->lock); 174 mutex_lock(&info->lock);
175 175
176 /* 176 /*
177 * We are assuming that before this functions gets called, the codec 177 * We are assuming that before this functions gets called, the codec
178 * BIT_CLK is stopped by forcing the codec into powerdown mode. We can 178 * BIT_CLK is stopped by forcing the codec into powerdown mode. We can
179 * control the SYNC signal directly via AC97SYNC register. Using 179 * control the SYNC signal directly via AC97SYNC register. Using
180 * TIMEDSYNC the controller will keep the SYNC high > 1us. 180 * TIMEDSYNC the controller will keep the SYNC high > 1us.
181 */ 181 */
182 ep93xx_ac97_write_reg(info, AC97SYNC, AC97SYNC_TIMEDSYNC); 182 ep93xx_ac97_write_reg(info, AC97SYNC, AC97SYNC_TIMEDSYNC);
183 ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY); 183 ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY);
184 if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT)) 184 if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
185 dev_warn(info->dev, "codec warm reset timeout\n"); 185 dev_warn(info->dev, "codec warm reset timeout\n");
186 186
187 mutex_unlock(&info->lock); 187 mutex_unlock(&info->lock);
188 } 188 }
189 189
190 static void ep93xx_ac97_cold_reset(struct snd_ac97 *ac97) 190 static void ep93xx_ac97_cold_reset(struct snd_ac97 *ac97)
191 { 191 {
192 struct ep93xx_ac97_info *info = ep93xx_ac97_info; 192 struct ep93xx_ac97_info *info = ep93xx_ac97_info;
193 193
194 mutex_lock(&info->lock); 194 mutex_lock(&info->lock);
195 195
196 /* 196 /*
197 * For doing cold reset, we disable the AC97 controller interface, clear 197 * For doing cold reset, we disable the AC97 controller interface, clear
198 * WINT and CODECREADY bits, and finally enable the interface again. 198 * WINT and CODECREADY bits, and finally enable the interface again.
199 */ 199 */
200 ep93xx_ac97_write_reg(info, AC97GCR, 0); 200 ep93xx_ac97_write_reg(info, AC97GCR, 0);
201 ep93xx_ac97_write_reg(info, AC97EOI, AC97EOI_CODECREADY | AC97EOI_WINT); 201 ep93xx_ac97_write_reg(info, AC97EOI, AC97EOI_CODECREADY | AC97EOI_WINT);
202 ep93xx_ac97_write_reg(info, AC97GCR, AC97GCR_AC97IFE); 202 ep93xx_ac97_write_reg(info, AC97GCR, AC97GCR_AC97IFE);
203 203
204 /* 204 /*
205 * Now, assert the reset and wait for the codec to become ready. 205 * Now, assert the reset and wait for the codec to become ready.
206 */ 206 */
207 ep93xx_ac97_write_reg(info, AC97RESET, AC97RESET_TIMEDRESET); 207 ep93xx_ac97_write_reg(info, AC97RESET, AC97RESET_TIMEDRESET);
208 ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY); 208 ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY);
209 if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT)) 209 if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
210 dev_warn(info->dev, "codec cold reset timeout\n"); 210 dev_warn(info->dev, "codec cold reset timeout\n");
211 211
212 /* 212 /*
213 * Give the codec some time to come fully out from the reset. This way 213 * Give the codec some time to come fully out from the reset. This way
214 * we ensure that the subsequent reads/writes will work. 214 * we ensure that the subsequent reads/writes will work.
215 */ 215 */
216 usleep_range(15000, 20000); 216 usleep_range(15000, 20000);
217 217
218 mutex_unlock(&info->lock); 218 mutex_unlock(&info->lock);
219 } 219 }
220 220
221 static irqreturn_t ep93xx_ac97_interrupt(int irq, void *dev_id) 221 static irqreturn_t ep93xx_ac97_interrupt(int irq, void *dev_id)
222 { 222 {
223 struct ep93xx_ac97_info *info = dev_id; 223 struct ep93xx_ac97_info *info = dev_id;
224 unsigned status, mask; 224 unsigned status, mask;
225 225
226 /* 226 /*
227 * Just mask out the interrupt and wake up the waiting thread. 227 * Just mask out the interrupt and wake up the waiting thread.
228 * Interrupts are cleared via reading/writing to slot 1 & 2 registers by 228 * Interrupts are cleared via reading/writing to slot 1 & 2 registers by
229 * the waiting thread. 229 * the waiting thread.
230 */ 230 */
231 status = ep93xx_ac97_read_reg(info, AC97GIS); 231 status = ep93xx_ac97_read_reg(info, AC97GIS);
232 mask = ep93xx_ac97_read_reg(info, AC97IM); 232 mask = ep93xx_ac97_read_reg(info, AC97IM);
233 mask &= ~status; 233 mask &= ~status;
234 ep93xx_ac97_write_reg(info, AC97IM, mask); 234 ep93xx_ac97_write_reg(info, AC97IM, mask);
235 235
236 complete(&info->done); 236 complete(&info->done);
237 return IRQ_HANDLED; 237 return IRQ_HANDLED;
238 } 238 }
239 239
240 struct snd_ac97_bus_ops soc_ac97_ops = { 240 struct snd_ac97_bus_ops soc_ac97_ops = {
241 .read = ep93xx_ac97_read, 241 .read = ep93xx_ac97_read,
242 .write = ep93xx_ac97_write, 242 .write = ep93xx_ac97_write,
243 .reset = ep93xx_ac97_cold_reset, 243 .reset = ep93xx_ac97_cold_reset,
244 .warm_reset = ep93xx_ac97_warm_reset, 244 .warm_reset = ep93xx_ac97_warm_reset,
245 }; 245 };
246 EXPORT_SYMBOL_GPL(soc_ac97_ops); 246 EXPORT_SYMBOL_GPL(soc_ac97_ops);
247 247
248 static int ep93xx_ac97_trigger(struct snd_pcm_substream *substream, 248 static int ep93xx_ac97_trigger(struct snd_pcm_substream *substream,
249 int cmd, struct snd_soc_dai *dai) 249 int cmd, struct snd_soc_dai *dai)
250 { 250 {
251 struct ep93xx_ac97_info *info = snd_soc_dai_get_drvdata(dai); 251 struct ep93xx_ac97_info *info = snd_soc_dai_get_drvdata(dai);
252 unsigned v = 0; 252 unsigned v = 0;
253 253
254 switch (cmd) { 254 switch (cmd) {
255 case SNDRV_PCM_TRIGGER_START: 255 case SNDRV_PCM_TRIGGER_START:
256 case SNDRV_PCM_TRIGGER_RESUME: 256 case SNDRV_PCM_TRIGGER_RESUME:
257 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 257 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
258 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 258 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
259 /* 259 /*
260 * Enable compact mode, TX slots 3 & 4, and the TX FIFO 260 * Enable compact mode, TX slots 3 & 4, and the TX FIFO
261 * itself. 261 * itself.
262 */ 262 */
263 v |= AC97TXCR_CM; 263 v |= AC97TXCR_CM;
264 v |= AC97TXCR_TX3 | AC97TXCR_TX4; 264 v |= AC97TXCR_TX3 | AC97TXCR_TX4;
265 v |= AC97TXCR_TEN; 265 v |= AC97TXCR_TEN;
266 ep93xx_ac97_write_reg(info, AC97TXCR(1), v); 266 ep93xx_ac97_write_reg(info, AC97TXCR(1), v);
267 } else { 267 } else {
268 /* 268 /*
269 * Enable compact mode, RX slots 3 & 4, and the RX FIFO 269 * Enable compact mode, RX slots 3 & 4, and the RX FIFO
270 * itself. 270 * itself.
271 */ 271 */
272 v |= AC97RXCR_CM; 272 v |= AC97RXCR_CM;
273 v |= AC97RXCR_RX3 | AC97RXCR_RX4; 273 v |= AC97RXCR_RX3 | AC97RXCR_RX4;
274 v |= AC97RXCR_REN; 274 v |= AC97RXCR_REN;
275 ep93xx_ac97_write_reg(info, AC97RXCR(1), v); 275 ep93xx_ac97_write_reg(info, AC97RXCR(1), v);
276 } 276 }
277 break; 277 break;
278 278
279 case SNDRV_PCM_TRIGGER_STOP: 279 case SNDRV_PCM_TRIGGER_STOP:
280 case SNDRV_PCM_TRIGGER_SUSPEND: 280 case SNDRV_PCM_TRIGGER_SUSPEND:
281 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 281 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
282 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 282 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
283 /* 283 /*
284 * As per Cirrus EP93xx errata described below: 284 * As per Cirrus EP93xx errata described below:
285 * 285 *
286 * http://www.cirrus.com/en/pubs/errata/ER667E2B.pdf 286 * http://www.cirrus.com/en/pubs/errata/ER667E2B.pdf
287 * 287 *
288 * we will wait for the TX FIFO to be empty before 288 * we will wait for the TX FIFO to be empty before
289 * clearing the TEN bit. 289 * clearing the TEN bit.
290 */ 290 */
291 unsigned long timeout = jiffies + AC97_TIMEOUT; 291 unsigned long timeout = jiffies + AC97_TIMEOUT;
292 292
293 do { 293 do {
294 v = ep93xx_ac97_read_reg(info, AC97SR(1)); 294 v = ep93xx_ac97_read_reg(info, AC97SR(1));
295 if (time_after(jiffies, timeout)) { 295 if (time_after(jiffies, timeout)) {
296 dev_warn(info->dev, "TX timeout\n"); 296 dev_warn(info->dev, "TX timeout\n");
297 break; 297 break;
298 } 298 }
299 } while (!(v & (AC97SR_TXFE | AC97SR_TXUE))); 299 } while (!(v & (AC97SR_TXFE | AC97SR_TXUE)));
300 300
301 /* disable the TX FIFO */ 301 /* disable the TX FIFO */
302 ep93xx_ac97_write_reg(info, AC97TXCR(1), 0); 302 ep93xx_ac97_write_reg(info, AC97TXCR(1), 0);
303 } else { 303 } else {
304 /* disable the RX FIFO */ 304 /* disable the RX FIFO */
305 ep93xx_ac97_write_reg(info, AC97RXCR(1), 0); 305 ep93xx_ac97_write_reg(info, AC97RXCR(1), 0);
306 } 306 }
307 break; 307 break;
308 308
309 default: 309 default:
310 dev_warn(info->dev, "unknown command %d\n", cmd); 310 dev_warn(info->dev, "unknown command %d\n", cmd);
311 return -EINVAL; 311 return -EINVAL;
312 } 312 }
313 313
314 return 0; 314 return 0;
315 } 315 }
316 316
317 static int ep93xx_ac97_startup(struct snd_pcm_substream *substream, 317 static int ep93xx_ac97_startup(struct snd_pcm_substream *substream,
318 struct snd_soc_dai *dai) 318 struct snd_soc_dai *dai)
319 { 319 {
320 struct ep93xx_dma_data *dma_data; 320 struct ep93xx_dma_data *dma_data;
321 321
322 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 322 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
323 dma_data = &ep93xx_ac97_pcm_out; 323 dma_data = &ep93xx_ac97_pcm_out;
324 else 324 else
325 dma_data = &ep93xx_ac97_pcm_in; 325 dma_data = &ep93xx_ac97_pcm_in;
326 326
327 snd_soc_dai_set_dma_data(dai, substream, dma_data); 327 snd_soc_dai_set_dma_data(dai, substream, dma_data);
328 return 0; 328 return 0;
329 } 329 }
330 330
331 static const struct snd_soc_dai_ops ep93xx_ac97_dai_ops = { 331 static const struct snd_soc_dai_ops ep93xx_ac97_dai_ops = {
332 .startup = ep93xx_ac97_startup, 332 .startup = ep93xx_ac97_startup,
333 .trigger = ep93xx_ac97_trigger, 333 .trigger = ep93xx_ac97_trigger,
334 }; 334 };
335 335
336 static struct snd_soc_dai_driver ep93xx_ac97_dai = { 336 static struct snd_soc_dai_driver ep93xx_ac97_dai = {
337 .name = "ep93xx-ac97", 337 .name = "ep93xx-ac97",
338 .id = 0, 338 .id = 0,
339 .ac97_control = 1, 339 .ac97_control = 1,
340 .playback = { 340 .playback = {
341 .stream_name = "AC97 Playback", 341 .stream_name = "AC97 Playback",
342 .channels_min = 2, 342 .channels_min = 2,
343 .channels_max = 2, 343 .channels_max = 2,
344 .rates = SNDRV_PCM_RATE_8000_48000, 344 .rates = SNDRV_PCM_RATE_8000_48000,
345 .formats = SNDRV_PCM_FMTBIT_S16_LE, 345 .formats = SNDRV_PCM_FMTBIT_S16_LE,
346 }, 346 },
347 .capture = { 347 .capture = {
348 .stream_name = "AC97 Capture", 348 .stream_name = "AC97 Capture",
349 .channels_min = 2, 349 .channels_min = 2,
350 .channels_max = 2, 350 .channels_max = 2,
351 .rates = SNDRV_PCM_RATE_8000_48000, 351 .rates = SNDRV_PCM_RATE_8000_48000,
352 .formats = SNDRV_PCM_FMTBIT_S16_LE, 352 .formats = SNDRV_PCM_FMTBIT_S16_LE,
353 }, 353 },
354 .ops = &ep93xx_ac97_dai_ops, 354 .ops = &ep93xx_ac97_dai_ops,
355 }; 355 };
356 356
357 static const struct snd_soc_component_driver ep93xx_ac97_component = { 357 static const struct snd_soc_component_driver ep93xx_ac97_component = {
358 .name = "ep93xx-ac97", 358 .name = "ep93xx-ac97",
359 }; 359 };
360 360
361 static int ep93xx_ac97_probe(struct platform_device *pdev) 361 static int ep93xx_ac97_probe(struct platform_device *pdev)
362 { 362 {
363 struct ep93xx_ac97_info *info; 363 struct ep93xx_ac97_info *info;
364 struct resource *res; 364 struct resource *res;
365 unsigned int irq; 365 unsigned int irq;
366 int ret; 366 int ret;
367 367
368 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); 368 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
369 if (!info) 369 if (!info)
370 return -ENOMEM; 370 return -ENOMEM;
371 371
372 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 372 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
373 if (!res) 373 if (!res)
374 return -ENODEV; 374 return -ENODEV;
375 375
376 info->regs = devm_ioremap_resource(&pdev->dev, res); 376 info->regs = devm_ioremap_resource(&pdev->dev, res);
377 if (IS_ERR(info->regs)) 377 if (IS_ERR(info->regs))
378 return PTR_ERR(info->regs); 378 return PTR_ERR(info->regs);
379 379
380 irq = platform_get_irq(pdev, 0); 380 irq = platform_get_irq(pdev, 0);
381 if (!irq) 381 if (!irq)
382 return -ENODEV; 382 return -ENODEV;
383 383
384 ret = devm_request_irq(&pdev->dev, irq, ep93xx_ac97_interrupt, 384 ret = devm_request_irq(&pdev->dev, irq, ep93xx_ac97_interrupt,
385 IRQF_TRIGGER_HIGH, pdev->name, info); 385 IRQF_TRIGGER_HIGH, pdev->name, info);
386 if (ret) 386 if (ret)
387 goto fail; 387 goto fail;
388 388
389 dev_set_drvdata(&pdev->dev, info); 389 dev_set_drvdata(&pdev->dev, info);
390 390
391 mutex_init(&info->lock); 391 mutex_init(&info->lock);
392 init_completion(&info->done); 392 init_completion(&info->done);
393 info->dev = &pdev->dev; 393 info->dev = &pdev->dev;
394 394
395 ep93xx_ac97_info = info; 395 ep93xx_ac97_info = info;
396 platform_set_drvdata(pdev, info); 396 platform_set_drvdata(pdev, info);
397 397
398 ret = snd_soc_register_component(&pdev->dev, &ep93xx_ac97_component, 398 ret = snd_soc_register_component(&pdev->dev, &ep93xx_ac97_component,
399 &ep93xx_ac97_dai, 1); 399 &ep93xx_ac97_dai, 1);
400 if (ret) 400 if (ret)
401 goto fail; 401 goto fail;
402 402
403 return 0; 403 return 0;
404 404
405 fail: 405 fail:
406 platform_set_drvdata(pdev, NULL);
407 ep93xx_ac97_info = NULL; 406 ep93xx_ac97_info = NULL;
408 dev_set_drvdata(&pdev->dev, NULL); 407 dev_set_drvdata(&pdev->dev, NULL);
409 return ret; 408 return ret;
410 } 409 }
411 410
412 static int ep93xx_ac97_remove(struct platform_device *pdev) 411 static int ep93xx_ac97_remove(struct platform_device *pdev)
413 { 412 {
414 struct ep93xx_ac97_info *info = platform_get_drvdata(pdev); 413 struct ep93xx_ac97_info *info = platform_get_drvdata(pdev);
415 414
416 snd_soc_unregister_component(&pdev->dev); 415 snd_soc_unregister_component(&pdev->dev);
417 416
418 /* disable the AC97 controller */ 417 /* disable the AC97 controller */
419 ep93xx_ac97_write_reg(info, AC97GCR, 0); 418 ep93xx_ac97_write_reg(info, AC97GCR, 0);
420 419
421 platform_set_drvdata(pdev, NULL);
422 ep93xx_ac97_info = NULL; 420 ep93xx_ac97_info = NULL;
423 dev_set_drvdata(&pdev->dev, NULL); 421 dev_set_drvdata(&pdev->dev, NULL);
424 422
425 return 0; 423 return 0;
426 } 424 }
427 425
428 static struct platform_driver ep93xx_ac97_driver = { 426 static struct platform_driver ep93xx_ac97_driver = {
429 .probe = ep93xx_ac97_probe, 427 .probe = ep93xx_ac97_probe,
430 .remove = ep93xx_ac97_remove, 428 .remove = ep93xx_ac97_remove,
431 .driver = { 429 .driver = {
432 .name = "ep93xx-ac97", 430 .name = "ep93xx-ac97",
433 .owner = THIS_MODULE, 431 .owner = THIS_MODULE,
434 }, 432 },
435 }; 433 };
436 434
437 module_platform_driver(ep93xx_ac97_driver); 435 module_platform_driver(ep93xx_ac97_driver);
438 436
439 MODULE_DESCRIPTION("EP93xx AC97 ASoC Driver"); 437 MODULE_DESCRIPTION("EP93xx AC97 ASoC Driver");
440 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>"); 438 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
441 MODULE_LICENSE("GPL"); 439 MODULE_LICENSE("GPL");
442 MODULE_ALIAS("platform:ep93xx-ac97"); 440 MODULE_ALIAS("platform:ep93xx-ac97");
443 441