Doug / smarc-fsl-linux-kernel | Embedian Git Server

Commit 716a3dc20084da9b3ab17bd125005a5345e23e3b

Authored by Russell King 2012-01-13 23:00:51 +0800

Exists in master and in 6 other branches

ARM: Add arm_memblock_steal() to allocate memory away from the kernel

Several platforms are now using the memblock_alloc+memblock_free+
memblock_remove trick to obtain memory which won't be mapped in the
kernel's page tables.  Most platforms do this (correctly) in the
->reserve callback.  However, OMAP has started to call these functions
outside of this callback, and this is extremely unsafe - memory will
not be unmapped, and could well be given out after memblock is no
longer responsible for its management.

So, provide arm_memblock_steal() to perform this function, and ensure
that it panic()s if it is used inappropriately.  Convert everyone
over, including OMAP.

As a result, OMAP with OMAP4_ERRATA_I688 enabled will panic on boot
with this change.  Mark this option as BROKEN and make it depend on
BROKEN.  OMAP needs to be fixed, or 137d105d50 (ARM: OMAP4: Fix
errata i688 with MPU interconnect barriers.) reverted until such
time it can be fixed correctly.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Showing 9 changed files with 34 additions and 32 deletions Inline Diff

arch/arm/include/asm/memblock.h
arch/arm/mach-imx/mach-mx31_3ds.c
arch/arm/mach-imx/mach-mx31moboard.c
arch/arm/mach-imx/mach-pcm037.c
arch/arm/mach-omap2/Kconfig
arch/arm/mach-omap2/omap-secure.c
arch/arm/mach-omap2/omap4-common.c
arch/arm/mm/init.c
arch/arm/plat-omap/devices.c

arch/arm/include/asm/memblock.h

Diff comments View file @ 716a3dc

1	#ifndef _ASM_ARM_MEMBLOCK_H	1	#ifndef _ASM_ARM_MEMBLOCK_H
2	#define _ASM_ARM_MEMBLOCK_H	2	#define _ASM_ARM_MEMBLOCK_H
3		3
4	struct meminfo;	4	struct meminfo;
5	struct machine_desc;	5	struct machine_desc;
6		6
7	extern void arm_memblock_init(struct meminfo , struct machine_desc );	7	extern void arm_memblock_init(struct meminfo , struct machine_desc );
8		8
		9	phys_addr_t arm_memblock_steal(phys_addr_t size, phys_addr_t align);
		10
9	#endif	11	#endif
10		12

arch/arm/mach-imx/mach-mx31_3ds.c

Diff comments View file @ 716a3dc

 /*
  *  Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
 #include <linux/delay.h>
 #include <linux/dma-mapping.h>
 #include <linux/types.h>
 #include <linux/init.h>
 #include <linux/clk.h>
 #include <linux/irq.h>
 #include <linux/gpio.h>
 #include <linux/platform_device.h>
 #include <linux/mfd/mc13783.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/l4f00242t03.h>
 #include <linux/regulator/machine.h>
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
 #include <linux/memblock.h>
 #include <media/soc_camera.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/memory.h>
 #include <asm/mach/map.h>
+#include <asm/memblock.h>
 #include <mach/common.h>
 #include <mach/iomux-mx3.h>
 #include <mach/3ds_debugboard.h>
 #include <mach/ulpi.h>
 #include "devices-imx31.h"
 /* CPLD IRQ line for external uart, external ethernet etc */
 #define EXPIO_PARENT_INT	IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
 static int mx31_3ds_pins[] = {
 	/* UART1 */
 	MX31_PIN_CTS1__CTS1,
 	MX31_PIN_RTS1__RTS1,
 	MX31_PIN_TXD1__TXD1,
 	MX31_PIN_RXD1__RXD1,
 	IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
 	/*SPI0*/
 	IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_ALT1),
 	IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_ALT1),
 	/* SPI 1 */
 	MX31_PIN_CSPI2_SCLK__SCLK,
 	MX31_PIN_CSPI2_MOSI__MOSI,
 	MX31_PIN_CSPI2_MISO__MISO,
 	MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
 	MX31_PIN_CSPI2_SS0__SS0,
 	MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
 	/* MC13783 IRQ */
 	IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
 	/* USB OTG reset */
 	IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO),
 	/* USB OTG */
 	MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
 	MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
 	MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
 	MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
 	MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
 	MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
 	MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
 	MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
 	MX31_PIN_USBOTG_CLK__USBOTG_CLK,
 	MX31_PIN_USBOTG_DIR__USBOTG_DIR,
 	MX31_PIN_USBOTG_NXT__USBOTG_NXT,
 	MX31_PIN_USBOTG_STP__USBOTG_STP,
 	/*Keyboard*/
 	MX31_PIN_KEY_ROW0_KEY_ROW0,
 	MX31_PIN_KEY_ROW1_KEY_ROW1,
 	MX31_PIN_KEY_ROW2_KEY_ROW2,
 	MX31_PIN_KEY_COL0_KEY_COL0,
 	MX31_PIN_KEY_COL1_KEY_COL1,
 	MX31_PIN_KEY_COL2_KEY_COL2,
 	MX31_PIN_KEY_COL3_KEY_COL3,
 	/* USB Host 2 */
 	IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
 	IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
 	IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
 	IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
 	IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
 	IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
 	IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1),
 	IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1),
 	IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1),
 	IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1),
 	IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1),
 	IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1),
 	/* USB Host2 reset */
 	IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO),
 	/* I2C1 */
 	MX31_PIN_I2C_CLK__I2C1_SCL,
 	MX31_PIN_I2C_DAT__I2C1_SDA,
 	/* SDHC1 */
 	MX31_PIN_SD1_DATA3__SD1_DATA3,
 	MX31_PIN_SD1_DATA2__SD1_DATA2,
 	MX31_PIN_SD1_DATA1__SD1_DATA1,
 	MX31_PIN_SD1_DATA0__SD1_DATA0,
 	MX31_PIN_SD1_CLK__SD1_CLK,
 	MX31_PIN_SD1_CMD__SD1_CMD,
 	MX31_PIN_GPIO3_1__GPIO3_1, /* Card detect */
 	MX31_PIN_GPIO3_0__GPIO3_0, /* OE */
 	/* Framebuffer */
 	MX31_PIN_LD0__LD0,
 	MX31_PIN_LD1__LD1,
 	MX31_PIN_LD2__LD2,
 	MX31_PIN_LD3__LD3,
 	MX31_PIN_LD4__LD4,
 	MX31_PIN_LD5__LD5,
 	MX31_PIN_LD6__LD6,
 	MX31_PIN_LD7__LD7,
 	MX31_PIN_LD8__LD8,
 	MX31_PIN_LD9__LD9,
 	MX31_PIN_LD10__LD10,
 	MX31_PIN_LD11__LD11,
 	MX31_PIN_LD12__LD12,
 	MX31_PIN_LD13__LD13,
 	MX31_PIN_LD14__LD14,
 	MX31_PIN_LD15__LD15,
 	MX31_PIN_LD16__LD16,
 	MX31_PIN_LD17__LD17,
 	MX31_PIN_VSYNC3__VSYNC3,
 	MX31_PIN_HSYNC__HSYNC,
 	MX31_PIN_FPSHIFT__FPSHIFT,
 	MX31_PIN_CONTRAST__CONTRAST,
 	/* CSI */
 	MX31_PIN_CSI_D6__CSI_D6,
 	MX31_PIN_CSI_D7__CSI_D7,
 	MX31_PIN_CSI_D8__CSI_D8,
 	MX31_PIN_CSI_D9__CSI_D9,
 	MX31_PIN_CSI_D10__CSI_D10,
 	MX31_PIN_CSI_D11__CSI_D11,
 	MX31_PIN_CSI_D12__CSI_D12,
 	MX31_PIN_CSI_D13__CSI_D13,
 	MX31_PIN_CSI_D14__CSI_D14,
 	MX31_PIN_CSI_D15__CSI_D15,
 	MX31_PIN_CSI_HSYNC__CSI_HSYNC,
 	MX31_PIN_CSI_MCLK__CSI_MCLK,
 	MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
 	MX31_PIN_CSI_VSYNC__CSI_VSYNC,
 	MX31_PIN_CSI_D5__GPIO3_5, /* CMOS PWDN */
 	IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_GPIO), /* CMOS reset */
 };
 /*
  * Camera support
  */
 static phys_addr_t mx3_camera_base __initdata;
 #define MX31_3DS_CAMERA_BUF_SIZE SZ_8M
 #define MX31_3DS_GPIO_CAMERA_PW IOMUX_TO_GPIO(MX31_PIN_CSI_D5)
 #define MX31_3DS_GPIO_CAMERA_RST IOMUX_TO_GPIO(MX31_PIN_RI_DTE1)
 static struct gpio mx31_3ds_camera_gpios[] = {
 	{ MX31_3DS_GPIO_CAMERA_PW, GPIOF_OUT_INIT_HIGH, "camera-power" },
 	{ MX31_3DS_GPIO_CAMERA_RST, GPIOF_OUT_INIT_HIGH, "camera-reset" },
 };
 static const struct mx3_camera_pdata mx31_3ds_camera_pdata __initconst = {
 	.flags = MX3_CAMERA_DATAWIDTH_10,
 	.mclk_10khz = 2600,
 };
 static int __init mx31_3ds_init_camera(void)
 {
 	int dma, ret = -ENOMEM;
 	struct platform_device *pdev =
 		imx31_alloc_mx3_camera(&mx31_3ds_camera_pdata);
 	if (IS_ERR(pdev))
 		return PTR_ERR(pdev);
 	if (!mx3_camera_base)
 		goto err;
 	dma = dma_declare_coherent_memory(&pdev->dev,
 					mx3_camera_base, mx3_camera_base,
 					MX31_3DS_CAMERA_BUF_SIZE,
 					DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
 	if (!(dma & DMA_MEMORY_MAP))
 		goto err;
 	ret = platform_device_add(pdev);
 	if (ret)
 err:
 		platform_device_put(pdev);
 	return ret;
 }
 static int mx31_3ds_camera_power(struct device *dev, int on)
 {
 	/* enable or disable the camera */
 	pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
 	gpio_set_value(MX31_3DS_GPIO_CAMERA_PW, on ? 0 : 1);
 	if (!on)
 		goto out;
 	/* If enabled, give a reset impulse */
 	gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 0);
 	msleep(20);
 	gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 1);
 	msleep(100);
 out:
 	return 0;
 }
 static struct i2c_board_info mx31_3ds_i2c_camera = {
 	I2C_BOARD_INFO("ov2640", 0x30),
 };
 static struct regulator_bulk_data mx31_3ds_camera_regs[] = {
 	{ .supply = "cmos_vcore" },
 	{ .supply = "cmos_2v8" },
 };
 static struct soc_camera_link iclink_ov2640 = {
 	.bus_id		= 0,
 	.board_info	= &mx31_3ds_i2c_camera,
 	.i2c_adapter_id	= 0,
 	.power		= mx31_3ds_camera_power,
 	.regulators	= mx31_3ds_camera_regs,
 	.num_regulators	= ARRAY_SIZE(mx31_3ds_camera_regs),
 };
 static struct platform_device mx31_3ds_ov2640 = {
 	.name	= "soc-camera-pdrv",
 	.id	= 0,
 	.dev	= {
 		.platform_data = &iclink_ov2640,
 	},
 };
 /*
  * FB support
  */
 static const struct fb_videomode fb_modedb[] = {
 	{	/* 480x640 @ 60 Hz */
 		.name		= "Epson-VGA",
 		.refresh	= 60,
 		.xres		= 480,
 		.yres		= 640,
 		.pixclock	= 41701,
 		.left_margin	= 20,
 		.right_margin	= 41,
 		.upper_margin	= 10,
 		.lower_margin	= 5,
 		.hsync_len	= 20,
 		.vsync_len	= 10,
 		.sync		= FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
 		.vmode		= FB_VMODE_NONINTERLACED,
 		.flag		= 0,
 	},
 };
 static struct ipu_platform_data mx3_ipu_data = {
 	.irq_base = MXC_IPU_IRQ_START,
 };
 static struct mx3fb_platform_data mx3fb_pdata __initdata = {
 	.name		= "Epson-VGA",
 	.mode		= fb_modedb,
 	.num_modes	= ARRAY_SIZE(fb_modedb),
 };
 /* LCD */
 static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = {
 	.reset_gpio		= IOMUX_TO_GPIO(MX31_PIN_LCS1),
 	.data_enable_gpio	= IOMUX_TO_GPIO(MX31_PIN_SER_RS),
 };
 /*
  * Support for SD card slot in personality board
  */
 #define MX31_3DS_GPIO_SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
 #define MX31_3DS_GPIO_SDHC1_BE IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
 static struct gpio mx31_3ds_sdhc1_gpios[] = {
 	{ MX31_3DS_GPIO_SDHC1_CD, GPIOF_IN, "sdhc1-card-detect" },
 	{ MX31_3DS_GPIO_SDHC1_BE, GPIOF_OUT_INIT_LOW, "sdhc1-bus-en" },
 };
 static int mx31_3ds_sdhc1_init(struct device *dev,
 			       irq_handler_t detect_irq,
 			       void *data)
 {
 	int ret;
 	ret = gpio_request_array(mx31_3ds_sdhc1_gpios,
 				 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
 	if (ret) {
 		pr_warning("Unable to request the SD/MMC GPIOs.\n");
 		return ret;
 	}
 	ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
 			  detect_irq, IRQF_DISABLED |
 			  IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
 			  "sdhc1-detect", data);
 	if (ret) {
 		pr_warning("Unable to request the SD/MMC card-detect IRQ.\n");
 		goto gpio_free;
 	}
 	return 0;
 gpio_free:
 	gpio_free_array(mx31_3ds_sdhc1_gpios,
 			ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
 	return ret;
 }
 static void mx31_3ds_sdhc1_exit(struct device *dev, void *data)
 {
 	free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), data);
 	gpio_free_array(mx31_3ds_sdhc1_gpios,
 			 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
 }
 static void mx31_3ds_sdhc1_setpower(struct device *dev, unsigned int vdd)
 {
 	/*
 	 * While the voltage stuff is done by the driver, activate the
 	 * Buffer Enable Pin only if there is a card in slot to fix the card
 	 * voltage issue caused by bi-directional chip TXB0108 on 3Stack.
 	 * Done here because at this stage we have for sure a debounced value
 	 * of the presence of the card, showed by the value of vdd.
 	 * 7 == ilog2(MMC_VDD_165_195)
 	 */
 	if (vdd > 7)
 		gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 1);
 	else
 		gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 0);
 }
 static struct imxmmc_platform_data sdhc1_pdata = {
 	.init		= mx31_3ds_sdhc1_init,
 	.exit		= mx31_3ds_sdhc1_exit,
 	.setpower	= mx31_3ds_sdhc1_setpower,
 };
 /*
  * Matrix keyboard
  */
 static const uint32_t mx31_3ds_keymap[] = {
 	KEY(0, 0, KEY_UP),
 	KEY(0, 1, KEY_DOWN),
 	KEY(1, 0, KEY_RIGHT),
 	KEY(1, 1, KEY_LEFT),
 	KEY(1, 2, KEY_ENTER),
 	KEY(2, 0, KEY_F6),
 	KEY(2, 1, KEY_F8),
 	KEY(2, 2, KEY_F9),
 	KEY(2, 3, KEY_F10),
 };
 static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = {
 	.keymap		= mx31_3ds_keymap,
 	.keymap_size	= ARRAY_SIZE(mx31_3ds_keymap),
 };
 /* Regulators */
 static struct regulator_init_data pwgtx_init = {
 	.constraints = {
 		.boot_on	= 1,
 		.always_on	= 1,
 	},
 };
 static struct regulator_init_data gpo_init = {
 	.constraints = {
 		.boot_on = 1,
 		.always_on = 1,
 	}
 };
 static struct regulator_consumer_supply vmmc2_consumers[] = {
 	REGULATOR_SUPPLY("vmmc", "mxc-mmc.0"),
 };
 static struct regulator_init_data vmmc2_init = {
 	.constraints = {
 		.min_uV = 3000000,
 		.max_uV = 3000000,
 		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 				  REGULATOR_CHANGE_STATUS,
 	},
 	.num_consumer_supplies = ARRAY_SIZE(vmmc2_consumers),
 	.consumer_supplies = vmmc2_consumers,
 };
 static struct regulator_consumer_supply vmmc1_consumers[] = {
 	REGULATOR_SUPPLY("vcore", "spi0.0"),
 	REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"),
 };
 static struct regulator_init_data vmmc1_init = {
 	.constraints = {
 		.min_uV = 2800000,
 		.max_uV = 2800000,
 		.apply_uV = 1,
 		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 				  REGULATOR_CHANGE_STATUS,
 	},
 	.num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
 	.consumer_supplies = vmmc1_consumers,
 };
 static struct regulator_consumer_supply vgen_consumers[] = {
 	REGULATOR_SUPPLY("vdd", "spi0.0"),
 };
 static struct regulator_init_data vgen_init = {
 	.constraints = {
 		.min_uV = 1800000,
 		.max_uV = 1800000,
 		.apply_uV = 1,
 		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 				  REGULATOR_CHANGE_STATUS,
 	},
 	.num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
 	.consumer_supplies = vgen_consumers,
 };
 static struct regulator_consumer_supply vvib_consumers[] = {
 	REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"),
 };
 static struct regulator_init_data vvib_init = {
 	.constraints = {
 		.min_uV = 1300000,
 		.max_uV = 1300000,
 		.apply_uV = 1,
 		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 				  REGULATOR_CHANGE_STATUS,
 	},
 	.num_consumer_supplies = ARRAY_SIZE(vvib_consumers),
 	.consumer_supplies = vvib_consumers,
 };
 static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = {
 	{
 		.id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */
 		.init_data = &pwgtx_init,
 	}, {
 		.id = MC13783_REG_PWGT2SPI, /* Power Gate for L2 Cache. */
 		.init_data = &pwgtx_init,
 	}, {
 		.id = MC13783_REG_GPO1, /* Turn on 1.8V */
 		.init_data = &gpo_init,
 	}, {
 		.id = MC13783_REG_GPO3, /* Turn on 3.3V */
 		.init_data = &gpo_init,
 	}, {
 		.id = MC13783_REG_VMMC2, /* Power MMC/SD, WiFi/Bluetooth. */
 		.init_data = &vmmc2_init,
 	}, {
 		.id = MC13783_REG_VMMC1, /* Power LCD, CMOS, FM, GPS, Accel. */
 		.init_data = &vmmc1_init,
 	}, {
 		.id = MC13783_REG_VGEN,  /* Power LCD */
 		.init_data = &vgen_init,
 	}, {
 		.id = MC13783_REG_VVIB,  /* Power CMOS */
 		.init_data = &vvib_init,
 	},
 };
 /* MC13783 */
 static struct mc13xxx_platform_data mc13783_pdata = {
 	.regulators = {
 		.regulators = mx31_3ds_regulators,
 		.num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
 	},
 	.flags  = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC,
 };
 /* SPI */
 static int spi0_internal_chipselect[] = {
 	MXC_SPI_CS(2),
 };
 static const struct spi_imx_master spi0_pdata __initconst = {
 	.chipselect	= spi0_internal_chipselect,
 	.num_chipselect	= ARRAY_SIZE(spi0_internal_chipselect),
 };
 static int spi1_internal_chipselect[] = {
 	MXC_SPI_CS(0),
 	MXC_SPI_CS(2),
 };
 static const struct spi_imx_master spi1_pdata __initconst = {
 	.chipselect	= spi1_internal_chipselect,
 	.num_chipselect	= ARRAY_SIZE(spi1_internal_chipselect),
 };
 static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
 	{
 		.modalias	= "mc13783",
 		.max_speed_hz	= 1000000,
 		.bus_num	= 1,
 		.chip_select	= 1, /* SS2 */
 		.platform_data	= &mc13783_pdata,
 		.irq		= IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
 		.mode = SPI_CS_HIGH,
 	}, {
 		.modalias	= "l4f00242t03",
 		.max_speed_hz	= 5000000,
 		.bus_num	= 0,
 		.chip_select	= 0, /* SS2 */
 		.platform_data	= &mx31_3ds_l4f00242t03_pdata,
 	},
 };
 /*
  * NAND Flash
  */
 static const struct mxc_nand_platform_data
 mx31_3ds_nand_board_info __initconst = {
 	.width		= 1,
 	.hw_ecc		= 1,
 #ifdef CONFIG_MACH_MX31_3DS_MXC_NAND_USE_BBT
 	.flash_bbt	= 1,
 #endif
 };
 /*
  * USB OTG
  */
 #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
 		     PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
 #define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
 #define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP)
 static int mx31_3ds_usbotg_init(void)
 {
 	int err;
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
 	err = gpio_request(USBOTG_RST_B, "otgusb-reset");
 	if (err) {
 		pr_err("Failed to request the USB OTG reset gpio\n");
 		return err;
 	}
 	err = gpio_direction_output(USBOTG_RST_B, 0);
 	if (err) {
 		pr_err("Failed to drive the USB OTG reset gpio\n");
 		goto usbotg_free_reset;
 	}
 	mdelay(1);
 	gpio_set_value(USBOTG_RST_B, 1);
 	return 0;
 usbotg_free_reset:
 	gpio_free(USBOTG_RST_B);
 	return err;
 }
 static int mx31_3ds_otg_init(struct platform_device *pdev)
 {
 	return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
 }
 static int mx31_3ds_host2_init(struct platform_device *pdev)
 {
 	int err;
 	mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG);
 	err = gpio_request(USBH2_RST_B, "usbh2-reset");
 	if (err) {
 		pr_err("Failed to request the USB Host 2 reset gpio\n");
 		return err;
 	}
 	err = gpio_direction_output(USBH2_RST_B, 0);
 	if (err) {
 		pr_err("Failed to drive the USB Host 2 reset gpio\n");
 		goto usbotg_free_reset;
 	}
 	mdelay(1);
 	gpio_set_value(USBH2_RST_B, 1);
 	mdelay(10);
 	return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
 usbotg_free_reset:
 	gpio_free(USBH2_RST_B);
 	return err;
 }
 static struct mxc_usbh_platform_data otg_pdata __initdata = {
 	.init	= mx31_3ds_otg_init,
 	.portsc	= MXC_EHCI_MODE_ULPI,
 };
 static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
 	.init = mx31_3ds_host2_init,
 	.portsc	= MXC_EHCI_MODE_ULPI,
 };
 static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
 	.operating_mode = FSL_USB2_DR_DEVICE,
 	.phy_mode	= FSL_USB2_PHY_ULPI,
 };
 static int otg_mode_host;
 static int __init mx31_3ds_otg_mode(char *options)
 {
 	if (!strcmp(options, "host"))
 		otg_mode_host = 1;
 	else if (!strcmp(options, "device"))
 		otg_mode_host = 0;
 	else
 		pr_info("otg_mode neither \"host\" nor \"device\". "
 			"Defaulting to device\n");
 	return 0;
 }
 __setup("otg_mode=", mx31_3ds_otg_mode);
 static const struct imxuart_platform_data uart_pdata __initconst = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };
 static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = {
 	.bitrate = 100000,
 };
 static struct platform_device *devices[] __initdata = {
 	&mx31_3ds_ov2640,
 };
 static void __init mx31_3ds_init(void)
 {
 	int ret;
 	imx31_soc_init();
 	/* Configure SPI1 IOMUX */
 	mxc_iomux_set_gpr(MUX_PGP_CSPI_BB, true);
 	mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
 				      "mx31_3ds");
 	imx31_add_imx_uart0(&uart_pdata);
 	imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
 	imx31_add_spi_imx1(&spi1_pdata);
 	spi_register_board_info(mx31_3ds_spi_devs,
 						ARRAY_SIZE(mx31_3ds_spi_devs));
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 	imx31_add_imx_keypad(&mx31_3ds_keymap_data);
 	mx31_3ds_usbotg_init();
 	if (otg_mode_host) {
 		otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
 				ULPI_OTG_DRVVBUS_EXT);
 		if (otg_pdata.otg)
 			imx31_add_mxc_ehci_otg(&otg_pdata);
 	}
 	usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
 			ULPI_OTG_DRVVBUS_EXT);
 	if (usbh2_pdata.otg)
 		imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
 	if (!otg_mode_host)
 		imx31_add_fsl_usb2_udc(&usbotg_pdata);
 	if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT))
 		printk(KERN_WARNING "Init of the debug board failed, all "
 				    "devices on the debug board are unusable.\n");
 	imx31_add_imx2_wdt(NULL);
 	imx31_add_imx_i2c0(&mx31_3ds_i2c0_data);
 	imx31_add_mxc_mmc(0, &sdhc1_pdata);
 	imx31_add_spi_imx0(&spi0_pdata);
 	imx31_add_ipu_core(&mx3_ipu_data);
 	imx31_add_mx3_sdc_fb(&mx3fb_pdata);
 	/* CSI */
 	/* Camera power: default - off */
 	ret = gpio_request_array(mx31_3ds_camera_gpios,
 				 ARRAY_SIZE(mx31_3ds_camera_gpios));
 	if (ret) {
 		pr_err("Failed to request camera gpios");
 		iclink_ov2640.power = NULL;
 	}
 	mx31_3ds_init_camera();
 }
 static void __init mx31_3ds_timer_init(void)
 {
 	mx31_clocks_init(26000000);
 }
 static struct sys_timer mx31_3ds_timer = {
 	.init	= mx31_3ds_timer_init,
 };
 static void __init mx31_3ds_reserve(void)
 {
 	/* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
-	mx3_camera_base = memblock_alloc(MX31_3DS_CAMERA_BUF_SIZE,
+	mx3_camera_base = arm_memblock_steal(MX31_3DS_CAMERA_BUF_SIZE,
 					 MX31_3DS_CAMERA_BUF_SIZE);
-	memblock_free(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
-	memblock_remove(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
 }
 MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
 	/* Maintainer: Freescale Semiconductor, Inc. */
 	.atag_offset = 0x100,
 	.map_io = mx31_map_io,
 	.init_early = imx31_init_early,
 	.init_irq = mx31_init_irq,
 	.handle_irq = imx31_handle_irq,
 	.timer = &mx31_3ds_timer,
 	.init_machine = mx31_3ds_init,
 	.reserve = mx31_3ds_reserve,
 	.restart	= mxc_restart,
 MACHINE_END

arch/arm/mach-imx/mach-mx31moboard.c

Diff comments View file @ 716a3dc

 /*
  *  Copyright (C) 2008 Valentin Longchamp, EPFL Mobots group
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
 #include <linux/delay.h>
 #include <linux/dma-mapping.h>
 #include <linux/gfp.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/moduleparam.h>
 #include <linux/leds.h>
 #include <linux/memory.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/partitions.h>
 #include <linux/platform_device.h>
 #include <linux/regulator/machine.h>
 #include <linux/mfd/mc13783.h>
 #include <linux/spi/spi.h>
 #include <linux/types.h>
 #include <linux/memblock.h>
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/err.h>
 #include <linux/input.h>
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
+#include <asm/memblock.h>
 #include <mach/board-mx31moboard.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx3.h>
 #include <mach/ulpi.h>
 #include "devices-imx31.h"
 static unsigned int moboard_pins[] = {
 	/* UART0 */
 	MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1,
 	MX31_PIN_CTS1__GPIO2_7,
 	/* UART4 */
 	MX31_PIN_PC_RST__CTS5, MX31_PIN_PC_VS2__RTS5,
 	MX31_PIN_PC_BVD2__TXD5, MX31_PIN_PC_BVD1__RXD5,
 	/* I2C0 */
 	MX31_PIN_I2C_DAT__I2C1_SDA, MX31_PIN_I2C_CLK__I2C1_SCL,
 	/* I2C1 */
 	MX31_PIN_DCD_DTE1__I2C2_SDA, MX31_PIN_RI_DTE1__I2C2_SCL,
 	/* SDHC1 */
 	MX31_PIN_SD1_DATA3__SD1_DATA3, MX31_PIN_SD1_DATA2__SD1_DATA2,
 	MX31_PIN_SD1_DATA1__SD1_DATA1, MX31_PIN_SD1_DATA0__SD1_DATA0,
 	MX31_PIN_SD1_CLK__SD1_CLK, MX31_PIN_SD1_CMD__SD1_CMD,
 	MX31_PIN_ATA_CS0__GPIO3_26, MX31_PIN_ATA_CS1__GPIO3_27,
 	/* USB reset */
 	MX31_PIN_GPIO1_0__GPIO1_0,
 	/* USB OTG */
 	MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
 	MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
 	MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
 	MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
 	MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
 	MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
 	MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
 	MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
 	MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR,
 	MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP,
 	MX31_PIN_USB_OC__GPIO1_30,
 	/* USB H2 */
 	MX31_PIN_USBH2_DATA0__USBH2_DATA0,
 	MX31_PIN_USBH2_DATA1__USBH2_DATA1,
 	MX31_PIN_STXD3__USBH2_DATA2, MX31_PIN_SRXD3__USBH2_DATA3,
 	MX31_PIN_SCK3__USBH2_DATA4, MX31_PIN_SFS3__USBH2_DATA5,
 	MX31_PIN_STXD6__USBH2_DATA6, MX31_PIN_SRXD6__USBH2_DATA7,
 	MX31_PIN_USBH2_CLK__USBH2_CLK, MX31_PIN_USBH2_DIR__USBH2_DIR,
 	MX31_PIN_USBH2_NXT__USBH2_NXT, MX31_PIN_USBH2_STP__USBH2_STP,
 	MX31_PIN_SCK6__GPIO1_25,
 	/* LEDs */
 	MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1,
 	MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3,
 	/* SPI1 */
 	MX31_PIN_CSPI2_MOSI__MOSI, MX31_PIN_CSPI2_MISO__MISO,
 	MX31_PIN_CSPI2_SCLK__SCLK, MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
 	MX31_PIN_CSPI2_SS0__SS0, MX31_PIN_CSPI2_SS2__SS2,
 	/* Atlas IRQ */
 	MX31_PIN_GPIO1_3__GPIO1_3,
 	/* SPI2 */
 	MX31_PIN_CSPI3_MOSI__MOSI, MX31_PIN_CSPI3_MISO__MISO,
 	MX31_PIN_CSPI3_SCLK__SCLK, MX31_PIN_CSPI3_SPI_RDY__SPI_RDY,
 	MX31_PIN_CSPI2_SS1__CSPI3_SS1,
 };
 static struct physmap_flash_data mx31moboard_flash_data = {
 	.width	= 2,
 };
 static struct resource mx31moboard_flash_resource = {
 	.start	= 0xa0000000,
 	.end	= 0xa1ffffff,
 	.flags	= IORESOURCE_MEM,
 };
 static struct platform_device mx31moboard_flash = {
 	.name	= "physmap-flash",
 	.id	= 0,
 	.dev	= {
 		.platform_data  = &mx31moboard_flash_data,
 	},
 	.resource = &mx31moboard_flash_resource,
 	.num_resources = 1,
 };
 static int moboard_uart0_init(struct platform_device *pdev)
 {
 	int ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack");
 	if (ret)
 		return ret;
 	ret = gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0);
 	if (ret)
 		gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1));
 	return ret;
 }
 static void moboard_uart0_exit(struct platform_device *pdev)
 {
 	gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1));
 }
 static const struct imxuart_platform_data uart0_pdata __initconst = {
 	.init = moboard_uart0_init,
 	.exit = moboard_uart0_exit,
 };
 static const struct imxuart_platform_data uart4_pdata __initconst = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };
 static const struct imxi2c_platform_data moboard_i2c0_data __initconst = {
 	.bitrate = 400000,
 };
 static const struct imxi2c_platform_data moboard_i2c1_data __initconst = {
 	.bitrate = 100000,
 };
 static int moboard_spi1_cs[] = {
 	MXC_SPI_CS(0),
 	MXC_SPI_CS(2),
 };
 static const struct spi_imx_master moboard_spi1_pdata __initconst = {
 	.chipselect	= moboard_spi1_cs,
 	.num_chipselect	= ARRAY_SIZE(moboard_spi1_cs),
 };
 static struct regulator_consumer_supply sdhc_consumers[] = {
 	{
 		.dev_name = "mxc-mmc.0",
 		.supply	= "sdhc0_vcc",
 	},
 	{
 		.dev_name = "mxc-mmc.1",
 		.supply	= "sdhc1_vcc",
 	},
 };
 static struct regulator_init_data sdhc_vreg_data = {
 	.constraints = {
 		.min_uV = 2700000,
 		.max_uV = 3000000,
 		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 			REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
 		.valid_modes_mask = REGULATOR_MODE_NORMAL |
 			REGULATOR_MODE_FAST,
 		.always_on = 0,
 		.boot_on = 1,
 	},
 	.num_consumer_supplies = ARRAY_SIZE(sdhc_consumers),
 	.consumer_supplies = sdhc_consumers,
 };
 static struct regulator_consumer_supply cam_consumers[] = {
 	{
 		.dev_name = "mx3_camera.0",
 		.supply = "cam_vcc",
 	},
 };
 static struct regulator_init_data cam_vreg_data = {
 	.constraints = {
 		.min_uV = 2700000,
 		.max_uV = 3000000,
 		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 			REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
 		.valid_modes_mask = REGULATOR_MODE_NORMAL |
 			REGULATOR_MODE_FAST,
 		.always_on = 0,
 		.boot_on = 1,
 	},
 	.num_consumer_supplies = ARRAY_SIZE(cam_consumers),
 	.consumer_supplies = cam_consumers,
 };
 static struct mc13xxx_regulator_init_data moboard_regulators[] = {
 	{
 		.id = MC13783_REG_VMMC1,
 		.init_data = &sdhc_vreg_data,
 	},
 	{
 		.id = MC13783_REG_VCAM,
 		.init_data = &cam_vreg_data,
 	},
 };
 static struct mc13xxx_led_platform_data moboard_led[] = {
 	{
 		.id = MC13783_LED_R1,
 		.name = "coreboard-led-4:red",
 		.max_current = 2,
 	},
 	{
 		.id = MC13783_LED_G1,
 		.name = "coreboard-led-4:green",
 		.max_current = 2,
 	},
 	{
 		.id = MC13783_LED_B1,
 		.name = "coreboard-led-4:blue",
 		.max_current = 2,
 	},
 	{
 		.id = MC13783_LED_R2,
 		.name = "coreboard-led-5:red",
 		.max_current = 3,
 	},
 	{
 		.id = MC13783_LED_G2,
 		.name = "coreboard-led-5:green",
 		.max_current = 3,
 	},
 	{
 		.id = MC13783_LED_B2,
 		.name = "coreboard-led-5:blue",
 		.max_current = 3,
 	},
 };
 static struct mc13xxx_leds_platform_data moboard_leds = {
 	.num_leds = ARRAY_SIZE(moboard_led),
 	.led = moboard_led,
 	.flags = MC13783_LED_SLEWLIMTC,
 	.abmode = MC13783_LED_AB_DISABLED,
 	.tc1_period = MC13783_LED_PERIOD_10MS,
 	.tc2_period = MC13783_LED_PERIOD_10MS,
 };
 static struct mc13xxx_buttons_platform_data moboard_buttons = {
 	.b1on_flags = MC13783_BUTTON_DBNC_750MS | MC13783_BUTTON_ENABLE |
 			MC13783_BUTTON_POL_INVERT,
 	.b1on_key = KEY_POWER,
 };
 static struct mc13xxx_platform_data moboard_pmic = {
 	.regulators = {
 		.regulators = moboard_regulators,
 		.num_regulators = ARRAY_SIZE(moboard_regulators),
 	},
 	.leds = &moboard_leds,
 	.buttons = &moboard_buttons,
 	.flags = MC13XXX_USE_RTC | MC13XXX_USE_ADC,
 };
 static struct spi_board_info moboard_spi_board_info[] __initdata = {
 	{
 		.modalias = "mc13783",
 		.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
 		.max_speed_hz = 300000,
 		.bus_num = 1,
 		.chip_select = 0,
 		.platform_data = &moboard_pmic,
 		.mode = SPI_CS_HIGH,
 	},
 };
 static int moboard_spi2_cs[] = {
 	MXC_SPI_CS(1),
 };
 static const struct spi_imx_master moboard_spi2_pdata __initconst = {
 	.chipselect	= moboard_spi2_cs,
 	.num_chipselect	= ARRAY_SIZE(moboard_spi2_cs),
 };
 #define SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_ATA_CS0)
 #define SDHC1_WP IOMUX_TO_GPIO(MX31_PIN_ATA_CS1)
 static int moboard_sdhc1_get_ro(struct device *dev)
 {
 	return !gpio_get_value(SDHC1_WP);
 }
 static int moboard_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
 		void *data)
 {
 	int ret;
 	ret = gpio_request(SDHC1_CD, "sdhc-detect");
 	if (ret)
 		return ret;
 	gpio_direction_input(SDHC1_CD);
 	ret = gpio_request(SDHC1_WP, "sdhc-wp");
 	if (ret)
 		goto err_gpio_free;
 	gpio_direction_input(SDHC1_WP);
 	ret = request_irq(gpio_to_irq(SDHC1_CD), detect_irq,
 		IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
 		"sdhc1-card-detect", data);
 	if (ret)
 		goto err_gpio_free_2;
 	return 0;
 err_gpio_free_2:
 	gpio_free(SDHC1_WP);
 err_gpio_free:
 	gpio_free(SDHC1_CD);
 	return ret;
 }
 static void moboard_sdhc1_exit(struct device *dev, void *data)
 {
 	free_irq(gpio_to_irq(SDHC1_CD), data);
 	gpio_free(SDHC1_WP);
 	gpio_free(SDHC1_CD);
 }
 static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
 	.get_ro	= moboard_sdhc1_get_ro,
 	.init	= moboard_sdhc1_init,
 	.exit	= moboard_sdhc1_exit,
 };
 /*
  * this pin is dedicated for all mx31moboard systems, so we do it here
  */
 #define USB_RESET_B	IOMUX_TO_GPIO(MX31_PIN_GPIO1_0)
 #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
 		      PAD_CTL_ODE_CMOS)
 #define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC)
 #define USBH2_EN_B IOMUX_TO_GPIO(MX31_PIN_SCK6)
 static void usb_xcvr_reset(void)
 {
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG | PAD_CTL_100K_PD);
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG | PAD_CTL_100K_PD);
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG | PAD_CTL_100K_PD);
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG | PAD_CTL_100K_PD);
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG | PAD_CTL_100K_PD);
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG | PAD_CTL_100K_PD);
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG | PAD_CTL_100K_PD);
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG | PAD_CTL_100K_PD);
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG | PAD_CTL_100K_PU);
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG | PAD_CTL_100K_PU);
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG | PAD_CTL_100K_PU);
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG | PAD_CTL_100K_PU);
 	mxc_iomux_set_gpr(MUX_PGP_UH2, true);
 	mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG | PAD_CTL_100K_PU);
 	mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG | PAD_CTL_100K_PU);
 	mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG | PAD_CTL_100K_PU);
 	mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG | PAD_CTL_100K_PU);
 	mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG | PAD_CTL_100K_PD);
 	mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG | PAD_CTL_100K_PD);
 	mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG | PAD_CTL_100K_PD);
 	mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG | PAD_CTL_100K_PD);
 	mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG | PAD_CTL_100K_PD);
 	mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG | PAD_CTL_100K_PD);
 	mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG | PAD_CTL_100K_PD);
 	mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG | PAD_CTL_100K_PD);
 	gpio_request(OTG_EN_B, "usb-udc-en");
 	gpio_direction_output(OTG_EN_B, 0);
 	gpio_request(USBH2_EN_B, "usbh2-en");
 	gpio_direction_output(USBH2_EN_B, 0);
 	gpio_request(USB_RESET_B, "usb-reset");
 	gpio_direction_output(USB_RESET_B, 0);
 	mdelay(1);
 	gpio_set_value(USB_RESET_B, 1);
 	mdelay(1);
 }
 static int moboard_usbh2_init_hw(struct platform_device *pdev)
 {
 	return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
 }
 static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
 	.init	= moboard_usbh2_init_hw,
 	.portsc	= MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
 };
 static int __init moboard_usbh2_init(void)
 {
 	struct platform_device *pdev;
 	usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
 			ULPI_OTG_DRVVBUS_EXT);
 	if (!usbh2_pdata.otg)
 		return -ENODEV;
 	pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
 	if (IS_ERR(pdev))
 		return PTR_ERR(pdev);
 	return 0;
 }
 static const struct gpio_led mx31moboard_leds[] __initconst = {
 	{
 		.name	= "coreboard-led-0:red:running",
 		.default_trigger = "heartbeat",
 		.gpio	= IOMUX_TO_GPIO(MX31_PIN_SVEN0),
 	}, {
 		.name	= "coreboard-led-1:red",
 		.gpio	= IOMUX_TO_GPIO(MX31_PIN_STX0),
 	}, {
 		.name	= "coreboard-led-2:red",
 		.gpio	= IOMUX_TO_GPIO(MX31_PIN_SRX0),
 	}, {
 		.name	= "coreboard-led-3:red",
 		.gpio	= IOMUX_TO_GPIO(MX31_PIN_SIMPD0),
 	},
 };
 static const struct gpio_led_platform_data mx31moboard_led_pdata __initconst = {
 	.num_leds	= ARRAY_SIZE(mx31moboard_leds),
 	.leds		= mx31moboard_leds,
 };
 static const struct ipu_platform_data mx3_ipu_data __initconst = {
 	.irq_base = MXC_IPU_IRQ_START,
 };
 static struct platform_device *devices[] __initdata = {
 	&mx31moboard_flash,
 };
 static struct mx3_camera_pdata camera_pdata __initdata = {
 	.flags		= MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
 	.mclk_10khz	= 4800,
 };
 static phys_addr_t mx3_camera_base __initdata;
 #define MX3_CAMERA_BUF_SIZE SZ_4M
 static int __init mx31moboard_init_cam(void)
 {
 	int dma, ret = -ENOMEM;
 	struct platform_device *pdev;
 	imx31_add_ipu_core(&mx3_ipu_data);
 	pdev = imx31_alloc_mx3_camera(&camera_pdata);
 	if (IS_ERR(pdev))
 		return PTR_ERR(pdev);
 	dma = dma_declare_coherent_memory(&pdev->dev,
 					mx3_camera_base, mx3_camera_base,
 					MX3_CAMERA_BUF_SIZE,
 					DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
 	if (!(dma & DMA_MEMORY_MAP))
 		goto err;
 	ret = platform_device_add(pdev);
 	if (ret)
 err:
 		platform_device_put(pdev);
 	return ret;
 }
 static void mx31moboard_poweroff(void)
 {
 	struct clk *clk = clk_get_sys("imx2-wdt.0", NULL);
 	if (!IS_ERR(clk))
 		clk_enable(clk);
 	mxc_iomux_mode(MX31_PIN_WATCHDOG_RST__WATCHDOG_RST);
 	__raw_writew(1 << 6 | 1 << 2, MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
 }
 static int mx31moboard_baseboard;
 core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444);
 /*
  * Board specific initialization.
  */
 static void __init mx31moboard_init(void)
 {
 	imx31_soc_init();
 	mxc_iomux_setup_multiple_pins(moboard_pins, ARRAY_SIZE(moboard_pins),
 		"moboard");
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 	gpio_led_register_device(-1, &mx31moboard_led_pdata);
 	imx31_add_imx_uart0(&uart0_pdata);
 	imx31_add_imx_uart4(&uart4_pdata);
 	imx31_add_imx_i2c0(&moboard_i2c0_data);
 	imx31_add_imx_i2c1(&moboard_i2c1_data);
 	imx31_add_spi_imx1(&moboard_spi1_pdata);
 	imx31_add_spi_imx2(&moboard_spi2_pdata);
 	gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3), "pmic-irq");
 	gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
 	spi_register_board_info(moboard_spi_board_info,
 		ARRAY_SIZE(moboard_spi_board_info));
 	imx31_add_mxc_mmc(0, &sdhc1_pdata);
 	mx31moboard_init_cam();
 	usb_xcvr_reset();
 	moboard_usbh2_init();
 	pm_power_off = mx31moboard_poweroff;
 	switch (mx31moboard_baseboard) {
 	case MX31NOBOARD:
 		break;
 	case MX31DEVBOARD:
 		mx31moboard_devboard_init();
 		break;
 	case MX31MARXBOT:
 		mx31moboard_marxbot_init();
 		break;
 	case MX31SMARTBOT:
 	case MX31EYEBOT:
 		mx31moboard_smartbot_init(mx31moboard_baseboard);
 		break;
 	default:
 		printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n",
 			mx31moboard_baseboard);
 	}
 }
 static void __init mx31moboard_timer_init(void)
 {
 	mx31_clocks_init(26000000);
 }
 struct sys_timer mx31moboard_timer = {
 	.init	= mx31moboard_timer_init,
 };
 static void __init mx31moboard_reserve(void)
 {
 	/* reserve 4 MiB for mx3-camera */
-	mx3_camera_base = memblock_alloc(MX3_CAMERA_BUF_SIZE,
+	mx3_camera_base = arm_memblock_steal(MX3_CAMERA_BUF_SIZE,
 			MX3_CAMERA_BUF_SIZE);
-	memblock_free(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
-	memblock_remove(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
 }
 MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
 	/* Maintainer: Valentin Longchamp, EPFL Mobots group */
 	.atag_offset = 0x100,
 	.reserve = mx31moboard_reserve,
 	.map_io = mx31_map_io,
 	.init_early = imx31_init_early,
 	.init_irq = mx31_init_irq,
 	.handle_irq = imx31_handle_irq,
 	.timer = &mx31moboard_timer,
 	.init_machine = mx31moboard_init,
 	.restart	= mxc_restart,
 MACHINE_END

arch/arm/mach-imx/mach-pcm037.c

Diff comments View file @ 716a3dc

 /*
  *  Copyright (C) 2008 Sascha Hauer, Pengutronix
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
 #include <linux/types.h>
 #include <linux/init.h>
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/plat-ram.h>
 #include <linux/memory.h>
 #include <linux/gpio.h>
 #include <linux/smsc911x.h>
 #include <linux/interrupt.h>
 #include <linux/i2c.h>
 #include <linux/i2c/at24.h>
 #include <linux/delay.h>
 #include <linux/spi/spi.h>
 #include <linux/irq.h>
 #include <linux/can/platform/sja1000.h>
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
 #include <linux/gfp.h>
 #include <linux/memblock.h>
 #include <media/soc_camera.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
+#include <asm/memblock.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx3.h>
 #include <mach/ulpi.h>
 #include "devices-imx31.h"
 #include "pcm037.h"
 static enum pcm037_board_variant pcm037_instance = PCM037_PCM970;
 static int __init pcm037_variant_setup(char *str)
 {
 	if (!strcmp("eet", str))
 		pcm037_instance = PCM037_EET;
 	else if (strcmp("pcm970", str))
 		pr_warning("Unknown pcm037 baseboard variant %s\n", str);
 	return 1;
 }
 /* Supported values: "pcm970" (default) and "eet" */
 __setup("pcm037_variant=", pcm037_variant_setup);
 enum pcm037_board_variant pcm037_variant(void)
 {
 	return pcm037_instance;
 }
 /* UART1 with RTS/CTS handshake signals */
 static unsigned int pcm037_uart1_handshake_pins[] = {
 	MX31_PIN_CTS1__CTS1,
 	MX31_PIN_RTS1__RTS1,
 	MX31_PIN_TXD1__TXD1,
 	MX31_PIN_RXD1__RXD1,
 };
 /* UART1 without RTS/CTS handshake signals */
 static unsigned int pcm037_uart1_pins[] = {
 	MX31_PIN_TXD1__TXD1,
 	MX31_PIN_RXD1__RXD1,
 };
 static unsigned int pcm037_pins[] = {
 	/* I2C */
 	MX31_PIN_CSPI2_MOSI__SCL,
 	MX31_PIN_CSPI2_MISO__SDA,
 	MX31_PIN_CSPI2_SS2__I2C3_SDA,
 	MX31_PIN_CSPI2_SCLK__I2C3_SCL,
 	/* SDHC1 */
 	MX31_PIN_SD1_DATA3__SD1_DATA3,
 	MX31_PIN_SD1_DATA2__SD1_DATA2,
 	MX31_PIN_SD1_DATA1__SD1_DATA1,
 	MX31_PIN_SD1_DATA0__SD1_DATA0,
 	MX31_PIN_SD1_CLK__SD1_CLK,
 	MX31_PIN_SD1_CMD__SD1_CMD,
 	IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */
 	IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */
 	/* SPI1 */
 	MX31_PIN_CSPI1_MOSI__MOSI,
 	MX31_PIN_CSPI1_MISO__MISO,
 	MX31_PIN_CSPI1_SCLK__SCLK,
 	MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
 	MX31_PIN_CSPI1_SS0__SS0,
 	MX31_PIN_CSPI1_SS1__SS1,
 	MX31_PIN_CSPI1_SS2__SS2,
 	/* UART2 */
 	MX31_PIN_TXD2__TXD2,
 	MX31_PIN_RXD2__RXD2,
 	MX31_PIN_CTS2__CTS2,
 	MX31_PIN_RTS2__RTS2,
 	/* UART3 */
 	MX31_PIN_CSPI3_MOSI__RXD3,
 	MX31_PIN_CSPI3_MISO__TXD3,
 	MX31_PIN_CSPI3_SCLK__RTS3,
 	MX31_PIN_CSPI3_SPI_RDY__CTS3,
 	/* LAN9217 irq pin */
 	IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO),
 	/* Onewire */
 	MX31_PIN_BATT_LINE__OWIRE,
 	/* Framebuffer */
 	MX31_PIN_LD0__LD0,
 	MX31_PIN_LD1__LD1,
 	MX31_PIN_LD2__LD2,
 	MX31_PIN_LD3__LD3,
 	MX31_PIN_LD4__LD4,
 	MX31_PIN_LD5__LD5,
 	MX31_PIN_LD6__LD6,
 	MX31_PIN_LD7__LD7,
 	MX31_PIN_LD8__LD8,
 	MX31_PIN_LD9__LD9,
 	MX31_PIN_LD10__LD10,
 	MX31_PIN_LD11__LD11,
 	MX31_PIN_LD12__LD12,
 	MX31_PIN_LD13__LD13,
 	MX31_PIN_LD14__LD14,
 	MX31_PIN_LD15__LD15,
 	MX31_PIN_LD16__LD16,
 	MX31_PIN_LD17__LD17,
 	MX31_PIN_VSYNC3__VSYNC3,
 	MX31_PIN_HSYNC__HSYNC,
 	MX31_PIN_FPSHIFT__FPSHIFT,
 	MX31_PIN_DRDY0__DRDY0,
 	MX31_PIN_D3_REV__D3_REV,
 	MX31_PIN_CONTRAST__CONTRAST,
 	MX31_PIN_D3_SPL__D3_SPL,
 	MX31_PIN_D3_CLS__D3_CLS,
 	MX31_PIN_LCS0__GPI03_23,
 	/* CSI */
 	IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO),
 	MX31_PIN_CSI_D6__CSI_D6,
 	MX31_PIN_CSI_D7__CSI_D7,
 	MX31_PIN_CSI_D8__CSI_D8,
 	MX31_PIN_CSI_D9__CSI_D9,
 	MX31_PIN_CSI_D10__CSI_D10,
 	MX31_PIN_CSI_D11__CSI_D11,
 	MX31_PIN_CSI_D12__CSI_D12,
 	MX31_PIN_CSI_D13__CSI_D13,
 	MX31_PIN_CSI_D14__CSI_D14,
 	MX31_PIN_CSI_D15__CSI_D15,
 	MX31_PIN_CSI_HSYNC__CSI_HSYNC,
 	MX31_PIN_CSI_MCLK__CSI_MCLK,
 	MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
 	MX31_PIN_CSI_VSYNC__CSI_VSYNC,
 	/* GPIO */
 	IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO),
 	/* OTG */
 	MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
 	MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
 	MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
 	MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
 	MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
 	MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
 	MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
 	MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
 	MX31_PIN_USBOTG_CLK__USBOTG_CLK,
 	MX31_PIN_USBOTG_DIR__USBOTG_DIR,
 	MX31_PIN_USBOTG_NXT__USBOTG_NXT,
 	MX31_PIN_USBOTG_STP__USBOTG_STP,
 	/* USB host 2 */
 	IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
 	IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
 	IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
 	IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
 	IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
 	IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
 	IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
 	IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
 	IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
 	IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
 	IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
 	IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
 };
 static struct physmap_flash_data pcm037_flash_data = {
 	.width  = 2,
 };
 static struct resource pcm037_flash_resource = {
 	.start	= 0xa0000000,
 	.end	= 0xa1ffffff,
 	.flags	= IORESOURCE_MEM,
 };
 static struct platform_device pcm037_flash = {
 	.name	= "physmap-flash",
 	.id	= 0,
 	.dev	= {
 		.platform_data  = &pcm037_flash_data,
 	},
 	.resource = &pcm037_flash_resource,
 	.num_resources = 1,
 };
 static const struct imxuart_platform_data uart_pdata __initconst = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };
 static struct resource smsc911x_resources[] = {
 	{
 		.start		= MX31_CS1_BASE_ADDR + 0x300,
 		.end		= MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
 		.flags		= IORESOURCE_MEM,
 	}, {
 		.start		= IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
 		.end		= IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
 		.flags		= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
 	},
 };
 static struct smsc911x_platform_config smsc911x_info = {
 	.flags		= SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY |
 			  SMSC911X_SAVE_MAC_ADDRESS,
 	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
 	.irq_type	= SMSC911X_IRQ_TYPE_OPEN_DRAIN,
 	.phy_interface	= PHY_INTERFACE_MODE_MII,
 };
 static struct platform_device pcm037_eth = {
 	.name		= "smsc911x",
 	.id		= -1,
 	.num_resources	= ARRAY_SIZE(smsc911x_resources),
 	.resource	= smsc911x_resources,
 	.dev		= {
 		.platform_data = &smsc911x_info,
 	},
 };
 static struct platdata_mtd_ram pcm038_sram_data = {
 	.bankwidth = 2,
 };
 static struct resource pcm038_sram_resource = {
 	.start = MX31_CS4_BASE_ADDR,
 	.end   = MX31_CS4_BASE_ADDR + 512 * 1024 - 1,
 	.flags = IORESOURCE_MEM,
 };
 static struct platform_device pcm037_sram_device = {
 	.name = "mtd-ram",
 	.id = 0,
 	.dev = {
 		.platform_data = &pcm038_sram_data,
 	},
 	.num_resources = 1,
 	.resource = &pcm038_sram_resource,
 };
 static const struct mxc_nand_platform_data
 pcm037_nand_board_info __initconst = {
 	.width = 1,
 	.hw_ecc = 1,
 };
 static const struct imxi2c_platform_data pcm037_i2c1_data __initconst = {
 	.bitrate = 100000,
 };
 static const struct imxi2c_platform_data pcm037_i2c2_data __initconst = {
 	.bitrate = 20000,
 };
 static struct at24_platform_data board_eeprom = {
 	.byte_len = 4096,
 	.page_size = 32,
 	.flags = AT24_FLAG_ADDR16,
 };
 static int pcm037_camera_power(struct device *dev, int on)
 {
 	/* disable or enable the camera in X7 or X8 PCM970 connector */
 	gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), !on);
 	return 0;
 }
 static struct i2c_board_info pcm037_i2c_camera[] = {
 	{
 		I2C_BOARD_INFO("mt9t031", 0x5d),
 	}, {
 		I2C_BOARD_INFO("mt9v022", 0x48),
 	},
 };
 static struct soc_camera_link iclink_mt9v022 = {
 	.bus_id		= 0,		/* Must match with the camera ID */
 	.board_info	= &pcm037_i2c_camera[1],
 	.i2c_adapter_id	= 2,
 };
 static struct soc_camera_link iclink_mt9t031 = {
 	.bus_id		= 0,		/* Must match with the camera ID */
 	.power		= pcm037_camera_power,
 	.board_info	= &pcm037_i2c_camera[0],
 	.i2c_adapter_id	= 2,
 };
 static struct i2c_board_info pcm037_i2c_devices[] = {
 	{
 		I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
 		.platform_data = &board_eeprom,
 	}, {
 		I2C_BOARD_INFO("pcf8563", 0x51),
 	}
 };
 static struct platform_device pcm037_mt9t031 = {
 	.name	= "soc-camera-pdrv",
 	.id	= 0,
 	.dev	= {
 		.platform_data = &iclink_mt9t031,
 	},
 };
 static struct platform_device pcm037_mt9v022 = {
 	.name	= "soc-camera-pdrv",
 	.id	= 1,
 	.dev	= {
 		.platform_data = &iclink_mt9v022,
 	},
 };
 /* Not connected by default */
 #ifdef PCM970_SDHC_RW_SWITCH
 static int pcm970_sdhc1_get_ro(struct device *dev)
 {
 	return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6));
 }
 #endif
 #define SDHC1_GPIO_WP	IOMUX_TO_GPIO(MX31_PIN_SFS6)
 #define SDHC1_GPIO_DET	IOMUX_TO_GPIO(MX31_PIN_SCK6)
 static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
 		void *data)
 {
 	int ret;
 	ret = gpio_request(SDHC1_GPIO_DET, "sdhc-detect");
 	if (ret)
 		return ret;
 	gpio_direction_input(SDHC1_GPIO_DET);
 #ifdef PCM970_SDHC_RW_SWITCH
 	ret = gpio_request(SDHC1_GPIO_WP, "sdhc-wp");
 	if (ret)
 		goto err_gpio_free;
 	gpio_direction_input(SDHC1_GPIO_WP);
 #endif
 	ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), detect_irq,
 			IRQF_DISABLED | IRQF_TRIGGER_FALLING,
 				"sdhc-detect", data);
 	if (ret)
 		goto err_gpio_free_2;
 	return 0;
 err_gpio_free_2:
 #ifdef PCM970_SDHC_RW_SWITCH
 	gpio_free(SDHC1_GPIO_WP);
 err_gpio_free:
 #endif
 	gpio_free(SDHC1_GPIO_DET);
 	return ret;
 }
 static void pcm970_sdhc1_exit(struct device *dev, void *data)
 {
 	free_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), data);
 	gpio_free(SDHC1_GPIO_DET);
 	gpio_free(SDHC1_GPIO_WP);
 }
 static const struct imxmmc_platform_data sdhc_pdata __initconst = {
 #ifdef PCM970_SDHC_RW_SWITCH
 	.get_ro = pcm970_sdhc1_get_ro,
 #endif
 	.init = pcm970_sdhc1_init,
 	.exit = pcm970_sdhc1_exit,
 };
 struct mx3_camera_pdata camera_pdata __initdata = {
 	.flags		= MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
 	.mclk_10khz	= 2000,
 };
 static phys_addr_t mx3_camera_base __initdata;
 #define MX3_CAMERA_BUF_SIZE SZ_4M
 static int __init pcm037_init_camera(void)
 {
 	int dma, ret = -ENOMEM;
 	struct platform_device *pdev = imx31_alloc_mx3_camera(&camera_pdata);
 	if (IS_ERR(pdev))
 		return PTR_ERR(pdev);
 	dma = dma_declare_coherent_memory(&pdev->dev,
 					mx3_camera_base, mx3_camera_base,
 					MX3_CAMERA_BUF_SIZE,
 					DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
 	if (!(dma & DMA_MEMORY_MAP))
 		goto err;
 	ret = platform_device_add(pdev);
 	if (ret)
 err:
 		platform_device_put(pdev);
 	return ret;
 }
 static struct platform_device *devices[] __initdata = {
 	&pcm037_flash,
 	&pcm037_sram_device,
 	&pcm037_mt9t031,
 	&pcm037_mt9v022,
 };
 static const struct ipu_platform_data mx3_ipu_data __initconst = {
 	.irq_base = MXC_IPU_IRQ_START,
 };
 static const struct fb_videomode fb_modedb[] = {
 	{
 		/* 240x320 @ 60 Hz Sharp */
 		.name		= "Sharp-LQ035Q7DH06-QVGA",
 		.refresh	= 60,
 		.xres		= 240,
 		.yres		= 320,
 		.pixclock	= 185925,
 		.left_margin	= 9,
 		.right_margin	= 16,
 		.upper_margin	= 7,
 		.lower_margin	= 9,
 		.hsync_len	= 1,
 		.vsync_len	= 1,
 		.sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
 				  FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
 		.vmode		= FB_VMODE_NONINTERLACED,
 		.flag		= 0,
 	}, {
 		/* 240x320 @ 60 Hz */
 		.name		= "TX090",
 		.refresh	= 60,
 		.xres		= 240,
 		.yres		= 320,
 		.pixclock	= 38255,
 		.left_margin	= 144,
 		.right_margin	= 0,
 		.upper_margin	= 7,
 		.lower_margin	= 40,
 		.hsync_len	= 96,
 		.vsync_len	= 1,
 		.sync		= FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
 		.vmode		= FB_VMODE_NONINTERLACED,
 		.flag		= 0,
 	}, {
 		/* 240x320 @ 60 Hz */
 		.name		= "CMEL-OLED",
 		.refresh	= 60,
 		.xres		= 240,
 		.yres		= 320,
 		.pixclock	= 185925,
 		.left_margin	= 9,
 		.right_margin	= 16,
 		.upper_margin	= 7,
 		.lower_margin	= 9,
 		.hsync_len	= 1,
 		.vsync_len	= 1,
 		.sync		= FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
 		.vmode		= FB_VMODE_NONINTERLACED,
 		.flag		= 0,
 	},
 };
 static struct mx3fb_platform_data mx3fb_pdata = {
 	.name		= "Sharp-LQ035Q7DH06-QVGA",
 	.mode		= fb_modedb,
 	.num_modes	= ARRAY_SIZE(fb_modedb),
 };
 static struct resource pcm970_sja1000_resources[] = {
 	{
 		.start   = MX31_CS5_BASE_ADDR,
 		.end     = MX31_CS5_BASE_ADDR + 0x100 - 1,
 		.flags   = IORESOURCE_MEM,
 	}, {
 		.start   = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
 		.end     = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
 		.flags   = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 	},
 };
 struct sja1000_platform_data pcm970_sja1000_platform_data = {
 	.osc_freq	= 16000000,
 	.ocr		= OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
 	.cdr		= CDR_CBP,
 };
 static struct platform_device pcm970_sja1000 = {
 	.name = "sja1000_platform",
 	.dev = {
 		.platform_data = &pcm970_sja1000_platform_data,
 	},
 	.resource = pcm970_sja1000_resources,
 	.num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
 };
 static int pcm037_otg_init(struct platform_device *pdev)
 {
 	return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
 }
 static struct mxc_usbh_platform_data otg_pdata __initdata = {
 	.init	= pcm037_otg_init,
 	.portsc	= MXC_EHCI_MODE_ULPI,
 };
 static int pcm037_usbh2_init(struct platform_device *pdev)
 {
 	return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
 }
 static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
 	.init	= pcm037_usbh2_init,
 	.portsc	= MXC_EHCI_MODE_ULPI,
 };
 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
 	.operating_mode = FSL_USB2_DR_DEVICE,
 	.phy_mode       = FSL_USB2_PHY_ULPI,
 };
 static int otg_mode_host;
 static int __init pcm037_otg_mode(char *options)
 {
 	if (!strcmp(options, "host"))
 		otg_mode_host = 1;
 	else if (!strcmp(options, "device"))
 		otg_mode_host = 0;
 	else
 		pr_info("otg_mode neither \"host\" nor \"device\". "
 			"Defaulting to device\n");
 	return 0;
 }
 __setup("otg_mode=", pcm037_otg_mode);
 /*
  * Board specific initialization.
  */
 static void __init pcm037_init(void)
 {
 	int ret;
 	imx31_soc_init();
 	mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
 	mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
 			"pcm037");
 #define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \
 		| PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
 	mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
 	mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
 	mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG);	/* USBH2_DATA2 */
 	mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG);	/* USBH2_DATA3 */
 	mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG);	/* USBH2_DATA4 */
 	mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG);	/* USBH2_DATA5 */
 	mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG);	/* USBH2_DATA6 */
 	mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG);	/* USBH2_DATA7 */
 	if (pcm037_variant() == PCM037_EET)
 		mxc_iomux_setup_multiple_pins(pcm037_uart1_pins,
 			ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1");
 	else
 		mxc_iomux_setup_multiple_pins(pcm037_uart1_handshake_pins,
 			ARRAY_SIZE(pcm037_uart1_handshake_pins),
 			"pcm037_uart1");
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 	imx31_add_imx2_wdt(NULL);
 	imx31_add_imx_uart0(&uart_pdata);
 	/* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */
 	imx31_add_imx_uart1(&uart_pdata);
 	imx31_add_imx_uart2(&uart_pdata);
 	imx31_add_mxc_w1(NULL);
 	/* LAN9217 IRQ pin */
 	ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
 	if (ret)
 		pr_warning("could not get LAN irq gpio\n");
 	else {
 		gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
 		platform_device_register(&pcm037_eth);
 	}
 	/* I2C adapters and devices */
 	i2c_register_board_info(1, pcm037_i2c_devices,
 			ARRAY_SIZE(pcm037_i2c_devices));
 	imx31_add_imx_i2c1(&pcm037_i2c1_data);
 	imx31_add_imx_i2c2(&pcm037_i2c2_data);
 	imx31_add_mxc_nand(&pcm037_nand_board_info);
 	imx31_add_mxc_mmc(0, &sdhc_pdata);
 	imx31_add_ipu_core(&mx3_ipu_data);
 	imx31_add_mx3_sdc_fb(&mx3fb_pdata);
 	/* CSI */
 	/* Camera power: default - off */
 	ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), "mt9t031-power");
 	if (!ret)
 		gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), 1);
 	else
 		iclink_mt9t031.power = NULL;
 	pcm037_init_camera();
 	platform_device_register(&pcm970_sja1000);
 	if (otg_mode_host) {
 		otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
 				ULPI_OTG_DRVVBUS_EXT);
 		if (otg_pdata.otg)
 			imx31_add_mxc_ehci_otg(&otg_pdata);
 	}
 	usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
 			ULPI_OTG_DRVVBUS_EXT);
 	if (usbh2_pdata.otg)
 		imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
 	if (!otg_mode_host)
 		imx31_add_fsl_usb2_udc(&otg_device_pdata);
 }
 static void __init pcm037_timer_init(void)
 {
 	mx31_clocks_init(26000000);
 }
 struct sys_timer pcm037_timer = {
 	.init	= pcm037_timer_init,
 };
 static void __init pcm037_reserve(void)
 {
 	/* reserve 4 MiB for mx3-camera */
-	mx3_camera_base = memblock_alloc(MX3_CAMERA_BUF_SIZE,
+	mx3_camera_base = arm_memblock_steal(MX3_CAMERA_BUF_SIZE,
 			MX3_CAMERA_BUF_SIZE);
-	memblock_free(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
-	memblock_remove(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
 }
 MACHINE_START(PCM037, "Phytec Phycore pcm037")
 	/* Maintainer: Pengutronix */
 	.atag_offset = 0x100,
 	.reserve = pcm037_reserve,
 	.map_io = mx31_map_io,
 	.init_early = imx31_init_early,
 	.init_irq = mx31_init_irq,
 	.handle_irq = imx31_handle_irq,
 	.timer = &pcm037_timer,
 	.init_machine = pcm037_init,
 	.restart	= mxc_restart,
 MACHINE_END

arch/arm/mach-omap2/Kconfig

Diff comments View file @ 716a3dc

1	if ARCH_OMAP2PLUS	1	if ARCH_OMAP2PLUS
2		2
3	menu "TI OMAP2/3/4 Specific Features"	3	menu "TI OMAP2/3/4 Specific Features"
4		4
5	config ARCH_OMAP2PLUS_TYPICAL	5	config ARCH_OMAP2PLUS_TYPICAL
6	bool "Typical OMAP configuration"	6	bool "Typical OMAP configuration"
7	default y	7	default y
8	select AEABI	8	select AEABI
9	select REGULATOR	9	select REGULATOR
10	select PM_RUNTIME	10	select PM_RUNTIME
11	select VFP	11	select VFP
12	select NEON if ARCH_OMAP3 \|\| ARCH_OMAP4	12	select NEON if ARCH_OMAP3 \|\| ARCH_OMAP4
13	select SERIAL_OMAP	13	select SERIAL_OMAP
14	select SERIAL_OMAP_CONSOLE	14	select SERIAL_OMAP_CONSOLE
15	select I2C	15	select I2C
16	select I2C_OMAP	16	select I2C_OMAP
17	select MENELAUS if ARCH_OMAP2	17	select MENELAUS if ARCH_OMAP2
18	select TWL4030_CORE if ARCH_OMAP3 \|\| ARCH_OMAP4	18	select TWL4030_CORE if ARCH_OMAP3 \|\| ARCH_OMAP4
19	select TWL4030_POWER if ARCH_OMAP3 \|\| ARCH_OMAP4	19	select TWL4030_POWER if ARCH_OMAP3 \|\| ARCH_OMAP4
20	help	20	help
21	Compile a kernel suitable for booting most boards	21	Compile a kernel suitable for booting most boards
22		22
23	config ARCH_OMAP2	23	config ARCH_OMAP2
24	bool "TI OMAP2"	24	bool "TI OMAP2"
25	depends on ARCH_OMAP2PLUS	25	depends on ARCH_OMAP2PLUS
26	default y	26	default y
27	select CPU_V6	27	select CPU_V6
28	select MULTI_IRQ_HANDLER	28	select MULTI_IRQ_HANDLER
29		29
30	config ARCH_OMAP3	30	config ARCH_OMAP3
31	bool "TI OMAP3"	31	bool "TI OMAP3"
32	depends on ARCH_OMAP2PLUS	32	depends on ARCH_OMAP2PLUS
33	default y	33	default y
34	select CPU_V7	34	select CPU_V7
35	select USB_ARCH_HAS_EHCI	35	select USB_ARCH_HAS_EHCI
36	select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4	36	select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4
37	select ARCH_HAS_OPP	37	select ARCH_HAS_OPP
38	select PM_OPP if PM	38	select PM_OPP if PM
39	select ARM_CPU_SUSPEND if PM	39	select ARM_CPU_SUSPEND if PM
40	select MULTI_IRQ_HANDLER	40	select MULTI_IRQ_HANDLER
41		41
42	config ARCH_OMAP4	42	config ARCH_OMAP4
43	bool "TI OMAP4"	43	bool "TI OMAP4"
44	default y	44	default y
45	depends on ARCH_OMAP2PLUS	45	depends on ARCH_OMAP2PLUS
46	select CACHE_L2X0	46	select CACHE_L2X0
47	select CPU_V7	47	select CPU_V7
48	select ARM_GIC	48	select ARM_GIC
49	select HAVE_SMP	49	select HAVE_SMP
50	select LOCAL_TIMERS if SMP	50	select LOCAL_TIMERS if SMP
51	select PL310_ERRATA_588369	51	select PL310_ERRATA_588369
52	select PL310_ERRATA_727915	52	select PL310_ERRATA_727915
53	select ARM_ERRATA_720789	53	select ARM_ERRATA_720789
54	select ARCH_HAS_OPP	54	select ARCH_HAS_OPP
55	select PM_OPP if PM	55	select PM_OPP if PM
56	select USB_ARCH_HAS_EHCI	56	select USB_ARCH_HAS_EHCI
57	select ARM_CPU_SUSPEND if PM	57	select ARM_CPU_SUSPEND if PM
58		58
59	comment "OMAP Core Type"	59	comment "OMAP Core Type"
60	depends on ARCH_OMAP2	60	depends on ARCH_OMAP2
61		61
62	config SOC_OMAP2420	62	config SOC_OMAP2420
63	bool "OMAP2420 support"	63	bool "OMAP2420 support"
64	depends on ARCH_OMAP2	64	depends on ARCH_OMAP2
65	default y	65	default y
66	select OMAP_DM_TIMER	66	select OMAP_DM_TIMER
67	select ARCH_OMAP_OTG	67	select ARCH_OMAP_OTG
68		68
69	config SOC_OMAP2430	69	config SOC_OMAP2430
70	bool "OMAP2430 support"	70	bool "OMAP2430 support"
71	depends on ARCH_OMAP2	71	depends on ARCH_OMAP2
72	default y	72	default y
73	select ARCH_OMAP_OTG	73	select ARCH_OMAP_OTG
74		74
75	config SOC_OMAP3430	75	config SOC_OMAP3430
76	bool "OMAP3430 support"	76	bool "OMAP3430 support"
77	depends on ARCH_OMAP3	77	depends on ARCH_OMAP3
78	default y	78	default y
79	select ARCH_OMAP_OTG	79	select ARCH_OMAP_OTG
80		80
81	config SOC_OMAPTI81XX	81	config SOC_OMAPTI81XX
82	bool "TI81XX support"	82	bool "TI81XX support"
83	depends on ARCH_OMAP3	83	depends on ARCH_OMAP3
84	default y	84	default y
85		85
86	config SOC_OMAPAM33XX	86	config SOC_OMAPAM33XX
87	bool "AM33XX support"	87	bool "AM33XX support"
88	depends on ARCH_OMAP3	88	depends on ARCH_OMAP3
89	default y	89	default y
90		90
91	config OMAP_PACKAGE_ZAF	91	config OMAP_PACKAGE_ZAF
92	bool	92	bool
93		93
94	config OMAP_PACKAGE_ZAC	94	config OMAP_PACKAGE_ZAC
95	bool	95	bool
96		96
97	config OMAP_PACKAGE_CBC	97	config OMAP_PACKAGE_CBC
98	bool	98	bool
99		99
100	config OMAP_PACKAGE_CBB	100	config OMAP_PACKAGE_CBB
101	bool	101	bool
102		102
103	config OMAP_PACKAGE_CUS	103	config OMAP_PACKAGE_CUS
104	bool	104	bool
105		105
106	config OMAP_PACKAGE_CBP	106	config OMAP_PACKAGE_CBP
107	bool	107	bool
108		108
109	config OMAP_PACKAGE_CBL	109	config OMAP_PACKAGE_CBL
110	bool	110	bool
111		111
112	config OMAP_PACKAGE_CBS	112	config OMAP_PACKAGE_CBS
113	bool	113	bool
114		114
115	comment "OMAP Board Type"	115	comment "OMAP Board Type"
116	depends on ARCH_OMAP2PLUS	116	depends on ARCH_OMAP2PLUS
117		117
118	config MACH_OMAP_GENERIC	118	config MACH_OMAP_GENERIC
119	bool "Generic OMAP2+ board"	119	bool "Generic OMAP2+ board"
120	depends on ARCH_OMAP2PLUS	120	depends on ARCH_OMAP2PLUS
121	select USE_OF	121	select USE_OF
122	default y	122	default y
123	help	123	help
124	Support for generic TI OMAP2+ boards using Flattened Device Tree.	124	Support for generic TI OMAP2+ boards using Flattened Device Tree.
125	More information at Documentation/devicetree	125	More information at Documentation/devicetree
126		126
127	config MACH_OMAP2_TUSB6010	127	config MACH_OMAP2_TUSB6010
128	bool	128	bool
129	depends on ARCH_OMAP2 && SOC_OMAP2420	129	depends on ARCH_OMAP2 && SOC_OMAP2420
130	default y if MACH_NOKIA_N8X0	130	default y if MACH_NOKIA_N8X0
131		131
132	config MACH_OMAP_H4	132	config MACH_OMAP_H4
133	bool "OMAP 2420 H4 board"	133	bool "OMAP 2420 H4 board"
134	depends on SOC_OMAP2420	134	depends on SOC_OMAP2420
135	default y	135	default y
136	select OMAP_PACKAGE_ZAF	136	select OMAP_PACKAGE_ZAF
137	select OMAP_DEBUG_DEVICES	137	select OMAP_DEBUG_DEVICES
138		138
139	config MACH_OMAP_APOLLON	139	config MACH_OMAP_APOLLON
140	bool "OMAP 2420 Apollon board"	140	bool "OMAP 2420 Apollon board"
141	depends on SOC_OMAP2420	141	depends on SOC_OMAP2420
142	default y	142	default y
143	select OMAP_PACKAGE_ZAC	143	select OMAP_PACKAGE_ZAC
144		144
145	config MACH_OMAP_2430SDP	145	config MACH_OMAP_2430SDP
146	bool "OMAP 2430 SDP board"	146	bool "OMAP 2430 SDP board"
147	depends on SOC_OMAP2430	147	depends on SOC_OMAP2430
148	default y	148	default y
149	select OMAP_PACKAGE_ZAC	149	select OMAP_PACKAGE_ZAC
150		150
151	config MACH_OMAP3_BEAGLE	151	config MACH_OMAP3_BEAGLE
152	bool "OMAP3 BEAGLE board"	152	bool "OMAP3 BEAGLE board"
153	depends on ARCH_OMAP3	153	depends on ARCH_OMAP3
154	default y	154	default y
155	select OMAP_PACKAGE_CBB	155	select OMAP_PACKAGE_CBB
156		156
157	config MACH_DEVKIT8000	157	config MACH_DEVKIT8000
158	bool "DEVKIT8000 board"	158	bool "DEVKIT8000 board"
159	depends on ARCH_OMAP3	159	depends on ARCH_OMAP3
160	default y	160	default y
161	select OMAP_PACKAGE_CUS	161	select OMAP_PACKAGE_CUS
162		162
163	config MACH_OMAP_LDP	163	config MACH_OMAP_LDP
164	bool "OMAP3 LDP board"	164	bool "OMAP3 LDP board"
165	depends on ARCH_OMAP3	165	depends on ARCH_OMAP3
166	default y	166	default y
167	select OMAP_PACKAGE_CBB	167	select OMAP_PACKAGE_CBB
168		168
169	config MACH_OMAP3530_LV_SOM	169	config MACH_OMAP3530_LV_SOM
170	bool "OMAP3 Logic 3530 LV SOM board"	170	bool "OMAP3 Logic 3530 LV SOM board"
171	depends on ARCH_OMAP3	171	depends on ARCH_OMAP3
172	select OMAP_PACKAGE_CBB	172	select OMAP_PACKAGE_CBB
173	default y	173	default y
174	help	174	help
175	Support for the LogicPD OMAP3530 SOM Development kit	175	Support for the LogicPD OMAP3530 SOM Development kit
176	for full description please see the products webpage at	176	for full description please see the products webpage at
177	http://www.logicpd.com/products/development-kits/texas-instruments-zoom%E2%84%A2-omap35x-development-kit	177	http://www.logicpd.com/products/development-kits/texas-instruments-zoom%E2%84%A2-omap35x-development-kit
178		178
179	config MACH_OMAP3_TORPEDO	179	config MACH_OMAP3_TORPEDO
180	bool "OMAP3 Logic 35x Torpedo board"	180	bool "OMAP3 Logic 35x Torpedo board"
181	depends on ARCH_OMAP3	181	depends on ARCH_OMAP3
182	select OMAP_PACKAGE_CBB	182	select OMAP_PACKAGE_CBB
183	default y	183	default y
184	help	184	help
185	Support for the LogicPD OMAP35x Torpedo Development kit	185	Support for the LogicPD OMAP35x Torpedo Development kit
186	for full description please see the products webpage at	186	for full description please see the products webpage at
187	http://www.logicpd.com/products/development-kits/zoom-omap35x-torpedo-development-kit	187	http://www.logicpd.com/products/development-kits/zoom-omap35x-torpedo-development-kit
188		188
189	config MACH_OVERO	189	config MACH_OVERO
190	bool "Gumstix Overo board"	190	bool "Gumstix Overo board"
191	depends on ARCH_OMAP3	191	depends on ARCH_OMAP3
192	default y	192	default y
193	select OMAP_PACKAGE_CBB	193	select OMAP_PACKAGE_CBB
194		194
195	config MACH_OMAP3EVM	195	config MACH_OMAP3EVM
196	bool "OMAP 3530 EVM board"	196	bool "OMAP 3530 EVM board"
197	depends on ARCH_OMAP3	197	depends on ARCH_OMAP3
198	default y	198	default y
199	select OMAP_PACKAGE_CBB	199	select OMAP_PACKAGE_CBB
200		200
201	config MACH_OMAP3517EVM	201	config MACH_OMAP3517EVM
202	bool "OMAP3517/ AM3517 EVM board"	202	bool "OMAP3517/ AM3517 EVM board"
203	depends on ARCH_OMAP3	203	depends on ARCH_OMAP3
204	default y	204	default y
205	select OMAP_PACKAGE_CBB	205	select OMAP_PACKAGE_CBB
206		206
207	config MACH_CRANEBOARD	207	config MACH_CRANEBOARD
208	bool "AM3517/05 CRANE board"	208	bool "AM3517/05 CRANE board"
209	depends on ARCH_OMAP3	209	depends on ARCH_OMAP3
210	select OMAP_PACKAGE_CBB	210	select OMAP_PACKAGE_CBB
211		211
212	config MACH_OMAP3_PANDORA	212	config MACH_OMAP3_PANDORA
213	bool "OMAP3 Pandora"	213	bool "OMAP3 Pandora"
214	depends on ARCH_OMAP3	214	depends on ARCH_OMAP3
215	default y	215	default y
216	select OMAP_PACKAGE_CBB	216	select OMAP_PACKAGE_CBB
217	select REGULATOR_FIXED_VOLTAGE	217	select REGULATOR_FIXED_VOLTAGE
218		218
219	config MACH_OMAP3_TOUCHBOOK	219	config MACH_OMAP3_TOUCHBOOK
220	bool "OMAP3 Touch Book"	220	bool "OMAP3 Touch Book"
221	depends on ARCH_OMAP3	221	depends on ARCH_OMAP3
222	default y	222	default y
223	select BACKLIGHT_CLASS_DEVICE	223	select BACKLIGHT_CLASS_DEVICE
224		224
225	config MACH_OMAP_3430SDP	225	config MACH_OMAP_3430SDP
226	bool "OMAP 3430 SDP board"	226	bool "OMAP 3430 SDP board"
227	depends on ARCH_OMAP3	227	depends on ARCH_OMAP3
228	default y	228	default y
229	select OMAP_PACKAGE_CBB	229	select OMAP_PACKAGE_CBB
230		230
231	config MACH_NOKIA_N800	231	config MACH_NOKIA_N800
232	bool	232	bool
233		233
234	config MACH_NOKIA_N810	234	config MACH_NOKIA_N810
235	bool	235	bool
236		236
237	config MACH_NOKIA_N810_WIMAX	237	config MACH_NOKIA_N810_WIMAX
238	bool	238	bool
239		239
240	config MACH_NOKIA_N8X0	240	config MACH_NOKIA_N8X0
241	bool "Nokia N800/N810"	241	bool "Nokia N800/N810"
242	depends on SOC_OMAP2420	242	depends on SOC_OMAP2420
243	default y	243	default y
244	select OMAP_PACKAGE_ZAC	244	select OMAP_PACKAGE_ZAC
245	select MACH_NOKIA_N800	245	select MACH_NOKIA_N800
246	select MACH_NOKIA_N810	246	select MACH_NOKIA_N810
247	select MACH_NOKIA_N810_WIMAX	247	select MACH_NOKIA_N810_WIMAX
248		248
249	config MACH_NOKIA_RM680	249	config MACH_NOKIA_RM680
250	bool "Nokia RM-680 board"	250	bool "Nokia RM-680 board"
251	depends on ARCH_OMAP3	251	depends on ARCH_OMAP3
252	default y	252	default y
253	select OMAP_PACKAGE_CBB	253	select OMAP_PACKAGE_CBB
254		254
255	config MACH_NOKIA_RX51	255	config MACH_NOKIA_RX51
256	bool "Nokia RX-51 board"	256	bool "Nokia RX-51 board"
257	depends on ARCH_OMAP3	257	depends on ARCH_OMAP3
258	default y	258	default y
259	select OMAP_PACKAGE_CBB	259	select OMAP_PACKAGE_CBB
260		260
261	config MACH_OMAP_ZOOM2	261	config MACH_OMAP_ZOOM2
262	bool "OMAP3 Zoom2 board"	262	bool "OMAP3 Zoom2 board"
263	depends on ARCH_OMAP3	263	depends on ARCH_OMAP3
264	default y	264	default y
265	select OMAP_PACKAGE_CBB	265	select OMAP_PACKAGE_CBB
266	select SERIAL_8250	266	select SERIAL_8250
267	select SERIAL_CORE_CONSOLE	267	select SERIAL_CORE_CONSOLE
268	select SERIAL_8250_CONSOLE	268	select SERIAL_8250_CONSOLE
269	select REGULATOR_FIXED_VOLTAGE	269	select REGULATOR_FIXED_VOLTAGE
270		270
271	config MACH_OMAP_ZOOM3	271	config MACH_OMAP_ZOOM3
272	bool "OMAP3630 Zoom3 board"	272	bool "OMAP3630 Zoom3 board"
273	depends on ARCH_OMAP3	273	depends on ARCH_OMAP3
274	default y	274	default y
275	select OMAP_PACKAGE_CBP	275	select OMAP_PACKAGE_CBP
276	select SERIAL_8250	276	select SERIAL_8250
277	select SERIAL_CORE_CONSOLE	277	select SERIAL_CORE_CONSOLE
278	select SERIAL_8250_CONSOLE	278	select SERIAL_8250_CONSOLE
279	select REGULATOR_FIXED_VOLTAGE	279	select REGULATOR_FIXED_VOLTAGE
280		280
281	config MACH_CM_T35	281	config MACH_CM_T35
282	bool "CompuLab CM-T35/CM-T3730 modules"	282	bool "CompuLab CM-T35/CM-T3730 modules"
283	depends on ARCH_OMAP3	283	depends on ARCH_OMAP3
284	default y	284	default y
285	select MACH_CM_T3730	285	select MACH_CM_T3730
286	select OMAP_PACKAGE_CUS	286	select OMAP_PACKAGE_CUS
287		287
288	config MACH_CM_T3517	288	config MACH_CM_T3517
289	bool "CompuLab CM-T3517 module"	289	bool "CompuLab CM-T3517 module"
290	depends on ARCH_OMAP3	290	depends on ARCH_OMAP3
291	default y	291	default y
292	select OMAP_PACKAGE_CBB	292	select OMAP_PACKAGE_CBB
293		293
294	config MACH_CM_T3730	294	config MACH_CM_T3730
295	bool	295	bool
296		296
297	config MACH_IGEP0020	297	config MACH_IGEP0020
298	bool "IGEP v2 board"	298	bool "IGEP v2 board"
299	depends on ARCH_OMAP3	299	depends on ARCH_OMAP3
300	default y	300	default y
301	select OMAP_PACKAGE_CBB	301	select OMAP_PACKAGE_CBB
302		302
303	config MACH_IGEP0030	303	config MACH_IGEP0030
304	bool "IGEP OMAP3 module"	304	bool "IGEP OMAP3 module"
305	depends on ARCH_OMAP3	305	depends on ARCH_OMAP3
306	default y	306	default y
307	select OMAP_PACKAGE_CBB	307	select OMAP_PACKAGE_CBB
308	select MACH_IGEP0020	308	select MACH_IGEP0020
309		309
310	config MACH_SBC3530	310	config MACH_SBC3530
311	bool "OMAP3 SBC STALKER board"	311	bool "OMAP3 SBC STALKER board"
312	depends on ARCH_OMAP3	312	depends on ARCH_OMAP3
313	default y	313	default y
314	select OMAP_PACKAGE_CUS	314	select OMAP_PACKAGE_CUS
315		315
316	config MACH_OMAP_3630SDP	316	config MACH_OMAP_3630SDP
317	bool "OMAP3630 SDP board"	317	bool "OMAP3630 SDP board"
318	depends on ARCH_OMAP3	318	depends on ARCH_OMAP3
319	default y	319	default y
320	select OMAP_PACKAGE_CBP	320	select OMAP_PACKAGE_CBP
321		321
322	config MACH_TI8168EVM	322	config MACH_TI8168EVM
323	bool "TI8168 Evaluation Module"	323	bool "TI8168 Evaluation Module"
324	depends on SOC_OMAPTI81XX	324	depends on SOC_OMAPTI81XX
325	default y	325	default y
326		326
327	config MACH_TI8148EVM	327	config MACH_TI8148EVM
328	bool "TI8148 Evaluation Module"	328	bool "TI8148 Evaluation Module"
329	depends on SOC_OMAPTI81XX	329	depends on SOC_OMAPTI81XX
330	default y	330	default y
331		331
332	config MACH_OMAP_4430SDP	332	config MACH_OMAP_4430SDP
333	bool "OMAP 4430 SDP board"	333	bool "OMAP 4430 SDP board"
334	default y	334	default y
335	depends on ARCH_OMAP4	335	depends on ARCH_OMAP4
336	select OMAP_PACKAGE_CBL	336	select OMAP_PACKAGE_CBL
337	select OMAP_PACKAGE_CBS	337	select OMAP_PACKAGE_CBS
338	select REGULATOR_FIXED_VOLTAGE	338	select REGULATOR_FIXED_VOLTAGE
339		339
340	config MACH_OMAP4_PANDA	340	config MACH_OMAP4_PANDA
341	bool "OMAP4 Panda Board"	341	bool "OMAP4 Panda Board"
342	default y	342	default y
343	depends on ARCH_OMAP4	343	depends on ARCH_OMAP4
344	select OMAP_PACKAGE_CBL	344	select OMAP_PACKAGE_CBL
345	select OMAP_PACKAGE_CBS	345	select OMAP_PACKAGE_CBS
346	select REGULATOR_FIXED_VOLTAGE	346	select REGULATOR_FIXED_VOLTAGE
347		347
348	config OMAP3_EMU	348	config OMAP3_EMU
349	bool "OMAP3 debugging peripherals"	349	bool "OMAP3 debugging peripherals"
350	depends on ARCH_OMAP3	350	depends on ARCH_OMAP3
351	select ARM_AMBA	351	select ARM_AMBA
352	select OC_ETM	352	select OC_ETM
353	help	353	help
354	Say Y here to enable debugging hardware of omap3	354	Say Y here to enable debugging hardware of omap3
355		355
356	config OMAP3_SDRC_AC_TIMING	356	config OMAP3_SDRC_AC_TIMING
357	bool "Enable SDRC AC timing register changes"	357	bool "Enable SDRC AC timing register changes"
358	depends on ARCH_OMAP3	358	depends on ARCH_OMAP3
359	default n	359	default n
360	help	360	help
361	If you know that none of your system initiators will attempt to	361	If you know that none of your system initiators will attempt to
362	access SDRAM during CORE DVFS, select Y here. This should boost	362	access SDRAM during CORE DVFS, select Y here. This should boost
363	SDRAM performance at lower CORE OPPs. There are relatively few	363	SDRAM performance at lower CORE OPPs. There are relatively few
364	users who will wish to say yes at this point - almost everyone will	364	users who will wish to say yes at this point - almost everyone will
365	wish to say no. Selecting yes without understanding what is	365	wish to say no. Selecting yes without understanding what is
366	going on could result in system crashes;	366	going on could result in system crashes;
367		367
368	config OMAP4_ERRATA_I688	368	config OMAP4_ERRATA_I688
369	bool "OMAP4 errata: Async Bridge Corruption"	369	bool "OMAP4 errata: Async Bridge Corruption (BROKEN)"
370	depends on ARCH_OMAP4	370	depends on ARCH_OMAP4 && BROKEN
371	select ARCH_HAS_BARRIERS	371	select ARCH_HAS_BARRIERS
372	help	372	help
373	If a data is stalled inside asynchronous bridge because of back	373	If a data is stalled inside asynchronous bridge because of back
374	pressure, it may be accepted multiple times, creating pointer	374	pressure, it may be accepted multiple times, creating pointer
375	misalignment that will corrupt next transfers on that data path	375	misalignment that will corrupt next transfers on that data path
376	until next reset of the system (No recovery procedure once the	376	until next reset of the system (No recovery procedure once the
377	issue is hit, the path remains consistently broken). Async bridge	377	issue is hit, the path remains consistently broken). Async bridge
378	can be found on path between MPU to EMIF and MPU to L3 interconnect.	378	can be found on path between MPU to EMIF and MPU to L3 interconnect.
379	This situation can happen only when the idle is initiated by a	379	This situation can happen only when the idle is initiated by a
380	Master Request Disconnection (which is trigged by software when	380	Master Request Disconnection (which is trigged by software when
381	executing WFI on CPU).	381	executing WFI on CPU).
382	The work-around for this errata needs all the initiators connected	382	The work-around for this errata needs all the initiators connected
383	through async bridge must ensure that data path is properly drained	383	through async bridge must ensure that data path is properly drained
384	before issuing WFI. This condition will be met if one Strongly ordered	384	before issuing WFI. This condition will be met if one Strongly ordered
385	access is performed to the target right before executing the WFI.	385	access is performed to the target right before executing the WFI.
386	In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.	386	In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
387	IO barrier ensure that there is no synchronisation loss on initiators	387	IO barrier ensure that there is no synchronisation loss on initiators
388	operating on both interconnect port simultaneously.	388	operating on both interconnect port simultaneously.
389	endmenu	389	endmenu
390		390
391	endif	391	endif
392		392

arch/arm/mach-omap2/omap-secure.c

Diff comments View file @ 716a3dc

 /*
  * OMAP Secure API infrastructure.
  *
  * Copyright (C) 2011 Texas Instruments, Inc.
  *	Santosh Shilimkar <santosh.shilimkar@ti.com>
  *
  *
  * This program is free software,you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/memblock.h>
 #include <asm/cacheflush.h>
+#include <asm/memblock.h>
 #include <mach/omap-secure.h>
 static phys_addr_t omap_secure_memblock_base;
 /**
  * omap_sec_dispatcher: Routine to dispatch low power secure
  * service routines
  * @idx: The HAL API index
  * @flag: The flag indicating criticality of operation
  * @nargs: Number of valid arguments out of four.
  * @arg1, arg2, arg3 args4: Parameters passed to secure API
  *
  * Return the non-zero error value on failure.
  */
 u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2,
 							 u32 arg3, u32 arg4)
 {
 	u32 ret;
 	u32 param[5];
 	param[0] = nargs;
 	param[1] = arg1;
 	param[2] = arg2;
 	param[3] = arg3;
 	param[4] = arg4;
 	/*
 	 * Secure API needs physical address
 	 * pointer for the parameters
 	 */
 	flush_cache_all();
 	outer_clean_range(__pa(param), __pa(param + 5));
 	ret = omap_smc2(idx, flag, __pa(param));
 	return ret;
 }
 /* Allocate the memory to save secure ram */
 int __init omap_secure_ram_reserve_memblock(void)
 {
-	phys_addr_t paddr;
 	u32 size = OMAP_SECURE_RAM_STORAGE;
 	size = ALIGN(size, SZ_1M);
-	paddr = memblock_alloc(size, SZ_1M);
+	omap_secure_memblock_base = arm_memblock_steal(size, SZ_1M);
-	if (!paddr) {
-		pr_err("%s: failed to reserve %x bytes\n",
-				__func__, size);
-		return -ENOMEM;
-	}
-	memblock_free(paddr, size);
-	memblock_remove(paddr, size);
-	omap_secure_memblock_base = paddr;
 	return 0;
 }
 phys_addr_t omap_secure_ram_mempool_base(void)
 {
 	return omap_secure_memblock_base;
 }

arch/arm/mach-omap2/omap4-common.c

Diff comments View file @ 716a3dc

1	/*	1	/*
2	* OMAP4 specific common source file.	2	* OMAP4 specific common source file.
3	*	3	*
4	* Copyright (C) 2010 Texas Instruments, Inc.	4	* Copyright (C) 2010 Texas Instruments, Inc.
5	* Author:	5	* Author:
6	* Santosh Shilimkar <santosh.shilimkar@ti.com>	6	* Santosh Shilimkar <santosh.shilimkar@ti.com>
7	*	7	*
8	*	8	*
9	* This program is free software,you can redistribute it and/or modify	9	* This program is free software,you can redistribute it and/or modify
10	* it under the terms of the GNU General Public License version 2 as	10	* it under the terms of the GNU General Public License version 2 as
11	* published by the Free Software Foundation.	11	* published by the Free Software Foundation.
12	*/	12	*/
13		13
14	#include <linux/kernel.h>	14	#include <linux/kernel.h>
15	#include <linux/init.h>	15	#include <linux/init.h>
16	#include <linux/io.h>	16	#include <linux/io.h>
17	#include <linux/platform_device.h>	17	#include <linux/platform_device.h>
18	#include <linux/memblock.h>	18	#include <linux/memblock.h>
19		19
20	#include <asm/hardware/gic.h>	20	#include <asm/hardware/gic.h>
21	#include <asm/hardware/cache-l2x0.h>	21	#include <asm/hardware/cache-l2x0.h>
22	#include <asm/mach/map.h>	22	#include <asm/mach/map.h>
		23	#include <asm/memblock.h>
23		24
24	#include <plat/irqs.h>	25	#include <plat/irqs.h>
25	#include <plat/sram.h>	26	#include <plat/sram.h>
26		27
27	#include <mach/hardware.h>	28	#include <mach/hardware.h>
28	#include <mach/omap-wakeupgen.h>	29	#include <mach/omap-wakeupgen.h>
29		30
30	#include "common.h"	31	#include "common.h"
31	#include "omap4-sar-layout.h"	32	#include "omap4-sar-layout.h"
32		33
33	#ifdef CONFIG_CACHE_L2X0	34	#ifdef CONFIG_CACHE_L2X0
34	static void __iomem *l2cache_base;	35	static void __iomem *l2cache_base;
35	#endif	36	#endif
36		37
37	static void __iomem *sar_ram_base;	38	static void __iomem *sar_ram_base;
38		39
39	#ifdef CONFIG_OMAP4_ERRATA_I688	40	#ifdef CONFIG_OMAP4_ERRATA_I688
40	/* Used to implement memory barrier on DRAM path */	41	/* Used to implement memory barrier on DRAM path */
41	#define OMAP4_DRAM_BARRIER_VA 0xfe600000	42	#define OMAP4_DRAM_BARRIER_VA 0xfe600000
42		43
43	void __iomem dram_sync, sram_sync;	44	void __iomem dram_sync, sram_sync;
44		45
45	void omap_bus_sync(void)	46	void omap_bus_sync(void)
46	{	47	{
47	if (dram_sync && sram_sync) {	48	if (dram_sync && sram_sync) {
48	writel_relaxed(readl_relaxed(dram_sync), dram_sync);	49	writel_relaxed(readl_relaxed(dram_sync), dram_sync);
49	writel_relaxed(readl_relaxed(sram_sync), sram_sync);	50	writel_relaxed(readl_relaxed(sram_sync), sram_sync);
50	isb();	51	isb();
51	}	52	}
52	}	53	}
53		54
54	static int __init omap_barriers_init(void)	55	static int __init omap_barriers_init(void)
55	{	56	{
56	struct map_desc dram_io_desc[1];	57	struct map_desc dram_io_desc[1];
57	phys_addr_t paddr;	58	phys_addr_t paddr;
58	u32 size;	59	u32 size;
59		60
60	if (!cpu_is_omap44xx())	61	if (!cpu_is_omap44xx())
61	return -ENODEV;	62	return -ENODEV;
62		63
63	size = ALIGN(PAGE_SIZE, SZ_1M);	64	size = ALIGN(PAGE_SIZE, SZ_1M);
64	paddr = memblock_alloc(size, SZ_1M);	65	paddr = arm_memblock_steal(size, SZ_1M);
65	if (!paddr) {	66
66	pr_err("%s: failed to reserve 4 Kbytes\n", __func__);
67	return -ENOMEM;
68	}
69	memblock_free(paddr, size);
70	memblock_remove(paddr, size);
71	dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;	67	dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
72	dram_io_desc[0].pfn = __phys_to_pfn(paddr);	68	dram_io_desc[0].pfn = __phys_to_pfn(paddr);
73	dram_io_desc[0].length = size;	69	dram_io_desc[0].length = size;
74	dram_io_desc[0].type = MT_MEMORY_SO;	70	dram_io_desc[0].type = MT_MEMORY_SO;
75	iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));	71	iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
76	dram_sync = (void __iomem *) dram_io_desc[0].virtual;	72	dram_sync = (void __iomem *) dram_io_desc[0].virtual;
77	sram_sync = (void __iomem *) OMAP4_SRAM_VA;	73	sram_sync = (void __iomem *) OMAP4_SRAM_VA;
78		74
79	pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",	75	pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
80	(long long) paddr, dram_io_desc[0].virtual);	76	(long long) paddr, dram_io_desc[0].virtual);
81		77
82	return 0;	78	return 0;
83	}	79	}
84	core_initcall(omap_barriers_init);	80	core_initcall(omap_barriers_init);
85	#endif	81	#endif
86		82
87	void __init gic_init_irq(void)	83	void __init gic_init_irq(void)
88	{	84	{
89	void __iomem *omap_irq_base;	85	void __iomem *omap_irq_base;
90	void __iomem *gic_dist_base_addr;	86	void __iomem *gic_dist_base_addr;
91		87
92	/* Static mapping, never released */	88	/* Static mapping, never released */
93	gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);	89	gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
94	BUG_ON(!gic_dist_base_addr);	90	BUG_ON(!gic_dist_base_addr);
95		91
96	/* Static mapping, never released */	92	/* Static mapping, never released */
97	omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);	93	omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
98	BUG_ON(!omap_irq_base);	94	BUG_ON(!omap_irq_base);
99		95
100	omap_wakeupgen_init();	96	omap_wakeupgen_init();
101		97
102	gic_init(0, 29, gic_dist_base_addr, omap_irq_base);	98	gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
103	}	99	}
104		100
105	#ifdef CONFIG_CACHE_L2X0	101	#ifdef CONFIG_CACHE_L2X0
106		102
107	void __iomem *omap4_get_l2cache_base(void)	103	void __iomem *omap4_get_l2cache_base(void)
108	{	104	{
109	return l2cache_base;	105	return l2cache_base;
110	}	106	}
111		107
112	static void omap4_l2x0_disable(void)	108	static void omap4_l2x0_disable(void)
113	{	109	{
114	/* Disable PL310 L2 Cache controller */	110	/* Disable PL310 L2 Cache controller */
115	omap_smc1(0x102, 0x0);	111	omap_smc1(0x102, 0x0);
116	}	112	}
117		113
118	static void omap4_l2x0_set_debug(unsigned long val)	114	static void omap4_l2x0_set_debug(unsigned long val)
119	{	115	{
120	/* Program PL310 L2 Cache controller debug register */	116	/* Program PL310 L2 Cache controller debug register */
121	omap_smc1(0x100, val);	117	omap_smc1(0x100, val);
122	}	118	}
123		119
124	static int __init omap_l2_cache_init(void)	120	static int __init omap_l2_cache_init(void)
125	{	121	{
126	u32 aux_ctrl = 0;	122	u32 aux_ctrl = 0;
127		123
128	/*	124	/*
129	* To avoid code running on other OMAPs in	125	* To avoid code running on other OMAPs in
130	* multi-omap builds	126	* multi-omap builds
131	*/	127	*/
132	if (!cpu_is_omap44xx())	128	if (!cpu_is_omap44xx())
133	return -ENODEV;	129	return -ENODEV;
134		130
135	/* Static mapping, never released */	131	/* Static mapping, never released */
136	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);	132	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
137	if (WARN_ON(!l2cache_base))	133	if (WARN_ON(!l2cache_base))
138	return -ENOMEM;	134	return -ENOMEM;
139		135
140	/*	136	/*
141	* 16-way associativity, parity disabled	137	* 16-way associativity, parity disabled
142	* Way size - 32KB (es1.0)	138	* Way size - 32KB (es1.0)
143	* Way size - 64KB (es2.0 +)	139	* Way size - 64KB (es2.0 +)
144	*/	140	*/
145	aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) \|	141	aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) \|
146	(0x1 << 25) \|	142	(0x1 << 25) \|
147	(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) \|	143	(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) \|
148	(0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));	144	(0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
149		145
150	if (omap_rev() == OMAP4430_REV_ES1_0) {	146	if (omap_rev() == OMAP4430_REV_ES1_0) {
151	aux_ctrl \|= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;	147	aux_ctrl \|= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
152	} else {	148	} else {
153	aux_ctrl \|= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) \|	149	aux_ctrl \|= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) \|
154	(1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) \|	150	(1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) \|
155	(1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) \|	151	(1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) \|
156	(1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) \|	152	(1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) \|
157	(1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));	153	(1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
158	}	154	}
159	if (omap_rev() != OMAP4430_REV_ES1_0)	155	if (omap_rev() != OMAP4430_REV_ES1_0)
160	omap_smc1(0x109, aux_ctrl);	156	omap_smc1(0x109, aux_ctrl);
161		157
162	/* Enable PL310 L2 Cache controller */	158	/* Enable PL310 L2 Cache controller */
163	omap_smc1(0x102, 0x1);	159	omap_smc1(0x102, 0x1);
164		160
165	l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);	161	l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
166		162
167	/*	163	/*
168	* Override default outer_cache.disable with a OMAP4	164	* Override default outer_cache.disable with a OMAP4
169	* specific one	165	* specific one
170	*/	166	*/
171	outer_cache.disable = omap4_l2x0_disable;	167	outer_cache.disable = omap4_l2x0_disable;
172	outer_cache.set_debug = omap4_l2x0_set_debug;	168	outer_cache.set_debug = omap4_l2x0_set_debug;
173		169
174	return 0;	170	return 0;
175	}	171	}
176	early_initcall(omap_l2_cache_init);	172	early_initcall(omap_l2_cache_init);
177	#endif	173	#endif
178		174
179	void __iomem *omap4_get_sar_ram_base(void)	175	void __iomem *omap4_get_sar_ram_base(void)
180	{	176	{
181	return sar_ram_base;	177	return sar_ram_base;
182	}	178	}
183		179
184	/*	180	/*
185	* SAR RAM used to save and restore the HW	181	* SAR RAM used to save and restore the HW
186	* context in low power modes	182	* context in low power modes
187	*/	183	*/
188	static int __init omap4_sar_ram_init(void)	184	static int __init omap4_sar_ram_init(void)
189	{	185	{
190	/*	186	/*
191	* To avoid code running on other OMAPs in	187	* To avoid code running on other OMAPs in
192	* multi-omap builds	188	* multi-omap builds
193	*/	189	*/
194	if (!cpu_is_omap44xx())	190	if (!cpu_is_omap44xx())
195	return -ENOMEM;	191	return -ENOMEM;
196		192
197	/* Static mapping, never released */	193	/* Static mapping, never released */
198	sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K);	194	sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K);
199	if (WARN_ON(!sar_ram_base))	195	if (WARN_ON(!sar_ram_base))
200	return -ENOMEM;	196	return -ENOMEM;
201		197
202	return 0;	198	return 0;
203	}	199	}
204	early_initcall(omap4_sar_ram_init);	200	early_initcall(omap4_sar_ram_init);

arch/arm/mm/init.c

Diff comments View file @ 716a3dc

 /*
  *  linux/arch/arm/mm/init.c
  *
  *  Copyright (C) 1995-2005 Russell King
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/swap.h>
 #include <linux/init.h>
 #include <linux/bootmem.h>
 #include <linux/mman.h>
 #include <linux/export.h>
 #include <linux/nodemask.h>
 #include <linux/initrd.h>
 #include <linux/of_fdt.h>
 #include <linux/highmem.h>
 #include <linux/gfp.h>
 #include <linux/memblock.h>
 #include <asm/mach-types.h>
+#include <asm/memblock.h>
 #include <asm/prom.h>
 #include <asm/sections.h>
 #include <asm/setup.h>
 #include <asm/sizes.h>
 #include <asm/tlb.h>
 #include <asm/fixmap.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/memblock.h>
 #include "mm.h"
 static unsigned long phys_initrd_start __initdata = 0;
 static unsigned long phys_initrd_size __initdata = 0;
 static int __init early_initrd(char *p)
 {
 	unsigned long start, size;
 	char *endp;
 	start = memparse(p, &endp);
 	if (*endp == ',') {
 		size = memparse(endp + 1, NULL);
 		phys_initrd_start = start;
 		phys_initrd_size = size;
 	}
 	return 0;
 }
 early_param("initrd", early_initrd);
 static int __init parse_tag_initrd(const struct tag *tag)
 {
 	printk(KERN_WARNING "ATAG_INITRD is deprecated; "
 		"please update your bootloader.\n");
 	phys_initrd_start = __virt_to_phys(tag->u.initrd.start);
 	phys_initrd_size = tag->u.initrd.size;
 	return 0;
 }
 __tagtable(ATAG_INITRD, parse_tag_initrd);
 static int __init parse_tag_initrd2(const struct tag *tag)
 {
 	phys_initrd_start = tag->u.initrd.start;
 	phys_initrd_size = tag->u.initrd.size;
 	return 0;
 }
 __tagtable(ATAG_INITRD2, parse_tag_initrd2);
 #ifdef CONFIG_OF_FLATTREE
 void __init early_init_dt_setup_initrd_arch(unsigned long start, unsigned long end)
 {
 	phys_initrd_start = start;
 	phys_initrd_size = end - start;
 }
 #endif /* CONFIG_OF_FLATTREE */
 /*
  * This keeps memory configuration data used by a couple memory
  * initialization functions, as well as show_mem() for the skipping
  * of holes in the memory map.  It is populated by arm_add_memory().
  */
 struct meminfo meminfo;
 void show_mem(unsigned int filter)
 {
 	int free = 0, total = 0, reserved = 0;
 	int shared = 0, cached = 0, slab = 0, i;
 	struct meminfo * mi = &meminfo;
 	printk("Mem-info:\n");
 	show_free_areas(filter);
 	for_each_bank (i, mi) {
 		struct membank *bank = &mi->bank[i];
 		unsigned int pfn1, pfn2;
 		struct page *page, *end;
 		pfn1 = bank_pfn_start(bank);
 		pfn2 = bank_pfn_end(bank);
 		page = pfn_to_page(pfn1);
 		end  = pfn_to_page(pfn2 - 1) + 1;
 		do {
 			total++;
 			if (PageReserved(page))
 				reserved++;
 			else if (PageSwapCache(page))
 				cached++;
 			else if (PageSlab(page))
 				slab++;
 			else if (!page_count(page))
 				free++;
 			else
 				shared += page_count(page) - 1;
 			page++;
 		} while (page < end);
 	}
 	printk("%d pages of RAM\n", total);
 	printk("%d free pages\n", free);
 	printk("%d reserved pages\n", reserved);
 	printk("%d slab pages\n", slab);
 	printk("%d pages shared\n", shared);
 	printk("%d pages swap cached\n", cached);
 }
 static void __init find_limits(unsigned long *min, unsigned long *max_low,
 			       unsigned long *max_high)
 {
 	struct meminfo *mi = &meminfo;
 	int i;
 	/* This assumes the meminfo array is properly sorted */
 	*min = bank_pfn_start(&mi->bank[0]);
 	for_each_bank (i, mi)
 		if (mi->bank[i].highmem)
 				break;
 	*max_low = bank_pfn_end(&mi->bank[i - 1]);
 	*max_high = bank_pfn_end(&mi->bank[mi->nr_banks - 1]);
 }
 static void __init arm_bootmem_init(unsigned long start_pfn,
 	unsigned long end_pfn)
 {
 	struct memblock_region *reg;
 	unsigned int boot_pages;
 	phys_addr_t bitmap;
 	pg_data_t *pgdat;
 	/*
 	 * Allocate the bootmem bitmap page.  This must be in a region
 	 * of memory which has already been mapped.
 	 */
 	boot_pages = bootmem_bootmap_pages(end_pfn - start_pfn);
 	bitmap = memblock_alloc_base(boot_pages << PAGE_SHIFT, L1_CACHE_BYTES,
 				__pfn_to_phys(end_pfn));
 	/*
 	 * Initialise the bootmem allocator, handing the
 	 * memory banks over to bootmem.
 	 */
 	node_set_online(0);
 	pgdat = NODE_DATA(0);
 	init_bootmem_node(pgdat, __phys_to_pfn(bitmap), start_pfn, end_pfn);
 	/* Free the lowmem regions from memblock into bootmem. */
 	for_each_memblock(memory, reg) {
 		unsigned long start = memblock_region_memory_base_pfn(reg);
 		unsigned long end = memblock_region_memory_end_pfn(reg);
 		if (end >= end_pfn)
 			end = end_pfn;
 		if (start >= end)
 			break;
 		free_bootmem(__pfn_to_phys(start), (end - start) << PAGE_SHIFT);
 	}
 	/* Reserve the lowmem memblock reserved regions in bootmem. */
 	for_each_memblock(reserved, reg) {
 		unsigned long start = memblock_region_reserved_base_pfn(reg);
 		unsigned long end = memblock_region_reserved_end_pfn(reg);
 		if (end >= end_pfn)
 			end = end_pfn;
 		if (start >= end)
 			break;
 		reserve_bootmem(__pfn_to_phys(start),
 			        (end - start) << PAGE_SHIFT, BOOTMEM_DEFAULT);
 	}
 }
 #ifdef CONFIG_ZONE_DMA
 unsigned long arm_dma_zone_size __read_mostly;
 EXPORT_SYMBOL(arm_dma_zone_size);
 /*
  * The DMA mask corresponding to the maximum bus address allocatable
  * using GFP_DMA.  The default here places no restriction on DMA
  * allocations.  This must be the smallest DMA mask in the system,
  * so a successful GFP_DMA allocation will always satisfy this.
  */
 u32 arm_dma_limit;
 static void __init arm_adjust_dma_zone(unsigned long *size, unsigned long *hole,
 	unsigned long dma_size)
 {
 	if (size[0] <= dma_size)
 		return;
 	size[ZONE_NORMAL] = size[0] - dma_size;
 	size[ZONE_DMA] = dma_size;
 	hole[ZONE_NORMAL] = hole[0];
 	hole[ZONE_DMA] = 0;
 }
 #endif
 static void __init arm_bootmem_free(unsigned long min, unsigned long max_low,
 	unsigned long max_high)
 {
 	unsigned long zone_size[MAX_NR_ZONES], zhole_size[MAX_NR_ZONES];
 	struct memblock_region *reg;
 	/*
 	 * initialise the zones.
 	 */
 	memset(zone_size, 0, sizeof(zone_size));
 	/*
 	 * The memory size has already been determined.  If we need
 	 * to do anything fancy with the allocation of this memory
 	 * to the zones, now is the time to do it.
 	 */
 	zone_size[0] = max_low - min;
 #ifdef CONFIG_HIGHMEM
 	zone_size[ZONE_HIGHMEM] = max_high - max_low;
 #endif
 	/*
 	 * Calculate the size of the holes.
 	 *  holes = node_size - sum(bank_sizes)
 	 */
 	memcpy(zhole_size, zone_size, sizeof(zhole_size));
 	for_each_memblock(memory, reg) {
 		unsigned long start = memblock_region_memory_base_pfn(reg);
 		unsigned long end = memblock_region_memory_end_pfn(reg);
 		if (start < max_low) {
 			unsigned long low_end = min(end, max_low);
 			zhole_size[0] -= low_end - start;
 		}
 #ifdef CONFIG_HIGHMEM
 		if (end > max_low) {
 			unsigned long high_start = max(start, max_low);
 			zhole_size[ZONE_HIGHMEM] -= end - high_start;
 		}
 #endif
 	}
 #ifdef CONFIG_ZONE_DMA
 	/*
 	 * Adjust the sizes according to any special requirements for
 	 * this machine type.
 	 */
 	if (arm_dma_zone_size) {
 		arm_adjust_dma_zone(zone_size, zhole_size,
 			arm_dma_zone_size >> PAGE_SHIFT);
 		arm_dma_limit = PHYS_OFFSET + arm_dma_zone_size - 1;
 	} else
 		arm_dma_limit = 0xffffffff;
 #endif
 	free_area_init_node(0, zone_size, min, zhole_size);
 }
 #ifdef CONFIG_HAVE_ARCH_PFN_VALID
 int pfn_valid(unsigned long pfn)
 {
 	return memblock_is_memory(__pfn_to_phys(pfn));
 }
 EXPORT_SYMBOL(pfn_valid);
 #endif
 #ifndef CONFIG_SPARSEMEM
 static void arm_memory_present(void)
 {
 }
 #else
 static void arm_memory_present(void)
 {
 	struct memblock_region *reg;
 	for_each_memblock(memory, reg)
 		memory_present(0, memblock_region_memory_base_pfn(reg),
 			       memblock_region_memory_end_pfn(reg));
 }
 #endif
+static bool arm_memblock_steal_permitted = true;
+phys_addr_t arm_memblock_steal(phys_addr_t size, phys_addr_t align)
+{
+	phys_addr_t phys;
+	BUG_ON(!arm_memblock_steal_permitted);
+	phys = memblock_alloc(size, align);
+	memblock_free(phys, size);
+	memblock_remove(phys, size);
+	return phys;
+}
 void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc)
 {
 	int i;
 	for (i = 0; i < mi->nr_banks; i++)
 		memblock_add(mi->bank[i].start, mi->bank[i].size);
 	/* Register the kernel text, kernel data and initrd with memblock. */
 #ifdef CONFIG_XIP_KERNEL
 	memblock_reserve(__pa(_sdata), _end - _sdata);
 #else
 	memblock_reserve(__pa(_stext), _end - _stext);
 #endif
 #ifdef CONFIG_BLK_DEV_INITRD
 	if (phys_initrd_size &&
 	    !memblock_is_region_memory(phys_initrd_start, phys_initrd_size)) {
 		pr_err("INITRD: 0x%08lx+0x%08lx is not a memory region - disabling initrd\n",
 		       phys_initrd_start, phys_initrd_size);
 		phys_initrd_start = phys_initrd_size = 0;
 	}
 	if (phys_initrd_size &&
 	    memblock_is_region_reserved(phys_initrd_start, phys_initrd_size)) {
 		pr_err("INITRD: 0x%08lx+0x%08lx overlaps in-use memory region - disabling initrd\n",
 		       phys_initrd_start, phys_initrd_size);
 		phys_initrd_start = phys_initrd_size = 0;
 	}
 	if (phys_initrd_size) {
 		memblock_reserve(phys_initrd_start, phys_initrd_size);
 		/* Now convert initrd to virtual addresses */
 		initrd_start = __phys_to_virt(phys_initrd_start);
 		initrd_end = initrd_start + phys_initrd_size;
 	}
 #endif
 	arm_mm_memblock_reserve();
 	arm_dt_memblock_reserve();
 	/* reserve any platform specific memblock areas */
 	if (mdesc->reserve)
 		mdesc->reserve();
+	arm_memblock_steal_permitted = false;
 	memblock_allow_resize();
 	memblock_dump_all();
 }
 void __init bootmem_init(void)
 {
 	unsigned long min, max_low, max_high;
 	max_low = max_high = 0;
 	find_limits(&min, &max_low, &max_high);
 	arm_bootmem_init(min, max_low);
 	/*
 	 * Sparsemem tries to allocate bootmem in memory_present(),
 	 * so must be done after the fixed reservations
 	 */
 	arm_memory_present();
 	/*
 	 * sparse_init() needs the bootmem allocator up and running.
 	 */
 	sparse_init();
 	/*
 	 * Now free the memory - free_area_init_node needs
 	 * the sparse mem_map arrays initialized by sparse_init()
 	 * for memmap_init_zone(), otherwise all PFNs are invalid.
 	 */
 	arm_bootmem_free(min, max_low, max_high);
 	/*
 	 * This doesn't seem to be used by the Linux memory manager any
 	 * more, but is used by ll_rw_block.  If we can get rid of it, we
 	 * also get rid of some of the stuff above as well.
 	 *
 	 * Note: max_low_pfn and max_pfn reflect the number of _pages_ in
 	 * the system, not the maximum PFN.
 	 */
 	max_low_pfn = max_low - PHYS_PFN_OFFSET;
 	max_pfn = max_high - PHYS_PFN_OFFSET;
 }
 static inline int free_area(unsigned long pfn, unsigned long end, char *s)
 {
 	unsigned int pages = 0, size = (end - pfn) << (PAGE_SHIFT - 10);
 	for (; pfn < end; pfn++) {
 		struct page *page = pfn_to_page(pfn);
 		ClearPageReserved(page);
 		init_page_count(page);
 		__free_page(page);
 		pages++;
 	}
 	if (size && s)
 		printk(KERN_INFO "Freeing %s memory: %dK\n", s, size);
 	return pages;
 }
 /*
  * Poison init memory with an undefined instruction (ARM) or a branch to an
  * undefined instruction (Thumb).
  */
 static inline void poison_init_mem(void *s, size_t count)
 {
 	u32 *p = (u32 *)s;
 	for (; count != 0; count -= 4)
 		*p++ = 0xe7fddef0;
 }
 static inline void
 free_memmap(unsigned long start_pfn, unsigned long end_pfn)
 {
 	struct page *start_pg, *end_pg;
 	unsigned long pg, pgend;
 	/*
 	 * Convert start_pfn/end_pfn to a struct page pointer.
 	 */
 	start_pg = pfn_to_page(start_pfn - 1) + 1;
 	end_pg = pfn_to_page(end_pfn - 1) + 1;
 	/*
 	 * Convert to physical addresses, and
 	 * round start upwards and end downwards.
 	 */
 	pg = (unsigned long)PAGE_ALIGN(__pa(start_pg));
 	pgend = (unsigned long)__pa(end_pg) & PAGE_MASK;
 	/*
 	 * If there are free pages between these,
 	 * free the section of the memmap array.
 	 */
 	if (pg < pgend)
 		free_bootmem(pg, pgend - pg);
 }
 /*
  * The mem_map array can get very big.  Free the unused area of the memory map.
  */
 static void __init free_unused_memmap(struct meminfo *mi)
 {
 	unsigned long bank_start, prev_bank_end = 0;
 	unsigned int i;
 	/*
 	 * This relies on each bank being in address order.
 	 * The banks are sorted previously in bootmem_init().
 	 */
 	for_each_bank(i, mi) {
 		struct membank *bank = &mi->bank[i];
 		bank_start = bank_pfn_start(bank);
 #ifdef CONFIG_SPARSEMEM
 		/*
 		 * Take care not to free memmap entries that don't exist
 		 * due to SPARSEMEM sections which aren't present.
 		 */
 		bank_start = min(bank_start,
 				 ALIGN(prev_bank_end, PAGES_PER_SECTION));
 #else
 		/*
 		 * Align down here since the VM subsystem insists that the
 		 * memmap entries are valid from the bank start aligned to
 		 * MAX_ORDER_NR_PAGES.
 		 */
 		bank_start = round_down(bank_start, MAX_ORDER_NR_PAGES);
 #endif
 		/*
 		 * If we had a previous bank, and there is a space
 		 * between the current bank and the previous, free it.
 		 */
 		if (prev_bank_end && prev_bank_end < bank_start)
 			free_memmap(prev_bank_end, bank_start);
 		/*
 		 * Align up here since the VM subsystem insists that the
 		 * memmap entries are valid from the bank end aligned to
 		 * MAX_ORDER_NR_PAGES.
 		 */
 		prev_bank_end = ALIGN(bank_pfn_end(bank), MAX_ORDER_NR_PAGES);
 	}
 #ifdef CONFIG_SPARSEMEM
 	if (!IS_ALIGNED(prev_bank_end, PAGES_PER_SECTION))
 		free_memmap(prev_bank_end,
 			    ALIGN(prev_bank_end, PAGES_PER_SECTION));
 #endif
 }
 static void __init free_highpages(void)
 {
 #ifdef CONFIG_HIGHMEM
 	unsigned long max_low = max_low_pfn + PHYS_PFN_OFFSET;
 	struct memblock_region *mem, *res;
 	/* set highmem page free */
 	for_each_memblock(memory, mem) {
 		unsigned long start = memblock_region_memory_base_pfn(mem);
 		unsigned long end = memblock_region_memory_end_pfn(mem);
 		/* Ignore complete lowmem entries */
 		if (end <= max_low)
 			continue;
 		/* Truncate partial highmem entries */
 		if (start < max_low)
 			start = max_low;
 		/* Find and exclude any reserved regions */
 		for_each_memblock(reserved, res) {
 			unsigned long res_start, res_end;
 			res_start = memblock_region_reserved_base_pfn(res);
 			res_end = memblock_region_reserved_end_pfn(res);
 			if (res_end < start)
 				continue;
 			if (res_start < start)
 				res_start = start;
 			if (res_start > end)
 				res_start = end;
 			if (res_end > end)
 				res_end = end;
 			if (res_start != start)
 				totalhigh_pages += free_area(start, res_start,
 							     NULL);
 			start = res_end;
 			if (start == end)
 				break;
 		}
 		/* And now free anything which remains */
 		if (start < end)
 			totalhigh_pages += free_area(start, end, NULL);
 	}
 	totalram_pages += totalhigh_pages;
 #endif
 }
 /*
  * mem_init() marks the free areas in the mem_map and tells us how much
  * memory is free.  This is done after various parts of the system have
  * claimed their memory after the kernel image.
  */
 void __init mem_init(void)
 {
 	unsigned long reserved_pages, free_pages;
 	struct memblock_region *reg;
 	int i;
 #ifdef CONFIG_HAVE_TCM
 	/* These pointers are filled in on TCM detection */
 	extern u32 dtcm_end;
 	extern u32 itcm_end;
 #endif
 	max_mapnr   = pfn_to_page(max_pfn + PHYS_PFN_OFFSET) - mem_map;
 	/* this will put all unused low memory onto the freelists */
 	free_unused_memmap(&meminfo);
 	totalram_pages += free_all_bootmem();
 #ifdef CONFIG_SA1111
 	/* now that our DMA memory is actually so designated, we can free it */
 	totalram_pages += free_area(PHYS_PFN_OFFSET,
 				    __phys_to_pfn(__pa(swapper_pg_dir)), NULL);
 #endif
 	free_highpages();
 	reserved_pages = free_pages = 0;
 	for_each_bank(i, &meminfo) {
 		struct membank *bank = &meminfo.bank[i];
 		unsigned int pfn1, pfn2;
 		struct page *page, *end;
 		pfn1 = bank_pfn_start(bank);
 		pfn2 = bank_pfn_end(bank);
 		page = pfn_to_page(pfn1);
 		end  = pfn_to_page(pfn2 - 1) + 1;
 		do {
 			if (PageReserved(page))
 				reserved_pages++;
 			else if (!page_count(page))
 				free_pages++;
 			page++;
 		} while (page < end);
 	}
 	/*
 	 * Since our memory may not be contiguous, calculate the
 	 * real number of pages we have in this system
 	 */
 	printk(KERN_INFO "Memory:");
 	num_physpages = 0;
 	for_each_memblock(memory, reg) {
 		unsigned long pages = memblock_region_memory_end_pfn(reg) -
 			memblock_region_memory_base_pfn(reg);
 		num_physpages += pages;
 		printk(" %ldMB", pages >> (20 - PAGE_SHIFT));
 	}
 	printk(" = %luMB total\n", num_physpages >> (20 - PAGE_SHIFT));
 	printk(KERN_NOTICE "Memory: %luk/%luk available, %luk reserved, %luK highmem\n",
 		nr_free_pages() << (PAGE_SHIFT-10),
 		free_pages << (PAGE_SHIFT-10),
 		reserved_pages << (PAGE_SHIFT-10),
 		totalhigh_pages << (PAGE_SHIFT-10));
 #define MLK(b, t) b, t, ((t) - (b)) >> 10
 #define MLM(b, t) b, t, ((t) - (b)) >> 20
 #define MLK_ROUNDUP(b, t) b, t, DIV_ROUND_UP(((t) - (b)), SZ_1K)
 	printk(KERN_NOTICE "Virtual kernel memory layout:\n"
 			"    vector  : 0x%08lx - 0x%08lx   (%4ld kB)\n"
 #ifdef CONFIG_HAVE_TCM
 			"    DTCM    : 0x%08lx - 0x%08lx   (%4ld kB)\n"
 			"    ITCM    : 0x%08lx - 0x%08lx   (%4ld kB)\n"
 #endif
 			"    fixmap  : 0x%08lx - 0x%08lx   (%4ld kB)\n"
 			"    vmalloc : 0x%08lx - 0x%08lx   (%4ld MB)\n"
 			"    lowmem  : 0x%08lx - 0x%08lx   (%4ld MB)\n"
 #ifdef CONFIG_HIGHMEM
 			"    pkmap   : 0x%08lx - 0x%08lx   (%4ld MB)\n"
 #endif
 			"    modules : 0x%08lx - 0x%08lx   (%4ld MB)\n"
 			"      .text : 0x%p" " - 0x%p" "   (%4d kB)\n"
 			"      .init : 0x%p" " - 0x%p" "   (%4d kB)\n"
 			"      .data : 0x%p" " - 0x%p" "   (%4d kB)\n"
 			"       .bss : 0x%p" " - 0x%p" "   (%4d kB)\n",
 			MLK(UL(CONFIG_VECTORS_BASE), UL(CONFIG_VECTORS_BASE) +
 				(PAGE_SIZE)),
 #ifdef CONFIG_HAVE_TCM
 			MLK(DTCM_OFFSET, (unsigned long) dtcm_end),
 			MLK(ITCM_OFFSET, (unsigned long) itcm_end),
 #endif
 			MLK(FIXADDR_START, FIXADDR_TOP),
 			MLM(VMALLOC_START, VMALLOC_END),
 			MLM(PAGE_OFFSET, (unsigned long)high_memory),
 #ifdef CONFIG_HIGHMEM
 			MLM(PKMAP_BASE, (PKMAP_BASE) + (LAST_PKMAP) *
 				(PAGE_SIZE)),
 #endif
 			MLM(MODULES_VADDR, MODULES_END),
 			MLK_ROUNDUP(_text, _etext),
 			MLK_ROUNDUP(__init_begin, __init_end),
 			MLK_ROUNDUP(_sdata, _edata),
 			MLK_ROUNDUP(__bss_start, __bss_stop));
 #undef MLK
 #undef MLM
 #undef MLK_ROUNDUP
 	/*
 	 * Check boundaries twice: Some fundamental inconsistencies can
 	 * be detected at build time already.
 	 */
 #ifdef CONFIG_MMU
 	BUILD_BUG_ON(TASK_SIZE				> MODULES_VADDR);
 	BUG_ON(TASK_SIZE 				> MODULES_VADDR);
 #endif
 #ifdef CONFIG_HIGHMEM
 	BUILD_BUG_ON(PKMAP_BASE + LAST_PKMAP * PAGE_SIZE > PAGE_OFFSET);
 	BUG_ON(PKMAP_BASE + LAST_PKMAP * PAGE_SIZE	> PAGE_OFFSET);
 #endif
 	if (PAGE_SIZE >= 16384 && num_physpages <= 128) {
 		extern int sysctl_overcommit_memory;
 		/*
 		 * On a machine this small we won't get
 		 * anywhere without overcommit, so turn
 		 * it on by default.
 		 */
 		sysctl_overcommit_memory = OVERCOMMIT_ALWAYS;
 	}
 }
 void free_initmem(void)
 {
 #ifdef CONFIG_HAVE_TCM
 	extern char __tcm_start, __tcm_end;
 	poison_init_mem(&__tcm_start, &__tcm_end - &__tcm_start);
 	totalram_pages += free_area(__phys_to_pfn(__pa(&__tcm_start)),
 				    __phys_to_pfn(__pa(&__tcm_end)),
 				    "TCM link");
 #endif
 	poison_init_mem(__init_begin, __init_end - __init_begin);
 	if (!machine_is_integrator() && !machine_is_cintegrator())
 		totalram_pages += free_area(__phys_to_pfn(__pa(__init_begin)),
 					    __phys_to_pfn(__pa(__init_end)),
 					    "init");
 }
 #ifdef CONFIG_BLK_DEV_INITRD
 static int keep_initrd;
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
 	if (!keep_initrd) {
 		poison_init_mem((void *)start, PAGE_ALIGN(end) - start);
 		totalram_pages += free_area(__phys_to_pfn(__pa(start)),
 					    __phys_to_pfn(__pa(end)),
 					    "initrd");
 	}
 }
 static int __init keepinitrd_setup(char *__unused)
 {
 	keep_initrd = 1;
 	return 1;
 }
 __setup("keepinitrd", keepinitrd_setup);
 #endif

arch/arm/plat-omap/devices.c

Diff comments View file @ 716a3dc

 /*
  * linux/arch/arm/plat-omap/devices.c
  *
  * Common platform device setup/initialization for OMAP1 and OMAP2
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  */
 #include <linux/gpio.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/slab.h>
 #include <linux/memblock.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
+#include <asm/memblock.h>
 #include <plat/tc.h>
 #include <plat/board.h>
 #include <plat/mmc.h>
 #include <plat/menelaus.h>
 #include <plat/omap44xx.h>
 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
 	defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
 #define OMAP_MMC_NR_RES		2
 /*
  * Register MMC devices. Called from mach-omap1 and mach-omap2 device init.
  */
 int __init omap_mmc_add(const char *name, int id, unsigned long base,
 				unsigned long size, unsigned int irq,
 				struct omap_mmc_platform_data *data)
 {
 	struct platform_device *pdev;
 	struct resource res[OMAP_MMC_NR_RES];
 	int ret;
 	pdev = platform_device_alloc(name, id);
 	if (!pdev)
 		return -ENOMEM;
 	memset(res, 0, OMAP_MMC_NR_RES * sizeof(struct resource));
 	res[0].start = base;
 	res[0].end = base + size - 1;
 	res[0].flags = IORESOURCE_MEM;
 	res[1].start = res[1].end = irq;
 	res[1].flags = IORESOURCE_IRQ;
 	ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
 	if (ret == 0)
 		ret = platform_device_add_data(pdev, data, sizeof(*data));
 	if (ret)
 		goto fail;
 	ret = platform_device_add(pdev);
 	if (ret)
 		goto fail;
 	/* return device handle to board setup code */
 	data->dev = &pdev->dev;
 	return 0;
 fail:
 	platform_device_put(pdev);
 	return ret;
 }
 #endif
 /*-------------------------------------------------------------------------*/
 #if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE)
 #ifdef CONFIG_ARCH_OMAP2
 #define	OMAP_RNG_BASE		0x480A0000
 #else
 #define	OMAP_RNG_BASE		0xfffe5000
 #endif
 static struct resource rng_resources[] = {
 	{
 		.start		= OMAP_RNG_BASE,
 		.end		= OMAP_RNG_BASE + 0x4f,
 		.flags		= IORESOURCE_MEM,
 	},
 };
 static struct platform_device omap_rng_device = {
 	.name		= "omap_rng",
 	.id		= -1,
 	.num_resources	= ARRAY_SIZE(rng_resources),
 	.resource	= rng_resources,
 };
 static void omap_init_rng(void)
 {
 	(void) platform_device_register(&omap_rng_device);
 }
 #else
 static inline void omap_init_rng(void) {}
 #endif
 /*-------------------------------------------------------------------------*/
 /* Numbering for the SPI-capable controllers when used for SPI:
  * spi		= 1
  * uwire	= 2
  * mmc1..2	= 3..4
  * mcbsp1..3	= 5..7
  */
 #if defined(CONFIG_SPI_OMAP_UWIRE) || defined(CONFIG_SPI_OMAP_UWIRE_MODULE)
 #define	OMAP_UWIRE_BASE		0xfffb3000
 static struct resource uwire_resources[] = {
 	{
 		.start		= OMAP_UWIRE_BASE,
 		.end		= OMAP_UWIRE_BASE + 0x20,
 		.flags		= IORESOURCE_MEM,
 	},
 };
 static struct platform_device omap_uwire_device = {
 	.name	   = "omap_uwire",
 	.id	     = -1,
 	.num_resources	= ARRAY_SIZE(uwire_resources),
 	.resource	= uwire_resources,
 };
 static void omap_init_uwire(void)
 {
 	/* FIXME define and use a boot tag; not all boards will be hooking
 	 * up devices to the microwire controller, and multi-board configs
 	 * mean that CONFIG_SPI_OMAP_UWIRE may be configured anyway...
 	 */
 	/* board-specific code must configure chipselects (only a few
 	 * are normally used) and SCLK/SDI/SDO (each has two choices).
 	 */
 	(void) platform_device_register(&omap_uwire_device);
 }
 #else
 static inline void omap_init_uwire(void) {}
 #endif
 #if defined(CONFIG_TIDSPBRIDGE) || defined(CONFIG_TIDSPBRIDGE_MODULE)
 static phys_addr_t omap_dsp_phys_mempool_base;
 void __init omap_dsp_reserve_sdram_memblock(void)
 {
 	phys_addr_t size = CONFIG_TIDSPBRIDGE_MEMPOOL_SIZE;
 	phys_addr_t paddr;
 	if (!size)
 		return;
-	paddr = memblock_alloc(size, SZ_1M);
+	paddr = arm_memblock_steal(size, SZ_1M);
 	if (!paddr) {
 		pr_err("%s: failed to reserve %x bytes\n",
 				__func__, size);
 		return;
 	}
-	memblock_free(paddr, size);
-	memblock_remove(paddr, size);
 	omap_dsp_phys_mempool_base = paddr;
 }
 phys_addr_t omap_dsp_get_mempool_base(void)
 {
 	return omap_dsp_phys_mempool_base;
 }
 EXPORT_SYMBOL(omap_dsp_get_mempool_base);
 #endif
 /*
  * This gets called after board-specific INIT_MACHINE, and initializes most
  * on-chip peripherals accessible on this board (except for few like USB):
  *
  *  (a) Does any "standard config" pin muxing needed.  Board-specific
  *	code will have muxed GPIO pins and done "nonstandard" setup;
  *	that code could live in the boot loader.
  *  (b) Populating board-specific platform_data with the data drivers
  *	rely on to handle wiring variations.
  *  (c) Creating platform devices as meaningful on this board and
  *	with this kernel configuration.
  *
  * Claiming GPIOs, and setting their direction and initial values, is the
  * responsibility of the device drivers.  So is responding to probe().
  *
  * Board-specific knowledge like creating devices or pin setup is to be
  * kept out of drivers as much as possible.  In particular, pin setup
  * may be handled by the boot loader, and drivers should expect it will
  * normally have been done by the time they're probed.
  */
 static int __init omap_init_devices(void)
 {
 	/* please keep these calls, and their implementations above,
 	 * in alphabetical order so they're easier to sort through.
 	 */
 	omap_init_rng();
 	omap_init_uwire();
 	return 0;
 }
 arch_initcall(omap_init_devices);