Doug / smarc-fsl-linux-kernel

1

/*

1

/*

2

3

*

3

*

4

* Permission is hereby granted, free of charge, to any person obtaining a

4

* Permission is hereby granted, free of charge, to any person obtaining a

5

* copy of this software and associated documentation files (the "Software"),

5

* copy of this software and associated documentation files (the "Software"),

6

* to deal in the Software without restriction, including without limitation

6

* to deal in the Software without restriction, including without limitation

7

* the rights to use, copy, modify, merge, publish, distribute, sublicense,

7

* the rights to use, copy, modify, merge, publish, distribute, sublicense,

8

* and/or sell copies of the Software, and to permit persons to whom the

8

* and/or sell copies of the Software, and to permit persons to whom the

9

* Software is furnished to do so, subject to the following conditions:

9

* Software is furnished to do so, subject to the following conditions:

10

*

10

*

11

* The above copyright notice and this permission notice (including the next

11

* The above copyright notice and this permission notice (including the next

12

* paragraph) shall be included in all copies or substantial portions of the

12

* paragraph) shall be included in all copies or substantial portions of the

13

* Software.

13

* Software.

14

*

14

*

15

* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

15

* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

16

* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

16

* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

17

* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

17

* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

18

* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

18

* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

19

* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

19

* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

20

* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

20

* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

21

* DEALINGS IN THE SOFTWARE.

21

* DEALINGS IN THE SOFTWARE.

22

*

22

*

23

* Authors:

23

* Authors:

24

* Eric Anholt <eric@anholt.net>

24

* Eric Anholt <eric@anholt.net>

25

*/

25

*/

26

27

#include <linux/cpufreq.h>

27

#include <linux/cpufreq.h>

28

#include <linux/module.h>

28

#include <linux/module.h>

29

#include <linux/input.h>

29

#include <linux/input.h>

30

#include <linux/i2c.h>

30

#include <linux/i2c.h>

31

#include <linux/kernel.h>

31

#include <linux/kernel.h>

32

#include <linux/slab.h>

32

#include <linux/slab.h>

33

#include <linux/vgaarb.h>

33

#include <linux/vgaarb.h>

34

#include <drm/drm_edid.h>

34

#include <drm/drm_edid.h>

35

#include "drmP.h"

35

#include "drmP.h"

36

#include "intel_drv.h"

36

#include "intel_drv.h"

37

#include "i915_drm.h"

37

#include "i915_drm.h"

38

#include "i915_drv.h"

38

#include "i915_drv.h"

39

#include "i915_trace.h"

39

#include "i915_trace.h"

40

#include "drm_dp_helper.h"

40

#include "drm_dp_helper.h"

41

#include "drm_crtc_helper.h"

41

#include "drm_crtc_helper.h"

42

#include <linux/dma_remapping.h>

42

#include <linux/dma_remapping.h>

43

44

#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))

44

#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))

45

46

bool intel_pipe_has_type(struct drm_crtc *crtc, int type);

46

bool intel_pipe_has_type(struct drm_crtc *crtc, int type);

47

static void intel_update_watermarks(struct drm_device *dev);

47

static void intel_update_watermarks(struct drm_device *dev);

48

static void intel_increase_pllclock(struct drm_crtc *crtc);

48

static void intel_increase_pllclock(struct drm_crtc *crtc);

49

static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);

49

static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);

50

51

typedef struct {

51

typedef struct {

52

/* given values */

52

/* given values */

53

int n;

53

int n;

54

int m1, m2;

54

int m1, m2;

55

int p1, p2;

55

int p1, p2;

56

/* derived values */

56

/* derived values */

57

int dot;

57

int dot;

58

int vco;

58

int vco;

59

int m;

59

int m;

60

int p;

60

int p;

61

} intel_clock_t;

61

} intel_clock_t;

62

63

typedef struct {

63

typedef struct {

64

int min, max;

64

int min, max;

65

} intel_range_t;

65

} intel_range_t;

66

67

typedef struct {

67

typedef struct {

68

int dot_limit;

68

int dot_limit;

69

int p2_slow, p2_fast;

69

int p2_slow, p2_fast;

70

} intel_p2_t;

70

} intel_p2_t;

71

72

#define INTEL_P2_NUM 2

72

#define INTEL_P2_NUM 2

73

typedef struct intel_limit intel_limit_t;

73

typedef struct intel_limit intel_limit_t;

74

struct intel_limit {

74

struct intel_limit {

75

intel_range_t dot, vco, n, m, m1, m2, p, p1;

75

intel_range_t dot, vco, n, m, m1, m2, p, p1;

76

intel_p2_t p2;

76

intel_p2_t p2;

77

bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,

77

bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,

78

int, int, intel_clock_t *);

78

int, int, intel_clock_t *);

79

};

79

};

80

81

/* FDI */

81

/* FDI */

82

#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */

82

#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */

83

84

static bool

84

static bool

85

intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,

85

intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,

86

int target, int refclk, intel_clock_t *best_clock);

86

int target, int refclk, intel_clock_t *best_clock);

87

static bool

87

static bool

88

intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,

88

intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,

89

int target, int refclk, intel_clock_t *best_clock);

89

int target, int refclk, intel_clock_t *best_clock);

90

91

static bool

91

static bool

92

intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,

92

intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,

93

int target, int refclk, intel_clock_t *best_clock);

93

int target, int refclk, intel_clock_t *best_clock);

94

static bool

94

static bool

95

intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,

95

intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,

96

int target, int refclk, intel_clock_t *best_clock);

96

int target, int refclk, intel_clock_t *best_clock);

97

98

static inline u32 /* units of 100MHz */

98

static inline u32 /* units of 100MHz */

99

intel_fdi_link_freq(struct drm_device *dev)

99

intel_fdi_link_freq(struct drm_device *dev)

100

{

100

{

101

if (IS_GEN5(dev)) {

101

if (IS_GEN5(dev)) {

102

struct drm_i915_private *dev_priv = dev->dev_private;

102

struct drm_i915_private *dev_priv = dev->dev_private;

103

return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;

103

return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;

104

} else

104

} else

105

return 27;

105

return 27;

106

}

106

}

107

108

static const intel_limit_t intel_limits_i8xx_dvo = {

108

static const intel_limit_t intel_limits_i8xx_dvo = {

109

.dot = { .min = 25000, .max = 350000 },

109

.dot = { .min = 25000, .max = 350000 },

110

.vco = { .min = 930000, .max = 1400000 },

110

.vco = { .min = 930000, .max = 1400000 },

111

.n = { .min = 3, .max = 16 },

111

.n = { .min = 3, .max = 16 },

112

.m = { .min = 96, .max = 140 },

112

.m = { .min = 96, .max = 140 },

113

.m1 = { .min = 18, .max = 26 },

113

.m1 = { .min = 18, .max = 26 },

114

.m2 = { .min = 6, .max = 16 },

114

.m2 = { .min = 6, .max = 16 },

115

.p = { .min = 4, .max = 128 },

115

.p = { .min = 4, .max = 128 },

116

.p1 = { .min = 2, .max = 33 },

116

.p1 = { .min = 2, .max = 33 },

117

.p2 = { .dot_limit = 165000,

117

.p2 = { .dot_limit = 165000,

118

.p2_slow = 4, .p2_fast = 2 },

118

.p2_slow = 4, .p2_fast = 2 },

119

.find_pll = intel_find_best_PLL,

119

.find_pll = intel_find_best_PLL,

120

};

120

};

121

122

static const intel_limit_t intel_limits_i8xx_lvds = {

122

static const intel_limit_t intel_limits_i8xx_lvds = {

123

.dot = { .min = 25000, .max = 350000 },

123

.dot = { .min = 25000, .max = 350000 },

124

.vco = { .min = 930000, .max = 1400000 },

124

.vco = { .min = 930000, .max = 1400000 },

125

.n = { .min = 3, .max = 16 },

125

.n = { .min = 3, .max = 16 },

126

.m = { .min = 96, .max = 140 },

126

.m = { .min = 96, .max = 140 },

127

.m1 = { .min = 18, .max = 26 },

127

.m1 = { .min = 18, .max = 26 },

128

.m2 = { .min = 6, .max = 16 },

128

.m2 = { .min = 6, .max = 16 },

129

.p = { .min = 4, .max = 128 },

129

.p = { .min = 4, .max = 128 },

130

.p1 = { .min = 1, .max = 6 },

130

.p1 = { .min = 1, .max = 6 },

131

.p2 = { .dot_limit = 165000,

131

.p2 = { .dot_limit = 165000,

132

.p2_slow = 14, .p2_fast = 7 },

132

.p2_slow = 14, .p2_fast = 7 },

133

.find_pll = intel_find_best_PLL,

133

.find_pll = intel_find_best_PLL,

134

};

134

};

135

136

static const intel_limit_t intel_limits_i9xx_sdvo = {

136

static const intel_limit_t intel_limits_i9xx_sdvo = {

137

.dot = { .min = 20000, .max = 400000 },

137

.dot = { .min = 20000, .max = 400000 },

138

.vco = { .min = 1400000, .max = 2800000 },

138

.vco = { .min = 1400000, .max = 2800000 },

139

.n = { .min = 1, .max = 6 },

139

.n = { .min = 1, .max = 6 },

140

.m = { .min = 70, .max = 120 },

140

.m = { .min = 70, .max = 120 },

141

.m1 = { .min = 10, .max = 22 },

141

.m1 = { .min = 10, .max = 22 },

142

.m2 = { .min = 5, .max = 9 },

142

.m2 = { .min = 5, .max = 9 },

143

.p = { .min = 5, .max = 80 },

143

.p = { .min = 5, .max = 80 },

144

.p1 = { .min = 1, .max = 8 },

144

.p1 = { .min = 1, .max = 8 },

145

.p2 = { .dot_limit = 200000,

145

.p2 = { .dot_limit = 200000,

146

.p2_slow = 10, .p2_fast = 5 },

146

.p2_slow = 10, .p2_fast = 5 },

147

.find_pll = intel_find_best_PLL,

147

.find_pll = intel_find_best_PLL,

148

};

148

};

149

150

static const intel_limit_t intel_limits_i9xx_lvds = {

150

static const intel_limit_t intel_limits_i9xx_lvds = {

151

.dot = { .min = 20000, .max = 400000 },

151

.dot = { .min = 20000, .max = 400000 },

152

.vco = { .min = 1400000, .max = 2800000 },

152

.vco = { .min = 1400000, .max = 2800000 },

153

.n = { .min = 1, .max = 6 },

153

.n = { .min = 1, .max = 6 },

154

.m = { .min = 70, .max = 120 },

154

.m = { .min = 70, .max = 120 },

155

.m1 = { .min = 10, .max = 22 },

155

.m1 = { .min = 10, .max = 22 },

156

.m2 = { .min = 5, .max = 9 },

156

.m2 = { .min = 5, .max = 9 },

157

.p = { .min = 7, .max = 98 },

157

.p = { .min = 7, .max = 98 },

158

.p1 = { .min = 1, .max = 8 },

158

.p1 = { .min = 1, .max = 8 },

159

.p2 = { .dot_limit = 112000,

159

.p2 = { .dot_limit = 112000,

160

.p2_slow = 14, .p2_fast = 7 },

160

.p2_slow = 14, .p2_fast = 7 },

161

.find_pll = intel_find_best_PLL,

161

.find_pll = intel_find_best_PLL,

162

};

162

};

163

164

165

static const intel_limit_t intel_limits_g4x_sdvo = {

165

static const intel_limit_t intel_limits_g4x_sdvo = {

166

.dot = { .min = 25000, .max = 270000 },

166

.dot = { .min = 25000, .max = 270000 },

167

.vco = { .min = 1750000, .max = 3500000},

167

.vco = { .min = 1750000, .max = 3500000},

168

.n = { .min = 1, .max = 4 },

168

.n = { .min = 1, .max = 4 },

169

.m = { .min = 104, .max = 138 },

169

.m = { .min = 104, .max = 138 },

170

.m1 = { .min = 17, .max = 23 },

170

.m1 = { .min = 17, .max = 23 },

171

.m2 = { .min = 5, .max = 11 },

171

.m2 = { .min = 5, .max = 11 },

172

.p = { .min = 10, .max = 30 },

172

.p = { .min = 10, .max = 30 },

173

.p1 = { .min = 1, .max = 3},

173

.p1 = { .min = 1, .max = 3},

174

.p2 = { .dot_limit = 270000,

174

.p2 = { .dot_limit = 270000,

175

.p2_slow = 10,

175

.p2_slow = 10,

176

.p2_fast = 10

176

.p2_fast = 10

177

},

177

},

178

.find_pll = intel_g4x_find_best_PLL,

178

.find_pll = intel_g4x_find_best_PLL,

179

};

179

};

180

181

static const intel_limit_t intel_limits_g4x_hdmi = {

181

static const intel_limit_t intel_limits_g4x_hdmi = {

182

.dot = { .min = 22000, .max = 400000 },

182

.dot = { .min = 22000, .max = 400000 },

183

.vco = { .min = 1750000, .max = 3500000},

183

.vco = { .min = 1750000, .max = 3500000},

184

.n = { .min = 1, .max = 4 },

184

.n = { .min = 1, .max = 4 },

185

.m = { .min = 104, .max = 138 },

185

.m = { .min = 104, .max = 138 },

186

.m1 = { .min = 16, .max = 23 },

186

.m1 = { .min = 16, .max = 23 },

187

.m2 = { .min = 5, .max = 11 },

187

.m2 = { .min = 5, .max = 11 },

188

.p = { .min = 5, .max = 80 },

188

.p = { .min = 5, .max = 80 },

189

.p1 = { .min = 1, .max = 8},

189

.p1 = { .min = 1, .max = 8},

190

.p2 = { .dot_limit = 165000,

190

.p2 = { .dot_limit = 165000,

191

.p2_slow = 10, .p2_fast = 5 },

191

.p2_slow = 10, .p2_fast = 5 },

192

.find_pll = intel_g4x_find_best_PLL,

192

.find_pll = intel_g4x_find_best_PLL,

193

};

193

};

194

195

static const intel_limit_t intel_limits_g4x_single_channel_lvds = {

195

static const intel_limit_t intel_limits_g4x_single_channel_lvds = {

196

.dot = { .min = 20000, .max = 115000 },

196

.dot = { .min = 20000, .max = 115000 },

197

.vco = { .min = 1750000, .max = 3500000 },

197

.vco = { .min = 1750000, .max = 3500000 },

198

.n = { .min = 1, .max = 3 },

198

.n = { .min = 1, .max = 3 },

199

.m = { .min = 104, .max = 138 },

199

.m = { .min = 104, .max = 138 },

200

.m1 = { .min = 17, .max = 23 },

200

.m1 = { .min = 17, .max = 23 },

201

.m2 = { .min = 5, .max = 11 },

201

.m2 = { .min = 5, .max = 11 },

202

.p = { .min = 28, .max = 112 },

202

.p = { .min = 28, .max = 112 },

203

.p1 = { .min = 2, .max = 8 },

203

.p1 = { .min = 2, .max = 8 },

204

.p2 = { .dot_limit = 0,

204

.p2 = { .dot_limit = 0,

205

.p2_slow = 14, .p2_fast = 14

205

.p2_slow = 14, .p2_fast = 14

206

},

206

},

207

.find_pll = intel_g4x_find_best_PLL,

207

.find_pll = intel_g4x_find_best_PLL,

208

};

208

};

209

210

static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {

210

static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {

211

.dot = { .min = 80000, .max = 224000 },

211

.dot = { .min = 80000, .max = 224000 },

212

.vco = { .min = 1750000, .max = 3500000 },

212

.vco = { .min = 1750000, .max = 3500000 },

213

.n = { .min = 1, .max = 3 },

213

.n = { .min = 1, .max = 3 },

214

.m = { .min = 104, .max = 138 },

214

.m = { .min = 104, .max = 138 },

215

.m1 = { .min = 17, .max = 23 },

215

.m1 = { .min = 17, .max = 23 },

216

.m2 = { .min = 5, .max = 11 },

216

.m2 = { .min = 5, .max = 11 },

217

.p = { .min = 14, .max = 42 },

217

.p = { .min = 14, .max = 42 },

218

.p1 = { .min = 2, .max = 6 },

218

.p1 = { .min = 2, .max = 6 },

219

.p2 = { .dot_limit = 0,

219

.p2 = { .dot_limit = 0,

220

.p2_slow = 7, .p2_fast = 7

220

.p2_slow = 7, .p2_fast = 7

221

},

221

},

222

.find_pll = intel_g4x_find_best_PLL,

222

.find_pll = intel_g4x_find_best_PLL,

223

};

223

};

224

225

static const intel_limit_t intel_limits_g4x_display_port = {

225

static const intel_limit_t intel_limits_g4x_display_port = {

226

.dot = { .min = 161670, .max = 227000 },

226

.dot = { .min = 161670, .max = 227000 },

227

.vco = { .min = 1750000, .max = 3500000},

227

.vco = { .min = 1750000, .max = 3500000},

228

.n = { .min = 1, .max = 2 },

228

.n = { .min = 1, .max = 2 },

229

.m = { .min = 97, .max = 108 },

229

.m = { .min = 97, .max = 108 },

230

.m1 = { .min = 0x10, .max = 0x12 },

230

.m1 = { .min = 0x10, .max = 0x12 },

231

.m2 = { .min = 0x05, .max = 0x06 },

231

.m2 = { .min = 0x05, .max = 0x06 },

232

.p = { .min = 10, .max = 20 },

232

.p = { .min = 10, .max = 20 },

233

.p1 = { .min = 1, .max = 2},

233

.p1 = { .min = 1, .max = 2},

234

.p2 = { .dot_limit = 0,

234

.p2 = { .dot_limit = 0,

235

.p2_slow = 10, .p2_fast = 10 },

235

.p2_slow = 10, .p2_fast = 10 },

236

.find_pll = intel_find_pll_g4x_dp,

236

.find_pll = intel_find_pll_g4x_dp,

237

};

237

};

238

239

static const intel_limit_t intel_limits_pineview_sdvo = {

239

static const intel_limit_t intel_limits_pineview_sdvo = {

240

.dot = { .min = 20000, .max = 400000},

240

.dot = { .min = 20000, .max = 400000},

241

.vco = { .min = 1700000, .max = 3500000 },

241

.vco = { .min = 1700000, .max = 3500000 },

242

/* Pineview's Ncounter is a ring counter */

242

/* Pineview's Ncounter is a ring counter */

243

.n = { .min = 3, .max = 6 },

243

.n = { .min = 3, .max = 6 },

244

.m = { .min = 2, .max = 256 },

244

.m = { .min = 2, .max = 256 },

245

/* Pineview only has one combined m divider, which we treat as m2. */

245

/* Pineview only has one combined m divider, which we treat as m2. */

246

.m1 = { .min = 0, .max = 0 },

246

.m1 = { .min = 0, .max = 0 },

247

.m2 = { .min = 0, .max = 254 },

247

.m2 = { .min = 0, .max = 254 },

248

.p = { .min = 5, .max = 80 },

248

.p = { .min = 5, .max = 80 },

249

.p1 = { .min = 1, .max = 8 },

249

.p1 = { .min = 1, .max = 8 },

250

.p2 = { .dot_limit = 200000,

250

.p2 = { .dot_limit = 200000,

251

.p2_slow = 10, .p2_fast = 5 },

251

.p2_slow = 10, .p2_fast = 5 },

252

.find_pll = intel_find_best_PLL,

252

.find_pll = intel_find_best_PLL,

253

};

253

};

254

255

static const intel_limit_t intel_limits_pineview_lvds = {

255

static const intel_limit_t intel_limits_pineview_lvds = {

256

.dot = { .min = 20000, .max = 400000 },

256

.dot = { .min = 20000, .max = 400000 },

257

.vco = { .min = 1700000, .max = 3500000 },

257

.vco = { .min = 1700000, .max = 3500000 },

258

.n = { .min = 3, .max = 6 },

258

.n = { .min = 3, .max = 6 },

259

.m = { .min = 2, .max = 256 },

259

.m = { .min = 2, .max = 256 },

260

.m1 = { .min = 0, .max = 0 },

260

.m1 = { .min = 0, .max = 0 },

261

.m2 = { .min = 0, .max = 254 },

261

.m2 = { .min = 0, .max = 254 },

262

.p = { .min = 7, .max = 112 },

262

.p = { .min = 7, .max = 112 },

263

.p1 = { .min = 1, .max = 8 },

263

.p1 = { .min = 1, .max = 8 },

264

.p2 = { .dot_limit = 112000,

264

.p2 = { .dot_limit = 112000,

265

.p2_slow = 14, .p2_fast = 14 },

265

.p2_slow = 14, .p2_fast = 14 },

266

.find_pll = intel_find_best_PLL,

266

.find_pll = intel_find_best_PLL,

267

};

267

};

268

269

/* Ironlake / Sandybridge

269

/* Ironlake / Sandybridge

270

*

270

*

271

* We calculate clock using (register_value + 2) for N/M1/M2, so here

271

* We calculate clock using (register_value + 2) for N/M1/M2, so here

272

* the range value for them is (actual_value - 2).

272

* the range value for them is (actual_value - 2).

273

*/

273

*/

274

static const intel_limit_t intel_limits_ironlake_dac = {

274

static const intel_limit_t intel_limits_ironlake_dac = {

275

.dot = { .min = 25000, .max = 350000 },

275

.dot = { .min = 25000, .max = 350000 },

276

.vco = { .min = 1760000, .max = 3510000 },

276

.vco = { .min = 1760000, .max = 3510000 },

277

.n = { .min = 1, .max = 5 },

277

.n = { .min = 1, .max = 5 },

278

.m = { .min = 79, .max = 127 },

278

.m = { .min = 79, .max = 127 },

279

.m1 = { .min = 12, .max = 22 },

279

.m1 = { .min = 12, .max = 22 },

280

.m2 = { .min = 5, .max = 9 },

280

.m2 = { .min = 5, .max = 9 },

281

.p = { .min = 5, .max = 80 },

281

.p = { .min = 5, .max = 80 },

282

.p1 = { .min = 1, .max = 8 },

282

.p1 = { .min = 1, .max = 8 },

283

.p2 = { .dot_limit = 225000,

283

.p2 = { .dot_limit = 225000,

284

.p2_slow = 10, .p2_fast = 5 },

284

.p2_slow = 10, .p2_fast = 5 },

285

.find_pll = intel_g4x_find_best_PLL,

285

.find_pll = intel_g4x_find_best_PLL,

286

};

286

};

287

288

static const intel_limit_t intel_limits_ironlake_single_lvds = {

288

static const intel_limit_t intel_limits_ironlake_single_lvds = {

289

.dot = { .min = 25000, .max = 350000 },

289

.dot = { .min = 25000, .max = 350000 },

290

.vco = { .min = 1760000, .max = 3510000 },

290

.vco = { .min = 1760000, .max = 3510000 },

291

.n = { .min = 1, .max = 3 },

291

.n = { .min = 1, .max = 3 },

292

.m = { .min = 79, .max = 118 },

292

.m = { .min = 79, .max = 118 },

293

.m1 = { .min = 12, .max = 22 },

293

.m1 = { .min = 12, .max = 22 },

294

.m2 = { .min = 5, .max = 9 },

294

.m2 = { .min = 5, .max = 9 },

295

.p = { .min = 28, .max = 112 },

295

.p = { .min = 28, .max = 112 },

296

.p1 = { .min = 2, .max = 8 },

296

.p1 = { .min = 2, .max = 8 },

297

.p2 = { .dot_limit = 225000,

297

.p2 = { .dot_limit = 225000,

298

.p2_slow = 14, .p2_fast = 14 },

298

.p2_slow = 14, .p2_fast = 14 },

299

.find_pll = intel_g4x_find_best_PLL,

299

.find_pll = intel_g4x_find_best_PLL,

300

};

300

};

301

302

static const intel_limit_t intel_limits_ironlake_dual_lvds = {

302

static const intel_limit_t intel_limits_ironlake_dual_lvds = {

303

.dot = { .min = 25000, .max = 350000 },

303

.dot = { .min = 25000, .max = 350000 },

304

.vco = { .min = 1760000, .max = 3510000 },

304

.vco = { .min = 1760000, .max = 3510000 },

305

.n = { .min = 1, .max = 3 },

305

.n = { .min = 1, .max = 3 },

306

.m = { .min = 79, .max = 127 },

306

.m = { .min = 79, .max = 127 },

307

.m1 = { .min = 12, .max = 22 },

307

.m1 = { .min = 12, .max = 22 },

308

.m2 = { .min = 5, .max = 9 },

308

.m2 = { .min = 5, .max = 9 },

309

.p = { .min = 14, .max = 56 },

309

.p = { .min = 14, .max = 56 },

310

.p1 = { .min = 2, .max = 8 },

310

.p1 = { .min = 2, .max = 8 },

311

.p2 = { .dot_limit = 225000,

311

.p2 = { .dot_limit = 225000,

312

.p2_slow = 7, .p2_fast = 7 },

312

.p2_slow = 7, .p2_fast = 7 },

313

.find_pll = intel_g4x_find_best_PLL,

313

.find_pll = intel_g4x_find_best_PLL,

314

};

314

};

315

316

/* LVDS 100mhz refclk limits. */

316

/* LVDS 100mhz refclk limits. */

317

static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {

317

static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {

318

.dot = { .min = 25000, .max = 350000 },

318

.dot = { .min = 25000, .max = 350000 },

319

.vco = { .min = 1760000, .max = 3510000 },

319

.vco = { .min = 1760000, .max = 3510000 },

320

.n = { .min = 1, .max = 2 },

320

.n = { .min = 1, .max = 2 },

321

.m = { .min = 79, .max = 126 },

321

.m = { .min = 79, .max = 126 },

322

.m1 = { .min = 12, .max = 22 },

322

.m1 = { .min = 12, .max = 22 },

323

.m2 = { .min = 5, .max = 9 },

323

.m2 = { .min = 5, .max = 9 },

324

.p = { .min = 28, .max = 112 },

324

.p = { .min = 28, .max = 112 },

325

.p1 = { .min = 2, .max = 8 },

325

.p1 = { .min = 2, .max = 8 },

326

.p2 = { .dot_limit = 225000,

326

.p2 = { .dot_limit = 225000,

327

.p2_slow = 14, .p2_fast = 14 },

327

.p2_slow = 14, .p2_fast = 14 },

328

.find_pll = intel_g4x_find_best_PLL,

328

.find_pll = intel_g4x_find_best_PLL,

329

};

329

};

330

331

static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {

331

static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {

332

.dot = { .min = 25000, .max = 350000 },

332

.dot = { .min = 25000, .max = 350000 },

333

.vco = { .min = 1760000, .max = 3510000 },

333

.vco = { .min = 1760000, .max = 3510000 },

334

.n = { .min = 1, .max = 3 },

334

.n = { .min = 1, .max = 3 },

335

.m = { .min = 79, .max = 126 },

335

.m = { .min = 79, .max = 126 },

336

.m1 = { .min = 12, .max = 22 },

336

.m1 = { .min = 12, .max = 22 },

337

.m2 = { .min = 5, .max = 9 },

337

.m2 = { .min = 5, .max = 9 },

338

.p = { .min = 14, .max = 42 },

338

.p = { .min = 14, .max = 42 },

339

.p1 = { .min = 2, .max = 6 },

339

.p1 = { .min = 2, .max = 6 },

340

.p2 = { .dot_limit = 225000,

340

.p2 = { .dot_limit = 225000,

341

.p2_slow = 7, .p2_fast = 7 },

341

.p2_slow = 7, .p2_fast = 7 },

342

.find_pll = intel_g4x_find_best_PLL,

342

.find_pll = intel_g4x_find_best_PLL,

343

};

343

};

344

345

static const intel_limit_t intel_limits_ironlake_display_port = {

345

static const intel_limit_t intel_limits_ironlake_display_port = {

346

.dot = { .min = 25000, .max = 350000 },

346

.dot = { .min = 25000, .max = 350000 },

347

.vco = { .min = 1760000, .max = 3510000},

347

.vco = { .min = 1760000, .max = 3510000},

348

.n = { .min = 1, .max = 2 },

348

.n = { .min = 1, .max = 2 },

349

.m = { .min = 81, .max = 90 },

349

.m = { .min = 81, .max = 90 },

350

.m1 = { .min = 12, .max = 22 },

350

.m1 = { .min = 12, .max = 22 },

351

.m2 = { .min = 5, .max = 9 },

351

.m2 = { .min = 5, .max = 9 },

352

.p = { .min = 10, .max = 20 },

352

.p = { .min = 10, .max = 20 },

353

.p1 = { .min = 1, .max = 2},

353

.p1 = { .min = 1, .max = 2},

354

.p2 = { .dot_limit = 0,

354

.p2 = { .dot_limit = 0,

355

.p2_slow = 10, .p2_fast = 10 },

355

.p2_slow = 10, .p2_fast = 10 },

356

.find_pll = intel_find_pll_ironlake_dp,

356

.find_pll = intel_find_pll_ironlake_dp,

357

};

357

};

358

359

static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,

359

static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,

360

int refclk)

360

int refclk)

361

{

361

{

362

struct drm_device *dev = crtc->dev;

362

struct drm_device *dev = crtc->dev;

363

struct drm_i915_private *dev_priv = dev->dev_private;

363

struct drm_i915_private *dev_priv = dev->dev_private;

364

const intel_limit_t *limit;

364

const intel_limit_t *limit;

365

366

if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {

366

if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {

367

if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==

367

if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==

368

LVDS_CLKB_POWER_UP) {

368

LVDS_CLKB_POWER_UP) {

369

/* LVDS dual channel */

369

/* LVDS dual channel */

370

if (refclk == 100000)

370

if (refclk == 100000)

371

limit = &intel_limits_ironlake_dual_lvds_100m;

371

limit = &intel_limits_ironlake_dual_lvds_100m;

372

else

372

else

373

limit = &intel_limits_ironlake_dual_lvds;

373

limit = &intel_limits_ironlake_dual_lvds;

374

} else {

374

} else {

375

if (refclk == 100000)

375

if (refclk == 100000)

376

limit = &intel_limits_ironlake_single_lvds_100m;

376

limit = &intel_limits_ironlake_single_lvds_100m;

377

else

377

else

378

limit = &intel_limits_ironlake_single_lvds;

378

limit = &intel_limits_ironlake_single_lvds;

379

}

379

}

380

} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||

380

} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||

381

HAS_eDP)

381

HAS_eDP)

382

limit = &intel_limits_ironlake_display_port;

382

limit = &intel_limits_ironlake_display_port;

383

else

383

else

384

limit = &intel_limits_ironlake_dac;

384

limit = &intel_limits_ironlake_dac;

385

386

return limit;

386

return limit;

387

}

387

}

388

389

static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)

389

static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)

390

{

390

{

391

struct drm_device *dev = crtc->dev;

391

struct drm_device *dev = crtc->dev;

392

struct drm_i915_private *dev_priv = dev->dev_private;

392

struct drm_i915_private *dev_priv = dev->dev_private;

393

const intel_limit_t *limit;

393

const intel_limit_t *limit;

394

395

if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {

395

if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {

396

if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==

396

if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==

397

LVDS_CLKB_POWER_UP)

397

LVDS_CLKB_POWER_UP)

398

/* LVDS with dual channel */

398

/* LVDS with dual channel */

399

limit = &intel_limits_g4x_dual_channel_lvds;

399

limit = &intel_limits_g4x_dual_channel_lvds;

400

else

400

else

401

/* LVDS with dual channel */

401

/* LVDS with dual channel */

402

limit = &intel_limits_g4x_single_channel_lvds;

402

limit = &intel_limits_g4x_single_channel_lvds;

403

} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||

403

} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||

404

intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {

404

intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {

405

limit = &intel_limits_g4x_hdmi;

405

limit = &intel_limits_g4x_hdmi;

406

} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {

406

} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {

407

limit = &intel_limits_g4x_sdvo;

407

limit = &intel_limits_g4x_sdvo;

408

} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {

408

} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {

409

limit = &intel_limits_g4x_display_port;

409

limit = &intel_limits_g4x_display_port;

410

} else /* The option is for other outputs */

410

} else /* The option is for other outputs */

411

limit = &intel_limits_i9xx_sdvo;

411

limit = &intel_limits_i9xx_sdvo;

412

413

return limit;

413

return limit;

414

}

414

}

415

416

static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)

416

static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)

417

{

417

{

418

struct drm_device *dev = crtc->dev;

418

struct drm_device *dev = crtc->dev;

419

const intel_limit_t *limit;

419

const intel_limit_t *limit;

420

421

if (HAS_PCH_SPLIT(dev))

421

if (HAS_PCH_SPLIT(dev))

422

limit = intel_ironlake_limit(crtc, refclk);

422

limit = intel_ironlake_limit(crtc, refclk);

423

else if (IS_G4X(dev)) {

423

else if (IS_G4X(dev)) {

424

limit = intel_g4x_limit(crtc);

424

limit = intel_g4x_limit(crtc);

425

} else if (IS_PINEVIEW(dev)) {

425

} else if (IS_PINEVIEW(dev)) {

426

if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))

426

if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))

427

limit = &intel_limits_pineview_lvds;

427

limit = &intel_limits_pineview_lvds;

428

else

428

else

429

limit = &intel_limits_pineview_sdvo;

429

limit = &intel_limits_pineview_sdvo;

430

} else if (!IS_GEN2(dev)) {

430

} else if (!IS_GEN2(dev)) {

431

if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))

431

if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))

432

limit = &intel_limits_i9xx_lvds;

432

limit = &intel_limits_i9xx_lvds;

433

else

433

else

434

limit = &intel_limits_i9xx_sdvo;

434

limit = &intel_limits_i9xx_sdvo;

435

} else {

435

} else {

436

if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))

436

if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))

437

limit = &intel_limits_i8xx_lvds;

437

limit = &intel_limits_i8xx_lvds;

438

else

438

else

439

limit = &intel_limits_i8xx_dvo;

439

limit = &intel_limits_i8xx_dvo;

440

}

440

}

441

return limit;

441

return limit;

442

}

442

}

443

444

/* m1 is reserved as 0 in Pineview, n is a ring counter */

444

/* m1 is reserved as 0 in Pineview, n is a ring counter */

445

static void pineview_clock(int refclk, intel_clock_t *clock)

445

static void pineview_clock(int refclk, intel_clock_t *clock)

446

{

446

{

447

clock->m = clock->m2 + 2;

447

clock->m = clock->m2 + 2;

448

clock->p = clock->p1 * clock->p2;

448

clock->p = clock->p1 * clock->p2;

449

clock->vco = refclk * clock->m / clock->n;

449

clock->vco = refclk * clock->m / clock->n;

450

clock->dot = clock->vco / clock->p;

450

clock->dot = clock->vco / clock->p;

451

}

451

}

452

453

static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)

453

static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)

454

{

454

{

455

if (IS_PINEVIEW(dev)) {

455

if (IS_PINEVIEW(dev)) {

456

pineview_clock(refclk, clock);

456

pineview_clock(refclk, clock);

457

return;

457

return;

458

}

458

}

459

clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);

459

clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);

460

clock->p = clock->p1 * clock->p2;

460

clock->p = clock->p1 * clock->p2;

461

clock->vco = refclk * clock->m / (clock->n + 2);

461

clock->vco = refclk * clock->m / (clock->n + 2);

462

clock->dot = clock->vco / clock->p;

462

clock->dot = clock->vco / clock->p;

463

}

463

}

464

465

/**

465

/**

466

* Returns whether any output on the specified pipe is of the specified type

466

* Returns whether any output on the specified pipe is of the specified type

467

*/

467

*/

468

bool intel_pipe_has_type(struct drm_crtc *crtc, int type)

468

bool intel_pipe_has_type(struct drm_crtc *crtc, int type)

469

{

469

{

470

struct drm_device *dev = crtc->dev;

470

struct drm_device *dev = crtc->dev;

471

struct drm_mode_config *mode_config = &dev->mode_config;

471

struct drm_mode_config *mode_config = &dev->mode_config;

472

struct intel_encoder *encoder;

472

struct intel_encoder *encoder;

473

474

list_for_each_entry(encoder, &mode_config->encoder_list, base.head)

474

list_for_each_entry(encoder, &mode_config->encoder_list, base.head)

475

if (encoder->base.crtc == crtc && encoder->type == type)

475

if (encoder->base.crtc == crtc && encoder->type == type)

476

return true;

476

return true;

477

478

return false;

478

return false;

479

}

479

}

480

481

#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)

481

#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)

482

/**

482

/**

483

* Returns whether the given set of divisors are valid for a given refclk with

483

* Returns whether the given set of divisors are valid for a given refclk with

484

* the given connectors.

484

* the given connectors.

485

*/

485

*/

486

487

static bool intel_PLL_is_valid(struct drm_device *dev,

487

static bool intel_PLL_is_valid(struct drm_device *dev,

488

const intel_limit_t *limit,

488

const intel_limit_t *limit,

489

const intel_clock_t *clock)

489

const intel_clock_t *clock)

490

{

490

{

491

if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)

491

if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)

492

INTELPllInvalid("p1 out of range\n");

492

INTELPllInvalid("p1 out of range\n");

493

if (clock->p < limit->p.min || limit->p.max < clock->p)

493

if (clock->p < limit->p.min || limit->p.max < clock->p)

494

INTELPllInvalid("p out of range\n");

494

INTELPllInvalid("p out of range\n");

495

if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)

495

if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)

496

INTELPllInvalid("m2 out of range\n");

496

INTELPllInvalid("m2 out of range\n");

497

if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)

497

if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)

498

INTELPllInvalid("m1 out of range\n");

498

INTELPllInvalid("m1 out of range\n");

499

if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))

499

if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))

500

INTELPllInvalid("m1 <= m2\n");

500

INTELPllInvalid("m1 <= m2\n");

501

if (clock->m < limit->m.min || limit->m.max < clock->m)

501

if (clock->m < limit->m.min || limit->m.max < clock->m)

502

INTELPllInvalid("m out of range\n");

502

INTELPllInvalid("m out of range\n");

503

if (clock->n < limit->n.min || limit->n.max < clock->n)

503

if (clock->n < limit->n.min || limit->n.max < clock->n)

504

INTELPllInvalid("n out of range\n");

504

INTELPllInvalid("n out of range\n");

505

if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)

505

if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)

506

INTELPllInvalid("vco out of range\n");

506

INTELPllInvalid("vco out of range\n");

507

/* XXX: We may need to be checking "Dot clock" depending on the multiplier,

507

/* XXX: We may need to be checking "Dot clock" depending on the multiplier,

508

* connector, etc., rather than just a single range.

508

* connector, etc., rather than just a single range.

509

*/

509

*/

510

if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)

510

if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)

511

INTELPllInvalid("dot out of range\n");

511

INTELPllInvalid("dot out of range\n");

512

513

return true;

513

return true;

514

}

514

}

515

516

static bool

516

static bool

517

intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,

517

intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,

518

int target, int refclk, intel_clock_t *best_clock)

518

int target, int refclk, intel_clock_t *best_clock)

519

520

{

520

{

521

struct drm_device *dev = crtc->dev;

521

struct drm_device *dev = crtc->dev;

522

struct drm_i915_private *dev_priv = dev->dev_private;

522

struct drm_i915_private *dev_priv = dev->dev_private;

523

intel_clock_t clock;

523

intel_clock_t clock;

524

int err = target;

524

int err = target;

525

526

if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&

526

if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&

527

(I915_READ(LVDS)) != 0) {

527

(I915_READ(LVDS)) != 0) {

528

/*

528

/*

529

* For LVDS, if the panel is on, just rely on its current

529

* For LVDS, if the panel is on, just rely on its current

530

* settings for dual-channel. We haven't figured out how to

530

* settings for dual-channel. We haven't figured out how to

531

* reliably set up different single/dual channel state, if we

531

* reliably set up different single/dual channel state, if we

532

* even can.

532

* even can.

533

*/

533

*/

534

if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==

534

if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==

535

LVDS_CLKB_POWER_UP)

535

LVDS_CLKB_POWER_UP)

536

clock.p2 = limit->p2.p2_fast;

536

clock.p2 = limit->p2.p2_fast;

537

else

537

else

538

clock.p2 = limit->p2.p2_slow;

538

clock.p2 = limit->p2.p2_slow;

539

} else {

539

} else {

540

if (target < limit->p2.dot_limit)

540

if (target < limit->p2.dot_limit)

541

clock.p2 = limit->p2.p2_slow;

541

clock.p2 = limit->p2.p2_slow;

542

else

542

else

543

clock.p2 = limit->p2.p2_fast;

543

clock.p2 = limit->p2.p2_fast;

544

}

544

}

545

546

memset(best_clock, 0, sizeof(*best_clock));

546

memset(best_clock, 0, sizeof(*best_clock));

547

548

for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;

548

for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;

549

clock.m1++) {

549

clock.m1++) {

550

for (clock.m2 = limit->m2.min;

550

for (clock.m2 = limit->m2.min;

551

clock.m2 <= limit->m2.max; clock.m2++) {

551

clock.m2 <= limit->m2.max; clock.m2++) {

552

/* m1 is always 0 in Pineview */

552

/* m1 is always 0 in Pineview */

553

if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))

553

if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))

554

break;

554

break;

555

for (clock.n = limit->n.min;

555

for (clock.n = limit->n.min;

556

clock.n <= limit->n.max; clock.n++) {

556

clock.n <= limit->n.max; clock.n++) {

557

for (clock.p1 = limit->p1.min;

557

for (clock.p1 = limit->p1.min;

558

clock.p1 <= limit->p1.max; clock.p1++) {

558

clock.p1 <= limit->p1.max; clock.p1++) {

559

int this_err;

559

int this_err;

560

561

intel_clock(dev, refclk, &clock);

561

intel_clock(dev, refclk, &clock);

562

if (!intel_PLL_is_valid(dev, limit,

562

if (!intel_PLL_is_valid(dev, limit,

563

&clock))

563

&clock))

564

continue;

564

continue;

565

566

this_err = abs(clock.dot - target);

566

this_err = abs(clock.dot - target);

567

if (this_err < err) {

567

if (this_err < err) {

568

*best_clock = clock;

568

*best_clock = clock;

569

err = this_err;

569

err = this_err;

570

}

570

}

571

}

571

}

572

}

572

}

573

}

573

}

574

}

574

}

575

576

return (err != target);

576

return (err != target);

577

}

577

}

578

579

static bool

579

static bool

580

intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,

580

intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,

581

int target, int refclk, intel_clock_t *best_clock)

581

int target, int refclk, intel_clock_t *best_clock)

582

{

582

{

583

struct drm_device *dev = crtc->dev;

583

struct drm_device *dev = crtc->dev;

584

struct drm_i915_private *dev_priv = dev->dev_private;

584

struct drm_i915_private *dev_priv = dev->dev_private;

585

intel_clock_t clock;

585

intel_clock_t clock;

586

int max_n;

586

int max_n;

587

bool found;

587

bool found;

588

/* approximately equals target * 0.00585 */

588

/* approximately equals target * 0.00585 */

589

int err_most = (target >> 8) + (target >> 9);

589

int err_most = (target >> 8) + (target >> 9);

590

found = false;

590

found = false;

591

592

if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {

592

if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {

593

int lvds_reg;

593

int lvds_reg;

594

595

if (HAS_PCH_SPLIT(dev))

595

if (HAS_PCH_SPLIT(dev))

596

lvds_reg = PCH_LVDS;

596

lvds_reg = PCH_LVDS;

597

else

597

else

598

lvds_reg = LVDS;

598

lvds_reg = LVDS;

599

if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==

599

if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==

600

LVDS_CLKB_POWER_UP)

600

LVDS_CLKB_POWER_UP)

601

clock.p2 = limit->p2.p2_fast;

601

clock.p2 = limit->p2.p2_fast;

602

else

602

else

603

clock.p2 = limit->p2.p2_slow;

603

clock.p2 = limit->p2.p2_slow;

604

} else {

604

} else {

605

if (target < limit->p2.dot_limit)

605

if (target < limit->p2.dot_limit)

606

clock.p2 = limit->p2.p2_slow;

606

clock.p2 = limit->p2.p2_slow;

607

else

607

else

608

clock.p2 = limit->p2.p2_fast;

608

clock.p2 = limit->p2.p2_fast;

609

}

609

}

610

611

memset(best_clock, 0, sizeof(*best_clock));

611

memset(best_clock, 0, sizeof(*best_clock));

612

max_n = limit->n.max;

612

max_n = limit->n.max;

613

/* based on hardware requirement, prefer smaller n to precision */

613

/* based on hardware requirement, prefer smaller n to precision */

614

for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {

614

for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {

615

/* based on hardware requirement, prefere larger m1,m2 */

615

/* based on hardware requirement, prefere larger m1,m2 */

616

for (clock.m1 = limit->m1.max;

616

for (clock.m1 = limit->m1.max;

617

clock.m1 >= limit->m1.min; clock.m1--) {

617

clock.m1 >= limit->m1.min; clock.m1--) {

618

for (clock.m2 = limit->m2.max;

618

for (clock.m2 = limit->m2.max;

619

clock.m2 >= limit->m2.min; clock.m2--) {

619

clock.m2 >= limit->m2.min; clock.m2--) {

620

for (clock.p1 = limit->p1.max;

620

for (clock.p1 = limit->p1.max;

621

clock.p1 >= limit->p1.min; clock.p1--) {

621

clock.p1 >= limit->p1.min; clock.p1--) {

622

int this_err;

622

int this_err;

623

624

intel_clock(dev, refclk, &clock);

624

intel_clock(dev, refclk, &clock);

625

if (!intel_PLL_is_valid(dev, limit,

625

if (!intel_PLL_is_valid(dev, limit,

626

&clock))

626

&clock))

627

continue;

627

continue;

628

629

this_err = abs(clock.dot - target);

629

this_err = abs(clock.dot - target);

630

if (this_err < err_most) {

630

if (this_err < err_most) {

631

*best_clock = clock;

631

*best_clock = clock;

632

err_most = this_err;

632

err_most = this_err;

633

max_n = clock.n;

633

max_n = clock.n;

634

found = true;

634

found = true;

635

}

635

}

636

}

636

}

637

}

637

}

638

}

638

}

639

}

639

}

640

return found;

640

return found;

641

}

641

}

642

643

static bool

643

static bool

644

intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,

644

intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,

645

int target, int refclk, intel_clock_t *best_clock)

645

int target, int refclk, intel_clock_t *best_clock)

646

{

646

{

647

struct drm_device *dev = crtc->dev;

647

struct drm_device *dev = crtc->dev;

648

intel_clock_t clock;

648

intel_clock_t clock;

649

650

if (target < 200000) {

650

if (target < 200000) {

651

clock.n = 1;

651

clock.n = 1;

652

clock.p1 = 2;

652

clock.p1 = 2;

653

clock.p2 = 10;

653

clock.p2 = 10;

654

clock.m1 = 12;

654

clock.m1 = 12;

655

clock.m2 = 9;

655

clock.m2 = 9;

656

} else {

656

} else {

657

clock.n = 2;

657

clock.n = 2;

658

clock.p1 = 1;

658

clock.p1 = 1;

659

clock.p2 = 10;

659

clock.p2 = 10;

660

clock.m1 = 14;

660

clock.m1 = 14;

661

clock.m2 = 8;

661

clock.m2 = 8;

662

}

662

}

663

intel_clock(dev, refclk, &clock);

663

intel_clock(dev, refclk, &clock);

664

memcpy(best_clock, &clock, sizeof(intel_clock_t));

664

memcpy(best_clock, &clock, sizeof(intel_clock_t));

665

return true;

665

return true;

666

}

666

}

667

668

/* DisplayPort has only two frequencies, 162MHz and 270MHz */

668

/* DisplayPort has only two frequencies, 162MHz and 270MHz */

669

static bool

669

static bool

670

intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,

670

intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,

671

int target, int refclk, intel_clock_t *best_clock)

671

int target, int refclk, intel_clock_t *best_clock)

672

{

672

{

673

intel_clock_t clock;

673

intel_clock_t clock;

674

if (target < 200000) {

674

if (target < 200000) {

675

clock.p1 = 2;

675

clock.p1 = 2;

676

clock.p2 = 10;

676

clock.p2 = 10;

677

clock.n = 2;

677

clock.n = 2;

678

clock.m1 = 23;

678

clock.m1 = 23;

679

clock.m2 = 8;

679

clock.m2 = 8;

680

} else {

680

} else {

681

clock.p1 = 1;

681

clock.p1 = 1;

682

clock.p2 = 10;

682

clock.p2 = 10;

683

clock.n = 1;

683

clock.n = 1;

684

clock.m1 = 14;

684

clock.m1 = 14;

685

clock.m2 = 2;

685

clock.m2 = 2;

686

}

686

}

687

clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);

687

clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);

688

clock.p = (clock.p1 * clock.p2);

688

clock.p = (clock.p1 * clock.p2);

689

clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;

689

clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;

690

clock.vco = 0;

690

clock.vco = 0;

691

memcpy(best_clock, &clock, sizeof(intel_clock_t));

691

memcpy(best_clock, &clock, sizeof(intel_clock_t));

692

return true;

692

return true;

693

}

693

}

694

695

/**

695

/**

696

* intel_wait_for_vblank - wait for vblank on a given pipe

696

* intel_wait_for_vblank - wait for vblank on a given pipe

697

* @dev: drm device

697

* @dev: drm device

698

* @pipe: pipe to wait for

698

* @pipe: pipe to wait for

699

*

699

*

700

* Wait for vblank to occur on a given pipe. Needed for various bits of

700

* Wait for vblank to occur on a given pipe. Needed for various bits of

701

* mode setting code.

701

* mode setting code.

702

*/

702

*/

703

void intel_wait_for_vblank(struct drm_device *dev, int pipe)

703

void intel_wait_for_vblank(struct drm_device *dev, int pipe)

704

{

704

{

705

struct drm_i915_private *dev_priv = dev->dev_private;

705

struct drm_i915_private *dev_priv = dev->dev_private;

706

int pipestat_reg = PIPESTAT(pipe);

706

int pipestat_reg = PIPESTAT(pipe);

707

708

/* Clear existing vblank status. Note this will clear any other

708

/* Clear existing vblank status. Note this will clear any other

709

* sticky status fields as well.

709

* sticky status fields as well.

710

*

710

*

711

* This races with i915_driver_irq_handler() with the result

711

* This races with i915_driver_irq_handler() with the result

712

* that either function could miss a vblank event. Here it is not

712

* that either function could miss a vblank event. Here it is not

713

* fatal, as we will either wait upon the next vblank interrupt or

713

* fatal, as we will either wait upon the next vblank interrupt or

714

* timeout. Generally speaking intel_wait_for_vblank() is only

714

* timeout. Generally speaking intel_wait_for_vblank() is only

715

* called during modeset at which time the GPU should be idle and

715

* called during modeset at which time the GPU should be idle and

716

* should *not* be performing page flips and thus not waiting on

716

* should *not* be performing page flips and thus not waiting on

717

* vblanks...

717

* vblanks...

718

* Currently, the result of us stealing a vblank from the irq

718

* Currently, the result of us stealing a vblank from the irq

719

* handler is that a single frame will be skipped during swapbuffers.

719

* handler is that a single frame will be skipped during swapbuffers.

720

*/

720

*/

721

I915_WRITE(pipestat_reg,

721

I915_WRITE(pipestat_reg,

722

I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);

722

I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);

723

724

/* Wait for vblank interrupt bit to set */

724

/* Wait for vblank interrupt bit to set */

725

if (wait_for(I915_READ(pipestat_reg) &

725

if (wait_for(I915_READ(pipestat_reg) &

726

PIPE_VBLANK_INTERRUPT_STATUS,

726

PIPE_VBLANK_INTERRUPT_STATUS,

727

50))

727

50))

728

DRM_DEBUG_KMS("vblank wait timed out\n");

728

DRM_DEBUG_KMS("vblank wait timed out\n");

729

}

729

}

730

731

/*

731

/*

732

* intel_wait_for_pipe_off - wait for pipe to turn off

732

* intel_wait_for_pipe_off - wait for pipe to turn off

733

* @dev: drm device

733

* @dev: drm device

734

* @pipe: pipe to wait for

734

* @pipe: pipe to wait for

735

*

735

*

736

* After disabling a pipe, we can't wait for vblank in the usual way,

736

* After disabling a pipe, we can't wait for vblank in the usual way,

737

* spinning on the vblank interrupt status bit, since we won't actually

737

* spinning on the vblank interrupt status bit, since we won't actually

738

* see an interrupt when the pipe is disabled.

738

* see an interrupt when the pipe is disabled.

739

*

739

*

740

* On Gen4 and above:

740

* On Gen4 and above:

741

* wait for the pipe register state bit to turn off

741

* wait for the pipe register state bit to turn off

742

*

742

*

743

* Otherwise:

743

* Otherwise:

744

* wait for the display line value to settle (it usually

744

* wait for the display line value to settle (it usually

745

* ends up stopping at the start of the next frame).

745

* ends up stopping at the start of the next frame).

746

*

746

*

747

*/

747

*/

748

void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)

748

void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)

749

{

749

{

750

struct drm_i915_private *dev_priv = dev->dev_private;

750

struct drm_i915_private *dev_priv = dev->dev_private;

751

752

if (INTEL_INFO(dev)->gen >= 4) {

752

if (INTEL_INFO(dev)->gen >= 4) {

753

int reg = PIPECONF(pipe);

753

int reg = PIPECONF(pipe);

754

755

/* Wait for the Pipe State to go off */

755

/* Wait for the Pipe State to go off */

756

if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,

756

if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,

757

100))

757

100))

758

DRM_DEBUG_KMS("pipe_off wait timed out\n");

758

DRM_DEBUG_KMS("pipe_off wait timed out\n");

759

} else {

759

} else {

760

u32 last_line;

760

u32 last_line;

761

int reg = PIPEDSL(pipe);

761

int reg = PIPEDSL(pipe);

762

unsigned long timeout = jiffies + msecs_to_jiffies(100);

762

unsigned long timeout = jiffies + msecs_to_jiffies(100);

763

764

/* Wait for the display line to settle */

764

/* Wait for the display line to settle */

765

do {

765

do {

766

last_line = I915_READ(reg) & DSL_LINEMASK;

766

last_line = I915_READ(reg) & DSL_LINEMASK;

767

mdelay(5);

767

mdelay(5);

768

} while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&

768

} while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&

769

time_after(timeout, jiffies));

769

time_after(timeout, jiffies));

770

if (time_after(jiffies, timeout))

770

if (time_after(jiffies, timeout))

771

DRM_DEBUG_KMS("pipe_off wait timed out\n");

771

DRM_DEBUG_KMS("pipe_off wait timed out\n");

772

}

772

}

773

}

773

}

774

775

static const char *state_string(bool enabled)

775

static const char *state_string(bool enabled)

776

{

776

{

777

return enabled ? "on" : "off";

777

return enabled ? "on" : "off";

778

}

778

}

779

780

/* Only for pre-ILK configs */

780

/* Only for pre-ILK configs */

781

static void assert_pll(struct drm_i915_private *dev_priv,

781

static void assert_pll(struct drm_i915_private *dev_priv,

782

enum pipe pipe, bool state)

782

enum pipe pipe, bool state)

783

{

783

{

784

int reg;

784

int reg;

785

u32 val;

785

u32 val;

786

bool cur_state;

786

bool cur_state;

787

788

reg = DPLL(pipe);

788

reg = DPLL(pipe);

789

val = I915_READ(reg);

789

val = I915_READ(reg);

790

cur_state = !!(val & DPLL_VCO_ENABLE);

790

cur_state = !!(val & DPLL_VCO_ENABLE);

791

WARN(cur_state != state,

791

WARN(cur_state != state,

792

"PLL state assertion failure (expected %s, current %s)\n",

792

"PLL state assertion failure (expected %s, current %s)\n",

793

state_string(state), state_string(cur_state));

793

state_string(state), state_string(cur_state));

794

}

794

}

795

#define assert_pll_enabled(d, p) assert_pll(d, p, true)

795

#define assert_pll_enabled(d, p) assert_pll(d, p, true)

796

#define assert_pll_disabled(d, p) assert_pll(d, p, false)

796

#define assert_pll_disabled(d, p) assert_pll(d, p, false)

797

798

/* For ILK+ */

798

/* For ILK+ */

799

static void assert_pch_pll(struct drm_i915_private *dev_priv,

799

static void assert_pch_pll(struct drm_i915_private *dev_priv,

800

enum pipe pipe, bool state)

800

enum pipe pipe, bool state)

801

{

801

{

802

int reg;

802

int reg;

803

u32 val;

803

u32 val;

804

bool cur_state;

804

bool cur_state;

805

806

if (HAS_PCH_CPT(dev_priv->dev)) {

806

if (HAS_PCH_CPT(dev_priv->dev)) {

807

u32 pch_dpll;

807

u32 pch_dpll;

808

809

pch_dpll = I915_READ(PCH_DPLL_SEL);

809

pch_dpll = I915_READ(PCH_DPLL_SEL);

810

811

/* Make sure the selected PLL is enabled to the transcoder */

811

/* Make sure the selected PLL is enabled to the transcoder */

812

WARN(!((pch_dpll >> (4 * pipe)) & 8),

812

WARN(!((pch_dpll >> (4 * pipe)) & 8),

813

"transcoder %d PLL not enabled\n", pipe);

813

"transcoder %d PLL not enabled\n", pipe);

814

815

/* Convert the transcoder pipe number to a pll pipe number */

815

/* Convert the transcoder pipe number to a pll pipe number */

816

pipe = (pch_dpll >> (4 * pipe)) & 1;

816

pipe = (pch_dpll >> (4 * pipe)) & 1;

817

}

817

}

818

819

reg = PCH_DPLL(pipe);

819

reg = PCH_DPLL(pipe);

820

val = I915_READ(reg);

820

val = I915_READ(reg);

821

cur_state = !!(val & DPLL_VCO_ENABLE);

821

cur_state = !!(val & DPLL_VCO_ENABLE);

822

WARN(cur_state != state,

822

WARN(cur_state != state,

823

"PCH PLL state assertion failure (expected %s, current %s)\n",

823

"PCH PLL state assertion failure (expected %s, current %s)\n",

824

state_string(state), state_string(cur_state));

824

state_string(state), state_string(cur_state));

825

}

825

}

826

#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)

826

#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)

827

#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)

827

#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)

828

829

static void assert_fdi_tx(struct drm_i915_private *dev_priv,

829

static void assert_fdi_tx(struct drm_i915_private *dev_priv,

830

enum pipe pipe, bool state)

830

enum pipe pipe, bool state)

831

{

831

{

832

int reg;

832

int reg;

833

u32 val;

833

u32 val;

834

bool cur_state;

834

bool cur_state;

835

836

reg = FDI_TX_CTL(pipe);

836

reg = FDI_TX_CTL(pipe);

837

val = I915_READ(reg);

837

val = I915_READ(reg);

838

cur_state = !!(val & FDI_TX_ENABLE);

838

cur_state = !!(val & FDI_TX_ENABLE);

839

WARN(cur_state != state,

839

WARN(cur_state != state,

840

"FDI TX state assertion failure (expected %s, current %s)\n",

840

"FDI TX state assertion failure (expected %s, current %s)\n",

841

state_string(state), state_string(cur_state));

841

state_string(state), state_string(cur_state));

842

}

842

}

843

#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)

843

#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)

844

#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)

844

#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)

845

846

static void assert_fdi_rx(struct drm_i915_private *dev_priv,

846

static void assert_fdi_rx(struct drm_i915_private *dev_priv,

847

enum pipe pipe, bool state)

847

enum pipe pipe, bool state)

848

{

848

{

849

int reg;

849

int reg;

850

u32 val;

850

u32 val;

851

bool cur_state;

851

bool cur_state;

852

853

reg = FDI_RX_CTL(pipe);

853

reg = FDI_RX_CTL(pipe);

854

val = I915_READ(reg);

854

val = I915_READ(reg);

855

cur_state = !!(val & FDI_RX_ENABLE);

855

cur_state = !!(val & FDI_RX_ENABLE);

856

WARN(cur_state != state,

856

WARN(cur_state != state,

857

"FDI RX state assertion failure (expected %s, current %s)\n",

857

"FDI RX state assertion failure (expected %s, current %s)\n",

858

state_string(state), state_string(cur_state));

858

state_string(state), state_string(cur_state));

859

}

859

}

860

#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)

860

#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)

861

#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)

861

#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)

862

863

static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,

863

static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,

864

enum pipe pipe)

864

enum pipe pipe)

865

{

865

{

866

int reg;

866

int reg;

867

u32 val;

867

u32 val;

868

869

/* ILK FDI PLL is always enabled */

869

/* ILK FDI PLL is always enabled */

870

if (dev_priv->info->gen == 5)

870

if (dev_priv->info->gen == 5)

871

return;

871

return;

872

873

reg = FDI_TX_CTL(pipe);

873

reg = FDI_TX_CTL(pipe);

874

val = I915_READ(reg);

874

val = I915_READ(reg);

875

WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");

875

WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");

876

}

876

}

877

878

static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,

878

static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,

879

enum pipe pipe)

879

enum pipe pipe)

880

{

880

{

881

int reg;

881

int reg;

882

u32 val;

882

u32 val;

883

884

reg = FDI_RX_CTL(pipe);

884

reg = FDI_RX_CTL(pipe);

885

val = I915_READ(reg);

885

val = I915_READ(reg);

886

WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");

886

WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");

887

}

887

}

888

889

static void assert_panel_unlocked(struct drm_i915_private *dev_priv,

889

static void assert_panel_unlocked(struct drm_i915_private *dev_priv,

890

enum pipe pipe)

890

enum pipe pipe)

891

{

891

{

892

int pp_reg, lvds_reg;

892

int pp_reg, lvds_reg;

893

u32 val;

893

u32 val;

894

enum pipe panel_pipe = PIPE_A;

894

enum pipe panel_pipe = PIPE_A;

895

bool locked = true;

895

bool locked = true;

896

897

if (HAS_PCH_SPLIT(dev_priv->dev)) {

897

if (HAS_PCH_SPLIT(dev_priv->dev)) {

898

pp_reg = PCH_PP_CONTROL;

898

pp_reg = PCH_PP_CONTROL;

899

lvds_reg = PCH_LVDS;

899

lvds_reg = PCH_LVDS;

900

} else {

900

} else {

901

pp_reg = PP_CONTROL;

901

pp_reg = PP_CONTROL;

902

lvds_reg = LVDS;

902

lvds_reg = LVDS;

903

}

903

}

904

905

val = I915_READ(pp_reg);

905

val = I915_READ(pp_reg);

906

if (!(val & PANEL_POWER_ON) ||

906

if (!(val & PANEL_POWER_ON) ||

907

((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))

907

((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))

908

locked = false;

908

locked = false;

909

910

if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)

910

if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)

911

panel_pipe = PIPE_B;

911

panel_pipe = PIPE_B;

912

913

WARN(panel_pipe == pipe && locked,

913

WARN(panel_pipe == pipe && locked,

914

"panel assertion failure, pipe %c regs locked\n",

914

"panel assertion failure, pipe %c regs locked\n",

915

pipe_name(pipe));

915

pipe_name(pipe));

916

}

916

}

917

918

static void assert_pipe(struct drm_i915_private *dev_priv,

918

static void assert_pipe(struct drm_i915_private *dev_priv,

919

enum pipe pipe, bool state)

919

enum pipe pipe, bool state)

920

{

920

{

921

int reg;

921

int reg;

922

u32 val;

922

u32 val;

923

bool cur_state;

923

bool cur_state;

924

925

reg = PIPECONF(pipe);

925

reg = PIPECONF(pipe);

926

val = I915_READ(reg);

926

val = I915_READ(reg);

927

cur_state = !!(val & PIPECONF_ENABLE);

927

cur_state = !!(val & PIPECONF_ENABLE);

928

WARN(cur_state != state,

928

WARN(cur_state != state,

929

"pipe %c assertion failure (expected %s, current %s)\n",

929

"pipe %c assertion failure (expected %s, current %s)\n",

930

pipe_name(pipe), state_string(state), state_string(cur_state));

930

pipe_name(pipe), state_string(state), state_string(cur_state));

931

}

931

}

932

#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)

932

#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)

933

#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)

933

#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)

934

935

static void assert_plane_enabled(struct drm_i915_private *dev_priv,

935

static void assert_plane_enabled(struct drm_i915_private *dev_priv,

936

enum plane plane)

936

enum plane plane)

937

{

937

{

938

int reg;

938

int reg;

939

u32 val;

939

u32 val;

940

941

reg = DSPCNTR(plane);

941

reg = DSPCNTR(plane);

942

val = I915_READ(reg);

942

val = I915_READ(reg);

943

WARN(!(val & DISPLAY_PLANE_ENABLE),

943

WARN(!(val & DISPLAY_PLANE_ENABLE),

944

"plane %c assertion failure, should be active but is disabled\n",

944

"plane %c assertion failure, should be active but is disabled\n",

945

plane_name(plane));

945

plane_name(plane));

946

}

946

}

947

948

static void assert_planes_disabled(struct drm_i915_private *dev_priv,

948

static void assert_planes_disabled(struct drm_i915_private *dev_priv,

949

enum pipe pipe)

949

enum pipe pipe)

950

{

950

{

951

int reg, i;

951

int reg, i;

952

u32 val;

952

u32 val;

953

int cur_pipe;

953

int cur_pipe;

954

955

/* Planes are fixed to pipes on ILK+ */

955

/* Planes are fixed to pipes on ILK+ */

956

if (HAS_PCH_SPLIT(dev_priv->dev))

956

if (HAS_PCH_SPLIT(dev_priv->dev))

957

return;

957

return;

958

959

/* Need to check both planes against the pipe */

959

/* Need to check both planes against the pipe */

960

for (i = 0; i < 2; i++) {

960

for (i = 0; i < 2; i++) {

961

reg = DSPCNTR(i);

961

reg = DSPCNTR(i);

962

val = I915_READ(reg);

962

val = I915_READ(reg);

963

cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>

963

cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>

964

DISPPLANE_SEL_PIPE_SHIFT;

964

DISPPLANE_SEL_PIPE_SHIFT;

965

WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,

965

WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,

966

"plane %c assertion failure, should be off on pipe %c but is still active\n",

966

"plane %c assertion failure, should be off on pipe %c but is still active\n",

967

plane_name(i), pipe_name(pipe));

967

plane_name(i), pipe_name(pipe));

968

}

968

}

969

}

969

}

970

971

static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)

971

static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)

972

{

972

{

973

u32 val;

973

u32 val;

974

bool enabled;

974

bool enabled;

975

976

val = I915_READ(PCH_DREF_CONTROL);

976

val = I915_READ(PCH_DREF_CONTROL);

977

enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |

977

enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |

978

DREF_SUPERSPREAD_SOURCE_MASK));

978

DREF_SUPERSPREAD_SOURCE_MASK));

979

WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");

979

WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");

980

}

980

}

981

982

static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,

982

static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,

983

enum pipe pipe)

983

enum pipe pipe)

984

{

984

{

985

int reg;

985

int reg;

986

u32 val;

986

u32 val;

987

bool enabled;

987

bool enabled;

988

989

reg = TRANSCONF(pipe);

989

reg = TRANSCONF(pipe);

990

val = I915_READ(reg);

990

val = I915_READ(reg);

991

enabled = !!(val & TRANS_ENABLE);

991

enabled = !!(val & TRANS_ENABLE);

992

WARN(enabled,

992

WARN(enabled,

993

"transcoder assertion failed, should be off on pipe %c but is still active\n",

993

"transcoder assertion failed, should be off on pipe %c but is still active\n",

994

pipe_name(pipe));

994

pipe_name(pipe));

995

}

995

}

996

997

static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,

997

static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,

998

enum pipe pipe, u32 port_sel, u32 val)

998

enum pipe pipe, u32 port_sel, u32 val)

999

{

999

{

1000

if ((val & DP_PORT_EN) == 0)

1000

if ((val & DP_PORT_EN) == 0)

1001

return false;

1001

return false;

1002

1003

if (HAS_PCH_CPT(dev_priv->dev)) {

1003

if (HAS_PCH_CPT(dev_priv->dev)) {

1004

u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);

1004

u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);

1005

u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);

1005

u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);

1006

if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)

1006

if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)

1007

return false;

1007

return false;

1008

} else {

1008

} else {

1009

if ((val & DP_PIPE_MASK) != (pipe << 30))

1009

if ((val & DP_PIPE_MASK) != (pipe << 30))

1010

return false;

1010

return false;

1011

}

1011

}

1012

return true;

1012

return true;

1013

}

1013

}

1014

1015

static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,

1015

static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,

1016

enum pipe pipe, u32 val)

1016

enum pipe pipe, u32 val)

1017

{

1017

{

1018

if ((val & PORT_ENABLE) == 0)

1018

if ((val & PORT_ENABLE) == 0)

1019

return false;

1019

return false;

1020

1021

if (HAS_PCH_CPT(dev_priv->dev)) {

1021

if (HAS_PCH_CPT(dev_priv->dev)) {

1022

if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))

1022

if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))

1023

return false;

1023

return false;

1024

} else {

1024

} else {

1025

if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))

1025

if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))

1026

return false;

1026

return false;

1027

}

1027

}

1028

return true;

1028

return true;

1029

}

1029

}

1030

1031

static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,

1031

static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,

1032

enum pipe pipe, u32 val)

1032

enum pipe pipe, u32 val)

1033

{

1033

{

1034

if ((val & LVDS_PORT_EN) == 0)

1034

if ((val & LVDS_PORT_EN) == 0)

1035

return false;

1035

return false;

1036

1037

if (HAS_PCH_CPT(dev_priv->dev)) {

1037

if (HAS_PCH_CPT(dev_priv->dev)) {

1038

if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))

1038

if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))

1039

return false;

1039

return false;

1040

} else {

1040

} else {

1041

if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))

1041

if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))

1042

return false;

1042

return false;

1043

}

1043

}

1044

return true;

1044

return true;

1045

}

1045

}

1046

1047

static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,

1047

static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,

1048

enum pipe pipe, u32 val)

1048

enum pipe pipe, u32 val)

1049

{

1049

{

1050

if ((val & ADPA_DAC_ENABLE) == 0)

1050

if ((val & ADPA_DAC_ENABLE) == 0)

1051

return false;

1051

return false;

1052

if (HAS_PCH_CPT(dev_priv->dev)) {

1052

if (HAS_PCH_CPT(dev_priv->dev)) {

1053

if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))

1053

if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))

1054

return false;

1054

return false;

1055

} else {

1055

} else {

1056

if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))

1056

if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))

1057

return false;

1057

return false;

1058

}

1058

}

1059

return true;

1059

return true;

1060

}

1060

}

1061

1062

static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,

1062

static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,

1063

enum pipe pipe, int reg, u32 port_sel)

1063

enum pipe pipe, int reg, u32 port_sel)

1064

{

1064

{

1065

u32 val = I915_READ(reg);

1065

u32 val = I915_READ(reg);

1066

WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),

1066

WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),

1067

"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",

1067

"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",

1068

reg, pipe_name(pipe));

1068

reg, pipe_name(pipe));

1069

}

1069

}

1070

1071

static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,

1071

static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,

1072

enum pipe pipe, int reg)

1072

enum pipe pipe, int reg)

1073

{

1073

{

1074

u32 val = I915_READ(reg);

1074

u32 val = I915_READ(reg);

1075

WARN(hdmi_pipe_enabled(dev_priv, val, pipe),

1075

WARN(hdmi_pipe_enabled(dev_priv, val, pipe),

1076

"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",

1076

"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",

1077

reg, pipe_name(pipe));

1077

reg, pipe_name(pipe));

1078

}

1078

}

1079

1080

static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,

1080

static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,

1081

enum pipe pipe)

1081

enum pipe pipe)

1082

{

1082

{

1083

int reg;

1083

int reg;

1084

u32 val;

1084

u32 val;

1085

1086

assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);

1086

assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);

1087

assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);

1087

assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);

1088

assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);

1088

assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);

1089

1090

reg = PCH_ADPA;

1090

reg = PCH_ADPA;

1091

val = I915_READ(reg);

1091

val = I915_READ(reg);

1092

WARN(adpa_pipe_enabled(dev_priv, val, pipe),

1092

WARN(adpa_pipe_enabled(dev_priv, val, pipe),

1093

"PCH VGA enabled on transcoder %c, should be disabled\n",

1093

"PCH VGA enabled on transcoder %c, should be disabled\n",

1094

pipe_name(pipe));

1094

pipe_name(pipe));

1095

1096

reg = PCH_LVDS;

1096

reg = PCH_LVDS;

1097

val = I915_READ(reg);

1097

val = I915_READ(reg);

1098

WARN(lvds_pipe_enabled(dev_priv, val, pipe),

1098

WARN(lvds_pipe_enabled(dev_priv, val, pipe),

1099

"PCH LVDS enabled on transcoder %c, should be disabled\n",

1099

"PCH LVDS enabled on transcoder %c, should be disabled\n",

1100

pipe_name(pipe));

1100

pipe_name(pipe));

1101

1102

assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);

1102

assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);

1103

assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);

1103

assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);

1104

assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);

1104

assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);

1105

}

1105

}

1106

1107

/**

1107

/**

1108

* intel_enable_pll - enable a PLL

1108

* intel_enable_pll - enable a PLL

1109

* @dev_priv: i915 private structure

1109

* @dev_priv: i915 private structure

1110

* @pipe: pipe PLL to enable

1110

* @pipe: pipe PLL to enable

1111

*

1111

*

1112

* Enable @pipe's PLL so we can start pumping pixels from a plane. Check to

1112

* Enable @pipe's PLL so we can start pumping pixels from a plane. Check to

1113

* make sure the PLL reg is writable first though, since the panel write

1113

* make sure the PLL reg is writable first though, since the panel write

1114

* protect mechanism may be enabled.

1114

* protect mechanism may be enabled.

1115

*

1115

*

1116

* Note! This is for pre-ILK only.

1116

* Note! This is for pre-ILK only.

1117

*/

1117

*/

1118

static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)

1118

static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)

1119

{

1119

{

1120

int reg;

1120

int reg;

1121

u32 val;

1121

u32 val;

1122

1123

/* No really, not for ILK+ */

1123

/* No really, not for ILK+ */

1124

BUG_ON(dev_priv->info->gen >= 5);

1124

BUG_ON(dev_priv->info->gen >= 5);

1125

1126

/* PLL is protected by panel, make sure we can write it */

1126

/* PLL is protected by panel, make sure we can write it */

1127

if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))

1127

if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))

1128

assert_panel_unlocked(dev_priv, pipe);

1128

assert_panel_unlocked(dev_priv, pipe);

1129

1130

reg = DPLL(pipe);

1130

reg = DPLL(pipe);

1131

val = I915_READ(reg);

1131

val = I915_READ(reg);

1132

val |= DPLL_VCO_ENABLE;

1132

val |= DPLL_VCO_ENABLE;

1133

1134

/* We do this three times for luck */

1134

/* We do this three times for luck */

1135

I915_WRITE(reg, val);

1135

I915_WRITE(reg, val);

1136

POSTING_READ(reg);

1136

POSTING_READ(reg);

1137

udelay(150); /* wait for warmup */

1137

udelay(150); /* wait for warmup */

1138

I915_WRITE(reg, val);

1138

I915_WRITE(reg, val);

1139

POSTING_READ(reg);

1139

POSTING_READ(reg);

1140

udelay(150); /* wait for warmup */

1140

udelay(150); /* wait for warmup */

1141

I915_WRITE(reg, val);

1141

I915_WRITE(reg, val);

1142

POSTING_READ(reg);

1142

POSTING_READ(reg);

1143

udelay(150); /* wait for warmup */

1143

udelay(150); /* wait for warmup */

1144

}

1144

}

1145

1146

/**

1146

/**

1147

* intel_disable_pll - disable a PLL

1147

* intel_disable_pll - disable a PLL

1148

* @dev_priv: i915 private structure

1148

* @dev_priv: i915 private structure

1149

* @pipe: pipe PLL to disable

1149

* @pipe: pipe PLL to disable

1150

*

1150

*

1151

* Disable the PLL for @pipe, making sure the pipe is off first.

1151

* Disable the PLL for @pipe, making sure the pipe is off first.

1152

*

1152

*

1153

* Note! This is for pre-ILK only.

1153

* Note! This is for pre-ILK only.

1154

*/

1154

*/

1155

static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)

1155

static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)

1156

{

1156

{

1157

int reg;

1157

int reg;

1158

u32 val;

1158

u32 val;

1159

1160

/* Don't disable pipe A or pipe A PLLs if needed */

1160

/* Don't disable pipe A or pipe A PLLs if needed */

1161

if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))

1161

if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))

1162

return;

1162

return;

1163

1164

/* Make sure the pipe isn't still relying on us */

1164

/* Make sure the pipe isn't still relying on us */

1165

assert_pipe_disabled(dev_priv, pipe);

1165

assert_pipe_disabled(dev_priv, pipe);

1166

1167

reg = DPLL(pipe);

1167

reg = DPLL(pipe);

1168

val = I915_READ(reg);

1168

val = I915_READ(reg);

1169

val &= ~DPLL_VCO_ENABLE;

1169

val &= ~DPLL_VCO_ENABLE;

1170

I915_WRITE(reg, val);

1170

I915_WRITE(reg, val);

1171

POSTING_READ(reg);

1171

POSTING_READ(reg);

1172

}

1172

}

1173

1174

/**

1174

/**

1175

* intel_enable_pch_pll - enable PCH PLL

1175

* intel_enable_pch_pll - enable PCH PLL

1176

* @dev_priv: i915 private structure

1176

* @dev_priv: i915 private structure

1177

* @pipe: pipe PLL to enable

1177

* @pipe: pipe PLL to enable

1178

*

1178

*

1179

* The PCH PLL needs to be enabled before the PCH transcoder, since it

1179

* The PCH PLL needs to be enabled before the PCH transcoder, since it

1180

* drives the transcoder clock.

1180

* drives the transcoder clock.

1181

*/

1181

*/

1182

static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,

1182

static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,

1183

enum pipe pipe)

1183

enum pipe pipe)

1184

{

1184

{

1185

int reg;

1185

int reg;

1186

u32 val;

1186

u32 val;

1187

1188

if (pipe > 1)

1188

if (pipe > 1)

1189

return;

1189

return;

1190

1191

/* PCH only available on ILK+ */

1191

/* PCH only available on ILK+ */

1192

BUG_ON(dev_priv->info->gen < 5);

1192

BUG_ON(dev_priv->info->gen < 5);

1193

1194

/* PCH refclock must be enabled first */

1194

/* PCH refclock must be enabled first */

1195

assert_pch_refclk_enabled(dev_priv);

1195

assert_pch_refclk_enabled(dev_priv);

1196

1197

reg = PCH_DPLL(pipe);

1197

reg = PCH_DPLL(pipe);

1198

val = I915_READ(reg);

1198

val = I915_READ(reg);

1199

val |= DPLL_VCO_ENABLE;

1199

val |= DPLL_VCO_ENABLE;

1200

I915_WRITE(reg, val);

1200

I915_WRITE(reg, val);

1201

POSTING_READ(reg);

1201

POSTING_READ(reg);

1202

udelay(200);

1202

udelay(200);

1203

}

1203

}

1204

1205

static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,

1205

static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,

1206

enum pipe pipe)

1206

enum pipe pipe)

1207

{

1207

{

1208

int reg;

1208

int reg;

1209

u32 val;

1209

u32 val;

1210

1211

if (pipe > 1)

1211

if (pipe > 1)

1212

return;

1212

return;

1213

1214

/* PCH only available on ILK+ */

1214

/* PCH only available on ILK+ */

1215

BUG_ON(dev_priv->info->gen < 5);

1215

BUG_ON(dev_priv->info->gen < 5);

1216

1217

/* Make sure transcoder isn't still depending on us */

1217

/* Make sure transcoder isn't still depending on us */

1218

assert_transcoder_disabled(dev_priv, pipe);

1218

assert_transcoder_disabled(dev_priv, pipe);

1219

1220

reg = PCH_DPLL(pipe);

1220

reg = PCH_DPLL(pipe);

1221

val = I915_READ(reg);

1221

val = I915_READ(reg);

1222

val &= ~DPLL_VCO_ENABLE;

1222

val &= ~DPLL_VCO_ENABLE;

1223

I915_WRITE(reg, val);

1223

I915_WRITE(reg, val);

1224

POSTING_READ(reg);

1224

POSTING_READ(reg);

1225

udelay(200);

1225

udelay(200);

1226

}

1226

}

1227

1228

static void intel_enable_transcoder(struct drm_i915_private *dev_priv,

1228

static void intel_enable_transcoder(struct drm_i915_private *dev_priv,

1229

enum pipe pipe)

1229

enum pipe pipe)

1230

{

1230

{

1231

int reg;

1231

int reg;

1232

u32 val;

1232

u32 val;

1233

1234

/* PCH only available on ILK+ */

1234

/* PCH only available on ILK+ */

1235

BUG_ON(dev_priv->info->gen < 5);

1235

BUG_ON(dev_priv->info->gen < 5);

1236

1237

/* Make sure PCH DPLL is enabled */

1237

/* Make sure PCH DPLL is enabled */

1238

assert_pch_pll_enabled(dev_priv, pipe);

1238

assert_pch_pll_enabled(dev_priv, pipe);

1239

1240

/* FDI must be feeding us bits for PCH ports */

1240

/* FDI must be feeding us bits for PCH ports */

1241

assert_fdi_tx_enabled(dev_priv, pipe);

1241

assert_fdi_tx_enabled(dev_priv, pipe);

1242

assert_fdi_rx_enabled(dev_priv, pipe);

1242

assert_fdi_rx_enabled(dev_priv, pipe);

1243

1244

reg = TRANSCONF(pipe);

1244

reg = TRANSCONF(pipe);

1245

val = I915_READ(reg);

1245

val = I915_READ(reg);

1246

1247

if (HAS_PCH_IBX(dev_priv->dev)) {

1247

if (HAS_PCH_IBX(dev_priv->dev)) {

1248

/*

1248

/*

1249

* make the BPC in transcoder be consistent with

1249

* make the BPC in transcoder be consistent with

1250

* that in pipeconf reg.

1250

* that in pipeconf reg.

1251

*/

1251

*/

1252

val &= ~PIPE_BPC_MASK;

1252

val &= ~PIPE_BPC_MASK;

1253

val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;

1253

val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;

1254

}

1254

}

1255

I915_WRITE(reg, val | TRANS_ENABLE);

1255

I915_WRITE(reg, val | TRANS_ENABLE);

1256

if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))

1256

if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))

1257

DRM_ERROR("failed to enable transcoder %d\n", pipe);

1257

DRM_ERROR("failed to enable transcoder %d\n", pipe);

1258

}

1258

}

1259

1260

static void intel_disable_transcoder(struct drm_i915_private *dev_priv,

1260

static void intel_disable_transcoder(struct drm_i915_private *dev_priv,

1261

enum pipe pipe)

1261

enum pipe pipe)

1262

{

1262

{

1263

int reg;

1263

int reg;

1264

u32 val;

1264

u32 val;

1265

1266

/* FDI relies on the transcoder */

1266

/* FDI relies on the transcoder */

1267

assert_fdi_tx_disabled(dev_priv, pipe);

1267

assert_fdi_tx_disabled(dev_priv, pipe);

1268

assert_fdi_rx_disabled(dev_priv, pipe);

1268

assert_fdi_rx_disabled(dev_priv, pipe);

1269

1270

/* Ports must be off as well */

1270

/* Ports must be off as well */

1271

assert_pch_ports_disabled(dev_priv, pipe);

1271

assert_pch_ports_disabled(dev_priv, pipe);

1272

1273

reg = TRANSCONF(pipe);

1273

reg = TRANSCONF(pipe);

1274

val = I915_READ(reg);

1274

val = I915_READ(reg);

1275

val &= ~TRANS_ENABLE;

1275

val &= ~TRANS_ENABLE;

1276

I915_WRITE(reg, val);

1276

I915_WRITE(reg, val);

1277

/* wait for PCH transcoder off, transcoder state */

1277

/* wait for PCH transcoder off, transcoder state */

1278

if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))

1278

if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))

1279

DRM_ERROR("failed to disable transcoder %d\n", pipe);

1279

DRM_ERROR("failed to disable transcoder %d\n", pipe);

1280

}

1280

}

1281

1282

/**

1282

/**

1283

* intel_enable_pipe - enable a pipe, asserting requirements

1283

* intel_enable_pipe - enable a pipe, asserting requirements

1284

* @dev_priv: i915 private structure

1284

* @dev_priv: i915 private structure

1285

* @pipe: pipe to enable

1285

* @pipe: pipe to enable

1286

* @pch_port: on ILK+, is this pipe driving a PCH port or not

1286

* @pch_port: on ILK+, is this pipe driving a PCH port or not

1287

*

1287

*

1288

* Enable @pipe, making sure that various hardware specific requirements

1288

* Enable @pipe, making sure that various hardware specific requirements

1289

* are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.

1289

* are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.

1290

*

1290

*

1291

* @pipe should be %PIPE_A or %PIPE_B.

1291

* @pipe should be %PIPE_A or %PIPE_B.

1292

*

1292

*

1293

* Will wait until the pipe is actually running (i.e. first vblank) before

1293

* Will wait until the pipe is actually running (i.e. first vblank) before

1294

* returning.

1294

* returning.

1295

*/

1295

*/

1296

static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,

1296

static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,

1297

bool pch_port)

1297

bool pch_port)

1298

{

1298

{

1299

int reg;

1299

int reg;

1300

u32 val;

1300

u32 val;

1301

1302

/*

1302

/*

1303

* A pipe without a PLL won't actually be able to drive bits from

1303

* A pipe without a PLL won't actually be able to drive bits from

1304

* a plane. On ILK+ the pipe PLLs are integrated, so we don't

1304

* a plane. On ILK+ the pipe PLLs are integrated, so we don't

1305

* need the check.

1305

* need the check.

1306

*/

1306

*/

1307

if (!HAS_PCH_SPLIT(dev_priv->dev))

1307

if (!HAS_PCH_SPLIT(dev_priv->dev))

1308

assert_pll_enabled(dev_priv, pipe);

1308

assert_pll_enabled(dev_priv, pipe);

1309

else {

1309

else {

1310

if (pch_port) {

1310

if (pch_port) {

1311

/* if driving the PCH, we need FDI enabled */

1311

/* if driving the PCH, we need FDI enabled */

1312

assert_fdi_rx_pll_enabled(dev_priv, pipe);

1312

assert_fdi_rx_pll_enabled(dev_priv, pipe);

1313

assert_fdi_tx_pll_enabled(dev_priv, pipe);

1313

assert_fdi_tx_pll_enabled(dev_priv, pipe);

1314

}

1314

}

1315

/* FIXME: assert CPU port conditions for SNB+ */

1315

/* FIXME: assert CPU port conditions for SNB+ */

1316

}

1316

}

1317

1318

reg = PIPECONF(pipe);

1318

reg = PIPECONF(pipe);

1319

val = I915_READ(reg);

1319

val = I915_READ(reg);

1320

if (val & PIPECONF_ENABLE)

1320

if (val & PIPECONF_ENABLE)

1321

return;

1321

return;

1322

1323

I915_WRITE(reg, val | PIPECONF_ENABLE);

1323

I915_WRITE(reg, val | PIPECONF_ENABLE);

1324

intel_wait_for_vblank(dev_priv->dev, pipe);

1324

intel_wait_for_vblank(dev_priv->dev, pipe);

1325

}

1325

}

1326

1327

/**

1327

/**

1328

* intel_disable_pipe - disable a pipe, asserting requirements

1328

* intel_disable_pipe - disable a pipe, asserting requirements

1329

* @dev_priv: i915 private structure

1329

* @dev_priv: i915 private structure

1330

* @pipe: pipe to disable

1330

* @pipe: pipe to disable

1331

*

1331

*

1332

* Disable @pipe, making sure that various hardware specific requirements

1332

* Disable @pipe, making sure that various hardware specific requirements

1333

* are met, if applicable, e.g. plane disabled, panel fitter off, etc.

1333

* are met, if applicable, e.g. plane disabled, panel fitter off, etc.

1334

*

1334

*

1335

* @pipe should be %PIPE_A or %PIPE_B.

1335

* @pipe should be %PIPE_A or %PIPE_B.

1336

*

1336

*

1337

* Will wait until the pipe has shut down before returning.

1337

* Will wait until the pipe has shut down before returning.

1338

*/

1338

*/

1339

static void intel_disable_pipe(struct drm_i915_private *dev_priv,

1339

static void intel_disable_pipe(struct drm_i915_private *dev_priv,

1340

enum pipe pipe)

1340

enum pipe pipe)

1341

{

1341

{

1342

int reg;

1342

int reg;

1343

u32 val;

1343

u32 val;

1344

1345

/*

1345

/*

1346

* Make sure planes won't keep trying to pump pixels to us,

1346

* Make sure planes won't keep trying to pump pixels to us,

1347

* or we might hang the display.

1347

* or we might hang the display.

1348

*/

1348

*/

1349

assert_planes_disabled(dev_priv, pipe);

1349

assert_planes_disabled(dev_priv, pipe);

1350

1351

/* Don't disable pipe A or pipe A PLLs if needed */

1351

/* Don't disable pipe A or pipe A PLLs if needed */

1352

if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))

1352

if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))

1353

return;

1353

return;

1354

1355

reg = PIPECONF(pipe);

1355

reg = PIPECONF(pipe);

1356

val = I915_READ(reg);

1356

val = I915_READ(reg);

1357

if ((val & PIPECONF_ENABLE) == 0)

1357

if ((val & PIPECONF_ENABLE) == 0)

1358

return;

1358

return;

1359

1360

I915_WRITE(reg, val & ~PIPECONF_ENABLE);

1360

I915_WRITE(reg, val & ~PIPECONF_ENABLE);

1361

intel_wait_for_pipe_off(dev_priv->dev, pipe);

1361

intel_wait_for_pipe_off(dev_priv->dev, pipe);

1362

}

1362

}

1363

1364

/*

1364

/*

1365

* Plane regs are double buffered, going from enabled->disabled needs a

1365

* Plane regs are double buffered, going from enabled->disabled needs a

1366

* trigger in order to latch. The display address reg provides this.

1366

* trigger in order to latch. The display address reg provides this.

1367

*/

1367

*/

1368

static void intel_flush_display_plane(struct drm_i915_private *dev_priv,

1368

static void intel_flush_display_plane(struct drm_i915_private *dev_priv,

1369

enum plane plane)

1369

enum plane plane)

1370

{

1370

{

1371

I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));

1371

I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));

1372

I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));

1372

I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));

1373

}

1373

}

1374

1375

/**

1375

/**

1376

* intel_enable_plane - enable a display plane on a given pipe

1376

* intel_enable_plane - enable a display plane on a given pipe

1377

* @dev_priv: i915 private structure

1377

* @dev_priv: i915 private structure

1378

* @plane: plane to enable

1378

* @plane: plane to enable

1379

* @pipe: pipe being fed

1379

* @pipe: pipe being fed

1380

*

1380

*

1381

* Enable @plane on @pipe, making sure that @pipe is running first.

1381

* Enable @plane on @pipe, making sure that @pipe is running first.

1382

*/

1382

*/

1383

static void intel_enable_plane(struct drm_i915_private *dev_priv,

1383

static void intel_enable_plane(struct drm_i915_private *dev_priv,

1384

enum plane plane, enum pipe pipe)

1384

enum plane plane, enum pipe pipe)

1385

{

1385

{

1386

int reg;

1386

int reg;

1387

u32 val;

1387

u32 val;

1388

1389

/* If the pipe isn't enabled, we can't pump pixels and may hang */

1389

/* If the pipe isn't enabled, we can't pump pixels and may hang */

1390

assert_pipe_enabled(dev_priv, pipe);

1390

assert_pipe_enabled(dev_priv, pipe);

1391

1392

reg = DSPCNTR(plane);

1392

reg = DSPCNTR(plane);

1393

val = I915_READ(reg);

1393

val = I915_READ(reg);

1394

if (val & DISPLAY_PLANE_ENABLE)

1394

if (val & DISPLAY_PLANE_ENABLE)

1395

return;

1395

return;

1396

1397

I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);

1397

I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);

1398

intel_flush_display_plane(dev_priv, plane);

1398

intel_flush_display_plane(dev_priv, plane);

1399

intel_wait_for_vblank(dev_priv->dev, pipe);

1399

intel_wait_for_vblank(dev_priv->dev, pipe);

1400

}

1400

}

1401

1402

/**

1402

/**

1403

* intel_disable_plane - disable a display plane

1403

* intel_disable_plane - disable a display plane

1404

* @dev_priv: i915 private structure

1404

* @dev_priv: i915 private structure

1405

* @plane: plane to disable

1405

* @plane: plane to disable

1406

* @pipe: pipe consuming the data

1406

* @pipe: pipe consuming the data

1407

*

1407

*

1408

* Disable @plane; should be an independent operation.

1408

* Disable @plane; should be an independent operation.

1409

*/

1409

*/

1410

static void intel_disable_plane(struct drm_i915_private *dev_priv,

1410

static void intel_disable_plane(struct drm_i915_private *dev_priv,

1411

enum plane plane, enum pipe pipe)

1411

enum plane plane, enum pipe pipe)

1412

{

1412

{

1413

int reg;

1413

int reg;

1414

u32 val;

1414

u32 val;

1415

1416

reg = DSPCNTR(plane);

1416

reg = DSPCNTR(plane);

1417

val = I915_READ(reg);

1417

val = I915_READ(reg);

1418

if ((val & DISPLAY_PLANE_ENABLE) == 0)

1418

if ((val & DISPLAY_PLANE_ENABLE) == 0)

1419

return;

1419

return;

1420

1421

I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);

1421

I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);

1422

intel_flush_display_plane(dev_priv, plane);

1422

intel_flush_display_plane(dev_priv, plane);

1423

intel_wait_for_vblank(dev_priv->dev, pipe);

1423

intel_wait_for_vblank(dev_priv->dev, pipe);

1424

}

1424

}

1425

1426

static void disable_pch_dp(struct drm_i915_private *dev_priv,

1426

static void disable_pch_dp(struct drm_i915_private *dev_priv,

1427

enum pipe pipe, int reg, u32 port_sel)

1427

enum pipe pipe, int reg, u32 port_sel)

1428

{

1428

{

1429

u32 val = I915_READ(reg);

1429

u32 val = I915_READ(reg);

1430

if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {

1430

if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {

1431

DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);

1431

DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);

1432

I915_WRITE(reg, val & ~DP_PORT_EN);

1432

I915_WRITE(reg, val & ~DP_PORT_EN);

1433

}

1433

}

1434

}

1434

}

1435

1436

static void disable_pch_hdmi(struct drm_i915_private *dev_priv,

1436

static void disable_pch_hdmi(struct drm_i915_private *dev_priv,

1437

enum pipe pipe, int reg)

1437

enum pipe pipe, int reg)

1438

{

1438

{

1439

u32 val = I915_READ(reg);

1439

u32 val = I915_READ(reg);

1440

if (hdmi_pipe_enabled(dev_priv, val, pipe)) {

1440

if (hdmi_pipe_enabled(dev_priv, val, pipe)) {

1441

DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",

1441

DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",

1442

reg, pipe);

1442

reg, pipe);

1443

I915_WRITE(reg, val & ~PORT_ENABLE);

1443

I915_WRITE(reg, val & ~PORT_ENABLE);

1444

}

1444

}

1445

}

1445

}

1446

1447

/* Disable any ports connected to this transcoder */

1447

/* Disable any ports connected to this transcoder */

1448

static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,

1448

static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,

1449

enum pipe pipe)

1449

enum pipe pipe)

1450

{

1450

{

1451

u32 reg, val;

1451

u32 reg, val;

1452

1453

val = I915_READ(PCH_PP_CONTROL);

1453

val = I915_READ(PCH_PP_CONTROL);

1454

I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);

1454

I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);

1455

1456

disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);

1456

disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);

1457

disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);

1457

disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);

1458

disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);

1458

disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);

1459

1460

reg = PCH_ADPA;

1460

reg = PCH_ADPA;

1461

val = I915_READ(reg);

1461

val = I915_READ(reg);

1462

if (adpa_pipe_enabled(dev_priv, val, pipe))

1462

if (adpa_pipe_enabled(dev_priv, val, pipe))

1463

I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);

1463

I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);

1464

1465

reg = PCH_LVDS;

1465

reg = PCH_LVDS;

1466

val = I915_READ(reg);

1466

val = I915_READ(reg);

1467

if (lvds_pipe_enabled(dev_priv, val, pipe)) {

1467

if (lvds_pipe_enabled(dev_priv, val, pipe)) {

1468

DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);

1468

DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);

1469

I915_WRITE(reg, val & ~LVDS_PORT_EN);

1469

I915_WRITE(reg, val & ~LVDS_PORT_EN);

1470

POSTING_READ(reg);

1470

POSTING_READ(reg);

1471

udelay(100);

1471

udelay(100);

1472

}

1472

}

1473

1474

disable_pch_hdmi(dev_priv, pipe, HDMIB);

1474

disable_pch_hdmi(dev_priv, pipe, HDMIB);

1475

disable_pch_hdmi(dev_priv, pipe, HDMIC);

1475

disable_pch_hdmi(dev_priv, pipe, HDMIC);

1476

disable_pch_hdmi(dev_priv, pipe, HDMID);

1476

disable_pch_hdmi(dev_priv, pipe, HDMID);

1477

}

1477

}

1478

1479

static void i8xx_disable_fbc(struct drm_device *dev)

1479

static void i8xx_disable_fbc(struct drm_device *dev)

1480

{

1480

{

1481

struct drm_i915_private *dev_priv = dev->dev_private;

1481

struct drm_i915_private *dev_priv = dev->dev_private;

1482

u32 fbc_ctl;

1482

u32 fbc_ctl;

1483

1484

/* Disable compression */

1484

/* Disable compression */

1485

fbc_ctl = I915_READ(FBC_CONTROL);

1485

fbc_ctl = I915_READ(FBC_CONTROL);

1486

if ((fbc_ctl & FBC_CTL_EN) == 0)

1486

if ((fbc_ctl & FBC_CTL_EN) == 0)

1487

return;

1487

return;

1488

1489

fbc_ctl &= ~FBC_CTL_EN;

1489

fbc_ctl &= ~FBC_CTL_EN;

1490

I915_WRITE(FBC_CONTROL, fbc_ctl);

1490

I915_WRITE(FBC_CONTROL, fbc_ctl);

1491

1492

/* Wait for compressing bit to clear */

1492

/* Wait for compressing bit to clear */

1493

if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {

1493

if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {

1494

DRM_DEBUG_KMS("FBC idle timed out\n");

1494

DRM_DEBUG_KMS("FBC idle timed out\n");

1495

return;

1495

return;

1496

}

1496

}

1497

1498

DRM_DEBUG_KMS("disabled FBC\n");

1498

DRM_DEBUG_KMS("disabled FBC\n");

1499

}

1499

}

1500

1501

static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)

1501

static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)

1502

{

1502

{

1503

struct drm_device *dev = crtc->dev;

1503

struct drm_device *dev = crtc->dev;

1504

struct drm_i915_private *dev_priv = dev->dev_private;

1504

struct drm_i915_private *dev_priv = dev->dev_private;

1505

struct drm_framebuffer *fb = crtc->fb;

1505

struct drm_framebuffer *fb = crtc->fb;

1506

struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);

1506

struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);

1507

struct drm_i915_gem_object *obj = intel_fb->obj;

1507

struct drm_i915_gem_object *obj = intel_fb->obj;

1508

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

1508

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

1509

int cfb_pitch;

1509

int cfb_pitch;

1510

int plane, i;

1510

int plane, i;

1511

u32 fbc_ctl, fbc_ctl2;

1511

u32 fbc_ctl, fbc_ctl2;

1512

1513

cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;

1513

cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;

1514

if (fb->pitch < cfb_pitch)

1514

if (fb->pitch < cfb_pitch)

1515

cfb_pitch = fb->pitch;

1515

cfb_pitch = fb->pitch;

1516

1517

/* FBC_CTL wants 64B units */

1517

/* FBC_CTL wants 64B units */

1518

cfb_pitch = (cfb_pitch / 64) - 1;

1518

cfb_pitch = (cfb_pitch / 64) - 1;

1519

plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;

1519

plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;

1520

1521

/* Clear old tags */

1521

/* Clear old tags */

1522

for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)

1522

for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)

1523

I915_WRITE(FBC_TAG + (i * 4), 0);

1523

I915_WRITE(FBC_TAG + (i * 4), 0);

1524

1525

/* Set it up... */

1525

/* Set it up... */

1526

fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;

1526

fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;

1527

fbc_ctl2 |= plane;

1527

fbc_ctl2 |= plane;

1528

I915_WRITE(FBC_CONTROL2, fbc_ctl2);

1528

I915_WRITE(FBC_CONTROL2, fbc_ctl2);

1529

I915_WRITE(FBC_FENCE_OFF, crtc->y);

1529

I915_WRITE(FBC_FENCE_OFF, crtc->y);

1530

1531

/* enable it... */

1531

/* enable it... */

1532

fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;

1532

fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;

1533

if (IS_I945GM(dev))

1533

if (IS_I945GM(dev))

1534

fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */

1534

fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */

1535

fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;

1535

fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;

1536

fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;

1536

fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;

1537

fbc_ctl |= obj->fence_reg;

1537

fbc_ctl |= obj->fence_reg;

1538

I915_WRITE(FBC_CONTROL, fbc_ctl);

1538

I915_WRITE(FBC_CONTROL, fbc_ctl);

1539

1540

DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",

1540

DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",

1541

cfb_pitch, crtc->y, intel_crtc->plane);

1541

cfb_pitch, crtc->y, intel_crtc->plane);

1542

}

1542

}

1543

1544

static bool i8xx_fbc_enabled(struct drm_device *dev)

1544

static bool i8xx_fbc_enabled(struct drm_device *dev)

1545

{

1545

{

1546

struct drm_i915_private *dev_priv = dev->dev_private;

1546

struct drm_i915_private *dev_priv = dev->dev_private;

1547

1548

return I915_READ(FBC_CONTROL) & FBC_CTL_EN;

1548

return I915_READ(FBC_CONTROL) & FBC_CTL_EN;

1549

}

1549

}

1550

1551

static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)

1551

static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)

1552

{

1552

{

1553

struct drm_device *dev = crtc->dev;

1553

struct drm_device *dev = crtc->dev;

1554

struct drm_i915_private *dev_priv = dev->dev_private;

1554

struct drm_i915_private *dev_priv = dev->dev_private;

1555

struct drm_framebuffer *fb = crtc->fb;

1555

struct drm_framebuffer *fb = crtc->fb;

1556

struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);

1556

struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);

1557

struct drm_i915_gem_object *obj = intel_fb->obj;

1557

struct drm_i915_gem_object *obj = intel_fb->obj;

1558

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

1558

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

1559

int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;

1559

int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;

1560

unsigned long stall_watermark = 200;

1560

unsigned long stall_watermark = 200;

1561

u32 dpfc_ctl;

1561

u32 dpfc_ctl;

1562

1563

dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;

1563

dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;

1564

dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;

1564

dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;

1565

I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);

1565

I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);

1566

1567

I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |

1567

I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |

1568

(stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |

1568

(stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |

1569

(interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));

1569

(interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));

1570

I915_WRITE(DPFC_FENCE_YOFF, crtc->y);

1570

I915_WRITE(DPFC_FENCE_YOFF, crtc->y);

1571

1572

/* enable it... */

1572

/* enable it... */

1573

I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);

1573

I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);

1574

1575

DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);

1575

DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);

1576

}

1576

}

1577

1578

static void g4x_disable_fbc(struct drm_device *dev)

1578

static void g4x_disable_fbc(struct drm_device *dev)

1579

{

1579

{

1580

struct drm_i915_private *dev_priv = dev->dev_private;

1580

struct drm_i915_private *dev_priv = dev->dev_private;

1581

u32 dpfc_ctl;

1581

u32 dpfc_ctl;

1582

1583

/* Disable compression */

1583

/* Disable compression */

1584

dpfc_ctl = I915_READ(DPFC_CONTROL);

1584

dpfc_ctl = I915_READ(DPFC_CONTROL);

1585

if (dpfc_ctl & DPFC_CTL_EN) {

1585

if (dpfc_ctl & DPFC_CTL_EN) {

1586

dpfc_ctl &= ~DPFC_CTL_EN;

1586

dpfc_ctl &= ~DPFC_CTL_EN;

1587

I915_WRITE(DPFC_CONTROL, dpfc_ctl);

1587

I915_WRITE(DPFC_CONTROL, dpfc_ctl);

1588

1589

DRM_DEBUG_KMS("disabled FBC\n");

1589

DRM_DEBUG_KMS("disabled FBC\n");

1590

}

1590

}

1591

}

1591

}

1592

1593

static bool g4x_fbc_enabled(struct drm_device *dev)

1593

static bool g4x_fbc_enabled(struct drm_device *dev)

1594

{

1594

{

1595

struct drm_i915_private *dev_priv = dev->dev_private;

1595

struct drm_i915_private *dev_priv = dev->dev_private;

1596

1597

return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;

1597

return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;

1598

}

1598

}

1599

1600

static void sandybridge_blit_fbc_update(struct drm_device *dev)

1600

static void sandybridge_blit_fbc_update(struct drm_device *dev)

1601

{

1601

{

1602

struct drm_i915_private *dev_priv = dev->dev_private;

1602

struct drm_i915_private *dev_priv = dev->dev_private;

1603

u32 blt_ecoskpd;

1603

u32 blt_ecoskpd;

1604

1605

/* Make sure blitter notifies FBC of writes */

1605

/* Make sure blitter notifies FBC of writes */

1606

gen6_gt_force_wake_get(dev_priv);

1606

gen6_gt_force_wake_get(dev_priv);

1607

blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);

1607

blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);

1608

blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<

1608

blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<

1609

GEN6_BLITTER_LOCK_SHIFT;

1609

GEN6_BLITTER_LOCK_SHIFT;

1610

I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);

1610

I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);

1611

blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;

1611

blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;

1612

I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);

1612

I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);

1613

blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<

1613

blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<

1614

GEN6_BLITTER_LOCK_SHIFT);

1614

GEN6_BLITTER_LOCK_SHIFT);

1615

I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);

1615

I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);

1616

POSTING_READ(GEN6_BLITTER_ECOSKPD);

1616

POSTING_READ(GEN6_BLITTER_ECOSKPD);

1617

gen6_gt_force_wake_put(dev_priv);

1617

gen6_gt_force_wake_put(dev_priv);

1618

}

1618

}

1619

1620

static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)

1620

static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)

1621

{

1621

{

1622

struct drm_device *dev = crtc->dev;

1622

struct drm_device *dev = crtc->dev;

1623

struct drm_i915_private *dev_priv = dev->dev_private;

1623

struct drm_i915_private *dev_priv = dev->dev_private;

1624

struct drm_framebuffer *fb = crtc->fb;

1624

struct drm_framebuffer *fb = crtc->fb;

1625

struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);

1625

struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);

1626

struct drm_i915_gem_object *obj = intel_fb->obj;

1626

struct drm_i915_gem_object *obj = intel_fb->obj;

1627

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

1627

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

1628

int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;

1628

int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;

1629

unsigned long stall_watermark = 200;

1629

unsigned long stall_watermark = 200;

1630

u32 dpfc_ctl;

1630

u32 dpfc_ctl;

1631

1632

dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);

1632

dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);

1633

dpfc_ctl &= DPFC_RESERVED;

1633

dpfc_ctl &= DPFC_RESERVED;

1634

dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);

1634

dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);

1635

/* Set persistent mode for front-buffer rendering, ala X. */

1635

/* Set persistent mode for front-buffer rendering, ala X. */

1636

dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;

1636

dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;

1637

dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);

1637

dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);

1638

I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);

1638

I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);

1639

1640

I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |

1640

I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |

1641

(stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |

1641

(stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |

1642

(interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));

1642

(interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));

1643

I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);

1643

I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);

1644

I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);

1644

I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);

1645

/* enable it... */

1645

/* enable it... */

1646

I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);

1646

I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);

1647

1648

if (IS_GEN6(dev)) {

1648

if (IS_GEN6(dev)) {

1649

I915_WRITE(SNB_DPFC_CTL_SA,

1649

I915_WRITE(SNB_DPFC_CTL_SA,

1650

SNB_CPU_FENCE_ENABLE | obj->fence_reg);

1650

SNB_CPU_FENCE_ENABLE | obj->fence_reg);

1651

I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);

1651

I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);

1652

sandybridge_blit_fbc_update(dev);

1652

sandybridge_blit_fbc_update(dev);

1653

}

1653

}

1654

1655

DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);

1655

DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);

1656

}

1656

}

1657

1658

static void ironlake_disable_fbc(struct drm_device *dev)

1658

static void ironlake_disable_fbc(struct drm_device *dev)

1659

{

1659

{

1660

struct drm_i915_private *dev_priv = dev->dev_private;

1660

struct drm_i915_private *dev_priv = dev->dev_private;

1661

u32 dpfc_ctl;

1661

u32 dpfc_ctl;

1662

1663

/* Disable compression */

1663

/* Disable compression */

1664

dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);

1664

dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);

1665

if (dpfc_ctl & DPFC_CTL_EN) {

1665

if (dpfc_ctl & DPFC_CTL_EN) {

1666

dpfc_ctl &= ~DPFC_CTL_EN;

1666

dpfc_ctl &= ~DPFC_CTL_EN;

1667

I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);

1667

I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);

1668

1669

DRM_DEBUG_KMS("disabled FBC\n");

1669

DRM_DEBUG_KMS("disabled FBC\n");

1670

}

1670

}

1671

}

1671

}

1672

1673

static bool ironlake_fbc_enabled(struct drm_device *dev)

1673

static bool ironlake_fbc_enabled(struct drm_device *dev)

1674

{

1674

{

1675

struct drm_i915_private *dev_priv = dev->dev_private;

1675

struct drm_i915_private *dev_priv = dev->dev_private;

1676

1677

return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;

1677

return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;

1678

}

1678

}

1679

1680

bool intel_fbc_enabled(struct drm_device *dev)

1680

bool intel_fbc_enabled(struct drm_device *dev)

1681

{

1681

{

1682

struct drm_i915_private *dev_priv = dev->dev_private;

1682

struct drm_i915_private *dev_priv = dev->dev_private;

1683

1684

if (!dev_priv->display.fbc_enabled)

1684

if (!dev_priv->display.fbc_enabled)

1685

return false;

1685

return false;

1686

1687

return dev_priv->display.fbc_enabled(dev);

1687

return dev_priv->display.fbc_enabled(dev);

1688

}

1688

}

1689

1690

static void intel_fbc_work_fn(struct work_struct *__work)

1690

static void intel_fbc_work_fn(struct work_struct *__work)

1691

{

1691

{

1692

struct intel_fbc_work *work =

1692

struct intel_fbc_work *work =

1693

container_of(to_delayed_work(__work),

1693

container_of(to_delayed_work(__work),

1694

struct intel_fbc_work, work);

1694

struct intel_fbc_work, work);

1695

struct drm_device *dev = work->crtc->dev;

1695

struct drm_device *dev = work->crtc->dev;

1696

struct drm_i915_private *dev_priv = dev->dev_private;

1696

struct drm_i915_private *dev_priv = dev->dev_private;

1697

1698

mutex_lock(&dev->struct_mutex);

1698

mutex_lock(&dev->struct_mutex);

1699

if (work == dev_priv->fbc_work) {

1699

if (work == dev_priv->fbc_work) {

1700

/* Double check that we haven't switched fb without cancelling

1700

/* Double check that we haven't switched fb without cancelling

1701

* the prior work.

1701

* the prior work.

1702

*/

1702

*/

1703

if (work->crtc->fb == work->fb) {

1703

if (work->crtc->fb == work->fb) {

1704

dev_priv->display.enable_fbc(work->crtc,

1704

dev_priv->display.enable_fbc(work->crtc,

1705

work->interval);

1705

work->interval);

1706

1707

dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;

1707

dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;

1708

dev_priv->cfb_fb = work->crtc->fb->base.id;

1708

dev_priv->cfb_fb = work->crtc->fb->base.id;

1709

dev_priv->cfb_y = work->crtc->y;

1709

dev_priv->cfb_y = work->crtc->y;

1710

}

1710

}

1711

1712

dev_priv->fbc_work = NULL;

1712

dev_priv->fbc_work = NULL;

1713

}

1713

}

1714

mutex_unlock(&dev->struct_mutex);

1714

mutex_unlock(&dev->struct_mutex);

1715

1716

kfree(work);

1716

kfree(work);

1717

}

1717

}

1718

1719

static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)

1719

static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)

1720

{

1720

{

1721

if (dev_priv->fbc_work == NULL)

1721

if (dev_priv->fbc_work == NULL)

1722

return;

1722

return;

1723

1724

DRM_DEBUG_KMS("cancelling pending FBC enable\n");

1724

DRM_DEBUG_KMS("cancelling pending FBC enable\n");

1725

1726

/* Synchronisation is provided by struct_mutex and checking of

1726

/* Synchronisation is provided by struct_mutex and checking of

1727

* dev_priv->fbc_work, so we can perform the cancellation

1727

* dev_priv->fbc_work, so we can perform the cancellation

1728

* entirely asynchronously.

1728

* entirely asynchronously.

1729

*/

1729

*/

1730

if (cancel_delayed_work(&dev_priv->fbc_work->work))

1730

if (cancel_delayed_work(&dev_priv->fbc_work->work))

1731

/* tasklet was killed before being run, clean up */

1731

/* tasklet was killed before being run, clean up */

1732

kfree(dev_priv->fbc_work);

1732

kfree(dev_priv->fbc_work);

1733

1734

/* Mark the work as no longer wanted so that if it does

1734

/* Mark the work as no longer wanted so that if it does

1735

* wake-up (because the work was already running and waiting

1735

* wake-up (because the work was already running and waiting

1736

* for our mutex), it will discover that is no longer

1736

* for our mutex), it will discover that is no longer

1737

* necessary to run.

1737

* necessary to run.

1738

*/

1738

*/

1739

dev_priv->fbc_work = NULL;

1739

dev_priv->fbc_work = NULL;

1740

}

1740

}

1741

1742

static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)

1742

static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)

1743

{

1743

{

1744

struct intel_fbc_work *work;

1744

struct intel_fbc_work *work;

1745

struct drm_device *dev = crtc->dev;

1745

struct drm_device *dev = crtc->dev;

1746

struct drm_i915_private *dev_priv = dev->dev_private;

1746

struct drm_i915_private *dev_priv = dev->dev_private;

1747

1748

if (!dev_priv->display.enable_fbc)

1748

if (!dev_priv->display.enable_fbc)

1749

return;

1749

return;

1750

1751

intel_cancel_fbc_work(dev_priv);

1751

intel_cancel_fbc_work(dev_priv);

1752

1753

work = kzalloc(sizeof *work, GFP_KERNEL);

1753

work = kzalloc(sizeof *work, GFP_KERNEL);

1754

if (work == NULL) {

1754

if (work == NULL) {

1755

dev_priv->display.enable_fbc(crtc, interval);

1755

dev_priv->display.enable_fbc(crtc, interval);

1756

return;

1756

return;

1757

}

1757

}

1758

1759

work->crtc = crtc;

1759

work->crtc = crtc;

1760

work->fb = crtc->fb;

1760

work->fb = crtc->fb;

1761

work->interval = interval;

1761

work->interval = interval;

1762

INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);

1762

INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);

1763

1764

dev_priv->fbc_work = work;

1764

dev_priv->fbc_work = work;

1765

1766

DRM_DEBUG_KMS("scheduling delayed FBC enable\n");

1766

DRM_DEBUG_KMS("scheduling delayed FBC enable\n");

1767

1768

/* Delay the actual enabling to let pageflipping cease and the

1768

/* Delay the actual enabling to let pageflipping cease and the

1769

* display to settle before starting the compression. Note that

1769

* display to settle before starting the compression. Note that

1770

* this delay also serves a second purpose: it allows for a

1770

* this delay also serves a second purpose: it allows for a

1771

* vblank to pass after disabling the FBC before we attempt

1771

* vblank to pass after disabling the FBC before we attempt

1772

* to modify the control registers.

1772

* to modify the control registers.

1773

*

1773

*

1774

* A more complicated solution would involve tracking vblanks

1774

* A more complicated solution would involve tracking vblanks

1775

* following the termination of the page-flipping sequence

1775

* following the termination of the page-flipping sequence

1776

* and indeed performing the enable as a co-routine and not

1776

* and indeed performing the enable as a co-routine and not

1777

* waiting synchronously upon the vblank.

1777

* waiting synchronously upon the vblank.

1778

*/

1778

*/

1779

schedule_delayed_work(&work->work, msecs_to_jiffies(50));

1779

schedule_delayed_work(&work->work, msecs_to_jiffies(50));

1780

}

1780

}

1781

1782

void intel_disable_fbc(struct drm_device *dev)

1782

void intel_disable_fbc(struct drm_device *dev)

1783

{

1783

{

1784

struct drm_i915_private *dev_priv = dev->dev_private;

1784

struct drm_i915_private *dev_priv = dev->dev_private;

1785

1786

intel_cancel_fbc_work(dev_priv);

1786

intel_cancel_fbc_work(dev_priv);

1787

1788

if (!dev_priv->display.disable_fbc)

1788

if (!dev_priv->display.disable_fbc)

1789

return;

1789

return;

1790

1791

dev_priv->display.disable_fbc(dev);

1791

dev_priv->display.disable_fbc(dev);

1792

dev_priv->cfb_plane = -1;

1792

dev_priv->cfb_plane = -1;

1793

}

1793

}

1794

1795

/**

1795

/**

1796

* intel_update_fbc - enable/disable FBC as needed

1796

* intel_update_fbc - enable/disable FBC as needed

1797

* @dev: the drm_device

1797

* @dev: the drm_device

1798

*

1798

*

1799

* Set up the framebuffer compression hardware at mode set time. We

1799

* Set up the framebuffer compression hardware at mode set time. We

1800

* enable it if possible:

1800

* enable it if possible:

1801

* - plane A only (on pre-965)

1801

* - plane A only (on pre-965)

1802

* - no pixel mulitply/line duplication

1802

* - no pixel mulitply/line duplication

1803

* - no alpha buffer discard

1803

* - no alpha buffer discard

1804

* - no dual wide

1804

* - no dual wide

1805

* - framebuffer <= 2048 in width, 1536 in height

1805

* - framebuffer <= 2048 in width, 1536 in height

1806

*

1806

*

1807

* We can't assume that any compression will take place (worst case),

1807

* We can't assume that any compression will take place (worst case),

1808

* so the compressed buffer has to be the same size as the uncompressed

1808

* so the compressed buffer has to be the same size as the uncompressed

1809

* one. It also must reside (along with the line length buffer) in

1809

* one. It also must reside (along with the line length buffer) in

1810

* stolen memory.

1810

* stolen memory.

1811

*

1811

*

1812

* We need to enable/disable FBC on a global basis.

1812

* We need to enable/disable FBC on a global basis.

1813

*/

1813

*/

1814

static void intel_update_fbc(struct drm_device *dev)

1814

static void intel_update_fbc(struct drm_device *dev)

1815

{

1815

{

1816

struct drm_i915_private *dev_priv = dev->dev_private;

1816

struct drm_i915_private *dev_priv = dev->dev_private;

1817

struct drm_crtc *crtc = NULL, *tmp_crtc;

1817

struct drm_crtc *crtc = NULL, *tmp_crtc;

1818

struct intel_crtc *intel_crtc;

1818

struct intel_crtc *intel_crtc;

1819

struct drm_framebuffer *fb;

1819

struct drm_framebuffer *fb;

1820

struct intel_framebuffer *intel_fb;

1820

struct intel_framebuffer *intel_fb;

1821

struct drm_i915_gem_object *obj;

1821

struct drm_i915_gem_object *obj;

1822

int enable_fbc;

1822

int enable_fbc;

1823

1824

DRM_DEBUG_KMS("\n");

1824

DRM_DEBUG_KMS("\n");

1825

1826

if (!i915_powersave)

1826

if (!i915_powersave)

1827

return;

1827

return;

1828

1829

if (!I915_HAS_FBC(dev))

1829

if (!I915_HAS_FBC(dev))

1830

return;

1830

return;

1831

1832

/*

1832

/*

1833

* If FBC is already on, we just have to verify that we can

1833

* If FBC is already on, we just have to verify that we can

1834

* keep it that way...

1834

* keep it that way...

1835

* Need to disable if:

1835

* Need to disable if:

1836

* - more than one pipe is active

1836

* - more than one pipe is active

1837

* - changing FBC params (stride, fence, mode)

1837

* - changing FBC params (stride, fence, mode)

1838

* - new fb is too large to fit in compressed buffer

1838

* - new fb is too large to fit in compressed buffer

1839

* - going to an unsupported config (interlace, pixel multiply, etc.)

1839

* - going to an unsupported config (interlace, pixel multiply, etc.)

1840

*/

1840

*/

1841

list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {

1841

list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {

1842

if (tmp_crtc->enabled && tmp_crtc->fb) {

1842

if (tmp_crtc->enabled && tmp_crtc->fb) {

1843

if (crtc) {

1843

if (crtc) {

1844

DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");

1844

DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");

1845

dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;

1845

dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;

1846

goto out_disable;

1846

goto out_disable;

1847

}

1847

}

1848

crtc = tmp_crtc;

1848

crtc = tmp_crtc;

1849

}

1849

}

1850

}

1850

}

1851

1852

if (!crtc || crtc->fb == NULL) {

1852

if (!crtc || crtc->fb == NULL) {

1853

DRM_DEBUG_KMS("no output, disabling\n");

1853

DRM_DEBUG_KMS("no output, disabling\n");

1854

dev_priv->no_fbc_reason = FBC_NO_OUTPUT;

1854

dev_priv->no_fbc_reason = FBC_NO_OUTPUT;

1855

goto out_disable;

1855

goto out_disable;

1856

}

1856

}

1857

1858

intel_crtc = to_intel_crtc(crtc);

1858

intel_crtc = to_intel_crtc(crtc);

1859

fb = crtc->fb;

1859

fb = crtc->fb;

1860

intel_fb = to_intel_framebuffer(fb);

1860

intel_fb = to_intel_framebuffer(fb);

1861

obj = intel_fb->obj;

1861

obj = intel_fb->obj;

1862

1863

enable_fbc = i915_enable_fbc;

1863

enable_fbc = i915_enable_fbc;

1864

if (enable_fbc < 0) {

1864

if (enable_fbc < 0) {

1865

DRM_DEBUG_KMS("fbc set to per-chip default\n");

1865

DRM_DEBUG_KMS("fbc set to per-chip default\n");

1866

enable_fbc = 1;

1866

enable_fbc = 1;

1867

if (INTEL_INFO(dev)->gen <= 5)

1867

if (INTEL_INFO(dev)->gen <= 5)

1868

enable_fbc = 0;

1868

enable_fbc = 0;

1869

}

1869

}

1870

if (!enable_fbc) {

1870

if (!enable_fbc) {

1871

DRM_DEBUG_KMS("fbc disabled per module param\n");

1871

DRM_DEBUG_KMS("fbc disabled per module param\n");

1872

dev_priv->no_fbc_reason = FBC_MODULE_PARAM;

1872

dev_priv->no_fbc_reason = FBC_MODULE_PARAM;

1873

goto out_disable;

1873

goto out_disable;

1874

}

1874

}

1875

if (intel_fb->obj->base.size > dev_priv->cfb_size) {

1875

if (intel_fb->obj->base.size > dev_priv->cfb_size) {

1876

DRM_DEBUG_KMS("framebuffer too large, disabling "

1876

DRM_DEBUG_KMS("framebuffer too large, disabling "

1877

"compression\n");

1877

"compression\n");

1878

dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;

1878

dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;

1879

goto out_disable;

1879

goto out_disable;

1880

}

1880

}

1881

if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||

1881

if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||

1882

(crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {

1882

(crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {

1883

DRM_DEBUG_KMS("mode incompatible with compression, "

1883

DRM_DEBUG_KMS("mode incompatible with compression, "

1884

"disabling\n");

1884

"disabling\n");

1885

dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;

1885

dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;

1886

goto out_disable;

1886

goto out_disable;

1887

}

1887

}

1888

if ((crtc->mode.hdisplay > 2048) ||

1888

if ((crtc->mode.hdisplay > 2048) ||

1889

(crtc->mode.vdisplay > 1536)) {

1889

(crtc->mode.vdisplay > 1536)) {

1890

DRM_DEBUG_KMS("mode too large for compression, disabling\n");

1890

DRM_DEBUG_KMS("mode too large for compression, disabling\n");

1891

dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;

1891

dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;

1892

goto out_disable;

1892

goto out_disable;

1893

}

1893

}

1894

if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {

1894

if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {

1895

DRM_DEBUG_KMS("plane not 0, disabling compression\n");

1895

DRM_DEBUG_KMS("plane not 0, disabling compression\n");

1896

dev_priv->no_fbc_reason = FBC_BAD_PLANE;

1896

dev_priv->no_fbc_reason = FBC_BAD_PLANE;

1897

goto out_disable;

1897

goto out_disable;

1898

}

1898

}

1899

1900

/* The use of a CPU fence is mandatory in order to detect writes

1900

/* The use of a CPU fence is mandatory in order to detect writes

1901

* by the CPU to the scanout and trigger updates to the FBC.

1901

* by the CPU to the scanout and trigger updates to the FBC.

1902

*/

1902

*/

1903

if (obj->tiling_mode != I915_TILING_X ||

1903

if (obj->tiling_mode != I915_TILING_X ||

1904

obj->fence_reg == I915_FENCE_REG_NONE) {

1904

obj->fence_reg == I915_FENCE_REG_NONE) {

1905

DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");

1905

DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");

1906

dev_priv->no_fbc_reason = FBC_NOT_TILED;

1906

dev_priv->no_fbc_reason = FBC_NOT_TILED;

1907

goto out_disable;

1907

goto out_disable;

1908

}

1908

}

1909

1910

/* If the kernel debugger is active, always disable compression */

1910

/* If the kernel debugger is active, always disable compression */

1911

if (in_dbg_master())

1911

if (in_dbg_master())

1912

goto out_disable;

1912

goto out_disable;

1913

1914

/* If the scanout has not changed, don't modify the FBC settings.

1914

/* If the scanout has not changed, don't modify the FBC settings.

1915

* Note that we make the fundamental assumption that the fb->obj

1915

* Note that we make the fundamental assumption that the fb->obj

1916

* cannot be unpinned (and have its GTT offset and fence revoked)

1916

* cannot be unpinned (and have its GTT offset and fence revoked)

1917

* without first being decoupled from the scanout and FBC disabled.

1917

* without first being decoupled from the scanout and FBC disabled.

1918

*/

1918

*/

1919

if (dev_priv->cfb_plane == intel_crtc->plane &&

1919

if (dev_priv->cfb_plane == intel_crtc->plane &&

1920

dev_priv->cfb_fb == fb->base.id &&

1920

dev_priv->cfb_fb == fb->base.id &&

1921

dev_priv->cfb_y == crtc->y)

1921

dev_priv->cfb_y == crtc->y)

1922

return;

1922

return;

1923

1924

if (intel_fbc_enabled(dev)) {

1924

if (intel_fbc_enabled(dev)) {

1925

/* We update FBC along two paths, after changing fb/crtc

1925

/* We update FBC along two paths, after changing fb/crtc

1926

* configuration (modeswitching) and after page-flipping

1926

* configuration (modeswitching) and after page-flipping

1927

* finishes. For the latter, we know that not only did

1927

* finishes. For the latter, we know that not only did

1928

* we disable the FBC at the start of the page-flip

1928

* we disable the FBC at the start of the page-flip

1929

* sequence, but also more than one vblank has passed.

1929

* sequence, but also more than one vblank has passed.

1930

*

1930

*

1931

* For the former case of modeswitching, it is possible

1931

* For the former case of modeswitching, it is possible

1932

* to switch between two FBC valid configurations

1932

* to switch between two FBC valid configurations

1933

* instantaneously so we do need to disable the FBC

1933

* instantaneously so we do need to disable the FBC

1934

* before we can modify its control registers. We also

1934

* before we can modify its control registers. We also

1935

* have to wait for the next vblank for that to take

1935

* have to wait for the next vblank for that to take

1936

* effect. However, since we delay enabling FBC we can

1936

* effect. However, since we delay enabling FBC we can

1937

* assume that a vblank has passed since disabling and

1937

* assume that a vblank has passed since disabling and

1938

* that we can safely alter the registers in the deferred

1938

* that we can safely alter the registers in the deferred

1939

* callback.

1939

* callback.

1940

*

1940

*

1941

* In the scenario that we go from a valid to invalid

1941

* In the scenario that we go from a valid to invalid

1942

* and then back to valid FBC configuration we have

1942

* and then back to valid FBC configuration we have

1943

* no strict enforcement that a vblank occurred since

1943

* no strict enforcement that a vblank occurred since

1944

* disabling the FBC. However, along all current pipe

1944

* disabling the FBC. However, along all current pipe

1945

* disabling paths we do need to wait for a vblank at

1945

* disabling paths we do need to wait for a vblank at

1946

* some point. And we wait before enabling FBC anyway.

1946

* some point. And we wait before enabling FBC anyway.

1947

*/

1947

*/

1948

DRM_DEBUG_KMS("disabling active FBC for update\n");

1948

DRM_DEBUG_KMS("disabling active FBC for update\n");

1949

intel_disable_fbc(dev);

1949

intel_disable_fbc(dev);

1950

}

1950

}

1951

1952

intel_enable_fbc(crtc, 500);

1952

intel_enable_fbc(crtc, 500);

1953

return;

1953

return;

1954

1955

out_disable:

1955

out_disable:

1956

/* Multiple disables should be harmless */

1956

/* Multiple disables should be harmless */

1957

if (intel_fbc_enabled(dev)) {

1957

if (intel_fbc_enabled(dev)) {

1958

DRM_DEBUG_KMS("unsupported config, disabling FBC\n");

1958

DRM_DEBUG_KMS("unsupported config, disabling FBC\n");

1959

intel_disable_fbc(dev);

1959

intel_disable_fbc(dev);

1960

}

1960

}

1961

}

1961

}

1962

1963

int

1963

int

1964

intel_pin_and_fence_fb_obj(struct drm_device *dev,

1964

intel_pin_and_fence_fb_obj(struct drm_device *dev,

1965

struct drm_i915_gem_object *obj,

1965

struct drm_i915_gem_object *obj,

1966

struct intel_ring_buffer *pipelined)

1966

struct intel_ring_buffer *pipelined)

1967

{

1967

{

1968

struct drm_i915_private *dev_priv = dev->dev_private;

1968

struct drm_i915_private *dev_priv = dev->dev_private;

1969

u32 alignment;

1969

u32 alignment;

1970

int ret;

1970

int ret;

1971

1972

switch (obj->tiling_mode) {

1972

switch (obj->tiling_mode) {

1973

case I915_TILING_NONE:

1973

case I915_TILING_NONE:

1974

if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))

1974

if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))

1975

alignment = 128 * 1024;

1975

alignment = 128 * 1024;

1976

else if (INTEL_INFO(dev)->gen >= 4)

1976

else if (INTEL_INFO(dev)->gen >= 4)

1977

alignment = 4 * 1024;

1977

alignment = 4 * 1024;

1978

else

1978

else

1979

alignment = 64 * 1024;

1979

alignment = 64 * 1024;

1980

break;

1980

break;

1981

case I915_TILING_X:

1981

case I915_TILING_X:

1982

/* pin() will align the object as required by fence */

1982

/* pin() will align the object as required by fence */

1983

alignment = 0;

1983

alignment = 0;

1984

break;

1984

break;

1985

case I915_TILING_Y:

1985

case I915_TILING_Y:

1986

/* FIXME: Is this true? */

1986

/* FIXME: Is this true? */

1987

DRM_ERROR("Y tiled not allowed for scan out buffers\n");

1987

DRM_ERROR("Y tiled not allowed for scan out buffers\n");

1988

return -EINVAL;

1988

return -EINVAL;

1989

default:

1989

default:

1990

BUG();

1990

BUG();

1991

}

1991

}

1992

1993

dev_priv->mm.interruptible = false;

1993

dev_priv->mm.interruptible = false;

1994

ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);

1994

ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);

1995

if (ret)

1995

if (ret)

1996

goto err_interruptible;

1996

goto err_interruptible;

1997

1998

/* Install a fence for tiled scan-out. Pre-i965 always needs a

1998

/* Install a fence for tiled scan-out. Pre-i965 always needs a

1999

* fence, whereas 965+ only requires a fence if using

1999

* fence, whereas 965+ only requires a fence if using

2000

* framebuffer compression. For simplicity, we always install

2000

* framebuffer compression. For simplicity, we always install

2001

* a fence as the cost is not that onerous.

2001

* a fence as the cost is not that onerous.

2002

*/

2002

*/

2003

if (obj->tiling_mode != I915_TILING_NONE) {

2003

if (obj->tiling_mode != I915_TILING_NONE) {

2004

ret = i915_gem_object_get_fence(obj, pipelined);

2004

ret = i915_gem_object_get_fence(obj, pipelined);

2005

if (ret)

2005

if (ret)

2006

goto err_unpin;

2006

goto err_unpin;

2007

}

2007

}

2008

2009

dev_priv->mm.interruptible = true;

2009

dev_priv->mm.interruptible = true;

2010

return 0;

2010

return 0;

2011

2012

err_unpin:

2012

err_unpin:

2013

i915_gem_object_unpin(obj);

2013

i915_gem_object_unpin(obj);

2014

err_interruptible:

2014

err_interruptible:

2015

dev_priv->mm.interruptible = true;

2015

dev_priv->mm.interruptible = true;

2016

return ret;

2016

return ret;

2017

}

2017

}

2018

2019

static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,

2019

static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,

2020

int x, int y)

2020

int x, int y)

2021

{

2021

{

2022

struct drm_device *dev = crtc->dev;

2022

struct drm_device *dev = crtc->dev;

2023

struct drm_i915_private *dev_priv = dev->dev_private;

2023

struct drm_i915_private *dev_priv = dev->dev_private;

2024

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

2024

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

2025

struct intel_framebuffer *intel_fb;

2025

struct intel_framebuffer *intel_fb;

2026

struct drm_i915_gem_object *obj;

2026

struct drm_i915_gem_object *obj;

2027

int plane = intel_crtc->plane;

2027

int plane = intel_crtc->plane;

2028

unsigned long Start, Offset;

2028

unsigned long Start, Offset;

2029

u32 dspcntr;

2029

u32 dspcntr;

2030

u32 reg;

2030

u32 reg;

2031

2032

switch (plane) {

2032

switch (plane) {

2033

case 0:

2033

case 0:

2034

case 1:

2034

case 1:

2035

break;

2035

break;

2036

default:

2036

default:

2037

DRM_ERROR("Can't update plane %d in SAREA\n", plane);

2037

DRM_ERROR("Can't update plane %d in SAREA\n", plane);

2038

return -EINVAL;

2038

return -EINVAL;

2039

}

2039

}

2040

2041

intel_fb = to_intel_framebuffer(fb);

2041

intel_fb = to_intel_framebuffer(fb);

2042

obj = intel_fb->obj;

2042

obj = intel_fb->obj;

2043

2044

reg = DSPCNTR(plane);

2044

reg = DSPCNTR(plane);

2045

dspcntr = I915_READ(reg);

2045

dspcntr = I915_READ(reg);

2046

/* Mask out pixel format bits in case we change it */

2046

/* Mask out pixel format bits in case we change it */

2047

dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;

2047

dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;

2048

switch (fb->bits_per_pixel) {

2048

switch (fb->bits_per_pixel) {

2049

case 8:

2049

case 8:

2050

dspcntr |= DISPPLANE_8BPP;

2050

dspcntr |= DISPPLANE_8BPP;

2051

break;

2051

break;

2052

case 16:

2052

case 16:

2053

if (fb->depth == 15)

2053

if (fb->depth == 15)

2054

dspcntr |= DISPPLANE_15_16BPP;

2054

dspcntr |= DISPPLANE_15_16BPP;

2055

else

2055

else

2056

dspcntr |= DISPPLANE_16BPP;

2056

dspcntr |= DISPPLANE_16BPP;

2057

break;

2057

break;

2058

case 24:

2058

case 24:

2059

case 32:

2059

case 32:

2060

dspcntr |= DISPPLANE_32BPP_NO_ALPHA;

2060

dspcntr |= DISPPLANE_32BPP_NO_ALPHA;

2061

break;

2061

break;

2062

default:

2062

default:

2063

DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);

2063

DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);

2064

return -EINVAL;

2064

return -EINVAL;

2065

}

2065

}

2066

if (INTEL_INFO(dev)->gen >= 4) {

2066

if (INTEL_INFO(dev)->gen >= 4) {

2067

if (obj->tiling_mode != I915_TILING_NONE)

2067

if (obj->tiling_mode != I915_TILING_NONE)

2068

dspcntr |= DISPPLANE_TILED;

2068

dspcntr |= DISPPLANE_TILED;

2069

else

2069

else

2070

dspcntr &= ~DISPPLANE_TILED;

2070

dspcntr &= ~DISPPLANE_TILED;

2071

}

2071

}

2072

2073

I915_WRITE(reg, dspcntr);

2073

I915_WRITE(reg, dspcntr);

2074

2075

Start = obj->gtt_offset;

2075

Start = obj->gtt_offset;

2076

Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);

2076

Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);

2077

2078

DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",

2078

DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",

2079

Start, Offset, x, y, fb->pitch);

2079

Start, Offset, x, y, fb->pitch);

2080

I915_WRITE(DSPSTRIDE(plane), fb->pitch);

2080

I915_WRITE(DSPSTRIDE(plane), fb->pitch);

2081

if (INTEL_INFO(dev)->gen >= 4) {

2081

if (INTEL_INFO(dev)->gen >= 4) {

2082

I915_WRITE(DSPSURF(plane), Start);

2082

I915_WRITE(DSPSURF(plane), Start);

2083

I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);

2083

I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);

2084

I915_WRITE(DSPADDR(plane), Offset);

2084

I915_WRITE(DSPADDR(plane), Offset);

2085

} else

2085

} else

2086

I915_WRITE(DSPADDR(plane), Start + Offset);

2086

I915_WRITE(DSPADDR(plane), Start + Offset);

2087

POSTING_READ(reg);

2087

POSTING_READ(reg);

2088

2089

return 0;

2089

return 0;

2090

}

2090

}

2091

2092

static int ironlake_update_plane(struct drm_crtc *crtc,

2092

static int ironlake_update_plane(struct drm_crtc *crtc,

2093

struct drm_framebuffer *fb, int x, int y)

2093

struct drm_framebuffer *fb, int x, int y)

2094

{

2094

{

2095

struct drm_device *dev = crtc->dev;

2095

struct drm_device *dev = crtc->dev;

2096

struct drm_i915_private *dev_priv = dev->dev_private;

2096

struct drm_i915_private *dev_priv = dev->dev_private;

2097

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

2097

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

2098

struct intel_framebuffer *intel_fb;

2098

struct intel_framebuffer *intel_fb;

2099

struct drm_i915_gem_object *obj;

2099

struct drm_i915_gem_object *obj;

2100

int plane = intel_crtc->plane;

2100

int plane = intel_crtc->plane;

2101

unsigned long Start, Offset;

2101

unsigned long Start, Offset;

2102

u32 dspcntr;

2102

u32 dspcntr;

2103

u32 reg;

2103

u32 reg;

2104

2105

switch (plane) {

2105

switch (plane) {

2106

case 0:

2106

case 0:

2107

case 1:

2107

case 1:

2108

case 2:

2108

case 2:

2109

break;

2109

break;

2110

default:

2110

default:

2111

DRM_ERROR("Can't update plane %d in SAREA\n", plane);

2111

DRM_ERROR("Can't update plane %d in SAREA\n", plane);

2112

return -EINVAL;

2112

return -EINVAL;

2113

}

2113

}

2114

2115

intel_fb = to_intel_framebuffer(fb);

2115

intel_fb = to_intel_framebuffer(fb);

2116

obj = intel_fb->obj;

2116

obj = intel_fb->obj;

2117

2118

reg = DSPCNTR(plane);

2118

reg = DSPCNTR(plane);

2119

dspcntr = I915_READ(reg);

2119

dspcntr = I915_READ(reg);

2120

/* Mask out pixel format bits in case we change it */

2120

/* Mask out pixel format bits in case we change it */

2121

dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;

2121

dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;

2122

switch (fb->bits_per_pixel) {

2122

switch (fb->bits_per_pixel) {

2123

case 8:

2123

case 8:

2124

dspcntr |= DISPPLANE_8BPP;

2124

dspcntr |= DISPPLANE_8BPP;

2125

break;

2125

break;

2126

case 16:

2126

case 16:

2127

if (fb->depth != 16)

2127

if (fb->depth != 16)

2128

return -EINVAL;

2128

return -EINVAL;

2129

2130

dspcntr |= DISPPLANE_16BPP;

2130

dspcntr |= DISPPLANE_16BPP;

2131

break;

2131

break;

2132

case 24:

2132

case 24:

2133

case 32:

2133

case 32:

2134

if (fb->depth == 24)

2134

if (fb->depth == 24)

2135

dspcntr |= DISPPLANE_32BPP_NO_ALPHA;

2135

dspcntr |= DISPPLANE_32BPP_NO_ALPHA;

2136

else if (fb->depth == 30)

2136

else if (fb->depth == 30)

2137

dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;

2137

dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;

2138

else

2138

else

2139

return -EINVAL;

2139

return -EINVAL;

2140

break;

2140

break;

2141

default:

2141

default:

2142

DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);

2142

DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);

2143

return -EINVAL;

2143

return -EINVAL;

2144

}

2144

}

2145

2146

if (obj->tiling_mode != I915_TILING_NONE)

2146

if (obj->tiling_mode != I915_TILING_NONE)

2147

dspcntr |= DISPPLANE_TILED;

2147

dspcntr |= DISPPLANE_TILED;

2148

else

2148

else

2149

dspcntr &= ~DISPPLANE_TILED;

2149

dspcntr &= ~DISPPLANE_TILED;

2150

2151

/* must disable */

2151

/* must disable */

2152

dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;

2152

dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;

2153

2154

I915_WRITE(reg, dspcntr);

2154

I915_WRITE(reg, dspcntr);

2155

2156

Start = obj->gtt_offset;

2156

Start = obj->gtt_offset;

2157

Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);

2157

Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);

2158

2159

DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",

2159

DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",

2160

Start, Offset, x, y, fb->pitch);

2160

Start, Offset, x, y, fb->pitch);

2161

I915_WRITE(DSPSTRIDE(plane), fb->pitch);

2161

I915_WRITE(DSPSTRIDE(plane), fb->pitch);

2162

I915_WRITE(DSPSURF(plane), Start);

2162

I915_WRITE(DSPSURF(plane), Start);

2163

I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);

2163

I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);

2164

I915_WRITE(DSPADDR(plane), Offset);

2164

I915_WRITE(DSPADDR(plane), Offset);

2165

POSTING_READ(reg);

2165

POSTING_READ(reg);

2166

2167

return 0;

2167

return 0;

2168

}

2168

}

2169

2170

/* Assume fb object is pinned & idle & fenced and just update base pointers */

2170

/* Assume fb object is pinned & idle & fenced and just update base pointers */

2171

static int

2171

static int

2172

intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,

2172

intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,

2173

int x, int y, enum mode_set_atomic state)

2173

int x, int y, enum mode_set_atomic state)

2174

{

2174

{

2175

struct drm_device *dev = crtc->dev;

2175

struct drm_device *dev = crtc->dev;

2176

struct drm_i915_private *dev_priv = dev->dev_private;

2176

struct drm_i915_private *dev_priv = dev->dev_private;

2177

int ret;

2177

int ret;

2178

2179

ret = dev_priv->display.update_plane(crtc, fb, x, y);

2179

ret = dev_priv->display.update_plane(crtc, fb, x, y);

2180

if (ret)

2180

if (ret)

2181

return ret;

2181

return ret;

2182

2183

intel_update_fbc(dev);

2183

intel_update_fbc(dev);

2184

intel_increase_pllclock(crtc);

2184

intel_increase_pllclock(crtc);

2185

2186

return 0;

2186

return 0;

2187

}

2187

}

2188

2189

static int

2189

static int

2190

intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,

2190

intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,

2191

struct drm_framebuffer *old_fb)

2191

struct drm_framebuffer *old_fb)

2192

{

2192

{

2193

struct drm_device *dev = crtc->dev;

2193

struct drm_device *dev = crtc->dev;

2194

struct drm_i915_master_private *master_priv;

2194

struct drm_i915_master_private *master_priv;

2195

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

2195

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

2196

int ret;

2196

int ret;

2197

2198

/* no fb bound */

2198

/* no fb bound */

2199

if (!crtc->fb) {

2199

if (!crtc->fb) {

2200

DRM_ERROR("No FB bound\n");

2200

DRM_ERROR("No FB bound\n");

2201

return 0;

2201

return 0;

2202

}

2202

}

2203

2204

switch (intel_crtc->plane) {

2204

switch (intel_crtc->plane) {

2205

case 0:

2205

case 0:

2206

case 1:

2206

case 1:

2207

break;

2207

break;

2208

case 2:

2208

case 2:

2209

if (IS_IVYBRIDGE(dev))

2209

if (IS_IVYBRIDGE(dev))

2210

break;

2210

break;

2211

/* fall through otherwise */

2211

/* fall through otherwise */

2212

default:

2212

default:

2213

DRM_ERROR("no plane for crtc\n");

2213

DRM_ERROR("no plane for crtc\n");

2214

return -EINVAL;

2214

return -EINVAL;

2215

}

2215

}

2216

2217

mutex_lock(&dev->struct_mutex);

2217

mutex_lock(&dev->struct_mutex);

2218

ret = intel_pin_and_fence_fb_obj(dev,

2218

ret = intel_pin_and_fence_fb_obj(dev,

2219

to_intel_framebuffer(crtc->fb)->obj,

2219

to_intel_framebuffer(crtc->fb)->obj,

2220

NULL);

2220

NULL);

2221

if (ret != 0) {

2221

if (ret != 0) {

2222

mutex_unlock(&dev->struct_mutex);

2222

mutex_unlock(&dev->struct_mutex);

2223

DRM_ERROR("pin & fence failed\n");

2223

DRM_ERROR("pin & fence failed\n");

2224

return ret;

2224

return ret;

2225

}

2225

}

2226

2227

if (old_fb) {

2227

if (old_fb) {

2228

struct drm_i915_private *dev_priv = dev->dev_private;

2228

struct drm_i915_private *dev_priv = dev->dev_private;

2229

struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;

2229

struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;

2230

2231

wait_event(dev_priv->pending_flip_queue,

2231

wait_event(dev_priv->pending_flip_queue,

2232

atomic_read(&dev_priv->mm.wedged) ||

2232

atomic_read(&dev_priv->mm.wedged) ||

2233

atomic_read(&obj->pending_flip) == 0);

2233

atomic_read(&obj->pending_flip) == 0);

2234

2235

/* Big Hammer, we also need to ensure that any pending

2235

/* Big Hammer, we also need to ensure that any pending

2236

* MI_WAIT_FOR_EVENT inside a user batch buffer on the

2236

* MI_WAIT_FOR_EVENT inside a user batch buffer on the

2237

* current scanout is retired before unpinning the old

2237

* current scanout is retired before unpinning the old

2238

* framebuffer.

2238

* framebuffer.

2239

*

2239

*

2240

* This should only fail upon a hung GPU, in which case we

2240

* This should only fail upon a hung GPU, in which case we

2241

* can safely continue.

2241

* can safely continue.

2242

*/

2242

*/

2243

ret = i915_gem_object_finish_gpu(obj);

2243

ret = i915_gem_object_finish_gpu(obj);

2244

(void) ret;

2244

(void) ret;

2245

}

2245

}

2246

2247

ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,

2247

ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,

2248

LEAVE_ATOMIC_MODE_SET);

2248

LEAVE_ATOMIC_MODE_SET);

2249

if (ret) {

2249

if (ret) {

2250

i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);

2250

i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);

2251

mutex_unlock(&dev->struct_mutex);

2251

mutex_unlock(&dev->struct_mutex);

2252

DRM_ERROR("failed to update base address\n");

2252

DRM_ERROR("failed to update base address\n");

2253

return ret;

2253

return ret;

2254

}

2254

}

2255

2256

if (old_fb) {

2256

if (old_fb) {

2257

intel_wait_for_vblank(dev, intel_crtc->pipe);

2257

intel_wait_for_vblank(dev, intel_crtc->pipe);

2258

i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);

2258

i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);

2259

}

2259

}

2260

2261

mutex_unlock(&dev->struct_mutex);

2261

mutex_unlock(&dev->struct_mutex);

2262

2263

if (!dev->primary->master)

2263

if (!dev->primary->master)

2264

return 0;

2264

return 0;

2265

2266

master_priv = dev->primary->master->driver_priv;

2266

master_priv = dev->primary->master->driver_priv;

2267

if (!master_priv->sarea_priv)

2267

if (!master_priv->sarea_priv)

2268

return 0;

2268

return 0;

2269

2270

if (intel_crtc->pipe) {

2270

if (intel_crtc->pipe) {

2271

master_priv->sarea_priv->pipeB_x = x;

2271

master_priv->sarea_priv->pipeB_x = x;

2272

master_priv->sarea_priv->pipeB_y = y;

2272

master_priv->sarea_priv->pipeB_y = y;

2273

} else {

2273

} else {

2274

master_priv->sarea_priv->pipeA_x = x;

2274

master_priv->sarea_priv->pipeA_x = x;

2275

master_priv->sarea_priv->pipeA_y = y;

2275

master_priv->sarea_priv->pipeA_y = y;

2276

}

2276

}

2277

2278

return 0;

2278

return 0;

2279

}

2279

}

2280

2281

static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)

2281

static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)

2282

{

2282

{

2283

struct drm_device *dev = crtc->dev;

2283

struct drm_device *dev = crtc->dev;

2284

struct drm_i915_private *dev_priv = dev->dev_private;

2284

struct drm_i915_private *dev_priv = dev->dev_private;

2285

u32 dpa_ctl;

2285

u32 dpa_ctl;

2286

2287

DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);

2287

DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);

2288

dpa_ctl = I915_READ(DP_A);

2288

dpa_ctl = I915_READ(DP_A);

2289

dpa_ctl &= ~DP_PLL_FREQ_MASK;

2289

dpa_ctl &= ~DP_PLL_FREQ_MASK;

2290

2291

if (clock < 200000) {

2291

if (clock < 200000) {

2292

u32 temp;

2292

u32 temp;

2293

dpa_ctl |= DP_PLL_FREQ_160MHZ;

2293

dpa_ctl |= DP_PLL_FREQ_160MHZ;

2294

/* workaround for 160Mhz:

2294

/* workaround for 160Mhz:

2295

1) program 0x4600c bits 15:0 = 0x8124

2295

1) program 0x4600c bits 15:0 = 0x8124

2296

2) program 0x46010 bit 0 = 1

2296

2) program 0x46010 bit 0 = 1

2297

3) program 0x46034 bit 24 = 1

2297

3) program 0x46034 bit 24 = 1

2298

4) program 0x64000 bit 14 = 1

2298

4) program 0x64000 bit 14 = 1

2299

*/

2299

*/

2300

temp = I915_READ(0x4600c);

2300

temp = I915_READ(0x4600c);

2301

temp &= 0xffff0000;

2301

temp &= 0xffff0000;

2302

I915_WRITE(0x4600c, temp | 0x8124);

2302

I915_WRITE(0x4600c, temp | 0x8124);

2303

2304

temp = I915_READ(0x46010);

2304

temp = I915_READ(0x46010);

2305

I915_WRITE(0x46010, temp | 1);

2305

I915_WRITE(0x46010, temp | 1);

2306

2307

temp = I915_READ(0x46034);

2307

temp = I915_READ(0x46034);

2308

I915_WRITE(0x46034, temp | (1 << 24));

2308

I915_WRITE(0x46034, temp | (1 << 24));

2309

} else {

2309

} else {

2310

dpa_ctl |= DP_PLL_FREQ_270MHZ;

2310

dpa_ctl |= DP_PLL_FREQ_270MHZ;

2311

}

2311

}

2312

I915_WRITE(DP_A, dpa_ctl);

2312

I915_WRITE(DP_A, dpa_ctl);

2313

2314

POSTING_READ(DP_A);

2314

POSTING_READ(DP_A);

2315

udelay(500);

2315

udelay(500);

2316

}

2316

}

2317

2318

static void intel_fdi_normal_train(struct drm_crtc *crtc)

2318

static void intel_fdi_normal_train(struct drm_crtc *crtc)

2319

{

2319

{

2320

struct drm_device *dev = crtc->dev;

2320

struct drm_device *dev = crtc->dev;

2321

struct drm_i915_private *dev_priv = dev->dev_private;

2321

struct drm_i915_private *dev_priv = dev->dev_private;

2322

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

2322

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

2323

int pipe = intel_crtc->pipe;

2323

int pipe = intel_crtc->pipe;

2324

u32 reg, temp;

2324

u32 reg, temp;

2325

2326

/* enable normal train */

2326

/* enable normal train */

2327

reg = FDI_TX_CTL(pipe);

2327

reg = FDI_TX_CTL(pipe);

2328

temp = I915_READ(reg);

2328

temp = I915_READ(reg);

2329

if (IS_IVYBRIDGE(dev)) {

2329

if (IS_IVYBRIDGE(dev)) {

2330

temp &= ~FDI_LINK_TRAIN_NONE_IVB;

2330

temp &= ~FDI_LINK_TRAIN_NONE_IVB;

2331

temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;

2331

temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;

2332

} else {

2332

} else {

2333

temp &= ~FDI_LINK_TRAIN_NONE;

2333

temp &= ~FDI_LINK_TRAIN_NONE;

2334

temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;

2334

temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;

2335

}

2335

}

2336

I915_WRITE(reg, temp);

2336

I915_WRITE(reg, temp);

2337

2338

reg = FDI_RX_CTL(pipe);

2338

reg = FDI_RX_CTL(pipe);

2339

temp = I915_READ(reg);

2339

temp = I915_READ(reg);

2340

if (HAS_PCH_CPT(dev)) {

2340

if (HAS_PCH_CPT(dev)) {

2341

temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;

2341

temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;

2342

temp |= FDI_LINK_TRAIN_NORMAL_CPT;

2342

temp |= FDI_LINK_TRAIN_NORMAL_CPT;

2343

} else {

2343

} else {

2344

temp &= ~FDI_LINK_TRAIN_NONE;

2344

temp &= ~FDI_LINK_TRAIN_NONE;

2345

temp |= FDI_LINK_TRAIN_NONE;

2345

temp |= FDI_LINK_TRAIN_NONE;

2346

}

2346

}

2347

I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);

2347

I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);

2348

2349

/* wait one idle pattern time */

2349

/* wait one idle pattern time */

2350

POSTING_READ(reg);

2350

POSTING_READ(reg);

2351

udelay(1000);

2351

udelay(1000);

2352

2353

/* IVB wants error correction enabled */

2353

/* IVB wants error correction enabled */

2354

if (IS_IVYBRIDGE(dev))

2354

if (IS_IVYBRIDGE(dev))

2355

I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |

2355

I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |

2356

FDI_FE_ERRC_ENABLE);

2356

FDI_FE_ERRC_ENABLE);

2357

}

2357

}

2358

2359

static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)

2359

static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)

2360

{

2360

{

2361

struct drm_i915_private *dev_priv = dev->dev_private;

2361

struct drm_i915_private *dev_priv = dev->dev_private;

2362

u32 flags = I915_READ(SOUTH_CHICKEN1);

2362

u32 flags = I915_READ(SOUTH_CHICKEN1);

2363

2364

flags |= FDI_PHASE_SYNC_OVR(pipe);

2364

flags |= FDI_PHASE_SYNC_OVR(pipe);

2365

I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */

2365

I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */

2366

flags |= FDI_PHASE_SYNC_EN(pipe);

2366

flags |= FDI_PHASE_SYNC_EN(pipe);

2367

I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */

2367

I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */

2368

POSTING_READ(SOUTH_CHICKEN1);

2368

POSTING_READ(SOUTH_CHICKEN1);

2369

}

2369

}

2370

2371

/* The FDI link training functions for ILK/Ibexpeak. */

2371

/* The FDI link training functions for ILK/Ibexpeak. */

2372

static void ironlake_fdi_link_train(struct drm_crtc *crtc)

2372

static void ironlake_fdi_link_train(struct drm_crtc *crtc)

2373

{

2373

{

2374

struct drm_device *dev = crtc->dev;

2374

struct drm_device *dev = crtc->dev;

2375

struct drm_i915_private *dev_priv = dev->dev_private;

2375

struct drm_i915_private *dev_priv = dev->dev_private;

2376

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

2376

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

2377

int pipe = intel_crtc->pipe;

2377

int pipe = intel_crtc->pipe;

2378

int plane = intel_crtc->plane;

2378

int plane = intel_crtc->plane;

2379

u32 reg, temp, tries;

2379

u32 reg, temp, tries;

2380

2381

/* FDI needs bits from pipe & plane first */

2381

/* FDI needs bits from pipe & plane first */

2382

assert_pipe_enabled(dev_priv, pipe);

2382

assert_pipe_enabled(dev_priv, pipe);

2383

assert_plane_enabled(dev_priv, plane);

2383

assert_plane_enabled(dev_priv, plane);

2384

2385

/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit

2385

/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit

2386

for train result */

2386

for train result */

2387

reg = FDI_RX_IMR(pipe);

2387

reg = FDI_RX_IMR(pipe);

2388

temp = I915_READ(reg);

2388

temp = I915_READ(reg);

2389

temp &= ~FDI_RX_SYMBOL_LOCK;

2389

temp &= ~FDI_RX_SYMBOL_LOCK;

2390

temp &= ~FDI_RX_BIT_LOCK;

2390

temp &= ~FDI_RX_BIT_LOCK;

2391

I915_WRITE(reg, temp);

2391

I915_WRITE(reg, temp);

2392

I915_READ(reg);

2392

I915_READ(reg);

2393

udelay(150);

2393

udelay(150);

2394

2395

/* enable CPU FDI TX and PCH FDI RX */

2395

/* enable CPU FDI TX and PCH FDI RX */

2396

reg = FDI_TX_CTL(pipe);

2396

reg = FDI_TX_CTL(pipe);

2397

temp = I915_READ(reg);

2397

temp = I915_READ(reg);

2398

temp &= ~(7 << 19);

2398

temp &= ~(7 << 19);

2399

temp |= (intel_crtc->fdi_lanes - 1) << 19;

2399

temp |= (intel_crtc->fdi_lanes - 1) << 19;

2400

temp &= ~FDI_LINK_TRAIN_NONE;

2400

temp &= ~FDI_LINK_TRAIN_NONE;

2401

temp |= FDI_LINK_TRAIN_PATTERN_1;

2401

temp |= FDI_LINK_TRAIN_PATTERN_1;

2402

I915_WRITE(reg, temp | FDI_TX_ENABLE);

2402

I915_WRITE(reg, temp | FDI_TX_ENABLE);

2403

2404

reg = FDI_RX_CTL(pipe);

2404

reg = FDI_RX_CTL(pipe);

2405

temp = I915_READ(reg);

2405

temp = I915_READ(reg);

2406

temp &= ~FDI_LINK_TRAIN_NONE;

2406

temp &= ~FDI_LINK_TRAIN_NONE;

2407

temp |= FDI_LINK_TRAIN_PATTERN_1;

2407

temp |= FDI_LINK_TRAIN_PATTERN_1;

2408

I915_WRITE(reg, temp | FDI_RX_ENABLE);

2408

I915_WRITE(reg, temp | FDI_RX_ENABLE);

2409

2410

POSTING_READ(reg);

2410

POSTING_READ(reg);

2411

udelay(150);

2411

udelay(150);

2412

2413

/* Ironlake workaround, enable clock pointer after FDI enable*/

2413

/* Ironlake workaround, enable clock pointer after FDI enable*/

2414

if (HAS_PCH_IBX(dev)) {

2414

if (HAS_PCH_IBX(dev)) {

2415

I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);

2415

I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);

2416

I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |

2416

I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |

2417

FDI_RX_PHASE_SYNC_POINTER_EN);

2417

FDI_RX_PHASE_SYNC_POINTER_EN);

2418

}

2418

}

2419

2420

reg = FDI_RX_IIR(pipe);

2420

reg = FDI_RX_IIR(pipe);

2421

for (tries = 0; tries < 5; tries++) {

2421

for (tries = 0; tries < 5; tries++) {

2422

temp = I915_READ(reg);

2422

temp = I915_READ(reg);

2423

DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

2423

DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

2424

2425

if ((temp & FDI_RX_BIT_LOCK)) {

2425

if ((temp & FDI_RX_BIT_LOCK)) {

2426

DRM_DEBUG_KMS("FDI train 1 done.\n");

2426

DRM_DEBUG_KMS("FDI train 1 done.\n");

2427

I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);

2427

I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);

2428

break;

2428

break;

2429

}

2429

}

2430

}

2430

}

2431

if (tries == 5)

2431

if (tries == 5)

2432

DRM_ERROR("FDI train 1 fail!\n");

2432

DRM_ERROR("FDI train 1 fail!\n");

2433

2434

/* Train 2 */

2434

/* Train 2 */

2435

reg = FDI_TX_CTL(pipe);

2435

reg = FDI_TX_CTL(pipe);

2436

temp = I915_READ(reg);

2436

temp = I915_READ(reg);

2437

temp &= ~FDI_LINK_TRAIN_NONE;

2437

temp &= ~FDI_LINK_TRAIN_NONE;

2438

temp |= FDI_LINK_TRAIN_PATTERN_2;

2438

temp |= FDI_LINK_TRAIN_PATTERN_2;

2439

I915_WRITE(reg, temp);

2439

I915_WRITE(reg, temp);

2440

2441

reg = FDI_RX_CTL(pipe);

2441

reg = FDI_RX_CTL(pipe);

2442

temp = I915_READ(reg);

2442

temp = I915_READ(reg);

2443

temp &= ~FDI_LINK_TRAIN_NONE;

2443

temp &= ~FDI_LINK_TRAIN_NONE;

2444

temp |= FDI_LINK_TRAIN_PATTERN_2;

2444

temp |= FDI_LINK_TRAIN_PATTERN_2;

2445

I915_WRITE(reg, temp);

2445

I915_WRITE(reg, temp);

2446

2447

POSTING_READ(reg);

2447

POSTING_READ(reg);

2448

udelay(150);

2448

udelay(150);

2449

2450

reg = FDI_RX_IIR(pipe);

2450

reg = FDI_RX_IIR(pipe);

2451

for (tries = 0; tries < 5; tries++) {

2451

for (tries = 0; tries < 5; tries++) {

2452

temp = I915_READ(reg);

2452

temp = I915_READ(reg);

2453

DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

2453

DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

2454

2455

if (temp & FDI_RX_SYMBOL_LOCK) {

2455

if (temp & FDI_RX_SYMBOL_LOCK) {

2456

I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);

2456

I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);

2457

DRM_DEBUG_KMS("FDI train 2 done.\n");

2457

DRM_DEBUG_KMS("FDI train 2 done.\n");

2458

break;

2458

break;

2459

}

2459

}

2460

}

2460

}

2461

if (tries == 5)

2461

if (tries == 5)

2462

DRM_ERROR("FDI train 2 fail!\n");

2462

DRM_ERROR("FDI train 2 fail!\n");

2463

2464

DRM_DEBUG_KMS("FDI train done\n");

2464

DRM_DEBUG_KMS("FDI train done\n");

2465

2466

}

2466

}

2467

2468

static const int snb_b_fdi_train_param[] = {

2468

static const int snb_b_fdi_train_param[] = {

2469

FDI_LINK_TRAIN_400MV_0DB_SNB_B,

2469

FDI_LINK_TRAIN_400MV_0DB_SNB_B,

2470

FDI_LINK_TRAIN_400MV_6DB_SNB_B,

2470

FDI_LINK_TRAIN_400MV_6DB_SNB_B,

2471

FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,

2471

FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,

2472

FDI_LINK_TRAIN_800MV_0DB_SNB_B,

2472

FDI_LINK_TRAIN_800MV_0DB_SNB_B,

2473

};

2473

};

2474

2475

/* The FDI link training functions for SNB/Cougarpoint. */

2475

/* The FDI link training functions for SNB/Cougarpoint. */

2476

static void gen6_fdi_link_train(struct drm_crtc *crtc)

2476

static void gen6_fdi_link_train(struct drm_crtc *crtc)

2477

{

2477

{

2478

struct drm_device *dev = crtc->dev;

2478

struct drm_device *dev = crtc->dev;

2479

struct drm_i915_private *dev_priv = dev->dev_private;

2479

struct drm_i915_private *dev_priv = dev->dev_private;

2480

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

2480

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

2481

int pipe = intel_crtc->pipe;

2481

int pipe = intel_crtc->pipe;

2482

u32 reg, temp, i;

2482

u32 reg, temp, i;

2483

2484

/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit

2484

/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit

2485

for train result */

2485

for train result */

2486

reg = FDI_RX_IMR(pipe);

2486

reg = FDI_RX_IMR(pipe);

2487

temp = I915_READ(reg);

2487

temp = I915_READ(reg);

2488

temp &= ~FDI_RX_SYMBOL_LOCK;

2488

temp &= ~FDI_RX_SYMBOL_LOCK;

2489

temp &= ~FDI_RX_BIT_LOCK;

2489

temp &= ~FDI_RX_BIT_LOCK;

2490

I915_WRITE(reg, temp);

2490

I915_WRITE(reg, temp);

2491

2492

POSTING_READ(reg);

2492

POSTING_READ(reg);

2493

udelay(150);

2493

udelay(150);

2494

2495

/* enable CPU FDI TX and PCH FDI RX */

2495

/* enable CPU FDI TX and PCH FDI RX */

2496

reg = FDI_TX_CTL(pipe);

2496

reg = FDI_TX_CTL(pipe);

2497

temp = I915_READ(reg);

2497

temp = I915_READ(reg);

2498

temp &= ~(7 << 19);

2498

temp &= ~(7 << 19);

2499

temp |= (intel_crtc->fdi_lanes - 1) << 19;

2499

temp |= (intel_crtc->fdi_lanes - 1) << 19;

2500

temp &= ~FDI_LINK_TRAIN_NONE;

2500

temp &= ~FDI_LINK_TRAIN_NONE;

2501

temp |= FDI_LINK_TRAIN_PATTERN_1;

2501

temp |= FDI_LINK_TRAIN_PATTERN_1;

2502

temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;

2502

temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;

2503

/* SNB-B */

2503

/* SNB-B */

2504

temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;

2504

temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;

2505

I915_WRITE(reg, temp | FDI_TX_ENABLE);

2505

I915_WRITE(reg, temp | FDI_TX_ENABLE);

2506

2507

reg = FDI_RX_CTL(pipe);

2507

reg = FDI_RX_CTL(pipe);

2508

temp = I915_READ(reg);

2508

temp = I915_READ(reg);

2509

if (HAS_PCH_CPT(dev)) {

2509

if (HAS_PCH_CPT(dev)) {

2510

temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;

2510

temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;

2511

temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;

2511

temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;

2512

} else {

2512

} else {

2513

temp &= ~FDI_LINK_TRAIN_NONE;

2513

temp &= ~FDI_LINK_TRAIN_NONE;

2514

temp |= FDI_LINK_TRAIN_PATTERN_1;

2514

temp |= FDI_LINK_TRAIN_PATTERN_1;

2515

}

2515

}

2516

I915_WRITE(reg, temp | FDI_RX_ENABLE);

2516

I915_WRITE(reg, temp | FDI_RX_ENABLE);

2517

2518

POSTING_READ(reg);

2518

POSTING_READ(reg);

2519

udelay(150);

2519

udelay(150);

2520

2521

if (HAS_PCH_CPT(dev))

2521

if (HAS_PCH_CPT(dev))

2522

cpt_phase_pointer_enable(dev, pipe);

2522

cpt_phase_pointer_enable(dev, pipe);

2523

2524

for (i = 0; i < 4; i++) {

2524

for (i = 0; i < 4; i++) {

2525

reg = FDI_TX_CTL(pipe);

2525

reg = FDI_TX_CTL(pipe);

2526

temp = I915_READ(reg);

2526

temp = I915_READ(reg);

2527

temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;

2527

temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;

2528

temp |= snb_b_fdi_train_param[i];

2528

temp |= snb_b_fdi_train_param[i];

2529

I915_WRITE(reg, temp);

2529

I915_WRITE(reg, temp);

2530

2531

POSTING_READ(reg);

2531

POSTING_READ(reg);

2532

udelay(500);

2532

udelay(500);

2533

2534

reg = FDI_RX_IIR(pipe);

2534

reg = FDI_RX_IIR(pipe);

2535

temp = I915_READ(reg);

2535

temp = I915_READ(reg);

2536

DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

2536

DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

2537

2538

if (temp & FDI_RX_BIT_LOCK) {

2538

if (temp & FDI_RX_BIT_LOCK) {

2539

I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);

2539

I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);

2540

DRM_DEBUG_KMS("FDI train 1 done.\n");

2540

DRM_DEBUG_KMS("FDI train 1 done.\n");

2541

break;

2541

break;

2542

}

2542

}

2543

}

2543

}

2544

if (i == 4)

2544

if (i == 4)

2545

DRM_ERROR("FDI train 1 fail!\n");

2545

DRM_ERROR("FDI train 1 fail!\n");

2546

2547

/* Train 2 */

2547

/* Train 2 */

2548

reg = FDI_TX_CTL(pipe);

2548

reg = FDI_TX_CTL(pipe);

2549

temp = I915_READ(reg);

2549

temp = I915_READ(reg);

2550

temp &= ~FDI_LINK_TRAIN_NONE;

2550

temp &= ~FDI_LINK_TRAIN_NONE;

2551

temp |= FDI_LINK_TRAIN_PATTERN_2;

2551

temp |= FDI_LINK_TRAIN_PATTERN_2;

2552

if (IS_GEN6(dev)) {

2552

if (IS_GEN6(dev)) {

2553

temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;

2553

temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;

2554

/* SNB-B */

2554

/* SNB-B */

2555

temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;

2555

temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;

2556

}

2556

}

2557

I915_WRITE(reg, temp);

2557

I915_WRITE(reg, temp);

2558

2559

reg = FDI_RX_CTL(pipe);

2559

reg = FDI_RX_CTL(pipe);

2560

temp = I915_READ(reg);

2560

temp = I915_READ(reg);

2561

if (HAS_PCH_CPT(dev)) {

2561

if (HAS_PCH_CPT(dev)) {

2562

temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;

2562

temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;

2563

temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;

2563

temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;

2564

} else {

2564

} else {

2565

temp &= ~FDI_LINK_TRAIN_NONE;

2565

temp &= ~FDI_LINK_TRAIN_NONE;

2566

temp |= FDI_LINK_TRAIN_PATTERN_2;

2566

temp |= FDI_LINK_TRAIN_PATTERN_2;

2567

}

2567

}

2568

I915_WRITE(reg, temp);

2568

I915_WRITE(reg, temp);

2569

2570

POSTING_READ(reg);

2570

POSTING_READ(reg);

2571

udelay(150);

2571

udelay(150);

2572

2573

for (i = 0; i < 4; i++) {

2573

for (i = 0; i < 4; i++) {

2574

reg = FDI_TX_CTL(pipe);

2574

reg = FDI_TX_CTL(pipe);

2575

temp = I915_READ(reg);

2575

temp = I915_READ(reg);

2576

temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;

2576

temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;

2577

temp |= snb_b_fdi_train_param[i];

2577

temp |= snb_b_fdi_train_param[i];

2578

I915_WRITE(reg, temp);

2578

I915_WRITE(reg, temp);

2579

2580

POSTING_READ(reg);

2580

POSTING_READ(reg);

2581

udelay(500);

2581

udelay(500);

2582

2583

reg = FDI_RX_IIR(pipe);

2583

reg = FDI_RX_IIR(pipe);

2584

temp = I915_READ(reg);

2584

temp = I915_READ(reg);

2585

DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

2585

DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

2586

2587

if (temp & FDI_RX_SYMBOL_LOCK) {

2587

if (temp & FDI_RX_SYMBOL_LOCK) {

2588

I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);

2588

I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);

2589

DRM_DEBUG_KMS("FDI train 2 done.\n");

2589

DRM_DEBUG_KMS("FDI train 2 done.\n");

2590

break;

2590

break;

2591

}

2591

}

2592

}

2592

}

2593

if (i == 4)

2593

if (i == 4)

2594

DRM_ERROR("FDI train 2 fail!\n");

2594

DRM_ERROR("FDI train 2 fail!\n");

2595

2596

DRM_DEBUG_KMS("FDI train done.\n");

2596

DRM_DEBUG_KMS("FDI train done.\n");

2597

}

2597

}

2598

2599

/* Manual link training for Ivy Bridge A0 parts */

2599

/* Manual link training for Ivy Bridge A0 parts */

2600

static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)

2600

static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)

2601

{

2601

{

2602

struct drm_device *dev = crtc->dev;

2602

struct drm_device *dev = crtc->dev;

2603

struct drm_i915_private *dev_priv = dev->dev_private;

2603

struct drm_i915_private *dev_priv = dev->dev_private;

2604

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

2604

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

2605

int pipe = intel_crtc->pipe;

2605

int pipe = intel_crtc->pipe;

2606

u32 reg, temp, i;

2606

u32 reg, temp, i;

2607

2608

/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit

2608

/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit

2609

for train result */

2609

for train result */

2610

reg = FDI_RX_IMR(pipe);

2610

reg = FDI_RX_IMR(pipe);

2611

temp = I915_READ(reg);

2611

temp = I915_READ(reg);

2612

temp &= ~FDI_RX_SYMBOL_LOCK;

2612

temp &= ~FDI_RX_SYMBOL_LOCK;

2613

temp &= ~FDI_RX_BIT_LOCK;

2613

temp &= ~FDI_RX_BIT_LOCK;

2614

I915_WRITE(reg, temp);

2614

I915_WRITE(reg, temp);

2615

2616

POSTING_READ(reg);

2616

POSTING_READ(reg);

2617

udelay(150);

2617

udelay(150);

2618

2619

/* enable CPU FDI TX and PCH FDI RX */

2619

/* enable CPU FDI TX and PCH FDI RX */

2620

reg = FDI_TX_CTL(pipe);

2620

reg = FDI_TX_CTL(pipe);

2621

temp = I915_READ(reg);

2621

temp = I915_READ(reg);

2622

temp &= ~(7 << 19);

2622

temp &= ~(7 << 19);

2623

temp |= (intel_crtc->fdi_lanes - 1) << 19;

2623

temp |= (intel_crtc->fdi_lanes - 1) << 19;

2624

temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);

2624

temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);

2625

temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;

2625

temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;

2626

temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;

2626

temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;

2627

temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;

2627

temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;

2628

temp |= FDI_COMPOSITE_SYNC;

2628

temp |= FDI_COMPOSITE_SYNC;

2629

I915_WRITE(reg, temp | FDI_TX_ENABLE);

2629

I915_WRITE(reg, temp | FDI_TX_ENABLE);

2630

2631

reg = FDI_RX_CTL(pipe);

2631

reg = FDI_RX_CTL(pipe);

2632

temp = I915_READ(reg);

2632

temp = I915_READ(reg);

2633

temp &= ~FDI_LINK_TRAIN_AUTO;

2633

temp &= ~FDI_LINK_TRAIN_AUTO;

2634

temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;

2634

temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;

2635

temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;

2635

temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;

2636

temp |= FDI_COMPOSITE_SYNC;

2636

temp |= FDI_COMPOSITE_SYNC;

2637

I915_WRITE(reg, temp | FDI_RX_ENABLE);

2637

I915_WRITE(reg, temp | FDI_RX_ENABLE);

2638

2639

POSTING_READ(reg);

2639

POSTING_READ(reg);

2640

udelay(150);

2640

udelay(150);

2641

2642

if (HAS_PCH_CPT(dev))

2642

if (HAS_PCH_CPT(dev))

2643

cpt_phase_pointer_enable(dev, pipe);

2643

cpt_phase_pointer_enable(dev, pipe);

2644

2645

for (i = 0; i < 4; i++) {

2645

for (i = 0; i < 4; i++) {

2646

reg = FDI_TX_CTL(pipe);

2646

reg = FDI_TX_CTL(pipe);

2647

temp = I915_READ(reg);

2647

temp = I915_READ(reg);

2648

temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;

2648

temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;

2649

temp |= snb_b_fdi_train_param[i];

2649

temp |= snb_b_fdi_train_param[i];

2650

I915_WRITE(reg, temp);

2650

I915_WRITE(reg, temp);

2651

2652

POSTING_READ(reg);

2652

POSTING_READ(reg);

2653

udelay(500);

2653

udelay(500);

2654

2655

reg = FDI_RX_IIR(pipe);

2655

reg = FDI_RX_IIR(pipe);

2656

temp = I915_READ(reg);

2656

temp = I915_READ(reg);

2657

DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

2657

DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

2658

2659

if (temp & FDI_RX_BIT_LOCK ||

2659

if (temp & FDI_RX_BIT_LOCK ||

2660

(I915_READ(reg) & FDI_RX_BIT_LOCK)) {

2660

(I915_READ(reg) & FDI_RX_BIT_LOCK)) {

2661

I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);

2661

I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);

2662

DRM_DEBUG_KMS("FDI train 1 done.\n");

2662

DRM_DEBUG_KMS("FDI train 1 done.\n");

2663

break;

2663

break;

2664

}

2664

}

2665

}

2665

}

2666

if (i == 4)

2666

if (i == 4)

2667

DRM_ERROR("FDI train 1 fail!\n");

2667

DRM_ERROR("FDI train 1 fail!\n");

2668

2669

/* Train 2 */

2669

/* Train 2 */

2670

reg = FDI_TX_CTL(pipe);

2670

reg = FDI_TX_CTL(pipe);

2671

temp = I915_READ(reg);

2671

temp = I915_READ(reg);

2672

temp &= ~FDI_LINK_TRAIN_NONE_IVB;

2672

temp &= ~FDI_LINK_TRAIN_NONE_IVB;

2673

temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;

2673

temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;

2674

temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;

2674

temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;

2675

temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;

2675

temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;

2676

I915_WRITE(reg, temp);

2676

I915_WRITE(reg, temp);

2677

2678

reg = FDI_RX_CTL(pipe);

2678

reg = FDI_RX_CTL(pipe);

2679

temp = I915_READ(reg);

2679

temp = I915_READ(reg);

2680

temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;

2680

temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;

2681

temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;

2681

temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;

2682

I915_WRITE(reg, temp);

2682

I915_WRITE(reg, temp);

2683

2684

POSTING_READ(reg);

2684

POSTING_READ(reg);

2685

udelay(150);

2685

udelay(150);

2686

2687

for (i = 0; i < 4; i++) {

2687

for (i = 0; i < 4; i++) {

2688

reg = FDI_TX_CTL(pipe);

2688

reg = FDI_TX_CTL(pipe);

2689

temp = I915_READ(reg);

2689

temp = I915_READ(reg);

2690

temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;

2690

temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;

2691

temp |= snb_b_fdi_train_param[i];

2691

temp |= snb_b_fdi_train_param[i];

2692

I915_WRITE(reg, temp);

2692

I915_WRITE(reg, temp);

2693

2694

POSTING_READ(reg);

2694

POSTING_READ(reg);

2695

udelay(500);

2695

udelay(500);

2696

2697

reg = FDI_RX_IIR(pipe);

2697

reg = FDI_RX_IIR(pipe);

2698

temp = I915_READ(reg);

2698

temp = I915_READ(reg);

2699

DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

2699

DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

2700

2701

if (temp & FDI_RX_SYMBOL_LOCK) {

2701

if (temp & FDI_RX_SYMBOL_LOCK) {

2702

I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);

2702

I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);

2703

DRM_DEBUG_KMS("FDI train 2 done.\n");

2703

DRM_DEBUG_KMS("FDI train 2 done.\n");

2704

break;

2704

break;

2705

}

2705

}

2706

}

2706

}

2707

if (i == 4)

2707

if (i == 4)

2708

DRM_ERROR("FDI train 2 fail!\n");

2708

DRM_ERROR("FDI train 2 fail!\n");

2709

2710

DRM_DEBUG_KMS("FDI train done.\n");

2710

DRM_DEBUG_KMS("FDI train done.\n");

2711

}

2711

}

2712

2713

static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)

2713

static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)

2714

{

2714

{

2715

struct drm_device *dev = crtc->dev;

2715

struct drm_device *dev = crtc->dev;

2716

struct drm_i915_private *dev_priv = dev->dev_private;

2716

struct drm_i915_private *dev_priv = dev->dev_private;

2717

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

2717

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

2718

int pipe = intel_crtc->pipe;

2718

int pipe = intel_crtc->pipe;

2719

u32 reg, temp;

2719

u32 reg, temp;

2720

2721

/* Write the TU size bits so error detection works */

2721

/* Write the TU size bits so error detection works */

2722

I915_WRITE(FDI_RX_TUSIZE1(pipe),

2722

I915_WRITE(FDI_RX_TUSIZE1(pipe),

2723

I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);

2723

I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);

2724

2725

/* enable PCH FDI RX PLL, wait warmup plus DMI latency */

2725

/* enable PCH FDI RX PLL, wait warmup plus DMI latency */

2726

reg = FDI_RX_CTL(pipe);

2726

reg = FDI_RX_CTL(pipe);

2727

temp = I915_READ(reg);

2727

temp = I915_READ(reg);

2728

temp &= ~((0x7 << 19) | (0x7 << 16));

2728

temp &= ~((0x7 << 19) | (0x7 << 16));

2729

temp |= (intel_crtc->fdi_lanes - 1) << 19;

2729

temp |= (intel_crtc->fdi_lanes - 1) << 19;

2730

temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;

2730

temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;

2731

I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);

2731

I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);

2732

2733

POSTING_READ(reg);

2733

POSTING_READ(reg);

2734

udelay(200);

2734

udelay(200);

2735

2736

/* Switch from Rawclk to PCDclk */

2736

/* Switch from Rawclk to PCDclk */

2737

temp = I915_READ(reg);

2737

temp = I915_READ(reg);

2738

I915_WRITE(reg, temp | FDI_PCDCLK);

2738

I915_WRITE(reg, temp | FDI_PCDCLK);

2739

2740

POSTING_READ(reg);

2740

POSTING_READ(reg);

2741

udelay(200);

2741

udelay(200);

2742

2743

/* Enable CPU FDI TX PLL, always on for Ironlake */

2743

/* Enable CPU FDI TX PLL, always on for Ironlake */

2744

reg = FDI_TX_CTL(pipe);

2744

reg = FDI_TX_CTL(pipe);

2745

temp = I915_READ(reg);

2745

temp = I915_READ(reg);

2746

if ((temp & FDI_TX_PLL_ENABLE) == 0) {

2746

if ((temp & FDI_TX_PLL_ENABLE) == 0) {

2747

I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);

2747

I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);

2748

2749

POSTING_READ(reg);

2749

POSTING_READ(reg);

2750

udelay(100);

2750

udelay(100);

2751

}

2751

}

2752

}

2752

}

2753

2754

static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)

2754

static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)

2755

{

2755

{

2756

struct drm_i915_private *dev_priv = dev->dev_private;

2756

struct drm_i915_private *dev_priv = dev->dev_private;

2757

u32 flags = I915_READ(SOUTH_CHICKEN1);

2757

u32 flags = I915_READ(SOUTH_CHICKEN1);

2758

2759

flags &= ~(FDI_PHASE_SYNC_EN(pipe));

2759

flags &= ~(FDI_PHASE_SYNC_EN(pipe));

2760

I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */

2760

I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */

2761

flags &= ~(FDI_PHASE_SYNC_OVR(pipe));

2761

flags &= ~(FDI_PHASE_SYNC_OVR(pipe));

2762

I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */

2762

I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */

2763

POSTING_READ(SOUTH_CHICKEN1);

2763

POSTING_READ(SOUTH_CHICKEN1);

2764

}

2764

}

2765

static void ironlake_fdi_disable(struct drm_crtc *crtc)

2765

static void ironlake_fdi_disable(struct drm_crtc *crtc)

2766

{

2766

{

2767

struct drm_device *dev = crtc->dev;

2767

struct drm_device *dev = crtc->dev;

2768

struct drm_i915_private *dev_priv = dev->dev_private;

2768

struct drm_i915_private *dev_priv = dev->dev_private;

2769

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

2769

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

2770

int pipe = intel_crtc->pipe;

2770

int pipe = intel_crtc->pipe;

2771

u32 reg, temp;

2771

u32 reg, temp;

2772

2773

/* disable CPU FDI tx and PCH FDI rx */

2773

/* disable CPU FDI tx and PCH FDI rx */

2774

reg = FDI_TX_CTL(pipe);

2774

reg = FDI_TX_CTL(pipe);

2775

temp = I915_READ(reg);

2775

temp = I915_READ(reg);

2776

I915_WRITE(reg, temp & ~FDI_TX_ENABLE);

2776

I915_WRITE(reg, temp & ~FDI_TX_ENABLE);

2777

POSTING_READ(reg);

2777

POSTING_READ(reg);

2778

2779

reg = FDI_RX_CTL(pipe);

2779

reg = FDI_RX_CTL(pipe);

2780

temp = I915_READ(reg);

2780

temp = I915_READ(reg);

2781

temp &= ~(0x7 << 16);

2781

temp &= ~(0x7 << 16);

2782

temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;

2782

temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;

2783

I915_WRITE(reg, temp & ~FDI_RX_ENABLE);

2783

I915_WRITE(reg, temp & ~FDI_RX_ENABLE);

2784

2785

POSTING_READ(reg);

2785

POSTING_READ(reg);

2786

udelay(100);

2786

udelay(100);

2787

2788

/* Ironlake workaround, disable clock pointer after downing FDI */

2788

/* Ironlake workaround, disable clock pointer after downing FDI */

2789

if (HAS_PCH_IBX(dev)) {

2789

if (HAS_PCH_IBX(dev)) {

2790

I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);

2790

I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);

2791

I915_WRITE(FDI_RX_CHICKEN(pipe),

2791

I915_WRITE(FDI_RX_CHICKEN(pipe),

2792

I915_READ(FDI_RX_CHICKEN(pipe) &

2792

I915_READ(FDI_RX_CHICKEN(pipe) &

2793

~FDI_RX_PHASE_SYNC_POINTER_EN));

2793

~FDI_RX_PHASE_SYNC_POINTER_EN));

2794

} else if (HAS_PCH_CPT(dev)) {

2794

} else if (HAS_PCH_CPT(dev)) {

2795

cpt_phase_pointer_disable(dev, pipe);

2795

cpt_phase_pointer_disable(dev, pipe);

2796

}

2796

}

2797

2798

/* still set train pattern 1 */

2798

/* still set train pattern 1 */

2799

reg = FDI_TX_CTL(pipe);

2799

reg = FDI_TX_CTL(pipe);

2800

temp = I915_READ(reg);

2800

temp = I915_READ(reg);

2801

temp &= ~FDI_LINK_TRAIN_NONE;

2801

temp &= ~FDI_LINK_TRAIN_NONE;

2802

temp |= FDI_LINK_TRAIN_PATTERN_1;

2802

temp |= FDI_LINK_TRAIN_PATTERN_1;

2803

I915_WRITE(reg, temp);

2803

I915_WRITE(reg, temp);

2804

2805

reg = FDI_RX_CTL(pipe);

2805

reg = FDI_RX_CTL(pipe);

2806

temp = I915_READ(reg);

2806

temp = I915_READ(reg);

2807

if (HAS_PCH_CPT(dev)) {

2807

if (HAS_PCH_CPT(dev)) {

2808

temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;

2808

temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;

2809

temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;

2809

temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;

2810

} else {

2810

} else {

2811

temp &= ~FDI_LINK_TRAIN_NONE;

2811

temp &= ~FDI_LINK_TRAIN_NONE;

2812

temp |= FDI_LINK_TRAIN_PATTERN_1;

2812

temp |= FDI_LINK_TRAIN_PATTERN_1;

2813

}

2813

}

2814

/* BPC in FDI rx is consistent with that in PIPECONF */

2814

/* BPC in FDI rx is consistent with that in PIPECONF */

2815

temp &= ~(0x07 << 16);

2815

temp &= ~(0x07 << 16);

2816

temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;

2816

temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;

2817

I915_WRITE(reg, temp);

2817

I915_WRITE(reg, temp);

2818

2819

POSTING_READ(reg);

2819

POSTING_READ(reg);

2820

udelay(100);

2820

udelay(100);

2821

}

2821

}

2822

2823

/*

2823

/*

2824

* When we disable a pipe, we need to clear any pending scanline wait events

2824

* When we disable a pipe, we need to clear any pending scanline wait events

2825

* to avoid hanging the ring, which we assume we are waiting on.

2825

* to avoid hanging the ring, which we assume we are waiting on.

2826

*/

2826

*/

2827

static void intel_clear_scanline_wait(struct drm_device *dev)

2827

static void intel_clear_scanline_wait(struct drm_device *dev)

2828

{

2828

{

2829

struct drm_i915_private *dev_priv = dev->dev_private;

2829

struct drm_i915_private *dev_priv = dev->dev_private;

2830

struct intel_ring_buffer *ring;

2830

struct intel_ring_buffer *ring;

2831

u32 tmp;

2831

u32 tmp;

2832

2833

if (IS_GEN2(dev))

2833

if (IS_GEN2(dev))

2834

/* Can't break the hang on i8xx */

2834

/* Can't break the hang on i8xx */

2835

return;

2835

return;

2836

2837

ring = LP_RING(dev_priv);

2837

ring = LP_RING(dev_priv);

2838

tmp = I915_READ_CTL(ring);

2838

tmp = I915_READ_CTL(ring);

2839

if (tmp & RING_WAIT)

2839

if (tmp & RING_WAIT)

2840

I915_WRITE_CTL(ring, tmp);

2840

I915_WRITE_CTL(ring, tmp);

2841

}

2841

}

2842

2843

static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)

2843

static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)

2844

{

2844

{

2845

struct drm_i915_gem_object *obj;

2845

struct drm_i915_gem_object *obj;

2846

struct drm_i915_private *dev_priv;

2846

struct drm_i915_private *dev_priv;

2847

2848

if (crtc->fb == NULL)

2848

if (crtc->fb == NULL)

2849

return;

2849

return;

2850

2851

obj = to_intel_framebuffer(crtc->fb)->obj;

2851

obj = to_intel_framebuffer(crtc->fb)->obj;

2852

dev_priv = crtc->dev->dev_private;

2852

dev_priv = crtc->dev->dev_private;

2853

wait_event(dev_priv->pending_flip_queue,

2853

wait_event(dev_priv->pending_flip_queue,

2854

atomic_read(&obj->pending_flip) == 0);

2854

atomic_read(&obj->pending_flip) == 0);

2855

}

2855

}

2856

2857

static bool intel_crtc_driving_pch(struct drm_crtc *crtc)

2857

static bool intel_crtc_driving_pch(struct drm_crtc *crtc)

2858

{

2858

{

2859

struct drm_device *dev = crtc->dev;

2859

struct drm_device *dev = crtc->dev;

2860

struct drm_mode_config *mode_config = &dev->mode_config;

2860

struct drm_mode_config *mode_config = &dev->mode_config;

2861

struct intel_encoder *encoder;

2861

struct intel_encoder *encoder;

2862

2863

/*

2863

/*

2864

* If there's a non-PCH eDP on this crtc, it must be DP_A, and that

2864

* If there's a non-PCH eDP on this crtc, it must be DP_A, and that

2865

* must be driven by its own crtc; no sharing is possible.

2865

* must be driven by its own crtc; no sharing is possible.

2866

*/

2866

*/

2867

list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {

2867

list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {

2868

if (encoder->base.crtc != crtc)

2868

if (encoder->base.crtc != crtc)

2869

continue;

2869

continue;

2870

2871

switch (encoder->type) {

2871

switch (encoder->type) {

2872

case INTEL_OUTPUT_EDP:

2872

case INTEL_OUTPUT_EDP:

2873

if (!intel_encoder_is_pch_edp(&encoder->base))

2873

if (!intel_encoder_is_pch_edp(&encoder->base))

2874

return false;

2874

return false;

2875

continue;

2875

continue;

2876

}

2876

}

2877

}

2877

}

2878

2879

return true;

2879

return true;

2880

}

2880

}

2881

2882

/*

2882

/*

2883

* Enable PCH resources required for PCH ports:

2883

* Enable PCH resources required for PCH ports:

2884

* - PCH PLLs

2884

* - PCH PLLs

2885

* - FDI training & RX/TX

2885

* - FDI training & RX/TX

2886

* - update transcoder timings

2886

* - update transcoder timings

2887

* - DP transcoding bits

2887

* - DP transcoding bits

2888

* - transcoder

2888

* - transcoder

2889

*/

2889

*/

2890

static void ironlake_pch_enable(struct drm_crtc *crtc)

2890

static void ironlake_pch_enable(struct drm_crtc *crtc)

2891

{

2891

{

2892

struct drm_device *dev = crtc->dev;

2892

struct drm_device *dev = crtc->dev;

2893

struct drm_i915_private *dev_priv = dev->dev_private;

2893

struct drm_i915_private *dev_priv = dev->dev_private;

2894

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

2894

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

2895

int pipe = intel_crtc->pipe;

2895

int pipe = intel_crtc->pipe;

2896

u32 reg, temp, transc_sel;

2896

u32 reg, temp, transc_sel;

2897

2898

/* For PCH output, training FDI link */

2898

/* For PCH output, training FDI link */

2899

dev_priv->display.fdi_link_train(crtc);

2899

dev_priv->display.fdi_link_train(crtc);

2900

2901

intel_enable_pch_pll(dev_priv, pipe);

2901

intel_enable_pch_pll(dev_priv, pipe);

2902

2903

if (HAS_PCH_CPT(dev)) {

2903

if (HAS_PCH_CPT(dev)) {

2904

transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :

2904

transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :

2905

TRANSC_DPLLB_SEL;

2905

TRANSC_DPLLB_SEL;

2906

2907

/* Be sure PCH DPLL SEL is set */

2907

/* Be sure PCH DPLL SEL is set */

2908

temp = I915_READ(PCH_DPLL_SEL);

2908

temp = I915_READ(PCH_DPLL_SEL);

2909

if (pipe == 0) {

2909

if (pipe == 0) {

2910

temp &= ~(TRANSA_DPLLB_SEL);

2910

temp &= ~(TRANSA_DPLLB_SEL);

2911

temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);

2911

temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);

2912

} else if (pipe == 1) {

2912

} else if (pipe == 1) {

2913

temp &= ~(TRANSB_DPLLB_SEL);

2913

temp &= ~(TRANSB_DPLLB_SEL);

2914

temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);

2914

temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);

2915

} else if (pipe == 2) {

2915

} else if (pipe == 2) {

2916

temp &= ~(TRANSC_DPLLB_SEL);

2916

temp &= ~(TRANSC_DPLLB_SEL);

2917

temp |= (TRANSC_DPLL_ENABLE | transc_sel);

2917

temp |= (TRANSC_DPLL_ENABLE | transc_sel);

2918

}

2918

}

2919

I915_WRITE(PCH_DPLL_SEL, temp);

2919

I915_WRITE(PCH_DPLL_SEL, temp);

2920

}

2920

}

2921

2922

/* set transcoder timing, panel must allow it */

2922

/* set transcoder timing, panel must allow it */

2923

assert_panel_unlocked(dev_priv, pipe);

2923

assert_panel_unlocked(dev_priv, pipe);

2924

I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));

2924

I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));

2925

I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));

2925

I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));

2926

I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));

2926

I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));

2927

2928

I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));

2928

I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));

2929

I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));

2929

I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));

2930

I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));

2930

I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));

2931

2932

intel_fdi_normal_train(crtc);

2932

intel_fdi_normal_train(crtc);

2933

2934

/* For PCH DP, enable TRANS_DP_CTL */

2934

/* For PCH DP, enable TRANS_DP_CTL */

2935

if (HAS_PCH_CPT(dev) &&

2935

if (HAS_PCH_CPT(dev) &&

2936

(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||

2936

(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||

2937

intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {

2937

intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {

2938

u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;

2938

u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;

2939

reg = TRANS_DP_CTL(pipe);

2939

reg = TRANS_DP_CTL(pipe);

2940

temp = I915_READ(reg);

2940

temp = I915_READ(reg);

2941

temp &= ~(TRANS_DP_PORT_SEL_MASK |

2941

temp &= ~(TRANS_DP_PORT_SEL_MASK |

2942

TRANS_DP_SYNC_MASK |

2942

TRANS_DP_SYNC_MASK |

2943

TRANS_DP_BPC_MASK);

2943

TRANS_DP_BPC_MASK);

2944

temp |= (TRANS_DP_OUTPUT_ENABLE |

2944

temp |= (TRANS_DP_OUTPUT_ENABLE |

2945

TRANS_DP_ENH_FRAMING);

2945

TRANS_DP_ENH_FRAMING);

2946

temp |= bpc << 9; /* same format but at 11:9 */

2946

temp |= bpc << 9; /* same format but at 11:9 */

2947

2948

if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)

2948

if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)

2949

temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;

2949

temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;

2950

if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)

2950

if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)

2951

temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;

2951

temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;

2952

2953

switch (intel_trans_dp_port_sel(crtc)) {

2953

switch (intel_trans_dp_port_sel(crtc)) {

2954

case PCH_DP_B:

2954

case PCH_DP_B:

2955

temp |= TRANS_DP_PORT_SEL_B;

2955

temp |= TRANS_DP_PORT_SEL_B;

2956

break;

2956

break;

2957

case PCH_DP_C:

2957

case PCH_DP_C:

2958

temp |= TRANS_DP_PORT_SEL_C;

2958

temp |= TRANS_DP_PORT_SEL_C;

2959

break;

2959

break;

2960

case PCH_DP_D:

2960

case PCH_DP_D:

2961

temp |= TRANS_DP_PORT_SEL_D;

2961

temp |= TRANS_DP_PORT_SEL_D;

2962

break;

2962

break;

2963

default:

2963

default:

2964

DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");

2964

DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");

2965

temp |= TRANS_DP_PORT_SEL_B;

2965

temp |= TRANS_DP_PORT_SEL_B;

2966

break;

2966

break;

2967

}

2967

}

2968

2969

I915_WRITE(reg, temp);

2969

I915_WRITE(reg, temp);

2970

}

2970

}

2971

2972

intel_enable_transcoder(dev_priv, pipe);

2972

intel_enable_transcoder(dev_priv, pipe);

2973

}

2973

}

2974

2975

void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)

2975

void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)

2976

{

2976

{

2977

struct drm_i915_private *dev_priv = dev->dev_private;

2977

struct drm_i915_private *dev_priv = dev->dev_private;

2978

int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);

2978

int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);

2979

u32 temp;

2979

u32 temp;

2980

2981

temp = I915_READ(dslreg);

2981

temp = I915_READ(dslreg);

2982

udelay(500);

2982

udelay(500);

2983

if (wait_for(I915_READ(dslreg) != temp, 5)) {

2983

if (wait_for(I915_READ(dslreg) != temp, 5)) {

2984

/* Without this, mode sets may fail silently on FDI */

2984

/* Without this, mode sets may fail silently on FDI */

2985

I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);

2985

I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);

2986

udelay(250);

2986

udelay(250);

2987

I915_WRITE(tc2reg, 0);

2987

I915_WRITE(tc2reg, 0);

2988

if (wait_for(I915_READ(dslreg) != temp, 5))

2988

if (wait_for(I915_READ(dslreg) != temp, 5))

2989

DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);

2989

DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);

2990

}

2990

}

2991

}

2991

}

2992

2993

static void ironlake_crtc_enable(struct drm_crtc *crtc)

2993

static void ironlake_crtc_enable(struct drm_crtc *crtc)

2994

{

2994

{

2995

struct drm_device *dev = crtc->dev;

2995

struct drm_device *dev = crtc->dev;

2996

struct drm_i915_private *dev_priv = dev->dev_private;

2996

struct drm_i915_private *dev_priv = dev->dev_private;

2997

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

2997

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

2998

int pipe = intel_crtc->pipe;

2998

int pipe = intel_crtc->pipe;

2999

int plane = intel_crtc->plane;

2999

int plane = intel_crtc->plane;

3000

u32 temp;

3000

u32 temp;

3001

bool is_pch_port;

3001

bool is_pch_port;

3002

3003

if (intel_crtc->active)

3003

if (intel_crtc->active)

3004

return;

3004

return;

3005

3006

intel_crtc->active = true;

3006

intel_crtc->active = true;

3007

intel_update_watermarks(dev);

3007

intel_update_watermarks(dev);

3008

3009

if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {

3009

if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {

3010

temp = I915_READ(PCH_LVDS);

3010

temp = I915_READ(PCH_LVDS);

3011

if ((temp & LVDS_PORT_EN) == 0)

3011

if ((temp & LVDS_PORT_EN) == 0)

3012

I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);

3012

I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);

3013

}

3013

}

3014

3015

is_pch_port = intel_crtc_driving_pch(crtc);

3015

is_pch_port = intel_crtc_driving_pch(crtc);

3016

3017

if (is_pch_port)

3017

if (is_pch_port)

3018

ironlake_fdi_pll_enable(crtc);

3018

ironlake_fdi_pll_enable(crtc);

3019

else

3019

else

3020

ironlake_fdi_disable(crtc);

3020

ironlake_fdi_disable(crtc);

3021

3022

/* Enable panel fitting for LVDS */

3022

/* Enable panel fitting for LVDS */

3023

if (dev_priv->pch_pf_size &&

3023

if (dev_priv->pch_pf_size &&

3024

(intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {

3024

(intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {

3025

/* Force use of hard-coded filter coefficients

3025

/* Force use of hard-coded filter coefficients

3026

* as some pre-programmed values are broken,

3026

* as some pre-programmed values are broken,

3027

* e.g. x201.

3027

* e.g. x201.

3028

*/

3028

*/

3029

I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);

3029

I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);

3030

I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);

3030

I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);

3031

I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);

3031

I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);

3032

}

3032

}

3033

3034

/*

3034

/*

3035

* On ILK+ LUT must be loaded before the pipe is running but with

3035

* On ILK+ LUT must be loaded before the pipe is running but with

3036

* clocks enabled

3036

* clocks enabled

3037

*/

3037

*/

3038

intel_crtc_load_lut(crtc);

3038

intel_crtc_load_lut(crtc);

3039

3040

intel_enable_pipe(dev_priv, pipe, is_pch_port);

3040

intel_enable_pipe(dev_priv, pipe, is_pch_port);

3041

intel_enable_plane(dev_priv, plane, pipe);

3041

intel_enable_plane(dev_priv, plane, pipe);

3042

3043

if (is_pch_port)

3043

if (is_pch_port)

3044

ironlake_pch_enable(crtc);

3044

ironlake_pch_enable(crtc);

3045

3046

mutex_lock(&dev->struct_mutex);

3046

mutex_lock(&dev->struct_mutex);

3047

intel_update_fbc(dev);

3047

intel_update_fbc(dev);

3048

mutex_unlock(&dev->struct_mutex);

3048

mutex_unlock(&dev->struct_mutex);

3049

3050

intel_crtc_update_cursor(crtc, true);

3050

intel_crtc_update_cursor(crtc, true);

3051

}

3051

}

3052

3053

static void ironlake_crtc_disable(struct drm_crtc *crtc)

3053

static void ironlake_crtc_disable(struct drm_crtc *crtc)

3054

{

3054

{

3055

struct drm_device *dev = crtc->dev;

3055

struct drm_device *dev = crtc->dev;

3056

struct drm_i915_private *dev_priv = dev->dev_private;

3056

struct drm_i915_private *dev_priv = dev->dev_private;

3057

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

3057

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

3058

int pipe = intel_crtc->pipe;

3058

int pipe = intel_crtc->pipe;

3059

int plane = intel_crtc->plane;

3059

int plane = intel_crtc->plane;

3060

u32 reg, temp;

3060

u32 reg, temp;

3061

3062

if (!intel_crtc->active)

3062

if (!intel_crtc->active)

3063

return;

3063

return;

3064

3065

intel_crtc_wait_for_pending_flips(crtc);

3065

intel_crtc_wait_for_pending_flips(crtc);

3066

drm_vblank_off(dev, pipe);

3066

drm_vblank_off(dev, pipe);

3067

intel_crtc_update_cursor(crtc, false);

3067

intel_crtc_update_cursor(crtc, false);

3068

3069

intel_disable_plane(dev_priv, plane, pipe);

3069

intel_disable_plane(dev_priv, plane, pipe);

3070

3071

if (dev_priv->cfb_plane == plane)

3071

if (dev_priv->cfb_plane == plane)

3072

intel_disable_fbc(dev);

3072

intel_disable_fbc(dev);

3073

3074

intel_disable_pipe(dev_priv, pipe);

3074

intel_disable_pipe(dev_priv, pipe);

3075

3076

/* Disable PF */

3076

/* Disable PF */

3077

I915_WRITE(PF_CTL(pipe), 0);

3077

I915_WRITE(PF_CTL(pipe), 0);

3078

I915_WRITE(PF_WIN_SZ(pipe), 0);

3078

I915_WRITE(PF_WIN_SZ(pipe), 0);

3079

3080

ironlake_fdi_disable(crtc);

3080

ironlake_fdi_disable(crtc);

3081

3082

/* This is a horrible layering violation; we should be doing this in

3082

/* This is a horrible layering violation; we should be doing this in

3083

* the connector/encoder ->prepare instead, but we don't always have

3083

* the connector/encoder ->prepare instead, but we don't always have

3084

* enough information there about the config to know whether it will

3084

* enough information there about the config to know whether it will

3085

* actually be necessary or just cause undesired flicker.

3085

* actually be necessary or just cause undesired flicker.

3086

*/

3086

*/

3087

intel_disable_pch_ports(dev_priv, pipe);

3087

intel_disable_pch_ports(dev_priv, pipe);

3088

3089

intel_disable_transcoder(dev_priv, pipe);

3089

intel_disable_transcoder(dev_priv, pipe);

3090

3091

if (HAS_PCH_CPT(dev)) {

3091

if (HAS_PCH_CPT(dev)) {

3092

/* disable TRANS_DP_CTL */

3092

/* disable TRANS_DP_CTL */

3093

reg = TRANS_DP_CTL(pipe);

3093

reg = TRANS_DP_CTL(pipe);

3094

temp = I915_READ(reg);

3094

temp = I915_READ(reg);

3095

temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);

3095

temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);

3096

temp |= TRANS_DP_PORT_SEL_NONE;

3096

temp |= TRANS_DP_PORT_SEL_NONE;

3097

I915_WRITE(reg, temp);

3097

I915_WRITE(reg, temp);

3098

3099

/* disable DPLL_SEL */

3099

/* disable DPLL_SEL */

3100

temp = I915_READ(PCH_DPLL_SEL);

3100

temp = I915_READ(PCH_DPLL_SEL);

3101

switch (pipe) {

3101

switch (pipe) {

3102

case 0:

3102

case 0:

3103

temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);

3103

temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);

3104

break;

3104

break;

3105

case 1:

3105

case 1:

3106

temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);

3106

temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);

3107

break;

3107

break;

3108

case 2:

3108

case 2:

3109

/* C shares PLL A or B */

3109

/* C shares PLL A or B */

3110

temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);

3110

temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);

3111

break;

3111

break;

3112

default:

3112

default:

3113

BUG(); /* wtf */

3113

BUG(); /* wtf */

3114

}

3114

}

3115

I915_WRITE(PCH_DPLL_SEL, temp);

3115

I915_WRITE(PCH_DPLL_SEL, temp);

3116

}

3116

}

3117

3118

/* disable PCH DPLL */

3118

/* disable PCH DPLL */

3119

if (!intel_crtc->no_pll)

3119

if (!intel_crtc->no_pll)

3120

intel_disable_pch_pll(dev_priv, pipe);

3120

intel_disable_pch_pll(dev_priv, pipe);

3121

3122

/* Switch from PCDclk to Rawclk */

3122

/* Switch from PCDclk to Rawclk */

3123

reg = FDI_RX_CTL(pipe);

3123

reg = FDI_RX_CTL(pipe);

3124

temp = I915_READ(reg);

3124

temp = I915_READ(reg);

3125

I915_WRITE(reg, temp & ~FDI_PCDCLK);

3125

I915_WRITE(reg, temp & ~FDI_PCDCLK);

3126

3127

/* Disable CPU FDI TX PLL */

3127

/* Disable CPU FDI TX PLL */

3128

reg = FDI_TX_CTL(pipe);

3128

reg = FDI_TX_CTL(pipe);

3129

temp = I915_READ(reg);

3129

temp = I915_READ(reg);

3130

I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);

3130

I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);

3131

3132

POSTING_READ(reg);

3132

POSTING_READ(reg);

3133

udelay(100);

3133

udelay(100);

3134

3135

reg = FDI_RX_CTL(pipe);

3135

reg = FDI_RX_CTL(pipe);

3136

temp = I915_READ(reg);

3136

temp = I915_READ(reg);

3137

I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);

3137

I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);

3138

3139

/* Wait for the clocks to turn off. */

3139

/* Wait for the clocks to turn off. */

3140

POSTING_READ(reg);

3140

POSTING_READ(reg);

3141

udelay(100);

3141

udelay(100);

3142

3143

intel_crtc->active = false;

3143

intel_crtc->active = false;

3144

intel_update_watermarks(dev);

3144

intel_update_watermarks(dev);

3145

3146

mutex_lock(&dev->struct_mutex);

3146

mutex_lock(&dev->struct_mutex);

3147

intel_update_fbc(dev);

3147

intel_update_fbc(dev);

3148

intel_clear_scanline_wait(dev);

3148

intel_clear_scanline_wait(dev);

3149

mutex_unlock(&dev->struct_mutex);

3149

mutex_unlock(&dev->struct_mutex);

3150

}

3150

}

3151

3152

static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)

3152

static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)

3153

{

3153

{

3154

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

3154

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

3155

int pipe = intel_crtc->pipe;

3155

int pipe = intel_crtc->pipe;

3156

int plane = intel_crtc->plane;

3156

int plane = intel_crtc->plane;

3157

3158

/* XXX: When our outputs are all unaware of DPMS modes other than off

3158

/* XXX: When our outputs are all unaware of DPMS modes other than off

3159

* and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.

3159

* and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.

3160

*/

3160

*/

3161

switch (mode) {

3161

switch (mode) {

3162

case DRM_MODE_DPMS_ON:

3162

case DRM_MODE_DPMS_ON:

3163

case DRM_MODE_DPMS_STANDBY:

3163

case DRM_MODE_DPMS_STANDBY:

3164

case DRM_MODE_DPMS_SUSPEND:

3164

case DRM_MODE_DPMS_SUSPEND:

3165

DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);

3165

DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);

3166

ironlake_crtc_enable(crtc);

3166

ironlake_crtc_enable(crtc);

3167

break;

3167

break;

3168

3169

case DRM_MODE_DPMS_OFF:

3169

case DRM_MODE_DPMS_OFF:

3170

DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);

3170

DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);

3171

ironlake_crtc_disable(crtc);

3171

ironlake_crtc_disable(crtc);

3172

break;

3172

break;

3173

}

3173

}

3174

}

3174

}

3175

3176

static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)

3176

static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)

3177

{

3177

{

3178

if (!enable && intel_crtc->overlay) {

3178

if (!enable && intel_crtc->overlay) {

3179

struct drm_device *dev = intel_crtc->base.dev;

3179

struct drm_device *dev = intel_crtc->base.dev;

3180

struct drm_i915_private *dev_priv = dev->dev_private;

3180

struct drm_i915_private *dev_priv = dev->dev_private;

3181

3182

mutex_lock(&dev->struct_mutex);

3182

mutex_lock(&dev->struct_mutex);

3183

dev_priv->mm.interruptible = false;

3183

dev_priv->mm.interruptible = false;

3184

(void) intel_overlay_switch_off(intel_crtc->overlay);

3184

(void) intel_overlay_switch_off(intel_crtc->overlay);

3185

dev_priv->mm.interruptible = true;

3185

dev_priv->mm.interruptible = true;

3186

mutex_unlock(&dev->struct_mutex);

3186

mutex_unlock(&dev->struct_mutex);

3187

}

3187

}

3188

3189

/* Let userspace switch the overlay on again. In most cases userspace

3189

/* Let userspace switch the overlay on again. In most cases userspace

3190

* has to recompute where to put it anyway.

3190

* has to recompute where to put it anyway.

3191

*/

3191

*/

3192

}

3192

}

3193

3194

static void i9xx_crtc_enable(struct drm_crtc *crtc)

3194

static void i9xx_crtc_enable(struct drm_crtc *crtc)

3195

{

3195

{

3196

struct drm_device *dev = crtc->dev;

3196

struct drm_device *dev = crtc->dev;

3197

struct drm_i915_private *dev_priv = dev->dev_private;

3197

struct drm_i915_private *dev_priv = dev->dev_private;

3198

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

3198

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

3199

int pipe = intel_crtc->pipe;

3199

int pipe = intel_crtc->pipe;

3200

int plane = intel_crtc->plane;

3200

int plane = intel_crtc->plane;

3201

3202

if (intel_crtc->active)

3202

if (intel_crtc->active)

3203

return;

3203

return;

3204

3205

intel_crtc->active = true;

3205

intel_crtc->active = true;

3206

intel_update_watermarks(dev);

3206

intel_update_watermarks(dev);

3207

3208

intel_enable_pll(dev_priv, pipe);

3208

intel_enable_pll(dev_priv, pipe);

3209

intel_enable_pipe(dev_priv, pipe, false);

3209

intel_enable_pipe(dev_priv, pipe, false);

3210

intel_enable_plane(dev_priv, plane, pipe);

3210

intel_enable_plane(dev_priv, plane, pipe);

3211

3212

intel_crtc_load_lut(crtc);

3212

intel_crtc_load_lut(crtc);

3213

intel_update_fbc(dev);

3213

intel_update_fbc(dev);

3214

3215

/* Give the overlay scaler a chance to enable if it's on this pipe */

3215

/* Give the overlay scaler a chance to enable if it's on this pipe */

3216

intel_crtc_dpms_overlay(intel_crtc, true);

3216

intel_crtc_dpms_overlay(intel_crtc, true);

3217

intel_crtc_update_cursor(crtc, true);

3217

intel_crtc_update_cursor(crtc, true);

3218

}

3218

}

3219

3220

static void i9xx_crtc_disable(struct drm_crtc *crtc)

3220

static void i9xx_crtc_disable(struct drm_crtc *crtc)

3221

{

3221

{

3222

struct drm_device *dev = crtc->dev;

3222

struct drm_device *dev = crtc->dev;

3223

struct drm_i915_private *dev_priv = dev->dev_private;

3223

struct drm_i915_private *dev_priv = dev->dev_private;

3224

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

3224

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

3225

int pipe = intel_crtc->pipe;

3225

int pipe = intel_crtc->pipe;

3226

int plane = intel_crtc->plane;

3226

int plane = intel_crtc->plane;

3227

3228

if (!intel_crtc->active)

3228

if (!intel_crtc->active)

3229

return;

3229

return;

3230

3231

/* Give the overlay scaler a chance to disable if it's on this pipe */

3231

/* Give the overlay scaler a chance to disable if it's on this pipe */

3232

intel_crtc_wait_for_pending_flips(crtc);

3232

intel_crtc_wait_for_pending_flips(crtc);

3233

drm_vblank_off(dev, pipe);

3233

drm_vblank_off(dev, pipe);

3234

intel_crtc_dpms_overlay(intel_crtc, false);

3234

intel_crtc_dpms_overlay(intel_crtc, false);

3235

intel_crtc_update_cursor(crtc, false);

3235

intel_crtc_update_cursor(crtc, false);

3236

3237

if (dev_priv->cfb_plane == plane)

3237

if (dev_priv->cfb_plane == plane)

3238

intel_disable_fbc(dev);

3238

intel_disable_fbc(dev);

3239

3240

intel_disable_plane(dev_priv, plane, pipe);

3240

intel_disable_plane(dev_priv, plane, pipe);

3241

intel_disable_pipe(dev_priv, pipe);

3241

intel_disable_pipe(dev_priv, pipe);

3242

intel_disable_pll(dev_priv, pipe);

3242

intel_disable_pll(dev_priv, pipe);

3243

3244

intel_crtc->active = false;

3244

intel_crtc->active = false;

3245

intel_update_fbc(dev);

3245

intel_update_fbc(dev);

3246

intel_update_watermarks(dev);

3246

intel_update_watermarks(dev);

3247

intel_clear_scanline_wait(dev);

3247

intel_clear_scanline_wait(dev);

3248

}

3248

}

3249

3250

static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)

3250

static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)

3251

{

3251

{

3252

/* XXX: When our outputs are all unaware of DPMS modes other than off

3252

/* XXX: When our outputs are all unaware of DPMS modes other than off

3253

* and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.

3253

* and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.

3254

*/

3254

*/

3255

switch (mode) {

3255

switch (mode) {

3256

case DRM_MODE_DPMS_ON:

3256

case DRM_MODE_DPMS_ON:

3257

case DRM_MODE_DPMS_STANDBY:

3257

case DRM_MODE_DPMS_STANDBY:

3258

case DRM_MODE_DPMS_SUSPEND:

3258

case DRM_MODE_DPMS_SUSPEND:

3259

i9xx_crtc_enable(crtc);

3259

i9xx_crtc_enable(crtc);

3260

break;

3260

break;

3261

case DRM_MODE_DPMS_OFF:

3261

case DRM_MODE_DPMS_OFF:

3262

i9xx_crtc_disable(crtc);

3262

i9xx_crtc_disable(crtc);

3263

break;

3263

break;

3264

}

3264

}

3265

}

3265

}

3266

3267

/**

3267

/**

3268

* Sets the power management mode of the pipe and plane.

3268

* Sets the power management mode of the pipe and plane.

3269

*/

3269

*/

3270

static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)

3270

static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)

3271

{

3271

{

3272

struct drm_device *dev = crtc->dev;

3272

struct drm_device *dev = crtc->dev;

3273

struct drm_i915_private *dev_priv = dev->dev_private;

3273

struct drm_i915_private *dev_priv = dev->dev_private;

3274

struct drm_i915_master_private *master_priv;

3274

struct drm_i915_master_private *master_priv;

3275

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

3275

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

3276

int pipe = intel_crtc->pipe;

3276

int pipe = intel_crtc->pipe;

3277

bool enabled;

3277

bool enabled;

3278

3279

if (intel_crtc->dpms_mode == mode)

3279

if (intel_crtc->dpms_mode == mode)

3280

return;

3280

return;

3281

3282

intel_crtc->dpms_mode = mode;

3282

intel_crtc->dpms_mode = mode;

3283

3284

dev_priv->display.dpms(crtc, mode);

3284

dev_priv->display.dpms(crtc, mode);

3285

3286

if (!dev->primary->master)

3286

if (!dev->primary->master)

3287

return;

3287

return;

3288

3289

master_priv = dev->primary->master->driver_priv;

3289

master_priv = dev->primary->master->driver_priv;

3290

if (!master_priv->sarea_priv)

3290

if (!master_priv->sarea_priv)

3291

return;

3291

return;

3292

3293

enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;

3293

enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;

3294

3295

switch (pipe) {

3295

switch (pipe) {

3296

case 0:

3296

case 0:

3297

master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;

3297

master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;

3298

master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;

3298

master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;

3299

break;

3299

break;

3300

case 1:

3300

case 1:

3301

master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;

3301

master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;

3302

master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;

3302

master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;

3303

break;

3303

break;

3304

default:

3304

default:

3305

DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));

3305

DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));

3306

break;

3306

break;

3307

}

3307

}

3308

}

3308

}

3309

3310

static void intel_crtc_disable(struct drm_crtc *crtc)

3310

static void intel_crtc_disable(struct drm_crtc *crtc)

3311

{

3311

{

3312

struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;

3312

struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;

3313

struct drm_device *dev = crtc->dev;

3313

struct drm_device *dev = crtc->dev;

3314

3315

crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);

3315

crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);

3316

3317

if (crtc->fb) {

3317

if (crtc->fb) {

3318

mutex_lock(&dev->struct_mutex);

3318

mutex_lock(&dev->struct_mutex);

3319

i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);

3319

i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);

3320

mutex_unlock(&dev->struct_mutex);

3320

mutex_unlock(&dev->struct_mutex);

3321

}

3321

}

3322

}

3322

}

3323

3324

/* Prepare for a mode set.

3324

/* Prepare for a mode set.

3325

*

3325

*

3326

* Note we could be a lot smarter here. We need to figure out which outputs

3326

* Note we could be a lot smarter here. We need to figure out which outputs

3327

* will be enabled, which disabled (in short, how the config will changes)

3327

* will be enabled, which disabled (in short, how the config will changes)

3328

* and perform the minimum necessary steps to accomplish that, e.g. updating

3328

* and perform the minimum necessary steps to accomplish that, e.g. updating

3329

* watermarks, FBC configuration, making sure PLLs are programmed correctly,

3329

* watermarks, FBC configuration, making sure PLLs are programmed correctly,

3330

* panel fitting is in the proper state, etc.

3330

* panel fitting is in the proper state, etc.

3331

*/

3331

*/

3332

static void i9xx_crtc_prepare(struct drm_crtc *crtc)

3332

static void i9xx_crtc_prepare(struct drm_crtc *crtc)

3333

{

3333

{

3334

i9xx_crtc_disable(crtc);

3334

i9xx_crtc_disable(crtc);

3335

}

3335

}

3336

3337

static void i9xx_crtc_commit(struct drm_crtc *crtc)

3337

static void i9xx_crtc_commit(struct drm_crtc *crtc)

3338

{

3338

{

3339

i9xx_crtc_enable(crtc);

3339

i9xx_crtc_enable(crtc);

3340

}

3340

}

3341

3342

static void ironlake_crtc_prepare(struct drm_crtc *crtc)

3342

static void ironlake_crtc_prepare(struct drm_crtc *crtc)

3343

{

3343

{

3344

ironlake_crtc_disable(crtc);

3344

ironlake_crtc_disable(crtc);

3345

}

3345

}

3346

3347

static void ironlake_crtc_commit(struct drm_crtc *crtc)

3347

static void ironlake_crtc_commit(struct drm_crtc *crtc)

3348

{

3348

{

3349

ironlake_crtc_enable(crtc);

3349

ironlake_crtc_enable(crtc);

3350

}

3350

}

3351

3352

void intel_encoder_prepare(struct drm_encoder *encoder)

3352

void intel_encoder_prepare(struct drm_encoder *encoder)

3353

{

3353

{

3354

struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;

3354

struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;

3355

/* lvds has its own version of prepare see intel_lvds_prepare */

3355

/* lvds has its own version of prepare see intel_lvds_prepare */

3356

encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);

3356

encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);

3357

}

3357

}

3358

3359

void intel_encoder_commit(struct drm_encoder *encoder)

3359

void intel_encoder_commit(struct drm_encoder *encoder)

3360

{

3360

{

3361

struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;

3361

struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;

3362

struct drm_device *dev = encoder->dev;

3362

struct drm_device *dev = encoder->dev;

3363

struct intel_encoder *intel_encoder = to_intel_encoder(encoder);

3363

struct intel_encoder *intel_encoder = to_intel_encoder(encoder);

3364

struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);

3364

struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);

3365

3366

/* lvds has its own version of commit see intel_lvds_commit */

3366

/* lvds has its own version of commit see intel_lvds_commit */

3367

encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);

3367

encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);

3368

3369

if (HAS_PCH_CPT(dev))

3369

if (HAS_PCH_CPT(dev))

3370

intel_cpt_verify_modeset(dev, intel_crtc->pipe);

3370

intel_cpt_verify_modeset(dev, intel_crtc->pipe);

3371

}

3371

}

3372

3373

void intel_encoder_destroy(struct drm_encoder *encoder)

3373

void intel_encoder_destroy(struct drm_encoder *encoder)

3374

{

3374

{

3375

struct intel_encoder *intel_encoder = to_intel_encoder(encoder);

3375

struct intel_encoder *intel_encoder = to_intel_encoder(encoder);

3376

3377

drm_encoder_cleanup(encoder);

3377

drm_encoder_cleanup(encoder);

3378

kfree(intel_encoder);

3378

kfree(intel_encoder);

3379

}

3379

}

3380

3381

static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,

3381

static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,

3382

struct drm_display_mode *mode,

3382

struct drm_display_mode *mode,

3383

struct drm_display_mode *adjusted_mode)

3383

struct drm_display_mode *adjusted_mode)

3384

{

3384

{

3385

struct drm_device *dev = crtc->dev;

3385

struct drm_device *dev = crtc->dev;

3386

3387

if (HAS_PCH_SPLIT(dev)) {

3387

if (HAS_PCH_SPLIT(dev)) {

3388

/* FDI link clock is fixed at 2.7G */

3388

/* FDI link clock is fixed at 2.7G */

3389

if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)

3389

if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)

3390

return false;

3390

return false;

3391

}

3391

}

3392

3393

/* XXX some encoders set the crtcinfo, others don't.

3393

/* XXX some encoders set the crtcinfo, others don't.

3394

* Obviously we need some form of conflict resolution here...

3394

* Obviously we need some form of conflict resolution here...

3395

*/

3395

*/

3396

if (adjusted_mode->crtc_htotal == 0)

3396

if (adjusted_mode->crtc_htotal == 0)

3397

drm_mode_set_crtcinfo(adjusted_mode, 0);

3397

drm_mode_set_crtcinfo(adjusted_mode, 0);

3398

3399

return true;

3399

return true;

3400

}

3400

}

3401

3402

static int i945_get_display_clock_speed(struct drm_device *dev)

3402

static int i945_get_display_clock_speed(struct drm_device *dev)

3403

{

3403

{

3404

return 400000;

3404

return 400000;

3405

}

3405

}

3406

3407

static int i915_get_display_clock_speed(struct drm_device *dev)

3407

static int i915_get_display_clock_speed(struct drm_device *dev)

3408

{

3408

{

3409

return 333000;

3409

return 333000;

3410

}

3410

}

3411

3412

static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)

3412

static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)

3413

{

3413

{

3414

return 200000;

3414

return 200000;

3415

}

3415

}

3416

3417

static int i915gm_get_display_clock_speed(struct drm_device *dev)

3417

static int i915gm_get_display_clock_speed(struct drm_device *dev)

3418

{

3418

{

3419

u16 gcfgc = 0;

3419

u16 gcfgc = 0;

3420

3421

pci_read_config_word(dev->pdev, GCFGC, &gcfgc);

3421

pci_read_config_word(dev->pdev, GCFGC, &gcfgc);

3422

3423

if (gcfgc & GC_LOW_FREQUENCY_ENABLE)

3423

if (gcfgc & GC_LOW_FREQUENCY_ENABLE)

3424

return 133000;

3424

return 133000;

3425

else {

3425

else {

3426

switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {

3426

switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {

3427

case GC_DISPLAY_CLOCK_333_MHZ:

3427

case GC_DISPLAY_CLOCK_333_MHZ:

3428

return 333000;

3428

return 333000;

3429

default:

3429

default:

3430

case GC_DISPLAY_CLOCK_190_200_MHZ:

3430

case GC_DISPLAY_CLOCK_190_200_MHZ:

3431

return 190000;

3431

return 190000;

3432

}

3432

}

3433

}

3433

}

3434

}

3434

}

3435

3436

static int i865_get_display_clock_speed(struct drm_device *dev)

3436

static int i865_get_display_clock_speed(struct drm_device *dev)

3437

{

3437

{

3438

return 266000;

3438

return 266000;

3439

}

3439

}

3440

3441

static int i855_get_display_clock_speed(struct drm_device *dev)

3441

static int i855_get_display_clock_speed(struct drm_device *dev)

3442

{

3442

{

3443

u16 hpllcc = 0;

3443

u16 hpllcc = 0;

3444

/* Assume that the hardware is in the high speed state. This

3444

/* Assume that the hardware is in the high speed state. This

3445

* should be the default.

3445

* should be the default.

3446

*/

3446

*/

3447

switch (hpllcc & GC_CLOCK_CONTROL_MASK) {

3447

switch (hpllcc & GC_CLOCK_CONTROL_MASK) {

3448

case GC_CLOCK_133_200:

3448

case GC_CLOCK_133_200:

3449

case GC_CLOCK_100_200:

3449

case GC_CLOCK_100_200:

3450

return 200000;

3450

return 200000;

3451

case GC_CLOCK_166_250:

3451

case GC_CLOCK_166_250:

3452

return 250000;

3452

return 250000;

3453

case GC_CLOCK_100_133:

3453

case GC_CLOCK_100_133:

3454

return 133000;

3454

return 133000;

3455

}

3455

}

3456

3457

/* Shouldn't happen */

3457

/* Shouldn't happen */

3458

return 0;

3458

return 0;

3459

}

3459

}

3460

3461

static int i830_get_display_clock_speed(struct drm_device *dev)

3461

static int i830_get_display_clock_speed(struct drm_device *dev)

3462

{

3462

{

3463

return 133000;

3463

return 133000;

3464

}

3464

}

3465

3466

struct fdi_m_n {

3466

struct fdi_m_n {

3467

u32 tu;

3467

u32 tu;

3468

u32 gmch_m;

3468

u32 gmch_m;

3469

u32 gmch_n;

3469

u32 gmch_n;

3470

u32 link_m;

3470

u32 link_m;

3471

u32 link_n;

3471

u32 link_n;

3472

};

3472

};

3473

3474

static void

3474

static void

3475

fdi_reduce_ratio(u32 *num, u32 *den)

3475

fdi_reduce_ratio(u32 *num, u32 *den)

3476

{

3476

{

3477

while (*num > 0xffffff || *den > 0xffffff) {

3477

while (*num > 0xffffff || *den > 0xffffff) {

3478

*num >>= 1;

3478

*num >>= 1;

3479

*den >>= 1;

3479

*den >>= 1;

3480

}

3480

}

3481

}

3481

}

3482

3483

static void

3483

static void

3484

ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,

3484

ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,

3485

int link_clock, struct fdi_m_n *m_n)

3485

int link_clock, struct fdi_m_n *m_n)

3486

{

3486

{

3487

m_n->tu = 64; /* default size */

3487

m_n->tu = 64; /* default size */

3488

3489

/* BUG_ON(pixel_clock > INT_MAX / 36); */

3489

/* BUG_ON(pixel_clock > INT_MAX / 36); */

3490

m_n->gmch_m = bits_per_pixel * pixel_clock;

3490

m_n->gmch_m = bits_per_pixel * pixel_clock;

3491

m_n->gmch_n = link_clock * nlanes * 8;

3491

m_n->gmch_n = link_clock * nlanes * 8;

3492

fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);

3492

fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);

3493

3494

m_n->link_m = pixel_clock;

3494

m_n->link_m = pixel_clock;

3495

m_n->link_n = link_clock;

3495

m_n->link_n = link_clock;

3496

fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);

3496

fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);

3497

}

3497

}

3498

3499

3500

struct intel_watermark_params {

3500

struct intel_watermark_params {

3501

unsigned long fifo_size;

3501

unsigned long fifo_size;

3502

unsigned long max_wm;

3502

unsigned long max_wm;

3503

unsigned long default_wm;

3503

unsigned long default_wm;

3504

unsigned long guard_size;

3504

unsigned long guard_size;

3505

unsigned long cacheline_size;

3505

unsigned long cacheline_size;

3506

};

3506

};

3507

3508

/* Pineview has different values for various configs */

3508

/* Pineview has different values for various configs */

3509

static const struct intel_watermark_params pineview_display_wm = {

3509

static const struct intel_watermark_params pineview_display_wm = {

3510

PINEVIEW_DISPLAY_FIFO,

3510

PINEVIEW_DISPLAY_FIFO,

3511

PINEVIEW_MAX_WM,

3511

PINEVIEW_MAX_WM,

3512

PINEVIEW_DFT_WM,

3512

PINEVIEW_DFT_WM,

3513

PINEVIEW_GUARD_WM,

3513

PINEVIEW_GUARD_WM,

3514

PINEVIEW_FIFO_LINE_SIZE

3514

PINEVIEW_FIFO_LINE_SIZE

3515

};

3515

};

3516

static const struct intel_watermark_params pineview_display_hplloff_wm = {

3516

static const struct intel_watermark_params pineview_display_hplloff_wm = {

3517

PINEVIEW_DISPLAY_FIFO,

3517

PINEVIEW_DISPLAY_FIFO,

3518

PINEVIEW_MAX_WM,

3518

PINEVIEW_MAX_WM,

3519

PINEVIEW_DFT_HPLLOFF_WM,

3519

PINEVIEW_DFT_HPLLOFF_WM,

3520

PINEVIEW_GUARD_WM,

3520

PINEVIEW_GUARD_WM,

3521

PINEVIEW_FIFO_LINE_SIZE

3521

PINEVIEW_FIFO_LINE_SIZE

3522

};

3522

};

3523

static const struct intel_watermark_params pineview_cursor_wm = {

3523

static const struct intel_watermark_params pineview_cursor_wm = {

3524

PINEVIEW_CURSOR_FIFO,

3524

PINEVIEW_CURSOR_FIFO,

3525

PINEVIEW_CURSOR_MAX_WM,

3525

PINEVIEW_CURSOR_MAX_WM,

3526

PINEVIEW_CURSOR_DFT_WM,

3526

PINEVIEW_CURSOR_DFT_WM,

3527

PINEVIEW_CURSOR_GUARD_WM,

3527

PINEVIEW_CURSOR_GUARD_WM,

3528

PINEVIEW_FIFO_LINE_SIZE,

3528

PINEVIEW_FIFO_LINE_SIZE,

3529

};

3529

};

3530

static const struct intel_watermark_params pineview_cursor_hplloff_wm = {

3530

static const struct intel_watermark_params pineview_cursor_hplloff_wm = {

3531

PINEVIEW_CURSOR_FIFO,

3531

PINEVIEW_CURSOR_FIFO,

3532

PINEVIEW_CURSOR_MAX_WM,

3532

PINEVIEW_CURSOR_MAX_WM,

3533

PINEVIEW_CURSOR_DFT_WM,

3533

PINEVIEW_CURSOR_DFT_WM,

3534

PINEVIEW_CURSOR_GUARD_WM,

3534

PINEVIEW_CURSOR_GUARD_WM,

3535

PINEVIEW_FIFO_LINE_SIZE

3535

PINEVIEW_FIFO_LINE_SIZE

3536

};

3536

};

3537

static const struct intel_watermark_params g4x_wm_info = {

3537

static const struct intel_watermark_params g4x_wm_info = {

3538

G4X_FIFO_SIZE,

3538

G4X_FIFO_SIZE,

3539

G4X_MAX_WM,

3539

G4X_MAX_WM,

3540

G4X_MAX_WM,

3540

G4X_MAX_WM,

3541

2,

3541

2,

3542

G4X_FIFO_LINE_SIZE,

3542

G4X_FIFO_LINE_SIZE,

3543

};

3543

};

3544

static const struct intel_watermark_params g4x_cursor_wm_info = {

3544

static const struct intel_watermark_params g4x_cursor_wm_info = {

3545

I965_CURSOR_FIFO,

3545

I965_CURSOR_FIFO,

3546

I965_CURSOR_MAX_WM,

3546

I965_CURSOR_MAX_WM,

3547

I965_CURSOR_DFT_WM,

3547

I965_CURSOR_DFT_WM,

3548

2,

3548

2,

3549

G4X_FIFO_LINE_SIZE,

3549

G4X_FIFO_LINE_SIZE,

3550

};

3550

};

3551

static const struct intel_watermark_params i965_cursor_wm_info = {

3551

static const struct intel_watermark_params i965_cursor_wm_info = {

3552

I965_CURSOR_FIFO,

3552

I965_CURSOR_FIFO,

3553

I965_CURSOR_MAX_WM,

3553

I965_CURSOR_MAX_WM,

3554

I965_CURSOR_DFT_WM,

3554

I965_CURSOR_DFT_WM,

3555

2,

3555

2,

3556

I915_FIFO_LINE_SIZE,

3556

I915_FIFO_LINE_SIZE,

3557

};

3557

};

3558

static const struct intel_watermark_params i945_wm_info = {

3558

static const struct intel_watermark_params i945_wm_info = {

3559

I945_FIFO_SIZE,

3559

I945_FIFO_SIZE,

3560

I915_MAX_WM,

3560

I915_MAX_WM,

3561

1,

3561

1,

3562

2,

3562

2,

3563

I915_FIFO_LINE_SIZE

3563

I915_FIFO_LINE_SIZE

3564

};

3564

};

3565

static const struct intel_watermark_params i915_wm_info = {

3565

static const struct intel_watermark_params i915_wm_info = {

3566

I915_FIFO_SIZE,

3566

I915_FIFO_SIZE,

3567

I915_MAX_WM,

3567

I915_MAX_WM,

3568

1,

3568

1,

3569

2,

3569

2,

3570

I915_FIFO_LINE_SIZE

3570

I915_FIFO_LINE_SIZE

3571

};

3571

};

3572

static const struct intel_watermark_params i855_wm_info = {

3572

static const struct intel_watermark_params i855_wm_info = {

3573

I855GM_FIFO_SIZE,

3573

I855GM_FIFO_SIZE,

3574

I915_MAX_WM,

3574

I915_MAX_WM,

3575

1,

3575

1,

3576

2,

3576

2,

3577

I830_FIFO_LINE_SIZE

3577

I830_FIFO_LINE_SIZE

3578

};

3578

};

3579

static const struct intel_watermark_params i830_wm_info = {

3579

static const struct intel_watermark_params i830_wm_info = {

3580

I830_FIFO_SIZE,

3580

I830_FIFO_SIZE,

3581

I915_MAX_WM,

3581

I915_MAX_WM,

3582

1,

3582

1,

3583

2,

3583

2,

3584

I830_FIFO_LINE_SIZE

3584

I830_FIFO_LINE_SIZE

3585

};

3585

};

3586

3587

static const struct intel_watermark_params ironlake_display_wm_info = {

3587

static const struct intel_watermark_params ironlake_display_wm_info = {

3588

ILK_DISPLAY_FIFO,

3588

ILK_DISPLAY_FIFO,

3589

ILK_DISPLAY_MAXWM,

3589

ILK_DISPLAY_MAXWM,

3590

ILK_DISPLAY_DFTWM,

3590

ILK_DISPLAY_DFTWM,

3591

2,

3591

2,

3592

ILK_FIFO_LINE_SIZE

3592

ILK_FIFO_LINE_SIZE

3593

};

3593

};

3594

static const struct intel_watermark_params ironlake_cursor_wm_info = {

3594

static const struct intel_watermark_params ironlake_cursor_wm_info = {

3595

ILK_CURSOR_FIFO,

3595

ILK_CURSOR_FIFO,

3596

ILK_CURSOR_MAXWM,

3596

ILK_CURSOR_MAXWM,

3597

ILK_CURSOR_DFTWM,

3597

ILK_CURSOR_DFTWM,

3598

2,

3598

2,

3599

ILK_FIFO_LINE_SIZE

3599

ILK_FIFO_LINE_SIZE

3600

};

3600

};

3601

static const struct intel_watermark_params ironlake_display_srwm_info = {

3601

static const struct intel_watermark_params ironlake_display_srwm_info = {

3602

ILK_DISPLAY_SR_FIFO,

3602

ILK_DISPLAY_SR_FIFO,

3603

ILK_DISPLAY_MAX_SRWM,

3603

ILK_DISPLAY_MAX_SRWM,

3604

ILK_DISPLAY_DFT_SRWM,

3604

ILK_DISPLAY_DFT_SRWM,

3605

2,

3605

2,

3606

ILK_FIFO_LINE_SIZE

3606

ILK_FIFO_LINE_SIZE

3607

};

3607

};

3608

static const struct intel_watermark_params ironlake_cursor_srwm_info = {

3608

static const struct intel_watermark_params ironlake_cursor_srwm_info = {

3609

ILK_CURSOR_SR_FIFO,

3609

ILK_CURSOR_SR_FIFO,

3610

ILK_CURSOR_MAX_SRWM,

3610

ILK_CURSOR_MAX_SRWM,

3611

ILK_CURSOR_DFT_SRWM,

3611

ILK_CURSOR_DFT_SRWM,

3612

2,

3612

2,

3613

ILK_FIFO_LINE_SIZE

3613

ILK_FIFO_LINE_SIZE

3614

};

3614

};

3615

3616

static const struct intel_watermark_params sandybridge_display_wm_info = {

3616

static const struct intel_watermark_params sandybridge_display_wm_info = {

3617

SNB_DISPLAY_FIFO,

3617

SNB_DISPLAY_FIFO,

3618

SNB_DISPLAY_MAXWM,

3618

SNB_DISPLAY_MAXWM,

3619

SNB_DISPLAY_DFTWM,

3619

SNB_DISPLAY_DFTWM,

3620

2,

3620

2,

3621

SNB_FIFO_LINE_SIZE

3621

SNB_FIFO_LINE_SIZE

3622

};

3622

};

3623

static const struct intel_watermark_params sandybridge_cursor_wm_info = {

3623

static const struct intel_watermark_params sandybridge_cursor_wm_info = {

3624

SNB_CURSOR_FIFO,

3624

SNB_CURSOR_FIFO,

3625

SNB_CURSOR_MAXWM,

3625

SNB_CURSOR_MAXWM,

3626

SNB_CURSOR_DFTWM,

3626

SNB_CURSOR_DFTWM,

3627

2,

3627

2,

3628

SNB_FIFO_LINE_SIZE

3628

SNB_FIFO_LINE_SIZE

3629

};

3629

};

3630

static const struct intel_watermark_params sandybridge_display_srwm_info = {

3630

static const struct intel_watermark_params sandybridge_display_srwm_info = {

3631

SNB_DISPLAY_SR_FIFO,

3631

SNB_DISPLAY_SR_FIFO,

3632

SNB_DISPLAY_MAX_SRWM,

3632

SNB_DISPLAY_MAX_SRWM,

3633

SNB_DISPLAY_DFT_SRWM,

3633

SNB_DISPLAY_DFT_SRWM,

3634

2,

3634

2,

3635

SNB_FIFO_LINE_SIZE

3635

SNB_FIFO_LINE_SIZE

3636

};

3636

};

3637

static const struct intel_watermark_params sandybridge_cursor_srwm_info = {

3637

static const struct intel_watermark_params sandybridge_cursor_srwm_info = {

3638

SNB_CURSOR_SR_FIFO,

3638

SNB_CURSOR_SR_FIFO,

3639

SNB_CURSOR_MAX_SRWM,

3639

SNB_CURSOR_MAX_SRWM,

3640

SNB_CURSOR_DFT_SRWM,

3640

SNB_CURSOR_DFT_SRWM,

3641

2,

3641

2,

3642

SNB_FIFO_LINE_SIZE

3642

SNB_FIFO_LINE_SIZE

3643

};

3643

};

3644

3645

3646

/**

3646

/**

3647

* intel_calculate_wm - calculate watermark level

3647

* intel_calculate_wm - calculate watermark level

3648

* @clock_in_khz: pixel clock

3648

* @clock_in_khz: pixel clock

3649

* @wm: chip FIFO params

3649

* @wm: chip FIFO params

3650

* @pixel_size: display pixel size

3650

* @pixel_size: display pixel size

3651

* @latency_ns: memory latency for the platform

3651

* @latency_ns: memory latency for the platform

3652

*

3652

*

3653

* Calculate the watermark level (the level at which the display plane will

3653

* Calculate the watermark level (the level at which the display plane will

3654

* start fetching from memory again). Each chip has a different display

3654

* start fetching from memory again). Each chip has a different display

3655

* FIFO size and allocation, so the caller needs to figure that out and pass

3655

* FIFO size and allocation, so the caller needs to figure that out and pass

3656

* in the correct intel_watermark_params structure.

3656

* in the correct intel_watermark_params structure.

3657

*

3657

*

3658

* As the pixel clock runs, the FIFO will be drained at a rate that depends

3658

* As the pixel clock runs, the FIFO will be drained at a rate that depends

3659

* on the pixel size. When it reaches the watermark level, it'll start

3659

* on the pixel size. When it reaches the watermark level, it'll start

3660

* fetching FIFO line sized based chunks from memory until the FIFO fills

3660

* fetching FIFO line sized based chunks from memory until the FIFO fills

3661

* past the watermark point. If the FIFO drains completely, a FIFO underrun

3661

* past the watermark point. If the FIFO drains completely, a FIFO underrun

3662

* will occur, and a display engine hang could result.

3662

* will occur, and a display engine hang could result.

3663

*/

3663

*/

3664

static unsigned long intel_calculate_wm(unsigned long clock_in_khz,

3664

static unsigned long intel_calculate_wm(unsigned long clock_in_khz,

3665

const struct intel_watermark_params *wm,

3665

const struct intel_watermark_params *wm,

3666

int fifo_size,

3666

int fifo_size,

3667

int pixel_size,

3667

int pixel_size,

3668

unsigned long latency_ns)

3668

unsigned long latency_ns)

3669

{

3669

{

3670

long entries_required, wm_size;

3670

long entries_required, wm_size;

3671

3672

/*

3672

/*

3673

* Note: we need to make sure we don't overflow for various clock &

3673

* Note: we need to make sure we don't overflow for various clock &

3674

* latency values.

3674

* latency values.

3675

* clocks go from a few thousand to several hundred thousand.

3675

* clocks go from a few thousand to several hundred thousand.

3676

* latency is usually a few thousand

3676

* latency is usually a few thousand

3677

*/

3677

*/

3678

entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /

3678

entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /

3679

1000;

3679

1000;

3680

entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);

3680

entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);

3681

3682

DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);

3682

DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);

3683

3684

wm_size = fifo_size - (entries_required + wm->guard_size);

3684

wm_size = fifo_size - (entries_required + wm->guard_size);

3685

3686

DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);

3686

DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);

3687

3688

/* Don't promote wm_size to unsigned... */

3688

/* Don't promote wm_size to unsigned... */

3689

if (wm_size > (long)wm->max_wm)

3689

if (wm_size > (long)wm->max_wm)

3690

wm_size = wm->max_wm;

3690

wm_size = wm->max_wm;

3691

if (wm_size <= 0)

3691

if (wm_size <= 0)

3692

wm_size = wm->default_wm;

3692

wm_size = wm->default_wm;

3693

return wm_size;

3693

return wm_size;

3694

}

3694

}

3695

3696

struct cxsr_latency {

3696

struct cxsr_latency {

3697

int is_desktop;

3697

int is_desktop;

3698

int is_ddr3;

3698

int is_ddr3;

3699

unsigned long fsb_freq;

3699

unsigned long fsb_freq;

3700

unsigned long mem_freq;

3700

unsigned long mem_freq;

3701

unsigned long display_sr;

3701

unsigned long display_sr;

3702

unsigned long display_hpll_disable;

3702

unsigned long display_hpll_disable;

3703

unsigned long cursor_sr;

3703

unsigned long cursor_sr;

3704

unsigned long cursor_hpll_disable;

3704

unsigned long cursor_hpll_disable;

3705

};

3705

};

3706

3707

static const struct cxsr_latency cxsr_latency_table[] = {

3707

static const struct cxsr_latency cxsr_latency_table[] = {

3708

{1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */

3708

{1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */

3709

{1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */

3709

{1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */

3710

{1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */

3710

{1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */

3711

{1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */

3711

{1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */

3712

{1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */

3712

{1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */

3713

3714

{1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */

3714

{1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */

3715

{1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */

3715

{1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */

3716

{1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */

3716

{1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */

3717

{1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */

3717

{1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */

3718

{1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */

3718

{1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */

3719

3720

{1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */

3720

{1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */

3721

{1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */

3721

{1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */

3722

{1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */

3722

{1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */

3723

{1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */

3723

{1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */

3724

{1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */

3724

{1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */

3725

3726

{0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */

3726

{0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */

3727

{0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */

3727

{0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */

3728

{0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */

3728

{0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */

3729

{0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */

3729

{0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */

3730

{0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */

3730

{0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */

3731

3732

{0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */

3732

{0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */

3733

{0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */

3733

{0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */

3734

{0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */

3734

{0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */

3735

{0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */

3735

{0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */

3736

{0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */

3736

{0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */

3737

3738

{0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */

3738

{0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */

3739

{0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */

3739

{0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */

3740

{0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */

3740

{0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */

3741

{0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */

3741

{0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */

3742

{0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */

3742

{0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */

3743

};

3743

};

3744

3745

static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,

3745

static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,

3746

int is_ddr3,

3746

int is_ddr3,

3747

int fsb,

3747

int fsb,

3748

int mem)

3748

int mem)

3749

{

3749

{

3750

const struct cxsr_latency *latency;

3750

const struct cxsr_latency *latency;

3751

int i;

3751

int i;

3752

3753

if (fsb == 0 || mem == 0)

3753

if (fsb == 0 || mem == 0)

3754

return NULL;

3754

return NULL;

3755

3756

for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {

3756

for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {

3757

latency = &cxsr_latency_table[i];

3757

latency = &cxsr_latency_table[i];

3758

if (is_desktop == latency->is_desktop &&

3758

if (is_desktop == latency->is_desktop &&

3759

is_ddr3 == latency->is_ddr3 &&

3759

is_ddr3 == latency->is_ddr3 &&

3760

fsb == latency->fsb_freq && mem == latency->mem_freq)

3760

fsb == latency->fsb_freq && mem == latency->mem_freq)

3761

return latency;

3761

return latency;

3762

}

3762

}

3763

3764

DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");

3764

DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");

3765

3766

return NULL;

3766

return NULL;

3767

}

3767

}

3768

3769

static void pineview_disable_cxsr(struct drm_device *dev)

3769

static void pineview_disable_cxsr(struct drm_device *dev)

3770

{

3770

{

3771

struct drm_i915_private *dev_priv = dev->dev_private;

3771

struct drm_i915_private *dev_priv = dev->dev_private;

3772

3773

/* deactivate cxsr */

3773

/* deactivate cxsr */

3774

I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);

3774

I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);

3775

}

3775

}

3776

3777

/*

3777

/*

3778

* Latency for FIFO fetches is dependent on several factors:

3778

* Latency for FIFO fetches is dependent on several factors:

3779

* - memory configuration (speed, channels)

3779

* - memory configuration (speed, channels)

3780

* - chipset

3780

* - chipset

3781

* - current MCH state

3781

* - current MCH state

3782

* It can be fairly high in some situations, so here we assume a fairly

3782

* It can be fairly high in some situations, so here we assume a fairly

3783

* pessimal value. It's a tradeoff between extra memory fetches (if we

3783

* pessimal value. It's a tradeoff between extra memory fetches (if we

3784

* set this value too high, the FIFO will fetch frequently to stay full)

3784

* set this value too high, the FIFO will fetch frequently to stay full)

3785

* and power consumption (set it too low to save power and we might see

3785

* and power consumption (set it too low to save power and we might see

3786

* FIFO underruns and display "flicker").

3786

* FIFO underruns and display "flicker").

3787

*

3787

*

3788

* A value of 5us seems to be a good balance; safe for very low end

3788

* A value of 5us seems to be a good balance; safe for very low end

3789

* platforms but not overly aggressive on lower latency configs.

3789

* platforms but not overly aggressive on lower latency configs.

3790

*/

3790

*/

3791

static const int latency_ns = 5000;

3791

static const int latency_ns = 5000;

3792

3793

static int i9xx_get_fifo_size(struct drm_device *dev, int plane)

3793

static int i9xx_get_fifo_size(struct drm_device *dev, int plane)

3794

{

3794

{

3795

struct drm_i915_private *dev_priv = dev->dev_private;

3795

struct drm_i915_private *dev_priv = dev->dev_private;

3796

uint32_t dsparb = I915_READ(DSPARB);

3796

uint32_t dsparb = I915_READ(DSPARB);

3797

int size;

3797

int size;

3798

3799

size = dsparb & 0x7f;

3799

size = dsparb & 0x7f;

3800

if (plane)

3800

if (plane)

3801

size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;

3801

size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;

3802

3803

DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,

3803

DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,

3804

plane ? "B" : "A", size);

3804

plane ? "B" : "A", size);

3805

3806

return size;

3806

return size;

3807

}

3807

}

3808

3809

static int i85x_get_fifo_size(struct drm_device *dev, int plane)

3809

static int i85x_get_fifo_size(struct drm_device *dev, int plane)

3810

{

3810

{

3811

struct drm_i915_private *dev_priv = dev->dev_private;

3811

struct drm_i915_private *dev_priv = dev->dev_private;

3812

uint32_t dsparb = I915_READ(DSPARB);

3812

uint32_t dsparb = I915_READ(DSPARB);

3813

int size;

3813

int size;

3814

3815

size = dsparb & 0x1ff;

3815

size = dsparb & 0x1ff;

3816

if (plane)

3816

if (plane)

3817

size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;

3817

size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;

3818

size >>= 1; /* Convert to cachelines */

3818

size >>= 1; /* Convert to cachelines */

3819

3820

DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,

3820

DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,

3821

plane ? "B" : "A", size);

3821

plane ? "B" : "A", size);

3822

3823

return size;

3823

return size;

3824

}

3824

}

3825

3826

static int i845_get_fifo_size(struct drm_device *dev, int plane)

3826

static int i845_get_fifo_size(struct drm_device *dev, int plane)

3827

{

3827

{

3828

struct drm_i915_private *dev_priv = dev->dev_private;

3828

struct drm_i915_private *dev_priv = dev->dev_private;

3829

uint32_t dsparb = I915_READ(DSPARB);

3829

uint32_t dsparb = I915_READ(DSPARB);

3830

int size;

3830

int size;

3831

3832

size = dsparb & 0x7f;

3832

size = dsparb & 0x7f;

3833

size >>= 2; /* Convert to cachelines */

3833

size >>= 2; /* Convert to cachelines */

3834

3835

DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,

3835

DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,

3836

plane ? "B" : "A",

3836

plane ? "B" : "A",

3837

size);

3837

size);

3838

3839

return size;

3839

return size;

3840

}

3840

}

3841

3842

static int i830_get_fifo_size(struct drm_device *dev, int plane)

3842

static int i830_get_fifo_size(struct drm_device *dev, int plane)

3843

{

3843

{

3844

struct drm_i915_private *dev_priv = dev->dev_private;

3844

struct drm_i915_private *dev_priv = dev->dev_private;

3845

uint32_t dsparb = I915_READ(DSPARB);

3845

uint32_t dsparb = I915_READ(DSPARB);

3846

int size;

3846

int size;

3847

3848

size = dsparb & 0x7f;

3848

size = dsparb & 0x7f;

3849

size >>= 1; /* Convert to cachelines */

3849

size >>= 1; /* Convert to cachelines */

3850

3851

DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,

3851

DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,

3852

plane ? "B" : "A", size);

3852

plane ? "B" : "A", size);

3853

3854

return size;

3854

return size;

3855

}

3855

}

3856

3857

static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)

3857

static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)

3858

{

3858

{

3859

struct drm_crtc *crtc, *enabled = NULL;

3859

struct drm_crtc *crtc, *enabled = NULL;

3860

3861

list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {

3861

list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {

3862

if (crtc->enabled && crtc->fb) {

3862

if (crtc->enabled && crtc->fb) {

3863

if (enabled)

3863

if (enabled)

3864

return NULL;

3864

return NULL;

3865

enabled = crtc;

3865

enabled = crtc;

3866

}

3866

}

3867

}

3867

}

3868

3869

return enabled;

3869

return enabled;

3870

}

3870

}

3871

3872

static void pineview_update_wm(struct drm_device *dev)

3872

static void pineview_update_wm(struct drm_device *dev)

3873

{

3873

{

3874

struct drm_i915_private *dev_priv = dev->dev_private;

3874

struct drm_i915_private *dev_priv = dev->dev_private;

3875

struct drm_crtc *crtc;

3875

struct drm_crtc *crtc;

3876

const struct cxsr_latency *latency;

3876

const struct cxsr_latency *latency;

3877

u32 reg;

3877

u32 reg;

3878

unsigned long wm;

3878

unsigned long wm;

3879

3880

latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,

3880

latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,

3881

dev_priv->fsb_freq, dev_priv->mem_freq);

3881

dev_priv->fsb_freq, dev_priv->mem_freq);

3882

if (!latency) {

3882

if (!latency) {

3883

DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");

3883

DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");

3884

pineview_disable_cxsr(dev);

3884

pineview_disable_cxsr(dev);

3885

return;

3885

return;

3886

}

3886

}

3887

3888

crtc = single_enabled_crtc(dev);

3888

crtc = single_enabled_crtc(dev);

3889

if (crtc) {

3889

if (crtc) {

3890

int clock = crtc->mode.clock;

3890

int clock = crtc->mode.clock;

3891

int pixel_size = crtc->fb->bits_per_pixel / 8;

3891

int pixel_size = crtc->fb->bits_per_pixel / 8;

3892

3893

/* Display SR */

3893

/* Display SR */

3894

wm = intel_calculate_wm(clock, &pineview_display_wm,

3894

wm = intel_calculate_wm(clock, &pineview_display_wm,

3895

pineview_display_wm.fifo_size,

3895

pineview_display_wm.fifo_size,

3896

pixel_size, latency->display_sr);

3896

pixel_size, latency->display_sr);

3897

reg = I915_READ(DSPFW1);

3897

reg = I915_READ(DSPFW1);

3898

reg &= ~DSPFW_SR_MASK;

3898

reg &= ~DSPFW_SR_MASK;

3899

reg |= wm << DSPFW_SR_SHIFT;

3899

reg |= wm << DSPFW_SR_SHIFT;

3900

I915_WRITE(DSPFW1, reg);

3900

I915_WRITE(DSPFW1, reg);

3901

DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);

3901

DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);

3902

3903

/* cursor SR */

3903

/* cursor SR */

3904

wm = intel_calculate_wm(clock, &pineview_cursor_wm,

3904

wm = intel_calculate_wm(clock, &pineview_cursor_wm,

3905

pineview_display_wm.fifo_size,

3905

pineview_display_wm.fifo_size,

3906

pixel_size, latency->cursor_sr);

3906

pixel_size, latency->cursor_sr);

3907

reg = I915_READ(DSPFW3);

3907

reg = I915_READ(DSPFW3);

3908

reg &= ~DSPFW_CURSOR_SR_MASK;

3908

reg &= ~DSPFW_CURSOR_SR_MASK;

3909

reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;

3909

reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;

3910

I915_WRITE(DSPFW3, reg);

3910

I915_WRITE(DSPFW3, reg);

3911

3912

/* Display HPLL off SR */

3912

/* Display HPLL off SR */

3913

wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,

3913

wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,

3914

pineview_display_hplloff_wm.fifo_size,

3914

pineview_display_hplloff_wm.fifo_size,

3915

pixel_size, latency->display_hpll_disable);

3915

pixel_size, latency->display_hpll_disable);

3916

reg = I915_READ(DSPFW3);

3916

reg = I915_READ(DSPFW3);

3917

reg &= ~DSPFW_HPLL_SR_MASK;

3917

reg &= ~DSPFW_HPLL_SR_MASK;

3918

reg |= wm & DSPFW_HPLL_SR_MASK;

3918

reg |= wm & DSPFW_HPLL_SR_MASK;

3919

I915_WRITE(DSPFW3, reg);

3919

I915_WRITE(DSPFW3, reg);

3920

3921

/* cursor HPLL off SR */

3921

/* cursor HPLL off SR */

3922

wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,

3922

wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,

3923

pineview_display_hplloff_wm.fifo_size,

3923

pineview_display_hplloff_wm.fifo_size,

3924

pixel_size, latency->cursor_hpll_disable);

3924

pixel_size, latency->cursor_hpll_disable);

3925

reg = I915_READ(DSPFW3);

3925

reg = I915_READ(DSPFW3);

3926

reg &= ~DSPFW_HPLL_CURSOR_MASK;

3926

reg &= ~DSPFW_HPLL_CURSOR_MASK;

3927

reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;

3927

reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;

3928

I915_WRITE(DSPFW3, reg);

3928

I915_WRITE(DSPFW3, reg);

3929

DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);

3929

DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);

3930

3931

/* activate cxsr */

3931

/* activate cxsr */

3932

I915_WRITE(DSPFW3,

3932

I915_WRITE(DSPFW3,

3933

I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);

3933

I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);

3934

DRM_DEBUG_KMS("Self-refresh is enabled\n");

3934

DRM_DEBUG_KMS("Self-refresh is enabled\n");

3935

} else {

3935

} else {

3936

pineview_disable_cxsr(dev);

3936

pineview_disable_cxsr(dev);

3937

DRM_DEBUG_KMS("Self-refresh is disabled\n");

3937

DRM_DEBUG_KMS("Self-refresh is disabled\n");

3938

}

3938

}

3939

}

3939

}

3940

3941

static bool g4x_compute_wm0(struct drm_device *dev,

3941

static bool g4x_compute_wm0(struct drm_device *dev,

3942

int plane,

3942

int plane,

3943

const struct intel_watermark_params *display,

3943

const struct intel_watermark_params *display,

3944

int display_latency_ns,

3944

int display_latency_ns,

3945

const struct intel_watermark_params *cursor,

3945

const struct intel_watermark_params *cursor,

3946

int cursor_latency_ns,

3946

int cursor_latency_ns,

3947

int *plane_wm,

3947

int *plane_wm,

3948

int *cursor_wm)

3948

int *cursor_wm)

3949

{

3949

{

3950

struct drm_crtc *crtc;

3950

struct drm_crtc *crtc;

3951

int htotal, hdisplay, clock, pixel_size;

3951

int htotal, hdisplay, clock, pixel_size;

3952

int line_time_us, line_count;

3952

int line_time_us, line_count;

3953

int entries, tlb_miss;

3953

int entries, tlb_miss;

3954

3955

crtc = intel_get_crtc_for_plane(dev, plane);

3955

crtc = intel_get_crtc_for_plane(dev, plane);

3956

if (crtc->fb == NULL || !crtc->enabled) {

3956

if (crtc->fb == NULL || !crtc->enabled) {

3957

*cursor_wm = cursor->guard_size;

3957

*cursor_wm = cursor->guard_size;

3958

*plane_wm = display->guard_size;

3958

*plane_wm = display->guard_size;

3959

return false;

3959

return false;

3960

}

3960

}

3961

3962

htotal = crtc->mode.htotal;

3962

htotal = crtc->mode.htotal;

3963

hdisplay = crtc->mode.hdisplay;

3963

hdisplay = crtc->mode.hdisplay;

3964

clock = crtc->mode.clock;

3964

clock = crtc->mode.clock;

3965

pixel_size = crtc->fb->bits_per_pixel / 8;

3965

pixel_size = crtc->fb->bits_per_pixel / 8;

3966

3967

/* Use the small buffer method to calculate plane watermark */

3967

/* Use the small buffer method to calculate plane watermark */

3968

entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;

3968

entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;

3969

tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;

3969

tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;

3970

if (tlb_miss > 0)

3970

if (tlb_miss > 0)

3971

entries += tlb_miss;

3971

entries += tlb_miss;

3972

entries = DIV_ROUND_UP(entries, display->cacheline_size);

3972

entries = DIV_ROUND_UP(entries, display->cacheline_size);

3973

*plane_wm = entries + display->guard_size;

3973

*plane_wm = entries + display->guard_size;

3974

if (*plane_wm > (int)display->max_wm)

3974

if (*plane_wm > (int)display->max_wm)

3975

*plane_wm = display->max_wm;

3975

*plane_wm = display->max_wm;

3976

3977

/* Use the large buffer method to calculate cursor watermark */

3977

/* Use the large buffer method to calculate cursor watermark */

3978

line_time_us = ((htotal * 1000) / clock);

3978

line_time_us = ((htotal * 1000) / clock);

3979

line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;

3979

line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;

3980

entries = line_count * 64 * pixel_size;

3980

entries = line_count * 64 * pixel_size;

3981

tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;

3981

tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;

3982

if (tlb_miss > 0)

3982

if (tlb_miss > 0)

3983

entries += tlb_miss;

3983

entries += tlb_miss;

3984

entries = DIV_ROUND_UP(entries, cursor->cacheline_size);

3984

entries = DIV_ROUND_UP(entries, cursor->cacheline_size);

3985

*cursor_wm = entries + cursor->guard_size;

3985

*cursor_wm = entries + cursor->guard_size;

3986

if (*cursor_wm > (int)cursor->max_wm)

3986

if (*cursor_wm > (int)cursor->max_wm)

3987

*cursor_wm = (int)cursor->max_wm;

3987

*cursor_wm = (int)cursor->max_wm;

3988

3989

return true;

3989

return true;

3990

}

3990

}

3991

3992

/*

3992

/*

3993

* Check the wm result.

3993

* Check the wm result.

3994

*

3994

*

3995

* If any calculated watermark values is larger than the maximum value that

3995

* If any calculated watermark values is larger than the maximum value that

3996

* can be programmed into the associated watermark register, that watermark

3996

* can be programmed into the associated watermark register, that watermark

3997

* must be disabled.

3997

* must be disabled.

3998

*/

3998

*/

3999

static bool g4x_check_srwm(struct drm_device *dev,

3999

static bool g4x_check_srwm(struct drm_device *dev,

4000

int display_wm, int cursor_wm,

4000

int display_wm, int cursor_wm,

4001

const struct intel_watermark_params *display,

4001

const struct intel_watermark_params *display,

4002

const struct intel_watermark_params *cursor)

4002

const struct intel_watermark_params *cursor)

4003

{

4003

{

4004

DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",

4004

DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",

4005

display_wm, cursor_wm);

4005

display_wm, cursor_wm);

4006

4007

if (display_wm > display->max_wm) {

4007

if (display_wm > display->max_wm) {

4008

DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",

4008

DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",

4009

display_wm, display->max_wm);

4009

display_wm, display->max_wm);

4010

return false;

4010

return false;

4011

}

4011

}

4012

4013

if (cursor_wm > cursor->max_wm) {

4013

if (cursor_wm > cursor->max_wm) {

4014

DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",

4014

DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",

4015

cursor_wm, cursor->max_wm);

4015

cursor_wm, cursor->max_wm);

4016

return false;

4016

return false;

4017

}

4017

}

4018

4019

if (!(display_wm || cursor_wm)) {

4019

if (!(display_wm || cursor_wm)) {

4020

DRM_DEBUG_KMS("SR latency is 0, disabling\n");

4020

DRM_DEBUG_KMS("SR latency is 0, disabling\n");

4021

return false;

4021

return false;

4022

}

4022

}

4023

4024

return true;

4024

return true;

4025

}

4025

}

4026

4027

static bool g4x_compute_srwm(struct drm_device *dev,

4027

static bool g4x_compute_srwm(struct drm_device *dev,

4028

int plane,

4028

int plane,

4029

int latency_ns,

4029

int latency_ns,

4030

const struct intel_watermark_params *display,

4030

const struct intel_watermark_params *display,

4031

const struct intel_watermark_params *cursor,

4031

const struct intel_watermark_params *cursor,

4032

int *display_wm, int *cursor_wm)

4032

int *display_wm, int *cursor_wm)

4033

{

4033

{

4034

struct drm_crtc *crtc;

4034

struct drm_crtc *crtc;

4035

int hdisplay, htotal, pixel_size, clock;

4035

int hdisplay, htotal, pixel_size, clock;

4036

unsigned long line_time_us;

4036

unsigned long line_time_us;

4037

int line_count, line_size;

4037

int line_count, line_size;

4038

int small, large;

4038

int small, large;

4039

int entries;

4039

int entries;

4040

4041

if (!latency_ns) {

4041

if (!latency_ns) {

4042

*display_wm = *cursor_wm = 0;

4042

*display_wm = *cursor_wm = 0;

4043

return false;

4043

return false;

4044

}

4044

}

4045

4046

crtc = intel_get_crtc_for_plane(dev, plane);

4046

crtc = intel_get_crtc_for_plane(dev, plane);

4047

hdisplay = crtc->mode.hdisplay;

4047

hdisplay = crtc->mode.hdisplay;

4048

htotal = crtc->mode.htotal;

4048

htotal = crtc->mode.htotal;

4049

clock = crtc->mode.clock;

4049

clock = crtc->mode.clock;

4050

pixel_size = crtc->fb->bits_per_pixel / 8;

4050

pixel_size = crtc->fb->bits_per_pixel / 8;

4051

4052

line_time_us = (htotal * 1000) / clock;

4052

line_time_us = (htotal * 1000) / clock;

4053

line_count = (latency_ns / line_time_us + 1000) / 1000;

4053

line_count = (latency_ns / line_time_us + 1000) / 1000;

4054

line_size = hdisplay * pixel_size;

4054

line_size = hdisplay * pixel_size;

4055

4056

/* Use the minimum of the small and large buffer method for primary */

4056

/* Use the minimum of the small and large buffer method for primary */

4057

small = ((clock * pixel_size / 1000) * latency_ns) / 1000;

4057

small = ((clock * pixel_size / 1000) * latency_ns) / 1000;

4058

large = line_count * line_size;

4058

large = line_count * line_size;

4059

4060

entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);

4060

entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);

4061

*display_wm = entries + display->guard_size;

4061

*display_wm = entries + display->guard_size;

4062

4063

/* calculate the self-refresh watermark for display cursor */

4063

/* calculate the self-refresh watermark for display cursor */

4064

entries = line_count * pixel_size * 64;

4064

entries = line_count * pixel_size * 64;

4065

entries = DIV_ROUND_UP(entries, cursor->cacheline_size);

4065

entries = DIV_ROUND_UP(entries, cursor->cacheline_size);

4066

*cursor_wm = entries + cursor->guard_size;

4066

*cursor_wm = entries + cursor->guard_size;

4067

4068

return g4x_check_srwm(dev,

4068

return g4x_check_srwm(dev,

4069

*display_wm, *cursor_wm,

4069

*display_wm, *cursor_wm,

4070

display, cursor);

4070

display, cursor);

4071

}

4071

}

4072

4073

#define single_plane_enabled(mask) is_power_of_2(mask)

4073

#define single_plane_enabled(mask) is_power_of_2(mask)

4074

4075

static void g4x_update_wm(struct drm_device *dev)

4075

static void g4x_update_wm(struct drm_device *dev)

4076

{

4076

{

4077

static const int sr_latency_ns = 12000;

4077

static const int sr_latency_ns = 12000;

4078

struct drm_i915_private *dev_priv = dev->dev_private;

4078

struct drm_i915_private *dev_priv = dev->dev_private;

4079

int planea_wm, planeb_wm, cursora_wm, cursorb_wm;

4079

int planea_wm, planeb_wm, cursora_wm, cursorb_wm;

4080

int plane_sr, cursor_sr;

4080

int plane_sr, cursor_sr;

4081

unsigned int enabled = 0;

4081

unsigned int enabled = 0;

4082

4083

if (g4x_compute_wm0(dev, 0,

4083

if (g4x_compute_wm0(dev, 0,

4084

&g4x_wm_info, latency_ns,

4084

&g4x_wm_info, latency_ns,

4085

&g4x_cursor_wm_info, latency_ns,

4085

&g4x_cursor_wm_info, latency_ns,

4086

&planea_wm, &cursora_wm))

4086

&planea_wm, &cursora_wm))

4087

enabled |= 1;

4087

enabled |= 1;

4088

4089

if (g4x_compute_wm0(dev, 1,

4089

if (g4x_compute_wm0(dev, 1,

4090

&g4x_wm_info, latency_ns,

4090

&g4x_wm_info, latency_ns,

4091

&g4x_cursor_wm_info, latency_ns,

4091

&g4x_cursor_wm_info, latency_ns,

4092

&planeb_wm, &cursorb_wm))

4092

&planeb_wm, &cursorb_wm))

4093

enabled |= 2;

4093

enabled |= 2;

4094

4095

plane_sr = cursor_sr = 0;

4095

plane_sr = cursor_sr = 0;

4096

if (single_plane_enabled(enabled) &&

4096

if (single_plane_enabled(enabled) &&

4097

g4x_compute_srwm(dev, ffs(enabled) - 1,

4097

g4x_compute_srwm(dev, ffs(enabled) - 1,

4098

sr_latency_ns,

4098

sr_latency_ns,

4099

&g4x_wm_info,

4099

&g4x_wm_info,

4100

&g4x_cursor_wm_info,

4100

&g4x_cursor_wm_info,

4101

&plane_sr, &cursor_sr))

4101

&plane_sr, &cursor_sr))

4102

I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);

4102

I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);

4103

else

4103

else

4104

I915_WRITE(FW_BLC_SELF,

4104

I915_WRITE(FW_BLC_SELF,

4105

I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);

4105

I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);

4106

4107

DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",

4107

DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",

4108

planea_wm, cursora_wm,

4108

planea_wm, cursora_wm,

4109

planeb_wm, cursorb_wm,

4109

planeb_wm, cursorb_wm,

4110

plane_sr, cursor_sr);

4110

plane_sr, cursor_sr);

4111

4112

I915_WRITE(DSPFW1,

4112

I915_WRITE(DSPFW1,

4113

(plane_sr << DSPFW_SR_SHIFT) |

4113

(plane_sr << DSPFW_SR_SHIFT) |

4114

(cursorb_wm << DSPFW_CURSORB_SHIFT) |

4114

(cursorb_wm << DSPFW_CURSORB_SHIFT) |

4115

(planeb_wm << DSPFW_PLANEB_SHIFT) |

4115

(planeb_wm << DSPFW_PLANEB_SHIFT) |

4116

planea_wm);

4116

planea_wm);

4117

I915_WRITE(DSPFW2,

4117

I915_WRITE(DSPFW2,

4118

(I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |

4118

(I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |

4119

(cursora_wm << DSPFW_CURSORA_SHIFT));

4119

(cursora_wm << DSPFW_CURSORA_SHIFT));

4120

/* HPLL off in SR has some issues on G4x... disable it */

4120

/* HPLL off in SR has some issues on G4x... disable it */

4121

I915_WRITE(DSPFW3,

4121

I915_WRITE(DSPFW3,

4122

(I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |

4122

(I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |

4123

(cursor_sr << DSPFW_CURSOR_SR_SHIFT));

4123

(cursor_sr << DSPFW_CURSOR_SR_SHIFT));

4124

}

4124

}

4125

4126

static void i965_update_wm(struct drm_device *dev)

4126

static void i965_update_wm(struct drm_device *dev)

4127

{

4127

{

4128

struct drm_i915_private *dev_priv = dev->dev_private;

4128

struct drm_i915_private *dev_priv = dev->dev_private;

4129

struct drm_crtc *crtc;

4129

struct drm_crtc *crtc;

4130

int srwm = 1;

4130

int srwm = 1;

4131

int cursor_sr = 16;

4131

int cursor_sr = 16;

4132

4133

/* Calc sr entries for one plane configs */

4133

/* Calc sr entries for one plane configs */

4134

crtc = single_enabled_crtc(dev);

4134

crtc = single_enabled_crtc(dev);

4135

if (crtc) {

4135

if (crtc) {

4136

/* self-refresh has much higher latency */

4136

/* self-refresh has much higher latency */

4137

static const int sr_latency_ns = 12000;

4137

static const int sr_latency_ns = 12000;

4138

int clock = crtc->mode.clock;

4138

int clock = crtc->mode.clock;

4139

int htotal = crtc->mode.htotal;

4139

int htotal = crtc->mode.htotal;

4140

int hdisplay = crtc->mode.hdisplay;

4140

int hdisplay = crtc->mode.hdisplay;

4141

int pixel_size = crtc->fb->bits_per_pixel / 8;

4141

int pixel_size = crtc->fb->bits_per_pixel / 8;

4142

unsigned long line_time_us;

4142

unsigned long line_time_us;

4143

int entries;

4143

int entries;

4144

4145

line_time_us = ((htotal * 1000) / clock);

4145

line_time_us = ((htotal * 1000) / clock);

4146

4147

/* Use ns/us then divide to preserve precision */

4147

/* Use ns/us then divide to preserve precision */

4148

entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *

4148

entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *

4149

pixel_size * hdisplay;

4149

pixel_size * hdisplay;

4150

entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);

4150

entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);

4151

srwm = I965_FIFO_SIZE - entries;

4151

srwm = I965_FIFO_SIZE - entries;

4152

if (srwm < 0)

4152

if (srwm < 0)

4153

srwm = 1;

4153

srwm = 1;

4154

srwm &= 0x1ff;

4154

srwm &= 0x1ff;

4155

DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",

4155

DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",

4156

entries, srwm);

4156

entries, srwm);

4157

4158

entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *

4158

entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *

4159

pixel_size * 64;

4159

pixel_size * 64;

4160

entries = DIV_ROUND_UP(entries,

4160

entries = DIV_ROUND_UP(entries,

4161

i965_cursor_wm_info.cacheline_size);

4161

i965_cursor_wm_info.cacheline_size);

4162

cursor_sr = i965_cursor_wm_info.fifo_size -

4162

cursor_sr = i965_cursor_wm_info.fifo_size -

4163

(entries + i965_cursor_wm_info.guard_size);

4163

(entries + i965_cursor_wm_info.guard_size);

4164

4165

if (cursor_sr > i965_cursor_wm_info.max_wm)

4165

if (cursor_sr > i965_cursor_wm_info.max_wm)

4166

cursor_sr = i965_cursor_wm_info.max_wm;

4166

cursor_sr = i965_cursor_wm_info.max_wm;

4167

4168

DRM_DEBUG_KMS("self-refresh watermark: display plane %d "

4168

DRM_DEBUG_KMS("self-refresh watermark: display plane %d "

4169

"cursor %d\n", srwm, cursor_sr);

4169

"cursor %d\n", srwm, cursor_sr);

4170

4171

if (IS_CRESTLINE(dev))

4171

if (IS_CRESTLINE(dev))

4172

I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);

4172

I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);

4173

} else {

4173

} else {

4174

/* Turn off self refresh if both pipes are enabled */

4174

/* Turn off self refresh if both pipes are enabled */

4175

if (IS_CRESTLINE(dev))

4175

if (IS_CRESTLINE(dev))

4176

I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)

4176

I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)

4177

& ~FW_BLC_SELF_EN);

4177

& ~FW_BLC_SELF_EN);

4178

}

4178

}

4179

4180

DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",

4180

DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",

4181

srwm);

4181

srwm);

4182

4183

/* 965 has limitations... */

4183

/* 965 has limitations... */

4184

I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |

4184

I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |

4185

(8 << 16) | (8 << 8) | (8 << 0));

4185

(8 << 16) | (8 << 8) | (8 << 0));

4186

I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));

4186

I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));

4187

/* update cursor SR watermark */

4187

/* update cursor SR watermark */

4188

I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));

4188

I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));

4189

}

4189

}

4190

4191

static void i9xx_update_wm(struct drm_device *dev)

4191

static void i9xx_update_wm(struct drm_device *dev)

4192

{

4192

{

4193

struct drm_i915_private *dev_priv = dev->dev_private;

4193

struct drm_i915_private *dev_priv = dev->dev_private;

4194

const struct intel_watermark_params *wm_info;

4194

const struct intel_watermark_params *wm_info;

4195

uint32_t fwater_lo;

4195

uint32_t fwater_lo;

4196

uint32_t fwater_hi;

4196

uint32_t fwater_hi;

4197

int cwm, srwm = 1;

4197

int cwm, srwm = 1;

4198

int fifo_size;

4198

int fifo_size;

4199

int planea_wm, planeb_wm;

4199

int planea_wm, planeb_wm;

4200

struct drm_crtc *crtc, *enabled = NULL;

4200

struct drm_crtc *crtc, *enabled = NULL;

4201

4202

if (IS_I945GM(dev))

4202

if (IS_I945GM(dev))

4203

wm_info = &i945_wm_info;

4203

wm_info = &i945_wm_info;

4204

else if (!IS_GEN2(dev))

4204

else if (!IS_GEN2(dev))

4205

wm_info = &i915_wm_info;

4205

wm_info = &i915_wm_info;

4206

else

4206

else

4207

wm_info = &i855_wm_info;

4207

wm_info = &i855_wm_info;

4208

4209

fifo_size = dev_priv->display.get_fifo_size(dev, 0);

4209

fifo_size = dev_priv->display.get_fifo_size(dev, 0);

4210

crtc = intel_get_crtc_for_plane(dev, 0);

4210

crtc = intel_get_crtc_for_plane(dev, 0);

4211

if (crtc->enabled && crtc->fb) {

4211

if (crtc->enabled && crtc->fb) {

4212

planea_wm = intel_calculate_wm(crtc->mode.clock,

4212

planea_wm = intel_calculate_wm(crtc->mode.clock,

4213

wm_info, fifo_size,

4213

wm_info, fifo_size,

4214

crtc->fb->bits_per_pixel / 8,

4214

crtc->fb->bits_per_pixel / 8,

4215

latency_ns);

4215

latency_ns);

4216

enabled = crtc;

4216

enabled = crtc;

4217

} else

4217

} else

4218

planea_wm = fifo_size - wm_info->guard_size;

4218

planea_wm = fifo_size - wm_info->guard_size;

4219

4220

fifo_size = dev_priv->display.get_fifo_size(dev, 1);

4220

fifo_size = dev_priv->display.get_fifo_size(dev, 1);

4221

crtc = intel_get_crtc_for_plane(dev, 1);

4221

crtc = intel_get_crtc_for_plane(dev, 1);

4222

if (crtc->enabled && crtc->fb) {

4222

if (crtc->enabled && crtc->fb) {

4223

planeb_wm = intel_calculate_wm(crtc->mode.clock,

4223

planeb_wm = intel_calculate_wm(crtc->mode.clock,

4224

wm_info, fifo_size,

4224

wm_info, fifo_size,

4225

crtc->fb->bits_per_pixel / 8,

4225

crtc->fb->bits_per_pixel / 8,

4226

latency_ns);

4226

latency_ns);

4227

if (enabled == NULL)

4227

if (enabled == NULL)

4228

enabled = crtc;

4228

enabled = crtc;

4229

else

4229

else

4230

enabled = NULL;

4230

enabled = NULL;

4231

} else

4231

} else

4232

planeb_wm = fifo_size - wm_info->guard_size;

4232

planeb_wm = fifo_size - wm_info->guard_size;

4233

4234

DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);

4234

DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);

4235

4236

/*

4236

/*

4237

* Overlay gets an aggressive default since video jitter is bad.

4237

* Overlay gets an aggressive default since video jitter is bad.

4238

*/

4238

*/

4239

cwm = 2;

4239

cwm = 2;

4240

4241

/* Play safe and disable self-refresh before adjusting watermarks. */

4241

/* Play safe and disable self-refresh before adjusting watermarks. */

4242

if (IS_I945G(dev) || IS_I945GM(dev))

4242

if (IS_I945G(dev) || IS_I945GM(dev))

4243

I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);

4243

I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);

4244

else if (IS_I915GM(dev))

4244

else if (IS_I915GM(dev))

4245

I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);

4245

I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);

4246

4247

/* Calc sr entries for one plane configs */

4247

/* Calc sr entries for one plane configs */

4248

if (HAS_FW_BLC(dev) && enabled) {

4248

if (HAS_FW_BLC(dev) && enabled) {

4249

/* self-refresh has much higher latency */

4249

/* self-refresh has much higher latency */

4250

static const int sr_latency_ns = 6000;

4250

static const int sr_latency_ns = 6000;

4251

int clock = enabled->mode.clock;

4251

int clock = enabled->mode.clock;

4252

int htotal = enabled->mode.htotal;

4252

int htotal = enabled->mode.htotal;

4253

int hdisplay = enabled->mode.hdisplay;

4253

int hdisplay = enabled->mode.hdisplay;

4254

int pixel_size = enabled->fb->bits_per_pixel / 8;

4254

int pixel_size = enabled->fb->bits_per_pixel / 8;

4255

unsigned long line_time_us;

4255

unsigned long line_time_us;

4256

int entries;

4256

int entries;

4257

4258

line_time_us = (htotal * 1000) / clock;

4258

line_time_us = (htotal * 1000) / clock;

4259

4260

/* Use ns/us then divide to preserve precision */

4260

/* Use ns/us then divide to preserve precision */

4261

entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *

4261

entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *

4262

pixel_size * hdisplay;

4262

pixel_size * hdisplay;

4263

entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);

4263

entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);

4264

DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);

4264

DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);

4265

srwm = wm_info->fifo_size - entries;

4265

srwm = wm_info->fifo_size - entries;

4266

if (srwm < 0)

4266

if (srwm < 0)

4267

srwm = 1;

4267

srwm = 1;

4268

4269

if (IS_I945G(dev) || IS_I945GM(dev))

4269

if (IS_I945G(dev) || IS_I945GM(dev))

4270

I915_WRITE(FW_BLC_SELF,

4270

I915_WRITE(FW_BLC_SELF,

4271

FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));

4271

FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));

4272

else if (IS_I915GM(dev))

4272

else if (IS_I915GM(dev))

4273

I915_WRITE(FW_BLC_SELF, srwm & 0x3f);

4273

I915_WRITE(FW_BLC_SELF, srwm & 0x3f);

4274

}

4274

}

4275

4276

DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",

4276

DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",

4277

planea_wm, planeb_wm, cwm, srwm);

4277

planea_wm, planeb_wm, cwm, srwm);

4278

4279

fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);

4279

fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);

4280

fwater_hi = (cwm & 0x1f);

4280

fwater_hi = (cwm & 0x1f);

4281

4282

/* Set request length to 8 cachelines per fetch */

4282

/* Set request length to 8 cachelines per fetch */

4283

fwater_lo = fwater_lo | (1 << 24) | (1 << 8);

4283

fwater_lo = fwater_lo | (1 << 24) | (1 << 8);

4284

fwater_hi = fwater_hi | (1 << 8);

4284

fwater_hi = fwater_hi | (1 << 8);

4285

4286

I915_WRITE(FW_BLC, fwater_lo);

4286

I915_WRITE(FW_BLC, fwater_lo);

4287

I915_WRITE(FW_BLC2, fwater_hi);

4287

I915_WRITE(FW_BLC2, fwater_hi);

4288

4289

if (HAS_FW_BLC(dev)) {

4289

if (HAS_FW_BLC(dev)) {

4290

if (enabled) {

4290

if (enabled) {

4291

if (IS_I945G(dev) || IS_I945GM(dev))

4291

if (IS_I945G(dev) || IS_I945GM(dev))

4292

I915_WRITE(FW_BLC_SELF,

4292

I915_WRITE(FW_BLC_SELF,

4293

FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);

4293

FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);

4294

else if (IS_I915GM(dev))

4294

else if (IS_I915GM(dev))

4295

I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);

4295

I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);

4296

DRM_DEBUG_KMS("memory self refresh enabled\n");

4296

DRM_DEBUG_KMS("memory self refresh enabled\n");

4297

} else

4297

} else

4298

DRM_DEBUG_KMS("memory self refresh disabled\n");

4298

DRM_DEBUG_KMS("memory self refresh disabled\n");

4299

}

4299

}

4300

}

4300

}

4301

4302

static void i830_update_wm(struct drm_device *dev)

4302

static void i830_update_wm(struct drm_device *dev)

4303

{

4303

{

4304

struct drm_i915_private *dev_priv = dev->dev_private;

4304

struct drm_i915_private *dev_priv = dev->dev_private;

4305

struct drm_crtc *crtc;

4305

struct drm_crtc *crtc;

4306

uint32_t fwater_lo;

4306

uint32_t fwater_lo;

4307

int planea_wm;

4307

int planea_wm;

4308

4309

crtc = single_enabled_crtc(dev);

4309

crtc = single_enabled_crtc(dev);

4310

if (crtc == NULL)

4310

if (crtc == NULL)

4311

return;

4311

return;

4312

4313

planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,

4313

planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,

4314

dev_priv->display.get_fifo_size(dev, 0),

4314

dev_priv->display.get_fifo_size(dev, 0),

4315

crtc->fb->bits_per_pixel / 8,

4315

crtc->fb->bits_per_pixel / 8,

4316

latency_ns);

4316

latency_ns);

4317

fwater_lo = I915_READ(FW_BLC) & ~0xfff;

4317

fwater_lo = I915_READ(FW_BLC) & ~0xfff;

4318

fwater_lo |= (3<<8) | planea_wm;

4318

fwater_lo |= (3<<8) | planea_wm;

4319

4320

DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);

4320

DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);

4321

4322

I915_WRITE(FW_BLC, fwater_lo);

4322

I915_WRITE(FW_BLC, fwater_lo);

4323

}

4323

}

4324

4325

#define ILK_LP0_PLANE_LATENCY 700

4325

#define ILK_LP0_PLANE_LATENCY 700

4326

#define ILK_LP0_CURSOR_LATENCY 1300

4326

#define ILK_LP0_CURSOR_LATENCY 1300

4327

4328

/*

4328

/*

4329

* Check the wm result.

4329

* Check the wm result.

4330

*

4330

*

4331

* If any calculated watermark values is larger than the maximum value that

4331

* If any calculated watermark values is larger than the maximum value that

4332

* can be programmed into the associated watermark register, that watermark

4332

* can be programmed into the associated watermark register, that watermark

4333

* must be disabled.

4333

* must be disabled.

4334

*/

4334

*/

4335

static bool ironlake_check_srwm(struct drm_device *dev, int level,

4335

static bool ironlake_check_srwm(struct drm_device *dev, int level,

4336

int fbc_wm, int display_wm, int cursor_wm,

4336

int fbc_wm, int display_wm, int cursor_wm,

4337

const struct intel_watermark_params *display,

4337

const struct intel_watermark_params *display,

4338

const struct intel_watermark_params *cursor)

4338

const struct intel_watermark_params *cursor)

4339

{

4339

{

4340

struct drm_i915_private *dev_priv = dev->dev_private;

4340

struct drm_i915_private *dev_priv = dev->dev_private;

4341

4342

DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"

4342

DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"

4343

" cursor %d\n", level, display_wm, fbc_wm, cursor_wm);

4343

" cursor %d\n", level, display_wm, fbc_wm, cursor_wm);

4344

4345

if (fbc_wm > SNB_FBC_MAX_SRWM) {

4345

if (fbc_wm > SNB_FBC_MAX_SRWM) {

4346

DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",

4346

DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",

4347

fbc_wm, SNB_FBC_MAX_SRWM, level);

4347

fbc_wm, SNB_FBC_MAX_SRWM, level);

4348

4349

/* fbc has it's own way to disable FBC WM */

4349

/* fbc has it's own way to disable FBC WM */

4350

I915_WRITE(DISP_ARB_CTL,

4350

I915_WRITE(DISP_ARB_CTL,

4351

I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);

4351

I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);

4352

return false;

4352

return false;

4353

}

4353

}

4354

4355

if (display_wm > display->max_wm) {

4355

if (display_wm > display->max_wm) {

4356

DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",

4356

DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",

4357

display_wm, SNB_DISPLAY_MAX_SRWM, level);

4357

display_wm, SNB_DISPLAY_MAX_SRWM, level);

4358

return false;

4358

return false;

4359

}

4359

}

4360

4361

if (cursor_wm > cursor->max_wm) {

4361

if (cursor_wm > cursor->max_wm) {

4362

DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",

4362

DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",

4363

cursor_wm, SNB_CURSOR_MAX_SRWM, level);

4363

cursor_wm, SNB_CURSOR_MAX_SRWM, level);

4364

return false;

4364

return false;

4365

}

4365

}

4366

4367

if (!(fbc_wm || display_wm || cursor_wm)) {

4367

if (!(fbc_wm || display_wm || cursor_wm)) {

4368

DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);

4368

DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);

4369

return false;

4369

return false;

4370

}

4370

}

4371

4372

return true;

4372

return true;

4373

}

4373

}

4374

4375

/*

4375

/*

4376

* Compute watermark values of WM[1-3],

4376

* Compute watermark values of WM[1-3],

4377

*/

4377

*/

4378

static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,

4378

static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,

4379

int latency_ns,

4379

int latency_ns,

4380

const struct intel_watermark_params *display,

4380

const struct intel_watermark_params *display,

4381

const struct intel_watermark_params *cursor,

4381

const struct intel_watermark_params *cursor,

4382

int *fbc_wm, int *display_wm, int *cursor_wm)

4382

int *fbc_wm, int *display_wm, int *cursor_wm)

4383

{

4383

{

4384

struct drm_crtc *crtc;

4384

struct drm_crtc *crtc;

4385

unsigned long line_time_us;

4385

unsigned long line_time_us;

4386

int hdisplay, htotal, pixel_size, clock;

4386

int hdisplay, htotal, pixel_size, clock;

4387

int line_count, line_size;

4387

int line_count, line_size;

4388

int small, large;

4388

int small, large;

4389

int entries;

4389

int entries;

4390

4391

if (!latency_ns) {

4391

if (!latency_ns) {

4392

*fbc_wm = *display_wm = *cursor_wm = 0;

4392

*fbc_wm = *display_wm = *cursor_wm = 0;

4393

return false;

4393

return false;

4394

}

4394

}

4395

4396

crtc = intel_get_crtc_for_plane(dev, plane);

4396

crtc = intel_get_crtc_for_plane(dev, plane);

4397

hdisplay = crtc->mode.hdisplay;

4397

hdisplay = crtc->mode.hdisplay;

4398

htotal = crtc->mode.htotal;

4398

htotal = crtc->mode.htotal;

4399

clock = crtc->mode.clock;

4399

clock = crtc->mode.clock;

4400

pixel_size = crtc->fb->bits_per_pixel / 8;

4400

pixel_size = crtc->fb->bits_per_pixel / 8;

4401

4402

line_time_us = (htotal * 1000) / clock;

4402

line_time_us = (htotal * 1000) / clock;

4403

line_count = (latency_ns / line_time_us + 1000) / 1000;

4403

line_count = (latency_ns / line_time_us + 1000) / 1000;

4404

line_size = hdisplay * pixel_size;

4404

line_size = hdisplay * pixel_size;

4405

4406

/* Use the minimum of the small and large buffer method for primary */

4406

/* Use the minimum of the small and large buffer method for primary */

4407

small = ((clock * pixel_size / 1000) * latency_ns) / 1000;

4407

small = ((clock * pixel_size / 1000) * latency_ns) / 1000;

4408

large = line_count * line_size;

4408

large = line_count * line_size;

4409

4410

entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);

4410

entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);

4411

*display_wm = entries + display->guard_size;

4411

*display_wm = entries + display->guard_size;

4412

4413

/*

4413

/*

4414

* Spec says:

4414

* Spec says:

4415

* FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2

4415

* FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2

4416

*/

4416

*/

4417

*fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;

4417

*fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;

4418

4419

/* calculate the self-refresh watermark for display cursor */

4419

/* calculate the self-refresh watermark for display cursor */

4420

entries = line_count * pixel_size * 64;

4420

entries = line_count * pixel_size * 64;

4421

entries = DIV_ROUND_UP(entries, cursor->cacheline_size);

4421

entries = DIV_ROUND_UP(entries, cursor->cacheline_size);

4422

*cursor_wm = entries + cursor->guard_size;

4422

*cursor_wm = entries + cursor->guard_size;

4423

4424

return ironlake_check_srwm(dev, level,

4424

return ironlake_check_srwm(dev, level,

4425

*fbc_wm, *display_wm, *cursor_wm,

4425

*fbc_wm, *display_wm, *cursor_wm,

4426

display, cursor);

4426

display, cursor);

4427

}

4427

}

4428

4429

static void ironlake_update_wm(struct drm_device *dev)

4429

static void ironlake_update_wm(struct drm_device *dev)

4430

{

4430

{

4431

struct drm_i915_private *dev_priv = dev->dev_private;

4431

struct drm_i915_private *dev_priv = dev->dev_private;

4432

int fbc_wm, plane_wm, cursor_wm;

4432

int fbc_wm, plane_wm, cursor_wm;

4433

unsigned int enabled;

4433

unsigned int enabled;

4434

4435

enabled = 0;

4435

enabled = 0;

4436

if (g4x_compute_wm0(dev, 0,

4436

if (g4x_compute_wm0(dev, 0,

4437

&ironlake_display_wm_info,

4437

&ironlake_display_wm_info,

4438

ILK_LP0_PLANE_LATENCY,

4438

ILK_LP0_PLANE_LATENCY,

4439

&ironlake_cursor_wm_info,

4439

&ironlake_cursor_wm_info,

4440

ILK_LP0_CURSOR_LATENCY,

4440

ILK_LP0_CURSOR_LATENCY,

4441

&plane_wm, &cursor_wm)) {

4441

&plane_wm, &cursor_wm)) {

4442

I915_WRITE(WM0_PIPEA_ILK,

4442

I915_WRITE(WM0_PIPEA_ILK,

4443

(plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);

4443

(plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);

4444

DRM_DEBUG_KMS("FIFO watermarks For pipe A -"

4444

DRM_DEBUG_KMS("FIFO watermarks For pipe A -"

4445

" plane %d, " "cursor: %d\n",

4445

" plane %d, " "cursor: %d\n",

4446

plane_wm, cursor_wm);

4446

plane_wm, cursor_wm);

4447

enabled |= 1;

4447

enabled |= 1;

4448

}

4448

}

4449

4450

if (g4x_compute_wm0(dev, 1,

4450

if (g4x_compute_wm0(dev, 1,

4451

&ironlake_display_wm_info,

4451

&ironlake_display_wm_info,

4452

ILK_LP0_PLANE_LATENCY,

4452

ILK_LP0_PLANE_LATENCY,

4453

&ironlake_cursor_wm_info,

4453

&ironlake_cursor_wm_info,

4454

ILK_LP0_CURSOR_LATENCY,

4454

ILK_LP0_CURSOR_LATENCY,

4455

&plane_wm, &cursor_wm)) {

4455

&plane_wm, &cursor_wm)) {

4456

I915_WRITE(WM0_PIPEB_ILK,

4456

I915_WRITE(WM0_PIPEB_ILK,

4457

(plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);

4457

(plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);

4458

DRM_DEBUG_KMS("FIFO watermarks For pipe B -"

4458

DRM_DEBUG_KMS("FIFO watermarks For pipe B -"

4459

" plane %d, cursor: %d\n",

4459

" plane %d, cursor: %d\n",

4460

plane_wm, cursor_wm);

4460

plane_wm, cursor_wm);

4461

enabled |= 2;

4461

enabled |= 2;

4462

}

4462

}

4463

4464

/*

4464

/*

4465

* Calculate and update the self-refresh watermark only when one

4465

* Calculate and update the self-refresh watermark only when one

4466

* display plane is used.

4466

* display plane is used.

4467

*/

4467

*/

4468

I915_WRITE(WM3_LP_ILK, 0);

4468

I915_WRITE(WM3_LP_ILK, 0);

4469

I915_WRITE(WM2_LP_ILK, 0);

4469

I915_WRITE(WM2_LP_ILK, 0);

4470

I915_WRITE(WM1_LP_ILK, 0);

4470

I915_WRITE(WM1_LP_ILK, 0);

4471

4472

if (!single_plane_enabled(enabled))

4472

if (!single_plane_enabled(enabled))

4473

return;

4473

return;

4474

enabled = ffs(enabled) - 1;

4474

enabled = ffs(enabled) - 1;

4475

4476

/* WM1 */

4476

/* WM1 */

4477

if (!ironlake_compute_srwm(dev, 1, enabled,

4477

if (!ironlake_compute_srwm(dev, 1, enabled,

4478

ILK_READ_WM1_LATENCY() * 500,

4478

ILK_READ_WM1_LATENCY() * 500,

4479

&ironlake_display_srwm_info,

4479

&ironlake_display_srwm_info,

4480

&ironlake_cursor_srwm_info,

4480

&ironlake_cursor_srwm_info,

4481

&fbc_wm, &plane_wm, &cursor_wm))

4481

&fbc_wm, &plane_wm, &cursor_wm))

4482

return;

4482

return;

4483

4484

I915_WRITE(WM1_LP_ILK,

4484

I915_WRITE(WM1_LP_ILK,

4485

WM1_LP_SR_EN |

4485

WM1_LP_SR_EN |

4486

(ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |

4486

(ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |

4487

(fbc_wm << WM1_LP_FBC_SHIFT) |

4487

(fbc_wm << WM1_LP_FBC_SHIFT) |

4488

(plane_wm << WM1_LP_SR_SHIFT) |

4488

(plane_wm << WM1_LP_SR_SHIFT) |

4489

cursor_wm);

4489

cursor_wm);

4490

4491

/* WM2 */

4491

/* WM2 */

4492

if (!ironlake_compute_srwm(dev, 2, enabled,

4492

if (!ironlake_compute_srwm(dev, 2, enabled,

4493

ILK_READ_WM2_LATENCY() * 500,

4493

ILK_READ_WM2_LATENCY() * 500,

4494

&ironlake_display_srwm_info,

4494

&ironlake_display_srwm_info,

4495

&ironlake_cursor_srwm_info,

4495

&ironlake_cursor_srwm_info,

4496

&fbc_wm, &plane_wm, &cursor_wm))

4496

&fbc_wm, &plane_wm, &cursor_wm))

4497

return;

4497

return;

4498

4499

I915_WRITE(WM2_LP_ILK,

4499

I915_WRITE(WM2_LP_ILK,

4500

WM2_LP_EN |

4500

WM2_LP_EN |

4501

(ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |

4501

(ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |

4502

(fbc_wm << WM1_LP_FBC_SHIFT) |

4502

(fbc_wm << WM1_LP_FBC_SHIFT) |

4503

(plane_wm << WM1_LP_SR_SHIFT) |

4503

(plane_wm << WM1_LP_SR_SHIFT) |

4504

cursor_wm);

4504

cursor_wm);

4505

4506

/*

4506

/*

4507

* WM3 is unsupported on ILK, probably because we don't have latency

4507

* WM3 is unsupported on ILK, probably because we don't have latency

4508

* data for that power state

4508

* data for that power state

4509

*/

4509

*/

4510

}

4510

}

4511

4512

static void sandybridge_update_wm(struct drm_device *dev)

4512

static void sandybridge_update_wm(struct drm_device *dev)

4513

{

4513

{

4514

struct drm_i915_private *dev_priv = dev->dev_private;

4514

struct drm_i915_private *dev_priv = dev->dev_private;

4515

int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */

4515

int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */

4516

int fbc_wm, plane_wm, cursor_wm;

4516

int fbc_wm, plane_wm, cursor_wm;

4517

unsigned int enabled;

4517

unsigned int enabled;

4518

4519

enabled = 0;

4519

enabled = 0;

4520

if (g4x_compute_wm0(dev, 0,

4520

if (g4x_compute_wm0(dev, 0,

4521

&sandybridge_display_wm_info, latency,

4521

&sandybridge_display_wm_info, latency,

4522

&sandybridge_cursor_wm_info, latency,

4522

&sandybridge_cursor_wm_info, latency,

4523

&plane_wm, &cursor_wm)) {

4523

&plane_wm, &cursor_wm)) {

4524

I915_WRITE(WM0_PIPEA_ILK,

4524

I915_WRITE(WM0_PIPEA_ILK,

4525

(plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);

4525

(plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);

4526

DRM_DEBUG_KMS("FIFO watermarks For pipe A -"

4526

DRM_DEBUG_KMS("FIFO watermarks For pipe A -"

4527

" plane %d, " "cursor: %d\n",

4527

" plane %d, " "cursor: %d\n",

4528

plane_wm, cursor_wm);

4528

plane_wm, cursor_wm);

4529

enabled |= 1;

4529

enabled |= 1;

4530

}

4530

}

4531

4532

if (g4x_compute_wm0(dev, 1,

4532

if (g4x_compute_wm0(dev, 1,

4533

&sandybridge_display_wm_info, latency,

4533

&sandybridge_display_wm_info, latency,

4534

&sandybridge_cursor_wm_info, latency,

4534

&sandybridge_cursor_wm_info, latency,

4535

&plane_wm, &cursor_wm)) {

4535

&plane_wm, &cursor_wm)) {

4536

I915_WRITE(WM0_PIPEB_ILK,

4536

I915_WRITE(WM0_PIPEB_ILK,

4537

(plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);

4537

(plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);

4538

DRM_DEBUG_KMS("FIFO watermarks For pipe B -"

4538

DRM_DEBUG_KMS("FIFO watermarks For pipe B -"

4539

" plane %d, cursor: %d\n",

4539

" plane %d, cursor: %d\n",

4540

plane_wm, cursor_wm);

4540

plane_wm, cursor_wm);

4541

enabled |= 2;

4541

enabled |= 2;

4542

}

4542

}

4543

4544

/* IVB has 3 pipes */

4544

/* IVB has 3 pipes */

4545

if (IS_IVYBRIDGE(dev) &&

4545

if (IS_IVYBRIDGE(dev) &&

4546

g4x_compute_wm0(dev, 2,

4546

g4x_compute_wm0(dev, 2,

4547

&sandybridge_display_wm_info, latency,

4547

&sandybridge_display_wm_info, latency,

4548

&sandybridge_cursor_wm_info, latency,

4548

&sandybridge_cursor_wm_info, latency,

4549

&plane_wm, &cursor_wm)) {

4549

&plane_wm, &cursor_wm)) {

4550

I915_WRITE(WM0_PIPEC_IVB,

4550

I915_WRITE(WM0_PIPEC_IVB,

4551

(plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);

4551

(plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);

4552

DRM_DEBUG_KMS("FIFO watermarks For pipe C -"

4552

DRM_DEBUG_KMS("FIFO watermarks For pipe C -"

4553

" plane %d, cursor: %d\n",

4553

" plane %d, cursor: %d\n",

4554

plane_wm, cursor_wm);

4554

plane_wm, cursor_wm);

4555

enabled |= 3;

4555

enabled |= 3;

4556

}

4556

}

4557

4558

/*

4558

/*

4559

* Calculate and update the self-refresh watermark only when one

4559

* Calculate and update the self-refresh watermark only when one

4560

* display plane is used.

4560

* display plane is used.

4561

*

4561

*

4562

* SNB support 3 levels of watermark.

4562

* SNB support 3 levels of watermark.

4563

*

4563

*

4564

* WM1/WM2/WM2 watermarks have to be enabled in the ascending order,

4564

* WM1/WM2/WM2 watermarks have to be enabled in the ascending order,

4565

* and disabled in the descending order

4565

* and disabled in the descending order

4566

*

4566

*

4567

*/

4567

*/

4568

I915_WRITE(WM3_LP_ILK, 0);

4568

I915_WRITE(WM3_LP_ILK, 0);

4569

I915_WRITE(WM2_LP_ILK, 0);

4569

I915_WRITE(WM2_LP_ILK, 0);

4570

I915_WRITE(WM1_LP_ILK, 0);

4570

I915_WRITE(WM1_LP_ILK, 0);

4571

4572

if (!single_plane_enabled(enabled))

4572

if (!single_plane_enabled(enabled))

4573

return;

4573

return;

4574

enabled = ffs(enabled) - 1;

4574

enabled = ffs(enabled) - 1;

4575

4576

/* WM1 */

4576

/* WM1 */

4577

if (!ironlake_compute_srwm(dev, 1, enabled,

4577

if (!ironlake_compute_srwm(dev, 1, enabled,

4578

SNB_READ_WM1_LATENCY() * 500,

4578

SNB_READ_WM1_LATENCY() * 500,

4579

&sandybridge_display_srwm_info,

4579

&sandybridge_display_srwm_info,

4580

&sandybridge_cursor_srwm_info,

4580

&sandybridge_cursor_srwm_info,

4581

&fbc_wm, &plane_wm, &cursor_wm))

4581

&fbc_wm, &plane_wm, &cursor_wm))

4582

return;

4582

return;

4583

4584

I915_WRITE(WM1_LP_ILK,

4584

I915_WRITE(WM1_LP_ILK,

4585

WM1_LP_SR_EN |

4585

WM1_LP_SR_EN |

4586

(SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |

4586

(SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |

4587

(fbc_wm << WM1_LP_FBC_SHIFT) |

4587

(fbc_wm << WM1_LP_FBC_SHIFT) |

4588

(plane_wm << WM1_LP_SR_SHIFT) |

4588

(plane_wm << WM1_LP_SR_SHIFT) |

4589

cursor_wm);

4589

cursor_wm);

4590

4591

/* WM2 */

4591

/* WM2 */

4592

if (!ironlake_compute_srwm(dev, 2, enabled,

4592

if (!ironlake_compute_srwm(dev, 2, enabled,

4593

SNB_READ_WM2_LATENCY() * 500,

4593

SNB_READ_WM2_LATENCY() * 500,

4594

&sandybridge_display_srwm_info,

4594

&sandybridge_display_srwm_info,

4595

&sandybridge_cursor_srwm_info,

4595

&sandybridge_cursor_srwm_info,

4596

&fbc_wm, &plane_wm, &cursor_wm))

4596

&fbc_wm, &plane_wm, &cursor_wm))

4597

return;

4597

return;

4598

4599

I915_WRITE(WM2_LP_ILK,

4599

I915_WRITE(WM2_LP_ILK,

4600

WM2_LP_EN |

4600

WM2_LP_EN |

4601

(SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |

4601

(SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |

4602

(fbc_wm << WM1_LP_FBC_SHIFT) |

4602

(fbc_wm << WM1_LP_FBC_SHIFT) |

4603

(plane_wm << WM1_LP_SR_SHIFT) |

4603

(plane_wm << WM1_LP_SR_SHIFT) |

4604

cursor_wm);

4604

cursor_wm);

4605

4606

/* WM3 */

4606

/* WM3 */

4607

if (!ironlake_compute_srwm(dev, 3, enabled,

4607

if (!ironlake_compute_srwm(dev, 3, enabled,

4608

SNB_READ_WM3_LATENCY() * 500,

4608

SNB_READ_WM3_LATENCY() * 500,

4609

&sandybridge_display_srwm_info,

4609

&sandybridge_display_srwm_info,

4610

&sandybridge_cursor_srwm_info,

4610

&sandybridge_cursor_srwm_info,

4611

&fbc_wm, &plane_wm, &cursor_wm))

4611

&fbc_wm, &plane_wm, &cursor_wm))

4612

return;

4612

return;

4613

4614

I915_WRITE(WM3_LP_ILK,

4614

I915_WRITE(WM3_LP_ILK,

4615

WM3_LP_EN |

4615

WM3_LP_EN |

4616

(SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |

4616

(SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |

4617

(fbc_wm << WM1_LP_FBC_SHIFT) |

4617

(fbc_wm << WM1_LP_FBC_SHIFT) |

4618

(plane_wm << WM1_LP_SR_SHIFT) |

4618

(plane_wm << WM1_LP_SR_SHIFT) |

4619

cursor_wm);

4619

cursor_wm);

4620

}

4620

}

4621

4622

/**

4622

/**

4623

* intel_update_watermarks - update FIFO watermark values based on current modes

4623

* intel_update_watermarks - update FIFO watermark values based on current modes

4624

*

4624

*

4625

* Calculate watermark values for the various WM regs based on current mode

4625

* Calculate watermark values for the various WM regs based on current mode

4626

* and plane configuration.

4626

* and plane configuration.

4627

*

4627

*

4628

* There are several cases to deal with here:

4628

* There are several cases to deal with here:

4629

* - normal (i.e. non-self-refresh)

4629

* - normal (i.e. non-self-refresh)

4630

* - self-refresh (SR) mode

4630

* - self-refresh (SR) mode

4631

* - lines are large relative to FIFO size (buffer can hold up to 2)

4631

* - lines are large relative to FIFO size (buffer can hold up to 2)

4632

* - lines are small relative to FIFO size (buffer can hold more than 2

4632

* - lines are small relative to FIFO size (buffer can hold more than 2

4633

* lines), so need to account for TLB latency

4633

* lines), so need to account for TLB latency

4634

*

4634

*

4635

* The normal calculation is:

4635

* The normal calculation is:

4636

* watermark = dotclock * bytes per pixel * latency

4636

* watermark = dotclock * bytes per pixel * latency

4637

* where latency is platform & configuration dependent (we assume pessimal

4637

* where latency is platform & configuration dependent (we assume pessimal

4638

* values here).

4638

* values here).

4639

*

4639

*

4640

* The SR calculation is:

4640

* The SR calculation is:

4641

* watermark = (trunc(latency/line time)+1) * surface width *

4641

* watermark = (trunc(latency/line time)+1) * surface width *

4642

* bytes per pixel

4642

* bytes per pixel

4643

* where

4643

* where

4644

* line time = htotal / dotclock

4644

* line time = htotal / dotclock

4645

* surface width = hdisplay for normal plane and 64 for cursor

4645

* surface width = hdisplay for normal plane and 64 for cursor

4646

* and latency is assumed to be high, as above.

4646

* and latency is assumed to be high, as above.

4647

*

4647

*

4648

* The final value programmed to the register should always be rounded up,

4648

* The final value programmed to the register should always be rounded up,

4649

* and include an extra 2 entries to account for clock crossings.

4649

* and include an extra 2 entries to account for clock crossings.

4650

*

4650

*

4651

* We don't use the sprite, so we can ignore that. And on Crestline we have

4651

* We don't use the sprite, so we can ignore that. And on Crestline we have

4652

* to set the non-SR watermarks to 8.

4652

* to set the non-SR watermarks to 8.

4653

*/

4653

*/

4654

static void intel_update_watermarks(struct drm_device *dev)

4654

static void intel_update_watermarks(struct drm_device *dev)

4655

{

4655

{

4656

struct drm_i915_private *dev_priv = dev->dev_private;

4656

struct drm_i915_private *dev_priv = dev->dev_private;

4657

4658

if (dev_priv->display.update_wm)

4658

if (dev_priv->display.update_wm)

4659

dev_priv->display.update_wm(dev);

4659

dev_priv->display.update_wm(dev);

4660

}

4660

}

4661

4662

static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)

4662

static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)

4663

{

4663

{

4664

if (i915_panel_use_ssc >= 0)

4664

if (i915_panel_use_ssc >= 0)

4665

return i915_panel_use_ssc != 0;

4665

return i915_panel_use_ssc != 0;

4666

return dev_priv->lvds_use_ssc

4666

return dev_priv->lvds_use_ssc

4667

&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);

4667

&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);

4668

}

4668

}

4669

4670

/**

4670

/**

4671

* intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send

4671

* intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send

4672

* @crtc: CRTC structure

4672

* @crtc: CRTC structure

4673

*

4673

*

4674

* A pipe may be connected to one or more outputs. Based on the depth of the

4674

* A pipe may be connected to one or more outputs. Based on the depth of the

4675

* attached framebuffer, choose a good color depth to use on the pipe.

4675

* attached framebuffer, choose a good color depth to use on the pipe.

4676

*

4676

*

4677

* If possible, match the pipe depth to the fb depth. In some cases, this

4677

* If possible, match the pipe depth to the fb depth. In some cases, this

4678

* isn't ideal, because the connected output supports a lesser or restricted

4678

* isn't ideal, because the connected output supports a lesser or restricted

4679

* set of depths. Resolve that here:

4679

* set of depths. Resolve that here:

4680

* LVDS typically supports only 6bpc, so clamp down in that case

4680

* LVDS typically supports only 6bpc, so clamp down in that case

4681

* HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc

4681

* HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc

4682

* Displays may support a restricted set as well, check EDID and clamp as

4682

* Displays may support a restricted set as well, check EDID and clamp as

4683

* appropriate.

4683

* appropriate.

4684

*

4684

*

4685

* RETURNS:

4685

* RETURNS:

4686

* Dithering requirement (i.e. false if display bpc and pipe bpc match,

4686

* Dithering requirement (i.e. false if display bpc and pipe bpc match,

4687

* true if they don't match).

4687

* true if they don't match).

4688

*/

4688

*/

4689

static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,

4689

static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,

4690

unsigned int *pipe_bpp)

4690

unsigned int *pipe_bpp)

4691

{

4691

{

4692

struct drm_device *dev = crtc->dev;

4692

struct drm_device *dev = crtc->dev;

4693

struct drm_i915_private *dev_priv = dev->dev_private;

4693

struct drm_i915_private *dev_priv = dev->dev_private;

4694

struct drm_encoder *encoder;

4694

struct drm_encoder *encoder;

4695

struct drm_connector *connector;

4695

struct drm_connector *connector;

4696

unsigned int display_bpc = UINT_MAX, bpc;

4696

unsigned int display_bpc = UINT_MAX, bpc;

4697

4698

/* Walk the encoders & connectors on this crtc, get min bpc */

4698

/* Walk the encoders & connectors on this crtc, get min bpc */

4699

list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {

4699

list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {

4700

struct intel_encoder *intel_encoder = to_intel_encoder(encoder);

4700

struct intel_encoder *intel_encoder = to_intel_encoder(encoder);

4701

4702

if (encoder->crtc != crtc)

4702

if (encoder->crtc != crtc)

4703

continue;

4703

continue;

4704

4705

if (intel_encoder->type == INTEL_OUTPUT_LVDS) {

4705

if (intel_encoder->type == INTEL_OUTPUT_LVDS) {

4706

unsigned int lvds_bpc;

4706

unsigned int lvds_bpc;

4707

4708

if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==

4708

if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==

4709

LVDS_A3_POWER_UP)

4709

LVDS_A3_POWER_UP)

4710

lvds_bpc = 8;

4710

lvds_bpc = 8;

4711

else

4711

else

4712

lvds_bpc = 6;

4712

lvds_bpc = 6;

4713

4714

if (lvds_bpc < display_bpc) {

4714

if (lvds_bpc < display_bpc) {

4715

DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);

4715

DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);

4716

display_bpc = lvds_bpc;

4716

display_bpc = lvds_bpc;

4717

}

4717

}

4718

continue;

4718

continue;

4719

}

4719

}

4720

4721

if (intel_encoder->type == INTEL_OUTPUT_EDP) {

4721

if (intel_encoder->type == INTEL_OUTPUT_EDP) {

4722

/* Use VBT settings if we have an eDP panel */

4722

/* Use VBT settings if we have an eDP panel */

4723

unsigned int edp_bpc = dev_priv->edp.bpp / 3;

4723

unsigned int edp_bpc = dev_priv->edp.bpp / 3;

4724

4725

if (edp_bpc < display_bpc) {

4725

if (edp_bpc < display_bpc) {

4726

DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);

4726

DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);

4727

display_bpc = edp_bpc;

4727

display_bpc = edp_bpc;

4728

}

4728

}

4729

continue;

4729

continue;

4730

}

4730

}

4731

4732

/* Not one of the known troublemakers, check the EDID */

4732

/* Not one of the known troublemakers, check the EDID */

4733

list_for_each_entry(connector, &dev->mode_config.connector_list,

4733

list_for_each_entry(connector, &dev->mode_config.connector_list,

4734

head) {

4734

head) {

4735

if (connector->encoder != encoder)

4735

if (connector->encoder != encoder)

4736

continue;

4736

continue;

4737

4738

/* Don't use an invalid EDID bpc value */

4738

/* Don't use an invalid EDID bpc value */

4739

if (connector->display_info.bpc &&

4739

if (connector->display_info.bpc &&

4740

connector->display_info.bpc < display_bpc) {

4740

connector->display_info.bpc < display_bpc) {

4741

DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);

4741

DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);

4742

display_bpc = connector->display_info.bpc;

4742

display_bpc = connector->display_info.bpc;

4743

}

4743

}

4744

}

4744

}

4745

4746

/*

4746

/*

4747

* HDMI is either 12 or 8, so if the display lets 10bpc sneak

4747

* HDMI is either 12 or 8, so if the display lets 10bpc sneak

4748

* through, clamp it down. (Note: >12bpc will be caught below.)

4748

* through, clamp it down. (Note: >12bpc will be caught below.)

4749

*/

4749

*/

4750

if (intel_encoder->type == INTEL_OUTPUT_HDMI) {

4750

if (intel_encoder->type == INTEL_OUTPUT_HDMI) {

4751

if (display_bpc > 8 && display_bpc < 12) {

4751

if (display_bpc > 8 && display_bpc < 12) {

4752

DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");

4752

DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");

4753

display_bpc = 12;

4753

display_bpc = 12;

4754

} else {

4754

} else {

4755

DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");

4755

DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");

4756

display_bpc = 8;

4756

display_bpc = 8;

4757

}

4757

}

4758

}

4758

}

4759

}

4759

}

4760

4761

/*

4761

/*

4762

* We could just drive the pipe at the highest bpc all the time and

4762

* We could just drive the pipe at the highest bpc all the time and

4763

* enable dithering as needed, but that costs bandwidth. So choose

4763

* enable dithering as needed, but that costs bandwidth. So choose

4764

* the minimum value that expresses the full color range of the fb but

4764

* the minimum value that expresses the full color range of the fb but

4765

* also stays within the max display bpc discovered above.

4765

* also stays within the max display bpc discovered above.

4766

*/

4766

*/

4767

4768

switch (crtc->fb->depth) {

4768

switch (crtc->fb->depth) {

4769

case 8:

4769

case 8:

4770

bpc = 8; /* since we go through a colormap */

4770

bpc = 8; /* since we go through a colormap */

4771

break;

4771

break;

4772

case 15:

4772

case 15:

4773

case 16:

4773

case 16:

4774

bpc = 6; /* min is 18bpp */

4774

bpc = 6; /* min is 18bpp */

4775

break;

4775

break;

4776

case 24:

4776

case 24:

4777

bpc = 8;

4777

bpc = 8;

4778

break;

4778

break;

4779

case 30:

4779

case 30:

4780

bpc = 10;

4780

bpc = 10;

4781

break;

4781

break;

4782

case 48:

4782

case 48:

4783

bpc = 12;

4783

bpc = 12;

4784

break;

4784

break;

4785

default:

4785

default:

4786

DRM_DEBUG("unsupported depth, assuming 24 bits\n");

4786

DRM_DEBUG("unsupported depth, assuming 24 bits\n");

4787

bpc = min((unsigned int)8, display_bpc);

4787

bpc = min((unsigned int)8, display_bpc);

4788

break;

4788

break;

4789

}

4789

}

4790

4791

display_bpc = min(display_bpc, bpc);

4791

display_bpc = min(display_bpc, bpc);

4792

4793

DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",

4793

DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",

4794

bpc, display_bpc);

4794

bpc, display_bpc);

4795

4796

*pipe_bpp = display_bpc * 3;

4796

*pipe_bpp = display_bpc * 3;

4797

4798

return display_bpc != bpc;

4798

return display_bpc != bpc;

4799

}

4799

}

4800

4801

static int i9xx_crtc_mode_set(struct drm_crtc *crtc,

4801

static int i9xx_crtc_mode_set(struct drm_crtc *crtc,

4802

struct drm_display_mode *mode,

4802

struct drm_display_mode *mode,

4803

struct drm_display_mode *adjusted_mode,

4803

struct drm_display_mode *adjusted_mode,

4804

int x, int y,

4804

int x, int y,

4805

struct drm_framebuffer *old_fb)

4805

struct drm_framebuffer *old_fb)

4806

{

4806

{

4807

struct drm_device *dev = crtc->dev;

4807

struct drm_device *dev = crtc->dev;

4808

struct drm_i915_private *dev_priv = dev->dev_private;

4808

struct drm_i915_private *dev_priv = dev->dev_private;

4809

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

4809

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

4810

int pipe = intel_crtc->pipe;

4810

int pipe = intel_crtc->pipe;

4811

int plane = intel_crtc->plane;

4811

int plane = intel_crtc->plane;

4812

int refclk, num_connectors = 0;

4812

int refclk, num_connectors = 0;

4813

intel_clock_t clock, reduced_clock;

4813

intel_clock_t clock, reduced_clock;

4814

u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;

4814

u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;

4815

bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;

4815

bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;

4816

bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;

4816

bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;

4817

struct drm_mode_config *mode_config = &dev->mode_config;

4817

struct drm_mode_config *mode_config = &dev->mode_config;

4818

struct intel_encoder *encoder;

4818

struct intel_encoder *encoder;

4819

const intel_limit_t *limit;

4819

const intel_limit_t *limit;

4820

int ret;

4820

int ret;

4821

u32 temp;

4821

u32 temp;

4822

u32 lvds_sync = 0;

4822

u32 lvds_sync = 0;

4823

4824

list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {

4824

list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {

4825

if (encoder->base.crtc != crtc)

4825

if (encoder->base.crtc != crtc)

4826

continue;

4826

continue;

4827

4828

switch (encoder->type) {

4828

switch (encoder->type) {

4829

case INTEL_OUTPUT_LVDS:

4829

case INTEL_OUTPUT_LVDS:

4830

is_lvds = true;

4830

is_lvds = true;

4831

break;

4831

break;

4832

case INTEL_OUTPUT_SDVO:

4832

case INTEL_OUTPUT_SDVO:

4833

case INTEL_OUTPUT_HDMI:

4833

case INTEL_OUTPUT_HDMI:

4834

is_sdvo = true;

4834

is_sdvo = true;

4835

if (encoder->needs_tv_clock)

4835

if (encoder->needs_tv_clock)

4836

is_tv = true;

4836

is_tv = true;

4837

break;

4837

break;

4838

case INTEL_OUTPUT_DVO:

4838

case INTEL_OUTPUT_DVO:

4839

is_dvo = true;

4839

is_dvo = true;

4840

break;

4840

break;

4841

case INTEL_OUTPUT_TVOUT:

4841

case INTEL_OUTPUT_TVOUT:

4842

is_tv = true;

4842

is_tv = true;

4843

break;

4843

break;

4844

case INTEL_OUTPUT_ANALOG:

4844

case INTEL_OUTPUT_ANALOG:

4845

is_crt = true;

4845

is_crt = true;

4846

break;

4846

break;

4847

case INTEL_OUTPUT_DISPLAYPORT:

4847

case INTEL_OUTPUT_DISPLAYPORT:

4848

is_dp = true;

4848

is_dp = true;

4849

break;

4849

break;

4850

}

4850

}

4851

4852

num_connectors++;

4852

num_connectors++;

4853

}

4853

}

4854

4855

if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {

4855

if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {

4856

refclk = dev_priv->lvds_ssc_freq * 1000;

4856

refclk = dev_priv->lvds_ssc_freq * 1000;

4857

DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",

4857

DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",

4858

refclk / 1000);

4858

refclk / 1000);

4859

} else if (!IS_GEN2(dev)) {

4859

} else if (!IS_GEN2(dev)) {

4860

refclk = 96000;

4860

refclk = 96000;

4861

} else {

4861

} else {

4862

refclk = 48000;

4862

refclk = 48000;

4863

}

4863

}

4864

4865

/*

4865

/*

4866

* Returns a set of divisors for the desired target clock with the given

4866

* Returns a set of divisors for the desired target clock with the given

4867

* refclk, or FALSE. The returned values represent the clock equation:

4867

* refclk, or FALSE. The returned values represent the clock equation:

4868

* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.

4868

* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.

4869

*/

4869

*/

4870

limit = intel_limit(crtc, refclk);

4870

limit = intel_limit(crtc, refclk);

4871

ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);

4871

ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);

4872

if (!ok) {

4872

if (!ok) {

4873

DRM_ERROR("Couldn't find PLL settings for mode!\n");

4873

DRM_ERROR("Couldn't find PLL settings for mode!\n");

4874

return -EINVAL;

4874

return -EINVAL;

4875

}

4875

}

4876

4877

/* Ensure that the cursor is valid for the new mode before changing... */

4877

/* Ensure that the cursor is valid for the new mode before changing... */

4878

intel_crtc_update_cursor(crtc, true);

4878

intel_crtc_update_cursor(crtc, true);

4879

4880

if (is_lvds && dev_priv->lvds_downclock_avail) {

4880

if (is_lvds && dev_priv->lvds_downclock_avail) {

4881

has_reduced_clock = limit->find_pll(limit, crtc,

4881

has_reduced_clock = limit->find_pll(limit, crtc,

4882

dev_priv->lvds_downclock,

4882

dev_priv->lvds_downclock,

4883

refclk,

4883

refclk,

4884

&reduced_clock);

4884

&reduced_clock);

4885

if (has_reduced_clock && (clock.p != reduced_clock.p)) {

4885

if (has_reduced_clock && (clock.p != reduced_clock.p)) {

4886

/*

4886

/*

4887

* If the different P is found, it means that we can't

4887

* If the different P is found, it means that we can't

4888

* switch the display clock by using the FP0/FP1.

4888

* switch the display clock by using the FP0/FP1.

4889

* In such case we will disable the LVDS downclock

4889

* In such case we will disable the LVDS downclock

4890

* feature.

4890

* feature.

4891

*/

4891

*/

4892

DRM_DEBUG_KMS("Different P is found for "

4892

DRM_DEBUG_KMS("Different P is found for "

4893

"LVDS clock/downclock\n");

4893

"LVDS clock/downclock\n");

4894

has_reduced_clock = 0;

4894

has_reduced_clock = 0;

4895

}

4895

}

4896

}

4896

}

4897

/* SDVO TV has fixed PLL values depend on its clock range,

4897

/* SDVO TV has fixed PLL values depend on its clock range,

4898

this mirrors vbios setting. */

4898

this mirrors vbios setting. */

4899

if (is_sdvo && is_tv) {

4899

if (is_sdvo && is_tv) {

4900

if (adjusted_mode->clock >= 100000

4900

if (adjusted_mode->clock >= 100000

4901

&& adjusted_mode->clock < 140500) {

4901

&& adjusted_mode->clock < 140500) {

4902

clock.p1 = 2;

4902

clock.p1 = 2;

4903

clock.p2 = 10;

4903

clock.p2 = 10;

4904

clock.n = 3;

4904

clock.n = 3;

4905

clock.m1 = 16;

4905

clock.m1 = 16;

4906

clock.m2 = 8;

4906

clock.m2 = 8;

4907

} else if (adjusted_mode->clock >= 140500

4907

} else if (adjusted_mode->clock >= 140500

4908

&& adjusted_mode->clock <= 200000) {

4908

&& adjusted_mode->clock <= 200000) {

4909

clock.p1 = 1;

4909

clock.p1 = 1;

4910

clock.p2 = 10;

4910

clock.p2 = 10;

4911

clock.n = 6;

4911

clock.n = 6;

4912

clock.m1 = 12;

4912

clock.m1 = 12;

4913

clock.m2 = 8;

4913

clock.m2 = 8;

4914

}

4914

}

4915

}

4915

}

4916

4917

if (IS_PINEVIEW(dev)) {

4917

if (IS_PINEVIEW(dev)) {

4918

fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;

4918

fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;

4919

if (has_reduced_clock)

4919

if (has_reduced_clock)

4920

fp2 = (1 << reduced_clock.n) << 16 |

4920

fp2 = (1 << reduced_clock.n) << 16 |

4921

reduced_clock.m1 << 8 | reduced_clock.m2;

4921

reduced_clock.m1 << 8 | reduced_clock.m2;

4922

} else {

4922

} else {

4923

fp = clock.n << 16 | clock.m1 << 8 | clock.m2;

4923

fp = clock.n << 16 | clock.m1 << 8 | clock.m2;

4924

if (has_reduced_clock)

4924

if (has_reduced_clock)

4925

fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |

4925

fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |

4926

reduced_clock.m2;

4926

reduced_clock.m2;

4927

}

4927

}

4928

4929

dpll = DPLL_VGA_MODE_DIS;

4929

dpll = DPLL_VGA_MODE_DIS;

4930

4931

if (!IS_GEN2(dev)) {

4931

if (!IS_GEN2(dev)) {

4932

if (is_lvds)

4932

if (is_lvds)

4933

dpll |= DPLLB_MODE_LVDS;

4933

dpll |= DPLLB_MODE_LVDS;

4934

else

4934

else

4935

dpll |= DPLLB_MODE_DAC_SERIAL;

4935

dpll |= DPLLB_MODE_DAC_SERIAL;

4936

if (is_sdvo) {

4936

if (is_sdvo) {

4937

int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);

4937

int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);

4938

if (pixel_multiplier > 1) {

4938

if (pixel_multiplier > 1) {

4939

if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))

4939

if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))

4940

dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;

4940

dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;

4941

}

4941

}

4942

dpll |= DPLL_DVO_HIGH_SPEED;

4942

dpll |= DPLL_DVO_HIGH_SPEED;

4943

}

4943

}

4944

if (is_dp)

4944

if (is_dp)

4945

dpll |= DPLL_DVO_HIGH_SPEED;

4945

dpll |= DPLL_DVO_HIGH_SPEED;

4946

4947

/* compute bitmask from p1 value */

4947

/* compute bitmask from p1 value */

4948

if (IS_PINEVIEW(dev))

4948

if (IS_PINEVIEW(dev))

4949

dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;

4949

dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;

4950

else {

4950

else {

4951

dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;

4951

dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;

4952

if (IS_G4X(dev) && has_reduced_clock)

4952

if (IS_G4X(dev) && has_reduced_clock)

4953

dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;

4953

dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;

4954

}

4954

}

4955

switch (clock.p2) {

4955

switch (clock.p2) {

4956

case 5:

4956

case 5:

4957

dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;

4957

dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;

4958

break;

4958

break;

4959

case 7:

4959

case 7:

4960

dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;

4960

dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;

4961

break;

4961

break;

4962

case 10:

4962

case 10:

4963

dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;

4963

dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;

4964

break;

4964

break;

4965

case 14:

4965

case 14:

4966

dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;

4966

dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;

4967

break;

4967

break;

4968

}

4968

}

4969

if (INTEL_INFO(dev)->gen >= 4)

4969

if (INTEL_INFO(dev)->gen >= 4)

4970

dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);

4970

dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);

4971

} else {

4971

} else {

4972

if (is_lvds) {

4972

if (is_lvds) {

4973

dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;

4973

dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;

4974

} else {

4974

} else {

4975

if (clock.p1 == 2)

4975

if (clock.p1 == 2)

4976

dpll |= PLL_P1_DIVIDE_BY_TWO;

4976

dpll |= PLL_P1_DIVIDE_BY_TWO;

4977

else

4977

else

4978

dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;

4978

dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;

4979

if (clock.p2 == 4)

4979

if (clock.p2 == 4)

4980

dpll |= PLL_P2_DIVIDE_BY_4;

4980

dpll |= PLL_P2_DIVIDE_BY_4;

4981

}

4981

}

4982

}

4982

}

4983

4984

if (is_sdvo && is_tv)

4984

if (is_sdvo && is_tv)

4985

dpll |= PLL_REF_INPUT_TVCLKINBC;

4985

dpll |= PLL_REF_INPUT_TVCLKINBC;

4986

else if (is_tv)

4986

else if (is_tv)

4987

/* XXX: just matching BIOS for now */

4987

/* XXX: just matching BIOS for now */

4988

/* dpll |= PLL_REF_INPUT_TVCLKINBC; */

4988

/* dpll |= PLL_REF_INPUT_TVCLKINBC; */

4989

dpll |= 3;

4989

dpll |= 3;

4990

else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)

4990

else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)

4991

dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;

4991

dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;

4992

else

4992

else

4993

dpll |= PLL_REF_INPUT_DREFCLK;

4993

dpll |= PLL_REF_INPUT_DREFCLK;

4994

4995

/* setup pipeconf */

4995

/* setup pipeconf */

4996

pipeconf = I915_READ(PIPECONF(pipe));

4996

pipeconf = I915_READ(PIPECONF(pipe));

4997

4998

/* Set up the display plane register */

4998

/* Set up the display plane register */

4999

dspcntr = DISPPLANE_GAMMA_ENABLE;

4999

dspcntr = DISPPLANE_GAMMA_ENABLE;

5000

5001

/* Ironlake's plane is forced to pipe, bit 24 is to

5001

/* Ironlake's plane is forced to pipe, bit 24 is to

5002

enable color space conversion */

5002

enable color space conversion */

5003

if (pipe == 0)

5003

if (pipe == 0)

5004

dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;

5004

dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;

5005

else

5005

else

5006

dspcntr |= DISPPLANE_SEL_PIPE_B;

5006

dspcntr |= DISPPLANE_SEL_PIPE_B;

5007

5008

if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {

5008

if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {

5009

/* Enable pixel doubling when the dot clock is > 90% of the (display)

5009

/* Enable pixel doubling when the dot clock is > 90% of the (display)

5010

* core speed.

5010

* core speed.

5011

*

5011

*

5012

* XXX: No double-wide on 915GM pipe B. Is that the only reason for the

5012

* XXX: No double-wide on 915GM pipe B. Is that the only reason for the

5013

* pipe == 0 check?

5013

* pipe == 0 check?

5014

*/

5014

*/

5015

if (mode->clock >

5015

if (mode->clock >

5016

dev_priv->display.get_display_clock_speed(dev) * 9 / 10)

5016

dev_priv->display.get_display_clock_speed(dev) * 9 / 10)

5017

pipeconf |= PIPECONF_DOUBLE_WIDE;

5017

pipeconf |= PIPECONF_DOUBLE_WIDE;

5018

else

5018

else

5019

pipeconf &= ~PIPECONF_DOUBLE_WIDE;

5019

pipeconf &= ~PIPECONF_DOUBLE_WIDE;

5020

}

5020

}

5021

5022

dpll |= DPLL_VCO_ENABLE;

5022

dpll |= DPLL_VCO_ENABLE;

5023

5024

DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');

5024

DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');

5025

drm_mode_debug_printmodeline(mode);

5025

drm_mode_debug_printmodeline(mode);

5026

5027

I915_WRITE(FP0(pipe), fp);

5027

I915_WRITE(FP0(pipe), fp);

5028

I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);

5028

I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);

5029

5030

POSTING_READ(DPLL(pipe));

5030

POSTING_READ(DPLL(pipe));

5031

udelay(150);

5031

udelay(150);

5032

5033

/* The LVDS pin pair needs to be on before the DPLLs are enabled.

5033

/* The LVDS pin pair needs to be on before the DPLLs are enabled.

5034

* This is an exception to the general rule that mode_set doesn't turn

5034

* This is an exception to the general rule that mode_set doesn't turn

5035

* things on.

5035

* things on.

5036

*/

5036

*/

5037

if (is_lvds) {

5037

if (is_lvds) {

5038

temp = I915_READ(LVDS);

5038

temp = I915_READ(LVDS);

5039

temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;

5039

temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;

5040

if (pipe == 1) {

5040

if (pipe == 1) {

5041

temp |= LVDS_PIPEB_SELECT;

5041

temp |= LVDS_PIPEB_SELECT;

5042

} else {

5042

} else {

5043

temp &= ~LVDS_PIPEB_SELECT;

5043

temp &= ~LVDS_PIPEB_SELECT;

5044

}

5044

}

5045

/* set the corresponsding LVDS_BORDER bit */

5045

/* set the corresponsding LVDS_BORDER bit */

5046

temp |= dev_priv->lvds_border_bits;

5046

temp |= dev_priv->lvds_border_bits;

5047

/* Set the B0-B3 data pairs corresponding to whether we're going to

5047

/* Set the B0-B3 data pairs corresponding to whether we're going to

5048

* set the DPLLs for dual-channel mode or not.

5048

* set the DPLLs for dual-channel mode or not.

5049

*/

5049

*/

5050

if (clock.p2 == 7)

5050

if (clock.p2 == 7)

5051

temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;

5051

temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;

5052

else

5052

else

5053

temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);

5053

temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);

5054

5055

/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)

5055

/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)

5056

* appropriately here, but we need to look more thoroughly into how

5056

* appropriately here, but we need to look more thoroughly into how

5057

* panels behave in the two modes.

5057

* panels behave in the two modes.

5058

*/

5058

*/

5059

/* set the dithering flag on LVDS as needed */

5059

/* set the dithering flag on LVDS as needed */

5060

if (INTEL_INFO(dev)->gen >= 4) {

5060

if (INTEL_INFO(dev)->gen >= 4) {

5061

if (dev_priv->lvds_dither)

5061

if (dev_priv->lvds_dither)

5062

temp |= LVDS_ENABLE_DITHER;

5062

temp |= LVDS_ENABLE_DITHER;

5063

else

5063

else

5064

temp &= ~LVDS_ENABLE_DITHER;

5064

temp &= ~LVDS_ENABLE_DITHER;

5065

}

5065

}

5066

if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)

5066

if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)

5067

lvds_sync |= LVDS_HSYNC_POLARITY;

5067

lvds_sync |= LVDS_HSYNC_POLARITY;

5068

if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)

5068

if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)

5069

lvds_sync |= LVDS_VSYNC_POLARITY;

5069

lvds_sync |= LVDS_VSYNC_POLARITY;

5070

if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))

5070

if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))

5071

!= lvds_sync) {

5071

!= lvds_sync) {

5072

char flags[2] = "-+";

5072

char flags[2] = "-+";

5073

DRM_INFO("Changing LVDS panel from "

5073

DRM_INFO("Changing LVDS panel from "

5074

"(%chsync, %cvsync) to (%chsync, %cvsync)\n",

5074

"(%chsync, %cvsync) to (%chsync, %cvsync)\n",

5075

flags[!(temp & LVDS_HSYNC_POLARITY)],

5075

flags[!(temp & LVDS_HSYNC_POLARITY)],

5076

flags[!(temp & LVDS_VSYNC_POLARITY)],

5076

flags[!(temp & LVDS_VSYNC_POLARITY)],

5077

flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],

5077

flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],

5078

flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);

5078

flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);

5079

temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);

5079

temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);

5080

temp |= lvds_sync;

5080

temp |= lvds_sync;

5081

}

5081

}

5082

I915_WRITE(LVDS, temp);

5082

I915_WRITE(LVDS, temp);

5083

}

5083

}

5084

5085

if (is_dp) {

5085

if (is_dp) {

5086

intel_dp_set_m_n(crtc, mode, adjusted_mode);

5086

intel_dp_set_m_n(crtc, mode, adjusted_mode);

5087

}

5087

}

5088

5089

I915_WRITE(DPLL(pipe), dpll);

5089

I915_WRITE(DPLL(pipe), dpll);

5090

5091

/* Wait for the clocks to stabilize. */

5091

/* Wait for the clocks to stabilize. */

5092

POSTING_READ(DPLL(pipe));

5092

POSTING_READ(DPLL(pipe));

5093

udelay(150);

5093

udelay(150);

5094

5095

if (INTEL_INFO(dev)->gen >= 4) {

5095

if (INTEL_INFO(dev)->gen >= 4) {

5096

temp = 0;

5096

temp = 0;

5097

if (is_sdvo) {

5097

if (is_sdvo) {

5098

temp = intel_mode_get_pixel_multiplier(adjusted_mode);

5098

temp = intel_mode_get_pixel_multiplier(adjusted_mode);

5099

if (temp > 1)

5099

if (temp > 1)

5100

temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;

5100

temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;

5101

else

5101

else

5102

temp = 0;

5102

temp = 0;

5103

}

5103

}

5104

I915_WRITE(DPLL_MD(pipe), temp);

5104

I915_WRITE(DPLL_MD(pipe), temp);

5105

} else {

5105

} else {

5106

/* The pixel multiplier can only be updated once the

5106

/* The pixel multiplier can only be updated once the

5107

* DPLL is enabled and the clocks are stable.

5107

* DPLL is enabled and the clocks are stable.

5108

*

5108

*

5109

* So write it again.

5109

* So write it again.

5110

*/

5110

*/

5111

I915_WRITE(DPLL(pipe), dpll);

5111

I915_WRITE(DPLL(pipe), dpll);

5112

}

5112

}

5113

5114

intel_crtc->lowfreq_avail = false;

5114

intel_crtc->lowfreq_avail = false;

5115

if (is_lvds && has_reduced_clock && i915_powersave) {

5115

if (is_lvds && has_reduced_clock && i915_powersave) {

5116

I915_WRITE(FP1(pipe), fp2);

5116

I915_WRITE(FP1(pipe), fp2);

5117

intel_crtc->lowfreq_avail = true;

5117

intel_crtc->lowfreq_avail = true;

5118

if (HAS_PIPE_CXSR(dev)) {

5118

if (HAS_PIPE_CXSR(dev)) {

5119

DRM_DEBUG_KMS("enabling CxSR downclocking\n");

5119

DRM_DEBUG_KMS("enabling CxSR downclocking\n");

5120

pipeconf |= PIPECONF_CXSR_DOWNCLOCK;

5120

pipeconf |= PIPECONF_CXSR_DOWNCLOCK;

5121

}

5121

}

5122

} else {

5122

} else {

5123

I915_WRITE(FP1(pipe), fp);

5123

I915_WRITE(FP1(pipe), fp);

5124

if (HAS_PIPE_CXSR(dev)) {

5124

if (HAS_PIPE_CXSR(dev)) {

5125

DRM_DEBUG_KMS("disabling CxSR downclocking\n");

5125

DRM_DEBUG_KMS("disabling CxSR downclocking\n");

5126

pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;

5126

pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;

5127

}

5127

}

5128

}

5128

}

5129

5130

if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {

5130

if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {

5131

pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;

5131

pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;

5132

/* the chip adds 2 halflines automatically */

5132

/* the chip adds 2 halflines automatically */

5133

adjusted_mode->crtc_vdisplay -= 1;

5133

adjusted_mode->crtc_vdisplay -= 1;

5134

adjusted_mode->crtc_vtotal -= 1;

5134

adjusted_mode->crtc_vtotal -= 1;

5135

adjusted_mode->crtc_vblank_start -= 1;

5135

adjusted_mode->crtc_vblank_start -= 1;

5136

adjusted_mode->crtc_vblank_end -= 1;

5136

adjusted_mode->crtc_vblank_end -= 1;

5137

adjusted_mode->crtc_vsync_end -= 1;

5137

adjusted_mode->crtc_vsync_end -= 1;

5138

adjusted_mode->crtc_vsync_start -= 1;

5138

adjusted_mode->crtc_vsync_start -= 1;

5139

} else

5139

} else

5140

pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */

5140

pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */

5141

5142

I915_WRITE(HTOTAL(pipe),

5142

I915_WRITE(HTOTAL(pipe),

5143

(adjusted_mode->crtc_hdisplay - 1) |

5143

(adjusted_mode->crtc_hdisplay - 1) |

5144

((adjusted_mode->crtc_htotal - 1) << 16));

5144

((adjusted_mode->crtc_htotal - 1) << 16));

5145

I915_WRITE(HBLANK(pipe),

5145

I915_WRITE(HBLANK(pipe),

5146

(adjusted_mode->crtc_hblank_start - 1) |

5146

(adjusted_mode->crtc_hblank_start - 1) |

5147

((adjusted_mode->crtc_hblank_end - 1) << 16));

5147

((adjusted_mode->crtc_hblank_end - 1) << 16));

5148

I915_WRITE(HSYNC(pipe),

5148

I915_WRITE(HSYNC(pipe),

5149

(adjusted_mode->crtc_hsync_start - 1) |

5149

(adjusted_mode->crtc_hsync_start - 1) |

5150

((adjusted_mode->crtc_hsync_end - 1) << 16));

5150

((adjusted_mode->crtc_hsync_end - 1) << 16));

5151

5152

I915_WRITE(VTOTAL(pipe),

5152

I915_WRITE(VTOTAL(pipe),

5153

(adjusted_mode->crtc_vdisplay - 1) |

5153

(adjusted_mode->crtc_vdisplay - 1) |

5154

((adjusted_mode->crtc_vtotal - 1) << 16));

5154

((adjusted_mode->crtc_vtotal - 1) << 16));

5155

I915_WRITE(VBLANK(pipe),

5155

I915_WRITE(VBLANK(pipe),

5156

(adjusted_mode->crtc_vblank_start - 1) |

5156

(adjusted_mode->crtc_vblank_start - 1) |

5157

((adjusted_mode->crtc_vblank_end - 1) << 16));

5157

((adjusted_mode->crtc_vblank_end - 1) << 16));

5158

I915_WRITE(VSYNC(pipe),

5158

I915_WRITE(VSYNC(pipe),

5159

(adjusted_mode->crtc_vsync_start - 1) |

5159

(adjusted_mode->crtc_vsync_start - 1) |

5160

((adjusted_mode->crtc_vsync_end - 1) << 16));

5160

((adjusted_mode->crtc_vsync_end - 1) << 16));

5161

5162

/* pipesrc and dspsize control the size that is scaled from,

5162

/* pipesrc and dspsize control the size that is scaled from,

5163

* which should always be the user's requested size.

5163

* which should always be the user's requested size.

5164

*/

5164

*/

5165

I915_WRITE(DSPSIZE(plane),

5165

I915_WRITE(DSPSIZE(plane),

5166

((mode->vdisplay - 1) << 16) |

5166

((mode->vdisplay - 1) << 16) |

5167

(mode->hdisplay - 1));

5167

(mode->hdisplay - 1));

5168

I915_WRITE(DSPPOS(plane), 0);

5168

I915_WRITE(DSPPOS(plane), 0);

5169

I915_WRITE(PIPESRC(pipe),

5169

I915_WRITE(PIPESRC(pipe),

5170

((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));

5170

((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));

5171

5172

I915_WRITE(PIPECONF(pipe), pipeconf);

5172

I915_WRITE(PIPECONF(pipe), pipeconf);

5173

POSTING_READ(PIPECONF(pipe));

5173

POSTING_READ(PIPECONF(pipe));

5174

intel_enable_pipe(dev_priv, pipe, false);

5174

intel_enable_pipe(dev_priv, pipe, false);

5175

5176

intel_wait_for_vblank(dev, pipe);

5176

intel_wait_for_vblank(dev, pipe);

5177

5178

I915_WRITE(DSPCNTR(plane), dspcntr);

5178

I915_WRITE(DSPCNTR(plane), dspcntr);

5179

POSTING_READ(DSPCNTR(plane));

5179

POSTING_READ(DSPCNTR(plane));

5180

intel_enable_plane(dev_priv, plane, pipe);

5180

intel_enable_plane(dev_priv, plane, pipe);

5181

5182

ret = intel_pipe_set_base(crtc, x, y, old_fb);

5182

ret = intel_pipe_set_base(crtc, x, y, old_fb);

5183

5184

intel_update_watermarks(dev);

5184

intel_update_watermarks(dev);

5185

5186

return ret;

5186

return ret;

5187

}

5187

}

5188

5189

/*

5189

/*

5190

* Initialize reference clocks when the driver loads

5190

* Initialize reference clocks when the driver loads

5191

*/

5191

*/

5192

void ironlake_init_pch_refclk(struct drm_device *dev)

5192

void ironlake_init_pch_refclk(struct drm_device *dev)

5193

{

5193

{

5194

struct drm_i915_private *dev_priv = dev->dev_private;

5194

struct drm_i915_private *dev_priv = dev->dev_private;

5195

struct drm_mode_config *mode_config = &dev->mode_config;

5195

struct drm_mode_config *mode_config = &dev->mode_config;

5196

struct intel_encoder *encoder;

5196

struct intel_encoder *encoder;

5197

u32 temp;

5197

u32 temp;

5198

bool has_lvds = false;

5198

bool has_lvds = false;

5199

bool has_cpu_edp = false;

5199

bool has_cpu_edp = false;

5200

bool has_pch_edp = false;

5200

bool has_pch_edp = false;

5201

bool has_panel = false;

5201

bool has_panel = false;

5202

bool has_ck505 = false;

5202

bool has_ck505 = false;

5203

bool can_ssc = false;

5203

bool can_ssc = false;

5204

5205

/* We need to take the global config into account */

5205

/* We need to take the global config into account */

5206

list_for_each_entry(encoder, &mode_config->encoder_list,

5206

list_for_each_entry(encoder, &mode_config->encoder_list,

5207

base.head) {

5207

base.head) {

5208

switch (encoder->type) {

5208

switch (encoder->type) {

5209

case INTEL_OUTPUT_LVDS:

5209

case INTEL_OUTPUT_LVDS:

5210

has_panel = true;

5210

has_panel = true;

5211

has_lvds = true;

5211

has_lvds = true;

5212

break;

5212

break;

5213

case INTEL_OUTPUT_EDP:

5213

case INTEL_OUTPUT_EDP:

5214

has_panel = true;

5214

has_panel = true;

5215

if (intel_encoder_is_pch_edp(&encoder->base))

5215

if (intel_encoder_is_pch_edp(&encoder->base))

5216

has_pch_edp = true;

5216

has_pch_edp = true;

5217

else

5217

else

5218

has_cpu_edp = true;

5218

has_cpu_edp = true;

5219

break;

5219

break;

5220

}

5220

}

5221

}

5221

}

5222

5223

if (HAS_PCH_IBX(dev)) {

5223

if (HAS_PCH_IBX(dev)) {

5224

has_ck505 = dev_priv->display_clock_mode;

5224

has_ck505 = dev_priv->display_clock_mode;

5225

can_ssc = has_ck505;

5225

can_ssc = has_ck505;

5226

} else {

5226

} else {

5227

has_ck505 = false;

5227

has_ck505 = false;

5228

can_ssc = true;

5228

can_ssc = true;

5229

}

5229

}

5230

5231

DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",

5231

DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",

5232

has_panel, has_lvds, has_pch_edp, has_cpu_edp,

5232

has_panel, has_lvds, has_pch_edp, has_cpu_edp,

5233

has_ck505);

5233

has_ck505);

5234

5235

/* Ironlake: try to setup display ref clock before DPLL

5235

/* Ironlake: try to setup display ref clock before DPLL

5236

* enabling. This is only under driver's control after

5236

* enabling. This is only under driver's control after

5237

* PCH B stepping, previous chipset stepping should be

5237

* PCH B stepping, previous chipset stepping should be

5238

* ignoring this setting.

5238

* ignoring this setting.

5239

*/

5239

*/

5240

temp = I915_READ(PCH_DREF_CONTROL);

5240

temp = I915_READ(PCH_DREF_CONTROL);

5241

/* Always enable nonspread source */

5241

/* Always enable nonspread source */

5242

temp &= ~DREF_NONSPREAD_SOURCE_MASK;

5242

temp &= ~DREF_NONSPREAD_SOURCE_MASK;

5243

5244

if (has_ck505)

5244

if (has_ck505)

5245

temp |= DREF_NONSPREAD_CK505_ENABLE;

5245

temp |= DREF_NONSPREAD_CK505_ENABLE;

5246

else

5246

else

5247

temp |= DREF_NONSPREAD_SOURCE_ENABLE;

5247

temp |= DREF_NONSPREAD_SOURCE_ENABLE;

5248

5249

if (has_panel) {

5249

if (has_panel) {

5250

temp &= ~DREF_SSC_SOURCE_MASK;

5250

temp &= ~DREF_SSC_SOURCE_MASK;

5251

temp |= DREF_SSC_SOURCE_ENABLE;

5251

temp |= DREF_SSC_SOURCE_ENABLE;

5252

5253

/* SSC must be turned on before enabling the CPU output */

5253

/* SSC must be turned on before enabling the CPU output */

5254

if (intel_panel_use_ssc(dev_priv) && can_ssc) {

5254

if (intel_panel_use_ssc(dev_priv) && can_ssc) {

5255

DRM_DEBUG_KMS("Using SSC on panel\n");

5255

DRM_DEBUG_KMS("Using SSC on panel\n");

5256

temp |= DREF_SSC1_ENABLE;

5256

temp |= DREF_SSC1_ENABLE;

5257

}

5257

}

5258

5259

/* Get SSC going before enabling the outputs */

5259

/* Get SSC going before enabling the outputs */

5260

I915_WRITE(PCH_DREF_CONTROL, temp);

5260

I915_WRITE(PCH_DREF_CONTROL, temp);

5261

POSTING_READ(PCH_DREF_CONTROL);

5261

POSTING_READ(PCH_DREF_CONTROL);

5262

udelay(200);

5262

udelay(200);

5263

5264

temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;

5264

temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;

5265

5266

/* Enable CPU source on CPU attached eDP */

5266

/* Enable CPU source on CPU attached eDP */

5267

if (has_cpu_edp) {

5267

if (has_cpu_edp) {

5268

if (intel_panel_use_ssc(dev_priv) && can_ssc) {

5268

if (intel_panel_use_ssc(dev_priv) && can_ssc) {

5269

DRM_DEBUG_KMS("Using SSC on eDP\n");

5269

DRM_DEBUG_KMS("Using SSC on eDP\n");

5270

temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;

5270

temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;

5271

}

5271

}

5272

else

5272

else

5273

temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;

5273

temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;

5274

} else

5274

} else

5275

temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;

5275

temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;

5276

5277

I915_WRITE(PCH_DREF_CONTROL, temp);

5277

I915_WRITE(PCH_DREF_CONTROL, temp);

5278

POSTING_READ(PCH_DREF_CONTROL);

5278

POSTING_READ(PCH_DREF_CONTROL);

5279

udelay(200);

5279

udelay(200);

5280

} else {

5280

} else {

5281

DRM_DEBUG_KMS("Disabling SSC entirely\n");

5281

DRM_DEBUG_KMS("Disabling SSC entirely\n");

5282

5283

temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;

5283

temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;

5284

5285

/* Turn off CPU output */

5285

/* Turn off CPU output */

5286

temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;

5286

temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;

5287

5288

I915_WRITE(PCH_DREF_CONTROL, temp);

5288

I915_WRITE(PCH_DREF_CONTROL, temp);

5289

POSTING_READ(PCH_DREF_CONTROL);

5289

POSTING_READ(PCH_DREF_CONTROL);

5290

udelay(200);

5290

udelay(200);

5291

5292

/* Turn off the SSC source */

5292

/* Turn off the SSC source */

5293

temp &= ~DREF_SSC_SOURCE_MASK;

5293

temp &= ~DREF_SSC_SOURCE_MASK;

5294

temp |= DREF_SSC_SOURCE_DISABLE;

5294

temp |= DREF_SSC_SOURCE_DISABLE;

5295

5296

/* Turn off SSC1 */

5296

/* Turn off SSC1 */

5297

temp &= ~ DREF_SSC1_ENABLE;

5297

temp &= ~ DREF_SSC1_ENABLE;

5298

5299

I915_WRITE(PCH_DREF_CONTROL, temp);

5299

I915_WRITE(PCH_DREF_CONTROL, temp);

5300

POSTING_READ(PCH_DREF_CONTROL);

5300

POSTING_READ(PCH_DREF_CONTROL);

5301

udelay(200);

5301

udelay(200);

5302

}

5302

}

5303

}

5303

}

5304

5305

static int ironlake_get_refclk(struct drm_crtc *crtc)

5305

static int ironlake_get_refclk(struct drm_crtc *crtc)

5306

{

5306

{

5307

struct drm_device *dev = crtc->dev;

5307

struct drm_device *dev = crtc->dev;

5308

struct drm_i915_private *dev_priv = dev->dev_private;

5308

struct drm_i915_private *dev_priv = dev->dev_private;

5309

struct intel_encoder *encoder;

5309

struct intel_encoder *encoder;

5310

struct drm_mode_config *mode_config = &dev->mode_config;

5310

struct drm_mode_config *mode_config = &dev->mode_config;

5311

struct intel_encoder *edp_encoder = NULL;

5311

struct intel_encoder *edp_encoder = NULL;

5312

int num_connectors = 0;

5312

int num_connectors = 0;

5313

bool is_lvds = false;

5313

bool is_lvds = false;

5314

5315

list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {

5315

list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {

5316

if (encoder->base.crtc != crtc)

5316

if (encoder->base.crtc != crtc)

5317

continue;

5317

continue;

5318

5319

switch (encoder->type) {

5319

switch (encoder->type) {

5320

case INTEL_OUTPUT_LVDS:

5320

case INTEL_OUTPUT_LVDS:

5321

is_lvds = true;

5321

is_lvds = true;

5322

break;

5322

break;

5323

case INTEL_OUTPUT_EDP:

5323

case INTEL_OUTPUT_EDP:

5324

edp_encoder = encoder;

5324

edp_encoder = encoder;

5325

break;

5325

break;

5326

}

5326

}

5327

num_connectors++;

5327

num_connectors++;

5328

}

5328

}

5329

5330

if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {

5330

if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {

5331

DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",

5331

DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",

5332

dev_priv->lvds_ssc_freq);

5332

dev_priv->lvds_ssc_freq);

5333

return dev_priv->lvds_ssc_freq * 1000;

5333

return dev_priv->lvds_ssc_freq * 1000;

5334

}

5334

}

5335

5336

return 120000;

5336

return 120000;

5337

}

5337

}

5338

5339

static int ironlake_crtc_mode_set(struct drm_crtc *crtc,

5339

static int ironlake_crtc_mode_set(struct drm_crtc *crtc,

5340

struct drm_display_mode *mode,

5340

struct drm_display_mode *mode,

5341

struct drm_display_mode *adjusted_mode,

5341

struct drm_display_mode *adjusted_mode,

5342

int x, int y,

5342

int x, int y,

5343

struct drm_framebuffer *old_fb)

5343

struct drm_framebuffer *old_fb)

5344

{

5344

{

5345

struct drm_device *dev = crtc->dev;

5345

struct drm_device *dev = crtc->dev;

5346

struct drm_i915_private *dev_priv = dev->dev_private;

5346

struct drm_i915_private *dev_priv = dev->dev_private;

5347

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

5347

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

5348

int pipe = intel_crtc->pipe;

5348

int pipe = intel_crtc->pipe;

5349

int plane = intel_crtc->plane;

5349

int plane = intel_crtc->plane;

5350

int refclk, num_connectors = 0;

5350

int refclk, num_connectors = 0;

5351

intel_clock_t clock, reduced_clock;

5351

intel_clock_t clock, reduced_clock;

5352

u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;

5352

u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;

5353

bool ok, has_reduced_clock = false, is_sdvo = false;

5353

bool ok, has_reduced_clock = false, is_sdvo = false;

5354

bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;

5354

bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;

5355

struct intel_encoder *has_edp_encoder = NULL;

5355

struct intel_encoder *has_edp_encoder = NULL;

5356

struct drm_mode_config *mode_config = &dev->mode_config;

5356

struct drm_mode_config *mode_config = &dev->mode_config;

5357

struct intel_encoder *encoder;

5357

struct intel_encoder *encoder;

5358

const intel_limit_t *limit;

5358

const intel_limit_t *limit;

5359

int ret;

5359

int ret;

5360

struct fdi_m_n m_n = {0};

5360

struct fdi_m_n m_n = {0};

5361

u32 temp;

5361

u32 temp;

5362

u32 lvds_sync = 0;

5362

u32 lvds_sync = 0;

5363

int target_clock, pixel_multiplier, lane, link_bw, factor;

5363

int target_clock, pixel_multiplier, lane, link_bw, factor;

5364

unsigned int pipe_bpp;

5364

unsigned int pipe_bpp;

5365

bool dither;

5365

bool dither;

5366

5367

list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {

5367

list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {

5368

if (encoder->base.crtc != crtc)

5368

if (encoder->base.crtc != crtc)

5369

continue;

5369

continue;

5370

5371

switch (encoder->type) {

5371

switch (encoder->type) {

5372

case INTEL_OUTPUT_LVDS:

5372

case INTEL_OUTPUT_LVDS:

5373

is_lvds = true;

5373

is_lvds = true;

5374

break;

5374

break;

5375

case INTEL_OUTPUT_SDVO:

5375

case INTEL_OUTPUT_SDVO:

5376

case INTEL_OUTPUT_HDMI:

5376

case INTEL_OUTPUT_HDMI:

5377

is_sdvo = true;

5377

is_sdvo = true;

5378

if (encoder->needs_tv_clock)

5378

if (encoder->needs_tv_clock)

5379

is_tv = true;

5379

is_tv = true;

5380

break;

5380

break;

5381

case INTEL_OUTPUT_TVOUT:

5381

case INTEL_OUTPUT_TVOUT:

5382

is_tv = true;

5382

is_tv = true;

5383

break;

5383

break;

5384

case INTEL_OUTPUT_ANALOG:

5384

case INTEL_OUTPUT_ANALOG:

5385

is_crt = true;

5385

is_crt = true;

5386

break;

5386

break;

5387

case INTEL_OUTPUT_DISPLAYPORT:

5387

case INTEL_OUTPUT_DISPLAYPORT:

5388

is_dp = true;

5388

is_dp = true;

5389

break;

5389

break;

5390

case INTEL_OUTPUT_EDP:

5390

case INTEL_OUTPUT_EDP:

5391

has_edp_encoder = encoder;

5391

has_edp_encoder = encoder;

5392

break;

5392

break;

5393

}

5393

}

5394

5395

num_connectors++;

5395

num_connectors++;

5396

}

5396

}

5397

5398

refclk = ironlake_get_refclk(crtc);

5398

refclk = ironlake_get_refclk(crtc);

5399

5400

/*

5400

/*

5401

* Returns a set of divisors for the desired target clock with the given

5401

* Returns a set of divisors for the desired target clock with the given

5402

* refclk, or FALSE. The returned values represent the clock equation:

5402

* refclk, or FALSE. The returned values represent the clock equation:

5403

* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.

5403

* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.

5404

*/

5404

*/

5405

limit = intel_limit(crtc, refclk);

5405

limit = intel_limit(crtc, refclk);

5406

ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);

5406

ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);

5407

if (!ok) {

5407

if (!ok) {

5408

DRM_ERROR("Couldn't find PLL settings for mode!\n");

5408

DRM_ERROR("Couldn't find PLL settings for mode!\n");

5409

return -EINVAL;

5409

return -EINVAL;

5410

}

5410

}

5411

5412

/* Ensure that the cursor is valid for the new mode before changing... */

5412

/* Ensure that the cursor is valid for the new mode before changing... */

5413

intel_crtc_update_cursor(crtc, true);

5413

intel_crtc_update_cursor(crtc, true);

5414

5415

if (is_lvds && dev_priv->lvds_downclock_avail) {

5415

if (is_lvds && dev_priv->lvds_downclock_avail) {

5416

has_reduced_clock = limit->find_pll(limit, crtc,

5416

has_reduced_clock = limit->find_pll(limit, crtc,

5417

dev_priv->lvds_downclock,

5417

dev_priv->lvds_downclock,

5418

refclk,

5418

refclk,

5419

&reduced_clock);

5419

&reduced_clock);

5420

if (has_reduced_clock && (clock.p != reduced_clock.p)) {

5420

if (has_reduced_clock && (clock.p != reduced_clock.p)) {

5421

/*

5421

/*

5422

* If the different P is found, it means that we can't

5422

* If the different P is found, it means that we can't

5423

* switch the display clock by using the FP0/FP1.

5423

* switch the display clock by using the FP0/FP1.

5424

* In such case we will disable the LVDS downclock

5424

* In such case we will disable the LVDS downclock

5425

* feature.

5425

* feature.

5426

*/

5426

*/

5427

DRM_DEBUG_KMS("Different P is found for "

5427

DRM_DEBUG_KMS("Different P is found for "

5428

"LVDS clock/downclock\n");

5428

"LVDS clock/downclock\n");

5429

has_reduced_clock = 0;

5429

has_reduced_clock = 0;

5430

}

5430

}

5431

}

5431

}

5432

/* SDVO TV has fixed PLL values depend on its clock range,

5432

/* SDVO TV has fixed PLL values depend on its clock range,

5433

this mirrors vbios setting. */

5433

this mirrors vbios setting. */

5434

if (is_sdvo && is_tv) {

5434

if (is_sdvo && is_tv) {

5435

if (adjusted_mode->clock >= 100000

5435

if (adjusted_mode->clock >= 100000

5436

&& adjusted_mode->clock < 140500) {

5436

&& adjusted_mode->clock < 140500) {

5437

clock.p1 = 2;

5437

clock.p1 = 2;

5438

clock.p2 = 10;

5438

clock.p2 = 10;

5439

clock.n = 3;

5439

clock.n = 3;

5440

clock.m1 = 16;

5440

clock.m1 = 16;

5441

clock.m2 = 8;

5441

clock.m2 = 8;

5442

} else if (adjusted_mode->clock >= 140500

5442

} else if (adjusted_mode->clock >= 140500

5443

&& adjusted_mode->clock <= 200000) {

5443

&& adjusted_mode->clock <= 200000) {

5444

clock.p1 = 1;

5444

clock.p1 = 1;

5445

clock.p2 = 10;

5445

clock.p2 = 10;

5446

clock.n = 6;

5446

clock.n = 6;

5447

clock.m1 = 12;

5447

clock.m1 = 12;

5448

clock.m2 = 8;

5448

clock.m2 = 8;

5449

}

5449

}

5450

}

5450

}

5451

5452

/* FDI link */

5452

/* FDI link */

5453

pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);

5453

pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);

5454

lane = 0;

5454

lane = 0;

5455

/* CPU eDP doesn't require FDI link, so just set DP M/N

5455

/* CPU eDP doesn't require FDI link, so just set DP M/N

5456

according to current link config */

5456

according to current link config */

5457

if (has_edp_encoder &&

5457

if (has_edp_encoder &&

5458

!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {

5458

!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {

5459

target_clock = mode->clock;

5459

target_clock = mode->clock;

5460

intel_edp_link_config(has_edp_encoder,

5460

intel_edp_link_config(has_edp_encoder,

5461

&lane, &link_bw);

5461

&lane, &link_bw);

5462

} else {

5462

} else {

5463

/* [e]DP over FDI requires target mode clock

5463

/* [e]DP over FDI requires target mode clock

5464

instead of link clock */

5464

instead of link clock */

5465

if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))

5465

if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))

5466

target_clock = mode->clock;

5466

target_clock = mode->clock;

5467

else

5467

else

5468

target_clock = adjusted_mode->clock;

5468

target_clock = adjusted_mode->clock;

5469

5470

/* FDI is a binary signal running at ~2.7GHz, encoding

5470

/* FDI is a binary signal running at ~2.7GHz, encoding

5471

* each output octet as 10 bits. The actual frequency

5471

* each output octet as 10 bits. The actual frequency

5472

* is stored as a divider into a 100MHz clock, and the

5472

* is stored as a divider into a 100MHz clock, and the

5473

* mode pixel clock is stored in units of 1KHz.

5473

* mode pixel clock is stored in units of 1KHz.

5474

* Hence the bw of each lane in terms of the mode signal

5474

* Hence the bw of each lane in terms of the mode signal

5475

* is:

5475

* is:

5476

*/

5476

*/

5477

link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;

5477

link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;

5478

}

5478

}

5479

5480

/* determine panel color depth */

5480

/* determine panel color depth */

5481

temp = I915_READ(PIPECONF(pipe));

5481

temp = I915_READ(PIPECONF(pipe));

5482

temp &= ~PIPE_BPC_MASK;

5482

temp &= ~PIPE_BPC_MASK;

5483

dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);

5483

dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);

5484

switch (pipe_bpp) {

5484

switch (pipe_bpp) {

5485

case 18:

5485

case 18:

5486

temp |= PIPE_6BPC;

5486

temp |= PIPE_6BPC;

5487

break;

5487

break;

5488

case 24:

5488

case 24:

5489

temp |= PIPE_8BPC;

5489

temp |= PIPE_8BPC;

5490

break;

5490

break;

5491

case 30:

5491

case 30:

5492

temp |= PIPE_10BPC;

5492

temp |= PIPE_10BPC;

5493

break;

5493

break;

5494

case 36:

5494

case 36:

5495

temp |= PIPE_12BPC;

5495

temp |= PIPE_12BPC;

5496

break;

5496

break;

5497

default:

5497

default:

5498

WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",

5498

WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",

5499

pipe_bpp);

5499

pipe_bpp);

5500

temp |= PIPE_8BPC;

5500

temp |= PIPE_8BPC;

5501

pipe_bpp = 24;

5501

pipe_bpp = 24;

5502

break;

5502

break;

5503

}

5503

}

5504

5505

intel_crtc->bpp = pipe_bpp;

5505

intel_crtc->bpp = pipe_bpp;

5506

I915_WRITE(PIPECONF(pipe), temp);

5506

I915_WRITE(PIPECONF(pipe), temp);

5507

5508

if (!lane) {

5508

if (!lane) {

5509

/*

5509

/*

5510

* Account for spread spectrum to avoid

5510

* Account for spread spectrum to avoid

5511

* oversubscribing the link. Max center spread

5511

* oversubscribing the link. Max center spread

5512

* is 2.5%; use 5% for safety's sake.

5512

* is 2.5%; use 5% for safety's sake.

5513

*/

5513

*/

5514

u32 bps = target_clock * intel_crtc->bpp * 21 / 20;

5514

u32 bps = target_clock * intel_crtc->bpp * 21 / 20;

5515

lane = bps / (link_bw * 8) + 1;

5515

lane = bps / (link_bw * 8) + 1;

5516

}

5516

}

5517

5518

intel_crtc->fdi_lanes = lane;

5518

intel_crtc->fdi_lanes = lane;

5519

5520

if (pixel_multiplier > 1)

5520

if (pixel_multiplier > 1)

5521

link_bw *= pixel_multiplier;

5521

link_bw *= pixel_multiplier;

5522

ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,

5522

ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,

5523

&m_n);

5523

&m_n);

5524

5525

fp = clock.n << 16 | clock.m1 << 8 | clock.m2;

5525

fp = clock.n << 16 | clock.m1 << 8 | clock.m2;

5526

if (has_reduced_clock)

5526

if (has_reduced_clock)

5527

fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |

5527

fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |

5528

reduced_clock.m2;

5528

reduced_clock.m2;

5529

5530

/* Enable autotuning of the PLL clock (if permissible) */

5530

/* Enable autotuning of the PLL clock (if permissible) */

5531

factor = 21;

5531

factor = 21;

5532

if (is_lvds) {

5532

if (is_lvds) {

5533

if ((intel_panel_use_ssc(dev_priv) &&

5533

if ((intel_panel_use_ssc(dev_priv) &&

5534

dev_priv->lvds_ssc_freq == 100) ||

5534

dev_priv->lvds_ssc_freq == 100) ||

5535

(I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)

5535

(I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)

5536

factor = 25;

5536

factor = 25;

5537

} else if (is_sdvo && is_tv)

5537

} else if (is_sdvo && is_tv)

5538

factor = 20;

5538

factor = 20;

5539

5540

if (clock.m < factor * clock.n)

5540

if (clock.m < factor * clock.n)

5541

fp |= FP_CB_TUNE;

5541

fp |= FP_CB_TUNE;

5542

5543

dpll = 0;

5543

dpll = 0;

5544

5545

if (is_lvds)

5545

if (is_lvds)

5546

dpll |= DPLLB_MODE_LVDS;

5546

dpll |= DPLLB_MODE_LVDS;

5547

else

5547

else

5548

dpll |= DPLLB_MODE_DAC_SERIAL;

5548

dpll |= DPLLB_MODE_DAC_SERIAL;

5549

if (is_sdvo) {

5549

if (is_sdvo) {

5550

int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);

5550

int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);

5551

if (pixel_multiplier > 1) {

5551

if (pixel_multiplier > 1) {

5552

dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;

5552

dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;

5553

}

5553

}

5554

dpll |= DPLL_DVO_HIGH_SPEED;

5554

dpll |= DPLL_DVO_HIGH_SPEED;

5555

}

5555

}

5556

if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))

5556

if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))

5557

dpll |= DPLL_DVO_HIGH_SPEED;

5557

dpll |= DPLL_DVO_HIGH_SPEED;

5558

5559

/* compute bitmask from p1 value */

5559

/* compute bitmask from p1 value */

5560

dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;

5560

dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;

5561

/* also FPA1 */

5561

/* also FPA1 */

5562

dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;

5562

dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;

5563

5564

switch (clock.p2) {

5564

switch (clock.p2) {

5565

case 5:

5565

case 5:

5566

dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;

5566

dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;

5567

break;

5567

break;

5568

case 7:

5568

case 7:

5569

dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;

5569

dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;

5570

break;

5570

break;

5571

case 10:

5571

case 10:

5572

dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;

5572

dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;

5573

break;

5573

break;

5574

case 14:

5574

case 14:

5575

dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;

5575

dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;

5576

break;

5576

break;

5577

}

5577

}

5578

5579

if (is_sdvo && is_tv)

5579

if (is_sdvo && is_tv)

5580

dpll |= PLL_REF_INPUT_TVCLKINBC;

5580

dpll |= PLL_REF_INPUT_TVCLKINBC;

5581

else if (is_tv)

5581

else if (is_tv)

5582

/* XXX: just matching BIOS for now */

5582

/* XXX: just matching BIOS for now */

5583

/* dpll |= PLL_REF_INPUT_TVCLKINBC; */

5583

/* dpll |= PLL_REF_INPUT_TVCLKINBC; */

5584

dpll |= 3;

5584

dpll |= 3;

5585

else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)

5585

else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)

5586

dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;

5586

dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;

5587

else

5587

else

5588

dpll |= PLL_REF_INPUT_DREFCLK;

5588

dpll |= PLL_REF_INPUT_DREFCLK;

5589

5590

/* setup pipeconf */

5590

/* setup pipeconf */

5591

pipeconf = I915_READ(PIPECONF(pipe));

5591

pipeconf = I915_READ(PIPECONF(pipe));

5592

5593

/* Set up the display plane register */

5593

/* Set up the display plane register */

5594

dspcntr = DISPPLANE_GAMMA_ENABLE;

5594

dspcntr = DISPPLANE_GAMMA_ENABLE;

5595

5596

DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);

5596

DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);

5597

drm_mode_debug_printmodeline(mode);

5597

drm_mode_debug_printmodeline(mode);

5598

5599

/* PCH eDP needs FDI, but CPU eDP does not */

5599

/* PCH eDP needs FDI, but CPU eDP does not */

5600

if (!intel_crtc->no_pll) {

5600

if (!intel_crtc->no_pll) {

5601

if (!has_edp_encoder ||

5601

if (!has_edp_encoder ||

5602

intel_encoder_is_pch_edp(&has_edp_encoder->base)) {

5602

intel_encoder_is_pch_edp(&has_edp_encoder->base)) {

5603

I915_WRITE(PCH_FP0(pipe), fp);

5603

I915_WRITE(PCH_FP0(pipe), fp);

5604

I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);

5604

I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);

5605

5606

POSTING_READ(PCH_DPLL(pipe));

5606

POSTING_READ(PCH_DPLL(pipe));

5607

udelay(150);

5607

udelay(150);

5608

}

5608

}

5609

} else {

5609

} else {

5610

if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&

5610

if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&

5611

fp == I915_READ(PCH_FP0(0))) {

5611

fp == I915_READ(PCH_FP0(0))) {

5612

intel_crtc->use_pll_a = true;

5612

intel_crtc->use_pll_a = true;

5613

DRM_DEBUG_KMS("using pipe a dpll\n");

5613

DRM_DEBUG_KMS("using pipe a dpll\n");

5614

} else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&

5614

} else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&

5615

fp == I915_READ(PCH_FP0(1))) {

5615

fp == I915_READ(PCH_FP0(1))) {

5616

intel_crtc->use_pll_a = false;

5616

intel_crtc->use_pll_a = false;

5617

DRM_DEBUG_KMS("using pipe b dpll\n");

5617

DRM_DEBUG_KMS("using pipe b dpll\n");

5618

} else {

5618

} else {

5619

DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");

5619

DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");

5620

return -EINVAL;

5620

return -EINVAL;

5621

}

5621

}

5622

}

5622

}

5623

5624

/* The LVDS pin pair needs to be on before the DPLLs are enabled.

5624

/* The LVDS pin pair needs to be on before the DPLLs are enabled.

5625

* This is an exception to the general rule that mode_set doesn't turn

5625

* This is an exception to the general rule that mode_set doesn't turn

5626

* things on.

5626

* things on.

5627

*/

5627

*/

5628

if (is_lvds) {

5628

if (is_lvds) {

5629

temp = I915_READ(PCH_LVDS);

5629

temp = I915_READ(PCH_LVDS);

5630

temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;

5630

temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;

5631

if (HAS_PCH_CPT(dev))

5631

if (HAS_PCH_CPT(dev))

5632

temp |= PORT_TRANS_SEL_CPT(pipe);

5632

temp |= PORT_TRANS_SEL_CPT(pipe);

5633

else if (pipe == 1)

5633

else if (pipe == 1)

5634

temp |= LVDS_PIPEB_SELECT;

5634

temp |= LVDS_PIPEB_SELECT;

5635

else

5635

else

5636

temp &= ~LVDS_PIPEB_SELECT;

5636

temp &= ~LVDS_PIPEB_SELECT;

5637

5638

/* set the corresponsding LVDS_BORDER bit */

5638

/* set the corresponsding LVDS_BORDER bit */

5639

temp |= dev_priv->lvds_border_bits;

5639

temp |= dev_priv->lvds_border_bits;

5640

/* Set the B0-B3 data pairs corresponding to whether we're going to

5640

/* Set the B0-B3 data pairs corresponding to whether we're going to

5641

* set the DPLLs for dual-channel mode or not.

5641

* set the DPLLs for dual-channel mode or not.

5642

*/

5642

*/

5643

if (clock.p2 == 7)

5643

if (clock.p2 == 7)

5644

temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;

5644

temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;

5645

else

5645

else

5646

temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);

5646

temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);

5647

5648

/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)

5648

/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)

5649

* appropriately here, but we need to look more thoroughly into how

5649

* appropriately here, but we need to look more thoroughly into how

5650

* panels behave in the two modes.

5650

* panels behave in the two modes.

5651

*/

5651

*/

5652

if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)

5652

if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)

5653

lvds_sync |= LVDS_HSYNC_POLARITY;

5653

lvds_sync |= LVDS_HSYNC_POLARITY;

5654

if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)

5654

if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)

5655

lvds_sync |= LVDS_VSYNC_POLARITY;

5655

lvds_sync |= LVDS_VSYNC_POLARITY;

5656

if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))

5656

if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))

5657

!= lvds_sync) {

5657

!= lvds_sync) {

5658

char flags[2] = "-+";

5658

char flags[2] = "-+";

5659

DRM_INFO("Changing LVDS panel from "

5659

DRM_INFO("Changing LVDS panel from "

5660

"(%chsync, %cvsync) to (%chsync, %cvsync)\n",

5660

"(%chsync, %cvsync) to (%chsync, %cvsync)\n",

5661

flags[!(temp & LVDS_HSYNC_POLARITY)],

5661

flags[!(temp & LVDS_HSYNC_POLARITY)],

5662

flags[!(temp & LVDS_VSYNC_POLARITY)],

5662

flags[!(temp & LVDS_VSYNC_POLARITY)],

5663

flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],

5663

flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],

5664

flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);

5664

flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);

5665

temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);

5665

temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);

5666

temp |= lvds_sync;

5666

temp |= lvds_sync;

5667

}

5667

}

5668

I915_WRITE(PCH_LVDS, temp);

5668

I915_WRITE(PCH_LVDS, temp);

5669

}

5669

}

5670

5671

pipeconf &= ~PIPECONF_DITHER_EN;

5671

pipeconf &= ~PIPECONF_DITHER_EN;

5672

pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;

5672

pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;

5673

if ((is_lvds && dev_priv->lvds_dither) || dither) {

5673

if ((is_lvds && dev_priv->lvds_dither) || dither) {

5674

pipeconf |= PIPECONF_DITHER_EN;

5674

pipeconf |= PIPECONF_DITHER_EN;

5675

pipeconf |= PIPECONF_DITHER_TYPE_SP;

5675

pipeconf |= PIPECONF_DITHER_TYPE_SP;

5676

}

5676

}

5677

if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {

5677

if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {

5678

intel_dp_set_m_n(crtc, mode, adjusted_mode);

5678

intel_dp_set_m_n(crtc, mode, adjusted_mode);

5679

} else {

5679

} else {

5680

/* For non-DP output, clear any trans DP clock recovery setting.*/

5680

/* For non-DP output, clear any trans DP clock recovery setting.*/

5681

I915_WRITE(TRANSDATA_M1(pipe), 0);

5681

I915_WRITE(TRANSDATA_M1(pipe), 0);

5682

I915_WRITE(TRANSDATA_N1(pipe), 0);

5682

I915_WRITE(TRANSDATA_N1(pipe), 0);

5683

I915_WRITE(TRANSDPLINK_M1(pipe), 0);

5683

I915_WRITE(TRANSDPLINK_M1(pipe), 0);

5684

I915_WRITE(TRANSDPLINK_N1(pipe), 0);

5684

I915_WRITE(TRANSDPLINK_N1(pipe), 0);

5685

}

5685

}

5686

5687

if (!intel_crtc->no_pll &&

5687

if (!intel_crtc->no_pll &&

5688

(!has_edp_encoder ||

5688

(!has_edp_encoder ||

5689

intel_encoder_is_pch_edp(&has_edp_encoder->base))) {

5689

intel_encoder_is_pch_edp(&has_edp_encoder->base))) {

5690

I915_WRITE(PCH_DPLL(pipe), dpll);

5690

I915_WRITE(PCH_DPLL(pipe), dpll);

5691

5692

/* Wait for the clocks to stabilize. */

5692

/* Wait for the clocks to stabilize. */

5693

POSTING_READ(PCH_DPLL(pipe));

5693

POSTING_READ(PCH_DPLL(pipe));

5694

udelay(150);

5694

udelay(150);

5695

5696

/* The pixel multiplier can only be updated once the

5696

/* The pixel multiplier can only be updated once the

5697

* DPLL is enabled and the clocks are stable.

5697

* DPLL is enabled and the clocks are stable.

5698

*

5698

*

5699

* So write it again.

5699

* So write it again.

5700

*/

5700

*/

5701

I915_WRITE(PCH_DPLL(pipe), dpll);

5701

I915_WRITE(PCH_DPLL(pipe), dpll);

5702

}

5702

}

5703

5704

intel_crtc->lowfreq_avail = false;

5704

intel_crtc->lowfreq_avail = false;

5705

if (!intel_crtc->no_pll) {

5705

if (!intel_crtc->no_pll) {

5706

if (is_lvds && has_reduced_clock && i915_powersave) {

5706

if (is_lvds && has_reduced_clock && i915_powersave) {

5707

I915_WRITE(PCH_FP1(pipe), fp2);

5707

I915_WRITE(PCH_FP1(pipe), fp2);

5708

intel_crtc->lowfreq_avail = true;

5708

intel_crtc->lowfreq_avail = true;

5709

if (HAS_PIPE_CXSR(dev)) {

5709

if (HAS_PIPE_CXSR(dev)) {

5710

DRM_DEBUG_KMS("enabling CxSR downclocking\n");

5710

DRM_DEBUG_KMS("enabling CxSR downclocking\n");

5711

pipeconf |= PIPECONF_CXSR_DOWNCLOCK;

5711

pipeconf |= PIPECONF_CXSR_DOWNCLOCK;

5712

}

5712

}

5713

} else {

5713

} else {

5714

I915_WRITE(PCH_FP1(pipe), fp);

5714

I915_WRITE(PCH_FP1(pipe), fp);

5715

if (HAS_PIPE_CXSR(dev)) {

5715

if (HAS_PIPE_CXSR(dev)) {

5716

DRM_DEBUG_KMS("disabling CxSR downclocking\n");

5716

DRM_DEBUG_KMS("disabling CxSR downclocking\n");

5717

pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;

5717

pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;

5718

}

5718

}

5719

}

5719

}

5720

}

5720

}

5721

5722

if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {

5722

if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {

5723

pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;

5723

pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;

5724

/* the chip adds 2 halflines automatically */

5724

/* the chip adds 2 halflines automatically */

5725

adjusted_mode->crtc_vdisplay -= 1;

5725

adjusted_mode->crtc_vdisplay -= 1;

5726

adjusted_mode->crtc_vtotal -= 1;

5726

adjusted_mode->crtc_vtotal -= 1;

5727

adjusted_mode->crtc_vblank_start -= 1;

5727

adjusted_mode->crtc_vblank_start -= 1;

5728

adjusted_mode->crtc_vblank_end -= 1;

5728

adjusted_mode->crtc_vblank_end -= 1;

5729

adjusted_mode->crtc_vsync_end -= 1;

5729

adjusted_mode->crtc_vsync_end -= 1;

5730

adjusted_mode->crtc_vsync_start -= 1;

5730

adjusted_mode->crtc_vsync_start -= 1;

5731

} else

5731

} else

5732

pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */

5732

pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */

5733

5734

I915_WRITE(HTOTAL(pipe),

5734

I915_WRITE(HTOTAL(pipe),

5735

(adjusted_mode->crtc_hdisplay - 1) |

5735

(adjusted_mode->crtc_hdisplay - 1) |

5736

((adjusted_mode->crtc_htotal - 1) << 16));

5736

((adjusted_mode->crtc_htotal - 1) << 16));

5737

I915_WRITE(HBLANK(pipe),

5737

I915_WRITE(HBLANK(pipe),

5738

(adjusted_mode->crtc_hblank_start - 1) |

5738

(adjusted_mode->crtc_hblank_start - 1) |

5739

((adjusted_mode->crtc_hblank_end - 1) << 16));

5739

((adjusted_mode->crtc_hblank_end - 1) << 16));

5740

I915_WRITE(HSYNC(pipe),

5740

I915_WRITE(HSYNC(pipe),

5741

(adjusted_mode->crtc_hsync_start - 1) |

5741

(adjusted_mode->crtc_hsync_start - 1) |

5742

((adjusted_mode->crtc_hsync_end - 1) << 16));

5742

((adjusted_mode->crtc_hsync_end - 1) << 16));

5743

5744

I915_WRITE(VTOTAL(pipe),

5744

I915_WRITE(VTOTAL(pipe),

5745

(adjusted_mode->crtc_vdisplay - 1) |

5745

(adjusted_mode->crtc_vdisplay - 1) |

5746

((adjusted_mode->crtc_vtotal - 1) << 16));

5746

((adjusted_mode->crtc_vtotal - 1) << 16));

5747

I915_WRITE(VBLANK(pipe),

5747

I915_WRITE(VBLANK(pipe),

5748

(adjusted_mode->crtc_vblank_start - 1) |

5748

(adjusted_mode->crtc_vblank_start - 1) |

5749

((adjusted_mode->crtc_vblank_end - 1) << 16));

5749

((adjusted_mode->crtc_vblank_end - 1) << 16));

5750

I915_WRITE(VSYNC(pipe),

5750

I915_WRITE(VSYNC(pipe),

5751

(adjusted_mode->crtc_vsync_start - 1) |

5751

(adjusted_mode->crtc_vsync_start - 1) |

5752

((adjusted_mode->crtc_vsync_end - 1) << 16));

5752

((adjusted_mode->crtc_vsync_end - 1) << 16));

5753

5754

/* pipesrc controls the size that is scaled from, which should

5754

/* pipesrc controls the size that is scaled from, which should

5755

* always be the user's requested size.

5755

* always be the user's requested size.

5756

*/

5756

*/

5757

I915_WRITE(PIPESRC(pipe),

5757

I915_WRITE(PIPESRC(pipe),

5758

((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));

5758

((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));

5759

5760

I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);

5760

I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);

5761

I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);

5761

I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);

5762

I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);

5762

I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);

5763

I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);

5763

I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);

5764

5765

if (has_edp_encoder &&

5765

if (has_edp_encoder &&

5766

!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {

5766

!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {

5767

ironlake_set_pll_edp(crtc, adjusted_mode->clock);

5767

ironlake_set_pll_edp(crtc, adjusted_mode->clock);

5768

}

5768

}

5769

5770

I915_WRITE(PIPECONF(pipe), pipeconf);

5770

I915_WRITE(PIPECONF(pipe), pipeconf);

5771

POSTING_READ(PIPECONF(pipe));

5771

POSTING_READ(PIPECONF(pipe));

5772

5773

intel_wait_for_vblank(dev, pipe);

5773

intel_wait_for_vblank(dev, pipe);

5774

5775

if (IS_GEN5(dev)) {

5775

if (IS_GEN5(dev)) {

5776

/* enable address swizzle for tiling buffer */

5776

/* enable address swizzle for tiling buffer */

5777

temp = I915_READ(DISP_ARB_CTL);

5777

temp = I915_READ(DISP_ARB_CTL);

5778

I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);

5778

I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);

5779

}

5779

}

5780

5781

I915_WRITE(DSPCNTR(plane), dspcntr);

5781

I915_WRITE(DSPCNTR(plane), dspcntr);

5782

POSTING_READ(DSPCNTR(plane));

5782

POSTING_READ(DSPCNTR(plane));

5783

5784

ret = intel_pipe_set_base(crtc, x, y, old_fb);

5784

ret = intel_pipe_set_base(crtc, x, y, old_fb);

5785

5786

intel_update_watermarks(dev);

5786

intel_update_watermarks(dev);

5787

5788

return ret;

5788

return ret;

5789

}

5789

}

5790

5791

static int intel_crtc_mode_set(struct drm_crtc *crtc,

5791

static int intel_crtc_mode_set(struct drm_crtc *crtc,

5792

struct drm_display_mode *mode,

5792

struct drm_display_mode *mode,

5793

struct drm_display_mode *adjusted_mode,

5793

struct drm_display_mode *adjusted_mode,

5794

int x, int y,

5794

int x, int y,

5795

struct drm_framebuffer *old_fb)

5795

struct drm_framebuffer *old_fb)

5796

{

5796

{

5797

struct drm_device *dev = crtc->dev;

5797

struct drm_device *dev = crtc->dev;

5798

struct drm_i915_private *dev_priv = dev->dev_private;

5798

struct drm_i915_private *dev_priv = dev->dev_private;

5799

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

5799

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

5800

int pipe = intel_crtc->pipe;

5800

int pipe = intel_crtc->pipe;

5801

int ret;

5801

int ret;

5802

5803

drm_vblank_pre_modeset(dev, pipe);

5803

drm_vblank_pre_modeset(dev, pipe);

5804

5805

ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,

5805

ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,

5806

x, y, old_fb);

5806

x, y, old_fb);

5807

5808

drm_vblank_post_modeset(dev, pipe);

5808

drm_vblank_post_modeset(dev, pipe);

5809

5810

intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;

5810

intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;

5811

5812

return ret;

5812

return ret;

5813

}

5813

}

5814

5815

static void g4x_write_eld(struct drm_connector *connector,

5815

static void g4x_write_eld(struct drm_connector *connector,

5816

struct drm_crtc *crtc)

5816

struct drm_crtc *crtc)

5817

{

5817

{

5818

struct drm_i915_private *dev_priv = connector->dev->dev_private;

5818

struct drm_i915_private *dev_priv = connector->dev->dev_private;

5819

uint8_t *eld = connector->eld;

5819

uint8_t *eld = connector->eld;

5820

uint32_t eldv;

5820

uint32_t eldv;

5821

uint32_t len;

5821

uint32_t len;

5822

uint32_t i;

5822

uint32_t i;

5823

5824

i = I915_READ(G4X_AUD_VID_DID);

5824

i = I915_READ(G4X_AUD_VID_DID);

5825

5826

if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)

5826

if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)

5827

eldv = G4X_ELDV_DEVCL_DEVBLC;

5827

eldv = G4X_ELDV_DEVCL_DEVBLC;

5828

else

5828

else

5829

eldv = G4X_ELDV_DEVCTG;

5829

eldv = G4X_ELDV_DEVCTG;

5830

5831

i = I915_READ(G4X_AUD_CNTL_ST);

5831

i = I915_READ(G4X_AUD_CNTL_ST);

5832

i &= ~(eldv | G4X_ELD_ADDR);

5832

i &= ~(eldv | G4X_ELD_ADDR);

5833

len = (i >> 9) & 0x1f; /* ELD buffer size */

5833

len = (i >> 9) & 0x1f; /* ELD buffer size */

5834

I915_WRITE(G4X_AUD_CNTL_ST, i);

5834

I915_WRITE(G4X_AUD_CNTL_ST, i);

5835

5836

if (!eld[0])

5836

if (!eld[0])

5837

return;

5837

return;

5838

5839

len = min_t(uint8_t, eld[2], len);

5839

len = min_t(uint8_t, eld[2], len);

5840

DRM_DEBUG_DRIVER("ELD size %d\n", len);

5840

DRM_DEBUG_DRIVER("ELD size %d\n", len);

5841

for (i = 0; i < len; i++)

5841

for (i = 0; i < len; i++)

5842

I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));

5842

I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));

5843

5844

i = I915_READ(G4X_AUD_CNTL_ST);

5844

i = I915_READ(G4X_AUD_CNTL_ST);

5845

i |= eldv;

5845

i |= eldv;

5846

I915_WRITE(G4X_AUD_CNTL_ST, i);

5846

I915_WRITE(G4X_AUD_CNTL_ST, i);

5847

}

5847

}

5848

5849

static void ironlake_write_eld(struct drm_connector *connector,

5849

static void ironlake_write_eld(struct drm_connector *connector,

5850

struct drm_crtc *crtc)

5850

struct drm_crtc *crtc)

5851

{

5851

{

5852

struct drm_i915_private *dev_priv = connector->dev->dev_private;

5852

struct drm_i915_private *dev_priv = connector->dev->dev_private;

5853

uint8_t *eld = connector->eld;

5853

uint8_t *eld = connector->eld;

5854

uint32_t eldv;

5854

uint32_t eldv;

5855

uint32_t i;

5855

uint32_t i;

5856

int len;

5856

int len;

5857

int hdmiw_hdmiedid;

5857

int hdmiw_hdmiedid;

5858

int aud_cntl_st;

5858

int aud_cntl_st;

5859

int aud_cntrl_st2;

5859

int aud_cntrl_st2;

5860

5861

if (IS_IVYBRIDGE(connector->dev)) {

5861

if (IS_IVYBRIDGE(connector->dev)) {

5862

hdmiw_hdmiedid = GEN7_HDMIW_HDMIEDID_A;

5862

hdmiw_hdmiedid = GEN7_HDMIW_HDMIEDID_A;

5863

aud_cntl_st = GEN7_AUD_CNTRL_ST_A;

5863

aud_cntl_st = GEN7_AUD_CNTRL_ST_A;

5864

aud_cntrl_st2 = GEN7_AUD_CNTRL_ST2;

5864

aud_cntrl_st2 = GEN7_AUD_CNTRL_ST2;

5865

} else {

5865

} else {

5866

hdmiw_hdmiedid = GEN5_HDMIW_HDMIEDID_A;

5866

hdmiw_hdmiedid = GEN5_HDMIW_HDMIEDID_A;

5867

aud_cntl_st = GEN5_AUD_CNTL_ST_A;

5867

aud_cntl_st = GEN5_AUD_CNTL_ST_A;

5868

aud_cntrl_st2 = GEN5_AUD_CNTL_ST2;

5868

aud_cntrl_st2 = GEN5_AUD_CNTL_ST2;

5869

}

5869

}

5870

5871

i = to_intel_crtc(crtc)->pipe;

5871

i = to_intel_crtc(crtc)->pipe;

5872

hdmiw_hdmiedid += i * 0x100;

5872

hdmiw_hdmiedid += i * 0x100;

5873

aud_cntl_st += i * 0x100;

5873

aud_cntl_st += i * 0x100;

5874

5875

DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));

5875

DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));

5876

5877

i = I915_READ(aud_cntl_st);

5877

i = I915_READ(aud_cntl_st);

5878

i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */

5878

i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */

5879

if (!i) {

5879

if (!i) {

5880

DRM_DEBUG_DRIVER("Audio directed to unknown port\n");

5880

DRM_DEBUG_DRIVER("Audio directed to unknown port\n");

5881

/* operate blindly on all ports */

5881

/* operate blindly on all ports */

5882

eldv = GEN5_ELD_VALIDB;

5882

eldv = GEN5_ELD_VALIDB;

5883

eldv |= GEN5_ELD_VALIDB << 4;

5883

eldv |= GEN5_ELD_VALIDB << 4;

5884

eldv |= GEN5_ELD_VALIDB << 8;

5884

eldv |= GEN5_ELD_VALIDB << 8;

5885

} else {

5885

} else {

5886

DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);

5886

DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);

5887

eldv = GEN5_ELD_VALIDB << ((i - 1) * 4);

5887

eldv = GEN5_ELD_VALIDB << ((i - 1) * 4);

5888

}

5888

}

5889

5890

i = I915_READ(aud_cntrl_st2);

5890

i = I915_READ(aud_cntrl_st2);

5891

i &= ~eldv;

5891

i &= ~eldv;

5892

I915_WRITE(aud_cntrl_st2, i);

5892

I915_WRITE(aud_cntrl_st2, i);

5893

5894

if (!eld[0])

5894

if (!eld[0])

5895

return;

5895

return;

5896

5897

if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {

5897

if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {

5898

DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");

5898

DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");

5899

eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */

5899

eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */

5900

}

5900

}

5901

5902

i = I915_READ(aud_cntl_st);

5902

i = I915_READ(aud_cntl_st);

5903

i &= ~GEN5_ELD_ADDRESS;

5903

i &= ~GEN5_ELD_ADDRESS;

5904

I915_WRITE(aud_cntl_st, i);

5904

I915_WRITE(aud_cntl_st, i);

5905

5906

len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */

5906

len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */

5907

DRM_DEBUG_DRIVER("ELD size %d\n", len);

5907

DRM_DEBUG_DRIVER("ELD size %d\n", len);

5908

for (i = 0; i < len; i++)

5908

for (i = 0; i < len; i++)

5909

I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));

5909

I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));

5910

5911

i = I915_READ(aud_cntrl_st2);

5911

i = I915_READ(aud_cntrl_st2);

5912

i |= eldv;

5912

i |= eldv;

5913

I915_WRITE(aud_cntrl_st2, i);

5913

I915_WRITE(aud_cntrl_st2, i);

5914

}

5914

}

5915

5916

void intel_write_eld(struct drm_encoder *encoder,

5916

void intel_write_eld(struct drm_encoder *encoder,

5917

struct drm_display_mode *mode)

5917

struct drm_display_mode *mode)

5918

{

5918

{

5919

struct drm_crtc *crtc = encoder->crtc;

5919

struct drm_crtc *crtc = encoder->crtc;

5920

struct drm_connector *connector;

5920

struct drm_connector *connector;

5921

struct drm_device *dev = encoder->dev;

5921

struct drm_device *dev = encoder->dev;

5922

struct drm_i915_private *dev_priv = dev->dev_private;

5922

struct drm_i915_private *dev_priv = dev->dev_private;

5923

5924

connector = drm_select_eld(encoder, mode);

5924

connector = drm_select_eld(encoder, mode);

5925

if (!connector)

5925

if (!connector)

5926

return;

5926

return;

5927

5928

DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",

5928

DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",

5929

connector->base.id,

5929

connector->base.id,

5930

drm_get_connector_name(connector),

5930

drm_get_connector_name(connector),

5931

connector->encoder->base.id,

5931

connector->encoder->base.id,

5932

drm_get_encoder_name(connector->encoder));

5932

drm_get_encoder_name(connector->encoder));

5933

5934

connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;

5934

connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;

5935

5936

if (dev_priv->display.write_eld)

5936

if (dev_priv->display.write_eld)

5937

dev_priv->display.write_eld(connector, crtc);

5937

dev_priv->display.write_eld(connector, crtc);

5938

}

5938

}

5939

5940

/** Loads the palette/gamma unit for the CRTC with the prepared values */

5940

/** Loads the palette/gamma unit for the CRTC with the prepared values */

5941

void intel_crtc_load_lut(struct drm_crtc *crtc)

5941

void intel_crtc_load_lut(struct drm_crtc *crtc)

5942

{

5942

{

5943

struct drm_device *dev = crtc->dev;

5943

struct drm_device *dev = crtc->dev;

5944

struct drm_i915_private *dev_priv = dev->dev_private;

5944

struct drm_i915_private *dev_priv = dev->dev_private;

5945

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

5945

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

5946

int palreg = PALETTE(intel_crtc->pipe);

5946

int palreg = PALETTE(intel_crtc->pipe);

5947

int i;

5947

int i;

5948

5949

/* The clocks have to be on to load the palette. */

5949

/* The clocks have to be on to load the palette. */

5950

if (!crtc->enabled)

5950

if (!crtc->enabled)

5951

return;

5951

return;

5952

5953

/* use legacy palette for Ironlake */

5953

/* use legacy palette for Ironlake */

5954

if (HAS_PCH_SPLIT(dev))

5954

if (HAS_PCH_SPLIT(dev))

5955

palreg = LGC_PALETTE(intel_crtc->pipe);

5955

palreg = LGC_PALETTE(intel_crtc->pipe);

5956

5957

for (i = 0; i < 256; i++) {

5957

for (i = 0; i < 256; i++) {

5958

I915_WRITE(palreg + 4 * i,

5958

I915_WRITE(palreg + 4 * i,

5959

(intel_crtc->lut_r[i] << 16) |

5959

(intel_crtc->lut_r[i] << 16) |

5960

(intel_crtc->lut_g[i] << 8) |

5960

(intel_crtc->lut_g[i] << 8) |

5961

intel_crtc->lut_b[i]);

5961

intel_crtc->lut_b[i]);

5962

}

5962

}

5963

}

5963

}

5964

5965

static void i845_update_cursor(struct drm_crtc *crtc, u32 base)

5965

static void i845_update_cursor(struct drm_crtc *crtc, u32 base)

5966

{

5966

{

5967

struct drm_device *dev = crtc->dev;

5967

struct drm_device *dev = crtc->dev;

5968

struct drm_i915_private *dev_priv = dev->dev_private;

5968

struct drm_i915_private *dev_priv = dev->dev_private;

5969

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

5969

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

5970

bool visible = base != 0;

5970

bool visible = base != 0;

5971

u32 cntl;

5971

u32 cntl;

5972

5973

if (intel_crtc->cursor_visible == visible)

5973

if (intel_crtc->cursor_visible == visible)

5974

return;

5974

return;

5975

5976

cntl = I915_READ(_CURACNTR);

5976

cntl = I915_READ(_CURACNTR);

5977

if (visible) {

5977

if (visible) {

5978

/* On these chipsets we can only modify the base whilst

5978

/* On these chipsets we can only modify the base whilst

5979

* the cursor is disabled.

5979

* the cursor is disabled.

5980

*/

5980

*/

5981

I915_WRITE(_CURABASE, base);

5981

I915_WRITE(_CURABASE, base);

5982

5983

cntl &= ~(CURSOR_FORMAT_MASK);

5983

cntl &= ~(CURSOR_FORMAT_MASK);

5984

/* XXX width must be 64, stride 256 => 0x00 << 28 */

5984

/* XXX width must be 64, stride 256 => 0x00 << 28 */

5985

cntl |= CURSOR_ENABLE |

5985

cntl |= CURSOR_ENABLE |

5986

CURSOR_GAMMA_ENABLE |

5986

CURSOR_GAMMA_ENABLE |

5987

CURSOR_FORMAT_ARGB;

5987

CURSOR_FORMAT_ARGB;

5988

} else

5988

} else

5989

cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);

5989

cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);

5990

I915_WRITE(_CURACNTR, cntl);

5990

I915_WRITE(_CURACNTR, cntl);

5991

5992

intel_crtc->cursor_visible = visible;

5992

intel_crtc->cursor_visible = visible;

5993

}

5993

}

5994

5995

static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)

5995

static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)

5996

{

5996

{

5997

struct drm_device *dev = crtc->dev;

5997

struct drm_device *dev = crtc->dev;

5998

struct drm_i915_private *dev_priv = dev->dev_private;

5998

struct drm_i915_private *dev_priv = dev->dev_private;

5999

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

5999

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6000

int pipe = intel_crtc->pipe;

6000

int pipe = intel_crtc->pipe;

6001

bool visible = base != 0;

6001

bool visible = base != 0;

6002

6003

if (intel_crtc->cursor_visible != visible) {

6003

if (intel_crtc->cursor_visible != visible) {

6004

uint32_t cntl = I915_READ(CURCNTR(pipe));

6004

uint32_t cntl = I915_READ(CURCNTR(pipe));

6005

if (base) {

6005

if (base) {

6006

cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);

6006

cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);

6007

cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;

6007

cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;

6008

cntl |= pipe << 28; /* Connect to correct pipe */

6008

cntl |= pipe << 28; /* Connect to correct pipe */

6009

} else {

6009

} else {

6010

cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);

6010

cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);

6011

cntl |= CURSOR_MODE_DISABLE;

6011

cntl |= CURSOR_MODE_DISABLE;

6012

}

6012

}

6013

I915_WRITE(CURCNTR(pipe), cntl);

6013

I915_WRITE(CURCNTR(pipe), cntl);

6014

6015

intel_crtc->cursor_visible = visible;

6015

intel_crtc->cursor_visible = visible;

6016

}

6016

}

6017

/* and commit changes on next vblank */

6017

/* and commit changes on next vblank */

6018

I915_WRITE(CURBASE(pipe), base);

6018

I915_WRITE(CURBASE(pipe), base);

6019

}

6019

}

6020

6021

static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)

6021

static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)

6022

{

6022

{

6023

struct drm_device *dev = crtc->dev;

6023

struct drm_device *dev = crtc->dev;

6024

struct drm_i915_private *dev_priv = dev->dev_private;

6024

struct drm_i915_private *dev_priv = dev->dev_private;

6025

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6025

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6026

int pipe = intel_crtc->pipe;

6026

int pipe = intel_crtc->pipe;

6027

bool visible = base != 0;

6027

bool visible = base != 0;

6028

6029

if (intel_crtc->cursor_visible != visible) {

6029

if (intel_crtc->cursor_visible != visible) {

6030

uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));

6030

uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));

6031

if (base) {

6031

if (base) {

6032

cntl &= ~CURSOR_MODE;

6032

cntl &= ~CURSOR_MODE;

6033

cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;

6033

cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;

6034

} else {

6034

} else {

6035

cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);

6035

cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);

6036

cntl |= CURSOR_MODE_DISABLE;

6036

cntl |= CURSOR_MODE_DISABLE;

6037

}

6037

}

6038

I915_WRITE(CURCNTR_IVB(pipe), cntl);

6038

I915_WRITE(CURCNTR_IVB(pipe), cntl);

6039

6040

intel_crtc->cursor_visible = visible;

6040

intel_crtc->cursor_visible = visible;

6041

}

6041

}

6042

/* and commit changes on next vblank */

6042

/* and commit changes on next vblank */

6043

I915_WRITE(CURBASE_IVB(pipe), base);

6043

I915_WRITE(CURBASE_IVB(pipe), base);

6044

}

6044

}

6045

6046

/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */

6046

/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */

6047

static void intel_crtc_update_cursor(struct drm_crtc *crtc,

6047

static void intel_crtc_update_cursor(struct drm_crtc *crtc,

6048

bool on)

6048

bool on)

6049

{

6049

{

6050

struct drm_device *dev = crtc->dev;

6050

struct drm_device *dev = crtc->dev;

6051

struct drm_i915_private *dev_priv = dev->dev_private;

6051

struct drm_i915_private *dev_priv = dev->dev_private;

6052

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6052

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6053

int pipe = intel_crtc->pipe;

6053

int pipe = intel_crtc->pipe;

6054

int x = intel_crtc->cursor_x;

6054

int x = intel_crtc->cursor_x;

6055

int y = intel_crtc->cursor_y;

6055

int y = intel_crtc->cursor_y;

6056

u32 base, pos;

6056

u32 base, pos;

6057

bool visible;

6057

bool visible;

6058

6059

pos = 0;

6059

pos = 0;

6060

6061

if (on && crtc->enabled && crtc->fb) {

6061

if (on && crtc->enabled && crtc->fb) {

6062

base = intel_crtc->cursor_addr;

6062

base = intel_crtc->cursor_addr;

6063

if (x > (int) crtc->fb->width)

6063

if (x > (int) crtc->fb->width)

6064

base = 0;

6064

base = 0;

6065

6066

if (y > (int) crtc->fb->height)

6066

if (y > (int) crtc->fb->height)

6067

base = 0;

6067

base = 0;

6068

} else

6068

} else

6069

base = 0;

6069

base = 0;

6070

6071

if (x < 0) {

6071

if (x < 0) {

6072

if (x + intel_crtc->cursor_width < 0)

6072

if (x + intel_crtc->cursor_width < 0)

6073

base = 0;

6073

base = 0;

6074

6075

pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;

6075

pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;

6076

x = -x;

6076

x = -x;

6077

}

6077

}

6078

pos |= x << CURSOR_X_SHIFT;

6078

pos |= x << CURSOR_X_SHIFT;

6079

6080

if (y < 0) {

6080

if (y < 0) {

6081

if (y + intel_crtc->cursor_height < 0)

6081

if (y + intel_crtc->cursor_height < 0)

6082

base = 0;

6082

base = 0;

6083

6084

pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;

6084

pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;

6085

y = -y;

6085

y = -y;

6086

}

6086

}

6087

pos |= y << CURSOR_Y_SHIFT;

6087

pos |= y << CURSOR_Y_SHIFT;

6088

6089

visible = base != 0;

6089

visible = base != 0;

6090

if (!visible && !intel_crtc->cursor_visible)

6090

if (!visible && !intel_crtc->cursor_visible)

6091

return;

6091

return;

6092

6093

if (IS_IVYBRIDGE(dev)) {

6093

if (IS_IVYBRIDGE(dev)) {

6094

I915_WRITE(CURPOS_IVB(pipe), pos);

6094

I915_WRITE(CURPOS_IVB(pipe), pos);

6095

ivb_update_cursor(crtc, base);

6095

ivb_update_cursor(crtc, base);

6096

} else {

6096

} else {

6097

I915_WRITE(CURPOS(pipe), pos);

6097

I915_WRITE(CURPOS(pipe), pos);

6098

if (IS_845G(dev) || IS_I865G(dev))

6098

if (IS_845G(dev) || IS_I865G(dev))

6099

i845_update_cursor(crtc, base);

6099

i845_update_cursor(crtc, base);

6100

else

6100

else

6101

i9xx_update_cursor(crtc, base);

6101

i9xx_update_cursor(crtc, base);

6102

}

6102

}

6103

6104

if (visible)

6104

if (visible)

6105

intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);

6105

intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);

6106

}

6106

}

6107

6108

static int intel_crtc_cursor_set(struct drm_crtc *crtc,

6108

static int intel_crtc_cursor_set(struct drm_crtc *crtc,

6109

struct drm_file *file,

6109

struct drm_file *file,

6110

uint32_t handle,

6110

uint32_t handle,

6111

uint32_t width, uint32_t height)

6111

uint32_t width, uint32_t height)

6112

{

6112

{

6113

struct drm_device *dev = crtc->dev;

6113

struct drm_device *dev = crtc->dev;

6114

struct drm_i915_private *dev_priv = dev->dev_private;

6114

struct drm_i915_private *dev_priv = dev->dev_private;

6115

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6115

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6116

struct drm_i915_gem_object *obj;

6116

struct drm_i915_gem_object *obj;

6117

uint32_t addr;

6117

uint32_t addr;

6118

int ret;

6118

int ret;

6119

6120

DRM_DEBUG_KMS("\n");

6120

DRM_DEBUG_KMS("\n");

6121

6122

/* if we want to turn off the cursor ignore width and height */

6122

/* if we want to turn off the cursor ignore width and height */

6123

if (!handle) {

6123

if (!handle) {

6124

DRM_DEBUG_KMS("cursor off\n");

6124

DRM_DEBUG_KMS("cursor off\n");

6125

addr = 0;

6125

addr = 0;

6126

obj = NULL;

6126

obj = NULL;

6127

mutex_lock(&dev->struct_mutex);

6127

mutex_lock(&dev->struct_mutex);

6128

goto finish;

6128

goto finish;

6129

}

6129

}

6130

6131

/* Currently we only support 64x64 cursors */

6131

/* Currently we only support 64x64 cursors */

6132

if (width != 64 || height != 64) {

6132

if (width != 64 || height != 64) {

6133

DRM_ERROR("we currently only support 64x64 cursors\n");

6133

DRM_ERROR("we currently only support 64x64 cursors\n");

6134

return -EINVAL;

6134

return -EINVAL;

6135

}

6135

}

6136

6137

obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));

6137

obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));

6138

if (&obj->base == NULL)

6138

if (&obj->base == NULL)

6139

return -ENOENT;

6139

return -ENOENT;

6140

6141

if (obj->base.size < width * height * 4) {

6141

if (obj->base.size < width * height * 4) {

6142

DRM_ERROR("buffer is to small\n");

6142

DRM_ERROR("buffer is to small\n");

6143

ret = -ENOMEM;

6143

ret = -ENOMEM;

6144

goto fail;

6144

goto fail;

6145

}

6145

}

6146

6147

/* we only need to pin inside GTT if cursor is non-phy */

6147

/* we only need to pin inside GTT if cursor is non-phy */

6148

mutex_lock(&dev->struct_mutex);

6148

mutex_lock(&dev->struct_mutex);

6149

if (!dev_priv->info->cursor_needs_physical) {

6149

if (!dev_priv->info->cursor_needs_physical) {

6150

if (obj->tiling_mode) {

6150

if (obj->tiling_mode) {

6151

DRM_ERROR("cursor cannot be tiled\n");

6151

DRM_ERROR("cursor cannot be tiled\n");

6152

ret = -EINVAL;

6152

ret = -EINVAL;

6153

goto fail_locked;

6153

goto fail_locked;

6154

}

6154

}

6155

6156

ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);

6156

ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);

6157

if (ret) {

6157

if (ret) {

6158

DRM_ERROR("failed to move cursor bo into the GTT\n");

6158

DRM_ERROR("failed to move cursor bo into the GTT\n");

6159

goto fail_locked;

6159

goto fail_locked;

6160

}

6160

}

6161

6162

ret = i915_gem_object_put_fence(obj);

6162

ret = i915_gem_object_put_fence(obj);

6163

if (ret) {

6163

if (ret) {

6164

DRM_ERROR("failed to release fence for cursor");

6164

DRM_ERROR("failed to release fence for cursor");

6165

goto fail_unpin;

6165

goto fail_unpin;

6166

}

6166

}

6167

6168

addr = obj->gtt_offset;

6168

addr = obj->gtt_offset;

6169

} else {

6169

} else {

6170

int align = IS_I830(dev) ? 16 * 1024 : 256;

6170

int align = IS_I830(dev) ? 16 * 1024 : 256;

6171

ret = i915_gem_attach_phys_object(dev, obj,

6171

ret = i915_gem_attach_phys_object(dev, obj,

6172

(intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,

6172

(intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,

6173

align);

6173

align);

6174

if (ret) {

6174

if (ret) {

6175

DRM_ERROR("failed to attach phys object\n");

6175

DRM_ERROR("failed to attach phys object\n");

6176

goto fail_locked;

6176

goto fail_locked;

6177

}

6177

}

6178

addr = obj->phys_obj->handle->busaddr;

6178

addr = obj->phys_obj->handle->busaddr;

6179

}

6179

}

6180

6181

if (IS_GEN2(dev))

6181

if (IS_GEN2(dev))

6182

I915_WRITE(CURSIZE, (height << 12) | width);

6182

I915_WRITE(CURSIZE, (height << 12) | width);

6183

6184

finish:

6184

finish:

6185

if (intel_crtc->cursor_bo) {

6185

if (intel_crtc->cursor_bo) {

6186

if (dev_priv->info->cursor_needs_physical) {

6186

if (dev_priv->info->cursor_needs_physical) {

6187

if (intel_crtc->cursor_bo != obj)

6187

if (intel_crtc->cursor_bo != obj)

6188

i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);

6188

i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);

6189

} else

6189

} else

6190

i915_gem_object_unpin(intel_crtc->cursor_bo);

6190

i915_gem_object_unpin(intel_crtc->cursor_bo);

6191

drm_gem_object_unreference(&intel_crtc->cursor_bo->base);

6191

drm_gem_object_unreference(&intel_crtc->cursor_bo->base);

6192

}

6192

}

6193

6194

mutex_unlock(&dev->struct_mutex);

6194

mutex_unlock(&dev->struct_mutex);

6195

6196

intel_crtc->cursor_addr = addr;

6196

intel_crtc->cursor_addr = addr;

6197

intel_crtc->cursor_bo = obj;

6197

intel_crtc->cursor_bo = obj;

6198

intel_crtc->cursor_width = width;

6198

intel_crtc->cursor_width = width;

6199

intel_crtc->cursor_height = height;

6199

intel_crtc->cursor_height = height;

6200

6201

intel_crtc_update_cursor(crtc, true);

6201

intel_crtc_update_cursor(crtc, true);

6202

6203

return 0;

6203

return 0;

6204

fail_unpin:

6204

fail_unpin:

6205

i915_gem_object_unpin(obj);

6205

i915_gem_object_unpin(obj);

6206

fail_locked:

6206

fail_locked:

6207

mutex_unlock(&dev->struct_mutex);

6207

mutex_unlock(&dev->struct_mutex);

6208

fail:

6208

fail:

6209

drm_gem_object_unreference_unlocked(&obj->base);

6209

drm_gem_object_unreference_unlocked(&obj->base);

6210

return ret;

6210

return ret;

6211

}

6211

}

6212

6213

static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)

6213

static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)

6214

{

6214

{

6215

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6215

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6216

6217

intel_crtc->cursor_x = x;

6217

intel_crtc->cursor_x = x;

6218

intel_crtc->cursor_y = y;

6218

intel_crtc->cursor_y = y;

6219

6220

intel_crtc_update_cursor(crtc, true);

6220

intel_crtc_update_cursor(crtc, true);

6221

6222

return 0;

6222

return 0;

6223

}

6223

}

6224

6225

/** Sets the color ramps on behalf of RandR */

6225

/** Sets the color ramps on behalf of RandR */

6226

void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,

6226

void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,

6227

u16 blue, int regno)

6227

u16 blue, int regno)

6228

{

6228

{

6229

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6229

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6230

6231

intel_crtc->lut_r[regno] = red >> 8;

6231

intel_crtc->lut_r[regno] = red >> 8;

6232

intel_crtc->lut_g[regno] = green >> 8;

6232

intel_crtc->lut_g[regno] = green >> 8;

6233

intel_crtc->lut_b[regno] = blue >> 8;

6233

intel_crtc->lut_b[regno] = blue >> 8;

6234

}

6234

}

6235

6236

void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,

6236

void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,

6237

u16 *blue, int regno)

6237

u16 *blue, int regno)

6238

{

6238

{

6239

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6239

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6240

6241

*red = intel_crtc->lut_r[regno] << 8;

6241

*red = intel_crtc->lut_r[regno] << 8;

6242

*green = intel_crtc->lut_g[regno] << 8;

6242

*green = intel_crtc->lut_g[regno] << 8;

6243

*blue = intel_crtc->lut_b[regno] << 8;

6243

*blue = intel_crtc->lut_b[regno] << 8;

6244

}

6244

}

6245

6246

static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,

6246

static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,

6247

u16 *blue, uint32_t start, uint32_t size)

6247

u16 *blue, uint32_t start, uint32_t size)

6248

{

6248

{

6249

int end = (start + size > 256) ? 256 : start + size, i;

6249

int end = (start + size > 256) ? 256 : start + size, i;

6250

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6250

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6251

6252

for (i = start; i < end; i++) {

6252

for (i = start; i < end; i++) {

6253

intel_crtc->lut_r[i] = red[i] >> 8;

6253

intel_crtc->lut_r[i] = red[i] >> 8;

6254

intel_crtc->lut_g[i] = green[i] >> 8;

6254

intel_crtc->lut_g[i] = green[i] >> 8;

6255

intel_crtc->lut_b[i] = blue[i] >> 8;

6255

intel_crtc->lut_b[i] = blue[i] >> 8;

6256

}

6256

}

6257

6258

intel_crtc_load_lut(crtc);

6258

intel_crtc_load_lut(crtc);

6259

}

6259

}

6260

6261

/**

6261

/**

6262

* Get a pipe with a simple mode set on it for doing load-based monitor

6262

* Get a pipe with a simple mode set on it for doing load-based monitor

6263

* detection.

6263

* detection.

6264

*

6264

*

6265

* It will be up to the load-detect code to adjust the pipe as appropriate for

6265

* It will be up to the load-detect code to adjust the pipe as appropriate for

6266

* its requirements. The pipe will be connected to no other encoders.

6266

* its requirements. The pipe will be connected to no other encoders.

6267

*

6267

*

6268

* Currently this code will only succeed if there is a pipe with no encoders

6268

* Currently this code will only succeed if there is a pipe with no encoders

6269

* configured for it. In the future, it could choose to temporarily disable

6269

* configured for it. In the future, it could choose to temporarily disable

6270

* some outputs to free up a pipe for its use.

6270

* some outputs to free up a pipe for its use.

6271

*

6271

*

6272

* \return crtc, or NULL if no pipes are available.

6272

* \return crtc, or NULL if no pipes are available.

6273

*/

6273

*/

6274

6275

/* VESA 640x480x72Hz mode to set on the pipe */

6275

/* VESA 640x480x72Hz mode to set on the pipe */

6276

static struct drm_display_mode load_detect_mode = {

6276

static struct drm_display_mode load_detect_mode = {

6277

DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,

6277

DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,

6278

704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),

6278

704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),

6279

};

6279

};

6280

6281

static struct drm_framebuffer *

6281

static struct drm_framebuffer *

6282

intel_framebuffer_create(struct drm_device *dev,

6282

intel_framebuffer_create(struct drm_device *dev,

6283

struct drm_mode_fb_cmd *mode_cmd,

6283

struct drm_mode_fb_cmd *mode_cmd,

6284

struct drm_i915_gem_object *obj)

6284

struct drm_i915_gem_object *obj)

6285

{

6285

{

6286

struct intel_framebuffer *intel_fb;

6286

struct intel_framebuffer *intel_fb;

6287

int ret;

6287

int ret;

6288

6289

intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);

6289

intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);

6290

if (!intel_fb) {

6290

if (!intel_fb) {

6291

drm_gem_object_unreference_unlocked(&obj->base);

6291

drm_gem_object_unreference_unlocked(&obj->base);

6292

return ERR_PTR(-ENOMEM);

6292

return ERR_PTR(-ENOMEM);

6293

}

6293

}

6294

6295

ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);

6295

ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);

6296

if (ret) {

6296

if (ret) {

6297

drm_gem_object_unreference_unlocked(&obj->base);

6297

drm_gem_object_unreference_unlocked(&obj->base);

6298

kfree(intel_fb);

6298

kfree(intel_fb);

6299

return ERR_PTR(ret);

6299

return ERR_PTR(ret);

6300

}

6300

}

6301

6302

return &intel_fb->base;

6302

return &intel_fb->base;

6303

}

6303

}

6304

6305

static u32

6305

static u32

6306

intel_framebuffer_pitch_for_width(int width, int bpp)

6306

intel_framebuffer_pitch_for_width(int width, int bpp)

6307

{

6307

{

6308

u32 pitch = DIV_ROUND_UP(width * bpp, 8);

6308

u32 pitch = DIV_ROUND_UP(width * bpp, 8);

6309

return ALIGN(pitch, 64);

6309

return ALIGN(pitch, 64);

6310

}

6310

}

6311

6312

static u32

6312

static u32

6313

intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)

6313

intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)

6314

{

6314

{

6315

u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);

6315

u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);

6316

return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);

6316

return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);

6317

}

6317

}

6318

6319

static struct drm_framebuffer *

6319

static struct drm_framebuffer *

6320

intel_framebuffer_create_for_mode(struct drm_device *dev,

6320

intel_framebuffer_create_for_mode(struct drm_device *dev,

6321

struct drm_display_mode *mode,

6321

struct drm_display_mode *mode,

6322

int depth, int bpp)

6322

int depth, int bpp)

6323

{

6323

{

6324

struct drm_i915_gem_object *obj;

6324

struct drm_i915_gem_object *obj;

6325

struct drm_mode_fb_cmd mode_cmd;

6325

struct drm_mode_fb_cmd mode_cmd;

6326

6327

obj = i915_gem_alloc_object(dev,

6327

obj = i915_gem_alloc_object(dev,

6328

intel_framebuffer_size_for_mode(mode, bpp));

6328

intel_framebuffer_size_for_mode(mode, bpp));

6329

if (obj == NULL)

6329

if (obj == NULL)

6330

return ERR_PTR(-ENOMEM);

6330

return ERR_PTR(-ENOMEM);

6331

6332

mode_cmd.width = mode->hdisplay;

6332

mode_cmd.width = mode->hdisplay;

6333

mode_cmd.height = mode->vdisplay;

6333

mode_cmd.height = mode->vdisplay;

6334

mode_cmd.depth = depth;

6334

mode_cmd.depth = depth;

6335

mode_cmd.bpp = bpp;

6335

mode_cmd.bpp = bpp;

6336

mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);

6336

mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);

6337

6338

return intel_framebuffer_create(dev, &mode_cmd, obj);

6338

return intel_framebuffer_create(dev, &mode_cmd, obj);

6339

}

6339

}

6340

6341

static struct drm_framebuffer *

6341

static struct drm_framebuffer *

6342

mode_fits_in_fbdev(struct drm_device *dev,

6342

mode_fits_in_fbdev(struct drm_device *dev,

6343

struct drm_display_mode *mode)

6343

struct drm_display_mode *mode)

6344

{

6344

{

6345

struct drm_i915_private *dev_priv = dev->dev_private;

6345

struct drm_i915_private *dev_priv = dev->dev_private;

6346

struct drm_i915_gem_object *obj;

6346

struct drm_i915_gem_object *obj;

6347

struct drm_framebuffer *fb;

6347

struct drm_framebuffer *fb;

6348

6349

if (dev_priv->fbdev == NULL)

6349

if (dev_priv->fbdev == NULL)

6350

return NULL;

6350

return NULL;

6351

6352

obj = dev_priv->fbdev->ifb.obj;

6352

obj = dev_priv->fbdev->ifb.obj;

6353

if (obj == NULL)

6353

if (obj == NULL)

6354

return NULL;

6354

return NULL;

6355

6356

fb = &dev_priv->fbdev->ifb.base;

6356

fb = &dev_priv->fbdev->ifb.base;

6357

if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,

6357

if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,

6358

fb->bits_per_pixel))

6358

fb->bits_per_pixel))

6359

return NULL;

6359

return NULL;

6360

6361

if (obj->base.size < mode->vdisplay * fb->pitch)

6361

if (obj->base.size < mode->vdisplay * fb->pitch)

6362

return NULL;

6362

return NULL;

6363

6364

return fb;

6364

return fb;

6365

}

6365

}

6366

6367

bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,

6367

bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,

6368

struct drm_connector *connector,

6368

struct drm_connector *connector,

6369

struct drm_display_mode *mode,

6369

struct drm_display_mode *mode,

6370

struct intel_load_detect_pipe *old)

6370

struct intel_load_detect_pipe *old)

6371

{

6371

{

6372

struct intel_crtc *intel_crtc;

6372

struct intel_crtc *intel_crtc;

6373

struct drm_crtc *possible_crtc;

6373

struct drm_crtc *possible_crtc;

6374

struct drm_encoder *encoder = &intel_encoder->base;

6374

struct drm_encoder *encoder = &intel_encoder->base;

6375

struct drm_crtc *crtc = NULL;

6375

struct drm_crtc *crtc = NULL;

6376

struct drm_device *dev = encoder->dev;

6376

struct drm_device *dev = encoder->dev;

6377

struct drm_framebuffer *old_fb;

6377

struct drm_framebuffer *old_fb;

6378

int i = -1;

6378

int i = -1;

6379

6380

DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",

6380

DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",

6381

connector->base.id, drm_get_connector_name(connector),

6381

connector->base.id, drm_get_connector_name(connector),

6382

encoder->base.id, drm_get_encoder_name(encoder));

6382

encoder->base.id, drm_get_encoder_name(encoder));

6383

6384

/*

6384

/*

6385

* Algorithm gets a little messy:

6385

* Algorithm gets a little messy:

6386

*

6386

*

6387

* - if the connector already has an assigned crtc, use it (but make

6387

* - if the connector already has an assigned crtc, use it (but make

6388

* sure it's on first)

6388

* sure it's on first)

6389

*

6389

*

6390

* - try to find the first unused crtc that can drive this connector,

6390

* - try to find the first unused crtc that can drive this connector,

6391

* and use that if we find one

6391

* and use that if we find one

6392

*/

6392

*/

6393

6394

/* See if we already have a CRTC for this connector */

6394

/* See if we already have a CRTC for this connector */

6395

if (encoder->crtc) {

6395

if (encoder->crtc) {

6396

crtc = encoder->crtc;

6396

crtc = encoder->crtc;

6397

6398

intel_crtc = to_intel_crtc(crtc);

6398

intel_crtc = to_intel_crtc(crtc);

6399

old->dpms_mode = intel_crtc->dpms_mode;

6399

old->dpms_mode = intel_crtc->dpms_mode;

6400

old->load_detect_temp = false;

6400

old->load_detect_temp = false;

6401

6402

/* Make sure the crtc and connector are running */

6402

/* Make sure the crtc and connector are running */

6403

if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {

6403

if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {

6404

struct drm_encoder_helper_funcs *encoder_funcs;

6404

struct drm_encoder_helper_funcs *encoder_funcs;

6405

struct drm_crtc_helper_funcs *crtc_funcs;

6405

struct drm_crtc_helper_funcs *crtc_funcs;

6406

6407

crtc_funcs = crtc->helper_private;

6407

crtc_funcs = crtc->helper_private;

6408

crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);

6408

crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);

6409

6410

encoder_funcs = encoder->helper_private;

6410

encoder_funcs = encoder->helper_private;

6411

encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);

6411

encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);

6412

}

6412

}

6413

6414

return true;

6414

return true;

6415

}

6415

}

6416

6417

/* Find an unused one (if possible) */

6417

/* Find an unused one (if possible) */

6418

list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {

6418

list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {

6419

i++;

6419

i++;

6420

if (!(encoder->possible_crtcs & (1 << i)))

6420

if (!(encoder->possible_crtcs & (1 << i)))

6421

continue;

6421

continue;

6422

if (!possible_crtc->enabled) {

6422

if (!possible_crtc->enabled) {

6423

crtc = possible_crtc;

6423

crtc = possible_crtc;

6424

break;

6424

break;

6425

}

6425

}

6426

}

6426

}

6427

6428

/*

6428

/*

6429

* If we didn't find an unused CRTC, don't use any.

6429

* If we didn't find an unused CRTC, don't use any.

6430

*/

6430

*/

6431

if (!crtc) {

6431

if (!crtc) {

6432

DRM_DEBUG_KMS("no pipe available for load-detect\n");

6432

DRM_DEBUG_KMS("no pipe available for load-detect\n");

6433

return false;

6433

return false;

6434

}

6434

}

6435

6436

encoder->crtc = crtc;

6436

encoder->crtc = crtc;

6437

connector->encoder = encoder;

6437

connector->encoder = encoder;

6438

6439

intel_crtc = to_intel_crtc(crtc);

6439

intel_crtc = to_intel_crtc(crtc);

6440

old->dpms_mode = intel_crtc->dpms_mode;

6440

old->dpms_mode = intel_crtc->dpms_mode;

6441

old->load_detect_temp = true;

6441

old->load_detect_temp = true;

6442

old->release_fb = NULL;

6442

old->release_fb = NULL;

6443

6444

if (!mode)

6444

if (!mode)

6445

mode = &load_detect_mode;

6445

mode = &load_detect_mode;

6446

6447

old_fb = crtc->fb;

6447

old_fb = crtc->fb;

6448

6449

/* We need a framebuffer large enough to accommodate all accesses

6449

/* We need a framebuffer large enough to accommodate all accesses

6450

* that the plane may generate whilst we perform load detection.

6450

* that the plane may generate whilst we perform load detection.

6451

* We can not rely on the fbcon either being present (we get called

6451

* We can not rely on the fbcon either being present (we get called

6452

* during its initialisation to detect all boot displays, or it may

6452

* during its initialisation to detect all boot displays, or it may

6453

* not even exist) or that it is large enough to satisfy the

6453

* not even exist) or that it is large enough to satisfy the

6454

* requested mode.

6454

* requested mode.

6455

*/

6455

*/

6456

crtc->fb = mode_fits_in_fbdev(dev, mode);

6456

crtc->fb = mode_fits_in_fbdev(dev, mode);

6457

if (crtc->fb == NULL) {

6457

if (crtc->fb == NULL) {

6458

DRM_DEBUG_KMS("creating tmp fb for load-detection\n");

6458

DRM_DEBUG_KMS("creating tmp fb for load-detection\n");

6459

crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);

6459

crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);

6460

old->release_fb = crtc->fb;

6460

old->release_fb = crtc->fb;

6461

} else

6461

} else

6462

DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");

6462

DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");

6463

if (IS_ERR(crtc->fb)) {

6463

if (IS_ERR(crtc->fb)) {

6464

DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");

6464

DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");

6465

crtc->fb = old_fb;

6465

crtc->fb = old_fb;

6466

return false;

6466

return false;

6467

}

6467

}

6468

6469

if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {

6469

if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {

6470

DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");

6470

DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");

6471

if (old->release_fb)

6471

if (old->release_fb)

6472

old->release_fb->funcs->destroy(old->release_fb);

6472

old->release_fb->funcs->destroy(old->release_fb);

6473

crtc->fb = old_fb;

6473

crtc->fb = old_fb;

6474

return false;

6474

return false;

6475

}

6475

}

6476

6477

/* let the connector get through one full cycle before testing */

6477

/* let the connector get through one full cycle before testing */

6478

intel_wait_for_vblank(dev, intel_crtc->pipe);

6478

intel_wait_for_vblank(dev, intel_crtc->pipe);

6479

6480

return true;

6480

return true;

6481

}

6481

}

6482

6483

void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,

6483

void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,

6484

struct drm_connector *connector,

6484

struct drm_connector *connector,

6485

struct intel_load_detect_pipe *old)

6485

struct intel_load_detect_pipe *old)

6486

{

6486

{

6487

struct drm_encoder *encoder = &intel_encoder->base;

6487

struct drm_encoder *encoder = &intel_encoder->base;

6488

struct drm_device *dev = encoder->dev;

6488

struct drm_device *dev = encoder->dev;

6489

struct drm_crtc *crtc = encoder->crtc;

6489

struct drm_crtc *crtc = encoder->crtc;

6490

struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;

6490

struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;

6491

struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;

6491

struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;

6492

6493

DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",

6493

DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",

6494

connector->base.id, drm_get_connector_name(connector),

6494

connector->base.id, drm_get_connector_name(connector),

6495

encoder->base.id, drm_get_encoder_name(encoder));

6495

encoder->base.id, drm_get_encoder_name(encoder));

6496

6497

if (old->load_detect_temp) {

6497

if (old->load_detect_temp) {

6498

connector->encoder = NULL;

6498

connector->encoder = NULL;

6499

drm_helper_disable_unused_functions(dev);

6499

drm_helper_disable_unused_functions(dev);

6500

6501

if (old->release_fb)

6501

if (old->release_fb)

6502

old->release_fb->funcs->destroy(old->release_fb);

6502

old->release_fb->funcs->destroy(old->release_fb);

6503

6504

return;

6504

return;

6505

}

6505

}

6506

6507

/* Switch crtc and encoder back off if necessary */

6507

/* Switch crtc and encoder back off if necessary */

6508

if (old->dpms_mode != DRM_MODE_DPMS_ON) {

6508

if (old->dpms_mode != DRM_MODE_DPMS_ON) {

6509

encoder_funcs->dpms(encoder, old->dpms_mode);

6509

encoder_funcs->dpms(encoder, old->dpms_mode);

6510

crtc_funcs->dpms(crtc, old->dpms_mode);

6510

crtc_funcs->dpms(crtc, old->dpms_mode);

6511

}

6511

}

6512

}

6512

}

6513

6514

/* Returns the clock of the currently programmed mode of the given pipe. */

6514

/* Returns the clock of the currently programmed mode of the given pipe. */

6515

static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)

6515

static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)

6516

{

6516

{

6517

struct drm_i915_private *dev_priv = dev->dev_private;

6517

struct drm_i915_private *dev_priv = dev->dev_private;

6518

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6518

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6519

int pipe = intel_crtc->pipe;

6519

int pipe = intel_crtc->pipe;

6520

u32 dpll = I915_READ(DPLL(pipe));

6520

u32 dpll = I915_READ(DPLL(pipe));

6521

u32 fp;

6521

u32 fp;

6522

intel_clock_t clock;

6522

intel_clock_t clock;

6523

6524

if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)

6524

if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)

6525

fp = I915_READ(FP0(pipe));

6525

fp = I915_READ(FP0(pipe));

6526

else

6526

else

6527

fp = I915_READ(FP1(pipe));

6527

fp = I915_READ(FP1(pipe));

6528

6529

clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;

6529

clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;

6530

if (IS_PINEVIEW(dev)) {

6530

if (IS_PINEVIEW(dev)) {

6531

clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;

6531

clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;

6532

clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;

6532

clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;

6533

} else {

6533

} else {

6534

clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;

6534

clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;

6535

clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;

6535

clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;

6536

}

6536

}

6537

6538

if (!IS_GEN2(dev)) {

6538

if (!IS_GEN2(dev)) {

6539

if (IS_PINEVIEW(dev))

6539

if (IS_PINEVIEW(dev))

6540

clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>

6540

clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>

6541

DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);

6541

DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);

6542

else

6542

else

6543

clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>

6543

clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>

6544

DPLL_FPA01_P1_POST_DIV_SHIFT);

6544

DPLL_FPA01_P1_POST_DIV_SHIFT);

6545

6546

switch (dpll & DPLL_MODE_MASK) {

6546

switch (dpll & DPLL_MODE_MASK) {

6547

case DPLLB_MODE_DAC_SERIAL:

6547

case DPLLB_MODE_DAC_SERIAL:

6548

clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?

6548

clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?

6549

5 : 10;

6549

5 : 10;

6550

break;

6550

break;

6551

case DPLLB_MODE_LVDS:

6551

case DPLLB_MODE_LVDS:

6552

clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?

6552

clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?

6553

7 : 14;

6553

7 : 14;

6554

break;

6554

break;

6555

default:

6555

default:

6556

DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "

6556

DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "

6557

"mode\n", (int)(dpll & DPLL_MODE_MASK));

6557

"mode\n", (int)(dpll & DPLL_MODE_MASK));

6558

return 0;

6558

return 0;

6559

}

6559

}

6560

6561

/* XXX: Handle the 100Mhz refclk */

6561

/* XXX: Handle the 100Mhz refclk */

6562

intel_clock(dev, 96000, &clock);

6562

intel_clock(dev, 96000, &clock);

6563

} else {

6563

} else {

6564

bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);

6564

bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);

6565

6566

if (is_lvds) {

6566

if (is_lvds) {

6567

clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>

6567

clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>

6568

DPLL_FPA01_P1_POST_DIV_SHIFT);

6568

DPLL_FPA01_P1_POST_DIV_SHIFT);

6569

clock.p2 = 14;

6569

clock.p2 = 14;

6570

6571

if ((dpll & PLL_REF_INPUT_MASK) ==

6571

if ((dpll & PLL_REF_INPUT_MASK) ==

6572

PLLB_REF_INPUT_SPREADSPECTRUMIN) {

6572

PLLB_REF_INPUT_SPREADSPECTRUMIN) {

6573

/* XXX: might not be 66MHz */

6573

/* XXX: might not be 66MHz */

6574

intel_clock(dev, 66000, &clock);

6574

intel_clock(dev, 66000, &clock);

6575

} else

6575

} else

6576

intel_clock(dev, 48000, &clock);

6576

intel_clock(dev, 48000, &clock);

6577

} else {

6577

} else {

6578

if (dpll & PLL_P1_DIVIDE_BY_TWO)

6578

if (dpll & PLL_P1_DIVIDE_BY_TWO)

6579

clock.p1 = 2;

6579

clock.p1 = 2;

6580

else {

6580

else {

6581

clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>

6581

clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>

6582

DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;

6582

DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;

6583

}

6583

}

6584

if (dpll & PLL_P2_DIVIDE_BY_4)

6584

if (dpll & PLL_P2_DIVIDE_BY_4)

6585

clock.p2 = 4;

6585

clock.p2 = 4;

6586

else

6586

else

6587

clock.p2 = 2;

6587

clock.p2 = 2;

6588

6589

intel_clock(dev, 48000, &clock);

6589

intel_clock(dev, 48000, &clock);

6590

}

6590

}

6591

}

6591

}

6592

6593

/* XXX: It would be nice to validate the clocks, but we can't reuse

6593

/* XXX: It would be nice to validate the clocks, but we can't reuse

6594

* i830PllIsValid() because it relies on the xf86_config connector

6594

* i830PllIsValid() because it relies on the xf86_config connector

6595

* configuration being accurate, which it isn't necessarily.

6595

* configuration being accurate, which it isn't necessarily.

6596

*/

6596

*/

6597

6598

return clock.dot;

6598

return clock.dot;

6599

}

6599

}

6600

6601

/** Returns the currently programmed mode of the given pipe. */

6601

/** Returns the currently programmed mode of the given pipe. */

6602

struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,

6602

struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,

6603

struct drm_crtc *crtc)

6603

struct drm_crtc *crtc)

6604

{

6604

{

6605

struct drm_i915_private *dev_priv = dev->dev_private;

6605

struct drm_i915_private *dev_priv = dev->dev_private;

6606

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6606

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6607

int pipe = intel_crtc->pipe;

6607

int pipe = intel_crtc->pipe;

6608

struct drm_display_mode *mode;

6608

struct drm_display_mode *mode;

6609

int htot = I915_READ(HTOTAL(pipe));

6609

int htot = I915_READ(HTOTAL(pipe));

6610

int hsync = I915_READ(HSYNC(pipe));

6610

int hsync = I915_READ(HSYNC(pipe));

6611

int vtot = I915_READ(VTOTAL(pipe));

6611

int vtot = I915_READ(VTOTAL(pipe));

6612

int vsync = I915_READ(VSYNC(pipe));

6612

int vsync = I915_READ(VSYNC(pipe));

6613

6614

mode = kzalloc(sizeof(*mode), GFP_KERNEL);

6614

mode = kzalloc(sizeof(*mode), GFP_KERNEL);

6615

if (!mode)

6615

if (!mode)

6616

return NULL;

6616

return NULL;

6617

6618

mode->clock = intel_crtc_clock_get(dev, crtc);

6618

mode->clock = intel_crtc_clock_get(dev, crtc);

6619

mode->hdisplay = (htot & 0xffff) + 1;

6619

mode->hdisplay = (htot & 0xffff) + 1;

6620

mode->htotal = ((htot & 0xffff0000) >> 16) + 1;

6620

mode->htotal = ((htot & 0xffff0000) >> 16) + 1;

6621

mode->hsync_start = (hsync & 0xffff) + 1;

6621

mode->hsync_start = (hsync & 0xffff) + 1;

6622

mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;

6622

mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;

6623

mode->vdisplay = (vtot & 0xffff) + 1;

6623

mode->vdisplay = (vtot & 0xffff) + 1;

6624

mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;

6624

mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;

6625

mode->vsync_start = (vsync & 0xffff) + 1;

6625

mode->vsync_start = (vsync & 0xffff) + 1;

6626

mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;

6626

mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;

6627

6628

drm_mode_set_name(mode);

6628

drm_mode_set_name(mode);

6629

drm_mode_set_crtcinfo(mode, 0);

6629

drm_mode_set_crtcinfo(mode, 0);

6630

6631

return mode;

6631

return mode;

6632

}

6632

}

6633

6634

#define GPU_IDLE_TIMEOUT 500 /* ms */

6634

#define GPU_IDLE_TIMEOUT 500 /* ms */

6635

6636

/* When this timer fires, we've been idle for awhile */

6636

/* When this timer fires, we've been idle for awhile */

6637

static void intel_gpu_idle_timer(unsigned long arg)

6637

static void intel_gpu_idle_timer(unsigned long arg)

6638

{

6638

{

6639

struct drm_device *dev = (struct drm_device *)arg;

6639

struct drm_device *dev = (struct drm_device *)arg;

6640

drm_i915_private_t *dev_priv = dev->dev_private;

6640

drm_i915_private_t *dev_priv = dev->dev_private;

6641

6642

if (!list_empty(&dev_priv->mm.active_list)) {

6642

if (!list_empty(&dev_priv->mm.active_list)) {

6643

/* Still processing requests, so just re-arm the timer. */

6643

/* Still processing requests, so just re-arm the timer. */

6644

mod_timer(&dev_priv->idle_timer, jiffies +

6644

mod_timer(&dev_priv->idle_timer, jiffies +

6645

msecs_to_jiffies(GPU_IDLE_TIMEOUT));

6645

msecs_to_jiffies(GPU_IDLE_TIMEOUT));

6646

return;

6646

return;

6647

}

6647

}

6648

6649

dev_priv->busy = false;

6649

dev_priv->busy = false;

6650

queue_work(dev_priv->wq, &dev_priv->idle_work);

6650

queue_work(dev_priv->wq, &dev_priv->idle_work);

6651

}

6651

}

6652

6653

#define CRTC_IDLE_TIMEOUT 1000 /* ms */

6653

#define CRTC_IDLE_TIMEOUT 1000 /* ms */

6654

6655

static void intel_crtc_idle_timer(unsigned long arg)

6655

static void intel_crtc_idle_timer(unsigned long arg)

6656

{

6656

{

6657

struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;

6657

struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;

6658

struct drm_crtc *crtc = &intel_crtc->base;

6658

struct drm_crtc *crtc = &intel_crtc->base;

6659

drm_i915_private_t *dev_priv = crtc->dev->dev_private;

6659

drm_i915_private_t *dev_priv = crtc->dev->dev_private;

6660

struct intel_framebuffer *intel_fb;

6660

struct intel_framebuffer *intel_fb;

6661

6662

intel_fb = to_intel_framebuffer(crtc->fb);

6662

intel_fb = to_intel_framebuffer(crtc->fb);

6663

if (intel_fb && intel_fb->obj->active) {

6663

if (intel_fb && intel_fb->obj->active) {

6664

/* The framebuffer is still being accessed by the GPU. */

6664

/* The framebuffer is still being accessed by the GPU. */

6665

mod_timer(&intel_crtc->idle_timer, jiffies +

6665

mod_timer(&intel_crtc->idle_timer, jiffies +

6666

msecs_to_jiffies(CRTC_IDLE_TIMEOUT));

6666

msecs_to_jiffies(CRTC_IDLE_TIMEOUT));

6667

return;

6667

return;

6668

}

6668

}

6669

6670

intel_crtc->busy = false;

6670

intel_crtc->busy = false;

6671

queue_work(dev_priv->wq, &dev_priv->idle_work);

6671

queue_work(dev_priv->wq, &dev_priv->idle_work);

6672

}

6672

}

6673

6674

static void intel_increase_pllclock(struct drm_crtc *crtc)

6674

static void intel_increase_pllclock(struct drm_crtc *crtc)

6675

{

6675

{

6676

struct drm_device *dev = crtc->dev;

6676

struct drm_device *dev = crtc->dev;

6677

drm_i915_private_t *dev_priv = dev->dev_private;

6677

drm_i915_private_t *dev_priv = dev->dev_private;

6678

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6678

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6679

int pipe = intel_crtc->pipe;

6679

int pipe = intel_crtc->pipe;

6680

int dpll_reg = DPLL(pipe);

6680

int dpll_reg = DPLL(pipe);

6681

int dpll;

6681

int dpll;

6682

6683

if (HAS_PCH_SPLIT(dev))

6683

if (HAS_PCH_SPLIT(dev))

6684

return;

6684

return;

6685

6686

if (!dev_priv->lvds_downclock_avail)

6686

if (!dev_priv->lvds_downclock_avail)

6687

return;

6687

return;

6688

6689

dpll = I915_READ(dpll_reg);

6689

dpll = I915_READ(dpll_reg);

6690

if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {

6690

if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {

6691

DRM_DEBUG_DRIVER("upclocking LVDS\n");

6691

DRM_DEBUG_DRIVER("upclocking LVDS\n");

6692

6693

/* Unlock panel regs */

6693

/* Unlock panel regs */

6694

I915_WRITE(PP_CONTROL,

6694

I915_WRITE(PP_CONTROL,

6695

I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);

6695

I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);

6696

6697

dpll &= ~DISPLAY_RATE_SELECT_FPA1;

6697

dpll &= ~DISPLAY_RATE_SELECT_FPA1;

6698

I915_WRITE(dpll_reg, dpll);

6698

I915_WRITE(dpll_reg, dpll);

6699

intel_wait_for_vblank(dev, pipe);

6699

intel_wait_for_vblank(dev, pipe);

6700

6701

dpll = I915_READ(dpll_reg);

6701

dpll = I915_READ(dpll_reg);

6702

if (dpll & DISPLAY_RATE_SELECT_FPA1)

6702

if (dpll & DISPLAY_RATE_SELECT_FPA1)

6703

DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");

6703

DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");

6704

6705

/* ...and lock them again */

6705

/* ...and lock them again */

6706

I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);

6706

I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);

6707

}

6707

}

6708

6709

/* Schedule downclock */

6709

/* Schedule downclock */

6710

mod_timer(&intel_crtc->idle_timer, jiffies +

6710

mod_timer(&intel_crtc->idle_timer, jiffies +

6711

msecs_to_jiffies(CRTC_IDLE_TIMEOUT));

6711

msecs_to_jiffies(CRTC_IDLE_TIMEOUT));

6712

}

6712

}

6713

6714

static void intel_decrease_pllclock(struct drm_crtc *crtc)

6714

static void intel_decrease_pllclock(struct drm_crtc *crtc)

6715

{

6715

{

6716

struct drm_device *dev = crtc->dev;

6716

struct drm_device *dev = crtc->dev;

6717

drm_i915_private_t *dev_priv = dev->dev_private;

6717

drm_i915_private_t *dev_priv = dev->dev_private;

6718

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6718

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6719

int pipe = intel_crtc->pipe;

6719

int pipe = intel_crtc->pipe;

6720

int dpll_reg = DPLL(pipe);

6720

int dpll_reg = DPLL(pipe);

6721

int dpll = I915_READ(dpll_reg);

6721

int dpll = I915_READ(dpll_reg);

6722

6723

if (HAS_PCH_SPLIT(dev))

6723

if (HAS_PCH_SPLIT(dev))

6724

return;

6724

return;

6725

6726

if (!dev_priv->lvds_downclock_avail)

6726

if (!dev_priv->lvds_downclock_avail)

6727

return;

6727

return;

6728

6729

/*

6729

/*

6730

* Since this is called by a timer, we should never get here in

6730

* Since this is called by a timer, we should never get here in

6731

* the manual case.

6731

* the manual case.

6732

*/

6732

*/

6733

if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {

6733

if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {

6734

DRM_DEBUG_DRIVER("downclocking LVDS\n");

6734

DRM_DEBUG_DRIVER("downclocking LVDS\n");

6735

6736

/* Unlock panel regs */

6736

/* Unlock panel regs */

6737

I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |

6737

I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |

6738

PANEL_UNLOCK_REGS);

6738

PANEL_UNLOCK_REGS);

6739

6740

dpll |= DISPLAY_RATE_SELECT_FPA1;

6740

dpll |= DISPLAY_RATE_SELECT_FPA1;

6741

I915_WRITE(dpll_reg, dpll);

6741

I915_WRITE(dpll_reg, dpll);

6742

intel_wait_for_vblank(dev, pipe);

6742

intel_wait_for_vblank(dev, pipe);

6743

dpll = I915_READ(dpll_reg);

6743

dpll = I915_READ(dpll_reg);

6744

if (!(dpll & DISPLAY_RATE_SELECT_FPA1))

6744

if (!(dpll & DISPLAY_RATE_SELECT_FPA1))

6745

DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");

6745

DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");

6746

6747

/* ...and lock them again */

6747

/* ...and lock them again */

6748

I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);

6748

I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);

6749

}

6749

}

6750

6751

}

6751

}

6752

6753

/**

6753

/**

6754

* intel_idle_update - adjust clocks for idleness

6754

* intel_idle_update - adjust clocks for idleness

6755

* @work: work struct

6755

* @work: work struct

6756

*

6756

*

6757

* Either the GPU or display (or both) went idle. Check the busy status

6757

* Either the GPU or display (or both) went idle. Check the busy status

6758

* here and adjust the CRTC and GPU clocks as necessary.

6758

* here and adjust the CRTC and GPU clocks as necessary.

6759

*/

6759

*/

6760

static void intel_idle_update(struct work_struct *work)

6760

static void intel_idle_update(struct work_struct *work)

6761

{

6761

{

6762

drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,

6762

drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,

6763

idle_work);

6763

idle_work);

6764

struct drm_device *dev = dev_priv->dev;

6764

struct drm_device *dev = dev_priv->dev;

6765

struct drm_crtc *crtc;

6765

struct drm_crtc *crtc;

6766

struct intel_crtc *intel_crtc;

6766

struct intel_crtc *intel_crtc;

6767

6768

if (!i915_powersave)

6768

if (!i915_powersave)

6769

return;

6769

return;

6770

6771

mutex_lock(&dev->struct_mutex);

6771

mutex_lock(&dev->struct_mutex);

6772

6773

i915_update_gfx_val(dev_priv);

6773

i915_update_gfx_val(dev_priv);

6774

6775

list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {

6775

list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {

6776

/* Skip inactive CRTCs */

6776

/* Skip inactive CRTCs */

6777

if (!crtc->fb)

6777

if (!crtc->fb)

6778

continue;

6778

continue;

6779

6780

intel_crtc = to_intel_crtc(crtc);

6780

intel_crtc = to_intel_crtc(crtc);

6781

if (!intel_crtc->busy)

6781

if (!intel_crtc->busy)

6782

intel_decrease_pllclock(crtc);

6782

intel_decrease_pllclock(crtc);

6783

}

6783

}

6784

6785

6786

mutex_unlock(&dev->struct_mutex);

6786

mutex_unlock(&dev->struct_mutex);

6787

}

6787

}

6788

6789

/**

6789

/**

6790

* intel_mark_busy - mark the GPU and possibly the display busy

6790

* intel_mark_busy - mark the GPU and possibly the display busy

6791

* @dev: drm device

6791

* @dev: drm device

6792

* @obj: object we're operating on

6792

* @obj: object we're operating on

6793

*

6793

*

6794

* Callers can use this function to indicate that the GPU is busy processing

6794

* Callers can use this function to indicate that the GPU is busy processing

6795

* commands. If @obj matches one of the CRTC objects (i.e. it's a scanout

6795

* commands. If @obj matches one of the CRTC objects (i.e. it's a scanout

6796

* buffer), we'll also mark the display as busy, so we know to increase its

6796

* buffer), we'll also mark the display as busy, so we know to increase its

6797

* clock frequency.

6797

* clock frequency.

6798

*/

6798

*/

6799

void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)

6799

void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)

6800

{

6800

{

6801

drm_i915_private_t *dev_priv = dev->dev_private;

6801

drm_i915_private_t *dev_priv = dev->dev_private;

6802

struct drm_crtc *crtc = NULL;

6802

struct drm_crtc *crtc = NULL;

6803

struct intel_framebuffer *intel_fb;

6803

struct intel_framebuffer *intel_fb;

6804

struct intel_crtc *intel_crtc;

6804

struct intel_crtc *intel_crtc;

6805

6806

if (!drm_core_check_feature(dev, DRIVER_MODESET))

6806

if (!drm_core_check_feature(dev, DRIVER_MODESET))

6807

return;

6807

return;

6808

6809

if (!dev_priv->busy)

6809

if (!dev_priv->busy)

6810

dev_priv->busy = true;

6810

dev_priv->busy = true;

6811

else

6811

else

6812

mod_timer(&dev_priv->idle_timer, jiffies +

6812

mod_timer(&dev_priv->idle_timer, jiffies +

6813

msecs_to_jiffies(GPU_IDLE_TIMEOUT));

6813

msecs_to_jiffies(GPU_IDLE_TIMEOUT));

6814

6815

list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {

6815

list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {

6816

if (!crtc->fb)

6816

if (!crtc->fb)

6817

continue;

6817

continue;

6818

6819

intel_crtc = to_intel_crtc(crtc);

6819

intel_crtc = to_intel_crtc(crtc);

6820

intel_fb = to_intel_framebuffer(crtc->fb);

6820

intel_fb = to_intel_framebuffer(crtc->fb);

6821

if (intel_fb->obj == obj) {

6821

if (intel_fb->obj == obj) {

6822

if (!intel_crtc->busy) {

6822

if (!intel_crtc->busy) {

6823

/* Non-busy -> busy, upclock */

6823

/* Non-busy -> busy, upclock */

6824

intel_increase_pllclock(crtc);

6824

intel_increase_pllclock(crtc);

6825

intel_crtc->busy = true;

6825

intel_crtc->busy = true;

6826

} else {

6826

} else {

6827

/* Busy -> busy, put off timer */

6827

/* Busy -> busy, put off timer */

6828

mod_timer(&intel_crtc->idle_timer, jiffies +

6828

mod_timer(&intel_crtc->idle_timer, jiffies +

6829

msecs_to_jiffies(CRTC_IDLE_TIMEOUT));

6829

msecs_to_jiffies(CRTC_IDLE_TIMEOUT));

6830

}

6830

}

6831

}

6831

}

6832

}

6832

}

6833

}

6833

}

6834

6835

static void intel_crtc_destroy(struct drm_crtc *crtc)

6835

static void intel_crtc_destroy(struct drm_crtc *crtc)

6836

{

6836

{

6837

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6837

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6838

struct drm_device *dev = crtc->dev;

6838

struct drm_device *dev = crtc->dev;

6839

struct intel_unpin_work *work;

6839

struct intel_unpin_work *work;

6840

unsigned long flags;

6840

unsigned long flags;

6841

6842

spin_lock_irqsave(&dev->event_lock, flags);

6842

spin_lock_irqsave(&dev->event_lock, flags);

6843

work = intel_crtc->unpin_work;

6843

work = intel_crtc->unpin_work;

6844

intel_crtc->unpin_work = NULL;

6844

intel_crtc->unpin_work = NULL;

6845

spin_unlock_irqrestore(&dev->event_lock, flags);

6845

spin_unlock_irqrestore(&dev->event_lock, flags);

6846

6847

if (work) {

6847

if (work) {

6848

cancel_work_sync(&work->work);

6848

cancel_work_sync(&work->work);

6849

kfree(work);

6849

kfree(work);

6850

}

6850

}

6851

6852

drm_crtc_cleanup(crtc);

6852

drm_crtc_cleanup(crtc);

6853

6854

kfree(intel_crtc);

6854

kfree(intel_crtc);

6855

}

6855

}

6856

6857

static void intel_unpin_work_fn(struct work_struct *__work)

6857

static void intel_unpin_work_fn(struct work_struct *__work)

6858

{

6858

{

6859

struct intel_unpin_work *work =

6859

struct intel_unpin_work *work =

6860

container_of(__work, struct intel_unpin_work, work);

6860

container_of(__work, struct intel_unpin_work, work);

6861

6862

mutex_lock(&work->dev->struct_mutex);

6862

mutex_lock(&work->dev->struct_mutex);

6863

i915_gem_object_unpin(work->old_fb_obj);

6863

i915_gem_object_unpin(work->old_fb_obj);

6864

drm_gem_object_unreference(&work->pending_flip_obj->base);

6864

drm_gem_object_unreference(&work->pending_flip_obj->base);

6865

drm_gem_object_unreference(&work->old_fb_obj->base);

6865

drm_gem_object_unreference(&work->old_fb_obj->base);

6866

6867

intel_update_fbc(work->dev);

6867

intel_update_fbc(work->dev);

6868

mutex_unlock(&work->dev->struct_mutex);

6868

mutex_unlock(&work->dev->struct_mutex);

6869

kfree(work);

6869

kfree(work);

6870

}

6870

}

6871

6872

static void do_intel_finish_page_flip(struct drm_device *dev,

6872

static void do_intel_finish_page_flip(struct drm_device *dev,

6873

struct drm_crtc *crtc)

6873

struct drm_crtc *crtc)

6874

{

6874

{

6875

drm_i915_private_t *dev_priv = dev->dev_private;

6875

drm_i915_private_t *dev_priv = dev->dev_private;

6876

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6876

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6877

struct intel_unpin_work *work;

6877

struct intel_unpin_work *work;

6878

struct drm_i915_gem_object *obj;

6878

struct drm_i915_gem_object *obj;

6879

struct drm_pending_vblank_event *e;

6879

struct drm_pending_vblank_event *e;

6880

struct timeval tnow, tvbl;

6880

struct timeval tnow, tvbl;

6881

unsigned long flags;

6881

unsigned long flags;

6882

6883

/* Ignore early vblank irqs */

6883

/* Ignore early vblank irqs */

6884

if (intel_crtc == NULL)

6884

if (intel_crtc == NULL)

6885

return;

6885

return;

6886

6887

do_gettimeofday(&tnow);

6887

do_gettimeofday(&tnow);

6888

6889

spin_lock_irqsave(&dev->event_lock, flags);

6889

spin_lock_irqsave(&dev->event_lock, flags);

6890

work = intel_crtc->unpin_work;

6890

work = intel_crtc->unpin_work;

6891

if (work == NULL || !work->pending) {

6891

if (work == NULL || !work->pending) {

6892

spin_unlock_irqrestore(&dev->event_lock, flags);

6892

spin_unlock_irqrestore(&dev->event_lock, flags);

6893

return;

6893

return;

6894

}

6894

}

6895

6896

intel_crtc->unpin_work = NULL;

6896

intel_crtc->unpin_work = NULL;

6897

6898

if (work->event) {

6898

if (work->event) {

6899

e = work->event;

6899

e = work->event;

6900

e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);

6900

e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);

6901

6902

/* Called before vblank count and timestamps have

6902

/* Called before vblank count and timestamps have

6903

* been updated for the vblank interval of flip

6903

* been updated for the vblank interval of flip

6904

* completion? Need to increment vblank count and

6904

* completion? Need to increment vblank count and

6905

* add one videorefresh duration to returned timestamp

6905

* add one videorefresh duration to returned timestamp

6906

* to account for this. We assume this happened if we

6906

* to account for this. We assume this happened if we

6907

* get called over 0.9 frame durations after the last

6907

* get called over 0.9 frame durations after the last

6908

* timestamped vblank.

6908

* timestamped vblank.

6909

*

6909

*

6910

* This calculation can not be used with vrefresh rates

6910

* This calculation can not be used with vrefresh rates

6911

* below 5Hz (10Hz to be on the safe side) without

6911

* below 5Hz (10Hz to be on the safe side) without

6912

* promoting to 64 integers.

6912

* promoting to 64 integers.

6913

*/

6913

*/

6914

if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >

6914

if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >

6915

9 * crtc->framedur_ns) {

6915

9 * crtc->framedur_ns) {

6916

e->event.sequence++;

6916

e->event.sequence++;

6917

tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +

6917

tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +

6918

crtc->framedur_ns);

6918

crtc->framedur_ns);

6919

}

6919

}

6920

6921

e->event.tv_sec = tvbl.tv_sec;

6921

e->event.tv_sec = tvbl.tv_sec;

6922

e->event.tv_usec = tvbl.tv_usec;

6922

e->event.tv_usec = tvbl.tv_usec;

6923

6924

list_add_tail(&e->base.link,

6924

list_add_tail(&e->base.link,

6925

&e->base.file_priv->event_list);

6925

&e->base.file_priv->event_list);

6926

wake_up_interruptible(&e->base.file_priv->event_wait);

6926

wake_up_interruptible(&e->base.file_priv->event_wait);

6927

}

6927

}

6928

6929

drm_vblank_put(dev, intel_crtc->pipe);

6929

drm_vblank_put(dev, intel_crtc->pipe);

6930

6931

spin_unlock_irqrestore(&dev->event_lock, flags);

6931

spin_unlock_irqrestore(&dev->event_lock, flags);

6932

6933

obj = work->old_fb_obj;

6933

obj = work->old_fb_obj;

6934

6935

atomic_clear_mask(1 << intel_crtc->plane,

6935

atomic_clear_mask(1 << intel_crtc->plane,

6936

&obj->pending_flip.counter);

6936

&obj->pending_flip.counter);

6937

if (atomic_read(&obj->pending_flip) == 0)

6937

if (atomic_read(&obj->pending_flip) == 0)

6938

wake_up(&dev_priv->pending_flip_queue);

6938

wake_up(&dev_priv->pending_flip_queue);

6939

6940

schedule_work(&work->work);

6940

schedule_work(&work->work);

6941

6942

trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);

6942

trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);

6943

}

6943

}

6944

6945

void intel_finish_page_flip(struct drm_device *dev, int pipe)

6945

void intel_finish_page_flip(struct drm_device *dev, int pipe)

6946

{

6946

{

6947

drm_i915_private_t *dev_priv = dev->dev_private;

6947

drm_i915_private_t *dev_priv = dev->dev_private;

6948

struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];

6948

struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];

6949

6950

do_intel_finish_page_flip(dev, crtc);

6950

do_intel_finish_page_flip(dev, crtc);

6951

}

6951

}

6952

6953

void intel_finish_page_flip_plane(struct drm_device *dev, int plane)

6953

void intel_finish_page_flip_plane(struct drm_device *dev, int plane)

6954

{

6954

{

6955

drm_i915_private_t *dev_priv = dev->dev_private;

6955

drm_i915_private_t *dev_priv = dev->dev_private;

6956

struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];

6956

struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];

6957

6958

do_intel_finish_page_flip(dev, crtc);

6958

do_intel_finish_page_flip(dev, crtc);

6959

}

6959

}

6960

6961

void intel_prepare_page_flip(struct drm_device *dev, int plane)

6961

void intel_prepare_page_flip(struct drm_device *dev, int plane)

6962

{

6962

{

6963

drm_i915_private_t *dev_priv = dev->dev_private;

6963

drm_i915_private_t *dev_priv = dev->dev_private;

6964

struct intel_crtc *intel_crtc =

6964

struct intel_crtc *intel_crtc =

6965

to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);

6965

to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);

6966

unsigned long flags;

6966

unsigned long flags;

6967

6968

spin_lock_irqsave(&dev->event_lock, flags);

6968

spin_lock_irqsave(&dev->event_lock, flags);

6969

if (intel_crtc->unpin_work) {

6969

if (intel_crtc->unpin_work) {

6970

if ((++intel_crtc->unpin_work->pending) > 1)

6970

if ((++intel_crtc->unpin_work->pending) > 1)

6971

DRM_ERROR("Prepared flip multiple times\n");

6971

DRM_ERROR("Prepared flip multiple times\n");

6972

} else {

6972

} else {

6973

DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");

6973

DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");

6974

}

6974

}

6975

spin_unlock_irqrestore(&dev->event_lock, flags);

6975

spin_unlock_irqrestore(&dev->event_lock, flags);

6976

}

6976

}

6977

6978

static int intel_gen2_queue_flip(struct drm_device *dev,

6978

static int intel_gen2_queue_flip(struct drm_device *dev,

6979

struct drm_crtc *crtc,

6979

struct drm_crtc *crtc,

6980

struct drm_framebuffer *fb,

6980

struct drm_framebuffer *fb,

6981

struct drm_i915_gem_object *obj)

6981

struct drm_i915_gem_object *obj)

6982

{

6982

{

6983

struct drm_i915_private *dev_priv = dev->dev_private;

6983

struct drm_i915_private *dev_priv = dev->dev_private;

6984

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6984

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

6985

unsigned long offset;

6985

unsigned long offset;

6986

u32 flip_mask;

6986

u32 flip_mask;

6987

int ret;

6987

int ret;

6988

6989

ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));

6989

ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));

6990

if (ret)

6990

if (ret)

6991

goto out;

6991

goto out;

6992

6993

/* Offset into the new buffer for cases of shared fbs between CRTCs */

6993

/* Offset into the new buffer for cases of shared fbs between CRTCs */

6994

offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;

6994

offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;

6995

6996

ret = BEGIN_LP_RING(6);

6996

ret = BEGIN_LP_RING(6);

6997

if (ret)

6997

if (ret)

6998

goto out;

6998

goto out;

6999

7000

/* Can't queue multiple flips, so wait for the previous

7000

/* Can't queue multiple flips, so wait for the previous

7001

* one to finish before executing the next.

7001

* one to finish before executing the next.

7002

*/

7002

*/

7003

if (intel_crtc->plane)

7003

if (intel_crtc->plane)

7004

flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;

7004

flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;

7005

else

7005

else

7006

flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;

7006

flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;

7007

OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);

7007

OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);

7008

OUT_RING(MI_NOOP);

7008

OUT_RING(MI_NOOP);

7009

OUT_RING(MI_DISPLAY_FLIP |

7009

OUT_RING(MI_DISPLAY_FLIP |

7010

MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));

7010

MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));

7011

OUT_RING(fb->pitch);

7011

OUT_RING(fb->pitch);

7012

OUT_RING(obj->gtt_offset + offset);

7012

OUT_RING(obj->gtt_offset + offset);

7013

OUT_RING(MI_NOOP);

7013

OUT_RING(MI_NOOP);

7014

ADVANCE_LP_RING();

7014

ADVANCE_LP_RING();

7015

out:

7015

out:

7016

return ret;

7016

return ret;

7017

}

7017

}

7018

7019

static int intel_gen3_queue_flip(struct drm_device *dev,

7019

static int intel_gen3_queue_flip(struct drm_device *dev,

7020

struct drm_crtc *crtc,

7020

struct drm_crtc *crtc,

7021

struct drm_framebuffer *fb,

7021

struct drm_framebuffer *fb,

7022

struct drm_i915_gem_object *obj)

7022

struct drm_i915_gem_object *obj)

7023

{

7023

{

7024

struct drm_i915_private *dev_priv = dev->dev_private;

7024

struct drm_i915_private *dev_priv = dev->dev_private;

7025

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

7025

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

7026

unsigned long offset;

7026

unsigned long offset;

7027

u32 flip_mask;

7027

u32 flip_mask;

7028

int ret;

7028

int ret;

7029

7030

ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));

7030

ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));

7031

if (ret)

7031

if (ret)

7032

goto out;

7032

goto out;

7033

7034

/* Offset into the new buffer for cases of shared fbs between CRTCs */

7034

/* Offset into the new buffer for cases of shared fbs between CRTCs */

7035

offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;

7035

offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;

7036

7037

ret = BEGIN_LP_RING(6);

7037

ret = BEGIN_LP_RING(6);

7038

if (ret)

7038

if (ret)

7039

goto out;

7039

goto out;

7040

7041

if (intel_crtc->plane)

7041

if (intel_crtc->plane)

7042

flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;

7042

flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;

7043

else

7043

else

7044

flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;

7044

flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;

7045

OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);

7045

OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);

7046

OUT_RING(MI_NOOP);

7046

OUT_RING(MI_NOOP);

7047

OUT_RING(MI_DISPLAY_FLIP_I915 |

7047

OUT_RING(MI_DISPLAY_FLIP_I915 |

7048

MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));

7048

MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));

7049

OUT_RING(fb->pitch);

7049

OUT_RING(fb->pitch);

7050

OUT_RING(obj->gtt_offset + offset);

7050

OUT_RING(obj->gtt_offset + offset);

7051

OUT_RING(MI_NOOP);

7051

OUT_RING(MI_NOOP);

7052

7053

ADVANCE_LP_RING();

7053

ADVANCE_LP_RING();

7054

out:

7054

out:

7055

return ret;

7055

return ret;

7056

}

7056

}

7057

7058

static int intel_gen4_queue_flip(struct drm_device *dev,

7058

static int intel_gen4_queue_flip(struct drm_device *dev,

7059

struct drm_crtc *crtc,

7059

struct drm_crtc *crtc,

7060

struct drm_framebuffer *fb,

7060

struct drm_framebuffer *fb,

7061

struct drm_i915_gem_object *obj)

7061

struct drm_i915_gem_object *obj)

7062

{

7062

{

7063

struct drm_i915_private *dev_priv = dev->dev_private;

7063

struct drm_i915_private *dev_priv = dev->dev_private;

7064

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

7064

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

7065

uint32_t pf, pipesrc;

7065

uint32_t pf, pipesrc;

7066

int ret;

7066

int ret;

7067

7068

ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));

7068

ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));

7069

if (ret)

7069

if (ret)

7070

goto out;

7070

goto out;

7071

7072

ret = BEGIN_LP_RING(4);

7072

ret = BEGIN_LP_RING(4);

7073

if (ret)

7073

if (ret)

7074

goto out;

7074

goto out;

7075

7076

/* i965+ uses the linear or tiled offsets from the

7076

/* i965+ uses the linear or tiled offsets from the

7077

* Display Registers (which do not change across a page-flip)

7077

* Display Registers (which do not change across a page-flip)

7078

* so we need only reprogram the base address.

7078

* so we need only reprogram the base address.

7079

*/

7079

*/

7080

OUT_RING(MI_DISPLAY_FLIP |

7080

OUT_RING(MI_DISPLAY_FLIP |

7081

MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));

7081

MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));

7082

OUT_RING(fb->pitch);

7082

OUT_RING(fb->pitch);

7083

OUT_RING(obj->gtt_offset | obj->tiling_mode);

7083

OUT_RING(obj->gtt_offset | obj->tiling_mode);

7084

7085

/* XXX Enabling the panel-fitter across page-flip is so far

7085

/* XXX Enabling the panel-fitter across page-flip is so far

7086

* untested on non-native modes, so ignore it for now.

7086

* untested on non-native modes, so ignore it for now.

7087

* pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;

7087

* pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;

7088

*/

7088

*/

7089

pf = 0;

7089

pf = 0;

7090

pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;

7090

pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;

7091

OUT_RING(pf | pipesrc);

7091

OUT_RING(pf | pipesrc);

7092

ADVANCE_LP_RING();

7092

ADVANCE_LP_RING();

7093

out:

7093

out:

7094

return ret;

7094

return ret;

7095

}

7095

}

7096

7097

static int intel_gen6_queue_flip(struct drm_device *dev,

7097

static int intel_gen6_queue_flip(struct drm_device *dev,

7098

struct drm_crtc *crtc,

7098

struct drm_crtc *crtc,

7099

struct drm_framebuffer *fb,

7099

struct drm_framebuffer *fb,

7100

struct drm_i915_gem_object *obj)

7100

struct drm_i915_gem_object *obj)

7101

{

7101

{

7102

struct drm_i915_private *dev_priv = dev->dev_private;

7102

struct drm_i915_private *dev_priv = dev->dev_private;

7103

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

7103

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

7104

uint32_t pf, pipesrc;

7104

uint32_t pf, pipesrc;

7105

int ret;

7105

int ret;

7106

7107

ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));

7107

ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));

7108

if (ret)

7108

if (ret)

7109

goto out;

7109

goto out;

7110

7111

ret = BEGIN_LP_RING(4);

7111

ret = BEGIN_LP_RING(4);

7112

if (ret)

7112

if (ret)

7113

goto out;

7113

goto out;

7114

7115

OUT_RING(MI_DISPLAY_FLIP |

7115

OUT_RING(MI_DISPLAY_FLIP |

7116

MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));

7116

MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));

7117

OUT_RING(fb->pitch | obj->tiling_mode);

7117

OUT_RING(fb->pitch | obj->tiling_mode);

7118

OUT_RING(obj->gtt_offset);

7118

OUT_RING(obj->gtt_offset);

7119

7120

pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;

7120

pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;

7121

pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;

7121

pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;

7122

OUT_RING(pf | pipesrc);

7122

OUT_RING(pf | pipesrc);

7123

ADVANCE_LP_RING();

7123

ADVANCE_LP_RING();

7124

out:

7124

out:

7125

return ret;

7125

return ret;

7126

}

7126

}

7127

7128

/*

7128

/*

7129

* On gen7 we currently use the blit ring because (in early silicon at least)

7129

* On gen7 we currently use the blit ring because (in early silicon at least)

7130

* the render ring doesn't give us interrpts for page flip completion, which

7130

* the render ring doesn't give us interrpts for page flip completion, which

7131

* means clients will hang after the first flip is queued. Fortunately the

7131

* means clients will hang after the first flip is queued. Fortunately the

7132

* blit ring generates interrupts properly, so use it instead.

7132

* blit ring generates interrupts properly, so use it instead.

7133

*/

7133

*/

7134

static int intel_gen7_queue_flip(struct drm_device *dev,

7134

static int intel_gen7_queue_flip(struct drm_device *dev,

7135

struct drm_crtc *crtc,

7135

struct drm_crtc *crtc,

7136

struct drm_framebuffer *fb,

7136

struct drm_framebuffer *fb,

7137

struct drm_i915_gem_object *obj)

7137

struct drm_i915_gem_object *obj)

7138

{

7138

{

7139

struct drm_i915_private *dev_priv = dev->dev_private;

7139

struct drm_i915_private *dev_priv = dev->dev_private;

7140

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

7140

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

7141

struct intel_ring_buffer *ring = &dev_priv->ring[BCS];

7141

struct intel_ring_buffer *ring = &dev_priv->ring[BCS];

7142

int ret;

7142

int ret;

7143

7144

ret = intel_pin_and_fence_fb_obj(dev, obj, ring);

7144

ret = intel_pin_and_fence_fb_obj(dev, obj, ring);

7145

if (ret)

7145

if (ret)

7146

goto out;

7146

goto out;

7147

7148

ret = intel_ring_begin(ring, 4);

7148

ret = intel_ring_begin(ring, 4);

7149

if (ret)

7149

if (ret)

7150

goto out;

7150

goto out;

7151

7152

intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));

7152

intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));

7153

intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));

7153

intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));

7154

intel_ring_emit(ring, (obj->gtt_offset));

7154

intel_ring_emit(ring, (obj->gtt_offset));

7155

intel_ring_emit(ring, (MI_NOOP));

7155

intel_ring_emit(ring, (MI_NOOP));

7156

intel_ring_advance(ring);

7156

intel_ring_advance(ring);

7157

out:

7157

out:

7158

return ret;

7158

return ret;

7159

}

7159

}

7160

7161

static int intel_default_queue_flip(struct drm_device *dev,

7161

static int intel_default_queue_flip(struct drm_device *dev,

7162

struct drm_crtc *crtc,

7162

struct drm_crtc *crtc,

7163

struct drm_framebuffer *fb,

7163

struct drm_framebuffer *fb,

7164

struct drm_i915_gem_object *obj)

7164

struct drm_i915_gem_object *obj)

7165

{

7165

{

7166

return -ENODEV;

7166

return -ENODEV;

7167

}

7167

}

7168

7169

static int intel_crtc_page_flip(struct drm_crtc *crtc,

7169

static int intel_crtc_page_flip(struct drm_crtc *crtc,

7170

struct drm_framebuffer *fb,

7170

struct drm_framebuffer *fb,

7171

struct drm_pending_vblank_event *event)

7171

struct drm_pending_vblank_event *event)

7172

{

7172

{

7173

struct drm_device *dev = crtc->dev;

7173

struct drm_device *dev = crtc->dev;

7174

struct drm_i915_private *dev_priv = dev->dev_private;

7174

struct drm_i915_private *dev_priv = dev->dev_private;

7175

struct intel_framebuffer *intel_fb;

7175

struct intel_framebuffer *intel_fb;

7176

struct drm_i915_gem_object *obj;

7176

struct drm_i915_gem_object *obj;

7177

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

7177

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

7178

struct intel_unpin_work *work;

7178

struct intel_unpin_work *work;

7179

unsigned long flags;

7179

unsigned long flags;

7180

int ret;

7180

int ret;

7181

7182

work = kzalloc(sizeof *work, GFP_KERNEL);

7182

work = kzalloc(sizeof *work, GFP_KERNEL);

7183

if (work == NULL)

7183

if (work == NULL)

7184

return -ENOMEM;

7184

return -ENOMEM;

7185

7186

work->event = event;

7186

work->event = event;

7187

work->dev = crtc->dev;

7187

work->dev = crtc->dev;

7188

intel_fb = to_intel_framebuffer(crtc->fb);

7188

intel_fb = to_intel_framebuffer(crtc->fb);

7189

work->old_fb_obj = intel_fb->obj;

7189

work->old_fb_obj = intel_fb->obj;

7190

INIT_WORK(&work->work, intel_unpin_work_fn);

7190

INIT_WORK(&work->work, intel_unpin_work_fn);

7191

7192

ret = drm_vblank_get(dev, intel_crtc->pipe);

7193

if (ret)

7194

goto free_work;

7195

7192

/* We borrow the event spin lock for protecting unpin_work */

7196

/* We borrow the event spin lock for protecting unpin_work */

7193

spin_lock_irqsave(&dev->event_lock, flags);

7197

spin_lock_irqsave(&dev->event_lock, flags);

7194

if (intel_crtc->unpin_work) {

7198

if (intel_crtc->unpin_work) {

7195

spin_unlock_irqrestore(&dev->event_lock, flags);

7199

spin_unlock_irqrestore(&dev->event_lock, flags);

7196

kfree(work);

7200

kfree(work);

7201

drm_vblank_put(dev, intel_crtc->pipe);

7197

7202

7198

DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");

7203

DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");

7199

return -EBUSY;

7204

return -EBUSY;

7200

}

7205

}

7201

intel_crtc->unpin_work = work;

7206

intel_crtc->unpin_work = work;

7202

spin_unlock_irqrestore(&dev->event_lock, flags);

7207

spin_unlock_irqrestore(&dev->event_lock, flags);

7203

7208

7204

intel_fb = to_intel_framebuffer(fb);

7209

intel_fb = to_intel_framebuffer(fb);

7205

obj = intel_fb->obj;

7210

obj = intel_fb->obj;

7206

7211

7207

mutex_lock(&dev->struct_mutex);

7212

mutex_lock(&dev->struct_mutex);

7208

7213

7209

/* Reference the objects for the scheduled work. */

7214

/* Reference the objects for the scheduled work. */

7210

drm_gem_object_reference(&work->old_fb_obj->base);

7215

drm_gem_object_reference(&work->old_fb_obj->base);

7211

drm_gem_object_reference(&obj->base);

7216

drm_gem_object_reference(&obj->base);

7212

7217

7213

crtc->fb = fb;

7218

crtc->fb = fb;

7214

7219

7215

ret = drm_vblank_get(dev, intel_crtc->pipe);

7216

if (ret)

7217

goto cleanup_objs;

7218

7219

work->pending_flip_obj = obj;

7220

work->pending_flip_obj = obj;

7220

7221

work->enable_stall_check = true;

7222

work->enable_stall_check = true;

7222

7223

/* Block clients from rendering to the new back buffer until

7224

/* Block clients from rendering to the new back buffer until

7224

* the flip occurs and the object is no longer visible.

7225

* the flip occurs and the object is no longer visible.

7225

*/

7226

*/

7226

atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);

7227

atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);

7227

7228

ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);

7229

ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);

7229

if (ret)

7230

if (ret)

7230

goto cleanup_pending;

7231

goto cleanup_pending;

7231

7232

intel_disable_fbc(dev);

7233

intel_disable_fbc(dev);

7233

mutex_unlock(&dev->struct_mutex);

7234

mutex_unlock(&dev->struct_mutex);

7234

7235

trace_i915_flip_request(intel_crtc->plane, obj);

7236

trace_i915_flip_request(intel_crtc->plane, obj);

7236

7237

return 0;

7238

return 0;

7238

7239

cleanup_pending:

7240

cleanup_pending:

7240

atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);

7241

atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);

7241

cleanup_objs:

7242

drm_gem_object_unreference(&work->old_fb_obj->base);

7242

drm_gem_object_unreference(&work->old_fb_obj->base);

7243

drm_gem_object_unreference(&obj->base);

7243

drm_gem_object_unreference(&obj->base);

7244

mutex_unlock(&dev->struct_mutex);

7244

mutex_unlock(&dev->struct_mutex);

7245

7246

spin_lock_irqsave(&dev->event_lock, flags);

7246

spin_lock_irqsave(&dev->event_lock, flags);

7247

intel_crtc->unpin_work = NULL;

7247

intel_crtc->unpin_work = NULL;

7248

spin_unlock_irqrestore(&dev->event_lock, flags);

7248

spin_unlock_irqrestore(&dev->event_lock, flags);

7249

7250

drm_vblank_put(dev, intel_crtc->pipe);

7251

free_work:

7250

kfree(work);

7252

kfree(work);

7251

7253

7252

return ret;

7254

return ret;

7253

}

7255

}

7254

7256

7255

static void intel_sanitize_modesetting(struct drm_device *dev,

7257

static void intel_sanitize_modesetting(struct drm_device *dev,

7256

int pipe, int plane)

7258

int pipe, int plane)

7257

{

7259

{

7258

struct drm_i915_private *dev_priv = dev->dev_private;

7260

struct drm_i915_private *dev_priv = dev->dev_private;

7259

u32 reg, val;

7261

u32 reg, val;

7260

7262

7261

if (HAS_PCH_SPLIT(dev))

7263

if (HAS_PCH_SPLIT(dev))

7262

return;

7264

return;

7263

7265

7264

/* Who knows what state these registers were left in by the BIOS or

7266

/* Who knows what state these registers were left in by the BIOS or

7265

* grub?

7267

* grub?

7266

*

7268

*

7267

* If we leave the registers in a conflicting state (e.g. with the

7269

* If we leave the registers in a conflicting state (e.g. with the

7268

* display plane reading from the other pipe than the one we intend

7270

* display plane reading from the other pipe than the one we intend

7269

* to use) then when we attempt to teardown the active mode, we will

7271

* to use) then when we attempt to teardown the active mode, we will

7270

* not disable the pipes and planes in the correct order -- leaving

7272

* not disable the pipes and planes in the correct order -- leaving

7271

* a plane reading from a disabled pipe and possibly leading to

7273

* a plane reading from a disabled pipe and possibly leading to

7272

* undefined behaviour.

7274

* undefined behaviour.

7273

*/

7275

*/

7274

7276

7275

reg = DSPCNTR(plane);

7277

reg = DSPCNTR(plane);

7276

val = I915_READ(reg);

7278

val = I915_READ(reg);

7277

7279

7278

if ((val & DISPLAY_PLANE_ENABLE) == 0)

7280

if ((val & DISPLAY_PLANE_ENABLE) == 0)

7279

return;

7281

return;

7280

if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)

7282

if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)

7281

return;

7283

return;

7282

7284

7283

/* This display plane is active and attached to the other CPU pipe. */

7285

/* This display plane is active and attached to the other CPU pipe. */

7284

pipe = !pipe;

7286

pipe = !pipe;

7285

7287

7286

/* Disable the plane and wait for it to stop reading from the pipe. */

7288

/* Disable the plane and wait for it to stop reading from the pipe. */

7287

intel_disable_plane(dev_priv, plane, pipe);

7289

intel_disable_plane(dev_priv, plane, pipe);

7288

intel_disable_pipe(dev_priv, pipe);

7290

intel_disable_pipe(dev_priv, pipe);

7289

}

7291

}

7290

7292

7291

static void intel_crtc_reset(struct drm_crtc *crtc)

7293

static void intel_crtc_reset(struct drm_crtc *crtc)

7292

{

7294

{

7293

struct drm_device *dev = crtc->dev;

7295

struct drm_device *dev = crtc->dev;

7294

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

7296

struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

7295

7297

7296

/* Reset flags back to the 'unknown' status so that they

7298

/* Reset flags back to the 'unknown' status so that they

7297

* will be correctly set on the initial modeset.

7299

* will be correctly set on the initial modeset.

7298

*/

7300

*/

7299

intel_crtc->dpms_mode = -1;

7301

intel_crtc->dpms_mode = -1;

7300

7302

7301

/* We need to fix up any BIOS configuration that conflicts with

7303

/* We need to fix up any BIOS configuration that conflicts with

7302

* our expectations.

7304

* our expectations.

7303

*/

7305

*/

7304

intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);

7306

intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);

7305

}

7307

}

7306

7308

7307

static struct drm_crtc_helper_funcs intel_helper_funcs = {

7309

static struct drm_crtc_helper_funcs intel_helper_funcs = {

7308

.dpms = intel_crtc_dpms,

7310

.dpms = intel_crtc_dpms,

7309

.mode_fixup = intel_crtc_mode_fixup,

7311

.mode_fixup = intel_crtc_mode_fixup,

7310

.mode_set = intel_crtc_mode_set,

7312

.mode_set = intel_crtc_mode_set,

7311

.mode_set_base = intel_pipe_set_base,

7313

.mode_set_base = intel_pipe_set_base,

7312

.mode_set_base_atomic = intel_pipe_set_base_atomic,

7314

.mode_set_base_atomic = intel_pipe_set_base_atomic,

7313

.load_lut = intel_crtc_load_lut,

7315

.load_lut = intel_crtc_load_lut,

7314

.disable = intel_crtc_disable,

7316

.disable = intel_crtc_disable,

7315

};

7317

};

7316

7318

7317

static const struct drm_crtc_funcs intel_crtc_funcs = {

7319

static const struct drm_crtc_funcs intel_crtc_funcs = {

7318

.reset = intel_crtc_reset,

7320

.reset = intel_crtc_reset,

7319

.cursor_set = intel_crtc_cursor_set,

7321

.cursor_set = intel_crtc_cursor_set,

7320

.cursor_move = intel_crtc_cursor_move,

7322

.cursor_move = intel_crtc_cursor_move,

7321

.gamma_set = intel_crtc_gamma_set,

7323

.gamma_set = intel_crtc_gamma_set,

7322

.set_config = drm_crtc_helper_set_config,

7324

.set_config = drm_crtc_helper_set_config,

7323

.destroy = intel_crtc_destroy,

7325

.destroy = intel_crtc_destroy,

7324

.page_flip = intel_crtc_page_flip,

7326

.page_flip = intel_crtc_page_flip,

7325

};

7327

};

7326

7328

7327

static void intel_crtc_init(struct drm_device *dev, int pipe)

7329

static void intel_crtc_init(struct drm_device *dev, int pipe)

7328

{

7330

{

7329

drm_i915_private_t *dev_priv = dev->dev_private;

7331

drm_i915_private_t *dev_priv = dev->dev_private;

7330

struct intel_crtc *intel_crtc;

7332

struct intel_crtc *intel_crtc;

7331

int i;

7333

int i;

7332

7334

7333

intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);

7335

intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);

7334

if (intel_crtc == NULL)

7336

if (intel_crtc == NULL)

7335

return;

7337

return;

7336

7338

7337

drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);

7339

drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);

7338

7340

7339

drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);

7341

drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);

7340

for (i = 0; i < 256; i++) {

7342

for (i = 0; i < 256; i++) {

7341

intel_crtc->lut_r[i] = i;

7343

intel_crtc->lut_r[i] = i;

7342

intel_crtc->lut_g[i] = i;

7344

intel_crtc->lut_g[i] = i;

7343

intel_crtc->lut_b[i] = i;

7345

intel_crtc->lut_b[i] = i;

7344

}

7346

}

7345

7347

7346

/* Swap pipes & planes for FBC on pre-965 */

7348

/* Swap pipes & planes for FBC on pre-965 */

7347

intel_crtc->pipe = pipe;

7349

intel_crtc->pipe = pipe;

7348

intel_crtc->plane = pipe;

7350

intel_crtc->plane = pipe;

7349

if (IS_MOBILE(dev) && IS_GEN3(dev)) {

7351

if (IS_MOBILE(dev) && IS_GEN3(dev)) {

7350

DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");

7352

DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");

7351

intel_crtc->plane = !pipe;

7353

intel_crtc->plane = !pipe;

7352

}

7354

}

7353

7355

7354

BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||

7356

BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||

7355

dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);

7357

dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);

7356

dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;

7358

dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;

7357

dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;

7359

dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;

7358

7360

7359

intel_crtc_reset(&intel_crtc->base);

7361

intel_crtc_reset(&intel_crtc->base);

7360

intel_crtc->active = true; /* force the pipe off on setup_init_config */

7362

intel_crtc->active = true; /* force the pipe off on setup_init_config */

7361

intel_crtc->bpp = 24; /* default for pre-Ironlake */

7363

intel_crtc->bpp = 24; /* default for pre-Ironlake */

7362

7364

7363

if (HAS_PCH_SPLIT(dev)) {

7365

if (HAS_PCH_SPLIT(dev)) {

7364

if (pipe == 2 && IS_IVYBRIDGE(dev))

7366

if (pipe == 2 && IS_IVYBRIDGE(dev))

7365

intel_crtc->no_pll = true;

7367

intel_crtc->no_pll = true;

7366

intel_helper_funcs.prepare = ironlake_crtc_prepare;

7368

intel_helper_funcs.prepare = ironlake_crtc_prepare;

7367

intel_helper_funcs.commit = ironlake_crtc_commit;

7369

intel_helper_funcs.commit = ironlake_crtc_commit;

7368

} else {

7370

} else {

7369

intel_helper_funcs.prepare = i9xx_crtc_prepare;

7371

intel_helper_funcs.prepare = i9xx_crtc_prepare;

7370

intel_helper_funcs.commit = i9xx_crtc_commit;

7372

intel_helper_funcs.commit = i9xx_crtc_commit;

7371

}

7373

}

7372

7374

7373

drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);

7375

drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);

7374

7376

7375

intel_crtc->busy = false;

7377

intel_crtc->busy = false;

7376

7378

7377

setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,

7379

setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,

7378

(unsigned long)intel_crtc);

7380

(unsigned long)intel_crtc);

7379

}

7381

}

7380

7382

7381

int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,

7383

int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,

7382

struct drm_file *file)

7384

struct drm_file *file)

7383

{

7385

{

7384

drm_i915_private_t *dev_priv = dev->dev_private;

7386

drm_i915_private_t *dev_priv = dev->dev_private;

7385

struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;

7387

struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;

7386

struct drm_mode_object *drmmode_obj;

7388

struct drm_mode_object *drmmode_obj;

7387

struct intel_crtc *crtc;

7389

struct intel_crtc *crtc;

7388

7390

7389

if (!dev_priv) {

7391

if (!dev_priv) {

7390

DRM_ERROR("called with no initialization\n");

7392

DRM_ERROR("called with no initialization\n");

7391

return -EINVAL;

7393

return -EINVAL;

7392

}

7394

}

7393

7395

7394

drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,

7396

drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,

7395

DRM_MODE_OBJECT_CRTC);

7397

DRM_MODE_OBJECT_CRTC);

7396

7398

7397

if (!drmmode_obj) {

7399

if (!drmmode_obj) {

7398

DRM_ERROR("no such CRTC id\n");

7400

DRM_ERROR("no such CRTC id\n");

7399

return -EINVAL;

7401

return -EINVAL;

7400

}

7402

}

7401

7403

7402

crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));

7404

crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));

7403

pipe_from_crtc_id->pipe = crtc->pipe;

7405

pipe_from_crtc_id->pipe = crtc->pipe;

7404

7406

7405

return 0;

7407

return 0;

7406

}

7408

}

7407

7409

7408

static int intel_encoder_clones(struct drm_device *dev, int type_mask)

7410

static int intel_encoder_clones(struct drm_device *dev, int type_mask)

7409

{

7411

{

7410

struct intel_encoder *encoder;

7412

struct intel_encoder *encoder;

7411

int index_mask = 0;

7413

int index_mask = 0;

7412

int entry = 0;

7414

int entry = 0;

7413

7415

7414

list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {

7416

list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {

7415

if (type_mask & encoder->clone_mask)

7417

if (type_mask & encoder->clone_mask)

7416

index_mask |= (1 << entry);

7418

index_mask |= (1 << entry);

7417

entry++;

7419

entry++;

7418

}

7420

}

7419

7421

7420

return index_mask;

7422

return index_mask;

7421

}

7423

}

7422

7424

7423

static bool has_edp_a(struct drm_device *dev)

7425

static bool has_edp_a(struct drm_device *dev)

7424

{

7426

{

7425

struct drm_i915_private *dev_priv = dev->dev_private;

7427

struct drm_i915_private *dev_priv = dev->dev_private;

7426

7428

7427

if (!IS_MOBILE(dev))

7429

if (!IS_MOBILE(dev))

7428

return false;

7430

return false;

7429

7431

7430

if ((I915_READ(DP_A) & DP_DETECTED) == 0)

7432

if ((I915_READ(DP_A) & DP_DETECTED) == 0)

7431

return false;

7433

return false;

7432

7434

7433

if (IS_GEN5(dev) &&

7435

if (IS_GEN5(dev) &&

7434

(I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))

7436

(I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))

7435

return false;

7437

return false;

7436

7438

7437

return true;

7439

return true;

7438

}

7440

}

7439

7441

7440

static void intel_setup_outputs(struct drm_device *dev)

7442

static void intel_setup_outputs(struct drm_device *dev)

7441

{

7443

{

7442

struct drm_i915_private *dev_priv = dev->dev_private;

7444

struct drm_i915_private *dev_priv = dev->dev_private;

7443

struct intel_encoder *encoder;

7445

struct intel_encoder *encoder;

7444

bool dpd_is_edp = false;

7446

bool dpd_is_edp = false;

7445

bool has_lvds = false;

7447

bool has_lvds = false;

7446

7448

7447

if (IS_MOBILE(dev) && !IS_I830(dev))

7449

if (IS_MOBILE(dev) && !IS_I830(dev))

7448

has_lvds = intel_lvds_init(dev);

7450

has_lvds = intel_lvds_init(dev);

7449

if (!has_lvds && !HAS_PCH_SPLIT(dev)) {

7451

if (!has_lvds && !HAS_PCH_SPLIT(dev)) {

7450

/* disable the panel fitter on everything but LVDS */

7452

/* disable the panel fitter on everything but LVDS */

7451

I915_WRITE(PFIT_CONTROL, 0);

7453

I915_WRITE(PFIT_CONTROL, 0);

7452

}

7454

}

7453

7455

7454

if (HAS_PCH_SPLIT(dev)) {

7456

if (HAS_PCH_SPLIT(dev)) {

7455

dpd_is_edp = intel_dpd_is_edp(dev);

7457

dpd_is_edp = intel_dpd_is_edp(dev);

7456

7458

7457

if (has_edp_a(dev))

7459

if (has_edp_a(dev))

7458

intel_dp_init(dev, DP_A);

7460

intel_dp_init(dev, DP_A);

7459

7461

7460

if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))

7462

if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))

7461

intel_dp_init(dev, PCH_DP_D);

7463

intel_dp_init(dev, PCH_DP_D);

7462

}

7464

}

7463

7465

7464

intel_crt_init(dev);

7466

intel_crt_init(dev);

7465

7467

7466

if (HAS_PCH_SPLIT(dev)) {

7468

if (HAS_PCH_SPLIT(dev)) {

7467

int found;

7469

int found;

7468

7470

7469

if (I915_READ(HDMIB) & PORT_DETECTED) {

7471

if (I915_READ(HDMIB) & PORT_DETECTED) {

7470

/* PCH SDVOB multiplex with HDMIB */

7472

/* PCH SDVOB multiplex with HDMIB */

7471

found = intel_sdvo_init(dev, PCH_SDVOB);

7473

found = intel_sdvo_init(dev, PCH_SDVOB);

7472

if (!found)

7474

if (!found)

7473

intel_hdmi_init(dev, HDMIB);

7475

intel_hdmi_init(dev, HDMIB);

7474

if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))

7476

if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))

7475

intel_dp_init(dev, PCH_DP_B);

7477

intel_dp_init(dev, PCH_DP_B);

7476

}

7478

}

7477

7479

7478

if (I915_READ(HDMIC) & PORT_DETECTED)

7480

if (I915_READ(HDMIC) & PORT_DETECTED)

7479

intel_hdmi_init(dev, HDMIC);

7481

intel_hdmi_init(dev, HDMIC);

7480

7482

7481

if (I915_READ(HDMID) & PORT_DETECTED)

7483

if (I915_READ(HDMID) & PORT_DETECTED)

7482

intel_hdmi_init(dev, HDMID);

7484

intel_hdmi_init(dev, HDMID);

7483

7485

7484

if (I915_READ(PCH_DP_C) & DP_DETECTED)

7486

if (I915_READ(PCH_DP_C) & DP_DETECTED)

7485

intel_dp_init(dev, PCH_DP_C);

7487

intel_dp_init(dev, PCH_DP_C);

7486

7488

7487

if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))

7489

if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))

7488

intel_dp_init(dev, PCH_DP_D);

7490

intel_dp_init(dev, PCH_DP_D);

7489

7491

7490

} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {

7492

} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {

7491

bool found = false;

7493

bool found = false;

7492

7494

7493

if (I915_READ(SDVOB) & SDVO_DETECTED) {

7495

if (I915_READ(SDVOB) & SDVO_DETECTED) {

7494

DRM_DEBUG_KMS("probing SDVOB\n");

7496

DRM_DEBUG_KMS("probing SDVOB\n");

7495

found = intel_sdvo_init(dev, SDVOB);

7497

found = intel_sdvo_init(dev, SDVOB);

7496

if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {

7498

if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {

7497

DRM_DEBUG_KMS("probing HDMI on SDVOB\n");

7499

DRM_DEBUG_KMS("probing HDMI on SDVOB\n");

7498

intel_hdmi_init(dev, SDVOB);

7500

intel_hdmi_init(dev, SDVOB);

7499

}

7501

}

7500

7502

7501

if (!found && SUPPORTS_INTEGRATED_DP(dev)) {

7503

if (!found && SUPPORTS_INTEGRATED_DP(dev)) {

7502

DRM_DEBUG_KMS("probing DP_B\n");

7504

DRM_DEBUG_KMS("probing DP_B\n");

7503

intel_dp_init(dev, DP_B);

7505

intel_dp_init(dev, DP_B);

7504

}

7506

}

7505

}

7507

}

7506

7508

7507

/* Before G4X SDVOC doesn't have its own detect register */

7509

/* Before G4X SDVOC doesn't have its own detect register */

7508

7510

7509

if (I915_READ(SDVOB) & SDVO_DETECTED) {

7511

if (I915_READ(SDVOB) & SDVO_DETECTED) {

7510

DRM_DEBUG_KMS("probing SDVOC\n");

7512

DRM_DEBUG_KMS("probing SDVOC\n");

7511

found = intel_sdvo_init(dev, SDVOC);

7513

found = intel_sdvo_init(dev, SDVOC);

7512

}

7514

}

7513

7515

7514

if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {

7516

if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {

7515

7517

7516

if (SUPPORTS_INTEGRATED_HDMI(dev)) {

7518

if (SUPPORTS_INTEGRATED_HDMI(dev)) {

7517

DRM_DEBUG_KMS("probing HDMI on SDVOC\n");

7519

DRM_DEBUG_KMS("probing HDMI on SDVOC\n");

7518

intel_hdmi_init(dev, SDVOC);

7520

intel_hdmi_init(dev, SDVOC);

7519

}

7521

}

7520

if (SUPPORTS_INTEGRATED_DP(dev)) {

7522

if (SUPPORTS_INTEGRATED_DP(dev)) {

7521

DRM_DEBUG_KMS("probing DP_C\n");

7523

DRM_DEBUG_KMS("probing DP_C\n");

7522

intel_dp_init(dev, DP_C);

7524

intel_dp_init(dev, DP_C);

7523

}

7525

}

7524

}

7526

}

7525

7527

7526

if (SUPPORTS_INTEGRATED_DP(dev) &&

7528

if (SUPPORTS_INTEGRATED_DP(dev) &&

7527

(I915_READ(DP_D) & DP_DETECTED)) {

7529

(I915_READ(DP_D) & DP_DETECTED)) {

7528

DRM_DEBUG_KMS("probing DP_D\n");

7530

DRM_DEBUG_KMS("probing DP_D\n");

7529

intel_dp_init(dev, DP_D);

7531

intel_dp_init(dev, DP_D);

7530

}

7532

}

7531

} else if (IS_GEN2(dev))

7533

} else if (IS_GEN2(dev))

7532

intel_dvo_init(dev);

7534

intel_dvo_init(dev);

7533

7535

7534

if (SUPPORTS_TV(dev))

7536

if (SUPPORTS_TV(dev))

7535

intel_tv_init(dev);

7537

intel_tv_init(dev);

7536

7538

7537

list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {

7539

list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {

7538

encoder->base.possible_crtcs = encoder->crtc_mask;

7540

encoder->base.possible_crtcs = encoder->crtc_mask;

7539

encoder->base.possible_clones =

7541

encoder->base.possible_clones =

7540

intel_encoder_clones(dev, encoder->clone_mask);

7542

intel_encoder_clones(dev, encoder->clone_mask);

7541

}

7543

}

7542

7544

7543

/* disable all the possible outputs/crtcs before entering KMS mode */

7545

/* disable all the possible outputs/crtcs before entering KMS mode */

7544

drm_helper_disable_unused_functions(dev);

7546

drm_helper_disable_unused_functions(dev);

7545

7547

7546

if (HAS_PCH_SPLIT(dev))

7548

if (HAS_PCH_SPLIT(dev))

7547

ironlake_init_pch_refclk(dev);

7549

ironlake_init_pch_refclk(dev);

7548

}

7550

}

7549

7551

7550

static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)

7552

static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)

7551

{

7553

{

7552

struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);

7554

struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);

7553

7555

7554

drm_framebuffer_cleanup(fb);

7556

drm_framebuffer_cleanup(fb);

7555

drm_gem_object_unreference_unlocked(&intel_fb->obj->base);

7557

drm_gem_object_unreference_unlocked(&intel_fb->obj->base);

7556

7558

7557

kfree(intel_fb);

7559

kfree(intel_fb);

7558

}

7560

}

7559

7561

7560

static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,

7562

static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,

7561

struct drm_file *file,

7563

struct drm_file *file,

7562

unsigned int *handle)

7564

unsigned int *handle)

7563

{

7565

{

7564

struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);

7566

struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);

7565

struct drm_i915_gem_object *obj = intel_fb->obj;

7567

struct drm_i915_gem_object *obj = intel_fb->obj;

7566

7568

7567

return drm_gem_handle_create(file, &obj->base, handle);

7569

return drm_gem_handle_create(file, &obj->base, handle);

7568

}

7570

}

7569

7571

7570

static const struct drm_framebuffer_funcs intel_fb_funcs = {

7572

static const struct drm_framebuffer_funcs intel_fb_funcs = {

7571

.destroy = intel_user_framebuffer_destroy,

7573

.destroy = intel_user_framebuffer_destroy,

7572

.create_handle = intel_user_framebuffer_create_handle,

7574

.create_handle = intel_user_framebuffer_create_handle,

7573

};

7575

};

7574

7576

7575

int intel_framebuffer_init(struct drm_device *dev,

7577

int intel_framebuffer_init(struct drm_device *dev,

7576

struct intel_framebuffer *intel_fb,

7578

struct intel_framebuffer *intel_fb,

7577

struct drm_mode_fb_cmd *mode_cmd,

7579

struct drm_mode_fb_cmd *mode_cmd,

7578

struct drm_i915_gem_object *obj)

7580

struct drm_i915_gem_object *obj)

7579

{

7581

{

7580

int ret;

7582

int ret;

7581

7583

7582

if (obj->tiling_mode == I915_TILING_Y)

7584

if (obj->tiling_mode == I915_TILING_Y)

7583

return -EINVAL;

7585

return -EINVAL;

7584

7586

7585

if (mode_cmd->pitch & 63)

7587

if (mode_cmd->pitch & 63)

7586

return -EINVAL;

7588

return -EINVAL;

7587

7589

7588

switch (mode_cmd->bpp) {

7590

switch (mode_cmd->bpp) {

7589

case 8:

7591

case 8:

7590

case 16:

7592

case 16:

7591

/* Only pre-ILK can handle 5:5:5 */

7593

/* Only pre-ILK can handle 5:5:5 */

7592

if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))

7594

if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))

7593

return -EINVAL;

7595

return -EINVAL;

7594

break;

7596

break;

7595

7597

7596

case 24:

7598

case 24:

7597

case 32:

7599

case 32:

7598

break;

7600

break;

7599

default:

7601

default:

7600

return -EINVAL;

7602

return -EINVAL;

7601

}

7603

}

7602

7604

7603

ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);

7605

ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);

7604

if (ret) {

7606

if (ret) {

7605

DRM_ERROR("framebuffer init failed %d\n", ret);

7607

DRM_ERROR("framebuffer init failed %d\n", ret);

7606

return ret;

7608

return ret;

7607

}

7609

}

7608

7610

7609

drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);

7611

drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);

7610

intel_fb->obj = obj;

7612

intel_fb->obj = obj;

7611

return 0;

7613

return 0;

7612

}

7614

}

7613

7615

7614

static struct drm_framebuffer *

7616

static struct drm_framebuffer *

7615

intel_user_framebuffer_create(struct drm_device *dev,

7617

intel_user_framebuffer_create(struct drm_device *dev,

7616

struct drm_file *filp,

7618

struct drm_file *filp,

7617

struct drm_mode_fb_cmd *mode_cmd)

7619

struct drm_mode_fb_cmd *mode_cmd)

7618

{

7620

{

7619

struct drm_i915_gem_object *obj;

7621

struct drm_i915_gem_object *obj;

7620

7622

7621

obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));

7623

obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));

7622

if (&obj->base == NULL)

7624

if (&obj->base == NULL)

7623

return ERR_PTR(-ENOENT);

7625

return ERR_PTR(-ENOENT);

7624

7626

7625

return intel_framebuffer_create(dev, mode_cmd, obj);

7627

return intel_framebuffer_create(dev, mode_cmd, obj);

7626

}

7628

}

7627

7629

7628

static const struct drm_mode_config_funcs intel_mode_funcs = {

7630

static const struct drm_mode_config_funcs intel_mode_funcs = {

7629

.fb_create = intel_user_framebuffer_create,

7631

.fb_create = intel_user_framebuffer_create,

7630

.output_poll_changed = intel_fb_output_poll_changed,

7632

.output_poll_changed = intel_fb_output_poll_changed,

7631

};

7633

};

7632

7634

7633

static struct drm_i915_gem_object *

7635

static struct drm_i915_gem_object *

7634

intel_alloc_context_page(struct drm_device *dev)

7636

intel_alloc_context_page(struct drm_device *dev)

7635

{

7637

{

7636

struct drm_i915_gem_object *ctx;

7638

struct drm_i915_gem_object *ctx;

7637

int ret;

7639

int ret;

7638

7640

7639

WARN_ON(!mutex_is_locked(&dev->struct_mutex));

7641

WARN_ON(!mutex_is_locked(&dev->struct_mutex));

7640

7642

7641

ctx = i915_gem_alloc_object(dev, 4096);

7643

ctx = i915_gem_alloc_object(dev, 4096);

7642

if (!ctx) {

7644

if (!ctx) {

7643

DRM_DEBUG("failed to alloc power context, RC6 disabled\n");

7645

DRM_DEBUG("failed to alloc power context, RC6 disabled\n");

7644

return NULL;

7646

return NULL;

7645

}

7647

}

7646

7648

7647

ret = i915_gem_object_pin(ctx, 4096, true);

7649

ret = i915_gem_object_pin(ctx, 4096, true);

7648

if (ret) {

7650

if (ret) {

7649

DRM_ERROR("failed to pin power context: %d\n", ret);

7651

DRM_ERROR("failed to pin power context: %d\n", ret);

7650

goto err_unref;

7652

goto err_unref;

7651

}

7653

}

7652

7654

7653

ret = i915_gem_object_set_to_gtt_domain(ctx, 1);

7655

ret = i915_gem_object_set_to_gtt_domain(ctx, 1);

7654

if (ret) {

7656

if (ret) {

7655

DRM_ERROR("failed to set-domain on power context: %d\n", ret);

7657

DRM_ERROR("failed to set-domain on power context: %d\n", ret);

7656

goto err_unpin;

7658

goto err_unpin;

7657

}

7659

}

7658

7660

7659

return ctx;

7661

return ctx;

7660

7662

7661

err_unpin:

7663

err_unpin:

7662

i915_gem_object_unpin(ctx);

7664

i915_gem_object_unpin(ctx);

7663

err_unref:

7665

err_unref:

7664

drm_gem_object_unreference(&ctx->base);

7666

drm_gem_object_unreference(&ctx->base);

7665

mutex_unlock(&dev->struct_mutex);

7667

mutex_unlock(&dev->struct_mutex);

7666

return NULL;

7668

return NULL;

7667

}

7669

}

7668

7670

7669

bool ironlake_set_drps(struct drm_device *dev, u8 val)

7671

bool ironlake_set_drps(struct drm_device *dev, u8 val)

7670

{

7672

{

7671

struct drm_i915_private *dev_priv = dev->dev_private;

7673

struct drm_i915_private *dev_priv = dev->dev_private;

7672

u16 rgvswctl;

7674

u16 rgvswctl;

7673

7675

7674

rgvswctl = I915_READ16(MEMSWCTL);

7676

rgvswctl = I915_READ16(MEMSWCTL);

7675

if (rgvswctl & MEMCTL_CMD_STS) {

7677

if (rgvswctl & MEMCTL_CMD_STS) {

7676

DRM_DEBUG("gpu busy, RCS change rejected\n");

7678

DRM_DEBUG("gpu busy, RCS change rejected\n");

7677

return false; /* still busy with another command */

7679

return false; /* still busy with another command */

7678

}

7680

}

7679

7681

7680

rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |

7682

rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |

7681

(val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;

7683

(val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;

7682

I915_WRITE16(MEMSWCTL, rgvswctl);

7684

I915_WRITE16(MEMSWCTL, rgvswctl);

7683

POSTING_READ16(MEMSWCTL);

7685

POSTING_READ16(MEMSWCTL);

7684

7686

7685

rgvswctl |= MEMCTL_CMD_STS;

7687

rgvswctl |= MEMCTL_CMD_STS;

7686

I915_WRITE16(MEMSWCTL, rgvswctl);

7688

I915_WRITE16(MEMSWCTL, rgvswctl);

7687

7689

7688

return true;

7690

return true;

7689

}

7691

}

7690

7692

7691

void ironlake_enable_drps(struct drm_device *dev)

7693

void ironlake_enable_drps(struct drm_device *dev)

7692

{

7694

{

7693

struct drm_i915_private *dev_priv = dev->dev_private;

7695

struct drm_i915_private *dev_priv = dev->dev_private;

7694

u32 rgvmodectl = I915_READ(MEMMODECTL);

7696

u32 rgvmodectl = I915_READ(MEMMODECTL);

7695

u8 fmax, fmin, fstart, vstart;

7697

u8 fmax, fmin, fstart, vstart;

7696

7698

7697

/* Enable temp reporting */

7699

/* Enable temp reporting */

7698

I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);

7700

I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);

7699

I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);

7701

I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);

7700

7702

7701

/* 100ms RC evaluation intervals */

7703

/* 100ms RC evaluation intervals */

7702

I915_WRITE(RCUPEI, 100000);

7704

I915_WRITE(RCUPEI, 100000);

7703

I915_WRITE(RCDNEI, 100000);

7705

I915_WRITE(RCDNEI, 100000);

7704

7706

7705

/* Set max/min thresholds to 90ms and 80ms respectively */

7707

/* Set max/min thresholds to 90ms and 80ms respectively */

7706

I915_WRITE(RCBMAXAVG, 90000);

7708

I915_WRITE(RCBMAXAVG, 90000);

7707

I915_WRITE(RCBMINAVG, 80000);

7709

I915_WRITE(RCBMINAVG, 80000);

7708

7710

7709

I915_WRITE(MEMIHYST, 1);

7711

I915_WRITE(MEMIHYST, 1);

7710

7712

7711

/* Set up min, max, and cur for interrupt handling */

7713

/* Set up min, max, and cur for interrupt handling */

7712

fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;

7714

fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;

7713

fmin = (rgvmodectl & MEMMODE_FMIN_MASK);

7715

fmin = (rgvmodectl & MEMMODE_FMIN_MASK);

7714

fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>

7716

fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>

7715

MEMMODE_FSTART_SHIFT;

7717

MEMMODE_FSTART_SHIFT;

7716

7718

7717

vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>

7719

vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>

7718

PXVFREQ_PX_SHIFT;

7720

PXVFREQ_PX_SHIFT;

7719

7721

7720

dev_priv->fmax = fmax; /* IPS callback will increase this */

7722

dev_priv->fmax = fmax; /* IPS callback will increase this */

7721

dev_priv->fstart = fstart;

7723

dev_priv->fstart = fstart;

7722

7724

7723

dev_priv->max_delay = fstart;

7725

dev_priv->max_delay = fstart;

7724

dev_priv->min_delay = fmin;

7726

dev_priv->min_delay = fmin;

7725

dev_priv->cur_delay = fstart;

7727

dev_priv->cur_delay = fstart;

7726

7728

7727

DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",

7729

DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",

7728

fmax, fmin, fstart);

7730

fmax, fmin, fstart);

7729

7731

7730

I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);

7732

I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);

7731

7733

7732

/*

7734

/*

7733

* Interrupts will be enabled in ironlake_irq_postinstall

7735

* Interrupts will be enabled in ironlake_irq_postinstall

7734

*/

7736

*/

7735

7737

7736

I915_WRITE(VIDSTART, vstart);

7738

I915_WRITE(VIDSTART, vstart);

7737

POSTING_READ(VIDSTART);

7739

POSTING_READ(VIDSTART);

7738

7740

7739

rgvmodectl |= MEMMODE_SWMODE_EN;

7741

rgvmodectl |= MEMMODE_SWMODE_EN;

7740

I915_WRITE(MEMMODECTL, rgvmodectl);

7742

I915_WRITE(MEMMODECTL, rgvmodectl);

7741

7743

7742

if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))

7744

if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))

7743

DRM_ERROR("stuck trying to change perf mode\n");

7745

DRM_ERROR("stuck trying to change perf mode\n");

7744

msleep(1);

7746

msleep(1);

7745

7747

7746

ironlake_set_drps(dev, fstart);

7748

ironlake_set_drps(dev, fstart);

7747

7749

7748

dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +

7750

dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +

7749

I915_READ(0x112e0);

7751

I915_READ(0x112e0);

7750

dev_priv->last_time1 = jiffies_to_msecs(jiffies);

7752

dev_priv->last_time1 = jiffies_to_msecs(jiffies);

7751

dev_priv->last_count2 = I915_READ(0x112f4);

7753

dev_priv->last_count2 = I915_READ(0x112f4);

7752

getrawmonotonic(&dev_priv->last_time2);

7754

getrawmonotonic(&dev_priv->last_time2);

7753

}

7755

}

7754

7756

7755

void ironlake_disable_drps(struct drm_device *dev)

7757

void ironlake_disable_drps(struct drm_device *dev)

7756

{

7758

{

7757

struct drm_i915_private *dev_priv = dev->dev_private;

7759

struct drm_i915_private *dev_priv = dev->dev_private;

7758

u16 rgvswctl = I915_READ16(MEMSWCTL);

7760

u16 rgvswctl = I915_READ16(MEMSWCTL);

7759

7761

7760

/* Ack interrupts, disable EFC interrupt */

7762

/* Ack interrupts, disable EFC interrupt */

7761

I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);

7763

I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);

7762

I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);

7764

I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);

7763

I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);

7765

I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);

7764

I915_WRITE(DEIIR, DE_PCU_EVENT);

7766

I915_WRITE(DEIIR, DE_PCU_EVENT);

7765

I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);

7767

I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);

7766

7768

7767

/* Go back to the starting frequency */

7769

/* Go back to the starting frequency */

7768

ironlake_set_drps(dev, dev_priv->fstart);

7770

ironlake_set_drps(dev, dev_priv->fstart);

7769

msleep(1);

7771

msleep(1);

7770

rgvswctl |= MEMCTL_CMD_STS;

7772

rgvswctl |= MEMCTL_CMD_STS;

7771

I915_WRITE(MEMSWCTL, rgvswctl);

7773

I915_WRITE(MEMSWCTL, rgvswctl);

7772

msleep(1);

7774

msleep(1);

7773

7775

7774

}

7776

}

7775

7777

7776

void gen6_set_rps(struct drm_device *dev, u8 val)

7778

void gen6_set_rps(struct drm_device *dev, u8 val)

7777

{

7779

{

7778

struct drm_i915_private *dev_priv = dev->dev_private;

7780

struct drm_i915_private *dev_priv = dev->dev_private;

7779

u32 swreq;

7781

u32 swreq;

7780

7782

7781

swreq = (val & 0x3ff) << 25;

7783

swreq = (val & 0x3ff) << 25;

7782

I915_WRITE(GEN6_RPNSWREQ, swreq);

7784

I915_WRITE(GEN6_RPNSWREQ, swreq);

7783

}

7785

}

7784

7786

7785

void gen6_disable_rps(struct drm_device *dev)

7787

void gen6_disable_rps(struct drm_device *dev)

7786

{

7788

{

7787

struct drm_i915_private *dev_priv = dev->dev_private;

7789

struct drm_i915_private *dev_priv = dev->dev_private;

7788

7790

7789

I915_WRITE(GEN6_RPNSWREQ, 1 << 31);

7791

I915_WRITE(GEN6_RPNSWREQ, 1 << 31);

7790

I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);

7792

I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);

7791

I915_WRITE(GEN6_PMIER, 0);

7793

I915_WRITE(GEN6_PMIER, 0);

7792

/* Complete PM interrupt masking here doesn't race with the rps work

7794

/* Complete PM interrupt masking here doesn't race with the rps work

7793

* item again unmasking PM interrupts because that is using a different

7795

* item again unmasking PM interrupts because that is using a different

7794

* register (PMIMR) to mask PM interrupts. The only risk is in leaving

7796

* register (PMIMR) to mask PM interrupts. The only risk is in leaving

7795

* stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */

7797

* stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */

7796

7798

7797

spin_lock_irq(&dev_priv->rps_lock);

7799

spin_lock_irq(&dev_priv->rps_lock);

7798

dev_priv->pm_iir = 0;

7800

dev_priv->pm_iir = 0;

7799

spin_unlock_irq(&dev_priv->rps_lock);

7801

spin_unlock_irq(&dev_priv->rps_lock);

7800

7802

7801

I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));

7803

I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));

7802

}

7804

}

7803

7805

7804

static unsigned long intel_pxfreq(u32 vidfreq)

7806

static unsigned long intel_pxfreq(u32 vidfreq)

7805

{

7807

{

7806

unsigned long freq;

7808

unsigned long freq;

7807

int div = (vidfreq & 0x3f0000) >> 16;

7809

int div = (vidfreq & 0x3f0000) >> 16;

7808

int post = (vidfreq & 0x3000) >> 12;

7810

int post = (vidfreq & 0x3000) >> 12;

7809

int pre = (vidfreq & 0x7);

7811

int pre = (vidfreq & 0x7);

7810

7812

7811

if (!pre)

7813

if (!pre)

7812

return 0;

7814

return 0;

7813

7815

7814

freq = ((div * 133333) / ((1<<post) * pre));

7816

freq = ((div * 133333) / ((1<<post) * pre));

7815

7817

7816

return freq;

7818

return freq;

7817

}

7819

}

7818

7820

7819

void intel_init_emon(struct drm_device *dev)

7821

void intel_init_emon(struct drm_device *dev)

7820

{

7822

{

7821

struct drm_i915_private *dev_priv = dev->dev_private;

7823

struct drm_i915_private *dev_priv = dev->dev_private;

7822

u32 lcfuse;

7824

u32 lcfuse;

7823

u8 pxw[16];

7825

u8 pxw[16];

7824

int i;

7826

int i;

7825

7827

7826

/* Disable to program */

7828

/* Disable to program */

7827

I915_WRITE(ECR, 0);

7829

I915_WRITE(ECR, 0);

7828

POSTING_READ(ECR);

7830

POSTING_READ(ECR);

7829

7831

7830

/* Program energy weights for various events */

7832

/* Program energy weights for various events */

7831

I915_WRITE(SDEW, 0x15040d00);

7833

I915_WRITE(SDEW, 0x15040d00);

7832

I915_WRITE(CSIEW0, 0x007f0000);

7834

I915_WRITE(CSIEW0, 0x007f0000);

7833

I915_WRITE(CSIEW1, 0x1e220004);

7835

I915_WRITE(CSIEW1, 0x1e220004);

7834

I915_WRITE(CSIEW2, 0x04000004);

7836

I915_WRITE(CSIEW2, 0x04000004);

7835

7837

7836

for (i = 0; i < 5; i++)

7838

for (i = 0; i < 5; i++)

7837

I915_WRITE(PEW + (i * 4), 0);

7839

I915_WRITE(PEW + (i * 4), 0);

7838

for (i = 0; i < 3; i++)

7840

for (i = 0; i < 3; i++)

7839

I915_WRITE(DEW + (i * 4), 0);

7841

I915_WRITE(DEW + (i * 4), 0);

7840

7842

7841

/* Program P-state weights to account for frequency power adjustment */

7843

/* Program P-state weights to account for frequency power adjustment */

7842

for (i = 0; i < 16; i++) {

7844

for (i = 0; i < 16; i++) {

7843

u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));

7845

u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));

7844

unsigned long freq = intel_pxfreq(pxvidfreq);

7846

unsigned long freq = intel_pxfreq(pxvidfreq);

7845

unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>

7847

unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>

7846

PXVFREQ_PX_SHIFT;

7848

PXVFREQ_PX_SHIFT;

7847

unsigned long val;

7849

unsigned long val;

7848

7850

7849

val = vid * vid;

7851

val = vid * vid;

7850

val *= (freq / 1000);

7852

val *= (freq / 1000);

7851

val *= 255;

7853

val *= 255;

7852

val /= (127*127*900);

7854

val /= (127*127*900);

7853

if (val > 0xff)

7855

if (val > 0xff)

7854

DRM_ERROR("bad pxval: %ld\n", val);

7856

DRM_ERROR("bad pxval: %ld\n", val);

7855

pxw[i] = val;

7857

pxw[i] = val;

7856

}

7858

}

7857

/* Render standby states get 0 weight */

7859

/* Render standby states get 0 weight */

7858

pxw[14] = 0;

7860

pxw[14] = 0;

7859

pxw[15] = 0;

7861

pxw[15] = 0;

7860

7862

7861

for (i = 0; i < 4; i++) {

7863

for (i = 0; i < 4; i++) {

7862

u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |

7864

u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |

7863

(pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);

7865

(pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);

7864

I915_WRITE(PXW + (i * 4), val);

7866

I915_WRITE(PXW + (i * 4), val);

7865

}

7867

}

7866

7868

7867

/* Adjust magic regs to magic values (more experimental results) */

7869

/* Adjust magic regs to magic values (more experimental results) */

7868

I915_WRITE(OGW0, 0);

7870

I915_WRITE(OGW0, 0);

7869

I915_WRITE(OGW1, 0);

7871

I915_WRITE(OGW1, 0);

7870

I915_WRITE(EG0, 0x00007f00);

7872

I915_WRITE(EG0, 0x00007f00);

7871

I915_WRITE(EG1, 0x0000000e);

7873

I915_WRITE(EG1, 0x0000000e);

7872

I915_WRITE(EG2, 0x000e0000);

7874

I915_WRITE(EG2, 0x000e0000);

7873

I915_WRITE(EG3, 0x68000300);

7875

I915_WRITE(EG3, 0x68000300);

7874

I915_WRITE(EG4, 0x42000000);

7876

I915_WRITE(EG4, 0x42000000);

7875

I915_WRITE(EG5, 0x00140031);

7877

I915_WRITE(EG5, 0x00140031);

7876

I915_WRITE(EG6, 0);

7878

I915_WRITE(EG6, 0);

7877

I915_WRITE(EG7, 0);

7879

I915_WRITE(EG7, 0);

7878

7880

7879

for (i = 0; i < 8; i++)

7881

for (i = 0; i < 8; i++)

7880

I915_WRITE(PXWL + (i * 4), 0);

7882

I915_WRITE(PXWL + (i * 4), 0);

7881

7883

7882

/* Enable PMON + select events */

7884

/* Enable PMON + select events */

7883

I915_WRITE(ECR, 0x80000019);

7885

I915_WRITE(ECR, 0x80000019);

7884

7886

7885

lcfuse = I915_READ(LCFUSE02);

7887

lcfuse = I915_READ(LCFUSE02);

7886

7888

7887

dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);

7889

dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);

7888

}

7890

}

7889

7891

7890

static bool intel_enable_rc6(struct drm_device *dev)

7892

static bool intel_enable_rc6(struct drm_device *dev)

7891

{

7893

{

7892

/*

7894

/*

7893

* Respect the kernel parameter if it is set

7895

* Respect the kernel parameter if it is set

7894

*/

7896

*/

7895

if (i915_enable_rc6 >= 0)

7897

if (i915_enable_rc6 >= 0)

7896

return i915_enable_rc6;

7898

return i915_enable_rc6;

7897

7899

7898

/*

7900

/*

7899

* Disable RC6 on Ironlake

7901

* Disable RC6 on Ironlake

7900

*/

7902

*/

7901

if (INTEL_INFO(dev)->gen == 5)

7903

if (INTEL_INFO(dev)->gen == 5)

7902

return 0;

7904

return 0;

7903

7905

7904

/*

7906

/*

7905

* Enable rc6 on Sandybridge if DMA remapping is disabled

7907

* Enable rc6 on Sandybridge if DMA remapping is disabled

7906

*/

7908

*/

7907

if (INTEL_INFO(dev)->gen == 6) {

7909

if (INTEL_INFO(dev)->gen == 6) {

7908

DRM_DEBUG_DRIVER("Sandybridge: intel_iommu_enabled %s -- RC6 %sabled\n",

7910

DRM_DEBUG_DRIVER("Sandybridge: intel_iommu_enabled %s -- RC6 %sabled\n",

7909

intel_iommu_enabled ? "true" : "false",

7911

intel_iommu_enabled ? "true" : "false",

7910

!intel_iommu_enabled ? "en" : "dis");

7912

!intel_iommu_enabled ? "en" : "dis");

7911

return !intel_iommu_enabled;

7913

return !intel_iommu_enabled;

7912

}

7914

}

7913

DRM_DEBUG_DRIVER("RC6 enabled\n");

7915

DRM_DEBUG_DRIVER("RC6 enabled\n");

7914

return 1;

7916

return 1;

7915

}

7917

}

7916

7918

7917

void gen6_enable_rps(struct drm_i915_private *dev_priv)

7919

void gen6_enable_rps(struct drm_i915_private *dev_priv)

7918

{

7920

{

7919

u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);

7921

u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);

7920

u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);

7922

u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);

7921

u32 pcu_mbox, rc6_mask = 0;

7923

u32 pcu_mbox, rc6_mask = 0;

7922

int cur_freq, min_freq, max_freq;

7924

int cur_freq, min_freq, max_freq;

7923

int i;

7925

int i;

7924

7926

7925

/* Here begins a magic sequence of register writes to enable

7927

/* Here begins a magic sequence of register writes to enable

7926

* auto-downclocking.

7928

* auto-downclocking.

7927

*

7929

*

7928

* Perhaps there might be some value in exposing these to

7930

* Perhaps there might be some value in exposing these to

7929

* userspace...

7931

* userspace...

7930

*/

7932

*/

7931

I915_WRITE(GEN6_RC_STATE, 0);

7933

I915_WRITE(GEN6_RC_STATE, 0);

7932

mutex_lock(&dev_priv->dev->struct_mutex);

7934

mutex_lock(&dev_priv->dev->struct_mutex);

7933

gen6_gt_force_wake_get(dev_priv);

7935

gen6_gt_force_wake_get(dev_priv);

7934

7936

7935

/* disable the counters and set deterministic thresholds */

7937

/* disable the counters and set deterministic thresholds */

7936

I915_WRITE(GEN6_RC_CONTROL, 0);

7938

I915_WRITE(GEN6_RC_CONTROL, 0);

7937

7939

7938

I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);

7940

I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);

7939

I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);

7941

I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);

7940

I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);

7942

I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);

7941

I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);

7943

I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);

7942

I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);

7944

I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);

7943

7945

7944

for (i = 0; i < I915_NUM_RINGS; i++)

7946

for (i = 0; i < I915_NUM_RINGS; i++)

7945

I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);

7947

I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);

7946

7948

7947

I915_WRITE(GEN6_RC_SLEEP, 0);

7949

I915_WRITE(GEN6_RC_SLEEP, 0);

7948

I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);

7950

I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);

7949

I915_WRITE(GEN6_RC6_THRESHOLD, 50000);

7951

I915_WRITE(GEN6_RC6_THRESHOLD, 50000);

7950

I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);

7952

I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);

7951

I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */

7953

I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */

7952

7954

7953

if (intel_enable_rc6(dev_priv->dev))

7955

if (intel_enable_rc6(dev_priv->dev))

7954

rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |

7956

rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |

7955

GEN6_RC_CTL_RC6_ENABLE;

7957

GEN6_RC_CTL_RC6_ENABLE;

7956

7958

7957

I915_WRITE(GEN6_RC_CONTROL,

7959

I915_WRITE(GEN6_RC_CONTROL,

7958

rc6_mask |

7960

rc6_mask |

7959

GEN6_RC_CTL_EI_MODE(1) |

7961

GEN6_RC_CTL_EI_MODE(1) |

7960

GEN6_RC_CTL_HW_ENABLE);

7962

GEN6_RC_CTL_HW_ENABLE);

7961

7963

7962

I915_WRITE(GEN6_RPNSWREQ,

7964

I915_WRITE(GEN6_RPNSWREQ,

7963

GEN6_FREQUENCY(10) |

7965

GEN6_FREQUENCY(10) |

7964

GEN6_OFFSET(0) |

7966

GEN6_OFFSET(0) |

7965

GEN6_AGGRESSIVE_TURBO);

7967

GEN6_AGGRESSIVE_TURBO);

7966

I915_WRITE(GEN6_RC_VIDEO_FREQ,

7968

I915_WRITE(GEN6_RC_VIDEO_FREQ,

7967

GEN6_FREQUENCY(12));

7969

GEN6_FREQUENCY(12));

7968

7970

7969

I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);

7971

I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);

7970

I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,

7972

I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,

7971

18 << 24 |

7973

18 << 24 |

7972

6 << 16);

7974

6 << 16);

7973

I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);

7975

I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);

7974

I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);

7976

I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);

7975

I915_WRITE(GEN6_RP_UP_EI, 100000);

7977

I915_WRITE(GEN6_RP_UP_EI, 100000);

7976

I915_WRITE(GEN6_RP_DOWN_EI, 5000000);

7978

I915_WRITE(GEN6_RP_DOWN_EI, 5000000);

7977

I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);

7979

I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);

7978

I915_WRITE(GEN6_RP_CONTROL,

7980

I915_WRITE(GEN6_RP_CONTROL,

7979

GEN6_RP_MEDIA_TURBO |

7981

GEN6_RP_MEDIA_TURBO |

7980

GEN6_RP_USE_NORMAL_FREQ |

7982

GEN6_RP_USE_NORMAL_FREQ |

7981

GEN6_RP_MEDIA_IS_GFX |

7983

GEN6_RP_MEDIA_IS_GFX |

7982

GEN6_RP_ENABLE |

7984

GEN6_RP_ENABLE |

7983

GEN6_RP_UP_BUSY_AVG |

7985

GEN6_RP_UP_BUSY_AVG |

7984

GEN6_RP_DOWN_IDLE_CONT);

7986

GEN6_RP_DOWN_IDLE_CONT);

7985

7987

7986

if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,

7988

if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,

7987

500))

7989

500))

7988

DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");

7990

DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");

7989

7991

7990

I915_WRITE(GEN6_PCODE_DATA, 0);

7992

I915_WRITE(GEN6_PCODE_DATA, 0);

7991

I915_WRITE(GEN6_PCODE_MAILBOX,

7993

I915_WRITE(GEN6_PCODE_MAILBOX,

7992

GEN6_PCODE_READY |

7994

GEN6_PCODE_READY |

7993

GEN6_PCODE_WRITE_MIN_FREQ_TABLE);

7995

GEN6_PCODE_WRITE_MIN_FREQ_TABLE);

7994

if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,

7996

if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,

7995

500))

7997

500))

7996

DRM_ERROR("timeout waiting for pcode mailbox to finish\n");

7998

DRM_ERROR("timeout waiting for pcode mailbox to finish\n");

7997

7999

7998

min_freq = (rp_state_cap & 0xff0000) >> 16;

8000

min_freq = (rp_state_cap & 0xff0000) >> 16;

7999

max_freq = rp_state_cap & 0xff;

8001

max_freq = rp_state_cap & 0xff;

8000

cur_freq = (gt_perf_status & 0xff00) >> 8;

8002

cur_freq = (gt_perf_status & 0xff00) >> 8;

8001

8003

8002

/* Check for overclock support */

8004

/* Check for overclock support */

8003

if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,

8005

if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,

8004

500))

8006

500))

8005

DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");

8007

DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");

8006

I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);

8008

I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);

8007

pcu_mbox = I915_READ(GEN6_PCODE_DATA);

8009

pcu_mbox = I915_READ(GEN6_PCODE_DATA);

8008

if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,

8010

if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,

8009

500))

8011

500))

8010

DRM_ERROR("timeout waiting for pcode mailbox to finish\n");

8012

DRM_ERROR("timeout waiting for pcode mailbox to finish\n");

8011

if (pcu_mbox & (1<<31)) { /* OC supported */

8013

if (pcu_mbox & (1<<31)) { /* OC supported */

8012

max_freq = pcu_mbox & 0xff;

8014

max_freq = pcu_mbox & 0xff;

8013

DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);

8015

DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);

8014

}

8016

}

8015

8017

8016

/* In units of 100MHz */

8018

/* In units of 100MHz */

8017

dev_priv->max_delay = max_freq;

8019

dev_priv->max_delay = max_freq;

8018

dev_priv->min_delay = min_freq;

8020

dev_priv->min_delay = min_freq;

8019

dev_priv->cur_delay = cur_freq;

8021

dev_priv->cur_delay = cur_freq;

8020

8022

8021

/* requires MSI enabled */

8023

/* requires MSI enabled */

8022

I915_WRITE(GEN6_PMIER,

8024

I915_WRITE(GEN6_PMIER,

8023

GEN6_PM_MBOX_EVENT |

8025

GEN6_PM_MBOX_EVENT |

8024

GEN6_PM_THERMAL_EVENT |

8026

GEN6_PM_THERMAL_EVENT |

8025

GEN6_PM_RP_DOWN_TIMEOUT |

8027

GEN6_PM_RP_DOWN_TIMEOUT |

8026

GEN6_PM_RP_UP_THRESHOLD |

8028

GEN6_PM_RP_UP_THRESHOLD |

8027

GEN6_PM_RP_DOWN_THRESHOLD |

8029

GEN6_PM_RP_DOWN_THRESHOLD |

8028

GEN6_PM_RP_UP_EI_EXPIRED |

8030

GEN6_PM_RP_UP_EI_EXPIRED |

8029

GEN6_PM_RP_DOWN_EI_EXPIRED);

8031

GEN6_PM_RP_DOWN_EI_EXPIRED);

8030

spin_lock_irq(&dev_priv->rps_lock);

8032

spin_lock_irq(&dev_priv->rps_lock);

8031

WARN_ON(dev_priv->pm_iir != 0);

8033

WARN_ON(dev_priv->pm_iir != 0);

8032

I915_WRITE(GEN6_PMIMR, 0);

8034

I915_WRITE(GEN6_PMIMR, 0);

8033

spin_unlock_irq(&dev_priv->rps_lock);

8035

spin_unlock_irq(&dev_priv->rps_lock);

8034

/* enable all PM interrupts */

8036

/* enable all PM interrupts */

8035

I915_WRITE(GEN6_PMINTRMSK, 0);

8037

I915_WRITE(GEN6_PMINTRMSK, 0);

8036

8038

8037

gen6_gt_force_wake_put(dev_priv);

8039

gen6_gt_force_wake_put(dev_priv);

8038

mutex_unlock(&dev_priv->dev->struct_mutex);

8040

mutex_unlock(&dev_priv->dev->struct_mutex);

8039

}

8041

}

8040

8042

8041

void gen6_update_ring_freq(struct drm_i915_private *dev_priv)

8043

void gen6_update_ring_freq(struct drm_i915_private *dev_priv)

8042

{

8044

{

8043

int min_freq = 15;

8045

int min_freq = 15;

8044

int gpu_freq, ia_freq, max_ia_freq;

8046

int gpu_freq, ia_freq, max_ia_freq;

8045

int scaling_factor = 180;

8047

int scaling_factor = 180;

8046

8048

8047

max_ia_freq = cpufreq_quick_get_max(0);

8049

max_ia_freq = cpufreq_quick_get_max(0);

8048

/*

8050

/*

8049

* Default to measured freq if none found, PCU will ensure we don't go

8051

* Default to measured freq if none found, PCU will ensure we don't go

8050

* over

8052

* over

8051

*/

8053

*/

8052

if (!max_ia_freq)

8054

if (!max_ia_freq)

8053

max_ia_freq = tsc_khz;

8055

max_ia_freq = tsc_khz;

8054

8056

8055

/* Convert from kHz to MHz */

8057

/* Convert from kHz to MHz */

8056

max_ia_freq /= 1000;

8058

max_ia_freq /= 1000;

8057

8059

8058

mutex_lock(&dev_priv->dev->struct_mutex);

8060

mutex_lock(&dev_priv->dev->struct_mutex);

8059

8061

8060

/*

8062

/*

8061

* For each potential GPU frequency, load a ring frequency we'd like

8063

* For each potential GPU frequency, load a ring frequency we'd like

8062

* to use for memory access. We do this by specifying the IA frequency

8064

* to use for memory access. We do this by specifying the IA frequency

8063

* the PCU should use as a reference to determine the ring frequency.

8065

* the PCU should use as a reference to determine the ring frequency.

8064

*/

8066

*/

8065

for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;

8067

for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;

8066

gpu_freq--) {

8068

gpu_freq--) {

8067

int diff = dev_priv->max_delay - gpu_freq;

8069

int diff = dev_priv->max_delay - gpu_freq;

8068

8070

8069

/*

8071

/*

8070

* For GPU frequencies less than 750MHz, just use the lowest

8072

* For GPU frequencies less than 750MHz, just use the lowest

8071

* ring freq.

8073

* ring freq.

8072

*/

8074

*/

8073

if (gpu_freq < min_freq)

8075

if (gpu_freq < min_freq)

8074

ia_freq = 800;

8076

ia_freq = 800;

8075

else

8077

else

8076

ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);

8078

ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);

8077

ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);

8079

ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);

8078

8080

8079

I915_WRITE(GEN6_PCODE_DATA,

8081

I915_WRITE(GEN6_PCODE_DATA,

8080

(ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |

8082

(ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |

8081

gpu_freq);

8083

gpu_freq);

8082

I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |

8084

I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |

8083

GEN6_PCODE_WRITE_MIN_FREQ_TABLE);

8085

GEN6_PCODE_WRITE_MIN_FREQ_TABLE);

8084

if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &

8086

if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &

8085

GEN6_PCODE_READY) == 0, 10)) {

8087

GEN6_PCODE_READY) == 0, 10)) {

8086

DRM_ERROR("pcode write of freq table timed out\n");

8088

DRM_ERROR("pcode write of freq table timed out\n");

8087

continue;

8089

continue;

8088

}

8090

}

8089

}

8091

}

8090

8092

8091

mutex_unlock(&dev_priv->dev->struct_mutex);

8093

mutex_unlock(&dev_priv->dev->struct_mutex);

8092

}

8094

}

8093

8095

8094

static void ironlake_init_clock_gating(struct drm_device *dev)

8096

static void ironlake_init_clock_gating(struct drm_device *dev)

8095

{

8097

{

8096

struct drm_i915_private *dev_priv = dev->dev_private;

8098

struct drm_i915_private *dev_priv = dev->dev_private;

8097

uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;

8099

uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;

8098

8100

8099

/* Required for FBC */

8101

/* Required for FBC */

8100

dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |

8102

dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |

8101

DPFCRUNIT_CLOCK_GATE_DISABLE |

8103

DPFCRUNIT_CLOCK_GATE_DISABLE |

8102

DPFDUNIT_CLOCK_GATE_DISABLE;

8104

DPFDUNIT_CLOCK_GATE_DISABLE;

8103

/* Required for CxSR */

8105

/* Required for CxSR */

8104

dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;

8106

dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;

8105

8107

8106

I915_WRITE(PCH_3DCGDIS0,

8108

I915_WRITE(PCH_3DCGDIS0,

8107

MARIUNIT_CLOCK_GATE_DISABLE |

8109

MARIUNIT_CLOCK_GATE_DISABLE |

8108

SVSMUNIT_CLOCK_GATE_DISABLE);

8110

SVSMUNIT_CLOCK_GATE_DISABLE);

8109

I915_WRITE(PCH_3DCGDIS1,

8111

I915_WRITE(PCH_3DCGDIS1,

8110

VFMUNIT_CLOCK_GATE_DISABLE);

8112

VFMUNIT_CLOCK_GATE_DISABLE);

8111

8113

8112

I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);

8114

I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);

8113

8115

8114

/*

8116

/*

8115

* According to the spec the following bits should be set in

8117

* According to the spec the following bits should be set in

8116

* order to enable memory self-refresh

8118

* order to enable memory self-refresh

8117

* The bit 22/21 of 0x42004

8119

* The bit 22/21 of 0x42004

8118

* The bit 5 of 0x42020

8120

* The bit 5 of 0x42020

8119

* The bit 15 of 0x45000

8121

* The bit 15 of 0x45000

8120

*/

8122

*/

8121

I915_WRITE(ILK_DISPLAY_CHICKEN2,

8123

I915_WRITE(ILK_DISPLAY_CHICKEN2,

8122

(I915_READ(ILK_DISPLAY_CHICKEN2) |

8124

(I915_READ(ILK_DISPLAY_CHICKEN2) |

8123

ILK_DPARB_GATE | ILK_VSDPFD_FULL));

8125

ILK_DPARB_GATE | ILK_VSDPFD_FULL));

8124

I915_WRITE(ILK_DSPCLK_GATE,

8126

I915_WRITE(ILK_DSPCLK_GATE,

8125

(I915_READ(ILK_DSPCLK_GATE) |

8127

(I915_READ(ILK_DSPCLK_GATE) |

8126

ILK_DPARB_CLK_GATE));

8128

ILK_DPARB_CLK_GATE));

8127

I915_WRITE(DISP_ARB_CTL,

8129

I915_WRITE(DISP_ARB_CTL,

8128

(I915_READ(DISP_ARB_CTL) |

8130

(I915_READ(DISP_ARB_CTL) |

8129

DISP_FBC_WM_DIS));

8131

DISP_FBC_WM_DIS));

8130

I915_WRITE(WM3_LP_ILK, 0);

8132

I915_WRITE(WM3_LP_ILK, 0);

8131

I915_WRITE(WM2_LP_ILK, 0);

8133

I915_WRITE(WM2_LP_ILK, 0);

8132

I915_WRITE(WM1_LP_ILK, 0);

8134

I915_WRITE(WM1_LP_ILK, 0);

8133

8135

8134

/*

8136

/*

8135

* Based on the document from hardware guys the following bits

8137

* Based on the document from hardware guys the following bits

8136

* should be set unconditionally in order to enable FBC.

8138

* should be set unconditionally in order to enable FBC.

8137

* The bit 22 of 0x42000

8139

* The bit 22 of 0x42000

8138

* The bit 22 of 0x42004

8140

* The bit 22 of 0x42004

8139

* The bit 7,8,9 of 0x42020.

8141

* The bit 7,8,9 of 0x42020.

8140

*/

8142

*/

8141

if (IS_IRONLAKE_M(dev)) {

8143

if (IS_IRONLAKE_M(dev)) {

8142

I915_WRITE(ILK_DISPLAY_CHICKEN1,

8144

I915_WRITE(ILK_DISPLAY_CHICKEN1,

8143

I915_READ(ILK_DISPLAY_CHICKEN1) |

8145

I915_READ(ILK_DISPLAY_CHICKEN1) |

8144

ILK_FBCQ_DIS);

8146

ILK_FBCQ_DIS);

8145

I915_WRITE(ILK_DISPLAY_CHICKEN2,

8147

I915_WRITE(ILK_DISPLAY_CHICKEN2,

8146

I915_READ(ILK_DISPLAY_CHICKEN2) |

8148

I915_READ(ILK_DISPLAY_CHICKEN2) |

8147

ILK_DPARB_GATE);

8149

ILK_DPARB_GATE);

8148

I915_WRITE(ILK_DSPCLK_GATE,

8150

I915_WRITE(ILK_DSPCLK_GATE,

8149

I915_READ(ILK_DSPCLK_GATE) |

8151

I915_READ(ILK_DSPCLK_GATE) |

8150

ILK_DPFC_DIS1 |

8152

ILK_DPFC_DIS1 |

8151

ILK_DPFC_DIS2 |

8153

ILK_DPFC_DIS2 |

8152

ILK_CLK_FBC);

8154

ILK_CLK_FBC);

8153

}

8155

}

8154

8156

8155

I915_WRITE(ILK_DISPLAY_CHICKEN2,

8157

I915_WRITE(ILK_DISPLAY_CHICKEN2,

8156

I915_READ(ILK_DISPLAY_CHICKEN2) |

8158

I915_READ(ILK_DISPLAY_CHICKEN2) |

8157

ILK_ELPIN_409_SELECT);

8159

ILK_ELPIN_409_SELECT);

8158

I915_WRITE(_3D_CHICKEN2,

8160

I915_WRITE(_3D_CHICKEN2,

8159

_3D_CHICKEN2_WM_READ_PIPELINED << 16 |

8161

_3D_CHICKEN2_WM_READ_PIPELINED << 16 |

8160

_3D_CHICKEN2_WM_READ_PIPELINED);

8162

_3D_CHICKEN2_WM_READ_PIPELINED);

8161

}

8163

}

8162

8164

8163

static void gen6_init_clock_gating(struct drm_device *dev)

8165

static void gen6_init_clock_gating(struct drm_device *dev)

8164

{

8166

{

8165

struct drm_i915_private *dev_priv = dev->dev_private;

8167

struct drm_i915_private *dev_priv = dev->dev_private;

8166

int pipe;

8168

int pipe;

8167

uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;

8169

uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;

8168

8170

8169

I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);

8171

I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);

8170

8172

8171

I915_WRITE(ILK_DISPLAY_CHICKEN2,

8173

I915_WRITE(ILK_DISPLAY_CHICKEN2,

8172

I915_READ(ILK_DISPLAY_CHICKEN2) |

8174

I915_READ(ILK_DISPLAY_CHICKEN2) |

8173

ILK_ELPIN_409_SELECT);

8175

ILK_ELPIN_409_SELECT);

8174

8176

8175

I915_WRITE(WM3_LP_ILK, 0);

8177

I915_WRITE(WM3_LP_ILK, 0);

8176

I915_WRITE(WM2_LP_ILK, 0);

8178

I915_WRITE(WM2_LP_ILK, 0);

8177

I915_WRITE(WM1_LP_ILK, 0);

8179

I915_WRITE(WM1_LP_ILK, 0);

8178

8180

8179

/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock

8181

/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock

8180

* gating disable must be set. Failure to set it results in

8182

* gating disable must be set. Failure to set it results in

8181

* flickering pixels due to Z write ordering failures after

8183

* flickering pixels due to Z write ordering failures after

8182

* some amount of runtime in the Mesa "fire" demo, and Unigine

8184

* some amount of runtime in the Mesa "fire" demo, and Unigine

8183

* Sanctuary and Tropics, and apparently anything else with

8185

* Sanctuary and Tropics, and apparently anything else with

8184

* alpha test or pixel discard.

8186

* alpha test or pixel discard.

8185

*

8187

*

8186

* According to the spec, bit 11 (RCCUNIT) must also be set,

8188

* According to the spec, bit 11 (RCCUNIT) must also be set,

8187

* but we didn't debug actual testcases to find it out.

8189

* but we didn't debug actual testcases to find it out.

8188

*/

8190

*/

8189

I915_WRITE(GEN6_UCGCTL2,

8191

I915_WRITE(GEN6_UCGCTL2,

8190

GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |

8192

GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |

8191

GEN6_RCCUNIT_CLOCK_GATE_DISABLE);

8193

GEN6_RCCUNIT_CLOCK_GATE_DISABLE);

8192

8194

8193

/*

8195

/*

8194

* According to the spec the following bits should be

8196

* According to the spec the following bits should be

8195

* set in order to enable memory self-refresh and fbc:

8197

* set in order to enable memory self-refresh and fbc:

8196

* The bit21 and bit22 of 0x42000

8198

* The bit21 and bit22 of 0x42000

8197

* The bit21 and bit22 of 0x42004

8199

* The bit21 and bit22 of 0x42004

8198

* The bit5 and bit7 of 0x42020

8200

* The bit5 and bit7 of 0x42020

8199

* The bit14 of 0x70180

8201

* The bit14 of 0x70180

8200

* The bit14 of 0x71180

8202

* The bit14 of 0x71180

8201

*/

8203

*/

8202

I915_WRITE(ILK_DISPLAY_CHICKEN1,

8204

I915_WRITE(ILK_DISPLAY_CHICKEN1,

8203

I915_READ(ILK_DISPLAY_CHICKEN1) |

8205

I915_READ(ILK_DISPLAY_CHICKEN1) |

8204

ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);

8206

ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);

8205

I915_WRITE(ILK_DISPLAY_CHICKEN2,

8207

I915_WRITE(ILK_DISPLAY_CHICKEN2,

8206

I915_READ(ILK_DISPLAY_CHICKEN2) |

8208

I915_READ(ILK_DISPLAY_CHICKEN2) |

8207

ILK_DPARB_GATE | ILK_VSDPFD_FULL);

8209

ILK_DPARB_GATE | ILK_VSDPFD_FULL);

8208

I915_WRITE(ILK_DSPCLK_GATE,

8210

I915_WRITE(ILK_DSPCLK_GATE,

8209

I915_READ(ILK_DSPCLK_GATE) |

8211

I915_READ(ILK_DSPCLK_GATE) |

8210

ILK_DPARB_CLK_GATE |

8212

ILK_DPARB_CLK_GATE |

8211

ILK_DPFD_CLK_GATE);

8213

ILK_DPFD_CLK_GATE);

8212

8214

8213

for_each_pipe(pipe) {

8215

for_each_pipe(pipe) {

8214

I915_WRITE(DSPCNTR(pipe),

8216

I915_WRITE(DSPCNTR(pipe),

8215

I915_READ(DSPCNTR(pipe)) |

8217

I915_READ(DSPCNTR(pipe)) |

8216

DISPPLANE_TRICKLE_FEED_DISABLE);

8218

DISPPLANE_TRICKLE_FEED_DISABLE);

8217

intel_flush_display_plane(dev_priv, pipe);

8219

intel_flush_display_plane(dev_priv, pipe);

8218

}

8220

}

8219

}

8221

}

8220

8222

8221

static void ivybridge_init_clock_gating(struct drm_device *dev)

8223

static void ivybridge_init_clock_gating(struct drm_device *dev)

8222

{

8224

{

8223

struct drm_i915_private *dev_priv = dev->dev_private;

8225

struct drm_i915_private *dev_priv = dev->dev_private;

8224

int pipe;

8226

int pipe;

8225

uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;

8227

uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;

8226

8228

8227

I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);

8229

I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);

8228

8230

8229

I915_WRITE(WM3_LP_ILK, 0);

8231

I915_WRITE(WM3_LP_ILK, 0);

8230

I915_WRITE(WM2_LP_ILK, 0);

8232

I915_WRITE(WM2_LP_ILK, 0);

8231

I915_WRITE(WM1_LP_ILK, 0);

8233

I915_WRITE(WM1_LP_ILK, 0);

8232

8234

8233

I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);

8235

I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);

8234

8236

8235

for_each_pipe(pipe) {

8237

for_each_pipe(pipe) {

8236

I915_WRITE(DSPCNTR(pipe),

8238

I915_WRITE(DSPCNTR(pipe),

8237

I915_READ(DSPCNTR(pipe)) |

8239

I915_READ(DSPCNTR(pipe)) |

8238

DISPPLANE_TRICKLE_FEED_DISABLE);

8240

DISPPLANE_TRICKLE_FEED_DISABLE);

8239

intel_flush_display_plane(dev_priv, pipe);

8241

intel_flush_display_plane(dev_priv, pipe);

8240

}

8242

}

8241

}

8243

}

8242

8244

8243

static void g4x_init_clock_gating(struct drm_device *dev)

8245

static void g4x_init_clock_gating(struct drm_device *dev)

8244

{

8246

{

8245

struct drm_i915_private *dev_priv = dev->dev_private;

8247

struct drm_i915_private *dev_priv = dev->dev_private;

8246

uint32_t dspclk_gate;

8248

uint32_t dspclk_gate;

8247

8249

8248

I915_WRITE(RENCLK_GATE_D1, 0);

8250

I915_WRITE(RENCLK_GATE_D1, 0);

8249

I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |

8251

I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |

8250

GS_UNIT_CLOCK_GATE_DISABLE |

8252

GS_UNIT_CLOCK_GATE_DISABLE |

8251

CL_UNIT_CLOCK_GATE_DISABLE);

8253

CL_UNIT_CLOCK_GATE_DISABLE);

8252

I915_WRITE(RAMCLK_GATE_D, 0);

8254

I915_WRITE(RAMCLK_GATE_D, 0);

8253

dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |

8255

dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |

8254

OVRUNIT_CLOCK_GATE_DISABLE |

8256

OVRUNIT_CLOCK_GATE_DISABLE |

8255

OVCUNIT_CLOCK_GATE_DISABLE;

8257

OVCUNIT_CLOCK_GATE_DISABLE;

8256

if (IS_GM45(dev))

8258

if (IS_GM45(dev))

8257

dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;

8259

dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;

8258

I915_WRITE(DSPCLK_GATE_D, dspclk_gate);

8260

I915_WRITE(DSPCLK_GATE_D, dspclk_gate);

8259

}

8261

}

8260

8262

8261

static void crestline_init_clock_gating(struct drm_device *dev)

8263

static void crestline_init_clock_gating(struct drm_device *dev)

8262

{

8264

{

8263

struct drm_i915_private *dev_priv = dev->dev_private;

8265

struct drm_i915_private *dev_priv = dev->dev_private;

8264

8266

8265

I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);

8267

I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);

8266

I915_WRITE(RENCLK_GATE_D2, 0);

8268

I915_WRITE(RENCLK_GATE_D2, 0);

8267

I915_WRITE(DSPCLK_GATE_D, 0);

8269

I915_WRITE(DSPCLK_GATE_D, 0);

8268

I915_WRITE(RAMCLK_GATE_D, 0);

8270

I915_WRITE(RAMCLK_GATE_D, 0);

8269

I915_WRITE16(DEUC, 0);

8271

I915_WRITE16(DEUC, 0);

8270

}

8272

}

8271

8273

8272

static void broadwater_init_clock_gating(struct drm_device *dev)

8274

static void broadwater_init_clock_gating(struct drm_device *dev)

8273

{

8275

{

8274

struct drm_i915_private *dev_priv = dev->dev_private;

8276

struct drm_i915_private *dev_priv = dev->dev_private;

8275

8277

8276

I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |

8278

I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |

8277

I965_RCC_CLOCK_GATE_DISABLE |

8279

I965_RCC_CLOCK_GATE_DISABLE |

8278

I965_RCPB_CLOCK_GATE_DISABLE |

8280

I965_RCPB_CLOCK_GATE_DISABLE |

8279

I965_ISC_CLOCK_GATE_DISABLE |

8281

I965_ISC_CLOCK_GATE_DISABLE |

8280

I965_FBC_CLOCK_GATE_DISABLE);

8282

I965_FBC_CLOCK_GATE_DISABLE);

8281

I915_WRITE(RENCLK_GATE_D2, 0);

8283

I915_WRITE(RENCLK_GATE_D2, 0);

8282

}

8284

}

8283

8285

8284

static void gen3_init_clock_gating(struct drm_device *dev)

8286

static void gen3_init_clock_gating(struct drm_device *dev)

8285

{

8287

{

8286

struct drm_i915_private *dev_priv = dev->dev_private;

8288

struct drm_i915_private *dev_priv = dev->dev_private;

8287

u32 dstate = I915_READ(D_STATE);

8289

u32 dstate = I915_READ(D_STATE);

8288

8290

8289

dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |

8291

dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |

8290

DSTATE_DOT_CLOCK_GATING;

8292

DSTATE_DOT_CLOCK_GATING;

8291

I915_WRITE(D_STATE, dstate);

8293

I915_WRITE(D_STATE, dstate);

8292

}

8294

}

8293

8295

8294

static void i85x_init_clock_gating(struct drm_device *dev)

8296

static void i85x_init_clock_gating(struct drm_device *dev)

8295

{

8297

{

8296

struct drm_i915_private *dev_priv = dev->dev_private;

8298

struct drm_i915_private *dev_priv = dev->dev_private;

8297

8299

8298

I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);

8300

I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);

8299

}

8301

}

8300

8302

8301

static void i830_init_clock_gating(struct drm_device *dev)

8303

static void i830_init_clock_gating(struct drm_device *dev)

8302

{

8304

{

8303

struct drm_i915_private *dev_priv = dev->dev_private;

8305

struct drm_i915_private *dev_priv = dev->dev_private;

8304

8306

8305

I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);

8307

I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);

8306

}

8308

}

8307

8309

8308

static void ibx_init_clock_gating(struct drm_device *dev)

8310

static void ibx_init_clock_gating(struct drm_device *dev)

8309

{

8311

{

8310

struct drm_i915_private *dev_priv = dev->dev_private;

8312

struct drm_i915_private *dev_priv = dev->dev_private;

8311

8313

8312

/*

8314

/*

8313

* On Ibex Peak and Cougar Point, we need to disable clock

8315

* On Ibex Peak and Cougar Point, we need to disable clock

8314

* gating for the panel power sequencer or it will fail to

8316

* gating for the panel power sequencer or it will fail to

8315

* start up when no ports are active.

8317

* start up when no ports are active.

8316

*/

8318

*/

8317

I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);

8319

I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);

8318

}

8320

}

8319

8321

8320

static void cpt_init_clock_gating(struct drm_device *dev)

8322

static void cpt_init_clock_gating(struct drm_device *dev)

8321

{

8323

{

8322

struct drm_i915_private *dev_priv = dev->dev_private;

8324

struct drm_i915_private *dev_priv = dev->dev_private;

8323

int pipe;

8325

int pipe;

8324

8326

8325

/*

8327

/*

8326

* On Ibex Peak and Cougar Point, we need to disable clock

8328

* On Ibex Peak and Cougar Point, we need to disable clock

8327

* gating for the panel power sequencer or it will fail to

8329

* gating for the panel power sequencer or it will fail to

8328

* start up when no ports are active.

8330

* start up when no ports are active.

8329

*/

8331

*/

8330

I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);

8332

I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);

8331

I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |

8333

I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |

8332

DPLS_EDP_PPS_FIX_DIS);

8334

DPLS_EDP_PPS_FIX_DIS);

8333

/* Without this, mode sets may fail silently on FDI */

8335

/* Without this, mode sets may fail silently on FDI */

8334

for_each_pipe(pipe)

8336

for_each_pipe(pipe)

8335

I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);

8337

I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);

8336

}

8338

}

8337

8339

8338

static void ironlake_teardown_rc6(struct drm_device *dev)

8340

static void ironlake_teardown_rc6(struct drm_device *dev)

8339

{

8341

{

8340

struct drm_i915_private *dev_priv = dev->dev_private;

8342

struct drm_i915_private *dev_priv = dev->dev_private;

8341

8343

8342

if (dev_priv->renderctx) {

8344

if (dev_priv->renderctx) {

8343

i915_gem_object_unpin(dev_priv->renderctx);

8345

i915_gem_object_unpin(dev_priv->renderctx);

8344

drm_gem_object_unreference(&dev_priv->renderctx->base);

8346

drm_gem_object_unreference(&dev_priv->renderctx->base);

8345

dev_priv->renderctx = NULL;

8347

dev_priv->renderctx = NULL;

8346

}

8348

}

8347

8349

8348

if (dev_priv->pwrctx) {

8350

if (dev_priv->pwrctx) {

8349

i915_gem_object_unpin(dev_priv->pwrctx);

8351

i915_gem_object_unpin(dev_priv->pwrctx);

8350

drm_gem_object_unreference(&dev_priv->pwrctx->base);

8352

drm_gem_object_unreference(&dev_priv->pwrctx->base);

8351

dev_priv->pwrctx = NULL;

8353

dev_priv->pwrctx = NULL;

8352

}

8354

}

8353

}

8355

}

8354

8356

8355

static void ironlake_disable_rc6(struct drm_device *dev)

8357

static void ironlake_disable_rc6(struct drm_device *dev)

8356

{

8358

{

8357

struct drm_i915_private *dev_priv = dev->dev_private;

8359

struct drm_i915_private *dev_priv = dev->dev_private;

8358

8360

8359

if (I915_READ(PWRCTXA)) {

8361

if (I915_READ(PWRCTXA)) {

8360

/* Wake the GPU, prevent RC6, then restore RSTDBYCTL */

8362

/* Wake the GPU, prevent RC6, then restore RSTDBYCTL */

8361

I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);

8363

I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);

8362

wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),

8364

wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),

8363

50);

8365

50);

8364

8366

8365

I915_WRITE(PWRCTXA, 0);

8367

I915_WRITE(PWRCTXA, 0);

8366

POSTING_READ(PWRCTXA);

8368

POSTING_READ(PWRCTXA);

8367

8369

8368

I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);

8370

I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);

8369

POSTING_READ(RSTDBYCTL);

8371

POSTING_READ(RSTDBYCTL);

8370

}

8372

}

8371

8373

8372

ironlake_teardown_rc6(dev);

8374

ironlake_teardown_rc6(dev);

8373

}

8375

}

8374

8376

8375

static int ironlake_setup_rc6(struct drm_device *dev)

8377

static int ironlake_setup_rc6(struct drm_device *dev)

8376

{

8378

{

8377

struct drm_i915_private *dev_priv = dev->dev_private;

8379

struct drm_i915_private *dev_priv = dev->dev_private;

8378

8380

8379

if (dev_priv->renderctx == NULL)

8381

if (dev_priv->renderctx == NULL)

8380

dev_priv->renderctx = intel_alloc_context_page(dev);

8382

dev_priv->renderctx = intel_alloc_context_page(dev);

8381

if (!dev_priv->renderctx)

8383

if (!dev_priv->renderctx)

8382

return -ENOMEM;

8384

return -ENOMEM;

8383

8385

8384

if (dev_priv->pwrctx == NULL)

8386

if (dev_priv->pwrctx == NULL)

8385

dev_priv->pwrctx = intel_alloc_context_page(dev);

8387

dev_priv->pwrctx = intel_alloc_context_page(dev);

8386

if (!dev_priv->pwrctx) {

8388

if (!dev_priv->pwrctx) {

8387

ironlake_teardown_rc6(dev);

8389

ironlake_teardown_rc6(dev);

8388

return -ENOMEM;

8390

return -ENOMEM;

8389

}

8391

}

8390

8392

8391

return 0;

8393

return 0;

8392

}

8394

}

8393

8395

8394

void ironlake_enable_rc6(struct drm_device *dev)

8396

void ironlake_enable_rc6(struct drm_device *dev)

8395

{

8397

{

8396

struct drm_i915_private *dev_priv = dev->dev_private;

8398

struct drm_i915_private *dev_priv = dev->dev_private;

8397

int ret;

8399

int ret;

8398

8400

8399

/* rc6 disabled by default due to repeated reports of hanging during

8401

/* rc6 disabled by default due to repeated reports of hanging during

8400

* boot and resume.

8402

* boot and resume.

8401

*/

8403

*/

8402

if (!intel_enable_rc6(dev))

8404

if (!intel_enable_rc6(dev))

8403

return;

8405

return;

8404

8406

8405

mutex_lock(&dev->struct_mutex);

8407

mutex_lock(&dev->struct_mutex);

8406

ret = ironlake_setup_rc6(dev);

8408

ret = ironlake_setup_rc6(dev);

8407

if (ret) {

8409

if (ret) {

8408

mutex_unlock(&dev->struct_mutex);

8410

mutex_unlock(&dev->struct_mutex);

8409

return;

8411

return;

8410

}

8412

}

8411

8413

8412

/*

8414

/*

8413

* GPU can automatically power down the render unit if given a page

8415

* GPU can automatically power down the render unit if given a page

8414

* to save state.

8416

* to save state.

8415

*/

8417

*/

8416

ret = BEGIN_LP_RING(6);

8418

ret = BEGIN_LP_RING(6);

8417

if (ret) {

8419

if (ret) {

8418

ironlake_teardown_rc6(dev);

8420

ironlake_teardown_rc6(dev);

8419

mutex_unlock(&dev->struct_mutex);

8421

mutex_unlock(&dev->struct_mutex);

8420

return;

8422

return;

8421

}

8423

}

8422

8424

8423

OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);

8425

OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);

8424

OUT_RING(MI_SET_CONTEXT);

8426

OUT_RING(MI_SET_CONTEXT);

8425

OUT_RING(dev_priv->renderctx->gtt_offset |

8427

OUT_RING(dev_priv->renderctx->gtt_offset |

8426

MI_MM_SPACE_GTT |

8428

MI_MM_SPACE_GTT |

8427

MI_SAVE_EXT_STATE_EN |

8429

MI_SAVE_EXT_STATE_EN |

8428

MI_RESTORE_EXT_STATE_EN |

8430

MI_RESTORE_EXT_STATE_EN |

8429

MI_RESTORE_INHIBIT);

8431

MI_RESTORE_INHIBIT);

8430

OUT_RING(MI_SUSPEND_FLUSH);

8432

OUT_RING(MI_SUSPEND_FLUSH);

8431

OUT_RING(MI_NOOP);

8433

OUT_RING(MI_NOOP);

8432

OUT_RING(MI_FLUSH);

8434

OUT_RING(MI_FLUSH);

8433

ADVANCE_LP_RING();

8435

ADVANCE_LP_RING();

8434

8436

8435

/*

8437

/*

8436

* Wait for the command parser to advance past MI_SET_CONTEXT. The HW

8438

* Wait for the command parser to advance past MI_SET_CONTEXT. The HW

8437

* does an implicit flush, combined with MI_FLUSH above, it should be

8439

* does an implicit flush, combined with MI_FLUSH above, it should be

8438

* safe to assume that renderctx is valid

8440

* safe to assume that renderctx is valid

8439

*/

8441

*/

8440

ret = intel_wait_ring_idle(LP_RING(dev_priv));

8442

ret = intel_wait_ring_idle(LP_RING(dev_priv));

8441

if (ret) {

8443

if (ret) {

8442

DRM_ERROR("failed to enable ironlake power power savings\n");

8444

DRM_ERROR("failed to enable ironlake power power savings\n");

8443

ironlake_teardown_rc6(dev);

8445

ironlake_teardown_rc6(dev);

8444

mutex_unlock(&dev->struct_mutex);

8446

mutex_unlock(&dev->struct_mutex);

8445

return;

8447

return;

8446

}

8448

}

8447

8449

8448

I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);

8450

I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);

8449

I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);

8451

I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);

8450

mutex_unlock(&dev->struct_mutex);

8452

mutex_unlock(&dev->struct_mutex);

8451

}

8453

}

8452

8454

8453

void intel_init_clock_gating(struct drm_device *dev)

8455

void intel_init_clock_gating(struct drm_device *dev)

8454

{

8456

{

8455

struct drm_i915_private *dev_priv = dev->dev_private;

8457

struct drm_i915_private *dev_priv = dev->dev_private;

8456

8458

8457

dev_priv->display.init_clock_gating(dev);

8459

dev_priv->display.init_clock_gating(dev);

8458

8460

8459

if (dev_priv->display.init_pch_clock_gating)

8461

if (dev_priv->display.init_pch_clock_gating)

8460

dev_priv->display.init_pch_clock_gating(dev);

8462

dev_priv->display.init_pch_clock_gating(dev);

8461

}

8463

}

8462

8464

8463

/* Set up chip specific display functions */

8465

/* Set up chip specific display functions */

8464

static void intel_init_display(struct drm_device *dev)

8466

static void intel_init_display(struct drm_device *dev)

8465

{

8467

{

8466

struct drm_i915_private *dev_priv = dev->dev_private;

8468

struct drm_i915_private *dev_priv = dev->dev_private;

8467

8469

8468

/* We always want a DPMS function */

8470

/* We always want a DPMS function */

8469

if (HAS_PCH_SPLIT(dev)) {

8471

if (HAS_PCH_SPLIT(dev)) {

8470

dev_priv->display.dpms = ironlake_crtc_dpms;

8472

dev_priv->display.dpms = ironlake_crtc_dpms;

8471

dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;

8473

dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;

8472

dev_priv->display.update_plane = ironlake_update_plane;

8474

dev_priv->display.update_plane = ironlake_update_plane;

8473

} else {

8475

} else {

8474

dev_priv->display.dpms = i9xx_crtc_dpms;

8476

dev_priv->display.dpms = i9xx_crtc_dpms;

8475

dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;

8477

dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;

8476

dev_priv->display.update_plane = i9xx_update_plane;

8478

dev_priv->display.update_plane = i9xx_update_plane;

8477

}

8479

}

8478

8480

8479

if (I915_HAS_FBC(dev)) {

8481

if (I915_HAS_FBC(dev)) {

8480

if (HAS_PCH_SPLIT(dev)) {

8482

if (HAS_PCH_SPLIT(dev)) {

8481

dev_priv->display.fbc_enabled = ironlake_fbc_enabled;

8483

dev_priv->display.fbc_enabled = ironlake_fbc_enabled;

8482

dev_priv->display.enable_fbc = ironlake_enable_fbc;

8484

dev_priv->display.enable_fbc = ironlake_enable_fbc;

8483

dev_priv->display.disable_fbc = ironlake_disable_fbc;

8485

dev_priv->display.disable_fbc = ironlake_disable_fbc;

8484

} else if (IS_GM45(dev)) {

8486

} else if (IS_GM45(dev)) {

8485

dev_priv->display.fbc_enabled = g4x_fbc_enabled;

8487

dev_priv->display.fbc_enabled = g4x_fbc_enabled;

8486

dev_priv->display.enable_fbc = g4x_enable_fbc;

8488

dev_priv->display.enable_fbc = g4x_enable_fbc;

8487

dev_priv->display.disable_fbc = g4x_disable_fbc;

8489

dev_priv->display.disable_fbc = g4x_disable_fbc;

8488

} else if (IS_CRESTLINE(dev)) {

8490

} else if (IS_CRESTLINE(dev)) {

8489

dev_priv->display.fbc_enabled = i8xx_fbc_enabled;

8491

dev_priv->display.fbc_enabled = i8xx_fbc_enabled;

8490

dev_priv->display.enable_fbc = i8xx_enable_fbc;

8492

dev_priv->display.enable_fbc = i8xx_enable_fbc;

8491

dev_priv->display.disable_fbc = i8xx_disable_fbc;

8493

dev_priv->display.disable_fbc = i8xx_disable_fbc;

8492

}

8494

}

8493

/* 855GM needs testing */

8495

/* 855GM needs testing */

8494

}

8496

}

8495

8497

8496

/* Returns the core display clock speed */

8498

/* Returns the core display clock speed */

8497

if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))

8499

if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))

8498

dev_priv->display.get_display_clock_speed =

8500

dev_priv->display.get_display_clock_speed =

8499

i945_get_display_clock_speed;

8501

i945_get_display_clock_speed;

8500

else if (IS_I915G(dev))

8502

else if (IS_I915G(dev))

8501

dev_priv->display.get_display_clock_speed =

8503

dev_priv->display.get_display_clock_speed =

8502

i915_get_display_clock_speed;

8504

i915_get_display_clock_speed;

8503

else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))

8505

else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))

8504

dev_priv->display.get_display_clock_speed =

8506

dev_priv->display.get_display_clock_speed =

8505

i9xx_misc_get_display_clock_speed;

8507

i9xx_misc_get_display_clock_speed;

8506

else if (IS_I915GM(dev))

8508

else if (IS_I915GM(dev))

8507

dev_priv->display.get_display_clock_speed =

8509

dev_priv->display.get_display_clock_speed =

8508

i915gm_get_display_clock_speed;

8510

i915gm_get_display_clock_speed;

8509

else if (IS_I865G(dev))

8511

else if (IS_I865G(dev))

8510

dev_priv->display.get_display_clock_speed =

8512

dev_priv->display.get_display_clock_speed =

8511

i865_get_display_clock_speed;

8513

i865_get_display_clock_speed;

8512

else if (IS_I85X(dev))

8514

else if (IS_I85X(dev))

8513

dev_priv->display.get_display_clock_speed =

8515

dev_priv->display.get_display_clock_speed =

8514

i855_get_display_clock_speed;

8516

i855_get_display_clock_speed;

8515

else /* 852, 830 */

8517

else /* 852, 830 */

8516

dev_priv->display.get_display_clock_speed =

8518

dev_priv->display.get_display_clock_speed =

8517

i830_get_display_clock_speed;

8519

i830_get_display_clock_speed;

8518

8520

8519

/* For FIFO watermark updates */

8521

/* For FIFO watermark updates */

8520

if (HAS_PCH_SPLIT(dev)) {

8522

if (HAS_PCH_SPLIT(dev)) {

8521

dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;

8523

dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;

8522

dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;

8524

dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;

8523

8525

8524

/* IVB configs may use multi-threaded forcewake */

8526

/* IVB configs may use multi-threaded forcewake */

8525

if (IS_IVYBRIDGE(dev)) {

8527

if (IS_IVYBRIDGE(dev)) {

8526

u32 ecobus;

8528

u32 ecobus;

8527

8529

8528

mutex_lock(&dev->struct_mutex);

8530

mutex_lock(&dev->struct_mutex);

8529

__gen6_gt_force_wake_mt_get(dev_priv);

8531

__gen6_gt_force_wake_mt_get(dev_priv);

8530

ecobus = I915_READ(ECOBUS);

8532

ecobus = I915_READ(ECOBUS);

8531

__gen6_gt_force_wake_mt_put(dev_priv);

8533

__gen6_gt_force_wake_mt_put(dev_priv);

8532

mutex_unlock(&dev->struct_mutex);

8534

mutex_unlock(&dev->struct_mutex);

8533

8535

8534

if (ecobus & FORCEWAKE_MT_ENABLE) {

8536

if (ecobus & FORCEWAKE_MT_ENABLE) {

8535

DRM_DEBUG_KMS("Using MT version of forcewake\n");

8537

DRM_DEBUG_KMS("Using MT version of forcewake\n");

8536

dev_priv->display.force_wake_get =

8538

dev_priv->display.force_wake_get =

8537

__gen6_gt_force_wake_mt_get;

8539

__gen6_gt_force_wake_mt_get;

8538

dev_priv->display.force_wake_put =

8540

dev_priv->display.force_wake_put =

8539

__gen6_gt_force_wake_mt_put;

8541

__gen6_gt_force_wake_mt_put;

8540

}

8542

}

8541

}

8543

}

8542

8544

8543

if (HAS_PCH_IBX(dev))

8545

if (HAS_PCH_IBX(dev))

8544

dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;

8546

dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;

8545

else if (HAS_PCH_CPT(dev))

8547

else if (HAS_PCH_CPT(dev))

8546

dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;

8548

dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;

8547

8549

8548

if (IS_GEN5(dev)) {

8550

if (IS_GEN5(dev)) {

8549

if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)

8551

if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)

8550

dev_priv->display.update_wm = ironlake_update_wm;

8552

dev_priv->display.update_wm = ironlake_update_wm;

8551

else {

8553

else {

8552

DRM_DEBUG_KMS("Failed to get proper latency. "

8554

DRM_DEBUG_KMS("Failed to get proper latency. "

8553

"Disable CxSR\n");

8555

"Disable CxSR\n");

8554

dev_priv->display.update_wm = NULL;

8556

dev_priv->display.update_wm = NULL;

8555

}

8557

}

8556

dev_priv->display.fdi_link_train = ironlake_fdi_link_train;

8558

dev_priv->display.fdi_link_train = ironlake_fdi_link_train;

8557

dev_priv->display.init_clock_gating = ironlake_init_clock_gating;

8559

dev_priv->display.init_clock_gating = ironlake_init_clock_gating;

8558

dev_priv->display.write_eld = ironlake_write_eld;

8560

dev_priv->display.write_eld = ironlake_write_eld;

8559

} else if (IS_GEN6(dev)) {

8561

} else if (IS_GEN6(dev)) {

8560

if (SNB_READ_WM0_LATENCY()) {

8562

if (SNB_READ_WM0_LATENCY()) {

8561

dev_priv->display.update_wm = sandybridge_update_wm;

8563

dev_priv->display.update_wm = sandybridge_update_wm;

8562

} else {

8564

} else {

8563

DRM_DEBUG_KMS("Failed to read display plane latency. "

8565

DRM_DEBUG_KMS("Failed to read display plane latency. "

8564

"Disable CxSR\n");

8566

"Disable CxSR\n");

8565

dev_priv->display.update_wm = NULL;

8567

dev_priv->display.update_wm = NULL;

8566

}

8568

}

8567

dev_priv->display.fdi_link_train = gen6_fdi_link_train;

8569

dev_priv->display.fdi_link_train = gen6_fdi_link_train;

8568

dev_priv->display.init_clock_gating = gen6_init_clock_gating;

8570

dev_priv->display.init_clock_gating = gen6_init_clock_gating;

8569

dev_priv->display.write_eld = ironlake_write_eld;

8571

dev_priv->display.write_eld = ironlake_write_eld;

8570

} else if (IS_IVYBRIDGE(dev)) {

8572

} else if (IS_IVYBRIDGE(dev)) {

8571

/* FIXME: detect B0+ stepping and use auto training */

8573

/* FIXME: detect B0+ stepping and use auto training */

8572

dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;

8574

dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;

8573

if (SNB_READ_WM0_LATENCY()) {

8575

if (SNB_READ_WM0_LATENCY()) {

8574

dev_priv->display.update_wm = sandybridge_update_wm;

8576

dev_priv->display.update_wm = sandybridge_update_wm;

8575

} else {

8577

} else {

8576

DRM_DEBUG_KMS("Failed to read display plane latency. "

8578

DRM_DEBUG_KMS("Failed to read display plane latency. "

8577

"Disable CxSR\n");

8579

"Disable CxSR\n");

8578

dev_priv->display.update_wm = NULL;

8580

dev_priv->display.update_wm = NULL;

8579

}

8581

}

8580

dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;

8582

dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;

8581

dev_priv->display.write_eld = ironlake_write_eld;

8583

dev_priv->display.write_eld = ironlake_write_eld;

8582

} else

8584

} else

8583

dev_priv->display.update_wm = NULL;

8585

dev_priv->display.update_wm = NULL;

8584

} else if (IS_PINEVIEW(dev)) {

8586

} else if (IS_PINEVIEW(dev)) {

8585

if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),

8587

if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),

8586

dev_priv->is_ddr3,

8588

dev_priv->is_ddr3,

8587

dev_priv->fsb_freq,

8589

dev_priv->fsb_freq,

8588

dev_priv->mem_freq)) {

8590

dev_priv->mem_freq)) {

8589

DRM_INFO("failed to find known CxSR latency "

8591

DRM_INFO("failed to find known CxSR latency "

8590

"(found ddr%s fsb freq %d, mem freq %d), "

8592

"(found ddr%s fsb freq %d, mem freq %d), "

8591

"disabling CxSR\n",

8593

"disabling CxSR\n",

8592

(dev_priv->is_ddr3 == 1) ? "3" : "2",

8594

(dev_priv->is_ddr3 == 1) ? "3" : "2",

8593

dev_priv->fsb_freq, dev_priv->mem_freq);

8595

dev_priv->fsb_freq, dev_priv->mem_freq);

8594

/* Disable CxSR and never update its watermark again */

8596

/* Disable CxSR and never update its watermark again */

8595

pineview_disable_cxsr(dev);

8597

pineview_disable_cxsr(dev);

8596

dev_priv->display.update_wm = NULL;

8598

dev_priv->display.update_wm = NULL;

8597

} else

8599

} else

8598

dev_priv->display.update_wm = pineview_update_wm;

8600

dev_priv->display.update_wm = pineview_update_wm;

8599

dev_priv->display.init_clock_gating = gen3_init_clock_gating;

8601

dev_priv->display.init_clock_gating = gen3_init_clock_gating;

8600

} else if (IS_G4X(dev)) {

8602

} else if (IS_G4X(dev)) {

8601

dev_priv->display.write_eld = g4x_write_eld;

8603

dev_priv->display.write_eld = g4x_write_eld;

8602

dev_priv->display.update_wm = g4x_update_wm;

8604

dev_priv->display.update_wm = g4x_update_wm;

8603

dev_priv->display.init_clock_gating = g4x_init_clock_gating;

8605

dev_priv->display.init_clock_gating = g4x_init_clock_gating;

8604

} else if (IS_GEN4(dev)) {

8606

} else if (IS_GEN4(dev)) {

8605

dev_priv->display.update_wm = i965_update_wm;

8607

dev_priv->display.update_wm = i965_update_wm;

8606

if (IS_CRESTLINE(dev))

8608

if (IS_CRESTLINE(dev))

8607

dev_priv->display.init_clock_gating = crestline_init_clock_gating;

8609

dev_priv->display.init_clock_gating = crestline_init_clock_gating;

8608

else if (IS_BROADWATER(dev))

8610

else if (IS_BROADWATER(dev))

8609

dev_priv->display.init_clock_gating = broadwater_init_clock_gating;

8611

dev_priv->display.init_clock_gating = broadwater_init_clock_gating;

8610

} else if (IS_GEN3(dev)) {

8612

} else if (IS_GEN3(dev)) {

8611

dev_priv->display.update_wm = i9xx_update_wm;

8613

dev_priv->display.update_wm = i9xx_update_wm;

8612

dev_priv->display.get_fifo_size = i9xx_get_fifo_size;

8614

dev_priv->display.get_fifo_size = i9xx_get_fifo_size;

8613

dev_priv->display.init_clock_gating = gen3_init_clock_gating;

8615

dev_priv->display.init_clock_gating = gen3_init_clock_gating;

8614

} else if (IS_I865G(dev)) {

8616

} else if (IS_I865G(dev)) {

8615

dev_priv->display.update_wm = i830_update_wm;

8617

dev_priv->display.update_wm = i830_update_wm;

8616

dev_priv->display.init_clock_gating = i85x_init_clock_gating;

8618

dev_priv->display.init_clock_gating = i85x_init_clock_gating;

8617

dev_priv->display.get_fifo_size = i830_get_fifo_size;

8619

dev_priv->display.get_fifo_size = i830_get_fifo_size;

8618

} else if (IS_I85X(dev)) {

8620

} else if (IS_I85X(dev)) {

8619

dev_priv->display.update_wm = i9xx_update_wm;

8621

dev_priv->display.update_wm = i9xx_update_wm;

8620

dev_priv->display.get_fifo_size = i85x_get_fifo_size;

8622

dev_priv->display.get_fifo_size = i85x_get_fifo_size;

8621

dev_priv->display.init_clock_gating = i85x_init_clock_gating;

8623

dev_priv->display.init_clock_gating = i85x_init_clock_gating;

8622

} else {

8624

} else {

8623

dev_priv->display.update_wm = i830_update_wm;

8625

dev_priv->display.update_wm = i830_update_wm;

8624

dev_priv->display.init_clock_gating = i830_init_clock_gating;

8626

dev_priv->display.init_clock_gating = i830_init_clock_gating;

8625

if (IS_845G(dev))

8627

if (IS_845G(dev))

8626

dev_priv->display.get_fifo_size = i845_get_fifo_size;

8628

dev_priv->display.get_fifo_size = i845_get_fifo_size;

8627

else

8629

else

8628

dev_priv->display.get_fifo_size = i830_get_fifo_size;

8630

dev_priv->display.get_fifo_size = i830_get_fifo_size;

8629

}

8631

}

8630

8632

8631

/* Default just returns -ENODEV to indicate unsupported */

8633

/* Default just returns -ENODEV to indicate unsupported */

8632

dev_priv->display.queue_flip = intel_default_queue_flip;

8634

dev_priv->display.queue_flip = intel_default_queue_flip;

8633

8635

8634

switch (INTEL_INFO(dev)->gen) {

8636

switch (INTEL_INFO(dev)->gen) {

8635

case 2:

8637

case 2:

8636

dev_priv->display.queue_flip = intel_gen2_queue_flip;

8638

dev_priv->display.queue_flip = intel_gen2_queue_flip;

8637

break;

8639

break;

8638

8640

8639

case 3:

8641

case 3:

8640

dev_priv->display.queue_flip = intel_gen3_queue_flip;

8642

dev_priv->display.queue_flip = intel_gen3_queue_flip;

8641

break;

8643

break;

8642

8644

8643

case 4:

8645

case 4:

8644

case 5:

8646

case 5:

8645

dev_priv->display.queue_flip = intel_gen4_queue_flip;

8647

dev_priv->display.queue_flip = intel_gen4_queue_flip;

8646

break;

8648

break;

8647

8649

8648

case 6:

8650

case 6:

8649

dev_priv->display.queue_flip = intel_gen6_queue_flip;

8651

dev_priv->display.queue_flip = intel_gen6_queue_flip;

8650

break;

8652

break;

8651

case 7:

8653

case 7:

8652

dev_priv->display.queue_flip = intel_gen7_queue_flip;

8654

dev_priv->display.queue_flip = intel_gen7_queue_flip;

8653

break;

8655

break;

8654

}

8656

}

8655

}

8657

}

8656

8658

8657

/*

8659

/*

8658

* Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,

8660

* Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,

8659

* resume, or other times. This quirk makes sure that's the case for

8661

* resume, or other times. This quirk makes sure that's the case for

8660

* affected systems.

8662

* affected systems.

8661

*/

8663

*/

8662

static void quirk_pipea_force(struct drm_device *dev)

8664

static void quirk_pipea_force(struct drm_device *dev)

8663

{

8665

{

8664

struct drm_i915_private *dev_priv = dev->dev_private;

8666

struct drm_i915_private *dev_priv = dev->dev_private;

8665

8667

8666

dev_priv->quirks |= QUIRK_PIPEA_FORCE;

8668

dev_priv->quirks |= QUIRK_PIPEA_FORCE;

8667

DRM_DEBUG_DRIVER("applying pipe a force quirk\n");

8669

DRM_DEBUG_DRIVER("applying pipe a force quirk\n");

8668

}

8670

}

8669

8671

8670

/*

8672

/*

8671

* Some machines (Lenovo U160) do not work with SSC on LVDS for some reason

8673

* Some machines (Lenovo U160) do not work with SSC on LVDS for some reason

8672

*/

8674

*/

8673

static void quirk_ssc_force_disable(struct drm_device *dev)

8675

static void quirk_ssc_force_disable(struct drm_device *dev)

8674

{

8676

{

8675

struct drm_i915_private *dev_priv = dev->dev_private;

8677

struct drm_i915_private *dev_priv = dev->dev_private;

8676

dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;

8678

dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;

8677

}

8679

}

8678

8680

8679

struct intel_quirk {

8681

struct intel_quirk {

8680

int device;

8682

int device;

8681

int subsystem_vendor;

8683

int subsystem_vendor;

8682

int subsystem_device;

8684

int subsystem_device;

8683

void (*hook)(struct drm_device *dev);

8685

void (*hook)(struct drm_device *dev);

8684

};

8686

};

8685

8687

8686

struct intel_quirk intel_quirks[] = {

8688

struct intel_quirk intel_quirks[] = {

8687

/* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */

8689

/* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */

8688

{ 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },

8690

{ 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },

8689

/* HP Mini needs pipe A force quirk (LP: #322104) */

8691

/* HP Mini needs pipe A force quirk (LP: #322104) */

8690

{ 0x27ae, 0x103c, 0x361a, quirk_pipea_force },

8692

{ 0x27ae, 0x103c, 0x361a, quirk_pipea_force },

8691

8693

8692

/* Thinkpad R31 needs pipe A force quirk */

8694

/* Thinkpad R31 needs pipe A force quirk */

8693

{ 0x3577, 0x1014, 0x0505, quirk_pipea_force },

8695

{ 0x3577, 0x1014, 0x0505, quirk_pipea_force },

8694

/* Toshiba Protege R-205, S-209 needs pipe A force quirk */

8696

/* Toshiba Protege R-205, S-209 needs pipe A force quirk */

8695

{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },

8697

{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },

8696

8698

8697

/* ThinkPad X30 needs pipe A force quirk (LP: #304614) */

8699

/* ThinkPad X30 needs pipe A force quirk (LP: #304614) */

8698

{ 0x3577, 0x1014, 0x0513, quirk_pipea_force },

8700

{ 0x3577, 0x1014, 0x0513, quirk_pipea_force },

8699

/* ThinkPad X40 needs pipe A force quirk */

8701

/* ThinkPad X40 needs pipe A force quirk */

8700

8702

8701

/* ThinkPad T60 needs pipe A force quirk (bug #16494) */

8703

/* ThinkPad T60 needs pipe A force quirk (bug #16494) */

8702

{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },

8704

{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },

8703

8705

8704

/* 855 & before need to leave pipe A & dpll A up */

8706

/* 855 & before need to leave pipe A & dpll A up */

8705

{ 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },

8707

{ 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },

8706

{ 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },

8708

{ 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },

8707

8709

8708

/* Lenovo U160 cannot use SSC on LVDS */

8710

/* Lenovo U160 cannot use SSC on LVDS */

8709

{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },

8711

{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },

8710

8712

8711

/* Sony Vaio Y cannot use SSC on LVDS */

8713

/* Sony Vaio Y cannot use SSC on LVDS */

8712

{ 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },

8714

{ 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },

8713

};

8715

};

8714

8716

8715

static void intel_init_quirks(struct drm_device *dev)

8717

static void intel_init_quirks(struct drm_device *dev)

8716

{

8718

{

8717

struct pci_dev *d = dev->pdev;

8719

struct pci_dev *d = dev->pdev;

8718

int i;

8720

int i;

8719

8721

8720

for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {

8722

for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {

8721

struct intel_quirk *q = &intel_quirks[i];

8723

struct intel_quirk *q = &intel_quirks[i];

8722

8724

8723

if (d->device == q->device &&

8725

if (d->device == q->device &&

8724

(d->subsystem_vendor == q->subsystem_vendor ||

8726

(d->subsystem_vendor == q->subsystem_vendor ||

8725

q->subsystem_vendor == PCI_ANY_ID) &&

8727

q->subsystem_vendor == PCI_ANY_ID) &&

8726

(d->subsystem_device == q->subsystem_device ||

8728

(d->subsystem_device == q->subsystem_device ||

8727

q->subsystem_device == PCI_ANY_ID))

8729

q->subsystem_device == PCI_ANY_ID))

8728

q->hook(dev);

8730

q->hook(dev);

8729

}

8731

}

8730

}

8732

}

8731

8733

8732

/* Disable the VGA plane that we never use */

8734

/* Disable the VGA plane that we never use */

8733

static void i915_disable_vga(struct drm_device *dev)

8735

static void i915_disable_vga(struct drm_device *dev)

8734

{

8736

{

8735

struct drm_i915_private *dev_priv = dev->dev_private;

8737

struct drm_i915_private *dev_priv = dev->dev_private;

8736

u8 sr1;

8738

u8 sr1;

8737

u32 vga_reg;

8739

u32 vga_reg;

8738

8740

8739

if (HAS_PCH_SPLIT(dev))

8741

if (HAS_PCH_SPLIT(dev))

8740

vga_reg = CPU_VGACNTRL;

8742

vga_reg = CPU_VGACNTRL;

8741

else

8743

else

8742

vga_reg = VGACNTRL;

8744

vga_reg = VGACNTRL;

8743

8745

8744

vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);

8746

vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);

8745

outb(1, VGA_SR_INDEX);

8747

outb(1, VGA_SR_INDEX);

8746

sr1 = inb(VGA_SR_DATA);

8748

sr1 = inb(VGA_SR_DATA);

8747

outb(sr1 | 1<<5, VGA_SR_DATA);

8749

outb(sr1 | 1<<5, VGA_SR_DATA);

8748

vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);

8750

vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);

8749

udelay(300);

8751

udelay(300);

8750

8752

8751

I915_WRITE(vga_reg, VGA_DISP_DISABLE);

8753

I915_WRITE(vga_reg, VGA_DISP_DISABLE);

8752

POSTING_READ(vga_reg);

8754

POSTING_READ(vga_reg);

8753

}

8755

}

8754

8756

8755

void intel_modeset_init(struct drm_device *dev)

8757

void intel_modeset_init(struct drm_device *dev)

8756

{

8758

{

8757

struct drm_i915_private *dev_priv = dev->dev_private;

8759

struct drm_i915_private *dev_priv = dev->dev_private;

8758

int i;

8760

int i;

8759

8761

8760

drm_mode_config_init(dev);

8762

drm_mode_config_init(dev);

8761

8763

8762

dev->mode_config.min_width = 0;

8764

dev->mode_config.min_width = 0;

8763

dev->mode_config.min_height = 0;

8765

dev->mode_config.min_height = 0;

8764

8766

8765

dev->mode_config.funcs = (void *)&intel_mode_funcs;

8767

dev->mode_config.funcs = (void *)&intel_mode_funcs;

8766

8768

8767

intel_init_quirks(dev);

8769

intel_init_quirks(dev);

8768

8770

8769

intel_init_display(dev);

8771

intel_init_display(dev);

8770

8772

8771

if (IS_GEN2(dev)) {

8773

if (IS_GEN2(dev)) {

8772

dev->mode_config.max_width = 2048;

8774

dev->mode_config.max_width = 2048;

8773

dev->mode_config.max_height = 2048;

8775

dev->mode_config.max_height = 2048;

8774

} else if (IS_GEN3(dev)) {

8776

} else if (IS_GEN3(dev)) {

8775

dev->mode_config.max_width = 4096;

8777

dev->mode_config.max_width = 4096;

8776

dev->mode_config.max_height = 4096;

8778

dev->mode_config.max_height = 4096;

8777

} else {

8779

} else {

8778

dev->mode_config.max_width = 8192;

8780

dev->mode_config.max_width = 8192;

8779

dev->mode_config.max_height = 8192;

8781

dev->mode_config.max_height = 8192;

8780

}

8782

}

8781

dev->mode_config.fb_base = dev->agp->base;

8783

dev->mode_config.fb_base = dev->agp->base;

8782

8784

8783

DRM_DEBUG_KMS("%d display pipe%s available.\n",

8785

DRM_DEBUG_KMS("%d display pipe%s available.\n",

8784

dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");

8786

dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");

8785

8787

8786

for (i = 0; i < dev_priv->num_pipe; i++) {

8788

for (i = 0; i < dev_priv->num_pipe; i++) {

8787

intel_crtc_init(dev, i);

8789

intel_crtc_init(dev, i);

8788

}

8790

}

8789

8791

8790

/* Just disable it once at startup */

8792

/* Just disable it once at startup */

8791

i915_disable_vga(dev);

8793

i915_disable_vga(dev);

8792

intel_setup_outputs(dev);

8794

intel_setup_outputs(dev);

8793

8795

8794

intel_init_clock_gating(dev);

8796

intel_init_clock_gating(dev);

8795

8797

8796

if (IS_IRONLAKE_M(dev)) {

8798

if (IS_IRONLAKE_M(dev)) {

8797

ironlake_enable_drps(dev);

8799

ironlake_enable_drps(dev);

8798

intel_init_emon(dev);

8800

intel_init_emon(dev);

8799

}

8801

}

8800

8802

8801

if (IS_GEN6(dev) || IS_GEN7(dev)) {

8803

if (IS_GEN6(dev) || IS_GEN7(dev)) {

8802

gen6_enable_rps(dev_priv);

8804

gen6_enable_rps(dev_priv);

8803

gen6_update_ring_freq(dev_priv);

8805

gen6_update_ring_freq(dev_priv);

8804

}

8806

}

8805

8807

8806

INIT_WORK(&dev_priv->idle_work, intel_idle_update);

8808

INIT_WORK(&dev_priv->idle_work, intel_idle_update);

8807

setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,

8809

setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,

8808

(unsigned long)dev);

8810

(unsigned long)dev);

8809

}

8811

}

8810

8812

8811

void intel_modeset_gem_init(struct drm_device *dev)

8813

void intel_modeset_gem_init(struct drm_device *dev)

8812

{

8814

{

8813

if (IS_IRONLAKE_M(dev))

8815

if (IS_IRONLAKE_M(dev))

8814

ironlake_enable_rc6(dev);

8816

ironlake_enable_rc6(dev);

8815

8817

8816

intel_setup_overlay(dev);

8818

intel_setup_overlay(dev);

8817

}

8819

}

8818

8820

8819

void intel_modeset_cleanup(struct drm_device *dev)

8821

void intel_modeset_cleanup(struct drm_device *dev)

8820

{

8822

{

8821

struct drm_i915_private *dev_priv = dev->dev_private;

8823

struct drm_i915_private *dev_priv = dev->dev_private;

8822

struct drm_crtc *crtc;

8824

struct drm_crtc *crtc;

8823

struct intel_crtc *intel_crtc;

8825

struct intel_crtc *intel_crtc;

8824

8826

8825

drm_kms_helper_poll_fini(dev);

8827

drm_kms_helper_poll_fini(dev);

8826

mutex_lock(&dev->struct_mutex);

8828

mutex_lock(&dev->struct_mutex);

8827

8829

8828

intel_unregister_dsm_handler();

8830

intel_unregister_dsm_handler();

8829

8831

8830

8832

8831

list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {

8833

list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {

8832

/* Skip inactive CRTCs */

8834

/* Skip inactive CRTCs */

8833

if (!crtc->fb)

8835

if (!crtc->fb)

8834

continue;

8836

continue;

8835

8837

8836

intel_crtc = to_intel_crtc(crtc);

8838

intel_crtc = to_intel_crtc(crtc);

8837

intel_increase_pllclock(crtc);

8839

intel_increase_pllclock(crtc);

8838

}

8840

}

8839

8841

8840

intel_disable_fbc(dev);

8842

intel_disable_fbc(dev);

8841

8843

8842

if (IS_IRONLAKE_M(dev))

8844

if (IS_IRONLAKE_M(dev))

8843

ironlake_disable_drps(dev);

8845

ironlake_disable_drps(dev);

8844

if (IS_GEN6(dev) || IS_GEN7(dev))

8846

if (IS_GEN6(dev) || IS_GEN7(dev))

8845

gen6_disable_rps(dev);

8847

gen6_disable_rps(dev);

8846

8848

8847

if (IS_IRONLAKE_M(dev))

8849

if (IS_IRONLAKE_M(dev))

8848

ironlake_disable_rc6(dev);

8850

ironlake_disable_rc6(dev);

8849

8851

8850

mutex_unlock(&dev->struct_mutex);

8852

mutex_unlock(&dev->struct_mutex);

8851

8853

8852

/* Disable the irq before mode object teardown, for the irq might

8854

/* Disable the irq before mode object teardown, for the irq might

8853

* enqueue unpin/hotplug work. */

8855

* enqueue unpin/hotplug work. */

8854

drm_irq_uninstall(dev);

8856

drm_irq_uninstall(dev);

8855

cancel_work_sync(&dev_priv->hotplug_work);

8857

cancel_work_sync(&dev_priv->hotplug_work);

8856

cancel_work_sync(&dev_priv->rps_work);

8858

cancel_work_sync(&dev_priv->rps_work);

8857

8859

8858

/* flush any delayed tasks or pending work */

8860

/* flush any delayed tasks or pending work */

8859

flush_scheduled_work();

8861

flush_scheduled_work();

8860

8862

8861

/* Shut off idle work before the crtcs get freed. */

8863

/* Shut off idle work before the crtcs get freed. */

8862

list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {

8864

list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {

8863

intel_crtc = to_intel_crtc(crtc);

8865

intel_crtc = to_intel_crtc(crtc);

8864

del_timer_sync(&intel_crtc->idle_timer);

8866

del_timer_sync(&intel_crtc->idle_timer);

8865

}

8867

}

8866

del_timer_sync(&dev_priv->idle_timer);

8868

del_timer_sync(&dev_priv->idle_timer);

8867

cancel_work_sync(&dev_priv->idle_work);

8869

cancel_work_sync(&dev_priv->idle_work);

8868

8870

8869

drm_mode_config_cleanup(dev);

8871

drm_mode_config_cleanup(dev);

8870

}

8872

}

8871

8873

8872

/*

8874

/*

8873

* Return which encoder is currently attached for connector.

8875

* Return which encoder is currently attached for connector.

8874

*/

8876

*/

8875

struct drm_encoder *intel_best_encoder(struct drm_connector *connector)

8877

struct drm_encoder *intel_best_encoder(struct drm_connector *connector)

8876

{

8878

{

8877

return &intel_attached_encoder(connector)->base;

8879

return &intel_attached_encoder(connector)->base;

8878

}

8880

}

8879

8881

8880

void intel_connector_attach_encoder(struct intel_connector *connector,

8882

void intel_connector_attach_encoder(struct intel_connector *connector,

8881

struct intel_encoder *encoder)

8883

struct intel_encoder *encoder)

8882

{

8884

{

8883

connector->encoder = encoder;

8885

connector->encoder = encoder;

8884

drm_mode_connector_attach_encoder(&connector->base,

8886

drm_mode_connector_attach_encoder(&connector->base,

8885

&encoder->base);

8887

&encoder->base);

8886

}

8888

}

8887

8889

8888

/*

8890

/*

8889

* set vga decode state - true == enable VGA decode

8891

* set vga decode state - true == enable VGA decode

8890

*/

8892

*/

8891

int intel_modeset_vga_set_state(struct drm_device *dev, bool state)

8893

int intel_modeset_vga_set_state(struct drm_device *dev, bool state)

8892

{

8894

{

8893

struct drm_i915_private *dev_priv = dev->dev_private;

8895

struct drm_i915_private *dev_priv = dev->dev_private;

8894

u16 gmch_ctrl;

8896

u16 gmch_ctrl;

8895

8897

8896

pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);

8898

pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);

8897

if (state)

8899

if (state)

8898

gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;

8900

gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;

8899

else

8901

else

8900

gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;

8902

gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;

8901

pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);

8903

pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);

8902

return 0;

8904

return 0;

8903

}

8905

}

8904

8906

8905

#ifdef CONFIG_DEBUG_FS

8907

#ifdef CONFIG_DEBUG_FS

8906

#include <linux/seq_file.h>

8908

#include <linux/seq_file.h>

8907

8909

8908

struct intel_display_error_state {

8910

struct intel_display_error_state {

8909

struct intel_cursor_error_state {

8911

struct intel_cursor_error_state {

8910

u32 control;

8912

u32 control;

8911

u32 position;

8913

u32 position;

8912

u32 base;

8914

u32 base;

8913

u32 size;

8915

u32 size;

8914

} cursor[2];

8916

} cursor[2];

8915

8917

8916

struct intel_pipe_error_state {

8918

struct intel_pipe_error_state {

8917

u32 conf;

8919

u32 conf;

8918

u32 source;

8920

u32 source;

8919

8921

8920

u32 htotal;

8922

u32 htotal;

8921

u32 hblank;

8923

u32 hblank;

8922

u32 hsync;

8924

u32 hsync;

8923

u32 vtotal;

8925

u32 vtotal;

8924

u32 vblank;

8926

u32 vblank;

8925

u32 vsync;

8927

u32 vsync;

8926

} pipe[2];

8928

} pipe[2];

8927

8929

8928

struct intel_plane_error_state {

8930

struct intel_plane_error_state {

8929

u32 control;

8931

u32 control;

8930

u32 stride;

8932

u32 stride;

8931

u32 size;

8933

u32 size;

8932

u32 pos;

8934

u32 pos;

8933

u32 addr;

8935

u32 addr;

8934

u32 surface;

8936

u32 surface;

8935

u32 tile_offset;

8937

u32 tile_offset;

8936

} plane[2];

8938

} plane[2];

8937

};

8939

};

8938

8940

8939

struct intel_display_error_state *

8941

struct intel_display_error_state *

8940

intel_display_capture_error_state(struct drm_device *dev)

8942

intel_display_capture_error_state(struct drm_device *dev)

8941

{

8943

{

8942

drm_i915_private_t *dev_priv = dev->dev_private;

8944

drm_i915_private_t *dev_priv = dev->dev_private;

8943

struct intel_display_error_state *error;

8945

struct intel_display_error_state *error;

8944

int i;

8946

int i;

8945

8947

8946

error = kmalloc(sizeof(*error), GFP_ATOMIC);

8948

error = kmalloc(sizeof(*error), GFP_ATOMIC);

8947

if (error == NULL)

8949

if (error == NULL)

8948

return NULL;

8950

return NULL;

8949

8951

8950

for (i = 0; i < 2; i++) {

8952

for (i = 0; i < 2; i++) {

8951

error->cursor[i].control = I915_READ(CURCNTR(i));

8953

error->cursor[i].control = I915_READ(CURCNTR(i));

8952

error->cursor[i].position = I915_READ(CURPOS(i));

8954

error->cursor[i].position = I915_READ(CURPOS(i));

8953

error->cursor[i].base = I915_READ(CURBASE(i));

8955

error->cursor[i].base = I915_READ(CURBASE(i));

8954

8956

8955

error->plane[i].control = I915_READ(DSPCNTR(i));

8957

error->plane[i].control = I915_READ(DSPCNTR(i));

8956

error->plane[i].stride = I915_READ(DSPSTRIDE(i));

8958

error->plane[i].stride = I915_READ(DSPSTRIDE(i));

8957

error->plane[i].size = I915_READ(DSPSIZE(i));

8959

error->plane[i].size = I915_READ(DSPSIZE(i));

8958

error->plane[i].pos = I915_READ(DSPPOS(i));

8960

error->plane[i].pos = I915_READ(DSPPOS(i));

8959

error->plane[i].addr = I915_READ(DSPADDR(i));

8961

error->plane[i].addr = I915_READ(DSPADDR(i));

8960

if (INTEL_INFO(dev)->gen >= 4) {

8962

if (INTEL_INFO(dev)->gen >= 4) {

8961

error->plane[i].surface = I915_READ(DSPSURF(i));

8963

error->plane[i].surface = I915_READ(DSPSURF(i));

8962

error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));

8964

error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));

8963

}

8965

}

8964

8966

8965

error->pipe[i].conf = I915_READ(PIPECONF(i));

8967

error->pipe[i].conf = I915_READ(PIPECONF(i));

8966

error->pipe[i].source = I915_READ(PIPESRC(i));

8968

error->pipe[i].source = I915_READ(PIPESRC(i));

8967

error->pipe[i].htotal = I915_READ(HTOTAL(i));

8969

error->pipe[i].htotal = I915_READ(HTOTAL(i));

8968

error->pipe[i].hblank = I915_READ(HBLANK(i));

8970

error->pipe[i].hblank = I915_READ(HBLANK(i));

8969

error->pipe[i].hsync = I915_READ(HSYNC(i));

8971

error->pipe[i].hsync = I915_READ(HSYNC(i));

8970

error->pipe[i].vtotal = I915_READ(VTOTAL(i));

8972

error->pipe[i].vtotal = I915_READ(VTOTAL(i));

8971

error->pipe[i].vblank = I915_READ(VBLANK(i));

8973

error->pipe[i].vblank = I915_READ(VBLANK(i));

8972

error->pipe[i].vsync = I915_READ(VSYNC(i));

8974

error->pipe[i].vsync = I915_READ(VSYNC(i));

8973

}

8975

}

8974

8976

8975

return error;

8977

return error;

8976

}

8978

}

8977

8979

8978

void

8980

void

8979

intel_display_print_error_state(struct seq_file *m,

8981

intel_display_print_error_state(struct seq_file *m,

8980

struct drm_device *dev,

8982

struct drm_device *dev,

8981

struct intel_display_error_state *error)

8983

struct intel_display_error_state *error)

8982

{

8984

{

8983

int i;

8985

int i;

8984

8986

8985

for (i = 0; i < 2; i++) {

8987

for (i = 0; i < 2; i++) {

8986

seq_printf(m, "Pipe [%d]:\n", i);

8988

seq_printf(m, "Pipe [%d]:\n", i);

8987

seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);

8989

seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);

8988

seq_printf(m, " SRC: %08x\n", error->pipe[i].source);

8990

seq_printf(m, " SRC: %08x\n", error->pipe[i].source);

8989

seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);

8991

seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);

8990

seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);

8992

seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);

8991

seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);

8993

seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);

8992

seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);

8994

seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);

8993

seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);

8995

seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);

8994

seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);

8996

seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);

8995

8997

8996

seq_printf(m, "Plane [%d]:\n", i);

8998

seq_printf(m, "Plane [%d]:\n", i);

8997

seq_printf(m, " CNTR: %08x\n", error->plane[i].control);

8999

seq_printf(m, " CNTR: %08x\n", error->plane[i].control);

8998

seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);

9000

seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);

8999

seq_printf(m, " SIZE: %08x\n", error->plane[i].size);

9001

seq_printf(m, " SIZE: %08x\n", error->plane[i].size);

9000

seq_printf(m, " POS: %08x\n", error->plane[i].pos);

9002

seq_printf(m, " POS: %08x\n", error->plane[i].pos);

9001

seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);

9003

seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);

9002

if (INTEL_INFO(dev)->gen >= 4) {

9004

if (INTEL_INFO(dev)->gen >= 4) {

9003

seq_printf(m, " SURF: %08x\n", error->plane[i].surface);

9005

seq_printf(m, " SURF: %08x\n", error->plane[i].surface);

9004

seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);

9006

seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);

9005

}

9007

}

9006

9008

9007

seq_printf(m, "Cursor [%d]:\n", i);

9009

seq_printf(m, "Cursor [%d]:\n", i);

9008

seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);

9010

seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);

9009

seq_printf(m, " POS: %08x\n", error->cursor[i].position);

9011

seq_printf(m, " POS: %08x\n", error->cursor[i].position);

GITLAB

drm/i915: don't set unpin_work if vblank_get fails

 /*
  * Copyright © 2006-2007 Intel Corporation
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice (including the next
  * paragraph) shall be included in all copies or substantial portions of the
  * Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  *
  * Authors:
  *	Eric Anholt <eric@anholt.net>
  */
 #include <linux/cpufreq.h>
 #include <linux/module.h>
 #include <linux/input.h>
 #include <linux/i2c.h>
 #include <linux/kernel.h>
 #include <linux/slab.h>
 #include <linux/vgaarb.h>
 #include <drm/drm_edid.h>
 #include "drmP.h"
 #include "intel_drv.h"
 #include "i915_drm.h"
 #include "i915_drv.h"
 #include "i915_trace.h"
 #include "drm_dp_helper.h"
 #include "drm_crtc_helper.h"
 #include <linux/dma_remapping.h>
 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
 static void intel_update_watermarks(struct drm_device *dev);
 static void intel_increase_pllclock(struct drm_crtc *crtc);
 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
 typedef struct {
 	/* given values */
 	int n;
 	int m1, m2;
 	int p1, p2;
 	/* derived values */
 	int	dot;
 	int	vco;
 	int	m;
 	int	p;
 } intel_clock_t;
 typedef struct {
 	int	min, max;
 } intel_range_t;
 typedef struct {
 	int	dot_limit;
 	int	p2_slow, p2_fast;
 } intel_p2_t;
 #define INTEL_P2_NUM		      2
 typedef struct intel_limit intel_limit_t;
 struct intel_limit {
 	intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 	intel_p2_t	    p2;
 	bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
 			int, int, intel_clock_t *);
 };
 /* FDI */
 #define IRONLAKE_FDI_FREQ		2700000 /* in kHz for mode->clock */
 static bool
 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 		    int target, int refclk, intel_clock_t *best_clock);
 static bool
 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 			int target, int refclk, intel_clock_t *best_clock);
 static bool
 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 		      int target, int refclk, intel_clock_t *best_clock);
 static bool
 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 			   int target, int refclk, intel_clock_t *best_clock);
 static inline u32 /* units of 100MHz */
 intel_fdi_link_freq(struct drm_device *dev)
 {
 	if (IS_GEN5(dev)) {
 		struct drm_i915_private *dev_priv = dev->dev_private;
 		return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 	} else
 		return 27;
 }
 static const intel_limit_t intel_limits_i8xx_dvo = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 930000, .max = 1400000 },
 	.n = { .min = 3, .max = 16 },
 	.m = { .min = 96, .max = 140 },
 	.m1 = { .min = 18, .max = 26 },
 	.m2 = { .min = 6, .max = 16 },
 	.p = { .min = 4, .max = 128 },
 	.p1 = { .min = 2, .max = 33 },
 	.p2 = { .dot_limit = 165000,
 		.p2_slow = 4, .p2_fast = 2 },
 	.find_pll = intel_find_best_PLL,
 };
 static const intel_limit_t intel_limits_i8xx_lvds = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 930000, .max = 1400000 },
 	.n = { .min = 3, .max = 16 },
 	.m = { .min = 96, .max = 140 },
 	.m1 = { .min = 18, .max = 26 },
 	.m2 = { .min = 6, .max = 16 },
 	.p = { .min = 4, .max = 128 },
 	.p1 = { .min = 1, .max = 6 },
 	.p2 = { .dot_limit = 165000,
 		.p2_slow = 14, .p2_fast = 7 },
 	.find_pll = intel_find_best_PLL,
 };
 static const intel_limit_t intel_limits_i9xx_sdvo = {
 	.dot = { .min = 20000, .max = 400000 },
 	.vco = { .min = 1400000, .max = 2800000 },
 	.n = { .min = 1, .max = 6 },
 	.m = { .min = 70, .max = 120 },
 	.m1 = { .min = 10, .max = 22 },
 	.m2 = { .min = 5, .max = 9 },
 	.p = { .min = 5, .max = 80 },
 	.p1 = { .min = 1, .max = 8 },
 	.p2 = { .dot_limit = 200000,
 		.p2_slow = 10, .p2_fast = 5 },
 	.find_pll = intel_find_best_PLL,
 };
 static const intel_limit_t intel_limits_i9xx_lvds = {
 	.dot = { .min = 20000, .max = 400000 },
 	.vco = { .min = 1400000, .max = 2800000 },
 	.n = { .min = 1, .max = 6 },
 	.m = { .min = 70, .max = 120 },
 	.m1 = { .min = 10, .max = 22 },
 	.m2 = { .min = 5, .max = 9 },
 	.p = { .min = 7, .max = 98 },
 	.p1 = { .min = 1, .max = 8 },
 	.p2 = { .dot_limit = 112000,
 		.p2_slow = 14, .p2_fast = 7 },
 	.find_pll = intel_find_best_PLL,
 };
 static const intel_limit_t intel_limits_g4x_sdvo = {
 	.dot = { .min = 25000, .max = 270000 },
 	.vco = { .min = 1750000, .max = 3500000},
 	.n = { .min = 1, .max = 4 },
 	.m = { .min = 104, .max = 138 },
 	.m1 = { .min = 17, .max = 23 },
 	.m2 = { .min = 5, .max = 11 },
 	.p = { .min = 10, .max = 30 },
 	.p1 = { .min = 1, .max = 3},
 	.p2 = { .dot_limit = 270000,
 		.p2_slow = 10,
 		.p2_fast = 10
 	},
 	.find_pll = intel_g4x_find_best_PLL,
 };
 static const intel_limit_t intel_limits_g4x_hdmi = {
 	.dot = { .min = 22000, .max = 400000 },
 	.vco = { .min = 1750000, .max = 3500000},
 	.n = { .min = 1, .max = 4 },
 	.m = { .min = 104, .max = 138 },
 	.m1 = { .min = 16, .max = 23 },
 	.m2 = { .min = 5, .max = 11 },
 	.p = { .min = 5, .max = 80 },
 	.p1 = { .min = 1, .max = 8},
 	.p2 = { .dot_limit = 165000,
 		.p2_slow = 10, .p2_fast = 5 },
 	.find_pll = intel_g4x_find_best_PLL,
 };
 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 	.dot = { .min = 20000, .max = 115000 },
 	.vco = { .min = 1750000, .max = 3500000 },
 	.n = { .min = 1, .max = 3 },
 	.m = { .min = 104, .max = 138 },
 	.m1 = { .min = 17, .max = 23 },
 	.m2 = { .min = 5, .max = 11 },
 	.p = { .min = 28, .max = 112 },
 	.p1 = { .min = 2, .max = 8 },
 	.p2 = { .dot_limit = 0,
 		.p2_slow = 14, .p2_fast = 14
 	},
 	.find_pll = intel_g4x_find_best_PLL,
 };
 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 	.dot = { .min = 80000, .max = 224000 },
 	.vco = { .min = 1750000, .max = 3500000 },
 	.n = { .min = 1, .max = 3 },
 	.m = { .min = 104, .max = 138 },
 	.m1 = { .min = 17, .max = 23 },
 	.m2 = { .min = 5, .max = 11 },
 	.p = { .min = 14, .max = 42 },
 	.p1 = { .min = 2, .max = 6 },
 	.p2 = { .dot_limit = 0,
 		.p2_slow = 7, .p2_fast = 7
 	},
 	.find_pll = intel_g4x_find_best_PLL,
 };
 static const intel_limit_t intel_limits_g4x_display_port = {
 	.dot = { .min = 161670, .max = 227000 },
 	.vco = { .min = 1750000, .max = 3500000},
 	.n = { .min = 1, .max = 2 },
 	.m = { .min = 97, .max = 108 },
 	.m1 = { .min = 0x10, .max = 0x12 },
 	.m2 = { .min = 0x05, .max = 0x06 },
 	.p = { .min = 10, .max = 20 },
 	.p1 = { .min = 1, .max = 2},
 	.p2 = { .dot_limit = 0,
 		.p2_slow = 10, .p2_fast = 10 },
 	.find_pll = intel_find_pll_g4x_dp,
 };
 static const intel_limit_t intel_limits_pineview_sdvo = {
 	.dot = { .min = 20000, .max = 400000},
 	.vco = { .min = 1700000, .max = 3500000 },
 	/* Pineview's Ncounter is a ring counter */
 	.n = { .min = 3, .max = 6 },
 	.m = { .min = 2, .max = 256 },
 	/* Pineview only has one combined m divider, which we treat as m2. */
 	.m1 = { .min = 0, .max = 0 },
 	.m2 = { .min = 0, .max = 254 },
 	.p = { .min = 5, .max = 80 },
 	.p1 = { .min = 1, .max = 8 },
 	.p2 = { .dot_limit = 200000,
 		.p2_slow = 10, .p2_fast = 5 },
 	.find_pll = intel_find_best_PLL,
 };
 static const intel_limit_t intel_limits_pineview_lvds = {
 	.dot = { .min = 20000, .max = 400000 },
 	.vco = { .min = 1700000, .max = 3500000 },
 	.n = { .min = 3, .max = 6 },
 	.m = { .min = 2, .max = 256 },
 	.m1 = { .min = 0, .max = 0 },
 	.m2 = { .min = 0, .max = 254 },
 	.p = { .min = 7, .max = 112 },
 	.p1 = { .min = 1, .max = 8 },
 	.p2 = { .dot_limit = 112000,
 		.p2_slow = 14, .p2_fast = 14 },
 	.find_pll = intel_find_best_PLL,
 };
 /* Ironlake / Sandybridge
  *
  * We calculate clock using (register_value + 2) for N/M1/M2, so here
  * the range value for them is (actual_value - 2).
  */
 static const intel_limit_t intel_limits_ironlake_dac = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 1760000, .max = 3510000 },
 	.n = { .min = 1, .max = 5 },
 	.m = { .min = 79, .max = 127 },
 	.m1 = { .min = 12, .max = 22 },
 	.m2 = { .min = 5, .max = 9 },
 	.p = { .min = 5, .max = 80 },
 	.p1 = { .min = 1, .max = 8 },
 	.p2 = { .dot_limit = 225000,
 		.p2_slow = 10, .p2_fast = 5 },
 	.find_pll = intel_g4x_find_best_PLL,
 };
 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 1760000, .max = 3510000 },
 	.n = { .min = 1, .max = 3 },
 	.m = { .min = 79, .max = 118 },
 	.m1 = { .min = 12, .max = 22 },
 	.m2 = { .min = 5, .max = 9 },
 	.p = { .min = 28, .max = 112 },
 	.p1 = { .min = 2, .max = 8 },
 	.p2 = { .dot_limit = 225000,
 		.p2_slow = 14, .p2_fast = 14 },
 	.find_pll = intel_g4x_find_best_PLL,
 };
 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 1760000, .max = 3510000 },
 	.n = { .min = 1, .max = 3 },
 	.m = { .min = 79, .max = 127 },
 	.m1 = { .min = 12, .max = 22 },
 	.m2 = { .min = 5, .max = 9 },
 	.p = { .min = 14, .max = 56 },
 	.p1 = { .min = 2, .max = 8 },
 	.p2 = { .dot_limit = 225000,
 		.p2_slow = 7, .p2_fast = 7 },
 	.find_pll = intel_g4x_find_best_PLL,
 };
 /* LVDS 100mhz refclk limits. */
 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 1760000, .max = 3510000 },
 	.n = { .min = 1, .max = 2 },
 	.m = { .min = 79, .max = 126 },
 	.m1 = { .min = 12, .max = 22 },
 	.m2 = { .min = 5, .max = 9 },
 	.p = { .min = 28, .max = 112 },
 	.p1 = { .min = 2, .max = 8 },
 	.p2 = { .dot_limit = 225000,
 		.p2_slow = 14, .p2_fast = 14 },
 	.find_pll = intel_g4x_find_best_PLL,
 };
 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 1760000, .max = 3510000 },
 	.n = { .min = 1, .max = 3 },
 	.m = { .min = 79, .max = 126 },
 	.m1 = { .min = 12, .max = 22 },
 	.m2 = { .min = 5, .max = 9 },
 	.p = { .min = 14, .max = 42 },
 	.p1 = { .min = 2, .max = 6 },
 	.p2 = { .dot_limit = 225000,
 		.p2_slow = 7, .p2_fast = 7 },
 	.find_pll = intel_g4x_find_best_PLL,
 };
 static const intel_limit_t intel_limits_ironlake_display_port = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 1760000, .max = 3510000},
 	.n = { .min = 1, .max = 2 },
 	.m = { .min = 81, .max = 90 },
 	.m1 = { .min = 12, .max = 22 },
 	.m2 = { .min = 5, .max = 9 },
 	.p = { .min = 10, .max = 20 },
 	.p1 = { .min = 1, .max = 2},
 	.p2 = { .dot_limit = 0,
 		.p2_slow = 10, .p2_fast = 10 },
 	.find_pll = intel_find_pll_ironlake_dp,
 };
 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 						int refclk)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	const intel_limit_t *limit;
 	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 		if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 		    LVDS_CLKB_POWER_UP) {
 			/* LVDS dual channel */
 			if (refclk == 100000)
 				limit = &intel_limits_ironlake_dual_lvds_100m;
 			else
 				limit = &intel_limits_ironlake_dual_lvds;
 		} else {
 			if (refclk == 100000)
 				limit = &intel_limits_ironlake_single_lvds_100m;
 			else
 				limit = &intel_limits_ironlake_single_lvds;
 		}
 	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 			HAS_eDP)
 		limit = &intel_limits_ironlake_display_port;
 	else
 		limit = &intel_limits_ironlake_dac;
 	return limit;
 }
 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	const intel_limit_t *limit;
 	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 		if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 		    LVDS_CLKB_POWER_UP)
 			/* LVDS with dual channel */
 			limit = &intel_limits_g4x_dual_channel_lvds;
 		else
 			/* LVDS with dual channel */
 			limit = &intel_limits_g4x_single_channel_lvds;
 	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 		   intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 		limit = &intel_limits_g4x_hdmi;
 	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 		limit = &intel_limits_g4x_sdvo;
 	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 		limit = &intel_limits_g4x_display_port;
 	} else /* The option is for other outputs */
 		limit = &intel_limits_i9xx_sdvo;
 	return limit;
 }
 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 {
 	struct drm_device *dev = crtc->dev;
 	const intel_limit_t *limit;
 	if (HAS_PCH_SPLIT(dev))
 		limit = intel_ironlake_limit(crtc, refclk);
 	else if (IS_G4X(dev)) {
 		limit = intel_g4x_limit(crtc);
 	} else if (IS_PINEVIEW(dev)) {
 		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 			limit = &intel_limits_pineview_lvds;
 		else
 			limit = &intel_limits_pineview_sdvo;
 	} else if (!IS_GEN2(dev)) {
 		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 			limit = &intel_limits_i9xx_lvds;
 		else
 			limit = &intel_limits_i9xx_sdvo;
 	} else {
 		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 			limit = &intel_limits_i8xx_lvds;
 		else
 			limit = &intel_limits_i8xx_dvo;
 	}
 	return limit;
 }
 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 static void pineview_clock(int refclk, intel_clock_t *clock)
 {
 	clock->m = clock->m2 + 2;
 	clock->p = clock->p1 * clock->p2;
 	clock->vco = refclk * clock->m / clock->n;
 	clock->dot = clock->vco / clock->p;
 }
 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 {
 	if (IS_PINEVIEW(dev)) {
 		pineview_clock(refclk, clock);
 		return;
 	}
 	clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 	clock->p = clock->p1 * clock->p2;
 	clock->vco = refclk * clock->m / (clock->n + 2);
 	clock->dot = clock->vco / clock->p;
 }
 /**
  * Returns whether any output on the specified pipe is of the specified type
  */
 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_mode_config *mode_config = &dev->mode_config;
 	struct intel_encoder *encoder;
 	list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 		if (encoder->base.crtc == crtc && encoder->type == type)
 			return true;
 	return false;
 }
 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 /**
  * Returns whether the given set of divisors are valid for a given refclk with
  * the given connectors.
  */
 static bool intel_PLL_is_valid(struct drm_device *dev,
 			       const intel_limit_t *limit,
 			       const intel_clock_t *clock)
 {
 	if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 		INTELPllInvalid("p1 out of range\n");
 	if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 		INTELPllInvalid("p out of range\n");
 	if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 		INTELPllInvalid("m2 out of range\n");
 	if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 		INTELPllInvalid("m1 out of range\n");
 	if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 		INTELPllInvalid("m1 <= m2\n");
 	if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 		INTELPllInvalid("m out of range\n");
 	if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 		INTELPllInvalid("n out of range\n");
 	if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 		INTELPllInvalid("vco out of range\n");
 	/* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 	 * connector, etc., rather than just a single range.
 	 */
 	if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 		INTELPllInvalid("dot out of range\n");
 	return true;
 }
 static bool
 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 		    int target, int refclk, intel_clock_t *best_clock)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	intel_clock_t clock;
 	int err = target;
 	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 	    (I915_READ(LVDS)) != 0) {
 		/*
 		 * For LVDS, if the panel is on, just rely on its current
 		 * settings for dual-channel.  We haven't figured out how to
 		 * reliably set up different single/dual channel state, if we
 		 * even can.
 		 */
 		if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 		    LVDS_CLKB_POWER_UP)
 			clock.p2 = limit->p2.p2_fast;
 		else
 			clock.p2 = limit->p2.p2_slow;
 	} else {
 		if (target < limit->p2.dot_limit)
 			clock.p2 = limit->p2.p2_slow;
 		else
 			clock.p2 = limit->p2.p2_fast;
 	}
 	memset(best_clock, 0, sizeof(*best_clock));
 	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 	     clock.m1++) {
 		for (clock.m2 = limit->m2.min;
 		     clock.m2 <= limit->m2.max; clock.m2++) {
 			/* m1 is always 0 in Pineview */
 			if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 				break;
 			for (clock.n = limit->n.min;
 			     clock.n <= limit->n.max; clock.n++) {
 				for (clock.p1 = limit->p1.min;
 					clock.p1 <= limit->p1.max; clock.p1++) {
 					int this_err;
 					intel_clock(dev, refclk, &clock);
 					if (!intel_PLL_is_valid(dev, limit,
 								&clock))
 						continue;
 					this_err = abs(clock.dot - target);
 					if (this_err < err) {
 						*best_clock = clock;
 						err = this_err;
 					}
 				}
 			}
 		}
 	}
 	return (err != target);
 }
 static bool
 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 			int target, int refclk, intel_clock_t *best_clock)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	intel_clock_t clock;
 	int max_n;
 	bool found;
 	/* approximately equals target * 0.00585 */
 	int err_most = (target >> 8) + (target >> 9);
 	found = false;
 	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 		int lvds_reg;
 		if (HAS_PCH_SPLIT(dev))
 			lvds_reg = PCH_LVDS;
 		else
 			lvds_reg = LVDS;
 		if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 		    LVDS_CLKB_POWER_UP)
 			clock.p2 = limit->p2.p2_fast;
 		else
 			clock.p2 = limit->p2.p2_slow;
 	} else {
 		if (target < limit->p2.dot_limit)
 			clock.p2 = limit->p2.p2_slow;
 		else
 			clock.p2 = limit->p2.p2_fast;
 	}
 	memset(best_clock, 0, sizeof(*best_clock));
 	max_n = limit->n.max;
 	/* based on hardware requirement, prefer smaller n to precision */
 	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 		/* based on hardware requirement, prefere larger m1,m2 */
 		for (clock.m1 = limit->m1.max;
 		     clock.m1 >= limit->m1.min; clock.m1--) {
 			for (clock.m2 = limit->m2.max;
 			     clock.m2 >= limit->m2.min; clock.m2--) {
 				for (clock.p1 = limit->p1.max;
 				     clock.p1 >= limit->p1.min; clock.p1--) {
 					int this_err;
 					intel_clock(dev, refclk, &clock);
 					if (!intel_PLL_is_valid(dev, limit,
 								&clock))
 						continue;
 					this_err = abs(clock.dot - target);
 					if (this_err < err_most) {
 						*best_clock = clock;
 						err_most = this_err;
 						max_n = clock.n;
 						found = true;
 					}
 				}
 			}
 		}
 	}
 	return found;
 }
 static bool
 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 			   int target, int refclk, intel_clock_t *best_clock)
 {
 	struct drm_device *dev = crtc->dev;
 	intel_clock_t clock;
 	if (target < 200000) {
 		clock.n = 1;
 		clock.p1 = 2;
 		clock.p2 = 10;
 		clock.m1 = 12;
 		clock.m2 = 9;
 	} else {
 		clock.n = 2;
 		clock.p1 = 1;
 		clock.p2 = 10;
 		clock.m1 = 14;
 		clock.m2 = 8;
 	}
 	intel_clock(dev, refclk, &clock);
 	memcpy(best_clock, &clock, sizeof(intel_clock_t));
 	return true;
 }
 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 static bool
 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 		      int target, int refclk, intel_clock_t *best_clock)
 {
 	intel_clock_t clock;
 	if (target < 200000) {
 		clock.p1 = 2;
 		clock.p2 = 10;
 		clock.n = 2;
 		clock.m1 = 23;
 		clock.m2 = 8;
 	} else {
 		clock.p1 = 1;
 		clock.p2 = 10;
 		clock.n = 1;
 		clock.m1 = 14;
 		clock.m2 = 2;
 	}
 	clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 	clock.p = (clock.p1 * clock.p2);
 	clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 	clock.vco = 0;
 	memcpy(best_clock, &clock, sizeof(intel_clock_t));
 	return true;
 }
 /**
  * intel_wait_for_vblank - wait for vblank on a given pipe
  * @dev: drm device
  * @pipe: pipe to wait for
  *
  * Wait for vblank to occur on a given pipe.  Needed for various bits of
  * mode setting code.
  */
 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int pipestat_reg = PIPESTAT(pipe);
 	/* Clear existing vblank status. Note this will clear any other
 	 * sticky status fields as well.
 	 *
 	 * This races with i915_driver_irq_handler() with the result
 	 * that either function could miss a vblank event.  Here it is not
 	 * fatal, as we will either wait upon the next vblank interrupt or
 	 * timeout.  Generally speaking intel_wait_for_vblank() is only
 	 * called during modeset at which time the GPU should be idle and
 	 * should *not* be performing page flips and thus not waiting on
 	 * vblanks...
 	 * Currently, the result of us stealing a vblank from the irq
 	 * handler is that a single frame will be skipped during swapbuffers.
 	 */
 	I915_WRITE(pipestat_reg,
 		   I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 	/* Wait for vblank interrupt bit to set */
 	if (wait_for(I915_READ(pipestat_reg) &
 		     PIPE_VBLANK_INTERRUPT_STATUS,
 		     50))
 		DRM_DEBUG_KMS("vblank wait timed out\n");
 }
 /*
  * intel_wait_for_pipe_off - wait for pipe to turn off
  * @dev: drm device
  * @pipe: pipe to wait for
  *
  * After disabling a pipe, we can't wait for vblank in the usual way,
  * spinning on the vblank interrupt status bit, since we won't actually
  * see an interrupt when the pipe is disabled.
  *
  * On Gen4 and above:
  *   wait for the pipe register state bit to turn off
  *
  * Otherwise:
  *   wait for the display line value to settle (it usually
  *   ends up stopping at the start of the next frame).
  *
  */
 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (INTEL_INFO(dev)->gen >= 4) {
 		int reg = PIPECONF(pipe);
 		/* Wait for the Pipe State to go off */
 		if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 			     100))
 			DRM_DEBUG_KMS("pipe_off wait timed out\n");
 	} else {
 		u32 last_line;
 		int reg = PIPEDSL(pipe);
 		unsigned long timeout = jiffies + msecs_to_jiffies(100);
 		/* Wait for the display line to settle */
 		do {
 			last_line = I915_READ(reg) & DSL_LINEMASK;
 			mdelay(5);
 		} while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 			 time_after(timeout, jiffies));
 		if (time_after(jiffies, timeout))
 			DRM_DEBUG_KMS("pipe_off wait timed out\n");
 	}
 }
 static const char *state_string(bool enabled)
 {
 	return enabled ? "on" : "off";
 }
 /* Only for pre-ILK configs */
 static void assert_pll(struct drm_i915_private *dev_priv,
 		       enum pipe pipe, bool state)
 {
 	int reg;
 	u32 val;
 	bool cur_state;
 	reg = DPLL(pipe);
 	val = I915_READ(reg);
 	cur_state = !!(val & DPLL_VCO_ENABLE);
 	WARN(cur_state != state,
 	     "PLL state assertion failure (expected %s, current %s)\n",
 	     state_string(state), state_string(cur_state));
 }
 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 /* For ILK+ */
 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 			   enum pipe pipe, bool state)
 {
 	int reg;
 	u32 val;
 	bool cur_state;
 	if (HAS_PCH_CPT(dev_priv->dev)) {
 		u32 pch_dpll;
 		pch_dpll = I915_READ(PCH_DPLL_SEL);
 		/* Make sure the selected PLL is enabled to the transcoder */
 		WARN(!((pch_dpll >> (4 * pipe)) & 8),
 		     "transcoder %d PLL not enabled\n", pipe);
 		/* Convert the transcoder pipe number to a pll pipe number */
 		pipe = (pch_dpll >> (4 * pipe)) & 1;
 	}
 	reg = PCH_DPLL(pipe);
 	val = I915_READ(reg);
 	cur_state = !!(val & DPLL_VCO_ENABLE);
 	WARN(cur_state != state,
 	     "PCH PLL state assertion failure (expected %s, current %s)\n",
 	     state_string(state), state_string(cur_state));
 }
 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 			  enum pipe pipe, bool state)
 {
 	int reg;
 	u32 val;
 	bool cur_state;
 	reg = FDI_TX_CTL(pipe);
 	val = I915_READ(reg);
 	cur_state = !!(val & FDI_TX_ENABLE);
 	WARN(cur_state != state,
 	     "FDI TX state assertion failure (expected %s, current %s)\n",
 	     state_string(state), state_string(cur_state));
 }
 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 			  enum pipe pipe, bool state)
 {
 	int reg;
 	u32 val;
 	bool cur_state;
 	reg = FDI_RX_CTL(pipe);
 	val = I915_READ(reg);
 	cur_state = !!(val & FDI_RX_ENABLE);
 	WARN(cur_state != state,
 	     "FDI RX state assertion failure (expected %s, current %s)\n",
 	     state_string(state), state_string(cur_state));
 }
 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 				      enum pipe pipe)
 {
 	int reg;
 	u32 val;
 	/* ILK FDI PLL is always enabled */
 	if (dev_priv->info->gen == 5)
 		return;
 	reg = FDI_TX_CTL(pipe);
 	val = I915_READ(reg);
 	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 }
 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 				      enum pipe pipe)
 {
 	int reg;
 	u32 val;
 	reg = FDI_RX_CTL(pipe);
 	val = I915_READ(reg);
 	WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
 }
 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 				  enum pipe pipe)
 {
 	int pp_reg, lvds_reg;
 	u32 val;
 	enum pipe panel_pipe = PIPE_A;
 	bool locked = true;
 	if (HAS_PCH_SPLIT(dev_priv->dev)) {
 		pp_reg = PCH_PP_CONTROL;
 		lvds_reg = PCH_LVDS;
 	} else {
 		pp_reg = PP_CONTROL;
 		lvds_reg = LVDS;
 	}
 	val = I915_READ(pp_reg);
 	if (!(val & PANEL_POWER_ON) ||
 	    ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
 		locked = false;
 	if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
 		panel_pipe = PIPE_B;
 	WARN(panel_pipe == pipe && locked,
 	     "panel assertion failure, pipe %c regs locked\n",
 	     pipe_name(pipe));
 }
 static void assert_pipe(struct drm_i915_private *dev_priv,
 			enum pipe pipe, bool state)
 {
 	int reg;
 	u32 val;
 	bool cur_state;
 	reg = PIPECONF(pipe);
 	val = I915_READ(reg);
 	cur_state = !!(val & PIPECONF_ENABLE);
 	WARN(cur_state != state,
 	     "pipe %c assertion failure (expected %s, current %s)\n",
 	     pipe_name(pipe), state_string(state), state_string(cur_state));
 }
 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
 				 enum plane plane)
 {
 	int reg;
 	u32 val;
 	reg = DSPCNTR(plane);
 	val = I915_READ(reg);
 	WARN(!(val & DISPLAY_PLANE_ENABLE),
 	     "plane %c assertion failure, should be active but is disabled\n",
 	     plane_name(plane));
 }
 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 				   enum pipe pipe)
 {
 	int reg, i;
 	u32 val;
 	int cur_pipe;
 	/* Planes are fixed to pipes on ILK+ */
 	if (HAS_PCH_SPLIT(dev_priv->dev))
 		return;
 	/* Need to check both planes against the pipe */
 	for (i = 0; i < 2; i++) {
 		reg = DSPCNTR(i);
 		val = I915_READ(reg);
 		cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
 			DISPPLANE_SEL_PIPE_SHIFT;
 		WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
 		     "plane %c assertion failure, should be off on pipe %c but is still active\n",
 		     plane_name(i), pipe_name(pipe));
 	}
 }
 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 {
 	u32 val;
 	bool enabled;
 	val = I915_READ(PCH_DREF_CONTROL);
 	enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
 			    DREF_SUPERSPREAD_SOURCE_MASK));
 	WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
 }
 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
 				       enum pipe pipe)
 {
 	int reg;
 	u32 val;
 	bool enabled;
 	reg = TRANSCONF(pipe);
 	val = I915_READ(reg);
 	enabled = !!(val & TRANS_ENABLE);
 	WARN(enabled,
 	     "transcoder assertion failed, should be off on pipe %c but is still active\n",
 	     pipe_name(pipe));
 }
 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
 			    enum pipe pipe, u32 port_sel, u32 val)
 {
 	if ((val & DP_PORT_EN) == 0)
 		return false;
 	if (HAS_PCH_CPT(dev_priv->dev)) {
 		u32	trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
 		u32	trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
 		if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
 			return false;
 	} else {
 		if ((val & DP_PIPE_MASK) != (pipe << 30))
 			return false;
 	}
 	return true;
 }
 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
 			      enum pipe pipe, u32 val)
 {
 	if ((val & PORT_ENABLE) == 0)
 		return false;
 	if (HAS_PCH_CPT(dev_priv->dev)) {
 		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
 			return false;
 	} else {
 		if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
 			return false;
 	}
 	return true;
 }
 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
 			      enum pipe pipe, u32 val)
 {
 	if ((val & LVDS_PORT_EN) == 0)
 		return false;
 	if (HAS_PCH_CPT(dev_priv->dev)) {
 		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
 			return false;
 	} else {
 		if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
 			return false;
 	}
 	return true;
 }
 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
 			      enum pipe pipe, u32 val)
 {
 	if ((val & ADPA_DAC_ENABLE) == 0)
 		return false;
 	if (HAS_PCH_CPT(dev_priv->dev)) {
 		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
 			return false;
 	} else {
 		if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
 			return false;
 	}
 	return true;
 }
 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
 				   enum pipe pipe, int reg, u32 port_sel)
 {
 	u32 val = I915_READ(reg);
 	WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
 	     "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
 	     reg, pipe_name(pipe));
 }
 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
 				     enum pipe pipe, int reg)
 {
 	u32 val = I915_READ(reg);
 	WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
 	     "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
 	     reg, pipe_name(pipe));
 }
 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
 				      enum pipe pipe)
 {
 	int reg;
 	u32 val;
 	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
 	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
 	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
 	reg = PCH_ADPA;
 	val = I915_READ(reg);
 	WARN(adpa_pipe_enabled(dev_priv, val, pipe),
 	     "PCH VGA enabled on transcoder %c, should be disabled\n",
 	     pipe_name(pipe));
 	reg = PCH_LVDS;
 	val = I915_READ(reg);
 	WARN(lvds_pipe_enabled(dev_priv, val, pipe),
 	     "PCH LVDS enabled on transcoder %c, should be disabled\n",
 	     pipe_name(pipe));
 	assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
 	assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
 	assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
 }
 /**
  * intel_enable_pll - enable a PLL
  * @dev_priv: i915 private structure
  * @pipe: pipe PLL to enable
  *
  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
  * make sure the PLL reg is writable first though, since the panel write
  * protect mechanism may be enabled.
  *
  * Note!  This is for pre-ILK only.
  */
 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 {
 	int reg;
 	u32 val;
 	/* No really, not for ILK+ */
 	BUG_ON(dev_priv->info->gen >= 5);
 	/* PLL is protected by panel, make sure we can write it */
 	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
 		assert_panel_unlocked(dev_priv, pipe);
 	reg = DPLL(pipe);
 	val = I915_READ(reg);
 	val |= DPLL_VCO_ENABLE;
 	/* We do this three times for luck */
 	I915_WRITE(reg, val);
 	POSTING_READ(reg);
 	udelay(150); /* wait for warmup */
 	I915_WRITE(reg, val);
 	POSTING_READ(reg);
 	udelay(150); /* wait for warmup */
 	I915_WRITE(reg, val);
 	POSTING_READ(reg);
 	udelay(150); /* wait for warmup */
 }
 /**
  * intel_disable_pll - disable a PLL
  * @dev_priv: i915 private structure
  * @pipe: pipe PLL to disable
  *
  * Disable the PLL for @pipe, making sure the pipe is off first.
  *
  * Note!  This is for pre-ILK only.
  */
 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 {
 	int reg;
 	u32 val;
 	/* Don't disable pipe A or pipe A PLLs if needed */
 	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
 		return;
 	/* Make sure the pipe isn't still relying on us */
 	assert_pipe_disabled(dev_priv, pipe);
 	reg = DPLL(pipe);
 	val = I915_READ(reg);
 	val &= ~DPLL_VCO_ENABLE;
 	I915_WRITE(reg, val);
 	POSTING_READ(reg);
 }
 /**
  * intel_enable_pch_pll - enable PCH PLL
  * @dev_priv: i915 private structure
  * @pipe: pipe PLL to enable
  *
  * The PCH PLL needs to be enabled before the PCH transcoder, since it
  * drives the transcoder clock.
  */
 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
 				 enum pipe pipe)
 {
 	int reg;
 	u32 val;
 	if (pipe > 1)
 		return;
 	/* PCH only available on ILK+ */
 	BUG_ON(dev_priv->info->gen < 5);
 	/* PCH refclock must be enabled first */
 	assert_pch_refclk_enabled(dev_priv);
 	reg = PCH_DPLL(pipe);
 	val = I915_READ(reg);
 	val |= DPLL_VCO_ENABLE;
 	I915_WRITE(reg, val);
 	POSTING_READ(reg);
 	udelay(200);
 }
 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
 				  enum pipe pipe)
 {
 	int reg;
 	u32 val;
 	if (pipe > 1)
 		return;
 	/* PCH only available on ILK+ */
 	BUG_ON(dev_priv->info->gen < 5);
 	/* Make sure transcoder isn't still depending on us */
 	assert_transcoder_disabled(dev_priv, pipe);
 	reg = PCH_DPLL(pipe);
 	val = I915_READ(reg);
 	val &= ~DPLL_VCO_ENABLE;
 	I915_WRITE(reg, val);
 	POSTING_READ(reg);
 	udelay(200);
 }
 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
 				    enum pipe pipe)
 {
 	int reg;
 	u32 val;
 	/* PCH only available on ILK+ */
 	BUG_ON(dev_priv->info->gen < 5);
 	/* Make sure PCH DPLL is enabled */
 	assert_pch_pll_enabled(dev_priv, pipe);
 	/* FDI must be feeding us bits for PCH ports */
 	assert_fdi_tx_enabled(dev_priv, pipe);
 	assert_fdi_rx_enabled(dev_priv, pipe);
 	reg = TRANSCONF(pipe);
 	val = I915_READ(reg);
 	if (HAS_PCH_IBX(dev_priv->dev)) {
 		/*
 		 * make the BPC in transcoder be consistent with
 		 * that in pipeconf reg.
 		 */
 		val &= ~PIPE_BPC_MASK;
 		val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
 	}
 	I915_WRITE(reg, val | TRANS_ENABLE);
 	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
 		DRM_ERROR("failed to enable transcoder %d\n", pipe);
 }
 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
 				     enum pipe pipe)
 {
 	int reg;
 	u32 val;
 	/* FDI relies on the transcoder */
 	assert_fdi_tx_disabled(dev_priv, pipe);
 	assert_fdi_rx_disabled(dev_priv, pipe);
 	/* Ports must be off as well */
 	assert_pch_ports_disabled(dev_priv, pipe);
 	reg = TRANSCONF(pipe);
 	val = I915_READ(reg);
 	val &= ~TRANS_ENABLE;
 	I915_WRITE(reg, val);
 	/* wait for PCH transcoder off, transcoder state */
 	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
 		DRM_ERROR("failed to disable transcoder %d\n", pipe);
 }
 /**
  * intel_enable_pipe - enable a pipe, asserting requirements
  * @dev_priv: i915 private structure
  * @pipe: pipe to enable
  * @pch_port: on ILK+, is this pipe driving a PCH port or not
  *
  * Enable @pipe, making sure that various hardware specific requirements
  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
  *
  * @pipe should be %PIPE_A or %PIPE_B.
  *
  * Will wait until the pipe is actually running (i.e. first vblank) before
  * returning.
  */
 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
 			      bool pch_port)
 {
 	int reg;
 	u32 val;
 	/*
 	 * A pipe without a PLL won't actually be able to drive bits from
 	 * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
 	 * need the check.
 	 */
 	if (!HAS_PCH_SPLIT(dev_priv->dev))
 		assert_pll_enabled(dev_priv, pipe);
 	else {
 		if (pch_port) {
 			/* if driving the PCH, we need FDI enabled */
 			assert_fdi_rx_pll_enabled(dev_priv, pipe);
 			assert_fdi_tx_pll_enabled(dev_priv, pipe);
 		}
 		/* FIXME: assert CPU port conditions for SNB+ */
 	}
 	reg = PIPECONF(pipe);
 	val = I915_READ(reg);
 	if (val & PIPECONF_ENABLE)
 		return;
 	I915_WRITE(reg, val | PIPECONF_ENABLE);
 	intel_wait_for_vblank(dev_priv->dev, pipe);
 }
 /**
  * intel_disable_pipe - disable a pipe, asserting requirements
  * @dev_priv: i915 private structure
  * @pipe: pipe to disable
  *
  * Disable @pipe, making sure that various hardware specific requirements
  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
  *
  * @pipe should be %PIPE_A or %PIPE_B.
  *
  * Will wait until the pipe has shut down before returning.
  */
 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
 			       enum pipe pipe)
 {
 	int reg;
 	u32 val;
 	/*
 	 * Make sure planes won't keep trying to pump pixels to us,
 	 * or we might hang the display.
 	 */
 	assert_planes_disabled(dev_priv, pipe);
 	/* Don't disable pipe A or pipe A PLLs if needed */
 	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
 		return;
 	reg = PIPECONF(pipe);
 	val = I915_READ(reg);
 	if ((val & PIPECONF_ENABLE) == 0)
 		return;
 	I915_WRITE(reg, val & ~PIPECONF_ENABLE);
 	intel_wait_for_pipe_off(dev_priv->dev, pipe);
 }
 /*
  * Plane regs are double buffered, going from enabled->disabled needs a
  * trigger in order to latch.  The display address reg provides this.
  */
 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
 				      enum plane plane)
 {
 	I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
 	I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
 }
 /**
  * intel_enable_plane - enable a display plane on a given pipe
  * @dev_priv: i915 private structure
  * @plane: plane to enable
  * @pipe: pipe being fed
  *
  * Enable @plane on @pipe, making sure that @pipe is running first.
  */
 static void intel_enable_plane(struct drm_i915_private *dev_priv,
 			       enum plane plane, enum pipe pipe)
 {
 	int reg;
 	u32 val;
 	/* If the pipe isn't enabled, we can't pump pixels and may hang */
 	assert_pipe_enabled(dev_priv, pipe);
 	reg = DSPCNTR(plane);
 	val = I915_READ(reg);
 	if (val & DISPLAY_PLANE_ENABLE)
 		return;
 	I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
 	intel_flush_display_plane(dev_priv, plane);
 	intel_wait_for_vblank(dev_priv->dev, pipe);
 }
 /**
  * intel_disable_plane - disable a display plane
  * @dev_priv: i915 private structure
  * @plane: plane to disable
  * @pipe: pipe consuming the data
  *
  * Disable @plane; should be an independent operation.
  */
 static void intel_disable_plane(struct drm_i915_private *dev_priv,
 				enum plane plane, enum pipe pipe)
 {
 	int reg;
 	u32 val;
 	reg = DSPCNTR(plane);
 	val = I915_READ(reg);
 	if ((val & DISPLAY_PLANE_ENABLE) == 0)
 		return;
 	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
 	intel_flush_display_plane(dev_priv, plane);
 	intel_wait_for_vblank(dev_priv->dev, pipe);
 }
 static void disable_pch_dp(struct drm_i915_private *dev_priv,
 			   enum pipe pipe, int reg, u32 port_sel)
 {
 	u32 val = I915_READ(reg);
 	if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
 		DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
 		I915_WRITE(reg, val & ~DP_PORT_EN);
 	}
 }
 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
 			     enum pipe pipe, int reg)
 {
 	u32 val = I915_READ(reg);
 	if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
 		DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
 			      reg, pipe);
 		I915_WRITE(reg, val & ~PORT_ENABLE);
 	}
 }
 /* Disable any ports connected to this transcoder */
 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
 				    enum pipe pipe)
 {
 	u32 reg, val;
 	val = I915_READ(PCH_PP_CONTROL);
 	I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
 	disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
 	disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
 	disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
 	reg = PCH_ADPA;
 	val = I915_READ(reg);
 	if (adpa_pipe_enabled(dev_priv, val, pipe))
 		I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
 	reg = PCH_LVDS;
 	val = I915_READ(reg);
 	if (lvds_pipe_enabled(dev_priv, val, pipe)) {
 		DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
 		I915_WRITE(reg, val & ~LVDS_PORT_EN);
 		POSTING_READ(reg);
 		udelay(100);
 	}
 	disable_pch_hdmi(dev_priv, pipe, HDMIB);
 	disable_pch_hdmi(dev_priv, pipe, HDMIC);
 	disable_pch_hdmi(dev_priv, pipe, HDMID);
 }
 static void i8xx_disable_fbc(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 fbc_ctl;
 	/* Disable compression */
 	fbc_ctl = I915_READ(FBC_CONTROL);
 	if ((fbc_ctl & FBC_CTL_EN) == 0)
 		return;
 	fbc_ctl &= ~FBC_CTL_EN;
 	I915_WRITE(FBC_CONTROL, fbc_ctl);
 	/* Wait for compressing bit to clear */
 	if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
 		DRM_DEBUG_KMS("FBC idle timed out\n");
 		return;
 	}
 	DRM_DEBUG_KMS("disabled FBC\n");
 }
 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_framebuffer *fb = crtc->fb;
 	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 	struct drm_i915_gem_object *obj = intel_fb->obj;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int cfb_pitch;
 	int plane, i;
 	u32 fbc_ctl, fbc_ctl2;
 	cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
 	if (fb->pitch < cfb_pitch)
 		cfb_pitch = fb->pitch;
 	/* FBC_CTL wants 64B units */
 	cfb_pitch = (cfb_pitch / 64) - 1;
 	plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
 	/* Clear old tags */
 	for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 		I915_WRITE(FBC_TAG + (i * 4), 0);
 	/* Set it up... */
 	fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 	fbc_ctl2 |= plane;
 	I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 	I915_WRITE(FBC_FENCE_OFF, crtc->y);
 	/* enable it... */
 	fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 	if (IS_I945GM(dev))
 		fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 	fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 	fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 	fbc_ctl |= obj->fence_reg;
 	I915_WRITE(FBC_CONTROL, fbc_ctl);
 	DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
 		      cfb_pitch, crtc->y, intel_crtc->plane);
 }
 static bool i8xx_fbc_enabled(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 }
 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_framebuffer *fb = crtc->fb;
 	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 	struct drm_i915_gem_object *obj = intel_fb->obj;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 	unsigned long stall_watermark = 200;
 	u32 dpfc_ctl;
 	dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
 	dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 	I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
 	I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 		   (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 		   (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 	I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 	/* enable it... */
 	I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
 	DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
 }
 static void g4x_disable_fbc(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 dpfc_ctl;
 	/* Disable compression */
 	dpfc_ctl = I915_READ(DPFC_CONTROL);
 	if (dpfc_ctl & DPFC_CTL_EN) {
 		dpfc_ctl &= ~DPFC_CTL_EN;
 		I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 		DRM_DEBUG_KMS("disabled FBC\n");
 	}
 }
 static bool g4x_fbc_enabled(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 }
 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 blt_ecoskpd;
 	/* Make sure blitter notifies FBC of writes */
 	gen6_gt_force_wake_get(dev_priv);
 	blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 	blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 		GEN6_BLITTER_LOCK_SHIFT;
 	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 	blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 	blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 			 GEN6_BLITTER_LOCK_SHIFT);
 	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 	POSTING_READ(GEN6_BLITTER_ECOSKPD);
 	gen6_gt_force_wake_put(dev_priv);
 }
 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_framebuffer *fb = crtc->fb;
 	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 	struct drm_i915_gem_object *obj = intel_fb->obj;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 	unsigned long stall_watermark = 200;
 	u32 dpfc_ctl;
 	dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 	dpfc_ctl &= DPFC_RESERVED;
 	dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
 	/* Set persistent mode for front-buffer rendering, ala X. */
 	dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
 	dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
 	I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
 	I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 		   (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 		   (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 	I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 	I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
 	/* enable it... */
 	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 	if (IS_GEN6(dev)) {
 		I915_WRITE(SNB_DPFC_CTL_SA,
 			   SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 		I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 		sandybridge_blit_fbc_update(dev);
 	}
 	DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
 }
 static void ironlake_disable_fbc(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 dpfc_ctl;
 	/* Disable compression */
 	dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 	if (dpfc_ctl & DPFC_CTL_EN) {
 		dpfc_ctl &= ~DPFC_CTL_EN;
 		I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 		DRM_DEBUG_KMS("disabled FBC\n");
 	}
 }
 static bool ironlake_fbc_enabled(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 }
 bool intel_fbc_enabled(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (!dev_priv->display.fbc_enabled)
 		return false;
 	return dev_priv->display.fbc_enabled(dev);
 }
 static void intel_fbc_work_fn(struct work_struct *__work)
 {
 	struct intel_fbc_work *work =
 		container_of(to_delayed_work(__work),
 			     struct intel_fbc_work, work);
 	struct drm_device *dev = work->crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	mutex_lock(&dev->struct_mutex);
 	if (work == dev_priv->fbc_work) {
 		/* Double check that we haven't switched fb without cancelling
 		 * the prior work.
 		 */
 		if (work->crtc->fb == work->fb) {
 			dev_priv->display.enable_fbc(work->crtc,
 						     work->interval);
 			dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
 			dev_priv->cfb_fb = work->crtc->fb->base.id;
 			dev_priv->cfb_y = work->crtc->y;
 		}
 		dev_priv->fbc_work = NULL;
 	}
 	mutex_unlock(&dev->struct_mutex);
 	kfree(work);
 }
 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 {
 	if (dev_priv->fbc_work == NULL)
 		return;
 	DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 	/* Synchronisation is provided by struct_mutex and checking of
 	 * dev_priv->fbc_work, so we can perform the cancellation
 	 * entirely asynchronously.
 	 */
 	if (cancel_delayed_work(&dev_priv->fbc_work->work))
 		/* tasklet was killed before being run, clean up */
 		kfree(dev_priv->fbc_work);
 	/* Mark the work as no longer wanted so that if it does
 	 * wake-up (because the work was already running and waiting
 	 * for our mutex), it will discover that is no longer
 	 * necessary to run.
 	 */
 	dev_priv->fbc_work = NULL;
 }
 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 {
 	struct intel_fbc_work *work;
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (!dev_priv->display.enable_fbc)
 		return;
 	intel_cancel_fbc_work(dev_priv);
 	work = kzalloc(sizeof *work, GFP_KERNEL);
 	if (work == NULL) {
 		dev_priv->display.enable_fbc(crtc, interval);
 		return;
 	}
 	work->crtc = crtc;
 	work->fb = crtc->fb;
 	work->interval = interval;
 	INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 	dev_priv->fbc_work = work;
 	DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
 	/* Delay the actual enabling to let pageflipping cease and the
 	 * display to settle before starting the compression. Note that
 	 * this delay also serves a second purpose: it allows for a
 	 * vblank to pass after disabling the FBC before we attempt
 	 * to modify the control registers.
 	 *
 	 * A more complicated solution would involve tracking vblanks
 	 * following the termination of the page-flipping sequence
 	 * and indeed performing the enable as a co-routine and not
 	 * waiting synchronously upon the vblank.
 	 */
 	schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 }
 void intel_disable_fbc(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	intel_cancel_fbc_work(dev_priv);
 	if (!dev_priv->display.disable_fbc)
 		return;
 	dev_priv->display.disable_fbc(dev);
 	dev_priv->cfb_plane = -1;
 }
 /**
  * intel_update_fbc - enable/disable FBC as needed
  * @dev: the drm_device
  *
  * Set up the framebuffer compression hardware at mode set time.  We
  * enable it if possible:
  *   - plane A only (on pre-965)
  *   - no pixel mulitply/line duplication
  *   - no alpha buffer discard
  *   - no dual wide
  *   - framebuffer <= 2048 in width, 1536 in height
  *
  * We can't assume that any compression will take place (worst case),
  * so the compressed buffer has to be the same size as the uncompressed
  * one.  It also must reside (along with the line length buffer) in
  * stolen memory.
  *
  * We need to enable/disable FBC on a global basis.
  */
 static void intel_update_fbc(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_crtc *crtc = NULL, *tmp_crtc;
 	struct intel_crtc *intel_crtc;
 	struct drm_framebuffer *fb;
 	struct intel_framebuffer *intel_fb;
 	struct drm_i915_gem_object *obj;
 	int enable_fbc;
 	DRM_DEBUG_KMS("\n");
 	if (!i915_powersave)
 		return;
 	if (!I915_HAS_FBC(dev))
 		return;
 	/*
 	 * If FBC is already on, we just have to verify that we can
 	 * keep it that way...
 	 * Need to disable if:
 	 *   - more than one pipe is active
 	 *   - changing FBC params (stride, fence, mode)
 	 *   - new fb is too large to fit in compressed buffer
 	 *   - going to an unsupported config (interlace, pixel multiply, etc.)
 	 */
 	list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
 		if (tmp_crtc->enabled && tmp_crtc->fb) {
 			if (crtc) {
 				DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 				dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
 				goto out_disable;
 			}
 			crtc = tmp_crtc;
 		}
 	}
 	if (!crtc || crtc->fb == NULL) {
 		DRM_DEBUG_KMS("no output, disabling\n");
 		dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
 		goto out_disable;
 	}
 	intel_crtc = to_intel_crtc(crtc);
 	fb = crtc->fb;
 	intel_fb = to_intel_framebuffer(fb);
 	obj = intel_fb->obj;
 	enable_fbc = i915_enable_fbc;
 	if (enable_fbc < 0) {
 		DRM_DEBUG_KMS("fbc set to per-chip default\n");
 		enable_fbc = 1;
 		if (INTEL_INFO(dev)->gen <= 5)
 			enable_fbc = 0;
 	}
 	if (!enable_fbc) {
 		DRM_DEBUG_KMS("fbc disabled per module param\n");
 		dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
 		goto out_disable;
 	}
 	if (intel_fb->obj->base.size > dev_priv->cfb_size) {
 		DRM_DEBUG_KMS("framebuffer too large, disabling "
 			      "compression\n");
 		dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
 		goto out_disable;
 	}
 	if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
 	    (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
 		DRM_DEBUG_KMS("mode incompatible with compression, "
 			      "disabling\n");
 		dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
 		goto out_disable;
 	}
 	if ((crtc->mode.hdisplay > 2048) ||
 	    (crtc->mode.vdisplay > 1536)) {
 		DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 		dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
 		goto out_disable;
 	}
 	if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
 		DRM_DEBUG_KMS("plane not 0, disabling compression\n");
 		dev_priv->no_fbc_reason = FBC_BAD_PLANE;
 		goto out_disable;
 	}
 	/* The use of a CPU fence is mandatory in order to detect writes
 	 * by the CPU to the scanout and trigger updates to the FBC.
 	 */
 	if (obj->tiling_mode != I915_TILING_X ||
 	    obj->fence_reg == I915_FENCE_REG_NONE) {
 		DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 		dev_priv->no_fbc_reason = FBC_NOT_TILED;
 		goto out_disable;
 	}
 	/* If the kernel debugger is active, always disable compression */
 	if (in_dbg_master())
 		goto out_disable;
 	/* If the scanout has not changed, don't modify the FBC settings.
 	 * Note that we make the fundamental assumption that the fb->obj
 	 * cannot be unpinned (and have its GTT offset and fence revoked)
 	 * without first being decoupled from the scanout and FBC disabled.
 	 */
 	if (dev_priv->cfb_plane == intel_crtc->plane &&
 	    dev_priv->cfb_fb == fb->base.id &&
 	    dev_priv->cfb_y == crtc->y)
 		return;
 	if (intel_fbc_enabled(dev)) {
 		/* We update FBC along two paths, after changing fb/crtc
 		 * configuration (modeswitching) and after page-flipping
 		 * finishes. For the latter, we know that not only did
 		 * we disable the FBC at the start of the page-flip
 		 * sequence, but also more than one vblank has passed.
 		 *
 		 * For the former case of modeswitching, it is possible
 		 * to switch between two FBC valid configurations
 		 * instantaneously so we do need to disable the FBC
 		 * before we can modify its control registers. We also
 		 * have to wait for the next vblank for that to take
 		 * effect. However, since we delay enabling FBC we can
 		 * assume that a vblank has passed since disabling and
 		 * that we can safely alter the registers in the deferred
 		 * callback.
 		 *
 		 * In the scenario that we go from a valid to invalid
 		 * and then back to valid FBC configuration we have
 		 * no strict enforcement that a vblank occurred since
 		 * disabling the FBC. However, along all current pipe
 		 * disabling paths we do need to wait for a vblank at
 		 * some point. And we wait before enabling FBC anyway.
 		 */
 		DRM_DEBUG_KMS("disabling active FBC for update\n");
 		intel_disable_fbc(dev);
 	}
 	intel_enable_fbc(crtc, 500);
 	return;
 out_disable:
 	/* Multiple disables should be harmless */
 	if (intel_fbc_enabled(dev)) {
 		DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 		intel_disable_fbc(dev);
 	}
 }
 int
 intel_pin_and_fence_fb_obj(struct drm_device *dev,
 			   struct drm_i915_gem_object *obj,
 			   struct intel_ring_buffer *pipelined)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 alignment;
 	int ret;
 	switch (obj->tiling_mode) {
 	case I915_TILING_NONE:
 		if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
 			alignment = 128 * 1024;
 		else if (INTEL_INFO(dev)->gen >= 4)
 			alignment = 4 * 1024;
 		else
 			alignment = 64 * 1024;
 		break;
 	case I915_TILING_X:
 		/* pin() will align the object as required by fence */
 		alignment = 0;
 		break;
 	case I915_TILING_Y:
 		/* FIXME: Is this true? */
 		DRM_ERROR("Y tiled not allowed for scan out buffers\n");
 		return -EINVAL;
 	default:
 		BUG();
 	}
 	dev_priv->mm.interruptible = false;
 	ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
 	if (ret)
 		goto err_interruptible;
 	/* Install a fence for tiled scan-out. Pre-i965 always needs a
 	 * fence, whereas 965+ only requires a fence if using
 	 * framebuffer compression.  For simplicity, we always install
 	 * a fence as the cost is not that onerous.
 	 */
 	if (obj->tiling_mode != I915_TILING_NONE) {
 		ret = i915_gem_object_get_fence(obj, pipelined);
 		if (ret)
 			goto err_unpin;
 	}
 	dev_priv->mm.interruptible = true;
 	return 0;
 err_unpin:
 	i915_gem_object_unpin(obj);
 err_interruptible:
 	dev_priv->mm.interruptible = true;
 	return ret;
 }
 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 			     int x, int y)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_framebuffer *intel_fb;
 	struct drm_i915_gem_object *obj;
 	int plane = intel_crtc->plane;
 	unsigned long Start, Offset;
 	u32 dspcntr;
 	u32 reg;
 	switch (plane) {
 	case 0:
 	case 1:
 		break;
 	default:
 		DRM_ERROR("Can't update plane %d in SAREA\n", plane);
 		return -EINVAL;
 	}
 	intel_fb = to_intel_framebuffer(fb);
 	obj = intel_fb->obj;
 	reg = DSPCNTR(plane);
 	dspcntr = I915_READ(reg);
 	/* Mask out pixel format bits in case we change it */
 	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
 	switch (fb->bits_per_pixel) {
 	case 8:
 		dspcntr |= DISPPLANE_8BPP;
 		break;
 	case 16:
 		if (fb->depth == 15)
 			dspcntr |= DISPPLANE_15_16BPP;
 		else
 			dspcntr |= DISPPLANE_16BPP;
 		break;
 	case 24:
 	case 32:
 		dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
 		break;
 	default:
 		DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
 		return -EINVAL;
 	}
 	if (INTEL_INFO(dev)->gen >= 4) {
 		if (obj->tiling_mode != I915_TILING_NONE)
 			dspcntr |= DISPPLANE_TILED;
 		else
 			dspcntr &= ~DISPPLANE_TILED;
 	}
 	I915_WRITE(reg, dspcntr);
 	Start = obj->gtt_offset;
 	Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
 	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
 		      Start, Offset, x, y, fb->pitch);
 	I915_WRITE(DSPSTRIDE(plane), fb->pitch);
 	if (INTEL_INFO(dev)->gen >= 4) {
 		I915_WRITE(DSPSURF(plane), Start);
 		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
 		I915_WRITE(DSPADDR(plane), Offset);
 	} else
 		I915_WRITE(DSPADDR(plane), Start + Offset);
 	POSTING_READ(reg);
 	return 0;
 }
 static int ironlake_update_plane(struct drm_crtc *crtc,
 				 struct drm_framebuffer *fb, int x, int y)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_framebuffer *intel_fb;
 	struct drm_i915_gem_object *obj;
 	int plane = intel_crtc->plane;
 	unsigned long Start, Offset;
 	u32 dspcntr;
 	u32 reg;
 	switch (plane) {
 	case 0:
 	case 1:
 	case 2:
 		break;
 	default:
 		DRM_ERROR("Can't update plane %d in SAREA\n", plane);
 		return -EINVAL;
 	}
 	intel_fb = to_intel_framebuffer(fb);
 	obj = intel_fb->obj;
 	reg = DSPCNTR(plane);
 	dspcntr = I915_READ(reg);
 	/* Mask out pixel format bits in case we change it */
 	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
 	switch (fb->bits_per_pixel) {
 	case 8:
 		dspcntr |= DISPPLANE_8BPP;
 		break;
 	case 16:
 		if (fb->depth != 16)
 			return -EINVAL;
 		dspcntr |= DISPPLANE_16BPP;
 		break;
 	case 24:
 	case 32:
 		if (fb->depth == 24)
 			dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
 		else if (fb->depth == 30)
 			dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
 		else
 			return -EINVAL;
 		break;
 	default:
 		DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
 		return -EINVAL;
 	}
 	if (obj->tiling_mode != I915_TILING_NONE)
 		dspcntr |= DISPPLANE_TILED;
 	else
 		dspcntr &= ~DISPPLANE_TILED;
 	/* must disable */
 	dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
 	I915_WRITE(reg, dspcntr);
 	Start = obj->gtt_offset;
 	Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
 	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
 		      Start, Offset, x, y, fb->pitch);
 	I915_WRITE(DSPSTRIDE(plane), fb->pitch);
 	I915_WRITE(DSPSURF(plane), Start);
 	I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
 	I915_WRITE(DSPADDR(plane), Offset);
 	POSTING_READ(reg);
 	return 0;
 }
 /* Assume fb object is pinned & idle & fenced and just update base pointers */
 static int
 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 			   int x, int y, enum mode_set_atomic state)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret;
 	ret = dev_priv->display.update_plane(crtc, fb, x, y);
 	if (ret)
 		return ret;
 	intel_update_fbc(dev);
 	intel_increase_pllclock(crtc);
 	return 0;
 }
 static int
 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
 		    struct drm_framebuffer *old_fb)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_master_private *master_priv;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int ret;
 	/* no fb bound */
 	if (!crtc->fb) {
 		DRM_ERROR("No FB bound\n");
 		return 0;
 	}
 	switch (intel_crtc->plane) {
 	case 0:
 	case 1:
 		break;
 	case 2:
 		if (IS_IVYBRIDGE(dev))
 			break;
 		/* fall through otherwise */
 	default:
 		DRM_ERROR("no plane for crtc\n");
 		return -EINVAL;
 	}
 	mutex_lock(&dev->struct_mutex);
 	ret = intel_pin_and_fence_fb_obj(dev,
 					 to_intel_framebuffer(crtc->fb)->obj,
 					 NULL);
 	if (ret != 0) {
 		mutex_unlock(&dev->struct_mutex);
 		DRM_ERROR("pin & fence failed\n");
 		return ret;
 	}
 	if (old_fb) {
 		struct drm_i915_private *dev_priv = dev->dev_private;
 		struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
 		wait_event(dev_priv->pending_flip_queue,
 			   atomic_read(&dev_priv->mm.wedged) ||
 			   atomic_read(&obj->pending_flip) == 0);
 		/* Big Hammer, we also need to ensure that any pending
 		 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
 		 * current scanout is retired before unpinning the old
 		 * framebuffer.
 		 *
 		 * This should only fail upon a hung GPU, in which case we
 		 * can safely continue.
 		 */
 		ret = i915_gem_object_finish_gpu(obj);
 		(void) ret;
 	}
 	ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
 					 LEAVE_ATOMIC_MODE_SET);
 	if (ret) {
 		i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
 		mutex_unlock(&dev->struct_mutex);
 		DRM_ERROR("failed to update base address\n");
 		return ret;
 	}
 	if (old_fb) {
 		intel_wait_for_vblank(dev, intel_crtc->pipe);
 		i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
 	}
 	mutex_unlock(&dev->struct_mutex);
 	if (!dev->primary->master)
 		return 0;
 	master_priv = dev->primary->master->driver_priv;
 	if (!master_priv->sarea_priv)
 		return 0;
 	if (intel_crtc->pipe) {
 		master_priv->sarea_priv->pipeB_x = x;
 		master_priv->sarea_priv->pipeB_y = y;
 	} else {
 		master_priv->sarea_priv->pipeA_x = x;
 		master_priv->sarea_priv->pipeA_y = y;
 	}
 	return 0;
 }
 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 dpa_ctl;
 	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
 	dpa_ctl = I915_READ(DP_A);
 	dpa_ctl &= ~DP_PLL_FREQ_MASK;
 	if (clock < 200000) {
 		u32 temp;
 		dpa_ctl |= DP_PLL_FREQ_160MHZ;
 		/* workaround for 160Mhz:
 		   1) program 0x4600c bits 15:0 = 0x8124
 		   2) program 0x46010 bit 0 = 1
 		   3) program 0x46034 bit 24 = 1
 		   4) program 0x64000 bit 14 = 1
 		   */
 		temp = I915_READ(0x4600c);
 		temp &= 0xffff0000;
 		I915_WRITE(0x4600c, temp | 0x8124);
 		temp = I915_READ(0x46010);
 		I915_WRITE(0x46010, temp | 1);
 		temp = I915_READ(0x46034);
 		I915_WRITE(0x46034, temp | (1 << 24));
 	} else {
 		dpa_ctl |= DP_PLL_FREQ_270MHZ;
 	}
 	I915_WRITE(DP_A, dpa_ctl);
 	POSTING_READ(DP_A);
 	udelay(500);
 }
 static void intel_fdi_normal_train(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	u32 reg, temp;
 	/* enable normal train */
 	reg = FDI_TX_CTL(pipe);
 	temp = I915_READ(reg);
 	if (IS_IVYBRIDGE(dev)) {
 		temp &= ~FDI_LINK_TRAIN_NONE_IVB;
 		temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
 	} else {
 		temp &= ~FDI_LINK_TRAIN_NONE;
 		temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
 	}
 	I915_WRITE(reg, temp);
 	reg = FDI_RX_CTL(pipe);
 	temp = I915_READ(reg);
 	if (HAS_PCH_CPT(dev)) {
 		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
 		temp |= FDI_LINK_TRAIN_NORMAL_CPT;
 	} else {
 		temp &= ~FDI_LINK_TRAIN_NONE;
 		temp |= FDI_LINK_TRAIN_NONE;
 	}
 	I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
 	/* wait one idle pattern time */
 	POSTING_READ(reg);
 	udelay(1000);
 	/* IVB wants error correction enabled */
 	if (IS_IVYBRIDGE(dev))
 		I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
 			   FDI_FE_ERRC_ENABLE);
 }
 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 flags = I915_READ(SOUTH_CHICKEN1);
 	flags |= FDI_PHASE_SYNC_OVR(pipe);
 	I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
 	flags |= FDI_PHASE_SYNC_EN(pipe);
 	I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
 	POSTING_READ(SOUTH_CHICKEN1);
 }
 /* The FDI link training functions for ILK/Ibexpeak. */
 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	int plane = intel_crtc->plane;
 	u32 reg, temp, tries;
 	/* FDI needs bits from pipe & plane first */
 	assert_pipe_enabled(dev_priv, pipe);
 	assert_plane_enabled(dev_priv, plane);
 	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
 	   for train result */
 	reg = FDI_RX_IMR(pipe);
 	temp = I915_READ(reg);
 	temp &= ~FDI_RX_SYMBOL_LOCK;
 	temp &= ~FDI_RX_BIT_LOCK;
 	I915_WRITE(reg, temp);
 	I915_READ(reg);
 	udelay(150);
 	/* enable CPU FDI TX and PCH FDI RX */
 	reg = FDI_TX_CTL(pipe);
 	temp = I915_READ(reg);
 	temp &= ~(7 << 19);
 	temp |= (intel_crtc->fdi_lanes - 1) << 19;
 	temp &= ~FDI_LINK_TRAIN_NONE;
 	temp |= FDI_LINK_TRAIN_PATTERN_1;
 	I915_WRITE(reg, temp | FDI_TX_ENABLE);
 	reg = FDI_RX_CTL(pipe);
 	temp = I915_READ(reg);
 	temp &= ~FDI_LINK_TRAIN_NONE;
 	temp |= FDI_LINK_TRAIN_PATTERN_1;
 	I915_WRITE(reg, temp | FDI_RX_ENABLE);
 	POSTING_READ(reg);
 	udelay(150);
 	/* Ironlake workaround, enable clock pointer after FDI enable*/
 	if (HAS_PCH_IBX(dev)) {
 		I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
 		I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
 			   FDI_RX_PHASE_SYNC_POINTER_EN);
 	}
 	reg = FDI_RX_IIR(pipe);
 	for (tries = 0; tries < 5; tries++) {
 		temp = I915_READ(reg);
 		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
 		if ((temp & FDI_RX_BIT_LOCK)) {
 			DRM_DEBUG_KMS("FDI train 1 done.\n");
 			I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
 			break;
 		}
 	}
 	if (tries == 5)
 		DRM_ERROR("FDI train 1 fail!\n");
 	/* Train 2 */
 	reg = FDI_TX_CTL(pipe);
 	temp = I915_READ(reg);
 	temp &= ~FDI_LINK_TRAIN_NONE;
 	temp |= FDI_LINK_TRAIN_PATTERN_2;
 	I915_WRITE(reg, temp);
 	reg = FDI_RX_CTL(pipe);
 	temp = I915_READ(reg);
 	temp &= ~FDI_LINK_TRAIN_NONE;
 	temp |= FDI_LINK_TRAIN_PATTERN_2;
 	I915_WRITE(reg, temp);
 	POSTING_READ(reg);
 	udelay(150);
 	reg = FDI_RX_IIR(pipe);
 	for (tries = 0; tries < 5; tries++) {
 		temp = I915_READ(reg);
 		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
 		if (temp & FDI_RX_SYMBOL_LOCK) {
 			I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
 			DRM_DEBUG_KMS("FDI train 2 done.\n");
 			break;
 		}
 	}
 	if (tries == 5)
 		DRM_ERROR("FDI train 2 fail!\n");
 	DRM_DEBUG_KMS("FDI train done\n");
 }
 static const int snb_b_fdi_train_param[] = {
 	FDI_LINK_TRAIN_400MV_0DB_SNB_B,
 	FDI_LINK_TRAIN_400MV_6DB_SNB_B,
 	FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
 	FDI_LINK_TRAIN_800MV_0DB_SNB_B,
 };
 /* The FDI link training functions for SNB/Cougarpoint. */
 static void gen6_fdi_link_train(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	u32 reg, temp, i;
 	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
 	   for train result */
 	reg = FDI_RX_IMR(pipe);
 	temp = I915_READ(reg);
 	temp &= ~FDI_RX_SYMBOL_LOCK;
 	temp &= ~FDI_RX_BIT_LOCK;
 	I915_WRITE(reg, temp);
 	POSTING_READ(reg);
 	udelay(150);
 	/* enable CPU FDI TX and PCH FDI RX */
 	reg = FDI_TX_CTL(pipe);
 	temp = I915_READ(reg);
 	temp &= ~(7 << 19);
 	temp |= (intel_crtc->fdi_lanes - 1) << 19;
 	temp &= ~FDI_LINK_TRAIN_NONE;
 	temp |= FDI_LINK_TRAIN_PATTERN_1;
 	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
 	/* SNB-B */
 	temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
 	I915_WRITE(reg, temp | FDI_TX_ENABLE);
 	reg = FDI_RX_CTL(pipe);
 	temp = I915_READ(reg);
 	if (HAS_PCH_CPT(dev)) {
 		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
 		temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
 	} else {
 		temp &= ~FDI_LINK_TRAIN_NONE;
 		temp |= FDI_LINK_TRAIN_PATTERN_1;
 	}
 	I915_WRITE(reg, temp | FDI_RX_ENABLE);
 	POSTING_READ(reg);
 	udelay(150);
 	if (HAS_PCH_CPT(dev))
 		cpt_phase_pointer_enable(dev, pipe);
 	for (i = 0; i < 4; i++) {
 		reg = FDI_TX_CTL(pipe);
 		temp = I915_READ(reg);
 		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
 		temp |= snb_b_fdi_train_param[i];
 		I915_WRITE(reg, temp);
 		POSTING_READ(reg);
 		udelay(500);
 		reg = FDI_RX_IIR(pipe);
 		temp = I915_READ(reg);
 		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
 		if (temp & FDI_RX_BIT_LOCK) {
 			I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
 			DRM_DEBUG_KMS("FDI train 1 done.\n");
 			break;
 		}
 	}
 	if (i == 4)
 		DRM_ERROR("FDI train 1 fail!\n");
 	/* Train 2 */
 	reg = FDI_TX_CTL(pipe);
 	temp = I915_READ(reg);
 	temp &= ~FDI_LINK_TRAIN_NONE;
 	temp |= FDI_LINK_TRAIN_PATTERN_2;
 	if (IS_GEN6(dev)) {
 		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
 		/* SNB-B */
 		temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
 	}
 	I915_WRITE(reg, temp);
 	reg = FDI_RX_CTL(pipe);
 	temp = I915_READ(reg);
 	if (HAS_PCH_CPT(dev)) {
 		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
 		temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
 	} else {
 		temp &= ~FDI_LINK_TRAIN_NONE;
 		temp |= FDI_LINK_TRAIN_PATTERN_2;
 	}
 	I915_WRITE(reg, temp);
 	POSTING_READ(reg);
 	udelay(150);
 	for (i = 0; i < 4; i++) {
 		reg = FDI_TX_CTL(pipe);
 		temp = I915_READ(reg);
 		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
 		temp |= snb_b_fdi_train_param[i];
 		I915_WRITE(reg, temp);
 		POSTING_READ(reg);
 		udelay(500);
 		reg = FDI_RX_IIR(pipe);
 		temp = I915_READ(reg);
 		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
 		if (temp & FDI_RX_SYMBOL_LOCK) {
 			I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
 			DRM_DEBUG_KMS("FDI train 2 done.\n");
 			break;
 		}
 	}
 	if (i == 4)
 		DRM_ERROR("FDI train 2 fail!\n");
 	DRM_DEBUG_KMS("FDI train done.\n");
 }
 /* Manual link training for Ivy Bridge A0 parts */
 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	u32 reg, temp, i;
 	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
 	   for train result */
 	reg = FDI_RX_IMR(pipe);
 	temp = I915_READ(reg);
 	temp &= ~FDI_RX_SYMBOL_LOCK;
 	temp &= ~FDI_RX_BIT_LOCK;
 	I915_WRITE(reg, temp);
 	POSTING_READ(reg);
 	udelay(150);
 	/* enable CPU FDI TX and PCH FDI RX */
 	reg = FDI_TX_CTL(pipe);
 	temp = I915_READ(reg);
 	temp &= ~(7 << 19);
 	temp |= (intel_crtc->fdi_lanes - 1) << 19;
 	temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
 	temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
 	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
 	temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
 	temp |= FDI_COMPOSITE_SYNC;
 	I915_WRITE(reg, temp | FDI_TX_ENABLE);
 	reg = FDI_RX_CTL(pipe);
 	temp = I915_READ(reg);
 	temp &= ~FDI_LINK_TRAIN_AUTO;
 	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
 	temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
 	temp |= FDI_COMPOSITE_SYNC;
 	I915_WRITE(reg, temp | FDI_RX_ENABLE);
 	POSTING_READ(reg);
 	udelay(150);
 	if (HAS_PCH_CPT(dev))
 		cpt_phase_pointer_enable(dev, pipe);
 	for (i = 0; i < 4; i++) {
 		reg = FDI_TX_CTL(pipe);
 		temp = I915_READ(reg);
 		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
 		temp |= snb_b_fdi_train_param[i];
 		I915_WRITE(reg, temp);
 		POSTING_READ(reg);
 		udelay(500);
 		reg = FDI_RX_IIR(pipe);
 		temp = I915_READ(reg);
 		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
 		if (temp & FDI_RX_BIT_LOCK ||
 		    (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
 			I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
 			DRM_DEBUG_KMS("FDI train 1 done.\n");
 			break;
 		}
 	}
 	if (i == 4)
 		DRM_ERROR("FDI train 1 fail!\n");
 	/* Train 2 */
 	reg = FDI_TX_CTL(pipe);
 	temp = I915_READ(reg);
 	temp &= ~FDI_LINK_TRAIN_NONE_IVB;
 	temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
 	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
 	temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
 	I915_WRITE(reg, temp);
 	reg = FDI_RX_CTL(pipe);
 	temp = I915_READ(reg);
 	temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
 	temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
 	I915_WRITE(reg, temp);
 	POSTING_READ(reg);
 	udelay(150);
 	for (i = 0; i < 4; i++) {
 		reg = FDI_TX_CTL(pipe);
 		temp = I915_READ(reg);
 		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
 		temp |= snb_b_fdi_train_param[i];
 		I915_WRITE(reg, temp);
 		POSTING_READ(reg);
 		udelay(500);
 		reg = FDI_RX_IIR(pipe);
 		temp = I915_READ(reg);
 		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
 		if (temp & FDI_RX_SYMBOL_LOCK) {
 			I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
 			DRM_DEBUG_KMS("FDI train 2 done.\n");
 			break;
 		}
 	}
 	if (i == 4)
 		DRM_ERROR("FDI train 2 fail!\n");
 	DRM_DEBUG_KMS("FDI train done.\n");
 }
 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	u32 reg, temp;
 	/* Write the TU size bits so error detection works */
 	I915_WRITE(FDI_RX_TUSIZE1(pipe),
 		   I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
 	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
 	reg = FDI_RX_CTL(pipe);
 	temp = I915_READ(reg);
 	temp &= ~((0x7 << 19) | (0x7 << 16));
 	temp |= (intel_crtc->fdi_lanes - 1) << 19;
 	temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
 	I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
 	POSTING_READ(reg);
 	udelay(200);
 	/* Switch from Rawclk to PCDclk */
 	temp = I915_READ(reg);
 	I915_WRITE(reg, temp | FDI_PCDCLK);
 	POSTING_READ(reg);
 	udelay(200);
 	/* Enable CPU FDI TX PLL, always on for Ironlake */
 	reg = FDI_TX_CTL(pipe);
 	temp = I915_READ(reg);
 	if ((temp & FDI_TX_PLL_ENABLE) == 0) {
 		I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
 		POSTING_READ(reg);
 		udelay(100);
 	}
 }
 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 flags = I915_READ(SOUTH_CHICKEN1);
 	flags &= ~(FDI_PHASE_SYNC_EN(pipe));
 	I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
 	flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
 	I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
 	POSTING_READ(SOUTH_CHICKEN1);
 }
 static void ironlake_fdi_disable(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	u32 reg, temp;
 	/* disable CPU FDI tx and PCH FDI rx */
 	reg = FDI_TX_CTL(pipe);
 	temp = I915_READ(reg);
 	I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
 	POSTING_READ(reg);
 	reg = FDI_RX_CTL(pipe);
 	temp = I915_READ(reg);
 	temp &= ~(0x7 << 16);
 	temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
 	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
 	POSTING_READ(reg);
 	udelay(100);
 	/* Ironlake workaround, disable clock pointer after downing FDI */
 	if (HAS_PCH_IBX(dev)) {
 		I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
 		I915_WRITE(FDI_RX_CHICKEN(pipe),
 			   I915_READ(FDI_RX_CHICKEN(pipe) &
 				     ~FDI_RX_PHASE_SYNC_POINTER_EN));
 	} else if (HAS_PCH_CPT(dev)) {
 		cpt_phase_pointer_disable(dev, pipe);
 	}
 	/* still set train pattern 1 */
 	reg = FDI_TX_CTL(pipe);
 	temp = I915_READ(reg);
 	temp &= ~FDI_LINK_TRAIN_NONE;
 	temp |= FDI_LINK_TRAIN_PATTERN_1;
 	I915_WRITE(reg, temp);
 	reg = FDI_RX_CTL(pipe);
 	temp = I915_READ(reg);
 	if (HAS_PCH_CPT(dev)) {
 		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
 		temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
 	} else {
 		temp &= ~FDI_LINK_TRAIN_NONE;
 		temp |= FDI_LINK_TRAIN_PATTERN_1;
 	}
 	/* BPC in FDI rx is consistent with that in PIPECONF */
 	temp &= ~(0x07 << 16);
 	temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
 	I915_WRITE(reg, temp);
 	POSTING_READ(reg);
 	udelay(100);
 }
 /*
  * When we disable a pipe, we need to clear any pending scanline wait events
  * to avoid hanging the ring, which we assume we are waiting on.
  */
 static void intel_clear_scanline_wait(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_ring_buffer *ring;
 	u32 tmp;
 	if (IS_GEN2(dev))
 		/* Can't break the hang on i8xx */
 		return;
 	ring = LP_RING(dev_priv);
 	tmp = I915_READ_CTL(ring);
 	if (tmp & RING_WAIT)
 		I915_WRITE_CTL(ring, tmp);
 }
 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
 {
 	struct drm_i915_gem_object *obj;
 	struct drm_i915_private *dev_priv;
 	if (crtc->fb == NULL)
 		return;
 	obj = to_intel_framebuffer(crtc->fb)->obj;
 	dev_priv = crtc->dev->dev_private;
 	wait_event(dev_priv->pending_flip_queue,
 		   atomic_read(&obj->pending_flip) == 0);
 }
 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_mode_config *mode_config = &dev->mode_config;
 	struct intel_encoder *encoder;
 	/*
 	 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
 	 * must be driven by its own crtc; no sharing is possible.
 	 */
 	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
 		if (encoder->base.crtc != crtc)
 			continue;
 		switch (encoder->type) {
 		case INTEL_OUTPUT_EDP:
 			if (!intel_encoder_is_pch_edp(&encoder->base))
 				return false;
 			continue;
 		}
 	}
 	return true;
 }
 /*
  * Enable PCH resources required for PCH ports:
  *   - PCH PLLs
  *   - FDI training & RX/TX
  *   - update transcoder timings
  *   - DP transcoding bits
  *   - transcoder
  */
 static void ironlake_pch_enable(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	u32 reg, temp, transc_sel;
 	/* For PCH output, training FDI link */
 	dev_priv->display.fdi_link_train(crtc);
 	intel_enable_pch_pll(dev_priv, pipe);
 	if (HAS_PCH_CPT(dev)) {
 		transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
 			TRANSC_DPLLB_SEL;
 		/* Be sure PCH DPLL SEL is set */
 		temp = I915_READ(PCH_DPLL_SEL);
 		if (pipe == 0) {
 			temp &= ~(TRANSA_DPLLB_SEL);
 			temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
 		} else if (pipe == 1) {
 			temp &= ~(TRANSB_DPLLB_SEL);
 			temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
 		} else if (pipe == 2) {
 			temp &= ~(TRANSC_DPLLB_SEL);
 			temp |= (TRANSC_DPLL_ENABLE | transc_sel);
 		}
 		I915_WRITE(PCH_DPLL_SEL, temp);
 	}
 	/* set transcoder timing, panel must allow it */
 	assert_panel_unlocked(dev_priv, pipe);
 	I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
 	I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
 	I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
 	I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
 	I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
 	I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
 	intel_fdi_normal_train(crtc);
 	/* For PCH DP, enable TRANS_DP_CTL */
 	if (HAS_PCH_CPT(dev) &&
 	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 	     intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
 		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
 		reg = TRANS_DP_CTL(pipe);
 		temp = I915_READ(reg);
 		temp &= ~(TRANS_DP_PORT_SEL_MASK |
 			  TRANS_DP_SYNC_MASK |
 			  TRANS_DP_BPC_MASK);
 		temp |= (TRANS_DP_OUTPUT_ENABLE |
 			 TRANS_DP_ENH_FRAMING);
 		temp |= bpc << 9; /* same format but at 11:9 */
 		if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
 			temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
 		if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
 			temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
 		switch (intel_trans_dp_port_sel(crtc)) {
 		case PCH_DP_B:
 			temp |= TRANS_DP_PORT_SEL_B;
 			break;
 		case PCH_DP_C:
 			temp |= TRANS_DP_PORT_SEL_C;
 			break;
 		case PCH_DP_D:
 			temp |= TRANS_DP_PORT_SEL_D;
 			break;
 		default:
 			DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
 			temp |= TRANS_DP_PORT_SEL_B;
 			break;
 		}
 		I915_WRITE(reg, temp);
 	}
 	intel_enable_transcoder(dev_priv, pipe);
 }
 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
 	u32 temp;
 	temp = I915_READ(dslreg);
 	udelay(500);
 	if (wait_for(I915_READ(dslreg) != temp, 5)) {
 		/* Without this, mode sets may fail silently on FDI */
 		I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
 		udelay(250);
 		I915_WRITE(tc2reg, 0);
 		if (wait_for(I915_READ(dslreg) != temp, 5))
 			DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
 	}
 }
 static void ironlake_crtc_enable(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	int plane = intel_crtc->plane;
 	u32 temp;
 	bool is_pch_port;
 	if (intel_crtc->active)
 		return;
 	intel_crtc->active = true;
 	intel_update_watermarks(dev);
 	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 		temp = I915_READ(PCH_LVDS);
 		if ((temp & LVDS_PORT_EN) == 0)
 			I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
 	}
 	is_pch_port = intel_crtc_driving_pch(crtc);
 	if (is_pch_port)
 		ironlake_fdi_pll_enable(crtc);
 	else
 		ironlake_fdi_disable(crtc);
 	/* Enable panel fitting for LVDS */
 	if (dev_priv->pch_pf_size &&
 	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
 		/* Force use of hard-coded filter coefficients
 		 * as some pre-programmed values are broken,
 		 * e.g. x201.
 		 */
 		I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
 		I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
 		I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
 	}
 	/*
 	 * On ILK+ LUT must be loaded before the pipe is running but with
 	 * clocks enabled
 	 */
 	intel_crtc_load_lut(crtc);
 	intel_enable_pipe(dev_priv, pipe, is_pch_port);
 	intel_enable_plane(dev_priv, plane, pipe);
 	if (is_pch_port)
 		ironlake_pch_enable(crtc);
 	mutex_lock(&dev->struct_mutex);
 	intel_update_fbc(dev);
 	mutex_unlock(&dev->struct_mutex);
 	intel_crtc_update_cursor(crtc, true);
 }
 static void ironlake_crtc_disable(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	int plane = intel_crtc->plane;
 	u32 reg, temp;
 	if (!intel_crtc->active)
 		return;
 	intel_crtc_wait_for_pending_flips(crtc);
 	drm_vblank_off(dev, pipe);
 	intel_crtc_update_cursor(crtc, false);
 	intel_disable_plane(dev_priv, plane, pipe);
 	if (dev_priv->cfb_plane == plane)
 		intel_disable_fbc(dev);
 	intel_disable_pipe(dev_priv, pipe);
 	/* Disable PF */
 	I915_WRITE(PF_CTL(pipe), 0);
 	I915_WRITE(PF_WIN_SZ(pipe), 0);
 	ironlake_fdi_disable(crtc);
 	/* This is a horrible layering violation; we should be doing this in
 	 * the connector/encoder ->prepare instead, but we don't always have
 	 * enough information there about the config to know whether it will
 	 * actually be necessary or just cause undesired flicker.
 	 */
 	intel_disable_pch_ports(dev_priv, pipe);
 	intel_disable_transcoder(dev_priv, pipe);
 	if (HAS_PCH_CPT(dev)) {
 		/* disable TRANS_DP_CTL */
 		reg = TRANS_DP_CTL(pipe);
 		temp = I915_READ(reg);
 		temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
 		temp |= TRANS_DP_PORT_SEL_NONE;
 		I915_WRITE(reg, temp);
 		/* disable DPLL_SEL */
 		temp = I915_READ(PCH_DPLL_SEL);
 		switch (pipe) {
 		case 0:
 			temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
 			break;
 		case 1:
 			temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
 			break;
 		case 2:
 			/* C shares PLL A or B */
 			temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
 			break;
 		default:
 			BUG(); /* wtf */
 		}
 		I915_WRITE(PCH_DPLL_SEL, temp);
 	}
 	/* disable PCH DPLL */
 	if (!intel_crtc->no_pll)
 		intel_disable_pch_pll(dev_priv, pipe);
 	/* Switch from PCDclk to Rawclk */
 	reg = FDI_RX_CTL(pipe);
 	temp = I915_READ(reg);
 	I915_WRITE(reg, temp & ~FDI_PCDCLK);
 	/* Disable CPU FDI TX PLL */
 	reg = FDI_TX_CTL(pipe);
 	temp = I915_READ(reg);
 	I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
 	POSTING_READ(reg);
 	udelay(100);
 	reg = FDI_RX_CTL(pipe);
 	temp = I915_READ(reg);
 	I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
 	/* Wait for the clocks to turn off. */
 	POSTING_READ(reg);
 	udelay(100);
 	intel_crtc->active = false;
 	intel_update_watermarks(dev);
 	mutex_lock(&dev->struct_mutex);
 	intel_update_fbc(dev);
 	intel_clear_scanline_wait(dev);
 	mutex_unlock(&dev->struct_mutex);
 }
 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
 {
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	int plane = intel_crtc->plane;
 	/* XXX: When our outputs are all unaware of DPMS modes other than off
 	 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
 	 */
 	switch (mode) {
 	case DRM_MODE_DPMS_ON:
 	case DRM_MODE_DPMS_STANDBY:
 	case DRM_MODE_DPMS_SUSPEND:
 		DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
 		ironlake_crtc_enable(crtc);
 		break;
 	case DRM_MODE_DPMS_OFF:
 		DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
 		ironlake_crtc_disable(crtc);
 		break;
 	}
 }
 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
 {
 	if (!enable && intel_crtc->overlay) {
 		struct drm_device *dev = intel_crtc->base.dev;
 		struct drm_i915_private *dev_priv = dev->dev_private;
 		mutex_lock(&dev->struct_mutex);
 		dev_priv->mm.interruptible = false;
 		(void) intel_overlay_switch_off(intel_crtc->overlay);
 		dev_priv->mm.interruptible = true;
 		mutex_unlock(&dev->struct_mutex);
 	}
 	/* Let userspace switch the overlay on again. In most cases userspace
 	 * has to recompute where to put it anyway.
 	 */
 }
 static void i9xx_crtc_enable(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	int plane = intel_crtc->plane;
 	if (intel_crtc->active)
 		return;
 	intel_crtc->active = true;
 	intel_update_watermarks(dev);
 	intel_enable_pll(dev_priv, pipe);
 	intel_enable_pipe(dev_priv, pipe, false);
 	intel_enable_plane(dev_priv, plane, pipe);
 	intel_crtc_load_lut(crtc);
 	intel_update_fbc(dev);
 	/* Give the overlay scaler a chance to enable if it's on this pipe */
 	intel_crtc_dpms_overlay(intel_crtc, true);
 	intel_crtc_update_cursor(crtc, true);
 }
 static void i9xx_crtc_disable(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	int plane = intel_crtc->plane;
 	if (!intel_crtc->active)
 		return;
 	/* Give the overlay scaler a chance to disable if it's on this pipe */
 	intel_crtc_wait_for_pending_flips(crtc);
 	drm_vblank_off(dev, pipe);
 	intel_crtc_dpms_overlay(intel_crtc, false);
 	intel_crtc_update_cursor(crtc, false);
 	if (dev_priv->cfb_plane == plane)
 		intel_disable_fbc(dev);
 	intel_disable_plane(dev_priv, plane, pipe);
 	intel_disable_pipe(dev_priv, pipe);
 	intel_disable_pll(dev_priv, pipe);
 	intel_crtc->active = false;
 	intel_update_fbc(dev);
 	intel_update_watermarks(dev);
 	intel_clear_scanline_wait(dev);
 }
 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
 {
 	/* XXX: When our outputs are all unaware of DPMS modes other than off
 	 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
 	 */
 	switch (mode) {
 	case DRM_MODE_DPMS_ON:
 	case DRM_MODE_DPMS_STANDBY:
 	case DRM_MODE_DPMS_SUSPEND:
 		i9xx_crtc_enable(crtc);
 		break;
 	case DRM_MODE_DPMS_OFF:
 		i9xx_crtc_disable(crtc);
 		break;
 	}
 }
 /**
  * Sets the power management mode of the pipe and plane.
  */
 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_i915_master_private *master_priv;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	bool enabled;
 	if (intel_crtc->dpms_mode == mode)
 		return;
 	intel_crtc->dpms_mode = mode;
 	dev_priv->display.dpms(crtc, mode);
 	if (!dev->primary->master)
 		return;
 	master_priv = dev->primary->master->driver_priv;
 	if (!master_priv->sarea_priv)
 		return;
 	enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
 	switch (pipe) {
 	case 0:
 		master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
 		master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
 		break;
 	case 1:
 		master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
 		master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
 		break;
 	default:
 		DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
 		break;
 	}
 }
 static void intel_crtc_disable(struct drm_crtc *crtc)
 {
 	struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 	struct drm_device *dev = crtc->dev;
 	crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
 	if (crtc->fb) {
 		mutex_lock(&dev->struct_mutex);
 		i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
 		mutex_unlock(&dev->struct_mutex);
 	}
 }
 /* Prepare for a mode set.
  *
  * Note we could be a lot smarter here.  We need to figure out which outputs
  * will be enabled, which disabled (in short, how the config will changes)
  * and perform the minimum necessary steps to accomplish that, e.g. updating
  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
  * panel fitting is in the proper state, etc.
  */
 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
 {
 	i9xx_crtc_disable(crtc);
 }
 static void i9xx_crtc_commit(struct drm_crtc *crtc)
 {
 	i9xx_crtc_enable(crtc);
 }
 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
 {
 	ironlake_crtc_disable(crtc);
 }
 static void ironlake_crtc_commit(struct drm_crtc *crtc)
 {
 	ironlake_crtc_enable(crtc);
 }
 void intel_encoder_prepare(struct drm_encoder *encoder)
 {
 	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
 	/* lvds has its own version of prepare see intel_lvds_prepare */
 	encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
 }
 void intel_encoder_commit(struct drm_encoder *encoder)
 {
 	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
 	struct drm_device *dev = encoder->dev;
 	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
 	struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
 	/* lvds has its own version of commit see intel_lvds_commit */
 	encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
 	if (HAS_PCH_CPT(dev))
 		intel_cpt_verify_modeset(dev, intel_crtc->pipe);
 }
 void intel_encoder_destroy(struct drm_encoder *encoder)
 {
 	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
 	drm_encoder_cleanup(encoder);
 	kfree(intel_encoder);
 }
 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
 				  struct drm_display_mode *mode,
 				  struct drm_display_mode *adjusted_mode)
 {
 	struct drm_device *dev = crtc->dev;
 	if (HAS_PCH_SPLIT(dev)) {
 		/* FDI link clock is fixed at 2.7G */
 		if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
 			return false;
 	}
 	/* XXX some encoders set the crtcinfo, others don't.
 	 * Obviously we need some form of conflict resolution here...
 	 */
 	if (adjusted_mode->crtc_htotal == 0)
 		drm_mode_set_crtcinfo(adjusted_mode, 0);
 	return true;
 }
 static int i945_get_display_clock_speed(struct drm_device *dev)
 {
 	return 400000;
 }
 static int i915_get_display_clock_speed(struct drm_device *dev)
 {
 	return 333000;
 }
 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
 {
 	return 200000;
 }
 static int i915gm_get_display_clock_speed(struct drm_device *dev)
 {
 	u16 gcfgc = 0;
 	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
 	if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
 		return 133000;
 	else {
 		switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 		case GC_DISPLAY_CLOCK_333_MHZ:
 			return 333000;
 		default:
 		case GC_DISPLAY_CLOCK_190_200_MHZ:
 			return 190000;
 		}
 	}
 }
 static int i865_get_display_clock_speed(struct drm_device *dev)
 {
 	return 266000;
 }
 static int i855_get_display_clock_speed(struct drm_device *dev)
 {
 	u16 hpllcc = 0;
 	/* Assume that the hardware is in the high speed state.  This
 	 * should be the default.
 	 */
 	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
 	case GC_CLOCK_133_200:
 	case GC_CLOCK_100_200:
 		return 200000;
 	case GC_CLOCK_166_250:
 		return 250000;
 	case GC_CLOCK_100_133:
 		return 133000;
 	}
 	/* Shouldn't happen */
 	return 0;
 }
 static int i830_get_display_clock_speed(struct drm_device *dev)
 {
 	return 133000;
 }
 struct fdi_m_n {
 	u32        tu;
 	u32        gmch_m;
 	u32        gmch_n;
 	u32        link_m;
 	u32        link_n;
 };
 static void
 fdi_reduce_ratio(u32 *num, u32 *den)
 {
 	while (*num > 0xffffff || *den > 0xffffff) {
 		*num >>= 1;
 		*den >>= 1;
 	}
 }
 static void
 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
 		     int link_clock, struct fdi_m_n *m_n)
 {
 	m_n->tu = 64; /* default size */
 	/* BUG_ON(pixel_clock > INT_MAX / 36); */
 	m_n->gmch_m = bits_per_pixel * pixel_clock;
 	m_n->gmch_n = link_clock * nlanes * 8;
 	fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 	m_n->link_m = pixel_clock;
 	m_n->link_n = link_clock;
 	fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
 }
 struct intel_watermark_params {
 	unsigned long fifo_size;
 	unsigned long max_wm;
 	unsigned long default_wm;
 	unsigned long guard_size;
 	unsigned long cacheline_size;
 };
 /* Pineview has different values for various configs */
 static const struct intel_watermark_params pineview_display_wm = {
 	PINEVIEW_DISPLAY_FIFO,
 	PINEVIEW_MAX_WM,
 	PINEVIEW_DFT_WM,
 	PINEVIEW_GUARD_WM,
 	PINEVIEW_FIFO_LINE_SIZE
 };
 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 	PINEVIEW_DISPLAY_FIFO,
 	PINEVIEW_MAX_WM,
 	PINEVIEW_DFT_HPLLOFF_WM,
 	PINEVIEW_GUARD_WM,
 	PINEVIEW_FIFO_LINE_SIZE
 };
 static const struct intel_watermark_params pineview_cursor_wm = {
 	PINEVIEW_CURSOR_FIFO,
 	PINEVIEW_CURSOR_MAX_WM,
 	PINEVIEW_CURSOR_DFT_WM,
 	PINEVIEW_CURSOR_GUARD_WM,
 	PINEVIEW_FIFO_LINE_SIZE,
 };
 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 	PINEVIEW_CURSOR_FIFO,
 	PINEVIEW_CURSOR_MAX_WM,
 	PINEVIEW_CURSOR_DFT_WM,
 	PINEVIEW_CURSOR_GUARD_WM,
 	PINEVIEW_FIFO_LINE_SIZE
 };
 static const struct intel_watermark_params g4x_wm_info = {
 	G4X_FIFO_SIZE,
 	G4X_MAX_WM,
 	G4X_MAX_WM,
 	2,
 	G4X_FIFO_LINE_SIZE,
 };
 static const struct intel_watermark_params g4x_cursor_wm_info = {
 	I965_CURSOR_FIFO,
 	I965_CURSOR_MAX_WM,
 	I965_CURSOR_DFT_WM,
 	2,
 	G4X_FIFO_LINE_SIZE,
 };
 static const struct intel_watermark_params i965_cursor_wm_info = {
 	I965_CURSOR_FIFO,
 	I965_CURSOR_MAX_WM,
 	I965_CURSOR_DFT_WM,
 	2,
 	I915_FIFO_LINE_SIZE,
 };
 static const struct intel_watermark_params i945_wm_info = {
 	I945_FIFO_SIZE,
 	I915_MAX_WM,
 	1,
 	2,
 	I915_FIFO_LINE_SIZE
 };
 static const struct intel_watermark_params i915_wm_info = {
 	I915_FIFO_SIZE,
 	I915_MAX_WM,
 	1,
 	2,
 	I915_FIFO_LINE_SIZE
 };
 static const struct intel_watermark_params i855_wm_info = {
 	I855GM_FIFO_SIZE,
 	I915_MAX_WM,
 	1,
 	2,
 	I830_FIFO_LINE_SIZE
 };
 static const struct intel_watermark_params i830_wm_info = {
 	I830_FIFO_SIZE,
 	I915_MAX_WM,
 	1,
 	2,
 	I830_FIFO_LINE_SIZE
 };
 static const struct intel_watermark_params ironlake_display_wm_info = {
 	ILK_DISPLAY_FIFO,
 	ILK_DISPLAY_MAXWM,
 	ILK_DISPLAY_DFTWM,
 	2,
 	ILK_FIFO_LINE_SIZE
 };
 static const struct intel_watermark_params ironlake_cursor_wm_info = {
 	ILK_CURSOR_FIFO,
 	ILK_CURSOR_MAXWM,
 	ILK_CURSOR_DFTWM,
 	2,
 	ILK_FIFO_LINE_SIZE
 };
 static const struct intel_watermark_params ironlake_display_srwm_info = {
 	ILK_DISPLAY_SR_FIFO,
 	ILK_DISPLAY_MAX_SRWM,
 	ILK_DISPLAY_DFT_SRWM,
 	2,
 	ILK_FIFO_LINE_SIZE
 };
 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
 	ILK_CURSOR_SR_FIFO,
 	ILK_CURSOR_MAX_SRWM,
 	ILK_CURSOR_DFT_SRWM,
 	2,
 	ILK_FIFO_LINE_SIZE
 };
 static const struct intel_watermark_params sandybridge_display_wm_info = {
 	SNB_DISPLAY_FIFO,
 	SNB_DISPLAY_MAXWM,
 	SNB_DISPLAY_DFTWM,
 	2,
 	SNB_FIFO_LINE_SIZE
 };
 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
 	SNB_CURSOR_FIFO,
 	SNB_CURSOR_MAXWM,
 	SNB_CURSOR_DFTWM,
 	2,
 	SNB_FIFO_LINE_SIZE
 };
 static const struct intel_watermark_params sandybridge_display_srwm_info = {
 	SNB_DISPLAY_SR_FIFO,
 	SNB_DISPLAY_MAX_SRWM,
 	SNB_DISPLAY_DFT_SRWM,
 	2,
 	SNB_FIFO_LINE_SIZE
 };
 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
 	SNB_CURSOR_SR_FIFO,
 	SNB_CURSOR_MAX_SRWM,
 	SNB_CURSOR_DFT_SRWM,
 	2,
 	SNB_FIFO_LINE_SIZE
 };
 /**
  * intel_calculate_wm - calculate watermark level
  * @clock_in_khz: pixel clock
  * @wm: chip FIFO params
  * @pixel_size: display pixel size
  * @latency_ns: memory latency for the platform
  *
  * Calculate the watermark level (the level at which the display plane will
  * start fetching from memory again).  Each chip has a different display
  * FIFO size and allocation, so the caller needs to figure that out and pass
  * in the correct intel_watermark_params structure.
  *
  * As the pixel clock runs, the FIFO will be drained at a rate that depends
  * on the pixel size.  When it reaches the watermark level, it'll start
  * fetching FIFO line sized based chunks from memory until the FIFO fills
  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
  * will occur, and a display engine hang could result.
  */
 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 					const struct intel_watermark_params *wm,
 					int fifo_size,
 					int pixel_size,
 					unsigned long latency_ns)
 {
 	long entries_required, wm_size;
 	/*
 	 * Note: we need to make sure we don't overflow for various clock &
 	 * latency values.
 	 * clocks go from a few thousand to several hundred thousand.
 	 * latency is usually a few thousand
 	 */
 	entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 		1000;
 	entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 	DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 	wm_size = fifo_size - (entries_required + wm->guard_size);
 	DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 	/* Don't promote wm_size to unsigned... */
 	if (wm_size > (long)wm->max_wm)
 		wm_size = wm->max_wm;
 	if (wm_size <= 0)
 		wm_size = wm->default_wm;
 	return wm_size;
 }
 struct cxsr_latency {
 	int is_desktop;
 	int is_ddr3;
 	unsigned long fsb_freq;
 	unsigned long mem_freq;
 	unsigned long display_sr;
 	unsigned long display_hpll_disable;
 	unsigned long cursor_sr;
 	unsigned long cursor_hpll_disable;
 };
 static const struct cxsr_latency cxsr_latency_table[] = {
 	{1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 	{1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 	{1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 	{1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 	{1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 	{1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 	{1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 	{1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 	{1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 	{1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 	{1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 	{1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 	{1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 	{1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 	{1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 	{0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 	{0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 	{0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 	{0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 	{0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 	{0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 	{0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 	{0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 	{0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 	{0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 	{0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 	{0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 	{0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 	{0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 	{0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 };
 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 							 int is_ddr3,
 							 int fsb,
 							 int mem)
 {
 	const struct cxsr_latency *latency;
 	int i;
 	if (fsb == 0 || mem == 0)
 		return NULL;
 	for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 		latency = &cxsr_latency_table[i];
 		if (is_desktop == latency->is_desktop &&
 		    is_ddr3 == latency->is_ddr3 &&
 		    fsb == latency->fsb_freq && mem == latency->mem_freq)
 			return latency;
 	}
 	DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 	return NULL;
 }
 static void pineview_disable_cxsr(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	/* deactivate cxsr */
 	I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 }
 /*
  * Latency for FIFO fetches is dependent on several factors:
  *   - memory configuration (speed, channels)
  *   - chipset
  *   - current MCH state
  * It can be fairly high in some situations, so here we assume a fairly
  * pessimal value.  It's a tradeoff between extra memory fetches (if we
  * set this value too high, the FIFO will fetch frequently to stay full)
  * and power consumption (set it too low to save power and we might see
  * FIFO underruns and display "flicker").
  *
  * A value of 5us seems to be a good balance; safe for very low end
  * platforms but not overly aggressive on lower latency configs.
  */
 static const int latency_ns = 5000;
 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t dsparb = I915_READ(DSPARB);
 	int size;
 	size = dsparb & 0x7f;
 	if (plane)
 		size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 		      plane ? "B" : "A", size);
 	return size;
 }
 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t dsparb = I915_READ(DSPARB);
 	int size;
 	size = dsparb & 0x1ff;
 	if (plane)
 		size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 	size >>= 1; /* Convert to cachelines */
 	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 		      plane ? "B" : "A", size);
 	return size;
 }
 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t dsparb = I915_READ(DSPARB);
 	int size;
 	size = dsparb & 0x7f;
 	size >>= 2; /* Convert to cachelines */
 	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 		      plane ? "B" : "A",
 		      size);
 	return size;
 }
 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t dsparb = I915_READ(DSPARB);
 	int size;
 	size = dsparb & 0x7f;
 	size >>= 1; /* Convert to cachelines */
 	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 		      plane ? "B" : "A", size);
 	return size;
 }
 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 {
 	struct drm_crtc *crtc, *enabled = NULL;
 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 		if (crtc->enabled && crtc->fb) {
 			if (enabled)
 				return NULL;
 			enabled = crtc;
 		}
 	}
 	return enabled;
 }
 static void pineview_update_wm(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_crtc *crtc;
 	const struct cxsr_latency *latency;
 	u32 reg;
 	unsigned long wm;
 	latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
 					 dev_priv->fsb_freq, dev_priv->mem_freq);
 	if (!latency) {
 		DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 		pineview_disable_cxsr(dev);
 		return;
 	}
 	crtc = single_enabled_crtc(dev);
 	if (crtc) {
 		int clock = crtc->mode.clock;
 		int pixel_size = crtc->fb->bits_per_pixel / 8;
 		/* Display SR */
 		wm = intel_calculate_wm(clock, &pineview_display_wm,
 					pineview_display_wm.fifo_size,
 					pixel_size, latency->display_sr);
 		reg = I915_READ(DSPFW1);
 		reg &= ~DSPFW_SR_MASK;
 		reg |= wm << DSPFW_SR_SHIFT;
 		I915_WRITE(DSPFW1, reg);
 		DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 		/* cursor SR */
 		wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 					pineview_display_wm.fifo_size,
 					pixel_size, latency->cursor_sr);
 		reg = I915_READ(DSPFW3);
 		reg &= ~DSPFW_CURSOR_SR_MASK;
 		reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
 		I915_WRITE(DSPFW3, reg);
 		/* Display HPLL off SR */
 		wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 					pineview_display_hplloff_wm.fifo_size,
 					pixel_size, latency->display_hpll_disable);
 		reg = I915_READ(DSPFW3);
 		reg &= ~DSPFW_HPLL_SR_MASK;
 		reg |= wm & DSPFW_HPLL_SR_MASK;
 		I915_WRITE(DSPFW3, reg);
 		/* cursor HPLL off SR */
 		wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 					pineview_display_hplloff_wm.fifo_size,
 					pixel_size, latency->cursor_hpll_disable);
 		reg = I915_READ(DSPFW3);
 		reg &= ~DSPFW_HPLL_CURSOR_MASK;
 		reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
 		I915_WRITE(DSPFW3, reg);
 		DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 		/* activate cxsr */
 		I915_WRITE(DSPFW3,
 			   I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
 		DRM_DEBUG_KMS("Self-refresh is enabled\n");
 	} else {
 		pineview_disable_cxsr(dev);
 		DRM_DEBUG_KMS("Self-refresh is disabled\n");
 	}
 }
 static bool g4x_compute_wm0(struct drm_device *dev,
 			    int plane,
 			    const struct intel_watermark_params *display,
 			    int display_latency_ns,
 			    const struct intel_watermark_params *cursor,
 			    int cursor_latency_ns,
 			    int *plane_wm,
 			    int *cursor_wm)
 {
 	struct drm_crtc *crtc;
 	int htotal, hdisplay, clock, pixel_size;
 	int line_time_us, line_count;
 	int entries, tlb_miss;
 	crtc = intel_get_crtc_for_plane(dev, plane);
 	if (crtc->fb == NULL || !crtc->enabled) {
 		*cursor_wm = cursor->guard_size;
 		*plane_wm = display->guard_size;
 		return false;
 	}
 	htotal = crtc->mode.htotal;
 	hdisplay = crtc->mode.hdisplay;
 	clock = crtc->mode.clock;
 	pixel_size = crtc->fb->bits_per_pixel / 8;
 	/* Use the small buffer method to calculate plane watermark */
 	entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
 	tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 	if (tlb_miss > 0)
 		entries += tlb_miss;
 	entries = DIV_ROUND_UP(entries, display->cacheline_size);
 	*plane_wm = entries + display->guard_size;
 	if (*plane_wm > (int)display->max_wm)
 		*plane_wm = display->max_wm;
 	/* Use the large buffer method to calculate cursor watermark */
 	line_time_us = ((htotal * 1000) / clock);
 	line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 	entries = line_count * 64 * pixel_size;
 	tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 	if (tlb_miss > 0)
 		entries += tlb_miss;
 	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 	*cursor_wm = entries + cursor->guard_size;
 	if (*cursor_wm > (int)cursor->max_wm)
 		*cursor_wm = (int)cursor->max_wm;
 	return true;
 }
 /*
  * Check the wm result.
  *
  * If any calculated watermark values is larger than the maximum value that
  * can be programmed into the associated watermark register, that watermark
  * must be disabled.
  */
 static bool g4x_check_srwm(struct drm_device *dev,
 			   int display_wm, int cursor_wm,
 			   const struct intel_watermark_params *display,
 			   const struct intel_watermark_params *cursor)
 {
 	DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 		      display_wm, cursor_wm);
 	if (display_wm > display->max_wm) {
 		DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
 			      display_wm, display->max_wm);
 		return false;
 	}
 	if (cursor_wm > cursor->max_wm) {
 		DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
 			      cursor_wm, cursor->max_wm);
 		return false;
 	}
 	if (!(display_wm || cursor_wm)) {
 		DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 		return false;
 	}
 	return true;
 }
 static bool g4x_compute_srwm(struct drm_device *dev,
 			     int plane,
 			     int latency_ns,
 			     const struct intel_watermark_params *display,
 			     const struct intel_watermark_params *cursor,
 			     int *display_wm, int *cursor_wm)
 {
 	struct drm_crtc *crtc;
 	int hdisplay, htotal, pixel_size, clock;
 	unsigned long line_time_us;
 	int line_count, line_size;
 	int small, large;
 	int entries;
 	if (!latency_ns) {
 		*display_wm = *cursor_wm = 0;
 		return false;
 	}
 	crtc = intel_get_crtc_for_plane(dev, plane);
 	hdisplay = crtc->mode.hdisplay;
 	htotal = crtc->mode.htotal;
 	clock = crtc->mode.clock;
 	pixel_size = crtc->fb->bits_per_pixel / 8;
 	line_time_us = (htotal * 1000) / clock;
 	line_count = (latency_ns / line_time_us + 1000) / 1000;
 	line_size = hdisplay * pixel_size;
 	/* Use the minimum of the small and large buffer method for primary */
 	small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
 	large = line_count * line_size;
 	entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 	*display_wm = entries + display->guard_size;
 	/* calculate the self-refresh watermark for display cursor */
 	entries = line_count * pixel_size * 64;
 	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 	*cursor_wm = entries + cursor->guard_size;
 	return g4x_check_srwm(dev,
 			      *display_wm, *cursor_wm,
 			      display, cursor);
 }
 #define single_plane_enabled(mask) is_power_of_2(mask)
 static void g4x_update_wm(struct drm_device *dev)
 {
 	static const int sr_latency_ns = 12000;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
 	int plane_sr, cursor_sr;
 	unsigned int enabled = 0;
 	if (g4x_compute_wm0(dev, 0,
 			    &g4x_wm_info, latency_ns,
 			    &g4x_cursor_wm_info, latency_ns,
 			    &planea_wm, &cursora_wm))
 		enabled |= 1;
 	if (g4x_compute_wm0(dev, 1,
 			    &g4x_wm_info, latency_ns,
 			    &g4x_cursor_wm_info, latency_ns,
 			    &planeb_wm, &cursorb_wm))
 		enabled |= 2;
 	plane_sr = cursor_sr = 0;
 	if (single_plane_enabled(enabled) &&
 	    g4x_compute_srwm(dev, ffs(enabled) - 1,
 			     sr_latency_ns,
 			     &g4x_wm_info,
 			     &g4x_cursor_wm_info,
 			     &plane_sr, &cursor_sr))
 		I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
 	else
 		I915_WRITE(FW_BLC_SELF,
 			   I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
 	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
 		      planea_wm, cursora_wm,
 		      planeb_wm, cursorb_wm,
 		      plane_sr, cursor_sr);
 	I915_WRITE(DSPFW1,
 		   (plane_sr << DSPFW_SR_SHIFT) |
 		   (cursorb_wm << DSPFW_CURSORB_SHIFT) |
 		   (planeb_wm << DSPFW_PLANEB_SHIFT) |
 		   planea_wm);
 	I915_WRITE(DSPFW2,
 		   (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
 		   (cursora_wm << DSPFW_CURSORA_SHIFT));
 	/* HPLL off in SR has some issues on G4x... disable it */
 	I915_WRITE(DSPFW3,
 		   (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
 		   (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
 }
 static void i965_update_wm(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_crtc *crtc;
 	int srwm = 1;
 	int cursor_sr = 16;
 	/* Calc sr entries for one plane configs */
 	crtc = single_enabled_crtc(dev);
 	if (crtc) {
 		/* self-refresh has much higher latency */
 		static const int sr_latency_ns = 12000;
 		int clock = crtc->mode.clock;
 		int htotal = crtc->mode.htotal;
 		int hdisplay = crtc->mode.hdisplay;
 		int pixel_size = crtc->fb->bits_per_pixel / 8;
 		unsigned long line_time_us;
 		int entries;
 		line_time_us = ((htotal * 1000) / clock);
 		/* Use ns/us then divide to preserve precision */
 		entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
 			pixel_size * hdisplay;
 		entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
 		srwm = I965_FIFO_SIZE - entries;
 		if (srwm < 0)
 			srwm = 1;
 		srwm &= 0x1ff;
 		DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
 			      entries, srwm);
 		entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
 			pixel_size * 64;
 		entries = DIV_ROUND_UP(entries,
 					  i965_cursor_wm_info.cacheline_size);
 		cursor_sr = i965_cursor_wm_info.fifo_size -
 			(entries + i965_cursor_wm_info.guard_size);
 		if (cursor_sr > i965_cursor_wm_info.max_wm)
 			cursor_sr = i965_cursor_wm_info.max_wm;
 		DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
 			      "cursor %d\n", srwm, cursor_sr);
 		if (IS_CRESTLINE(dev))
 			I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
 	} else {
 		/* Turn off self refresh if both pipes are enabled */
 		if (IS_CRESTLINE(dev))
 			I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
 				   & ~FW_BLC_SELF_EN);
 	}
 	DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
 		      srwm);
 	/* 965 has limitations... */
 	I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
 		   (8 << 16) | (8 << 8) | (8 << 0));
 	I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
 	/* update cursor SR watermark */
 	I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
 }
 static void i9xx_update_wm(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	const struct intel_watermark_params *wm_info;
 	uint32_t fwater_lo;
 	uint32_t fwater_hi;
 	int cwm, srwm = 1;
 	int fifo_size;
 	int planea_wm, planeb_wm;
 	struct drm_crtc *crtc, *enabled = NULL;
 	if (IS_I945GM(dev))
 		wm_info = &i945_wm_info;
 	else if (!IS_GEN2(dev))
 		wm_info = &i915_wm_info;
 	else
 		wm_info = &i855_wm_info;
 	fifo_size = dev_priv->display.get_fifo_size(dev, 0);
 	crtc = intel_get_crtc_for_plane(dev, 0);
 	if (crtc->enabled && crtc->fb) {
 		planea_wm = intel_calculate_wm(crtc->mode.clock,
 					       wm_info, fifo_size,
 					       crtc->fb->bits_per_pixel / 8,
 					       latency_ns);
 		enabled = crtc;
 	} else
 		planea_wm = fifo_size - wm_info->guard_size;
 	fifo_size = dev_priv->display.get_fifo_size(dev, 1);
 	crtc = intel_get_crtc_for_plane(dev, 1);
 	if (crtc->enabled && crtc->fb) {
 		planeb_wm = intel_calculate_wm(crtc->mode.clock,
 					       wm_info, fifo_size,
 					       crtc->fb->bits_per_pixel / 8,
 					       latency_ns);
 		if (enabled == NULL)
 			enabled = crtc;
 		else
 			enabled = NULL;
 	} else
 		planeb_wm = fifo_size - wm_info->guard_size;
 	DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
 	/*
 	 * Overlay gets an aggressive default since video jitter is bad.
 	 */
 	cwm = 2;
 	/* Play safe and disable self-refresh before adjusting watermarks. */
 	if (IS_I945G(dev) || IS_I945GM(dev))
 		I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
 	else if (IS_I915GM(dev))
 		I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
 	/* Calc sr entries for one plane configs */
 	if (HAS_FW_BLC(dev) && enabled) {
 		/* self-refresh has much higher latency */
 		static const int sr_latency_ns = 6000;
 		int clock = enabled->mode.clock;
 		int htotal = enabled->mode.htotal;
 		int hdisplay = enabled->mode.hdisplay;
 		int pixel_size = enabled->fb->bits_per_pixel / 8;
 		unsigned long line_time_us;
 		int entries;
 		line_time_us = (htotal * 1000) / clock;
 		/* Use ns/us then divide to preserve precision */
 		entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
 			pixel_size * hdisplay;
 		entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
 		DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
 		srwm = wm_info->fifo_size - entries;
 		if (srwm < 0)
 			srwm = 1;
 		if (IS_I945G(dev) || IS_I945GM(dev))
 			I915_WRITE(FW_BLC_SELF,
 				   FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
 		else if (IS_I915GM(dev))
 			I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
 	}
 	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
 		      planea_wm, planeb_wm, cwm, srwm);
 	fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
 	fwater_hi = (cwm & 0x1f);
 	/* Set request length to 8 cachelines per fetch */
 	fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
 	fwater_hi = fwater_hi | (1 << 8);
 	I915_WRITE(FW_BLC, fwater_lo);
 	I915_WRITE(FW_BLC2, fwater_hi);
 	if (HAS_FW_BLC(dev)) {
 		if (enabled) {
 			if (IS_I945G(dev) || IS_I945GM(dev))
 				I915_WRITE(FW_BLC_SELF,
 					   FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
 			else if (IS_I915GM(dev))
 				I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
 			DRM_DEBUG_KMS("memory self refresh enabled\n");
 		} else
 			DRM_DEBUG_KMS("memory self refresh disabled\n");
 	}
 }
 static void i830_update_wm(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_crtc *crtc;
 	uint32_t fwater_lo;
 	int planea_wm;
 	crtc = single_enabled_crtc(dev);
 	if (crtc == NULL)
 		return;
 	planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
 				       dev_priv->display.get_fifo_size(dev, 0),
 				       crtc->fb->bits_per_pixel / 8,
 				       latency_ns);
 	fwater_lo = I915_READ(FW_BLC) & ~0xfff;
 	fwater_lo |= (3<<8) | planea_wm;
 	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
 	I915_WRITE(FW_BLC, fwater_lo);
 }
 #define ILK_LP0_PLANE_LATENCY		700
 #define ILK_LP0_CURSOR_LATENCY		1300
 /*
  * Check the wm result.
  *
  * If any calculated watermark values is larger than the maximum value that
  * can be programmed into the associated watermark register, that watermark
  * must be disabled.
  */
 static bool ironlake_check_srwm(struct drm_device *dev, int level,
 				int fbc_wm, int display_wm, int cursor_wm,
 				const struct intel_watermark_params *display,
 				const struct intel_watermark_params *cursor)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
 		      " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
 	if (fbc_wm > SNB_FBC_MAX_SRWM) {
 		DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
 			      fbc_wm, SNB_FBC_MAX_SRWM, level);
 		/* fbc has it's own way to disable FBC WM */
 		I915_WRITE(DISP_ARB_CTL,
 			   I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
 		return false;
 	}
 	if (display_wm > display->max_wm) {
 		DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
 			      display_wm, SNB_DISPLAY_MAX_SRWM, level);
 		return false;
 	}
 	if (cursor_wm > cursor->max_wm) {
 		DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
 			      cursor_wm, SNB_CURSOR_MAX_SRWM, level);
 		return false;
 	}
 	if (!(fbc_wm || display_wm || cursor_wm)) {
 		DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
 		return false;
 	}
 	return true;
 }
 /*
  * Compute watermark values of WM[1-3],
  */
 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
 				  int latency_ns,
 				  const struct intel_watermark_params *display,
 				  const struct intel_watermark_params *cursor,
 				  int *fbc_wm, int *display_wm, int *cursor_wm)
 {
 	struct drm_crtc *crtc;
 	unsigned long line_time_us;
 	int hdisplay, htotal, pixel_size, clock;
 	int line_count, line_size;
 	int small, large;
 	int entries;
 	if (!latency_ns) {
 		*fbc_wm = *display_wm = *cursor_wm = 0;
 		return false;
 	}
 	crtc = intel_get_crtc_for_plane(dev, plane);
 	hdisplay = crtc->mode.hdisplay;
 	htotal = crtc->mode.htotal;
 	clock = crtc->mode.clock;
 	pixel_size = crtc->fb->bits_per_pixel / 8;
 	line_time_us = (htotal * 1000) / clock;
 	line_count = (latency_ns / line_time_us + 1000) / 1000;
 	line_size = hdisplay * pixel_size;
 	/* Use the minimum of the small and large buffer method for primary */
 	small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
 	large = line_count * line_size;
 	entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 	*display_wm = entries + display->guard_size;
 	/*
 	 * Spec says:
 	 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
 	 */
 	*fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
 	/* calculate the self-refresh watermark for display cursor */
 	entries = line_count * pixel_size * 64;
 	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 	*cursor_wm = entries + cursor->guard_size;
 	return ironlake_check_srwm(dev, level,
 				   *fbc_wm, *display_wm, *cursor_wm,
 				   display, cursor);
 }
 static void ironlake_update_wm(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int fbc_wm, plane_wm, cursor_wm;
 	unsigned int enabled;
 	enabled = 0;
 	if (g4x_compute_wm0(dev, 0,
 			    &ironlake_display_wm_info,
 			    ILK_LP0_PLANE_LATENCY,
 			    &ironlake_cursor_wm_info,
 			    ILK_LP0_CURSOR_LATENCY,
 			    &plane_wm, &cursor_wm)) {
 		I915_WRITE(WM0_PIPEA_ILK,
 			   (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
 		DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
 			      " plane %d, " "cursor: %d\n",
 			      plane_wm, cursor_wm);
 		enabled |= 1;
 	}
 	if (g4x_compute_wm0(dev, 1,
 			    &ironlake_display_wm_info,
 			    ILK_LP0_PLANE_LATENCY,
 			    &ironlake_cursor_wm_info,
 			    ILK_LP0_CURSOR_LATENCY,
 			    &plane_wm, &cursor_wm)) {
 		I915_WRITE(WM0_PIPEB_ILK,
 			   (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
 		DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
 			      " plane %d, cursor: %d\n",
 			      plane_wm, cursor_wm);
 		enabled |= 2;
 	}
 	/*
 	 * Calculate and update the self-refresh watermark only when one
 	 * display plane is used.
 	 */
 	I915_WRITE(WM3_LP_ILK, 0);
 	I915_WRITE(WM2_LP_ILK, 0);
 	I915_WRITE(WM1_LP_ILK, 0);
 	if (!single_plane_enabled(enabled))
 		return;
 	enabled = ffs(enabled) - 1;
 	/* WM1 */
 	if (!ironlake_compute_srwm(dev, 1, enabled,
 				   ILK_READ_WM1_LATENCY() * 500,
 				   &ironlake_display_srwm_info,
 				   &ironlake_cursor_srwm_info,
 				   &fbc_wm, &plane_wm, &cursor_wm))
 		return;
 	I915_WRITE(WM1_LP_ILK,
 		   WM1_LP_SR_EN |
 		   (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
 		   (fbc_wm << WM1_LP_FBC_SHIFT) |
 		   (plane_wm << WM1_LP_SR_SHIFT) |
 		   cursor_wm);
 	/* WM2 */
 	if (!ironlake_compute_srwm(dev, 2, enabled,
 				   ILK_READ_WM2_LATENCY() * 500,
 				   &ironlake_display_srwm_info,
 				   &ironlake_cursor_srwm_info,
 				   &fbc_wm, &plane_wm, &cursor_wm))
 		return;
 	I915_WRITE(WM2_LP_ILK,
 		   WM2_LP_EN |
 		   (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
 		   (fbc_wm << WM1_LP_FBC_SHIFT) |
 		   (plane_wm << WM1_LP_SR_SHIFT) |
 		   cursor_wm);
 	/*
 	 * WM3 is unsupported on ILK, probably because we don't have latency
 	 * data for that power state
 	 */
 }
 static void sandybridge_update_wm(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int latency = SNB_READ_WM0_LATENCY() * 100;	/* In unit 0.1us */
 	int fbc_wm, plane_wm, cursor_wm;
 	unsigned int enabled;
 	enabled = 0;
 	if (g4x_compute_wm0(dev, 0,
 			    &sandybridge_display_wm_info, latency,
 			    &sandybridge_cursor_wm_info, latency,
 			    &plane_wm, &cursor_wm)) {
 		I915_WRITE(WM0_PIPEA_ILK,
 			   (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
 		DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
 			      " plane %d, " "cursor: %d\n",
 			      plane_wm, cursor_wm);
 		enabled |= 1;
 	}
 	if (g4x_compute_wm0(dev, 1,
 			    &sandybridge_display_wm_info, latency,
 			    &sandybridge_cursor_wm_info, latency,
 			    &plane_wm, &cursor_wm)) {
 		I915_WRITE(WM0_PIPEB_ILK,
 			   (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
 		DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
 			      " plane %d, cursor: %d\n",
 			      plane_wm, cursor_wm);
 		enabled |= 2;
 	}
 	/* IVB has 3 pipes */
 	if (IS_IVYBRIDGE(dev) &&
 	    g4x_compute_wm0(dev, 2,
 			    &sandybridge_display_wm_info, latency,
 			    &sandybridge_cursor_wm_info, latency,
 			    &plane_wm, &cursor_wm)) {
 		I915_WRITE(WM0_PIPEC_IVB,
 			   (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
 		DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
 			      " plane %d, cursor: %d\n",
 			      plane_wm, cursor_wm);
 		enabled |= 3;
 	}
 	/*
 	 * Calculate and update the self-refresh watermark only when one
 	 * display plane is used.
 	 *
 	 * SNB support 3 levels of watermark.
 	 *
 	 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
 	 * and disabled in the descending order
 	 *
 	 */
 	I915_WRITE(WM3_LP_ILK, 0);
 	I915_WRITE(WM2_LP_ILK, 0);
 	I915_WRITE(WM1_LP_ILK, 0);
 	if (!single_plane_enabled(enabled))
 		return;
 	enabled = ffs(enabled) - 1;
 	/* WM1 */
 	if (!ironlake_compute_srwm(dev, 1, enabled,
 				   SNB_READ_WM1_LATENCY() * 500,
 				   &sandybridge_display_srwm_info,
 				   &sandybridge_cursor_srwm_info,
 				   &fbc_wm, &plane_wm, &cursor_wm))
 		return;
 	I915_WRITE(WM1_LP_ILK,
 		   WM1_LP_SR_EN |
 		   (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
 		   (fbc_wm << WM1_LP_FBC_SHIFT) |
 		   (plane_wm << WM1_LP_SR_SHIFT) |
 		   cursor_wm);
 	/* WM2 */
 	if (!ironlake_compute_srwm(dev, 2, enabled,
 				   SNB_READ_WM2_LATENCY() * 500,
 				   &sandybridge_display_srwm_info,
 				   &sandybridge_cursor_srwm_info,
 				   &fbc_wm, &plane_wm, &cursor_wm))
 		return;
 	I915_WRITE(WM2_LP_ILK,
 		   WM2_LP_EN |
 		   (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
 		   (fbc_wm << WM1_LP_FBC_SHIFT) |
 		   (plane_wm << WM1_LP_SR_SHIFT) |
 		   cursor_wm);
 	/* WM3 */
 	if (!ironlake_compute_srwm(dev, 3, enabled,
 				   SNB_READ_WM3_LATENCY() * 500,
 				   &sandybridge_display_srwm_info,
 				   &sandybridge_cursor_srwm_info,
 				   &fbc_wm, &plane_wm, &cursor_wm))
 		return;
 	I915_WRITE(WM3_LP_ILK,
 		   WM3_LP_EN |
 		   (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
 		   (fbc_wm << WM1_LP_FBC_SHIFT) |
 		   (plane_wm << WM1_LP_SR_SHIFT) |
 		   cursor_wm);
 }
 /**
  * intel_update_watermarks - update FIFO watermark values based on current modes
  *
  * Calculate watermark values for the various WM regs based on current mode
  * and plane configuration.
  *
  * There are several cases to deal with here:
  *   - normal (i.e. non-self-refresh)
  *   - self-refresh (SR) mode
  *   - lines are large relative to FIFO size (buffer can hold up to 2)
  *   - lines are small relative to FIFO size (buffer can hold more than 2
  *     lines), so need to account for TLB latency
  *
  *   The normal calculation is:
  *     watermark = dotclock * bytes per pixel * latency
  *   where latency is platform & configuration dependent (we assume pessimal
  *   values here).
  *
  *   The SR calculation is:
  *     watermark = (trunc(latency/line time)+1) * surface width *
  *       bytes per pixel
  *   where
  *     line time = htotal / dotclock
  *     surface width = hdisplay for normal plane and 64 for cursor
  *   and latency is assumed to be high, as above.
  *
  * The final value programmed to the register should always be rounded up,
  * and include an extra 2 entries to account for clock crossings.
  *
  * We don't use the sprite, so we can ignore that.  And on Crestline we have
  * to set the non-SR watermarks to 8.
  */
 static void intel_update_watermarks(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (dev_priv->display.update_wm)
 		dev_priv->display.update_wm(dev);
 }
 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
 {
 	if (i915_panel_use_ssc >= 0)
 		return i915_panel_use_ssc != 0;
 	return dev_priv->lvds_use_ssc
 		&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
 }
 /**
  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
  * @crtc: CRTC structure
  *
  * A pipe may be connected to one or more outputs.  Based on the depth of the
  * attached framebuffer, choose a good color depth to use on the pipe.
  *
  * If possible, match the pipe depth to the fb depth.  In some cases, this
  * isn't ideal, because the connected output supports a lesser or restricted
  * set of depths.  Resolve that here:
  *    LVDS typically supports only 6bpc, so clamp down in that case
  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
  *    Displays may support a restricted set as well, check EDID and clamp as
  *      appropriate.
  *
  * RETURNS:
  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
  * true if they don't match).
  */
 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
 					 unsigned int *pipe_bpp)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_encoder *encoder;
 	struct drm_connector *connector;
 	unsigned int display_bpc = UINT_MAX, bpc;
 	/* Walk the encoders & connectors on this crtc, get min bpc */
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 		struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
 		if (encoder->crtc != crtc)
 			continue;
 		if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
 			unsigned int lvds_bpc;
 			if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
 			    LVDS_A3_POWER_UP)
 				lvds_bpc = 8;
 			else
 				lvds_bpc = 6;
 			if (lvds_bpc < display_bpc) {
 				DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
 				display_bpc = lvds_bpc;
 			}
 			continue;
 		}
 		if (intel_encoder->type == INTEL_OUTPUT_EDP) {
 			/* Use VBT settings if we have an eDP panel */
 			unsigned int edp_bpc = dev_priv->edp.bpp / 3;
 			if (edp_bpc < display_bpc) {
 				DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
 				display_bpc = edp_bpc;
 			}
 			continue;
 		}
 		/* Not one of the known troublemakers, check the EDID */
 		list_for_each_entry(connector, &dev->mode_config.connector_list,
 				    head) {
 			if (connector->encoder != encoder)
 				continue;
 			/* Don't use an invalid EDID bpc value */
 			if (connector->display_info.bpc &&
 			    connector->display_info.bpc < display_bpc) {
 				DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
 				display_bpc = connector->display_info.bpc;
 			}
 		}
 		/*
 		 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
 		 * through, clamp it down.  (Note: >12bpc will be caught below.)
 		 */
 		if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
 			if (display_bpc > 8 && display_bpc < 12) {
 				DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
 				display_bpc = 12;
 			} else {
 				DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
 				display_bpc = 8;
 			}
 		}
 	}
 	/*
 	 * We could just drive the pipe at the highest bpc all the time and
 	 * enable dithering as needed, but that costs bandwidth.  So choose
 	 * the minimum value that expresses the full color range of the fb but
 	 * also stays within the max display bpc discovered above.
 	 */
 	switch (crtc->fb->depth) {
 	case 8:
 		bpc = 8; /* since we go through a colormap */
 		break;
 	case 15:
 	case 16:
 		bpc = 6; /* min is 18bpp */
 		break;
 	case 24:
 		bpc = 8;
 		break;
 	case 30:
 		bpc = 10;
 		break;
 	case 48:
 		bpc = 12;
 		break;
 	default:
 		DRM_DEBUG("unsupported depth, assuming 24 bits\n");
 		bpc = min((unsigned int)8, display_bpc);
 		break;
 	}
 	display_bpc = min(display_bpc, bpc);
 	DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
 		      bpc, display_bpc);
 	*pipe_bpp = display_bpc * 3;
 	return display_bpc != bpc;
 }
 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 			      struct drm_display_mode *mode,
 			      struct drm_display_mode *adjusted_mode,
 			      int x, int y,
 			      struct drm_framebuffer *old_fb)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	int plane = intel_crtc->plane;
 	int refclk, num_connectors = 0;
 	intel_clock_t clock, reduced_clock;
 	u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
 	bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
 	bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
 	struct drm_mode_config *mode_config = &dev->mode_config;
 	struct intel_encoder *encoder;
 	const intel_limit_t *limit;
 	int ret;
 	u32 temp;
 	u32 lvds_sync = 0;
 	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
 		if (encoder->base.crtc != crtc)
 			continue;
 		switch (encoder->type) {
 		case INTEL_OUTPUT_LVDS:
 			is_lvds = true;
 			break;
 		case INTEL_OUTPUT_SDVO:
 		case INTEL_OUTPUT_HDMI:
 			is_sdvo = true;
 			if (encoder->needs_tv_clock)
 				is_tv = true;
 			break;
 		case INTEL_OUTPUT_DVO:
 			is_dvo = true;
 			break;
 		case INTEL_OUTPUT_TVOUT:
 			is_tv = true;
 			break;
 		case INTEL_OUTPUT_ANALOG:
 			is_crt = true;
 			break;
 		case INTEL_OUTPUT_DISPLAYPORT:
 			is_dp = true;
 			break;
 		}
 		num_connectors++;
 	}
 	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
 		refclk = dev_priv->lvds_ssc_freq * 1000;
 		DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
 			      refclk / 1000);
 	} else if (!IS_GEN2(dev)) {
 		refclk = 96000;
 	} else {
 		refclk = 48000;
 	}
 	/*
 	 * Returns a set of divisors for the desired target clock with the given
 	 * refclk, or FALSE.  The returned values represent the clock equation:
 	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 	 */
 	limit = intel_limit(crtc, refclk);
 	ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
 	if (!ok) {
 		DRM_ERROR("Couldn't find PLL settings for mode!\n");
 		return -EINVAL;
 	}
 	/* Ensure that the cursor is valid for the new mode before changing... */
 	intel_crtc_update_cursor(crtc, true);
 	if (is_lvds && dev_priv->lvds_downclock_avail) {
 		has_reduced_clock = limit->find_pll(limit, crtc,
 						    dev_priv->lvds_downclock,
 						    refclk,
 						    &reduced_clock);
 		if (has_reduced_clock && (clock.p != reduced_clock.p)) {
 			/*
 			 * If the different P is found, it means that we can't
 			 * switch the display clock by using the FP0/FP1.
 			 * In such case we will disable the LVDS downclock
 			 * feature.
 			 */
 			DRM_DEBUG_KMS("Different P is found for "
 				      "LVDS clock/downclock\n");
 			has_reduced_clock = 0;
 		}
 	}
 	/* SDVO TV has fixed PLL values depend on its clock range,
 	   this mirrors vbios setting. */
 	if (is_sdvo && is_tv) {
 		if (adjusted_mode->clock >= 100000
 		    && adjusted_mode->clock < 140500) {
 			clock.p1 = 2;
 			clock.p2 = 10;
 			clock.n = 3;
 			clock.m1 = 16;
 			clock.m2 = 8;
 		} else if (adjusted_mode->clock >= 140500
 			   && adjusted_mode->clock <= 200000) {
 			clock.p1 = 1;
 			clock.p2 = 10;
 			clock.n = 6;
 			clock.m1 = 12;
 			clock.m2 = 8;
 		}
 	}
 	if (IS_PINEVIEW(dev)) {
 		fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
 		if (has_reduced_clock)
 			fp2 = (1 << reduced_clock.n) << 16 |
 				reduced_clock.m1 << 8 | reduced_clock.m2;
 	} else {
 		fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
 		if (has_reduced_clock)
 			fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
 				reduced_clock.m2;
 	}
 	dpll = DPLL_VGA_MODE_DIS;
 	if (!IS_GEN2(dev)) {
 		if (is_lvds)
 			dpll |= DPLLB_MODE_LVDS;
 		else
 			dpll |= DPLLB_MODE_DAC_SERIAL;
 		if (is_sdvo) {
 			int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
 			if (pixel_multiplier > 1) {
 				if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 					dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
 			}
 			dpll |= DPLL_DVO_HIGH_SPEED;
 		}
 		if (is_dp)
 			dpll |= DPLL_DVO_HIGH_SPEED;
 		/* compute bitmask from p1 value */
 		if (IS_PINEVIEW(dev))
 			dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
 		else {
 			dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
 			if (IS_G4X(dev) && has_reduced_clock)
 				dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
 		}
 		switch (clock.p2) {
 		case 5:
 			dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
 			break;
 		case 7:
 			dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
 			break;
 		case 10:
 			dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
 			break;
 		case 14:
 			dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
 			break;
 		}
 		if (INTEL_INFO(dev)->gen >= 4)
 			dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
 	} else {
 		if (is_lvds) {
 			dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
 		} else {
 			if (clock.p1 == 2)
 				dpll |= PLL_P1_DIVIDE_BY_TWO;
 			else
 				dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
 			if (clock.p2 == 4)
 				dpll |= PLL_P2_DIVIDE_BY_4;
 		}
 	}
 	if (is_sdvo && is_tv)
 		dpll |= PLL_REF_INPUT_TVCLKINBC;
 	else if (is_tv)
 		/* XXX: just matching BIOS for now */
 		/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
 		dpll |= 3;
 	else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
 		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
 	else
 		dpll |= PLL_REF_INPUT_DREFCLK;
 	/* setup pipeconf */
 	pipeconf = I915_READ(PIPECONF(pipe));
 	/* Set up the display plane register */
 	dspcntr = DISPPLANE_GAMMA_ENABLE;
 	/* Ironlake's plane is forced to pipe, bit 24 is to
 	   enable color space conversion */
 	if (pipe == 0)
 		dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
 	else
 		dspcntr |= DISPPLANE_SEL_PIPE_B;
 	if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
 		/* Enable pixel doubling when the dot clock is > 90% of the (display)
 		 * core speed.
 		 *
 		 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
 		 * pipe == 0 check?
 		 */
 		if (mode->clock >
 		    dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
 			pipeconf |= PIPECONF_DOUBLE_WIDE;
 		else
 			pipeconf &= ~PIPECONF_DOUBLE_WIDE;
 	}
 	dpll |= DPLL_VCO_ENABLE;
 	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
 	drm_mode_debug_printmodeline(mode);
 	I915_WRITE(FP0(pipe), fp);
 	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
 	POSTING_READ(DPLL(pipe));
 	udelay(150);
 	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
 	 * This is an exception to the general rule that mode_set doesn't turn
 	 * things on.
 	 */
 	if (is_lvds) {
 		temp = I915_READ(LVDS);
 		temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
 		if (pipe == 1) {
 			temp |= LVDS_PIPEB_SELECT;
 		} else {
 			temp &= ~LVDS_PIPEB_SELECT;
 		}
 		/* set the corresponsding LVDS_BORDER bit */
 		temp |= dev_priv->lvds_border_bits;
 		/* Set the B0-B3 data pairs corresponding to whether we're going to
 		 * set the DPLLs for dual-channel mode or not.
 		 */
 		if (clock.p2 == 7)
 			temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
 		else
 			temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
 		/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
 		 * appropriately here, but we need to look more thoroughly into how
 		 * panels behave in the two modes.
 		 */
 		/* set the dithering flag on LVDS as needed */
 		if (INTEL_INFO(dev)->gen >= 4) {
 			if (dev_priv->lvds_dither)
 				temp |= LVDS_ENABLE_DITHER;
 			else
 				temp &= ~LVDS_ENABLE_DITHER;
 		}
 		if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 			lvds_sync |= LVDS_HSYNC_POLARITY;
 		if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
 			lvds_sync |= LVDS_VSYNC_POLARITY;
 		if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
 		    != lvds_sync) {
 			char flags[2] = "-+";
 			DRM_INFO("Changing LVDS panel from "
 				 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
 				 flags[!(temp & LVDS_HSYNC_POLARITY)],
 				 flags[!(temp & LVDS_VSYNC_POLARITY)],
 				 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
 				 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
 			temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
 			temp |= lvds_sync;
 		}
 		I915_WRITE(LVDS, temp);
 	}
 	if (is_dp) {
 		intel_dp_set_m_n(crtc, mode, adjusted_mode);
 	}
 	I915_WRITE(DPLL(pipe), dpll);
 	/* Wait for the clocks to stabilize. */
 	POSTING_READ(DPLL(pipe));
 	udelay(150);
 	if (INTEL_INFO(dev)->gen >= 4) {
 		temp = 0;
 		if (is_sdvo) {
 			temp = intel_mode_get_pixel_multiplier(adjusted_mode);
 			if (temp > 1)
 				temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
 			else
 				temp = 0;
 		}
 		I915_WRITE(DPLL_MD(pipe), temp);
 	} else {
 		/* The pixel multiplier can only be updated once the
 		 * DPLL is enabled and the clocks are stable.
 		 *
 		 * So write it again.
 		 */
 		I915_WRITE(DPLL(pipe), dpll);
 	}
 	intel_crtc->lowfreq_avail = false;
 	if (is_lvds && has_reduced_clock && i915_powersave) {
 		I915_WRITE(FP1(pipe), fp2);
 		intel_crtc->lowfreq_avail = true;
 		if (HAS_PIPE_CXSR(dev)) {
 			DRM_DEBUG_KMS("enabling CxSR downclocking\n");
 			pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
 		}
 	} else {
 		I915_WRITE(FP1(pipe), fp);
 		if (HAS_PIPE_CXSR(dev)) {
 			DRM_DEBUG_KMS("disabling CxSR downclocking\n");
 			pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
 		}
 	}
 	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
 		pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
 		/* the chip adds 2 halflines automatically */
 		adjusted_mode->crtc_vdisplay -= 1;
 		adjusted_mode->crtc_vtotal -= 1;
 		adjusted_mode->crtc_vblank_start -= 1;
 		adjusted_mode->crtc_vblank_end -= 1;
 		adjusted_mode->crtc_vsync_end -= 1;
 		adjusted_mode->crtc_vsync_start -= 1;
 	} else
 		pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
 	I915_WRITE(HTOTAL(pipe),
 		   (adjusted_mode->crtc_hdisplay - 1) |
 		   ((adjusted_mode->crtc_htotal - 1) << 16));
 	I915_WRITE(HBLANK(pipe),
 		   (adjusted_mode->crtc_hblank_start - 1) |
 		   ((adjusted_mode->crtc_hblank_end - 1) << 16));
 	I915_WRITE(HSYNC(pipe),
 		   (adjusted_mode->crtc_hsync_start - 1) |
 		   ((adjusted_mode->crtc_hsync_end - 1) << 16));
 	I915_WRITE(VTOTAL(pipe),
 		   (adjusted_mode->crtc_vdisplay - 1) |
 		   ((adjusted_mode->crtc_vtotal - 1) << 16));
 	I915_WRITE(VBLANK(pipe),
 		   (adjusted_mode->crtc_vblank_start - 1) |
 		   ((adjusted_mode->crtc_vblank_end - 1) << 16));
 	I915_WRITE(VSYNC(pipe),
 		   (adjusted_mode->crtc_vsync_start - 1) |
 		   ((adjusted_mode->crtc_vsync_end - 1) << 16));
 	/* pipesrc and dspsize control the size that is scaled from,
 	 * which should always be the user's requested size.
 	 */
 	I915_WRITE(DSPSIZE(plane),
 		   ((mode->vdisplay - 1) << 16) |
 		   (mode->hdisplay - 1));
 	I915_WRITE(DSPPOS(plane), 0);
 	I915_WRITE(PIPESRC(pipe),
 		   ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
 	I915_WRITE(PIPECONF(pipe), pipeconf);
 	POSTING_READ(PIPECONF(pipe));
 	intel_enable_pipe(dev_priv, pipe, false);
 	intel_wait_for_vblank(dev, pipe);
 	I915_WRITE(DSPCNTR(plane), dspcntr);
 	POSTING_READ(DSPCNTR(plane));
 	intel_enable_plane(dev_priv, plane, pipe);
 	ret = intel_pipe_set_base(crtc, x, y, old_fb);
 	intel_update_watermarks(dev);
 	return ret;
 }
 /*
  * Initialize reference clocks when the driver loads
  */
 void ironlake_init_pch_refclk(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_mode_config *mode_config = &dev->mode_config;
 	struct intel_encoder *encoder;
 	u32 temp;
 	bool has_lvds = false;
 	bool has_cpu_edp = false;
 	bool has_pch_edp = false;
 	bool has_panel = false;
 	bool has_ck505 = false;
 	bool can_ssc = false;
 	/* We need to take the global config into account */
 	list_for_each_entry(encoder, &mode_config->encoder_list,
 			    base.head) {
 		switch (encoder->type) {
 		case INTEL_OUTPUT_LVDS:
 			has_panel = true;
 			has_lvds = true;
 			break;
 		case INTEL_OUTPUT_EDP:
 			has_panel = true;
 			if (intel_encoder_is_pch_edp(&encoder->base))
 				has_pch_edp = true;
 			else
 				has_cpu_edp = true;
 			break;
 		}
 	}
 	if (HAS_PCH_IBX(dev)) {
 		has_ck505 = dev_priv->display_clock_mode;
 		can_ssc = has_ck505;
 	} else {
 		has_ck505 = false;
 		can_ssc = true;
 	}
 	DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
 		      has_panel, has_lvds, has_pch_edp, has_cpu_edp,
 		      has_ck505);
 	/* Ironlake: try to setup display ref clock before DPLL
 	 * enabling. This is only under driver's control after
 	 * PCH B stepping, previous chipset stepping should be
 	 * ignoring this setting.
 	 */
 	temp = I915_READ(PCH_DREF_CONTROL);
 	/* Always enable nonspread source */
 	temp &= ~DREF_NONSPREAD_SOURCE_MASK;
 	if (has_ck505)
 		temp |= DREF_NONSPREAD_CK505_ENABLE;
 	else
 		temp |= DREF_NONSPREAD_SOURCE_ENABLE;
 	if (has_panel) {
 		temp &= ~DREF_SSC_SOURCE_MASK;
 		temp |= DREF_SSC_SOURCE_ENABLE;
 		/* SSC must be turned on before enabling the CPU output  */
 		if (intel_panel_use_ssc(dev_priv) && can_ssc) {
 			DRM_DEBUG_KMS("Using SSC on panel\n");
 			temp |= DREF_SSC1_ENABLE;
 		}
 		/* Get SSC going before enabling the outputs */
 		I915_WRITE(PCH_DREF_CONTROL, temp);
 		POSTING_READ(PCH_DREF_CONTROL);
 		udelay(200);
 		temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
 		/* Enable CPU source on CPU attached eDP */
 		if (has_cpu_edp) {
 			if (intel_panel_use_ssc(dev_priv) && can_ssc) {
 				DRM_DEBUG_KMS("Using SSC on eDP\n");
 				temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
 			}
 			else
 				temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
 		} else
 			temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
 		I915_WRITE(PCH_DREF_CONTROL, temp);
 		POSTING_READ(PCH_DREF_CONTROL);
 		udelay(200);
 	} else {
 		DRM_DEBUG_KMS("Disabling SSC entirely\n");
 		temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
 		/* Turn off CPU output */
 		temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
 		I915_WRITE(PCH_DREF_CONTROL, temp);
 		POSTING_READ(PCH_DREF_CONTROL);
 		udelay(200);
 		/* Turn off the SSC source */
 		temp &= ~DREF_SSC_SOURCE_MASK;
 		temp |= DREF_SSC_SOURCE_DISABLE;
 		/* Turn off SSC1 */
 		temp &= ~ DREF_SSC1_ENABLE;
 		I915_WRITE(PCH_DREF_CONTROL, temp);
 		POSTING_READ(PCH_DREF_CONTROL);
 		udelay(200);
 	}
 }
 static int ironlake_get_refclk(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_encoder *encoder;
 	struct drm_mode_config *mode_config = &dev->mode_config;
 	struct intel_encoder *edp_encoder = NULL;
 	int num_connectors = 0;
 	bool is_lvds = false;
 	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
 		if (encoder->base.crtc != crtc)
 			continue;
 		switch (encoder->type) {
 		case INTEL_OUTPUT_LVDS:
 			is_lvds = true;
 			break;
 		case INTEL_OUTPUT_EDP:
 			edp_encoder = encoder;
 			break;
 		}
 		num_connectors++;
 	}
 	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
 		DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
 			      dev_priv->lvds_ssc_freq);
 		return dev_priv->lvds_ssc_freq * 1000;
 	}
 	return 120000;
 }
 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 				  struct drm_display_mode *mode,
 				  struct drm_display_mode *adjusted_mode,
 				  int x, int y,
 				  struct drm_framebuffer *old_fb)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	int plane = intel_crtc->plane;
 	int refclk, num_connectors = 0;
 	intel_clock_t clock, reduced_clock;
 	u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
 	bool ok, has_reduced_clock = false, is_sdvo = false;
 	bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
 	struct intel_encoder *has_edp_encoder = NULL;
 	struct drm_mode_config *mode_config = &dev->mode_config;
 	struct intel_encoder *encoder;
 	const intel_limit_t *limit;
 	int ret;
 	struct fdi_m_n m_n = {0};
 	u32 temp;
 	u32 lvds_sync = 0;
 	int target_clock, pixel_multiplier, lane, link_bw, factor;
 	unsigned int pipe_bpp;
 	bool dither;
 	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
 		if (encoder->base.crtc != crtc)
 			continue;
 		switch (encoder->type) {
 		case INTEL_OUTPUT_LVDS:
 			is_lvds = true;
 			break;
 		case INTEL_OUTPUT_SDVO:
 		case INTEL_OUTPUT_HDMI:
 			is_sdvo = true;
 			if (encoder->needs_tv_clock)
 				is_tv = true;
 			break;
 		case INTEL_OUTPUT_TVOUT:
 			is_tv = true;
 			break;
 		case INTEL_OUTPUT_ANALOG:
 			is_crt = true;
 			break;
 		case INTEL_OUTPUT_DISPLAYPORT:
 			is_dp = true;
 			break;
 		case INTEL_OUTPUT_EDP:
 			has_edp_encoder = encoder;
 			break;
 		}
 		num_connectors++;
 	}
 	refclk = ironlake_get_refclk(crtc);
 	/*
 	 * Returns a set of divisors for the desired target clock with the given
 	 * refclk, or FALSE.  The returned values represent the clock equation:
 	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 	 */
 	limit = intel_limit(crtc, refclk);
 	ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
 	if (!ok) {
 		DRM_ERROR("Couldn't find PLL settings for mode!\n");
 		return -EINVAL;
 	}
 	/* Ensure that the cursor is valid for the new mode before changing... */
 	intel_crtc_update_cursor(crtc, true);
 	if (is_lvds && dev_priv->lvds_downclock_avail) {
 		has_reduced_clock = limit->find_pll(limit, crtc,
 						    dev_priv->lvds_downclock,
 						    refclk,
 						    &reduced_clock);
 		if (has_reduced_clock && (clock.p != reduced_clock.p)) {
 			/*
 			 * If the different P is found, it means that we can't
 			 * switch the display clock by using the FP0/FP1.
 			 * In such case we will disable the LVDS downclock
 			 * feature.
 			 */
 			DRM_DEBUG_KMS("Different P is found for "
 				      "LVDS clock/downclock\n");
 			has_reduced_clock = 0;
 		}
 	}
 	/* SDVO TV has fixed PLL values depend on its clock range,
 	   this mirrors vbios setting. */
 	if (is_sdvo && is_tv) {
 		if (adjusted_mode->clock >= 100000
 		    && adjusted_mode->clock < 140500) {
 			clock.p1 = 2;
 			clock.p2 = 10;
 			clock.n = 3;
 			clock.m1 = 16;
 			clock.m2 = 8;
 		} else if (adjusted_mode->clock >= 140500
 			   && adjusted_mode->clock <= 200000) {
 			clock.p1 = 1;
 			clock.p2 = 10;
 			clock.n = 6;
 			clock.m1 = 12;
 			clock.m2 = 8;
 		}
 	}
 	/* FDI link */
 	pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
 	lane = 0;
 	/* CPU eDP doesn't require FDI link, so just set DP M/N
 	   according to current link config */
 	if (has_edp_encoder &&
 	    !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
 		target_clock = mode->clock;
 		intel_edp_link_config(has_edp_encoder,
 				      &lane, &link_bw);
 	} else {
 		/* [e]DP over FDI requires target mode clock
 		   instead of link clock */
 		if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
 			target_clock = mode->clock;
 		else
 			target_clock = adjusted_mode->clock;
 		/* FDI is a binary signal running at ~2.7GHz, encoding
 		 * each output octet as 10 bits. The actual frequency
 		 * is stored as a divider into a 100MHz clock, and the
 		 * mode pixel clock is stored in units of 1KHz.
 		 * Hence the bw of each lane in terms of the mode signal
 		 * is:
 		 */
 		link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
 	}
 	/* determine panel color depth */
 	temp = I915_READ(PIPECONF(pipe));
 	temp &= ~PIPE_BPC_MASK;
 	dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
 	switch (pipe_bpp) {
 	case 18:
 		temp |= PIPE_6BPC;
 		break;
 	case 24:
 		temp |= PIPE_8BPC;
 		break;
 	case 30:
 		temp |= PIPE_10BPC;
 		break;
 	case 36:
 		temp |= PIPE_12BPC;
 		break;
 	default:
 		WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
 			pipe_bpp);
 		temp |= PIPE_8BPC;
 		pipe_bpp = 24;
 		break;
 	}
 	intel_crtc->bpp = pipe_bpp;
 	I915_WRITE(PIPECONF(pipe), temp);
 	if (!lane) {
 		/*
 		 * Account for spread spectrum to avoid
 		 * oversubscribing the link. Max center spread
 		 * is 2.5%; use 5% for safety's sake.
 		 */
 		u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
 		lane = bps / (link_bw * 8) + 1;
 	}
 	intel_crtc->fdi_lanes = lane;
 	if (pixel_multiplier > 1)
 		link_bw *= pixel_multiplier;
 	ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
 			     &m_n);
 	fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
 	if (has_reduced_clock)
 		fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
 			reduced_clock.m2;
 	/* Enable autotuning of the PLL clock (if permissible) */
 	factor = 21;
 	if (is_lvds) {
 		if ((intel_panel_use_ssc(dev_priv) &&
 		     dev_priv->lvds_ssc_freq == 100) ||
 		    (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
 			factor = 25;
 	} else if (is_sdvo && is_tv)
 		factor = 20;
 	if (clock.m < factor * clock.n)
 		fp |= FP_CB_TUNE;
 	dpll = 0;
 	if (is_lvds)
 		dpll |= DPLLB_MODE_LVDS;
 	else
 		dpll |= DPLLB_MODE_DAC_SERIAL;
 	if (is_sdvo) {
 		int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
 		if (pixel_multiplier > 1) {
 			dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
 		}
 		dpll |= DPLL_DVO_HIGH_SPEED;
 	}
 	if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
 		dpll |= DPLL_DVO_HIGH_SPEED;
 	/* compute bitmask from p1 value */
 	dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
 	/* also FPA1 */
 	dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
 	switch (clock.p2) {
 	case 5:
 		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
 		break;
 	case 7:
 		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
 		break;
 	case 10:
 		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
 		break;
 	case 14:
 		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
 		break;
 	}
 	if (is_sdvo && is_tv)
 		dpll |= PLL_REF_INPUT_TVCLKINBC;
 	else if (is_tv)
 		/* XXX: just matching BIOS for now */
 		/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
 		dpll |= 3;
 	else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
 		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
 	else
 		dpll |= PLL_REF_INPUT_DREFCLK;
 	/* setup pipeconf */
 	pipeconf = I915_READ(PIPECONF(pipe));
 	/* Set up the display plane register */
 	dspcntr = DISPPLANE_GAMMA_ENABLE;
 	DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
 	drm_mode_debug_printmodeline(mode);
 	/* PCH eDP needs FDI, but CPU eDP does not */
 	if (!intel_crtc->no_pll) {
 		if (!has_edp_encoder ||
 		    intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
 			I915_WRITE(PCH_FP0(pipe), fp);
 			I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
 			POSTING_READ(PCH_DPLL(pipe));
 			udelay(150);
 		}
 	} else {
 		if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
 		    fp == I915_READ(PCH_FP0(0))) {
 			intel_crtc->use_pll_a = true;
 			DRM_DEBUG_KMS("using pipe a dpll\n");
 		} else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
 			   fp == I915_READ(PCH_FP0(1))) {
 			intel_crtc->use_pll_a = false;
 			DRM_DEBUG_KMS("using pipe b dpll\n");
 		} else {
 			DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
 			return -EINVAL;
 		}
 	}
 	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
 	 * This is an exception to the general rule that mode_set doesn't turn
 	 * things on.
 	 */
 	if (is_lvds) {
 		temp = I915_READ(PCH_LVDS);
 		temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
 		if (HAS_PCH_CPT(dev))
 			temp |= PORT_TRANS_SEL_CPT(pipe);
 		else if (pipe == 1)
 			temp |= LVDS_PIPEB_SELECT;
 		else
 			temp &= ~LVDS_PIPEB_SELECT;
 		/* set the corresponsding LVDS_BORDER bit */
 		temp |= dev_priv->lvds_border_bits;
 		/* Set the B0-B3 data pairs corresponding to whether we're going to
 		 * set the DPLLs for dual-channel mode or not.
 		 */
 		if (clock.p2 == 7)
 			temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
 		else
 			temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
 		/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
 		 * appropriately here, but we need to look more thoroughly into how
 		 * panels behave in the two modes.
 		 */
 		if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 			lvds_sync |= LVDS_HSYNC_POLARITY;
 		if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
 			lvds_sync |= LVDS_VSYNC_POLARITY;
 		if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
 		    != lvds_sync) {
 			char flags[2] = "-+";
 			DRM_INFO("Changing LVDS panel from "
 				 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
 				 flags[!(temp & LVDS_HSYNC_POLARITY)],
 				 flags[!(temp & LVDS_VSYNC_POLARITY)],
 				 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
 				 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
 			temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
 			temp |= lvds_sync;
 		}
 		I915_WRITE(PCH_LVDS, temp);
 	}
 	pipeconf &= ~PIPECONF_DITHER_EN;
 	pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
 	if ((is_lvds && dev_priv->lvds_dither) || dither) {
 		pipeconf |= PIPECONF_DITHER_EN;
 		pipeconf |= PIPECONF_DITHER_TYPE_SP;
 	}
 	if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
 		intel_dp_set_m_n(crtc, mode, adjusted_mode);
 	} else {
 		/* For non-DP output, clear any trans DP clock recovery setting.*/
 		I915_WRITE(TRANSDATA_M1(pipe), 0);
 		I915_WRITE(TRANSDATA_N1(pipe), 0);
 		I915_WRITE(TRANSDPLINK_M1(pipe), 0);
 		I915_WRITE(TRANSDPLINK_N1(pipe), 0);
 	}
 	if (!intel_crtc->no_pll &&
 	    (!has_edp_encoder ||
 	     intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
 		I915_WRITE(PCH_DPLL(pipe), dpll);
 		/* Wait for the clocks to stabilize. */
 		POSTING_READ(PCH_DPLL(pipe));
 		udelay(150);
 		/* The pixel multiplier can only be updated once the
 		 * DPLL is enabled and the clocks are stable.
 		 *
 		 * So write it again.
 		 */
 		I915_WRITE(PCH_DPLL(pipe), dpll);
 	}
 	intel_crtc->lowfreq_avail = false;
 	if (!intel_crtc->no_pll) {
 		if (is_lvds && has_reduced_clock && i915_powersave) {
 			I915_WRITE(PCH_FP1(pipe), fp2);
 			intel_crtc->lowfreq_avail = true;
 			if (HAS_PIPE_CXSR(dev)) {
 				DRM_DEBUG_KMS("enabling CxSR downclocking\n");
 				pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
 			}
 		} else {
 			I915_WRITE(PCH_FP1(pipe), fp);
 			if (HAS_PIPE_CXSR(dev)) {
 				DRM_DEBUG_KMS("disabling CxSR downclocking\n");
 				pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
 			}
 		}
 	}
 	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
 		pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
 		/* the chip adds 2 halflines automatically */
 		adjusted_mode->crtc_vdisplay -= 1;
 		adjusted_mode->crtc_vtotal -= 1;
 		adjusted_mode->crtc_vblank_start -= 1;
 		adjusted_mode->crtc_vblank_end -= 1;
 		adjusted_mode->crtc_vsync_end -= 1;
 		adjusted_mode->crtc_vsync_start -= 1;
 	} else
 		pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
 	I915_WRITE(HTOTAL(pipe),
 		   (adjusted_mode->crtc_hdisplay - 1) |
 		   ((adjusted_mode->crtc_htotal - 1) << 16));
 	I915_WRITE(HBLANK(pipe),
 		   (adjusted_mode->crtc_hblank_start - 1) |
 		   ((adjusted_mode->crtc_hblank_end - 1) << 16));
 	I915_WRITE(HSYNC(pipe),
 		   (adjusted_mode->crtc_hsync_start - 1) |
 		   ((adjusted_mode->crtc_hsync_end - 1) << 16));
 	I915_WRITE(VTOTAL(pipe),
 		   (adjusted_mode->crtc_vdisplay - 1) |
 		   ((adjusted_mode->crtc_vtotal - 1) << 16));
 	I915_WRITE(VBLANK(pipe),
 		   (adjusted_mode->crtc_vblank_start - 1) |
 		   ((adjusted_mode->crtc_vblank_end - 1) << 16));
 	I915_WRITE(VSYNC(pipe),
 		   (adjusted_mode->crtc_vsync_start - 1) |
 		   ((adjusted_mode->crtc_vsync_end - 1) << 16));
 	/* pipesrc controls the size that is scaled from, which should
 	 * always be the user's requested size.
 	 */
 	I915_WRITE(PIPESRC(pipe),
 		   ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
 	I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
 	I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
 	I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
 	I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
 	if (has_edp_encoder &&
 	    !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
 		ironlake_set_pll_edp(crtc, adjusted_mode->clock);
 	}
 	I915_WRITE(PIPECONF(pipe), pipeconf);
 	POSTING_READ(PIPECONF(pipe));
 	intel_wait_for_vblank(dev, pipe);
 	if (IS_GEN5(dev)) {
 		/* enable address swizzle for tiling buffer */
 		temp = I915_READ(DISP_ARB_CTL);
 		I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
 	}
 	I915_WRITE(DSPCNTR(plane), dspcntr);
 	POSTING_READ(DSPCNTR(plane));
 	ret = intel_pipe_set_base(crtc, x, y, old_fb);
 	intel_update_watermarks(dev);
 	return ret;
 }
 static int intel_crtc_mode_set(struct drm_crtc *crtc,
 			       struct drm_display_mode *mode,
 			       struct drm_display_mode *adjusted_mode,
 			       int x, int y,
 			       struct drm_framebuffer *old_fb)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	int ret;
 	drm_vblank_pre_modeset(dev, pipe);
 	ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
 					      x, y, old_fb);
 	drm_vblank_post_modeset(dev, pipe);
 	intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
 	return ret;
 }
 static void g4x_write_eld(struct drm_connector *connector,
 			  struct drm_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = connector->dev->dev_private;
 	uint8_t *eld = connector->eld;
 	uint32_t eldv;
 	uint32_t len;
 	uint32_t i;
 	i = I915_READ(G4X_AUD_VID_DID);
 	if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
 		eldv = G4X_ELDV_DEVCL_DEVBLC;
 	else
 		eldv = G4X_ELDV_DEVCTG;
 	i = I915_READ(G4X_AUD_CNTL_ST);
 	i &= ~(eldv | G4X_ELD_ADDR);
 	len = (i >> 9) & 0x1f;		/* ELD buffer size */
 	I915_WRITE(G4X_AUD_CNTL_ST, i);
 	if (!eld[0])
 		return;
 	len = min_t(uint8_t, eld[2], len);
 	DRM_DEBUG_DRIVER("ELD size %d\n", len);
 	for (i = 0; i < len; i++)
 		I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
 	i = I915_READ(G4X_AUD_CNTL_ST);
 	i |= eldv;
 	I915_WRITE(G4X_AUD_CNTL_ST, i);
 }
 static void ironlake_write_eld(struct drm_connector *connector,
 				     struct drm_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = connector->dev->dev_private;
 	uint8_t *eld = connector->eld;
 	uint32_t eldv;
 	uint32_t i;
 	int len;
 	int hdmiw_hdmiedid;
 	int aud_cntl_st;
 	int aud_cntrl_st2;
 	if (IS_IVYBRIDGE(connector->dev)) {
 		hdmiw_hdmiedid = GEN7_HDMIW_HDMIEDID_A;
 		aud_cntl_st = GEN7_AUD_CNTRL_ST_A;
 		aud_cntrl_st2 = GEN7_AUD_CNTRL_ST2;
 	} else {
 		hdmiw_hdmiedid = GEN5_HDMIW_HDMIEDID_A;
 		aud_cntl_st = GEN5_AUD_CNTL_ST_A;
 		aud_cntrl_st2 = GEN5_AUD_CNTL_ST2;
 	}
 	i = to_intel_crtc(crtc)->pipe;
 	hdmiw_hdmiedid += i * 0x100;
 	aud_cntl_st += i * 0x100;
 	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
 	i = I915_READ(aud_cntl_st);
 	i = (i >> 29) & 0x3;		/* DIP_Port_Select, 0x1 = PortB */
 	if (!i) {
 		DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
 		/* operate blindly on all ports */
 		eldv = GEN5_ELD_VALIDB;
 		eldv |= GEN5_ELD_VALIDB << 4;
 		eldv |= GEN5_ELD_VALIDB << 8;
 	} else {
 		DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
 		eldv = GEN5_ELD_VALIDB << ((i - 1) * 4);
 	}
 	i = I915_READ(aud_cntrl_st2);
 	i &= ~eldv;
 	I915_WRITE(aud_cntrl_st2, i);
 	if (!eld[0])
 		return;
 	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 		DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
 		eld[5] |= (1 << 2);	/* Conn_Type, 0x1 = DisplayPort */
 	}
 	i = I915_READ(aud_cntl_st);
 	i &= ~GEN5_ELD_ADDRESS;
 	I915_WRITE(aud_cntl_st, i);
 	len = min_t(uint8_t, eld[2], 21);	/* 84 bytes of hw ELD buffer */
 	DRM_DEBUG_DRIVER("ELD size %d\n", len);
 	for (i = 0; i < len; i++)
 		I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
 	i = I915_READ(aud_cntrl_st2);
 	i |= eldv;
 	I915_WRITE(aud_cntrl_st2, i);
 }
 void intel_write_eld(struct drm_encoder *encoder,
 		     struct drm_display_mode *mode)
 {
 	struct drm_crtc *crtc = encoder->crtc;
 	struct drm_connector *connector;
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	connector = drm_select_eld(encoder, mode);
 	if (!connector)
 		return;
 	DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
 			 connector->base.id,
 			 drm_get_connector_name(connector),
 			 connector->encoder->base.id,
 			 drm_get_encoder_name(connector->encoder));
 	connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
 	if (dev_priv->display.write_eld)
 		dev_priv->display.write_eld(connector, crtc);
 }
 /** Loads the palette/gamma unit for the CRTC with the prepared values */
 void intel_crtc_load_lut(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int palreg = PALETTE(intel_crtc->pipe);
 	int i;
 	/* The clocks have to be on to load the palette. */
 	if (!crtc->enabled)
 		return;
 	/* use legacy palette for Ironlake */
 	if (HAS_PCH_SPLIT(dev))
 		palreg = LGC_PALETTE(intel_crtc->pipe);
 	for (i = 0; i < 256; i++) {
 		I915_WRITE(palreg + 4 * i,
 			   (intel_crtc->lut_r[i] << 16) |
 			   (intel_crtc->lut_g[i] << 8) |
 			   intel_crtc->lut_b[i]);
 	}
 }
 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	bool visible = base != 0;
 	u32 cntl;
 	if (intel_crtc->cursor_visible == visible)
 		return;
 	cntl = I915_READ(_CURACNTR);
 	if (visible) {
 		/* On these chipsets we can only modify the base whilst
 		 * the cursor is disabled.
 		 */
 		I915_WRITE(_CURABASE, base);
 		cntl &= ~(CURSOR_FORMAT_MASK);
 		/* XXX width must be 64, stride 256 => 0x00 << 28 */
 		cntl |= CURSOR_ENABLE |
 			CURSOR_GAMMA_ENABLE |
 			CURSOR_FORMAT_ARGB;
 	} else
 		cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
 	I915_WRITE(_CURACNTR, cntl);
 	intel_crtc->cursor_visible = visible;
 }
 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	bool visible = base != 0;
 	if (intel_crtc->cursor_visible != visible) {
 		uint32_t cntl = I915_READ(CURCNTR(pipe));
 		if (base) {
 			cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
 			cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
 			cntl |= pipe << 28; /* Connect to correct pipe */
 		} else {
 			cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
 			cntl |= CURSOR_MODE_DISABLE;
 		}
 		I915_WRITE(CURCNTR(pipe), cntl);
 		intel_crtc->cursor_visible = visible;
 	}
 	/* and commit changes on next vblank */
 	I915_WRITE(CURBASE(pipe), base);
 }
 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	bool visible = base != 0;
 	if (intel_crtc->cursor_visible != visible) {
 		uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
 		if (base) {
 			cntl &= ~CURSOR_MODE;
 			cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
 		} else {
 			cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
 			cntl |= CURSOR_MODE_DISABLE;
 		}
 		I915_WRITE(CURCNTR_IVB(pipe), cntl);
 		intel_crtc->cursor_visible = visible;
 	}
 	/* and commit changes on next vblank */
 	I915_WRITE(CURBASE_IVB(pipe), base);
 }
 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
 				     bool on)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	int x = intel_crtc->cursor_x;
 	int y = intel_crtc->cursor_y;
 	u32 base, pos;
 	bool visible;
 	pos = 0;
 	if (on && crtc->enabled && crtc->fb) {
 		base = intel_crtc->cursor_addr;
 		if (x > (int) crtc->fb->width)
 			base = 0;
 		if (y > (int) crtc->fb->height)
 			base = 0;
 	} else
 		base = 0;
 	if (x < 0) {
 		if (x + intel_crtc->cursor_width < 0)
 			base = 0;
 		pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
 		x = -x;
 	}
 	pos |= x << CURSOR_X_SHIFT;
 	if (y < 0) {
 		if (y + intel_crtc->cursor_height < 0)
 			base = 0;
 		pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
 		y = -y;
 	}
 	pos |= y << CURSOR_Y_SHIFT;
 	visible = base != 0;
 	if (!visible && !intel_crtc->cursor_visible)
 		return;
 	if (IS_IVYBRIDGE(dev)) {
 		I915_WRITE(CURPOS_IVB(pipe), pos);
 		ivb_update_cursor(crtc, base);
 	} else {
 		I915_WRITE(CURPOS(pipe), pos);
 		if (IS_845G(dev) || IS_I865G(dev))
 			i845_update_cursor(crtc, base);
 		else
 			i9xx_update_cursor(crtc, base);
 	}
 	if (visible)
 		intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
 }
 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
 				 struct drm_file *file,
 				 uint32_t handle,
 				 uint32_t width, uint32_t height)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct drm_i915_gem_object *obj;
 	uint32_t addr;
 	int ret;
 	DRM_DEBUG_KMS("\n");
 	/* if we want to turn off the cursor ignore width and height */
 	if (!handle) {
 		DRM_DEBUG_KMS("cursor off\n");
 		addr = 0;
 		obj = NULL;
 		mutex_lock(&dev->struct_mutex);
 		goto finish;
 	}
 	/* Currently we only support 64x64 cursors */
 	if (width != 64 || height != 64) {
 		DRM_ERROR("we currently only support 64x64 cursors\n");
 		return -EINVAL;
 	}
 	obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
 	if (&obj->base == NULL)
 		return -ENOENT;
 	if (obj->base.size < width * height * 4) {
 		DRM_ERROR("buffer is to small\n");
 		ret = -ENOMEM;
 		goto fail;
 	}
 	/* we only need to pin inside GTT if cursor is non-phy */
 	mutex_lock(&dev->struct_mutex);
 	if (!dev_priv->info->cursor_needs_physical) {
 		if (obj->tiling_mode) {
 			DRM_ERROR("cursor cannot be tiled\n");
 			ret = -EINVAL;
 			goto fail_locked;
 		}
 		ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
 		if (ret) {
 			DRM_ERROR("failed to move cursor bo into the GTT\n");
 			goto fail_locked;
 		}
 		ret = i915_gem_object_put_fence(obj);
 		if (ret) {
 			DRM_ERROR("failed to release fence for cursor");
 			goto fail_unpin;
 		}
 		addr = obj->gtt_offset;
 	} else {
 		int align = IS_I830(dev) ? 16 * 1024 : 256;
 		ret = i915_gem_attach_phys_object(dev, obj,
 						  (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
 						  align);
 		if (ret) {
 			DRM_ERROR("failed to attach phys object\n");
 			goto fail_locked;
 		}
 		addr = obj->phys_obj->handle->busaddr;
 	}
 	if (IS_GEN2(dev))
 		I915_WRITE(CURSIZE, (height << 12) | width);
  finish:
 	if (intel_crtc->cursor_bo) {
 		if (dev_priv->info->cursor_needs_physical) {
 			if (intel_crtc->cursor_bo != obj)
 				i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
 		} else
 			i915_gem_object_unpin(intel_crtc->cursor_bo);
 		drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
 	}
 	mutex_unlock(&dev->struct_mutex);
 	intel_crtc->cursor_addr = addr;
 	intel_crtc->cursor_bo = obj;
 	intel_crtc->cursor_width = width;
 	intel_crtc->cursor_height = height;
 	intel_crtc_update_cursor(crtc, true);
 	return 0;
 fail_unpin:
 	i915_gem_object_unpin(obj);
 fail_locked:
 	mutex_unlock(&dev->struct_mutex);
 fail:
 	drm_gem_object_unreference_unlocked(&obj->base);
 	return ret;
 }
 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 {
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	intel_crtc->cursor_x = x;
 	intel_crtc->cursor_y = y;
 	intel_crtc_update_cursor(crtc, true);
 	return 0;
 }
 /** Sets the color ramps on behalf of RandR */
 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 				 u16 blue, int regno)
 {
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	intel_crtc->lut_r[regno] = red >> 8;
 	intel_crtc->lut_g[regno] = green >> 8;
 	intel_crtc->lut_b[regno] = blue >> 8;
 }
 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 			     u16 *blue, int regno)
 {
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	*red = intel_crtc->lut_r[regno] << 8;
 	*green = intel_crtc->lut_g[regno] << 8;
 	*blue = intel_crtc->lut_b[regno] << 8;
 }
 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 				 u16 *blue, uint32_t start, uint32_t size)
 {
 	int end = (start + size > 256) ? 256 : start + size, i;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	for (i = start; i < end; i++) {
 		intel_crtc->lut_r[i] = red[i] >> 8;
 		intel_crtc->lut_g[i] = green[i] >> 8;
 		intel_crtc->lut_b[i] = blue[i] >> 8;
 	}
 	intel_crtc_load_lut(crtc);
 }
 /**
  * Get a pipe with a simple mode set on it for doing load-based monitor
  * detection.
  *
  * It will be up to the load-detect code to adjust the pipe as appropriate for
  * its requirements.  The pipe will be connected to no other encoders.
  *
  * Currently this code will only succeed if there is a pipe with no encoders
  * configured for it.  In the future, it could choose to temporarily disable
  * some outputs to free up a pipe for its use.
  *
  * \return crtc, or NULL if no pipes are available.
  */
 /* VESA 640x480x72Hz mode to set on the pipe */
 static struct drm_display_mode load_detect_mode = {
 	DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
 		 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 };
 static struct drm_framebuffer *
 intel_framebuffer_create(struct drm_device *dev,
 			 struct drm_mode_fb_cmd *mode_cmd,
 			 struct drm_i915_gem_object *obj)
 {
 	struct intel_framebuffer *intel_fb;
 	int ret;
 	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
 	if (!intel_fb) {
 		drm_gem_object_unreference_unlocked(&obj->base);
 		return ERR_PTR(-ENOMEM);
 	}
 	ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
 	if (ret) {
 		drm_gem_object_unreference_unlocked(&obj->base);
 		kfree(intel_fb);
 		return ERR_PTR(ret);
 	}
 	return &intel_fb->base;
 }
 static u32
 intel_framebuffer_pitch_for_width(int width, int bpp)
 {
 	u32 pitch = DIV_ROUND_UP(width * bpp, 8);
 	return ALIGN(pitch, 64);
 }
 static u32
 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
 {
 	u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
 	return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
 }
 static struct drm_framebuffer *
 intel_framebuffer_create_for_mode(struct drm_device *dev,
 				  struct drm_display_mode *mode,
 				  int depth, int bpp)
 {
 	struct drm_i915_gem_object *obj;
 	struct drm_mode_fb_cmd mode_cmd;
 	obj = i915_gem_alloc_object(dev,
 				    intel_framebuffer_size_for_mode(mode, bpp));
 	if (obj == NULL)
 		return ERR_PTR(-ENOMEM);
 	mode_cmd.width = mode->hdisplay;
 	mode_cmd.height = mode->vdisplay;
 	mode_cmd.depth = depth;
 	mode_cmd.bpp = bpp;
 	mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
 	return intel_framebuffer_create(dev, &mode_cmd, obj);
 }
 static struct drm_framebuffer *
 mode_fits_in_fbdev(struct drm_device *dev,
 		   struct drm_display_mode *mode)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_i915_gem_object *obj;
 	struct drm_framebuffer *fb;
 	if (dev_priv->fbdev == NULL)
 		return NULL;
 	obj = dev_priv->fbdev->ifb.obj;
 	if (obj == NULL)
 		return NULL;
 	fb = &dev_priv->fbdev->ifb.base;
 	if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
 							  fb->bits_per_pixel))
 		return NULL;
 	if (obj->base.size < mode->vdisplay * fb->pitch)
 		return NULL;
 	return fb;
 }
 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
 				struct drm_connector *connector,
 				struct drm_display_mode *mode,
 				struct intel_load_detect_pipe *old)
 {
 	struct intel_crtc *intel_crtc;
 	struct drm_crtc *possible_crtc;
 	struct drm_encoder *encoder = &intel_encoder->base;
 	struct drm_crtc *crtc = NULL;
 	struct drm_device *dev = encoder->dev;
 	struct drm_framebuffer *old_fb;
 	int i = -1;
 	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
 		      connector->base.id, drm_get_connector_name(connector),
 		      encoder->base.id, drm_get_encoder_name(encoder));
 	/*
 	 * Algorithm gets a little messy:
 	 *
 	 *   - if the connector already has an assigned crtc, use it (but make
 	 *     sure it's on first)
 	 *
 	 *   - try to find the first unused crtc that can drive this connector,
 	 *     and use that if we find one
 	 */
 	/* See if we already have a CRTC for this connector */
 	if (encoder->crtc) {
 		crtc = encoder->crtc;
 		intel_crtc = to_intel_crtc(crtc);
 		old->dpms_mode = intel_crtc->dpms_mode;
 		old->load_detect_temp = false;
 		/* Make sure the crtc and connector are running */
 		if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
 			struct drm_encoder_helper_funcs *encoder_funcs;
 			struct drm_crtc_helper_funcs *crtc_funcs;
 			crtc_funcs = crtc->helper_private;
 			crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
 			encoder_funcs = encoder->helper_private;
 			encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
 		}
 		return true;
 	}
 	/* Find an unused one (if possible) */
 	list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
 		i++;
 		if (!(encoder->possible_crtcs & (1 << i)))
 			continue;
 		if (!possible_crtc->enabled) {
 			crtc = possible_crtc;
 			break;
 		}
 	}
 	/*
 	 * If we didn't find an unused CRTC, don't use any.
 	 */
 	if (!crtc) {
 		DRM_DEBUG_KMS("no pipe available for load-detect\n");
 		return false;
 	}
 	encoder->crtc = crtc;
 	connector->encoder = encoder;
 	intel_crtc = to_intel_crtc(crtc);
 	old->dpms_mode = intel_crtc->dpms_mode;
 	old->load_detect_temp = true;
 	old->release_fb = NULL;
 	if (!mode)
 		mode = &load_detect_mode;
 	old_fb = crtc->fb;
 	/* We need a framebuffer large enough to accommodate all accesses
 	 * that the plane may generate whilst we perform load detection.
 	 * We can not rely on the fbcon either being present (we get called
 	 * during its initialisation to detect all boot displays, or it may
 	 * not even exist) or that it is large enough to satisfy the
 	 * requested mode.
 	 */
 	crtc->fb = mode_fits_in_fbdev(dev, mode);
 	if (crtc->fb == NULL) {
 		DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
 		crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
 		old->release_fb = crtc->fb;
 	} else
 		DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
 	if (IS_ERR(crtc->fb)) {
 		DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
 		crtc->fb = old_fb;
 		return false;
 	}
 	if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
 		DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
 		if (old->release_fb)
 			old->release_fb->funcs->destroy(old->release_fb);
 		crtc->fb = old_fb;
 		return false;
 	}
 	/* let the connector get through one full cycle before testing */
 	intel_wait_for_vblank(dev, intel_crtc->pipe);
 	return true;
 }
 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
 				    struct drm_connector *connector,
 				    struct intel_load_detect_pipe *old)
 {
 	struct drm_encoder *encoder = &intel_encoder->base;
 	struct drm_device *dev = encoder->dev;
 	struct drm_crtc *crtc = encoder->crtc;
 	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
 	struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 	DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
 		      connector->base.id, drm_get_connector_name(connector),
 		      encoder->base.id, drm_get_encoder_name(encoder));
 	if (old->load_detect_temp) {
 		connector->encoder = NULL;
 		drm_helper_disable_unused_functions(dev);
 		if (old->release_fb)
 			old->release_fb->funcs->destroy(old->release_fb);
 		return;
 	}
 	/* Switch crtc and encoder back off if necessary */
 	if (old->dpms_mode != DRM_MODE_DPMS_ON) {
 		encoder_funcs->dpms(encoder, old->dpms_mode);
 		crtc_funcs->dpms(crtc, old->dpms_mode);
 	}
 }
 /* Returns the clock of the currently programmed mode of the given pipe. */
 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	u32 dpll = I915_READ(DPLL(pipe));
 	u32 fp;
 	intel_clock_t clock;
 	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
 		fp = I915_READ(FP0(pipe));
 	else
 		fp = I915_READ(FP1(pipe));
 	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
 	if (IS_PINEVIEW(dev)) {
 		clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
 		clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
 	} else {
 		clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
 		clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
 	}
 	if (!IS_GEN2(dev)) {
 		if (IS_PINEVIEW(dev))
 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
 				DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
 		else
 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
 			       DPLL_FPA01_P1_POST_DIV_SHIFT);
 		switch (dpll & DPLL_MODE_MASK) {
 		case DPLLB_MODE_DAC_SERIAL:
 			clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
 				5 : 10;
 			break;
 		case DPLLB_MODE_LVDS:
 			clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
 				7 : 14;
 			break;
 		default:
 			DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
 				  "mode\n", (int)(dpll & DPLL_MODE_MASK));
 			return 0;
 		}
 		/* XXX: Handle the 100Mhz refclk */
 		intel_clock(dev, 96000, &clock);
 	} else {
 		bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
 		if (is_lvds) {
 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
 				       DPLL_FPA01_P1_POST_DIV_SHIFT);
 			clock.p2 = 14;
 			if ((dpll & PLL_REF_INPUT_MASK) ==
 			    PLLB_REF_INPUT_SPREADSPECTRUMIN) {
 				/* XXX: might not be 66MHz */
 				intel_clock(dev, 66000, &clock);
 			} else
 				intel_clock(dev, 48000, &clock);
 		} else {
 			if (dpll & PLL_P1_DIVIDE_BY_TWO)
 				clock.p1 = 2;
 			else {
 				clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
 					    DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
 			}
 			if (dpll & PLL_P2_DIVIDE_BY_4)
 				clock.p2 = 4;
 			else
 				clock.p2 = 2;
 			intel_clock(dev, 48000, &clock);
 		}
 	}
 	/* XXX: It would be nice to validate the clocks, but we can't reuse
 	 * i830PllIsValid() because it relies on the xf86_config connector
 	 * configuration being accurate, which it isn't necessarily.
 	 */
 	return clock.dot;
 }
 /** Returns the currently programmed mode of the given pipe. */
 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 					     struct drm_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	struct drm_display_mode *mode;
 	int htot = I915_READ(HTOTAL(pipe));
 	int hsync = I915_READ(HSYNC(pipe));
 	int vtot = I915_READ(VTOTAL(pipe));
 	int vsync = I915_READ(VSYNC(pipe));
 	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
 	if (!mode)
 		return NULL;
 	mode->clock = intel_crtc_clock_get(dev, crtc);
 	mode->hdisplay = (htot & 0xffff) + 1;
 	mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
 	mode->hsync_start = (hsync & 0xffff) + 1;
 	mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
 	mode->vdisplay = (vtot & 0xffff) + 1;
 	mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
 	mode->vsync_start = (vsync & 0xffff) + 1;
 	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
 	drm_mode_set_name(mode);
 	drm_mode_set_crtcinfo(mode, 0);
 	return mode;
 }
 #define GPU_IDLE_TIMEOUT 500 /* ms */
 /* When this timer fires, we've been idle for awhile */
 static void intel_gpu_idle_timer(unsigned long arg)
 {
 	struct drm_device *dev = (struct drm_device *)arg;
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	if (!list_empty(&dev_priv->mm.active_list)) {
 		/* Still processing requests, so just re-arm the timer. */
 		mod_timer(&dev_priv->idle_timer, jiffies +
 			  msecs_to_jiffies(GPU_IDLE_TIMEOUT));
 		return;
 	}
 	dev_priv->busy = false;
 	queue_work(dev_priv->wq, &dev_priv->idle_work);
 }
 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
 static void intel_crtc_idle_timer(unsigned long arg)
 {
 	struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
 	struct drm_crtc *crtc = &intel_crtc->base;
 	drm_i915_private_t *dev_priv = crtc->dev->dev_private;
 	struct intel_framebuffer *intel_fb;
 	intel_fb = to_intel_framebuffer(crtc->fb);
 	if (intel_fb && intel_fb->obj->active) {
 		/* The framebuffer is still being accessed by the GPU. */
 		mod_timer(&intel_crtc->idle_timer, jiffies +
 			  msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
 		return;
 	}
 	intel_crtc->busy = false;
 	queue_work(dev_priv->wq, &dev_priv->idle_work);
 }
 static void intel_increase_pllclock(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	int dpll_reg = DPLL(pipe);
 	int dpll;
 	if (HAS_PCH_SPLIT(dev))
 		return;
 	if (!dev_priv->lvds_downclock_avail)
 		return;
 	dpll = I915_READ(dpll_reg);
 	if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
 		DRM_DEBUG_DRIVER("upclocking LVDS\n");
 		/* Unlock panel regs */
 		I915_WRITE(PP_CONTROL,
 			   I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
 		dpll &= ~DISPLAY_RATE_SELECT_FPA1;
 		I915_WRITE(dpll_reg, dpll);
 		intel_wait_for_vblank(dev, pipe);
 		dpll = I915_READ(dpll_reg);
 		if (dpll & DISPLAY_RATE_SELECT_FPA1)
 			DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
 		/* ...and lock them again */
 		I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
 	}
 	/* Schedule downclock */
 	mod_timer(&intel_crtc->idle_timer, jiffies +
 		  msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
 }
 static void intel_decrease_pllclock(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	int dpll_reg = DPLL(pipe);
 	int dpll = I915_READ(dpll_reg);
 	if (HAS_PCH_SPLIT(dev))
 		return;
 	if (!dev_priv->lvds_downclock_avail)
 		return;
 	/*
 	 * Since this is called by a timer, we should never get here in
 	 * the manual case.
 	 */
 	if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
 		DRM_DEBUG_DRIVER("downclocking LVDS\n");
 		/* Unlock panel regs */
 		I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
 			   PANEL_UNLOCK_REGS);
 		dpll |= DISPLAY_RATE_SELECT_FPA1;
 		I915_WRITE(dpll_reg, dpll);
 		intel_wait_for_vblank(dev, pipe);
 		dpll = I915_READ(dpll_reg);
 		if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
 			DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
 		/* ...and lock them again */
 		I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
 	}
 }
 /**
  * intel_idle_update - adjust clocks for idleness
  * @work: work struct
  *
  * Either the GPU or display (or both) went idle.  Check the busy status
  * here and adjust the CRTC and GPU clocks as necessary.
  */
 static void intel_idle_update(struct work_struct *work)
 {
 	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 						    idle_work);
 	struct drm_device *dev = dev_priv->dev;
 	struct drm_crtc *crtc;
 	struct intel_crtc *intel_crtc;
 	if (!i915_powersave)
 		return;
 	mutex_lock(&dev->struct_mutex);
 	i915_update_gfx_val(dev_priv);
 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 		/* Skip inactive CRTCs */
 		if (!crtc->fb)
 			continue;
 		intel_crtc = to_intel_crtc(crtc);
 		if (!intel_crtc->busy)
 			intel_decrease_pllclock(crtc);
 	}
 	mutex_unlock(&dev->struct_mutex);
 }
 /**
  * intel_mark_busy - mark the GPU and possibly the display busy
  * @dev: drm device
  * @obj: object we're operating on
  *
  * Callers can use this function to indicate that the GPU is busy processing
  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
  * buffer), we'll also mark the display as busy, so we know to increase its
  * clock frequency.
  */
 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct drm_crtc *crtc = NULL;
 	struct intel_framebuffer *intel_fb;
 	struct intel_crtc *intel_crtc;
 	if (!drm_core_check_feature(dev, DRIVER_MODESET))
 		return;
 	if (!dev_priv->busy)
 		dev_priv->busy = true;
 	else
 		mod_timer(&dev_priv->idle_timer, jiffies +
 			  msecs_to_jiffies(GPU_IDLE_TIMEOUT));
 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 		if (!crtc->fb)
 			continue;
 		intel_crtc = to_intel_crtc(crtc);
 		intel_fb = to_intel_framebuffer(crtc->fb);
 		if (intel_fb->obj == obj) {
 			if (!intel_crtc->busy) {
 				/* Non-busy -> busy, upclock */
 				intel_increase_pllclock(crtc);
 				intel_crtc->busy = true;
 			} else {
 				/* Busy -> busy, put off timer */
 				mod_timer(&intel_crtc->idle_timer, jiffies +
 					  msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
 			}
 		}
 	}
 }
 static void intel_crtc_destroy(struct drm_crtc *crtc)
 {
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct drm_device *dev = crtc->dev;
 	struct intel_unpin_work *work;
 	unsigned long flags;
 	spin_lock_irqsave(&dev->event_lock, flags);
 	work = intel_crtc->unpin_work;
 	intel_crtc->unpin_work = NULL;
 	spin_unlock_irqrestore(&dev->event_lock, flags);
 	if (work) {
 		cancel_work_sync(&work->work);
 		kfree(work);
 	}
 	drm_crtc_cleanup(crtc);
 	kfree(intel_crtc);
 }
 static void intel_unpin_work_fn(struct work_struct *__work)
 {
 	struct intel_unpin_work *work =
 		container_of(__work, struct intel_unpin_work, work);
 	mutex_lock(&work->dev->struct_mutex);
 	i915_gem_object_unpin(work->old_fb_obj);
 	drm_gem_object_unreference(&work->pending_flip_obj->base);
 	drm_gem_object_unreference(&work->old_fb_obj->base);
 	intel_update_fbc(work->dev);
 	mutex_unlock(&work->dev->struct_mutex);
 	kfree(work);
 }
 static void do_intel_finish_page_flip(struct drm_device *dev,
 				      struct drm_crtc *crtc)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_unpin_work *work;
 	struct drm_i915_gem_object *obj;
 	struct drm_pending_vblank_event *e;
 	struct timeval tnow, tvbl;
 	unsigned long flags;
 	/* Ignore early vblank irqs */
 	if (intel_crtc == NULL)
 		return;
 	do_gettimeofday(&tnow);
 	spin_lock_irqsave(&dev->event_lock, flags);
 	work = intel_crtc->unpin_work;
 	if (work == NULL || !work->pending) {
 		spin_unlock_irqrestore(&dev->event_lock, flags);
 		return;
 	}
 	intel_crtc->unpin_work = NULL;
 	if (work->event) {
 		e = work->event;
 		e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
 		/* Called before vblank count and timestamps have
 		 * been updated for the vblank interval of flip
 		 * completion? Need to increment vblank count and
 		 * add one videorefresh duration to returned timestamp
 		 * to account for this. We assume this happened if we
 		 * get called over 0.9 frame durations after the last
 		 * timestamped vblank.
 		 *
 		 * This calculation can not be used with vrefresh rates
 		 * below 5Hz (10Hz to be on the safe side) without
 		 * promoting to 64 integers.
 		 */
 		if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
 		    9 * crtc->framedur_ns) {
 			e->event.sequence++;
 			tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
 					     crtc->framedur_ns);
 		}
 		e->event.tv_sec = tvbl.tv_sec;
 		e->event.tv_usec = tvbl.tv_usec;
 		list_add_tail(&e->base.link,
 			      &e->base.file_priv->event_list);
 		wake_up_interruptible(&e->base.file_priv->event_wait);
 	}
 	drm_vblank_put(dev, intel_crtc->pipe);
 	spin_unlock_irqrestore(&dev->event_lock, flags);
 	obj = work->old_fb_obj;
 	atomic_clear_mask(1 << intel_crtc->plane,
 			  &obj->pending_flip.counter);
 	if (atomic_read(&obj->pending_flip) == 0)
 		wake_up(&dev_priv->pending_flip_queue);
 	schedule_work(&work->work);
 	trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
 }
 void intel_finish_page_flip(struct drm_device *dev, int pipe)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 	do_intel_finish_page_flip(dev, crtc);
 }
 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
 	do_intel_finish_page_flip(dev, crtc);
 }
 void intel_prepare_page_flip(struct drm_device *dev, int plane)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc =
 		to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
 	unsigned long flags;
 	spin_lock_irqsave(&dev->event_lock, flags);
 	if (intel_crtc->unpin_work) {
 		if ((++intel_crtc->unpin_work->pending) > 1)
 			DRM_ERROR("Prepared flip multiple times\n");
 	} else {
 		DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
 	}
 	spin_unlock_irqrestore(&dev->event_lock, flags);
 }
 static int intel_gen2_queue_flip(struct drm_device *dev,
 				 struct drm_crtc *crtc,
 				 struct drm_framebuffer *fb,
 				 struct drm_i915_gem_object *obj)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	unsigned long offset;
 	u32 flip_mask;
 	int ret;
 	ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
 	if (ret)
 		goto out;
 	/* Offset into the new buffer for cases of shared fbs between CRTCs */
 	offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
 	ret = BEGIN_LP_RING(6);
 	if (ret)
 		goto out;
 	/* Can't queue multiple flips, so wait for the previous
 	 * one to finish before executing the next.
 	 */
 	if (intel_crtc->plane)
 		flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
 	else
 		flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
 	OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
 	OUT_RING(MI_NOOP);
 	OUT_RING(MI_DISPLAY_FLIP |
 		 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
 	OUT_RING(fb->pitch);
 	OUT_RING(obj->gtt_offset + offset);
 	OUT_RING(MI_NOOP);
 	ADVANCE_LP_RING();
 out:
 	return ret;
 }
 static int intel_gen3_queue_flip(struct drm_device *dev,
 				 struct drm_crtc *crtc,
 				 struct drm_framebuffer *fb,
 				 struct drm_i915_gem_object *obj)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	unsigned long offset;
 	u32 flip_mask;
 	int ret;
 	ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
 	if (ret)
 		goto out;
 	/* Offset into the new buffer for cases of shared fbs between CRTCs */
 	offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
 	ret = BEGIN_LP_RING(6);
 	if (ret)
 		goto out;
 	if (intel_crtc->plane)
 		flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
 	else
 		flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
 	OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
 	OUT_RING(MI_NOOP);
 	OUT_RING(MI_DISPLAY_FLIP_I915 |
 		 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
 	OUT_RING(fb->pitch);
 	OUT_RING(obj->gtt_offset + offset);
 	OUT_RING(MI_NOOP);
 	ADVANCE_LP_RING();
 out:
 	return ret;
 }
 static int intel_gen4_queue_flip(struct drm_device *dev,
 				 struct drm_crtc *crtc,
 				 struct drm_framebuffer *fb,
 				 struct drm_i915_gem_object *obj)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	uint32_t pf, pipesrc;
 	int ret;
 	ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
 	if (ret)
 		goto out;
 	ret = BEGIN_LP_RING(4);
 	if (ret)
 		goto out;
 	/* i965+ uses the linear or tiled offsets from the
 	 * Display Registers (which do not change across a page-flip)
 	 * so we need only reprogram the base address.
 	 */
 	OUT_RING(MI_DISPLAY_FLIP |
 		 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
 	OUT_RING(fb->pitch);
 	OUT_RING(obj->gtt_offset | obj->tiling_mode);
 	/* XXX Enabling the panel-fitter across page-flip is so far
 	 * untested on non-native modes, so ignore it for now.
 	 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
 	 */
 	pf = 0;
 	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
 	OUT_RING(pf | pipesrc);
 	ADVANCE_LP_RING();
 out:
 	return ret;
 }
 static int intel_gen6_queue_flip(struct drm_device *dev,
 				 struct drm_crtc *crtc,
 				 struct drm_framebuffer *fb,
 				 struct drm_i915_gem_object *obj)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	uint32_t pf, pipesrc;
 	int ret;
 	ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
 	if (ret)
 		goto out;
 	ret = BEGIN_LP_RING(4);
 	if (ret)
 		goto out;
 	OUT_RING(MI_DISPLAY_FLIP |
 		 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
 	OUT_RING(fb->pitch | obj->tiling_mode);
 	OUT_RING(obj->gtt_offset);
 	pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
 	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
 	OUT_RING(pf | pipesrc);
 	ADVANCE_LP_RING();
 out:
 	return ret;
 }
 /*
  * On gen7 we currently use the blit ring because (in early silicon at least)
  * the render ring doesn't give us interrpts for page flip completion, which
  * means clients will hang after the first flip is queued.  Fortunately the
  * blit ring generates interrupts properly, so use it instead.
  */
 static int intel_gen7_queue_flip(struct drm_device *dev,
 				 struct drm_crtc *crtc,
 				 struct drm_framebuffer *fb,
 				 struct drm_i915_gem_object *obj)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
 	int ret;
 	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
 	if (ret)
 		goto out;
 	ret = intel_ring_begin(ring, 4);
 	if (ret)
 		goto out;
 	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
 	intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
 	intel_ring_emit(ring, (obj->gtt_offset));
 	intel_ring_emit(ring, (MI_NOOP));
 	intel_ring_advance(ring);
 out:
 	return ret;
 }
 static int intel_default_queue_flip(struct drm_device *dev,
 				    struct drm_crtc *crtc,
 				    struct drm_framebuffer *fb,
 				    struct drm_i915_gem_object *obj)
 {
 	return -ENODEV;
 }
 static int intel_crtc_page_flip(struct drm_crtc *crtc,
 				struct drm_framebuffer *fb,
 				struct drm_pending_vblank_event *event)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_framebuffer *intel_fb;
 	struct drm_i915_gem_object *obj;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_unpin_work *work;
 	unsigned long flags;
 	int ret;
 	work = kzalloc(sizeof *work, GFP_KERNEL);
 	if (work == NULL)
 		return -ENOMEM;
 	work->event = event;
 	work->dev = crtc->dev;
 	intel_fb = to_intel_framebuffer(crtc->fb);
 	work->old_fb_obj = intel_fb->obj;
 	INIT_WORK(&work->work, intel_unpin_work_fn);
+	ret = drm_vblank_get(dev, intel_crtc->pipe);
+	if (ret)
+		goto free_work;
 	/* We borrow the event spin lock for protecting unpin_work */
 	spin_lock_irqsave(&dev->event_lock, flags);
 	if (intel_crtc->unpin_work) {
 		spin_unlock_irqrestore(&dev->event_lock, flags);
 		kfree(work);
+		drm_vblank_put(dev, intel_crtc->pipe);
 		DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 		return -EBUSY;
 	}
 	intel_crtc->unpin_work = work;
 	spin_unlock_irqrestore(&dev->event_lock, flags);
 	intel_fb = to_intel_framebuffer(fb);
 	obj = intel_fb->obj;
 	mutex_lock(&dev->struct_mutex);
 	/* Reference the objects for the scheduled work. */
 	drm_gem_object_reference(&work->old_fb_obj->base);
 	drm_gem_object_reference(&obj->base);
 	crtc->fb = fb;
-	ret = drm_vblank_get(dev, intel_crtc->pipe);
-	if (ret)
-		goto cleanup_objs;
 	work->pending_flip_obj = obj;
 	work->enable_stall_check = true;
 	/* Block clients from rendering to the new back buffer until
 	 * the flip occurs and the object is no longer visible.
 	 */
 	atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
 	ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
 	if (ret)
 		goto cleanup_pending;
 	intel_disable_fbc(dev);
 	mutex_unlock(&dev->struct_mutex);
 	trace_i915_flip_request(intel_crtc->plane, obj);
 	return 0;
 cleanup_pending:
 	atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
-cleanup_objs:
 	drm_gem_object_unreference(&work->old_fb_obj->base);
 	drm_gem_object_unreference(&obj->base);
 	mutex_unlock(&dev->struct_mutex);
 	spin_lock_irqsave(&dev->event_lock, flags);
 	intel_crtc->unpin_work = NULL;
 	spin_unlock_irqrestore(&dev->event_lock, flags);
+	drm_vblank_put(dev, intel_crtc->pipe);
+free_work:
 	kfree(work);
 	return ret;
 }
 static void intel_sanitize_modesetting(struct drm_device *dev,
 				       int pipe, int plane)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 reg, val;
 	if (HAS_PCH_SPLIT(dev))
 		return;
 	/* Who knows what state these registers were left in by the BIOS or
 	 * grub?
 	 *
 	 * If we leave the registers in a conflicting state (e.g. with the
 	 * display plane reading from the other pipe than the one we intend
 	 * to use) then when we attempt to teardown the active mode, we will
 	 * not disable the pipes and planes in the correct order -- leaving
 	 * a plane reading from a disabled pipe and possibly leading to
 	 * undefined behaviour.
 	 */
 	reg = DSPCNTR(plane);
 	val = I915_READ(reg);
 	if ((val & DISPLAY_PLANE_ENABLE) == 0)
 		return;
 	if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
 		return;
 	/* This display plane is active and attached to the other CPU pipe. */
 	pipe = !pipe;
 	/* Disable the plane and wait for it to stop reading from the pipe. */
 	intel_disable_plane(dev_priv, plane, pipe);
 	intel_disable_pipe(dev_priv, pipe);
 }
 static void intel_crtc_reset(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	/* Reset flags back to the 'unknown' status so that they
 	 * will be correctly set on the initial modeset.
 	 */
 	intel_crtc->dpms_mode = -1;
 	/* We need to fix up any BIOS configuration that conflicts with
 	 * our expectations.
 	 */
 	intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
 }
 static struct drm_crtc_helper_funcs intel_helper_funcs = {
 	.dpms = intel_crtc_dpms,
 	.mode_fixup = intel_crtc_mode_fixup,
 	.mode_set = intel_crtc_mode_set,
 	.mode_set_base = intel_pipe_set_base,
 	.mode_set_base_atomic = intel_pipe_set_base_atomic,
 	.load_lut = intel_crtc_load_lut,
 	.disable = intel_crtc_disable,
 };
 static const struct drm_crtc_funcs intel_crtc_funcs = {
 	.reset = intel_crtc_reset,
 	.cursor_set = intel_crtc_cursor_set,
 	.cursor_move = intel_crtc_cursor_move,
 	.gamma_set = intel_crtc_gamma_set,
 	.set_config = drm_crtc_helper_set_config,
 	.destroy = intel_crtc_destroy,
 	.page_flip = intel_crtc_page_flip,
 };
 static void intel_crtc_init(struct drm_device *dev, int pipe)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc;
 	int i;
 	intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 	if (intel_crtc == NULL)
 		return;
 	drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
 	drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
 	for (i = 0; i < 256; i++) {
 		intel_crtc->lut_r[i] = i;
 		intel_crtc->lut_g[i] = i;
 		intel_crtc->lut_b[i] = i;
 	}
 	/* Swap pipes & planes for FBC on pre-965 */
 	intel_crtc->pipe = pipe;
 	intel_crtc->plane = pipe;
 	if (IS_MOBILE(dev) && IS_GEN3(dev)) {
 		DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
 		intel_crtc->plane = !pipe;
 	}
 	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
 	       dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
 	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
 	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
 	intel_crtc_reset(&intel_crtc->base);
 	intel_crtc->active = true; /* force the pipe off on setup_init_config */
 	intel_crtc->bpp = 24; /* default for pre-Ironlake */
 	if (HAS_PCH_SPLIT(dev)) {
 		if (pipe == 2 && IS_IVYBRIDGE(dev))
 			intel_crtc->no_pll = true;
 		intel_helper_funcs.prepare = ironlake_crtc_prepare;
 		intel_helper_funcs.commit = ironlake_crtc_commit;
 	} else {
 		intel_helper_funcs.prepare = i9xx_crtc_prepare;
 		intel_helper_funcs.commit = i9xx_crtc_commit;
 	}
 	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
 	intel_crtc->busy = false;
 	setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
 		    (unsigned long)intel_crtc);
 }
 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 				struct drm_file *file)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
 	struct drm_mode_object *drmmode_obj;
 	struct intel_crtc *crtc;
 	if (!dev_priv) {
 		DRM_ERROR("called with no initialization\n");
 		return -EINVAL;
 	}
 	drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
 			DRM_MODE_OBJECT_CRTC);
 	if (!drmmode_obj) {
 		DRM_ERROR("no such CRTC id\n");
 		return -EINVAL;
 	}
 	crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
 	pipe_from_crtc_id->pipe = crtc->pipe;
 	return 0;
 }
 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
 {
 	struct intel_encoder *encoder;
 	int index_mask = 0;
 	int entry = 0;
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
 		if (type_mask & encoder->clone_mask)
 			index_mask |= (1 << entry);
 		entry++;
 	}
 	return index_mask;
 }
 static bool has_edp_a(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (!IS_MOBILE(dev))
 		return false;
 	if ((I915_READ(DP_A) & DP_DETECTED) == 0)
 		return false;
 	if (IS_GEN5(dev) &&
 	    (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
 		return false;
 	return true;
 }
 static void intel_setup_outputs(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_encoder *encoder;
 	bool dpd_is_edp = false;
 	bool has_lvds = false;
 	if (IS_MOBILE(dev) && !IS_I830(dev))
 		has_lvds = intel_lvds_init(dev);
 	if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
 		/* disable the panel fitter on everything but LVDS */
 		I915_WRITE(PFIT_CONTROL, 0);
 	}
 	if (HAS_PCH_SPLIT(dev)) {
 		dpd_is_edp = intel_dpd_is_edp(dev);
 		if (has_edp_a(dev))
 			intel_dp_init(dev, DP_A);
 		if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
 			intel_dp_init(dev, PCH_DP_D);
 	}
 	intel_crt_init(dev);
 	if (HAS_PCH_SPLIT(dev)) {
 		int found;
 		if (I915_READ(HDMIB) & PORT_DETECTED) {
 			/* PCH SDVOB multiplex with HDMIB */
 			found = intel_sdvo_init(dev, PCH_SDVOB);
 			if (!found)
 				intel_hdmi_init(dev, HDMIB);
 			if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
 				intel_dp_init(dev, PCH_DP_B);
 		}
 		if (I915_READ(HDMIC) & PORT_DETECTED)
 			intel_hdmi_init(dev, HDMIC);
 		if (I915_READ(HDMID) & PORT_DETECTED)
 			intel_hdmi_init(dev, HDMID);
 		if (I915_READ(PCH_DP_C) & DP_DETECTED)
 			intel_dp_init(dev, PCH_DP_C);
 		if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
 			intel_dp_init(dev, PCH_DP_D);
 	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
 		bool found = false;
 		if (I915_READ(SDVOB) & SDVO_DETECTED) {
 			DRM_DEBUG_KMS("probing SDVOB\n");
 			found = intel_sdvo_init(dev, SDVOB);
 			if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
 				DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
 				intel_hdmi_init(dev, SDVOB);
 			}
 			if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
 				DRM_DEBUG_KMS("probing DP_B\n");
 				intel_dp_init(dev, DP_B);
 			}
 		}
 		/* Before G4X SDVOC doesn't have its own detect register */
 		if (I915_READ(SDVOB) & SDVO_DETECTED) {
 			DRM_DEBUG_KMS("probing SDVOC\n");
 			found = intel_sdvo_init(dev, SDVOC);
 		}
 		if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
 			if (SUPPORTS_INTEGRATED_HDMI(dev)) {
 				DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
 				intel_hdmi_init(dev, SDVOC);
 			}
 			if (SUPPORTS_INTEGRATED_DP(dev)) {
 				DRM_DEBUG_KMS("probing DP_C\n");
 				intel_dp_init(dev, DP_C);
 			}
 		}
 		if (SUPPORTS_INTEGRATED_DP(dev) &&
 		    (I915_READ(DP_D) & DP_DETECTED)) {
 			DRM_DEBUG_KMS("probing DP_D\n");
 			intel_dp_init(dev, DP_D);
 		}
 	} else if (IS_GEN2(dev))
 		intel_dvo_init(dev);
 	if (SUPPORTS_TV(dev))
 		intel_tv_init(dev);
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
 		encoder->base.possible_crtcs = encoder->crtc_mask;
 		encoder->base.possible_clones =
 			intel_encoder_clones(dev, encoder->clone_mask);
 	}
 	/* disable all the possible outputs/crtcs before entering KMS mode */
 	drm_helper_disable_unused_functions(dev);
 	if (HAS_PCH_SPLIT(dev))
 		ironlake_init_pch_refclk(dev);
 }
 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
 {
 	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 	drm_framebuffer_cleanup(fb);
 	drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
 	kfree(intel_fb);
 }
 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
 						struct drm_file *file,
 						unsigned int *handle)
 {
 	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 	struct drm_i915_gem_object *obj = intel_fb->obj;
 	return drm_gem_handle_create(file, &obj->base, handle);
 }
 static const struct drm_framebuffer_funcs intel_fb_funcs = {
 	.destroy = intel_user_framebuffer_destroy,
 	.create_handle = intel_user_framebuffer_create_handle,
 };
 int intel_framebuffer_init(struct drm_device *dev,
 			   struct intel_framebuffer *intel_fb,
 			   struct drm_mode_fb_cmd *mode_cmd,
 			   struct drm_i915_gem_object *obj)
 {
 	int ret;
 	if (obj->tiling_mode == I915_TILING_Y)
 		return -EINVAL;
 	if (mode_cmd->pitch & 63)
 		return -EINVAL;
 	switch (mode_cmd->bpp) {
 	case 8:
 	case 16:
 		/* Only pre-ILK can handle 5:5:5 */
 		if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
 			return -EINVAL;
 		break;
 	case 24:
 	case 32:
 		break;
 	default:
 		return -EINVAL;
 	}
 	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
 	if (ret) {
 		DRM_ERROR("framebuffer init failed %d\n", ret);
 		return ret;
 	}
 	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
 	intel_fb->obj = obj;
 	return 0;
 }
 static struct drm_framebuffer *
 intel_user_framebuffer_create(struct drm_device *dev,
 			      struct drm_file *filp,
 			      struct drm_mode_fb_cmd *mode_cmd)
 {
 	struct drm_i915_gem_object *obj;
 	obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
 	if (&obj->base == NULL)
 		return ERR_PTR(-ENOENT);
 	return intel_framebuffer_create(dev, mode_cmd, obj);
 }
 static const struct drm_mode_config_funcs intel_mode_funcs = {
 	.fb_create = intel_user_framebuffer_create,
 	.output_poll_changed = intel_fb_output_poll_changed,
 };
 static struct drm_i915_gem_object *
 intel_alloc_context_page(struct drm_device *dev)
 {
 	struct drm_i915_gem_object *ctx;
 	int ret;
 	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 	ctx = i915_gem_alloc_object(dev, 4096);
 	if (!ctx) {
 		DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
 		return NULL;
 	}
 	ret = i915_gem_object_pin(ctx, 4096, true);
 	if (ret) {
 		DRM_ERROR("failed to pin power context: %d\n", ret);
 		goto err_unref;
 	}
 	ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
 	if (ret) {
 		DRM_ERROR("failed to set-domain on power context: %d\n", ret);
 		goto err_unpin;
 	}
 	return ctx;
 err_unpin:
 	i915_gem_object_unpin(ctx);
 err_unref:
 	drm_gem_object_unreference(&ctx->base);
 	mutex_unlock(&dev->struct_mutex);
 	return NULL;
 }
 bool ironlake_set_drps(struct drm_device *dev, u8 val)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u16 rgvswctl;
 	rgvswctl = I915_READ16(MEMSWCTL);
 	if (rgvswctl & MEMCTL_CMD_STS) {
 		DRM_DEBUG("gpu busy, RCS change rejected\n");
 		return false; /* still busy with another command */
 	}
 	rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
 		(val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
 	I915_WRITE16(MEMSWCTL, rgvswctl);
 	POSTING_READ16(MEMSWCTL);
 	rgvswctl |= MEMCTL_CMD_STS;
 	I915_WRITE16(MEMSWCTL, rgvswctl);
 	return true;
 }
 void ironlake_enable_drps(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 rgvmodectl = I915_READ(MEMMODECTL);
 	u8 fmax, fmin, fstart, vstart;
 	/* Enable temp reporting */
 	I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
 	I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
 	/* 100ms RC evaluation intervals */
 	I915_WRITE(RCUPEI, 100000);
 	I915_WRITE(RCDNEI, 100000);
 	/* Set max/min thresholds to 90ms and 80ms respectively */
 	I915_WRITE(RCBMAXAVG, 90000);
 	I915_WRITE(RCBMINAVG, 80000);
 	I915_WRITE(MEMIHYST, 1);
 	/* Set up min, max, and cur for interrupt handling */
 	fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
 	fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
 	fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
 		MEMMODE_FSTART_SHIFT;
 	vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
 		PXVFREQ_PX_SHIFT;
 	dev_priv->fmax = fmax; /* IPS callback will increase this */
 	dev_priv->fstart = fstart;
 	dev_priv->max_delay = fstart;
 	dev_priv->min_delay = fmin;
 	dev_priv->cur_delay = fstart;
 	DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
 			 fmax, fmin, fstart);
 	I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
 	/*
 	 * Interrupts will be enabled in ironlake_irq_postinstall
 	 */
 	I915_WRITE(VIDSTART, vstart);
 	POSTING_READ(VIDSTART);
 	rgvmodectl |= MEMMODE_SWMODE_EN;
 	I915_WRITE(MEMMODECTL, rgvmodectl);
 	if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
 		DRM_ERROR("stuck trying to change perf mode\n");
 	msleep(1);
 	ironlake_set_drps(dev, fstart);
 	dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
 		I915_READ(0x112e0);
 	dev_priv->last_time1 = jiffies_to_msecs(jiffies);
 	dev_priv->last_count2 = I915_READ(0x112f4);
 	getrawmonotonic(&dev_priv->last_time2);
 }
 void ironlake_disable_drps(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u16 rgvswctl = I915_READ16(MEMSWCTL);
 	/* Ack interrupts, disable EFC interrupt */
 	I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
 	I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
 	I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
 	I915_WRITE(DEIIR, DE_PCU_EVENT);
 	I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
 	/* Go back to the starting frequency */
 	ironlake_set_drps(dev, dev_priv->fstart);
 	msleep(1);
 	rgvswctl |= MEMCTL_CMD_STS;
 	I915_WRITE(MEMSWCTL, rgvswctl);
 	msleep(1);
 }
 void gen6_set_rps(struct drm_device *dev, u8 val)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 swreq;
 	swreq = (val & 0x3ff) << 25;
 	I915_WRITE(GEN6_RPNSWREQ, swreq);
 }
 void gen6_disable_rps(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
 	I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
 	I915_WRITE(GEN6_PMIER, 0);
 	/* Complete PM interrupt masking here doesn't race with the rps work
 	 * item again unmasking PM interrupts because that is using a different
 	 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
 	 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
 	spin_lock_irq(&dev_priv->rps_lock);
 	dev_priv->pm_iir = 0;
 	spin_unlock_irq(&dev_priv->rps_lock);
 	I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
 }
 static unsigned long intel_pxfreq(u32 vidfreq)
 {
 	unsigned long freq;
 	int div = (vidfreq & 0x3f0000) >> 16;
 	int post = (vidfreq & 0x3000) >> 12;
 	int pre = (vidfreq & 0x7);
 	if (!pre)
 		return 0;
 	freq = ((div * 133333) / ((1<<post) * pre));
 	return freq;
 }
 void intel_init_emon(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 lcfuse;
 	u8 pxw[16];
 	int i;
 	/* Disable to program */
 	I915_WRITE(ECR, 0);
 	POSTING_READ(ECR);
 	/* Program energy weights for various events */
 	I915_WRITE(SDEW, 0x15040d00);
 	I915_WRITE(CSIEW0, 0x007f0000);
 	I915_WRITE(CSIEW1, 0x1e220004);
 	I915_WRITE(CSIEW2, 0x04000004);
 	for (i = 0; i < 5; i++)
 		I915_WRITE(PEW + (i * 4), 0);
 	for (i = 0; i < 3; i++)
 		I915_WRITE(DEW + (i * 4), 0);
 	/* Program P-state weights to account for frequency power adjustment */
 	for (i = 0; i < 16; i++) {
 		u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
 		unsigned long freq = intel_pxfreq(pxvidfreq);
 		unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
 			PXVFREQ_PX_SHIFT;
 		unsigned long val;
 		val = vid * vid;
 		val *= (freq / 1000);
 		val *= 255;
 		val /= (127*127*900);
 		if (val > 0xff)
 			DRM_ERROR("bad pxval: %ld\n", val);
 		pxw[i] = val;
 	}
 	/* Render standby states get 0 weight */
 	pxw[14] = 0;
 	pxw[15] = 0;
 	for (i = 0; i < 4; i++) {
 		u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
 			(pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
 		I915_WRITE(PXW + (i * 4), val);
 	}
 	/* Adjust magic regs to magic values (more experimental results) */
 	I915_WRITE(OGW0, 0);
 	I915_WRITE(OGW1, 0);
 	I915_WRITE(EG0, 0x00007f00);
 	I915_WRITE(EG1, 0x0000000e);
 	I915_WRITE(EG2, 0x000e0000);
 	I915_WRITE(EG3, 0x68000300);
 	I915_WRITE(EG4, 0x42000000);
 	I915_WRITE(EG5, 0x00140031);
 	I915_WRITE(EG6, 0);
 	I915_WRITE(EG7, 0);
 	for (i = 0; i < 8; i++)
 		I915_WRITE(PXWL + (i * 4), 0);
 	/* Enable PMON + select events */
 	I915_WRITE(ECR, 0x80000019);
 	lcfuse = I915_READ(LCFUSE02);
 	dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
 }
 static bool intel_enable_rc6(struct drm_device *dev)
 {
 	/*
 	 * Respect the kernel parameter if it is set
 	 */
 	if (i915_enable_rc6 >= 0)
 		return i915_enable_rc6;
 	/*
 	 * Disable RC6 on Ironlake
 	 */
 	if (INTEL_INFO(dev)->gen == 5)
 		return 0;
 	/*
 	 * Enable rc6 on Sandybridge if DMA remapping is disabled
 	 */
 	if (INTEL_INFO(dev)->gen == 6) {
 		DRM_DEBUG_DRIVER("Sandybridge: intel_iommu_enabled %s -- RC6 %sabled\n",
 				 intel_iommu_enabled ? "true" : "false",
 				 !intel_iommu_enabled ? "en" : "dis");
 		return !intel_iommu_enabled;
 	}
 	DRM_DEBUG_DRIVER("RC6 enabled\n");
 	return 1;
 }
 void gen6_enable_rps(struct drm_i915_private *dev_priv)
 {
 	u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
 	u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
 	u32 pcu_mbox, rc6_mask = 0;
 	int cur_freq, min_freq, max_freq;
 	int i;
 	/* Here begins a magic sequence of register writes to enable
 	 * auto-downclocking.
 	 *
 	 * Perhaps there might be some value in exposing these to
 	 * userspace...
 	 */
 	I915_WRITE(GEN6_RC_STATE, 0);
 	mutex_lock(&dev_priv->dev->struct_mutex);
 	gen6_gt_force_wake_get(dev_priv);
 	/* disable the counters and set deterministic thresholds */
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 	I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
 	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
 	I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
 	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
 	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
 	for (i = 0; i < I915_NUM_RINGS; i++)
 		I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
 	I915_WRITE(GEN6_RC_SLEEP, 0);
 	I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
 	I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
 	I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
 	I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
 	if (intel_enable_rc6(dev_priv->dev))
 		rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
 			GEN6_RC_CTL_RC6_ENABLE;
 	I915_WRITE(GEN6_RC_CONTROL,
 		   rc6_mask |
 		   GEN6_RC_CTL_EI_MODE(1) |
 		   GEN6_RC_CTL_HW_ENABLE);
 	I915_WRITE(GEN6_RPNSWREQ,
 		   GEN6_FREQUENCY(10) |
 		   GEN6_OFFSET(0) |
 		   GEN6_AGGRESSIVE_TURBO);
 	I915_WRITE(GEN6_RC_VIDEO_FREQ,
 		   GEN6_FREQUENCY(12));
 	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
 	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
 		   18 << 24 |
 		   6 << 16);
 	I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
 	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
 	I915_WRITE(GEN6_RP_UP_EI, 100000);
 	I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
 	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
 	I915_WRITE(GEN6_RP_CONTROL,
 		   GEN6_RP_MEDIA_TURBO |
 		   GEN6_RP_USE_NORMAL_FREQ |
 		   GEN6_RP_MEDIA_IS_GFX |
 		   GEN6_RP_ENABLE |
 		   GEN6_RP_UP_BUSY_AVG |
 		   GEN6_RP_DOWN_IDLE_CONT);
 	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
 		     500))
 		DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
 	I915_WRITE(GEN6_PCODE_DATA, 0);
 	I915_WRITE(GEN6_PCODE_MAILBOX,
 		   GEN6_PCODE_READY |
 		   GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
 	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
 		     500))
 		DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
 	min_freq = (rp_state_cap & 0xff0000) >> 16;
 	max_freq = rp_state_cap & 0xff;
 	cur_freq = (gt_perf_status & 0xff00) >> 8;
 	/* Check for overclock support */
 	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
 		     500))
 		DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
 	I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
 	pcu_mbox = I915_READ(GEN6_PCODE_DATA);
 	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
 		     500))
 		DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
 	if (pcu_mbox & (1<<31)) { /* OC supported */
 		max_freq = pcu_mbox & 0xff;
 		DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
 	}
 	/* In units of 100MHz */
 	dev_priv->max_delay = max_freq;
 	dev_priv->min_delay = min_freq;
 	dev_priv->cur_delay = cur_freq;
 	/* requires MSI enabled */
 	I915_WRITE(GEN6_PMIER,
 		   GEN6_PM_MBOX_EVENT |
 		   GEN6_PM_THERMAL_EVENT |
 		   GEN6_PM_RP_DOWN_TIMEOUT |
 		   GEN6_PM_RP_UP_THRESHOLD |
 		   GEN6_PM_RP_DOWN_THRESHOLD |
 		   GEN6_PM_RP_UP_EI_EXPIRED |
 		   GEN6_PM_RP_DOWN_EI_EXPIRED);
 	spin_lock_irq(&dev_priv->rps_lock);
 	WARN_ON(dev_priv->pm_iir != 0);
 	I915_WRITE(GEN6_PMIMR, 0);
 	spin_unlock_irq(&dev_priv->rps_lock);
 	/* enable all PM interrupts */
 	I915_WRITE(GEN6_PMINTRMSK, 0);
 	gen6_gt_force_wake_put(dev_priv);
 	mutex_unlock(&dev_priv->dev->struct_mutex);
 }
 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
 {
 	int min_freq = 15;
 	int gpu_freq, ia_freq, max_ia_freq;
 	int scaling_factor = 180;
 	max_ia_freq = cpufreq_quick_get_max(0);
 	/*
 	 * Default to measured freq if none found, PCU will ensure we don't go
 	 * over
 	 */
 	if (!max_ia_freq)
 		max_ia_freq = tsc_khz;
 	/* Convert from kHz to MHz */
 	max_ia_freq /= 1000;
 	mutex_lock(&dev_priv->dev->struct_mutex);
 	/*
 	 * For each potential GPU frequency, load a ring frequency we'd like
 	 * to use for memory access.  We do this by specifying the IA frequency
 	 * the PCU should use as a reference to determine the ring frequency.
 	 */
 	for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
 	     gpu_freq--) {
 		int diff = dev_priv->max_delay - gpu_freq;
 		/*
 		 * For GPU frequencies less than 750MHz, just use the lowest
 		 * ring freq.
 		 */
 		if (gpu_freq < min_freq)
 			ia_freq = 800;
 		else
 			ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
 		ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
 		I915_WRITE(GEN6_PCODE_DATA,
 			   (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
 			   gpu_freq);
 		I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
 			   GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
 		if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
 			      GEN6_PCODE_READY) == 0, 10)) {
 			DRM_ERROR("pcode write of freq table timed out\n");
 			continue;
 		}
 	}
 	mutex_unlock(&dev_priv->dev->struct_mutex);
 }
 static void ironlake_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
 	/* Required for FBC */
 	dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
 		DPFCRUNIT_CLOCK_GATE_DISABLE |
 		DPFDUNIT_CLOCK_GATE_DISABLE;
 	/* Required for CxSR */
 	dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
 	I915_WRITE(PCH_3DCGDIS0,
 		   MARIUNIT_CLOCK_GATE_DISABLE |
 		   SVSMUNIT_CLOCK_GATE_DISABLE);
 	I915_WRITE(PCH_3DCGDIS1,
 		   VFMUNIT_CLOCK_GATE_DISABLE);
 	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
 	/*
 	 * According to the spec the following bits should be set in
 	 * order to enable memory self-refresh
 	 * The bit 22/21 of 0x42004
 	 * The bit 5 of 0x42020
 	 * The bit 15 of 0x45000
 	 */
 	I915_WRITE(ILK_DISPLAY_CHICKEN2,
 		   (I915_READ(ILK_DISPLAY_CHICKEN2) |
 		    ILK_DPARB_GATE | ILK_VSDPFD_FULL));
 	I915_WRITE(ILK_DSPCLK_GATE,
 		   (I915_READ(ILK_DSPCLK_GATE) |
 		    ILK_DPARB_CLK_GATE));
 	I915_WRITE(DISP_ARB_CTL,
 		   (I915_READ(DISP_ARB_CTL) |
 		    DISP_FBC_WM_DIS));
 	I915_WRITE(WM3_LP_ILK, 0);
 	I915_WRITE(WM2_LP_ILK, 0);
 	I915_WRITE(WM1_LP_ILK, 0);
 	/*
 	 * Based on the document from hardware guys the following bits
 	 * should be set unconditionally in order to enable FBC.
 	 * The bit 22 of 0x42000
 	 * The bit 22 of 0x42004
 	 * The bit 7,8,9 of 0x42020.
 	 */
 	if (IS_IRONLAKE_M(dev)) {
 		I915_WRITE(ILK_DISPLAY_CHICKEN1,
 			   I915_READ(ILK_DISPLAY_CHICKEN1) |
 			   ILK_FBCQ_DIS);
 		I915_WRITE(ILK_DISPLAY_CHICKEN2,
 			   I915_READ(ILK_DISPLAY_CHICKEN2) |
 			   ILK_DPARB_GATE);
 		I915_WRITE(ILK_DSPCLK_GATE,
 			   I915_READ(ILK_DSPCLK_GATE) |
 			   ILK_DPFC_DIS1 |
 			   ILK_DPFC_DIS2 |
 			   ILK_CLK_FBC);
 	}
 	I915_WRITE(ILK_DISPLAY_CHICKEN2,
 		   I915_READ(ILK_DISPLAY_CHICKEN2) |
 		   ILK_ELPIN_409_SELECT);
 	I915_WRITE(_3D_CHICKEN2,
 		   _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
 		   _3D_CHICKEN2_WM_READ_PIPELINED);
 }
 static void gen6_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int pipe;
 	uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
 	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
 	I915_WRITE(ILK_DISPLAY_CHICKEN2,
 		   I915_READ(ILK_DISPLAY_CHICKEN2) |
 		   ILK_ELPIN_409_SELECT);
 	I915_WRITE(WM3_LP_ILK, 0);
 	I915_WRITE(WM2_LP_ILK, 0);
 	I915_WRITE(WM1_LP_ILK, 0);
 	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
 	 * gating disable must be set.  Failure to set it results in
 	 * flickering pixels due to Z write ordering failures after
 	 * some amount of runtime in the Mesa "fire" demo, and Unigine
 	 * Sanctuary and Tropics, and apparently anything else with
 	 * alpha test or pixel discard.
 	 *
 	 * According to the spec, bit 11 (RCCUNIT) must also be set,
 	 * but we didn't debug actual testcases to find it out.
 	 */
 	I915_WRITE(GEN6_UCGCTL2,
 		   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
 		   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
 	/*
 	 * According to the spec the following bits should be
 	 * set in order to enable memory self-refresh and fbc:
 	 * The bit21 and bit22 of 0x42000
 	 * The bit21 and bit22 of 0x42004
 	 * The bit5 and bit7 of 0x42020
 	 * The bit14 of 0x70180
 	 * The bit14 of 0x71180
 	 */
 	I915_WRITE(ILK_DISPLAY_CHICKEN1,
 		   I915_READ(ILK_DISPLAY_CHICKEN1) |
 		   ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
 	I915_WRITE(ILK_DISPLAY_CHICKEN2,
 		   I915_READ(ILK_DISPLAY_CHICKEN2) |
 		   ILK_DPARB_GATE | ILK_VSDPFD_FULL);
 	I915_WRITE(ILK_DSPCLK_GATE,
 		   I915_READ(ILK_DSPCLK_GATE) |
 		   ILK_DPARB_CLK_GATE  |
 		   ILK_DPFD_CLK_GATE);
 	for_each_pipe(pipe) {
 		I915_WRITE(DSPCNTR(pipe),
 			   I915_READ(DSPCNTR(pipe)) |
 			   DISPPLANE_TRICKLE_FEED_DISABLE);
 		intel_flush_display_plane(dev_priv, pipe);
 	}
 }
 static void ivybridge_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int pipe;
 	uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
 	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
 	I915_WRITE(WM3_LP_ILK, 0);
 	I915_WRITE(WM2_LP_ILK, 0);
 	I915_WRITE(WM1_LP_ILK, 0);
 	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
 	for_each_pipe(pipe) {
 		I915_WRITE(DSPCNTR(pipe),
 			   I915_READ(DSPCNTR(pipe)) |
 			   DISPPLANE_TRICKLE_FEED_DISABLE);
 		intel_flush_display_plane(dev_priv, pipe);
 	}
 }
 static void g4x_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t dspclk_gate;
 	I915_WRITE(RENCLK_GATE_D1, 0);
 	I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
 		   GS_UNIT_CLOCK_GATE_DISABLE |
 		   CL_UNIT_CLOCK_GATE_DISABLE);
 	I915_WRITE(RAMCLK_GATE_D, 0);
 	dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
 		OVRUNIT_CLOCK_GATE_DISABLE |
 		OVCUNIT_CLOCK_GATE_DISABLE;
 	if (IS_GM45(dev))
 		dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
 	I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
 }
 static void crestline_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
 	I915_WRITE(RENCLK_GATE_D2, 0);
 	I915_WRITE(DSPCLK_GATE_D, 0);
 	I915_WRITE(RAMCLK_GATE_D, 0);
 	I915_WRITE16(DEUC, 0);
 }
 static void broadwater_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
 		   I965_RCC_CLOCK_GATE_DISABLE |
 		   I965_RCPB_CLOCK_GATE_DISABLE |
 		   I965_ISC_CLOCK_GATE_DISABLE |
 		   I965_FBC_CLOCK_GATE_DISABLE);
 	I915_WRITE(RENCLK_GATE_D2, 0);
 }
 static void gen3_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 dstate = I915_READ(D_STATE);
 	dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
 		DSTATE_DOT_CLOCK_GATING;
 	I915_WRITE(D_STATE, dstate);
 }
 static void i85x_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
 }
 static void i830_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
 }
 static void ibx_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	/*
 	 * On Ibex Peak and Cougar Point, we need to disable clock
 	 * gating for the panel power sequencer or it will fail to
 	 * start up when no ports are active.
 	 */
 	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
 }
 static void cpt_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int pipe;
 	/*
 	 * On Ibex Peak and Cougar Point, we need to disable clock
 	 * gating for the panel power sequencer or it will fail to
 	 * start up when no ports are active.
 	 */
 	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
 	I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
 		   DPLS_EDP_PPS_FIX_DIS);
 	/* Without this, mode sets may fail silently on FDI */
 	for_each_pipe(pipe)
 		I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
 }
 static void ironlake_teardown_rc6(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (dev_priv->renderctx) {
 		i915_gem_object_unpin(dev_priv->renderctx);
 		drm_gem_object_unreference(&dev_priv->renderctx->base);
 		dev_priv->renderctx = NULL;
 	}
 	if (dev_priv->pwrctx) {
 		i915_gem_object_unpin(dev_priv->pwrctx);
 		drm_gem_object_unreference(&dev_priv->pwrctx->base);
 		dev_priv->pwrctx = NULL;
 	}
 }
 static void ironlake_disable_rc6(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (I915_READ(PWRCTXA)) {
 		/* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
 		I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
 		wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
 			 50);
 		I915_WRITE(PWRCTXA, 0);
 		POSTING_READ(PWRCTXA);
 		I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
 		POSTING_READ(RSTDBYCTL);
 	}
 	ironlake_teardown_rc6(dev);
 }
 static int ironlake_setup_rc6(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (dev_priv->renderctx == NULL)
 		dev_priv->renderctx = intel_alloc_context_page(dev);
 	if (!dev_priv->renderctx)
 		return -ENOMEM;
 	if (dev_priv->pwrctx == NULL)
 		dev_priv->pwrctx = intel_alloc_context_page(dev);
 	if (!dev_priv->pwrctx) {
 		ironlake_teardown_rc6(dev);
 		return -ENOMEM;
 	}
 	return 0;
 }
 void ironlake_enable_rc6(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret;
 	/* rc6 disabled by default due to repeated reports of hanging during
 	 * boot and resume.
 	 */
 	if (!intel_enable_rc6(dev))
 		return;
 	mutex_lock(&dev->struct_mutex);
 	ret = ironlake_setup_rc6(dev);
 	if (ret) {
 		mutex_unlock(&dev->struct_mutex);
 		return;
 	}
 	/*
 	 * GPU can automatically power down the render unit if given a page
 	 * to save state.
 	 */
 	ret = BEGIN_LP_RING(6);
 	if (ret) {
 		ironlake_teardown_rc6(dev);
 		mutex_unlock(&dev->struct_mutex);
 		return;
 	}
 	OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
 	OUT_RING(MI_SET_CONTEXT);
 	OUT_RING(dev_priv->renderctx->gtt_offset |
 		 MI_MM_SPACE_GTT |
 		 MI_SAVE_EXT_STATE_EN |
 		 MI_RESTORE_EXT_STATE_EN |
 		 MI_RESTORE_INHIBIT);
 	OUT_RING(MI_SUSPEND_FLUSH);
 	OUT_RING(MI_NOOP);
 	OUT_RING(MI_FLUSH);
 	ADVANCE_LP_RING();
 	/*
 	 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
 	 * does an implicit flush, combined with MI_FLUSH above, it should be
 	 * safe to assume that renderctx is valid
 	 */
 	ret = intel_wait_ring_idle(LP_RING(dev_priv));
 	if (ret) {
 		DRM_ERROR("failed to enable ironlake power power savings\n");
 		ironlake_teardown_rc6(dev);
 		mutex_unlock(&dev->struct_mutex);
 		return;
 	}
 	I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
 	I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
 	mutex_unlock(&dev->struct_mutex);
 }
 void intel_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	dev_priv->display.init_clock_gating(dev);
 	if (dev_priv->display.init_pch_clock_gating)
 		dev_priv->display.init_pch_clock_gating(dev);
 }
 /* Set up chip specific display functions */
 static void intel_init_display(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	/* We always want a DPMS function */
 	if (HAS_PCH_SPLIT(dev)) {
 		dev_priv->display.dpms = ironlake_crtc_dpms;
 		dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
 		dev_priv->display.update_plane = ironlake_update_plane;
 	} else {
 		dev_priv->display.dpms = i9xx_crtc_dpms;
 		dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
 		dev_priv->display.update_plane = i9xx_update_plane;
 	}
 	if (I915_HAS_FBC(dev)) {
 		if (HAS_PCH_SPLIT(dev)) {
 			dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
 			dev_priv->display.enable_fbc = ironlake_enable_fbc;
 			dev_priv->display.disable_fbc = ironlake_disable_fbc;
 		} else if (IS_GM45(dev)) {
 			dev_priv->display.fbc_enabled = g4x_fbc_enabled;
 			dev_priv->display.enable_fbc = g4x_enable_fbc;
 			dev_priv->display.disable_fbc = g4x_disable_fbc;
 		} else if (IS_CRESTLINE(dev)) {
 			dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
 			dev_priv->display.enable_fbc = i8xx_enable_fbc;
 			dev_priv->display.disable_fbc = i8xx_disable_fbc;
 		}
 		/* 855GM needs testing */
 	}
 	/* Returns the core display clock speed */
 	if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
 		dev_priv->display.get_display_clock_speed =
 			i945_get_display_clock_speed;
 	else if (IS_I915G(dev))
 		dev_priv->display.get_display_clock_speed =
 			i915_get_display_clock_speed;
 	else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
 		dev_priv->display.get_display_clock_speed =
 			i9xx_misc_get_display_clock_speed;
 	else if (IS_I915GM(dev))
 		dev_priv->display.get_display_clock_speed =
 			i915gm_get_display_clock_speed;
 	else if (IS_I865G(dev))
 		dev_priv->display.get_display_clock_speed =
 			i865_get_display_clock_speed;
 	else if (IS_I85X(dev))
 		dev_priv->display.get_display_clock_speed =
 			i855_get_display_clock_speed;
 	else /* 852, 830 */
 		dev_priv->display.get_display_clock_speed =
 			i830_get_display_clock_speed;
 	/* For FIFO watermark updates */
 	if (HAS_PCH_SPLIT(dev)) {
 		dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
 		dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
 		/* IVB configs may use multi-threaded forcewake */
 		if (IS_IVYBRIDGE(dev)) {
 			u32	ecobus;
 			mutex_lock(&dev->struct_mutex);
 			__gen6_gt_force_wake_mt_get(dev_priv);
 			ecobus = I915_READ(ECOBUS);
 			__gen6_gt_force_wake_mt_put(dev_priv);
 			mutex_unlock(&dev->struct_mutex);
 			if (ecobus & FORCEWAKE_MT_ENABLE) {
 				DRM_DEBUG_KMS("Using MT version of forcewake\n");
 				dev_priv->display.force_wake_get =
 					__gen6_gt_force_wake_mt_get;
 				dev_priv->display.force_wake_put =
 					__gen6_gt_force_wake_mt_put;
 			}
 		}
 		if (HAS_PCH_IBX(dev))
 			dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
 		else if (HAS_PCH_CPT(dev))
 			dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
 		if (IS_GEN5(dev)) {
 			if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
 				dev_priv->display.update_wm = ironlake_update_wm;
 			else {
 				DRM_DEBUG_KMS("Failed to get proper latency. "
 					      "Disable CxSR\n");
 				dev_priv->display.update_wm = NULL;
 			}
 			dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
 			dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
 			dev_priv->display.write_eld = ironlake_write_eld;
 		} else if (IS_GEN6(dev)) {
 			if (SNB_READ_WM0_LATENCY()) {
 				dev_priv->display.update_wm = sandybridge_update_wm;
 			} else {
 				DRM_DEBUG_KMS("Failed to read display plane latency. "
 					      "Disable CxSR\n");
 				dev_priv->display.update_wm = NULL;
 			}
 			dev_priv->display.fdi_link_train = gen6_fdi_link_train;
 			dev_priv->display.init_clock_gating = gen6_init_clock_gating;
 			dev_priv->display.write_eld = ironlake_write_eld;
 		} else if (IS_IVYBRIDGE(dev)) {
 			/* FIXME: detect B0+ stepping and use auto training */
 			dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
 			if (SNB_READ_WM0_LATENCY()) {
 				dev_priv->display.update_wm = sandybridge_update_wm;
 			} else {
 				DRM_DEBUG_KMS("Failed to read display plane latency. "
 					      "Disable CxSR\n");
 				dev_priv->display.update_wm = NULL;
 			}
 			dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
 			dev_priv->display.write_eld = ironlake_write_eld;
 		} else
 			dev_priv->display.update_wm = NULL;
 	} else if (IS_PINEVIEW(dev)) {
 		if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
 					    dev_priv->is_ddr3,
 					    dev_priv->fsb_freq,
 					    dev_priv->mem_freq)) {
 			DRM_INFO("failed to find known CxSR latency "
 				 "(found ddr%s fsb freq %d, mem freq %d), "
 				 "disabling CxSR\n",
 				 (dev_priv->is_ddr3 == 1) ? "3" : "2",
 				 dev_priv->fsb_freq, dev_priv->mem_freq);
 			/* Disable CxSR and never update its watermark again */
 			pineview_disable_cxsr(dev);
 			dev_priv->display.update_wm = NULL;
 		} else
 			dev_priv->display.update_wm = pineview_update_wm;
 		dev_priv->display.init_clock_gating = gen3_init_clock_gating;
 	} else if (IS_G4X(dev)) {
 		dev_priv->display.write_eld = g4x_write_eld;
 		dev_priv->display.update_wm = g4x_update_wm;
 		dev_priv->display.init_clock_gating = g4x_init_clock_gating;
 	} else if (IS_GEN4(dev)) {
 		dev_priv->display.update_wm = i965_update_wm;
 		if (IS_CRESTLINE(dev))
 			dev_priv->display.init_clock_gating = crestline_init_clock_gating;
 		else if (IS_BROADWATER(dev))
 			dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
 	} else if (IS_GEN3(dev)) {
 		dev_priv->display.update_wm = i9xx_update_wm;
 		dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
 		dev_priv->display.init_clock_gating = gen3_init_clock_gating;
 	} else if (IS_I865G(dev)) {
 		dev_priv->display.update_wm = i830_update_wm;
 		dev_priv->display.init_clock_gating = i85x_init_clock_gating;
 		dev_priv->display.get_fifo_size = i830_get_fifo_size;
 	} else if (IS_I85X(dev)) {
 		dev_priv->display.update_wm = i9xx_update_wm;
 		dev_priv->display.get_fifo_size = i85x_get_fifo_size;
 		dev_priv->display.init_clock_gating = i85x_init_clock_gating;
 	} else {
 		dev_priv->display.update_wm = i830_update_wm;
 		dev_priv->display.init_clock_gating = i830_init_clock_gating;
 		if (IS_845G(dev))
 			dev_priv->display.get_fifo_size = i845_get_fifo_size;
 		else
 			dev_priv->display.get_fifo_size = i830_get_fifo_size;
 	}
 	/* Default just returns -ENODEV to indicate unsupported */
 	dev_priv->display.queue_flip = intel_default_queue_flip;
 	switch (INTEL_INFO(dev)->gen) {
 	case 2:
 		dev_priv->display.queue_flip = intel_gen2_queue_flip;
 		break;
 	case 3:
 		dev_priv->display.queue_flip = intel_gen3_queue_flip;
 		break;
 	case 4:
 	case 5:
 		dev_priv->display.queue_flip = intel_gen4_queue_flip;
 		break;
 	case 6:
 		dev_priv->display.queue_flip = intel_gen6_queue_flip;
 		break;
 	case 7:
 		dev_priv->display.queue_flip = intel_gen7_queue_flip;
 		break;
 	}
 }
 /*
  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
  * resume, or other times.  This quirk makes sure that's the case for
  * affected systems.
  */
 static void quirk_pipea_force(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	dev_priv->quirks |= QUIRK_PIPEA_FORCE;
 	DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
 }
 /*
  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
  */
 static void quirk_ssc_force_disable(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
 }
 struct intel_quirk {
 	int device;
 	int subsystem_vendor;
 	int subsystem_device;
 	void (*hook)(struct drm_device *dev);
 };
 struct intel_quirk intel_quirks[] = {
 	/* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
 	{ 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
 	/* HP Mini needs pipe A force quirk (LP: #322104) */
 	{ 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
 	/* Thinkpad R31 needs pipe A force quirk */
 	{ 0x3577, 0x1014, 0x0505, quirk_pipea_force },
 	/* Toshiba Protege R-205, S-209 needs pipe A force quirk */
 	{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },
 	/* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
 	{ 0x3577,  0x1014, 0x0513, quirk_pipea_force },
 	/* ThinkPad X40 needs pipe A force quirk */
 	/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
 	{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
 	/* 855 & before need to leave pipe A & dpll A up */
 	{ 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
 	{ 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
 	/* Lenovo U160 cannot use SSC on LVDS */
 	{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
 	/* Sony Vaio Y cannot use SSC on LVDS */
 	{ 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
 };
 static void intel_init_quirks(struct drm_device *dev)
 {
 	struct pci_dev *d = dev->pdev;
 	int i;
 	for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
 		struct intel_quirk *q = &intel_quirks[i];
 		if (d->device == q->device &&
 		    (d->subsystem_vendor == q->subsystem_vendor ||
 		     q->subsystem_vendor == PCI_ANY_ID) &&
 		    (d->subsystem_device == q->subsystem_device ||
 		     q->subsystem_device == PCI_ANY_ID))
 			q->hook(dev);
 	}
 }
 /* Disable the VGA plane that we never use */
 static void i915_disable_vga(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u8 sr1;
 	u32 vga_reg;
 	if (HAS_PCH_SPLIT(dev))
 		vga_reg = CPU_VGACNTRL;
 	else
 		vga_reg = VGACNTRL;
 	vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 	outb(1, VGA_SR_INDEX);
 	sr1 = inb(VGA_SR_DATA);
 	outb(sr1 | 1<<5, VGA_SR_DATA);
 	vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 	udelay(300);
 	I915_WRITE(vga_reg, VGA_DISP_DISABLE);
 	POSTING_READ(vga_reg);
 }
 void intel_modeset_init(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int i;
 	drm_mode_config_init(dev);
 	dev->mode_config.min_width = 0;
 	dev->mode_config.min_height = 0;
 	dev->mode_config.funcs = (void *)&intel_mode_funcs;
 	intel_init_quirks(dev);
 	intel_init_display(dev);
 	if (IS_GEN2(dev)) {
 		dev->mode_config.max_width = 2048;
 		dev->mode_config.max_height = 2048;
 	} else if (IS_GEN3(dev)) {
 		dev->mode_config.max_width = 4096;
 		dev->mode_config.max_height = 4096;
 	} else {
 		dev->mode_config.max_width = 8192;
 		dev->mode_config.max_height = 8192;
 	}
 	dev->mode_config.fb_base = dev->agp->base;
 	DRM_DEBUG_KMS("%d display pipe%s available.\n",
 		      dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
 	for (i = 0; i < dev_priv->num_pipe; i++) {
 		intel_crtc_init(dev, i);
 	}
 	/* Just disable it once at startup */
 	i915_disable_vga(dev);
 	intel_setup_outputs(dev);
 	intel_init_clock_gating(dev);
 	if (IS_IRONLAKE_M(dev)) {
 		ironlake_enable_drps(dev);
 		intel_init_emon(dev);
 	}
 	if (IS_GEN6(dev) || IS_GEN7(dev)) {
 		gen6_enable_rps(dev_priv);
 		gen6_update_ring_freq(dev_priv);
 	}
 	INIT_WORK(&dev_priv->idle_work, intel_idle_update);
 	setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
 		    (unsigned long)dev);
 }
 void intel_modeset_gem_init(struct drm_device *dev)
 {
 	if (IS_IRONLAKE_M(dev))
 		ironlake_enable_rc6(dev);
 	intel_setup_overlay(dev);
 }
 void intel_modeset_cleanup(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_crtc *crtc;
 	struct intel_crtc *intel_crtc;
 	drm_kms_helper_poll_fini(dev);
 	mutex_lock(&dev->struct_mutex);
 	intel_unregister_dsm_handler();
 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 		/* Skip inactive CRTCs */
 		if (!crtc->fb)
 			continue;
 		intel_crtc = to_intel_crtc(crtc);
 		intel_increase_pllclock(crtc);
 	}
 	intel_disable_fbc(dev);
 	if (IS_IRONLAKE_M(dev))
 		ironlake_disable_drps(dev);
 	if (IS_GEN6(dev) || IS_GEN7(dev))
 		gen6_disable_rps(dev);
 	if (IS_IRONLAKE_M(dev))
 		ironlake_disable_rc6(dev);
 	mutex_unlock(&dev->struct_mutex);
 	/* Disable the irq before mode object teardown, for the irq might
 	 * enqueue unpin/hotplug work. */
 	drm_irq_uninstall(dev);
 	cancel_work_sync(&dev_priv->hotplug_work);
 	cancel_work_sync(&dev_priv->rps_work);
 	/* flush any delayed tasks or pending work */
 	flush_scheduled_work();
 	/* Shut off idle work before the crtcs get freed. */
 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 		intel_crtc = to_intel_crtc(crtc);
 		del_timer_sync(&intel_crtc->idle_timer);
 	}
 	del_timer_sync(&dev_priv->idle_timer);
 	cancel_work_sync(&dev_priv->idle_work);
 	drm_mode_config_cleanup(dev);
 }
 /*
  * Return which encoder is currently attached for connector.
  */
 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
 {
 	return &intel_attached_encoder(connector)->base;
 }
 void intel_connector_attach_encoder(struct intel_connector *connector,
 				    struct intel_encoder *encoder)
 {
 	connector->encoder = encoder;
 	drm_mode_connector_attach_encoder(&connector->base,
 					  &encoder->base);
 }
 /*
  * set vga decode state - true == enable VGA decode
  */
 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u16 gmch_ctrl;
 	pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
 	if (state)
 		gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
 	else
 		gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
 	pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
 	return 0;
 }
 #ifdef CONFIG_DEBUG_FS
 #include <linux/seq_file.h>
 struct intel_display_error_state {
 	struct intel_cursor_error_state {
 		u32 control;
 		u32 position;
 		u32 base;
 		u32 size;
 	} cursor[2];
 	struct intel_pipe_error_state {
 		u32 conf;
 		u32 source;
 		u32 htotal;
 		u32 hblank;
 		u32 hsync;
 		u32 vtotal;
 		u32 vblank;
 		u32 vsync;
 	} pipe[2];
 	struct intel_plane_error_state {
 		u32 control;
 		u32 stride;
 		u32 size;
 		u32 pos;
 		u32 addr;
 		u32 surface;
 		u32 tile_offset;
 	} plane[2];
 };
 struct intel_display_error_state *
 intel_display_capture_error_state(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct intel_display_error_state *error;
 	int i;
 	error = kmalloc(sizeof(*error), GFP_ATOMIC);
 	if (error == NULL)
 		return NULL;
 	for (i = 0; i < 2; i++) {
 		error->cursor[i].control = I915_READ(CURCNTR(i));
 		error->cursor[i].position = I915_READ(CURPOS(i));
 		error->cursor[i].base = I915_READ(CURBASE(i));
 		error->plane[i].control = I915_READ(DSPCNTR(i));
 		error->plane[i].stride = I915_READ(DSPSTRIDE(i));
 		error->plane[i].size = I915_READ(DSPSIZE(i));
 		error->plane[i].pos = I915_READ(DSPPOS(i));
 		error->plane[i].addr = I915_READ(DSPADDR(i));
 		if (INTEL_INFO(dev)->gen >= 4) {
 			error->plane[i].surface = I915_READ(DSPSURF(i));
 			error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
 		}
 		error->pipe[i].conf = I915_READ(PIPECONF(i));
 		error->pipe[i].source = I915_READ(PIPESRC(i));
 		error->pipe[i].htotal = I915_READ(HTOTAL(i));
 		error->pipe[i].hblank = I915_READ(HBLANK(i));
 		error->pipe[i].hsync = I915_READ(HSYNC(i));
 		error->pipe[i].vtotal = I915_READ(VTOTAL(i));
 		error->pipe[i].vblank = I915_READ(VBLANK(i));
 		error->pipe[i].vsync = I915_READ(VSYNC(i));
 	}
 	return error;
 }
 void
 intel_display_print_error_state(struct seq_file *m,
 				struct drm_device *dev,
 				struct intel_display_error_state *error)
 {
 	int i;
 	for (i = 0; i < 2; i++) {
 		seq_printf(m, "Pipe [%d]:\n", i);
 		seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
 		seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
 		seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
 		seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
 		seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
 		seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
 		seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
 		seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
 		seq_printf(m, "Plane [%d]:\n", i);
 		seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
 		seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
 		seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
 		seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
 		seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
 		if (INTEL_INFO(dev)->gen >= 4) {
 			seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
 			seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
 		}
 		seq_printf(m, "Cursor [%d]:\n", i);
 		seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
 		seq_printf(m, "  POS: %08x\n", error->cursor[i].position);