Doug / smarc-fsl-linux-kernel

Download as
Browse Code ยป

Commit 795570561cc9c8dc7f7582ed6c4d07121b1c4831

Authored by Jorge Eduardo Candelaria
Committed by Liam Girdwood
1 parent 3c24019dde
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

MFD: TPS65910: Add support for TPS65911 device 

The TPS65911 is the next generation of the TPS65910 family of
PMIC chips. It adds a few features:

- Watchdog Timer
- PWM & LED generators
- Comparators for system control status

It also adds a set of Interrupts and GPIOs, among other things.

The driver exports a function to identify between different
versions of the tps65910 family, allowing other modules to
identify the capabilities of the current chip.

Signed-off-by: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
Acked-by: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>

Showing 2 changed files with 49 additions and 1 deletions Inline Diff

drivers/mfd/tps65910.c
Diff comments   View file @ 7955705
1 /* 1 /*
2 * tps65910.c -- TI TPS6591x 2 * tps65910.c -- TI TPS6591x
3 * 3 *
4 * Copyright 2010 Texas Instruments Inc. 4 * Copyright 2010 Texas Instruments Inc.
5 * 5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk> 6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk> 7 * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify it 9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the 10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your 11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version. 12 * option) any later version.
13 * 13 *
14 */ 14 */
15 15
16 #include <linux/module.h> 16 #include <linux/module.h>
17 #include <linux/moduleparam.h> 17 #include <linux/moduleparam.h>
18 #include <linux/init.h> 18 #include <linux/init.h>
19 #include <linux/slab.h> 19 #include <linux/slab.h>
20 #include <linux/i2c.h> 20 #include <linux/i2c.h>
21 #include <linux/gpio.h> 21 #include <linux/gpio.h>
22 #include <linux/mfd/core.h> 22 #include <linux/mfd/core.h>
23 #include <linux/mfd/tps65910.h> 23 #include <linux/mfd/tps65910.h>
24 24
25 static struct mfd_cell tps65910s[] = { 25 static struct mfd_cell tps65910s[] = {
26 { 26 {
27 .name = "tps65910-pmic", 27 .name = "tps65910-pmic",
28 }, 28 },
29 { 29 {
30 .name = "tps65910-rtc", 30 .name = "tps65910-rtc",
31 }, 31 },
32 { 32 {
33 .name = "tps65910-power", 33 .name = "tps65910-power",
34 }, 34 },
35 }; 35 };
36 36
37 37
38 static int tps65910_i2c_read(struct tps65910 *tps65910, u8 reg, 38 static int tps65910_i2c_read(struct tps65910 *tps65910, u8 reg,
39 int bytes, void *dest) 39 int bytes, void *dest)
40 { 40 {
41 struct i2c_client *i2c = tps65910->i2c_client; 41 struct i2c_client *i2c = tps65910->i2c_client;
42 struct i2c_msg xfer[2]; 42 struct i2c_msg xfer[2];
43 int ret; 43 int ret;
44 44
45 /* Write register */ 45 /* Write register */
46 xfer[0].addr = i2c->addr; 46 xfer[0].addr = i2c->addr;
47 xfer[0].flags = 0; 47 xfer[0].flags = 0;
48 xfer[0].len = 1; 48 xfer[0].len = 1;
49 xfer[0].buf = &reg; 49 xfer[0].buf = &reg;
50 50
51 /* Read data */ 51 /* Read data */
52 xfer[1].addr = i2c->addr; 52 xfer[1].addr = i2c->addr;
53 xfer[1].flags = I2C_M_RD; 53 xfer[1].flags = I2C_M_RD;
54 xfer[1].len = bytes; 54 xfer[1].len = bytes;
55 xfer[1].buf = dest; 55 xfer[1].buf = dest;
56 56
57 ret = i2c_transfer(i2c->adapter, xfer, 2); 57 ret = i2c_transfer(i2c->adapter, xfer, 2);
58 if (ret == 2) 58 if (ret == 2)
59 ret = 0; 59 ret = 0;
60 else if (ret >= 0) 60 else if (ret >= 0)
61 ret = -EIO; 61 ret = -EIO;
62 62
63 return ret; 63 return ret;
64 } 64 }
65 65
66 static int tps65910_i2c_write(struct tps65910 *tps65910, u8 reg, 66 static int tps65910_i2c_write(struct tps65910 *tps65910, u8 reg,
67 int bytes, void *src) 67 int bytes, void *src)
68 { 68 {
69 struct i2c_client *i2c = tps65910->i2c_client; 69 struct i2c_client *i2c = tps65910->i2c_client;
70 /* we add 1 byte for device register */ 70 /* we add 1 byte for device register */
71 u8 msg[TPS65910_MAX_REGISTER + 1]; 71 u8 msg[TPS65910_MAX_REGISTER + 1];
72 int ret; 72 int ret;
73 73
74 if (bytes > TPS65910_MAX_REGISTER) 74 if (bytes > TPS65910_MAX_REGISTER)
75 return -EINVAL; 75 return -EINVAL;
76 76
77 msg[0] = reg; 77 msg[0] = reg;
78 memcpy(&msg[1], src, bytes); 78 memcpy(&msg[1], src, bytes);
79 79
80 ret = i2c_master_send(i2c, msg, bytes + 1); 80 ret = i2c_master_send(i2c, msg, bytes + 1);
81 if (ret < 0) 81 if (ret < 0)
82 return ret; 82 return ret;
83 if (ret != bytes + 1) 83 if (ret != bytes + 1)
84 return -EIO; 84 return -EIO;
85 return 0; 85 return 0;
86 } 86 }
87 87
88 int tps65910_set_bits(struct tps65910 *tps65910, u8 reg, u8 mask) 88 int tps65910_set_bits(struct tps65910 *tps65910, u8 reg, u8 mask)
89 { 89 {
90 u8 data; 90 u8 data;
91 int err; 91 int err;
92 92
93 mutex_lock(&tps65910->io_mutex); 93 mutex_lock(&tps65910->io_mutex);
94 err = tps65910_i2c_read(tps65910, reg, 1, &data); 94 err = tps65910_i2c_read(tps65910, reg, 1, &data);
95 if (err) { 95 if (err) {
96 dev_err(tps65910->dev, "read from reg %x failed\n", reg); 96 dev_err(tps65910->dev, "read from reg %x failed\n", reg);
97 goto out; 97 goto out;
98 } 98 }
99 99
100 data |= mask; 100 data |= mask;
101 err = tps65910_i2c_write(tps65910, reg, 1, &data); 101 err = tps65910_i2c_write(tps65910, reg, 1, &data);
102 if (err) 102 if (err)
103 dev_err(tps65910->dev, "write to reg %x failed\n", reg); 103 dev_err(tps65910->dev, "write to reg %x failed\n", reg);
104 104
105 out: 105 out:
106 mutex_unlock(&tps65910->io_mutex); 106 mutex_unlock(&tps65910->io_mutex);
107 return err; 107 return err;
108 } 108 }
109 EXPORT_SYMBOL_GPL(tps65910_set_bits); 109 EXPORT_SYMBOL_GPL(tps65910_set_bits);
110 110
111 int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask) 111 int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask)
112 { 112 {
113 u8 data; 113 u8 data;
114 int err; 114 int err;
115 115
116 mutex_lock(&tps65910->io_mutex); 116 mutex_lock(&tps65910->io_mutex);
117 err = tps65910_i2c_read(tps65910, reg, 1, &data); 117 err = tps65910_i2c_read(tps65910, reg, 1, &data);
118 if (err) { 118 if (err) {
119 dev_err(tps65910->dev, "read from reg %x failed\n", reg); 119 dev_err(tps65910->dev, "read from reg %x failed\n", reg);
120 goto out; 120 goto out;
121 } 121 }
122 122
123 data &= mask; 123 data &= mask;
124 err = tps65910_i2c_write(tps65910, reg, 1, &data); 124 err = tps65910_i2c_write(tps65910, reg, 1, &data);
125 if (err) 125 if (err)
126 dev_err(tps65910->dev, "write to reg %x failed\n", reg); 126 dev_err(tps65910->dev, "write to reg %x failed\n", reg);
127 127
128 out: 128 out:
129 mutex_unlock(&tps65910->io_mutex); 129 mutex_unlock(&tps65910->io_mutex);
130 return err; 130 return err;
131 } 131 }
132 EXPORT_SYMBOL_GPL(tps65910_clear_bits); 132 EXPORT_SYMBOL_GPL(tps65910_clear_bits);
133 133
134 static int tps65910_i2c_probe(struct i2c_client *i2c, 134 static int tps65910_i2c_probe(struct i2c_client *i2c,
135 const struct i2c_device_id *id) 135 const struct i2c_device_id *id)
136 { 136 {
137 struct tps65910 *tps65910; 137 struct tps65910 *tps65910;
138 struct tps65910_board *pmic_plat_data; 138 struct tps65910_board *pmic_plat_data;
139 struct tps65910_platform_data *init_data; 139 struct tps65910_platform_data *init_data;
140 int ret = 0; 140 int ret = 0;
141 141
142 pmic_plat_data = dev_get_platdata(&i2c->dev); 142 pmic_plat_data = dev_get_platdata(&i2c->dev);
143 if (!pmic_plat_data) 143 if (!pmic_plat_data)
144 return -EINVAL; 144 return -EINVAL;
145 145
146 init_data = kzalloc(sizeof(struct tps65910_platform_data), GFP_KERNEL); 146 init_data = kzalloc(sizeof(struct tps65910_platform_data), GFP_KERNEL);
147 if (init_data == NULL) 147 if (init_data == NULL)
148 return -ENOMEM; 148 return -ENOMEM;
149 149
150 init_data->irq = pmic_plat_data->irq; 150 init_data->irq = pmic_plat_data->irq;
151 init_data->irq_base = pmic_plat_data->irq; 151 init_data->irq_base = pmic_plat_data->irq;
152 152
153 tps65910 = kzalloc(sizeof(struct tps65910), GFP_KERNEL); 153 tps65910 = kzalloc(sizeof(struct tps65910), GFP_KERNEL);
154 if (tps65910 == NULL) 154 if (tps65910 == NULL)
155 return -ENOMEM; 155 return -ENOMEM;
156 156
157 i2c_set_clientdata(i2c, tps65910); 157 i2c_set_clientdata(i2c, tps65910);
158 tps65910->dev = &i2c->dev; 158 tps65910->dev = &i2c->dev;
159 tps65910->i2c_client = i2c; 159 tps65910->i2c_client = i2c;
160 tps65910->id = id->driver_data;
160 tps65910->read = tps65910_i2c_read; 161 tps65910->read = tps65910_i2c_read;
161 tps65910->write = tps65910_i2c_write; 162 tps65910->write = tps65910_i2c_write;
162 mutex_init(&tps65910->io_mutex); 163 mutex_init(&tps65910->io_mutex);
163 164
164 ret = mfd_add_devices(tps65910->dev, -1, 165 ret = mfd_add_devices(tps65910->dev, -1,
165 tps65910s, ARRAY_SIZE(tps65910s), 166 tps65910s, ARRAY_SIZE(tps65910s),
166 NULL, 0); 167 NULL, 0);
167 if (ret < 0) 168 if (ret < 0)
168 goto err; 169 goto err;
169 170
170 tps65910_gpio_init(tps65910, pmic_plat_data->gpio_base); 171 tps65910_gpio_init(tps65910, pmic_plat_data->gpio_base);
171 172
172 ret = tps65910_irq_init(tps65910, init_data->irq, init_data); 173 ret = tps65910_irq_init(tps65910, init_data->irq, init_data);
173 if (ret < 0) 174 if (ret < 0)
174 goto err; 175 goto err;
175 176
176 return ret; 177 return ret;
177 178
178 err: 179 err:
179 mfd_remove_devices(tps65910->dev); 180 mfd_remove_devices(tps65910->dev);
180 kfree(tps65910); 181 kfree(tps65910);
181 return ret; 182 return ret;
182 } 183 }
183 184
184 static int tps65910_i2c_remove(struct i2c_client *i2c) 185 static int tps65910_i2c_remove(struct i2c_client *i2c)
185 { 186 {
186 struct tps65910 *tps65910 = i2c_get_clientdata(i2c); 187 struct tps65910 *tps65910 = i2c_get_clientdata(i2c);
187 188
188 mfd_remove_devices(tps65910->dev); 189 mfd_remove_devices(tps65910->dev);
189 kfree(tps65910); 190 kfree(tps65910);
190 191
191 return 0; 192 return 0;
192 } 193 }
193 194
194 static const struct i2c_device_id tps65910_i2c_id[] = { 195 static const struct i2c_device_id tps65910_i2c_id[] = {
195 { "tps65910", 0 }, 196 { "tps65910", TPS65910 },
197 { "tps65911", TPS65911 },
196 { } 198 { }
197 }; 199 };
198 MODULE_DEVICE_TABLE(i2c, tps65910_i2c_id); 200 MODULE_DEVICE_TABLE(i2c, tps65910_i2c_id);
199 201
200 202
201 static struct i2c_driver tps65910_i2c_driver = { 203 static struct i2c_driver tps65910_i2c_driver = {
202 .driver = { 204 .driver = {
203 .name = "tps65910", 205 .name = "tps65910",
204 .owner = THIS_MODULE, 206 .owner = THIS_MODULE,
205 }, 207 },
206 .probe = tps65910_i2c_probe, 208 .probe = tps65910_i2c_probe,
207 .remove = tps65910_i2c_remove, 209 .remove = tps65910_i2c_remove,
208 .id_table = tps65910_i2c_id, 210 .id_table = tps65910_i2c_id,
209 }; 211 };
210 212
211 static int __init tps65910_i2c_init(void) 213 static int __init tps65910_i2c_init(void)
212 { 214 {
213 return i2c_add_driver(&tps65910_i2c_driver); 215 return i2c_add_driver(&tps65910_i2c_driver);
214 } 216 }
215 /* init early so consumer devices can complete system boot */ 217 /* init early so consumer devices can complete system boot */
216 subsys_initcall(tps65910_i2c_init); 218 subsys_initcall(tps65910_i2c_init);
217 219
218 static void __exit tps65910_i2c_exit(void) 220 static void __exit tps65910_i2c_exit(void)
219 { 221 {
220 i2c_del_driver(&tps65910_i2c_driver); 222 i2c_del_driver(&tps65910_i2c_driver);
221 } 223 }
222 module_exit(tps65910_i2c_exit); 224 module_exit(tps65910_i2c_exit);
223 225
224 MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>"); 226 MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
225 MODULE_AUTHOR("Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>"); 227 MODULE_AUTHOR("Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>");
226 MODULE_DESCRIPTION("TPS6591x chip family multi-function driver"); 228 MODULE_DESCRIPTION("TPS6591x chip family multi-function driver");
227 MODULE_LICENSE("GPL"); 229 MODULE_LICENSE("GPL");
228 230
include/linux/mfd/tps65910.h
Diff comments   View file @ 7955705
1 /* 1 /*
2 * tps65910.h -- TI TPS6591x 2 * tps65910.h -- TI TPS6591x
3 * 3 *
4 * Copyright 2010-2011 Texas Instruments Inc. 4 * Copyright 2010-2011 Texas Instruments Inc.
5 * 5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk> 6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk> 7 * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
8 * Author: Arnaud Deconinck <a-deconinck@ti.com> 8 * Author: Arnaud Deconinck <a-deconinck@ti.com>
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify it 10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the 11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your 12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version. 13 * option) any later version.
14 * 14 *
15 */ 15 */
16 16
17 #ifndef __LINUX_MFD_TPS65910_H 17 #ifndef __LINUX_MFD_TPS65910_H
18 #define __LINUX_MFD_TPS65910_H 18 #define __LINUX_MFD_TPS65910_H
19 19
20 /* TPS chip id list */
21 #define TPS65910 0
22 #define TPS65911 1
23
24 /* TPS regulator type list */
25 #define REGULATOR_LDO 0
26 #define REGULATOR_DCDC 1
27
20 /* 28 /*
21 * List of registers for component TPS65910 29 * List of registers for component TPS65910
22 * 30 *
23 */ 31 */
24 32
25 #define TPS65910_SECONDS 0x0 33 #define TPS65910_SECONDS 0x0
26 #define TPS65910_MINUTES 0x1 34 #define TPS65910_MINUTES 0x1
27 #define TPS65910_HOURS 0x2 35 #define TPS65910_HOURS 0x2
28 #define TPS65910_DAYS 0x3 36 #define TPS65910_DAYS 0x3
29 #define TPS65910_MONTHS 0x4 37 #define TPS65910_MONTHS 0x4
30 #define TPS65910_YEARS 0x5 38 #define TPS65910_YEARS 0x5
31 #define TPS65910_WEEKS 0x6 39 #define TPS65910_WEEKS 0x6
32 #define TPS65910_ALARM_SECONDS 0x8 40 #define TPS65910_ALARM_SECONDS 0x8
33 #define TPS65910_ALARM_MINUTES 0x9 41 #define TPS65910_ALARM_MINUTES 0x9
34 #define TPS65910_ALARM_HOURS 0xA 42 #define TPS65910_ALARM_HOURS 0xA
35 #define TPS65910_ALARM_DAYS 0xB 43 #define TPS65910_ALARM_DAYS 0xB
36 #define TPS65910_ALARM_MONTHS 0xC 44 #define TPS65910_ALARM_MONTHS 0xC
37 #define TPS65910_ALARM_YEARS 0xD 45 #define TPS65910_ALARM_YEARS 0xD
38 #define TPS65910_RTC_CTRL 0x10 46 #define TPS65910_RTC_CTRL 0x10
39 #define TPS65910_RTC_STATUS 0x11 47 #define TPS65910_RTC_STATUS 0x11
40 #define TPS65910_RTC_INTERRUPTS 0x12 48 #define TPS65910_RTC_INTERRUPTS 0x12
41 #define TPS65910_RTC_COMP_LSB 0x13 49 #define TPS65910_RTC_COMP_LSB 0x13
42 #define TPS65910_RTC_COMP_MSB 0x14 50 #define TPS65910_RTC_COMP_MSB 0x14
43 #define TPS65910_RTC_RES_PROG 0x15 51 #define TPS65910_RTC_RES_PROG 0x15
44 #define TPS65910_RTC_RESET_STATUS 0x16 52 #define TPS65910_RTC_RESET_STATUS 0x16
45 #define TPS65910_BCK1 0x17 53 #define TPS65910_BCK1 0x17
46 #define TPS65910_BCK2 0x18 54 #define TPS65910_BCK2 0x18
47 #define TPS65910_BCK3 0x19 55 #define TPS65910_BCK3 0x19
48 #define TPS65910_BCK4 0x1A 56 #define TPS65910_BCK4 0x1A
49 #define TPS65910_BCK5 0x1B 57 #define TPS65910_BCK5 0x1B
50 #define TPS65910_PUADEN 0x1C 58 #define TPS65910_PUADEN 0x1C
51 #define TPS65910_REF 0x1D 59 #define TPS65910_REF 0x1D
52 #define TPS65910_VRTC 0x1E 60 #define TPS65910_VRTC 0x1E
53 #define TPS65910_VIO 0x20 61 #define TPS65910_VIO 0x20
54 #define TPS65910_VDD1 0x21 62 #define TPS65910_VDD1 0x21
55 #define TPS65910_VDD1_OP 0x22 63 #define TPS65910_VDD1_OP 0x22
56 #define TPS65910_VDD1_SR 0x23 64 #define TPS65910_VDD1_SR 0x23
57 #define TPS65910_VDD2 0x24 65 #define TPS65910_VDD2 0x24
58 #define TPS65910_VDD2_OP 0x25 66 #define TPS65910_VDD2_OP 0x25
59 #define TPS65910_VDD2_SR 0x26 67 #define TPS65910_VDD2_SR 0x26
60 #define TPS65910_VDD3 0x27 68 #define TPS65910_VDD3 0x27
61 #define TPS65910_VDIG1 0x30 69 #define TPS65910_VDIG1 0x30
62 #define TPS65910_VDIG2 0x31 70 #define TPS65910_VDIG2 0x31
63 #define TPS65910_VAUX1 0x32 71 #define TPS65910_VAUX1 0x32
64 #define TPS65910_VAUX2 0x33 72 #define TPS65910_VAUX2 0x33
65 #define TPS65910_VAUX33 0x34 73 #define TPS65910_VAUX33 0x34
66 #define TPS65910_VMMC 0x35 74 #define TPS65910_VMMC 0x35
67 #define TPS65910_VPLL 0x36 75 #define TPS65910_VPLL 0x36
68 #define TPS65910_VDAC 0x37 76 #define TPS65910_VDAC 0x37
69 #define TPS65910_THERM 0x38 77 #define TPS65910_THERM 0x38
70 #define TPS65910_BBCH 0x39 78 #define TPS65910_BBCH 0x39
71 #define TPS65910_DCDCCTRL 0x3E 79 #define TPS65910_DCDCCTRL 0x3E
72 #define TPS65910_DEVCTRL 0x3F 80 #define TPS65910_DEVCTRL 0x3F
73 #define TPS65910_DEVCTRL2 0x40 81 #define TPS65910_DEVCTRL2 0x40
74 #define TPS65910_SLEEP_KEEP_LDO_ON 0x41 82 #define TPS65910_SLEEP_KEEP_LDO_ON 0x41
75 #define TPS65910_SLEEP_KEEP_RES_ON 0x42 83 #define TPS65910_SLEEP_KEEP_RES_ON 0x42
76 #define TPS65910_SLEEP_SET_LDO_OFF 0x43 84 #define TPS65910_SLEEP_SET_LDO_OFF 0x43
77 #define TPS65910_SLEEP_SET_RES_OFF 0x44 85 #define TPS65910_SLEEP_SET_RES_OFF 0x44
78 #define TPS65910_EN1_LDO_ASS 0x45 86 #define TPS65910_EN1_LDO_ASS 0x45
79 #define TPS65910_EN1_SMPS_ASS 0x46 87 #define TPS65910_EN1_SMPS_ASS 0x46
80 #define TPS65910_EN2_LDO_ASS 0x47 88 #define TPS65910_EN2_LDO_ASS 0x47
81 #define TPS65910_EN2_SMPS_ASS 0x48 89 #define TPS65910_EN2_SMPS_ASS 0x48
82 #define TPS65910_EN3_LDO_ASS 0x49 90 #define TPS65910_EN3_LDO_ASS 0x49
83 #define TPS65910_SPARE 0x4A 91 #define TPS65910_SPARE 0x4A
84 #define TPS65910_INT_STS 0x50 92 #define TPS65910_INT_STS 0x50
85 #define TPS65910_INT_MSK 0x51 93 #define TPS65910_INT_MSK 0x51
86 #define TPS65910_INT_STS2 0x52 94 #define TPS65910_INT_STS2 0x52
87 #define TPS65910_INT_MSK2 0x53 95 #define TPS65910_INT_MSK2 0x53
88 #define TPS65910_INT_STS3 0x54 96 #define TPS65910_INT_STS3 0x54
89 #define TPS65910_INT_MSK3 0x55 97 #define TPS65910_INT_MSK3 0x55
90 #define TPS65910_GPIO0 0x60 98 #define TPS65910_GPIO0 0x60
91 #define TPS65910_GPIO1 0x61 99 #define TPS65910_GPIO1 0x61
92 #define TPS65910_GPIO2 0x62 100 #define TPS65910_GPIO2 0x62
93 #define TPS65910_GPIO3 0x63 101 #define TPS65910_GPIO3 0x63
94 #define TPS65910_GPIO4 0x64 102 #define TPS65910_GPIO4 0x64
95 #define TPS65910_GPIO5 0x65 103 #define TPS65910_GPIO5 0x65
96 #define TPS65910_JTAGVERNUM 0x80 104 #define TPS65910_JTAGVERNUM 0x80
97 #define TPS65910_MAX_REGISTER 0x80 105 #define TPS65910_MAX_REGISTER 0x80
98 106
99 /* 107 /*
108 * List of registers specific to TPS65911
109 */
110 #define TPS65911_VDDCTRL 0x27
111 #define TPS65911_VDDCTRL_OP 0x28
112 #define TPS65911_VDDCTRL_SR 0x29
113 #define TPS65911_LDO1 0x30
114 #define TPS65911_LDO2 0x31
115 #define TPS65911_LDO5 0x32
116 #define TPS65911_LDO8 0x33
117 #define TPS65911_LDO7 0x34
118 #define TPS65911_LDO6 0x35
119 #define TPS65911_LDO4 0x36
120 #define TPS65911_LDO3 0x37
121
122 /*
100 * List of register bitfields for component TPS65910 123 * List of register bitfields for component TPS65910
101 * 124 *
102 */ 125 */
103 126
104 127
105 /*Register BCK1 (0x80) register.RegisterDescription */ 128 /*Register BCK1 (0x80) register.RegisterDescription */
106 #define BCK1_BCKUP_MASK 0xFF 129 #define BCK1_BCKUP_MASK 0xFF
107 #define BCK1_BCKUP_SHIFT 0 130 #define BCK1_BCKUP_SHIFT 0
108 131
109 132
110 /*Register BCK2 (0x80) register.RegisterDescription */ 133 /*Register BCK2 (0x80) register.RegisterDescription */
111 #define BCK2_BCKUP_MASK 0xFF 134 #define BCK2_BCKUP_MASK 0xFF
112 #define BCK2_BCKUP_SHIFT 0 135 #define BCK2_BCKUP_SHIFT 0
113 136
114 137
115 /*Register BCK3 (0x80) register.RegisterDescription */ 138 /*Register BCK3 (0x80) register.RegisterDescription */
116 #define BCK3_BCKUP_MASK 0xFF 139 #define BCK3_BCKUP_MASK 0xFF
117 #define BCK3_BCKUP_SHIFT 0 140 #define BCK3_BCKUP_SHIFT 0
118 141
119 142
120 /*Register BCK4 (0x80) register.RegisterDescription */ 143 /*Register BCK4 (0x80) register.RegisterDescription */
121 #define BCK4_BCKUP_MASK 0xFF 144 #define BCK4_BCKUP_MASK 0xFF
122 #define BCK4_BCKUP_SHIFT 0 145 #define BCK4_BCKUP_SHIFT 0
123 146
124 147
125 /*Register BCK5 (0x80) register.RegisterDescription */ 148 /*Register BCK5 (0x80) register.RegisterDescription */
126 #define BCK5_BCKUP_MASK 0xFF 149 #define BCK5_BCKUP_MASK 0xFF
127 #define BCK5_BCKUP_SHIFT 0 150 #define BCK5_BCKUP_SHIFT 0
128 151
129 152
130 /*Register PUADEN (0x80) register.RegisterDescription */ 153 /*Register PUADEN (0x80) register.RegisterDescription */
131 #define PUADEN_EN3P_MASK 0x80 154 #define PUADEN_EN3P_MASK 0x80
132 #define PUADEN_EN3P_SHIFT 7 155 #define PUADEN_EN3P_SHIFT 7
133 #define PUADEN_I2CCTLP_MASK 0x40 156 #define PUADEN_I2CCTLP_MASK 0x40
134 #define PUADEN_I2CCTLP_SHIFT 6 157 #define PUADEN_I2CCTLP_SHIFT 6
135 #define PUADEN_I2CSRP_MASK 0x20 158 #define PUADEN_I2CSRP_MASK 0x20
136 #define PUADEN_I2CSRP_SHIFT 5 159 #define PUADEN_I2CSRP_SHIFT 5
137 #define PUADEN_PWRONP_MASK 0x10 160 #define PUADEN_PWRONP_MASK 0x10
138 #define PUADEN_PWRONP_SHIFT 4 161 #define PUADEN_PWRONP_SHIFT 4
139 #define PUADEN_SLEEPP_MASK 0x08 162 #define PUADEN_SLEEPP_MASK 0x08
140 #define PUADEN_SLEEPP_SHIFT 3 163 #define PUADEN_SLEEPP_SHIFT 3
141 #define PUADEN_PWRHOLDP_MASK 0x04 164 #define PUADEN_PWRHOLDP_MASK 0x04
142 #define PUADEN_PWRHOLDP_SHIFT 2 165 #define PUADEN_PWRHOLDP_SHIFT 2
143 #define PUADEN_BOOT1P_MASK 0x02 166 #define PUADEN_BOOT1P_MASK 0x02
144 #define PUADEN_BOOT1P_SHIFT 1 167 #define PUADEN_BOOT1P_SHIFT 1
145 #define PUADEN_BOOT0P_MASK 0x01 168 #define PUADEN_BOOT0P_MASK 0x01
146 #define PUADEN_BOOT0P_SHIFT 0 169 #define PUADEN_BOOT0P_SHIFT 0
147 170
148 171
149 /*Register REF (0x80) register.RegisterDescription */ 172 /*Register REF (0x80) register.RegisterDescription */
150 #define REF_VMBCH_SEL_MASK 0x0C 173 #define REF_VMBCH_SEL_MASK 0x0C
151 #define REF_VMBCH_SEL_SHIFT 2 174 #define REF_VMBCH_SEL_SHIFT 2
152 #define REF_ST_MASK 0x03 175 #define REF_ST_MASK 0x03
153 #define REF_ST_SHIFT 0 176 #define REF_ST_SHIFT 0
154 177
155 178
156 /*Register VRTC (0x80) register.RegisterDescription */ 179 /*Register VRTC (0x80) register.RegisterDescription */
157 #define VRTC_VRTC_OFFMASK_MASK 0x08 180 #define VRTC_VRTC_OFFMASK_MASK 0x08
158 #define VRTC_VRTC_OFFMASK_SHIFT 3 181 #define VRTC_VRTC_OFFMASK_SHIFT 3
159 #define VRTC_ST_MASK 0x03 182 #define VRTC_ST_MASK 0x03
160 #define VRTC_ST_SHIFT 0 183 #define VRTC_ST_SHIFT 0
161 184
162 185
163 /*Register VIO (0x80) register.RegisterDescription */ 186 /*Register VIO (0x80) register.RegisterDescription */
164 #define VIO_ILMAX_MASK 0xC0 187 #define VIO_ILMAX_MASK 0xC0
165 #define VIO_ILMAX_SHIFT 6 188 #define VIO_ILMAX_SHIFT 6
166 #define VIO_SEL_MASK 0x0C 189 #define VIO_SEL_MASK 0x0C
167 #define VIO_SEL_SHIFT 2 190 #define VIO_SEL_SHIFT 2
168 #define VIO_ST_MASK 0x03 191 #define VIO_ST_MASK 0x03
169 #define VIO_ST_SHIFT 0 192 #define VIO_ST_SHIFT 0
170 193
171 194
172 /*Register VDD1 (0x80) register.RegisterDescription */ 195 /*Register VDD1 (0x80) register.RegisterDescription */
173 #define VDD1_VGAIN_SEL_MASK 0xC0 196 #define VDD1_VGAIN_SEL_MASK 0xC0
174 #define VDD1_VGAIN_SEL_SHIFT 6 197 #define VDD1_VGAIN_SEL_SHIFT 6
175 #define VDD1_ILMAX_MASK 0x20 198 #define VDD1_ILMAX_MASK 0x20
176 #define VDD1_ILMAX_SHIFT 5 199 #define VDD1_ILMAX_SHIFT 5
177 #define VDD1_TSTEP_MASK 0x1C 200 #define VDD1_TSTEP_MASK 0x1C
178 #define VDD1_TSTEP_SHIFT 2 201 #define VDD1_TSTEP_SHIFT 2
179 #define VDD1_ST_MASK 0x03 202 #define VDD1_ST_MASK 0x03
180 #define VDD1_ST_SHIFT 0 203 #define VDD1_ST_SHIFT 0
181 204
182 205
183 /*Register VDD1_OP (0x80) register.RegisterDescription */ 206 /*Register VDD1_OP (0x80) register.RegisterDescription */
184 #define VDD1_OP_CMD_MASK 0x80 207 #define VDD1_OP_CMD_MASK 0x80
185 #define VDD1_OP_CMD_SHIFT 7 208 #define VDD1_OP_CMD_SHIFT 7
186 #define VDD1_OP_SEL_MASK 0x7F 209 #define VDD1_OP_SEL_MASK 0x7F
187 #define VDD1_OP_SEL_SHIFT 0 210 #define VDD1_OP_SEL_SHIFT 0
188 211
189 212
190 /*Register VDD1_SR (0x80) register.RegisterDescription */ 213 /*Register VDD1_SR (0x80) register.RegisterDescription */
191 #define VDD1_SR_SEL_MASK 0x7F 214 #define VDD1_SR_SEL_MASK 0x7F
192 #define VDD1_SR_SEL_SHIFT 0 215 #define VDD1_SR_SEL_SHIFT 0
193 216
194 217
195 /*Register VDD2 (0x80) register.RegisterDescription */ 218 /*Register VDD2 (0x80) register.RegisterDescription */
196 #define VDD2_VGAIN_SEL_MASK 0xC0 219 #define VDD2_VGAIN_SEL_MASK 0xC0
197 #define VDD2_VGAIN_SEL_SHIFT 6 220 #define VDD2_VGAIN_SEL_SHIFT 6
198 #define VDD2_ILMAX_MASK 0x20 221 #define VDD2_ILMAX_MASK 0x20
199 #define VDD2_ILMAX_SHIFT 5 222 #define VDD2_ILMAX_SHIFT 5
200 #define VDD2_TSTEP_MASK 0x1C 223 #define VDD2_TSTEP_MASK 0x1C
201 #define VDD2_TSTEP_SHIFT 2 224 #define VDD2_TSTEP_SHIFT 2
202 #define VDD2_ST_MASK 0x03 225 #define VDD2_ST_MASK 0x03
203 #define VDD2_ST_SHIFT 0 226 #define VDD2_ST_SHIFT 0
204 227
205 228
206 /*Register VDD2_OP (0x80) register.RegisterDescription */ 229 /*Register VDD2_OP (0x80) register.RegisterDescription */
207 #define VDD2_OP_CMD_MASK 0x80 230 #define VDD2_OP_CMD_MASK 0x80
208 #define VDD2_OP_CMD_SHIFT 7 231 #define VDD2_OP_CMD_SHIFT 7
209 #define VDD2_OP_SEL_MASK 0x7F 232 #define VDD2_OP_SEL_MASK 0x7F
210 #define VDD2_OP_SEL_SHIFT 0 233 #define VDD2_OP_SEL_SHIFT 0
211 234
212 235
213 /*Register VDD2_SR (0x80) register.RegisterDescription */ 236 /*Register VDD2_SR (0x80) register.RegisterDescription */
214 #define VDD2_SR_SEL_MASK 0x7F 237 #define VDD2_SR_SEL_MASK 0x7F
215 #define VDD2_SR_SEL_SHIFT 0 238 #define VDD2_SR_SEL_SHIFT 0
216 239
217 240
218 /*Registers VDD1, VDD2 voltage values definitions */ 241 /*Registers VDD1, VDD2 voltage values definitions */
219 #define VDD1_2_NUM_VOLTS 73 242 #define VDD1_2_NUM_VOLTS 73
220 #define VDD1_2_MIN_VOLT 6000 243 #define VDD1_2_MIN_VOLT 6000
221 #define VDD1_2_OFFSET 125 244 #define VDD1_2_OFFSET 125
222 245
223 246
224 /*Register VDD3 (0x80) register.RegisterDescription */ 247 /*Register VDD3 (0x80) register.RegisterDescription */
225 #define VDD3_CKINEN_MASK 0x04 248 #define VDD3_CKINEN_MASK 0x04
226 #define VDD3_CKINEN_SHIFT 2 249 #define VDD3_CKINEN_SHIFT 2
227 #define VDD3_ST_MASK 0x03 250 #define VDD3_ST_MASK 0x03
228 #define VDD3_ST_SHIFT 0 251 #define VDD3_ST_SHIFT 0
229 252
230 /*Registers VDIG (0x80) to VDAC register.RegisterDescription */ 253 /*Registers VDIG (0x80) to VDAC register.RegisterDescription */
231 #define LDO_SEL_MASK 0x0C 254 #define LDO_SEL_MASK 0x0C
232 #define LDO_SEL_SHIFT 2 255 #define LDO_SEL_SHIFT 2
233 #define LDO_ST_MASK 0x03 256 #define LDO_ST_MASK 0x03
234 #define LDO_ST_SHIFT 0 257 #define LDO_ST_SHIFT 0
235 #define LDO_ST_ON_BIT 0x01 258 #define LDO_ST_ON_BIT 0x01
236 #define LDO_ST_MODE_BIT 0x02 259 #define LDO_ST_MODE_BIT 0x02
237 260
238 261
239 /*Register VDIG1 (0x80) register.RegisterDescription */ 262 /*Register VDIG1 (0x80) register.RegisterDescription */
240 #define VDIG1_SEL_MASK 0x0C 263 #define VDIG1_SEL_MASK 0x0C
241 #define VDIG1_SEL_SHIFT 2 264 #define VDIG1_SEL_SHIFT 2
242 #define VDIG1_ST_MASK 0x03 265 #define VDIG1_ST_MASK 0x03
243 #define VDIG1_ST_SHIFT 0 266 #define VDIG1_ST_SHIFT 0
244 267
245 268
246 /*Register VDIG2 (0x80) register.RegisterDescription */ 269 /*Register VDIG2 (0x80) register.RegisterDescription */
247 #define VDIG2_SEL_MASK 0x0C 270 #define VDIG2_SEL_MASK 0x0C
248 #define VDIG2_SEL_SHIFT 2 271 #define VDIG2_SEL_SHIFT 2
249 #define VDIG2_ST_MASK 0x03 272 #define VDIG2_ST_MASK 0x03
250 #define VDIG2_ST_SHIFT 0 273 #define VDIG2_ST_SHIFT 0
251 274
252 275
253 /*Register VAUX1 (0x80) register.RegisterDescription */ 276 /*Register VAUX1 (0x80) register.RegisterDescription */
254 #define VAUX1_SEL_MASK 0x0C 277 #define VAUX1_SEL_MASK 0x0C
255 #define VAUX1_SEL_SHIFT 2 278 #define VAUX1_SEL_SHIFT 2
256 #define VAUX1_ST_MASK 0x03 279 #define VAUX1_ST_MASK 0x03
257 #define VAUX1_ST_SHIFT 0 280 #define VAUX1_ST_SHIFT 0
258 281
259 282
260 /*Register VAUX2 (0x80) register.RegisterDescription */ 283 /*Register VAUX2 (0x80) register.RegisterDescription */
261 #define VAUX2_SEL_MASK 0x0C 284 #define VAUX2_SEL_MASK 0x0C
262 #define VAUX2_SEL_SHIFT 2 285 #define VAUX2_SEL_SHIFT 2
263 #define VAUX2_ST_MASK 0x03 286 #define VAUX2_ST_MASK 0x03
264 #define VAUX2_ST_SHIFT 0 287 #define VAUX2_ST_SHIFT 0
265 288
266 289
267 /*Register VAUX33 (0x80) register.RegisterDescription */ 290 /*Register VAUX33 (0x80) register.RegisterDescription */
268 #define VAUX33_SEL_MASK 0x0C 291 #define VAUX33_SEL_MASK 0x0C
269 #define VAUX33_SEL_SHIFT 2 292 #define VAUX33_SEL_SHIFT 2
270 #define VAUX33_ST_MASK 0x03 293 #define VAUX33_ST_MASK 0x03
271 #define VAUX33_ST_SHIFT 0 294 #define VAUX33_ST_SHIFT 0
272 295
273 296
274 /*Register VMMC (0x80) register.RegisterDescription */ 297 /*Register VMMC (0x80) register.RegisterDescription */
275 #define VMMC_SEL_MASK 0x0C 298 #define VMMC_SEL_MASK 0x0C
276 #define VMMC_SEL_SHIFT 2 299 #define VMMC_SEL_SHIFT 2
277 #define VMMC_ST_MASK 0x03 300 #define VMMC_ST_MASK 0x03
278 #define VMMC_ST_SHIFT 0 301 #define VMMC_ST_SHIFT 0
279 302
280 303
281 /*Register VPLL (0x80) register.RegisterDescription */ 304 /*Register VPLL (0x80) register.RegisterDescription */
282 #define VPLL_SEL_MASK 0x0C 305 #define VPLL_SEL_MASK 0x0C
283 #define VPLL_SEL_SHIFT 2 306 #define VPLL_SEL_SHIFT 2
284 #define VPLL_ST_MASK 0x03 307 #define VPLL_ST_MASK 0x03
285 #define VPLL_ST_SHIFT 0 308 #define VPLL_ST_SHIFT 0
286 309
287 310
288 /*Register VDAC (0x80) register.RegisterDescription */ 311 /*Register VDAC (0x80) register.RegisterDescription */
289 #define VDAC_SEL_MASK 0x0C 312 #define VDAC_SEL_MASK 0x0C
290 #define VDAC_SEL_SHIFT 2 313 #define VDAC_SEL_SHIFT 2
291 #define VDAC_ST_MASK 0x03 314 #define VDAC_ST_MASK 0x03
292 #define VDAC_ST_SHIFT 0 315 #define VDAC_ST_SHIFT 0
293 316
294 317
295 /*Register THERM (0x80) register.RegisterDescription */ 318 /*Register THERM (0x80) register.RegisterDescription */
296 #define THERM_THERM_HD_MASK 0x20 319 #define THERM_THERM_HD_MASK 0x20
297 #define THERM_THERM_HD_SHIFT 5 320 #define THERM_THERM_HD_SHIFT 5
298 #define THERM_THERM_TS_MASK 0x10 321 #define THERM_THERM_TS_MASK 0x10
299 #define THERM_THERM_TS_SHIFT 4 322 #define THERM_THERM_TS_SHIFT 4
300 #define THERM_THERM_HDSEL_MASK 0x0C 323 #define THERM_THERM_HDSEL_MASK 0x0C
301 #define THERM_THERM_HDSEL_SHIFT 2 324 #define THERM_THERM_HDSEL_SHIFT 2
302 #define THERM_RSVD1_MASK 0x02 325 #define THERM_RSVD1_MASK 0x02
303 #define THERM_RSVD1_SHIFT 1 326 #define THERM_RSVD1_SHIFT 1
304 #define THERM_THERM_STATE_MASK 0x01 327 #define THERM_THERM_STATE_MASK 0x01
305 #define THERM_THERM_STATE_SHIFT 0 328 #define THERM_THERM_STATE_SHIFT 0
306 329
307 330
308 /*Register BBCH (0x80) register.RegisterDescription */ 331 /*Register BBCH (0x80) register.RegisterDescription */
309 #define BBCH_BBSEL_MASK 0x06 332 #define BBCH_BBSEL_MASK 0x06
310 #define BBCH_BBSEL_SHIFT 1 333 #define BBCH_BBSEL_SHIFT 1
311 #define BBCH_BBCHEN_MASK 0x01 334 #define BBCH_BBCHEN_MASK 0x01
312 #define BBCH_BBCHEN_SHIFT 0 335 #define BBCH_BBCHEN_SHIFT 0
313 336
314 337
315 /*Register DCDCCTRL (0x80) register.RegisterDescription */ 338 /*Register DCDCCTRL (0x80) register.RegisterDescription */
316 #define DCDCCTRL_VDD2_PSKIP_MASK 0x20 339 #define DCDCCTRL_VDD2_PSKIP_MASK 0x20
317 #define DCDCCTRL_VDD2_PSKIP_SHIFT 5 340 #define DCDCCTRL_VDD2_PSKIP_SHIFT 5
318 #define DCDCCTRL_VDD1_PSKIP_MASK 0x10 341 #define DCDCCTRL_VDD1_PSKIP_MASK 0x10
319 #define DCDCCTRL_VDD1_PSKIP_SHIFT 4 342 #define DCDCCTRL_VDD1_PSKIP_SHIFT 4
320 #define DCDCCTRL_VIO_PSKIP_MASK 0x08 343 #define DCDCCTRL_VIO_PSKIP_MASK 0x08
321 #define DCDCCTRL_VIO_PSKIP_SHIFT 3 344 #define DCDCCTRL_VIO_PSKIP_SHIFT 3
322 #define DCDCCTRL_DCDCCKEXT_MASK 0x04 345 #define DCDCCTRL_DCDCCKEXT_MASK 0x04
323 #define DCDCCTRL_DCDCCKEXT_SHIFT 2 346 #define DCDCCTRL_DCDCCKEXT_SHIFT 2
324 #define DCDCCTRL_DCDCCKSYNC_MASK 0x03 347 #define DCDCCTRL_DCDCCKSYNC_MASK 0x03
325 #define DCDCCTRL_DCDCCKSYNC_SHIFT 0 348 #define DCDCCTRL_DCDCCKSYNC_SHIFT 0
326 349
327 350
328 /*Register DEVCTRL (0x80) register.RegisterDescription */ 351 /*Register DEVCTRL (0x80) register.RegisterDescription */
329 #define DEVCTRL_RTC_PWDN_MASK 0x40 352 #define DEVCTRL_RTC_PWDN_MASK 0x40
330 #define DEVCTRL_RTC_PWDN_SHIFT 6 353 #define DEVCTRL_RTC_PWDN_SHIFT 6
331 #define DEVCTRL_CK32K_CTRL_MASK 0x20 354 #define DEVCTRL_CK32K_CTRL_MASK 0x20
332 #define DEVCTRL_CK32K_CTRL_SHIFT 5 355 #define DEVCTRL_CK32K_CTRL_SHIFT 5
333 #define DEVCTRL_SR_CTL_I2C_SEL_MASK 0x10 356 #define DEVCTRL_SR_CTL_I2C_SEL_MASK 0x10
334 #define DEVCTRL_SR_CTL_I2C_SEL_SHIFT 4 357 #define DEVCTRL_SR_CTL_I2C_SEL_SHIFT 4
335 #define DEVCTRL_DEV_OFF_RST_MASK 0x08 358 #define DEVCTRL_DEV_OFF_RST_MASK 0x08
336 #define DEVCTRL_DEV_OFF_RST_SHIFT 3 359 #define DEVCTRL_DEV_OFF_RST_SHIFT 3
337 #define DEVCTRL_DEV_ON_MASK 0x04 360 #define DEVCTRL_DEV_ON_MASK 0x04
338 #define DEVCTRL_DEV_ON_SHIFT 2 361 #define DEVCTRL_DEV_ON_SHIFT 2
339 #define DEVCTRL_DEV_SLP_MASK 0x02 362 #define DEVCTRL_DEV_SLP_MASK 0x02
340 #define DEVCTRL_DEV_SLP_SHIFT 1 363 #define DEVCTRL_DEV_SLP_SHIFT 1
341 #define DEVCTRL_DEV_OFF_MASK 0x01 364 #define DEVCTRL_DEV_OFF_MASK 0x01
342 #define DEVCTRL_DEV_OFF_SHIFT 0 365 #define DEVCTRL_DEV_OFF_SHIFT 0
343 366
344 367
345 /*Register DEVCTRL2 (0x80) register.RegisterDescription */ 368 /*Register DEVCTRL2 (0x80) register.RegisterDescription */
346 #define DEVCTRL2_TSLOT_LENGTH_MASK 0x30 369 #define DEVCTRL2_TSLOT_LENGTH_MASK 0x30
347 #define DEVCTRL2_TSLOT_LENGTH_SHIFT 4 370 #define DEVCTRL2_TSLOT_LENGTH_SHIFT 4
348 #define DEVCTRL2_SLEEPSIG_POL_MASK 0x08 371 #define DEVCTRL2_SLEEPSIG_POL_MASK 0x08
349 #define DEVCTRL2_SLEEPSIG_POL_SHIFT 3 372 #define DEVCTRL2_SLEEPSIG_POL_SHIFT 3
350 #define DEVCTRL2_PWON_LP_OFF_MASK 0x04 373 #define DEVCTRL2_PWON_LP_OFF_MASK 0x04
351 #define DEVCTRL2_PWON_LP_OFF_SHIFT 2 374 #define DEVCTRL2_PWON_LP_OFF_SHIFT 2
352 #define DEVCTRL2_PWON_LP_RST_MASK 0x02 375 #define DEVCTRL2_PWON_LP_RST_MASK 0x02
353 #define DEVCTRL2_PWON_LP_RST_SHIFT 1 376 #define DEVCTRL2_PWON_LP_RST_SHIFT 1
354 #define DEVCTRL2_IT_POL_MASK 0x01 377 #define DEVCTRL2_IT_POL_MASK 0x01
355 #define DEVCTRL2_IT_POL_SHIFT 0 378 #define DEVCTRL2_IT_POL_SHIFT 0
356 379
357 380
358 /*Register SLEEP_KEEP_LDO_ON (0x80) register.RegisterDescription */ 381 /*Register SLEEP_KEEP_LDO_ON (0x80) register.RegisterDescription */
359 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK 0x80 382 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK 0x80
360 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT 7 383 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT 7
361 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK 0x40 384 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK 0x40
362 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_SHIFT 6 385 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_SHIFT 6
363 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK 0x20 386 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK 0x20
364 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_SHIFT 5 387 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_SHIFT 5
365 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK 0x10 388 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK 0x10
366 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_SHIFT 4 389 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_SHIFT 4
367 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK 0x08 390 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK 0x08
368 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_SHIFT 3 391 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_SHIFT 3
369 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK 0x04 392 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK 0x04
370 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_SHIFT 2 393 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_SHIFT 2
371 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK 0x02 394 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK 0x02
372 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_SHIFT 1 395 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_SHIFT 1
373 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK 0x01 396 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK 0x01
374 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT 0 397 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT 0
375 398
376 399
377 /*Register SLEEP_KEEP_RES_ON (0x80) register.RegisterDescription */ 400 /*Register SLEEP_KEEP_RES_ON (0x80) register.RegisterDescription */
378 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK 0x80 401 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK 0x80
379 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT 7 402 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT 7
380 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK 0x40 403 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK 0x40
381 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_SHIFT 6 404 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_SHIFT 6
382 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK 0x20 405 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK 0x20
383 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_SHIFT 5 406 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_SHIFT 5
384 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK 0x10 407 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK 0x10
385 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_SHIFT 4 408 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_SHIFT 4
386 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK 0x08 409 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK 0x08
387 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_SHIFT 3 410 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_SHIFT 3
388 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK 0x04 411 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK 0x04
389 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_SHIFT 2 412 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_SHIFT 2
390 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK 0x02 413 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK 0x02
391 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_SHIFT 1 414 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_SHIFT 1
392 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK 0x01 415 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK 0x01
393 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT 0 416 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT 0
394 417
395 418
396 /*Register SLEEP_SET_LDO_OFF (0x80) register.RegisterDescription */ 419 /*Register SLEEP_SET_LDO_OFF (0x80) register.RegisterDescription */
397 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK 0x80 420 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK 0x80
398 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT 7 421 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT 7
399 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK 0x40 422 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK 0x40
400 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_SHIFT 6 423 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_SHIFT 6
401 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK 0x20 424 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK 0x20
402 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_SHIFT 5 425 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_SHIFT 5
403 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK 0x10 426 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK 0x10
404 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_SHIFT 4 427 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_SHIFT 4
405 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK 0x08 428 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK 0x08
406 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_SHIFT 3 429 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_SHIFT 3
407 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK 0x04 430 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK 0x04
408 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_SHIFT 2 431 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_SHIFT 2
409 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK 0x02 432 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK 0x02
410 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_SHIFT 1 433 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_SHIFT 1
411 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK 0x01 434 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK 0x01
412 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT 0 435 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT 0
413 436
414 437
415 /*Register SLEEP_SET_RES_OFF (0x80) register.RegisterDescription */ 438 /*Register SLEEP_SET_RES_OFF (0x80) register.RegisterDescription */
416 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK 0x80 439 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK 0x80
417 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT 7 440 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT 7
418 #define SLEEP_SET_RES_OFF_RSVD_MASK 0x60 441 #define SLEEP_SET_RES_OFF_RSVD_MASK 0x60
419 #define SLEEP_SET_RES_OFF_RSVD_SHIFT 5 442 #define SLEEP_SET_RES_OFF_RSVD_SHIFT 5
420 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK 0x10 443 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK 0x10
421 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_SHIFT 4 444 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_SHIFT 4
422 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK 0x08 445 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK 0x08
423 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_SHIFT 3 446 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_SHIFT 3
424 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK 0x04 447 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK 0x04
425 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_SHIFT 2 448 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_SHIFT 2
426 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK 0x02 449 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK 0x02
427 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_SHIFT 1 450 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_SHIFT 1
428 #define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK 0x01 451 #define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK 0x01
429 #define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT 0 452 #define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT 0
430 453
431 454
432 /*Register EN1_LDO_ASS (0x80) register.RegisterDescription */ 455 /*Register EN1_LDO_ASS (0x80) register.RegisterDescription */
433 #define EN1_LDO_ASS_VDAC_EN1_MASK 0x80 456 #define EN1_LDO_ASS_VDAC_EN1_MASK 0x80
434 #define EN1_LDO_ASS_VDAC_EN1_SHIFT 7 457 #define EN1_LDO_ASS_VDAC_EN1_SHIFT 7
435 #define EN1_LDO_ASS_VPLL_EN1_MASK 0x40 458 #define EN1_LDO_ASS_VPLL_EN1_MASK 0x40
436 #define EN1_LDO_ASS_VPLL_EN1_SHIFT 6 459 #define EN1_LDO_ASS_VPLL_EN1_SHIFT 6
437 #define EN1_LDO_ASS_VAUX33_EN1_MASK 0x20 460 #define EN1_LDO_ASS_VAUX33_EN1_MASK 0x20
438 #define EN1_LDO_ASS_VAUX33_EN1_SHIFT 5 461 #define EN1_LDO_ASS_VAUX33_EN1_SHIFT 5
439 #define EN1_LDO_ASS_VAUX2_EN1_MASK 0x10 462 #define EN1_LDO_ASS_VAUX2_EN1_MASK 0x10
440 #define EN1_LDO_ASS_VAUX2_EN1_SHIFT 4 463 #define EN1_LDO_ASS_VAUX2_EN1_SHIFT 4
441 #define EN1_LDO_ASS_VAUX1_EN1_MASK 0x08 464 #define EN1_LDO_ASS_VAUX1_EN1_MASK 0x08
442 #define EN1_LDO_ASS_VAUX1_EN1_SHIFT 3 465 #define EN1_LDO_ASS_VAUX1_EN1_SHIFT 3
443 #define EN1_LDO_ASS_VDIG2_EN1_MASK 0x04 466 #define EN1_LDO_ASS_VDIG2_EN1_MASK 0x04
444 #define EN1_LDO_ASS_VDIG2_EN1_SHIFT 2 467 #define EN1_LDO_ASS_VDIG2_EN1_SHIFT 2
445 #define EN1_LDO_ASS_VDIG1_EN1_MASK 0x02 468 #define EN1_LDO_ASS_VDIG1_EN1_MASK 0x02
446 #define EN1_LDO_ASS_VDIG1_EN1_SHIFT 1 469 #define EN1_LDO_ASS_VDIG1_EN1_SHIFT 1
447 #define EN1_LDO_ASS_VMMC_EN1_MASK 0x01 470 #define EN1_LDO_ASS_VMMC_EN1_MASK 0x01
448 #define EN1_LDO_ASS_VMMC_EN1_SHIFT 0 471 #define EN1_LDO_ASS_VMMC_EN1_SHIFT 0
449 472
450 473
451 /*Register EN1_SMPS_ASS (0x80) register.RegisterDescription */ 474 /*Register EN1_SMPS_ASS (0x80) register.RegisterDescription */
452 #define EN1_SMPS_ASS_RSVD_MASK 0xE0 475 #define EN1_SMPS_ASS_RSVD_MASK 0xE0
453 #define EN1_SMPS_ASS_RSVD_SHIFT 5 476 #define EN1_SMPS_ASS_RSVD_SHIFT 5
454 #define EN1_SMPS_ASS_SPARE_EN1_MASK 0x10 477 #define EN1_SMPS_ASS_SPARE_EN1_MASK 0x10
455 #define EN1_SMPS_ASS_SPARE_EN1_SHIFT 4 478 #define EN1_SMPS_ASS_SPARE_EN1_SHIFT 4
456 #define EN1_SMPS_ASS_VDD3_EN1_MASK 0x08 479 #define EN1_SMPS_ASS_VDD3_EN1_MASK 0x08
457 #define EN1_SMPS_ASS_VDD3_EN1_SHIFT 3 480 #define EN1_SMPS_ASS_VDD3_EN1_SHIFT 3
458 #define EN1_SMPS_ASS_VDD2_EN1_MASK 0x04 481 #define EN1_SMPS_ASS_VDD2_EN1_MASK 0x04
459 #define EN1_SMPS_ASS_VDD2_EN1_SHIFT 2 482 #define EN1_SMPS_ASS_VDD2_EN1_SHIFT 2
460 #define EN1_SMPS_ASS_VDD1_EN1_MASK 0x02 483 #define EN1_SMPS_ASS_VDD1_EN1_MASK 0x02
461 #define EN1_SMPS_ASS_VDD1_EN1_SHIFT 1 484 #define EN1_SMPS_ASS_VDD1_EN1_SHIFT 1
462 #define EN1_SMPS_ASS_VIO_EN1_MASK 0x01 485 #define EN1_SMPS_ASS_VIO_EN1_MASK 0x01
463 #define EN1_SMPS_ASS_VIO_EN1_SHIFT 0 486 #define EN1_SMPS_ASS_VIO_EN1_SHIFT 0
464 487
465 488
466 /*Register EN2_LDO_ASS (0x80) register.RegisterDescription */ 489 /*Register EN2_LDO_ASS (0x80) register.RegisterDescription */
467 #define EN2_LDO_ASS_VDAC_EN2_MASK 0x80 490 #define EN2_LDO_ASS_VDAC_EN2_MASK 0x80
468 #define EN2_LDO_ASS_VDAC_EN2_SHIFT 7 491 #define EN2_LDO_ASS_VDAC_EN2_SHIFT 7
469 #define EN2_LDO_ASS_VPLL_EN2_MASK 0x40 492 #define EN2_LDO_ASS_VPLL_EN2_MASK 0x40
470 #define EN2_LDO_ASS_VPLL_EN2_SHIFT 6 493 #define EN2_LDO_ASS_VPLL_EN2_SHIFT 6
471 #define EN2_LDO_ASS_VAUX33_EN2_MASK 0x20 494 #define EN2_LDO_ASS_VAUX33_EN2_MASK 0x20
472 #define EN2_LDO_ASS_VAUX33_EN2_SHIFT 5 495 #define EN2_LDO_ASS_VAUX33_EN2_SHIFT 5
473 #define EN2_LDO_ASS_VAUX2_EN2_MASK 0x10 496 #define EN2_LDO_ASS_VAUX2_EN2_MASK 0x10
474 #define EN2_LDO_ASS_VAUX2_EN2_SHIFT 4 497 #define EN2_LDO_ASS_VAUX2_EN2_SHIFT 4
475 #define EN2_LDO_ASS_VAUX1_EN2_MASK 0x08 498 #define EN2_LDO_ASS_VAUX1_EN2_MASK 0x08
476 #define EN2_LDO_ASS_VAUX1_EN2_SHIFT 3 499 #define EN2_LDO_ASS_VAUX1_EN2_SHIFT 3
477 #define EN2_LDO_ASS_VDIG2_EN2_MASK 0x04 500 #define EN2_LDO_ASS_VDIG2_EN2_MASK 0x04
478 #define EN2_LDO_ASS_VDIG2_EN2_SHIFT 2 501 #define EN2_LDO_ASS_VDIG2_EN2_SHIFT 2
479 #define EN2_LDO_ASS_VDIG1_EN2_MASK 0x02 502 #define EN2_LDO_ASS_VDIG1_EN2_MASK 0x02
480 #define EN2_LDO_ASS_VDIG1_EN2_SHIFT 1 503 #define EN2_LDO_ASS_VDIG1_EN2_SHIFT 1
481 #define EN2_LDO_ASS_VMMC_EN2_MASK 0x01 504 #define EN2_LDO_ASS_VMMC_EN2_MASK 0x01
482 #define EN2_LDO_ASS_VMMC_EN2_SHIFT 0 505 #define EN2_LDO_ASS_VMMC_EN2_SHIFT 0
483 506
484 507
485 /*Register EN2_SMPS_ASS (0x80) register.RegisterDescription */ 508 /*Register EN2_SMPS_ASS (0x80) register.RegisterDescription */
486 #define EN2_SMPS_ASS_RSVD_MASK 0xE0 509 #define EN2_SMPS_ASS_RSVD_MASK 0xE0
487 #define EN2_SMPS_ASS_RSVD_SHIFT 5 510 #define EN2_SMPS_ASS_RSVD_SHIFT 5
488 #define EN2_SMPS_ASS_SPARE_EN2_MASK 0x10 511 #define EN2_SMPS_ASS_SPARE_EN2_MASK 0x10
489 #define EN2_SMPS_ASS_SPARE_EN2_SHIFT 4 512 #define EN2_SMPS_ASS_SPARE_EN2_SHIFT 4
490 #define EN2_SMPS_ASS_VDD3_EN2_MASK 0x08 513 #define EN2_SMPS_ASS_VDD3_EN2_MASK 0x08
491 #define EN2_SMPS_ASS_VDD3_EN2_SHIFT 3 514 #define EN2_SMPS_ASS_VDD3_EN2_SHIFT 3
492 #define EN2_SMPS_ASS_VDD2_EN2_MASK 0x04 515 #define EN2_SMPS_ASS_VDD2_EN2_MASK 0x04
493 #define EN2_SMPS_ASS_VDD2_EN2_SHIFT 2 516 #define EN2_SMPS_ASS_VDD2_EN2_SHIFT 2
494 #define EN2_SMPS_ASS_VDD1_EN2_MASK 0x02 517 #define EN2_SMPS_ASS_VDD1_EN2_MASK 0x02
495 #define EN2_SMPS_ASS_VDD1_EN2_SHIFT 1 518 #define EN2_SMPS_ASS_VDD1_EN2_SHIFT 1
496 #define EN2_SMPS_ASS_VIO_EN2_MASK 0x01 519 #define EN2_SMPS_ASS_VIO_EN2_MASK 0x01
497 #define EN2_SMPS_ASS_VIO_EN2_SHIFT 0 520 #define EN2_SMPS_ASS_VIO_EN2_SHIFT 0
498 521
499 522
500 /*Register EN3_LDO_ASS (0x80) register.RegisterDescription */ 523 /*Register EN3_LDO_ASS (0x80) register.RegisterDescription */
501 #define EN3_LDO_ASS_VDAC_EN3_MASK 0x80 524 #define EN3_LDO_ASS_VDAC_EN3_MASK 0x80
502 #define EN3_LDO_ASS_VDAC_EN3_SHIFT 7 525 #define EN3_LDO_ASS_VDAC_EN3_SHIFT 7
503 #define EN3_LDO_ASS_VPLL_EN3_MASK 0x40 526 #define EN3_LDO_ASS_VPLL_EN3_MASK 0x40
504 #define EN3_LDO_ASS_VPLL_EN3_SHIFT 6 527 #define EN3_LDO_ASS_VPLL_EN3_SHIFT 6
505 #define EN3_LDO_ASS_VAUX33_EN3_MASK 0x20 528 #define EN3_LDO_ASS_VAUX33_EN3_MASK 0x20
506 #define EN3_LDO_ASS_VAUX33_EN3_SHIFT 5 529 #define EN3_LDO_ASS_VAUX33_EN3_SHIFT 5
507 #define EN3_LDO_ASS_VAUX2_EN3_MASK 0x10 530 #define EN3_LDO_ASS_VAUX2_EN3_MASK 0x10
508 #define EN3_LDO_ASS_VAUX2_EN3_SHIFT 4 531 #define EN3_LDO_ASS_VAUX2_EN3_SHIFT 4
509 #define EN3_LDO_ASS_VAUX1_EN3_MASK 0x08 532 #define EN3_LDO_ASS_VAUX1_EN3_MASK 0x08
510 #define EN3_LDO_ASS_VAUX1_EN3_SHIFT 3 533 #define EN3_LDO_ASS_VAUX1_EN3_SHIFT 3
511 #define EN3_LDO_ASS_VDIG2_EN3_MASK 0x04 534 #define EN3_LDO_ASS_VDIG2_EN3_MASK 0x04
512 #define EN3_LDO_ASS_VDIG2_EN3_SHIFT 2 535 #define EN3_LDO_ASS_VDIG2_EN3_SHIFT 2
513 #define EN3_LDO_ASS_VDIG1_EN3_MASK 0x02 536 #define EN3_LDO_ASS_VDIG1_EN3_MASK 0x02
514 #define EN3_LDO_ASS_VDIG1_EN3_SHIFT 1 537 #define EN3_LDO_ASS_VDIG1_EN3_SHIFT 1
515 #define EN3_LDO_ASS_VMMC_EN3_MASK 0x01 538 #define EN3_LDO_ASS_VMMC_EN3_MASK 0x01
516 #define EN3_LDO_ASS_VMMC_EN3_SHIFT 0 539 #define EN3_LDO_ASS_VMMC_EN3_SHIFT 0
517 540
518 541
519 /*Register SPARE (0x80) register.RegisterDescription */ 542 /*Register SPARE (0x80) register.RegisterDescription */
520 #define SPARE_SPARE_MASK 0xFF 543 #define SPARE_SPARE_MASK 0xFF
521 #define SPARE_SPARE_SHIFT 0 544 #define SPARE_SPARE_SHIFT 0
522 545
523 546
524 /*Register INT_STS (0x80) register.RegisterDescription */ 547 /*Register INT_STS (0x80) register.RegisterDescription */
525 #define INT_STS_RTC_PERIOD_IT_MASK 0x80 548 #define INT_STS_RTC_PERIOD_IT_MASK 0x80
526 #define INT_STS_RTC_PERIOD_IT_SHIFT 7 549 #define INT_STS_RTC_PERIOD_IT_SHIFT 7
527 #define INT_STS_RTC_ALARM_IT_MASK 0x40 550 #define INT_STS_RTC_ALARM_IT_MASK 0x40
528 #define INT_STS_RTC_ALARM_IT_SHIFT 6 551 #define INT_STS_RTC_ALARM_IT_SHIFT 6
529 #define INT_STS_HOTDIE_IT_MASK 0x20 552 #define INT_STS_HOTDIE_IT_MASK 0x20
530 #define INT_STS_HOTDIE_IT_SHIFT 5 553 #define INT_STS_HOTDIE_IT_SHIFT 5
531 #define INT_STS_PWRHOLD_IT_MASK 0x10 554 #define INT_STS_PWRHOLD_IT_MASK 0x10
532 #define INT_STS_PWRHOLD_IT_SHIFT 4 555 #define INT_STS_PWRHOLD_IT_SHIFT 4
533 #define INT_STS_PWRON_LP_IT_MASK 0x08 556 #define INT_STS_PWRON_LP_IT_MASK 0x08
534 #define INT_STS_PWRON_LP_IT_SHIFT 3 557 #define INT_STS_PWRON_LP_IT_SHIFT 3
535 #define INT_STS_PWRON_IT_MASK 0x04 558 #define INT_STS_PWRON_IT_MASK 0x04
536 #define INT_STS_PWRON_IT_SHIFT 2 559 #define INT_STS_PWRON_IT_SHIFT 2
537 #define INT_STS_VMBHI_IT_MASK 0x02 560 #define INT_STS_VMBHI_IT_MASK 0x02
538 #define INT_STS_VMBHI_IT_SHIFT 1 561 #define INT_STS_VMBHI_IT_SHIFT 1
539 #define INT_STS_VMBDCH_IT_MASK 0x01 562 #define INT_STS_VMBDCH_IT_MASK 0x01
540 #define INT_STS_VMBDCH_IT_SHIFT 0 563 #define INT_STS_VMBDCH_IT_SHIFT 0
541 564
542 565
543 /*Register INT_MSK (0x80) register.RegisterDescription */ 566 /*Register INT_MSK (0x80) register.RegisterDescription */
544 #define INT_MSK_RTC_PERIOD_IT_MSK_MASK 0x80 567 #define INT_MSK_RTC_PERIOD_IT_MSK_MASK 0x80
545 #define INT_MSK_RTC_PERIOD_IT_MSK_SHIFT 7 568 #define INT_MSK_RTC_PERIOD_IT_MSK_SHIFT 7
546 #define INT_MSK_RTC_ALARM_IT_MSK_MASK 0x40 569 #define INT_MSK_RTC_ALARM_IT_MSK_MASK 0x40
547 #define INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6 570 #define INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6
548 #define INT_MSK_HOTDIE_IT_MSK_MASK 0x20 571 #define INT_MSK_HOTDIE_IT_MSK_MASK 0x20
549 #define INT_MSK_HOTDIE_IT_MSK_SHIFT 5 572 #define INT_MSK_HOTDIE_IT_MSK_SHIFT 5
550 #define INT_MSK_PWRHOLD_IT_MSK_MASK 0x10 573 #define INT_MSK_PWRHOLD_IT_MSK_MASK 0x10
551 #define INT_MSK_PWRHOLD_IT_MSK_SHIFT 4 574 #define INT_MSK_PWRHOLD_IT_MSK_SHIFT 4
552 #define INT_MSK_PWRON_LP_IT_MSK_MASK 0x08 575 #define INT_MSK_PWRON_LP_IT_MSK_MASK 0x08
553 #define INT_MSK_PWRON_LP_IT_MSK_SHIFT 3 576 #define INT_MSK_PWRON_LP_IT_MSK_SHIFT 3
554 #define INT_MSK_PWRON_IT_MSK_MASK 0x04 577 #define INT_MSK_PWRON_IT_MSK_MASK 0x04
555 #define INT_MSK_PWRON_IT_MSK_SHIFT 2 578 #define INT_MSK_PWRON_IT_MSK_SHIFT 2
556 #define INT_MSK_VMBHI_IT_MSK_MASK 0x02 579 #define INT_MSK_VMBHI_IT_MSK_MASK 0x02
557 #define INT_MSK_VMBHI_IT_MSK_SHIFT 1 580 #define INT_MSK_VMBHI_IT_MSK_SHIFT 1
558 #define INT_MSK_VMBDCH_IT_MSK_MASK 0x01 581 #define INT_MSK_VMBDCH_IT_MSK_MASK 0x01
559 #define INT_MSK_VMBDCH_IT_MSK_SHIFT 0 582 #define INT_MSK_VMBDCH_IT_MSK_SHIFT 0
560 583
561 584
562 /*Register INT_STS2 (0x80) register.RegisterDescription */ 585 /*Register INT_STS2 (0x80) register.RegisterDescription */
563 #define INT_STS2_GPIO3_F_IT_MASK 0x80 586 #define INT_STS2_GPIO3_F_IT_MASK 0x80
564 #define INT_STS2_GPIO3_F_IT_SHIFT 7 587 #define INT_STS2_GPIO3_F_IT_SHIFT 7
565 #define INT_STS2_GPIO3_R_IT_MASK 0x40 588 #define INT_STS2_GPIO3_R_IT_MASK 0x40
566 #define INT_STS2_GPIO3_R_IT_SHIFT 6 589 #define INT_STS2_GPIO3_R_IT_SHIFT 6
567 #define INT_STS2_GPIO2_F_IT_MASK 0x20 590 #define INT_STS2_GPIO2_F_IT_MASK 0x20
568 #define INT_STS2_GPIO2_F_IT_SHIFT 5 591 #define INT_STS2_GPIO2_F_IT_SHIFT 5
569 #define INT_STS2_GPIO2_R_IT_MASK 0x10 592 #define INT_STS2_GPIO2_R_IT_MASK 0x10
570 #define INT_STS2_GPIO2_R_IT_SHIFT 4 593 #define INT_STS2_GPIO2_R_IT_SHIFT 4
571 #define INT_STS2_GPIO1_F_IT_MASK 0x08 594 #define INT_STS2_GPIO1_F_IT_MASK 0x08
572 #define INT_STS2_GPIO1_F_IT_SHIFT 3 595 #define INT_STS2_GPIO1_F_IT_SHIFT 3
573 #define INT_STS2_GPIO1_R_IT_MASK 0x04 596 #define INT_STS2_GPIO1_R_IT_MASK 0x04
574 #define INT_STS2_GPIO1_R_IT_SHIFT 2 597 #define INT_STS2_GPIO1_R_IT_SHIFT 2
575 #define INT_STS2_GPIO0_F_IT_MASK 0x02 598 #define INT_STS2_GPIO0_F_IT_MASK 0x02
576 #define INT_STS2_GPIO0_F_IT_SHIFT 1 599 #define INT_STS2_GPIO0_F_IT_SHIFT 1
577 #define INT_STS2_GPIO0_R_IT_MASK 0x01 600 #define INT_STS2_GPIO0_R_IT_MASK 0x01
578 #define INT_STS2_GPIO0_R_IT_SHIFT 0 601 #define INT_STS2_GPIO0_R_IT_SHIFT 0
579 602
580 603
581 /*Register INT_MSK2 (0x80) register.RegisterDescription */ 604 /*Register INT_MSK2 (0x80) register.RegisterDescription */
582 #define INT_MSK2_GPIO3_F_IT_MSK_MASK 0x80 605 #define INT_MSK2_GPIO3_F_IT_MSK_MASK 0x80
583 #define INT_MSK2_GPIO3_F_IT_MSK_SHIFT 7 606 #define INT_MSK2_GPIO3_F_IT_MSK_SHIFT 7
584 #define INT_MSK2_GPIO3_R_IT_MSK_MASK 0x40 607 #define INT_MSK2_GPIO3_R_IT_MSK_MASK 0x40
585 #define INT_MSK2_GPIO3_R_IT_MSK_SHIFT 6 608 #define INT_MSK2_GPIO3_R_IT_MSK_SHIFT 6
586 #define INT_MSK2_GPIO2_F_IT_MSK_MASK 0x20 609 #define INT_MSK2_GPIO2_F_IT_MSK_MASK 0x20
587 #define INT_MSK2_GPIO2_F_IT_MSK_SHIFT 5 610 #define INT_MSK2_GPIO2_F_IT_MSK_SHIFT 5
588 #define INT_MSK2_GPIO2_R_IT_MSK_MASK 0x10 611 #define INT_MSK2_GPIO2_R_IT_MSK_MASK 0x10
589 #define INT_MSK2_GPIO2_R_IT_MSK_SHIFT 4 612 #define INT_MSK2_GPIO2_R_IT_MSK_SHIFT 4
590 #define INT_MSK2_GPIO1_F_IT_MSK_MASK 0x08 613 #define INT_MSK2_GPIO1_F_IT_MSK_MASK 0x08
591 #define INT_MSK2_GPIO1_F_IT_MSK_SHIFT 3 614 #define INT_MSK2_GPIO1_F_IT_MSK_SHIFT 3
592 #define INT_MSK2_GPIO1_R_IT_MSK_MASK 0x04 615 #define INT_MSK2_GPIO1_R_IT_MSK_MASK 0x04
593 #define INT_MSK2_GPIO1_R_IT_MSK_SHIFT 2 616 #define INT_MSK2_GPIO1_R_IT_MSK_SHIFT 2
594 #define INT_MSK2_GPIO0_F_IT_MSK_MASK 0x02 617 #define INT_MSK2_GPIO0_F_IT_MSK_MASK 0x02
595 #define INT_MSK2_GPIO0_F_IT_MSK_SHIFT 1 618 #define INT_MSK2_GPIO0_F_IT_MSK_SHIFT 1
596 #define INT_MSK2_GPIO0_R_IT_MSK_MASK 0x01 619 #define INT_MSK2_GPIO0_R_IT_MSK_MASK 0x01
597 #define INT_MSK2_GPIO0_R_IT_MSK_SHIFT 0 620 #define INT_MSK2_GPIO0_R_IT_MSK_SHIFT 0
598 621
599 622
600 /*Register INT_STS3 (0x80) register.RegisterDescription */ 623 /*Register INT_STS3 (0x80) register.RegisterDescription */
601 #define INT_STS3_GPIO5_F_IT_MASK 0x08 624 #define INT_STS3_GPIO5_F_IT_MASK 0x08
602 #define INT_STS3_GPIO5_F_IT_SHIFT 3 625 #define INT_STS3_GPIO5_F_IT_SHIFT 3
603 #define INT_STS3_GPIO5_R_IT_MASK 0x04 626 #define INT_STS3_GPIO5_R_IT_MASK 0x04
604 #define INT_STS3_GPIO5_R_IT_SHIFT 2 627 #define INT_STS3_GPIO5_R_IT_SHIFT 2
605 #define INT_STS3_GPIO4_F_IT_MASK 0x02 628 #define INT_STS3_GPIO4_F_IT_MASK 0x02
606 #define INT_STS3_GPIO4_F_IT_SHIFT 1 629 #define INT_STS3_GPIO4_F_IT_SHIFT 1
607 #define INT_STS3_GPIO4_R_IT_MASK 0x01 630 #define INT_STS3_GPIO4_R_IT_MASK 0x01
608 #define INT_STS3_GPIO4_R_IT_SHIFT 0 631 #define INT_STS3_GPIO4_R_IT_SHIFT 0
609 632
610 633
611 /*Register INT_MSK3 (0x80) register.RegisterDescription */ 634 /*Register INT_MSK3 (0x80) register.RegisterDescription */
612 #define INT_MSK3_GPIO5_F_IT_MSK_MASK 0x08 635 #define INT_MSK3_GPIO5_F_IT_MSK_MASK 0x08
613 #define INT_MSK3_GPIO5_F_IT_MSK_SHIFT 3 636 #define INT_MSK3_GPIO5_F_IT_MSK_SHIFT 3
614 #define INT_MSK3_GPIO5_R_IT_MSK_MASK 0x04 637 #define INT_MSK3_GPIO5_R_IT_MSK_MASK 0x04
615 #define INT_MSK3_GPIO5_R_IT_MSK_SHIFT 2 638 #define INT_MSK3_GPIO5_R_IT_MSK_SHIFT 2
616 #define INT_MSK3_GPIO4_F_IT_MSK_MASK 0x02 639 #define INT_MSK3_GPIO4_F_IT_MSK_MASK 0x02
617 #define INT_MSK3_GPIO4_F_IT_MSK_SHIFT 1 640 #define INT_MSK3_GPIO4_F_IT_MSK_SHIFT 1
618 #define INT_MSK3_GPIO4_R_IT_MSK_MASK 0x01 641 #define INT_MSK3_GPIO4_R_IT_MSK_MASK 0x01
619 #define INT_MSK3_GPIO4_R_IT_MSK_SHIFT 0 642 #define INT_MSK3_GPIO4_R_IT_MSK_SHIFT 0
620 643
621 644
622 /*Register GPIO0 (0x80) register.RegisterDescription */ 645 /*Register GPIO0 (0x80) register.RegisterDescription */
623 #define GPIO0_GPIO_DEB_MASK 0x10 646 #define GPIO0_GPIO_DEB_MASK 0x10
624 #define GPIO0_GPIO_DEB_SHIFT 4 647 #define GPIO0_GPIO_DEB_SHIFT 4
625 #define GPIO0_GPIO_PUEN_MASK 0x08 648 #define GPIO0_GPIO_PUEN_MASK 0x08
626 #define GPIO0_GPIO_PUEN_SHIFT 3 649 #define GPIO0_GPIO_PUEN_SHIFT 3
627 #define GPIO0_GPIO_CFG_MASK 0x04 650 #define GPIO0_GPIO_CFG_MASK 0x04
628 #define GPIO0_GPIO_CFG_SHIFT 2 651 #define GPIO0_GPIO_CFG_SHIFT 2
629 #define GPIO0_GPIO_STS_MASK 0x02 652 #define GPIO0_GPIO_STS_MASK 0x02
630 #define GPIO0_GPIO_STS_SHIFT 1 653 #define GPIO0_GPIO_STS_SHIFT 1
631 #define GPIO0_GPIO_SET_MASK 0x01 654 #define GPIO0_GPIO_SET_MASK 0x01
632 #define GPIO0_GPIO_SET_SHIFT 0 655 #define GPIO0_GPIO_SET_SHIFT 0
633 656
634 657
635 /*Register GPIO1 (0x80) register.RegisterDescription */ 658 /*Register GPIO1 (0x80) register.RegisterDescription */
636 #define GPIO1_GPIO_DEB_MASK 0x10 659 #define GPIO1_GPIO_DEB_MASK 0x10
637 #define GPIO1_GPIO_DEB_SHIFT 4 660 #define GPIO1_GPIO_DEB_SHIFT 4
638 #define GPIO1_GPIO_PUEN_MASK 0x08 661 #define GPIO1_GPIO_PUEN_MASK 0x08
639 #define GPIO1_GPIO_PUEN_SHIFT 3 662 #define GPIO1_GPIO_PUEN_SHIFT 3
640 #define GPIO1_GPIO_CFG_MASK 0x04 663 #define GPIO1_GPIO_CFG_MASK 0x04
641 #define GPIO1_GPIO_CFG_SHIFT 2 664 #define GPIO1_GPIO_CFG_SHIFT 2
642 #define GPIO1_GPIO_STS_MASK 0x02 665 #define GPIO1_GPIO_STS_MASK 0x02
643 #define GPIO1_GPIO_STS_SHIFT 1 666 #define GPIO1_GPIO_STS_SHIFT 1
644 #define GPIO1_GPIO_SET_MASK 0x01 667 #define GPIO1_GPIO_SET_MASK 0x01
645 #define GPIO1_GPIO_SET_SHIFT 0 668 #define GPIO1_GPIO_SET_SHIFT 0
646 669
647 670
648 /*Register GPIO2 (0x80) register.RegisterDescription */ 671 /*Register GPIO2 (0x80) register.RegisterDescription */
649 #define GPIO2_GPIO_DEB_MASK 0x10 672 #define GPIO2_GPIO_DEB_MASK 0x10
650 #define GPIO2_GPIO_DEB_SHIFT 4 673 #define GPIO2_GPIO_DEB_SHIFT 4
651 #define GPIO2_GPIO_PUEN_MASK 0x08 674 #define GPIO2_GPIO_PUEN_MASK 0x08
652 #define GPIO2_GPIO_PUEN_SHIFT 3 675 #define GPIO2_GPIO_PUEN_SHIFT 3
653 #define GPIO2_GPIO_CFG_MASK 0x04 676 #define GPIO2_GPIO_CFG_MASK 0x04
654 #define GPIO2_GPIO_CFG_SHIFT 2 677 #define GPIO2_GPIO_CFG_SHIFT 2
655 #define GPIO2_GPIO_STS_MASK 0x02 678 #define GPIO2_GPIO_STS_MASK 0x02
656 #define GPIO2_GPIO_STS_SHIFT 1 679 #define GPIO2_GPIO_STS_SHIFT 1
657 #define GPIO2_GPIO_SET_MASK 0x01 680 #define GPIO2_GPIO_SET_MASK 0x01
658 #define GPIO2_GPIO_SET_SHIFT 0 681 #define GPIO2_GPIO_SET_SHIFT 0
659 682
660 683
661 /*Register GPIO3 (0x80) register.RegisterDescription */ 684 /*Register GPIO3 (0x80) register.RegisterDescription */
662 #define GPIO3_GPIO_DEB_MASK 0x10 685 #define GPIO3_GPIO_DEB_MASK 0x10
663 #define GPIO3_GPIO_DEB_SHIFT 4 686 #define GPIO3_GPIO_DEB_SHIFT 4
664 #define GPIO3_GPIO_PUEN_MASK 0x08 687 #define GPIO3_GPIO_PUEN_MASK 0x08
665 #define GPIO3_GPIO_PUEN_SHIFT 3 688 #define GPIO3_GPIO_PUEN_SHIFT 3
666 #define GPIO3_GPIO_CFG_MASK 0x04 689 #define GPIO3_GPIO_CFG_MASK 0x04
667 #define GPIO3_GPIO_CFG_SHIFT 2 690 #define GPIO3_GPIO_CFG_SHIFT 2
668 #define GPIO3_GPIO_STS_MASK 0x02 691 #define GPIO3_GPIO_STS_MASK 0x02
669 #define GPIO3_GPIO_STS_SHIFT 1 692 #define GPIO3_GPIO_STS_SHIFT 1
670 #define GPIO3_GPIO_SET_MASK 0x01 693 #define GPIO3_GPIO_SET_MASK 0x01
671 #define GPIO3_GPIO_SET_SHIFT 0 694 #define GPIO3_GPIO_SET_SHIFT 0
672 695
673 696
674 /*Register GPIO4 (0x80) register.RegisterDescription */ 697 /*Register GPIO4 (0x80) register.RegisterDescription */
675 #define GPIO4_GPIO_DEB_MASK 0x10 698 #define GPIO4_GPIO_DEB_MASK 0x10
676 #define GPIO4_GPIO_DEB_SHIFT 4 699 #define GPIO4_GPIO_DEB_SHIFT 4
677 #define GPIO4_GPIO_PUEN_MASK 0x08 700 #define GPIO4_GPIO_PUEN_MASK 0x08
678 #define GPIO4_GPIO_PUEN_SHIFT 3 701 #define GPIO4_GPIO_PUEN_SHIFT 3
679 #define GPIO4_GPIO_CFG_MASK 0x04 702 #define GPIO4_GPIO_CFG_MASK 0x04
680 #define GPIO4_GPIO_CFG_SHIFT 2 703 #define GPIO4_GPIO_CFG_SHIFT 2
681 #define GPIO4_GPIO_STS_MASK 0x02 704 #define GPIO4_GPIO_STS_MASK 0x02
682 #define GPIO4_GPIO_STS_SHIFT 1 705 #define GPIO4_GPIO_STS_SHIFT 1
683 #define GPIO4_GPIO_SET_MASK 0x01 706 #define GPIO4_GPIO_SET_MASK 0x01
684 #define GPIO4_GPIO_SET_SHIFT 0 707 #define GPIO4_GPIO_SET_SHIFT 0
685 708
686 709
687 /*Register GPIO5 (0x80) register.RegisterDescription */ 710 /*Register GPIO5 (0x80) register.RegisterDescription */
688 #define GPIO5_GPIO_DEB_MASK 0x10 711 #define GPIO5_GPIO_DEB_MASK 0x10
689 #define GPIO5_GPIO_DEB_SHIFT 4 712 #define GPIO5_GPIO_DEB_SHIFT 4
690 #define GPIO5_GPIO_PUEN_MASK 0x08 713 #define GPIO5_GPIO_PUEN_MASK 0x08
691 #define GPIO5_GPIO_PUEN_SHIFT 3 714 #define GPIO5_GPIO_PUEN_SHIFT 3
692 #define GPIO5_GPIO_CFG_MASK 0x04 715 #define GPIO5_GPIO_CFG_MASK 0x04
693 #define GPIO5_GPIO_CFG_SHIFT 2 716 #define GPIO5_GPIO_CFG_SHIFT 2
694 #define GPIO5_GPIO_STS_MASK 0x02 717 #define GPIO5_GPIO_STS_MASK 0x02
695 #define GPIO5_GPIO_STS_SHIFT 1 718 #define GPIO5_GPIO_STS_SHIFT 1
696 #define GPIO5_GPIO_SET_MASK 0x01 719 #define GPIO5_GPIO_SET_MASK 0x01
697 #define GPIO5_GPIO_SET_SHIFT 0 720 #define GPIO5_GPIO_SET_SHIFT 0
698 721
699 722
700 /*Register JTAGVERNUM (0x80) register.RegisterDescription */ 723 /*Register JTAGVERNUM (0x80) register.RegisterDescription */
701 #define JTAGVERNUM_VERNUM_MASK 0x0F 724 #define JTAGVERNUM_VERNUM_MASK 0x0F
702 #define JTAGVERNUM_VERNUM_SHIFT 0 725 #define JTAGVERNUM_VERNUM_SHIFT 0
703 726
704 727
728 /* Register VDDCTRL (0x27) bit definitions */
729 #define VDDCTRL_ST_MASK 0x03
730 #define VDDCTRL_ST_SHIFT 0
731
732
733 /*Register VDDCTRL_OP (0x28) bit definitios */
734 #define VDDCTRL_OP_CMD_MASK 0x80
735 #define VDDCTRL_OP_CMD_SHIFT 7
736 #define VDDCTRL_OP_SEL_MASK 0x7F
737 #define VDDCTRL_OP_SEL_SHIFT 0
738
739
740 /*Register VDDCTRL_SR (0x29) bit definitions */
741 #define VDDCTRL_SR_SEL_MASK 0x7F
742 #define VDDCTRL_SR_SEL_SHIFT 0
743
744
705 /* IRQ Definitions */ 745 /* IRQ Definitions */
706 #define TPS65910_IRQ_VBAT_VMBDCH 0 746 #define TPS65910_IRQ_VBAT_VMBDCH 0
707 #define TPS65910_IRQ_VBAT_VMHI 1 747 #define TPS65910_IRQ_VBAT_VMHI 1
708 #define TPS65910_IRQ_PWRON 2 748 #define TPS65910_IRQ_PWRON 2
709 #define TPS65910_IRQ_PWRON_LP 3 749 #define TPS65910_IRQ_PWRON_LP 3
710 #define TPS65910_IRQ_PWRHOLD 4 750 #define TPS65910_IRQ_PWRHOLD 4
711 #define TPS65910_IRQ_HOTDIE 5 751 #define TPS65910_IRQ_HOTDIE 5
712 #define TPS65910_IRQ_RTC_ALARM 6 752 #define TPS65910_IRQ_RTC_ALARM 6
713 #define TPS65910_IRQ_RTC_PERIOD 7 753 #define TPS65910_IRQ_RTC_PERIOD 7
714 #define TPS65910_IRQ_GPIO_R 8 754 #define TPS65910_IRQ_GPIO_R 8
715 #define TPS65910_IRQ_GPIO_F 9 755 #define TPS65910_IRQ_GPIO_F 9
716 #define TPS65910_NUM_IRQ 10 756 #define TPS65910_NUM_IRQ 10
717 757
718 /* GPIO Register Definitions */ 758 /* GPIO Register Definitions */
719 #define TPS65910_GPIO_DEB BIT(2) 759 #define TPS65910_GPIO_DEB BIT(2)
720 #define TPS65910_GPIO_PUEN BIT(3) 760 #define TPS65910_GPIO_PUEN BIT(3)
721 #define TPS65910_GPIO_CFG BIT(2) 761 #define TPS65910_GPIO_CFG BIT(2)
722 #define TPS65910_GPIO_STS BIT(1) 762 #define TPS65910_GPIO_STS BIT(1)
723 #define TPS65910_GPIO_SET BIT(0) 763 #define TPS65910_GPIO_SET BIT(0)
724 764
725 /** 765 /**
726 * struct tps65910_board 766 * struct tps65910_board
727 * Board platform data may be used to initialize regulators. 767 * Board platform data may be used to initialize regulators.
728 */ 768 */
729 769
730 struct tps65910_board { 770 struct tps65910_board {
731 int gpio_base; 771 int gpio_base;
732 int irq; 772 int irq;
733 int irq_base; 773 int irq_base;
734 struct regulator_init_data *tps65910_pmic_init_data; 774 struct regulator_init_data *tps65910_pmic_init_data;
735 }; 775 };
736 776
737 /** 777 /**
738 * struct tps65910 - tps65910 sub-driver chip access routines 778 * struct tps65910 - tps65910 sub-driver chip access routines
739 */ 779 */
740 780
741 struct tps65910 { 781 struct tps65910 {
742 struct device *dev; 782 struct device *dev;
743 struct i2c_client *i2c_client; 783 struct i2c_client *i2c_client;
744 struct mutex io_mutex; 784 struct mutex io_mutex;
785 unsigned int id;
745 int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest); 786 int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest);
746 int (*write)(struct tps65910 *tps65910, u8 reg, int size, void *src); 787 int (*write)(struct tps65910 *tps65910, u8 reg, int size, void *src);
747 788
748 /* Client devices */ 789 /* Client devices */
749 struct tps65910_pmic *pmic; 790 struct tps65910_pmic *pmic;
750 struct tps65910_rtc *rtc; 791 struct tps65910_rtc *rtc;
751 struct tps65910_power *power; 792 struct tps65910_power *power;
752 793
753 /* GPIO Handling */ 794 /* GPIO Handling */
754 struct gpio_chip gpio; 795 struct gpio_chip gpio;
755 796
756 /* IRQ Handling */ 797 /* IRQ Handling */
757 struct mutex irq_lock; 798 struct mutex irq_lock;
758 int chip_irq; 799 int chip_irq;
759 int irq_base; 800 int irq_base;
760 u16 irq_mask; 801 u16 irq_mask;
761 }; 802 };
762 803
763 struct tps65910_platform_data { 804 struct tps65910_platform_data {
764 int irq; 805 int irq;
765 int irq_base; 806 int irq_base;
766 }; 807 };
767 808
768 int tps65910_set_bits(struct tps65910 *tps65910, u8 reg, u8 mask); 809 int tps65910_set_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
769 int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask); 810 int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
770 void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base); 811 void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base);
771 int tps65910_irq_init(struct tps65910 *tps65910, int irq, 812 int tps65910_irq_init(struct tps65910 *tps65910, int irq,
772 struct tps65910_platform_data *pdata); 813 struct tps65910_platform_data *pdata);
814
815 static inline int tps65910_chip_id(struct tps65910 *tps65910)
816 {
817 return tps65910->id;
818 }
773 819
774 #endif /* __LINUX_MFD_TPS65910_H */ 820 #endif /* __LINUX_MFD_TPS65910_H */
775 821