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Commit 80aba53616a5f2f97adf386a2a3ccd5fb0dbfdd6

Authored by Pekka Enberg
Committed by Greg Kroah-Hartman
1 parent 8971280fb2
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

Staging: w35und: #include cleanup 

This patch moves #includes from sysdef.h and common.h to the files which
actually need them. This makes the dependencies less complex and allows us to
move code around much easily.

Acked-by: Pavel Machek <pavel@suse.cz>
Signed-off-by: Pekka Enberg <penberg@cs.helsinki.fi>

Showing 41 changed files with 208 additions and 94 deletions Inline Diff

drivers/staging/winbond/adapter.h
Diff comments   View file @ 80aba53
1 #ifndef __WINBOND_ADAPTER_H
2 #define __WINBOND_ADAPTER_H
3
4 #include <linux/wireless.h>
5
6 #include "bssdscpt.h"
7 #include "mto.h"
8 #include "wbhal_s.h"
9
1 #define OS_SET_SHUTDOWN( _A ) _A->shutdown=1 10 #define OS_SET_SHUTDOWN( _A ) _A->shutdown=1
2 #define OS_SET_RESUME( _A ) _A->shutdown=0 11 #define OS_SET_RESUME( _A ) _A->shutdown=0
3 #define OS_STOP( _A ) WBLINUX_stop( _A ) 12 #define OS_STOP( _A ) WBLINUX_stop( _A )
4 13
5 #define OS_CURRENT_RX_BYTE( _A ) _A->RxByteCount 14 #define OS_CURRENT_RX_BYTE( _A ) _A->RxByteCount
6 #define OS_CURRENT_TX_BYTE( _A ) _A->TxByteCount 15 #define OS_CURRENT_TX_BYTE( _A ) _A->TxByteCount
7 #define OS_EVENT_INDICATE( _A, _B, _F ) 16 #define OS_EVENT_INDICATE( _A, _B, _F )
8 #define OS_PMKID_STATUS_EVENT( _A ) 17 #define OS_PMKID_STATUS_EVENT( _A )
9 #define OS_RECEIVE_PACKET_INDICATE( _A, _D ) WBLinux_ReceivePacket( _A, _D ) 18 #define OS_RECEIVE_PACKET_INDICATE( _A, _D ) WBLinux_ReceivePacket( _A, _D )
10 #define OS_RECEIVE_802_1X_PACKET_INDICATE( _A, _D ) EAP_ReceivePacket( _A, _D ) 19 #define OS_RECEIVE_802_1X_PACKET_INDICATE( _A, _D ) EAP_ReceivePacket( _A, _D )
11 #define OS_GET_PACKET( _A, _D ) WBLINUX_GetNextPacket( _A, _D ) 20 #define OS_GET_PACKET( _A, _D ) WBLINUX_GetNextPacket( _A, _D )
12 #define OS_GET_PACKET_COMPLETE( _A, _D ) WBLINUX_GetNextPacketCompleted( _A, _D ) 21 #define OS_GET_PACKET_COMPLETE( _A, _D ) WBLINUX_GetNextPacketCompleted( _A, _D )
13 #define OS_SEND_RESULT( _A, _ID, _R ) 22 #define OS_SEND_RESULT( _A, _ID, _R )
14 23
15 #define WBLINUX_PACKET_ARRAY_SIZE (ETHERNET_TX_DESCRIPTORS*4) 24 #define WBLINUX_PACKET_ARRAY_SIZE (ETHERNET_TX_DESCRIPTORS*4)
16 25
17 #define MAX_ANSI_STRING 40 26 #define MAX_ANSI_STRING 40
18 27
19 struct wb35_adapter { 28 struct wb35_adapter {
20 u32 adapterIndex; // 20060703.4 Add for using padapterContext global adapter point 29 u32 adapterIndex; // 20060703.4 Add for using padapterContext global adapter point
21 30
22 WB_LOCALDESCRIPT sLocalPara; // Myself connected parameters 31 WB_LOCALDESCRIPT sLocalPara; // Myself connected parameters
23 PWB_BSSDESCRIPTION asBSSDescriptElement; 32 PWB_BSSDESCRIPTION asBSSDescriptElement;
24 33
25 MLME_FRAME sMlmeFrame; // connect to peerSTA parameters 34 MLME_FRAME sMlmeFrame; // connect to peerSTA parameters
26 35
27 MTO_PARAMETERS sMtoPara; // MTO_struct ... 36 MTO_PARAMETERS sMtoPara; // MTO_struct ...
28 hw_data_t sHwData; //For HAL 37 hw_data_t sHwData; //For HAL
29 MDS Mds; 38 MDS Mds;
30 39
31 spinlock_t SpinLock; 40 spinlock_t SpinLock;
32 u32 shutdown; 41 u32 shutdown;
33 42
34 atomic_t ThreadCount; 43 atomic_t ThreadCount;
35 44
36 u32 RxByteCount; 45 u32 RxByteCount;
37 u32 TxByteCount; 46 u32 TxByteCount;
38 47
39 struct sk_buff *skb_array[WBLINUX_PACKET_ARRAY_SIZE]; 48 struct sk_buff *skb_array[WBLINUX_PACKET_ARRAY_SIZE];
40 struct sk_buff *packet_return; 49 struct sk_buff *packet_return;
41 s32 skb_SetIndex; 50 s32 skb_SetIndex;
42 s32 skb_GetIndex; 51 s32 skb_GetIndex;
43 s32 netif_state_stop; // 1: stop 0: normal 52 s32 netif_state_stop; // 1: stop 0: normal
44 struct iw_statistics iw_stats; 53 struct iw_statistics iw_stats;
45 54
46 u8 LinkName[MAX_ANSI_STRING]; 55 u8 LinkName[MAX_ANSI_STRING];
47 }; 56 };
57
58 #endif
48 59
drivers/staging/winbond/bss_f.h
Diff comments   View file @ 80aba53
1 #ifndef __WINBOND_BSS_F_H
2 #define __WINBOND_BSS_F_H
3
4 #include "adapter.h"
5
6 struct PMKID_Information_Element;
7
1 // 8 //
2 // BSS descriptor DataBase management global function 9 // BSS descriptor DataBase management global function
3 // 10 //
4 11
5 void vBSSdescriptionInit(struct wb35_adapter * adapter); 12 void vBSSdescriptionInit(struct wb35_adapter * adapter);
6 void vBSSfoundList(struct wb35_adapter * adapter); 13 void vBSSfoundList(struct wb35_adapter * adapter);
7 u8 boChanFilter(struct wb35_adapter * adapter, u8 ChanNo); 14 u8 boChanFilter(struct wb35_adapter * adapter, u8 ChanNo);
8 u16 wBSSallocateEntry(struct wb35_adapter * adapter); 15 u16 wBSSallocateEntry(struct wb35_adapter * adapter);
9 u16 wBSSGetEntry(struct wb35_adapter * adapter); 16 u16 wBSSGetEntry(struct wb35_adapter * adapter);
10 void vSimpleHouseKeeping(struct wb35_adapter * adapter); 17 void vSimpleHouseKeeping(struct wb35_adapter * adapter);
11 u16 wBSShouseKeeping(struct wb35_adapter * adapter); 18 u16 wBSShouseKeeping(struct wb35_adapter * adapter);
12 void ClearBSSdescpt(struct wb35_adapter * adapter, u16 i); 19 void ClearBSSdescpt(struct wb35_adapter * adapter, u16 i);
13 u16 wBSSfindBssID(struct wb35_adapter * adapter, u8 *pbBssid); 20 u16 wBSSfindBssID(struct wb35_adapter * adapter, u8 *pbBssid);
14 u16 wBSSfindDedicateCandidate(struct wb35_adapter * adapter, struct SSID_Element *psSsid, u8 *pbBssid); 21 u16 wBSSfindDedicateCandidate(struct wb35_adapter * adapter, struct SSID_Element *psSsid, u8 *pbBssid);
15 u16 wBSSfindMACaddr(struct wb35_adapter * adapter, u8 *pbMacAddr); 22 u16 wBSSfindMACaddr(struct wb35_adapter * adapter, u8 *pbMacAddr);
16 u16 wBSSsearchMACaddr(struct wb35_adapter * adapter, u8 *pbMacAddr, u8 band); 23 u16 wBSSsearchMACaddr(struct wb35_adapter * adapter, u8 *pbMacAddr, u8 band);
17 u16 wBSSaddScanData(struct wb35_adapter *, u16, psRXDATA); 24 u16 wBSSaddScanData(struct wb35_adapter *, u16, psRXDATA);
18 u16 wBSSUpdateScanData(struct wb35_adapter * adapter, u16 wBssIdx, psRXDATA psRcvData); 25 u16 wBSSUpdateScanData(struct wb35_adapter * adapter, u16 wBssIdx, psRXDATA psRcvData);
19 u16 wBSScreateIBSSdata(struct wb35_adapter * adapter, PWB_BSSDESCRIPTION psDesData); 26 u16 wBSScreateIBSSdata(struct wb35_adapter * adapter, PWB_BSSDESCRIPTION psDesData);
20 void DesiredRate2BSSdescriptor(struct wb35_adapter * adapter, PWB_BSSDESCRIPTION psDesData, 27 void DesiredRate2BSSdescriptor(struct wb35_adapter * adapter, PWB_BSSDESCRIPTION psDesData,
21 u8 *pBasicRateSet, u8 BasicRateCount, 28 u8 *pBasicRateSet, u8 BasicRateCount,
22 u8 *pOperationRateSet, u8 OperationRateCount); 29 u8 *pOperationRateSet, u8 OperationRateCount);
23 void DesiredRate2InfoElement(struct wb35_adapter * adapter, u8 *addr, u16 *iFildOffset, 30 void DesiredRate2InfoElement(struct wb35_adapter * adapter, u8 *addr, u16 *iFildOffset,
24 u8 *pBasicRateSet, u8 BasicRateCount, 31 u8 *pBasicRateSet, u8 BasicRateCount,
25 u8 *pOperationRateSet, u8 OperationRateCount); 32 u8 *pOperationRateSet, u8 OperationRateCount);
26 void BSSAddIBSSdata(struct wb35_adapter * adapter, PWB_BSSDESCRIPTION psDesData); 33 void BSSAddIBSSdata(struct wb35_adapter * adapter, PWB_BSSDESCRIPTION psDesData);
27 unsigned char boCmpMacAddr( u8 *, u8 *); 34 unsigned char boCmpMacAddr( u8 *, u8 *);
28 unsigned char boCmpSSID(struct SSID_Element *psSSID1, struct SSID_Element *psSSID2); 35 unsigned char boCmpSSID(struct SSID_Element *psSSID1, struct SSID_Element *psSSID2);
29 u16 wBSSfindSSID(struct wb35_adapter * adapter, struct SSID_Element *psSsid); 36 u16 wBSSfindSSID(struct wb35_adapter * adapter, struct SSID_Element *psSsid);
30 u16 wRoamingQuery(struct wb35_adapter * adapter); 37 u16 wRoamingQuery(struct wb35_adapter * adapter);
31 void vRateToBitmap(struct wb35_adapter * adapter, u16 index); 38 void vRateToBitmap(struct wb35_adapter * adapter, u16 index);
32 u8 bRateToBitmapIndex(struct wb35_adapter * adapter, u8 bRate); 39 u8 bRateToBitmapIndex(struct wb35_adapter * adapter, u8 bRate);
33 u8 bBitmapToRate(u8 i); 40 u8 bBitmapToRate(u8 i);
34 unsigned char boIsERPsta(struct wb35_adapter * adapter, u16 i); 41 unsigned char boIsERPsta(struct wb35_adapter * adapter, u16 i);
35 unsigned char boCheckConnect(struct wb35_adapter * adapter); 42 unsigned char boCheckConnect(struct wb35_adapter * adapter);
36 unsigned char boCheckSignal(struct wb35_adapter * adapter); 43 unsigned char boCheckSignal(struct wb35_adapter * adapter);
37 void AddIBSSIe(struct wb35_adapter * adapter,PWB_BSSDESCRIPTION psDesData );//added by ws for WPA_None06/01/04 44 void AddIBSSIe(struct wb35_adapter * adapter,PWB_BSSDESCRIPTION psDesData );//added by ws for WPA_None06/01/04
38 void BssScanUpToDate(struct wb35_adapter * adapter); 45 void BssScanUpToDate(struct wb35_adapter * adapter);
39 void BssUpToDate(struct wb35_adapter * adapter); 46 void BssUpToDate(struct wb35_adapter * adapter);
40 void RateSort(u8 *RateArray, u8 num, u8 mode); 47 void RateSort(u8 *RateArray, u8 num, u8 mode);
41 void RateReSortForSRate(struct wb35_adapter * adapter, u8 *RateArray, u8 num); 48 void RateReSortForSRate(struct wb35_adapter * adapter, u8 *RateArray, u8 num);
42 void Assemble_IE(struct wb35_adapter * adapter, u16 wBssIdx); 49 void Assemble_IE(struct wb35_adapter * adapter, u16 wBssIdx);
43 void SetMaxTxRate(struct wb35_adapter * adapter); 50 void SetMaxTxRate(struct wb35_adapter * adapter);
44 51
45 void CreateWpaIE(struct wb35_adapter * adapter, u16* iFildOffset, u8 *msg, struct Management_Frame* msgHeader, 52 void CreateWpaIE(struct wb35_adapter * adapter, u16* iFildOffset, u8 *msg, struct Management_Frame* msgHeader,
46 struct Association_Request_Frame_Body* msgBody, u16 iMSindex); //added by WS 05/14/05 53 struct Association_Request_Frame_Body* msgBody, u16 iMSindex); //added by WS 05/14/05
47 54
48 #ifdef _WPA2_ 55 #ifdef _WPA2_
49 void CreateRsnIE(struct wb35_adapter * adapter, u16* iFildOffset, u8 *msg, struct Management_Frame* msgHeader, 56 void CreateRsnIE(struct wb35_adapter * adapter, u16* iFildOffset, u8 *msg, struct Management_Frame* msgHeader,
50 struct Association_Request_Frame_Body* msgBody, u16 iMSindex);//added by WS 05/14/05 57 struct Association_Request_Frame_Body* msgBody, u16 iMSindex);//added by WS 05/14/05
51 58
52 u16 SearchPmkid(struct wb35_adapter * adapter, struct Management_Frame* msgHeader, 59 u16 SearchPmkid(struct wb35_adapter * adapter, struct Management_Frame* msgHeader,
53 struct PMKID_Information_Element * AssoReq_PMKID ); 60 struct PMKID_Information_Element * AssoReq_PMKID );
61 #endif
62
54 #endif 63 #endif
55 64
drivers/staging/winbond/bssdscpt.h
Diff comments   View file @ 80aba53
1 #ifndef __WINBOND_BSSDSCPT_H
2 #define __WINBOND_BSSDSCPT_H
3
4 #include <linux/types.h>
5
6 #include "mds_s.h"
7 #include "mlme_s.h"
8
1 //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 9 //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2 // bssdscpt.c 10 // bssdscpt.c
3 // BSS descriptor data base 11 // BSS descriptor data base
4 // history : 12 // history :
5 // 13 //
6 // Description: 14 // Description:
7 // BSS descriptor data base will store the information of the stations at the 15 // BSS descriptor data base will store the information of the stations at the
8 // surrounding environment. The first entry( psBSS(0) ) will not be used and the 16 // surrounding environment. The first entry( psBSS(0) ) will not be used and the
9 // second one( psBSS(1) ) will be used for the broadcast address. 17 // second one( psBSS(1) ) will be used for the broadcast address.
10 //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 18 //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
11 19
12 //#define MAX_ACC_RSSI_COUNT 10 20 //#define MAX_ACC_RSSI_COUNT 10
13 #define MAX_ACC_RSSI_COUNT 6 21 #define MAX_ACC_RSSI_COUNT 6
14 22
15 /////////////////////////////////////////////////////////////////////////// 23 ///////////////////////////////////////////////////////////////////////////
16 // 24 //
17 // BSS Description set Element , to store scan received Beacon information 25 // BSS Description set Element , to store scan received Beacon information
18 // 26 //
19 // Our's differs slightly from the specs. The specify a PHY_Parameter_Set. 27 // Our's differs slightly from the specs. The specify a PHY_Parameter_Set.
20 // Since we're only doing a DS design right now, we just have a DS structure. 28 // Since we're only doing a DS design right now, we just have a DS structure.
21 ////////////////////////////////////////////////////////////////////////////// 29 //////////////////////////////////////////////////////////////////////////////
22 typedef struct BSSDescriptionElement 30 typedef struct BSSDescriptionElement
23 { 31 {
24 u32 SlotValid; 32 u32 SlotValid;
25 u32 PowerSaveMode; 33 u32 PowerSaveMode;
26 RXLAYER1 RxLayer1; 34 RXLAYER1 RxLayer1;
27 35
28 u8 abPeerAddress[ MAC_ADDR_LENGTH + 2 ]; // peer MAC Address associated with this session. 6-OCTET value 36 u8 abPeerAddress[ MAC_ADDR_LENGTH + 2 ]; // peer MAC Address associated with this session. 6-OCTET value
29 u32 dwBgScanStamp; // BgScan Sequence Counter stamp, record psROAM->dwScanCounter. 37 u32 dwBgScanStamp; // BgScan Sequence Counter stamp, record psROAM->dwScanCounter.
30 38
31 u16 Beacon_Period; 39 u16 Beacon_Period;
32 u16 wATIM_Window; 40 u16 wATIM_Window;
33 41
34 u8 abBssID[ MAC_ADDR_LENGTH + 2 ]; // 6B 42 u8 abBssID[ MAC_ADDR_LENGTH + 2 ]; // 6B
35 43
36 u8 bBssType; 44 u8 bBssType;
37 u8 DTIM_Period; // 1 octet usually from TIM element, if present 45 u8 DTIM_Period; // 1 octet usually from TIM element, if present
38 u8 boInTimerHandler; 46 u8 boInTimerHandler;
39 u8 boERP; // analysis ERP or (extended) supported rate element 47 u8 boERP; // analysis ERP or (extended) supported rate element
40 48
41 u8 Timestamp[8]; 49 u8 Timestamp[8];
42 u8 BasicRate[32]; 50 u8 BasicRate[32];
43 u8 OperationalRate[32]; 51 u8 OperationalRate[32];
44 u32 dwBasicRateBitmap; //bit map, retrieve from SupportedRateSet 52 u32 dwBasicRateBitmap; //bit map, retrieve from SupportedRateSet
45 u32 dwOperationalRateBitmap; //bit map, retrieve from SupportedRateSet and 53 u32 dwOperationalRateBitmap; //bit map, retrieve from SupportedRateSet and
46 // ExtendedSupportedRateSet 54 // ExtendedSupportedRateSet
47 // For RSSI calculating 55 // For RSSI calculating
48 u32 HalRssi[MAX_ACC_RSSI_COUNT]; // Encode. It must use MACRO of HAL to get the LNA and AGC data 56 u32 HalRssi[MAX_ACC_RSSI_COUNT]; // Encode. It must use MACRO of HAL to get the LNA and AGC data
49 u32 HalRssiIndex; 57 u32 HalRssiIndex;
50 58
51 ////From beacon/probe response 59 ////From beacon/probe response
52 struct SSID_Element SSID; // 34B 60 struct SSID_Element SSID; // 34B
53 u8 reserved_1[ 2 ]; 61 u8 reserved_1[ 2 ];
54 62
55 struct Capability_Information_Element CapabilityInformation; // 2B 63 struct Capability_Information_Element CapabilityInformation; // 2B
56 u8 reserved_2[ 2 ]; 64 u8 reserved_2[ 2 ];
57 65
58 struct CF_Parameter_Set_Element CF_Parameter_Set; // 8B 66 struct CF_Parameter_Set_Element CF_Parameter_Set; // 8B
59 struct IBSS_Parameter_Set_Element IBSS_Parameter_Set; // 4B 67 struct IBSS_Parameter_Set_Element IBSS_Parameter_Set; // 4B
60 struct TIM_Element TIM_Element_Set; // 256B 68 struct TIM_Element TIM_Element_Set; // 256B
61 69
62 struct DS_Parameter_Set_Element DS_Parameter_Set; // 3B 70 struct DS_Parameter_Set_Element DS_Parameter_Set; // 3B
63 u8 reserved_3; 71 u8 reserved_3;
64 72
65 struct ERP_Information_Element ERP_Information_Set; // 3B 73 struct ERP_Information_Element ERP_Information_Set; // 3B
66 u8 reserved_4; 74 u8 reserved_4;
67 75
68 struct Supported_Rates_Element SupportedRateSet; // 10B 76 struct Supported_Rates_Element SupportedRateSet; // 10B
69 u8 reserved_5[2]; 77 u8 reserved_5[2];
70 78
71 struct Extended_Supported_Rates_Element ExtendedSupportedRateSet; // 257B 79 struct Extended_Supported_Rates_Element ExtendedSupportedRateSet; // 257B
72 u8 reserved_6[3]; 80 u8 reserved_6[3];
73 81
74 u8 band; 82 u8 band;
75 u8 reserved_7[3]; 83 u8 reserved_7[3];
76 84
77 // for MLME module 85 // for MLME module
78 u16 wState; // the current state of the system 86 u16 wState; // the current state of the system
79 u16 wIndex; // THIS BSS element entry index 87 u16 wIndex; // THIS BSS element entry index
80 88
81 void* psadapter; // pointer to THIS adapter 89 void* psadapter; // pointer to THIS adapter
82 struct timer_list timer; // MLME timer 90 struct timer_list timer; // MLME timer
83 91
84 // Authentication 92 // Authentication
85 u16 wAuthAlgo; // peer MAC MLME use Auth algorithm, default OPEN_AUTH 93 u16 wAuthAlgo; // peer MAC MLME use Auth algorithm, default OPEN_AUTH
86 u16 wAuthSeqNum; // current local MAC sendout AuthReq sequence number 94 u16 wAuthSeqNum; // current local MAC sendout AuthReq sequence number
87 95
88 u8 auth_challengeText[128]; 96 u8 auth_challengeText[128];
89 97
90 ////For XP: 98 ////For XP:
91 u32 ies_len; // information element length 99 u32 ies_len; // information element length
92 u8 ies[256]; // information element 100 u8 ies[256]; // information element
93 101
94 ////For WPA 102 ////For WPA
95 u8 RsnIe_Type[2]; //added by ws for distinguish WPA and WPA2 05/14/04 103 u8 RsnIe_Type[2]; //added by ws for distinguish WPA and WPA2 05/14/04
96 u8 RsnIe_len; 104 u8 RsnIe_len;
97 u8 Rsn_Num; 105 u8 Rsn_Num;
98 106
99 // to record the rsn cipher suites,addded by ws 09/05/04 107 // to record the rsn cipher suites,addded by ws 09/05/04
100 SUITE_SELECTOR group_cipher; // 4B 108 SUITE_SELECTOR group_cipher; // 4B
101 SUITE_SELECTOR pairwise_key_cipher_suites[WLAN_MAX_PAIRWISE_CIPHER_SUITE_COUNT]; 109 SUITE_SELECTOR pairwise_key_cipher_suites[WLAN_MAX_PAIRWISE_CIPHER_SUITE_COUNT];
102 SUITE_SELECTOR auth_key_mgt_suites[WLAN_MAX_AUTH_KEY_MGT_SUITE_LIST_COUNT]; 110 SUITE_SELECTOR auth_key_mgt_suites[WLAN_MAX_AUTH_KEY_MGT_SUITE_LIST_COUNT];
103 111
104 u16 pairwise_key_cipher_suite_count; 112 u16 pairwise_key_cipher_suite_count;
105 u16 auth_key_mgt_suite_count; 113 u16 auth_key_mgt_suite_count;
106 114
107 u8 pairwise_key_cipher_suite_selected; 115 u8 pairwise_key_cipher_suite_selected;
108 u8 auth_key_mgt_suite_selected; 116 u8 auth_key_mgt_suite_selected;
109 u8 reserved_8[2]; 117 u8 reserved_8[2];
110 118
111 struct RSN_Capability_Element rsn_capabilities; // 2B 119 struct RSN_Capability_Element rsn_capabilities; // 2B
112 u8 reserved_9[2]; 120 u8 reserved_9[2];
113 121
114 //to record the rsn cipher suites for WPA2 122 //to record the rsn cipher suites for WPA2
115 #ifdef _WPA2_ 123 #ifdef _WPA2_
116 u32 pre_auth; //added by WS for distinguish for 05/04/04 124 u32 pre_auth; //added by WS for distinguish for 05/04/04
117 SUITE_SELECTOR wpa2_group_cipher; // 4B 125 SUITE_SELECTOR wpa2_group_cipher; // 4B
118 SUITE_SELECTOR wpa2_pairwise_key_cipher_suites[WLAN_MAX_PAIRWISE_CIPHER_SUITE_COUNT]; 126 SUITE_SELECTOR wpa2_pairwise_key_cipher_suites[WLAN_MAX_PAIRWISE_CIPHER_SUITE_COUNT];
119 SUITE_SELECTOR wpa2_auth_key_mgt_suites[WLAN_MAX_AUTH_KEY_MGT_SUITE_LIST_COUNT]; 127 SUITE_SELECTOR wpa2_auth_key_mgt_suites[WLAN_MAX_AUTH_KEY_MGT_SUITE_LIST_COUNT];
120 128
121 u16 wpa2_pairwise_key_cipher_suite_count; 129 u16 wpa2_pairwise_key_cipher_suite_count;
122 u16 wpa2_auth_key_mgt_suite_count; 130 u16 wpa2_auth_key_mgt_suite_count;
123 131
124 u8 wpa2_pairwise_key_cipher_suite_selected; 132 u8 wpa2_pairwise_key_cipher_suite_selected;
125 u8 wpa2_auth_key_mgt_suite_selected; 133 u8 wpa2_auth_key_mgt_suite_selected;
126 u8 reserved_10[2]; 134 u8 reserved_10[2];
127 135
128 struct RSN_Capability_Element wpa2_rsn_capabilities; // 2B 136 struct RSN_Capability_Element wpa2_rsn_capabilities; // 2B
129 u8 reserved_11[2]; 137 u8 reserved_11[2];
130 #endif //endif _WPA2_ 138 #endif //endif _WPA2_
131 139
132 //For Replay protection 140 //For Replay protection
133 // u8 PairwiseTSC[6]; 141 // u8 PairwiseTSC[6];
134 // u8 GroupTSC[6]; 142 // u8 GroupTSC[6];
135 143
136 ////For up-to-date 144 ////For up-to-date
137 u32 ScanTimeStamp; //for the decision whether the station/AP(may exist at 145 u32 ScanTimeStamp; //for the decision whether the station/AP(may exist at
138 //different channels) has left. It must be detected by 146 //different channels) has left. It must be detected by
139 //scanning. Local device may connected or disconnected. 147 //scanning. Local device may connected or disconnected.
140 u32 BssTimeStamp; //Only for the decision whether the station/AP(exist in 148 u32 BssTimeStamp; //Only for the decision whether the station/AP(exist in
141 //the same channel, and no scanning) if local device has 149 //the same channel, and no scanning) if local device has
142 //connected successfully. 150 //connected successfully.
143 151
144 // 20061108 Add for storing WPS_IE. [E id][Length][OUI][Data] 152 // 20061108 Add for storing WPS_IE. [E id][Length][OUI][Data]
145 u8 WPS_IE_Data[MAX_IE_APPEND_SIZE]; 153 u8 WPS_IE_Data[MAX_IE_APPEND_SIZE];
146 u16 WPS_IE_length; 154 u16 WPS_IE_length;
147 u16 WPS_IE_length_tmp; // For verify there is an WPS_IE in Beacon or probe response 155 u16 WPS_IE_length_tmp; // For verify there is an WPS_IE in Beacon or probe response
148 156
149 } WB_BSSDESCRIPTION, *PWB_BSSDESCRIPTION; 157 } WB_BSSDESCRIPTION, *PWB_BSSDESCRIPTION;
150 158
151 #define wBSSConnectedSTA(adapter) \ 159 #define wBSSConnectedSTA(adapter) \
152 ((u16)(adapter)->sLocalPara.wConnectedSTAindex) 160 ((u16)(adapter)->sLocalPara.wConnectedSTAindex)
153 161
154 #define psBSS(i) (&(adapter->asBSSDescriptElement[(i)])) 162 #define psBSS(i) (&(adapter->asBSSDescriptElement[(i)]))
163
164 #endif
155 165
drivers/staging/winbond/ds_tkip.h
Diff comments   View file @ 80aba53
1 #ifndef __WINBOND_DS_TKIP_H
2 #define __WINBOND_DS_TKIP_H
3
4 #include <linux/types.h>
5
1 // Rotation functions on 32 bit values 6 // Rotation functions on 32 bit values
2 #define ROL32( A, n ) \ 7 #define ROL32( A, n ) \
3 ( ((A) << (n)) | ( ((A)>>(32-(n))) & ( (1UL << (n)) - 1 ) ) ) 8 ( ((A) << (n)) | ( ((A)>>(32-(n))) & ( (1UL << (n)) - 1 ) ) )
4 9
5 #define ROR32( A, n ) ROL32( (A), 32-(n) ) 10 #define ROR32( A, n ) ROL32( (A), 32-(n) )
6 11
7 12
8 typedef struct tkip 13 typedef struct tkip
9 { 14 {
10 u32 K0, K1; // Key 15 u32 K0, K1; // Key
11 union 16 union
12 { 17 {
13 struct // Current state 18 struct // Current state
14 { 19 {
15 u32 L; 20 u32 L;
16 u32 R; 21 u32 R;
17 }; 22 };
18 u8 LR[8]; 23 u8 LR[8];
19 }; 24 };
20 union 25 union
21 { 26 {
22 u32 M; // Message accumulator (single word) 27 u32 M; // Message accumulator (single word)
23 u8 Mb[4]; 28 u8 Mb[4];
24 }; 29 };
25 s32 bytes_in_M; // # bytes in M 30 s32 bytes_in_M; // # bytes in M
26 } tkip_t; 31 } tkip_t;
27 32
28 //void _append_data( u8 *pData, u16 size, tkip_t *p ); 33 //void _append_data( u8 *pData, u16 size, tkip_t *p );
29 void Mds_MicGet( void* adapter, void* pRxLayer1, u8 *pKey, u8 *pMic ); 34 void Mds_MicGet( void* adapter, void* pRxLayer1, u8 *pKey, u8 *pMic );
30 void Mds_MicFill( void* adapter, void* pDes, u8 *XmitBufAddress ); 35 void Mds_MicFill( void* adapter, void* pDes, u8 *XmitBufAddress );
36
37 #endif
31 38
drivers/staging/winbond/gl_80211.h
Diff comments   View file @ 80aba53
1
2 #ifndef __GL_80211_H__ 1 #ifndef __GL_80211_H__
3 #define __GL_80211_H__ 2 #define __GL_80211_H__
3
4 #include <linux/types.h>
4 5
5 /****************** CONSTANT AND MACRO SECTION ******************************/ 6 /****************** CONSTANT AND MACRO SECTION ******************************/
6 7
7 /* BSS Type */ 8 /* BSS Type */
8 enum { 9 enum {
9 WLAN_BSSTYPE_INFRASTRUCTURE = 0, 10 WLAN_BSSTYPE_INFRASTRUCTURE = 0,
10 WLAN_BSSTYPE_INDEPENDENT, 11 WLAN_BSSTYPE_INDEPENDENT,
11 WLAN_BSSTYPE_ANY_BSS, 12 WLAN_BSSTYPE_ANY_BSS,
12 }; 13 };
13 14
14 15
15 16
16 /* Preamble_Type, see <SFS-802.11G-MIB-203> */ 17 /* Preamble_Type, see <SFS-802.11G-MIB-203> */
17 typedef enum preamble_type { 18 typedef enum preamble_type {
18 WLAN_PREAMBLE_TYPE_SHORT, 19 WLAN_PREAMBLE_TYPE_SHORT,
19 WLAN_PREAMBLE_TYPE_LONG, 20 WLAN_PREAMBLE_TYPE_LONG,
20 } preamble_type_e; 21 } preamble_type_e;
21 22
22 23
23 /* Slot_Time_Type, see <SFS-802.11G-MIB-208> */ 24 /* Slot_Time_Type, see <SFS-802.11G-MIB-208> */
24 typedef enum slot_time_type { 25 typedef enum slot_time_type {
25 WLAN_SLOT_TIME_TYPE_LONG, 26 WLAN_SLOT_TIME_TYPE_LONG,
26 WLAN_SLOT_TIME_TYPE_SHORT, 27 WLAN_SLOT_TIME_TYPE_SHORT,
27 } slot_time_type_e; 28 } slot_time_type_e;
28 29
29 /*--------------------------------------------------------------------------*/ 30 /*--------------------------------------------------------------------------*/
30 /* Encryption Mode */ 31 /* Encryption Mode */
31 typedef enum { 32 typedef enum {
32 WEP_DISABLE = 0, 33 WEP_DISABLE = 0,
33 WEP_64, 34 WEP_64,
34 WEP_128, 35 WEP_128,
35 36
36 ENCRYPT_DISABLE, 37 ENCRYPT_DISABLE,
37 ENCRYPT_WEP, 38 ENCRYPT_WEP,
38 ENCRYPT_WEP_NOKEY, 39 ENCRYPT_WEP_NOKEY,
39 ENCRYPT_TKIP, 40 ENCRYPT_TKIP,
40 ENCRYPT_TKIP_NOKEY, 41 ENCRYPT_TKIP_NOKEY,
41 ENCRYPT_CCMP, 42 ENCRYPT_CCMP,
42 ENCRYPT_CCMP_NOKEY, 43 ENCRYPT_CCMP_NOKEY,
43 } encryption_mode_e; 44 } encryption_mode_e;
44 45
45 typedef enum _WLAN_RADIO { 46 typedef enum _WLAN_RADIO {
46 WLAN_RADIO_ON, 47 WLAN_RADIO_ON,
47 WLAN_RADIO_OFF, 48 WLAN_RADIO_OFF,
48 WLAN_RADIO_MAX, // not a real type, defined as an upper bound 49 WLAN_RADIO_MAX, // not a real type, defined as an upper bound
49 } WLAN_RADIO; 50 } WLAN_RADIO;
50 51
51 typedef struct _WLAN_RADIO_STATUS { 52 typedef struct _WLAN_RADIO_STATUS {
52 WLAN_RADIO HWStatus; 53 WLAN_RADIO HWStatus;
53 WLAN_RADIO SWStatus; 54 WLAN_RADIO SWStatus;
54 } WLAN_RADIO_STATUS; 55 } WLAN_RADIO_STATUS;
55 56
56 //---------------------------------------------------------------------------- 57 //----------------------------------------------------------------------------
57 // 20041021 1.1.81.1000 ybjiang 58 // 20041021 1.1.81.1000 ybjiang
58 // add for radio notification 59 // add for radio notification
59 typedef 60 typedef
60 void (*RADIO_NOTIFICATION_HANDLER)( 61 void (*RADIO_NOTIFICATION_HANDLER)(
61 void *Data, 62 void *Data,
62 void *RadioStatusBuffer, 63 void *RadioStatusBuffer,
63 u32 RadioStatusBufferLen 64 u32 RadioStatusBufferLen
64 ); 65 );
65 66
66 typedef struct _WLAN_RADIO_NOTIFICATION 67 typedef struct _WLAN_RADIO_NOTIFICATION
67 { 68 {
68 RADIO_NOTIFICATION_HANDLER RadioChangeHandler; 69 RADIO_NOTIFICATION_HANDLER RadioChangeHandler;
69 void *Data; 70 void *Data;
70 } WLAN_RADIO_NOTIFICATION; 71 } WLAN_RADIO_NOTIFICATION;
71 72
72 //---------------------------------------------------------------------------- 73 //----------------------------------------------------------------------------
73 // 20041102 1.1.91.1000 ybjiang 74 // 20041102 1.1.91.1000 ybjiang
74 // add for OID_802_11_CUST_REGION_CAPABILITIES and OID_802_11_OID_REGION 75 // add for OID_802_11_CUST_REGION_CAPABILITIES and OID_802_11_OID_REGION
75 typedef enum _WLAN_REGION_CODE 76 typedef enum _WLAN_REGION_CODE
76 { 77 {
77 WLAN_REGION_UNKNOWN, 78 WLAN_REGION_UNKNOWN,
78 WLAN_REGION_EUROPE, 79 WLAN_REGION_EUROPE,
79 WLAN_REGION_JAPAN, 80 WLAN_REGION_JAPAN,
80 WLAN_REGION_USA, 81 WLAN_REGION_USA,
81 WLAN_REGION_FRANCE, 82 WLAN_REGION_FRANCE,
82 WLAN_REGION_SPAIN, 83 WLAN_REGION_SPAIN,
83 WLAN_REGION_ISRAEL, 84 WLAN_REGION_ISRAEL,
84 WLAN_REGION_MAX, // not a real type, defined as an upper bound 85 WLAN_REGION_MAX, // not a real type, defined as an upper bound
85 } WLAN_REGION_CODE; 86 } WLAN_REGION_CODE;
86 87
87 #define REGION_NAME_MAX_LENGTH 256 88 #define REGION_NAME_MAX_LENGTH 256
88 89
89 typedef struct _WLAN_REGION_CHANNELS 90 typedef struct _WLAN_REGION_CHANNELS
90 { 91 {
91 u32 Length; 92 u32 Length;
92 u32 NameLength; 93 u32 NameLength;
93 u8 Name[REGION_NAME_MAX_LENGTH]; 94 u8 Name[REGION_NAME_MAX_LENGTH];
94 WLAN_REGION_CODE Code; 95 WLAN_REGION_CODE Code;
95 u32 Frequency[1]; 96 u32 Frequency[1];
96 } WLAN_REGION_CHANNELS; 97 } WLAN_REGION_CHANNELS;
97 98
98 typedef struct _WLAN_REGION_CAPABILITIES 99 typedef struct _WLAN_REGION_CAPABILITIES
99 { 100 {
100 u32 NumberOfItems; 101 u32 NumberOfItems;
101 WLAN_REGION_CHANNELS Region[1]; 102 WLAN_REGION_CHANNELS Region[1];
102 } WLAN_REGION_CAPABILITIES; 103 } WLAN_REGION_CAPABILITIES;
103 104
104 typedef struct _region_name_map { 105 typedef struct _region_name_map {
105 WLAN_REGION_CODE region; 106 WLAN_REGION_CODE region;
106 u8 *name; 107 u8 *name;
107 u32 *channels; 108 u32 *channels;
108 } region_name_map; 109 } region_name_map;
109 110
110 /*--------------------------------------------------------------------------*/ 111 /*--------------------------------------------------------------------------*/
111 #define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5] 112 #define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
112 #define MACSTR "%02X:%02X:%02X:%02X:%02X:%02X" 113 #define MACSTR "%02X:%02X:%02X:%02X:%02X:%02X"
113 114
114 // TODO: 0627 kevin 115 // TODO: 0627 kevin
115 #define MIC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5], (a)[6], (a)[7] 116 #define MIC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5], (a)[6], (a)[7]
116 #define MICSTR "%02X %02X %02X %02X %02X %02X %02X %02X" 117 #define MICSTR "%02X %02X %02X %02X %02X %02X %02X %02X"
117 118
118 #define MICKEY2STR(a) MIC2STR(a) 119 #define MICKEY2STR(a) MIC2STR(a)
119 #define MICKEYSTR MICSTR 120 #define MICKEYSTR MICSTR
120 121
121 122
122 #endif /* __GL_80211_H__ */ 123 #endif /* __GL_80211_H__ */
123 /*** end of file ***/ 124 /*** end of file ***/
124 125
125 126
drivers/staging/winbond/linux/common.h
Diff comments   View file @ 80aba53
1 // 1 //
2 // common.h 2 // common.h
3 // 3 //
4 // This file contains the OS dependant definition and function. 4 // This file contains the OS dependant definition and function.
5 // Every OS has this file individual. 5 // Every OS has this file individual.
6 // 6 //
7 7
8 #define DebugUsbdStatusInformation( _A ) 8 #define DebugUsbdStatusInformation( _A )
9 9
10 #ifndef COMMON_DEF 10 #ifndef COMMON_DEF
11 #define COMMON_DEF 11 #define COMMON_DEF
12 12
13 #include <linux/version.h>
14 #include <linux/usb.h>
15 #include <linux/kernel.h> //need for kernel alert
16 #include <linux/autoconf.h>
17 #include <linux/sched.h>
18 #include <linux/signal.h>
19 #include <linux/slab.h> //memory allocate
20 #include <linux/module.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/init.h>//need for init and exit modules marco
24 #include <linux/ctype.h>
25 #include <linux/wait.h>
26 #include <linux/list.h>
27 #include <linux/wireless.h>
28 #include <linux/if_arp.h>
29 #include <asm/uaccess.h>
30 #include <net/iw_handler.h>
31 #include <linux/skbuff.h>
32
33
34 //#define DEBUG_ENABLED 1 13 //#define DEBUG_ENABLED 1
35 14
36 //================================================================================================== 15 //==================================================================================================
37 // Common function definition 16 // Common function definition
38 //================================================================================================== 17 //==================================================================================================
39 #define DEBUG_ENABLED 18 #define DEBUG_ENABLED
40 #define ETH_LENGTH_OF_ADDRESS 6 19 #define ETH_LENGTH_OF_ADDRESS 6
41 #ifdef DEBUG_ENABLED 20 #ifdef DEBUG_ENABLED
42 #define WBDEBUG( _M ) printk _M 21 #define WBDEBUG( _M ) printk _M
43 #else 22 #else
44 #define WBDEBUG( _M ) 0 23 #define WBDEBUG( _M ) 0
45 #endif 24 #endif
46 25
47 #define OS_EVENT_INDICATE( _A, _B, _F ) 26 #define OS_EVENT_INDICATE( _A, _B, _F )
48 #define OS_PMKID_STATUS_EVENT( _A ) 27 #define OS_PMKID_STATUS_EVENT( _A )
49 28
50 #endif // COMMON_DEF 29 #endif // COMMON_DEF
51 30
52 31
drivers/staging/winbond/linux/sysdef.h
Diff comments   View file @ 80aba53
1 1
2 2
3 // 3 //
4 // Winbond WLAN System Configuration defines 4 // Winbond WLAN System Configuration defines
5 // 5 //
6 6
7 //===================================================================== 7 //=====================================================================
8 // Current directory is Linux 8 // Current directory is Linux
9 // The definition WB_LINUX is a keyword for this OS 9 // The definition WB_LINUX is a keyword for this OS
10 //===================================================================== 10 //=====================================================================
11 #ifndef SYS_DEF_H 11 #ifndef SYS_DEF_H
12 #define SYS_DEF_H 12 #define SYS_DEF_H
13 #define WB_LINUX 13 #define WB_LINUX
14 #define WB_LINUX_WPA_PSK 14 #define WB_LINUX_WPA_PSK
15 15
16 16
17 //#define _IBSS_BEACON_SEQ_STICK_ 17 //#define _IBSS_BEACON_SEQ_STICK_
18 #define _USE_FALLBACK_RATE_ 18 #define _USE_FALLBACK_RATE_
19 //#define ANTDIV_DEFAULT_ON 19 //#define ANTDIV_DEFAULT_ON
20 20
21 #define _WPA2_ // 20061122 It's needed for current Linux driver 21 #define _WPA2_ // 20061122 It's needed for current Linux driver
22 22
23 23
24 #ifndef _WPA_PSK_DEBUG 24 #ifndef _WPA_PSK_DEBUG
25 #undef _WPA_PSK_DEBUG 25 #undef _WPA_PSK_DEBUG
26 #endif 26 #endif
27 27
28 // debug print options, mark what debug you don't need 28 // debug print options, mark what debug you don't need
29 29
30 #ifdef FULL_DEBUG 30 #ifdef FULL_DEBUG
31 #define _PE_STATE_DUMP_ 31 #define _PE_STATE_DUMP_
32 #define _PE_TX_DUMP_ 32 #define _PE_TX_DUMP_
33 #define _PE_RX_DUMP_ 33 #define _PE_RX_DUMP_
34 #define _PE_OID_DUMP_ 34 #define _PE_OID_DUMP_
35 #define _PE_DTO_DUMP_ 35 #define _PE_DTO_DUMP_
36 #define _PE_REG_DUMP_ 36 #define _PE_REG_DUMP_
37 #define _PE_USB_INI_DUMP_ 37 #define _PE_USB_INI_DUMP_
38 #endif 38 #endif
39 39
40
41
42 #include "common.h" // Individual file depends on OS
43
44 #include "../wb35_ver.h"
45 #include "../mac_structures.h"
46 #include "../ds_tkip.h"
47 #include "../localpara.h"
48 #include "../sme_s.h"
49 #include "../scan_s.h"
50 #include "../mds_s.h"
51 #include "../mlme_s.h"
52 #include "../bssdscpt.h"
53 #include "../sme_api.h"
54 #include "../gl_80211.h"
55 #include "../mto.h"
56 #include "../wbhal_s.h"
57
58
59 #include "../adapter.h"
60
61 #include "../mlme_mib.h"
62 #include "../mds_f.h"
63 #include "../bss_f.h"
64 #include "../mlmetxrx_f.h"
65 #include "../mto_f.h"
66 #include "../wbhal_f.h"
67 #include "../wblinux_f.h"
68 // Kernel Timer resolution, NDIS is 10ms, 10000us 40 // Kernel Timer resolution, NDIS is 10ms, 10000us
69 #define MIN_TIMEOUT_VAL (10) //ms 41 #define MIN_TIMEOUT_VAL (10) //ms
70
71 42
72 #endif 43 #endif
73 44
drivers/staging/winbond/linux/wb35reg.c
Diff comments   View file @ 80aba53
1 #include "sysdef.h" 1 #include "sysdef.h"
2 #include "wb35reg_f.h"
3
4 #include <linux/usb.h>
2 5
3 extern void phy_calibration_winbond(hw_data_t *phw_data, u32 frequency); 6 extern void phy_calibration_winbond(hw_data_t *phw_data, u32 frequency);
4 7
5 // true : read command process successfully 8 // true : read command process successfully
6 // false : register not support 9 // false : register not support
7 // RegisterNo : start base 10 // RegisterNo : start base
8 // pRegisterData : data point 11 // pRegisterData : data point
9 // NumberOfData : number of register data 12 // NumberOfData : number of register data
10 // Flag : AUTO_INCREMENT - RegisterNo will auto increment 4 13 // Flag : AUTO_INCREMENT - RegisterNo will auto increment 4
11 // NO_INCREMENT - Function will write data into the same register 14 // NO_INCREMENT - Function will write data into the same register
12 unsigned char 15 unsigned char
13 Wb35Reg_BurstWrite(phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterData, u8 NumberOfData, u8 Flag) 16 Wb35Reg_BurstWrite(phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterData, u8 NumberOfData, u8 Flag)
14 { 17 {
15 struct wb35_reg *reg = &pHwData->reg; 18 struct wb35_reg *reg = &pHwData->reg;
16 struct urb *urb = NULL; 19 struct urb *urb = NULL;
17 struct wb35_reg_queue *reg_queue = NULL; 20 struct wb35_reg_queue *reg_queue = NULL;
18 u16 UrbSize; 21 u16 UrbSize;
19 struct usb_ctrlrequest *dr; 22 struct usb_ctrlrequest *dr;
20 u16 i, DataSize = NumberOfData*4; 23 u16 i, DataSize = NumberOfData*4;
21 24
22 // Module shutdown 25 // Module shutdown
23 if (pHwData->SurpriseRemove) 26 if (pHwData->SurpriseRemove)
24 return false; 27 return false;
25 28
26 // Trying to use burst write function if use new hardware 29 // Trying to use burst write function if use new hardware
27 UrbSize = sizeof(struct wb35_reg_queue) + DataSize + sizeof(struct usb_ctrlrequest); 30 UrbSize = sizeof(struct wb35_reg_queue) + DataSize + sizeof(struct usb_ctrlrequest);
28 reg_queue = kzalloc(UrbSize, GFP_ATOMIC); 31 reg_queue = kzalloc(UrbSize, GFP_ATOMIC);
29 urb = usb_alloc_urb(0, GFP_ATOMIC); 32 urb = usb_alloc_urb(0, GFP_ATOMIC);
30 if( urb && reg_queue ) { 33 if( urb && reg_queue ) {
31 reg_queue->DIRECT = 2;// burst write register 34 reg_queue->DIRECT = 2;// burst write register
32 reg_queue->INDEX = RegisterNo; 35 reg_queue->INDEX = RegisterNo;
33 reg_queue->pBuffer = (u32 *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue)); 36 reg_queue->pBuffer = (u32 *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue));
34 memcpy( reg_queue->pBuffer, pRegisterData, DataSize ); 37 memcpy( reg_queue->pBuffer, pRegisterData, DataSize );
35 //the function for reversing register data from little endian to big endian 38 //the function for reversing register data from little endian to big endian
36 for( i=0; i<NumberOfData ; i++ ) 39 for( i=0; i<NumberOfData ; i++ )
37 reg_queue->pBuffer[i] = cpu_to_le32( reg_queue->pBuffer[i] ); 40 reg_queue->pBuffer[i] = cpu_to_le32( reg_queue->pBuffer[i] );
38 41
39 dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue) + DataSize); 42 dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue) + DataSize);
40 dr->bRequestType = USB_TYPE_VENDOR | USB_DIR_OUT | USB_RECIP_DEVICE; 43 dr->bRequestType = USB_TYPE_VENDOR | USB_DIR_OUT | USB_RECIP_DEVICE;
41 dr->bRequest = 0x04; // USB or vendor-defined request code, burst mode 44 dr->bRequest = 0x04; // USB or vendor-defined request code, burst mode
42 dr->wValue = cpu_to_le16( Flag ); // 0: Register number auto-increment, 1: No auto increment 45 dr->wValue = cpu_to_le16( Flag ); // 0: Register number auto-increment, 1: No auto increment
43 dr->wIndex = cpu_to_le16( RegisterNo ); 46 dr->wIndex = cpu_to_le16( RegisterNo );
44 dr->wLength = cpu_to_le16( DataSize ); 47 dr->wLength = cpu_to_le16( DataSize );
45 reg_queue->Next = NULL; 48 reg_queue->Next = NULL;
46 reg_queue->pUsbReq = dr; 49 reg_queue->pUsbReq = dr;
47 reg_queue->urb = urb; 50 reg_queue->urb = urb;
48 51
49 spin_lock_irq( &reg->EP0VM_spin_lock ); 52 spin_lock_irq( &reg->EP0VM_spin_lock );
50 if (reg->reg_first == NULL) 53 if (reg->reg_first == NULL)
51 reg->reg_first = reg_queue; 54 reg->reg_first = reg_queue;
52 else 55 else
53 reg->reg_last->Next = reg_queue; 56 reg->reg_last->Next = reg_queue;
54 reg->reg_last = reg_queue; 57 reg->reg_last = reg_queue;
55 58
56 spin_unlock_irq( &reg->EP0VM_spin_lock ); 59 spin_unlock_irq( &reg->EP0VM_spin_lock );
57 60
58 // Start EP0VM 61 // Start EP0VM
59 Wb35Reg_EP0VM_start(pHwData); 62 Wb35Reg_EP0VM_start(pHwData);
60 63
61 return true; 64 return true;
62 } else { 65 } else {
63 if (urb) 66 if (urb)
64 usb_free_urb(urb); 67 usb_free_urb(urb);
65 if (reg_queue) 68 if (reg_queue)
66 kfree(reg_queue); 69 kfree(reg_queue);
67 return false; 70 return false;
68 } 71 }
69 return false; 72 return false;
70 } 73 }
71 74
72 void 75 void
73 Wb35Reg_Update(phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue) 76 Wb35Reg_Update(phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue)
74 { 77 {
75 struct wb35_reg *reg = &pHwData->reg; 78 struct wb35_reg *reg = &pHwData->reg;
76 switch (RegisterNo) { 79 switch (RegisterNo) {
77 case 0x3b0: reg->U1B0 = RegisterValue; break; 80 case 0x3b0: reg->U1B0 = RegisterValue; break;
78 case 0x3bc: reg->U1BC_LEDConfigure = RegisterValue; break; 81 case 0x3bc: reg->U1BC_LEDConfigure = RegisterValue; break;
79 case 0x400: reg->D00_DmaControl = RegisterValue; break; 82 case 0x400: reg->D00_DmaControl = RegisterValue; break;
80 case 0x800: reg->M00_MacControl = RegisterValue; break; 83 case 0x800: reg->M00_MacControl = RegisterValue; break;
81 case 0x804: reg->M04_MulticastAddress1 = RegisterValue; break; 84 case 0x804: reg->M04_MulticastAddress1 = RegisterValue; break;
82 case 0x808: reg->M08_MulticastAddress2 = RegisterValue; break; 85 case 0x808: reg->M08_MulticastAddress2 = RegisterValue; break;
83 case 0x824: reg->M24_MacControl = RegisterValue; break; 86 case 0x824: reg->M24_MacControl = RegisterValue; break;
84 case 0x828: reg->M28_MacControl = RegisterValue; break; 87 case 0x828: reg->M28_MacControl = RegisterValue; break;
85 case 0x82c: reg->M2C_MacControl = RegisterValue; break; 88 case 0x82c: reg->M2C_MacControl = RegisterValue; break;
86 case 0x838: reg->M38_MacControl = RegisterValue; break; 89 case 0x838: reg->M38_MacControl = RegisterValue; break;
87 case 0x840: reg->M40_MacControl = RegisterValue; break; 90 case 0x840: reg->M40_MacControl = RegisterValue; break;
88 case 0x844: reg->M44_MacControl = RegisterValue; break; 91 case 0x844: reg->M44_MacControl = RegisterValue; break;
89 case 0x848: reg->M48_MacControl = RegisterValue; break; 92 case 0x848: reg->M48_MacControl = RegisterValue; break;
90 case 0x84c: reg->M4C_MacStatus = RegisterValue; break; 93 case 0x84c: reg->M4C_MacStatus = RegisterValue; break;
91 case 0x860: reg->M60_MacControl = RegisterValue; break; 94 case 0x860: reg->M60_MacControl = RegisterValue; break;
92 case 0x868: reg->M68_MacControl = RegisterValue; break; 95 case 0x868: reg->M68_MacControl = RegisterValue; break;
93 case 0x870: reg->M70_MacControl = RegisterValue; break; 96 case 0x870: reg->M70_MacControl = RegisterValue; break;
94 case 0x874: reg->M74_MacControl = RegisterValue; break; 97 case 0x874: reg->M74_MacControl = RegisterValue; break;
95 case 0x878: reg->M78_ERPInformation = RegisterValue; break; 98 case 0x878: reg->M78_ERPInformation = RegisterValue; break;
96 case 0x87C: reg->M7C_MacControl = RegisterValue; break; 99 case 0x87C: reg->M7C_MacControl = RegisterValue; break;
97 case 0x880: reg->M80_MacControl = RegisterValue; break; 100 case 0x880: reg->M80_MacControl = RegisterValue; break;
98 case 0x884: reg->M84_MacControl = RegisterValue; break; 101 case 0x884: reg->M84_MacControl = RegisterValue; break;
99 case 0x888: reg->M88_MacControl = RegisterValue; break; 102 case 0x888: reg->M88_MacControl = RegisterValue; break;
100 case 0x898: reg->M98_MacControl = RegisterValue; break; 103 case 0x898: reg->M98_MacControl = RegisterValue; break;
101 case 0x100c: reg->BB0C = RegisterValue; break; 104 case 0x100c: reg->BB0C = RegisterValue; break;
102 case 0x102c: reg->BB2C = RegisterValue; break; 105 case 0x102c: reg->BB2C = RegisterValue; break;
103 case 0x1030: reg->BB30 = RegisterValue; break; 106 case 0x1030: reg->BB30 = RegisterValue; break;
104 case 0x103c: reg->BB3C = RegisterValue; break; 107 case 0x103c: reg->BB3C = RegisterValue; break;
105 case 0x1048: reg->BB48 = RegisterValue; break; 108 case 0x1048: reg->BB48 = RegisterValue; break;
106 case 0x104c: reg->BB4C = RegisterValue; break; 109 case 0x104c: reg->BB4C = RegisterValue; break;
107 case 0x1050: reg->BB50 = RegisterValue; break; 110 case 0x1050: reg->BB50 = RegisterValue; break;
108 case 0x1054: reg->BB54 = RegisterValue; break; 111 case 0x1054: reg->BB54 = RegisterValue; break;
109 case 0x1058: reg->BB58 = RegisterValue; break; 112 case 0x1058: reg->BB58 = RegisterValue; break;
110 case 0x105c: reg->BB5C = RegisterValue; break; 113 case 0x105c: reg->BB5C = RegisterValue; break;
111 case 0x1060: reg->BB60 = RegisterValue; break; 114 case 0x1060: reg->BB60 = RegisterValue; break;
112 } 115 }
113 } 116 }
114 117
115 // true : read command process successfully 118 // true : read command process successfully
116 // false : register not support 119 // false : register not support
117 unsigned char 120 unsigned char
118 Wb35Reg_WriteSync( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue ) 121 Wb35Reg_WriteSync( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue )
119 { 122 {
120 struct wb35_reg *reg = &pHwData->reg; 123 struct wb35_reg *reg = &pHwData->reg;
121 int ret = -1; 124 int ret = -1;
122 125
123 // Module shutdown 126 // Module shutdown
124 if (pHwData->SurpriseRemove) 127 if (pHwData->SurpriseRemove)
125 return false; 128 return false;
126 129
127 RegisterValue = cpu_to_le32(RegisterValue); 130 RegisterValue = cpu_to_le32(RegisterValue);
128 131
129 // update the register by send usb message------------------------------------ 132 // update the register by send usb message------------------------------------
130 reg->SyncIoPause = 1; 133 reg->SyncIoPause = 1;
131 134
132 // 20060717.5 Wait until EP0VM stop 135 // 20060717.5 Wait until EP0VM stop
133 while (reg->EP0vm_state != VM_STOP) 136 while (reg->EP0vm_state != VM_STOP)
134 msleep(10); 137 msleep(10);
135 138
136 // Sync IoCallDriver 139 // Sync IoCallDriver
137 reg->EP0vm_state = VM_RUNNING; 140 reg->EP0vm_state = VM_RUNNING;
138 ret = usb_control_msg( pHwData->WbUsb.udev, 141 ret = usb_control_msg( pHwData->WbUsb.udev,
139 usb_sndctrlpipe( pHwData->WbUsb.udev, 0 ), 142 usb_sndctrlpipe( pHwData->WbUsb.udev, 0 ),
140 0x03, USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT, 143 0x03, USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT,
141 0x0,RegisterNo, &RegisterValue, 4, HZ*100 ); 144 0x0,RegisterNo, &RegisterValue, 4, HZ*100 );
142 reg->EP0vm_state = VM_STOP; 145 reg->EP0vm_state = VM_STOP;
143 reg->SyncIoPause = 0; 146 reg->SyncIoPause = 0;
144 147
145 Wb35Reg_EP0VM_start(pHwData); 148 Wb35Reg_EP0VM_start(pHwData);
146 149
147 if (ret < 0) { 150 if (ret < 0) {
148 #ifdef _PE_REG_DUMP_ 151 #ifdef _PE_REG_DUMP_
149 WBDEBUG(("EP0 Write register usb message sending error\n")); 152 WBDEBUG(("EP0 Write register usb message sending error\n"));
150 #endif 153 #endif
151 154
152 pHwData->SurpriseRemove = 1; // 20060704.2 155 pHwData->SurpriseRemove = 1; // 20060704.2
153 return false; 156 return false;
154 } 157 }
155 158
156 return true; 159 return true;
157 } 160 }
158 161
159 // true : read command process successfully 162 // true : read command process successfully
160 // false : register not support 163 // false : register not support
161 unsigned char 164 unsigned char
162 Wb35Reg_Write( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue ) 165 Wb35Reg_Write( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue )
163 { 166 {
164 struct wb35_reg *reg = &pHwData->reg; 167 struct wb35_reg *reg = &pHwData->reg;
165 struct usb_ctrlrequest *dr; 168 struct usb_ctrlrequest *dr;
166 struct urb *urb = NULL; 169 struct urb *urb = NULL;
167 struct wb35_reg_queue *reg_queue = NULL; 170 struct wb35_reg_queue *reg_queue = NULL;
168 u16 UrbSize; 171 u16 UrbSize;
169 172
170 173
171 // Module shutdown 174 // Module shutdown
172 if (pHwData->SurpriseRemove) 175 if (pHwData->SurpriseRemove)
173 return false; 176 return false;
174 177
175 // update the register by send urb request------------------------------------ 178 // update the register by send urb request------------------------------------
176 UrbSize = sizeof(struct wb35_reg_queue) + sizeof(struct usb_ctrlrequest); 179 UrbSize = sizeof(struct wb35_reg_queue) + sizeof(struct usb_ctrlrequest);
177 reg_queue = kzalloc(UrbSize, GFP_ATOMIC); 180 reg_queue = kzalloc(UrbSize, GFP_ATOMIC);
178 urb = usb_alloc_urb(0, GFP_ATOMIC); 181 urb = usb_alloc_urb(0, GFP_ATOMIC);
179 if (urb && reg_queue) { 182 if (urb && reg_queue) {
180 reg_queue->DIRECT = 1;// burst write register 183 reg_queue->DIRECT = 1;// burst write register
181 reg_queue->INDEX = RegisterNo; 184 reg_queue->INDEX = RegisterNo;
182 reg_queue->VALUE = cpu_to_le32(RegisterValue); 185 reg_queue->VALUE = cpu_to_le32(RegisterValue);
183 reg_queue->RESERVED_VALID = false; 186 reg_queue->RESERVED_VALID = false;
184 dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue)); 187 dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue));
185 dr->bRequestType = USB_TYPE_VENDOR|USB_DIR_OUT |USB_RECIP_DEVICE; 188 dr->bRequestType = USB_TYPE_VENDOR|USB_DIR_OUT |USB_RECIP_DEVICE;
186 dr->bRequest = 0x03; // USB or vendor-defined request code, burst mode 189 dr->bRequest = 0x03; // USB or vendor-defined request code, burst mode
187 dr->wValue = cpu_to_le16(0x0); 190 dr->wValue = cpu_to_le16(0x0);
188 dr->wIndex = cpu_to_le16(RegisterNo); 191 dr->wIndex = cpu_to_le16(RegisterNo);
189 dr->wLength = cpu_to_le16(4); 192 dr->wLength = cpu_to_le16(4);
190 193
191 // Enter the sending queue 194 // Enter the sending queue
192 reg_queue->Next = NULL; 195 reg_queue->Next = NULL;
193 reg_queue->pUsbReq = dr; 196 reg_queue->pUsbReq = dr;
194 reg_queue->urb = urb; 197 reg_queue->urb = urb;
195 198
196 spin_lock_irq(&reg->EP0VM_spin_lock ); 199 spin_lock_irq(&reg->EP0VM_spin_lock );
197 if (reg->reg_first == NULL) 200 if (reg->reg_first == NULL)
198 reg->reg_first = reg_queue; 201 reg->reg_first = reg_queue;
199 else 202 else
200 reg->reg_last->Next = reg_queue; 203 reg->reg_last->Next = reg_queue;
201 reg->reg_last = reg_queue; 204 reg->reg_last = reg_queue;
202 205
203 spin_unlock_irq( &reg->EP0VM_spin_lock ); 206 spin_unlock_irq( &reg->EP0VM_spin_lock );
204 207
205 // Start EP0VM 208 // Start EP0VM
206 Wb35Reg_EP0VM_start(pHwData); 209 Wb35Reg_EP0VM_start(pHwData);
207 210
208 return true; 211 return true;
209 } else { 212 } else {
210 if (urb) 213 if (urb)
211 usb_free_urb(urb); 214 usb_free_urb(urb);
212 kfree(reg_queue); 215 kfree(reg_queue);
213 return false; 216 return false;
214 } 217 }
215 } 218 }
216 219
217 //This command will be executed with a user defined value. When it completes, 220 //This command will be executed with a user defined value. When it completes,
218 //this value is useful. For example, hal_set_current_channel will use it. 221 //this value is useful. For example, hal_set_current_channel will use it.
219 // true : read command process successfully 222 // true : read command process successfully
220 // false : register not support 223 // false : register not support
221 unsigned char 224 unsigned char
222 Wb35Reg_WriteWithCallbackValue( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue, 225 Wb35Reg_WriteWithCallbackValue( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue,
223 s8 *pValue, s8 Len) 226 s8 *pValue, s8 Len)
224 { 227 {
225 struct wb35_reg *reg = &pHwData->reg; 228 struct wb35_reg *reg = &pHwData->reg;
226 struct usb_ctrlrequest *dr; 229 struct usb_ctrlrequest *dr;
227 struct urb *urb = NULL; 230 struct urb *urb = NULL;
228 struct wb35_reg_queue *reg_queue = NULL; 231 struct wb35_reg_queue *reg_queue = NULL;
229 u16 UrbSize; 232 u16 UrbSize;
230 233
231 // Module shutdown 234 // Module shutdown
232 if (pHwData->SurpriseRemove) 235 if (pHwData->SurpriseRemove)
233 return false; 236 return false;
234 237
235 // update the register by send urb request------------------------------------ 238 // update the register by send urb request------------------------------------
236 UrbSize = sizeof(struct wb35_reg_queue) + sizeof(struct usb_ctrlrequest); 239 UrbSize = sizeof(struct wb35_reg_queue) + sizeof(struct usb_ctrlrequest);
237 reg_queue = kzalloc(UrbSize, GFP_ATOMIC); 240 reg_queue = kzalloc(UrbSize, GFP_ATOMIC);
238 urb = usb_alloc_urb(0, GFP_ATOMIC); 241 urb = usb_alloc_urb(0, GFP_ATOMIC);
239 if (urb && reg_queue) { 242 if (urb && reg_queue) {
240 reg_queue->DIRECT = 1;// burst write register 243 reg_queue->DIRECT = 1;// burst write register
241 reg_queue->INDEX = RegisterNo; 244 reg_queue->INDEX = RegisterNo;
242 reg_queue->VALUE = cpu_to_le32(RegisterValue); 245 reg_queue->VALUE = cpu_to_le32(RegisterValue);
243 //NOTE : Users must guarantee the size of value will not exceed the buffer size. 246 //NOTE : Users must guarantee the size of value will not exceed the buffer size.
244 memcpy(reg_queue->RESERVED, pValue, Len); 247 memcpy(reg_queue->RESERVED, pValue, Len);
245 reg_queue->RESERVED_VALID = true; 248 reg_queue->RESERVED_VALID = true;
246 dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue)); 249 dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue));
247 dr->bRequestType = USB_TYPE_VENDOR|USB_DIR_OUT |USB_RECIP_DEVICE; 250 dr->bRequestType = USB_TYPE_VENDOR|USB_DIR_OUT |USB_RECIP_DEVICE;
248 dr->bRequest = 0x03; // USB or vendor-defined request code, burst mode 251 dr->bRequest = 0x03; // USB or vendor-defined request code, burst mode
249 dr->wValue = cpu_to_le16(0x0); 252 dr->wValue = cpu_to_le16(0x0);
250 dr->wIndex = cpu_to_le16(RegisterNo); 253 dr->wIndex = cpu_to_le16(RegisterNo);
251 dr->wLength = cpu_to_le16(4); 254 dr->wLength = cpu_to_le16(4);
252 255
253 // Enter the sending queue 256 // Enter the sending queue
254 reg_queue->Next = NULL; 257 reg_queue->Next = NULL;
255 reg_queue->pUsbReq = dr; 258 reg_queue->pUsbReq = dr;
256 reg_queue->urb = urb; 259 reg_queue->urb = urb;
257 spin_lock_irq (&reg->EP0VM_spin_lock ); 260 spin_lock_irq (&reg->EP0VM_spin_lock );
258 if( reg->reg_first == NULL ) 261 if( reg->reg_first == NULL )
259 reg->reg_first = reg_queue; 262 reg->reg_first = reg_queue;
260 else 263 else
261 reg->reg_last->Next = reg_queue; 264 reg->reg_last->Next = reg_queue;
262 reg->reg_last = reg_queue; 265 reg->reg_last = reg_queue;
263 266
264 spin_unlock_irq ( &reg->EP0VM_spin_lock ); 267 spin_unlock_irq ( &reg->EP0VM_spin_lock );
265 268
266 // Start EP0VM 269 // Start EP0VM
267 Wb35Reg_EP0VM_start(pHwData); 270 Wb35Reg_EP0VM_start(pHwData);
268 return true; 271 return true;
269 } else { 272 } else {
270 if (urb) 273 if (urb)
271 usb_free_urb(urb); 274 usb_free_urb(urb);
272 kfree(reg_queue); 275 kfree(reg_queue);
273 return false; 276 return false;
274 } 277 }
275 } 278 }
276 279
277 // true : read command process successfully 280 // true : read command process successfully
278 // false : register not support 281 // false : register not support
279 // pRegisterValue : It must be a resident buffer due to asynchronous read register. 282 // pRegisterValue : It must be a resident buffer due to asynchronous read register.
280 unsigned char 283 unsigned char
281 Wb35Reg_ReadSync( phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterValue ) 284 Wb35Reg_ReadSync( phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterValue )
282 { 285 {
283 struct wb35_reg *reg = &pHwData->reg; 286 struct wb35_reg *reg = &pHwData->reg;
284 u32 * pltmp = pRegisterValue; 287 u32 * pltmp = pRegisterValue;
285 int ret = -1; 288 int ret = -1;
286 289
287 // Module shutdown 290 // Module shutdown
288 if (pHwData->SurpriseRemove) 291 if (pHwData->SurpriseRemove)
289 return false; 292 return false;
290 293
291 // Read the register by send usb message------------------------------------ 294 // Read the register by send usb message------------------------------------
292 295
293 reg->SyncIoPause = 1; 296 reg->SyncIoPause = 1;
294 297
295 // 20060717.5 Wait until EP0VM stop 298 // 20060717.5 Wait until EP0VM stop
296 while (reg->EP0vm_state != VM_STOP) 299 while (reg->EP0vm_state != VM_STOP)
297 msleep(10); 300 msleep(10);
298 301
299 reg->EP0vm_state = VM_RUNNING; 302 reg->EP0vm_state = VM_RUNNING;
300 ret = usb_control_msg( pHwData->WbUsb.udev, 303 ret = usb_control_msg( pHwData->WbUsb.udev,
301 usb_rcvctrlpipe(pHwData->WbUsb.udev, 0), 304 usb_rcvctrlpipe(pHwData->WbUsb.udev, 0),
302 0x01, USB_TYPE_VENDOR|USB_RECIP_DEVICE|USB_DIR_IN, 305 0x01, USB_TYPE_VENDOR|USB_RECIP_DEVICE|USB_DIR_IN,
303 0x0, RegisterNo, pltmp, 4, HZ*100 ); 306 0x0, RegisterNo, pltmp, 4, HZ*100 );
304 307
305 *pRegisterValue = cpu_to_le32(*pltmp); 308 *pRegisterValue = cpu_to_le32(*pltmp);
306 309
307 reg->EP0vm_state = VM_STOP; 310 reg->EP0vm_state = VM_STOP;
308 311
309 Wb35Reg_Update( pHwData, RegisterNo, *pRegisterValue ); 312 Wb35Reg_Update( pHwData, RegisterNo, *pRegisterValue );
310 reg->SyncIoPause = 0; 313 reg->SyncIoPause = 0;
311 314
312 Wb35Reg_EP0VM_start( pHwData ); 315 Wb35Reg_EP0VM_start( pHwData );
313 316
314 if (ret < 0) { 317 if (ret < 0) {
315 #ifdef _PE_REG_DUMP_ 318 #ifdef _PE_REG_DUMP_
316 WBDEBUG(("EP0 Read register usb message sending error\n")); 319 WBDEBUG(("EP0 Read register usb message sending error\n"));
317 #endif 320 #endif
318 321
319 pHwData->SurpriseRemove = 1; // 20060704.2 322 pHwData->SurpriseRemove = 1; // 20060704.2
320 return false; 323 return false;
321 } 324 }
322 325
323 return true; 326 return true;
324 } 327 }
325 328
326 // true : read command process successfully 329 // true : read command process successfully
327 // false : register not support 330 // false : register not support
328 // pRegisterValue : It must be a resident buffer due to asynchronous read register. 331 // pRegisterValue : It must be a resident buffer due to asynchronous read register.
329 unsigned char 332 unsigned char
330 Wb35Reg_Read(phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterValue ) 333 Wb35Reg_Read(phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterValue )
331 { 334 {
332 struct wb35_reg *reg = &pHwData->reg; 335 struct wb35_reg *reg = &pHwData->reg;
333 struct usb_ctrlrequest * dr; 336 struct usb_ctrlrequest * dr;
334 struct urb *urb; 337 struct urb *urb;
335 struct wb35_reg_queue *reg_queue; 338 struct wb35_reg_queue *reg_queue;
336 u16 UrbSize; 339 u16 UrbSize;
337 340
338 // Module shutdown 341 // Module shutdown
339 if (pHwData->SurpriseRemove) 342 if (pHwData->SurpriseRemove)
340 return false; 343 return false;
341 344
342 // update the variable by send Urb to read register ------------------------------------ 345 // update the variable by send Urb to read register ------------------------------------
343 UrbSize = sizeof(struct wb35_reg_queue) + sizeof(struct usb_ctrlrequest); 346 UrbSize = sizeof(struct wb35_reg_queue) + sizeof(struct usb_ctrlrequest);
344 reg_queue = kzalloc(UrbSize, GFP_ATOMIC); 347 reg_queue = kzalloc(UrbSize, GFP_ATOMIC);
345 urb = usb_alloc_urb(0, GFP_ATOMIC); 348 urb = usb_alloc_urb(0, GFP_ATOMIC);
346 if( urb && reg_queue ) 349 if( urb && reg_queue )
347 { 350 {
348 reg_queue->DIRECT = 0;// read register 351 reg_queue->DIRECT = 0;// read register
349 reg_queue->INDEX = RegisterNo; 352 reg_queue->INDEX = RegisterNo;
350 reg_queue->pBuffer = pRegisterValue; 353 reg_queue->pBuffer = pRegisterValue;
351 dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue)); 354 dr = (struct usb_ctrlrequest *)((u8 *)reg_queue + sizeof(struct wb35_reg_queue));
352 dr->bRequestType = USB_TYPE_VENDOR|USB_RECIP_DEVICE|USB_DIR_IN; 355 dr->bRequestType = USB_TYPE_VENDOR|USB_RECIP_DEVICE|USB_DIR_IN;
353 dr->bRequest = 0x01; // USB or vendor-defined request code, burst mode 356 dr->bRequest = 0x01; // USB or vendor-defined request code, burst mode
354 dr->wValue = cpu_to_le16(0x0); 357 dr->wValue = cpu_to_le16(0x0);
355 dr->wIndex = cpu_to_le16 (RegisterNo); 358 dr->wIndex = cpu_to_le16 (RegisterNo);
356 dr->wLength = cpu_to_le16 (4); 359 dr->wLength = cpu_to_le16 (4);
357 360
358 // Enter the sending queue 361 // Enter the sending queue
359 reg_queue->Next = NULL; 362 reg_queue->Next = NULL;
360 reg_queue->pUsbReq = dr; 363 reg_queue->pUsbReq = dr;
361 reg_queue->urb = urb; 364 reg_queue->urb = urb;
362 spin_lock_irq ( &reg->EP0VM_spin_lock ); 365 spin_lock_irq ( &reg->EP0VM_spin_lock );
363 if( reg->reg_first == NULL ) 366 if( reg->reg_first == NULL )
364 reg->reg_first = reg_queue; 367 reg->reg_first = reg_queue;
365 else 368 else
366 reg->reg_last->Next = reg_queue; 369 reg->reg_last->Next = reg_queue;
367 reg->reg_last = reg_queue; 370 reg->reg_last = reg_queue;
368 371
369 spin_unlock_irq( &reg->EP0VM_spin_lock ); 372 spin_unlock_irq( &reg->EP0VM_spin_lock );
370 373
371 // Start EP0VM 374 // Start EP0VM
372 Wb35Reg_EP0VM_start( pHwData ); 375 Wb35Reg_EP0VM_start( pHwData );
373 376
374 return true; 377 return true;
375 } else { 378 } else {
376 if (urb) 379 if (urb)
377 usb_free_urb( urb ); 380 usb_free_urb( urb );
378 kfree(reg_queue); 381 kfree(reg_queue);
379 return false; 382 return false;
380 } 383 }
381 } 384 }
382 385
383 386
384 void 387 void
385 Wb35Reg_EP0VM_start( phw_data_t pHwData ) 388 Wb35Reg_EP0VM_start( phw_data_t pHwData )
386 { 389 {
387 struct wb35_reg *reg = &pHwData->reg; 390 struct wb35_reg *reg = &pHwData->reg;
388 391
389 if (atomic_inc_return(&reg->RegFireCount) == 1) { 392 if (atomic_inc_return(&reg->RegFireCount) == 1) {
390 reg->EP0vm_state = VM_RUNNING; 393 reg->EP0vm_state = VM_RUNNING;
391 Wb35Reg_EP0VM(pHwData); 394 Wb35Reg_EP0VM(pHwData);
392 } else 395 } else
393 atomic_dec(&reg->RegFireCount); 396 atomic_dec(&reg->RegFireCount);
394 } 397 }
395 398
396 void 399 void
397 Wb35Reg_EP0VM(phw_data_t pHwData ) 400 Wb35Reg_EP0VM(phw_data_t pHwData )
398 { 401 {
399 struct wb35_reg *reg = &pHwData->reg; 402 struct wb35_reg *reg = &pHwData->reg;
400 struct urb *urb; 403 struct urb *urb;
401 struct usb_ctrlrequest *dr; 404 struct usb_ctrlrequest *dr;
402 u32 * pBuffer; 405 u32 * pBuffer;
403 int ret = -1; 406 int ret = -1;
404 struct wb35_reg_queue *reg_queue; 407 struct wb35_reg_queue *reg_queue;
405 408
406 409
407 if (reg->SyncIoPause) 410 if (reg->SyncIoPause)
408 goto cleanup; 411 goto cleanup;
409 412
410 if (pHwData->SurpriseRemove) 413 if (pHwData->SurpriseRemove)
411 goto cleanup; 414 goto cleanup;
412 415
413 // Get the register data and send to USB through Irp 416 // Get the register data and send to USB through Irp
414 spin_lock_irq( &reg->EP0VM_spin_lock ); 417 spin_lock_irq( &reg->EP0VM_spin_lock );
415 reg_queue = reg->reg_first; 418 reg_queue = reg->reg_first;
416 spin_unlock_irq( &reg->EP0VM_spin_lock ); 419 spin_unlock_irq( &reg->EP0VM_spin_lock );
417 420
418 if (!reg_queue) 421 if (!reg_queue)
419 goto cleanup; 422 goto cleanup;
420 423
421 // Get an Urb, send it 424 // Get an Urb, send it
422 urb = (struct urb *)reg_queue->urb; 425 urb = (struct urb *)reg_queue->urb;
423 426
424 dr = reg_queue->pUsbReq; 427 dr = reg_queue->pUsbReq;
425 urb = reg_queue->urb; 428 urb = reg_queue->urb;
426 pBuffer = reg_queue->pBuffer; 429 pBuffer = reg_queue->pBuffer;
427 if (reg_queue->DIRECT == 1) // output 430 if (reg_queue->DIRECT == 1) // output
428 pBuffer = &reg_queue->VALUE; 431 pBuffer = &reg_queue->VALUE;
429 432
430 usb_fill_control_urb( urb, pHwData->WbUsb.udev, 433 usb_fill_control_urb( urb, pHwData->WbUsb.udev,
431 REG_DIRECTION(pHwData->WbUsb.udev,reg_queue), 434 REG_DIRECTION(pHwData->WbUsb.udev,reg_queue),
432 (u8 *)dr,pBuffer,cpu_to_le16(dr->wLength), 435 (u8 *)dr,pBuffer,cpu_to_le16(dr->wLength),
433 Wb35Reg_EP0VM_complete, (void*)pHwData); 436 Wb35Reg_EP0VM_complete, (void*)pHwData);
434 437
435 reg->EP0vm_state = VM_RUNNING; 438 reg->EP0vm_state = VM_RUNNING;
436 439
437 ret = usb_submit_urb(urb, GFP_ATOMIC); 440 ret = usb_submit_urb(urb, GFP_ATOMIC);
438 441
439 if (ret < 0) { 442 if (ret < 0) {
440 #ifdef _PE_REG_DUMP_ 443 #ifdef _PE_REG_DUMP_
441 WBDEBUG(("EP0 Irp sending error\n")); 444 WBDEBUG(("EP0 Irp sending error\n"));
442 #endif 445 #endif
443 goto cleanup; 446 goto cleanup;
444 } 447 }
445 448
446 return; 449 return;
447 450
448 cleanup: 451 cleanup:
449 reg->EP0vm_state = VM_STOP; 452 reg->EP0vm_state = VM_STOP;
450 atomic_dec(&reg->RegFireCount); 453 atomic_dec(&reg->RegFireCount);
451 } 454 }
452 455
453 456
454 void 457 void
455 Wb35Reg_EP0VM_complete(struct urb *urb) 458 Wb35Reg_EP0VM_complete(struct urb *urb)
456 { 459 {
457 phw_data_t pHwData = (phw_data_t)urb->context; 460 phw_data_t pHwData = (phw_data_t)urb->context;
458 struct wb35_reg *reg = &pHwData->reg; 461 struct wb35_reg *reg = &pHwData->reg;
459 struct wb35_reg_queue *reg_queue; 462 struct wb35_reg_queue *reg_queue;
460 463
461 464
462 // Variable setting 465 // Variable setting
463 reg->EP0vm_state = VM_COMPLETED; 466 reg->EP0vm_state = VM_COMPLETED;
464 reg->EP0VM_status = urb->status; 467 reg->EP0VM_status = urb->status;
465 468
466 if (pHwData->SurpriseRemove) { // Let WbWlanHalt to handle surprise remove 469 if (pHwData->SurpriseRemove) { // Let WbWlanHalt to handle surprise remove
467 reg->EP0vm_state = VM_STOP; 470 reg->EP0vm_state = VM_STOP;
468 atomic_dec(&reg->RegFireCount); 471 atomic_dec(&reg->RegFireCount);
469 } else { 472 } else {
470 // Complete to send, remove the URB from the first 473 // Complete to send, remove the URB from the first
471 spin_lock_irq( &reg->EP0VM_spin_lock ); 474 spin_lock_irq( &reg->EP0VM_spin_lock );
472 reg_queue = reg->reg_first; 475 reg_queue = reg->reg_first;
473 if (reg_queue == reg->reg_last) 476 if (reg_queue == reg->reg_last)
474 reg->reg_last = NULL; 477 reg->reg_last = NULL;
475 reg->reg_first = reg->reg_first->Next; 478 reg->reg_first = reg->reg_first->Next;
476 spin_unlock_irq( &reg->EP0VM_spin_lock ); 479 spin_unlock_irq( &reg->EP0VM_spin_lock );
477 480
478 if (reg->EP0VM_status) { 481 if (reg->EP0VM_status) {
479 #ifdef _PE_REG_DUMP_ 482 #ifdef _PE_REG_DUMP_
480 WBDEBUG(("EP0 IoCompleteRoutine return error\n")); 483 WBDEBUG(("EP0 IoCompleteRoutine return error\n"));
481 DebugUsbdStatusInformation( reg->EP0VM_status ); 484 DebugUsbdStatusInformation( reg->EP0VM_status );
482 #endif 485 #endif
483 reg->EP0vm_state = VM_STOP; 486 reg->EP0vm_state = VM_STOP;
484 pHwData->SurpriseRemove = 1; 487 pHwData->SurpriseRemove = 1;
485 } else { 488 } else {
486 // Success. Update the result 489 // Success. Update the result
487 490
488 // Start the next send 491 // Start the next send
489 Wb35Reg_EP0VM(pHwData); 492 Wb35Reg_EP0VM(pHwData);
490 } 493 }
491 494
492 kfree(reg_queue); 495 kfree(reg_queue);
493 } 496 }
494 497
495 usb_free_urb(urb); 498 usb_free_urb(urb);
496 } 499 }
497 500
498 501
499 void 502 void
500 Wb35Reg_destroy(phw_data_t pHwData) 503 Wb35Reg_destroy(phw_data_t pHwData)
501 { 504 {
502 struct wb35_reg *reg = &pHwData->reg; 505 struct wb35_reg *reg = &pHwData->reg;
503 struct urb *urb; 506 struct urb *urb;
504 struct wb35_reg_queue *reg_queue; 507 struct wb35_reg_queue *reg_queue;
505 508
506 509
507 Uxx_power_off_procedure(pHwData); 510 Uxx_power_off_procedure(pHwData);
508 511
509 // Wait for Reg operation completed 512 // Wait for Reg operation completed
510 do { 513 do {
511 msleep(10); // Delay for waiting function enter 940623.1.a 514 msleep(10); // Delay for waiting function enter 940623.1.a
512 } while (reg->EP0vm_state != VM_STOP); 515 } while (reg->EP0vm_state != VM_STOP);
513 msleep(10); // Delay for waiting function enter 940623.1.b 516 msleep(10); // Delay for waiting function enter 940623.1.b
514 517
515 // Release all the data in RegQueue 518 // Release all the data in RegQueue
516 spin_lock_irq(&reg->EP0VM_spin_lock); 519 spin_lock_irq(&reg->EP0VM_spin_lock);
517 reg_queue = reg->reg_first; 520 reg_queue = reg->reg_first;
518 while (reg_queue) { 521 while (reg_queue) {
519 if (reg_queue == reg->reg_last) 522 if (reg_queue == reg->reg_last)
520 reg->reg_last = NULL; 523 reg->reg_last = NULL;
521 reg->reg_first = reg->reg_first->Next; 524 reg->reg_first = reg->reg_first->Next;
522 525
523 urb = reg_queue->urb; 526 urb = reg_queue->urb;
524 spin_unlock_irq(&reg->EP0VM_spin_lock); 527 spin_unlock_irq(&reg->EP0VM_spin_lock);
525 if (urb) { 528 if (urb) {
526 usb_free_urb(urb); 529 usb_free_urb(urb);
527 kfree(reg_queue); 530 kfree(reg_queue);
528 } else { 531 } else {
529 #ifdef _PE_REG_DUMP_ 532 #ifdef _PE_REG_DUMP_
530 WBDEBUG(("EP0 queue release error\n")); 533 WBDEBUG(("EP0 queue release error\n"));
531 #endif 534 #endif
532 } 535 }
533 spin_lock_irq( &reg->EP0VM_spin_lock ); 536 spin_lock_irq( &reg->EP0VM_spin_lock );
534 537
535 reg_queue = reg->reg_first; 538 reg_queue = reg->reg_first;
536 } 539 }
537 spin_unlock_irq( &reg->EP0VM_spin_lock ); 540 spin_unlock_irq( &reg->EP0VM_spin_lock );
538 } 541 }
539 542
540 //==================================================================================== 543 //====================================================================================
541 // The function can be run in passive-level only. 544 // The function can be run in passive-level only.
542 //==================================================================================== 545 //====================================================================================
543 unsigned char Wb35Reg_initial(phw_data_t pHwData) 546 unsigned char Wb35Reg_initial(phw_data_t pHwData)
544 { 547 {
545 struct wb35_reg *reg=&pHwData->reg; 548 struct wb35_reg *reg=&pHwData->reg;
546 u32 ltmp; 549 u32 ltmp;
547 u32 SoftwareSet, VCO_trim, TxVga, Region_ScanInterval; 550 u32 SoftwareSet, VCO_trim, TxVga, Region_ScanInterval;
548 551
549 // Spin lock is acquired for read and write IRP command 552 // Spin lock is acquired for read and write IRP command
550 spin_lock_init( &reg->EP0VM_spin_lock ); 553 spin_lock_init( &reg->EP0VM_spin_lock );
551 554
552 // Getting RF module type from EEPROM ------------------------------------ 555 // Getting RF module type from EEPROM ------------------------------------
553 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x080d0000 ); // Start EEPROM access + Read + address(0x0d) 556 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x080d0000 ); // Start EEPROM access + Read + address(0x0d)
554 Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp ); 557 Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp );
555 558
556 //Update RF module type and determine the PHY type by inf or EEPROM 559 //Update RF module type and determine the PHY type by inf or EEPROM
557 reg->EEPROMPhyType = (u8)( ltmp & 0xff ); 560 reg->EEPROMPhyType = (u8)( ltmp & 0xff );
558 // 0 V MAX2825, 1 V MAX2827, 2 V MAX2828, 3 V MAX2829 561 // 0 V MAX2825, 1 V MAX2827, 2 V MAX2828, 3 V MAX2829
559 // 16V AL2230, 17 - AL7230, 18 - AL2230S 562 // 16V AL2230, 17 - AL7230, 18 - AL2230S
560 // 32 Reserved 563 // 32 Reserved
561 // 33 - W89RF242(TxVGA 0~19), 34 - W89RF242(TxVGA 0~34) 564 // 33 - W89RF242(TxVGA 0~19), 34 - W89RF242(TxVGA 0~34)
562 if (reg->EEPROMPhyType != RF_DECIDE_BY_INF) { 565 if (reg->EEPROMPhyType != RF_DECIDE_BY_INF) {
563 if( (reg->EEPROMPhyType == RF_MAXIM_2825) || 566 if( (reg->EEPROMPhyType == RF_MAXIM_2825) ||
564 (reg->EEPROMPhyType == RF_MAXIM_2827) || 567 (reg->EEPROMPhyType == RF_MAXIM_2827) ||
565 (reg->EEPROMPhyType == RF_MAXIM_2828) || 568 (reg->EEPROMPhyType == RF_MAXIM_2828) ||
566 (reg->EEPROMPhyType == RF_MAXIM_2829) || 569 (reg->EEPROMPhyType == RF_MAXIM_2829) ||
567 (reg->EEPROMPhyType == RF_MAXIM_V1) || 570 (reg->EEPROMPhyType == RF_MAXIM_V1) ||
568 (reg->EEPROMPhyType == RF_AIROHA_2230) || 571 (reg->EEPROMPhyType == RF_AIROHA_2230) ||
569 (reg->EEPROMPhyType == RF_AIROHA_2230S) || 572 (reg->EEPROMPhyType == RF_AIROHA_2230S) ||
570 (reg->EEPROMPhyType == RF_AIROHA_7230) || 573 (reg->EEPROMPhyType == RF_AIROHA_7230) ||
571 (reg->EEPROMPhyType == RF_WB_242) || 574 (reg->EEPROMPhyType == RF_WB_242) ||
572 (reg->EEPROMPhyType == RF_WB_242_1)) 575 (reg->EEPROMPhyType == RF_WB_242_1))
573 pHwData->phy_type = reg->EEPROMPhyType; 576 pHwData->phy_type = reg->EEPROMPhyType;
574 } 577 }
575 578
576 // Power On procedure running. The relative parameter will be set according to phy_type 579 // Power On procedure running. The relative parameter will be set according to phy_type
577 Uxx_power_on_procedure( pHwData ); 580 Uxx_power_on_procedure( pHwData );
578 581
579 // Reading MAC address 582 // Reading MAC address
580 Uxx_ReadEthernetAddress( pHwData ); 583 Uxx_ReadEthernetAddress( pHwData );
581 584
582 // Read VCO trim for RF parameter 585 // Read VCO trim for RF parameter
583 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08200000 ); 586 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08200000 );
584 Wb35Reg_ReadSync( pHwData, 0x03b4, &VCO_trim ); 587 Wb35Reg_ReadSync( pHwData, 0x03b4, &VCO_trim );
585 588
586 // Read Antenna On/Off of software flag 589 // Read Antenna On/Off of software flag
587 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08210000 ); 590 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08210000 );
588 Wb35Reg_ReadSync( pHwData, 0x03b4, &SoftwareSet ); 591 Wb35Reg_ReadSync( pHwData, 0x03b4, &SoftwareSet );
589 592
590 // Read TXVGA 593 // Read TXVGA
591 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08100000 ); 594 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08100000 );
592 Wb35Reg_ReadSync( pHwData, 0x03b4, &TxVga ); 595 Wb35Reg_ReadSync( pHwData, 0x03b4, &TxVga );
593 596
594 // Get Scan interval setting from EEPROM offset 0x1c 597 // Get Scan interval setting from EEPROM offset 0x1c
595 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x081d0000 ); 598 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x081d0000 );
596 Wb35Reg_ReadSync( pHwData, 0x03b4, &Region_ScanInterval ); 599 Wb35Reg_ReadSync( pHwData, 0x03b4, &Region_ScanInterval );
597 600
598 // Update Ethernet address 601 // Update Ethernet address
599 memcpy( pHwData->CurrentMacAddress, pHwData->PermanentMacAddress, ETH_LENGTH_OF_ADDRESS ); 602 memcpy( pHwData->CurrentMacAddress, pHwData->PermanentMacAddress, ETH_LENGTH_OF_ADDRESS );
600 603
601 // Update software variable 604 // Update software variable
602 pHwData->SoftwareSet = (u16)(SoftwareSet & 0xffff); 605 pHwData->SoftwareSet = (u16)(SoftwareSet & 0xffff);
603 TxVga &= 0x000000ff; 606 TxVga &= 0x000000ff;
604 pHwData->PowerIndexFromEEPROM = (u8)TxVga; 607 pHwData->PowerIndexFromEEPROM = (u8)TxVga;
605 pHwData->VCO_trim = (u8)VCO_trim & 0xff; 608 pHwData->VCO_trim = (u8)VCO_trim & 0xff;
606 if (pHwData->VCO_trim == 0xff) 609 if (pHwData->VCO_trim == 0xff)
607 pHwData->VCO_trim = 0x28; 610 pHwData->VCO_trim = 0x28;
608 611
609 reg->EEPROMRegion = (u8)(Region_ScanInterval>>8); // 20060720 612 reg->EEPROMRegion = (u8)(Region_ScanInterval>>8); // 20060720
610 if( reg->EEPROMRegion<1 || reg->EEPROMRegion>6 ) 613 if( reg->EEPROMRegion<1 || reg->EEPROMRegion>6 )
611 reg->EEPROMRegion = REGION_AUTO; 614 reg->EEPROMRegion = REGION_AUTO;
612 615
613 //For Get Tx VGA from EEPROM 20060315.5 move here 616 //For Get Tx VGA from EEPROM 20060315.5 move here
614 GetTxVgaFromEEPROM( pHwData ); 617 GetTxVgaFromEEPROM( pHwData );
615 618
616 // Set Scan Interval 619 // Set Scan Interval
617 pHwData->Scan_Interval = (u8)(Region_ScanInterval & 0xff) * 10; 620 pHwData->Scan_Interval = (u8)(Region_ScanInterval & 0xff) * 10;
618 if ((pHwData->Scan_Interval == 2550) || (pHwData->Scan_Interval < 10)) // Is default setting 0xff * 10 621 if ((pHwData->Scan_Interval == 2550) || (pHwData->Scan_Interval < 10)) // Is default setting 0xff * 10
619 pHwData->Scan_Interval = SCAN_MAX_CHNL_TIME; 622 pHwData->Scan_Interval = SCAN_MAX_CHNL_TIME;
620 623
621 // Initial register 624 // Initial register
622 RFSynthesizer_initial(pHwData); 625 RFSynthesizer_initial(pHwData);
623 626
624 BBProcessor_initial(pHwData); // Async write, must wait until complete 627 BBProcessor_initial(pHwData); // Async write, must wait until complete
625 628
626 Wb35Reg_phy_calibration(pHwData); 629 Wb35Reg_phy_calibration(pHwData);
627 630
628 Mxx_initial(pHwData); 631 Mxx_initial(pHwData);
629 Dxx_initial(pHwData); 632 Dxx_initial(pHwData);
630 633
631 if (pHwData->SurpriseRemove) 634 if (pHwData->SurpriseRemove)
632 return false; 635 return false;
633 else 636 else
634 return true; // Initial fail 637 return true; // Initial fail
635 } 638 }
636 639
637 //=================================================================================== 640 //===================================================================================
638 // CardComputeCrc -- 641 // CardComputeCrc --
639 // 642 //
640 // Description: 643 // Description:
641 // Runs the AUTODIN II CRC algorithm on buffer Buffer of length, Length. 644 // Runs the AUTODIN II CRC algorithm on buffer Buffer of length, Length.
642 // 645 //
643 // Arguments: 646 // Arguments:
644 // Buffer - the input buffer 647 // Buffer - the input buffer
645 // Length - the length of Buffer 648 // Length - the length of Buffer
646 // 649 //
647 // Return Value: 650 // Return Value:
648 // The 32-bit CRC value. 651 // The 32-bit CRC value.
649 // 652 //
650 // Note: 653 // Note:
651 // This is adapted from the comments in the assembly language 654 // This is adapted from the comments in the assembly language
652 // version in _GENREQ.ASM of the DWB NE1000/2000 driver. 655 // version in _GENREQ.ASM of the DWB NE1000/2000 driver.
653 //================================================================================== 656 //==================================================================================
654 u32 657 u32
655 CardComputeCrc(u8 * Buffer, u32 Length) 658 CardComputeCrc(u8 * Buffer, u32 Length)
656 { 659 {
657 u32 Crc, Carry; 660 u32 Crc, Carry;
658 u32 i, j; 661 u32 i, j;
659 u8 CurByte; 662 u8 CurByte;
660 663
661 Crc = 0xffffffff; 664 Crc = 0xffffffff;
662 665
663 for (i = 0; i < Length; i++) { 666 for (i = 0; i < Length; i++) {
664 667
665 CurByte = Buffer[i]; 668 CurByte = Buffer[i];
666 669
667 for (j = 0; j < 8; j++) { 670 for (j = 0; j < 8; j++) {
668 671
669 Carry = ((Crc & 0x80000000) ? 1 : 0) ^ (CurByte & 0x01); 672 Carry = ((Crc & 0x80000000) ? 1 : 0) ^ (CurByte & 0x01);
670 Crc <<= 1; 673 Crc <<= 1;
671 CurByte >>= 1; 674 CurByte >>= 1;
672 675
673 if (Carry) { 676 if (Carry) {
674 Crc =(Crc ^ 0x04c11db6) | Carry; 677 Crc =(Crc ^ 0x04c11db6) | Carry;
675 } 678 }
676 } 679 }
677 } 680 }
678 681
679 return Crc; 682 return Crc;
680 } 683 }
681 684
682 685
683 //================================================================== 686 //==================================================================
684 // BitReverse -- 687 // BitReverse --
685 // Reverse the bits in the input argument, dwData, which is 688 // Reverse the bits in the input argument, dwData, which is
686 // regarded as a string of bits with the length, DataLength. 689 // regarded as a string of bits with the length, DataLength.
687 // 690 //
688 // Arguments: 691 // Arguments:
689 // dwData : 692 // dwData :
690 // DataLength : 693 // DataLength :
691 // 694 //
692 // Return: 695 // Return:
693 // The converted value. 696 // The converted value.
694 //================================================================== 697 //==================================================================
695 u32 BitReverse( u32 dwData, u32 DataLength) 698 u32 BitReverse( u32 dwData, u32 DataLength)
696 { 699 {
697 u32 HalfLength, i, j; 700 u32 HalfLength, i, j;
698 u32 BitA, BitB; 701 u32 BitA, BitB;
699 702
700 if ( DataLength <= 0) return 0; // No conversion is done. 703 if ( DataLength <= 0) return 0; // No conversion is done.
701 dwData = dwData & (0xffffffff >> (32 - DataLength)); 704 dwData = dwData & (0xffffffff >> (32 - DataLength));
702 705
703 HalfLength = DataLength / 2; 706 HalfLength = DataLength / 2;
704 for ( i = 0, j = DataLength-1 ; i < HalfLength; i++, j--) 707 for ( i = 0, j = DataLength-1 ; i < HalfLength; i++, j--)
705 { 708 {
706 BitA = GetBit( dwData, i); 709 BitA = GetBit( dwData, i);
707 BitB = GetBit( dwData, j); 710 BitB = GetBit( dwData, j);
708 if (BitA && !BitB) { 711 if (BitA && !BitB) {
709 dwData = ClearBit( dwData, i); 712 dwData = ClearBit( dwData, i);
710 dwData = SetBit( dwData, j); 713 dwData = SetBit( dwData, j);
711 } else if (!BitA && BitB) { 714 } else if (!BitA && BitB) {
712 dwData = SetBit( dwData, i); 715 dwData = SetBit( dwData, i);
713 dwData = ClearBit( dwData, j); 716 dwData = ClearBit( dwData, j);
714 } else 717 } else
715 { 718 {
716 // Do nothing since these two bits are of the save values. 719 // Do nothing since these two bits are of the save values.
717 } 720 }
718 } 721 }
719 722
720 return dwData; 723 return dwData;
721 } 724 }
722 725
723 void Wb35Reg_phy_calibration( phw_data_t pHwData ) 726 void Wb35Reg_phy_calibration( phw_data_t pHwData )
724 { 727 {
725 u32 BB3c, BB54; 728 u32 BB3c, BB54;
726 729
727 if ((pHwData->phy_type == RF_WB_242) || 730 if ((pHwData->phy_type == RF_WB_242) ||
728 (pHwData->phy_type == RF_WB_242_1)) { 731 (pHwData->phy_type == RF_WB_242_1)) {
729 phy_calibration_winbond ( pHwData, 2412 ); // Sync operation 732 phy_calibration_winbond ( pHwData, 2412 ); // Sync operation
730 Wb35Reg_ReadSync( pHwData, 0x103c, &BB3c ); 733 Wb35Reg_ReadSync( pHwData, 0x103c, &BB3c );
731 Wb35Reg_ReadSync( pHwData, 0x1054, &BB54 ); 734 Wb35Reg_ReadSync( pHwData, 0x1054, &BB54 );
732 735
733 pHwData->BB3c_cal = BB3c; 736 pHwData->BB3c_cal = BB3c;
734 pHwData->BB54_cal = BB54; 737 pHwData->BB54_cal = BB54;
735 738
736 RFSynthesizer_initial(pHwData); 739 RFSynthesizer_initial(pHwData);
737 BBProcessor_initial(pHwData); // Async operation 740 BBProcessor_initial(pHwData); // Async operation
738 741
739 Wb35Reg_WriteSync( pHwData, 0x103c, BB3c ); 742 Wb35Reg_WriteSync( pHwData, 0x103c, BB3c );
740 Wb35Reg_WriteSync( pHwData, 0x1054, BB54 ); 743 Wb35Reg_WriteSync( pHwData, 0x1054, BB54 );
741 } 744 }
742 } 745 }
743 746
744 747
745 748
drivers/staging/winbond/linux/wb35reg_f.h
Diff comments   View file @ 80aba53
1 #ifndef __WINBOND_WB35REG_F_H
2 #define __WINBOND_WB35REG_F_H
3
4 #include "../wbhal_s.h"
5
1 //==================================== 6 //====================================
2 // Interface function declare 7 // Interface function declare
3 //==================================== 8 //====================================
4 unsigned char Wb35Reg_initial( phw_data_t pHwData ); 9 unsigned char Wb35Reg_initial( phw_data_t pHwData );
5 void Uxx_power_on_procedure( phw_data_t pHwData ); 10 void Uxx_power_on_procedure( phw_data_t pHwData );
6 void Uxx_power_off_procedure( phw_data_t pHwData ); 11 void Uxx_power_off_procedure( phw_data_t pHwData );
7 void Uxx_ReadEthernetAddress( phw_data_t pHwData ); 12 void Uxx_ReadEthernetAddress( phw_data_t pHwData );
8 void Dxx_initial( phw_data_t pHwData ); 13 void Dxx_initial( phw_data_t pHwData );
9 void Mxx_initial( phw_data_t pHwData ); 14 void Mxx_initial( phw_data_t pHwData );
10 void RFSynthesizer_initial( phw_data_t pHwData ); 15 void RFSynthesizer_initial( phw_data_t pHwData );
11 //void RFSynthesizer_SwitchingChannel( phw_data_t pHwData, s8 Channel ); 16 //void RFSynthesizer_SwitchingChannel( phw_data_t pHwData, s8 Channel );
12 void RFSynthesizer_SwitchingChannel( phw_data_t pHwData, ChanInfo Channel ); 17 void RFSynthesizer_SwitchingChannel( phw_data_t pHwData, ChanInfo Channel );
13 void BBProcessor_initial( phw_data_t pHwData ); 18 void BBProcessor_initial( phw_data_t pHwData );
14 void BBProcessor_RateChanging( phw_data_t pHwData, u8 rate ); // 20060613.1 19 void BBProcessor_RateChanging( phw_data_t pHwData, u8 rate ); // 20060613.1
15 //void RF_RateChanging( phw_data_t pHwData, u8 rate ); // 20060626.5.c Add 20 //void RF_RateChanging( phw_data_t pHwData, u8 rate ); // 20060626.5.c Add
16 u8 RFSynthesizer_SetPowerIndex( phw_data_t pHwData, u8 PowerIndex ); 21 u8 RFSynthesizer_SetPowerIndex( phw_data_t pHwData, u8 PowerIndex );
17 u8 RFSynthesizer_SetMaxim2828_24Power( phw_data_t, u8 index ); 22 u8 RFSynthesizer_SetMaxim2828_24Power( phw_data_t, u8 index );
18 u8 RFSynthesizer_SetMaxim2828_50Power( phw_data_t, u8 index ); 23 u8 RFSynthesizer_SetMaxim2828_50Power( phw_data_t, u8 index );
19 u8 RFSynthesizer_SetMaxim2827_24Power( phw_data_t, u8 index ); 24 u8 RFSynthesizer_SetMaxim2827_24Power( phw_data_t, u8 index );
20 u8 RFSynthesizer_SetMaxim2827_50Power( phw_data_t, u8 index ); 25 u8 RFSynthesizer_SetMaxim2827_50Power( phw_data_t, u8 index );
21 u8 RFSynthesizer_SetMaxim2825Power( phw_data_t, u8 index ); 26 u8 RFSynthesizer_SetMaxim2825Power( phw_data_t, u8 index );
22 u8 RFSynthesizer_SetAiroha2230Power( phw_data_t, u8 index ); 27 u8 RFSynthesizer_SetAiroha2230Power( phw_data_t, u8 index );
23 u8 RFSynthesizer_SetAiroha7230Power( phw_data_t, u8 index ); 28 u8 RFSynthesizer_SetAiroha7230Power( phw_data_t, u8 index );
24 u8 RFSynthesizer_SetWinbond242Power( phw_data_t, u8 index ); 29 u8 RFSynthesizer_SetWinbond242Power( phw_data_t, u8 index );
25 void GetTxVgaFromEEPROM( phw_data_t pHwData ); 30 void GetTxVgaFromEEPROM( phw_data_t pHwData );
26 void EEPROMTxVgaAdjust( phw_data_t pHwData ); // 20060619.5 Add 31 void EEPROMTxVgaAdjust( phw_data_t pHwData ); // 20060619.5 Add
27 32
28 #define RFWriteControlData( _A, _V ) Wb35Reg_Write( _A, 0x0864, _V ) 33 #define RFWriteControlData( _A, _V ) Wb35Reg_Write( _A, 0x0864, _V )
29 34
30 void Wb35Reg_destroy( phw_data_t pHwData ); 35 void Wb35Reg_destroy( phw_data_t pHwData );
31 36
32 unsigned char Wb35Reg_Read( phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterValue ); 37 unsigned char Wb35Reg_Read( phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterValue );
33 unsigned char Wb35Reg_ReadSync( phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterValue ); 38 unsigned char Wb35Reg_ReadSync( phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterValue );
34 unsigned char Wb35Reg_Write( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue ); 39 unsigned char Wb35Reg_Write( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue );
35 unsigned char Wb35Reg_WriteSync( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue ); 40 unsigned char Wb35Reg_WriteSync( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue );
36 unsigned char Wb35Reg_WriteWithCallbackValue( phw_data_t pHwData, 41 unsigned char Wb35Reg_WriteWithCallbackValue( phw_data_t pHwData,
37 u16 RegisterNo, 42 u16 RegisterNo,
38 u32 RegisterValue, 43 u32 RegisterValue,
39 s8 *pValue, 44 s8 *pValue,
40 s8 Len); 45 s8 Len);
41 unsigned char Wb35Reg_BurstWrite( phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterData, u8 NumberOfData, u8 Flag ); 46 unsigned char Wb35Reg_BurstWrite( phw_data_t pHwData, u16 RegisterNo, u32 * pRegisterData, u8 NumberOfData, u8 Flag );
42 47
43 void Wb35Reg_EP0VM( phw_data_t pHwData ); 48 void Wb35Reg_EP0VM( phw_data_t pHwData );
44 void Wb35Reg_EP0VM_start( phw_data_t pHwData ); 49 void Wb35Reg_EP0VM_start( phw_data_t pHwData );
45 void Wb35Reg_EP0VM_complete(struct urb *urb); 50 void Wb35Reg_EP0VM_complete(struct urb *urb);
46 51
47 u32 BitReverse( u32 dwData, u32 DataLength); 52 u32 BitReverse( u32 dwData, u32 DataLength);
48 53
49 void CardGetMulticastBit( u8 Address[MAC_ADDR_LENGTH], u8 *Byte, u8 *Value ); 54 void CardGetMulticastBit( u8 Address[MAC_ADDR_LENGTH], u8 *Byte, u8 *Value );
50 u32 CardComputeCrc( u8 * Buffer, u32 Length ); 55 u32 CardComputeCrc( u8 * Buffer, u32 Length );
51 56
52 void Wb35Reg_phy_calibration( phw_data_t pHwData ); 57 void Wb35Reg_phy_calibration( phw_data_t pHwData );
53 void Wb35Reg_Update( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue ); 58 void Wb35Reg_Update( phw_data_t pHwData, u16 RegisterNo, u32 RegisterValue );
54 unsigned char adjust_TXVGA_for_iq_mag( phw_data_t pHwData ); 59 unsigned char adjust_TXVGA_for_iq_mag( phw_data_t pHwData );
60
61 #endif
55 62
drivers/staging/winbond/linux/wb35reg_s.h
Diff comments   View file @ 80aba53
1 #ifndef __WINBOND_WB35REG_S_H
2 #define __WINBOND_WB35REG_S_H
3
4 #include <linux/spinlock.h>
5 #include <linux/types.h>
6 #include <asm/atomic.h>
7
1 //======================================================================================= 8 //=======================================================================================
2 /* 9 /*
3 HAL setting function 10 HAL setting function
4 11
5 ======================================== 12 ========================================
6 |Uxx| |Dxx| |Mxx| |BB| |RF| 13 |Uxx| |Dxx| |Mxx| |BB| |RF|
7 ======================================== 14 ========================================
8 | | 15 | |
9 Wb35Reg_Read Wb35Reg_Write 16 Wb35Reg_Read Wb35Reg_Write
10 17
11 ---------------------------------------- 18 ----------------------------------------
12 WbUsb_CallUSBDASync supplied By WbUsb module 19 WbUsb_CallUSBDASync supplied By WbUsb module
13 */ 20 */
14 //======================================================================================= 21 //=======================================================================================
15 22
16 #define GetBit( dwData, i) ( dwData & (0x00000001 << i)) 23 #define GetBit( dwData, i) ( dwData & (0x00000001 << i))
17 #define SetBit( dwData, i) ( dwData | (0x00000001 << i)) 24 #define SetBit( dwData, i) ( dwData | (0x00000001 << i))
18 #define ClearBit( dwData, i) ( dwData & ~(0x00000001 << i)) 25 #define ClearBit( dwData, i) ( dwData & ~(0x00000001 << i))
19 26
20 #define IGNORE_INCREMENT 0 27 #define IGNORE_INCREMENT 0
21 #define AUTO_INCREMENT 0 28 #define AUTO_INCREMENT 0
22 #define NO_INCREMENT 1 29 #define NO_INCREMENT 1
23 #define REG_DIRECTION(_x,_y) ((_y)->DIRECT ==0 ? usb_rcvctrlpipe(_x,0) : usb_sndctrlpipe(_x,0)) 30 #define REG_DIRECTION(_x,_y) ((_y)->DIRECT ==0 ? usb_rcvctrlpipe(_x,0) : usb_sndctrlpipe(_x,0))
24 #define REG_BUF_SIZE(_x) ((_x)->bRequest== 0x04 ? cpu_to_le16((_x)->wLength) : 4) 31 #define REG_BUF_SIZE(_x) ((_x)->bRequest== 0x04 ? cpu_to_le16((_x)->wLength) : 4)
25 32
26 // 20060613.2 Add the follow definition 33 // 20060613.2 Add the follow definition
27 #define BB48_DEFAULT_AL2230_11B 0x0033447c 34 #define BB48_DEFAULT_AL2230_11B 0x0033447c
28 #define BB4C_DEFAULT_AL2230_11B 0x0A00FEFF 35 #define BB4C_DEFAULT_AL2230_11B 0x0A00FEFF
29 #define BB48_DEFAULT_AL2230_11G 0x00332C1B 36 #define BB48_DEFAULT_AL2230_11G 0x00332C1B
30 #define BB4C_DEFAULT_AL2230_11G 0x0A00FEFF 37 #define BB4C_DEFAULT_AL2230_11G 0x0A00FEFF
31 38
32 39
33 #define BB48_DEFAULT_WB242_11B 0x00292315 //backoff 2dB 40 #define BB48_DEFAULT_WB242_11B 0x00292315 //backoff 2dB
34 #define BB4C_DEFAULT_WB242_11B 0x0800FEFF //backoff 2dB 41 #define BB4C_DEFAULT_WB242_11B 0x0800FEFF //backoff 2dB
35 //#define BB48_DEFAULT_WB242_11B 0x00201B11 //backoff 4dB 42 //#define BB48_DEFAULT_WB242_11B 0x00201B11 //backoff 4dB
36 //#define BB4C_DEFAULT_WB242_11B 0x0600FF00 //backoff 4dB 43 //#define BB4C_DEFAULT_WB242_11B 0x0600FF00 //backoff 4dB
37 #define BB48_DEFAULT_WB242_11G 0x00453B24 44 #define BB48_DEFAULT_WB242_11G 0x00453B24
38 #define BB4C_DEFAULT_WB242_11G 0x0E00FEFF 45 #define BB4C_DEFAULT_WB242_11G 0x0E00FEFF
39 46
40 //==================================== 47 //====================================
41 // Default setting for Mxx 48 // Default setting for Mxx
42 //==================================== 49 //====================================
43 #define DEFAULT_CWMIN 31 //(M2C) CWmin. Its value is in the range 0-31. 50 #define DEFAULT_CWMIN 31 //(M2C) CWmin. Its value is in the range 0-31.
44 #define DEFAULT_CWMAX 1023 //(M2C) CWmax. Its value is in the range 0-1023. 51 #define DEFAULT_CWMAX 1023 //(M2C) CWmax. Its value is in the range 0-1023.
45 #define DEFAULT_AID 1 //(M34) AID. Its value is in the range 1-2007. 52 #define DEFAULT_AID 1 //(M34) AID. Its value is in the range 1-2007.
46 53
47 #ifdef _USE_FALLBACK_RATE_ 54 #ifdef _USE_FALLBACK_RATE_
48 #define DEFAULT_RATE_RETRY_LIMIT 2 //(M38) as named 55 #define DEFAULT_RATE_RETRY_LIMIT 2 //(M38) as named
49 #else 56 #else
50 #define DEFAULT_RATE_RETRY_LIMIT 7 //(M38) as named 57 #define DEFAULT_RATE_RETRY_LIMIT 7 //(M38) as named
51 #endif 58 #endif
52 59
53 #define DEFAULT_LONG_RETRY_LIMIT 7 //(M38) LongRetryLimit. Its value is in the range 0-15. 60 #define DEFAULT_LONG_RETRY_LIMIT 7 //(M38) LongRetryLimit. Its value is in the range 0-15.
54 #define DEFAULT_SHORT_RETRY_LIMIT 7 //(M38) ShortRetryLimit. Its value is in the range 0-15. 61 #define DEFAULT_SHORT_RETRY_LIMIT 7 //(M38) ShortRetryLimit. Its value is in the range 0-15.
55 #define DEFAULT_PIFST 25 //(M3C) PIFS Time. Its value is in the range 0-65535. 62 #define DEFAULT_PIFST 25 //(M3C) PIFS Time. Its value is in the range 0-65535.
56 #define DEFAULT_EIFST 354 //(M3C) EIFS Time. Its value is in the range 0-1048575. 63 #define DEFAULT_EIFST 354 //(M3C) EIFS Time. Its value is in the range 0-1048575.
57 #define DEFAULT_DIFST 45 //(M3C) DIFS Time. Its value is in the range 0-65535. 64 #define DEFAULT_DIFST 45 //(M3C) DIFS Time. Its value is in the range 0-65535.
58 #define DEFAULT_SIFST 5 //(M3C) SIFS Time. Its value is in the range 0-65535. 65 #define DEFAULT_SIFST 5 //(M3C) SIFS Time. Its value is in the range 0-65535.
59 #define DEFAULT_OSIFST 10 //(M3C) Original SIFS Time. Its value is in the range 0-15. 66 #define DEFAULT_OSIFST 10 //(M3C) Original SIFS Time. Its value is in the range 0-15.
60 #define DEFAULT_ATIMWD 0 //(M40) ATIM Window. Its value is in the range 0-65535. 67 #define DEFAULT_ATIMWD 0 //(M40) ATIM Window. Its value is in the range 0-65535.
61 #define DEFAULT_SLOT_TIME 20 //(M40) ($) SlotTime. Its value is in the range 0-255. 68 #define DEFAULT_SLOT_TIME 20 //(M40) ($) SlotTime. Its value is in the range 0-255.
62 #define DEFAULT_MAX_TX_MSDU_LIFE_TIME 512 //(M44) MaxTxMSDULifeTime. Its value is in the range 0-4294967295. 69 #define DEFAULT_MAX_TX_MSDU_LIFE_TIME 512 //(M44) MaxTxMSDULifeTime. Its value is in the range 0-4294967295.
63 #define DEFAULT_BEACON_INTERVAL 500 //(M48) Beacon Interval. Its value is in the range 0-65535. 70 #define DEFAULT_BEACON_INTERVAL 500 //(M48) Beacon Interval. Its value is in the range 0-65535.
64 #define DEFAULT_PROBE_DELAY_TIME 200 //(M48) Probe Delay Time. Its value is in the range 0-65535. 71 #define DEFAULT_PROBE_DELAY_TIME 200 //(M48) Probe Delay Time. Its value is in the range 0-65535.
65 #define DEFAULT_PROTOCOL_VERSION 0 //(M4C) 72 #define DEFAULT_PROTOCOL_VERSION 0 //(M4C)
66 #define DEFAULT_MAC_POWER_STATE 2 //(M4C) 2: MAC at power active 73 #define DEFAULT_MAC_POWER_STATE 2 //(M4C) 2: MAC at power active
67 #define DEFAULT_DTIM_ALERT_TIME 0 74 #define DEFAULT_DTIM_ALERT_TIME 0
68 75
69 76
70 struct wb35_reg_queue { 77 struct wb35_reg_queue {
71 struct urb *urb; 78 struct urb *urb;
72 void *pUsbReq; 79 void *pUsbReq;
73 void *Next; 80 void *Next;
74 union { 81 union {
75 u32 VALUE; 82 u32 VALUE;
76 u32 *pBuffer; 83 u32 *pBuffer;
77 }; 84 };
78 u8 RESERVED[4]; // space reserved for communication 85 u8 RESERVED[4]; // space reserved for communication
79 u16 INDEX; // For storing the register index 86 u16 INDEX; // For storing the register index
80 u8 RESERVED_VALID; // Indicate whether the RESERVED space is valid at this command. 87 u8 RESERVED_VALID; // Indicate whether the RESERVED space is valid at this command.
81 u8 DIRECT; // 0:In 1:Out 88 u8 DIRECT; // 0:In 1:Out
82 }; 89 };
83 90
84 //==================================== 91 //====================================
85 // Internal variable for module 92 // Internal variable for module
86 //==================================== 93 //====================================
87 #define MAX_SQ3_FILTER_SIZE 5 94 #define MAX_SQ3_FILTER_SIZE 5
88 struct wb35_reg { 95 struct wb35_reg {
89 //============================ 96 //============================
90 // Register Bank backup 97 // Register Bank backup
91 //============================ 98 //============================
92 u32 U1B0; //bit16 record the h/w radio on/off status 99 u32 U1B0; //bit16 record the h/w radio on/off status
93 u32 U1BC_LEDConfigure; 100 u32 U1BC_LEDConfigure;
94 u32 D00_DmaControl; 101 u32 D00_DmaControl;
95 u32 M00_MacControl; 102 u32 M00_MacControl;
96 union { 103 union {
97 struct { 104 struct {
98 u32 M04_MulticastAddress1; 105 u32 M04_MulticastAddress1;
99 u32 M08_MulticastAddress2; 106 u32 M08_MulticastAddress2;
100 }; 107 };
101 u8 Multicast[8]; // contents of card multicast registers 108 u8 Multicast[8]; // contents of card multicast registers
102 }; 109 };
103 110
104 u32 M24_MacControl; 111 u32 M24_MacControl;
105 u32 M28_MacControl; 112 u32 M28_MacControl;
106 u32 M2C_MacControl; 113 u32 M2C_MacControl;
107 u32 M38_MacControl; 114 u32 M38_MacControl;
108 u32 M3C_MacControl; // 20060214 backup only 115 u32 M3C_MacControl; // 20060214 backup only
109 u32 M40_MacControl; 116 u32 M40_MacControl;
110 u32 M44_MacControl; // 20060214 backup only 117 u32 M44_MacControl; // 20060214 backup only
111 u32 M48_MacControl; // 20060214 backup only 118 u32 M48_MacControl; // 20060214 backup only
112 u32 M4C_MacStatus; 119 u32 M4C_MacStatus;
113 u32 M60_MacControl; // 20060214 backup only 120 u32 M60_MacControl; // 20060214 backup only
114 u32 M68_MacControl; // 20060214 backup only 121 u32 M68_MacControl; // 20060214 backup only
115 u32 M70_MacControl; // 20060214 backup only 122 u32 M70_MacControl; // 20060214 backup only
116 u32 M74_MacControl; // 20060214 backup only 123 u32 M74_MacControl; // 20060214 backup only
117 u32 M78_ERPInformation;//930206.2.b 124 u32 M78_ERPInformation;//930206.2.b
118 u32 M7C_MacControl; // 20060214 backup only 125 u32 M7C_MacControl; // 20060214 backup only
119 u32 M80_MacControl; // 20060214 backup only 126 u32 M80_MacControl; // 20060214 backup only
120 u32 M84_MacControl; // 20060214 backup only 127 u32 M84_MacControl; // 20060214 backup only
121 u32 M88_MacControl; // 20060214 backup only 128 u32 M88_MacControl; // 20060214 backup only
122 u32 M98_MacControl; // 20060214 backup only 129 u32 M98_MacControl; // 20060214 backup only
123 130
124 //[20040722 WK] 131 //[20040722 WK]
125 //Baseband register 132 //Baseband register
126 u32 BB0C; // Used for LNA calculation 133 u32 BB0C; // Used for LNA calculation
127 u32 BB2C; // 134 u32 BB2C; //
128 u32 BB30; //11b acquisition control register 135 u32 BB30; //11b acquisition control register
129 u32 BB3C; 136 u32 BB3C;
130 u32 BB48; // 20051221.1.a 20060613.1 Fix OBW issue of 11b/11g rate 137 u32 BB48; // 20051221.1.a 20060613.1 Fix OBW issue of 11b/11g rate
131 u32 BB4C; // 20060613.1 Fix OBW issue of 11b/11g rate 138 u32 BB4C; // 20060613.1 Fix OBW issue of 11b/11g rate
132 u32 BB50; //mode control register 139 u32 BB50; //mode control register
133 u32 BB54; 140 u32 BB54;
134 u32 BB58; //IQ_ALPHA 141 u32 BB58; //IQ_ALPHA
135 u32 BB5C; // For test 142 u32 BB5C; // For test
136 u32 BB60; // for WTO read value 143 u32 BB60; // for WTO read value
137 144
138 //------------------- 145 //-------------------
139 // VM 146 // VM
140 //------------------- 147 //-------------------
141 spinlock_t EP0VM_spin_lock; // 4B 148 spinlock_t EP0VM_spin_lock; // 4B
142 u32 EP0VM_status;//$$ 149 u32 EP0VM_status;//$$
143 struct wb35_reg_queue *reg_first; 150 struct wb35_reg_queue *reg_first;
144 struct wb35_reg_queue *reg_last; 151 struct wb35_reg_queue *reg_last;
145 atomic_t RegFireCount; 152 atomic_t RegFireCount;
146 153
147 // Hardware status 154 // Hardware status
148 u8 EP0vm_state; 155 u8 EP0vm_state;
149 u8 mac_power_save; 156 u8 mac_power_save;
150 u8 EEPROMPhyType; // 0 ~ 15 for Maxim (0 ฤ„V MAX2825, 1 ฤ„V MAX2827, 2 ฤ„V MAX2828, 3 ฤ„V MAX2829), 157 u8 EEPROMPhyType; // 0 ~ 15 for Maxim (0 ฤ„V MAX2825, 1 ฤ„V MAX2827, 2 ฤ„V MAX2828, 3 ฤ„V MAX2829),
151 // 16 ~ 31 for Airoha (16 ฤ„V AL2230, 11 - AL7230) 158 // 16 ~ 31 for Airoha (16 ฤ„V AL2230, 11 - AL7230)
152 // 32 ~ Reserved 159 // 32 ~ Reserved
153 // 33 ~ 47 For WB242 ( 33 - WB242, 34 - WB242 with new Txvga 0.5 db step) 160 // 33 ~ 47 For WB242 ( 33 - WB242, 34 - WB242 with new Txvga 0.5 db step)
154 // 48 ~ 255 ARE RESERVED. 161 // 48 ~ 255 ARE RESERVED.
155 u8 EEPROMRegion; //Region setting in EEPROM 162 u8 EEPROMRegion; //Region setting in EEPROM
156 163
157 u32 SyncIoPause; // If user use the Sync Io to access Hw, then pause the async access 164 u32 SyncIoPause; // If user use the Sync Io to access Hw, then pause the async access
158 165
159 u8 LNAValue[4]; //Table for speed up running 166 u8 LNAValue[4]; //Table for speed up running
160 u32 SQ3_filter[MAX_SQ3_FILTER_SIZE]; 167 u32 SQ3_filter[MAX_SQ3_FILTER_SIZE];
161 u32 SQ3_index; 168 u32 SQ3_index;
162 169
163 }; 170 };
171
172 #endif
164 173
drivers/staging/winbond/linux/wb35rx.c
Diff comments   View file @ 80aba53
1 //============================================================================ 1 //============================================================================
2 // Copyright (c) 1996-2002 Winbond Electronic Corporation 2 // Copyright (c) 1996-2002 Winbond Electronic Corporation
3 // 3 //
4 // Module Name: 4 // Module Name:
5 // Wb35Rx.c 5 // Wb35Rx.c
6 // 6 //
7 // Abstract: 7 // Abstract:
8 // Processing the Rx message from down layer 8 // Processing the Rx message from down layer
9 // 9 //
10 //============================================================================ 10 //============================================================================
11 #include <linux/usb.h>
12
11 #include "sysdef.h" 13 #include "sysdef.h"
14 #include "wb35rx_f.h"
12 15
13 void Wb35Rx_start(phw_data_t pHwData) 16 void Wb35Rx_start(phw_data_t pHwData)
14 { 17 {
15 PWB35RX pWb35Rx = &pHwData->Wb35Rx; 18 PWB35RX pWb35Rx = &pHwData->Wb35Rx;
16 19
17 // Allow only one thread to run into the Wb35Rx() function 20 // Allow only one thread to run into the Wb35Rx() function
18 if (atomic_inc_return(&pWb35Rx->RxFireCounter) == 1) { 21 if (atomic_inc_return(&pWb35Rx->RxFireCounter) == 1) {
19 pWb35Rx->EP3vm_state = VM_RUNNING; 22 pWb35Rx->EP3vm_state = VM_RUNNING;
20 Wb35Rx(pHwData); 23 Wb35Rx(pHwData);
21 } else 24 } else
22 atomic_dec(&pWb35Rx->RxFireCounter); 25 atomic_dec(&pWb35Rx->RxFireCounter);
23 } 26 }
24 27
25 // This function cannot reentrain 28 // This function cannot reentrain
26 void Wb35Rx( phw_data_t pHwData ) 29 void Wb35Rx( phw_data_t pHwData )
27 { 30 {
28 PWB35RX pWb35Rx = &pHwData->Wb35Rx; 31 PWB35RX pWb35Rx = &pHwData->Wb35Rx;
29 u8 * pRxBufferAddress; 32 u8 * pRxBufferAddress;
30 struct urb *urb = pWb35Rx->RxUrb; 33 struct urb *urb = pWb35Rx->RxUrb;
31 int retv; 34 int retv;
32 u32 RxBufferId; 35 u32 RxBufferId;
33 36
34 // 37 //
35 // Issuing URB 38 // Issuing URB
36 // 39 //
37 if (pHwData->SurpriseRemove || pHwData->HwStop) 40 if (pHwData->SurpriseRemove || pHwData->HwStop)
38 goto error; 41 goto error;
39 42
40 if (pWb35Rx->rx_halt) 43 if (pWb35Rx->rx_halt)
41 goto error; 44 goto error;
42 45
43 // Get RxBuffer's ID 46 // Get RxBuffer's ID
44 RxBufferId = pWb35Rx->RxBufferId; 47 RxBufferId = pWb35Rx->RxBufferId;
45 if (!pWb35Rx->RxOwner[RxBufferId]) { 48 if (!pWb35Rx->RxOwner[RxBufferId]) {
46 // It's impossible to run here. 49 // It's impossible to run here.
47 #ifdef _PE_RX_DUMP_ 50 #ifdef _PE_RX_DUMP_
48 WBDEBUG(("Rx driver fifo unavailable\n")); 51 WBDEBUG(("Rx driver fifo unavailable\n"));
49 #endif 52 #endif
50 goto error; 53 goto error;
51 } 54 }
52 55
53 // Update buffer point, then start to bulkin the data from USB 56 // Update buffer point, then start to bulkin the data from USB
54 pWb35Rx->RxBufferId++; 57 pWb35Rx->RxBufferId++;
55 pWb35Rx->RxBufferId %= MAX_USB_RX_BUFFER_NUMBER; 58 pWb35Rx->RxBufferId %= MAX_USB_RX_BUFFER_NUMBER;
56 59
57 pWb35Rx->CurrentRxBufferId = RxBufferId; 60 pWb35Rx->CurrentRxBufferId = RxBufferId;
58 61
59 pWb35Rx->pDRx = kzalloc(MAX_USB_RX_BUFFER, GFP_ATOMIC); 62 pWb35Rx->pDRx = kzalloc(MAX_USB_RX_BUFFER, GFP_ATOMIC);
60 if (!pWb35Rx->pDRx) { 63 if (!pWb35Rx->pDRx) {
61 printk("w35und: Rx memory alloc failed\n"); 64 printk("w35und: Rx memory alloc failed\n");
62 goto error; 65 goto error;
63 } 66 }
64 pRxBufferAddress = pWb35Rx->pDRx; 67 pRxBufferAddress = pWb35Rx->pDRx;
65 68
66 usb_fill_bulk_urb(urb, pHwData->WbUsb.udev, 69 usb_fill_bulk_urb(urb, pHwData->WbUsb.udev,
67 usb_rcvbulkpipe(pHwData->WbUsb.udev, 3), 70 usb_rcvbulkpipe(pHwData->WbUsb.udev, 3),
68 pRxBufferAddress, MAX_USB_RX_BUFFER, 71 pRxBufferAddress, MAX_USB_RX_BUFFER,
69 Wb35Rx_Complete, pHwData); 72 Wb35Rx_Complete, pHwData);
70 73
71 pWb35Rx->EP3vm_state = VM_RUNNING; 74 pWb35Rx->EP3vm_state = VM_RUNNING;
72 75
73 retv = usb_submit_urb(urb, GFP_ATOMIC); 76 retv = usb_submit_urb(urb, GFP_ATOMIC);
74 77
75 if (retv != 0) { 78 if (retv != 0) {
76 printk("Rx URB sending error\n"); 79 printk("Rx URB sending error\n");
77 goto error; 80 goto error;
78 } 81 }
79 return; 82 return;
80 83
81 error: 84 error:
82 // VM stop 85 // VM stop
83 pWb35Rx->EP3vm_state = VM_STOP; 86 pWb35Rx->EP3vm_state = VM_STOP;
84 atomic_dec(&pWb35Rx->RxFireCounter); 87 atomic_dec(&pWb35Rx->RxFireCounter);
85 } 88 }
86 89
87 void Wb35Rx_Complete(struct urb *urb) 90 void Wb35Rx_Complete(struct urb *urb)
88 { 91 {
89 phw_data_t pHwData = urb->context; 92 phw_data_t pHwData = urb->context;
90 PWB35RX pWb35Rx = &pHwData->Wb35Rx; 93 PWB35RX pWb35Rx = &pHwData->Wb35Rx;
91 u8 * pRxBufferAddress; 94 u8 * pRxBufferAddress;
92 u32 SizeCheck; 95 u32 SizeCheck;
93 u16 BulkLength; 96 u16 BulkLength;
94 u32 RxBufferId; 97 u32 RxBufferId;
95 R00_DESCRIPTOR R00; 98 R00_DESCRIPTOR R00;
96 99
97 // Variable setting 100 // Variable setting
98 pWb35Rx->EP3vm_state = VM_COMPLETED; 101 pWb35Rx->EP3vm_state = VM_COMPLETED;
99 pWb35Rx->EP3VM_status = urb->status;//Store the last result of Irp 102 pWb35Rx->EP3VM_status = urb->status;//Store the last result of Irp
100 103
101 RxBufferId = pWb35Rx->CurrentRxBufferId; 104 RxBufferId = pWb35Rx->CurrentRxBufferId;
102 105
103 pRxBufferAddress = pWb35Rx->pDRx; 106 pRxBufferAddress = pWb35Rx->pDRx;
104 BulkLength = (u16)urb->actual_length; 107 BulkLength = (u16)urb->actual_length;
105 108
106 // The IRP is completed 109 // The IRP is completed
107 pWb35Rx->EP3vm_state = VM_COMPLETED; 110 pWb35Rx->EP3vm_state = VM_COMPLETED;
108 111
109 if (pHwData->SurpriseRemove || pHwData->HwStop) // Must be here, or RxBufferId is invalid 112 if (pHwData->SurpriseRemove || pHwData->HwStop) // Must be here, or RxBufferId is invalid
110 goto error; 113 goto error;
111 114
112 if (pWb35Rx->rx_halt) 115 if (pWb35Rx->rx_halt)
113 goto error; 116 goto error;
114 117
115 // Start to process the data only in successful condition 118 // Start to process the data only in successful condition
116 pWb35Rx->RxOwner[ RxBufferId ] = 0; // Set the owner to driver 119 pWb35Rx->RxOwner[ RxBufferId ] = 0; // Set the owner to driver
117 R00.value = le32_to_cpu(*(u32 *)pRxBufferAddress); 120 R00.value = le32_to_cpu(*(u32 *)pRxBufferAddress);
118 121
119 // The URB is completed, check the result 122 // The URB is completed, check the result
120 if (pWb35Rx->EP3VM_status != 0) { 123 if (pWb35Rx->EP3VM_status != 0) {
121 #ifdef _PE_USB_STATE_DUMP_ 124 #ifdef _PE_USB_STATE_DUMP_
122 WBDEBUG(("EP3 IoCompleteRoutine return error\n")); 125 WBDEBUG(("EP3 IoCompleteRoutine return error\n"));
123 DebugUsbdStatusInformation( pWb35Rx->EP3VM_status ); 126 DebugUsbdStatusInformation( pWb35Rx->EP3VM_status );
124 #endif 127 #endif
125 pWb35Rx->EP3vm_state = VM_STOP; 128 pWb35Rx->EP3vm_state = VM_STOP;
126 goto error; 129 goto error;
127 } 130 }
128 131
129 // 20060220 For recovering. check if operating in single USB mode 132 // 20060220 For recovering. check if operating in single USB mode
130 if (!HAL_USB_MODE_BURST(pHwData)) { 133 if (!HAL_USB_MODE_BURST(pHwData)) {
131 SizeCheck = R00.R00_receive_byte_count; //20060926 anson's endian 134 SizeCheck = R00.R00_receive_byte_count; //20060926 anson's endian
132 if ((SizeCheck & 0x03) > 0) 135 if ((SizeCheck & 0x03) > 0)
133 SizeCheck -= 4; 136 SizeCheck -= 4;
134 SizeCheck = (SizeCheck + 3) & ~0x03; 137 SizeCheck = (SizeCheck + 3) & ~0x03;
135 SizeCheck += 12; // 8 + 4 badbeef 138 SizeCheck += 12; // 8 + 4 badbeef
136 if ((BulkLength > 1600) || 139 if ((BulkLength > 1600) ||
137 (SizeCheck > 1600) || 140 (SizeCheck > 1600) ||
138 (BulkLength != SizeCheck) || 141 (BulkLength != SizeCheck) ||
139 (BulkLength == 0)) { // Add for fail Urb 142 (BulkLength == 0)) { // Add for fail Urb
140 pWb35Rx->EP3vm_state = VM_STOP; 143 pWb35Rx->EP3vm_state = VM_STOP;
141 pWb35Rx->Ep3ErrorCount2++; 144 pWb35Rx->Ep3ErrorCount2++;
142 } 145 }
143 } 146 }
144 147
145 // Indicating the receiving data 148 // Indicating the receiving data
146 pWb35Rx->ByteReceived += BulkLength; 149 pWb35Rx->ByteReceived += BulkLength;
147 pWb35Rx->RxBufferSize[ RxBufferId ] = BulkLength; 150 pWb35Rx->RxBufferSize[ RxBufferId ] = BulkLength;
148 151
149 if (!pWb35Rx->RxOwner[ RxBufferId ]) 152 if (!pWb35Rx->RxOwner[ RxBufferId ])
150 Wb35Rx_indicate(pHwData); 153 Wb35Rx_indicate(pHwData);
151 154
152 kfree(pWb35Rx->pDRx); 155 kfree(pWb35Rx->pDRx);
153 // Do the next receive 156 // Do the next receive
154 Wb35Rx(pHwData); 157 Wb35Rx(pHwData);
155 return; 158 return;
156 159
157 error: 160 error:
158 pWb35Rx->RxOwner[ RxBufferId ] = 1; // Set the owner to hardware 161 pWb35Rx->RxOwner[ RxBufferId ] = 1; // Set the owner to hardware
159 atomic_dec(&pWb35Rx->RxFireCounter); 162 atomic_dec(&pWb35Rx->RxFireCounter);
160 pWb35Rx->EP3vm_state = VM_STOP; 163 pWb35Rx->EP3vm_state = VM_STOP;
161 } 164 }
162 165
163 //===================================================================================== 166 //=====================================================================================
164 unsigned char Wb35Rx_initial(phw_data_t pHwData) 167 unsigned char Wb35Rx_initial(phw_data_t pHwData)
165 { 168 {
166 PWB35RX pWb35Rx = &pHwData->Wb35Rx; 169 PWB35RX pWb35Rx = &pHwData->Wb35Rx;
167 170
168 // Initial the Buffer Queue 171 // Initial the Buffer Queue
169 Wb35Rx_reset_descriptor( pHwData ); 172 Wb35Rx_reset_descriptor( pHwData );
170 173
171 pWb35Rx->RxUrb = usb_alloc_urb(0, GFP_ATOMIC); 174 pWb35Rx->RxUrb = usb_alloc_urb(0, GFP_ATOMIC);
172 return (!!pWb35Rx->RxUrb); 175 return (!!pWb35Rx->RxUrb);
173 } 176 }
174 177
175 void Wb35Rx_stop(phw_data_t pHwData) 178 void Wb35Rx_stop(phw_data_t pHwData)
176 { 179 {
177 PWB35RX pWb35Rx = &pHwData->Wb35Rx; 180 PWB35RX pWb35Rx = &pHwData->Wb35Rx;
178 181
179 // Canceling the Irp if already sends it out. 182 // Canceling the Irp if already sends it out.
180 if (pWb35Rx->EP3vm_state == VM_RUNNING) { 183 if (pWb35Rx->EP3vm_state == VM_RUNNING) {
181 usb_unlink_urb( pWb35Rx->RxUrb ); // Only use unlink, let Wb35Rx_destroy to free them 184 usb_unlink_urb( pWb35Rx->RxUrb ); // Only use unlink, let Wb35Rx_destroy to free them
182 #ifdef _PE_RX_DUMP_ 185 #ifdef _PE_RX_DUMP_
183 WBDEBUG(("EP3 Rx stop\n")); 186 WBDEBUG(("EP3 Rx stop\n"));
184 #endif 187 #endif
185 } 188 }
186 } 189 }
187 190
188 // Needs process context 191 // Needs process context
189 void Wb35Rx_destroy(phw_data_t pHwData) 192 void Wb35Rx_destroy(phw_data_t pHwData)
190 { 193 {
191 PWB35RX pWb35Rx = &pHwData->Wb35Rx; 194 PWB35RX pWb35Rx = &pHwData->Wb35Rx;
192 195
193 do { 196 do {
194 msleep(10); // Delay for waiting function enter 940623.1.a 197 msleep(10); // Delay for waiting function enter 940623.1.a
195 } while (pWb35Rx->EP3vm_state != VM_STOP); 198 } while (pWb35Rx->EP3vm_state != VM_STOP);
196 msleep(10); // Delay for waiting function exit 940623.1.b 199 msleep(10); // Delay for waiting function exit 940623.1.b
197 200
198 if (pWb35Rx->RxUrb) 201 if (pWb35Rx->RxUrb)
199 usb_free_urb( pWb35Rx->RxUrb ); 202 usb_free_urb( pWb35Rx->RxUrb );
200 #ifdef _PE_RX_DUMP_ 203 #ifdef _PE_RX_DUMP_
201 WBDEBUG(("Wb35Rx_destroy OK\n")); 204 WBDEBUG(("Wb35Rx_destroy OK\n"));
202 #endif 205 #endif
203 } 206 }
204 207
205 void Wb35Rx_reset_descriptor( phw_data_t pHwData ) 208 void Wb35Rx_reset_descriptor( phw_data_t pHwData )
206 { 209 {
207 PWB35RX pWb35Rx = &pHwData->Wb35Rx; 210 PWB35RX pWb35Rx = &pHwData->Wb35Rx;
208 u32 i; 211 u32 i;
209 212
210 pWb35Rx->ByteReceived = 0; 213 pWb35Rx->ByteReceived = 0;
211 pWb35Rx->RxProcessIndex = 0; 214 pWb35Rx->RxProcessIndex = 0;
212 pWb35Rx->RxBufferId = 0; 215 pWb35Rx->RxBufferId = 0;
213 pWb35Rx->EP3vm_state = VM_STOP; 216 pWb35Rx->EP3vm_state = VM_STOP;
214 pWb35Rx->rx_halt = 0; 217 pWb35Rx->rx_halt = 0;
215 218
216 // Initial the Queue. The last buffer is reserved for used if the Rx resource is unavailable. 219 // Initial the Queue. The last buffer is reserved for used if the Rx resource is unavailable.
217 for( i=0; i<MAX_USB_RX_BUFFER_NUMBER; i++ ) 220 for( i=0; i<MAX_USB_RX_BUFFER_NUMBER; i++ )
218 pWb35Rx->RxOwner[i] = 1; 221 pWb35Rx->RxOwner[i] = 1;
219 } 222 }
220 223
221 void Wb35Rx_adjust(PDESCRIPTOR pRxDes) 224 void Wb35Rx_adjust(PDESCRIPTOR pRxDes)
222 { 225 {
223 u32 * pRxBufferAddress; 226 u32 * pRxBufferAddress;
224 u32 DecryptionMethod; 227 u32 DecryptionMethod;
225 u32 i; 228 u32 i;
226 u16 BufferSize; 229 u16 BufferSize;
227 230
228 DecryptionMethod = pRxDes->R01.R01_decryption_method; 231 DecryptionMethod = pRxDes->R01.R01_decryption_method;
229 pRxBufferAddress = pRxDes->buffer_address[0]; 232 pRxBufferAddress = pRxDes->buffer_address[0];
230 BufferSize = pRxDes->buffer_size[0]; 233 BufferSize = pRxDes->buffer_size[0];
231 234
232 // Adjust the last part of data. Only data left 235 // Adjust the last part of data. Only data left
233 BufferSize -= 4; // For CRC-32 236 BufferSize -= 4; // For CRC-32
234 if (DecryptionMethod) 237 if (DecryptionMethod)
235 BufferSize -= 4; 238 BufferSize -= 4;
236 if (DecryptionMethod == 3) // For CCMP 239 if (DecryptionMethod == 3) // For CCMP
237 BufferSize -= 4; 240 BufferSize -= 4;
238 241
239 // Adjust the IV field which after 802.11 header and ICV field. 242 // Adjust the IV field which after 802.11 header and ICV field.
240 if (DecryptionMethod == 1) // For WEP 243 if (DecryptionMethod == 1) // For WEP
241 { 244 {
242 for( i=6; i>0; i-- ) 245 for( i=6; i>0; i-- )
243 pRxBufferAddress[i] = pRxBufferAddress[i-1]; 246 pRxBufferAddress[i] = pRxBufferAddress[i-1];
244 pRxDes->buffer_address[0] = pRxBufferAddress + 1; 247 pRxDes->buffer_address[0] = pRxBufferAddress + 1;
245 BufferSize -= 4; // 4 byte for IV 248 BufferSize -= 4; // 4 byte for IV
246 } 249 }
247 else if( DecryptionMethod ) // For TKIP and CCMP 250 else if( DecryptionMethod ) // For TKIP and CCMP
248 { 251 {
249 for (i=7; i>1; i--) 252 for (i=7; i>1; i--)
250 pRxBufferAddress[i] = pRxBufferAddress[i-2]; 253 pRxBufferAddress[i] = pRxBufferAddress[i-2];
251 pRxDes->buffer_address[0] = pRxBufferAddress + 2;//Update the descriptor, shift 8 byte 254 pRxDes->buffer_address[0] = pRxBufferAddress + 2;//Update the descriptor, shift 8 byte
252 BufferSize -= 8; // 8 byte for IV + ICV 255 BufferSize -= 8; // 8 byte for IV + ICV
253 } 256 }
254 pRxDes->buffer_size[0] = BufferSize; 257 pRxDes->buffer_size[0] = BufferSize;
255 } 258 }
256 259
257 extern void packet_came(char *pRxBufferAddress, int PacketSize); 260 extern void packet_came(char *pRxBufferAddress, int PacketSize);
258 261
259 262
260 u16 Wb35Rx_indicate(phw_data_t pHwData) 263 u16 Wb35Rx_indicate(phw_data_t pHwData)
261 { 264 {
262 DESCRIPTOR RxDes; 265 DESCRIPTOR RxDes;
263 PWB35RX pWb35Rx = &pHwData->Wb35Rx; 266 PWB35RX pWb35Rx = &pHwData->Wb35Rx;
264 u8 * pRxBufferAddress; 267 u8 * pRxBufferAddress;
265 u16 PacketSize; 268 u16 PacketSize;
266 u16 stmp, BufferSize, stmp2 = 0; 269 u16 stmp, BufferSize, stmp2 = 0;
267 u32 RxBufferId; 270 u32 RxBufferId;
268 271
269 // Only one thread be allowed to run into the following 272 // Only one thread be allowed to run into the following
270 do { 273 do {
271 RxBufferId = pWb35Rx->RxProcessIndex; 274 RxBufferId = pWb35Rx->RxProcessIndex;
272 if (pWb35Rx->RxOwner[ RxBufferId ]) //Owner by VM 275 if (pWb35Rx->RxOwner[ RxBufferId ]) //Owner by VM
273 break; 276 break;
274 277
275 pWb35Rx->RxProcessIndex++; 278 pWb35Rx->RxProcessIndex++;
276 pWb35Rx->RxProcessIndex %= MAX_USB_RX_BUFFER_NUMBER; 279 pWb35Rx->RxProcessIndex %= MAX_USB_RX_BUFFER_NUMBER;
277 280
278 pRxBufferAddress = pWb35Rx->pDRx; 281 pRxBufferAddress = pWb35Rx->pDRx;
279 BufferSize = pWb35Rx->RxBufferSize[ RxBufferId ]; 282 BufferSize = pWb35Rx->RxBufferSize[ RxBufferId ];
280 283
281 // Parse the bulkin buffer 284 // Parse the bulkin buffer
282 while (BufferSize >= 4) { 285 while (BufferSize >= 4) {
283 if ((cpu_to_le32(*(u32 *)pRxBufferAddress) & 0x0fffffff) == RX_END_TAG) //Is ending? 921002.9.a 286 if ((cpu_to_le32(*(u32 *)pRxBufferAddress) & 0x0fffffff) == RX_END_TAG) //Is ending? 921002.9.a
284 break; 287 break;
285 288
286 // Get the R00 R01 first 289 // Get the R00 R01 first
287 RxDes.R00.value = le32_to_cpu(*(u32 *)pRxBufferAddress); 290 RxDes.R00.value = le32_to_cpu(*(u32 *)pRxBufferAddress);
288 PacketSize = (u16)RxDes.R00.R00_receive_byte_count; 291 PacketSize = (u16)RxDes.R00.R00_receive_byte_count;
289 RxDes.R01.value = le32_to_cpu(*((u32 *)(pRxBufferAddress+4))); 292 RxDes.R01.value = le32_to_cpu(*((u32 *)(pRxBufferAddress+4)));
290 // For new DMA 4k 293 // For new DMA 4k
291 if ((PacketSize & 0x03) > 0) 294 if ((PacketSize & 0x03) > 0)
292 PacketSize -= 4; 295 PacketSize -= 4;
293 296
294 // Basic check for Rx length. Is length valid? 297 // Basic check for Rx length. Is length valid?
295 if (PacketSize > MAX_PACKET_SIZE) { 298 if (PacketSize > MAX_PACKET_SIZE) {
296 #ifdef _PE_RX_DUMP_ 299 #ifdef _PE_RX_DUMP_
297 WBDEBUG(("Serious ERROR : Rx data size too long, size =%d\n", PacketSize)); 300 WBDEBUG(("Serious ERROR : Rx data size too long, size =%d\n", PacketSize));
298 #endif 301 #endif
299 302
300 pWb35Rx->EP3vm_state = VM_STOP; 303 pWb35Rx->EP3vm_state = VM_STOP;
301 pWb35Rx->Ep3ErrorCount2++; 304 pWb35Rx->Ep3ErrorCount2++;
302 break; 305 break;
303 } 306 }
304 307
305 // Start to process Rx buffer 308 // Start to process Rx buffer
306 // RxDes.Descriptor_ID = RxBufferId; // Due to synchronous indicate, the field doesn't necessary to use. 309 // RxDes.Descriptor_ID = RxBufferId; // Due to synchronous indicate, the field doesn't necessary to use.
307 BufferSize -= 8; //subtract 8 byte for 35's USB header length 310 BufferSize -= 8; //subtract 8 byte for 35's USB header length
308 pRxBufferAddress += 8; 311 pRxBufferAddress += 8;
309 312
310 RxDes.buffer_address[0] = pRxBufferAddress; 313 RxDes.buffer_address[0] = pRxBufferAddress;
311 RxDes.buffer_size[0] = PacketSize; 314 RxDes.buffer_size[0] = PacketSize;
312 RxDes.buffer_number = 1; 315 RxDes.buffer_number = 1;
313 RxDes.buffer_start_index = 0; 316 RxDes.buffer_start_index = 0;
314 RxDes.buffer_total_size = RxDes.buffer_size[0]; 317 RxDes.buffer_total_size = RxDes.buffer_size[0];
315 Wb35Rx_adjust(&RxDes); 318 Wb35Rx_adjust(&RxDes);
316 319
317 packet_came(pRxBufferAddress, PacketSize); 320 packet_came(pRxBufferAddress, PacketSize);
318 321
319 // Move RxBuffer point to the next 322 // Move RxBuffer point to the next
320 stmp = PacketSize + 3; 323 stmp = PacketSize + 3;
321 stmp &= ~0x03; // 4n alignment 324 stmp &= ~0x03; // 4n alignment
322 pRxBufferAddress += stmp; 325 pRxBufferAddress += stmp;
323 BufferSize -= stmp; 326 BufferSize -= stmp;
324 stmp2 += stmp; 327 stmp2 += stmp;
325 } 328 }
326 329
327 // Reclaim resource 330 // Reclaim resource
328 pWb35Rx->RxOwner[ RxBufferId ] = 1; 331 pWb35Rx->RxOwner[ RxBufferId ] = 1;
329 } while (true); 332 } while (true);
330 333
331 return stmp2; 334 return stmp2;
332 } 335 }
333 336
334 337
335 338
drivers/staging/winbond/linux/wb35rx_f.h
Diff comments   View file @ 80aba53
1 #ifndef __WINBOND_WB35RX_F_H
2 #define __WINBOND_WB35RX_F_H
3
4 #include "../wbhal_s.h"
5
1 //==================================== 6 //====================================
2 // Interface function declare 7 // Interface function declare
3 //==================================== 8 //====================================
4 void Wb35Rx_reset_descriptor( phw_data_t pHwData ); 9 void Wb35Rx_reset_descriptor( phw_data_t pHwData );
5 unsigned char Wb35Rx_initial( phw_data_t pHwData ); 10 unsigned char Wb35Rx_initial( phw_data_t pHwData );
6 void Wb35Rx_destroy( phw_data_t pHwData ); 11 void Wb35Rx_destroy( phw_data_t pHwData );
7 void Wb35Rx_stop( phw_data_t pHwData ); 12 void Wb35Rx_stop( phw_data_t pHwData );
8 u16 Wb35Rx_indicate( phw_data_t pHwData ); 13 u16 Wb35Rx_indicate( phw_data_t pHwData );
9 void Wb35Rx_adjust( PDESCRIPTOR pRxDes ); 14 void Wb35Rx_adjust( PDESCRIPTOR pRxDes );
10 void Wb35Rx_start( phw_data_t pHwData ); 15 void Wb35Rx_start( phw_data_t pHwData );
11 16
12 void Wb35Rx( phw_data_t pHwData ); 17 void Wb35Rx( phw_data_t pHwData );
13 void Wb35Rx_Complete(struct urb *urb); 18 void Wb35Rx_Complete(struct urb *urb);
19
20 #endif
14 21
drivers/staging/winbond/linux/wb35tx.c
Diff comments   View file @ 80aba53
1 //============================================================================ 1 //============================================================================
2 // Copyright (c) 1996-2002 Winbond Electronic Corporation 2 // Copyright (c) 1996-2002 Winbond Electronic Corporation
3 // 3 //
4 // Module Name: 4 // Module Name:
5 // Wb35Tx.c 5 // Wb35Tx.c
6 // 6 //
7 // Abstract: 7 // Abstract:
8 // Processing the Tx message and put into down layer 8 // Processing the Tx message and put into down layer
9 // 9 //
10 //============================================================================ 10 //============================================================================
11 #include "sysdef.h" 11 #include <linux/usb.h>
12 12
13 #include "wb35tx_f.h"
14 #include "../mds_f.h"
15 #include "sysdef.h"
13 16
14 unsigned char 17 unsigned char
15 Wb35Tx_get_tx_buffer(phw_data_t pHwData, u8 **pBuffer) 18 Wb35Tx_get_tx_buffer(phw_data_t pHwData, u8 **pBuffer)
16 { 19 {
17 PWB35TX pWb35Tx = &pHwData->Wb35Tx; 20 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
18 21
19 *pBuffer = pWb35Tx->TxBuffer[0]; 22 *pBuffer = pWb35Tx->TxBuffer[0];
20 return true; 23 return true;
21 } 24 }
22 25
23 void Wb35Tx_start(phw_data_t pHwData) 26 void Wb35Tx_start(phw_data_t pHwData)
24 { 27 {
25 PWB35TX pWb35Tx = &pHwData->Wb35Tx; 28 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
26 29
27 // Allow only one thread to run into function 30 // Allow only one thread to run into function
28 if (atomic_inc_return(&pWb35Tx->TxFireCounter) == 1) { 31 if (atomic_inc_return(&pWb35Tx->TxFireCounter) == 1) {
29 pWb35Tx->EP4vm_state = VM_RUNNING; 32 pWb35Tx->EP4vm_state = VM_RUNNING;
30 Wb35Tx(pHwData); 33 Wb35Tx(pHwData);
31 } else 34 } else
32 atomic_dec(&pWb35Tx->TxFireCounter); 35 atomic_dec(&pWb35Tx->TxFireCounter);
33 } 36 }
34 37
35 38
36 void Wb35Tx(phw_data_t pHwData) 39 void Wb35Tx(phw_data_t pHwData)
37 { 40 {
38 PWB35TX pWb35Tx = &pHwData->Wb35Tx; 41 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
39 struct wb35_adapter *adapter = pHwData->adapter; 42 struct wb35_adapter *adapter = pHwData->adapter;
40 u8 *pTxBufferAddress; 43 u8 *pTxBufferAddress;
41 PMDS pMds = &adapter->Mds; 44 PMDS pMds = &adapter->Mds;
42 struct urb * pUrb = (struct urb *)pWb35Tx->Tx4Urb; 45 struct urb * pUrb = (struct urb *)pWb35Tx->Tx4Urb;
43 int retv; 46 int retv;
44 u32 SendIndex; 47 u32 SendIndex;
45 48
46 49
47 if (pHwData->SurpriseRemove || pHwData->HwStop) 50 if (pHwData->SurpriseRemove || pHwData->HwStop)
48 goto cleanup; 51 goto cleanup;
49 52
50 if (pWb35Tx->tx_halt) 53 if (pWb35Tx->tx_halt)
51 goto cleanup; 54 goto cleanup;
52 55
53 // Ownership checking 56 // Ownership checking
54 SendIndex = pWb35Tx->TxSendIndex; 57 SendIndex = pWb35Tx->TxSendIndex;
55 if (!pMds->TxOwner[SendIndex]) //No more data need to be sent, return immediately 58 if (!pMds->TxOwner[SendIndex]) //No more data need to be sent, return immediately
56 goto cleanup; 59 goto cleanup;
57 60
58 pTxBufferAddress = pWb35Tx->TxBuffer[SendIndex]; 61 pTxBufferAddress = pWb35Tx->TxBuffer[SendIndex];
59 // 62 //
60 // Issuing URB 63 // Issuing URB
61 // 64 //
62 usb_fill_bulk_urb(pUrb, pHwData->WbUsb.udev, 65 usb_fill_bulk_urb(pUrb, pHwData->WbUsb.udev,
63 usb_sndbulkpipe(pHwData->WbUsb.udev, 4), 66 usb_sndbulkpipe(pHwData->WbUsb.udev, 4),
64 pTxBufferAddress, pMds->TxBufferSize[ SendIndex ], 67 pTxBufferAddress, pMds->TxBufferSize[ SendIndex ],
65 Wb35Tx_complete, pHwData); 68 Wb35Tx_complete, pHwData);
66 69
67 pWb35Tx->EP4vm_state = VM_RUNNING; 70 pWb35Tx->EP4vm_state = VM_RUNNING;
68 retv = usb_submit_urb(pUrb, GFP_ATOMIC); 71 retv = usb_submit_urb(pUrb, GFP_ATOMIC);
69 if (retv<0) { 72 if (retv<0) {
70 printk("EP4 Tx Irp sending error\n"); 73 printk("EP4 Tx Irp sending error\n");
71 goto cleanup; 74 goto cleanup;
72 } 75 }
73 76
74 // Check if driver needs issue Irp for EP2 77 // Check if driver needs issue Irp for EP2
75 pWb35Tx->TxFillCount += pMds->TxCountInBuffer[SendIndex]; 78 pWb35Tx->TxFillCount += pMds->TxCountInBuffer[SendIndex];
76 if (pWb35Tx->TxFillCount > 12) 79 if (pWb35Tx->TxFillCount > 12)
77 Wb35Tx_EP2VM_start( pHwData ); 80 Wb35Tx_EP2VM_start( pHwData );
78 81
79 pWb35Tx->ByteTransfer += pMds->TxBufferSize[SendIndex]; 82 pWb35Tx->ByteTransfer += pMds->TxBufferSize[SendIndex];
80 return; 83 return;
81 84
82 cleanup: 85 cleanup:
83 pWb35Tx->EP4vm_state = VM_STOP; 86 pWb35Tx->EP4vm_state = VM_STOP;
84 atomic_dec(&pWb35Tx->TxFireCounter); 87 atomic_dec(&pWb35Tx->TxFireCounter);
85 } 88 }
86 89
87 90
88 void Wb35Tx_complete(struct urb * pUrb) 91 void Wb35Tx_complete(struct urb * pUrb)
89 { 92 {
90 phw_data_t pHwData = pUrb->context; 93 phw_data_t pHwData = pUrb->context;
91 struct wb35_adapter *adapter = pHwData->adapter; 94 struct wb35_adapter *adapter = pHwData->adapter;
92 PWB35TX pWb35Tx = &pHwData->Wb35Tx; 95 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
93 PMDS pMds = &adapter->Mds; 96 PMDS pMds = &adapter->Mds;
94 97
95 printk("wb35: tx complete\n"); 98 printk("wb35: tx complete\n");
96 // Variable setting 99 // Variable setting
97 pWb35Tx->EP4vm_state = VM_COMPLETED; 100 pWb35Tx->EP4vm_state = VM_COMPLETED;
98 pWb35Tx->EP4VM_status = pUrb->status; //Store the last result of Irp 101 pWb35Tx->EP4VM_status = pUrb->status; //Store the last result of Irp
99 pMds->TxOwner[ pWb35Tx->TxSendIndex ] = 0;// Set the owner. Free the owner bit always. 102 pMds->TxOwner[ pWb35Tx->TxSendIndex ] = 0;// Set the owner. Free the owner bit always.
100 pWb35Tx->TxSendIndex++; 103 pWb35Tx->TxSendIndex++;
101 pWb35Tx->TxSendIndex %= MAX_USB_TX_BUFFER_NUMBER; 104 pWb35Tx->TxSendIndex %= MAX_USB_TX_BUFFER_NUMBER;
102 105
103 if (pHwData->SurpriseRemove || pHwData->HwStop) // Let WbWlanHalt to handle surprise remove 106 if (pHwData->SurpriseRemove || pHwData->HwStop) // Let WbWlanHalt to handle surprise remove
104 goto error; 107 goto error;
105 108
106 if (pWb35Tx->tx_halt) 109 if (pWb35Tx->tx_halt)
107 goto error; 110 goto error;
108 111
109 // The URB is completed, check the result 112 // The URB is completed, check the result
110 if (pWb35Tx->EP4VM_status != 0) { 113 if (pWb35Tx->EP4VM_status != 0) {
111 printk("URB submission failed\n"); 114 printk("URB submission failed\n");
112 pWb35Tx->EP4vm_state = VM_STOP; 115 pWb35Tx->EP4vm_state = VM_STOP;
113 goto error; 116 goto error;
114 } 117 }
115 118
116 Mds_Tx(adapter); 119 Mds_Tx(adapter);
117 Wb35Tx(pHwData); 120 Wb35Tx(pHwData);
118 return; 121 return;
119 122
120 error: 123 error:
121 atomic_dec(&pWb35Tx->TxFireCounter); 124 atomic_dec(&pWb35Tx->TxFireCounter);
122 pWb35Tx->EP4vm_state = VM_STOP; 125 pWb35Tx->EP4vm_state = VM_STOP;
123 } 126 }
124 127
125 void Wb35Tx_reset_descriptor( phw_data_t pHwData ) 128 void Wb35Tx_reset_descriptor( phw_data_t pHwData )
126 { 129 {
127 PWB35TX pWb35Tx = &pHwData->Wb35Tx; 130 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
128 131
129 pWb35Tx->TxSendIndex = 0; 132 pWb35Tx->TxSendIndex = 0;
130 pWb35Tx->tx_halt = 0; 133 pWb35Tx->tx_halt = 0;
131 } 134 }
132 135
133 unsigned char Wb35Tx_initial(phw_data_t pHwData) 136 unsigned char Wb35Tx_initial(phw_data_t pHwData)
134 { 137 {
135 PWB35TX pWb35Tx = &pHwData->Wb35Tx; 138 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
136 139
137 pWb35Tx->Tx4Urb = usb_alloc_urb(0, GFP_ATOMIC); 140 pWb35Tx->Tx4Urb = usb_alloc_urb(0, GFP_ATOMIC);
138 if (!pWb35Tx->Tx4Urb) 141 if (!pWb35Tx->Tx4Urb)
139 return false; 142 return false;
140 143
141 pWb35Tx->Tx2Urb = usb_alloc_urb(0, GFP_ATOMIC); 144 pWb35Tx->Tx2Urb = usb_alloc_urb(0, GFP_ATOMIC);
142 if (!pWb35Tx->Tx2Urb) 145 if (!pWb35Tx->Tx2Urb)
143 { 146 {
144 usb_free_urb( pWb35Tx->Tx4Urb ); 147 usb_free_urb( pWb35Tx->Tx4Urb );
145 return false; 148 return false;
146 } 149 }
147 150
148 return true; 151 return true;
149 } 152 }
150 153
151 //====================================================== 154 //======================================================
152 void Wb35Tx_stop(phw_data_t pHwData) 155 void Wb35Tx_stop(phw_data_t pHwData)
153 { 156 {
154 PWB35TX pWb35Tx = &pHwData->Wb35Tx; 157 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
155 158
156 // Trying to canceling the Trp of EP2 159 // Trying to canceling the Trp of EP2
157 if (pWb35Tx->EP2vm_state == VM_RUNNING) 160 if (pWb35Tx->EP2vm_state == VM_RUNNING)
158 usb_unlink_urb( pWb35Tx->Tx2Urb ); // Only use unlink, let Wb35Tx_destrot to free them 161 usb_unlink_urb( pWb35Tx->Tx2Urb ); // Only use unlink, let Wb35Tx_destrot to free them
159 #ifdef _PE_TX_DUMP_ 162 #ifdef _PE_TX_DUMP_
160 WBDEBUG(("EP2 Tx stop\n")); 163 WBDEBUG(("EP2 Tx stop\n"));
161 #endif 164 #endif
162 165
163 // Trying to canceling the Irp of EP4 166 // Trying to canceling the Irp of EP4
164 if (pWb35Tx->EP4vm_state == VM_RUNNING) 167 if (pWb35Tx->EP4vm_state == VM_RUNNING)
165 usb_unlink_urb( pWb35Tx->Tx4Urb ); // Only use unlink, let Wb35Tx_destrot to free them 168 usb_unlink_urb( pWb35Tx->Tx4Urb ); // Only use unlink, let Wb35Tx_destrot to free them
166 #ifdef _PE_TX_DUMP_ 169 #ifdef _PE_TX_DUMP_
167 WBDEBUG(("EP4 Tx stop\n")); 170 WBDEBUG(("EP4 Tx stop\n"));
168 #endif 171 #endif
169 } 172 }
170 173
171 //====================================================== 174 //======================================================
172 void Wb35Tx_destroy(phw_data_t pHwData) 175 void Wb35Tx_destroy(phw_data_t pHwData)
173 { 176 {
174 PWB35TX pWb35Tx = &pHwData->Wb35Tx; 177 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
175 178
176 // Wait for VM stop 179 // Wait for VM stop
177 do { 180 do {
178 msleep(10); // Delay for waiting function enter 940623.1.a 181 msleep(10); // Delay for waiting function enter 940623.1.a
179 } while( (pWb35Tx->EP2vm_state != VM_STOP) && (pWb35Tx->EP4vm_state != VM_STOP) ); 182 } while( (pWb35Tx->EP2vm_state != VM_STOP) && (pWb35Tx->EP4vm_state != VM_STOP) );
180 msleep(10); // Delay for waiting function enter 940623.1.b 183 msleep(10); // Delay for waiting function enter 940623.1.b
181 184
182 if (pWb35Tx->Tx4Urb) 185 if (pWb35Tx->Tx4Urb)
183 usb_free_urb( pWb35Tx->Tx4Urb ); 186 usb_free_urb( pWb35Tx->Tx4Urb );
184 187
185 if (pWb35Tx->Tx2Urb) 188 if (pWb35Tx->Tx2Urb)
186 usb_free_urb( pWb35Tx->Tx2Urb ); 189 usb_free_urb( pWb35Tx->Tx2Urb );
187 190
188 #ifdef _PE_TX_DUMP_ 191 #ifdef _PE_TX_DUMP_
189 WBDEBUG(("Wb35Tx_destroy OK\n")); 192 WBDEBUG(("Wb35Tx_destroy OK\n"));
190 #endif 193 #endif
191 } 194 }
192 195
193 void Wb35Tx_CurrentTime(phw_data_t pHwData, u32 TimeCount) 196 void Wb35Tx_CurrentTime(phw_data_t pHwData, u32 TimeCount)
194 { 197 {
195 PWB35TX pWb35Tx = &pHwData->Wb35Tx; 198 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
196 unsigned char Trigger = false; 199 unsigned char Trigger = false;
197 200
198 if (pWb35Tx->TxTimer > TimeCount) 201 if (pWb35Tx->TxTimer > TimeCount)
199 Trigger = true; 202 Trigger = true;
200 else if (TimeCount > (pWb35Tx->TxTimer+500)) 203 else if (TimeCount > (pWb35Tx->TxTimer+500))
201 Trigger = true; 204 Trigger = true;
202 205
203 if (Trigger) { 206 if (Trigger) {
204 pWb35Tx->TxTimer = TimeCount; 207 pWb35Tx->TxTimer = TimeCount;
205 Wb35Tx_EP2VM_start( pHwData ); 208 Wb35Tx_EP2VM_start( pHwData );
206 } 209 }
207 } 210 }
208 211
209 void Wb35Tx_EP2VM_start(phw_data_t pHwData) 212 void Wb35Tx_EP2VM_start(phw_data_t pHwData)
210 { 213 {
211 PWB35TX pWb35Tx = &pHwData->Wb35Tx; 214 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
212 215
213 // Allow only one thread to run into function 216 // Allow only one thread to run into function
214 if (atomic_inc_return(&pWb35Tx->TxResultCount) == 1) { 217 if (atomic_inc_return(&pWb35Tx->TxResultCount) == 1) {
215 pWb35Tx->EP2vm_state = VM_RUNNING; 218 pWb35Tx->EP2vm_state = VM_RUNNING;
216 Wb35Tx_EP2VM( pHwData ); 219 Wb35Tx_EP2VM( pHwData );
217 } 220 }
218 else 221 else
219 atomic_dec(&pWb35Tx->TxResultCount); 222 atomic_dec(&pWb35Tx->TxResultCount);
220 } 223 }
221 224
222 225
223 void Wb35Tx_EP2VM(phw_data_t pHwData) 226 void Wb35Tx_EP2VM(phw_data_t pHwData)
224 { 227 {
225 PWB35TX pWb35Tx = &pHwData->Wb35Tx; 228 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
226 struct urb * pUrb = (struct urb *)pWb35Tx->Tx2Urb; 229 struct urb * pUrb = (struct urb *)pWb35Tx->Tx2Urb;
227 u32 * pltmp = (u32 *)pWb35Tx->EP2_buf; 230 u32 * pltmp = (u32 *)pWb35Tx->EP2_buf;
228 int retv; 231 int retv;
229 232
230 if (pHwData->SurpriseRemove || pHwData->HwStop) 233 if (pHwData->SurpriseRemove || pHwData->HwStop)
231 goto error; 234 goto error;
232 235
233 if (pWb35Tx->tx_halt) 236 if (pWb35Tx->tx_halt)
234 goto error; 237 goto error;
235 238
236 // 239 //
237 // Issuing URB 240 // Issuing URB
238 // 241 //
239 usb_fill_int_urb( pUrb, pHwData->WbUsb.udev, usb_rcvintpipe(pHwData->WbUsb.udev,2), 242 usb_fill_int_urb( pUrb, pHwData->WbUsb.udev, usb_rcvintpipe(pHwData->WbUsb.udev,2),
240 pltmp, MAX_INTERRUPT_LENGTH, Wb35Tx_EP2VM_complete, pHwData, 32); 243 pltmp, MAX_INTERRUPT_LENGTH, Wb35Tx_EP2VM_complete, pHwData, 32);
241 244
242 pWb35Tx->EP2vm_state = VM_RUNNING; 245 pWb35Tx->EP2vm_state = VM_RUNNING;
243 retv = usb_submit_urb(pUrb, GFP_ATOMIC); 246 retv = usb_submit_urb(pUrb, GFP_ATOMIC);
244 247
245 if (retv < 0) { 248 if (retv < 0) {
246 #ifdef _PE_TX_DUMP_ 249 #ifdef _PE_TX_DUMP_
247 WBDEBUG(("EP2 Tx Irp sending error\n")); 250 WBDEBUG(("EP2 Tx Irp sending error\n"));
248 #endif 251 #endif
249 goto error; 252 goto error;
250 } 253 }
251 254
252 return; 255 return;
253 error: 256 error:
254 pWb35Tx->EP2vm_state = VM_STOP; 257 pWb35Tx->EP2vm_state = VM_STOP;
255 atomic_dec(&pWb35Tx->TxResultCount); 258 atomic_dec(&pWb35Tx->TxResultCount);
256 } 259 }
257 260
258 261
259 void Wb35Tx_EP2VM_complete(struct urb * pUrb) 262 void Wb35Tx_EP2VM_complete(struct urb * pUrb)
260 { 263 {
261 phw_data_t pHwData = pUrb->context; 264 phw_data_t pHwData = pUrb->context;
262 T02_DESCRIPTOR T02, TSTATUS; 265 T02_DESCRIPTOR T02, TSTATUS;
263 struct wb35_adapter *adapter = pHwData->adapter; 266 struct wb35_adapter *adapter = pHwData->adapter;
264 PWB35TX pWb35Tx = &pHwData->Wb35Tx; 267 PWB35TX pWb35Tx = &pHwData->Wb35Tx;
265 u32 * pltmp = (u32 *)pWb35Tx->EP2_buf; 268 u32 * pltmp = (u32 *)pWb35Tx->EP2_buf;
266 u32 i; 269 u32 i;
267 u16 InterruptInLength; 270 u16 InterruptInLength;
268 271
269 272
270 // Variable setting 273 // Variable setting
271 pWb35Tx->EP2vm_state = VM_COMPLETED; 274 pWb35Tx->EP2vm_state = VM_COMPLETED;
272 pWb35Tx->EP2VM_status = pUrb->status; 275 pWb35Tx->EP2VM_status = pUrb->status;
273 276
274 // For Linux 2.4. Interrupt will always trigger 277 // For Linux 2.4. Interrupt will always trigger
275 if (pHwData->SurpriseRemove || pHwData->HwStop) // Let WbWlanHalt to handle surprise remove 278 if (pHwData->SurpriseRemove || pHwData->HwStop) // Let WbWlanHalt to handle surprise remove
276 goto error; 279 goto error;
277 280
278 if (pWb35Tx->tx_halt) 281 if (pWb35Tx->tx_halt)
279 goto error; 282 goto error;
280 283
281 //The Urb is completed, check the result 284 //The Urb is completed, check the result
282 if (pWb35Tx->EP2VM_status != 0) { 285 if (pWb35Tx->EP2VM_status != 0) {
283 WBDEBUG(("EP2 IoCompleteRoutine return error\n")); 286 WBDEBUG(("EP2 IoCompleteRoutine return error\n"));
284 pWb35Tx->EP2vm_state= VM_STOP; 287 pWb35Tx->EP2vm_state= VM_STOP;
285 goto error; 288 goto error;
286 } 289 }
287 290
288 // Update the Tx result 291 // Update the Tx result
289 InterruptInLength = pUrb->actual_length; 292 InterruptInLength = pUrb->actual_length;
290 // Modify for minimum memory access and DWORD alignment. 293 // Modify for minimum memory access and DWORD alignment.
291 T02.value = cpu_to_le32(pltmp[0]) >> 8; // [31:8] -> [24:0] 294 T02.value = cpu_to_le32(pltmp[0]) >> 8; // [31:8] -> [24:0]
292 InterruptInLength -= 1;// 20051221.1.c Modify the follow for more stable 295 InterruptInLength -= 1;// 20051221.1.c Modify the follow for more stable
293 InterruptInLength >>= 2; // InterruptInLength/4 296 InterruptInLength >>= 2; // InterruptInLength/4
294 for (i = 1; i <= InterruptInLength; i++) { 297 for (i = 1; i <= InterruptInLength; i++) {
295 T02.value |= ((cpu_to_le32(pltmp[i]) & 0xff) << 24); 298 T02.value |= ((cpu_to_le32(pltmp[i]) & 0xff) << 24);
296 299
297 TSTATUS.value = T02.value; //20061009 anson's endian 300 TSTATUS.value = T02.value; //20061009 anson's endian
298 Mds_SendComplete( adapter, &TSTATUS ); 301 Mds_SendComplete( adapter, &TSTATUS );
299 T02.value = cpu_to_le32(pltmp[i]) >> 8; 302 T02.value = cpu_to_le32(pltmp[i]) >> 8;
300 } 303 }
301 304
302 return; 305 return;
303 error: 306 error:
304 atomic_dec(&pWb35Tx->TxResultCount); 307 atomic_dec(&pWb35Tx->TxResultCount);
305 pWb35Tx->EP2vm_state = VM_STOP; 308 pWb35Tx->EP2vm_state = VM_STOP;
306 } 309 }
307 310
308 311
drivers/staging/winbond/linux/wb35tx_f.h
Diff comments   View file @ 80aba53
1 #ifndef __WINBOND_WB35TX_F_H
2 #define __WINBOND_WB35TX_F_H
3
4 #include "../wbhal_f.h"
5
1 //==================================== 6 //====================================
2 // Interface function declare 7 // Interface function declare
3 //==================================== 8 //====================================
4 unsigned char Wb35Tx_initial( phw_data_t pHwData ); 9 unsigned char Wb35Tx_initial( phw_data_t pHwData );
5 void Wb35Tx_destroy( phw_data_t pHwData ); 10 void Wb35Tx_destroy( phw_data_t pHwData );
6 unsigned char Wb35Tx_get_tx_buffer( phw_data_t pHwData, u8 **pBuffer ); 11 unsigned char Wb35Tx_get_tx_buffer( phw_data_t pHwData, u8 **pBuffer );
7 12
8 void Wb35Tx_EP2VM( phw_data_t pHwData ); 13 void Wb35Tx_EP2VM( phw_data_t pHwData );
9 void Wb35Tx_EP2VM_start( phw_data_t pHwData ); 14 void Wb35Tx_EP2VM_start( phw_data_t pHwData );
10 void Wb35Tx_EP2VM_complete(struct urb *urb); 15 void Wb35Tx_EP2VM_complete(struct urb *urb);
11 16
12 void Wb35Tx_start( phw_data_t pHwData ); 17 void Wb35Tx_start( phw_data_t pHwData );
13 void Wb35Tx_stop( phw_data_t pHwData ); 18 void Wb35Tx_stop( phw_data_t pHwData );
14 void Wb35Tx( phw_data_t pHwData ); 19 void Wb35Tx( phw_data_t pHwData );
15 void Wb35Tx_complete(struct urb *urb); 20 void Wb35Tx_complete(struct urb *urb);
16 void Wb35Tx_reset_descriptor( phw_data_t pHwData ); 21 void Wb35Tx_reset_descriptor( phw_data_t pHwData );
17 22
18 void Wb35Tx_CurrentTime( phw_data_t pHwData, u32 TimeCount ); 23 void Wb35Tx_CurrentTime( phw_data_t pHwData, u32 TimeCount );
24
25 #endif
19 26
drivers/staging/winbond/linux/wb35tx_s.h
Diff comments   View file @ 80aba53
1 #ifndef __WINBOND_WB35_TX_S_H
2 #define __WINBOND_WB35_TX_S_H
3
4 #include "../mds_s.h"
5
1 //==================================== 6 //====================================
2 // IS89C35 Tx related definition 7 // IS89C35 Tx related definition
3 //==================================== 8 //====================================
4 #define TX_INTERFACE 0 // Interface 1 9 #define TX_INTERFACE 0 // Interface 1
5 #define TX_PIPE 3 // endpoint 4 10 #define TX_PIPE 3 // endpoint 4
6 #define TX_INTERRUPT 1 // endpoint 2 11 #define TX_INTERRUPT 1 // endpoint 2
7 #define MAX_INTERRUPT_LENGTH 64 // It must be 64 for EP2 hardware 12 #define MAX_INTERRUPT_LENGTH 64 // It must be 64 for EP2 hardware
8 13
9 14
10 15
11 //==================================== 16 //====================================
12 // Internal variable for module 17 // Internal variable for module
13 //==================================== 18 //====================================
14 19
15 20
16 typedef struct _WB35TX 21 typedef struct _WB35TX
17 { 22 {
18 // For Tx buffer 23 // For Tx buffer
19 u8 TxBuffer[ MAX_USB_TX_BUFFER_NUMBER ][ MAX_USB_TX_BUFFER ]; 24 u8 TxBuffer[ MAX_USB_TX_BUFFER_NUMBER ][ MAX_USB_TX_BUFFER ];
20 25
21 // For Interrupt pipe 26 // For Interrupt pipe
22 u8 EP2_buf[MAX_INTERRUPT_LENGTH]; 27 u8 EP2_buf[MAX_INTERRUPT_LENGTH];
23 28
24 atomic_t TxResultCount;// For thread control of EP2 931130.4.m 29 atomic_t TxResultCount;// For thread control of EP2 931130.4.m
25 atomic_t TxFireCounter;// For thread control of EP4 931130.4.n 30 atomic_t TxFireCounter;// For thread control of EP4 931130.4.n
26 u32 ByteTransfer; 31 u32 ByteTransfer;
27 32
28 u32 TxSendIndex;// The next index of Mds array to be sent 33 u32 TxSendIndex;// The next index of Mds array to be sent
29 u32 EP2vm_state; // for EP2vm state 34 u32 EP2vm_state; // for EP2vm state
30 u32 EP4vm_state; // for EP4vm state 35 u32 EP4vm_state; // for EP4vm state
31 u32 tx_halt; // Stopping VM 36 u32 tx_halt; // Stopping VM
32 37
33 struct urb * Tx4Urb; 38 struct urb * Tx4Urb;
34 struct urb * Tx2Urb; 39 struct urb * Tx2Urb;
35 40
36 int EP2VM_status; 41 int EP2VM_status;
37 int EP4VM_status; 42 int EP4VM_status;
38 43
39 u32 TxFillCount; // 20060928 44 u32 TxFillCount; // 20060928
40 u32 TxTimer; // 20060928 Add if sending packet not great than 13 45 u32 TxTimer; // 20060928 Add if sending packet not great than 13
41 46
42 } WB35TX, *PWB35TX; 47 } WB35TX, *PWB35TX;
48
49 #endif
43 50
drivers/staging/winbond/linux/wbusb.c
Diff comments   View file @ 80aba53
1 /* 1 /*
2 * Copyright 2008 Pavel Machek <pavel@suse.cz> 2 * Copyright 2008 Pavel Machek <pavel@suse.cz>
3 * 3 *
4 * Distribute under GPLv2. 4 * Distribute under GPLv2.
5 */ 5 */
6 #include "sysdef.h"
7 #include <net/mac80211.h> 6 #include <net/mac80211.h>
7 #include <linux/usb.h>
8
9 #include "../mlmetxrx_f.h"
10 #include "../wbhal_f.h"
11 #include "../wblinux_f.h"
8 12
9 MODULE_AUTHOR(DRIVER_AUTHOR); 13 MODULE_AUTHOR(DRIVER_AUTHOR);
10 MODULE_DESCRIPTION(DRIVER_DESC); 14 MODULE_DESCRIPTION(DRIVER_DESC);
11 MODULE_LICENSE("GPL"); 15 MODULE_LICENSE("GPL");
12 MODULE_VERSION("0.1"); 16 MODULE_VERSION("0.1");
13 17
14 static struct usb_device_id wb35_table[] __devinitdata = { 18 static struct usb_device_id wb35_table[] __devinitdata = {
15 {USB_DEVICE(0x0416, 0x0035)}, 19 {USB_DEVICE(0x0416, 0x0035)},
16 {USB_DEVICE(0x18E8, 0x6201)}, 20 {USB_DEVICE(0x18E8, 0x6201)},
17 {USB_DEVICE(0x18E8, 0x6206)}, 21 {USB_DEVICE(0x18E8, 0x6206)},
18 {USB_DEVICE(0x18E8, 0x6217)}, 22 {USB_DEVICE(0x18E8, 0x6217)},
19 {USB_DEVICE(0x18E8, 0x6230)}, 23 {USB_DEVICE(0x18E8, 0x6230)},
20 {USB_DEVICE(0x18E8, 0x6233)}, 24 {USB_DEVICE(0x18E8, 0x6233)},
21 {USB_DEVICE(0x1131, 0x2035)}, 25 {USB_DEVICE(0x1131, 0x2035)},
22 { 0, } 26 { 0, }
23 }; 27 };
24 28
25 MODULE_DEVICE_TABLE(usb, wb35_table); 29 MODULE_DEVICE_TABLE(usb, wb35_table);
26 30
27 static struct ieee80211_rate wbsoft_rates[] = { 31 static struct ieee80211_rate wbsoft_rates[] = {
28 { .bitrate = 10, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 32 { .bitrate = 10, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
29 }; 33 };
30 34
31 static struct ieee80211_channel wbsoft_channels[] = { 35 static struct ieee80211_channel wbsoft_channels[] = {
32 { .center_freq = 2412}, 36 { .center_freq = 2412},
33 }; 37 };
34 38
35 static struct ieee80211_supported_band wbsoft_band_2GHz = { 39 static struct ieee80211_supported_band wbsoft_band_2GHz = {
36 .channels = wbsoft_channels, 40 .channels = wbsoft_channels,
37 .n_channels = ARRAY_SIZE(wbsoft_channels), 41 .n_channels = ARRAY_SIZE(wbsoft_channels),
38 .bitrates = wbsoft_rates, 42 .bitrates = wbsoft_rates,
39 .n_bitrates = ARRAY_SIZE(wbsoft_rates), 43 .n_bitrates = ARRAY_SIZE(wbsoft_rates),
40 }; 44 };
41 45
42 int wbsoft_enabled; 46 int wbsoft_enabled;
43 struct ieee80211_hw *my_dev; 47 struct ieee80211_hw *my_dev;
44 struct wb35_adapter * my_adapter; 48 struct wb35_adapter * my_adapter;
45 49
46 static int wbsoft_add_interface(struct ieee80211_hw *dev, 50 static int wbsoft_add_interface(struct ieee80211_hw *dev,
47 struct ieee80211_if_init_conf *conf) 51 struct ieee80211_if_init_conf *conf)
48 { 52 {
49 printk("wbsoft_add interface called\n"); 53 printk("wbsoft_add interface called\n");
50 return 0; 54 return 0;
51 } 55 }
52 56
53 static void wbsoft_remove_interface(struct ieee80211_hw *dev, 57 static void wbsoft_remove_interface(struct ieee80211_hw *dev,
54 struct ieee80211_if_init_conf *conf) 58 struct ieee80211_if_init_conf *conf)
55 { 59 {
56 printk("wbsoft_remove interface called\n"); 60 printk("wbsoft_remove interface called\n");
57 } 61 }
58 62
59 static void wbsoft_stop(struct ieee80211_hw *hw) 63 static void wbsoft_stop(struct ieee80211_hw *hw)
60 { 64 {
61 printk(KERN_INFO "%s called\n", __func__); 65 printk(KERN_INFO "%s called\n", __func__);
62 } 66 }
63 67
64 static int wbsoft_get_stats(struct ieee80211_hw *hw, 68 static int wbsoft_get_stats(struct ieee80211_hw *hw,
65 struct ieee80211_low_level_stats *stats) 69 struct ieee80211_low_level_stats *stats)
66 { 70 {
67 printk(KERN_INFO "%s called\n", __func__); 71 printk(KERN_INFO "%s called\n", __func__);
68 return 0; 72 return 0;
69 } 73 }
70 74
71 static int wbsoft_get_tx_stats(struct ieee80211_hw *hw, 75 static int wbsoft_get_tx_stats(struct ieee80211_hw *hw,
72 struct ieee80211_tx_queue_stats *stats) 76 struct ieee80211_tx_queue_stats *stats)
73 { 77 {
74 printk(KERN_INFO "%s called\n", __func__); 78 printk(KERN_INFO "%s called\n", __func__);
75 return 0; 79 return 0;
76 } 80 }
77 81
78 static void wbsoft_configure_filter(struct ieee80211_hw *dev, 82 static void wbsoft_configure_filter(struct ieee80211_hw *dev,
79 unsigned int changed_flags, 83 unsigned int changed_flags,
80 unsigned int *total_flags, 84 unsigned int *total_flags,
81 int mc_count, struct dev_mc_list *mclist) 85 int mc_count, struct dev_mc_list *mclist)
82 { 86 {
83 unsigned int bit_nr, new_flags; 87 unsigned int bit_nr, new_flags;
84 u32 mc_filter[2]; 88 u32 mc_filter[2];
85 int i; 89 int i;
86 90
87 new_flags = 0; 91 new_flags = 0;
88 92
89 if (*total_flags & FIF_PROMISC_IN_BSS) { 93 if (*total_flags & FIF_PROMISC_IN_BSS) {
90 new_flags |= FIF_PROMISC_IN_BSS; 94 new_flags |= FIF_PROMISC_IN_BSS;
91 mc_filter[1] = mc_filter[0] = ~0; 95 mc_filter[1] = mc_filter[0] = ~0;
92 } else if ((*total_flags & FIF_ALLMULTI) || (mc_count > 32)) { 96 } else if ((*total_flags & FIF_ALLMULTI) || (mc_count > 32)) {
93 new_flags |= FIF_ALLMULTI; 97 new_flags |= FIF_ALLMULTI;
94 mc_filter[1] = mc_filter[0] = ~0; 98 mc_filter[1] = mc_filter[0] = ~0;
95 } else { 99 } else {
96 mc_filter[1] = mc_filter[0] = 0; 100 mc_filter[1] = mc_filter[0] = 0;
97 for (i = 0; i < mc_count; i++) { 101 for (i = 0; i < mc_count; i++) {
98 if (!mclist) 102 if (!mclist)
99 break; 103 break;
100 printk("Should call ether_crc here\n"); 104 printk("Should call ether_crc here\n");
101 //bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26; 105 //bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
102 bit_nr = 0; 106 bit_nr = 0;
103 107
104 bit_nr &= 0x3F; 108 bit_nr &= 0x3F;
105 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 109 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
106 mclist = mclist->next; 110 mclist = mclist->next;
107 } 111 }
108 } 112 }
109 113
110 dev->flags &= ~IEEE80211_HW_RX_INCLUDES_FCS; 114 dev->flags &= ~IEEE80211_HW_RX_INCLUDES_FCS;
111 115
112 *total_flags = new_flags; 116 *total_flags = new_flags;
113 } 117 }
114 118
115 static int wbsoft_tx(struct ieee80211_hw *dev, struct sk_buff *skb) 119 static int wbsoft_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
116 { 120 {
117 MLMESendFrame(my_adapter, skb->data, skb->len, FRAME_TYPE_802_11_MANAGEMENT); 121 MLMESendFrame(my_adapter, skb->data, skb->len, FRAME_TYPE_802_11_MANAGEMENT);
118 122
119 return NETDEV_TX_OK; 123 return NETDEV_TX_OK;
120 } 124 }
121 125
122 126
123 static int wbsoft_start(struct ieee80211_hw *dev) 127 static int wbsoft_start(struct ieee80211_hw *dev)
124 { 128 {
125 wbsoft_enabled = 1; 129 wbsoft_enabled = 1;
126 printk("wbsoft_start called\n"); 130 printk("wbsoft_start called\n");
127 return 0; 131 return 0;
128 } 132 }
129 133
130 static int wbsoft_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf) 134 static int wbsoft_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
131 { 135 {
132 ChanInfo ch; 136 ChanInfo ch;
133 printk("wbsoft_config called\n"); 137 printk("wbsoft_config called\n");
134 138
135 ch.band = 1; 139 ch.band = 1;
136 ch.ChanNo = 1; /* Should use channel_num, or something, as that is already pre-translated */ 140 ch.ChanNo = 1; /* Should use channel_num, or something, as that is already pre-translated */
137 141
138 142
139 hal_set_current_channel(&my_adapter->sHwData, ch); 143 hal_set_current_channel(&my_adapter->sHwData, ch);
140 hal_set_beacon_period(&my_adapter->sHwData, conf->beacon_int); 144 hal_set_beacon_period(&my_adapter->sHwData, conf->beacon_int);
141 // hal_set_cap_info(&my_adapter->sHwData, ?? ); 145 // hal_set_cap_info(&my_adapter->sHwData, ?? );
142 // hal_set_ssid(phw_data_t pHwData, u8 * pssid, u8 ssid_len); ?? 146 // hal_set_ssid(phw_data_t pHwData, u8 * pssid, u8 ssid_len); ??
143 hal_set_accept_broadcast(&my_adapter->sHwData, 1); 147 hal_set_accept_broadcast(&my_adapter->sHwData, 1);
144 hal_set_accept_promiscuous(&my_adapter->sHwData, 1); 148 hal_set_accept_promiscuous(&my_adapter->sHwData, 1);
145 hal_set_accept_multicast(&my_adapter->sHwData, 1); 149 hal_set_accept_multicast(&my_adapter->sHwData, 1);
146 hal_set_accept_beacon(&my_adapter->sHwData, 1); 150 hal_set_accept_beacon(&my_adapter->sHwData, 1);
147 hal_set_radio_mode(&my_adapter->sHwData, 0); 151 hal_set_radio_mode(&my_adapter->sHwData, 0);
148 //hal_set_antenna_number( phw_data_t pHwData, u8 number ) 152 //hal_set_antenna_number( phw_data_t pHwData, u8 number )
149 //hal_set_rf_power(phw_data_t pHwData, u8 PowerIndex) 153 //hal_set_rf_power(phw_data_t pHwData, u8 PowerIndex)
150 154
151 155
152 // hal_start_bss(&my_adapter->sHwData, WLAN_BSSTYPE_INFRASTRUCTURE); ?? 156 // hal_start_bss(&my_adapter->sHwData, WLAN_BSSTYPE_INFRASTRUCTURE); ??
153 157
154 //void hal_set_rates(phw_data_t pHwData, u8 * pbss_rates, 158 //void hal_set_rates(phw_data_t pHwData, u8 * pbss_rates,
155 // u8 length, unsigned char basic_rate_set) 159 // u8 length, unsigned char basic_rate_set)
156 160
157 return 0; 161 return 0;
158 } 162 }
159 163
160 static int wbsoft_config_interface(struct ieee80211_hw *dev, 164 static int wbsoft_config_interface(struct ieee80211_hw *dev,
161 struct ieee80211_vif *vif, 165 struct ieee80211_vif *vif,
162 struct ieee80211_if_conf *conf) 166 struct ieee80211_if_conf *conf)
163 { 167 {
164 printk("wbsoft_config_interface called\n"); 168 printk("wbsoft_config_interface called\n");
165 return 0; 169 return 0;
166 } 170 }
167 171
168 static u64 wbsoft_get_tsf(struct ieee80211_hw *dev) 172 static u64 wbsoft_get_tsf(struct ieee80211_hw *dev)
169 { 173 {
170 printk("wbsoft_get_tsf called\n"); 174 printk("wbsoft_get_tsf called\n");
171 return 0; 175 return 0;
172 } 176 }
173 177
174 static const struct ieee80211_ops wbsoft_ops = { 178 static const struct ieee80211_ops wbsoft_ops = {
175 .tx = wbsoft_tx, 179 .tx = wbsoft_tx,
176 .start = wbsoft_start, /* Start can be pretty much empty as we do WbWLanInitialize() during probe? */ 180 .start = wbsoft_start, /* Start can be pretty much empty as we do WbWLanInitialize() during probe? */
177 .stop = wbsoft_stop, 181 .stop = wbsoft_stop,
178 .add_interface = wbsoft_add_interface, 182 .add_interface = wbsoft_add_interface,
179 .remove_interface = wbsoft_remove_interface, 183 .remove_interface = wbsoft_remove_interface,
180 .config = wbsoft_config, 184 .config = wbsoft_config,
181 .config_interface = wbsoft_config_interface, 185 .config_interface = wbsoft_config_interface,
182 .configure_filter = wbsoft_configure_filter, 186 .configure_filter = wbsoft_configure_filter,
183 .get_stats = wbsoft_get_stats, 187 .get_stats = wbsoft_get_stats,
184 .get_tx_stats = wbsoft_get_tx_stats, 188 .get_tx_stats = wbsoft_get_tx_stats,
185 .get_tsf = wbsoft_get_tsf, 189 .get_tsf = wbsoft_get_tsf,
186 // conf_tx: hal_set_cwmin()/hal_set_cwmax; 190 // conf_tx: hal_set_cwmin()/hal_set_cwmax;
187 }; 191 };
188 192
189 struct wbsoft_priv { 193 struct wbsoft_priv {
190 }; 194 };
191 195
192 static int wb35_probe(struct usb_interface *intf, const struct usb_device_id *id_table) 196 static int wb35_probe(struct usb_interface *intf, const struct usb_device_id *id_table)
193 { 197 {
194 struct wb35_adapter *adapter; 198 struct wb35_adapter *adapter;
195 PWBUSB pWbUsb; 199 PWBUSB pWbUsb;
196 struct usb_host_interface *interface; 200 struct usb_host_interface *interface;
197 struct usb_endpoint_descriptor *endpoint; 201 struct usb_endpoint_descriptor *endpoint;
198 u32 ltmp; 202 u32 ltmp;
199 struct usb_device *udev = interface_to_usbdev(intf); 203 struct usb_device *udev = interface_to_usbdev(intf);
200 struct wbsoft_priv *priv; 204 struct wbsoft_priv *priv;
201 struct ieee80211_hw *dev; 205 struct ieee80211_hw *dev;
202 int err; 206 int err;
203 207
204 usb_get_dev(udev); 208 usb_get_dev(udev);
205 209
206 // 20060630.2 Check the device if it already be opened 210 // 20060630.2 Check the device if it already be opened
207 err = usb_control_msg(udev, usb_rcvctrlpipe( udev, 0 ), 211 err = usb_control_msg(udev, usb_rcvctrlpipe( udev, 0 ),
208 0x01, USB_TYPE_VENDOR|USB_RECIP_DEVICE|USB_DIR_IN, 212 0x01, USB_TYPE_VENDOR|USB_RECIP_DEVICE|USB_DIR_IN,
209 0x0, 0x400, &ltmp, 4, HZ*100 ); 213 0x0, 0x400, &ltmp, 4, HZ*100 );
210 if (err) 214 if (err)
211 goto error; 215 goto error;
212 216
213 ltmp = cpu_to_le32(ltmp); 217 ltmp = cpu_to_le32(ltmp);
214 if (ltmp) { // Is already initialized? 218 if (ltmp) { // Is already initialized?
215 err = -EBUSY; 219 err = -EBUSY;
216 goto error; 220 goto error;
217 } 221 }
218 222
219 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL); 223 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
220 if (!adapter) { 224 if (!adapter) {
221 err = -ENOMEM; 225 err = -ENOMEM;
222 goto error; 226 goto error;
223 } 227 }
224 228
225 my_adapter = adapter; 229 my_adapter = adapter;
226 pWbUsb = &adapter->sHwData.WbUsb; 230 pWbUsb = &adapter->sHwData.WbUsb;
227 pWbUsb->udev = udev; 231 pWbUsb->udev = udev;
228 232
229 interface = intf->cur_altsetting; 233 interface = intf->cur_altsetting;
230 endpoint = &interface->endpoint[0].desc; 234 endpoint = &interface->endpoint[0].desc;
231 235
232 if (endpoint[2].wMaxPacketSize == 512) { 236 if (endpoint[2].wMaxPacketSize == 512) {
233 printk("[w35und] Working on USB 2.0\n"); 237 printk("[w35und] Working on USB 2.0\n");
234 pWbUsb->IsUsb20 = 1; 238 pWbUsb->IsUsb20 = 1;
235 } 239 }
236 240
237 if (!WbWLanInitialize(adapter)) { 241 if (!WbWLanInitialize(adapter)) {
238 err = -EINVAL; 242 err = -EINVAL;
239 goto error_free_adapter; 243 goto error_free_adapter;
240 } 244 }
241 245
242 dev = ieee80211_alloc_hw(sizeof(*priv), &wbsoft_ops); 246 dev = ieee80211_alloc_hw(sizeof(*priv), &wbsoft_ops);
243 if (!dev) 247 if (!dev)
244 goto error_free_adapter; 248 goto error_free_adapter;
245 249
246 my_dev = dev; 250 my_dev = dev;
247 251
248 SET_IEEE80211_DEV(dev, &udev->dev); 252 SET_IEEE80211_DEV(dev, &udev->dev);
249 { 253 {
250 phw_data_t pHwData = &adapter->sHwData; 254 phw_data_t pHwData = &adapter->sHwData;
251 unsigned char dev_addr[MAX_ADDR_LEN]; 255 unsigned char dev_addr[MAX_ADDR_LEN];
252 hal_get_permanent_address(pHwData, dev_addr); 256 hal_get_permanent_address(pHwData, dev_addr);
253 SET_IEEE80211_PERM_ADDR(dev, dev_addr); 257 SET_IEEE80211_PERM_ADDR(dev, dev_addr);
254 } 258 }
255 259
256 dev->extra_tx_headroom = 12; /* FIXME */ 260 dev->extra_tx_headroom = 12; /* FIXME */
257 dev->flags = 0; 261 dev->flags = 0;
258 262
259 dev->channel_change_time = 1000; 263 dev->channel_change_time = 1000;
260 dev->queues = 1; 264 dev->queues = 1;
261 265
262 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &wbsoft_band_2GHz; 266 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &wbsoft_band_2GHz;
263 267
264 err = ieee80211_register_hw(dev); 268 err = ieee80211_register_hw(dev);
265 if (err) 269 if (err)
266 goto error_free_hw; 270 goto error_free_hw;
267 271
268 usb_set_intfdata(intf, adapter); 272 usb_set_intfdata(intf, adapter);
269 273
270 return 0; 274 return 0;
271 275
272 error_free_hw: 276 error_free_hw:
273 ieee80211_free_hw(dev); 277 ieee80211_free_hw(dev);
274 error_free_adapter: 278 error_free_adapter:
275 kfree(adapter); 279 kfree(adapter);
276 error: 280 error:
277 usb_put_dev(udev); 281 usb_put_dev(udev);
278 return err; 282 return err;
279 } 283 }
280 284
281 void packet_came(char *pRxBufferAddress, int PacketSize) 285 void packet_came(char *pRxBufferAddress, int PacketSize)
282 { 286 {
283 struct sk_buff *skb; 287 struct sk_buff *skb;
284 struct ieee80211_rx_status rx_status = {0}; 288 struct ieee80211_rx_status rx_status = {0};
285 289
286 if (!wbsoft_enabled) 290 if (!wbsoft_enabled)
287 return; 291 return;
288 292
289 skb = dev_alloc_skb(PacketSize); 293 skb = dev_alloc_skb(PacketSize);
290 if (!skb) { 294 if (!skb) {
291 printk("Not enough memory for packet, FIXME\n"); 295 printk("Not enough memory for packet, FIXME\n");
292 return; 296 return;
293 } 297 }
294 298
295 memcpy(skb_put(skb, PacketSize), 299 memcpy(skb_put(skb, PacketSize),
296 pRxBufferAddress, 300 pRxBufferAddress,
297 PacketSize); 301 PacketSize);
298 302
299 /* 303 /*
300 rx_status.rate = 10; 304 rx_status.rate = 10;
301 rx_status.channel = 1; 305 rx_status.channel = 1;
302 rx_status.freq = 12345; 306 rx_status.freq = 12345;
303 rx_status.phymode = MODE_IEEE80211B; 307 rx_status.phymode = MODE_IEEE80211B;
304 */ 308 */
305 309
306 ieee80211_rx_irqsafe(my_dev, skb, &rx_status); 310 ieee80211_rx_irqsafe(my_dev, skb, &rx_status);
307 } 311 }
308 312
309 static void wb35_disconnect(struct usb_interface *intf) 313 static void wb35_disconnect(struct usb_interface *intf)
310 { 314 {
311 struct wb35_adapter *adapter = usb_get_intfdata(intf); 315 struct wb35_adapter *adapter = usb_get_intfdata(intf);
312 316
313 WbWlanHalt(adapter); 317 WbWlanHalt(adapter);
314 318
315 usb_set_intfdata(intf, NULL); 319 usb_set_intfdata(intf, NULL);
316 usb_put_dev(interface_to_usbdev(intf)); 320 usb_put_dev(interface_to_usbdev(intf));
317 } 321 }
318 322
319 static struct usb_driver wb35_driver = { 323 static struct usb_driver wb35_driver = {
320 .name = "w35und", 324 .name = "w35und",
321 .id_table = wb35_table, 325 .id_table = wb35_table,
322 .probe = wb35_probe, 326 .probe = wb35_probe,
323 .disconnect = wb35_disconnect, 327 .disconnect = wb35_disconnect,
324 }; 328 };
325 329
326 static int __init wb35_init(void) 330 static int __init wb35_init(void)
327 { 331 {
328 return usb_register(&wb35_driver); 332 return usb_register(&wb35_driver);
329 } 333 }
330 334
331 static void __exit wb35_exit(void) 335 static void __exit wb35_exit(void)
332 { 336 {
333 usb_deregister(&wb35_driver); 337 usb_deregister(&wb35_driver);
334 } 338 }
335 339
336 module_init(wb35_init); 340 module_init(wb35_init);
337 module_exit(wb35_exit); 341 module_exit(wb35_exit);
drivers/staging/winbond/linux/wbusb_s.h
Diff comments   View file @ 80aba53
1 //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2 // Copyright (c) 1996-2004 Winbond Electronic Corporation 2 // Copyright (c) 1996-2004 Winbond Electronic Corporation
3 // 3 //
4 // Module Name: 4 // Module Name:
5 // wbusb_s.h 5 // wbusb_s.h
6 // 6 //
7 // Abstract: 7 // Abstract:
8 // Linux driver. 8 // Linux driver.
9 // 9 //
10 // Author: 10 // Author:
11 // 11 //
12 //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 12 //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
13 13
14 #ifndef __WINBOND_WBUSB_S_H
15 #define __WINBOND_WBUSB_S_H
16
17 #include <linux/types.h>
18
14 //--------------------------------------------------------------------------- 19 //---------------------------------------------------------------------------
15 // RW_CONTEXT -- 20 // RW_CONTEXT --
16 // 21 //
17 // Used to track driver-generated io irps 22 // Used to track driver-generated io irps
18 //--------------------------------------------------------------------------- 23 //---------------------------------------------------------------------------
19 typedef struct _RW_CONTEXT 24 typedef struct _RW_CONTEXT
20 { 25 {
21 void* pHwData; 26 void* pHwData;
22 struct urb *urb; 27 struct urb *urb;
23 void* pCallBackFunctionParameter; 28 void* pCallBackFunctionParameter;
24 } RW_CONTEXT, *PRW_CONTEXT; 29 } RW_CONTEXT, *PRW_CONTEXT;
25 30
26
27
28
29 #define DRIVER_AUTHOR "Original by: Jeff Lee<YY_Lee@issc.com.tw> Adapted to 2.6.x by Costantino Leandro (Rxart Desktop) <le_costantino@pixartargentina.com.ar>" 31 #define DRIVER_AUTHOR "Original by: Jeff Lee<YY_Lee@issc.com.tw> Adapted to 2.6.x by Costantino Leandro (Rxart Desktop) <le_costantino@pixartargentina.com.ar>"
30 #define DRIVER_DESC "IS89C35 802.11bg WLAN USB Driver" 32 #define DRIVER_DESC "IS89C35 802.11bg WLAN USB Driver"
31 33
32
33
34 typedef struct _WBUSB { 34 typedef struct _WBUSB {
35 u32 IsUsb20; 35 u32 IsUsb20;
36 struct usb_device *udev; 36 struct usb_device *udev;
drivers/staging/winbond/localpara.h
Diff comments   View file @ 80aba53
1 #ifndef __WINBOND_LOCALPARA_H
2 #define __WINBOND_LOCALPARA_H
3
1 //============================================================= 4 //=============================================================
2 // LocalPara.h - 5 // LocalPara.h -
3 //============================================================= 6 //=============================================================
7
8 #include "mac_structures.h"
9
4 //Define the local ability 10 //Define the local ability
5 11
6 #define LOCAL_DEFAULT_BEACON_PERIOD 100 //ms 12 #define LOCAL_DEFAULT_BEACON_PERIOD 100 //ms
7 #define LOCAL_DEFAULT_ATIM_WINDOW 0 13 #define LOCAL_DEFAULT_ATIM_WINDOW 0
8 #define LOCAL_DEFAULT_ERP_CAPABILITY 0x0431 //0x0001: ESS 14 #define LOCAL_DEFAULT_ERP_CAPABILITY 0x0431 //0x0001: ESS
9 //0x0010: Privacy 15 //0x0010: Privacy
10 //0x0020: short preamble 16 //0x0020: short preamble
11 //0x0400: short slot time 17 //0x0400: short slot time
12 #define LOCAL_DEFAULT_LISTEN_INTERVAL 5 18 #define LOCAL_DEFAULT_LISTEN_INTERVAL 5
13 19
14 //#define LOCAL_DEFAULT_24_CHANNEL_NUM 11 // channel 1..11 20 //#define LOCAL_DEFAULT_24_CHANNEL_NUM 11 // channel 1..11
15 #define LOCAL_DEFAULT_24_CHANNEL_NUM 13 // channel 1..13 21 #define LOCAL_DEFAULT_24_CHANNEL_NUM 13 // channel 1..13
16 #define LOCAL_DEFAULT_5_CHANNEL_NUM 8 // channel 36..64 22 #define LOCAL_DEFAULT_5_CHANNEL_NUM 8 // channel 36..64
17 23
18 #define LOCAL_USA_24_CHANNEL_NUM 11 24 #define LOCAL_USA_24_CHANNEL_NUM 11
19 #define LOCAL_USA_5_CHANNEL_NUM 12 25 #define LOCAL_USA_5_CHANNEL_NUM 12
20 #define LOCAL_EUROPE_24_CHANNEL_NUM 13 26 #define LOCAL_EUROPE_24_CHANNEL_NUM 13
21 #define LOCAL_EUROPE_5_CHANNEL_NUM 19 27 #define LOCAL_EUROPE_5_CHANNEL_NUM 19
22 #define LOCAL_JAPAN_24_CHANNEL_NUM 14 28 #define LOCAL_JAPAN_24_CHANNEL_NUM 14
23 #define LOCAL_JAPAN_5_CHANNEL_NUM 11 29 #define LOCAL_JAPAN_5_CHANNEL_NUM 11
24 #define LOCAL_UNKNOWN_24_CHANNEL_NUM 14 30 #define LOCAL_UNKNOWN_24_CHANNEL_NUM 14
25 #define LOCAL_UNKNOWN_5_CHANNEL_NUM 34 //not include 165 31 #define LOCAL_UNKNOWN_5_CHANNEL_NUM 34 //not include 165
26 32
27 33
28 #define psLOCAL (&(adapter->sLocalPara)) 34 #define psLOCAL (&(adapter->sLocalPara))
29 35
30 #define MODE_802_11_BG 0 36 #define MODE_802_11_BG 0
31 #define MODE_802_11_A 1 37 #define MODE_802_11_A 1
32 #define MODE_802_11_ABG 2 38 #define MODE_802_11_ABG 2
33 #define MODE_802_11_BG_IBSS 3 39 #define MODE_802_11_BG_IBSS 3
34 #define MODE_802_11_B 4 40 #define MODE_802_11_B 4
35 #define MODE_AUTO 255 41 #define MODE_AUTO 255
36 42
37 #define BAND_TYPE_DSSS 0 43 #define BAND_TYPE_DSSS 0
38 #define BAND_TYPE_OFDM_24 1 44 #define BAND_TYPE_OFDM_24 1
39 #define BAND_TYPE_OFDM_5 2 45 #define BAND_TYPE_OFDM_5 2
40 46
41 //refer Bitmap2RateValue table 47 //refer Bitmap2RateValue table
42 #define LOCAL_ALL_SUPPORTED_RATES_BITMAP 0x130c1a66 //the bitmap value of all the H/W supported rates 48 #define LOCAL_ALL_SUPPORTED_RATES_BITMAP 0x130c1a66 //the bitmap value of all the H/W supported rates
43 //1, 2, 5.5, 11, 6, 9, 12, 18, 24, 36, 48, 54 49 //1, 2, 5.5, 11, 6, 9, 12, 18, 24, 36, 48, 54
44 #define LOCAL_OFDM_SUPPORTED_RATES_BITMAP 0x130c1240 //the bitmap value of all the H/W supported rates 50 #define LOCAL_OFDM_SUPPORTED_RATES_BITMAP 0x130c1240 //the bitmap value of all the H/W supported rates
45 //except to non-OFDM rates 51 //except to non-OFDM rates
46 //6, 9, 12, 18, 24, 36, 48, 54 52 //6, 9, 12, 18, 24, 36, 48, 54
47 53
48 #define LOCAL_11B_SUPPORTED_RATE_BITMAP 0x826 54 #define LOCAL_11B_SUPPORTED_RATE_BITMAP 0x826
49 #define LOCAL_11B_BASIC_RATE_BITMAP 0x826 55 #define LOCAL_11B_BASIC_RATE_BITMAP 0x826
50 #define LOCAL_11B_OPERATION_RATE_BITMAP 0x826 56 #define LOCAL_11B_OPERATION_RATE_BITMAP 0x826
51 #define LOCAL_11G_BASIC_RATE_BITMAP 0x826 //1, 2, 5.5, 11 57 #define LOCAL_11G_BASIC_RATE_BITMAP 0x826 //1, 2, 5.5, 11
52 #define LOCAL_11G_OPERATION_RATE_BITMAP 0x130c1240 //6, 9, 12, 18, 24, 36, 48, 54 58 #define LOCAL_11G_OPERATION_RATE_BITMAP 0x130c1240 //6, 9, 12, 18, 24, 36, 48, 54
53 #define LOCAL_11A_BASIC_RATE_BITMAP 0x01001040 //6, 12, 24 59 #define LOCAL_11A_BASIC_RATE_BITMAP 0x01001040 //6, 12, 24
54 #define LOCAL_11A_OPERATION_RATE_BITMAP 0x120c0200 //9, 18, 36, 48, 54 60 #define LOCAL_11A_OPERATION_RATE_BITMAP 0x120c0200 //9, 18, 36, 48, 54
55 61
56 62
57 63
58 #define PWR_ACTIVE 0 64 #define PWR_ACTIVE 0
59 #define PWR_SAVE 1 65 #define PWR_SAVE 1
60 #define PWR_TX_IDLE_CYCLE 6 66 #define PWR_TX_IDLE_CYCLE 6
61 67
62 //bPreambleMode and bSlotTimeMode 68 //bPreambleMode and bSlotTimeMode
63 #define AUTO_MODE 0 69 #define AUTO_MODE 0
64 #define LONG_MODE 1 70 #define LONG_MODE 1
65 71
66 //Region definition 72 //Region definition
67 #define REGION_AUTO 0xff 73 #define REGION_AUTO 0xff
68 #define REGION_UNKNOWN 0 74 #define REGION_UNKNOWN 0
69 #define REGION_EUROPE 1 //ETSI 75 #define REGION_EUROPE 1 //ETSI
70 #define REGION_JAPAN 2 //MKK 76 #define REGION_JAPAN 2 //MKK
71 #define REGION_USA 3 //FCC 77 #define REGION_USA 3 //FCC
72 #define REGION_FRANCE 4 //FRANCE 78 #define REGION_FRANCE 4 //FRANCE
73 #define REGION_SPAIN 5 //SPAIN 79 #define REGION_SPAIN 5 //SPAIN
74 #define REGION_ISRAEL 6 //ISRAEL 80 #define REGION_ISRAEL 6 //ISRAEL
75 //#define REGION_CANADA 7 //IC 81 //#define REGION_CANADA 7 //IC
76 82
77 #define MAX_BSS_DESCRIPT_ELEMENT 32 83 #define MAX_BSS_DESCRIPT_ELEMENT 32
78 #define MAX_PMKID_CandidateList 16 84 #define MAX_PMKID_CandidateList 16
79 85
80 //High byte : Event number, low byte : reason 86 //High byte : Event number, low byte : reason
81 //Event definition 87 //Event definition
82 //-- SME/MLME event 88 //-- SME/MLME event
83 #define EVENT_RCV_DEAUTH 0x0100 89 #define EVENT_RCV_DEAUTH 0x0100
84 #define EVENT_JOIN_FAIL 0x0200 90 #define EVENT_JOIN_FAIL 0x0200
85 #define EVENT_AUTH_FAIL 0x0300 91 #define EVENT_AUTH_FAIL 0x0300
86 #define EVENT_ASSOC_FAIL 0x0400 92 #define EVENT_ASSOC_FAIL 0x0400
87 #define EVENT_LOST_SIGNAL 0x0500 93 #define EVENT_LOST_SIGNAL 0x0500
88 #define EVENT_BSS_DESCRIPT_LACK 0x0600 94 #define EVENT_BSS_DESCRIPT_LACK 0x0600
89 #define EVENT_COUNTERMEASURE 0x0700 95 #define EVENT_COUNTERMEASURE 0x0700
90 #define EVENT_JOIN_FILTER 0x0800 96 #define EVENT_JOIN_FILTER 0x0800
91 //-- TX/RX event 97 //-- TX/RX event
92 #define EVENT_RX_BUFF_UNAVAILABLE 0x4100 98 #define EVENT_RX_BUFF_UNAVAILABLE 0x4100
93 99
94 #define EVENT_CONNECT 0x8100 100 #define EVENT_CONNECT 0x8100
95 #define EVENT_DISCONNECT 0x8200 101 #define EVENT_DISCONNECT 0x8200
96 #define EVENT_SCAN_REQ 0x8300 102 #define EVENT_SCAN_REQ 0x8300
97 103
98 //Reason of Event 104 //Reason of Event
99 #define EVENT_REASON_FILTER_BASIC_RATE 0x0001 105 #define EVENT_REASON_FILTER_BASIC_RATE 0x0001
100 #define EVENT_REASON_FILTER_PRIVACY 0x0002 106 #define EVENT_REASON_FILTER_PRIVACY 0x0002
101 #define EVENT_REASON_FILTER_AUTH_MODE 0x0003 107 #define EVENT_REASON_FILTER_AUTH_MODE 0x0003
102 #define EVENT_REASON_TIMEOUT 0x00ff 108 #define EVENT_REASON_TIMEOUT 0x00ff
103 109
104 // 20061108 WPS IE buffer 110 // 20061108 WPS IE buffer
105 #define MAX_IE_APPEND_SIZE 256 + 4 // Due to [E id][Length][OUI][Data] may 257 bytes 111 #define MAX_IE_APPEND_SIZE 256 + 4 // Due to [E id][Length][OUI][Data] may 257 bytes
106 112
107 typedef struct _EVENTLOG 113 typedef struct _EVENTLOG
108 { 114 {
109 u16 Count; //Total count from start 115 u16 Count; //Total count from start
110 u16 index; //Buffer index, 0 ~ 63 116 u16 index; //Buffer index, 0 ~ 63
111 u32 EventValue[64]; //BYTE 3~2 : count, BYTE 1 : Event, BYTE 0 : reason 117 u32 EventValue[64]; //BYTE 3~2 : count, BYTE 1 : Event, BYTE 0 : reason
112 } Event_Log, *pEvent_Log; 118 } Event_Log, *pEvent_Log;
113 119
114 typedef struct _ChanInfo 120 typedef struct _ChanInfo
115 { 121 {
116 u8 band; 122 u8 band;
117 u8 ChanNo; 123 u8 ChanNo;
118 } ChanInfo, *pChanInfo; 124 } ChanInfo, *pChanInfo;
119 125
120 typedef struct _CHAN_LIST 126 typedef struct _CHAN_LIST
121 { 127 {
122 u16 Count; 128 u16 Count;
123 ChanInfo Channel[50]; // 100B 129 ChanInfo Channel[50]; // 100B
124 } CHAN_LIST, *psCHAN_LIST; 130 } CHAN_LIST, *psCHAN_LIST;
125 131
126 typedef struct _RadioOff 132 typedef struct _RadioOff
127 { 133 {
128 u8 boHwRadioOff; 134 u8 boHwRadioOff;
129 u8 boSwRadioOff; 135 u8 boSwRadioOff;
130 } RadioOff, *psRadioOff; 136 } RadioOff, *psRadioOff;
131 137
132 //=========================================================================== 138 //===========================================================================
133 typedef struct LOCAL_PARA 139 typedef struct LOCAL_PARA
134 { 140 {
135 u8 PermanentAddress[ MAC_ADDR_LENGTH + 2 ]; // read from EPROM, manufacture set for each NetCard 141 u8 PermanentAddress[ MAC_ADDR_LENGTH + 2 ]; // read from EPROM, manufacture set for each NetCard
136 u8 ThisMacAddress[ MAC_ADDR_LENGTH + 2 ]; // the driver will use actually. 142 u8 ThisMacAddress[ MAC_ADDR_LENGTH + 2 ]; // the driver will use actually.
137 143
138 u32 MTUsize; // Ind to Uplayer, Max transmission unit size 144 u32 MTUsize; // Ind to Uplayer, Max transmission unit size
139 145
140 u8 region_INF; //region setting from INF 146 u8 region_INF; //region setting from INF
141 u8 region; //real region setting of the device 147 u8 region; //real region setting of the device
142 u8 Reserved_1[2]; 148 u8 Reserved_1[2];
143 149
144 //// power-save variables 150 //// power-save variables
145 u8 iPowerSaveMode; // 0 indicates it is on, 1 indicates it is off 151 u8 iPowerSaveMode; // 0 indicates it is on, 1 indicates it is off
146 u8 ShutDowned; 152 u8 ShutDowned;
147 u8 ATIMmode; 153 u8 ATIMmode;
148 u8 ExcludeUnencrypted; 154 u8 ExcludeUnencrypted;
149 155
150 u16 CheckCountForPS; //Unit ime count for the decision to enter PS mode 156 u16 CheckCountForPS; //Unit ime count for the decision to enter PS mode
151 u8 boHasTxActivity; //tx activity has occurred 157 u8 boHasTxActivity; //tx activity has occurred
152 u8 boMacPsValid; //Power save mode obtained from H/W is valid or not 158 u8 boMacPsValid; //Power save mode obtained from H/W is valid or not
153 159
154 //// Rate 160 //// Rate
155 u8 TxRateMode; // Initial, input from Registry, may be updated by GUI 161 u8 TxRateMode; // Initial, input from Registry, may be updated by GUI
156 //Tx Rate Mode: auto(DTO on), max, 1M, 2M, .. 162 //Tx Rate Mode: auto(DTO on), max, 1M, 2M, ..
157 u8 CurrentTxRate; // The current Tx rate 163 u8 CurrentTxRate; // The current Tx rate
158 u8 CurrentTxRateForMng; // The current Tx rate for management frames 164 u8 CurrentTxRateForMng; // The current Tx rate for management frames
159 // It will be decided before connection succeeds. 165 // It will be decided before connection succeeds.
160 u8 CurrentTxFallbackRate; 166 u8 CurrentTxFallbackRate;
161 167
162 //for Rate handler 168 //for Rate handler
163 u8 BRateSet[32]; //basic rate set 169 u8 BRateSet[32]; //basic rate set
164 u8 SRateSet[32]; //support rate set 170 u8 SRateSet[32]; //support rate set
165 171
166 u8 NumOfBRate; 172 u8 NumOfBRate;
167 u8 NumOfSRate; 173 u8 NumOfSRate;
168 u8 NumOfDsssRateInSRate; //number of DSSS rates in supported rate set 174 u8 NumOfDsssRateInSRate; //number of DSSS rates in supported rate set
169 u8 reserved1; 175 u8 reserved1;
170 176
171 u32 dwBasicRateBitmap; //bit map of basic rates 177 u32 dwBasicRateBitmap; //bit map of basic rates
172 u32 dwSupportRateBitmap; //bit map of all support rates including 178 u32 dwSupportRateBitmap; //bit map of all support rates including
173 //basic and operational rates 179 //basic and operational rates
174 180
175 ////For SME/MLME handler 181 ////For SME/MLME handler
176 u16 wOldSTAindex; // valid when boHandover=TRUE, store old connected STA index 182 u16 wOldSTAindex; // valid when boHandover=TRUE, store old connected STA index
177 u16 wConnectedSTAindex; // Index of peerly connected AP or IBSS in 183 u16 wConnectedSTAindex; // Index of peerly connected AP or IBSS in
178 // the descriptionset. 184 // the descriptionset.
179 u16 Association_ID; // The Association ID in the (Re)Association 185 u16 Association_ID; // The Association ID in the (Re)Association
180 // Response frame. 186 // Response frame.
181 u16 ListenInterval; // The listen interval when SME invoking MLME_ 187 u16 ListenInterval; // The listen interval when SME invoking MLME_
182 // (Re)Associate_Request(). 188 // (Re)Associate_Request().
183 189
184 RadioOff RadioOffStatus; 190 RadioOff RadioOffStatus;
185 u8 Reserved0[2]; 191 u8 Reserved0[2];
186 192
187 u8 boMsRadioOff; // Ndis demands to be true when set Disassoc. OID and be false when set SSID OID. 193 u8 boMsRadioOff; // Ndis demands to be true when set Disassoc. OID and be false when set SSID OID.
188 u8 boAntennaDiversity; //TRUE/ON or FALSE/OFF 194 u8 boAntennaDiversity; //TRUE/ON or FALSE/OFF
189 u8 bAntennaNo; //which antenna 195 u8 bAntennaNo; //which antenna
190 u8 bConnectFlag; //the connect status flag for roaming task 196 u8 bConnectFlag; //the connect status flag for roaming task
191 197
192 u8 RoamStatus; 198 u8 RoamStatus;
193 u8 reserved7[3]; 199 u8 reserved7[3];
194 200
195 ChanInfo CurrentChan; //Current channel no. and channel band. It may be changed by scanning. 201 ChanInfo CurrentChan; //Current channel no. and channel band. It may be changed by scanning.
196 u8 boHandover; // Roaming, Hnadover to other AP. 202 u8 boHandover; // Roaming, Hnadover to other AP.
197 u8 boCCAbusy; 203 u8 boCCAbusy;
198 204
199 u16 CWMax; // It may not be the real value that H/W used 205 u16 CWMax; // It may not be the real value that H/W used
200 u8 CWMin; // 255: set according to 802.11 spec. 206 u8 CWMin; // 255: set according to 802.11 spec.
201 u8 reserved2; 207 u8 reserved2;
202 208
203 //11G: 209 //11G:
204 u8 bMacOperationMode; // operation in 802.11b or 802.11g 210 u8 bMacOperationMode; // operation in 802.11b or 802.11g
205 u8 bSlotTimeMode; //AUTO, s32 211 u8 bSlotTimeMode; //AUTO, s32
206 u8 bPreambleMode; //AUTO, s32 212 u8 bPreambleMode; //AUTO, s32
207 u8 boNonERPpresent; 213 u8 boNonERPpresent;
208 214
209 u8 boProtectMechanism; // H/W will take the necessary action based on this variable 215 u8 boProtectMechanism; // H/W will take the necessary action based on this variable
210 u8 boShortPreamble; // H/W will take the necessary action based on this variable 216 u8 boShortPreamble; // H/W will take the necessary action based on this variable
211 u8 boShortSlotTime; // H/W will take the necessary action based on this variable 217 u8 boShortSlotTime; // H/W will take the necessary action based on this variable
212 u8 reserved_3; 218 u8 reserved_3;
213 219
214 u32 RSN_IE_Bitmap; //added by WS 220 u32 RSN_IE_Bitmap; //added by WS
215 u32 RSN_OUI_Type; //added by WS 221 u32 RSN_OUI_Type; //added by WS
216 222
217 //For the BSSID 223 //For the BSSID
218 u8 HwBssid[MAC_ADDR_LENGTH + 2]; 224 u8 HwBssid[MAC_ADDR_LENGTH + 2];
219 u32 HwBssidValid; 225 u32 HwBssidValid;
220 226
221 //For scan list 227 //For scan list
222 u8 BssListCount; //Total count of valid descriptor indexes 228 u8 BssListCount; //Total count of valid descriptor indexes
223 u8 boReceiveUncorrectInfo; //important settings in beacon/probe resp. have been changed 229 u8 boReceiveUncorrectInfo; //important settings in beacon/probe resp. have been changed
224 u8 NoOfJoinerInIbss; 230 u8 NoOfJoinerInIbss;
225 u8 reserved_4; 231 u8 reserved_4;
226 232
227 u8 BssListIndex[ (MAX_BSS_DESCRIPT_ELEMENT+3) & ~0x03 ]; //Store the valid descriptor indexes obtained from scannings 233 u8 BssListIndex[ (MAX_BSS_DESCRIPT_ELEMENT+3) & ~0x03 ]; //Store the valid descriptor indexes obtained from scannings
228 u8 JoinerInIbss[ (MAX_BSS_DESCRIPT_ELEMENT+3) & ~0x03 ]; //save the BssDescriptor index in this 234 u8 JoinerInIbss[ (MAX_BSS_DESCRIPT_ELEMENT+3) & ~0x03 ]; //save the BssDescriptor index in this
229 //IBSS. The index 0 is local descriptor 235 //IBSS. The index 0 is local descriptor
230 //(psLOCAL->wConnectedSTAindex). 236 //(psLOCAL->wConnectedSTAindex).
231 //If CONNECTED : NoOfJoinerInIbss >=2 237 //If CONNECTED : NoOfJoinerInIbss >=2
232 // else : NoOfJoinerInIbss <=1 238 // else : NoOfJoinerInIbss <=1
233 239
234 //// General Statistics, count at Rx_handler or Tx_callback interrupt handler 240 //// General Statistics, count at Rx_handler or Tx_callback interrupt handler
235 u64 GS_XMIT_OK; // Good Frames Transmitted 241 u64 GS_XMIT_OK; // Good Frames Transmitted
236 u64 GS_RCV_OK; // Good Frames Received 242 u64 GS_RCV_OK; // Good Frames Received
237 u32 GS_RCV_ERROR; // Frames received with crc error 243 u32 GS_RCV_ERROR; // Frames received with crc error
238 u32 GS_XMIT_ERROR; // Bad Frames Transmitted 244 u32 GS_XMIT_ERROR; // Bad Frames Transmitted
239 u32 GS_RCV_NO_BUFFER; // Receive Buffer underrun 245 u32 GS_RCV_NO_BUFFER; // Receive Buffer underrun
240 u32 GS_XMIT_ONE_COLLISION; // one collision 246 u32 GS_XMIT_ONE_COLLISION; // one collision
241 u32 GS_XMIT_MORE_COLLISIONS;// more collisions 247 u32 GS_XMIT_MORE_COLLISIONS;// more collisions
242 248
243 //================================================================ 249 //================================================================
244 // Statistics (no matter whether it had done successfully) -wkchen 250 // Statistics (no matter whether it had done successfully) -wkchen
245 //================================================================ 251 //================================================================
246 u32 _NumRxMSDU; 252 u32 _NumRxMSDU;
247 u32 _NumTxMSDU; 253 u32 _NumTxMSDU;
248 u32 _dot11WEPExcludedCount; 254 u32 _dot11WEPExcludedCount;
249 u32 _dot11WEPUndecryptableCount; 255 u32 _dot11WEPUndecryptableCount;
250 u32 _dot11FrameDuplicateCount; 256 u32 _dot11FrameDuplicateCount;
251 257
252 ChanInfo IbssChanSetting; // 2B. Start IBSS Channel setting by registry or WWU. 258 ChanInfo IbssChanSetting; // 2B. Start IBSS Channel setting by registry or WWU.
253 u8 reserved_5[2]; //It may not be used after considering RF type, 259 u8 reserved_5[2]; //It may not be used after considering RF type,
254 //region and modulation type. 260 //region and modulation type.
255 261
256 CHAN_LIST sSupportChanList; // 86B. It will be obtained according to RF type and region 262 CHAN_LIST sSupportChanList; // 86B. It will be obtained according to RF type and region
257 u8 reserved_6[2]; //two variables are for wep key error detection added by ws 02/02/04 263 u8 reserved_6[2]; //two variables are for wep key error detection added by ws 02/02/04
258 264
259 u32 bWepKeyError; 265 u32 bWepKeyError;
260 u32 bToSelfPacketReceived; 266 u32 bToSelfPacketReceived;
261 u32 WepKeyDetectTimerCount; 267 u32 WepKeyDetectTimerCount;
262 268
263 Event_Log EventLog; 269 Event_Log EventLog;
264 270
265 u16 SignalLostTh; 271 u16 SignalLostTh;
266 u16 SignalRoamTh; 272 u16 SignalRoamTh;
267 273
268 // 20061108 WPS IE Append 274 // 20061108 WPS IE Append
269 u8 IE_Append_data[MAX_IE_APPEND_SIZE]; 275 u8 IE_Append_data[MAX_IE_APPEND_SIZE];
270 u16 IE_Append_size; 276 u16 IE_Append_size;
271 u16 reserved_7; 277 u16 reserved_7;
272 278
273 } WB_LOCALDESCRIPT, *PWB_LOCALDESCRIPT; 279 } WB_LOCALDESCRIPT, *PWB_LOCALDESCRIPT;
280
281 #endif
274 282
drivers/staging/winbond/mac_structures.h
Diff comments   View file @ 80aba53
1 //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2 // MAC_Structures.h 2 // MAC_Structures.h
3 // 3 //
4 // This file contains the definitions and data structures used by SW-MAC. 4 // This file contains the definitions and data structures used by SW-MAC.
5 // 5 //
6 // Revision Histoy 6 // Revision Histoy
7 //================= 7 //=================
8 // 0.1 2002 UN00 8 // 0.1 2002 UN00
9 // 0.2 20021004 PD43 CCLiu6 9 // 0.2 20021004 PD43 CCLiu6
10 // 20021018 PD43 CCLiu6 10 // 20021018 PD43 CCLiu6
11 // Add enum_TxRate type 11 // Add enum_TxRate type
12 // Modify enum_STAState type 12 // Modify enum_STAState type
13 // 0.3 20021023 PE23 CYLiu update MAC session struct 13 // 0.3 20021023 PE23 CYLiu update MAC session struct
14 // 20021108 14 // 20021108
15 // 20021122 PD43 Austin 15 // 20021122 PD43 Austin
16 // Deleted some unused. 16 // Deleted some unused.
17 // 20021129 PD43 Austin 17 // 20021129 PD43 Austin
18 // 20030617 increase the 802.11g definition 18 // 20030617 increase the 802.11g definition
19 //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 19 //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
20 20
21 #ifndef _MAC_Structures_H_ 21 #ifndef _MAC_Structures_H_
22 #define _MAC_Structures_H_ 22 #define _MAC_Structures_H_
23 23
24 #include <linux/skbuff.h>
24 25
25 //========================================================= 26 //=========================================================
26 // Some miscellaneous definitions 27 // Some miscellaneous definitions
27 //----- 28 //-----
28 #define MAX_CHANNELS 30 29 #define MAX_CHANNELS 30
29 #define MAC_ADDR_LENGTH 6 30 #define MAC_ADDR_LENGTH 6
30 #define MAX_WEP_KEY_SIZE 16 // 128 bits 31 #define MAX_WEP_KEY_SIZE 16 // 128 bits
31 #define MAX_802_11_FRAGMENT_NUMBER 10 // By spec 32 #define MAX_802_11_FRAGMENT_NUMBER 10 // By spec
32 33
33 //======================================================== 34 //========================================================
34 // 802.11 Frame define 35 // 802.11 Frame define
35 //----- 36 //-----
36 #define MASK_PROTOCOL_VERSION_TYPE 0x0F 37 #define MASK_PROTOCOL_VERSION_TYPE 0x0F
37 #define MASK_FRAGMENT_NUMBER 0x000F 38 #define MASK_FRAGMENT_NUMBER 0x000F
38 #define SEQUENCE_NUMBER_SHIFT 4 39 #define SEQUENCE_NUMBER_SHIFT 4
39 #define DIFFER_11_TO_3 18 40 #define DIFFER_11_TO_3 18
40 #define DOT_11_MAC_HEADER_SIZE 24 41 #define DOT_11_MAC_HEADER_SIZE 24
41 #define DOT_11_SNAP_SIZE 6 42 #define DOT_11_SNAP_SIZE 6
42 #define DOT_11_DURATION_OFFSET 2 43 #define DOT_11_DURATION_OFFSET 2
43 #define DOT_11_SEQUENCE_OFFSET 22 //Sequence control offset 44 #define DOT_11_SEQUENCE_OFFSET 22 //Sequence control offset
44 #define DOT_11_TYPE_OFFSET 30 //The start offset of 802.11 Frame// 45 #define DOT_11_TYPE_OFFSET 30 //The start offset of 802.11 Frame//
45 #define DOT_11_DATA_OFFSET 24 46 #define DOT_11_DATA_OFFSET 24
46 #define DOT_11_DA_OFFSET 4 47 #define DOT_11_DA_OFFSET 4
47 #define DOT_3_TYPE_ARP 0x80F3 48 #define DOT_3_TYPE_ARP 0x80F3
48 #define DOT_3_TYPE_IPX 0x8137 49 #define DOT_3_TYPE_IPX 0x8137
49 #define DOT_3_TYPE_OFFSET 12 50 #define DOT_3_TYPE_OFFSET 12
50 51
51 52
52 #define ETHERNET_HEADER_SIZE 14 53 #define ETHERNET_HEADER_SIZE 14
53 #define MAX_ETHERNET_PACKET_SIZE 1514 54 #define MAX_ETHERNET_PACKET_SIZE 1514
54 55
55 56
56 //----- management : Type of Bits (2, 3) and Subtype of Bits (4, 5, 6, 7) 57 //----- management : Type of Bits (2, 3) and Subtype of Bits (4, 5, 6, 7)
57 #define MAC_SUBTYPE_MNGMNT_ASSOC_REQUEST 0x00 58 #define MAC_SUBTYPE_MNGMNT_ASSOC_REQUEST 0x00
58 #define MAC_SUBTYPE_MNGMNT_ASSOC_RESPONSE 0x10 59 #define MAC_SUBTYPE_MNGMNT_ASSOC_RESPONSE 0x10
59 #define MAC_SUBTYPE_MNGMNT_REASSOC_REQUEST 0x20 60 #define MAC_SUBTYPE_MNGMNT_REASSOC_REQUEST 0x20
60 #define MAC_SUBTYPE_MNGMNT_REASSOC_RESPONSE 0x30 61 #define MAC_SUBTYPE_MNGMNT_REASSOC_RESPONSE 0x30
61 #define MAC_SUBTYPE_MNGMNT_PROBE_REQUEST 0x40 62 #define MAC_SUBTYPE_MNGMNT_PROBE_REQUEST 0x40
62 #define MAC_SUBTYPE_MNGMNT_PROBE_RESPONSE 0x50 63 #define MAC_SUBTYPE_MNGMNT_PROBE_RESPONSE 0x50
63 #define MAC_SUBTYPE_MNGMNT_BEACON 0x80 64 #define MAC_SUBTYPE_MNGMNT_BEACON 0x80
64 #define MAC_SUBTYPE_MNGMNT_ATIM 0x90 65 #define MAC_SUBTYPE_MNGMNT_ATIM 0x90
65 #define MAC_SUBTYPE_MNGMNT_DISASSOCIATION 0xA0 66 #define MAC_SUBTYPE_MNGMNT_DISASSOCIATION 0xA0
66 #define MAC_SUBTYPE_MNGMNT_AUTHENTICATION 0xB0 67 #define MAC_SUBTYPE_MNGMNT_AUTHENTICATION 0xB0
67 #define MAC_SUBTYPE_MNGMNT_DEAUTHENTICATION 0xC0 68 #define MAC_SUBTYPE_MNGMNT_DEAUTHENTICATION 0xC0
68 69
69 //----- control : Type of Bits (2, 3) and Subtype of Bits (4, 5, 6, 7) 70 //----- control : Type of Bits (2, 3) and Subtype of Bits (4, 5, 6, 7)
70 #define MAC_SUBTYPE_CONTROL_PSPOLL 0xA4 71 #define MAC_SUBTYPE_CONTROL_PSPOLL 0xA4
71 #define MAC_SUBTYPE_CONTROL_RTS 0xB4 72 #define MAC_SUBTYPE_CONTROL_RTS 0xB4
72 #define MAC_SUBTYPE_CONTROL_CTS 0xC4 73 #define MAC_SUBTYPE_CONTROL_CTS 0xC4
73 #define MAC_SUBTYPE_CONTROL_ACK 0xD4 74 #define MAC_SUBTYPE_CONTROL_ACK 0xD4
74 #define MAC_SUBTYPE_CONTROL_CFEND 0xE4 75 #define MAC_SUBTYPE_CONTROL_CFEND 0xE4
75 #define MAC_SUBTYPE_CONTROL_CFEND_CFACK 0xF4 76 #define MAC_SUBTYPE_CONTROL_CFEND_CFACK 0xF4
76 77
77 //----- data : Type of Bits (2, 3) and Subtype of Bits (4, 5, 6, 7) 78 //----- data : Type of Bits (2, 3) and Subtype of Bits (4, 5, 6, 7)
78 #define MAC_SUBTYPE_DATA 0x08 79 #define MAC_SUBTYPE_DATA 0x08
79 #define MAC_SUBTYPE_DATA_CFACK 0x18 80 #define MAC_SUBTYPE_DATA_CFACK 0x18
80 #define MAC_SUBTYPE_DATA_CFPOLL 0x28 81 #define MAC_SUBTYPE_DATA_CFPOLL 0x28
81 #define MAC_SUBTYPE_DATA_CFACK_CFPOLL 0x38 82 #define MAC_SUBTYPE_DATA_CFACK_CFPOLL 0x38
82 #define MAC_SUBTYPE_DATA_NULL 0x48 83 #define MAC_SUBTYPE_DATA_NULL 0x48
83 #define MAC_SUBTYPE_DATA_CFACK_NULL 0x58 84 #define MAC_SUBTYPE_DATA_CFACK_NULL 0x58
84 #define MAC_SUBTYPE_DATA_CFPOLL_NULL 0x68 85 #define MAC_SUBTYPE_DATA_CFPOLL_NULL 0x68
85 #define MAC_SUBTYPE_DATA_CFACK_CFPOLL_NULL 0x78 86 #define MAC_SUBTYPE_DATA_CFACK_CFPOLL_NULL 0x78
86 87
87 //----- Frame Type of Bits (2, 3) 88 //----- Frame Type of Bits (2, 3)
88 #define MAC_TYPE_MANAGEMENT 0x00 89 #define MAC_TYPE_MANAGEMENT 0x00
89 #define MAC_TYPE_CONTROL 0x04 90 #define MAC_TYPE_CONTROL 0x04
90 #define MAC_TYPE_DATA 0x08 91 #define MAC_TYPE_DATA 0x08
91 92
92 //----- definitions for Management Frame Element ID (1 BYTE) 93 //----- definitions for Management Frame Element ID (1 BYTE)
93 #define ELEMENT_ID_SSID 0 94 #define ELEMENT_ID_SSID 0
94 #define ELEMENT_ID_SUPPORTED_RATES 1 95 #define ELEMENT_ID_SUPPORTED_RATES 1
95 #define ELEMENT_ID_FH_PARAMETER_SET 2 96 #define ELEMENT_ID_FH_PARAMETER_SET 2
96 #define ELEMENT_ID_DS_PARAMETER_SET 3 97 #define ELEMENT_ID_DS_PARAMETER_SET 3
97 #define ELEMENT_ID_CF_PARAMETER_SET 4 98 #define ELEMENT_ID_CF_PARAMETER_SET 4
98 #define ELEMENT_ID_TIM 5 99 #define ELEMENT_ID_TIM 5
99 #define ELEMENT_ID_IBSS_PARAMETER_SET 6 100 #define ELEMENT_ID_IBSS_PARAMETER_SET 6
100 // 7~15 reserverd 101 // 7~15 reserverd
101 #define ELEMENT_ID_CHALLENGE_TEXT 16 102 #define ELEMENT_ID_CHALLENGE_TEXT 16
102 // 17~31 reserved for challenge text extension 103 // 17~31 reserved for challenge text extension
103 // 32~255 reserved 104 // 32~255 reserved
104 //-- 11G -- 105 //-- 11G --
105 #define ELEMENT_ID_ERP_INFORMATION 42 106 #define ELEMENT_ID_ERP_INFORMATION 42
106 #define ELEMENT_ID_EXTENDED_SUPPORTED_RATES 50 107 #define ELEMENT_ID_EXTENDED_SUPPORTED_RATES 50
107 108
108 //-- WPA -- 109 //-- WPA --
109 110
110 #define ELEMENT_ID_RSN_WPA 221 111 #define ELEMENT_ID_RSN_WPA 221
111 #ifdef _WPA2_ 112 #ifdef _WPA2_
112 #define ELEMENT_ID_RSN_WPA2 48 113 #define ELEMENT_ID_RSN_WPA2 48
113 #endif //endif WPA2 114 #endif //endif WPA2
114 115
115 #define WLAN_MAX_PAIRWISE_CIPHER_SUITE_COUNT ((u16) 6) 116 #define WLAN_MAX_PAIRWISE_CIPHER_SUITE_COUNT ((u16) 6)
116 #define WLAN_MAX_AUTH_KEY_MGT_SUITE_LIST_COUNT ((u16) 2) 117 #define WLAN_MAX_AUTH_KEY_MGT_SUITE_LIST_COUNT ((u16) 2)
117 118
118 #ifdef WB_LINUX
119 #define UNALIGNED
120 #endif
121
122 //======================================================== 119 //========================================================
123 typedef enum enum_PowerManagementMode 120 typedef enum enum_PowerManagementMode
124 { 121 {
125 ACTIVE = 0, 122 ACTIVE = 0,
126 POWER_SAVE 123 POWER_SAVE
127 } WB_PM_Mode, *PWB_PM_MODE; 124 } WB_PM_Mode, *PWB_PM_MODE;
128 125
129 //=================================================================== 126 //===================================================================
130 // Reason Code (Table 18): indicate the reason of DisAssoc, DeAuthen 127 // Reason Code (Table 18): indicate the reason of DisAssoc, DeAuthen
131 // length of ReasonCode is 2 Octs. 128 // length of ReasonCode is 2 Octs.
132 //=================================================================== 129 //===================================================================
133 #define REASON_REASERED 0 130 #define REASON_REASERED 0
134 #define REASON_UNSPECIDIED 1 131 #define REASON_UNSPECIDIED 1
135 #define REASON_PREAUTH_INVALID 2 132 #define REASON_PREAUTH_INVALID 2
136 #define DEAUTH_REASON_LEFT_BSS 3 133 #define DEAUTH_REASON_LEFT_BSS 3
137 #define DISASS_REASON_AP_INACTIVE 4 134 #define DISASS_REASON_AP_INACTIVE 4
138 #define DISASS_REASON_AP_BUSY 5 135 #define DISASS_REASON_AP_BUSY 5
139 #define REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6 136 #define REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6
140 #define REASON_CLASS3_FRAME_FROM_NONASSO_STA 7 137 #define REASON_CLASS3_FRAME_FROM_NONASSO_STA 7
141 #define DISASS_REASON_LEFT_BSS 8 138 #define DISASS_REASON_LEFT_BSS 8
142 #define REASON_NOT_AUTH_YET 9 139 #define REASON_NOT_AUTH_YET 9
143 //802.11i define 140 //802.11i define
144 #define REASON_INVALID_IE 13 141 #define REASON_INVALID_IE 13
145 #define REASON_MIC_ERROR 14 142 #define REASON_MIC_ERROR 14
146 #define REASON_4WAY_HANDSHAKE_TIMEOUT 15 143 #define REASON_4WAY_HANDSHAKE_TIMEOUT 15
147 #define REASON_GROUPKEY_UPDATE_TIMEOUT 16 144 #define REASON_GROUPKEY_UPDATE_TIMEOUT 16
148 #define REASON_IE_DIFF_4WAY_ASSOC 17 145 #define REASON_IE_DIFF_4WAY_ASSOC 17
149 #define REASON_INVALID_MULTICAST_CIPHER 18 146 #define REASON_INVALID_MULTICAST_CIPHER 18
150 #define REASON_INVALID_UNICAST_CIPHER 19 147 #define REASON_INVALID_UNICAST_CIPHER 19
151 #define REASON_INVALID_AKMP 20 148 #define REASON_INVALID_AKMP 20
152 #define REASON_UNSUPPORTED_RSNIE_VERSION 21 149 #define REASON_UNSUPPORTED_RSNIE_VERSION 21
153 #define REASON_INVALID_RSNIE_CAPABILITY 22 150 #define REASON_INVALID_RSNIE_CAPABILITY 22
154 #define REASON_802_1X_AUTH_FAIL 23 151 #define REASON_802_1X_AUTH_FAIL 23
155 #define REASON_CIPHER_REJECT_PER_SEC_POLICY 14 152 #define REASON_CIPHER_REJECT_PER_SEC_POLICY 14
156 153
157 /* 154 /*
158 //=========================================================== 155 //===========================================================
159 // enum_MMPDUResultCode -- 156 // enum_MMPDUResultCode --
160 // Status code (2 Octs) in the MMPDU's frame body. Table.19 157 // Status code (2 Octs) in the MMPDU's frame body. Table.19
161 // 158 //
162 //=========================================================== 159 //===========================================================
163 enum enum_MMPDUResultCode 160 enum enum_MMPDUResultCode
164 { 161 {
165 // SUCCESS = 0, // Redefined 162 // SUCCESS = 0, // Redefined
166 UNSPECIFIED_FAILURE = 1, 163 UNSPECIFIED_FAILURE = 1,
167 164
168 // 2 - 9 Reserved 165 // 2 - 9 Reserved
169 166
170 NOT_SUPPROT_CAPABILITIES = 10, 167 NOT_SUPPROT_CAPABILITIES = 10,
171 168
172 //REASSOCIATION_DENIED 169 //REASSOCIATION_DENIED
173 // 170 //
174 REASSOC_DENIED_UNABLE_CFM_ASSOC_EXIST = 11, 171 REASSOC_DENIED_UNABLE_CFM_ASSOC_EXIST = 11,
175 172
176 //ASSOCIATION_DENIED_NOT_IN_STANDARD 173 //ASSOCIATION_DENIED_NOT_IN_STANDARD
177 // 174 //
178 ASSOC_DENIED_REASON_NOT_IN_STANDARD = 12, 175 ASSOC_DENIED_REASON_NOT_IN_STANDARD = 12,
179 PEER_NOT_SUPPORT_AUTH_ALGORITHM = 13, 176 PEER_NOT_SUPPORT_AUTH_ALGORITHM = 13,
180 AUTH_SEQNUM_OUT_OF_EXPECT = 14, 177 AUTH_SEQNUM_OUT_OF_EXPECT = 14,
181 AUTH_REJECT_REASON_CHALLENGE_FAIL = 15, 178 AUTH_REJECT_REASON_CHALLENGE_FAIL = 15,
182 AUTH_REJECT_REASON_WAIT_TIMEOUT = 16, 179 AUTH_REJECT_REASON_WAIT_TIMEOUT = 16,
183 ASSOC_DENIED_REASON_AP_BUSY = 17, 180 ASSOC_DENIED_REASON_AP_BUSY = 17,
184 ASSOC_DENIED_REASON_NOT_SUPPORT_BASIC_RATE = 18 181 ASSOC_DENIED_REASON_NOT_SUPPORT_BASIC_RATE = 18
185 } WB_MMPDURESULTCODE, *PWB_MMPDURESULTCODE; 182 } WB_MMPDURESULTCODE, *PWB_MMPDURESULTCODE;
186 */ 183 */
187 184
188 //=========================================================== 185 //===========================================================
189 // enum_TxRate -- 186 // enum_TxRate --
190 // Define the transmission constants based on W89C32 MAC 187 // Define the transmission constants based on W89C32 MAC
191 // target specification. 188 // target specification.
192 //=========================================================== 189 //===========================================================
193 typedef enum enum_TxRate 190 typedef enum enum_TxRate
194 { 191 {
195 TXRATE_1M = 0, 192 TXRATE_1M = 0,
196 TXRATE_2MLONG = 2, 193 TXRATE_2MLONG = 2,
197 TXRATE_2MSHORT = 3, 194 TXRATE_2MSHORT = 3,
198 TXRATE_55MLONG = 4, 195 TXRATE_55MLONG = 4,
199 TXRATE_55MSHORT = 5, 196 TXRATE_55MSHORT = 5,
200 TXRATE_11MLONG = 6, 197 TXRATE_11MLONG = 6,
201 TXRATE_11MSHORT = 7, 198 TXRATE_11MSHORT = 7,
202 TXRATE_AUTO = 255 // PD43 20021108 199 TXRATE_AUTO = 255 // PD43 20021108
203 } WB_TXRATE, *PWB_TXRATE; 200 } WB_TXRATE, *PWB_TXRATE;
204 201
205 202
206 #define RATE_BITMAP_1M 1 203 #define RATE_BITMAP_1M 1
207 #define RATE_BITMAP_2M 2 204 #define RATE_BITMAP_2M 2
208 #define RATE_BITMAP_5dot5M 5 205 #define RATE_BITMAP_5dot5M 5
209 #define RATE_BITMAP_6M 6 206 #define RATE_BITMAP_6M 6
210 #define RATE_BITMAP_9M 9 207 #define RATE_BITMAP_9M 9
211 #define RATE_BITMAP_11M 11 208 #define RATE_BITMAP_11M 11
212 #define RATE_BITMAP_12M 12 209 #define RATE_BITMAP_12M 12
213 #define RATE_BITMAP_18M 18 210 #define RATE_BITMAP_18M 18
214 #define RATE_BITMAP_22M 22 211 #define RATE_BITMAP_22M 22
215 #define RATE_BITMAP_24M 24 212 #define RATE_BITMAP_24M 24
216 #define RATE_BITMAP_33M 17 213 #define RATE_BITMAP_33M 17
217 #define RATE_BITMAP_36M 19 214 #define RATE_BITMAP_36M 19
218 #define RATE_BITMAP_48M 25 215 #define RATE_BITMAP_48M 25
219 #define RATE_BITMAP_54M 28 216 #define RATE_BITMAP_54M 28
220 217
221 #define RATE_AUTO 0 218 #define RATE_AUTO 0
222 #define RATE_1M 2 219 #define RATE_1M 2
223 #define RATE_2M 4 220 #define RATE_2M 4
224 #define RATE_5dot5M 11 221 #define RATE_5dot5M 11
225 #define RATE_6M 12 222 #define RATE_6M 12
226 #define RATE_9M 18 223 #define RATE_9M 18
227 #define RATE_11M 22 224 #define RATE_11M 22
228 #define RATE_12M 24 225 #define RATE_12M 24
229 #define RATE_18M 36 226 #define RATE_18M 36
230 #define RATE_22M 44 227 #define RATE_22M 44
231 #define RATE_24M 48 228 #define RATE_24M 48
232 #define RATE_33M 66 229 #define RATE_33M 66
233 #define RATE_36M 72 230 #define RATE_36M 72
234 #define RATE_48M 96 231 #define RATE_48M 96
235 #define RATE_54M 108 232 #define RATE_54M 108
236 #define RATE_MAX 255 233 #define RATE_MAX 255
237 234
238 //CAPABILITY 235 //CAPABILITY
239 #define CAPABILITY_ESS_BIT 0x0001 236 #define CAPABILITY_ESS_BIT 0x0001
240 #define CAPABILITY_IBSS_BIT 0x0002 237 #define CAPABILITY_IBSS_BIT 0x0002
241 #define CAPABILITY_CF_POLL_BIT 0x0004 238 #define CAPABILITY_CF_POLL_BIT 0x0004
242 #define CAPABILITY_CF_POLL_REQ_BIT 0x0008 239 #define CAPABILITY_CF_POLL_REQ_BIT 0x0008
243 #define CAPABILITY_PRIVACY_BIT 0x0010 240 #define CAPABILITY_PRIVACY_BIT 0x0010
244 #define CAPABILITY_SHORT_PREAMBLE_BIT 0x0020 241 #define CAPABILITY_SHORT_PREAMBLE_BIT 0x0020
245 #define CAPABILITY_PBCC_BIT 0x0040 242 #define CAPABILITY_PBCC_BIT 0x0040
246 #define CAPABILITY_CHAN_AGILITY_BIT 0x0080 243 #define CAPABILITY_CHAN_AGILITY_BIT 0x0080
247 #define CAPABILITY_SHORT_SLOT_TIME_BIT 0x0400 244 #define CAPABILITY_SHORT_SLOT_TIME_BIT 0x0400
248 #define CAPABILITY_DSSS_OFDM_BIT 0x2000 245 #define CAPABILITY_DSSS_OFDM_BIT 0x2000
249 246
250 247
251 struct Capability_Information_Element 248 struct Capability_Information_Element
252 { 249 {
253 union 250 union
254 { 251 {
255 u16 __attribute__ ((packed)) wValue; 252 u16 __attribute__ ((packed)) wValue;
256 #ifdef _BIG_ENDIAN_ //20060926 add by anson's endian 253 #ifdef _BIG_ENDIAN_ //20060926 add by anson's endian
257 struct _Capability 254 struct _Capability
258 { 255 {
259 //-- 11G -- 256 //-- 11G --
260 u8 Reserved3 : 2; 257 u8 Reserved3 : 2;
261 u8 DSSS_OFDM : 1; 258 u8 DSSS_OFDM : 1;
262 u8 Reserved2 : 2; 259 u8 Reserved2 : 2;
263 u8 Short_Slot_Time : 1; 260 u8 Short_Slot_Time : 1;
264 u8 Reserved1 : 2; 261 u8 Reserved1 : 2;
265 u8 Channel_Agility : 1; 262 u8 Channel_Agility : 1;
266 u8 PBCC : 1; 263 u8 PBCC : 1;
267 u8 ShortPreamble : 1; 264 u8 ShortPreamble : 1;
268 u8 CF_Privacy : 1; 265 u8 CF_Privacy : 1;
269 u8 CF_Poll_Request : 1; 266 u8 CF_Poll_Request : 1;
270 u8 CF_Pollable : 1; 267 u8 CF_Pollable : 1;
271 u8 IBSS : 1; 268 u8 IBSS : 1;
272 u8 ESS : 1; 269 u8 ESS : 1;
273 } __attribute__ ((packed)) Capability; 270 } __attribute__ ((packed)) Capability;
274 #else 271 #else
275 struct _Capability 272 struct _Capability
276 { 273 {
277 u8 ESS : 1; 274 u8 ESS : 1;
278 u8 IBSS : 1; 275 u8 IBSS : 1;
279 u8 CF_Pollable : 1; 276 u8 CF_Pollable : 1;
280 u8 CF_Poll_Request : 1; 277 u8 CF_Poll_Request : 1;
281 u8 CF_Privacy : 1; 278 u8 CF_Privacy : 1;
282 u8 ShortPreamble : 1; 279 u8 ShortPreamble : 1;
283 u8 PBCC : 1; 280 u8 PBCC : 1;
284 u8 Channel_Agility : 1; 281 u8 Channel_Agility : 1;
285 u8 Reserved1 : 2; 282 u8 Reserved1 : 2;
286 //-- 11G -- 283 //-- 11G --
287 u8 Short_Slot_Time : 1; 284 u8 Short_Slot_Time : 1;
288 u8 Reserved2 : 2; 285 u8 Reserved2 : 2;
289 u8 DSSS_OFDM : 1; 286 u8 DSSS_OFDM : 1;
290 u8 Reserved3 : 2; 287 u8 Reserved3 : 2;
291 } __attribute__ ((packed)) Capability; 288 } __attribute__ ((packed)) Capability;
292 #endif 289 #endif
293 }__attribute__ ((packed)) ; 290 }__attribute__ ((packed)) ;
294 }__attribute__ ((packed)); 291 }__attribute__ ((packed));
295 292
296 struct FH_Parameter_Set_Element 293 struct FH_Parameter_Set_Element
297 { 294 {
298 u8 Element_ID; 295 u8 Element_ID;
299 u8 Length; 296 u8 Length;
300 u8 Dwell_Time[2]; 297 u8 Dwell_Time[2];
301 u8 Hop_Set; 298 u8 Hop_Set;
302 u8 Hop_Pattern; 299 u8 Hop_Pattern;
303 u8 Hop_Index; 300 u8 Hop_Index;
304 }; 301 };
305 302
306 struct DS_Parameter_Set_Element 303 struct DS_Parameter_Set_Element
307 { 304 {
308 u8 Element_ID; 305 u8 Element_ID;
309 u8 Length; 306 u8 Length;
310 u8 Current_Channel; 307 u8 Current_Channel;
311 }; 308 };
312 309
313 struct Supported_Rates_Element 310 struct Supported_Rates_Element
314 { 311 {
315 u8 Element_ID; 312 u8 Element_ID;
316 u8 Length; 313 u8 Length;
317 u8 SupportedRates[8]; 314 u8 SupportedRates[8];
318 }__attribute__ ((packed)); 315 }__attribute__ ((packed));
319 316
320 struct SSID_Element 317 struct SSID_Element
321 { 318 {
322 u8 Element_ID; 319 u8 Element_ID;
323 u8 Length; 320 u8 Length;
324 u8 SSID[32]; 321 u8 SSID[32];
325 }__attribute__ ((packed)) ; 322 }__attribute__ ((packed)) ;
326 323
327 struct CF_Parameter_Set_Element 324 struct CF_Parameter_Set_Element
328 { 325 {
329 u8 Element_ID; 326 u8 Element_ID;
330 u8 Length; 327 u8 Length;
331 u8 CFP_Count; 328 u8 CFP_Count;
332 u8 CFP_Period; 329 u8 CFP_Period;
333 u8 CFP_MaxDuration[2]; // in Time Units 330 u8 CFP_MaxDuration[2]; // in Time Units
334 u8 CFP_DurRemaining[2]; // in time units 331 u8 CFP_DurRemaining[2]; // in time units
335 }; 332 };
336 333
337 struct TIM_Element 334 struct TIM_Element
338 { 335 {
339 u8 Element_ID; 336 u8 Element_ID;
340 u8 Length; 337 u8 Length;
341 u8 DTIM_Count; 338 u8 DTIM_Count;
342 u8 DTIM_Period; 339 u8 DTIM_Period;
343 u8 Bitmap_Control; 340 u8 Bitmap_Control;
344 u8 Partial_Virtual_Bitmap[251]; 341 u8 Partial_Virtual_Bitmap[251];
345 }; 342 };
346 343
347 struct IBSS_Parameter_Set_Element 344 struct IBSS_Parameter_Set_Element
348 { 345 {
349 u8 Element_ID; 346 u8 Element_ID;
350 u8 Length; 347 u8 Length;
351 u8 ATIM_Window[2]; 348 u8 ATIM_Window[2];
352 }; 349 };
353 350
354 struct Challenge_Text_Element 351 struct Challenge_Text_Element
355 { 352 {
356 u8 Element_ID; 353 u8 Element_ID;
357 u8 Length; 354 u8 Length;
358 u8 Challenge_Text[253]; 355 u8 Challenge_Text[253];
359 }; 356 };
360 357
361 struct PHY_Parameter_Set_Element 358 struct PHY_Parameter_Set_Element
362 { 359 {
363 // int aSlotTime; 360 // int aSlotTime;
364 // int aSifsTime; 361 // int aSifsTime;
365 s32 aCCATime; 362 s32 aCCATime;
366 s32 aRxTxTurnaroundTime; 363 s32 aRxTxTurnaroundTime;
367 s32 aTxPLCPDelay; 364 s32 aTxPLCPDelay;
368 s32 RxPLCPDelay; 365 s32 RxPLCPDelay;
369 s32 aRxTxSwitchTime; 366 s32 aRxTxSwitchTime;
370 s32 aTxRampOntime; 367 s32 aTxRampOntime;
371 s32 aTxRampOffTime; 368 s32 aTxRampOffTime;
372 s32 aTxRFDelay; 369 s32 aTxRFDelay;
373 s32 aRxRFDelay; 370 s32 aRxRFDelay;
374 s32 aAirPropagationTime; 371 s32 aAirPropagationTime;
375 s32 aMACProcessingDelay; 372 s32 aMACProcessingDelay;
376 s32 aPreambleLength; 373 s32 aPreambleLength;
377 s32 aPLCPHeaderLength; 374 s32 aPLCPHeaderLength;
378 s32 aMPDUDurationFactor; 375 s32 aMPDUDurationFactor;
379 s32 aMPDUMaxLength; 376 s32 aMPDUMaxLength;
380 // int aCWmin; 377 // int aCWmin;
381 // int aCWmax; 378 // int aCWmax;
382 }; 379 };
383 380
384 //-- 11G -- 381 //-- 11G --
385 struct ERP_Information_Element 382 struct ERP_Information_Element
386 { 383 {
387 u8 Element_ID; 384 u8 Element_ID;
388 u8 Length; 385 u8 Length;
389 #ifdef _BIG_ENDIAN_ //20060926 add by anson's endian 386 #ifdef _BIG_ENDIAN_ //20060926 add by anson's endian
390 u8 Reserved:5; //20060926 add by anson 387 u8 Reserved:5; //20060926 add by anson
391 u8 Barker_Preamble_Mode:1; 388 u8 Barker_Preamble_Mode:1;
392 u8 Use_Protection:1; 389 u8 Use_Protection:1;
393 u8 NonERP_Present:1; 390 u8 NonERP_Present:1;
394 #else 391 #else
395 u8 NonERP_Present:1; 392 u8 NonERP_Present:1;
396 u8 Use_Protection:1; 393 u8 Use_Protection:1;
397 u8 Barker_Preamble_Mode:1; 394 u8 Barker_Preamble_Mode:1;
398 u8 Reserved:5; 395 u8 Reserved:5;
399 #endif 396 #endif
400 }; 397 };
401 398
402 struct Extended_Supported_Rates_Element 399 struct Extended_Supported_Rates_Element
403 { 400 {
404 u8 Element_ID; 401 u8 Element_ID;
405 u8 Length; 402 u8 Length;
406 u8 ExtendedSupportedRates[255]; 403 u8 ExtendedSupportedRates[255];
407 }__attribute__ ((packed)); 404 }__attribute__ ((packed));
408 405
409 //WPA(802.11i draft 3.0) 406 //WPA(802.11i draft 3.0)
410 #define VERSION_WPA 1 407 #define VERSION_WPA 1
411 #ifdef _WPA2_ 408 #ifdef _WPA2_
412 #define VERSION_WPA2 1 409 #define VERSION_WPA2 1
413 #endif //end def _WPA2_ 410 #endif //end def _WPA2_
414 #define OUI_WPA 0x00F25000 //WPA2.0 OUI=00:50:F2, the MSB is reserved for suite type 411 #define OUI_WPA 0x00F25000 //WPA2.0 OUI=00:50:F2, the MSB is reserved for suite type
415 #ifdef _WPA2_ 412 #ifdef _WPA2_
416 #define OUI_WPA2 0x00AC0F00 // for wpa2 change to 0x00ACOF04 by Ws 26/04/04 413 #define OUI_WPA2 0x00AC0F00 // for wpa2 change to 0x00ACOF04 by Ws 26/04/04
417 #endif //end def _WPA2_ 414 #endif //end def _WPA2_
418 415
419 #define OUI_WPA_ADDITIONAL 0x01 416 #define OUI_WPA_ADDITIONAL 0x01
420 #define WLAN_MIN_RSN_WPA_LENGTH 6 //added by ws 09/10/04 417 #define WLAN_MIN_RSN_WPA_LENGTH 6 //added by ws 09/10/04
421 #ifdef _WPA2_ 418 #ifdef _WPA2_
422 #define WLAN_MIN_RSN_WPA2_LENGTH 2 // Fix to 2 09/14/05 419 #define WLAN_MIN_RSN_WPA2_LENGTH 2 // Fix to 2 09/14/05
423 #endif //end def _WPA2_ 420 #endif //end def _WPA2_
424 421
425 #define oui_wpa (u32)(OUI_WPA|OUI_WPA_ADDITIONAL) 422 #define oui_wpa (u32)(OUI_WPA|OUI_WPA_ADDITIONAL)
426 423
427 #define WPA_OUI_BIG ((u32) 0x01F25000)//added by ws 09/23/04 424 #define WPA_OUI_BIG ((u32) 0x01F25000)//added by ws 09/23/04
428 #define WPA_OUI_LITTLE ((u32) 0x01F25001)//added by ws 09/23/04 425 #define WPA_OUI_LITTLE ((u32) 0x01F25001)//added by ws 09/23/04
429 426
430 #define WPA_WPS_OUI cpu_to_le32(0x04F25000) // 20061108 For WPS. It's little endian. Big endian is 0x0050F204 427 #define WPA_WPS_OUI cpu_to_le32(0x04F25000) // 20061108 For WPS. It's little endian. Big endian is 0x0050F204
431 428
432 //-----WPA2----- 429 //-----WPA2-----
433 #ifdef _WPA2_ 430 #ifdef _WPA2_
434 #define WPA2_OUI_BIG ((u32)0x01AC0F00) 431 #define WPA2_OUI_BIG ((u32)0x01AC0F00)
435 #define WPA2_OUI_LITTLE ((u32)0x01AC0F01) 432 #define WPA2_OUI_LITTLE ((u32)0x01AC0F01)
436 #endif //end def _WPA2_ 433 #endif //end def _WPA2_
437 434
438 //Authentication suite 435 //Authentication suite
439 #define OUI_AUTH_WPA_NONE 0x00 //for WPA_NONE 436 #define OUI_AUTH_WPA_NONE 0x00 //for WPA_NONE
440 #define OUI_AUTH_8021X 0x01 437 #define OUI_AUTH_8021X 0x01
441 #define OUI_AUTH_PSK 0x02 438 #define OUI_AUTH_PSK 0x02
442 //Cipher suite 439 //Cipher suite
443 #define OUI_CIPHER_GROUP_KEY 0x00 //added by ws 05/21/04 440 #define OUI_CIPHER_GROUP_KEY 0x00 //added by ws 05/21/04
444 #define OUI_CIPHER_WEP_40 0x01 441 #define OUI_CIPHER_WEP_40 0x01
445 #define OUI_CIPHER_TKIP 0x02 442 #define OUI_CIPHER_TKIP 0x02
446 #define OUI_CIPHER_CCMP 0x04 443 #define OUI_CIPHER_CCMP 0x04
447 #define OUI_CIPHER_WEP_104 0x05 444 #define OUI_CIPHER_WEP_104 0x05
448 445
449 typedef struct _SUITE_SELECTOR_ 446 typedef struct _SUITE_SELECTOR_
450 { 447 {
451 union 448 union
452 { 449 {
453 u8 Value[4]; 450 u8 Value[4];
454 struct _SUIT_ 451 struct _SUIT_
455 { 452 {
456 u8 OUI[3]; 453 u8 OUI[3];
457 u8 Type; 454 u8 Type;
458 }SuitSelector; 455 }SuitSelector;
459 }; 456 };
460 }SUITE_SELECTOR; 457 }SUITE_SELECTOR;
461 458
462 //-- WPA -- 459 //-- WPA --
463 struct RSN_Information_Element 460 struct RSN_Information_Element
464 { 461 {
465 u8 Element_ID; 462 u8 Element_ID;
466 u8 Length; 463 u8 Length;
467 UNALIGNED SUITE_SELECTOR OuiWPAAdditional;//WPA version 2.0 additional field, and should be 00:50:F2:01 464 SUITE_SELECTOR OuiWPAAdditional;//WPA version 2.0 additional field, and should be 00:50:F2:01
468 u16 Version; 465 u16 Version;
469 SUITE_SELECTOR GroupKeySuite; 466 SUITE_SELECTOR GroupKeySuite;
470 u16 PairwiseKeySuiteCount; 467 u16 PairwiseKeySuiteCount;
471 SUITE_SELECTOR PairwiseKeySuite[1]; 468 SUITE_SELECTOR PairwiseKeySuite[1];
472 }__attribute__ ((packed)); 469 }__attribute__ ((packed));
473 struct RSN_Auth_Sub_Information_Element 470 struct RSN_Auth_Sub_Information_Element
474 { 471 {
475 u16 AuthKeyMngtSuiteCount; 472 u16 AuthKeyMngtSuiteCount;
476 SUITE_SELECTOR AuthKeyMngtSuite[1]; 473 SUITE_SELECTOR AuthKeyMngtSuite[1];
477 }__attribute__ ((packed)); 474 }__attribute__ ((packed));
478 475
479 //-- WPA2 -- 476 //-- WPA2 --
480 struct RSN_Capability_Element 477 struct RSN_Capability_Element
481 { 478 {
482 union 479 union
483 { 480 {
484 u16 __attribute__ ((packed)) wValue; 481 u16 __attribute__ ((packed)) wValue;
485 #ifdef _BIG_ENDIAN_ //20060927 add by anson's endian 482 #ifdef _BIG_ENDIAN_ //20060927 add by anson's endian
486 struct _RSN_Capability 483 struct _RSN_Capability
487 { 484 {
488 u16 __attribute__ ((packed)) Reserved2 : 8; // 20051201 485 u16 __attribute__ ((packed)) Reserved2 : 8; // 20051201
489 u16 __attribute__ ((packed)) Reserved1 : 2; 486 u16 __attribute__ ((packed)) Reserved1 : 2;
490 u16 __attribute__ ((packed)) GTK_Replay_Counter : 2; 487 u16 __attribute__ ((packed)) GTK_Replay_Counter : 2;
491 u16 __attribute__ ((packed)) PTK_Replay_Counter : 2; 488 u16 __attribute__ ((packed)) PTK_Replay_Counter : 2;
492 u16 __attribute__ ((packed)) No_Pairwise : 1; 489 u16 __attribute__ ((packed)) No_Pairwise : 1;
493 u16 __attribute__ ((packed)) Pre_Auth : 1; 490 u16 __attribute__ ((packed)) Pre_Auth : 1;
494 }__attribute__ ((packed)) RSN_Capability; 491 }__attribute__ ((packed)) RSN_Capability;
495 #else 492 #else
496 struct _RSN_Capability 493 struct _RSN_Capability
497 { 494 {
498 u16 __attribute__ ((packed)) Pre_Auth : 1; 495 u16 __attribute__ ((packed)) Pre_Auth : 1;
499 u16 __attribute__ ((packed)) No_Pairwise : 1; 496 u16 __attribute__ ((packed)) No_Pairwise : 1;
500 u16 __attribute__ ((packed)) PTK_Replay_Counter : 2; 497 u16 __attribute__ ((packed)) PTK_Replay_Counter : 2;
501 u16 __attribute__ ((packed)) GTK_Replay_Counter : 2; 498 u16 __attribute__ ((packed)) GTK_Replay_Counter : 2;
502 u16 __attribute__ ((packed)) Reserved1 : 2; 499 u16 __attribute__ ((packed)) Reserved1 : 2;
503 u16 __attribute__ ((packed)) Reserved2 : 8; // 20051201 500 u16 __attribute__ ((packed)) Reserved2 : 8; // 20051201
504 }__attribute__ ((packed)) RSN_Capability; 501 }__attribute__ ((packed)) RSN_Capability;
505 #endif 502 #endif
506 503
507 }__attribute__ ((packed)) ; 504 }__attribute__ ((packed)) ;
508 }__attribute__ ((packed)) ; 505 }__attribute__ ((packed)) ;
509 506
510 #ifdef _WPA2_ 507 #ifdef _WPA2_
511 typedef struct _PMKID 508 typedef struct _PMKID
512 { 509 {
513 u8 pValue[16]; 510 u8 pValue[16];
514 }PMKID; 511 }PMKID;
515 512
516 struct WPA2_RSN_Information_Element 513 struct WPA2_RSN_Information_Element
517 { 514 {
518 u8 Element_ID; 515 u8 Element_ID;
519 u8 Length; 516 u8 Length;
520 u16 Version; 517 u16 Version;
521 SUITE_SELECTOR GroupKeySuite; 518 SUITE_SELECTOR GroupKeySuite;
522 u16 PairwiseKeySuiteCount; 519 u16 PairwiseKeySuiteCount;
523 SUITE_SELECTOR PairwiseKeySuite[1]; 520 SUITE_SELECTOR PairwiseKeySuite[1];
524 521
525 }__attribute__ ((packed)); 522 }__attribute__ ((packed));
526 523
527 struct WPA2_RSN_Auth_Sub_Information_Element 524 struct WPA2_RSN_Auth_Sub_Information_Element
528 { 525 {
529 u16 AuthKeyMngtSuiteCount; 526 u16 AuthKeyMngtSuiteCount;
530 SUITE_SELECTOR AuthKeyMngtSuite[1]; 527 SUITE_SELECTOR AuthKeyMngtSuite[1];
531 }__attribute__ ((packed)); 528 }__attribute__ ((packed));
532 529
533 530
534 struct PMKID_Information_Element 531 struct PMKID_Information_Element
535 { 532 {
536 u16 PMKID_Count; 533 u16 PMKID_Count;
537 PMKID pmkid [16] ; 534 PMKID pmkid [16] ;
538 }__attribute__ ((packed)); 535 }__attribute__ ((packed));
539 536
540 #endif //enddef _WPA2_ 537 #endif //enddef _WPA2_
541 //============================================================ 538 //============================================================
542 // MAC Frame structure (different type) and subfield structure 539 // MAC Frame structure (different type) and subfield structure
543 //============================================================ 540 //============================================================
544 struct MAC_frame_control 541 struct MAC_frame_control
545 { 542 {
546 u8 mac_frame_info; // a combination of the [Protocol Version, Control Type, Control Subtype] 543 u8 mac_frame_info; // a combination of the [Protocol Version, Control Type, Control Subtype]
547 #ifdef _BIG_ENDIAN_ //20060927 add by anson's endian 544 #ifdef _BIG_ENDIAN_ //20060927 add by anson's endian
548 u8 order:1; 545 u8 order:1;
549 u8 WEP:1; 546 u8 WEP:1;
550 u8 more_data:1; 547 u8 more_data:1;
551 u8 pwr_mgt:1; 548 u8 pwr_mgt:1;
552 u8 retry:1; 549 u8 retry:1;
553 u8 more_frag:1; 550 u8 more_frag:1;
554 u8 from_ds:1; 551 u8 from_ds:1;
555 u8 to_ds:1; 552 u8 to_ds:1;
556 #else 553 #else
557 u8 to_ds:1; 554 u8 to_ds:1;
558 u8 from_ds:1; 555 u8 from_ds:1;
559 u8 more_frag:1; 556 u8 more_frag:1;
560 u8 retry:1; 557 u8 retry:1;
561 u8 pwr_mgt:1; 558 u8 pwr_mgt:1;
562 u8 more_data:1; 559 u8 more_data:1;
563 u8 WEP:1; 560 u8 WEP:1;
564 u8 order:1; 561 u8 order:1;
565 #endif 562 #endif
566 } __attribute__ ((packed)); 563 } __attribute__ ((packed));
567 564
568 struct Management_Frame { 565 struct Management_Frame {
569 struct MAC_frame_control frame_control; // 2B, ToDS,FromDS,MoreFrag,MoreData,Order=0 566 struct MAC_frame_control frame_control; // 2B, ToDS,FromDS,MoreFrag,MoreData,Order=0
570 u16 duration; 567 u16 duration;
571 u8 DA[MAC_ADDR_LENGTH]; // Addr1 568 u8 DA[MAC_ADDR_LENGTH]; // Addr1
572 u8 SA[MAC_ADDR_LENGTH]; // Addr2 569 u8 SA[MAC_ADDR_LENGTH]; // Addr2
573 u8 BSSID[MAC_ADDR_LENGTH]; // Addr3 570 u8 BSSID[MAC_ADDR_LENGTH]; // Addr3
574 u16 Sequence_Control; 571 u16 Sequence_Control;
575 // Management Frame Body <= 325 bytes 572 // Management Frame Body <= 325 bytes
576 // FCS 4 bytes 573 // FCS 4 bytes
577 }__attribute__ ((packed)); 574 }__attribute__ ((packed));
578 575
579 // SW-MAC don't Tx/Rx Control-Frame, HW-MAC do it. 576 // SW-MAC don't Tx/Rx Control-Frame, HW-MAC do it.
580 struct Control_Frame { 577 struct Control_Frame {
581 struct MAC_frame_control frame_control; // ToDS,FromDS,MoreFrag,Retry,MoreData,WEP,Order=0 578 struct MAC_frame_control frame_control; // ToDS,FromDS,MoreFrag,Retry,MoreData,WEP,Order=0
582 u16 duration; 579 u16 duration;
583 u8 RA[MAC_ADDR_LENGTH]; 580 u8 RA[MAC_ADDR_LENGTH];
584 u8 TA[MAC_ADDR_LENGTH]; 581 u8 TA[MAC_ADDR_LENGTH];
585 u16 FCS; 582 u16 FCS;
586 }__attribute__ ((packed)); 583 }__attribute__ ((packed));
587 584
588 struct Data_Frame { 585 struct Data_Frame {
589 struct MAC_frame_control frame_control; 586 struct MAC_frame_control frame_control;
590 u16 duration; 587 u16 duration;
591 u8 Addr1[MAC_ADDR_LENGTH]; 588 u8 Addr1[MAC_ADDR_LENGTH];
592 u8 Addr2[MAC_ADDR_LENGTH]; 589 u8 Addr2[MAC_ADDR_LENGTH];
593 u8 Addr3[MAC_ADDR_LENGTH]; 590 u8 Addr3[MAC_ADDR_LENGTH];
594 u16 Sequence_Control; 591 u16 Sequence_Control;
595 u8 Addr4[MAC_ADDR_LENGTH]; // only exist when ToDS=FromDS=1 592 u8 Addr4[MAC_ADDR_LENGTH]; // only exist when ToDS=FromDS=1
596 // Data Frame Body <= 2312 593 // Data Frame Body <= 2312
597 // FCS 594 // FCS
598 }__attribute__ ((packed)); 595 }__attribute__ ((packed));
599 596
600 struct Disassociation_Frame_Body 597 struct Disassociation_Frame_Body
601 { 598 {
602 u16 reasonCode; 599 u16 reasonCode;
603 }__attribute__ ((packed)); 600 }__attribute__ ((packed));
604 601
605 struct Association_Request_Frame_Body 602 struct Association_Request_Frame_Body
606 { 603 {
607 u16 capability_information; 604 u16 capability_information;
608 u16 listenInterval; 605 u16 listenInterval;
609 u8 Current_AP_Address[MAC_ADDR_LENGTH];//for reassociation only 606 u8 Current_AP_Address[MAC_ADDR_LENGTH];//for reassociation only
610 // SSID (2+32 bytes) 607 // SSID (2+32 bytes)
611 // Supported_Rates (2+8 bytes) 608 // Supported_Rates (2+8 bytes)
612 }__attribute__ ((packed)); 609 }__attribute__ ((packed));
613 610
614 struct Association_Response_Frame_Body 611 struct Association_Response_Frame_Body
615 { 612 {
616 u16 capability_information; 613 u16 capability_information;
617 u16 statusCode; 614 u16 statusCode;
618 u16 Association_ID; 615 u16 Association_ID;
619 struct Supported_Rates_Element supportedRates; 616 struct Supported_Rates_Element supportedRates;
620 }__attribute__ ((packed)); 617 }__attribute__ ((packed));
621 618
622 /*struct Reassociation_Request_Frame_Body 619 /*struct Reassociation_Request_Frame_Body
623 { 620 {
624 u16 capability_information; 621 u16 capability_information;
625 u16 listenInterval; 622 u16 listenInterval;
626 u8 Current_AP_Address[MAC_ADDR_LENGTH]; 623 u8 Current_AP_Address[MAC_ADDR_LENGTH];
627 // SSID (2+32 bytes) 624 // SSID (2+32 bytes)
628 // Supported_Rates (2+8 bytes) 625 // Supported_Rates (2+8 bytes)
629 };*/ 626 };*/
630 // eliminated by WS 07/22/04 comboined with associateion request frame. 627 // eliminated by WS 07/22/04 comboined with associateion request frame.
631 628
632 struct Reassociation_Response_Frame_Body 629 struct Reassociation_Response_Frame_Body
633 { 630 {
634 u16 capability_information; 631 u16 capability_information;
635 u16 statusCode; 632 u16 statusCode;
636 u16 Association_ID; 633 u16 Association_ID;
637 struct Supported_Rates_Element supportedRates; 634 struct Supported_Rates_Element supportedRates;
638 }__attribute__ ((packed)); 635 }__attribute__ ((packed));
639 636
640 struct Deauthentication_Frame_Body 637 struct Deauthentication_Frame_Body
641 { 638 {
642 u16 reasonCode; 639 u16 reasonCode;
643 }__attribute__ ((packed)); 640 }__attribute__ ((packed));
644 641
645 642
646 struct Probe_Response_Frame_Body 643 struct Probe_Response_Frame_Body
647 { 644 {
648 u16 Timestamp; 645 u16 Timestamp;
649 u16 Beacon_Interval; 646 u16 Beacon_Interval;
650 u16 Capability_Information; 647 u16 Capability_Information;
651 // SSID 648 // SSID
652 // Supported_Rates 649 // Supported_Rates
653 // PHY parameter Set (DS Parameters) 650 // PHY parameter Set (DS Parameters)
654 // CF parameter Set 651 // CF parameter Set
655 // IBSS parameter Set 652 // IBSS parameter Set
656 }__attribute__ ((packed)); 653 }__attribute__ ((packed));
657 654
658 struct Authentication_Frame_Body 655 struct Authentication_Frame_Body
659 { 656 {
660 u16 algorithmNumber; 657 u16 algorithmNumber;
661 u16 sequenceNumber; 658 u16 sequenceNumber;
662 u16 statusCode; 659 u16 statusCode;
663 // NB: don't include ChallengeText in this structure 660 // NB: don't include ChallengeText in this structure
664 // struct Challenge_Text_Element sChallengeTextElement; // wkchen added 661 // struct Challenge_Text_Element sChallengeTextElement; // wkchen added
665 }__attribute__ ((packed)); 662 }__attribute__ ((packed));
666 663
667 664
668 #endif // _MAC_Structure_H_ 665 #endif // _MAC_Structure_H_
669 666
670 667
drivers/staging/winbond/mds.c
Diff comments   View file @ 80aba53
1 #include "ds_tkip.h"
2 #include "gl_80211.h"
3 #include "mds_f.h"
4 #include "mlmetxrx_f.h"
5 #include "mto_f.h"
1 #include "os_common.h" 6 #include "os_common.h"
7 #include "wbhal_f.h"
8 #include "wblinux_f.h"
2 9
3 void 10 void
4 Mds_reset_descriptor(struct wb35_adapter * adapter) 11 Mds_reset_descriptor(struct wb35_adapter * adapter)
5 { 12 {
6 PMDS pMds = &adapter->Mds; 13 PMDS pMds = &adapter->Mds;
7 14
8 pMds->TxPause = 0; 15 pMds->TxPause = 0;
9 atomic_set(&pMds->TxThreadCount, 0); 16 atomic_set(&pMds->TxThreadCount, 0);
10 pMds->TxFillIndex = 0; 17 pMds->TxFillIndex = 0;
11 pMds->TxDesIndex = 0; 18 pMds->TxDesIndex = 0;
12 pMds->ScanTxPause = 0; 19 pMds->ScanTxPause = 0;
13 memset(pMds->TxOwner, 0, ((MAX_USB_TX_BUFFER_NUMBER + 3) & ~0x03)); 20 memset(pMds->TxOwner, 0, ((MAX_USB_TX_BUFFER_NUMBER + 3) & ~0x03));
14 } 21 }
15 22
16 unsigned char 23 unsigned char
17 Mds_initial(struct wb35_adapter * adapter) 24 Mds_initial(struct wb35_adapter * adapter)
18 { 25 {
19 PMDS pMds = &adapter->Mds; 26 PMDS pMds = &adapter->Mds;
20 27
21 pMds->TxPause = false; 28 pMds->TxPause = false;
22 pMds->TxRTSThreshold = DEFAULT_RTSThreshold; 29 pMds->TxRTSThreshold = DEFAULT_RTSThreshold;
23 pMds->TxFragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD; 30 pMds->TxFragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD;
24 31
25 vRxTimerInit(adapter);//for WPA countermeasure 32 vRxTimerInit(adapter);//for WPA countermeasure
26 33
27 return hal_get_tx_buffer( &adapter->sHwData, &pMds->pTxBuffer ); 34 return hal_get_tx_buffer( &adapter->sHwData, &pMds->pTxBuffer );
28 } 35 }
29 36
30 void 37 void
31 Mds_Destroy(struct wb35_adapter * adapter) 38 Mds_Destroy(struct wb35_adapter * adapter)
32 { 39 {
33 vRxTimerStop(adapter); 40 vRxTimerStop(adapter);
34 } 41 }
35 42
36 void 43 void
37 Mds_Tx(struct wb35_adapter * adapter) 44 Mds_Tx(struct wb35_adapter * adapter)
38 { 45 {
39 phw_data_t pHwData = &adapter->sHwData; 46 phw_data_t pHwData = &adapter->sHwData;
40 PMDS pMds = &adapter->Mds; 47 PMDS pMds = &adapter->Mds;
41 DESCRIPTOR TxDes; 48 DESCRIPTOR TxDes;
42 PDESCRIPTOR pTxDes = &TxDes; 49 PDESCRIPTOR pTxDes = &TxDes;
43 u8 *XmitBufAddress; 50 u8 *XmitBufAddress;
44 u16 XmitBufSize, PacketSize, stmp, CurrentSize, FragmentThreshold; 51 u16 XmitBufSize, PacketSize, stmp, CurrentSize, FragmentThreshold;
45 u8 FillIndex, TxDesIndex, FragmentCount, FillCount; 52 u8 FillIndex, TxDesIndex, FragmentCount, FillCount;
46 unsigned char BufferFilled = false, MICAdd = 0; 53 unsigned char BufferFilled = false, MICAdd = 0;
47 54
48 55
49 if (pMds->TxPause) 56 if (pMds->TxPause)
50 return; 57 return;
51 if (!hal_driver_init_OK(pHwData)) 58 if (!hal_driver_init_OK(pHwData))
52 return; 59 return;
53 60
54 //Only one thread can be run here 61 //Only one thread can be run here
55 if (!atomic_inc_return(&pMds->TxThreadCount) == 1) 62 if (!atomic_inc_return(&pMds->TxThreadCount) == 1)
56 goto cleanup; 63 goto cleanup;
57 64
58 // Start to fill the data 65 // Start to fill the data
59 do { 66 do {
60 FillIndex = pMds->TxFillIndex; 67 FillIndex = pMds->TxFillIndex;
61 if (pMds->TxOwner[FillIndex]) { // Is owned by software 0:Yes 1:No 68 if (pMds->TxOwner[FillIndex]) { // Is owned by software 0:Yes 1:No
62 #ifdef _PE_TX_DUMP_ 69 #ifdef _PE_TX_DUMP_
63 WBDEBUG(("[Mds_Tx] Tx Owner is H/W.\n")); 70 WBDEBUG(("[Mds_Tx] Tx Owner is H/W.\n"));
64 #endif 71 #endif
65 break; 72 break;
66 } 73 }
67 74
68 XmitBufAddress = pMds->pTxBuffer + (MAX_USB_TX_BUFFER * FillIndex); //Get buffer 75 XmitBufAddress = pMds->pTxBuffer + (MAX_USB_TX_BUFFER * FillIndex); //Get buffer
69 XmitBufSize = 0; 76 XmitBufSize = 0;
70 FillCount = 0; 77 FillCount = 0;
71 do { 78 do {
72 PacketSize = adapter->sMlmeFrame.len; 79 PacketSize = adapter->sMlmeFrame.len;
73 if (!PacketSize) 80 if (!PacketSize)
74 break; 81 break;
75 82
76 //For Check the buffer resource 83 //For Check the buffer resource
77 FragmentThreshold = CURRENT_FRAGMENT_THRESHOLD; 84 FragmentThreshold = CURRENT_FRAGMENT_THRESHOLD;
78 //931130.5.b 85 //931130.5.b
79 FragmentCount = PacketSize/FragmentThreshold + 1; 86 FragmentCount = PacketSize/FragmentThreshold + 1;
80 stmp = PacketSize + FragmentCount*32 + 8;//931130.5.c 8:MIC 87 stmp = PacketSize + FragmentCount*32 + 8;//931130.5.c 8:MIC
81 if ((XmitBufSize + stmp) >= MAX_USB_TX_BUFFER) { 88 if ((XmitBufSize + stmp) >= MAX_USB_TX_BUFFER) {
82 printk("[Mds_Tx] Excess max tx buffer.\n"); 89 printk("[Mds_Tx] Excess max tx buffer.\n");
83 break; // buffer is not enough 90 break; // buffer is not enough
84 } 91 }
85 92
86 93
87 // 94 //
88 // Start transmitting 95 // Start transmitting
89 // 96 //
90 BufferFilled = true; 97 BufferFilled = true;
91 98
92 /* Leaves first u8 intact */ 99 /* Leaves first u8 intact */
93 memset((u8 *)pTxDes + 1, 0, sizeof(DESCRIPTOR) - 1); 100 memset((u8 *)pTxDes + 1, 0, sizeof(DESCRIPTOR) - 1);
94 101
95 TxDesIndex = pMds->TxDesIndex;//Get the current ID 102 TxDesIndex = pMds->TxDesIndex;//Get the current ID
96 pTxDes->Descriptor_ID = TxDesIndex; 103 pTxDes->Descriptor_ID = TxDesIndex;
97 pMds->TxDesFrom[ TxDesIndex ] = 2;//Storing the information of source comming from 104 pMds->TxDesFrom[ TxDesIndex ] = 2;//Storing the information of source comming from
98 pMds->TxDesIndex++; 105 pMds->TxDesIndex++;
99 pMds->TxDesIndex %= MAX_USB_TX_DESCRIPTOR; 106 pMds->TxDesIndex %= MAX_USB_TX_DESCRIPTOR;
100 107
101 MLME_GetNextPacket( adapter, pTxDes ); 108 MLME_GetNextPacket( adapter, pTxDes );
102 109
103 // Copy header. 8byte USB + 24byte 802.11Hdr. Set TxRate, Preamble type 110 // Copy header. 8byte USB + 24byte 802.11Hdr. Set TxRate, Preamble type
104 Mds_HeaderCopy( adapter, pTxDes, XmitBufAddress ); 111 Mds_HeaderCopy( adapter, pTxDes, XmitBufAddress );
105 112
106 // For speed up Key setting 113 // For speed up Key setting
107 if (pTxDes->EapFix) { 114 if (pTxDes->EapFix) {
108 #ifdef _PE_TX_DUMP_ 115 #ifdef _PE_TX_DUMP_
109 WBDEBUG(("35: EPA 4th frame detected. Size = %d\n", PacketSize)); 116 WBDEBUG(("35: EPA 4th frame detected. Size = %d\n", PacketSize));
110 #endif 117 #endif
111 pHwData->IsKeyPreSet = 1; 118 pHwData->IsKeyPreSet = 1;
112 } 119 }
113 120
114 // Copy (fragment) frame body, and set USB, 802.11 hdr flag 121 // Copy (fragment) frame body, and set USB, 802.11 hdr flag
115 CurrentSize = Mds_BodyCopy(adapter, pTxDes, XmitBufAddress); 122 CurrentSize = Mds_BodyCopy(adapter, pTxDes, XmitBufAddress);
116 123
117 // Set RTS/CTS and Normal duration field into buffer 124 // Set RTS/CTS and Normal duration field into buffer
118 Mds_DurationSet(adapter, pTxDes, XmitBufAddress); 125 Mds_DurationSet(adapter, pTxDes, XmitBufAddress);
119 126
120 // 127 //
121 // Calculation MIC from buffer which maybe fragment, then fill into temporary address 8 byte 128 // Calculation MIC from buffer which maybe fragment, then fill into temporary address 8 byte
122 // 931130.5.e 129 // 931130.5.e
123 if (MICAdd) 130 if (MICAdd)
124 Mds_MicFill( adapter, pTxDes, XmitBufAddress ); 131 Mds_MicFill( adapter, pTxDes, XmitBufAddress );
125 132
126 //Shift to the next address 133 //Shift to the next address
127 XmitBufSize += CurrentSize; 134 XmitBufSize += CurrentSize;
128 XmitBufAddress += CurrentSize; 135 XmitBufAddress += CurrentSize;
129 136
130 #ifdef _IBSS_BEACON_SEQ_STICK_ 137 #ifdef _IBSS_BEACON_SEQ_STICK_
131 if ((XmitBufAddress[ DOT_11_DA_OFFSET+8 ] & 0xfc) != MAC_SUBTYPE_MNGMNT_PROBE_REQUEST) // +8 for USB hdr 138 if ((XmitBufAddress[ DOT_11_DA_OFFSET+8 ] & 0xfc) != MAC_SUBTYPE_MNGMNT_PROBE_REQUEST) // +8 for USB hdr
132 #endif 139 #endif
133 pMds->TxToggle = true; 140 pMds->TxToggle = true;
134 141
135 // Get packet to transmit completed, 1:TESTSTA 2:MLME 3: Ndis data 142 // Get packet to transmit completed, 1:TESTSTA 2:MLME 3: Ndis data
136 MLME_SendComplete(adapter, 0, true); 143 MLME_SendComplete(adapter, 0, true);
137 144
138 // Software TSC count 20060214 145 // Software TSC count 20060214
139 pMds->TxTsc++; 146 pMds->TxTsc++;
140 if (pMds->TxTsc == 0) 147 if (pMds->TxTsc == 0)
141 pMds->TxTsc_2++; 148 pMds->TxTsc_2++;
142 149
143 FillCount++; // 20060928 150 FillCount++; // 20060928
144 } while (HAL_USB_MODE_BURST(pHwData)); // End of multiple MSDU copy loop. false = single true = multiple sending 151 } while (HAL_USB_MODE_BURST(pHwData)); // End of multiple MSDU copy loop. false = single true = multiple sending
145 152
146 // Move to the next one, if necessary 153 // Move to the next one, if necessary
147 if (BufferFilled) { 154 if (BufferFilled) {
148 // size setting 155 // size setting
149 pMds->TxBufferSize[ FillIndex ] = XmitBufSize; 156 pMds->TxBufferSize[ FillIndex ] = XmitBufSize;
150 157
151 // 20060928 set Tx count 158 // 20060928 set Tx count
152 pMds->TxCountInBuffer[FillIndex] = FillCount; 159 pMds->TxCountInBuffer[FillIndex] = FillCount;
153 160
154 // Set owner flag 161 // Set owner flag
155 pMds->TxOwner[FillIndex] = 1; 162 pMds->TxOwner[FillIndex] = 1;
156 163
157 pMds->TxFillIndex++; 164 pMds->TxFillIndex++;
158 pMds->TxFillIndex %= MAX_USB_TX_BUFFER_NUMBER; 165 pMds->TxFillIndex %= MAX_USB_TX_BUFFER_NUMBER;
159 BufferFilled = false; 166 BufferFilled = false;
160 } else 167 } else
161 break; 168 break;
162 169
163 if (!PacketSize) // No more pk for transmitting 170 if (!PacketSize) // No more pk for transmitting
164 break; 171 break;
165 172
166 } while(true); 173 } while(true);
167 174
168 // 175 //
169 // Start to send by lower module 176 // Start to send by lower module
170 // 177 //
171 if (!pHwData->IsKeyPreSet) 178 if (!pHwData->IsKeyPreSet)
172 Wb35Tx_start(pHwData); 179 Wb35Tx_start(pHwData);
173 180
174 cleanup: 181 cleanup:
175 atomic_dec(&pMds->TxThreadCount); 182 atomic_dec(&pMds->TxThreadCount);
176 } 183 }
177 184
178 void 185 void
179 Mds_SendComplete(struct wb35_adapter * adapter, PT02_DESCRIPTOR pT02) 186 Mds_SendComplete(struct wb35_adapter * adapter, PT02_DESCRIPTOR pT02)
180 { 187 {
181 PMDS pMds = &adapter->Mds; 188 PMDS pMds = &adapter->Mds;
182 phw_data_t pHwData = &adapter->sHwData; 189 phw_data_t pHwData = &adapter->sHwData;
183 u8 PacketId = (u8)pT02->T02_Tx_PktID; 190 u8 PacketId = (u8)pT02->T02_Tx_PktID;
184 unsigned char SendOK = true; 191 unsigned char SendOK = true;
185 u8 RetryCount, TxRate; 192 u8 RetryCount, TxRate;
186 193
187 if (pT02->T02_IgnoreResult) // Don't care the result 194 if (pT02->T02_IgnoreResult) // Don't care the result
188 return; 195 return;
189 if (pT02->T02_IsLastMpdu) { 196 if (pT02->T02_IsLastMpdu) {
190 //TODO: DTO -- get the retry count and fragment count 197 //TODO: DTO -- get the retry count and fragment count
191 // Tx rate 198 // Tx rate
192 TxRate = pMds->TxRate[ PacketId ][ 0 ]; 199 TxRate = pMds->TxRate[ PacketId ][ 0 ];
193 RetryCount = (u8)pT02->T02_MPDU_Cnt; 200 RetryCount = (u8)pT02->T02_MPDU_Cnt;
194 if (pT02->value & FLAG_ERROR_TX_MASK) { 201 if (pT02->value & FLAG_ERROR_TX_MASK) {
195 SendOK = false; 202 SendOK = false;
196 203
197 if (pT02->T02_transmit_abort || pT02->T02_out_of_MaxTxMSDULiftTime) { 204 if (pT02->T02_transmit_abort || pT02->T02_out_of_MaxTxMSDULiftTime) {
198 //retry error 205 //retry error
199 pHwData->dto_tx_retry_count += (RetryCount+1); 206 pHwData->dto_tx_retry_count += (RetryCount+1);
200 //[for tx debug] 207 //[for tx debug]
201 if (RetryCount<7) 208 if (RetryCount<7)
202 pHwData->tx_retry_count[RetryCount] += RetryCount; 209 pHwData->tx_retry_count[RetryCount] += RetryCount;
203 else 210 else
204 pHwData->tx_retry_count[7] += RetryCount; 211 pHwData->tx_retry_count[7] += RetryCount;
205 #ifdef _PE_STATE_DUMP_ 212 #ifdef _PE_STATE_DUMP_
206 WBDEBUG(("dto_tx_retry_count =%d\n", pHwData->dto_tx_retry_count)); 213 WBDEBUG(("dto_tx_retry_count =%d\n", pHwData->dto_tx_retry_count));
207 #endif 214 #endif
208 MTO_SetTxCount(adapter, TxRate, RetryCount); 215 MTO_SetTxCount(adapter, TxRate, RetryCount);
209 } 216 }
210 pHwData->dto_tx_frag_count += (RetryCount+1); 217 pHwData->dto_tx_frag_count += (RetryCount+1);
211 218
212 //[for tx debug] 219 //[for tx debug]
213 if (pT02->T02_transmit_abort_due_to_TBTT) 220 if (pT02->T02_transmit_abort_due_to_TBTT)
214 pHwData->tx_TBTT_start_count++; 221 pHwData->tx_TBTT_start_count++;
215 if (pT02->T02_transmit_without_encryption_due_to_wep_on_false) 222 if (pT02->T02_transmit_without_encryption_due_to_wep_on_false)
216 pHwData->tx_WepOn_false_count++; 223 pHwData->tx_WepOn_false_count++;
217 if (pT02->T02_discard_due_to_null_wep_key) 224 if (pT02->T02_discard_due_to_null_wep_key)
218 pHwData->tx_Null_key_count++; 225 pHwData->tx_Null_key_count++;
219 } else { 226 } else {
220 if (pT02->T02_effective_transmission_rate) 227 if (pT02->T02_effective_transmission_rate)
221 pHwData->tx_ETR_count++; 228 pHwData->tx_ETR_count++;
222 MTO_SetTxCount(adapter, TxRate, RetryCount); 229 MTO_SetTxCount(adapter, TxRate, RetryCount);
223 } 230 }
224 231
225 // Clear send result buffer 232 // Clear send result buffer
226 pMds->TxResult[ PacketId ] = 0; 233 pMds->TxResult[ PacketId ] = 0;
227 } else 234 } else
228 pMds->TxResult[ PacketId ] |= ((u16)(pT02->value & 0x0ffff)); 235 pMds->TxResult[ PacketId ] |= ((u16)(pT02->value & 0x0ffff));
229 } 236 }
230 237
231 void 238 void
232 Mds_HeaderCopy(struct wb35_adapter * adapter, PDESCRIPTOR pDes, u8 *TargetBuffer) 239 Mds_HeaderCopy(struct wb35_adapter * adapter, PDESCRIPTOR pDes, u8 *TargetBuffer)
233 { 240 {
234 PMDS pMds = &adapter->Mds; 241 PMDS pMds = &adapter->Mds;
235 u8 *src_buffer = pDes->buffer_address[0];//931130.5.g 242 u8 *src_buffer = pDes->buffer_address[0];//931130.5.g
236 PT00_DESCRIPTOR pT00; 243 PT00_DESCRIPTOR pT00;
237 PT01_DESCRIPTOR pT01; 244 PT01_DESCRIPTOR pT01;
238 u16 stmp; 245 u16 stmp;
239 u8 i, ctmp1, ctmp2, ctmpf; 246 u8 i, ctmp1, ctmp2, ctmpf;
240 u16 FragmentThreshold = CURRENT_FRAGMENT_THRESHOLD; 247 u16 FragmentThreshold = CURRENT_FRAGMENT_THRESHOLD;
241 248
242 249
243 stmp = pDes->buffer_total_size; 250 stmp = pDes->buffer_total_size;
244 // 251 //
245 // Set USB header 8 byte 252 // Set USB header 8 byte
246 // 253 //
247 pT00 = (PT00_DESCRIPTOR)TargetBuffer; 254 pT00 = (PT00_DESCRIPTOR)TargetBuffer;
248 TargetBuffer += 4; 255 TargetBuffer += 4;
249 pT01 = (PT01_DESCRIPTOR)TargetBuffer; 256 pT01 = (PT01_DESCRIPTOR)TargetBuffer;
250 TargetBuffer += 4; 257 TargetBuffer += 4;
251 258
252 pT00->value = 0;// Clear 259 pT00->value = 0;// Clear
253 pT01->value = 0;// Clear 260 pT01->value = 0;// Clear
254 261
255 pT00->T00_tx_packet_id = pDes->Descriptor_ID;// Set packet ID 262 pT00->T00_tx_packet_id = pDes->Descriptor_ID;// Set packet ID
256 pT00->T00_header_length = 24;// Set header length 263 pT00->T00_header_length = 24;// Set header length
257 pT01->T01_retry_abort_ebable = 1;//921013 931130.5.h 264 pT01->T01_retry_abort_ebable = 1;//921013 931130.5.h
258 265
259 // Key ID setup 266 // Key ID setup
260 pT01->T01_wep_id = 0; 267 pT01->T01_wep_id = 0;
261 268
262 FragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD; //Do not fragment 269 FragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD; //Do not fragment
263 // Copy full data, the 1'st buffer contain all the data 931130.5.j 270 // Copy full data, the 1'st buffer contain all the data 931130.5.j
264 memcpy( TargetBuffer, src_buffer, DOT_11_MAC_HEADER_SIZE );// Copy header 271 memcpy( TargetBuffer, src_buffer, DOT_11_MAC_HEADER_SIZE );// Copy header
265 pDes->buffer_address[0] = src_buffer + DOT_11_MAC_HEADER_SIZE; 272 pDes->buffer_address[0] = src_buffer + DOT_11_MAC_HEADER_SIZE;
266 pDes->buffer_total_size -= DOT_11_MAC_HEADER_SIZE; 273 pDes->buffer_total_size -= DOT_11_MAC_HEADER_SIZE;
267 pDes->buffer_size[0] = pDes->buffer_total_size; 274 pDes->buffer_size[0] = pDes->buffer_total_size;
268 275
269 // Set fragment threshold 276 // Set fragment threshold
270 FragmentThreshold -= (DOT_11_MAC_HEADER_SIZE + 4); 277 FragmentThreshold -= (DOT_11_MAC_HEADER_SIZE + 4);
271 pDes->FragmentThreshold = FragmentThreshold; 278 pDes->FragmentThreshold = FragmentThreshold;
272 279
273 // Set more frag bit 280 // Set more frag bit
274 TargetBuffer[1] |= 0x04;// Set more frag bit 281 TargetBuffer[1] |= 0x04;// Set more frag bit
275 282
276 // 283 //
277 // Set tx rate 284 // Set tx rate
278 // 285 //
279 stmp = *(u16 *)(TargetBuffer+30); // 2n alignment address 286 stmp = *(u16 *)(TargetBuffer+30); // 2n alignment address
280 287
281 //Use basic rate 288 //Use basic rate
282 ctmp1 = ctmpf = CURRENT_TX_RATE_FOR_MNG; 289 ctmp1 = ctmpf = CURRENT_TX_RATE_FOR_MNG;
283 290
284 pDes->TxRate = ctmp1; 291 pDes->TxRate = ctmp1;
285 #ifdef _PE_TX_DUMP_ 292 #ifdef _PE_TX_DUMP_
286 WBDEBUG(("Tx rate =%x\n", ctmp1)); 293 WBDEBUG(("Tx rate =%x\n", ctmp1));
287 #endif 294 #endif
288 295
289 pT01->T01_modulation_type = (ctmp1%3) ? 0 : 1; 296 pT01->T01_modulation_type = (ctmp1%3) ? 0 : 1;
290 297
291 for( i=0; i<2; i++ ) { 298 for( i=0; i<2; i++ ) {
292 if( i == 1 ) 299 if( i == 1 )
293 ctmp1 = ctmpf; 300 ctmp1 = ctmpf;
294 301
295 pMds->TxRate[pDes->Descriptor_ID][i] = ctmp1; // backup the ta rate and fall back rate 302 pMds->TxRate[pDes->Descriptor_ID][i] = ctmp1; // backup the ta rate and fall back rate
296 303
297 if( ctmp1 == 108) ctmp2 = 7; 304 if( ctmp1 == 108) ctmp2 = 7;
298 else if( ctmp1 == 96 ) ctmp2 = 6; // Rate convert for USB 305 else if( ctmp1 == 96 ) ctmp2 = 6; // Rate convert for USB
299 else if( ctmp1 == 72 ) ctmp2 = 5; 306 else if( ctmp1 == 72 ) ctmp2 = 5;
300 else if( ctmp1 == 48 ) ctmp2 = 4; 307 else if( ctmp1 == 48 ) ctmp2 = 4;
301 else if( ctmp1 == 36 ) ctmp2 = 3; 308 else if( ctmp1 == 36 ) ctmp2 = 3;
302 else if( ctmp1 == 24 ) ctmp2 = 2; 309 else if( ctmp1 == 24 ) ctmp2 = 2;
303 else if( ctmp1 == 18 ) ctmp2 = 1; 310 else if( ctmp1 == 18 ) ctmp2 = 1;
304 else if( ctmp1 == 12 ) ctmp2 = 0; 311 else if( ctmp1 == 12 ) ctmp2 = 0;
305 else if( ctmp1 == 22 ) ctmp2 = 3; 312 else if( ctmp1 == 22 ) ctmp2 = 3;
306 else if( ctmp1 == 11 ) ctmp2 = 2; 313 else if( ctmp1 == 11 ) ctmp2 = 2;
307 else if( ctmp1 == 4 ) ctmp2 = 1; 314 else if( ctmp1 == 4 ) ctmp2 = 1;
308 else ctmp2 = 0; // if( ctmp1 == 2 ) or default 315 else ctmp2 = 0; // if( ctmp1 == 2 ) or default
309 316
310 if( i == 0 ) 317 if( i == 0 )
311 pT01->T01_transmit_rate = ctmp2; 318 pT01->T01_transmit_rate = ctmp2;
312 else 319 else
313 pT01->T01_fall_back_rate = ctmp2; 320 pT01->T01_fall_back_rate = ctmp2;
314 } 321 }
315 322
316 // 323 //
317 // Set preamble type 324 // Set preamble type
318 // 325 //
319 if ((pT01->T01_modulation_type == 0) && (pT01->T01_transmit_rate == 0)) // RATE_1M 326 if ((pT01->T01_modulation_type == 0) && (pT01->T01_transmit_rate == 0)) // RATE_1M
320 pDes->PreambleMode = WLAN_PREAMBLE_TYPE_LONG; 327 pDes->PreambleMode = WLAN_PREAMBLE_TYPE_LONG;
321 else 328 else
322 pDes->PreambleMode = CURRENT_PREAMBLE_MODE; 329 pDes->PreambleMode = CURRENT_PREAMBLE_MODE;
323 pT01->T01_plcp_header_length = pDes->PreambleMode; // Set preamble 330 pT01->T01_plcp_header_length = pDes->PreambleMode; // Set preamble
324 331
325 } 332 }
326 333
327 // The function return the 4n size of usb pk 334 // The function return the 4n size of usb pk
328 u16 335 u16
329 Mds_BodyCopy(struct wb35_adapter * adapter, PDESCRIPTOR pDes, u8 *TargetBuffer) 336 Mds_BodyCopy(struct wb35_adapter * adapter, PDESCRIPTOR pDes, u8 *TargetBuffer)
330 { 337 {
331 PT00_DESCRIPTOR pT00; 338 PT00_DESCRIPTOR pT00;
332 PMDS pMds = &adapter->Mds; 339 PMDS pMds = &adapter->Mds;
333 u8 *buffer; 340 u8 *buffer;
334 u8 *src_buffer; 341 u8 *src_buffer;
335 u8 *pctmp; 342 u8 *pctmp;
336 u16 Size = 0; 343 u16 Size = 0;
337 u16 SizeLeft, CopySize, CopyLeft, stmp; 344 u16 SizeLeft, CopySize, CopyLeft, stmp;
338 u8 buf_index, FragmentCount = 0; 345 u8 buf_index, FragmentCount = 0;
339 346
340 347
341 // Copy fragment body 348 // Copy fragment body
342 buffer = TargetBuffer; // shift 8B usb + 24B 802.11 349 buffer = TargetBuffer; // shift 8B usb + 24B 802.11
343 SizeLeft = pDes->buffer_total_size; 350 SizeLeft = pDes->buffer_total_size;
344 buf_index = pDes->buffer_start_index; 351 buf_index = pDes->buffer_start_index;
345 352
346 pT00 = (PT00_DESCRIPTOR)buffer; 353 pT00 = (PT00_DESCRIPTOR)buffer;
347 while (SizeLeft) { 354 while (SizeLeft) {
348 pT00 = (PT00_DESCRIPTOR)buffer; 355 pT00 = (PT00_DESCRIPTOR)buffer;
349 CopySize = SizeLeft; 356 CopySize = SizeLeft;
350 if (SizeLeft > pDes->FragmentThreshold) { 357 if (SizeLeft > pDes->FragmentThreshold) {
351 CopySize = pDes->FragmentThreshold; 358 CopySize = pDes->FragmentThreshold;
352 pT00->T00_frame_length = 24 + CopySize;//Set USB length 359 pT00->T00_frame_length = 24 + CopySize;//Set USB length
353 } else 360 } else
354 pT00->T00_frame_length = 24 + SizeLeft;//Set USB length 361 pT00->T00_frame_length = 24 + SizeLeft;//Set USB length
355 362
356 SizeLeft -= CopySize; 363 SizeLeft -= CopySize;
357 364
358 // 1 Byte operation 365 // 1 Byte operation
359 pctmp = (u8 *)( buffer + 8 + DOT_11_SEQUENCE_OFFSET ); 366 pctmp = (u8 *)( buffer + 8 + DOT_11_SEQUENCE_OFFSET );
360 *pctmp &= 0xf0; 367 *pctmp &= 0xf0;
361 *pctmp |= FragmentCount;//931130.5.m 368 *pctmp |= FragmentCount;//931130.5.m
362 if( !FragmentCount ) 369 if( !FragmentCount )
363 pT00->T00_first_mpdu = 1; 370 pT00->T00_first_mpdu = 1;
364 371
365 buffer += 32; // 8B usb + 24B 802.11 header 372 buffer += 32; // 8B usb + 24B 802.11 header
366 Size += 32; 373 Size += 32;
367 374
368 // Copy into buffer 375 // Copy into buffer
369 stmp = CopySize + 3; 376 stmp = CopySize + 3;
370 stmp &= ~0x03;//4n Alignment 377 stmp &= ~0x03;//4n Alignment
371 Size += stmp;// Current 4n offset of mpdu 378 Size += stmp;// Current 4n offset of mpdu
372 379
373 while (CopySize) { 380 while (CopySize) {
374 // Copy body 381 // Copy body
375 src_buffer = pDes->buffer_address[buf_index]; 382 src_buffer = pDes->buffer_address[buf_index];
376 CopyLeft = CopySize; 383 CopyLeft = CopySize;
377 if (CopySize >= pDes->buffer_size[buf_index]) { 384 if (CopySize >= pDes->buffer_size[buf_index]) {
378 CopyLeft = pDes->buffer_size[buf_index]; 385 CopyLeft = pDes->buffer_size[buf_index];
379 386
380 // Get the next buffer of descriptor 387 // Get the next buffer of descriptor
381 buf_index++; 388 buf_index++;
382 buf_index %= MAX_DESCRIPTOR_BUFFER_INDEX; 389 buf_index %= MAX_DESCRIPTOR_BUFFER_INDEX;
383 } else { 390 } else {
384 u8 *pctmp = pDes->buffer_address[buf_index]; 391 u8 *pctmp = pDes->buffer_address[buf_index];
385 pctmp += CopySize; 392 pctmp += CopySize;
386 pDes->buffer_address[buf_index] = pctmp; 393 pDes->buffer_address[buf_index] = pctmp;
387 pDes->buffer_size[buf_index] -= CopySize; 394 pDes->buffer_size[buf_index] -= CopySize;
388 } 395 }
389 396
390 memcpy(buffer, src_buffer, CopyLeft); 397 memcpy(buffer, src_buffer, CopyLeft);
391 buffer += CopyLeft; 398 buffer += CopyLeft;
392 CopySize -= CopyLeft; 399 CopySize -= CopyLeft;
393 } 400 }
394 401
395 // 931130.5.n 402 // 931130.5.n
396 if (pMds->MicAdd) { 403 if (pMds->MicAdd) {
397 if (!SizeLeft) { 404 if (!SizeLeft) {
398 pMds->MicWriteAddress[ pMds->MicWriteIndex ] = buffer - pMds->MicAdd; 405 pMds->MicWriteAddress[ pMds->MicWriteIndex ] = buffer - pMds->MicAdd;
399 pMds->MicWriteSize[ pMds->MicWriteIndex ] = pMds->MicAdd; 406 pMds->MicWriteSize[ pMds->MicWriteIndex ] = pMds->MicAdd;
400 pMds->MicAdd = 0; 407 pMds->MicAdd = 0;
401 } 408 }
402 else if( SizeLeft < 8 ) //931130.5.p 409 else if( SizeLeft < 8 ) //931130.5.p
403 { 410 {
404 pMds->MicAdd = SizeLeft; 411 pMds->MicAdd = SizeLeft;
405 pMds->MicWriteAddress[ pMds->MicWriteIndex ] = buffer - ( 8 - SizeLeft ); 412 pMds->MicWriteAddress[ pMds->MicWriteIndex ] = buffer - ( 8 - SizeLeft );
406 pMds->MicWriteSize[ pMds->MicWriteIndex ] = 8 - SizeLeft; 413 pMds->MicWriteSize[ pMds->MicWriteIndex ] = 8 - SizeLeft;
407 pMds->MicWriteIndex++; 414 pMds->MicWriteIndex++;
408 } 415 }
409 } 416 }
410 417
411 // Does it need to generate the new header for next mpdu? 418 // Does it need to generate the new header for next mpdu?
412 if (SizeLeft) { 419 if (SizeLeft) {
413 buffer = TargetBuffer + Size; // Get the next 4n start address 420 buffer = TargetBuffer + Size; // Get the next 4n start address
414 memcpy( buffer, TargetBuffer, 32 );//Copy 8B USB +24B 802.11 421 memcpy( buffer, TargetBuffer, 32 );//Copy 8B USB +24B 802.11
415 pT00 = (PT00_DESCRIPTOR)buffer; 422 pT00 = (PT00_DESCRIPTOR)buffer;
416 pT00->T00_first_mpdu = 0; 423 pT00->T00_first_mpdu = 0;
417 } 424 }
418 425
419 FragmentCount++; 426 FragmentCount++;
420 } 427 }
421 428
422 pT00->T00_last_mpdu = 1; 429 pT00->T00_last_mpdu = 1;
423 pT00->T00_IsLastMpdu = 1; 430 pT00->T00_IsLastMpdu = 1;
424 buffer = (u8 *)pT00 + 8; // +8 for USB hdr 431 buffer = (u8 *)pT00 + 8; // +8 for USB hdr
425 buffer[1] &= ~0x04; // Clear more frag bit of 802.11 frame control 432 buffer[1] &= ~0x04; // Clear more frag bit of 802.11 frame control
426 pDes->FragmentCount = FragmentCount; // Update the correct fragment number 433 pDes->FragmentCount = FragmentCount; // Update the correct fragment number
427 return Size; 434 return Size;
428 } 435 }
429 436
430 437
431 void 438 void
432 Mds_DurationSet( struct wb35_adapter * adapter, PDESCRIPTOR pDes, u8 *buffer ) 439 Mds_DurationSet( struct wb35_adapter * adapter, PDESCRIPTOR pDes, u8 *buffer )
433 { 440 {
434 PT00_DESCRIPTOR pT00; 441 PT00_DESCRIPTOR pT00;
435 PT01_DESCRIPTOR pT01; 442 PT01_DESCRIPTOR pT01;
436 u16 Duration, NextBodyLen, OffsetSize; 443 u16 Duration, NextBodyLen, OffsetSize;
437 u8 Rate, i; 444 u8 Rate, i;
438 unsigned char CTS_on = false, RTS_on = false; 445 unsigned char CTS_on = false, RTS_on = false;
439 PT00_DESCRIPTOR pNextT00; 446 PT00_DESCRIPTOR pNextT00;
440 u16 BodyLen = 0; 447 u16 BodyLen = 0;
441 unsigned char boGroupAddr = false; 448 unsigned char boGroupAddr = false;
442 449
443 OffsetSize = pDes->FragmentThreshold + 32 + 3; 450 OffsetSize = pDes->FragmentThreshold + 32 + 3;
444 OffsetSize &= ~0x03; 451 OffsetSize &= ~0x03;
445 Rate = pDes->TxRate >> 1; 452 Rate = pDes->TxRate >> 1;
446 if (!Rate) 453 if (!Rate)
447 Rate = 1; 454 Rate = 1;
448 455
449 pT00 = (PT00_DESCRIPTOR)buffer; 456 pT00 = (PT00_DESCRIPTOR)buffer;
450 pT01 = (PT01_DESCRIPTOR)(buffer+4); 457 pT01 = (PT01_DESCRIPTOR)(buffer+4);
451 pNextT00 = (PT00_DESCRIPTOR)(buffer+OffsetSize); 458 pNextT00 = (PT00_DESCRIPTOR)(buffer+OffsetSize);
452 459
453 if( buffer[ DOT_11_DA_OFFSET+8 ] & 0x1 ) // +8 for USB hdr 460 if( buffer[ DOT_11_DA_OFFSET+8 ] & 0x1 ) // +8 for USB hdr
454 boGroupAddr = true; 461 boGroupAddr = true;
455 462
456 //======================================== 463 //========================================
457 // Set RTS/CTS mechanism 464 // Set RTS/CTS mechanism
458 //======================================== 465 //========================================
459 if (!boGroupAddr) 466 if (!boGroupAddr)
460 { 467 {
461 //NOTE : If the protection mode is enabled and the MSDU will be fragmented, 468 //NOTE : If the protection mode is enabled and the MSDU will be fragmented,
462 // the tx rates of MPDUs will all be DSSS rates. So it will not use 469 // the tx rates of MPDUs will all be DSSS rates. So it will not use
463 // CTS-to-self in this case. CTS-To-self will only be used when without 470 // CTS-to-self in this case. CTS-To-self will only be used when without
464 // fragmentation. -- 20050112 471 // fragmentation. -- 20050112
465 BodyLen = (u16)pT00->T00_frame_length; //include 802.11 header 472 BodyLen = (u16)pT00->T00_frame_length; //include 802.11 header
466 BodyLen += 4; //CRC 473 BodyLen += 4; //CRC
467 474
468 if( BodyLen >= CURRENT_RTS_THRESHOLD ) 475 if( BodyLen >= CURRENT_RTS_THRESHOLD )
469 RTS_on = true; // Using RTS 476 RTS_on = true; // Using RTS
470 else 477 else
471 { 478 {
472 if( pT01->T01_modulation_type ) // Is using OFDM 479 if( pT01->T01_modulation_type ) // Is using OFDM
473 { 480 {
474 if( CURRENT_PROTECT_MECHANISM ) // Is using protect 481 if( CURRENT_PROTECT_MECHANISM ) // Is using protect
475 CTS_on = true; // Using CTS 482 CTS_on = true; // Using CTS
476 } 483 }
477 } 484 }
478 } 485 }
479 486
480 if( RTS_on || CTS_on ) 487 if( RTS_on || CTS_on )
481 { 488 {
482 if( pT01->T01_modulation_type) // Is using OFDM 489 if( pT01->T01_modulation_type) // Is using OFDM
483 { 490 {
484 //CTS duration 491 //CTS duration
485 // 2 SIFS + DATA transmit time + 1 ACK 492 // 2 SIFS + DATA transmit time + 1 ACK
486 // ACK Rate : 24 Mega bps 493 // ACK Rate : 24 Mega bps
487 // ACK frame length = 14 bytes 494 // ACK frame length = 14 bytes
488 Duration = 2*DEFAULT_SIFSTIME + 495 Duration = 2*DEFAULT_SIFSTIME +
489 2*PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION + 496 2*PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION +
490 ((BodyLen*8 + 22 + Rate*4 - 1)/(Rate*4))*Tsym + 497 ((BodyLen*8 + 22 + Rate*4 - 1)/(Rate*4))*Tsym +
491 ((112 + 22 + 95)/96)*Tsym; 498 ((112 + 22 + 95)/96)*Tsym;
492 } 499 }
493 else //DSSS 500 else //DSSS
494 { 501 {
495 //CTS duration 502 //CTS duration
496 // 2 SIFS + DATA transmit time + 1 ACK 503 // 2 SIFS + DATA transmit time + 1 ACK
497 // Rate : ?? Mega bps 504 // Rate : ?? Mega bps
498 // ACK frame length = 14 bytes 505 // ACK frame length = 14 bytes
499 if( pT01->T01_plcp_header_length ) //long preamble 506 if( pT01->T01_plcp_header_length ) //long preamble
500 Duration = LONG_PREAMBLE_PLUS_PLCPHEADER_TIME*2; 507 Duration = LONG_PREAMBLE_PLUS_PLCPHEADER_TIME*2;
501 else 508 else
502 Duration = SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME*2; 509 Duration = SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME*2;
503 510
504 Duration += ( ((BodyLen + 14)*8 + Rate-1) / Rate + 511 Duration += ( ((BodyLen + 14)*8 + Rate-1) / Rate +
505 DEFAULT_SIFSTIME*2 ); 512 DEFAULT_SIFSTIME*2 );
506 } 513 }
507 514
508 if( RTS_on ) 515 if( RTS_on )
509 { 516 {
510 if( pT01->T01_modulation_type ) // Is using OFDM 517 if( pT01->T01_modulation_type ) // Is using OFDM
511 { 518 {
512 //CTS + 1 SIFS + CTS duration 519 //CTS + 1 SIFS + CTS duration
513 //CTS Rate : 24 Mega bps 520 //CTS Rate : 24 Mega bps
514 //CTS frame length = 14 bytes 521 //CTS frame length = 14 bytes
515 Duration += (DEFAULT_SIFSTIME + 522 Duration += (DEFAULT_SIFSTIME +
516 PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION + 523 PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION +
517 ((112 + 22 + 95)/96)*Tsym); 524 ((112 + 22 + 95)/96)*Tsym);
518 } 525 }
519 else 526 else
520 { 527 {
521 //CTS + 1 SIFS + CTS duration 528 //CTS + 1 SIFS + CTS duration
522 //CTS Rate : ?? Mega bps 529 //CTS Rate : ?? Mega bps
523 //CTS frame length = 14 bytes 530 //CTS frame length = 14 bytes
524 if( pT01->T01_plcp_header_length ) //long preamble 531 if( pT01->T01_plcp_header_length ) //long preamble
525 Duration += LONG_PREAMBLE_PLUS_PLCPHEADER_TIME; 532 Duration += LONG_PREAMBLE_PLUS_PLCPHEADER_TIME;
526 else 533 else
527 Duration += SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME; 534 Duration += SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME;
528 535
529 Duration += ( ((112 + Rate-1) / Rate) + DEFAULT_SIFSTIME ); 536 Duration += ( ((112 + Rate-1) / Rate) + DEFAULT_SIFSTIME );
530 } 537 }
531 } 538 }
532 539
533 // Set the value into USB descriptor 540 // Set the value into USB descriptor
534 pT01->T01_add_rts = RTS_on ? 1 : 0; 541 pT01->T01_add_rts = RTS_on ? 1 : 0;
535 pT01->T01_add_cts = CTS_on ? 1 : 0; 542 pT01->T01_add_cts = CTS_on ? 1 : 0;
536 pT01->T01_rts_cts_duration = Duration; 543 pT01->T01_rts_cts_duration = Duration;
537 } 544 }
538 545
539 //===================================== 546 //=====================================
540 // Fill the more fragment descriptor 547 // Fill the more fragment descriptor
541 //===================================== 548 //=====================================
542 if( boGroupAddr ) 549 if( boGroupAddr )
543 Duration = 0; 550 Duration = 0;
544 else 551 else
545 { 552 {
546 for( i=pDes->FragmentCount-1; i>0; i-- ) 553 for( i=pDes->FragmentCount-1; i>0; i-- )
547 { 554 {
548 NextBodyLen = (u16)pNextT00->T00_frame_length; 555 NextBodyLen = (u16)pNextT00->T00_frame_length;
549 NextBodyLen += 4; //CRC 556 NextBodyLen += 4; //CRC
550 557
551 if( pT01->T01_modulation_type ) 558 if( pT01->T01_modulation_type )
552 { 559 {
553 //OFDM 560 //OFDM
554 // data transmit time + 3 SIFS + 2 ACK 561 // data transmit time + 3 SIFS + 2 ACK
555 // Rate : ??Mega bps 562 // Rate : ??Mega bps
556 // ACK frame length = 14 bytes, tx rate = 24M 563 // ACK frame length = 14 bytes, tx rate = 24M
557 Duration = PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION * 3; 564 Duration = PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION * 3;
558 Duration += (((NextBodyLen*8 + 22 + Rate*4 - 1)/(Rate*4)) * Tsym + 565 Duration += (((NextBodyLen*8 + 22 + Rate*4 - 1)/(Rate*4)) * Tsym +
559 (((2*14)*8 + 22 + 95)/96)*Tsym + 566 (((2*14)*8 + 22 + 95)/96)*Tsym +
560 DEFAULT_SIFSTIME*3); 567 DEFAULT_SIFSTIME*3);
561 } 568 }
562 else 569 else
563 { 570 {
564 //DSSS 571 //DSSS
565 // data transmit time + 2 ACK + 3 SIFS 572 // data transmit time + 2 ACK + 3 SIFS
566 // Rate : ??Mega bps 573 // Rate : ??Mega bps
567 // ACK frame length = 14 bytes 574 // ACK frame length = 14 bytes
568 //TODO : 575 //TODO :
569 if( pT01->T01_plcp_header_length ) //long preamble 576 if( pT01->T01_plcp_header_length ) //long preamble
570 Duration = LONG_PREAMBLE_PLUS_PLCPHEADER_TIME*3; 577 Duration = LONG_PREAMBLE_PLUS_PLCPHEADER_TIME*3;
571 else 578 else
572 Duration = SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME*3; 579 Duration = SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME*3;
573 580
574 Duration += ( ((NextBodyLen + (2*14))*8 + Rate-1) / Rate + 581 Duration += ( ((NextBodyLen + (2*14))*8 + Rate-1) / Rate +
575 DEFAULT_SIFSTIME*3 ); 582 DEFAULT_SIFSTIME*3 );
576 } 583 }
577 584
578 ((u16 *)buffer)[5] = cpu_to_le16(Duration);// 4 USHOR for skip 8B USB, 2USHORT=FC + Duration 585 ((u16 *)buffer)[5] = cpu_to_le16(Duration);// 4 USHOR for skip 8B USB, 2USHORT=FC + Duration
579 586
580 //----20061009 add by anson's endian 587 //----20061009 add by anson's endian
581 pNextT00->value = cpu_to_le32(pNextT00->value); 588 pNextT00->value = cpu_to_le32(pNextT00->value);
582 pT01->value = cpu_to_le32( pT01->value ); 589 pT01->value = cpu_to_le32( pT01->value );
583 //----end 20061009 add by anson's endian 590 //----end 20061009 add by anson's endian
584 591
585 buffer += OffsetSize; 592 buffer += OffsetSize;
586 pT01 = (PT01_DESCRIPTOR)(buffer+4); 593 pT01 = (PT01_DESCRIPTOR)(buffer+4);
587 if (i != 1) //The last fragment will not have the next fragment 594 if (i != 1) //The last fragment will not have the next fragment
588 pNextT00 = (PT00_DESCRIPTOR)(buffer+OffsetSize); 595 pNextT00 = (PT00_DESCRIPTOR)(buffer+OffsetSize);
589 } 596 }
590 597
591 //===================================== 598 //=====================================
592 // Fill the last fragment descriptor 599 // Fill the last fragment descriptor
593 //===================================== 600 //=====================================
594 if( pT01->T01_modulation_type ) 601 if( pT01->T01_modulation_type )
595 { 602 {
596 //OFDM 603 //OFDM
597 // 1 SIFS + 1 ACK 604 // 1 SIFS + 1 ACK
598 // Rate : 24 Mega bps 605 // Rate : 24 Mega bps
599 // ACK frame length = 14 bytes 606 // ACK frame length = 14 bytes
600 Duration = PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION; 607 Duration = PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION;
601 //The Tx rate of ACK use 24M 608 //The Tx rate of ACK use 24M
602 Duration += (((112 + 22 + 95)/96)*Tsym + DEFAULT_SIFSTIME ); 609 Duration += (((112 + 22 + 95)/96)*Tsym + DEFAULT_SIFSTIME );
603 } 610 }
604 else 611 else
605 { 612 {
606 // DSSS 613 // DSSS
607 // 1 ACK + 1 SIFS 614 // 1 ACK + 1 SIFS
608 // Rate : ?? Mega bps 615 // Rate : ?? Mega bps
609 // ACK frame length = 14 bytes(112 bits) 616 // ACK frame length = 14 bytes(112 bits)
610 if( pT01->T01_plcp_header_length ) //long preamble 617 if( pT01->T01_plcp_header_length ) //long preamble
611 Duration = LONG_PREAMBLE_PLUS_PLCPHEADER_TIME; 618 Duration = LONG_PREAMBLE_PLUS_PLCPHEADER_TIME;
612 else 619 else
613 Duration = SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME; 620 Duration = SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME;
614 621
615 Duration += ( (112 + Rate-1)/Rate + DEFAULT_SIFSTIME ); 622 Duration += ( (112 + Rate-1)/Rate + DEFAULT_SIFSTIME );
616 } 623 }
617 } 624 }
618 625
619 ((u16 *)buffer)[5] = cpu_to_le16(Duration);// 4 USHOR for skip 8B USB, 2USHORT=FC + Duration 626 ((u16 *)buffer)[5] = cpu_to_le16(Duration);// 4 USHOR for skip 8B USB, 2USHORT=FC + Duration
620 pT00->value = cpu_to_le32(pT00->value); 627 pT00->value = cpu_to_le32(pT00->value);
621 pT01->value = cpu_to_le32(pT01->value); 628 pT01->value = cpu_to_le32(pT01->value);
622 //--end 20061009 add 629 //--end 20061009 add
623 630
624 } 631 }
625 632
626 void MDS_EthernetPacketReceive( struct wb35_adapter * adapter, PRXLAYER1 pRxLayer1 ) 633 void MDS_EthernetPacketReceive( struct wb35_adapter * adapter, PRXLAYER1 pRxLayer1 )
627 { 634 {
628 OS_RECEIVE_PACKET_INDICATE( adapter, pRxLayer1 ); 635 OS_RECEIVE_PACKET_INDICATE( adapter, pRxLayer1 );
629 } 636 }
630 637
631 638
632 639
drivers/staging/winbond/mds_f.h
Diff comments   View file @ 80aba53
1 #ifndef __WINBOND_MDS_F_H
2 #define __WINBOND_MDS_F_H
3
4 #include "wbhal_s.h"
5 #include "adapter.h"
6
1 unsigned char Mds_initial( struct wb35_adapter *adapter ); 7 unsigned char Mds_initial( struct wb35_adapter *adapter );
2 void Mds_Destroy( struct wb35_adapter *adapter ); 8 void Mds_Destroy( struct wb35_adapter *adapter );
3 void Mds_Tx( struct wb35_adapter *adapter ); 9 void Mds_Tx( struct wb35_adapter *adapter );
4 void Mds_HeaderCopy( struct wb35_adapter *adapter, PDESCRIPTOR pDes, u8 *TargetBuffer ); 10 void Mds_HeaderCopy( struct wb35_adapter *adapter, PDESCRIPTOR pDes, u8 *TargetBuffer );
5 u16 Mds_BodyCopy( struct wb35_adapter *adapter, PDESCRIPTOR pDes, u8 *TargetBuffer ); 11 u16 Mds_BodyCopy( struct wb35_adapter *adapter, PDESCRIPTOR pDes, u8 *TargetBuffer );
6 void Mds_DurationSet( struct wb35_adapter *adapter, PDESCRIPTOR pDes, u8 *TargetBuffer ); 12 void Mds_DurationSet( struct wb35_adapter *adapter, PDESCRIPTOR pDes, u8 *TargetBuffer );
7 void Mds_SendComplete( struct wb35_adapter *adapter, PT02_DESCRIPTOR pT02 ); 13 void Mds_SendComplete( struct wb35_adapter *adapter, PT02_DESCRIPTOR pT02 );
8 void Mds_MpduProcess( struct wb35_adapter *adapter, PDESCRIPTOR pRxDes ); 14 void Mds_MpduProcess( struct wb35_adapter *adapter, PDESCRIPTOR pRxDes );
9 void Mds_reset_descriptor( struct wb35_adapter *adapter ); 15 void Mds_reset_descriptor( struct wb35_adapter *adapter );
10 extern void DataDmp(u8 *pdata, u32 len, u32 offset); 16 extern void DataDmp(u8 *pdata, u32 len, u32 offset);
11 17
12 18
13 void vRxTimerInit(struct wb35_adapter *adapter); 19 void vRxTimerInit(struct wb35_adapter *adapter);
14 void vRxTimerStart(struct wb35_adapter *adapter, int timeout_value); 20 void vRxTimerStart(struct wb35_adapter *adapter, int timeout_value);
15 void vRxTimerStop(struct wb35_adapter *adapter); 21 void vRxTimerStop(struct wb35_adapter *adapter);
16 22
17 // For Asynchronous indicating. The routine collocates with USB. 23 // For Asynchronous indicating. The routine collocates with USB.
18 void Mds_MsduProcess( struct wb35_adapter *adapter, PRXLAYER1 pRxLayer1, u8 SlotIndex); 24 void Mds_MsduProcess( struct wb35_adapter *adapter, PRXLAYER1 pRxLayer1, u8 SlotIndex);
19 25
20 // For data frame sending 20060802 26 // For data frame sending 20060802
21 u16 MDS_GetPacketSize( struct wb35_adapter *adapter ); 27 u16 MDS_GetPacketSize( struct wb35_adapter *adapter );
22 void MDS_GetNextPacket( struct wb35_adapter *adapter, PDESCRIPTOR pDes ); 28 void MDS_GetNextPacket( struct wb35_adapter *adapter, PDESCRIPTOR pDes );
23 void MDS_GetNextPacketComplete( struct wb35_adapter *adapter, PDESCRIPTOR pDes ); 29 void MDS_GetNextPacketComplete( struct wb35_adapter *adapter, PDESCRIPTOR pDes );
24 void MDS_SendResult( struct wb35_adapter *adapter, u8 PacketId, unsigned char SendOK ); 30 void MDS_SendResult( struct wb35_adapter *adapter, u8 PacketId, unsigned char SendOK );
25 void MDS_EthernetPacketReceive( struct wb35_adapter *adapter, PRXLAYER1 pRxLayer1 ); 31 void MDS_EthernetPacketReceive( struct wb35_adapter *adapter, PRXLAYER1 pRxLayer1 );
32
33 #endif
26 34
drivers/staging/winbond/mds_s.h
Diff comments   View file @ 80aba53
1 #ifndef __WINBOND_MDS_H
2 #define __WINBOND_MDS_H
3
4 #include <linux/timer.h>
5 #include <linux/types.h>
6 #include <asm/atomic.h>
7
8 #include "localpara.h"
9 #include "mac_structures.h"
10 #include "scan_s.h"
11
1 //////////////////////////////////////////////////////////////////////////////////////////////////////// 12 ////////////////////////////////////////////////////////////////////////////////////////////////////////
2 #define MAX_USB_TX_DESCRIPTOR 15 // IS89C35 ability 13 #define MAX_USB_TX_DESCRIPTOR 15 // IS89C35 ability
3 #define MAX_USB_TX_BUFFER_NUMBER 4 // Virtual pre-buffer number of MAX_USB_TX_BUFFER 14 #define MAX_USB_TX_BUFFER_NUMBER 4 // Virtual pre-buffer number of MAX_USB_TX_BUFFER
4 #define MAX_USB_TX_BUFFER 4096 // IS89C35 ability 4n alignment is required for hardware 15 #define MAX_USB_TX_BUFFER 4096 // IS89C35 ability 4n alignment is required for hardware
5 16
6 #define MDS_EVENT_INDICATE( _A, _B, _F ) OS_EVENT_INDICATE( _A, _B, _F ) 17 #define MDS_EVENT_INDICATE( _A, _B, _F ) OS_EVENT_INDICATE( _A, _B, _F )
7 #define AUTH_REQUEST_PAIRWISE_ERROR 0 // _F flag setting 18 #define AUTH_REQUEST_PAIRWISE_ERROR 0 // _F flag setting
8 #define AUTH_REQUEST_GROUP_ERROR 1 // _F flag setting 19 #define AUTH_REQUEST_GROUP_ERROR 1 // _F flag setting
9 20
10 // For variable setting 21 // For variable setting
11 #define CURRENT_BSS_TYPE psBSS(psLOCAL->wConnectedSTAindex)->bBssType 22 #define CURRENT_BSS_TYPE psBSS(psLOCAL->wConnectedSTAindex)->bBssType
12 #define CURRENT_WEP_MODE psSME->_dot11PrivacyInvoked 23 #define CURRENT_WEP_MODE psSME->_dot11PrivacyInvoked
13 #define CURRENT_BSSID psBSS(psLOCAL->wConnectedSTAindex)->abBssID 24 #define CURRENT_BSSID psBSS(psLOCAL->wConnectedSTAindex)->abBssID
14 #define CURRENT_DESIRED_WPA_ENABLE ((psSME->bDesiredAuthMode==WPA_AUTH)||(psSME->bDesiredAuthMode==WPAPSK_AUTH)) 25 #define CURRENT_DESIRED_WPA_ENABLE ((psSME->bDesiredAuthMode==WPA_AUTH)||(psSME->bDesiredAuthMode==WPAPSK_AUTH))
15 #ifdef _WPA2_ 26 #ifdef _WPA2_
16 #define CURRENT_DESIRED_WPA2_ENABLE ((psSME->bDesiredAuthMode==WPA2_AUTH)||(psSME->bDesiredAuthMode==WPA2PSK_AUTH)) 27 #define CURRENT_DESIRED_WPA2_ENABLE ((psSME->bDesiredAuthMode==WPA2_AUTH)||(psSME->bDesiredAuthMode==WPA2PSK_AUTH))
17 #endif //end def _WPA2_ 28 #endif //end def _WPA2_
18 #define CURRENT_PAIRWISE_KEY_OK psSME->pairwise_key_ok 29 #define CURRENT_PAIRWISE_KEY_OK psSME->pairwise_key_ok
19 //[20040712 WS] 30 //[20040712 WS]
20 #define CURRENT_GROUP_KEY_OK psSME->group_key_ok 31 #define CURRENT_GROUP_KEY_OK psSME->group_key_ok
21 #define CURRENT_PAIRWISE_KEY psSME->tx_mic_key 32 #define CURRENT_PAIRWISE_KEY psSME->tx_mic_key
22 #define CURRENT_GROUP_KEY psSME->group_tx_mic_key 33 #define CURRENT_GROUP_KEY psSME->group_tx_mic_key
23 #define CURRENT_ENCRYPT_STATUS psSME->encrypt_status 34 #define CURRENT_ENCRYPT_STATUS psSME->encrypt_status
24 #define CURRENT_WEP_ID adapter->sSmePara._dot11WEPDefaultKeyID 35 #define CURRENT_WEP_ID adapter->sSmePara._dot11WEPDefaultKeyID
25 #define CURRENT_CONTROL_PORT_BLOCK ( psSME->wpa_ok!=1 || (adapter->Mds.boCounterMeasureBlock==1 && (CURRENT_ENCRYPT_STATUS==ENCRYPT_TKIP)) ) 36 #define CURRENT_CONTROL_PORT_BLOCK ( psSME->wpa_ok!=1 || (adapter->Mds.boCounterMeasureBlock==1 && (CURRENT_ENCRYPT_STATUS==ENCRYPT_TKIP)) )
26 #define CURRENT_FRAGMENT_THRESHOLD (adapter->Mds.TxFragmentThreshold & ~0x1) 37 #define CURRENT_FRAGMENT_THRESHOLD (adapter->Mds.TxFragmentThreshold & ~0x1)
27 #define CURRENT_PREAMBLE_MODE psLOCAL->boShortPreamble?WLAN_PREAMBLE_TYPE_SHORT:WLAN_PREAMBLE_TYPE_LONG 38 #define CURRENT_PREAMBLE_MODE psLOCAL->boShortPreamble?WLAN_PREAMBLE_TYPE_SHORT:WLAN_PREAMBLE_TYPE_LONG
28 #define CURRENT_TX_RATE adapter->sLocalPara.CurrentTxRate 39 #define CURRENT_TX_RATE adapter->sLocalPara.CurrentTxRate
29 #define CURRENT_FALL_BACK_TX_RATE adapter->sLocalPara.CurrentTxFallbackRate 40 #define CURRENT_FALL_BACK_TX_RATE adapter->sLocalPara.CurrentTxFallbackRate
30 #define CURRENT_TX_RATE_FOR_MNG adapter->sLocalPara.CurrentTxRateForMng 41 #define CURRENT_TX_RATE_FOR_MNG adapter->sLocalPara.CurrentTxRateForMng
31 #define CURRENT_PROTECT_MECHANISM psLOCAL->boProtectMechanism 42 #define CURRENT_PROTECT_MECHANISM psLOCAL->boProtectMechanism
32 #define CURRENT_RTS_THRESHOLD adapter->Mds.TxRTSThreshold 43 #define CURRENT_RTS_THRESHOLD adapter->Mds.TxRTSThreshold
33 44
34 #define MIB_GS_XMIT_OK_INC adapter->sLocalPara.GS_XMIT_OK++ 45 #define MIB_GS_XMIT_OK_INC adapter->sLocalPara.GS_XMIT_OK++
35 #define MIB_GS_RCV_OK_INC adapter->sLocalPara.GS_RCV_OK++ 46 #define MIB_GS_RCV_OK_INC adapter->sLocalPara.GS_RCV_OK++
36 #define MIB_GS_XMIT_ERROR_INC adapter->sLocalPara.GS_XMIT_ERROR 47 #define MIB_GS_XMIT_ERROR_INC adapter->sLocalPara.GS_XMIT_ERROR
37 48
38 //---------- TX ----------------------------------- 49 //---------- TX -----------------------------------
39 #define ETHERNET_TX_DESCRIPTORS MAX_USB_TX_BUFFER_NUMBER 50 #define ETHERNET_TX_DESCRIPTORS MAX_USB_TX_BUFFER_NUMBER
40 51
41 //---------- RX ------------------------------------ 52 //---------- RX ------------------------------------
42 #define ETHERNET_RX_DESCRIPTORS 8 //It's not necessary to allocate more than 2 in sync indicate 53 #define ETHERNET_RX_DESCRIPTORS 8 //It's not necessary to allocate more than 2 in sync indicate
43 54
44 //================================================================ 55 //================================================================
45 // Configration default value 56 // Configration default value
46 //================================================================ 57 //================================================================
47 #define DEFAULT_MULTICASTLISTMAX 32 // standard 58 #define DEFAULT_MULTICASTLISTMAX 32 // standard
48 #define DEFAULT_TX_BURSTLENGTH 3 // 32 Longwords 59 #define DEFAULT_TX_BURSTLENGTH 3 // 32 Longwords
49 #define DEFAULT_RX_BURSTLENGTH 3 // 32 Longwords 60 #define DEFAULT_RX_BURSTLENGTH 3 // 32 Longwords
50 #define DEFAULT_TX_THRESHOLD 0 // Full Packet 61 #define DEFAULT_TX_THRESHOLD 0 // Full Packet
51 #define DEFAULT_RX_THRESHOLD 0 // Full Packet 62 #define DEFAULT_RX_THRESHOLD 0 // Full Packet
52 #define DEFAULT_MAXTXRATE 6 // 11 Mbps (Long) 63 #define DEFAULT_MAXTXRATE 6 // 11 Mbps (Long)
53 #define DEFAULT_CHANNEL 3 // Chennel 3 64 #define DEFAULT_CHANNEL 3 // Chennel 3
54 #define DEFAULT_RTSThreshold 2347 // Disable RTS 65 #define DEFAULT_RTSThreshold 2347 // Disable RTS
55 //#define DEFAULT_PME 1 // Enable 66 //#define DEFAULT_PME 1 // Enable
56 #define DEFAULT_PME 0 // Disable 67 #define DEFAULT_PME 0 // Disable
57 #define DEFAULT_SIFSTIME 10 68 #define DEFAULT_SIFSTIME 10
58 #define DEFAULT_ACKTIME_1ML 304 // 148+44+112 911220 by LCC 69 #define DEFAULT_ACKTIME_1ML 304 // 148+44+112 911220 by LCC
59 #define DEFAULT_ACKTIME_2ML 248 // 148+44+56 911220 by LCC 70 #define DEFAULT_ACKTIME_2ML 248 // 148+44+56 911220 by LCC
60 #define DEFAULT_FRAGMENT_THRESHOLD 2346 // No fragment 71 #define DEFAULT_FRAGMENT_THRESHOLD 2346 // No fragment
61 #define DEFAULT_PREAMBLE_LENGTH 72 72 #define DEFAULT_PREAMBLE_LENGTH 72
62 #define DEFAULT_PLCPHEADERTIME_LENGTH 24 73 #define DEFAULT_PLCPHEADERTIME_LENGTH 24
63 74
64 /*------------------------------------------------------------------------ 75 /*------------------------------------------------------------------------
65 0.96 sec since time unit of the R03 for the current, W89C32 is about 60ns 76 0.96 sec since time unit of the R03 for the current, W89C32 is about 60ns
66 instead of 960 ns. This shall be fixed in the future W89C32 77 instead of 960 ns. This shall be fixed in the future W89C32
67 -------------------------------------------------------------------------*/ 78 -------------------------------------------------------------------------*/
68 #define DEFAULT_MAX_RECEIVE_TIME 16440000 79 #define DEFAULT_MAX_RECEIVE_TIME 16440000
69 80
70 #define RX_BUF_SIZE 2352 // 600 // For 301 must be multiple of 8 81 #define RX_BUF_SIZE 2352 // 600 // For 301 must be multiple of 8
71 #define MAX_RX_DESCRIPTORS 18 // Rx Layer 2 82 #define MAX_RX_DESCRIPTORS 18 // Rx Layer 2
72 #define MAX_BUFFER_QUEUE 8 // The value is always equal 8 due to NDIS_PACKET's MiniportReserved field size 83 #define MAX_BUFFER_QUEUE 8 // The value is always equal 8 due to NDIS_PACKET's MiniportReserved field size
73 84
74 85
75 // For brand-new rx system 86 // For brand-new rx system
76 #define MDS_ID_IGNORE ETHERNET_RX_DESCRIPTORS 87 #define MDS_ID_IGNORE ETHERNET_RX_DESCRIPTORS
77 88
78 // For Tx Packet status classify 89 // For Tx Packet status classify
79 #define PACKET_FREE_TO_USE 0 90 #define PACKET_FREE_TO_USE 0
80 #define PACKET_COME_FROM_NDIS 0x08 91 #define PACKET_COME_FROM_NDIS 0x08
81 #define PACKET_COME_FROM_MLME 0x80 92 #define PACKET_COME_FROM_MLME 0x80
82 #define PACKET_SEND_COMPLETE 0xff 93 #define PACKET_SEND_COMPLETE 0xff
83 94
84 typedef struct _MDS 95 typedef struct _MDS
85 { 96 {
86 // For Tx usage 97 // For Tx usage
87 u8 TxOwner[ ((MAX_USB_TX_BUFFER_NUMBER + 3) & ~0x03) ]; 98 u8 TxOwner[ ((MAX_USB_TX_BUFFER_NUMBER + 3) & ~0x03) ];
88 u8 *pTxBuffer; 99 u8 *pTxBuffer;
89 u16 TxBufferSize[ ((MAX_USB_TX_BUFFER_NUMBER + 1) & ~0x01) ]; 100 u16 TxBufferSize[ ((MAX_USB_TX_BUFFER_NUMBER + 1) & ~0x01) ];
90 u8 TxDesFrom[ ((MAX_USB_TX_DESCRIPTOR + 3) & ~0x03) ];//931130.4.u // 1: MLME 2: NDIS control 3: NDIS data 101 u8 TxDesFrom[ ((MAX_USB_TX_DESCRIPTOR + 3) & ~0x03) ];//931130.4.u // 1: MLME 2: NDIS control 3: NDIS data
91 u8 TxCountInBuffer[ ((MAX_USB_TX_DESCRIPTOR + 3) & ~0x03) ]; // 20060928 102 u8 TxCountInBuffer[ ((MAX_USB_TX_DESCRIPTOR + 3) & ~0x03) ]; // 20060928
92 103
93 u8 TxFillIndex;//the next index of TxBuffer can be used 104 u8 TxFillIndex;//the next index of TxBuffer can be used
94 u8 TxDesIndex;//The next index of TxDes can be used 105 u8 TxDesIndex;//The next index of TxDes can be used
95 u8 ScanTxPause; //data Tx pause because the scanning is progressing, but probe request Tx won't. 106 u8 ScanTxPause; //data Tx pause because the scanning is progressing, but probe request Tx won't.
96 u8 TxPause;//For pause the Mds_Tx modult 107 u8 TxPause;//For pause the Mds_Tx modult
97 108
98 atomic_t TxThreadCount;//For thread counting 931130.4.v 109 atomic_t TxThreadCount;//For thread counting 931130.4.v
99 //950301 delete due to HW 110 //950301 delete due to HW
100 // atomic_t TxConcurrentCount;//931130.4.w 111 // atomic_t TxConcurrentCount;//931130.4.w
101 112
102 u16 TxResult[ ((MAX_USB_TX_DESCRIPTOR + 1) & ~0x01) ];//Collect the sending result of Mpdu 113 u16 TxResult[ ((MAX_USB_TX_DESCRIPTOR + 1) & ~0x01) ];//Collect the sending result of Mpdu
103 114
104 u8 MicRedundant[8]; // For tmp use 115 u8 MicRedundant[8]; // For tmp use
105 u8 *MicWriteAddress[2]; //The start address to fill the Mic, use 2 point due to Mic maybe fragment 116 u8 *MicWriteAddress[2]; //The start address to fill the Mic, use 2 point due to Mic maybe fragment
106 117
107 u16 MicWriteSize[2]; //931130.4.x 118 u16 MicWriteSize[2]; //931130.4.x
108 119
109 u16 MicAdd; // If want to add the Mic, this variable equal to 8 120 u16 MicAdd; // If want to add the Mic, this variable equal to 8
110 u16 MicWriteIndex;//The number of MicWriteAddress 931130.4.y 121 u16 MicWriteIndex;//The number of MicWriteAddress 931130.4.y
111 122
112 u8 TxRate[ ((MAX_USB_TX_DESCRIPTOR+1)&~0x01) ][2]; // [0] current tx rate, [1] fall back rate 123 u8 TxRate[ ((MAX_USB_TX_DESCRIPTOR+1)&~0x01) ][2]; // [0] current tx rate, [1] fall back rate
113 u8 TxInfo[ ((MAX_USB_TX_DESCRIPTOR+1)&~0x01) ]; //Store information for callback function 124 u8 TxInfo[ ((MAX_USB_TX_DESCRIPTOR+1)&~0x01) ]; //Store information for callback function
114 125
115 //WKCHEN added for scanning mechanism 126 //WKCHEN added for scanning mechanism
116 u8 TxToggle; //It is TRUE if there are tx activities in some time interval 127 u8 TxToggle; //It is TRUE if there are tx activities in some time interval
117 u8 Reserved_[3]; 128 u8 Reserved_[3];
118 129
119 //---------- for Tx Parameter 130 //---------- for Tx Parameter
120 u16 TxFragmentThreshold; // For frame body only 131 u16 TxFragmentThreshold; // For frame body only
121 u16 TxRTSThreshold; 132 u16 TxRTSThreshold;
122 133
123 u32 MaxReceiveTime;//911220.3 Add 134 u32 MaxReceiveTime;//911220.3 Add
124 135
125 // depend on OS, 136 // depend on OS,
126 u32 MulticastListNo; 137 u32 MulticastListNo;
127 u32 PacketFilter; // Setting by NDIS, the current packet filter in use. 138 u32 PacketFilter; // Setting by NDIS, the current packet filter in use.
128 u8 MulticastAddressesArray[DEFAULT_MULTICASTLISTMAX][MAC_ADDR_LENGTH]; 139 u8 MulticastAddressesArray[DEFAULT_MULTICASTLISTMAX][MAC_ADDR_LENGTH];
129 140
130 //COUNTERMEASURE 141 //COUNTERMEASURE
131 u8 bMICfailCount; 142 u8 bMICfailCount;
132 u8 boCounterMeasureBlock; 143 u8 boCounterMeasureBlock;
133 u8 reserved_4[2]; 144 u8 reserved_4[2];
134 145
135 struct timer_list timer; 146 struct timer_list timer;
136 147
137 u32 TxTsc; // 20060214 148 u32 TxTsc; // 20060214
138 u32 TxTsc_2; // 20060214 149 u32 TxTsc_2; // 20060214
139 150
140 } MDS, *PMDS; 151 } MDS, *PMDS;
141 152
142 153
143 typedef struct _RxBuffer 154 typedef struct _RxBuffer
144 { 155 {
145 u8 * pBufferAddress; // Pointer the received data buffer. 156 u8 * pBufferAddress; // Pointer the received data buffer.
146 u16 BufferSize; 157 u16 BufferSize;
147 u8 RESERVED; 158 u8 RESERVED;
148 u8 BufferIndex;// Only 1 byte 159 u8 BufferIndex;// Only 1 byte
149 } RXBUFFER, *PRXBUFFER; 160 } RXBUFFER, *PRXBUFFER;
150 161
151 // 162 //
152 // Reveive Layer 1 Format. 163 // Reveive Layer 1 Format.
153 //---------------------------- 164 //----------------------------
154 typedef struct _RXLAYER1 165 typedef struct _RXLAYER1
155 { 166 {
156 u16 SequenceNumber; // The sequence number of the last received packet. 167 u16 SequenceNumber; // The sequence number of the last received packet.
157 u16 BufferTotalSize; 168 u16 BufferTotalSize;
158 169
159 u32 InUsed; 170 u32 InUsed;
160 u32 DecryptionMethod; // The desired defragment number of the next incoming packet. 171 u32 DecryptionMethod; // The desired defragment number of the next incoming packet.
161 172
162 u8 DeFragmentNumber; 173 u8 DeFragmentNumber;
163 u8 FrameType; 174 u8 FrameType;
164 u8 TypeEncapsulated; 175 u8 TypeEncapsulated;
165 u8 BufferNumber; 176 u8 BufferNumber;
166 177
167 u32 FirstFrameArrivedTime; 178 u32 FirstFrameArrivedTime;
168 179
169 RXBUFFER BufferQueue[ MAX_BUFFER_QUEUE ]; 180 RXBUFFER BufferQueue[ MAX_BUFFER_QUEUE ];
170 181
171 u8 LastFrameType; // 20061004 for fix intel 3945 's bug 182 u8 LastFrameType; // 20061004 for fix intel 3945 's bug
172 u8 RESERVED[3]; //@@ anson 183 u8 RESERVED[3]; //@@ anson
173 184
174 ///////////////////////////////////////////////////////////////////////////////////////////// 185 /////////////////////////////////////////////////////////////////////////////////////////////
175 // For brand-new Rx system 186 // For brand-new Rx system
176 u8 ReservedBuffer[ 2400 ];//If Buffer ID is reserved one, it must copy the data into this area 187 u8 ReservedBuffer[ 2400 ];//If Buffer ID is reserved one, it must copy the data into this area
177 u8 *ReservedBufferPoint;// Point to the next availabe address of reserved buffer 188 u8 *ReservedBufferPoint;// Point to the next availabe address of reserved buffer
178 189
179 }RXLAYER1, * PRXLAYER1; 190 }RXLAYER1, * PRXLAYER1;
191
192 #endif
180 193
drivers/staging/winbond/mlme_s.h
Diff comments   View file @ 80aba53
1 #ifndef __WINBOND_MLME_H
2 #define __WINBOND_MLME_H
3
4 #include <linux/types.h>
5 #include <linux/spinlock.h>
6
7 #include "mac_structures.h"
8 #include "mds_s.h"
9
1 //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 10 //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2 // Mlme.h 11 // Mlme.h
3 // Define the related definitions of MLME module 12 // Define the related definitions of MLME module
4 // history -- 01/14/03' created 13 // history -- 01/14/03' created
5 // 14 //
6 //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 15 //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
7 16
8 #define AUTH_REJECT_REASON_CHALLENGE_FAIL 1 17 #define AUTH_REJECT_REASON_CHALLENGE_FAIL 1
9 18
10 //====== the state of MLME module 19 //====== the state of MLME module
11 #define INACTIVE 0x0 20 #define INACTIVE 0x0
12 #define IDLE_SCAN 0x1 21 #define IDLE_SCAN 0x1
13 22
14 //====== the state of MLME/ESS module 23 //====== the state of MLME/ESS module
15 #define STATE_1 0x2 24 #define STATE_1 0x2
16 #define AUTH_REQ 0x3 25 #define AUTH_REQ 0x3
17 #define AUTH_WEP 0x4 26 #define AUTH_WEP 0x4
18 #define STATE_2 0x5 27 #define STATE_2 0x5
19 #define ASSOC_REQ 0x6 28 #define ASSOC_REQ 0x6
20 #define STATE_3 0x7 29 #define STATE_3 0x7
21 30
22 //====== the state of MLME/IBSS module 31 //====== the state of MLME/IBSS module
23 #define IBSS_JOIN_SYNC 0x8 32 #define IBSS_JOIN_SYNC 0x8
24 #define IBSS_AUTH_REQ 0x9 33 #define IBSS_AUTH_REQ 0x9
25 #define IBSS_AUTH_CHANLGE 0xa 34 #define IBSS_AUTH_CHANLGE 0xa
26 #define IBSS_AUTH_WEP 0xb 35 #define IBSS_AUTH_WEP 0xb
27 #define IBSS_AUTH_IND 0xc 36 #define IBSS_AUTH_IND 0xc
28 #define IBSS_STATE_2 0xd 37 #define IBSS_STATE_2 0xd
29 38
30 39
31 40
32 //========================================= 41 //=========================================
33 //depend on D5C(MAC timing control 03 register): MaxTxMSDULifeTime default 0x80000us 42 //depend on D5C(MAC timing control 03 register): MaxTxMSDULifeTime default 0x80000us
34 #define AUTH_FAIL_TIMEOUT 550 43 #define AUTH_FAIL_TIMEOUT 550
35 #define ASSOC_FAIL_TIMEOUT 550 44 #define ASSOC_FAIL_TIMEOUT 550
36 #define REASSOC_FAIL_TIMEOUT 550 45 #define REASSOC_FAIL_TIMEOUT 550
37 46
38 47
39 48
40 // 49 //
41 // MLME task global CONSTANTS, STRUCTURE, variables 50 // MLME task global CONSTANTS, STRUCTURE, variables
42 // 51 //
43 52
44 53
45 ///////////////////////////////////////////////////////////// 54 /////////////////////////////////////////////////////////////
46 // enum_ResultCode -- 55 // enum_ResultCode --
47 // Result code returned from MLME to SME. 56 // Result code returned from MLME to SME.
48 // 57 //
49 ///////////////////////////////////////////////////////////// 58 /////////////////////////////////////////////////////////////
50 // PD43 20030829 Modifiled 59 // PD43 20030829 Modifiled
51 //#define SUCCESS 0 60 //#define SUCCESS 0
52 #define MLME_SUCCESS 0 //follow spec. 61 #define MLME_SUCCESS 0 //follow spec.
53 #define INVALID_PARAMETERS 1 //Not following spec. 62 #define INVALID_PARAMETERS 1 //Not following spec.
54 #define NOT_SUPPPORTED 2 63 #define NOT_SUPPPORTED 2
55 #define TIMEOUT 3 64 #define TIMEOUT 3
56 #define TOO_MANY_SIMULTANEOUS_REQUESTS 4 65 #define TOO_MANY_SIMULTANEOUS_REQUESTS 4
57 #define REFUSED 5 66 #define REFUSED 5
58 #define BSS_ALREADY_STARTED_OR_JOINED 6 67 #define BSS_ALREADY_STARTED_OR_JOINED 6
59 #define TRANSMIT_FRAME_FAIL 7 68 #define TRANSMIT_FRAME_FAIL 7
60 #define NO_BSS_FOUND 8 69 #define NO_BSS_FOUND 8
61 #define RETRY 9 70 #define RETRY 9
62 #define GIVE_UP 10 71 #define GIVE_UP 10
63 72
64 73
65 #define OPEN_AUTH 0 74 #define OPEN_AUTH 0
66 #define SHARE_AUTH 1 75 #define SHARE_AUTH 1
67 #define ANY_AUTH 2 76 #define ANY_AUTH 2
68 #define WPA_AUTH 3 //for WPA 77 #define WPA_AUTH 3 //for WPA
69 #define WPAPSK_AUTH 4 78 #define WPAPSK_AUTH 4
70 #define WPANONE_AUTH 5 79 #define WPANONE_AUTH 5
71 ///////////////////////////////////////////// added by ws 04/19/04 80 ///////////////////////////////////////////// added by ws 04/19/04
72 #ifdef _WPA2_ 81 #ifdef _WPA2_
73 #define WPA2_AUTH 6//for WPA2 82 #define WPA2_AUTH 6//for WPA2
74 #define WPA2PSK_AUTH 7 83 #define WPA2PSK_AUTH 7
75 #endif //end def _WPA2_ 84 #endif //end def _WPA2_
76 85
77 ////////////////////////////////////////////////////////////////// 86 //////////////////////////////////////////////////////////////////
78 //define the msg type of MLME module 87 //define the msg type of MLME module
79 ////////////////////////////////////////////////////////////////// 88 //////////////////////////////////////////////////////////////////
80 //-------------------------------------------------------- 89 //--------------------------------------------------------
81 //from SME 90 //from SME
82 91
83 #define MLMEMSG_AUTH_REQ 0x0b 92 #define MLMEMSG_AUTH_REQ 0x0b
84 #define MLMEMSG_DEAUTH_REQ 0x0c 93 #define MLMEMSG_DEAUTH_REQ 0x0c
85 #define MLMEMSG_ASSOC_REQ 0x0d 94 #define MLMEMSG_ASSOC_REQ 0x0d
86 #define MLMEMSG_REASSOC_REQ 0x0e 95 #define MLMEMSG_REASSOC_REQ 0x0e
87 #define MLMEMSG_DISASSOC_REQ 0x0f 96 #define MLMEMSG_DISASSOC_REQ 0x0f
88 #define MLMEMSG_START_IBSS_REQ 0x10 97 #define MLMEMSG_START_IBSS_REQ 0x10
89 #define MLMEMSG_IBSS_NET_CFM 0x11 98 #define MLMEMSG_IBSS_NET_CFM 0x11
90 99
91 //from RX : 100 //from RX :
92 #define MLMEMSG_RCV_MLMEFRAME 0x20 101 #define MLMEMSG_RCV_MLMEFRAME 0x20
93 #define MLMEMSG_RCV_ASSOCRSP 0x22 102 #define MLMEMSG_RCV_ASSOCRSP 0x22
94 #define MLMEMSG_RCV_REASSOCRSP 0x24 103 #define MLMEMSG_RCV_REASSOCRSP 0x24
95 #define MLMEMSG_RCV_DISASSOC 0x2b 104 #define MLMEMSG_RCV_DISASSOC 0x2b
96 #define MLMEMSG_RCV_AUTH 0x2c 105 #define MLMEMSG_RCV_AUTH 0x2c
97 #define MLMEMSG_RCV_DEAUTH 0x2d 106 #define MLMEMSG_RCV_DEAUTH 0x2d
98 107
99 108
100 //from TX callback 109 //from TX callback
101 #define MLMEMSG_TX_CALLBACK 0x40 110 #define MLMEMSG_TX_CALLBACK 0x40
102 #define MLMEMSG_ASSOCREQ_CALLBACK 0x41 111 #define MLMEMSG_ASSOCREQ_CALLBACK 0x41
103 #define MLMEMSG_REASSOCREQ_CALLBACK 0x43 112 #define MLMEMSG_REASSOCREQ_CALLBACK 0x43
104 #define MLMEMSG_DISASSOC_CALLBACK 0x4a 113 #define MLMEMSG_DISASSOC_CALLBACK 0x4a
105 #define MLMEMSG_AUTH_CALLBACK 0x4c 114 #define MLMEMSG_AUTH_CALLBACK 0x4c
106 #define MLMEMSG_DEAUTH_CALLBACK 0x4d 115 #define MLMEMSG_DEAUTH_CALLBACK 0x4d
107 116
108 //#define MLMEMSG_JOIN_FAIL 4 117 //#define MLMEMSG_JOIN_FAIL 4
109 //#define MLMEMSG_AUTHEN_FAIL 18 118 //#define MLMEMSG_AUTHEN_FAIL 18
110 #define MLMEMSG_TIMEOUT 0x50 119 #define MLMEMSG_TIMEOUT 0x50
111 120
112 /////////////////////////////////////////////////////////////////////////// 121 ///////////////////////////////////////////////////////////////////////////
113 //Global data structures 122 //Global data structures
114 #define MAX_NUM_TX_MMPDU 2 123 #define MAX_NUM_TX_MMPDU 2
115 #define MAX_MMPDU_SIZE 1512 124 #define MAX_MMPDU_SIZE 1512
116 #define MAX_NUM_RX_MMPDU 6 125 #define MAX_NUM_RX_MMPDU 6
117 126
118 127
119 /////////////////////////////////////////////////////////////////////////// 128 ///////////////////////////////////////////////////////////////////////////
120 //MACRO 129 //MACRO
121 #define boMLME_InactiveState(_AA_) (_AA_->wState==INACTIVE) 130 #define boMLME_InactiveState(_AA_) (_AA_->wState==INACTIVE)
122 #define boMLME_IdleScanState(_BB_) (_BB_->wState==IDLE_SCAN) 131 #define boMLME_IdleScanState(_BB_) (_BB_->wState==IDLE_SCAN)
123 #define boMLME_FoundSTAinfo(_CC_) (_CC_->wState>=IDLE_SCAN) 132 #define boMLME_FoundSTAinfo(_CC_) (_CC_->wState>=IDLE_SCAN)
124 133
125 typedef struct _MLME_FRAME 134 typedef struct _MLME_FRAME
126 { 135 {
127 //NDIS_PACKET MLME_Packet; 136 //NDIS_PACKET MLME_Packet;
128 s8 * pMMPDU; 137 s8 * pMMPDU;
129 u16 len; 138 u16 len;
130 u8 DataType; 139 u8 DataType;
131 u8 IsInUsed; 140 u8 IsInUsed;
132 141
133 spinlock_t MLMESpinLock; 142 spinlock_t MLMESpinLock;
134 143
135 u8 TxMMPDU[MAX_NUM_TX_MMPDU][MAX_MMPDU_SIZE]; 144 u8 TxMMPDU[MAX_NUM_TX_MMPDU][MAX_MMPDU_SIZE];
136 u8 TxMMPDUInUse[ (MAX_NUM_TX_MMPDU+3) & ~0x03 ]; 145 u8 TxMMPDUInUse[ (MAX_NUM_TX_MMPDU+3) & ~0x03 ];
137 146
138 u16 wNumTxMMPDU; 147 u16 wNumTxMMPDU;
139 u16 wNumTxMMPDUDiscarded; 148 u16 wNumTxMMPDUDiscarded;
140 149
141 u8 RxMMPDU[MAX_NUM_RX_MMPDU][MAX_MMPDU_SIZE]; 150 u8 RxMMPDU[MAX_NUM_RX_MMPDU][MAX_MMPDU_SIZE];
142 u8 SaveRxBufSlotInUse[ (MAX_NUM_RX_MMPDU+3) & ~0x03 ]; 151 u8 SaveRxBufSlotInUse[ (MAX_NUM_RX_MMPDU+3) & ~0x03 ];
143 152
144 u16 wNumRxMMPDU; 153 u16 wNumRxMMPDU;
145 u16 wNumRxMMPDUDiscarded; 154 u16 wNumRxMMPDUDiscarded;
146 155
147 u16 wNumRxMMPDUInMLME; // Number of the Rx MMPDU 156 u16 wNumRxMMPDUInMLME; // Number of the Rx MMPDU
148 u16 reserved_1; // in MLME. 157 u16 reserved_1; // in MLME.
149 // excluding the discarded 158 // excluding the discarded
150 } MLME_FRAME, *psMLME_FRAME; 159 } MLME_FRAME, *psMLME_FRAME;
151 160
152 typedef struct _AUTHREQ { 161 typedef struct _AUTHREQ {
153 162
154 u8 peerMACaddr[MAC_ADDR_LENGTH]; 163 u8 peerMACaddr[MAC_ADDR_LENGTH];
155 u16 wAuthAlgorithm; 164 u16 wAuthAlgorithm;
156 165
157 } MLME_AUTHREQ_PARA, *psMLME_AUTHREQ_PARA; 166 } MLME_AUTHREQ_PARA, *psMLME_AUTHREQ_PARA;
158 167
159 struct _Reason_Code { 168 struct _Reason_Code {
160 169
161 u8 peerMACaddr[MAC_ADDR_LENGTH]; 170 u8 peerMACaddr[MAC_ADDR_LENGTH];
162 u16 wReasonCode; 171 u16 wReasonCode;
163 }; 172 };
164 typedef struct _Reason_Code MLME_DEAUTHREQ_PARA, *psMLME_DEAUTHREQ_PARA; 173 typedef struct _Reason_Code MLME_DEAUTHREQ_PARA, *psMLME_DEAUTHREQ_PARA;
165 typedef struct _Reason_Code MLME_DISASSOCREQ_PARA, *psMLME_DISASSOCREQ_PARA; 174 typedef struct _Reason_Code MLME_DISASSOCREQ_PARA, *psMLME_DISASSOCREQ_PARA;
166 175
167 typedef struct _ASSOCREQ { 176 typedef struct _ASSOCREQ {
168 u8 PeerSTAAddr[MAC_ADDR_LENGTH]; 177 u8 PeerSTAAddr[MAC_ADDR_LENGTH];
169 u16 CapabilityInfo; 178 u16 CapabilityInfo;
170 u16 ListenInterval; 179 u16 ListenInterval;
171 180
172 }__attribute__ ((packed)) MLME_ASSOCREQ_PARA, *psMLME_ASSOCREQ_PARA; 181 }__attribute__ ((packed)) MLME_ASSOCREQ_PARA, *psMLME_ASSOCREQ_PARA;
173 182
174 typedef struct _REASSOCREQ { 183 typedef struct _REASSOCREQ {
175 u8 NewAPAddr[MAC_ADDR_LENGTH]; 184 u8 NewAPAddr[MAC_ADDR_LENGTH];
176 u16 CapabilityInfo; 185 u16 CapabilityInfo;
177 u16 ListenInterval; 186 u16 ListenInterval;
178 187
179 }__attribute__ ((packed)) MLME_REASSOCREQ_PARA, *psMLME_REASSOCREQ_PARA; 188 }__attribute__ ((packed)) MLME_REASSOCREQ_PARA, *psMLME_REASSOCREQ_PARA;
180 189
181 typedef struct _MLMECALLBACK { 190 typedef struct _MLMECALLBACK {
182 191
183 u8 *psFramePtr; 192 u8 *psFramePtr;
184 u8 bResult; 193 u8 bResult;
185 194
186 } MLME_TXCALLBACK, *psMLME_TXCALLBACK; 195 } MLME_TXCALLBACK, *psMLME_TXCALLBACK;
187 196
188 typedef struct _RXDATA 197 typedef struct _RXDATA
189 { 198 {
190 s32 FrameLength; 199 s32 FrameLength;
191 u8 __attribute__ ((packed)) *pbFramePtr; 200 u8 __attribute__ ((packed)) *pbFramePtr;
192 201
193 }__attribute__ ((packed)) RXDATA, *psRXDATA; 202 }__attribute__ ((packed)) RXDATA, *psRXDATA;
203
204 #endif
194 205
drivers/staging/winbond/mlmetxrx.c
Diff comments   View file @ 80aba53
1 //============================================================================ 1 //============================================================================
2 // Module Name: 2 // Module Name:
3 // MLMETxRx.C 3 // MLMETxRx.C
4 // 4 //
5 // Description: 5 // Description:
6 // The interface between MDS (MAC Data Service) and MLME. 6 // The interface between MDS (MAC Data Service) and MLME.
7 // 7 //
8 // Revision History: 8 // Revision History:
9 // -------------------------------------------------------------------------- 9 // --------------------------------------------------------------------------
10 // 200209 UN20 Jennifer Xu 10 // 200209 UN20 Jennifer Xu
11 // Initial Release 11 // Initial Release
12 // 20021108 PD43 Austin Liu 12 // 20021108 PD43 Austin Liu
13 // 20030117 PD43 Austin Liu 13 // 20030117 PD43 Austin Liu
14 // Deleted MLMEReturnPacket and MLMEProcThread() 14 // Deleted MLMEReturnPacket and MLMEProcThread()
15 // 15 //
16 // Copyright (c) 1996-2002 Winbond Electronics Corp. All Rights Reserved. 16 // Copyright (c) 1996-2002 Winbond Electronics Corp. All Rights Reserved.
17 //============================================================================ 17 //============================================================================
18 #include "os_common.h" 18 #include "os_common.h"
19 19
20 #include "mds_f.h"
21
20 void MLMEResetTxRx(struct wb35_adapter * adapter) 22 void MLMEResetTxRx(struct wb35_adapter * adapter)
21 { 23 {
22 s32 i; 24 s32 i;
23 25
24 // Reset the interface between MDS and MLME 26 // Reset the interface between MDS and MLME
25 for (i = 0; i < MAX_NUM_TX_MMPDU; i++) 27 for (i = 0; i < MAX_NUM_TX_MMPDU; i++)
26 adapter->sMlmeFrame.TxMMPDUInUse[i] = false; 28 adapter->sMlmeFrame.TxMMPDUInUse[i] = false;
27 for (i = 0; i < MAX_NUM_RX_MMPDU; i++) 29 for (i = 0; i < MAX_NUM_RX_MMPDU; i++)
28 adapter->sMlmeFrame.SaveRxBufSlotInUse[i] = false; 30 adapter->sMlmeFrame.SaveRxBufSlotInUse[i] = false;
29 31
30 adapter->sMlmeFrame.wNumRxMMPDUInMLME = 0; 32 adapter->sMlmeFrame.wNumRxMMPDUInMLME = 0;
31 adapter->sMlmeFrame.wNumRxMMPDUDiscarded = 0; 33 adapter->sMlmeFrame.wNumRxMMPDUDiscarded = 0;
32 adapter->sMlmeFrame.wNumRxMMPDU = 0; 34 adapter->sMlmeFrame.wNumRxMMPDU = 0;
33 adapter->sMlmeFrame.wNumTxMMPDUDiscarded = 0; 35 adapter->sMlmeFrame.wNumTxMMPDUDiscarded = 0;
34 adapter->sMlmeFrame.wNumTxMMPDU = 0; 36 adapter->sMlmeFrame.wNumTxMMPDU = 0;
35 adapter->sLocalPara.boCCAbusy = false; 37 adapter->sLocalPara.boCCAbusy = false;
36 adapter->sLocalPara.iPowerSaveMode = PWR_ACTIVE; // Power active 38 adapter->sLocalPara.iPowerSaveMode = PWR_ACTIVE; // Power active
37 } 39 }
38 40
39 //============================================================================= 41 //=============================================================================
40 // Function: 42 // Function:
41 // MLMEGetMMPDUBuffer() 43 // MLMEGetMMPDUBuffer()
42 // 44 //
43 // Description: 45 // Description:
44 // Return the pointer to an available data buffer with 46 // Return the pointer to an available data buffer with
45 // the size MAX_MMPDU_SIZE for a MMPDU. 47 // the size MAX_MMPDU_SIZE for a MMPDU.
46 // 48 //
47 // Arguments: 49 // Arguments:
48 // adapter - pointer to the miniport adapter context. 50 // adapter - pointer to the miniport adapter context.
49 // 51 //
50 // Return value: 52 // Return value:
51 // NULL : No available data buffer available 53 // NULL : No available data buffer available
52 // Otherwise: Pointer to the data buffer 54 // Otherwise: Pointer to the data buffer
53 //============================================================================= 55 //=============================================================================
54 56
55 /* FIXME: Should this just be replaced with kmalloc() and kfree()? */ 57 /* FIXME: Should this just be replaced with kmalloc() and kfree()? */
56 u8 *MLMEGetMMPDUBuffer(struct wb35_adapter * adapter) 58 u8 *MLMEGetMMPDUBuffer(struct wb35_adapter * adapter)
57 { 59 {
58 s32 i; 60 s32 i;
59 u8 *returnVal; 61 u8 *returnVal;
60 62
61 for (i = 0; i< MAX_NUM_TX_MMPDU; i++) { 63 for (i = 0; i< MAX_NUM_TX_MMPDU; i++) {
62 if (adapter->sMlmeFrame.TxMMPDUInUse[i] == false) 64 if (adapter->sMlmeFrame.TxMMPDUInUse[i] == false)
63 break; 65 break;
64 } 66 }
65 if (i >= MAX_NUM_TX_MMPDU) return NULL; 67 if (i >= MAX_NUM_TX_MMPDU) return NULL;
66 68
67 returnVal = (u8 *)&(adapter->sMlmeFrame.TxMMPDU[i]); 69 returnVal = (u8 *)&(adapter->sMlmeFrame.TxMMPDU[i]);
68 adapter->sMlmeFrame.TxMMPDUInUse[i] = true; 70 adapter->sMlmeFrame.TxMMPDUInUse[i] = true;
69 71
70 return returnVal; 72 return returnVal;
71 } 73 }
72 74
73 //============================================================================= 75 //=============================================================================
74 u8 MLMESendFrame(struct wb35_adapter * adapter, u8 *pMMPDU, u16 len, u8 DataType) 76 u8 MLMESendFrame(struct wb35_adapter * adapter, u8 *pMMPDU, u16 len, u8 DataType)
75 /* DataType : FRAME_TYPE_802_11_MANAGEMENT, FRAME_TYPE_802_11_MANAGEMENT_CHALLENGE, 77 /* DataType : FRAME_TYPE_802_11_MANAGEMENT, FRAME_TYPE_802_11_MANAGEMENT_CHALLENGE,
76 FRAME_TYPE_802_11_DATA */ 78 FRAME_TYPE_802_11_DATA */
77 { 79 {
78 if (adapter->sMlmeFrame.IsInUsed != PACKET_FREE_TO_USE) { 80 if (adapter->sMlmeFrame.IsInUsed != PACKET_FREE_TO_USE) {
79 adapter->sMlmeFrame.wNumTxMMPDUDiscarded++; 81 adapter->sMlmeFrame.wNumTxMMPDUDiscarded++;
80 return false; 82 return false;
81 } 83 }
82 adapter->sMlmeFrame.IsInUsed = PACKET_COME_FROM_MLME; 84 adapter->sMlmeFrame.IsInUsed = PACKET_COME_FROM_MLME;
83 85
84 // Keep information for sending 86 // Keep information for sending
85 adapter->sMlmeFrame.pMMPDU = pMMPDU; 87 adapter->sMlmeFrame.pMMPDU = pMMPDU;
86 adapter->sMlmeFrame.DataType = DataType; 88 adapter->sMlmeFrame.DataType = DataType;
87 // len must be the last setting due to QUERY_SIZE_SECOND of Mds 89 // len must be the last setting due to QUERY_SIZE_SECOND of Mds
88 adapter->sMlmeFrame.len = len; 90 adapter->sMlmeFrame.len = len;
89 adapter->sMlmeFrame.wNumTxMMPDU++; 91 adapter->sMlmeFrame.wNumTxMMPDU++;
90 92
91 // H/W will enter power save by set the register. S/W don't send null frame 93 // H/W will enter power save by set the register. S/W don't send null frame
92 //with PWRMgt bit enbled to enter power save now. 94 //with PWRMgt bit enbled to enter power save now.
93 95
94 // Transmit NDIS packet 96 // Transmit NDIS packet
95 Mds_Tx(adapter); 97 Mds_Tx(adapter);
96 return true; 98 return true;
97 } 99 }
98 100
99 void MLME_GetNextPacket(struct wb35_adapter *adapter, PDESCRIPTOR desc) 101 void MLME_GetNextPacket(struct wb35_adapter *adapter, PDESCRIPTOR desc)
100 { 102 {
101 desc->InternalUsed = desc->buffer_start_index + desc->buffer_number; 103 desc->InternalUsed = desc->buffer_start_index + desc->buffer_number;
102 desc->InternalUsed %= MAX_DESCRIPTOR_BUFFER_INDEX; 104 desc->InternalUsed %= MAX_DESCRIPTOR_BUFFER_INDEX;
103 desc->buffer_address[desc->InternalUsed] = adapter->sMlmeFrame.pMMPDU; 105 desc->buffer_address[desc->InternalUsed] = adapter->sMlmeFrame.pMMPDU;
104 desc->buffer_size[desc->InternalUsed] = adapter->sMlmeFrame.len; 106 desc->buffer_size[desc->InternalUsed] = adapter->sMlmeFrame.len;
105 desc->buffer_total_size += adapter->sMlmeFrame.len; 107 desc->buffer_total_size += adapter->sMlmeFrame.len;
106 desc->buffer_number++; 108 desc->buffer_number++;
107 desc->Type = adapter->sMlmeFrame.DataType; 109 desc->Type = adapter->sMlmeFrame.DataType;
108 } 110 }
109 111
110 void MLMEfreeMMPDUBuffer(struct wb35_adapter * adapter, s8 *pData) 112 void MLMEfreeMMPDUBuffer(struct wb35_adapter * adapter, s8 *pData)
111 { 113 {
112 int i; 114 int i;
113 115
114 // Reclaim the data buffer 116 // Reclaim the data buffer
115 for (i = 0; i < MAX_NUM_TX_MMPDU; i++) { 117 for (i = 0; i < MAX_NUM_TX_MMPDU; i++) {
116 if (pData == (s8 *)&(adapter->sMlmeFrame.TxMMPDU[i])) 118 if (pData == (s8 *)&(adapter->sMlmeFrame.TxMMPDU[i]))
117 break; 119 break;
118 } 120 }
119 if (adapter->sMlmeFrame.TxMMPDUInUse[i]) 121 if (adapter->sMlmeFrame.TxMMPDUInUse[i])
120 adapter->sMlmeFrame.TxMMPDUInUse[i] = false; 122 adapter->sMlmeFrame.TxMMPDUInUse[i] = false;
121 else { 123 else {
122 // Something wrong 124 // Something wrong
123 // PD43 Add debug code here??? 125 // PD43 Add debug code here???
124 } 126 }
125 } 127 }
126 128
127 void 129 void
128 MLME_SendComplete(struct wb35_adapter * adapter, u8 PacketID, unsigned char SendOK) 130 MLME_SendComplete(struct wb35_adapter * adapter, u8 PacketID, unsigned char SendOK)
129 { 131 {
130 MLME_TXCALLBACK TxCallback; 132 MLME_TXCALLBACK TxCallback;
131 133
132 // Reclaim the data buffer 134 // Reclaim the data buffer
133 adapter->sMlmeFrame.len = 0; 135 adapter->sMlmeFrame.len = 0;
134 MLMEfreeMMPDUBuffer( adapter, adapter->sMlmeFrame.pMMPDU ); 136 MLMEfreeMMPDUBuffer( adapter, adapter->sMlmeFrame.pMMPDU );
135 137
136 138
137 TxCallback.bResult = MLME_SUCCESS; 139 TxCallback.bResult = MLME_SUCCESS;
138 140
139 // Return resource 141 // Return resource
140 adapter->sMlmeFrame.IsInUsed = PACKET_FREE_TO_USE; 142 adapter->sMlmeFrame.IsInUsed = PACKET_FREE_TO_USE;
141 } 143 }
142 144
143 145
144 146
145 147
drivers/staging/winbond/mlmetxrx_f.h
Diff comments   View file @ 80aba53
1 //================================================================ 1 //================================================================
2 // MLMETxRx.H -- 2 // MLMETxRx.H --
3 // 3 //
4 // Functions defined in MLMETxRx.c. 4 // Functions defined in MLMETxRx.c.
5 // 5 //
6 // Copyright (c) 2002 Winbond Electrics Corp. All Rights Reserved. 6 // Copyright (c) 2002 Winbond Electrics Corp. All Rights Reserved.
7 //================================================================ 7 //================================================================
8 #ifndef _MLMETXRX_H 8 #ifndef _MLMETXRX_H
9 #define _MLMETXRX_H 9 #define _MLMETXRX_H
10 10
11 #include "adapter.h"
12
11 void 13 void
12 MLMEProcThread( 14 MLMEProcThread(
13 struct wb35_adapter * adapter 15 struct wb35_adapter * adapter
14 ); 16 );
15 17
16 void MLMEResetTxRx( struct wb35_adapter * adapter); 18 void MLMEResetTxRx( struct wb35_adapter * adapter);
17 19
18 u8 * 20 u8 *
19 MLMEGetMMPDUBuffer( 21 MLMEGetMMPDUBuffer(
20 struct wb35_adapter * adapter 22 struct wb35_adapter * adapter
21 ); 23 );
22 24
23 void MLMEfreeMMPDUBuffer( struct wb35_adapter * adapter, s8 * pData); 25 void MLMEfreeMMPDUBuffer( struct wb35_adapter * adapter, s8 * pData);
24 26
25 void MLME_GetNextPacket( struct wb35_adapter * adapter, PDESCRIPTOR pDes ); 27 void MLME_GetNextPacket( struct wb35_adapter * adapter, PDESCRIPTOR pDes );
26 u8 MLMESendFrame( struct wb35_adapter * adapter, 28 u8 MLMESendFrame( struct wb35_adapter * adapter,
27 u8 *pMMPDU, 29 u8 *pMMPDU,
28 u16 len, 30 u16 len,
29 u8 DataType); 31 u8 DataType);
30 32
31 void 33 void
32 MLME_SendComplete( struct wb35_adapter * adapter, u8 PacketID, unsigned char SendOK ); 34 MLME_SendComplete( struct wb35_adapter * adapter, u8 PacketID, unsigned char SendOK );
33 35
34 void 36 void
35 MLMERcvFrame( 37 MLMERcvFrame(
36 struct wb35_adapter * adapter, 38 struct wb35_adapter * adapter,
37 PRXBUFFER pRxBufferArray, 39 PRXBUFFER pRxBufferArray,
38 u8 NumOfBuffer, 40 u8 NumOfBuffer,
39 u8 ReturnSlotIndex 41 u8 ReturnSlotIndex
40 ); 42 );
41 43
42 void 44 void
43 MLMEReturnPacket( 45 MLMEReturnPacket(
44 struct wb35_adapter * adapter, 46 struct wb35_adapter * adapter,
45 u8 * pRxBufer 47 u8 * pRxBufer
46 ); 48 );
47 #ifdef _IBSS_BEACON_SEQ_STICK_ 49 #ifdef _IBSS_BEACON_SEQ_STICK_
48 s8 SendBCNullData(struct wb35_adapter * adapter, u16 wIdx); 50 s8 SendBCNullData(struct wb35_adapter * adapter, u16 wIdx);
49 #endif 51 #endif
50 52
51 #endif 53 #endif
52 54
53 55
drivers/staging/winbond/mto.c
Diff comments   View file @ 80aba53
1 //============================================================================ 1 //============================================================================
2 // MTO.C - 2 // MTO.C -
3 // 3 //
4 // Description: 4 // Description:
5 // MAC Throughput Optimization for W89C33 802.11g WLAN STA. 5 // MAC Throughput Optimization for W89C33 802.11g WLAN STA.
6 // 6 //
7 // The following MIB attributes or internal variables will be affected 7 // The following MIB attributes or internal variables will be affected
8 // while the MTO is being executed: 8 // while the MTO is being executed:
9 // dot11FragmentationThreshold, 9 // dot11FragmentationThreshold,
10 // dot11RTSThreshold, 10 // dot11RTSThreshold,
11 // transmission rate and PLCP preamble type, 11 // transmission rate and PLCP preamble type,
12 // CCA mode, 12 // CCA mode,
13 // antenna diversity. 13 // antenna diversity.
14 // 14 //
15 // Revision history: 15 // Revision history:
16 // -------------------------------------------------------------------------- 16 // --------------------------------------------------------------------------
17 // 20031227 UN20 Pete Chao 17 // 20031227 UN20 Pete Chao
18 // First draft 18 // First draft
19 // 20031229 Turbo copy from PD43 19 // 20031229 Turbo copy from PD43
20 // 20040210 Kevin revised 20 // 20040210 Kevin revised
21 // Copyright (c) 2003 Winbond Electronics Corp. All rights reserved. 21 // Copyright (c) 2003 Winbond Electronics Corp. All rights reserved.
22 //============================================================================ 22 //============================================================================
23 23
24 // LA20040210_DTO kevin 24 // LA20040210_DTO kevin
25 #include "os_common.h" 25 #include "os_common.h"
26 #include "sme_api.h"
27 #include "gl_80211.h"
28 #include "wbhal_f.h"
26 29
27 // Declare SQ3 to rate and fragmentation threshold table 30 // Declare SQ3 to rate and fragmentation threshold table
28 // Declare fragmentation thresholds table 31 // Declare fragmentation thresholds table
29 #define MTO_MAX_SQ3_LEVELS 14 32 #define MTO_MAX_SQ3_LEVELS 14
30 #define MTO_MAX_FRAG_TH_LEVELS 5 33 #define MTO_MAX_FRAG_TH_LEVELS 5
31 #define MTO_MAX_DATA_RATE_LEVELS 12 34 #define MTO_MAX_DATA_RATE_LEVELS 12
32 35
33 u16 MTO_Frag_Th_Tbl[MTO_MAX_FRAG_TH_LEVELS] = 36 u16 MTO_Frag_Th_Tbl[MTO_MAX_FRAG_TH_LEVELS] =
34 { 37 {
35 256, 384, 512, 768, 1536 38 256, 384, 512, 768, 1536
36 }; 39 };
37 40
38 u8 MTO_SQ3_Level[MTO_MAX_SQ3_LEVELS] = 41 u8 MTO_SQ3_Level[MTO_MAX_SQ3_LEVELS] =
39 { 42 {
40 0, 26, 30, 32, 34, 35, 37, 42, 44, 46, 54, 62, 78, 81 43 0, 26, 30, 32, 34, 35, 37, 42, 44, 46, 54, 62, 78, 81
41 }; 44 };
42 u8 MTO_SQ3toRate[MTO_MAX_SQ3_LEVELS] = 45 u8 MTO_SQ3toRate[MTO_MAX_SQ3_LEVELS] =
43 { 46 {
44 0, 1, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 47 0, 1, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11
45 }; 48 };
46 u8 MTO_SQ3toFrag[MTO_MAX_SQ3_LEVELS] = 49 u8 MTO_SQ3toFrag[MTO_MAX_SQ3_LEVELS] =
47 { 50 {
48 0, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4 51 0, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4
49 }; 52 };
50 53
51 // One Exchange Time table 54 // One Exchange Time table
52 // 55 //
53 u16 MTO_One_Exchange_Time_Tbl_l[MTO_MAX_FRAG_TH_LEVELS][MTO_MAX_DATA_RATE_LEVELS] = 56 u16 MTO_One_Exchange_Time_Tbl_l[MTO_MAX_FRAG_TH_LEVELS][MTO_MAX_DATA_RATE_LEVELS] =
54 { 57 {
55 { 2554, 1474, 822, 0, 0, 636, 0, 0, 0, 0, 0, 0}, 58 { 2554, 1474, 822, 0, 0, 636, 0, 0, 0, 0, 0, 0},
56 { 3578, 1986, 1009, 0, 0, 729, 0, 0, 0, 0, 0, 0}, 59 { 3578, 1986, 1009, 0, 0, 729, 0, 0, 0, 0, 0, 0},
57 { 4602, 2498, 1195, 0, 0, 822, 0, 0, 0, 0, 0, 0}, 60 { 4602, 2498, 1195, 0, 0, 822, 0, 0, 0, 0, 0, 0},
58 { 6650, 3522, 1567, 0, 0, 1009, 0, 0, 0, 0, 0, 0}, 61 { 6650, 3522, 1567, 0, 0, 1009, 0, 0, 0, 0, 0, 0},
59 {12794, 6594, 2684, 0, 0, 1567, 0, 0, 0, 0, 0, 0} 62 {12794, 6594, 2684, 0, 0, 1567, 0, 0, 0, 0, 0, 0}
60 }; 63 };
61 64
62 u16 MTO_One_Exchange_Time_Tbl_s[MTO_MAX_FRAG_TH_LEVELS][MTO_MAX_DATA_RATE_LEVELS] = 65 u16 MTO_One_Exchange_Time_Tbl_s[MTO_MAX_FRAG_TH_LEVELS][MTO_MAX_DATA_RATE_LEVELS] =
63 { 66 {
64 { 0, 1282, 630, 404, 288, 444, 232, 172, 144, 116, 100, 96}, 67 { 0, 1282, 630, 404, 288, 444, 232, 172, 144, 116, 100, 96},
65 { 0, 1794, 817, 572, 400, 537, 316, 228, 188, 144, 124, 116}, 68 { 0, 1794, 817, 572, 400, 537, 316, 228, 188, 144, 124, 116},
66 { 0, 2306, 1003, 744, 516, 630, 400, 288, 228, 172, 144, 136}, 69 { 0, 2306, 1003, 744, 516, 630, 400, 288, 228, 172, 144, 136},
67 { 0, 3330, 1375, 1084, 744, 817, 572, 400, 316, 228, 188, 172}, 70 { 0, 3330, 1375, 1084, 744, 817, 572, 400, 316, 228, 188, 172},
68 { 0, 6402, 2492, 2108, 1424, 1375, 1084, 740, 572, 400, 316, 284} 71 { 0, 6402, 2492, 2108, 1424, 1375, 1084, 740, 572, 400, 316, 284}
69 }; 72 };
70 73
71 #define MTO_ONE_EXCHANGE_TIME(preamble_type, frag_th_lvl, data_rate_lvl) \ 74 #define MTO_ONE_EXCHANGE_TIME(preamble_type, frag_th_lvl, data_rate_lvl) \
72 (preamble_type) ? MTO_One_Exchange_Time_Tbl_s[frag_th_lvl][data_rate_lvl] : \ 75 (preamble_type) ? MTO_One_Exchange_Time_Tbl_s[frag_th_lvl][data_rate_lvl] : \
73 MTO_One_Exchange_Time_Tbl_l[frag_th_lvl][data_rate_lvl] 76 MTO_One_Exchange_Time_Tbl_l[frag_th_lvl][data_rate_lvl]
74 77
75 // Declare data rate table 78 // Declare data rate table
76 //The following table will be changed at anytime if the opration rate supported by AP don't 79 //The following table will be changed at anytime if the opration rate supported by AP don't
77 //match the table 80 //match the table
78 u8 MTO_Data_Rate_Tbl[MTO_MAX_DATA_RATE_LEVELS] = 81 u8 MTO_Data_Rate_Tbl[MTO_MAX_DATA_RATE_LEVELS] =
79 { 82 {
80 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 83 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108
81 }; 84 };
82 85
83 //The Stardard_Data_Rate_Tbl and Level2PerTbl table is used to indirectly retreive PER 86 //The Stardard_Data_Rate_Tbl and Level2PerTbl table is used to indirectly retreive PER
84 //information from Rate_PER_TBL 87 //information from Rate_PER_TBL
85 //The default settings is AP can support full rate set. 88 //The default settings is AP can support full rate set.
86 static u8 Stardard_Data_Rate_Tbl[MTO_MAX_DATA_RATE_LEVELS] = 89 static u8 Stardard_Data_Rate_Tbl[MTO_MAX_DATA_RATE_LEVELS] =
87 { 90 {
88 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 91 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108
89 }; 92 };
90 static u8 Level2PerTbl[MTO_MAX_DATA_RATE_LEVELS] = 93 static u8 Level2PerTbl[MTO_MAX_DATA_RATE_LEVELS] =
91 { 94 {
92 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 95 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11
93 }; 96 };
94 //How many kind of tx rate can be supported by AP 97 //How many kind of tx rate can be supported by AP
95 //DTO will change Rate between MTO_Data_Rate_Tbl[0] and MTO_Data_Rate_Tbl[MTO_DataRateAvailableLevel-1] 98 //DTO will change Rate between MTO_Data_Rate_Tbl[0] and MTO_Data_Rate_Tbl[MTO_DataRateAvailableLevel-1]
96 static u8 MTO_DataRateAvailableLevel = MTO_MAX_DATA_RATE_LEVELS; 99 static u8 MTO_DataRateAvailableLevel = MTO_MAX_DATA_RATE_LEVELS;
97 //Smoothed PER table for each different RATE based on packet length of 1514 100 //Smoothed PER table for each different RATE based on packet length of 1514
98 static int Rate_PER_TBL[91][MTO_MAX_DATA_RATE_LEVELS] = { 101 static int Rate_PER_TBL[91][MTO_MAX_DATA_RATE_LEVELS] = {
99 // 1M 2M 5.5M 11M 6M 9M 12M 18M 24M 36M 48M 54M 102 // 1M 2M 5.5M 11M 6M 9M 12M 18M 24M 36M 48M 54M
100 /* 0% */{ 93, 177, 420, 538, 690, 774, 1001, 1401, 1768, 2358, 2838, 3039}, 103 /* 0% */{ 93, 177, 420, 538, 690, 774, 1001, 1401, 1768, 2358, 2838, 3039},
101 /* 1% */{ 92, 176, 416, 533, 683, 767, 992, 1389, 1752, 2336, 2811, 3010}, 104 /* 1% */{ 92, 176, 416, 533, 683, 767, 992, 1389, 1752, 2336, 2811, 3010},
102 /* 2% */{ 91, 174, 412, 528, 675, 760, 983, 1376, 1735, 2313, 2783, 2979}, 105 /* 2% */{ 91, 174, 412, 528, 675, 760, 983, 1376, 1735, 2313, 2783, 2979},
103 /* 3% */{ 90, 172, 407, 523, 667, 753, 973, 1363, 1719, 2290, 2755, 2948}, 106 /* 3% */{ 90, 172, 407, 523, 667, 753, 973, 1363, 1719, 2290, 2755, 2948},
104 /* 4% */{ 90, 170, 403, 518, 659, 746, 964, 1350, 1701, 2266, 2726, 2916}, 107 /* 4% */{ 90, 170, 403, 518, 659, 746, 964, 1350, 1701, 2266, 2726, 2916},
105 /* 5% */{ 89, 169, 398, 512, 651, 738, 954, 1336, 1684, 2242, 2696, 2884}, 108 /* 5% */{ 89, 169, 398, 512, 651, 738, 954, 1336, 1684, 2242, 2696, 2884},
106 /* 6% */{ 88, 167, 394, 507, 643, 731, 944, 1322, 1666, 2217, 2665, 2851}, 109 /* 6% */{ 88, 167, 394, 507, 643, 731, 944, 1322, 1666, 2217, 2665, 2851},
107 /* 7% */{ 87, 165, 389, 502, 635, 723, 935, 1308, 1648, 2192, 2634, 2817}, 110 /* 7% */{ 87, 165, 389, 502, 635, 723, 935, 1308, 1648, 2192, 2634, 2817},
108 /* 8% */{ 86, 163, 384, 497, 626, 716, 924, 1294, 1629, 2166, 2602, 2782}, 111 /* 8% */{ 86, 163, 384, 497, 626, 716, 924, 1294, 1629, 2166, 2602, 2782},
109 /* 9% */{ 85, 161, 380, 491, 618, 708, 914, 1279, 1611, 2140, 2570, 2747}, 112 /* 9% */{ 85, 161, 380, 491, 618, 708, 914, 1279, 1611, 2140, 2570, 2747},
110 /* 10% */{ 84, 160, 375, 486, 609, 700, 904, 1265, 1591, 2113, 2537, 2711}, 113 /* 10% */{ 84, 160, 375, 486, 609, 700, 904, 1265, 1591, 2113, 2537, 2711},
111 /* 11% */{ 83, 158, 370, 480, 600, 692, 894, 1250, 1572, 2086, 2503, 2675}, 114 /* 11% */{ 83, 158, 370, 480, 600, 692, 894, 1250, 1572, 2086, 2503, 2675},
112 /* 12% */{ 82, 156, 365, 475, 592, 684, 883, 1234, 1552, 2059, 2469, 2638}, 115 /* 12% */{ 82, 156, 365, 475, 592, 684, 883, 1234, 1552, 2059, 2469, 2638},
113 /* 13% */{ 81, 154, 360, 469, 583, 676, 872, 1219, 1532, 2031, 2435, 2600}, 116 /* 13% */{ 81, 154, 360, 469, 583, 676, 872, 1219, 1532, 2031, 2435, 2600},
114 /* 14% */{ 80, 152, 355, 464, 574, 668, 862, 1204, 1512, 2003, 2400, 2562}, 117 /* 14% */{ 80, 152, 355, 464, 574, 668, 862, 1204, 1512, 2003, 2400, 2562},
115 /* 15% */{ 79, 150, 350, 458, 565, 660, 851, 1188, 1492, 1974, 2365, 2524}, 118 /* 15% */{ 79, 150, 350, 458, 565, 660, 851, 1188, 1492, 1974, 2365, 2524},
116 /* 16% */{ 78, 148, 345, 453, 556, 652, 840, 1172, 1471, 1945, 2329, 2485}, 119 /* 16% */{ 78, 148, 345, 453, 556, 652, 840, 1172, 1471, 1945, 2329, 2485},
117 /* 17% */{ 77, 146, 340, 447, 547, 643, 829, 1156, 1450, 1916, 2293, 2446}, 120 /* 17% */{ 77, 146, 340, 447, 547, 643, 829, 1156, 1450, 1916, 2293, 2446},
118 /* 18% */{ 76, 144, 335, 441, 538, 635, 818, 1140, 1429, 1887, 2256, 2406}, 121 /* 18% */{ 76, 144, 335, 441, 538, 635, 818, 1140, 1429, 1887, 2256, 2406},
119 /* 19% */{ 75, 143, 330, 436, 529, 627, 807, 1124, 1408, 1857, 2219, 2366}, 122 /* 19% */{ 75, 143, 330, 436, 529, 627, 807, 1124, 1408, 1857, 2219, 2366},
120 /* 20% */{ 74, 141, 325, 430, 520, 618, 795, 1107, 1386, 1827, 2182, 2326}, 123 /* 20% */{ 74, 141, 325, 430, 520, 618, 795, 1107, 1386, 1827, 2182, 2326},
121 /* 21% */{ 73, 139, 320, 424, 510, 610, 784, 1091, 1365, 1797, 2145, 2285}, 124 /* 21% */{ 73, 139, 320, 424, 510, 610, 784, 1091, 1365, 1797, 2145, 2285},
122 /* 22% */{ 72, 137, 314, 418, 501, 601, 772, 1074, 1343, 1766, 2107, 2244}, 125 /* 22% */{ 72, 137, 314, 418, 501, 601, 772, 1074, 1343, 1766, 2107, 2244},
123 /* 23% */{ 71, 135, 309, 412, 492, 592, 761, 1057, 1321, 1736, 2069, 2203}, 126 /* 23% */{ 71, 135, 309, 412, 492, 592, 761, 1057, 1321, 1736, 2069, 2203},
124 /* 24% */{ 70, 133, 304, 407, 482, 584, 749, 1040, 1299, 1705, 2031, 2161}, 127 /* 24% */{ 70, 133, 304, 407, 482, 584, 749, 1040, 1299, 1705, 2031, 2161},
125 /* 25% */{ 69, 131, 299, 401, 473, 575, 738, 1023, 1277, 1674, 1992, 2120}, 128 /* 25% */{ 69, 131, 299, 401, 473, 575, 738, 1023, 1277, 1674, 1992, 2120},
126 /* 26% */{ 68, 129, 293, 395, 464, 566, 726, 1006, 1254, 1642, 1953, 2078}, 129 /* 26% */{ 68, 129, 293, 395, 464, 566, 726, 1006, 1254, 1642, 1953, 2078},
127 /* 27% */{ 67, 127, 288, 389, 454, 557, 714, 989, 1232, 1611, 1915, 2035}, 130 /* 27% */{ 67, 127, 288, 389, 454, 557, 714, 989, 1232, 1611, 1915, 2035},
128 /* 28% */{ 66, 125, 283, 383, 445, 549, 703, 972, 1209, 1579, 1876, 1993}, 131 /* 28% */{ 66, 125, 283, 383, 445, 549, 703, 972, 1209, 1579, 1876, 1993},
129 /* 29% */{ 65, 123, 278, 377, 436, 540, 691, 955, 1187, 1548, 1836, 1951}, 132 /* 29% */{ 65, 123, 278, 377, 436, 540, 691, 955, 1187, 1548, 1836, 1951},
130 /* 30% */{ 64, 121, 272, 371, 426, 531, 679, 937, 1164, 1516, 1797, 1908}, 133 /* 30% */{ 64, 121, 272, 371, 426, 531, 679, 937, 1164, 1516, 1797, 1908},
131 /* 31% */{ 63, 119, 267, 365, 417, 522, 667, 920, 1141, 1484, 1758, 1866}, 134 /* 31% */{ 63, 119, 267, 365, 417, 522, 667, 920, 1141, 1484, 1758, 1866},
132 /* 32% */{ 62, 117, 262, 359, 407, 513, 655, 902, 1118, 1453, 1719, 1823}, 135 /* 32% */{ 62, 117, 262, 359, 407, 513, 655, 902, 1118, 1453, 1719, 1823},
133 /* 33% */{ 61, 115, 256, 353, 398, 504, 643, 885, 1095, 1421, 1679, 1781}, 136 /* 33% */{ 61, 115, 256, 353, 398, 504, 643, 885, 1095, 1421, 1679, 1781},
134 /* 34% */{ 60, 113, 251, 347, 389, 495, 631, 867, 1072, 1389, 1640, 1738}, 137 /* 34% */{ 60, 113, 251, 347, 389, 495, 631, 867, 1072, 1389, 1640, 1738},
135 /* 35% */{ 59, 111, 246, 341, 379, 486, 619, 850, 1049, 1357, 1600, 1695}, 138 /* 35% */{ 59, 111, 246, 341, 379, 486, 619, 850, 1049, 1357, 1600, 1695},
136 /* 36% */{ 58, 108, 240, 335, 370, 477, 607, 832, 1027, 1325, 1561, 1653}, 139 /* 36% */{ 58, 108, 240, 335, 370, 477, 607, 832, 1027, 1325, 1561, 1653},
137 /* 37% */{ 57, 106, 235, 329, 361, 468, 595, 815, 1004, 1293, 1522, 1610}, 140 /* 37% */{ 57, 106, 235, 329, 361, 468, 595, 815, 1004, 1293, 1522, 1610},
138 /* 38% */{ 56, 104, 230, 323, 351, 459, 584, 797, 981, 1261, 1483, 1568}, 141 /* 38% */{ 56, 104, 230, 323, 351, 459, 584, 797, 981, 1261, 1483, 1568},
139 /* 39% */{ 55, 102, 224, 317, 342, 450, 572, 780, 958, 1230, 1443, 1526}, 142 /* 39% */{ 55, 102, 224, 317, 342, 450, 572, 780, 958, 1230, 1443, 1526},
140 /* 40% */{ 54, 100, 219, 311, 333, 441, 560, 762, 935, 1198, 1404, 1484}, 143 /* 40% */{ 54, 100, 219, 311, 333, 441, 560, 762, 935, 1198, 1404, 1484},
141 /* 41% */{ 53, 98, 214, 305, 324, 432, 548, 744, 912, 1166, 1366, 1442}, 144 /* 41% */{ 53, 98, 214, 305, 324, 432, 548, 744, 912, 1166, 1366, 1442},
142 /* 42% */{ 52, 96, 209, 299, 315, 423, 536, 727, 889, 1135, 1327, 1400}, 145 /* 42% */{ 52, 96, 209, 299, 315, 423, 536, 727, 889, 1135, 1327, 1400},
143 /* 43% */{ 51, 94, 203, 293, 306, 414, 524, 709, 866, 1104, 1289, 1358}, 146 /* 43% */{ 51, 94, 203, 293, 306, 414, 524, 709, 866, 1104, 1289, 1358},
144 /* 44% */{ 50, 92, 198, 287, 297, 405, 512, 692, 844, 1072, 1250, 1317}, 147 /* 44% */{ 50, 92, 198, 287, 297, 405, 512, 692, 844, 1072, 1250, 1317},
145 /* 45% */{ 49, 90, 193, 281, 288, 396, 500, 675, 821, 1041, 1212, 1276}, 148 /* 45% */{ 49, 90, 193, 281, 288, 396, 500, 675, 821, 1041, 1212, 1276},
146 /* 46% */{ 48, 88, 188, 275, 279, 387, 488, 657, 799, 1011, 1174, 1236}, 149 /* 46% */{ 48, 88, 188, 275, 279, 387, 488, 657, 799, 1011, 1174, 1236},
147 /* 47% */{ 47, 86, 183, 269, 271, 378, 476, 640, 777, 980, 1137, 1195}, 150 /* 47% */{ 47, 86, 183, 269, 271, 378, 476, 640, 777, 980, 1137, 1195},
148 /* 48% */{ 46, 84, 178, 262, 262, 369, 464, 623, 754, 949, 1100, 1155}, 151 /* 48% */{ 46, 84, 178, 262, 262, 369, 464, 623, 754, 949, 1100, 1155},
149 /* 49% */{ 45, 82, 173, 256, 254, 360, 452, 606, 732, 919, 1063, 1116}, 152 /* 49% */{ 45, 82, 173, 256, 254, 360, 452, 606, 732, 919, 1063, 1116},
150 /* 50% */{ 44, 80, 168, 251, 245, 351, 441, 589, 710, 889, 1026, 1076}, 153 /* 50% */{ 44, 80, 168, 251, 245, 351, 441, 589, 710, 889, 1026, 1076},
151 /* 51% */{ 43, 78, 163, 245, 237, 342, 429, 572, 689, 860, 990, 1038}, 154 /* 51% */{ 43, 78, 163, 245, 237, 342, 429, 572, 689, 860, 990, 1038},
152 /* 52% */{ 42, 76, 158, 239, 228, 333, 417, 555, 667, 830, 955, 999}, 155 /* 52% */{ 42, 76, 158, 239, 228, 333, 417, 555, 667, 830, 955, 999},
153 /* 53% */{ 41, 74, 153, 233, 220, 324, 406, 538, 645, 801, 919, 961}, 156 /* 53% */{ 41, 74, 153, 233, 220, 324, 406, 538, 645, 801, 919, 961},
154 /* 54% */{ 40, 72, 148, 227, 212, 315, 394, 522, 624, 773, 884, 924}, 157 /* 54% */{ 40, 72, 148, 227, 212, 315, 394, 522, 624, 773, 884, 924},
155 /* 55% */{ 39, 70, 143, 221, 204, 307, 383, 505, 603, 744, 850, 887}, 158 /* 55% */{ 39, 70, 143, 221, 204, 307, 383, 505, 603, 744, 850, 887},
156 /* 56% */{ 38, 68, 138, 215, 196, 298, 371, 489, 582, 716, 816, 851}, 159 /* 56% */{ 38, 68, 138, 215, 196, 298, 371, 489, 582, 716, 816, 851},
157 /* 57% */{ 37, 67, 134, 209, 189, 289, 360, 473, 562, 688, 783, 815}, 160 /* 57% */{ 37, 67, 134, 209, 189, 289, 360, 473, 562, 688, 783, 815},
158 /* 58% */{ 36, 65, 129, 203, 181, 281, 349, 457, 541, 661, 750, 780}, 161 /* 58% */{ 36, 65, 129, 203, 181, 281, 349, 457, 541, 661, 750, 780},
159 /* 59% */{ 35, 63, 124, 197, 174, 272, 338, 441, 521, 634, 717, 745}, 162 /* 59% */{ 35, 63, 124, 197, 174, 272, 338, 441, 521, 634, 717, 745},
160 /* 60% */{ 34, 61, 120, 192, 166, 264, 327, 425, 501, 608, 686, 712}, 163 /* 60% */{ 34, 61, 120, 192, 166, 264, 327, 425, 501, 608, 686, 712},
161 /* 61% */{ 33, 59, 115, 186, 159, 255, 316, 409, 482, 582, 655, 678}, 164 /* 61% */{ 33, 59, 115, 186, 159, 255, 316, 409, 482, 582, 655, 678},
162 /* 62% */{ 32, 57, 111, 180, 152, 247, 305, 394, 462, 556, 624, 646}, 165 /* 62% */{ 32, 57, 111, 180, 152, 247, 305, 394, 462, 556, 624, 646},
163 /* 63% */{ 31, 55, 107, 174, 145, 238, 294, 379, 443, 531, 594, 614}, 166 /* 63% */{ 31, 55, 107, 174, 145, 238, 294, 379, 443, 531, 594, 614},
164 /* 64% */{ 30, 53, 102, 169, 138, 230, 283, 364, 425, 506, 565, 583}, 167 /* 64% */{ 30, 53, 102, 169, 138, 230, 283, 364, 425, 506, 565, 583},
165 /* 65% */{ 29, 52, 98, 163, 132, 222, 273, 349, 406, 482, 536, 553}, 168 /* 65% */{ 29, 52, 98, 163, 132, 222, 273, 349, 406, 482, 536, 553},
166 /* 66% */{ 28, 50, 94, 158, 125, 214, 262, 334, 388, 459, 508, 523}, 169 /* 66% */{ 28, 50, 94, 158, 125, 214, 262, 334, 388, 459, 508, 523},
167 /* 67% */{ 27, 48, 90, 152, 119, 206, 252, 320, 370, 436, 481, 495}, 170 /* 67% */{ 27, 48, 90, 152, 119, 206, 252, 320, 370, 436, 481, 495},
168 /* 68% */{ 26, 46, 86, 147, 113, 198, 242, 306, 353, 413, 455, 467}, 171 /* 68% */{ 26, 46, 86, 147, 113, 198, 242, 306, 353, 413, 455, 467},
169 /* 69% */{ 26, 44, 82, 141, 107, 190, 231, 292, 336, 391, 429, 440}, 172 /* 69% */{ 26, 44, 82, 141, 107, 190, 231, 292, 336, 391, 429, 440},
170 /* 70% */{ 25, 43, 78, 136, 101, 182, 221, 278, 319, 370, 405, 414}, 173 /* 70% */{ 25, 43, 78, 136, 101, 182, 221, 278, 319, 370, 405, 414},
171 /* 71% */{ 24, 41, 74, 130, 95, 174, 212, 265, 303, 350, 381, 389}, 174 /* 71% */{ 24, 41, 74, 130, 95, 174, 212, 265, 303, 350, 381, 389},
172 /* 72% */{ 23, 39, 71, 125, 90, 167, 202, 252, 287, 329, 358, 365}, 175 /* 72% */{ 23, 39, 71, 125, 90, 167, 202, 252, 287, 329, 358, 365},
173 /* 73% */{ 22, 37, 67, 119, 85, 159, 192, 239, 271, 310, 335, 342}, 176 /* 73% */{ 22, 37, 67, 119, 85, 159, 192, 239, 271, 310, 335, 342},
174 /* 74% */{ 21, 36, 63, 114, 80, 151, 183, 226, 256, 291, 314, 320}, 177 /* 74% */{ 21, 36, 63, 114, 80, 151, 183, 226, 256, 291, 314, 320},
175 /* 75% */{ 20, 34, 60, 109, 75, 144, 174, 214, 241, 273, 294, 298}, 178 /* 75% */{ 20, 34, 60, 109, 75, 144, 174, 214, 241, 273, 294, 298},
176 /* 76% */{ 19, 32, 57, 104, 70, 137, 164, 202, 227, 256, 274, 278}, 179 /* 76% */{ 19, 32, 57, 104, 70, 137, 164, 202, 227, 256, 274, 278},
177 /* 77% */{ 18, 31, 53, 99, 66, 130, 155, 190, 213, 239, 256, 259}, 180 /* 77% */{ 18, 31, 53, 99, 66, 130, 155, 190, 213, 239, 256, 259},
178 /* 78% */{ 17, 29, 50, 94, 62, 122, 146, 178, 200, 223, 238, 241}, 181 /* 78% */{ 17, 29, 50, 94, 62, 122, 146, 178, 200, 223, 238, 241},
179 /* 79% */{ 16, 28, 47, 89, 58, 115, 138, 167, 187, 208, 222, 225}, 182 /* 79% */{ 16, 28, 47, 89, 58, 115, 138, 167, 187, 208, 222, 225},
180 /* 80% */{ 16, 26, 44, 84, 54, 109, 129, 156, 175, 194, 206, 209}, 183 /* 80% */{ 16, 26, 44, 84, 54, 109, 129, 156, 175, 194, 206, 209},
181 /* 81% */{ 15, 24, 41, 79, 50, 102, 121, 146, 163, 180, 192, 194}, 184 /* 81% */{ 15, 24, 41, 79, 50, 102, 121, 146, 163, 180, 192, 194},
182 /* 82% */{ 14, 23, 39, 74, 47, 95, 113, 136, 151, 167, 178, 181}, 185 /* 82% */{ 14, 23, 39, 74, 47, 95, 113, 136, 151, 167, 178, 181},
183 /* 83% */{ 13, 21, 36, 69, 44, 89, 105, 126, 140, 155, 166, 169}, 186 /* 83% */{ 13, 21, 36, 69, 44, 89, 105, 126, 140, 155, 166, 169},
184 /* 84% */{ 12, 20, 33, 64, 41, 82, 97, 116, 130, 144, 155, 158}, 187 /* 84% */{ 12, 20, 33, 64, 41, 82, 97, 116, 130, 144, 155, 158},
185 /* 85% */{ 11, 19, 31, 60, 39, 76, 89, 107, 120, 134, 145, 149}, 188 /* 85% */{ 11, 19, 31, 60, 39, 76, 89, 107, 120, 134, 145, 149},
186 /* 86% */{ 11, 17, 29, 55, 36, 70, 82, 98, 110, 125, 136, 140}, 189 /* 86% */{ 11, 17, 29, 55, 36, 70, 82, 98, 110, 125, 136, 140},
187 /* 87% */{ 10, 16, 26, 51, 34, 64, 75, 90, 102, 116, 128, 133}, 190 /* 87% */{ 10, 16, 26, 51, 34, 64, 75, 90, 102, 116, 128, 133},
188 /* 88% */{ 9, 14, 24, 46, 32, 58, 68, 81, 93, 108, 121, 128}, 191 /* 88% */{ 9, 14, 24, 46, 32, 58, 68, 81, 93, 108, 121, 128},
189 /* 89% */{ 8, 13, 22, 42, 31, 52, 61, 74, 86, 102, 116, 124}, 192 /* 89% */{ 8, 13, 22, 42, 31, 52, 61, 74, 86, 102, 116, 124},
190 /* 90% */{ 7, 12, 21, 37, 29, 46, 54, 66, 79, 96, 112, 121} 193 /* 90% */{ 7, 12, 21, 37, 29, 46, 54, 66, 79, 96, 112, 121}
191 }; 194 };
192 195
193 #define RSSIBUF_NUM 10 196 #define RSSIBUF_NUM 10
194 #define RSSI2RATE_SIZE 9 197 #define RSSI2RATE_SIZE 9
195 198
196 static TXRETRY_REC TxRateRec={MTO_MAX_DATA_RATE_LEVELS - 1, 0}; //new record=>TxRateRec 199 static TXRETRY_REC TxRateRec={MTO_MAX_DATA_RATE_LEVELS - 1, 0}; //new record=>TxRateRec
197 static int TxRetryRate; 200 static int TxRetryRate;
198 //static int SQ3, BSS_PK_CNT, NIDLESLOT, SLOT_CNT, INTERF_CNT, GAP_CNT, DS_EVM; 201 //static int SQ3, BSS_PK_CNT, NIDLESLOT, SLOT_CNT, INTERF_CNT, GAP_CNT, DS_EVM;
199 static s32 RSSIBuf[RSSIBUF_NUM]={-70, -70, -70, -70, -70, -70, -70, -70, -70, -70}; 202 static s32 RSSIBuf[RSSIBUF_NUM]={-70, -70, -70, -70, -70, -70, -70, -70, -70, -70};
200 static s32 RSSISmoothed=-700; 203 static s32 RSSISmoothed=-700;
201 static int RSSIBufIndex=0; 204 static int RSSIBufIndex=0;
202 static u8 max_rssi_rate; 205 static u8 max_rssi_rate;
203 static int rate_tbl[13] = {0,1,2,5,11,6,9,12,18,24,36,48,54}; 206 static int rate_tbl[13] = {0,1,2,5,11,6,9,12,18,24,36,48,54};
204 //[WKCHEN]static core_data_t *pMTOcore_data=NULL; 207 //[WKCHEN]static core_data_t *pMTOcore_data=NULL;
205 208
206 static int TotalTxPkt = 0; 209 static int TotalTxPkt = 0;
207 static int TotalTxPktRetry = 0; 210 static int TotalTxPktRetry = 0;
208 static int TxPktPerAnt[3] = {0,0,0}; 211 static int TxPktPerAnt[3] = {0,0,0};
209 static int RXRSSIANT[3] ={-70,-70,-70}; 212 static int RXRSSIANT[3] ={-70,-70,-70};
210 static int TxPktRetryPerAnt[3] = {0,0,0}; 213 static int TxPktRetryPerAnt[3] = {0,0,0};
211 //static int TxDominateFlag=false; 214 //static int TxDominateFlag=false;
212 static u8 old_antenna[4]={1 ,0 ,1 ,0}; 215 static u8 old_antenna[4]={1 ,0 ,1 ,0};
213 static int retryrate_rec[MTO_MAX_DATA_RATE_LEVELS];//this record the retry rate at different data rate 216 static int retryrate_rec[MTO_MAX_DATA_RATE_LEVELS];//this record the retry rate at different data rate
214 217
215 static int PeriodTotalTxPkt = 0; 218 static int PeriodTotalTxPkt = 0;
216 static int PeriodTotalTxPktRetry = 0; 219 static int PeriodTotalTxPktRetry = 0;
217 220
218 typedef struct 221 typedef struct
219 { 222 {
220 s32 RSSI; 223 s32 RSSI;
221 u8 TxRate; 224 u8 TxRate;
222 }RSSI2RATE; 225 }RSSI2RATE;
223 226
224 static RSSI2RATE RSSI2RateTbl[RSSI2RATE_SIZE] = 227 static RSSI2RATE RSSI2RateTbl[RSSI2RATE_SIZE] =
225 { 228 {
226 {-740, 108}, // 54M 229 {-740, 108}, // 54M
227 {-760, 96}, // 48M 230 {-760, 96}, // 48M
228 {-820, 72}, // 36M 231 {-820, 72}, // 36M
229 {-850, 48}, // 24M 232 {-850, 48}, // 24M
230 {-870, 36}, // 18M 233 {-870, 36}, // 18M
231 {-890, 24}, // 12M 234 {-890, 24}, // 12M
232 {-900, 12}, // 6M 235 {-900, 12}, // 6M
233 {-920, 11}, // 5.5M 236 {-920, 11}, // 5.5M
234 {-950, 4}, // 2M 237 {-950, 4}, // 2M
235 }; 238 };
236 static u8 untogglecount; 239 static u8 untogglecount;
237 static u8 last_rate_ant; //this is used for antenna backoff-hh 240 static u8 last_rate_ant; //this is used for antenna backoff-hh
238 241
239 u8 boSparseTxTraffic = false; 242 u8 boSparseTxTraffic = false;
240 243
241 void MTO_Init(MTO_FUNC_INPUT); 244 void MTO_Init(MTO_FUNC_INPUT);
242 void AntennaToggleInitiator(MTO_FUNC_INPUT); 245 void AntennaToggleInitiator(MTO_FUNC_INPUT);
243 void AntennaToggleState(MTO_FUNC_INPUT); 246 void AntennaToggleState(MTO_FUNC_INPUT);
244 void TxPwrControl(MTO_FUNC_INPUT); 247 void TxPwrControl(MTO_FUNC_INPUT);
245 void GetFreshAntennaData(MTO_FUNC_INPUT); 248 void GetFreshAntennaData(MTO_FUNC_INPUT);
246 void TxRateReductionCtrl(MTO_FUNC_INPUT); 249 void TxRateReductionCtrl(MTO_FUNC_INPUT);
247 /** 1.1.31.1000 Turbo modify */ 250 /** 1.1.31.1000 Turbo modify */
248 //void MTO_SetDTORateRange(int type); 251 //void MTO_SetDTORateRange(int type);
249 void MTO_SetDTORateRange(MTO_FUNC_INPUT, u8 *pRateArray, u8 ArraySize); 252 void MTO_SetDTORateRange(MTO_FUNC_INPUT, u8 *pRateArray, u8 ArraySize);
250 void MTO_SetTxCount(MTO_FUNC_INPUT, u8 t0, u8 index); 253 void MTO_SetTxCount(MTO_FUNC_INPUT, u8 t0, u8 index);
251 void MTO_TxFailed(MTO_FUNC_INPUT); 254 void MTO_TxFailed(MTO_FUNC_INPUT);
252 void SmoothRSSI(s32 new_rssi); 255 void SmoothRSSI(s32 new_rssi);
253 void hal_get_dto_para(MTO_FUNC_INPUT, char *buffer); 256 void hal_get_dto_para(MTO_FUNC_INPUT, char *buffer);
254 u8 CalcNewRate(MTO_FUNC_INPUT, u8 old_rate, u32 retry_cnt, u32 tx_frag_cnt); 257 u8 CalcNewRate(MTO_FUNC_INPUT, u8 old_rate, u32 retry_cnt, u32 tx_frag_cnt);
255 u8 GetMaxRateLevelFromRSSI(void); 258 u8 GetMaxRateLevelFromRSSI(void);
256 u8 MTO_GetTxFallbackRate(MTO_FUNC_INPUT); 259 u8 MTO_GetTxFallbackRate(MTO_FUNC_INPUT);
257 int Divide(int a, int b); 260 int Divide(int a, int b);
258 void multiagc(MTO_FUNC_INPUT, u8 high_gain_mode); 261 void multiagc(MTO_FUNC_INPUT, u8 high_gain_mode);
259 262
260 //=========================================================================== 263 //===========================================================================
261 // MTO_Init -- 264 // MTO_Init --
262 // 265 //
263 // Description: 266 // Description:
264 // Set DTO Tx Rate Scope because different AP could have different Rate set. 267 // Set DTO Tx Rate Scope because different AP could have different Rate set.
265 // After our staion join with AP, LM core will call this function to initialize 268 // After our staion join with AP, LM core will call this function to initialize
266 // Tx Rate table. 269 // Tx Rate table.
267 // 270 //
268 // Arguments: 271 // Arguments:
269 // pRateArray - The pointer to the Tx Rate Array by the following order 272 // pRateArray - The pointer to the Tx Rate Array by the following order
270 // - 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 273 // - 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108
271 // - DTO won't check whether rate order is invalid or not 274 // - DTO won't check whether rate order is invalid or not
272 // ArraySize - The array size to indicate how many tx rate we can choose 275 // ArraySize - The array size to indicate how many tx rate we can choose
273 // 276 //
274 // sample code: 277 // sample code:
275 // { 278 // {
276 // u8 RateArray[4] = {2, 4, 11, 22}; 279 // u8 RateArray[4] = {2, 4, 11, 22};
277 // MTO_SetDTORateRange(RateArray, 4); 280 // MTO_SetDTORateRange(RateArray, 4);
278 // } 281 // }
279 // 282 //
280 // Return Value: 283 // Return Value:
281 // None 284 // None
282 //============================================================================ 285 //============================================================================
283 void MTO_SetDTORateRange(MTO_FUNC_INPUT,u8 *pRateArray, u8 ArraySize) 286 void MTO_SetDTORateRange(MTO_FUNC_INPUT,u8 *pRateArray, u8 ArraySize)
284 { 287 {
285 u8 i, j=0; 288 u8 i, j=0;
286 289
287 for(i=0;i<ArraySize;i++) 290 for(i=0;i<ArraySize;i++)
288 { 291 {
289 if(pRateArray[i] == 22) 292 if(pRateArray[i] == 22)
290 break; 293 break;
291 } 294 }
292 if(i < ArraySize) //we need adjust the order of rate list because 11Mbps rate exists 295 if(i < ArraySize) //we need adjust the order of rate list because 11Mbps rate exists
293 { 296 {
294 for(;i>0;i--) 297 for(;i>0;i--)
295 { 298 {
296 if(pRateArray[i-1] <= 11) 299 if(pRateArray[i-1] <= 11)
297 break; 300 break;
298 pRateArray[i] = pRateArray[i-1]; 301 pRateArray[i] = pRateArray[i-1];
299 } 302 }
300 pRateArray[i] = 22; 303 pRateArray[i] = 22;
301 MTO_OFDM_RATE_LEVEL() = i; 304 MTO_OFDM_RATE_LEVEL() = i;
302 } 305 }
303 else 306 else
304 { 307 {
305 for(i=0; i<ArraySize; i++) 308 for(i=0; i<ArraySize; i++)
306 { 309 {
307 if (pRateArray[i] >= 12) 310 if (pRateArray[i] >= 12)
308 break; 311 break;
309 } 312 }
310 MTO_OFDM_RATE_LEVEL() = i; 313 MTO_OFDM_RATE_LEVEL() = i;
311 } 314 }
312 315
313 for(i=0;i<ArraySize;i++) 316 for(i=0;i<ArraySize;i++)
314 { 317 {
315 MTO_Data_Rate_Tbl[i] = pRateArray[i]; 318 MTO_Data_Rate_Tbl[i] = pRateArray[i];
316 for(;j<MTO_MAX_DATA_RATE_LEVELS;j++) 319 for(;j<MTO_MAX_DATA_RATE_LEVELS;j++)
317 { 320 {
318 if(Stardard_Data_Rate_Tbl[j] == pRateArray[i]) 321 if(Stardard_Data_Rate_Tbl[j] == pRateArray[i])
319 break; 322 break;
320 } 323 }
321 Level2PerTbl[i] = j; 324 Level2PerTbl[i] = j;
322 #ifdef _PE_DTO_DUMP_ 325 #ifdef _PE_DTO_DUMP_
323 WBDEBUG(("[MTO]:Op Rate[%d]: %d\n",i, MTO_Data_Rate_Tbl[i])); 326 WBDEBUG(("[MTO]:Op Rate[%d]: %d\n",i, MTO_Data_Rate_Tbl[i]));
324 #endif 327 #endif
325 } 328 }
326 MTO_DataRateAvailableLevel = ArraySize; 329 MTO_DataRateAvailableLevel = ArraySize;
327 if( MTO_DATA().RatePolicy ) // 0 means that no registry setting 330 if( MTO_DATA().RatePolicy ) // 0 means that no registry setting
328 { 331 {
329 if( MTO_DATA().RatePolicy == 1 ) 332 if( MTO_DATA().RatePolicy == 1 )
330 TxRateRec.tx_rate = 0; //ascent 333 TxRateRec.tx_rate = 0; //ascent
331 else 334 else
332 TxRateRec.tx_rate = MTO_DataRateAvailableLevel -1 ; //descent 335 TxRateRec.tx_rate = MTO_DataRateAvailableLevel -1 ; //descent
333 } 336 }
334 else 337 else
335 { 338 {
336 if( MTO_INITTXRATE_MODE ) 339 if( MTO_INITTXRATE_MODE )
337 TxRateRec.tx_rate = 0; //ascent 340 TxRateRec.tx_rate = 0; //ascent
338 else 341 else
339 TxRateRec.tx_rate = MTO_DataRateAvailableLevel -1 ; //descent 342 TxRateRec.tx_rate = MTO_DataRateAvailableLevel -1 ; //descent
340 } 343 }
341 TxRateRec.tx_retry_rate = 0; 344 TxRateRec.tx_retry_rate = 0;
342 //set default rate for initial use 345 //set default rate for initial use
343 MTO_RATE_LEVEL() = TxRateRec.tx_rate; 346 MTO_RATE_LEVEL() = TxRateRec.tx_rate;
344 MTO_FALLBACK_RATE_LEVEL() = MTO_RATE_LEVEL(); 347 MTO_FALLBACK_RATE_LEVEL() = MTO_RATE_LEVEL();
345 } 348 }
346 349
347 //=========================================================================== 350 //===========================================================================
348 // MTO_Init -- 351 // MTO_Init --
349 // 352 //
350 // Description: 353 // Description:
351 // Initialize MTO parameters. 354 // Initialize MTO parameters.
352 // 355 //
353 // This function should be invoked during system initialization. 356 // This function should be invoked during system initialization.
354 // 357 //
355 // Arguments: 358 // Arguments:
356 // adapter - The pointer to the Miniport adapter Context 359 // adapter - The pointer to the Miniport adapter Context
357 // 360 //
358 // Return Value: 361 // Return Value:
359 // None 362 // None
360 //============================================================================ 363 //============================================================================
361 void MTO_Init(MTO_FUNC_INPUT) 364 void MTO_Init(MTO_FUNC_INPUT)
362 { 365 {
363 int i; 366 int i;
364 //WBDEBUG(("[MTO] -> MTO_Init()\n")); 367 //WBDEBUG(("[MTO] -> MTO_Init()\n"));
365 //[WKCHEN]pMTOcore_data = pcore_data; 368 //[WKCHEN]pMTOcore_data = pcore_data;
366 // 20040510 Turbo add for global variable 369 // 20040510 Turbo add for global variable
367 MTO_TMR_CNT() = 0; 370 MTO_TMR_CNT() = 0;
368 MTO_TOGGLE_STATE() = TOGGLE_STATE_IDLE; 371 MTO_TOGGLE_STATE() = TOGGLE_STATE_IDLE;
369 MTO_TX_RATE_REDUCTION_STATE() = RATE_CHGSTATE_IDLE; 372 MTO_TX_RATE_REDUCTION_STATE() = RATE_CHGSTATE_IDLE;
370 MTO_BACKOFF_TMR() = 0; 373 MTO_BACKOFF_TMR() = 0;
371 MTO_LAST_RATE() = 11; 374 MTO_LAST_RATE() = 11;
372 MTO_CO_EFFICENT() = 0; 375 MTO_CO_EFFICENT() = 0;
373 376
374 //MTO_TH_FIXANT() = MTO_DEFAULT_TH_FIXANT; 377 //MTO_TH_FIXANT() = MTO_DEFAULT_TH_FIXANT;
375 MTO_TH_CNT() = MTO_DEFAULT_TH_CNT; 378 MTO_TH_CNT() = MTO_DEFAULT_TH_CNT;
376 MTO_TH_SQ3() = MTO_DEFAULT_TH_SQ3; 379 MTO_TH_SQ3() = MTO_DEFAULT_TH_SQ3;
377 MTO_TH_IDLE_SLOT() = MTO_DEFAULT_TH_IDLE_SLOT; 380 MTO_TH_IDLE_SLOT() = MTO_DEFAULT_TH_IDLE_SLOT;
378 MTO_TH_PR_INTERF() = MTO_DEFAULT_TH_PR_INTERF; 381 MTO_TH_PR_INTERF() = MTO_DEFAULT_TH_PR_INTERF;
379 382
380 MTO_TMR_AGING() = MTO_DEFAULT_TMR_AGING; 383 MTO_TMR_AGING() = MTO_DEFAULT_TMR_AGING;
381 MTO_TMR_PERIODIC() = MTO_DEFAULT_TMR_PERIODIC; 384 MTO_TMR_PERIODIC() = MTO_DEFAULT_TMR_PERIODIC;
382 385
383 //[WKCHEN]MTO_CCA_MODE_SETUP()= (u8) hal_get_cca_mode(MTO_HAL()); 386 //[WKCHEN]MTO_CCA_MODE_SETUP()= (u8) hal_get_cca_mode(MTO_HAL());
384 //[WKCHEN]MTO_CCA_MODE() = MTO_CCA_MODE_SETUP(); 387 //[WKCHEN]MTO_CCA_MODE() = MTO_CCA_MODE_SETUP();
385 388
386 //MTO_PREAMBLE_TYPE() = MTO_PREAMBLE_LONG; 389 //MTO_PREAMBLE_TYPE() = MTO_PREAMBLE_LONG;
387 MTO_PREAMBLE_TYPE() = MTO_PREAMBLE_SHORT; // for test 390 MTO_PREAMBLE_TYPE() = MTO_PREAMBLE_SHORT; // for test
388 391
389 MTO_ANT_SEL() = hal_get_antenna_number(MTO_HAL()); 392 MTO_ANT_SEL() = hal_get_antenna_number(MTO_HAL());
390 MTO_ANT_MAC() = MTO_ANT_SEL(); 393 MTO_ANT_MAC() = MTO_ANT_SEL();
391 MTO_CNT_ANT(0) = 0; 394 MTO_CNT_ANT(0) = 0;
392 MTO_CNT_ANT(1) = 0; 395 MTO_CNT_ANT(1) = 0;
393 MTO_SQ_ANT(0) = 0; 396 MTO_SQ_ANT(0) = 0;
394 MTO_SQ_ANT(1) = 0; 397 MTO_SQ_ANT(1) = 0;
395 MTO_ANT_DIVERSITY() = MTO_ANTENNA_DIVERSITY_ON; 398 MTO_ANT_DIVERSITY() = MTO_ANTENNA_DIVERSITY_ON;
396 //CardSet_AntennaDiversity(adapter, MTO_ANT_DIVERSITY()); 399 //CardSet_AntennaDiversity(adapter, MTO_ANT_DIVERSITY());
397 //PLMESetAntennaDiversity( adapter, MTO_ANT_DIVERSITY()); 400 //PLMESetAntennaDiversity( adapter, MTO_ANT_DIVERSITY());
398 401
399 MTO_AGING_TIMEOUT() = 0;//MTO_TMR_AGING() / MTO_TMR_PERIODIC(); 402 MTO_AGING_TIMEOUT() = 0;//MTO_TMR_AGING() / MTO_TMR_PERIODIC();
400 403
401 // The following parameters should be initialized to the values set by user 404 // The following parameters should be initialized to the values set by user
402 // 405 //
403 //MTO_RATE_LEVEL() = 10; 406 //MTO_RATE_LEVEL() = 10;
404 MTO_RATE_LEVEL() = 0; 407 MTO_RATE_LEVEL() = 0;
405 MTO_FALLBACK_RATE_LEVEL() = MTO_RATE_LEVEL(); 408 MTO_FALLBACK_RATE_LEVEL() = MTO_RATE_LEVEL();
406 MTO_FRAG_TH_LEVEL() = 4; 409 MTO_FRAG_TH_LEVEL() = 4;
407 /** 1.1.23.1000 Turbo modify from -1 to +1 410 /** 1.1.23.1000 Turbo modify from -1 to +1
408 MTO_RTS_THRESHOLD() = MTO_FRAG_TH() - 1; 411 MTO_RTS_THRESHOLD() = MTO_FRAG_TH() - 1;
409 MTO_RTS_THRESHOLD_SETUP() = MTO_FRAG_TH() - 1; 412 MTO_RTS_THRESHOLD_SETUP() = MTO_FRAG_TH() - 1;
410 */ 413 */
411 MTO_RTS_THRESHOLD() = MTO_FRAG_TH() + 1; 414 MTO_RTS_THRESHOLD() = MTO_FRAG_TH() + 1;
412 MTO_RTS_THRESHOLD_SETUP() = MTO_FRAG_TH() + 1; 415 MTO_RTS_THRESHOLD_SETUP() = MTO_FRAG_TH() + 1;
413 // 1.1.23.1000 Turbo add for mto change preamble from 0 to 1 416 // 1.1.23.1000 Turbo add for mto change preamble from 0 to 1
414 MTO_RATE_CHANGE_ENABLE() = 1; 417 MTO_RATE_CHANGE_ENABLE() = 1;
415 MTO_FRAG_CHANGE_ENABLE() = 0; // 1.1.29.1000 Turbo add don't support frag 418 MTO_FRAG_CHANGE_ENABLE() = 0; // 1.1.29.1000 Turbo add don't support frag
416 //The default valud of ANTDIV_DEFAULT_ON will be decided by EEPROM 419 //The default valud of ANTDIV_DEFAULT_ON will be decided by EEPROM
417 //#ifdef ANTDIV_DEFAULT_ON 420 //#ifdef ANTDIV_DEFAULT_ON
418 //MTO_ANT_DIVERSITY_ENABLE() = 1; 421 //MTO_ANT_DIVERSITY_ENABLE() = 1;
419 //#else 422 //#else
420 //MTO_ANT_DIVERSITY_ENABLE() = 0; 423 //MTO_ANT_DIVERSITY_ENABLE() = 0;
421 //#endif 424 //#endif
422 MTO_POWER_CHANGE_ENABLE() = 1; 425 MTO_POWER_CHANGE_ENABLE() = 1;
423 MTO_PREAMBLE_CHANGE_ENABLE()= 1; 426 MTO_PREAMBLE_CHANGE_ENABLE()= 1;
424 MTO_RTS_CHANGE_ENABLE() = 0; // 1.1.29.1000 Turbo add don't support frag 427 MTO_RTS_CHANGE_ENABLE() = 0; // 1.1.29.1000 Turbo add don't support frag
425 // 20040512 Turbo add 428 // 20040512 Turbo add
426 //old_antenna[0] = 1; 429 //old_antenna[0] = 1;
427 //old_antenna[1] = 0; 430 //old_antenna[1] = 0;
428 //old_antenna[2] = 1; 431 //old_antenna[2] = 1;
429 //old_antenna[3] = 0; 432 //old_antenna[3] = 0;
430 for (i=0;i<MTO_MAX_DATA_RATE_LEVELS;i++) 433 for (i=0;i<MTO_MAX_DATA_RATE_LEVELS;i++)
431 retryrate_rec[i]=5; 434 retryrate_rec[i]=5;
432 435
433 MTO_TXFLOWCOUNT() = 0; 436 MTO_TXFLOWCOUNT() = 0;
434 //--------- DTO threshold parameters ------------- 437 //--------- DTO threshold parameters -------------
435 //MTOPARA_PERIODIC_CHECK_CYCLE() = 50; 438 //MTOPARA_PERIODIC_CHECK_CYCLE() = 50;
436 MTOPARA_PERIODIC_CHECK_CYCLE() = 10; 439 MTOPARA_PERIODIC_CHECK_CYCLE() = 10;
437 MTOPARA_RSSI_TH_FOR_ANTDIV() = 10; 440 MTOPARA_RSSI_TH_FOR_ANTDIV() = 10;
438 MTOPARA_TXCOUNT_TH_FOR_CALC_RATE() = 50; 441 MTOPARA_TXCOUNT_TH_FOR_CALC_RATE() = 50;
439 MTOPARA_TXRATE_INC_TH() = 10; 442 MTOPARA_TXRATE_INC_TH() = 10;
440 MTOPARA_TXRATE_DEC_TH() = 30; 443 MTOPARA_TXRATE_DEC_TH() = 30;
441 MTOPARA_TXRATE_EQ_TH() = 40; 444 MTOPARA_TXRATE_EQ_TH() = 40;
442 MTOPARA_TXRATE_BACKOFF() = 12; 445 MTOPARA_TXRATE_BACKOFF() = 12;
443 MTOPARA_TXRETRYRATE_REDUCE() = 6; 446 MTOPARA_TXRETRYRATE_REDUCE() = 6;
444 if ( MTO_TXPOWER_FROM_EEPROM == 0xff) 447 if ( MTO_TXPOWER_FROM_EEPROM == 0xff)
445 { 448 {
446 switch( MTO_HAL()->phy_type) 449 switch( MTO_HAL()->phy_type)
447 { 450 {
448 case RF_AIROHA_2230: 451 case RF_AIROHA_2230:
449 case RF_AIROHA_2230S: // 20060420 Add this 452 case RF_AIROHA_2230S: // 20060420 Add this
450 MTOPARA_TXPOWER_INDEX() = 46; // MAX-8 // @@ Only for AL 2230 453 MTOPARA_TXPOWER_INDEX() = 46; // MAX-8 // @@ Only for AL 2230
451 break; 454 break;
452 case RF_AIROHA_7230: 455 case RF_AIROHA_7230:
453 MTOPARA_TXPOWER_INDEX() = 49; 456 MTOPARA_TXPOWER_INDEX() = 49;
454 break; 457 break;
455 case RF_WB_242: 458 case RF_WB_242:
456 MTOPARA_TXPOWER_INDEX() = 10; 459 MTOPARA_TXPOWER_INDEX() = 10;
457 break; 460 break;
458 case RF_WB_242_1: 461 case RF_WB_242_1:
459 MTOPARA_TXPOWER_INDEX() = 24; // ->10 20060316.1 modify 462 MTOPARA_TXPOWER_INDEX() = 24; // ->10 20060316.1 modify
460 break; 463 break;
461 } 464 }
462 } 465 }
463 else //follow the setting from EEPROM 466 else //follow the setting from EEPROM
464 MTOPARA_TXPOWER_INDEX() = MTO_TXPOWER_FROM_EEPROM; 467 MTOPARA_TXPOWER_INDEX() = MTO_TXPOWER_FROM_EEPROM;
465 hal_set_rf_power(MTO_HAL(), (u8)MTOPARA_TXPOWER_INDEX()); 468 hal_set_rf_power(MTO_HAL(), (u8)MTOPARA_TXPOWER_INDEX());
466 //------------------------------------------------ 469 //------------------------------------------------
467 470
468 // For RSSI turning 20060808.4 Cancel load from EEPROM 471 // For RSSI turning 20060808.4 Cancel load from EEPROM
469 MTO_DATA().RSSI_high = -41; 472 MTO_DATA().RSSI_high = -41;
470 MTO_DATA().RSSI_low = -60; 473 MTO_DATA().RSSI_low = -60;
471 } 474 }
472 475
473 //---------------------------------------------------------------------------// 476 //---------------------------------------------------------------------------//
474 static u32 DTO_Rx_Info[13][3]; 477 static u32 DTO_Rx_Info[13][3];
475 static u32 DTO_RxCRCFail_Info[13][3]; 478 static u32 DTO_RxCRCFail_Info[13][3];
476 static u32 AntennaToggleBkoffTimer=5; 479 static u32 AntennaToggleBkoffTimer=5;
477 typedef struct{ 480 typedef struct{
478 int RxRate; 481 int RxRate;
479 int RxRatePkts; 482 int RxRatePkts;
480 int index; 483 int index;
481 }RXRATE_ANT; 484 }RXRATE_ANT;
482 RXRATE_ANT RxRatePeakAnt[3]; 485 RXRATE_ANT RxRatePeakAnt[3];
483 486
484 #define ANT0 0 487 #define ANT0 0
485 #define ANT1 1 488 #define ANT1 1
486 #define OLD_ANT 2 489 #define OLD_ANT 2
487 490
488 void SearchPeakRxRate(int index) 491 void SearchPeakRxRate(int index)
489 { 492 {
490 int i; 493 int i;
491 RxRatePeakAnt[index].RxRatePkts=0; 494 RxRatePeakAnt[index].RxRatePkts=0;
492 //Find out the best rx rate which is used on different antenna 495 //Find out the best rx rate which is used on different antenna
493 for(i=1;i<13;i++) 496 for(i=1;i<13;i++)
494 { 497 {
495 if(DTO_Rx_Info[i][index] > (u32) RxRatePeakAnt[index].RxRatePkts) 498 if(DTO_Rx_Info[i][index] > (u32) RxRatePeakAnt[index].RxRatePkts)
496 { 499 {
497 RxRatePeakAnt[index].RxRatePkts = DTO_Rx_Info[i][index]; 500 RxRatePeakAnt[index].RxRatePkts = DTO_Rx_Info[i][index];
498 RxRatePeakAnt[index].RxRate = rate_tbl[i]; 501 RxRatePeakAnt[index].RxRate = rate_tbl[i];
499 RxRatePeakAnt[index].index = i; 502 RxRatePeakAnt[index].index = i;
500 } 503 }
501 } 504 }
502 } 505 }
503 506
504 void ResetDTO_RxInfo(int index, MTO_FUNC_INPUT) 507 void ResetDTO_RxInfo(int index, MTO_FUNC_INPUT)
505 { 508 {
506 int i; 509 int i;
507 510
508 #ifdef _PE_DTO_DUMP_ 511 #ifdef _PE_DTO_DUMP_
509 WBDEBUG(("ResetDTOrx\n")); 512 WBDEBUG(("ResetDTOrx\n"));
510 #endif 513 #endif
511 514
512 for(i=0;i<13;i++) 515 for(i=0;i<13;i++)
513 DTO_Rx_Info[i][index] = MTO_HAL()->rx_ok_count[i]; 516 DTO_Rx_Info[i][index] = MTO_HAL()->rx_ok_count[i];
514 517
515 for(i=0;i<13;i++) 518 for(i=0;i<13;i++)
516 DTO_RxCRCFail_Info[i][index] = MTO_HAL()->rx_err_count[i]; 519 DTO_RxCRCFail_Info[i][index] = MTO_HAL()->rx_err_count[i];
517 520
518 TotalTxPkt = 0; 521 TotalTxPkt = 0;
519 TotalTxPktRetry = 0; 522 TotalTxPktRetry = 0;
520 } 523 }
521 524
522 void GetDTO_RxInfo(int index, MTO_FUNC_INPUT) 525 void GetDTO_RxInfo(int index, MTO_FUNC_INPUT)
523 { 526 {
524 int i; 527 int i;
525 528
526 #ifdef _PE_DTO_DUMP_ 529 #ifdef _PE_DTO_DUMP_
527 WBDEBUG(("GetDTOrx\n")); 530 WBDEBUG(("GetDTOrx\n"));
528 #endif 531 #endif
529 532
530 //PDEBUG(("[MTO]:DTO_Rx_Info[%d]=%d, rx_ok_count=%d\n", index, DTO_Rx_Info[0][index], phw_data->rx_ok_count[0])); 533 //PDEBUG(("[MTO]:DTO_Rx_Info[%d]=%d, rx_ok_count=%d\n", index, DTO_Rx_Info[0][index], phw_data->rx_ok_count[0]));
531 for(i=0;i<13;i++) 534 for(i=0;i<13;i++)
532 DTO_Rx_Info[i][index] = abs(MTO_HAL()->rx_ok_count[i] - DTO_Rx_Info[i][index]); 535 DTO_Rx_Info[i][index] = abs(MTO_HAL()->rx_ok_count[i] - DTO_Rx_Info[i][index]);
533 if(DTO_Rx_Info[0][index]==0) DTO_Rx_Info[0][index] = 1; 536 if(DTO_Rx_Info[0][index]==0) DTO_Rx_Info[0][index] = 1;
534 537
535 for(i=0;i<13;i++) 538 for(i=0;i<13;i++)
536 DTO_RxCRCFail_Info[i][index] = MTO_HAL()->rx_err_count[i] - DTO_RxCRCFail_Info[i][index]; 539 DTO_RxCRCFail_Info[i][index] = MTO_HAL()->rx_err_count[i] - DTO_RxCRCFail_Info[i][index];
537 540
538 TxPktPerAnt[index] = TotalTxPkt; 541 TxPktPerAnt[index] = TotalTxPkt;
539 TxPktRetryPerAnt[index] = TotalTxPktRetry; 542 TxPktRetryPerAnt[index] = TotalTxPktRetry;
540 TotalTxPkt = 0; 543 TotalTxPkt = 0;
541 TotalTxPktRetry = 0; 544 TotalTxPktRetry = 0;
542 } 545 }
543 546
544 void OutputDebugInfo(int index1, int index2) 547 void OutputDebugInfo(int index1, int index2)
545 { 548 {
546 #ifdef _PE_DTO_DUMP_ 549 #ifdef _PE_DTO_DUMP_
547 WBDEBUG(("[HHDTO]:Total Rx (%d)\t\t(%d) \n ", DTO_Rx_Info[0][index1], DTO_Rx_Info[0][index2])); 550 WBDEBUG(("[HHDTO]:Total Rx (%d)\t\t(%d) \n ", DTO_Rx_Info[0][index1], DTO_Rx_Info[0][index2]));
548 WBDEBUG(("[HHDTO]:RECEIVE RSSI: (%d)\t\t(%d) \n ", RXRSSIANT[index1], RXRSSIANT[index2])); 551 WBDEBUG(("[HHDTO]:RECEIVE RSSI: (%d)\t\t(%d) \n ", RXRSSIANT[index1], RXRSSIANT[index2]));
549 WBDEBUG(("[HHDTO]:TX packet correct rate: (%d)%%\t\t(%d)%% \n ",Divide(TxPktPerAnt[index1]*100,TxPktRetryPerAnt[index1]), Divide(TxPktPerAnt[index2]*100,TxPktRetryPerAnt[index2]))); 552 WBDEBUG(("[HHDTO]:TX packet correct rate: (%d)%%\t\t(%d)%% \n ",Divide(TxPktPerAnt[index1]*100,TxPktRetryPerAnt[index1]), Divide(TxPktPerAnt[index2]*100,TxPktRetryPerAnt[index2])));
550 #endif 553 #endif
551 { 554 {
552 int tmp1, tmp2; 555 int tmp1, tmp2;
553 #ifdef _PE_DTO_DUMP_ 556 #ifdef _PE_DTO_DUMP_
554 WBDEBUG(("[HHDTO]:Total Tx (%d)\t\t(%d) \n ", TxPktPerAnt[index1], TxPktPerAnt[index2])); 557 WBDEBUG(("[HHDTO]:Total Tx (%d)\t\t(%d) \n ", TxPktPerAnt[index1], TxPktPerAnt[index2]));
555 WBDEBUG(("[HHDTO]:Total Tx retry (%d)\t\t(%d) \n ", TxPktRetryPerAnt[index1], TxPktRetryPerAnt[index2])); 558 WBDEBUG(("[HHDTO]:Total Tx retry (%d)\t\t(%d) \n ", TxPktRetryPerAnt[index1], TxPktRetryPerAnt[index2]));
556 #endif 559 #endif
557 tmp1 = TxPktPerAnt[index1] + DTO_Rx_Info[0][index1]; 560 tmp1 = TxPktPerAnt[index1] + DTO_Rx_Info[0][index1];
558 tmp2 = TxPktPerAnt[index2] + DTO_Rx_Info[0][index2]; 561 tmp2 = TxPktPerAnt[index2] + DTO_Rx_Info[0][index2];
559 #ifdef _PE_DTO_DUMP_ 562 #ifdef _PE_DTO_DUMP_
560 WBDEBUG(("[HHDTO]:Total Tx+RX (%d)\t\t(%d) \n ", tmp1, tmp2)); 563 WBDEBUG(("[HHDTO]:Total Tx+RX (%d)\t\t(%d) \n ", tmp1, tmp2));
561 #endif 564 #endif
562 } 565 }
563 } 566 }
564 567
565 unsigned char TxDominate(int index) 568 unsigned char TxDominate(int index)
566 { 569 {
567 int tmp; 570 int tmp;
568 571
569 tmp = TxPktPerAnt[index] + DTO_Rx_Info[0][index]; 572 tmp = TxPktPerAnt[index] + DTO_Rx_Info[0][index];
570 573
571 if(Divide(TxPktPerAnt[index]*100, tmp) > 40) 574 if(Divide(TxPktPerAnt[index]*100, tmp) > 40)
572 return true; 575 return true;
573 else 576 else
574 return false; 577 return false;
575 } 578 }
576 579
577 unsigned char CmpTxRetryRate(int index1, int index2) 580 unsigned char CmpTxRetryRate(int index1, int index2)
578 { 581 {
579 int tx_retry_rate1, tx_retry_rate2; 582 int tx_retry_rate1, tx_retry_rate2;
580 tx_retry_rate1 = Divide((TxPktRetryPerAnt[index1] - TxPktPerAnt[index1])*100, TxPktRetryPerAnt[index1]); 583 tx_retry_rate1 = Divide((TxPktRetryPerAnt[index1] - TxPktPerAnt[index1])*100, TxPktRetryPerAnt[index1]);
581 tx_retry_rate2 = Divide((TxPktRetryPerAnt[index2] - TxPktPerAnt[index2])*100, TxPktRetryPerAnt[index2]); 584 tx_retry_rate2 = Divide((TxPktRetryPerAnt[index2] - TxPktPerAnt[index2])*100, TxPktRetryPerAnt[index2]);
582 #ifdef _PE_DTO_DUMP_ 585 #ifdef _PE_DTO_DUMP_
583 WBDEBUG(("[MTO]:TxRetry Ant0: (%d%%) Ant1: (%d%%) \n ", tx_retry_rate1, tx_retry_rate2)); 586 WBDEBUG(("[MTO]:TxRetry Ant0: (%d%%) Ant1: (%d%%) \n ", tx_retry_rate1, tx_retry_rate2));
584 #endif 587 #endif
585 588
586 if(tx_retry_rate1 > tx_retry_rate2) 589 if(tx_retry_rate1 > tx_retry_rate2)
587 return true; 590 return true;
588 else 591 else
589 return false; 592 return false;
590 } 593 }
591 594
592 void GetFreshAntennaData(MTO_FUNC_INPUT) 595 void GetFreshAntennaData(MTO_FUNC_INPUT)
593 { 596 {
594 u8 x; 597 u8 x;
595 598
596 x = hal_get_antenna_number(MTO_HAL()); 599 x = hal_get_antenna_number(MTO_HAL());
597 //hal_get_bss_pk_cnt(MTO_HAL()); 600 //hal_get_bss_pk_cnt(MTO_HAL());
598 //hal_get_est_sq3(MTO_HAL(), 1); 601 //hal_get_est_sq3(MTO_HAL(), 1);
599 old_antenna[0] = x; 602 old_antenna[0] = x;
600 //if this is the function for timer 603 //if this is the function for timer
601 ResetDTO_RxInfo(x, MTO_FUNC_INPUT_DATA); 604 ResetDTO_RxInfo(x, MTO_FUNC_INPUT_DATA);
602 if(AntennaToggleBkoffTimer) 605 if(AntennaToggleBkoffTimer)
603 AntennaToggleBkoffTimer--; 606 AntennaToggleBkoffTimer--;
604 if (abs(last_rate_ant-MTO_RATE_LEVEL())>1) //backoff timer reset 607 if (abs(last_rate_ant-MTO_RATE_LEVEL())>1) //backoff timer reset
605 AntennaToggleBkoffTimer=0; 608 AntennaToggleBkoffTimer=0;
606 609
607 if (MTO_ANT_DIVERSITY() != MTO_ANTENNA_DIVERSITY_ON || 610 if (MTO_ANT_DIVERSITY() != MTO_ANTENNA_DIVERSITY_ON ||
608 MTO_ANT_DIVERSITY_ENABLE() != 1) 611 MTO_ANT_DIVERSITY_ENABLE() != 1)
609 AntennaToggleBkoffTimer=1; 612 AntennaToggleBkoffTimer=1;
610 #ifdef _PE_DTO_DUMP_ 613 #ifdef _PE_DTO_DUMP_
611 WBDEBUG(("[HHDTO]:**last data rate=%d,now data rate=%d**antenna toggle timer=%d",last_rate_ant,MTO_RATE_LEVEL(),AntennaToggleBkoffTimer)); 614 WBDEBUG(("[HHDTO]:**last data rate=%d,now data rate=%d**antenna toggle timer=%d",last_rate_ant,MTO_RATE_LEVEL(),AntennaToggleBkoffTimer));
612 #endif 615 #endif
613 last_rate_ant=MTO_RATE_LEVEL(); 616 last_rate_ant=MTO_RATE_LEVEL();
614 if(AntennaToggleBkoffTimer==0) 617 if(AntennaToggleBkoffTimer==0)
615 { 618 {
616 MTO_TOGGLE_STATE() = TOGGLE_STATE_WAIT0; 619 MTO_TOGGLE_STATE() = TOGGLE_STATE_WAIT0;
617 #ifdef _PE_DTO_DUMP_ 620 #ifdef _PE_DTO_DUMP_
618 WBDEBUG(("[HHDTO]:===state is starting==for antenna toggle===")); 621 WBDEBUG(("[HHDTO]:===state is starting==for antenna toggle==="));
619 #endif 622 #endif
620 } 623 }
621 else 624 else
622 MTO_TOGGLE_STATE() = TOGGLE_STATE_IDLE; 625 MTO_TOGGLE_STATE() = TOGGLE_STATE_IDLE;
623 626
624 if ((MTO_BACKOFF_TMR()!=0)&&(MTO_RATE_LEVEL()>MTO_DataRateAvailableLevel - 3)) 627 if ((MTO_BACKOFF_TMR()!=0)&&(MTO_RATE_LEVEL()>MTO_DataRateAvailableLevel - 3))
625 { 628 {
626 MTO_TOGGLE_STATE() = TOGGLE_STATE_IDLE; 629 MTO_TOGGLE_STATE() = TOGGLE_STATE_IDLE;
627 #ifdef _PE_DTO_DUMP_ 630 #ifdef _PE_DTO_DUMP_
628 WBDEBUG(("[HHDTO]:===the data rate is %d (good)and will not toogle ===",MTO_DATA_RATE()>>1)); 631 WBDEBUG(("[HHDTO]:===the data rate is %d (good)and will not toogle ===",MTO_DATA_RATE()>>1));
629 #endif 632 #endif
630 } 633 }
631 634
632 635
633 } 636 }
634 637
635 int WB_PCR[2]; //packet correct rate 638 int WB_PCR[2]; //packet correct rate
636 639
637 void AntennaToggleState(MTO_FUNC_INPUT) 640 void AntennaToggleState(MTO_FUNC_INPUT)
638 { 641 {
639 int decideantflag = 0; 642 int decideantflag = 0;
640 u8 x; 643 u8 x;
641 s32 rssi; 644 s32 rssi;
642 645
643 if(MTO_ANT_DIVERSITY_ENABLE() != 1) 646 if(MTO_ANT_DIVERSITY_ENABLE() != 1)
644 return; 647 return;
645 x = hal_get_antenna_number(MTO_HAL()); 648 x = hal_get_antenna_number(MTO_HAL());
646 switch(MTO_TOGGLE_STATE()) 649 switch(MTO_TOGGLE_STATE())
647 { 650 {
648 651
649 //Missing..... 652 //Missing.....
650 case TOGGLE_STATE_IDLE: 653 case TOGGLE_STATE_IDLE:
651 case TOGGLE_STATE_BKOFF: 654 case TOGGLE_STATE_BKOFF:
652 break;; 655 break;;
653 656
654 case TOGGLE_STATE_WAIT0://======== 657 case TOGGLE_STATE_WAIT0://========
655 GetDTO_RxInfo(x, MTO_FUNC_INPUT_DATA); 658 GetDTO_RxInfo(x, MTO_FUNC_INPUT_DATA);
656 sme_get_rssi(MTO_FUNC_INPUT_DATA, &rssi); 659 sme_get_rssi(MTO_FUNC_INPUT_DATA, &rssi);
657 RXRSSIANT[x] = rssi; 660 RXRSSIANT[x] = rssi;
658 #ifdef _PE_DTO_DUMP_ 661 #ifdef _PE_DTO_DUMP_
659 WBDEBUG(("[HHDTO] **wait0==== Collecting Ant%d--rssi=%d\n", x,RXRSSIANT[x])); 662 WBDEBUG(("[HHDTO] **wait0==== Collecting Ant%d--rssi=%d\n", x,RXRSSIANT[x]));
660 #endif 663 #endif
661 664
662 //change antenna and reset the data at changed antenna 665 //change antenna and reset the data at changed antenna
663 x = (~x) & 0x01; 666 x = (~x) & 0x01;
664 MTO_ANT_SEL() = x; 667 MTO_ANT_SEL() = x;
665 hal_set_antenna_number(MTO_HAL(), MTO_ANT_SEL()); 668 hal_set_antenna_number(MTO_HAL(), MTO_ANT_SEL());
666 LOCAL_ANTENNA_NO() = x; 669 LOCAL_ANTENNA_NO() = x;
667 670
668 MTO_TOGGLE_STATE() = TOGGLE_STATE_WAIT1;//go to wait1 671 MTO_TOGGLE_STATE() = TOGGLE_STATE_WAIT1;//go to wait1
669 ResetDTO_RxInfo(x, MTO_FUNC_INPUT_DATA); 672 ResetDTO_RxInfo(x, MTO_FUNC_INPUT_DATA);
670 break; 673 break;
671 case TOGGLE_STATE_WAIT1://=====wait1 674 case TOGGLE_STATE_WAIT1://=====wait1
672 //MTO_CNT_ANT(x) = hal_get_bss_pk_cnt(MTO_HAL()); 675 //MTO_CNT_ANT(x) = hal_get_bss_pk_cnt(MTO_HAL());
673 //RXRSSIANT[x] = hal_get_rssi(MTO_HAL()); 676 //RXRSSIANT[x] = hal_get_rssi(MTO_HAL());
674 sme_get_rssi(MTO_FUNC_INPUT_DATA, &rssi); 677 sme_get_rssi(MTO_FUNC_INPUT_DATA, &rssi);
675 RXRSSIANT[x] = rssi; 678 RXRSSIANT[x] = rssi;
676 GetDTO_RxInfo(x, MTO_FUNC_INPUT_DATA); 679 GetDTO_RxInfo(x, MTO_FUNC_INPUT_DATA);
677 #ifdef _PE_DTO_DUMP_ 680 #ifdef _PE_DTO_DUMP_
678 WBDEBUG(("[HHDTO] **wait1==== Collecting Ant%d--rssi=%d\n", x,RXRSSIANT[x])); 681 WBDEBUG(("[HHDTO] **wait1==== Collecting Ant%d--rssi=%d\n", x,RXRSSIANT[x]));
679 #endif 682 #endif
680 MTO_TOGGLE_STATE() = TOGGLE_STATE_MAKEDESISION; 683 MTO_TOGGLE_STATE() = TOGGLE_STATE_MAKEDESISION;
681 break; 684 break;
682 case TOGGLE_STATE_MAKEDESISION: 685 case TOGGLE_STATE_MAKEDESISION:
683 #ifdef _PE_DTO_DUMP_ 686 #ifdef _PE_DTO_DUMP_
684 WBDEBUG(("[HHDTO]:Ant--0-----------------1---\n")); 687 WBDEBUG(("[HHDTO]:Ant--0-----------------1---\n"));
685 OutputDebugInfo(ANT0,ANT1); 688 OutputDebugInfo(ANT0,ANT1);
686 #endif 689 #endif
687 //PDEBUG(("[HHDTO] **decision====\n ")); 690 //PDEBUG(("[HHDTO] **decision====\n "));
688 691
689 //=====following is the decision produrce 692 //=====following is the decision produrce
690 // 693 //
691 // first: compare the rssi if difference >10 694 // first: compare the rssi if difference >10
692 // select the larger one 695 // select the larger one
693 // ,others go to second 696 // ,others go to second
694 // second: comapre the tx+rx packet count if difference >100 697 // second: comapre the tx+rx packet count if difference >100
695 // use larger total packets antenna 698 // use larger total packets antenna
696 // third::compare the tx PER if packets>20 699 // third::compare the tx PER if packets>20
697 // if difference >5% using the bigger one 700 // if difference >5% using the bigger one
698 // 701 //
699 // fourth:compare the RX PER if packets>20 702 // fourth:compare the RX PER if packets>20
700 // if PER difference <5% 703 // if PER difference <5%
701 // using old antenna 704 // using old antenna
702 // 705 //
703 // 706 //
704 if (abs(RXRSSIANT[ANT0]-RXRSSIANT[ANT1]) > MTOPARA_RSSI_TH_FOR_ANTDIV())//====rssi_th 707 if (abs(RXRSSIANT[ANT0]-RXRSSIANT[ANT1]) > MTOPARA_RSSI_TH_FOR_ANTDIV())//====rssi_th
705 { 708 {
706 if (RXRSSIANT[ANT0]>RXRSSIANT[ANT1]) 709 if (RXRSSIANT[ANT0]>RXRSSIANT[ANT1])
707 { 710 {
708 decideantflag=1; 711 decideantflag=1;
709 MTO_ANT_MAC() = ANT0; 712 MTO_ANT_MAC() = ANT0;
710 } 713 }
711 else 714 else
712 { 715 {
713 decideantflag=1; 716 decideantflag=1;
714 MTO_ANT_MAC() = ANT1; 717 MTO_ANT_MAC() = ANT1;
715 } 718 }
716 #ifdef _PE_DTO_DUMP_ 719 #ifdef _PE_DTO_DUMP_
717 WBDEBUG(("Select antenna by RSSI\n")); 720 WBDEBUG(("Select antenna by RSSI\n"));
718 #endif 721 #endif
719 } 722 }
720 else if (abs(TxPktPerAnt[ANT0] + DTO_Rx_Info[0][ANT0]-TxPktPerAnt[ANT1]-DTO_Rx_Info[0][ANT1])<50)//=====total packet_th 723 else if (abs(TxPktPerAnt[ANT0] + DTO_Rx_Info[0][ANT0]-TxPktPerAnt[ANT1]-DTO_Rx_Info[0][ANT1])<50)//=====total packet_th
721 { 724 {
722 #ifdef _PE_DTO_DUMP_ 725 #ifdef _PE_DTO_DUMP_
723 WBDEBUG(("Total tx/rx is close\n")); 726 WBDEBUG(("Total tx/rx is close\n"));
724 #endif 727 #endif
725 if (TxDominate(ANT0) && TxDominate(ANT1)) 728 if (TxDominate(ANT0) && TxDominate(ANT1))
726 { 729 {
727 if ((TxPktPerAnt[ANT0]>10) && (TxPktPerAnt[ANT1]>10))//====tx packet_th 730 if ((TxPktPerAnt[ANT0]>10) && (TxPktPerAnt[ANT1]>10))//====tx packet_th
728 { 731 {
729 WB_PCR[ANT0]=Divide(TxPktPerAnt[ANT0]*100,TxPktRetryPerAnt[ANT0]); 732 WB_PCR[ANT0]=Divide(TxPktPerAnt[ANT0]*100,TxPktRetryPerAnt[ANT0]);
730 WB_PCR[ANT1]=Divide(TxPktPerAnt[ANT1]*100,TxPktRetryPerAnt[ANT1]); 733 WB_PCR[ANT1]=Divide(TxPktPerAnt[ANT1]*100,TxPktRetryPerAnt[ANT1]);
731 if (abs(WB_PCR[ANT0]-WB_PCR[ANT1])>5)// tx PER_th 734 if (abs(WB_PCR[ANT0]-WB_PCR[ANT1])>5)// tx PER_th
732 { 735 {
733 #ifdef _PE_DTO_DUMP_ 736 #ifdef _PE_DTO_DUMP_
734 WBDEBUG(("Decide by Tx correct rate\n")); 737 WBDEBUG(("Decide by Tx correct rate\n"));
735 #endif 738 #endif
736 if (WB_PCR[ANT0]>WB_PCR[ANT1]) 739 if (WB_PCR[ANT0]>WB_PCR[ANT1])
737 { 740 {
738 decideantflag=1; 741 decideantflag=1;
739 MTO_ANT_MAC() = ANT0; 742 MTO_ANT_MAC() = ANT0;
740 } 743 }
741 else 744 else
742 { 745 {
743 decideantflag=1; 746 decideantflag=1;
744 MTO_ANT_MAC() = ANT1; 747 MTO_ANT_MAC() = ANT1;
745 } 748 }
746 } 749 }
747 else 750 else
748 { 751 {
749 decideantflag=0; 752 decideantflag=0;
750 untogglecount++; 753 untogglecount++;
751 MTO_ANT_MAC() = old_antenna[0]; 754 MTO_ANT_MAC() = old_antenna[0];
752 } 755 }
753 } 756 }
754 else 757 else
755 { 758 {
756 decideantflag=0; 759 decideantflag=0;
757 MTO_ANT_MAC() = old_antenna[0]; 760 MTO_ANT_MAC() = old_antenna[0];
758 } 761 }
759 } 762 }
760 else if ((DTO_Rx_Info[0][ANT0]>10)&&(DTO_Rx_Info[0][ANT1]>10))//rx packet th 763 else if ((DTO_Rx_Info[0][ANT0]>10)&&(DTO_Rx_Info[0][ANT1]>10))//rx packet th
761 { 764 {
762 #ifdef _PE_DTO_DUMP_ 765 #ifdef _PE_DTO_DUMP_
763 WBDEBUG(("Decide by Rx\n")); 766 WBDEBUG(("Decide by Rx\n"));
764 #endif 767 #endif
765 if (abs(DTO_Rx_Info[0][ANT0] - DTO_Rx_Info[0][ANT1])>50) 768 if (abs(DTO_Rx_Info[0][ANT0] - DTO_Rx_Info[0][ANT1])>50)
766 { 769 {
767 if (DTO_Rx_Info[0][ANT0] > DTO_Rx_Info[0][ANT1]) 770 if (DTO_Rx_Info[0][ANT0] > DTO_Rx_Info[0][ANT1])
768 { 771 {
769 decideantflag=1; 772 decideantflag=1;
770 MTO_ANT_MAC() = ANT0; 773 MTO_ANT_MAC() = ANT0;
771 } 774 }
772 else 775 else
773 { 776 {
774 decideantflag=1; 777 decideantflag=1;
775 MTO_ANT_MAC() = ANT1; 778 MTO_ANT_MAC() = ANT1;
776 } 779 }
777 } 780 }
778 else 781 else
779 { 782 {
780 decideantflag=0; 783 decideantflag=0;
781 untogglecount++; 784 untogglecount++;
782 MTO_ANT_MAC() = old_antenna[0]; 785 MTO_ANT_MAC() = old_antenna[0];
783 } 786 }
784 } 787 }
785 else 788 else
786 { 789 {
787 decideantflag=0; 790 decideantflag=0;
788 MTO_ANT_MAC() = old_antenna[0]; 791 MTO_ANT_MAC() = old_antenna[0];
789 } 792 }
790 } 793 }
791 else if ((TxPktPerAnt[ANT0]+DTO_Rx_Info[0][ANT0])>(TxPktPerAnt[ANT1]+DTO_Rx_Info[0][ANT1]))//use more packekts 794 else if ((TxPktPerAnt[ANT0]+DTO_Rx_Info[0][ANT0])>(TxPktPerAnt[ANT1]+DTO_Rx_Info[0][ANT1]))//use more packekts
792 { 795 {
793 #ifdef _PE_DTO_DUMP_ 796 #ifdef _PE_DTO_DUMP_
794 WBDEBUG(("decide by total tx/rx : ANT 0\n")); 797 WBDEBUG(("decide by total tx/rx : ANT 0\n"));
795 #endif 798 #endif
796 799
797 decideantflag=1; 800 decideantflag=1;
798 MTO_ANT_MAC() = ANT0; 801 MTO_ANT_MAC() = ANT0;
799 } 802 }
800 else 803 else
801 { 804 {
802 #ifdef _PE_DTO_DUMP_ 805 #ifdef _PE_DTO_DUMP_
803 WBDEBUG(("decide by total tx/rx : ANT 1\n")); 806 WBDEBUG(("decide by total tx/rx : ANT 1\n"));
804 #endif 807 #endif
805 decideantflag=1; 808 decideantflag=1;
806 MTO_ANT_MAC() = ANT1; 809 MTO_ANT_MAC() = ANT1;
807 810
808 } 811 }
809 //this is force ant toggle 812 //this is force ant toggle
810 if (decideantflag==1) 813 if (decideantflag==1)
811 untogglecount=0; 814 untogglecount=0;
812 815
813 untogglecount=untogglecount%4; 816 untogglecount=untogglecount%4;
814 if (untogglecount==3) //change antenna 817 if (untogglecount==3) //change antenna
815 MTO_ANT_MAC() = ((~old_antenna[0]) & 0x1); 818 MTO_ANT_MAC() = ((~old_antenna[0]) & 0x1);
816 #ifdef _PE_DTO_DUMP_ 819 #ifdef _PE_DTO_DUMP_
817 WBDEBUG(("[HHDTO]:==================untoggle-count=%d",untogglecount)); 820 WBDEBUG(("[HHDTO]:==================untoggle-count=%d",untogglecount));
818 #endif 821 #endif
819 822
820 823
821 824
822 825
823 //PDEBUG(("[HHDTO] **********************************DTO ENABLE=%d",MTO_ANT_DIVERSITY_ENABLE())); 826 //PDEBUG(("[HHDTO] **********************************DTO ENABLE=%d",MTO_ANT_DIVERSITY_ENABLE()));
824 if(MTO_ANT_DIVERSITY_ENABLE() == 1) 827 if(MTO_ANT_DIVERSITY_ENABLE() == 1)
825 { 828 {
826 MTO_ANT_SEL() = MTO_ANT_MAC(); 829 MTO_ANT_SEL() = MTO_ANT_MAC();
827 hal_set_antenna_number(MTO_HAL(), MTO_ANT_SEL()); 830 hal_set_antenna_number(MTO_HAL(), MTO_ANT_SEL());
828 LOCAL_ANTENNA_NO() = MTO_ANT_SEL(); 831 LOCAL_ANTENNA_NO() = MTO_ANT_SEL();
829 #ifdef _PE_DTO_DUMP_ 832 #ifdef _PE_DTO_DUMP_
830 WBDEBUG(("[HHDTO] ==decision==*******antflag=%d******************selected antenna=%d\n",decideantflag,MTO_ANT_SEL())); 833 WBDEBUG(("[HHDTO] ==decision==*******antflag=%d******************selected antenna=%d\n",decideantflag,MTO_ANT_SEL()));
831 #endif 834 #endif
832 } 835 }
833 if (decideantflag) 836 if (decideantflag)
834 { 837 {
835 old_antenna[3]=old_antenna[2];//store antenna info 838 old_antenna[3]=old_antenna[2];//store antenna info
836 old_antenna[2]=old_antenna[1]; 839 old_antenna[2]=old_antenna[1];
837 old_antenna[1]=old_antenna[0]; 840 old_antenna[1]=old_antenna[0];
838 old_antenna[0]= MTO_ANT_MAC(); 841 old_antenna[0]= MTO_ANT_MAC();
839 } 842 }
840 #ifdef _PE_DTO_DUMP_ 843 #ifdef _PE_DTO_DUMP_
841 WBDEBUG(("[HHDTO]:**old antenna=[%d][%d][%d][%d]\n",old_antenna[0],old_antenna[1],old_antenna[2],old_antenna[3])); 844 WBDEBUG(("[HHDTO]:**old antenna=[%d][%d][%d][%d]\n",old_antenna[0],old_antenna[1],old_antenna[2],old_antenna[3]));
842 #endif 845 #endif
843 if (old_antenna[0]!=old_antenna[1]) 846 if (old_antenna[0]!=old_antenna[1])
844 AntennaToggleBkoffTimer=0; 847 AntennaToggleBkoffTimer=0;
845 else if (old_antenna[1]!=old_antenna[2]) 848 else if (old_antenna[1]!=old_antenna[2])
846 AntennaToggleBkoffTimer=1; 849 AntennaToggleBkoffTimer=1;
847 else if (old_antenna[2]!=old_antenna[3]) 850 else if (old_antenna[2]!=old_antenna[3])
848 AntennaToggleBkoffTimer=2; 851 AntennaToggleBkoffTimer=2;
849 else 852 else
850 AntennaToggleBkoffTimer=4; 853 AntennaToggleBkoffTimer=4;
851 854
852 #ifdef _PE_DTO_DUMP_ 855 #ifdef _PE_DTO_DUMP_
853 WBDEBUG(("[HHDTO]:**back off timer=%d",AntennaToggleBkoffTimer)); 856 WBDEBUG(("[HHDTO]:**back off timer=%d",AntennaToggleBkoffTimer));
854 #endif 857 #endif
855 858
856 ResetDTO_RxInfo(MTO_ANT_MAC(), MTO_FUNC_INPUT_DATA); 859 ResetDTO_RxInfo(MTO_ANT_MAC(), MTO_FUNC_INPUT_DATA);
857 if (AntennaToggleBkoffTimer==0 && decideantflag) 860 if (AntennaToggleBkoffTimer==0 && decideantflag)
858 MTO_TOGGLE_STATE() = TOGGLE_STATE_WAIT0; 861 MTO_TOGGLE_STATE() = TOGGLE_STATE_WAIT0;
859 else 862 else
860 MTO_TOGGLE_STATE() = TOGGLE_STATE_IDLE; 863 MTO_TOGGLE_STATE() = TOGGLE_STATE_IDLE;
861 break; 864 break;
862 } 865 }
863 866
864 } 867 }
865 868
866 void multiagc(MTO_FUNC_INPUT, u8 high_gain_mode ) 869 void multiagc(MTO_FUNC_INPUT, u8 high_gain_mode )
867 { 870 {
868 s32 rssi; 871 s32 rssi;
869 hw_data_t *pHwData = MTO_HAL(); 872 hw_data_t *pHwData = MTO_HAL();
870 873
871 sme_get_rssi(MTO_FUNC_INPUT_DATA, &rssi); 874 sme_get_rssi(MTO_FUNC_INPUT_DATA, &rssi);
872 875
873 if( (RF_WB_242 == pHwData->phy_type) || 876 if( (RF_WB_242 == pHwData->phy_type) ||
874 (RF_WB_242_1 == pHwData->phy_type) ) // 20060619.5 Add 877 (RF_WB_242_1 == pHwData->phy_type) ) // 20060619.5 Add
875 { 878 {
876 if (high_gain_mode==1) 879 if (high_gain_mode==1)
877 { 880 {
878 //hw_set_dxx_reg(phw_data, 0x0C, 0xf8f52230); 881 //hw_set_dxx_reg(phw_data, 0x0C, 0xf8f52230);
879 //hw_set_dxx_reg(phw_data, 0x20, 0x06C43440); 882 //hw_set_dxx_reg(phw_data, 0x20, 0x06C43440);
880 Wb35Reg_Write( pHwData, 0x100C, 0xF2F32232 ); // 940916 0xf8f52230 ); 883 Wb35Reg_Write( pHwData, 0x100C, 0xF2F32232 ); // 940916 0xf8f52230 );
881 Wb35Reg_Write( pHwData, 0x1020, 0x04cb3440 ); // 940915 0x06C43440 884 Wb35Reg_Write( pHwData, 0x1020, 0x04cb3440 ); // 940915 0x06C43440
882 } 885 }
883 else if (high_gain_mode==0) 886 else if (high_gain_mode==0)
884 { 887 {
885 //hw_set_dxx_reg(phw_data, 0x0C, 0xEEEE000D); 888 //hw_set_dxx_reg(phw_data, 0x0C, 0xEEEE000D);
886 //hw_set_dxx_reg(phw_data, 0x20, 0x06c41440); 889 //hw_set_dxx_reg(phw_data, 0x20, 0x06c41440);
887 Wb35Reg_Write( pHwData, 0x100C, 0xEEEE000D ); 890 Wb35Reg_Write( pHwData, 0x100C, 0xEEEE000D );
888 Wb35Reg_Write( pHwData, 0x1020, 0x04cb1440 ); // 940915 0x06c41440 891 Wb35Reg_Write( pHwData, 0x1020, 0x04cb1440 ); // 940915 0x06c41440
889 } 892 }
890 #ifdef _PE_DTO_DUMP_ 893 #ifdef _PE_DTO_DUMP_
891 WBDEBUG(("[HHDTOAGC] **rssi=%d, high gain mode=%d", rssi, high_gain_mode)); 894 WBDEBUG(("[HHDTOAGC] **rssi=%d, high gain mode=%d", rssi, high_gain_mode));
892 #endif 895 #endif
893 } 896 }
894 } 897 }
895 898
896 void TxPwrControl(MTO_FUNC_INPUT) 899 void TxPwrControl(MTO_FUNC_INPUT)
897 { 900 {
898 s32 rssi; 901 s32 rssi;
899 hw_data_t *pHwData = MTO_HAL(); 902 hw_data_t *pHwData = MTO_HAL();
900 903
901 sme_get_rssi(MTO_FUNC_INPUT_DATA, &rssi); 904 sme_get_rssi(MTO_FUNC_INPUT_DATA, &rssi);
902 if( (RF_WB_242 == pHwData->phy_type) || 905 if( (RF_WB_242 == pHwData->phy_type) ||
903 (RF_WB_242_1 == pHwData->phy_type) ) // 20060619.5 Add 906 (RF_WB_242_1 == pHwData->phy_type) ) // 20060619.5 Add
904 { 907 {
905 static u8 high_gain_mode; //this is for winbond RF switch LNA 908 static u8 high_gain_mode; //this is for winbond RF switch LNA
906 //using different register setting 909 //using different register setting
907 910
908 if (high_gain_mode==1) 911 if (high_gain_mode==1)
909 { 912 {
910 if( rssi > MTO_DATA().RSSI_high ) 913 if( rssi > MTO_DATA().RSSI_high )
911 { 914 {
912 //hw_set_dxx_reg(phw_data, 0x0C, 0xf8f52230); 915 //hw_set_dxx_reg(phw_data, 0x0C, 0xf8f52230);
913 //hw_set_dxx_reg(phw_data, 0x20, 0x05541640); 916 //hw_set_dxx_reg(phw_data, 0x20, 0x05541640);
914 high_gain_mode=0; 917 high_gain_mode=0;
915 } 918 }
916 else 919 else
917 { 920 {
918 //hw_set_dxx_reg(phw_data, 0x0C, 0xf8f51830); 921 //hw_set_dxx_reg(phw_data, 0x0C, 0xf8f51830);
919 //hw_set_dxx_reg(phw_data, 0x20, 0x05543E40); 922 //hw_set_dxx_reg(phw_data, 0x20, 0x05543E40);
920 high_gain_mode=1; 923 high_gain_mode=1;
921 } 924 }
922 } 925 }
923 else //if (high_gain_mode==0) 926 else //if (high_gain_mode==0)
924 { 927 {
925 if( rssi < MTO_DATA().RSSI_low ) 928 if( rssi < MTO_DATA().RSSI_low )
926 { 929 {
927 //hw_set_dxx_reg(phw_data, 0x0C, 0xf8f51830); 930 //hw_set_dxx_reg(phw_data, 0x0C, 0xf8f51830);
928 //hw_set_dxx_reg(phw_data, 0x20, 0x05543E40); 931 //hw_set_dxx_reg(phw_data, 0x20, 0x05543E40);
929 high_gain_mode=1; 932 high_gain_mode=1;
930 } 933 }
931 else 934 else
932 { 935 {
933 //hw_set_dxx_reg(phw_data, 0x0C, 0xf8f52230); 936 //hw_set_dxx_reg(phw_data, 0x0C, 0xf8f52230);
934 //hw_set_dxx_reg(phw_data, 0x20, 0x05541640); 937 //hw_set_dxx_reg(phw_data, 0x20, 0x05541640);
935 high_gain_mode=0; 938 high_gain_mode=0;
936 } 939 }
937 } 940 }
938 941
939 // Always high gain 20051014. Using the initial value only. 942 // Always high gain 20051014. Using the initial value only.
940 multiagc(MTO_FUNC_INPUT_DATA, high_gain_mode); 943 multiagc(MTO_FUNC_INPUT_DATA, high_gain_mode);
941 } 944 }
942 } 945 }
943 946
944 947
945 u8 CalcNewRate(MTO_FUNC_INPUT, u8 old_rate, u32 retry_cnt, u32 tx_frag_cnt) 948 u8 CalcNewRate(MTO_FUNC_INPUT, u8 old_rate, u32 retry_cnt, u32 tx_frag_cnt)
946 { 949 {
947 int i; 950 int i;
948 u8 new_rate; 951 u8 new_rate;
949 u32 retry_rate; 952 u32 retry_rate;
950 int TxThrouput1, TxThrouput2, TxThrouput3, BestThroupht; 953 int TxThrouput1, TxThrouput2, TxThrouput3, BestThroupht;
951 954
952 if(tx_frag_cnt < MTOPARA_TXCOUNT_TH_FOR_CALC_RATE()) //too few packets transmit 955 if(tx_frag_cnt < MTOPARA_TXCOUNT_TH_FOR_CALC_RATE()) //too few packets transmit
953 { 956 {
954 return 0xff; 957 return 0xff;
955 } 958 }
956 retry_rate = Divide(retry_cnt * 100, tx_frag_cnt); 959 retry_rate = Divide(retry_cnt * 100, tx_frag_cnt);
957 960
958 if(retry_rate > 90) retry_rate = 90; //always truncate to 90% due to lookup table size 961 if(retry_rate > 90) retry_rate = 90; //always truncate to 90% due to lookup table size
959 #ifdef _PE_DTO_DUMP_ 962 #ifdef _PE_DTO_DUMP_
960 WBDEBUG(("##### Current level =%d, Retry count =%d, Frag count =%d\n", 963 WBDEBUG(("##### Current level =%d, Retry count =%d, Frag count =%d\n",
961 old_rate, retry_cnt, tx_frag_cnt)); 964 old_rate, retry_cnt, tx_frag_cnt));
962 WBDEBUG(("*##* Retry rate =%d, throughput =%d\n", 965 WBDEBUG(("*##* Retry rate =%d, throughput =%d\n",
963 retry_rate, Rate_PER_TBL[retry_rate][old_rate])); 966 retry_rate, Rate_PER_TBL[retry_rate][old_rate]));
964 WBDEBUG(("TxRateRec.tx_rate =%d, Retry rate = %d, throughput = %d\n", 967 WBDEBUG(("TxRateRec.tx_rate =%d, Retry rate = %d, throughput = %d\n",
965 TxRateRec.tx_rate, TxRateRec.tx_retry_rate, 968 TxRateRec.tx_rate, TxRateRec.tx_retry_rate,
966 Rate_PER_TBL[TxRateRec.tx_retry_rate][Level2PerTbl[TxRateRec.tx_rate]])); 969 Rate_PER_TBL[TxRateRec.tx_retry_rate][Level2PerTbl[TxRateRec.tx_rate]]));
967 WBDEBUG(("old_rate-1 =%d, Retry rate = %d, throughput = %d\n", 970 WBDEBUG(("old_rate-1 =%d, Retry rate = %d, throughput = %d\n",
968 old_rate-1, retryrate_rec[old_rate-1], 971 old_rate-1, retryrate_rec[old_rate-1],
969 Rate_PER_TBL[retryrate_rec[old_rate-1]][old_rate-1])); 972 Rate_PER_TBL[retryrate_rec[old_rate-1]][old_rate-1]));
970 WBDEBUG(("old_rate+1 =%d, Retry rate = %d, throughput = %d\n", 973 WBDEBUG(("old_rate+1 =%d, Retry rate = %d, throughput = %d\n",
971 old_rate+1, retryrate_rec[old_rate+1], 974 old_rate+1, retryrate_rec[old_rate+1],
972 Rate_PER_TBL[retryrate_rec[old_rate+1]][old_rate+1])); 975 Rate_PER_TBL[retryrate_rec[old_rate+1]][old_rate+1]));
973 #endif 976 #endif
974 977
975 //following is for record the retry rate at the different data rate 978 //following is for record the retry rate at the different data rate
976 if (abs(retry_rate-retryrate_rec[old_rate])<50)//---the per TH 979 if (abs(retry_rate-retryrate_rec[old_rate])<50)//---the per TH
977 retryrate_rec[old_rate] = retry_rate; //update retry rate 980 retryrate_rec[old_rate] = retry_rate; //update retry rate
978 else 981 else
979 { 982 {
980 for (i=0;i<MTO_DataRateAvailableLevel;i++) //reset all retry rate 983 for (i=0;i<MTO_DataRateAvailableLevel;i++) //reset all retry rate
981 retryrate_rec[i]=0; 984 retryrate_rec[i]=0;
982 retryrate_rec[old_rate] = retry_rate; 985 retryrate_rec[old_rate] = retry_rate;
983 #ifdef _PE_DTO_DUMP_ 986 #ifdef _PE_DTO_DUMP_
984 WBDEBUG(("Reset retry rate table\n")); 987 WBDEBUG(("Reset retry rate table\n"));
985 #endif 988 #endif
986 } 989 }
987 990
988 if(TxRateRec.tx_rate > old_rate) //Decrease Tx Rate 991 if(TxRateRec.tx_rate > old_rate) //Decrease Tx Rate
989 { 992 {
990 TxThrouput1 = Rate_PER_TBL[TxRateRec.tx_retry_rate][Level2PerTbl[TxRateRec.tx_rate]]; 993 TxThrouput1 = Rate_PER_TBL[TxRateRec.tx_retry_rate][Level2PerTbl[TxRateRec.tx_rate]];
991 TxThrouput2 = Rate_PER_TBL[retry_rate][Level2PerTbl[old_rate]]; 994 TxThrouput2 = Rate_PER_TBL[retry_rate][Level2PerTbl[old_rate]];
992 if(TxThrouput1 > TxThrouput2) 995 if(TxThrouput1 > TxThrouput2)
993 { 996 {
994 new_rate = TxRateRec.tx_rate; 997 new_rate = TxRateRec.tx_rate;
995 BestThroupht = TxThrouput1; 998 BestThroupht = TxThrouput1;
996 } 999 }
997 else 1000 else
998 { 1001 {
999 new_rate = old_rate; 1002 new_rate = old_rate;
1000 BestThroupht = TxThrouput2; 1003 BestThroupht = TxThrouput2;
1001 } 1004 }
1002 if((old_rate > 0) &&(retry_rate>MTOPARA_TXRATE_DEC_TH())) //Min Rate 1005 if((old_rate > 0) &&(retry_rate>MTOPARA_TXRATE_DEC_TH())) //Min Rate
1003 { 1006 {
1004 TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate-1]][Level2PerTbl[old_rate-1]]; 1007 TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate-1]][Level2PerTbl[old_rate-1]];
1005 if(BestThroupht < TxThrouput3) 1008 if(BestThroupht < TxThrouput3)
1006 { 1009 {
1007 new_rate = old_rate - 1; 1010 new_rate = old_rate - 1;
1008 #ifdef _PE_DTO_DUMP_ 1011 #ifdef _PE_DTO_DUMP_
1009 WBDEBUG(("--------\n")); 1012 WBDEBUG(("--------\n"));
1010 #endif 1013 #endif
1011 BestThroupht = TxThrouput3; 1014 BestThroupht = TxThrouput3;
1012 } 1015 }
1013 } 1016 }
1014 } 1017 }
1015 else if(TxRateRec.tx_rate < old_rate) //Increase Tx Rate 1018 else if(TxRateRec.tx_rate < old_rate) //Increase Tx Rate
1016 { 1019 {
1017 TxThrouput1 = Rate_PER_TBL[TxRateRec.tx_retry_rate][Level2PerTbl[TxRateRec.tx_rate]]; 1020 TxThrouput1 = Rate_PER_TBL[TxRateRec.tx_retry_rate][Level2PerTbl[TxRateRec.tx_rate]];
1018 TxThrouput2 = Rate_PER_TBL[retry_rate][Level2PerTbl[old_rate]]; 1021 TxThrouput2 = Rate_PER_TBL[retry_rate][Level2PerTbl[old_rate]];
1019 if(TxThrouput1 > TxThrouput2) 1022 if(TxThrouput1 > TxThrouput2)
1020 { 1023 {
1021 new_rate = TxRateRec.tx_rate; 1024 new_rate = TxRateRec.tx_rate;
1022 BestThroupht = TxThrouput1; 1025 BestThroupht = TxThrouput1;
1023 } 1026 }
1024 else 1027 else
1025 { 1028 {
1026 new_rate = old_rate; 1029 new_rate = old_rate;
1027 BestThroupht = TxThrouput2; 1030 BestThroupht = TxThrouput2;
1028 } 1031 }
1029 if ((old_rate < MTO_DataRateAvailableLevel - 1)&&(retry_rate<MTOPARA_TXRATE_INC_TH())) 1032 if ((old_rate < MTO_DataRateAvailableLevel - 1)&&(retry_rate<MTOPARA_TXRATE_INC_TH()))
1030 { 1033 {
1031 //TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate+1]][Level2PerTbl[old_rate+1]]; 1034 //TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate+1]][Level2PerTbl[old_rate+1]];
1032 if (retryrate_rec[old_rate+1] > MTOPARA_TXRETRYRATE_REDUCE()) 1035 if (retryrate_rec[old_rate+1] > MTOPARA_TXRETRYRATE_REDUCE())
1033 TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate+1]-MTOPARA_TXRETRYRATE_REDUCE()][Level2PerTbl[old_rate+1]]; 1036 TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate+1]-MTOPARA_TXRETRYRATE_REDUCE()][Level2PerTbl[old_rate+1]];
1034 else 1037 else
1035 TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate+1]][Level2PerTbl[old_rate+1]]; 1038 TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate+1]][Level2PerTbl[old_rate+1]];
1036 if(BestThroupht < TxThrouput3) 1039 if(BestThroupht < TxThrouput3)
1037 { 1040 {
1038 new_rate = old_rate + 1; 1041 new_rate = old_rate + 1;
1039 #ifdef _PE_DTO_DUMP_ 1042 #ifdef _PE_DTO_DUMP_
1040 WBDEBUG(("++++++++++\n")); 1043 WBDEBUG(("++++++++++\n"));
1041 #endif 1044 #endif
1042 BestThroupht = TxThrouput3; 1045 BestThroupht = TxThrouput3;
1043 } 1046 }
1044 } 1047 }
1045 } 1048 }
1046 else //Tx Rate no change 1049 else //Tx Rate no change
1047 { 1050 {
1048 TxThrouput2 = Rate_PER_TBL[retry_rate][Level2PerTbl[old_rate]]; 1051 TxThrouput2 = Rate_PER_TBL[retry_rate][Level2PerTbl[old_rate]];
1049 new_rate = old_rate; 1052 new_rate = old_rate;
1050 BestThroupht = TxThrouput2; 1053 BestThroupht = TxThrouput2;
1051 1054
1052 if (retry_rate <MTOPARA_TXRATE_EQ_TH()) //th for change higher rate 1055 if (retry_rate <MTOPARA_TXRATE_EQ_TH()) //th for change higher rate
1053 { 1056 {
1054 if(old_rate < MTO_DataRateAvailableLevel - 1) 1057 if(old_rate < MTO_DataRateAvailableLevel - 1)
1055 { 1058 {
1056 //TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate+1]][Level2PerTbl[old_rate+1]]; 1059 //TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate+1]][Level2PerTbl[old_rate+1]];
1057 if (retryrate_rec[old_rate+1] > MTOPARA_TXRETRYRATE_REDUCE()) 1060 if (retryrate_rec[old_rate+1] > MTOPARA_TXRETRYRATE_REDUCE())
1058 TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate+1]-MTOPARA_TXRETRYRATE_REDUCE()][Level2PerTbl[old_rate+1]]; 1061 TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate+1]-MTOPARA_TXRETRYRATE_REDUCE()][Level2PerTbl[old_rate+1]];
1059 else 1062 else
1060 TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate+1]][Level2PerTbl[old_rate+1]]; 1063 TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate+1]][Level2PerTbl[old_rate+1]];
1061 if(BestThroupht < TxThrouput3) 1064 if(BestThroupht < TxThrouput3)
1062 { 1065 {
1063 new_rate = old_rate + 1; 1066 new_rate = old_rate + 1;
1064 BestThroupht = TxThrouput3; 1067 BestThroupht = TxThrouput3;
1065 #ifdef _PE_DTO_DUMP_ 1068 #ifdef _PE_DTO_DUMP_
1066 WBDEBUG(("=++++++++++\n")); 1069 WBDEBUG(("=++++++++++\n"));
1067 #endif 1070 #endif
1068 } 1071 }
1069 } 1072 }
1070 } 1073 }
1071 else 1074 else
1072 if(old_rate > 0) //Min Rate 1075 if(old_rate > 0) //Min Rate
1073 { 1076 {
1074 TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate-1]][Level2PerTbl[old_rate-1]]; 1077 TxThrouput3 = Rate_PER_TBL[retryrate_rec[old_rate-1]][Level2PerTbl[old_rate-1]];
1075 if(BestThroupht < TxThrouput3) 1078 if(BestThroupht < TxThrouput3)
1076 { 1079 {
1077 new_rate = old_rate - 1; 1080 new_rate = old_rate - 1;
1078 #ifdef _PE_DTO_DUMP_ 1081 #ifdef _PE_DTO_DUMP_
1079 WBDEBUG(("=--------\n")); 1082 WBDEBUG(("=--------\n"));
1080 #endif 1083 #endif
1081 BestThroupht = TxThrouput3; 1084 BestThroupht = TxThrouput3;
1082 } 1085 }
1083 } 1086 }
1084 } 1087 }
1085 1088
1086 if (!LOCAL_IS_IBSS_MODE()) 1089 if (!LOCAL_IS_IBSS_MODE())
1087 { 1090 {
1088 max_rssi_rate = GetMaxRateLevelFromRSSI(); 1091 max_rssi_rate = GetMaxRateLevelFromRSSI();
1089 #ifdef _PE_DTO_DUMP_ 1092 #ifdef _PE_DTO_DUMP_
1090 WBDEBUG(("[MTO]:RSSI2Rate=%d\n", MTO_Data_Rate_Tbl[max_rssi_rate])); 1093 WBDEBUG(("[MTO]:RSSI2Rate=%d\n", MTO_Data_Rate_Tbl[max_rssi_rate]));
1091 #endif 1094 #endif
1092 if(new_rate > max_rssi_rate) 1095 if(new_rate > max_rssi_rate)
1093 new_rate = max_rssi_rate; 1096 new_rate = max_rssi_rate;
1094 } 1097 }
1095 1098
1096 //save new rate; 1099 //save new rate;
1097 TxRateRec.tx_rate = old_rate; 1100 TxRateRec.tx_rate = old_rate;
1098 TxRateRec.tx_retry_rate = (u8) retry_rate; 1101 TxRateRec.tx_retry_rate = (u8) retry_rate;
1099 TxRetryRate = retry_rate; 1102 TxRetryRate = retry_rate;
1100 return new_rate; 1103 return new_rate;
1101 } 1104 }
1102 1105
1103 void SmoothRSSI(s32 new_rssi) 1106 void SmoothRSSI(s32 new_rssi)
1104 { 1107 {
1105 RSSISmoothed = RSSISmoothed + new_rssi - RSSIBuf[RSSIBufIndex]; 1108 RSSISmoothed = RSSISmoothed + new_rssi - RSSIBuf[RSSIBufIndex];
1106 RSSIBuf[RSSIBufIndex] = new_rssi; 1109 RSSIBuf[RSSIBufIndex] = new_rssi;
1107 RSSIBufIndex = (RSSIBufIndex + 1) % 10; 1110 RSSIBufIndex = (RSSIBufIndex + 1) % 10;
1108 } 1111 }
1109 1112
1110 u8 GetMaxRateLevelFromRSSI(void) 1113 u8 GetMaxRateLevelFromRSSI(void)
1111 { 1114 {
1112 u8 i; 1115 u8 i;
1113 u8 TxRate; 1116 u8 TxRate;
1114 1117
1115 for(i=0;i<RSSI2RATE_SIZE;i++) 1118 for(i=0;i<RSSI2RATE_SIZE;i++)
1116 { 1119 {
1117 if(RSSISmoothed > RSSI2RateTbl[i].RSSI) 1120 if(RSSISmoothed > RSSI2RateTbl[i].RSSI)
1118 break; 1121 break;
1119 } 1122 }
1120 #ifdef _PE_DTO_DUMP_ 1123 #ifdef _PE_DTO_DUMP_
1121 WBDEBUG(("[MTO]:RSSI=%d\n", Divide(RSSISmoothed, 10))); 1124 WBDEBUG(("[MTO]:RSSI=%d\n", Divide(RSSISmoothed, 10)));
1122 #endif 1125 #endif
1123 if(i < RSSI2RATE_SIZE) 1126 if(i < RSSI2RATE_SIZE)
1124 TxRate = RSSI2RateTbl[i].TxRate; 1127 TxRate = RSSI2RateTbl[i].TxRate;
1125 else 1128 else
1126 TxRate = 2; //divided by 2 = 1Mbps 1129 TxRate = 2; //divided by 2 = 1Mbps
1127 1130
1128 for(i=MTO_DataRateAvailableLevel-1;i>0;i--) 1131 for(i=MTO_DataRateAvailableLevel-1;i>0;i--)
1129 { 1132 {
1130 if(TxRate >=MTO_Data_Rate_Tbl[i]) 1133 if(TxRate >=MTO_Data_Rate_Tbl[i])
1131 break; 1134 break;
1132 } 1135 }
1133 return i; 1136 return i;
1134 } 1137 }
1135 1138
1136 //=========================================================================== 1139 //===========================================================================
1137 // Description: 1140 // Description:
1138 // If we enable DTO, we will ignore the tx count with different tx rate from 1141 // If we enable DTO, we will ignore the tx count with different tx rate from
1139 // DTO rate. This is because when we adjust DTO tx rate, there could be some 1142 // DTO rate. This is because when we adjust DTO tx rate, there could be some
1140 // packets in the tx queue with previous tx rate 1143 // packets in the tx queue with previous tx rate
1141 void MTO_SetTxCount(MTO_FUNC_INPUT, u8 tx_rate, u8 index) 1144 void MTO_SetTxCount(MTO_FUNC_INPUT, u8 tx_rate, u8 index)
1142 { 1145 {
1143 MTO_TXFLOWCOUNT()++; 1146 MTO_TXFLOWCOUNT()++;
1144 if ((MTO_ENABLE==1) && (MTO_RATE_CHANGE_ENABLE()==1)) 1147 if ((MTO_ENABLE==1) && (MTO_RATE_CHANGE_ENABLE()==1))
1145 { 1148 {
1146 if(tx_rate == MTO_DATA_RATE()) 1149 if(tx_rate == MTO_DATA_RATE())
1147 { 1150 {
1148 if (index == 0) 1151 if (index == 0)
1149 { 1152 {
1150 if (boSparseTxTraffic) 1153 if (boSparseTxTraffic)
1151 MTO_HAL()->dto_tx_frag_count += MTOPARA_PERIODIC_CHECK_CYCLE(); 1154 MTO_HAL()->dto_tx_frag_count += MTOPARA_PERIODIC_CHECK_CYCLE();
1152 else 1155 else
1153 MTO_HAL()->dto_tx_frag_count += 1; 1156 MTO_HAL()->dto_tx_frag_count += 1;
1154 } 1157 }
1155 else 1158 else
1156 { 1159 {
1157 if (index<8) 1160 if (index<8)
1158 { 1161 {
1159 MTO_HAL()->dto_tx_retry_count += index; 1162 MTO_HAL()->dto_tx_retry_count += index;
1160 MTO_HAL()->dto_tx_frag_count += (index+1); 1163 MTO_HAL()->dto_tx_frag_count += (index+1);
1161 } 1164 }
1162 else 1165 else
1163 { 1166 {
1164 MTO_HAL()->dto_tx_retry_count += 7; 1167 MTO_HAL()->dto_tx_retry_count += 7;
1165 MTO_HAL()->dto_tx_frag_count += 7; 1168 MTO_HAL()->dto_tx_frag_count += 7;
1166 } 1169 }
1167 } 1170 }
1168 } 1171 }
1169 else if(MTO_DATA_RATE()>48 && tx_rate ==48) 1172 else if(MTO_DATA_RATE()>48 && tx_rate ==48)
1170 {//ALFRED 1173 {//ALFRED
1171 if (index<3) //for reduciing data rate scheme , 1174 if (index<3) //for reduciing data rate scheme ,
1172 //do not calcu different data rate 1175 //do not calcu different data rate
1173 //3 is the reducing data rate at retry 1176 //3 is the reducing data rate at retry
1174 { 1177 {
1175 MTO_HAL()->dto_tx_retry_count += index; 1178 MTO_HAL()->dto_tx_retry_count += index;
1176 MTO_HAL()->dto_tx_frag_count += (index+1); 1179 MTO_HAL()->dto_tx_frag_count += (index+1);
1177 } 1180 }
1178 else 1181 else
1179 { 1182 {
1180 MTO_HAL()->dto_tx_retry_count += 3; 1183 MTO_HAL()->dto_tx_retry_count += 3;
1181 MTO_HAL()->dto_tx_frag_count += 3; 1184 MTO_HAL()->dto_tx_frag_count += 3;
1182 } 1185 }
1183 1186
1184 } 1187 }
1185 } 1188 }
1186 else 1189 else
1187 { 1190 {
1188 MTO_HAL()->dto_tx_retry_count += index; 1191 MTO_HAL()->dto_tx_retry_count += index;
1189 MTO_HAL()->dto_tx_frag_count += (index+1); 1192 MTO_HAL()->dto_tx_frag_count += (index+1);
1190 } 1193 }
1191 TotalTxPkt ++; 1194 TotalTxPkt ++;
1192 TotalTxPktRetry += (index+1); 1195 TotalTxPktRetry += (index+1);
1193 1196
1194 PeriodTotalTxPkt ++; 1197 PeriodTotalTxPkt ++;
1195 PeriodTotalTxPktRetry += (index+1); 1198 PeriodTotalTxPktRetry += (index+1);
1196 } 1199 }
1197 1200
1198 u8 MTO_GetTxFallbackRate(MTO_FUNC_INPUT) 1201 u8 MTO_GetTxFallbackRate(MTO_FUNC_INPUT)
1199 { 1202 {
1200 return MTO_DATA_FALLBACK_RATE(); 1203 return MTO_DATA_FALLBACK_RATE();
1201 } 1204 }
1202 1205
1203 1206
1204 //=========================================================================== 1207 //===========================================================================
1205 // MTO_TxFailed -- 1208 // MTO_TxFailed --
1206 // 1209 //
1207 // Description: 1210 // Description:
1208 // Failure of transmitting a packet indicates that certain MTO parmeters 1211 // Failure of transmitting a packet indicates that certain MTO parmeters
1209 // may need to be adjusted. This function is called when NIC just failed 1212 // may need to be adjusted. This function is called when NIC just failed
1210 // to transmit a packet or when MSDULifeTime expired. 1213 // to transmit a packet or when MSDULifeTime expired.
1211 // 1214 //
1212 // Arguments: 1215 // Arguments:
1213 // adapter - The pointer to the Miniport adapter Context 1216 // adapter - The pointer to the Miniport adapter Context
1214 // 1217 //
1215 // Return Value: 1218 // Return Value:
1216 // None 1219 // None
1217 //============================================================================ 1220 //============================================================================
1218 void MTO_TxFailed(MTO_FUNC_INPUT) 1221 void MTO_TxFailed(MTO_FUNC_INPUT)
1219 { 1222 {
1220 return; 1223 return;
1221 } 1224 }
1222 1225
1223 int Divide(int a, int b) 1226 int Divide(int a, int b)
1224 { 1227 {
1225 if (b==0) b=1; 1228 if (b==0) b=1;
1226 return a/b; 1229 return a/b;
1227 } 1230 }
1228 1231
1229 1232
1230 1233
drivers/staging/winbond/mto.h
Diff comments   View file @ 80aba53
1 //================================================================== 1 //==================================================================
2 // MTO.H 2 // MTO.H
3 // 3 //
4 // Revision history 4 // Revision history
5 //================================= 5 //=================================
6 // 20030110 UN20 Pete Chao 6 // 20030110 UN20 Pete Chao
7 // Initial Release 7 // Initial Release
8 // 8 //
9 // Copyright (c) 2003 Winbond Electronics Corp. All rights reserved. 9 // Copyright (c) 2003 Winbond Electronics Corp. All rights reserved.
10 //================================================================== 10 //==================================================================
11 #ifndef __MTO_H__ 11 #ifndef __MTO_H__
12 #define __MTO_H__ 12 #define __MTO_H__
13 13
14 #include <linux/types.h>
15
14 #define MTO_DEFAULT_TH_CNT 5 16 #define MTO_DEFAULT_TH_CNT 5
15 #define MTO_DEFAULT_TH_SQ3 112 //OLD IS 13 reference JohnXu 17 #define MTO_DEFAULT_TH_SQ3 112 //OLD IS 13 reference JohnXu
16 #define MTO_DEFAULT_TH_IDLE_SLOT 15 18 #define MTO_DEFAULT_TH_IDLE_SLOT 15
17 #define MTO_DEFAULT_TH_PR_INTERF 30 19 #define MTO_DEFAULT_TH_PR_INTERF 30
18 #define MTO_DEFAULT_TMR_AGING 25 // unit: slot time 10 reference JohnXu 20 #define MTO_DEFAULT_TMR_AGING 25 // unit: slot time 10 reference JohnXu
19 #define MTO_DEFAULT_TMR_PERIODIC 5 // unit: slot time 21 #define MTO_DEFAULT_TMR_PERIODIC 5 // unit: slot time
20 22
21 #define MTO_ANTENNA_DIVERSITY_OFF 0 23 #define MTO_ANTENNA_DIVERSITY_OFF 0
22 #define MTO_ANTENNA_DIVERSITY_ON 1 24 #define MTO_ANTENNA_DIVERSITY_ON 1
23 25
24 // LA20040210_DTO kevin 26 // LA20040210_DTO kevin
25 //#define MTO_PREAMBLE_LONG 0 27 //#define MTO_PREAMBLE_LONG 0
26 //#define MTO_PREAMBLE_SHORT 1 28 //#define MTO_PREAMBLE_SHORT 1
27 #define MTO_PREAMBLE_LONG WLAN_PREAMBLE_TYPE_LONG 29 #define MTO_PREAMBLE_LONG WLAN_PREAMBLE_TYPE_LONG
28 #define MTO_PREAMBLE_SHORT WLAN_PREAMBLE_TYPE_SHORT 30 #define MTO_PREAMBLE_SHORT WLAN_PREAMBLE_TYPE_SHORT
29 31
30 typedef enum { 32 typedef enum {
31 TOGGLE_STATE_IDLE = 0, 33 TOGGLE_STATE_IDLE = 0,
32 TOGGLE_STATE_WAIT0 = 1, 34 TOGGLE_STATE_WAIT0 = 1,
33 TOGGLE_STATE_WAIT1 = 2, 35 TOGGLE_STATE_WAIT1 = 2,
34 TOGGLE_STATE_MAKEDESISION = 3, 36 TOGGLE_STATE_MAKEDESISION = 3,
35 TOGGLE_STATE_BKOFF = 4 37 TOGGLE_STATE_BKOFF = 4
36 } TOGGLE_STATE; 38 } TOGGLE_STATE;
37 39
38 typedef enum { 40 typedef enum {
39 RATE_CHGSTATE_IDLE = 0, 41 RATE_CHGSTATE_IDLE = 0,
40 RATE_CHGSTATE_CALCULATE = 1, 42 RATE_CHGSTATE_CALCULATE = 1,
41 RATE_CHGSTATE_BACKOFF = 2 43 RATE_CHGSTATE_BACKOFF = 2
42 } TX_RATE_REDUCTION_STATE; 44 } TX_RATE_REDUCTION_STATE;
43 45
44 //============================================================================ 46 //============================================================================
45 // struct _MTOParameters -- 47 // struct _MTOParameters --
46 // 48 //
47 // Defines the parameters used in the MAC Throughput Optimization algorithm 49 // Defines the parameters used in the MAC Throughput Optimization algorithm
48 //============================================================================ 50 //============================================================================
49 typedef struct _MTO_PARAMETERS 51 typedef struct _MTO_PARAMETERS
50 { 52 {
51 u8 Th_Fixant; 53 u8 Th_Fixant;
52 u8 Th_Cnt; 54 u8 Th_Cnt;
53 u8 Th_SQ3; 55 u8 Th_SQ3;
54 u8 Th_IdleSlot; 56 u8 Th_IdleSlot;
55 57
56 u16 Tmr_Aging; 58 u16 Tmr_Aging;
57 u8 Th_PrInterf; 59 u8 Th_PrInterf;
58 u8 Tmr_Periodic; 60 u8 Tmr_Periodic;
59 61
60 //--------- wkchen added ------------- 62 //--------- wkchen added -------------
61 u32 TxFlowCount; //to judge what kind the tx flow(sparse or busy) is 63 u32 TxFlowCount; //to judge what kind the tx flow(sparse or busy) is
62 //------------------------------------------------ 64 //------------------------------------------------
63 65
64 //--------- DTO threshold parameters ------------- 66 //--------- DTO threshold parameters -------------
65 u16 DTO_PeriodicCheckCycle; 67 u16 DTO_PeriodicCheckCycle;
66 u16 DTO_RssiThForAntDiv; 68 u16 DTO_RssiThForAntDiv;
67 69
68 u16 DTO_TxCountThForCalcNewRate; 70 u16 DTO_TxCountThForCalcNewRate;
69 u16 DTO_TxRateIncTh; 71 u16 DTO_TxRateIncTh;
70 72
71 u16 DTO_TxRateDecTh; 73 u16 DTO_TxRateDecTh;
72 u16 DTO_TxRateEqTh; 74 u16 DTO_TxRateEqTh;
73 75
74 u16 DTO_TxRateBackOff; 76 u16 DTO_TxRateBackOff;
75 u16 DTO_TxRetryRateReduce; 77 u16 DTO_TxRetryRateReduce;
76 78
77 u16 DTO_TxPowerIndex; //0 ~ 31 79 u16 DTO_TxPowerIndex; //0 ~ 31
78 u16 reserved_1; 80 u16 reserved_1;
79 //------------------------------------------------ 81 //------------------------------------------------
80 82
81 u8 PowerChangeEnable; 83 u8 PowerChangeEnable;
82 u8 AntDiversityEnable; 84 u8 AntDiversityEnable;
83 u8 Ant_mac; 85 u8 Ant_mac;
84 u8 Ant_div; 86 u8 Ant_div;
85 87
86 u8 CCA_Mode; 88 u8 CCA_Mode;
87 u8 CCA_Mode_Setup; 89 u8 CCA_Mode_Setup;
88 u8 Preamble_Type; 90 u8 Preamble_Type;
89 u8 PreambleChangeEnable; 91 u8 PreambleChangeEnable;
90 92
91 u8 DataRateLevel; 93 u8 DataRateLevel;
92 u8 DataRateChangeEnable; 94 u8 DataRateChangeEnable;
93 u8 FragThresholdLevel; 95 u8 FragThresholdLevel;
94 u8 FragThresholdChangeEnable; 96 u8 FragThresholdChangeEnable;
95 97
96 u16 RTSThreshold; 98 u16 RTSThreshold;
97 u16 RTSThreshold_Setup; 99 u16 RTSThreshold_Setup;
98 100
99 u32 AvgIdleSlot; 101 u32 AvgIdleSlot;
100 u32 Pr_Interf; 102 u32 Pr_Interf;
101 u32 AvgGapBtwnInterf; 103 u32 AvgGapBtwnInterf;
102 104
103 u8 RTSChangeEnable; 105 u8 RTSChangeEnable;
104 u8 Ant_sel; 106 u8 Ant_sel;
105 u8 aging_timeout; 107 u8 aging_timeout;
106 u8 reserved_2; 108 u8 reserved_2;
107 109
108 u32 Cnt_Ant[2]; 110 u32 Cnt_Ant[2];
109 u32 SQ_Ant[2]; 111 u32 SQ_Ant[2];
110 112
111 // 20040510 remove from globe vairable 113 // 20040510 remove from globe vairable
112 u32 TmrCnt; 114 u32 TmrCnt;
113 u32 BackoffTmr; 115 u32 BackoffTmr;
114 TOGGLE_STATE ToggleState; 116 TOGGLE_STATE ToggleState;
115 TX_RATE_REDUCTION_STATE TxRateReductionState; 117 TX_RATE_REDUCTION_STATE TxRateReductionState;
116 118
117 u8 Last_Rate; 119 u8 Last_Rate;
118 u8 Co_efficent; 120 u8 Co_efficent;
119 u8 FallbackRateLevel; 121 u8 FallbackRateLevel;
120 u8 OfdmRateLevel; 122 u8 OfdmRateLevel;
121 123
122 u8 RatePolicy; 124 u8 RatePolicy;
123 u8 reserved_3[3]; 125 u8 reserved_3[3];
124 126
125 // For RSSI turning 127 // For RSSI turning
126 s32 RSSI_high; 128 s32 RSSI_high;
127 s32 RSSI_low; 129 s32 RSSI_low;
128 130
129 } MTO_PARAMETERS, *PMTO_PARAMETERS; 131 } MTO_PARAMETERS, *PMTO_PARAMETERS;
130 132
131 133
132 #define MTO_FUNC_INPUT struct wb35_adapter * adapter 134 #define MTO_FUNC_INPUT struct wb35_adapter * adapter
133 #define MTO_FUNC_INPUT_DATA adapter 135 #define MTO_FUNC_INPUT_DATA adapter
134 #define MTO_DATA() (adapter->sMtoPara) 136 #define MTO_DATA() (adapter->sMtoPara)
135 #define MTO_HAL() (&adapter->sHwData) 137 #define MTO_HAL() (&adapter->sHwData)
136 #define MTO_SET_PREAMBLE_TYPE(x) // 20040511 Turbo mark LM_PREAMBLE_TYPE(&pcore_data->lm_data) = (x) 138 #define MTO_SET_PREAMBLE_TYPE(x) // 20040511 Turbo mark LM_PREAMBLE_TYPE(&pcore_data->lm_data) = (x)
137 #define MTO_ENABLE (adapter->sLocalPara.TxRateMode == RATE_AUTO) 139 #define MTO_ENABLE (adapter->sLocalPara.TxRateMode == RATE_AUTO)
138 #define MTO_TXPOWER_FROM_EEPROM (adapter->sHwData.PowerIndexFromEEPROM) 140 #define MTO_TXPOWER_FROM_EEPROM (adapter->sHwData.PowerIndexFromEEPROM)
139 #define LOCAL_ANTENNA_NO() (adapter->sLocalPara.bAntennaNo) 141 #define LOCAL_ANTENNA_NO() (adapter->sLocalPara.bAntennaNo)
140 #define LOCAL_IS_CONNECTED() (adapter->sLocalPara.wConnectedSTAindex != 0) 142 #define LOCAL_IS_CONNECTED() (adapter->sLocalPara.wConnectedSTAindex != 0)
141 #define LOCAL_IS_IBSS_MODE() (adapter->asBSSDescriptElement[adapter->sLocalPara.wConnectedSTAindex].bBssType == IBSS_NET) 143 #define LOCAL_IS_IBSS_MODE() (adapter->asBSSDescriptElement[adapter->sLocalPara.wConnectedSTAindex].bBssType == IBSS_NET)
142 #define MTO_INITTXRATE_MODE (adapter->sHwData.SoftwareSet&0x2) //bit 1 144 #define MTO_INITTXRATE_MODE (adapter->sHwData.SoftwareSet&0x2) //bit 1
143 // 20040510 Turbo add 145 // 20040510 Turbo add
144 #define MTO_TMR_CNT() MTO_DATA().TmrCnt 146 #define MTO_TMR_CNT() MTO_DATA().TmrCnt
145 #define MTO_TOGGLE_STATE() MTO_DATA().ToggleState 147 #define MTO_TOGGLE_STATE() MTO_DATA().ToggleState
146 #define MTO_TX_RATE_REDUCTION_STATE() MTO_DATA().TxRateReductionState 148 #define MTO_TX_RATE_REDUCTION_STATE() MTO_DATA().TxRateReductionState
147 #define MTO_BACKOFF_TMR() MTO_DATA().BackoffTmr 149 #define MTO_BACKOFF_TMR() MTO_DATA().BackoffTmr
148 #define MTO_LAST_RATE() MTO_DATA().Last_Rate 150 #define MTO_LAST_RATE() MTO_DATA().Last_Rate
149 #define MTO_CO_EFFICENT() MTO_DATA().Co_efficent 151 #define MTO_CO_EFFICENT() MTO_DATA().Co_efficent
150 152
151 #define MTO_TH_CNT() MTO_DATA().Th_Cnt 153 #define MTO_TH_CNT() MTO_DATA().Th_Cnt
152 #define MTO_TH_SQ3() MTO_DATA().Th_SQ3 154 #define MTO_TH_SQ3() MTO_DATA().Th_SQ3
153 #define MTO_TH_IDLE_SLOT() MTO_DATA().Th_IdleSlot 155 #define MTO_TH_IDLE_SLOT() MTO_DATA().Th_IdleSlot
154 #define MTO_TH_PR_INTERF() MTO_DATA().Th_PrInterf 156 #define MTO_TH_PR_INTERF() MTO_DATA().Th_PrInterf
155 157
156 #define MTO_TMR_AGING() MTO_DATA().Tmr_Aging 158 #define MTO_TMR_AGING() MTO_DATA().Tmr_Aging
157 #define MTO_TMR_PERIODIC() MTO_DATA().Tmr_Periodic 159 #define MTO_TMR_PERIODIC() MTO_DATA().Tmr_Periodic
158 160
159 #define MTO_POWER_CHANGE_ENABLE() MTO_DATA().PowerChangeEnable 161 #define MTO_POWER_CHANGE_ENABLE() MTO_DATA().PowerChangeEnable
160 #define MTO_ANT_DIVERSITY_ENABLE() adapter->sLocalPara.boAntennaDiversity 162 #define MTO_ANT_DIVERSITY_ENABLE() adapter->sLocalPara.boAntennaDiversity
161 #define MTO_ANT_MAC() MTO_DATA().Ant_mac 163 #define MTO_ANT_MAC() MTO_DATA().Ant_mac
162 #define MTO_ANT_DIVERSITY() MTO_DATA().Ant_div 164 #define MTO_ANT_DIVERSITY() MTO_DATA().Ant_div
163 #define MTO_CCA_MODE() MTO_DATA().CCA_Mode 165 #define MTO_CCA_MODE() MTO_DATA().CCA_Mode
164 #define MTO_CCA_MODE_SETUP() MTO_DATA().CCA_Mode_Setup 166 #define MTO_CCA_MODE_SETUP() MTO_DATA().CCA_Mode_Setup
165 #define MTO_PREAMBLE_TYPE() MTO_DATA().Preamble_Type 167 #define MTO_PREAMBLE_TYPE() MTO_DATA().Preamble_Type
166 #define MTO_PREAMBLE_CHANGE_ENABLE() MTO_DATA().PreambleChangeEnable 168 #define MTO_PREAMBLE_CHANGE_ENABLE() MTO_DATA().PreambleChangeEnable
167 169
168 #define MTO_RATE_LEVEL() MTO_DATA().DataRateLevel 170 #define MTO_RATE_LEVEL() MTO_DATA().DataRateLevel
169 #define MTO_FALLBACK_RATE_LEVEL() MTO_DATA().FallbackRateLevel 171 #define MTO_FALLBACK_RATE_LEVEL() MTO_DATA().FallbackRateLevel
170 #define MTO_OFDM_RATE_LEVEL() MTO_DATA().OfdmRateLevel 172 #define MTO_OFDM_RATE_LEVEL() MTO_DATA().OfdmRateLevel
171 #define MTO_RATE_CHANGE_ENABLE() MTO_DATA().DataRateChangeEnable 173 #define MTO_RATE_CHANGE_ENABLE() MTO_DATA().DataRateChangeEnable
172 #define MTO_FRAG_TH_LEVEL() MTO_DATA().FragThresholdLevel 174 #define MTO_FRAG_TH_LEVEL() MTO_DATA().FragThresholdLevel
173 #define MTO_FRAG_CHANGE_ENABLE() MTO_DATA().FragThresholdChangeEnable 175 #define MTO_FRAG_CHANGE_ENABLE() MTO_DATA().FragThresholdChangeEnable
174 #define MTO_RTS_THRESHOLD() MTO_DATA().RTSThreshold 176 #define MTO_RTS_THRESHOLD() MTO_DATA().RTSThreshold
175 #define MTO_RTS_CHANGE_ENABLE() MTO_DATA().RTSChangeEnable 177 #define MTO_RTS_CHANGE_ENABLE() MTO_DATA().RTSChangeEnable
176 #define MTO_RTS_THRESHOLD_SETUP() MTO_DATA().RTSThreshold_Setup 178 #define MTO_RTS_THRESHOLD_SETUP() MTO_DATA().RTSThreshold_Setup
177 179
178 #define MTO_AVG_IDLE_SLOT() MTO_DATA().AvgIdleSlot 180 #define MTO_AVG_IDLE_SLOT() MTO_DATA().AvgIdleSlot
179 #define MTO_PR_INTERF() MTO_DATA().Pr_Interf 181 #define MTO_PR_INTERF() MTO_DATA().Pr_Interf
180 #define MTO_AVG_GAP_BTWN_INTERF() MTO_DATA().AvgGapBtwnInterf 182 #define MTO_AVG_GAP_BTWN_INTERF() MTO_DATA().AvgGapBtwnInterf
181 183
182 #define MTO_ANT_SEL() MTO_DATA().Ant_sel 184 #define MTO_ANT_SEL() MTO_DATA().Ant_sel
183 #define MTO_CNT_ANT(x) MTO_DATA().Cnt_Ant[(x)] 185 #define MTO_CNT_ANT(x) MTO_DATA().Cnt_Ant[(x)]
184 #define MTO_SQ_ANT(x) MTO_DATA().SQ_Ant[(x)] 186 #define MTO_SQ_ANT(x) MTO_DATA().SQ_Ant[(x)]
185 #define MTO_AGING_TIMEOUT() MTO_DATA().aging_timeout 187 #define MTO_AGING_TIMEOUT() MTO_DATA().aging_timeout
186 188
187 189
188 #define MTO_TXFLOWCOUNT() MTO_DATA().TxFlowCount 190 #define MTO_TXFLOWCOUNT() MTO_DATA().TxFlowCount
189 //--------- DTO threshold parameters ------------- 191 //--------- DTO threshold parameters -------------
190 #define MTOPARA_PERIODIC_CHECK_CYCLE() MTO_DATA().DTO_PeriodicCheckCycle 192 #define MTOPARA_PERIODIC_CHECK_CYCLE() MTO_DATA().DTO_PeriodicCheckCycle
191 #define MTOPARA_RSSI_TH_FOR_ANTDIV() MTO_DATA().DTO_RssiThForAntDiv 193 #define MTOPARA_RSSI_TH_FOR_ANTDIV() MTO_DATA().DTO_RssiThForAntDiv
192 #define MTOPARA_TXCOUNT_TH_FOR_CALC_RATE() MTO_DATA().DTO_TxCountThForCalcNewRate 194 #define MTOPARA_TXCOUNT_TH_FOR_CALC_RATE() MTO_DATA().DTO_TxCountThForCalcNewRate
193 #define MTOPARA_TXRATE_INC_TH() MTO_DATA().DTO_TxRateIncTh 195 #define MTOPARA_TXRATE_INC_TH() MTO_DATA().DTO_TxRateIncTh
194 #define MTOPARA_TXRATE_DEC_TH() MTO_DATA().DTO_TxRateDecTh 196 #define MTOPARA_TXRATE_DEC_TH() MTO_DATA().DTO_TxRateDecTh
195 #define MTOPARA_TXRATE_EQ_TH() MTO_DATA().DTO_TxRateEqTh 197 #define MTOPARA_TXRATE_EQ_TH() MTO_DATA().DTO_TxRateEqTh
196 #define MTOPARA_TXRATE_BACKOFF() MTO_DATA().DTO_TxRateBackOff 198 #define MTOPARA_TXRATE_BACKOFF() MTO_DATA().DTO_TxRateBackOff
197 #define MTOPARA_TXRETRYRATE_REDUCE() MTO_DATA().DTO_TxRetryRateReduce 199 #define MTOPARA_TXRETRYRATE_REDUCE() MTO_DATA().DTO_TxRetryRateReduce
198 #define MTOPARA_TXPOWER_INDEX() MTO_DATA().DTO_TxPowerIndex 200 #define MTOPARA_TXPOWER_INDEX() MTO_DATA().DTO_TxPowerIndex
199 //------------------------------------------------ 201 //------------------------------------------------
200 202
201 203
202 extern u8 MTO_Data_Rate_Tbl[]; 204 extern u8 MTO_Data_Rate_Tbl[];
203 extern u16 MTO_Frag_Th_Tbl[]; 205 extern u16 MTO_Frag_Th_Tbl[];
204 206
205 #define MTO_DATA_RATE() MTO_Data_Rate_Tbl[MTO_RATE_LEVEL()] 207 #define MTO_DATA_RATE() MTO_Data_Rate_Tbl[MTO_RATE_LEVEL()]
206 #define MTO_DATA_FALLBACK_RATE() MTO_Data_Rate_Tbl[MTO_FALLBACK_RATE_LEVEL()] //next level 208 #define MTO_DATA_FALLBACK_RATE() MTO_Data_Rate_Tbl[MTO_FALLBACK_RATE_LEVEL()] //next level
207 #define MTO_FRAG_TH() MTO_Frag_Th_Tbl[MTO_FRAG_TH_LEVEL()] 209 #define MTO_FRAG_TH() MTO_Frag_Th_Tbl[MTO_FRAG_TH_LEVEL()]
208 210
209 typedef struct { 211 typedef struct {
210 u8 tx_rate; 212 u8 tx_rate;
211 u8 tx_retry_rate; 213 u8 tx_retry_rate;
212 } TXRETRY_REC; 214 } TXRETRY_REC;
213 215
214 typedef struct _STATISTICS_INFO { 216 typedef struct _STATISTICS_INFO {
215 u32 Rate54M; 217 u32 Rate54M;
216 u32 Rate48M; 218 u32 Rate48M;
217 u32 Rate36M; 219 u32 Rate36M;
218 u32 Rate24M; 220 u32 Rate24M;
219 u32 Rate18M; 221 u32 Rate18M;
220 u32 Rate12M; 222 u32 Rate12M;
221 u32 Rate9M; 223 u32 Rate9M;
222 u32 Rate6M; 224 u32 Rate6M;
223 u32 Rate11MS; 225 u32 Rate11MS;
224 u32 Rate11ML; 226 u32 Rate11ML;
225 u32 Rate55MS; 227 u32 Rate55MS;
226 u32 Rate55ML; 228 u32 Rate55ML;
227 u32 Rate2MS; 229 u32 Rate2MS;
228 u32 Rate2ML; 230 u32 Rate2ML;
229 u32 Rate1M; 231 u32 Rate1M;
230 u32 Rate54MOK; 232 u32 Rate54MOK;
231 u32 Rate48MOK; 233 u32 Rate48MOK;
232 u32 Rate36MOK; 234 u32 Rate36MOK;
233 u32 Rate24MOK; 235 u32 Rate24MOK;
234 u32 Rate18MOK; 236 u32 Rate18MOK;
235 u32 Rate12MOK; 237 u32 Rate12MOK;
236 u32 Rate9MOK; 238 u32 Rate9MOK;
237 u32 Rate6MOK; 239 u32 Rate6MOK;
238 u32 Rate11MSOK; 240 u32 Rate11MSOK;
239 u32 Rate11MLOK; 241 u32 Rate11MLOK;
240 u32 Rate55MSOK; 242 u32 Rate55MSOK;
241 u32 Rate55MLOK; 243 u32 Rate55MLOK;
242 u32 Rate2MSOK; 244 u32 Rate2MSOK;
243 u32 Rate2MLOK; 245 u32 Rate2MLOK;
244 u32 Rate1MOK; 246 u32 Rate1MOK;
245 u32 SQ3; 247 u32 SQ3;
246 s32 RSSIAVG; 248 s32 RSSIAVG;
247 s32 RSSIMAX; 249 s32 RSSIMAX;
248 s32 TXRATE; 250 s32 TXRATE;
249 s32 TxRetryRate; 251 s32 TxRetryRate;
250 s32 BSS_PK_CNT; 252 s32 BSS_PK_CNT;
251 s32 NIDLESLOT; 253 s32 NIDLESLOT;
252 s32 SLOT_CNT; 254 s32 SLOT_CNT;
253 s32 INTERF_CNT; 255 s32 INTERF_CNT;
254 s32 GAP_CNT; 256 s32 GAP_CNT;
255 s32 DS_EVM; 257 s32 DS_EVM;
256 s32 RcvBeaconNum; 258 s32 RcvBeaconNum;
257 s32 RXRATE; 259 s32 RXRATE;
258 s32 RxBytes; 260 s32 RxBytes;
259 s32 TxBytes; 261 s32 TxBytes;
260 s32 Antenna; 262 s32 Antenna;
261 } STATISTICS_INFO, *PSTATISTICS_INFO; 263 } STATISTICS_INFO, *PSTATISTICS_INFO;
262 264
263 #endif //__MTO_H__ 265 #endif //__MTO_H__
264 266
265 267
266 268
drivers/staging/winbond/mto_f.h
Diff comments   View file @ 80aba53
1 #ifndef __WINBOND_MTO_F_H
2 #define __WINBOND_MTO_F_H
3
4 #include "adapter.h"
5
1 extern void MTO_Init(struct wb35_adapter *); 6 extern void MTO_Init(struct wb35_adapter *);
2 extern void MTO_PeriodicTimerExpired(struct wb35_adapter *); 7 extern void MTO_PeriodicTimerExpired(struct wb35_adapter *);
3 extern void MTO_SetDTORateRange(struct wb35_adapter *, u8 *, u8); 8 extern void MTO_SetDTORateRange(struct wb35_adapter *, u8 *, u8);
4 extern u8 MTO_GetTxRate(MTO_FUNC_INPUT, u32 fpdu_len); 9 extern u8 MTO_GetTxRate(MTO_FUNC_INPUT, u32 fpdu_len);
5 extern u8 MTO_GetTxFallbackRate(MTO_FUNC_INPUT); 10 extern u8 MTO_GetTxFallbackRate(MTO_FUNC_INPUT);
6 extern void MTO_SetTxCount(MTO_FUNC_INPUT, u8 t0, u8 index); 11 extern void MTO_SetTxCount(MTO_FUNC_INPUT, u8 t0, u8 index);
12
13 #endif
7 14
drivers/staging/winbond/phy_calibration.c
Diff comments   View file @ 80aba53
1 /* 1 /*
2 * phy_302_calibration.c 2 * phy_302_calibration.c
3 * 3 *
4 * Copyright (C) 2002, 2005 Winbond Electronics Corp. 4 * Copyright (C) 2002, 2005 Winbond Electronics Corp.
5 * 5 *
6 * modification history 6 * modification history
7 * --------------------------------------------------------------------------- 7 * ---------------------------------------------------------------------------
8 * 0.01.001, 2003-04-16, Kevin created 8 * 0.01.001, 2003-04-16, Kevin created
9 * 9 *
10 */ 10 */
11 11
12 /****************** INCLUDE FILES SECTION ***********************************/ 12 /****************** INCLUDE FILES SECTION ***********************************/
13 #include "os_common.h" 13 #include "os_common.h"
14 #include "phy_calibration.h" 14 #include "phy_calibration.h"
15 #include "wbhal_f.h"
15 16
16 17
17 /****************** DEBUG CONSTANT AND MACRO SECTION ************************/ 18 /****************** DEBUG CONSTANT AND MACRO SECTION ************************/
18 19
19 /****************** LOCAL CONSTANT AND MACRO SECTION ************************/ 20 /****************** LOCAL CONSTANT AND MACRO SECTION ************************/
20 #define LOOP_TIMES 20 21 #define LOOP_TIMES 20
21 #define US 1000//MICROSECOND 22 #define US 1000//MICROSECOND
22 23
23 #define AG_CONST 0.6072529350 24 #define AG_CONST 0.6072529350
24 #define FIXED(X) ((s32)((X) * 32768.0)) 25 #define FIXED(X) ((s32)((X) * 32768.0))
25 #define DEG2RAD(X) 0.017453 * (X) 26 #define DEG2RAD(X) 0.017453 * (X)
26 27
27 /****************** LOCAL TYPE DEFINITION SECTION ***************************/ 28 /****************** LOCAL TYPE DEFINITION SECTION ***************************/
28 typedef s32 fixed; /* 16.16 fixed-point */ 29 typedef s32 fixed; /* 16.16 fixed-point */
29 30
30 static const fixed Angles[]= 31 static const fixed Angles[]=
31 { 32 {
32 FIXED(DEG2RAD(45.0)), FIXED(DEG2RAD(26.565)), FIXED(DEG2RAD(14.0362)), 33 FIXED(DEG2RAD(45.0)), FIXED(DEG2RAD(26.565)), FIXED(DEG2RAD(14.0362)),
33 FIXED(DEG2RAD(7.12502)), FIXED(DEG2RAD(3.57633)), FIXED(DEG2RAD(1.78991)), 34 FIXED(DEG2RAD(7.12502)), FIXED(DEG2RAD(3.57633)), FIXED(DEG2RAD(1.78991)),
34 FIXED(DEG2RAD(0.895174)),FIXED(DEG2RAD(0.447614)),FIXED(DEG2RAD(0.223811)), 35 FIXED(DEG2RAD(0.895174)),FIXED(DEG2RAD(0.447614)),FIXED(DEG2RAD(0.223811)),
35 FIXED(DEG2RAD(0.111906)),FIXED(DEG2RAD(0.055953)),FIXED(DEG2RAD(0.027977)) 36 FIXED(DEG2RAD(0.111906)),FIXED(DEG2RAD(0.055953)),FIXED(DEG2RAD(0.027977))
36 }; 37 };
37 38
38 /****************** LOCAL FUNCTION DECLARATION SECTION **********************/ 39 /****************** LOCAL FUNCTION DECLARATION SECTION **********************/
39 //void _phy_rf_write_delay(hw_data_t *phw_data); 40 //void _phy_rf_write_delay(hw_data_t *phw_data);
40 //void phy_init_rf(hw_data_t *phw_data); 41 //void phy_init_rf(hw_data_t *phw_data);
41 42
42 /****************** FUNCTION DEFINITION SECTION *****************************/ 43 /****************** FUNCTION DEFINITION SECTION *****************************/
43 44
44 s32 _s13_to_s32(u32 data) 45 s32 _s13_to_s32(u32 data)
45 { 46 {
46 u32 val; 47 u32 val;
47 48
48 val = (data & 0x0FFF); 49 val = (data & 0x0FFF);
49 50
50 if ((data & BIT(12)) != 0) 51 if ((data & BIT(12)) != 0)
51 { 52 {
52 val |= 0xFFFFF000; 53 val |= 0xFFFFF000;
53 } 54 }
54 55
55 return ((s32) val); 56 return ((s32) val);
56 } 57 }
57 58
58 u32 _s32_to_s13(s32 data) 59 u32 _s32_to_s13(s32 data)
59 { 60 {
60 u32 val; 61 u32 val;
61 62
62 if (data > 4095) 63 if (data > 4095)
63 { 64 {
64 data = 4095; 65 data = 4095;
65 } 66 }
66 else if (data < -4096) 67 else if (data < -4096)
67 { 68 {
68 data = -4096; 69 data = -4096;
69 } 70 }
70 71
71 val = data & 0x1FFF; 72 val = data & 0x1FFF;
72 73
73 return val; 74 return val;
74 } 75 }
75 76
76 /****************************************************************************/ 77 /****************************************************************************/
77 s32 _s4_to_s32(u32 data) 78 s32 _s4_to_s32(u32 data)
78 { 79 {
79 s32 val; 80 s32 val;
80 81
81 val = (data & 0x0007); 82 val = (data & 0x0007);
82 83
83 if ((data & BIT(3)) != 0) 84 if ((data & BIT(3)) != 0)
84 { 85 {
85 val |= 0xFFFFFFF8; 86 val |= 0xFFFFFFF8;
86 } 87 }
87 88
88 return val; 89 return val;
89 } 90 }
90 91
91 u32 _s32_to_s4(s32 data) 92 u32 _s32_to_s4(s32 data)
92 { 93 {
93 u32 val; 94 u32 val;
94 95
95 if (data > 7) 96 if (data > 7)
96 { 97 {
97 data = 7; 98 data = 7;
98 } 99 }
99 else if (data < -8) 100 else if (data < -8)
100 { 101 {
101 data = -8; 102 data = -8;
102 } 103 }
103 104
104 val = data & 0x000F; 105 val = data & 0x000F;
105 106
106 return val; 107 return val;
107 } 108 }
108 109
109 /****************************************************************************/ 110 /****************************************************************************/
110 s32 _s5_to_s32(u32 data) 111 s32 _s5_to_s32(u32 data)
111 { 112 {
112 s32 val; 113 s32 val;
113 114
114 val = (data & 0x000F); 115 val = (data & 0x000F);
115 116
116 if ((data & BIT(4)) != 0) 117 if ((data & BIT(4)) != 0)
117 { 118 {
118 val |= 0xFFFFFFF0; 119 val |= 0xFFFFFFF0;
119 } 120 }
120 121
121 return val; 122 return val;
122 } 123 }
123 124
124 u32 _s32_to_s5(s32 data) 125 u32 _s32_to_s5(s32 data)
125 { 126 {
126 u32 val; 127 u32 val;
127 128
128 if (data > 15) 129 if (data > 15)
129 { 130 {
130 data = 15; 131 data = 15;
131 } 132 }
132 else if (data < -16) 133 else if (data < -16)
133 { 134 {
134 data = -16; 135 data = -16;
135 } 136 }
136 137
137 val = data & 0x001F; 138 val = data & 0x001F;
138 139
139 return val; 140 return val;
140 } 141 }
141 142
142 /****************************************************************************/ 143 /****************************************************************************/
143 s32 _s6_to_s32(u32 data) 144 s32 _s6_to_s32(u32 data)
144 { 145 {
145 s32 val; 146 s32 val;
146 147
147 val = (data & 0x001F); 148 val = (data & 0x001F);
148 149
149 if ((data & BIT(5)) != 0) 150 if ((data & BIT(5)) != 0)
150 { 151 {
151 val |= 0xFFFFFFE0; 152 val |= 0xFFFFFFE0;
152 } 153 }
153 154
154 return val; 155 return val;
155 } 156 }
156 157
157 u32 _s32_to_s6(s32 data) 158 u32 _s32_to_s6(s32 data)
158 { 159 {
159 u32 val; 160 u32 val;
160 161
161 if (data > 31) 162 if (data > 31)
162 { 163 {
163 data = 31; 164 data = 31;
164 } 165 }
165 else if (data < -32) 166 else if (data < -32)
166 { 167 {
167 data = -32; 168 data = -32;
168 } 169 }
169 170
170 val = data & 0x003F; 171 val = data & 0x003F;
171 172
172 return val; 173 return val;
173 } 174 }
174 175
175 /****************************************************************************/ 176 /****************************************************************************/
176 s32 _s9_to_s32(u32 data) 177 s32 _s9_to_s32(u32 data)
177 { 178 {
178 s32 val; 179 s32 val;
179 180
180 val = data & 0x00FF; 181 val = data & 0x00FF;
181 182
182 if ((data & BIT(8)) != 0) 183 if ((data & BIT(8)) != 0)
183 { 184 {
184 val |= 0xFFFFFF00; 185 val |= 0xFFFFFF00;
185 } 186 }
186 187
187 return val; 188 return val;
188 } 189 }
189 190
190 u32 _s32_to_s9(s32 data) 191 u32 _s32_to_s9(s32 data)
191 { 192 {
192 u32 val; 193 u32 val;
193 194
194 if (data > 255) 195 if (data > 255)
195 { 196 {
196 data = 255; 197 data = 255;
197 } 198 }
198 else if (data < -256) 199 else if (data < -256)
199 { 200 {
200 data = -256; 201 data = -256;
201 } 202 }
202 203
203 val = data & 0x01FF; 204 val = data & 0x01FF;
204 205
205 return val; 206 return val;
206 } 207 }
207 208
208 /****************************************************************************/ 209 /****************************************************************************/
209 s32 _floor(s32 n) 210 s32 _floor(s32 n)
210 { 211 {
211 if (n > 0) 212 if (n > 0)
212 { 213 {
213 n += 5; 214 n += 5;
214 } 215 }
215 else 216 else
216 { 217 {
217 n -= 5; 218 n -= 5;
218 } 219 }
219 220
220 return (n/10); 221 return (n/10);
221 } 222 }
222 223
223 /****************************************************************************/ 224 /****************************************************************************/
224 // The following code is sqare-root function. 225 // The following code is sqare-root function.
225 // sqsum is the input and the output is sq_rt; 226 // sqsum is the input and the output is sq_rt;
226 // The maximum of sqsum = 2^27 -1; 227 // The maximum of sqsum = 2^27 -1;
227 u32 _sqrt(u32 sqsum) 228 u32 _sqrt(u32 sqsum)
228 { 229 {
229 u32 sq_rt; 230 u32 sq_rt;
230 231
231 int g0, g1, g2, g3, g4; 232 int g0, g1, g2, g3, g4;
232 int seed; 233 int seed;
233 int next; 234 int next;
234 int step; 235 int step;
235 236
236 g4 = sqsum / 100000000; 237 g4 = sqsum / 100000000;
237 g3 = (sqsum - g4*100000000) /1000000; 238 g3 = (sqsum - g4*100000000) /1000000;
238 g2 = (sqsum - g4*100000000 - g3*1000000) /10000; 239 g2 = (sqsum - g4*100000000 - g3*1000000) /10000;
239 g1 = (sqsum - g4*100000000 - g3*1000000 - g2*10000) /100; 240 g1 = (sqsum - g4*100000000 - g3*1000000 - g2*10000) /100;
240 g0 = (sqsum - g4*100000000 - g3*1000000 - g2*10000 - g1*100); 241 g0 = (sqsum - g4*100000000 - g3*1000000 - g2*10000 - g1*100);
241 242
242 next = g4; 243 next = g4;
243 step = 0; 244 step = 0;
244 seed = 0; 245 seed = 0;
245 while (((seed+1)*(step+1)) <= next) 246 while (((seed+1)*(step+1)) <= next)
246 { 247 {
247 step++; 248 step++;
248 seed++; 249 seed++;
249 } 250 }
250 251
251 sq_rt = seed * 10000; 252 sq_rt = seed * 10000;
252 next = (next-(seed*step))*100 + g3; 253 next = (next-(seed*step))*100 + g3;
253 254
254 step = 0; 255 step = 0;
255 seed = 2 * seed * 10; 256 seed = 2 * seed * 10;
256 while (((seed+1)*(step+1)) <= next) 257 while (((seed+1)*(step+1)) <= next)
257 { 258 {
258 step++; 259 step++;
259 seed++; 260 seed++;
260 } 261 }
261 262
262 sq_rt = sq_rt + step * 1000; 263 sq_rt = sq_rt + step * 1000;
263 next = (next - seed * step) * 100 + g2; 264 next = (next - seed * step) * 100 + g2;
264 seed = (seed + step) * 10; 265 seed = (seed + step) * 10;
265 step = 0; 266 step = 0;
266 while (((seed+1)*(step+1)) <= next) 267 while (((seed+1)*(step+1)) <= next)
267 { 268 {
268 step++; 269 step++;
269 seed++; 270 seed++;
270 } 271 }
271 272
272 sq_rt = sq_rt + step * 100; 273 sq_rt = sq_rt + step * 100;
273 next = (next - seed * step) * 100 + g1; 274 next = (next - seed * step) * 100 + g1;
274 seed = (seed + step) * 10; 275 seed = (seed + step) * 10;
275 step = 0; 276 step = 0;
276 277
277 while (((seed+1)*(step+1)) <= next) 278 while (((seed+1)*(step+1)) <= next)
278 { 279 {
279 step++; 280 step++;
280 seed++; 281 seed++;
281 } 282 }
282 283
283 sq_rt = sq_rt + step * 10; 284 sq_rt = sq_rt + step * 10;
284 next = (next - seed* step) * 100 + g0; 285 next = (next - seed* step) * 100 + g0;
285 seed = (seed + step) * 10; 286 seed = (seed + step) * 10;
286 step = 0; 287 step = 0;
287 288
288 while (((seed+1)*(step+1)) <= next) 289 while (((seed+1)*(step+1)) <= next)
289 { 290 {
290 step++; 291 step++;
291 seed++; 292 seed++;
292 } 293 }
293 294
294 sq_rt = sq_rt + step; 295 sq_rt = sq_rt + step;
295 296
296 return sq_rt; 297 return sq_rt;
297 } 298 }
298 299
299 /****************************************************************************/ 300 /****************************************************************************/
300 void _sin_cos(s32 angle, s32 *sin, s32 *cos) 301 void _sin_cos(s32 angle, s32 *sin, s32 *cos)
301 { 302 {
302 fixed X, Y, TargetAngle, CurrAngle; 303 fixed X, Y, TargetAngle, CurrAngle;
303 unsigned Step; 304 unsigned Step;
304 305
305 X=FIXED(AG_CONST); // AG_CONST * cos(0) 306 X=FIXED(AG_CONST); // AG_CONST * cos(0)
306 Y=0; // AG_CONST * sin(0) 307 Y=0; // AG_CONST * sin(0)
307 TargetAngle=abs(angle); 308 TargetAngle=abs(angle);
308 CurrAngle=0; 309 CurrAngle=0;
309 310
310 for (Step=0; Step < 12; Step++) 311 for (Step=0; Step < 12; Step++)
311 { 312 {
312 fixed NewX; 313 fixed NewX;
313 314
314 if(TargetAngle > CurrAngle) 315 if(TargetAngle > CurrAngle)
315 { 316 {
316 NewX=X - (Y >> Step); 317 NewX=X - (Y >> Step);
317 Y=(X >> Step) + Y; 318 Y=(X >> Step) + Y;
318 X=NewX; 319 X=NewX;
319 CurrAngle += Angles[Step]; 320 CurrAngle += Angles[Step];
320 } 321 }
321 else 322 else
322 { 323 {
323 NewX=X + (Y >> Step); 324 NewX=X + (Y >> Step);
324 Y=-(X >> Step) + Y; 325 Y=-(X >> Step) + Y;
325 X=NewX; 326 X=NewX;
326 CurrAngle -= Angles[Step]; 327 CurrAngle -= Angles[Step];
327 } 328 }
328 } 329 }
329 330
330 if (angle > 0) 331 if (angle > 0)
331 { 332 {
332 *cos = X; 333 *cos = X;
333 *sin = Y; 334 *sin = Y;
334 } 335 }
335 else 336 else
336 { 337 {
337 *cos = X; 338 *cos = X;
338 *sin = -Y; 339 *sin = -Y;
339 } 340 }
340 } 341 }
341 342
342 343
343 void _reset_rx_cal(hw_data_t *phw_data) 344 void _reset_rx_cal(hw_data_t *phw_data)
344 { 345 {
345 u32 val; 346 u32 val;
346 347
347 hw_get_dxx_reg(phw_data, 0x54, &val); 348 hw_get_dxx_reg(phw_data, 0x54, &val);
348 349
349 if (phw_data->revision == 0x2002) // 1st-cut 350 if (phw_data->revision == 0x2002) // 1st-cut
350 { 351 {
351 val &= 0xFFFF0000; 352 val &= 0xFFFF0000;
352 } 353 }
353 else // 2nd-cut 354 else // 2nd-cut
354 { 355 {
355 val &= 0x000003FF; 356 val &= 0x000003FF;
356 } 357 }
357 358
358 hw_set_dxx_reg(phw_data, 0x54, val); 359 hw_set_dxx_reg(phw_data, 0x54, val);
359 } 360 }
360 361
361 362
362 // ************for winbond calibration********* 363 // ************for winbond calibration*********
363 // 364 //
364 365
365 // 366 //
366 // 367 //
367 // ********************************************* 368 // *********************************************
368 void _rxadc_dc_offset_cancellation_winbond(hw_data_t *phw_data, u32 frequency) 369 void _rxadc_dc_offset_cancellation_winbond(hw_data_t *phw_data, u32 frequency)
369 { 370 {
370 u32 reg_agc_ctrl3; 371 u32 reg_agc_ctrl3;
371 u32 reg_a_acq_ctrl; 372 u32 reg_a_acq_ctrl;
372 u32 reg_b_acq_ctrl; 373 u32 reg_b_acq_ctrl;
373 u32 val; 374 u32 val;
374 375
375 PHY_DEBUG(("[CAL] -> [1]_rxadc_dc_offset_cancellation()\n")); 376 PHY_DEBUG(("[CAL] -> [1]_rxadc_dc_offset_cancellation()\n"));
376 phy_init_rf(phw_data); 377 phy_init_rf(phw_data);
377 378
378 // set calibration channel 379 // set calibration channel
379 if( (RF_WB_242 == phw_data->phy_type) || 380 if( (RF_WB_242 == phw_data->phy_type) ||
380 (RF_WB_242_1 == phw_data->phy_type) ) // 20060619.5 Add 381 (RF_WB_242_1 == phw_data->phy_type) ) // 20060619.5 Add
381 { 382 {
382 if ((frequency >= 2412) && (frequency <= 2484)) 383 if ((frequency >= 2412) && (frequency <= 2484))
383 { 384 {
384 // w89rf242 change frequency to 2390Mhz 385 // w89rf242 change frequency to 2390Mhz
385 PHY_DEBUG(("[CAL] W89RF242/11G/Channel=2390Mhz\n")); 386 PHY_DEBUG(("[CAL] W89RF242/11G/Channel=2390Mhz\n"));
386 phy_set_rf_data(phw_data, 3, (3<<24)|0x025586); 387 phy_set_rf_data(phw_data, 3, (3<<24)|0x025586);
387 388
388 } 389 }
389 } 390 }
390 else 391 else
391 { 392 {
392 393
393 } 394 }
394 395
395 // reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel 396 // reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel
396 hw_get_dxx_reg(phw_data, 0x5C, &val); 397 hw_get_dxx_reg(phw_data, 0x5C, &val);
397 val &= ~(0x03FF); 398 val &= ~(0x03FF);
398 hw_set_dxx_reg(phw_data, 0x5C, val); 399 hw_set_dxx_reg(phw_data, 0x5C, val);
399 400
400 // reset the TX and RX IQ calibration data 401 // reset the TX and RX IQ calibration data
401 hw_set_dxx_reg(phw_data, 0x3C, 0); 402 hw_set_dxx_reg(phw_data, 0x3C, 0);
402 hw_set_dxx_reg(phw_data, 0x54, 0); 403 hw_set_dxx_reg(phw_data, 0x54, 0);
403 404
404 hw_set_dxx_reg(phw_data, 0x58, 0x30303030); // IQ_Alpha Changed 405 hw_set_dxx_reg(phw_data, 0x58, 0x30303030); // IQ_Alpha Changed
405 406
406 // a. Disable AGC 407 // a. Disable AGC
407 hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3); 408 hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3);
408 reg_agc_ctrl3 &= ~BIT(2); 409 reg_agc_ctrl3 &= ~BIT(2);
409 reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX); 410 reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
410 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3); 411 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
411 412
412 hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val); 413 hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val);
413 val |= MASK_AGC_FIX_GAIN; 414 val |= MASK_AGC_FIX_GAIN;
414 hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val); 415 hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val);
415 416
416 // b. Turn off BB RX 417 // b. Turn off BB RX
417 hw_get_dxx_reg(phw_data, REG_A_ACQ_CTRL, &reg_a_acq_ctrl); 418 hw_get_dxx_reg(phw_data, REG_A_ACQ_CTRL, &reg_a_acq_ctrl);
418 reg_a_acq_ctrl |= MASK_AMER_OFF_REG; 419 reg_a_acq_ctrl |= MASK_AMER_OFF_REG;
419 hw_set_dxx_reg(phw_data, REG_A_ACQ_CTRL, reg_a_acq_ctrl); 420 hw_set_dxx_reg(phw_data, REG_A_ACQ_CTRL, reg_a_acq_ctrl);
420 421
421 hw_get_dxx_reg(phw_data, REG_B_ACQ_CTRL, &reg_b_acq_ctrl); 422 hw_get_dxx_reg(phw_data, REG_B_ACQ_CTRL, &reg_b_acq_ctrl);
422 reg_b_acq_ctrl |= MASK_BMER_OFF_REG; 423 reg_b_acq_ctrl |= MASK_BMER_OFF_REG;
423 hw_set_dxx_reg(phw_data, REG_B_ACQ_CTRL, reg_b_acq_ctrl); 424 hw_set_dxx_reg(phw_data, REG_B_ACQ_CTRL, reg_b_acq_ctrl);
424 425
425 // c. Make sure MAC is in receiving mode 426 // c. Make sure MAC is in receiving mode
426 // d. Turn ON ADC calibration 427 // d. Turn ON ADC calibration
427 // - ADC calibrator is triggered by this signal rising from 0 to 1 428 // - ADC calibrator is triggered by this signal rising from 0 to 1
428 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val); 429 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val);
429 val &= ~MASK_ADC_DC_CAL_STR; 430 val &= ~MASK_ADC_DC_CAL_STR;
430 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val); 431 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val);
431 432
432 val |= MASK_ADC_DC_CAL_STR; 433 val |= MASK_ADC_DC_CAL_STR;
433 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val); 434 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val);
434 435
435 // e. The result are shown in "adc_dc_cal_i[8:0] and adc_dc_cal_q[8:0]" 436 // e. The result are shown in "adc_dc_cal_i[8:0] and adc_dc_cal_q[8:0]"
436 #ifdef _DEBUG 437 #ifdef _DEBUG
437 hw_get_dxx_reg(phw_data, REG_OFFSET_READ, &val); 438 hw_get_dxx_reg(phw_data, REG_OFFSET_READ, &val);
438 PHY_DEBUG(("[CAL] REG_OFFSET_READ = 0x%08X\n", val)); 439 PHY_DEBUG(("[CAL] REG_OFFSET_READ = 0x%08X\n", val));
439 440
440 PHY_DEBUG(("[CAL] ** adc_dc_cal_i = %d (0x%04X)\n", 441 PHY_DEBUG(("[CAL] ** adc_dc_cal_i = %d (0x%04X)\n",
441 _s9_to_s32(val&0x000001FF), val&0x000001FF)); 442 _s9_to_s32(val&0x000001FF), val&0x000001FF));
442 PHY_DEBUG(("[CAL] ** adc_dc_cal_q = %d (0x%04X)\n", 443 PHY_DEBUG(("[CAL] ** adc_dc_cal_q = %d (0x%04X)\n",
443 _s9_to_s32((val&0x0003FE00)>>9), (val&0x0003FE00)>>9)); 444 _s9_to_s32((val&0x0003FE00)>>9), (val&0x0003FE00)>>9));
444 #endif 445 #endif
445 446
446 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val); 447 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val);
447 val &= ~MASK_ADC_DC_CAL_STR; 448 val &= ~MASK_ADC_DC_CAL_STR;
448 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val); 449 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val);
449 450
450 // f. Turn on BB RX 451 // f. Turn on BB RX
451 //hw_get_dxx_reg(phw_data, REG_A_ACQ_CTRL, &reg_a_acq_ctrl); 452 //hw_get_dxx_reg(phw_data, REG_A_ACQ_CTRL, &reg_a_acq_ctrl);
452 reg_a_acq_ctrl &= ~MASK_AMER_OFF_REG; 453 reg_a_acq_ctrl &= ~MASK_AMER_OFF_REG;
453 hw_set_dxx_reg(phw_data, REG_A_ACQ_CTRL, reg_a_acq_ctrl); 454 hw_set_dxx_reg(phw_data, REG_A_ACQ_CTRL, reg_a_acq_ctrl);
454 455
455 //hw_get_dxx_reg(phw_data, REG_B_ACQ_CTRL, &reg_b_acq_ctrl); 456 //hw_get_dxx_reg(phw_data, REG_B_ACQ_CTRL, &reg_b_acq_ctrl);
456 reg_b_acq_ctrl &= ~MASK_BMER_OFF_REG; 457 reg_b_acq_ctrl &= ~MASK_BMER_OFF_REG;
457 hw_set_dxx_reg(phw_data, REG_B_ACQ_CTRL, reg_b_acq_ctrl); 458 hw_set_dxx_reg(phw_data, REG_B_ACQ_CTRL, reg_b_acq_ctrl);
458 459
459 // g. Enable AGC 460 // g. Enable AGC
460 //hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val); 461 //hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val);
461 reg_agc_ctrl3 |= BIT(2); 462 reg_agc_ctrl3 |= BIT(2);
462 reg_agc_ctrl3 &= ~(MASK_LNA_FIX_GAIN|MASK_AGC_FIX); 463 reg_agc_ctrl3 &= ~(MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
463 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3); 464 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
464 } 465 }
465 466
466 //////////////////////////////////////////////////////// 467 ////////////////////////////////////////////////////////
467 void _txidac_dc_offset_cancellation_winbond(hw_data_t *phw_data) 468 void _txidac_dc_offset_cancellation_winbond(hw_data_t *phw_data)
468 { 469 {
469 u32 reg_agc_ctrl3; 470 u32 reg_agc_ctrl3;
470 u32 reg_mode_ctrl; 471 u32 reg_mode_ctrl;
471 u32 reg_dc_cancel; 472 u32 reg_dc_cancel;
472 s32 iqcal_image_i; 473 s32 iqcal_image_i;
473 s32 iqcal_image_q; 474 s32 iqcal_image_q;
474 u32 sqsum; 475 u32 sqsum;
475 s32 mag_0; 476 s32 mag_0;
476 s32 mag_1; 477 s32 mag_1;
477 s32 fix_cancel_dc_i = 0; 478 s32 fix_cancel_dc_i = 0;
478 u32 val; 479 u32 val;
479 int loop; 480 int loop;
480 481
481 PHY_DEBUG(("[CAL] -> [2]_txidac_dc_offset_cancellation()\n")); 482 PHY_DEBUG(("[CAL] -> [2]_txidac_dc_offset_cancellation()\n"));
482 483
483 // a. Set to "TX calibration mode" 484 // a. Set to "TX calibration mode"
484 485
485 //0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits 486 //0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits
486 phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2); 487 phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2);
487 //0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit 488 //0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit
488 phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6); 489 phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6);
489 //0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized 490 //0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized
490 phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A); 491 phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A);
491 //0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized 492 //0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized
492 phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C); 493 phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C);
493 //0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode 494 //0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode
494 phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0); 495 phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0);
495 496
496 hw_set_dxx_reg(phw_data, 0x58, 0x30303030); // IQ_Alpha Changed 497 hw_set_dxx_reg(phw_data, 0x58, 0x30303030); // IQ_Alpha Changed
497 498
498 // a. Disable AGC 499 // a. Disable AGC
499 hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3); 500 hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3);
500 reg_agc_ctrl3 &= ~BIT(2); 501 reg_agc_ctrl3 &= ~BIT(2);
501 reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX); 502 reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
502 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3); 503 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
503 504
504 hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val); 505 hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val);
505 val |= MASK_AGC_FIX_GAIN; 506 val |= MASK_AGC_FIX_GAIN;
506 hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val); 507 hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val);
507 508
508 // b. set iqcal_mode[1:0] to 0x2 and set iqcal_tone[3:2] to 0 509 // b. set iqcal_mode[1:0] to 0x2 and set iqcal_tone[3:2] to 0
509 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl); 510 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
510 511
511 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl)); 512 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
512 reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE); 513 reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE);
513 514
514 // mode=2, tone=0 515 // mode=2, tone=0
515 //reg_mode_ctrl |= (MASK_CALIB_START|2); 516 //reg_mode_ctrl |= (MASK_CALIB_START|2);
516 517
517 // mode=2, tone=1 518 // mode=2, tone=1
518 //reg_mode_ctrl |= (MASK_CALIB_START|2|(1<<2)); 519 //reg_mode_ctrl |= (MASK_CALIB_START|2|(1<<2));
519 520
520 // mode=2, tone=2 521 // mode=2, tone=2
521 reg_mode_ctrl |= (MASK_CALIB_START|2|(2<<2)); 522 reg_mode_ctrl |= (MASK_CALIB_START|2|(2<<2));
522 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 523 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
523 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 524 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
524 525
525 hw_get_dxx_reg(phw_data, 0x5C, &reg_dc_cancel); 526 hw_get_dxx_reg(phw_data, 0x5C, &reg_dc_cancel);
526 PHY_DEBUG(("[CAL] DC_CANCEL (read) = 0x%08X\n", reg_dc_cancel)); 527 PHY_DEBUG(("[CAL] DC_CANCEL (read) = 0x%08X\n", reg_dc_cancel));
527 528
528 for (loop = 0; loop < LOOP_TIMES; loop++) 529 for (loop = 0; loop < LOOP_TIMES; loop++)
529 { 530 {
530 PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop)); 531 PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop));
531 532
532 // c. 533 // c.
533 // reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel 534 // reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel
534 reg_dc_cancel &= ~(0x03FF); 535 reg_dc_cancel &= ~(0x03FF);
535 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); 536 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
536 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); 537 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
537 538
538 hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val); 539 hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
539 PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val)); 540 PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val));
540 541
541 iqcal_image_i = _s13_to_s32(val & 0x00001FFF); 542 iqcal_image_i = _s13_to_s32(val & 0x00001FFF);
542 iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13); 543 iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
543 sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q; 544 sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q;
544 mag_0 = (s32) _sqrt(sqsum); 545 mag_0 = (s32) _sqrt(sqsum);
545 PHY_DEBUG(("[CAL] mag_0=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n", 546 PHY_DEBUG(("[CAL] mag_0=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
546 mag_0, iqcal_image_i, iqcal_image_q)); 547 mag_0, iqcal_image_i, iqcal_image_q));
547 548
548 // d. 549 // d.
549 reg_dc_cancel |= (1 << CANCEL_DC_I_SHIFT); 550 reg_dc_cancel |= (1 << CANCEL_DC_I_SHIFT);
550 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); 551 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
551 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); 552 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
552 553
553 hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val); 554 hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
554 PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val)); 555 PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val));
555 556
556 iqcal_image_i = _s13_to_s32(val & 0x00001FFF); 557 iqcal_image_i = _s13_to_s32(val & 0x00001FFF);
557 iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13); 558 iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
558 sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q; 559 sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q;
559 mag_1 = (s32) _sqrt(sqsum); 560 mag_1 = (s32) _sqrt(sqsum);
560 PHY_DEBUG(("[CAL] mag_1=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n", 561 PHY_DEBUG(("[CAL] mag_1=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
561 mag_1, iqcal_image_i, iqcal_image_q)); 562 mag_1, iqcal_image_i, iqcal_image_q));
562 563
563 // e. Calculate the correct DC offset cancellation value for I 564 // e. Calculate the correct DC offset cancellation value for I
564 if (mag_0 != mag_1) 565 if (mag_0 != mag_1)
565 { 566 {
566 fix_cancel_dc_i = (mag_0*10000) / (mag_0*10000 - mag_1*10000); 567 fix_cancel_dc_i = (mag_0*10000) / (mag_0*10000 - mag_1*10000);
567 } 568 }
568 else 569 else
569 { 570 {
570 if (mag_0 == mag_1) 571 if (mag_0 == mag_1)
571 { 572 {
572 PHY_DEBUG(("[CAL] ***** mag_0 = mag_1 !!\n")); 573 PHY_DEBUG(("[CAL] ***** mag_0 = mag_1 !!\n"));
573 } 574 }
574 575
575 fix_cancel_dc_i = 0; 576 fix_cancel_dc_i = 0;
576 } 577 }
577 578
578 PHY_DEBUG(("[CAL] ** fix_cancel_dc_i = %d (0x%04X)\n", 579 PHY_DEBUG(("[CAL] ** fix_cancel_dc_i = %d (0x%04X)\n",
579 fix_cancel_dc_i, _s32_to_s5(fix_cancel_dc_i))); 580 fix_cancel_dc_i, _s32_to_s5(fix_cancel_dc_i)));
580 581
581 if ((abs(mag_1-mag_0)*6) > mag_0) 582 if ((abs(mag_1-mag_0)*6) > mag_0)
582 { 583 {
583 break; 584 break;
584 } 585 }
585 } 586 }
586 587
587 if ( loop >= 19 ) 588 if ( loop >= 19 )
588 fix_cancel_dc_i = 0; 589 fix_cancel_dc_i = 0;
589 590
590 reg_dc_cancel &= ~(0x03FF); 591 reg_dc_cancel &= ~(0x03FF);
591 reg_dc_cancel |= (_s32_to_s5(fix_cancel_dc_i) << CANCEL_DC_I_SHIFT); 592 reg_dc_cancel |= (_s32_to_s5(fix_cancel_dc_i) << CANCEL_DC_I_SHIFT);
592 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); 593 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
593 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); 594 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
594 595
595 // g. 596 // g.
596 reg_mode_ctrl &= ~MASK_CALIB_START; 597 reg_mode_ctrl &= ~MASK_CALIB_START;
597 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 598 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
598 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 599 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
599 } 600 }
600 601
601 /////////////////////////////////////////////////////// 602 ///////////////////////////////////////////////////////
602 void _txqdac_dc_offset_cacellation_winbond(hw_data_t *phw_data) 603 void _txqdac_dc_offset_cacellation_winbond(hw_data_t *phw_data)
603 { 604 {
604 u32 reg_agc_ctrl3; 605 u32 reg_agc_ctrl3;
605 u32 reg_mode_ctrl; 606 u32 reg_mode_ctrl;
606 u32 reg_dc_cancel; 607 u32 reg_dc_cancel;
607 s32 iqcal_image_i; 608 s32 iqcal_image_i;
608 s32 iqcal_image_q; 609 s32 iqcal_image_q;
609 u32 sqsum; 610 u32 sqsum;
610 s32 mag_0; 611 s32 mag_0;
611 s32 mag_1; 612 s32 mag_1;
612 s32 fix_cancel_dc_q = 0; 613 s32 fix_cancel_dc_q = 0;
613 u32 val; 614 u32 val;
614 int loop; 615 int loop;
615 616
616 PHY_DEBUG(("[CAL] -> [3]_txqdac_dc_offset_cacellation()\n")); 617 PHY_DEBUG(("[CAL] -> [3]_txqdac_dc_offset_cacellation()\n"));
617 //0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits 618 //0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits
618 phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2); 619 phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2);
619 //0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit 620 //0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit
620 phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6); 621 phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6);
621 //0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized 622 //0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized
622 phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A); 623 phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A);
623 //0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized 624 //0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized
624 phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C); 625 phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C);
625 //0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode 626 //0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode
626 phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0); 627 phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0);
627 628
628 hw_set_dxx_reg(phw_data, 0x58, 0x30303030); // IQ_Alpha Changed 629 hw_set_dxx_reg(phw_data, 0x58, 0x30303030); // IQ_Alpha Changed
629 630
630 // a. Disable AGC 631 // a. Disable AGC
631 hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3); 632 hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3);
632 reg_agc_ctrl3 &= ~BIT(2); 633 reg_agc_ctrl3 &= ~BIT(2);
633 reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX); 634 reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
634 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3); 635 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
635 636
636 hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val); 637 hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val);
637 val |= MASK_AGC_FIX_GAIN; 638 val |= MASK_AGC_FIX_GAIN;
638 hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val); 639 hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val);
639 640
640 // a. set iqcal_mode[1:0] to 0x3 and set iqcal_tone[3:2] to 0 641 // a. set iqcal_mode[1:0] to 0x3 and set iqcal_tone[3:2] to 0
641 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl); 642 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
642 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl)); 643 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
643 644
644 //reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE); 645 //reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE);
645 reg_mode_ctrl &= ~(MASK_IQCAL_MODE); 646 reg_mode_ctrl &= ~(MASK_IQCAL_MODE);
646 reg_mode_ctrl |= (MASK_CALIB_START|3); 647 reg_mode_ctrl |= (MASK_CALIB_START|3);
647 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 648 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
648 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 649 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
649 650
650 hw_get_dxx_reg(phw_data, 0x5C, &reg_dc_cancel); 651 hw_get_dxx_reg(phw_data, 0x5C, &reg_dc_cancel);
651 PHY_DEBUG(("[CAL] DC_CANCEL (read) = 0x%08X\n", reg_dc_cancel)); 652 PHY_DEBUG(("[CAL] DC_CANCEL (read) = 0x%08X\n", reg_dc_cancel));
652 653
653 for (loop = 0; loop < LOOP_TIMES; loop++) 654 for (loop = 0; loop < LOOP_TIMES; loop++)
654 { 655 {
655 PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop)); 656 PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop));
656 657
657 // b. 658 // b.
658 // reset cancel_dc_q[4:0] in register DC_Cancel 659 // reset cancel_dc_q[4:0] in register DC_Cancel
659 reg_dc_cancel &= ~(0x001F); 660 reg_dc_cancel &= ~(0x001F);
660 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); 661 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
661 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); 662 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
662 663
663 hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val); 664 hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
664 PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val)); 665 PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val));
665 666
666 iqcal_image_i = _s13_to_s32(val & 0x00001FFF); 667 iqcal_image_i = _s13_to_s32(val & 0x00001FFF);
667 iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13); 668 iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
668 sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q; 669 sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q;
669 mag_0 = _sqrt(sqsum); 670 mag_0 = _sqrt(sqsum);
670 PHY_DEBUG(("[CAL] mag_0=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n", 671 PHY_DEBUG(("[CAL] mag_0=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
671 mag_0, iqcal_image_i, iqcal_image_q)); 672 mag_0, iqcal_image_i, iqcal_image_q));
672 673
673 // c. 674 // c.
674 reg_dc_cancel |= (1 << CANCEL_DC_Q_SHIFT); 675 reg_dc_cancel |= (1 << CANCEL_DC_Q_SHIFT);
675 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); 676 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
676 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); 677 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
677 678
678 hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val); 679 hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
679 PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val)); 680 PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val));
680 681
681 iqcal_image_i = _s13_to_s32(val & 0x00001FFF); 682 iqcal_image_i = _s13_to_s32(val & 0x00001FFF);
682 iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13); 683 iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
683 sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q; 684 sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q;
684 mag_1 = _sqrt(sqsum); 685 mag_1 = _sqrt(sqsum);
685 PHY_DEBUG(("[CAL] mag_1=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n", 686 PHY_DEBUG(("[CAL] mag_1=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
686 mag_1, iqcal_image_i, iqcal_image_q)); 687 mag_1, iqcal_image_i, iqcal_image_q));
687 688
688 // d. Calculate the correct DC offset cancellation value for I 689 // d. Calculate the correct DC offset cancellation value for I
689 if (mag_0 != mag_1) 690 if (mag_0 != mag_1)
690 { 691 {
691 fix_cancel_dc_q = (mag_0*10000) / (mag_0*10000 - mag_1*10000); 692 fix_cancel_dc_q = (mag_0*10000) / (mag_0*10000 - mag_1*10000);
692 } 693 }
693 else 694 else
694 { 695 {
695 if (mag_0 == mag_1) 696 if (mag_0 == mag_1)
696 { 697 {
697 PHY_DEBUG(("[CAL] ***** mag_0 = mag_1 !!\n")); 698 PHY_DEBUG(("[CAL] ***** mag_0 = mag_1 !!\n"));
698 } 699 }
699 700
700 fix_cancel_dc_q = 0; 701 fix_cancel_dc_q = 0;
701 } 702 }
702 703
703 PHY_DEBUG(("[CAL] ** fix_cancel_dc_q = %d (0x%04X)\n", 704 PHY_DEBUG(("[CAL] ** fix_cancel_dc_q = %d (0x%04X)\n",
704 fix_cancel_dc_q, _s32_to_s5(fix_cancel_dc_q))); 705 fix_cancel_dc_q, _s32_to_s5(fix_cancel_dc_q)));
705 706
706 if ((abs(mag_1-mag_0)*6) > mag_0) 707 if ((abs(mag_1-mag_0)*6) > mag_0)
707 { 708 {
708 break; 709 break;
709 } 710 }
710 } 711 }
711 712
712 if ( loop >= 19 ) 713 if ( loop >= 19 )
713 fix_cancel_dc_q = 0; 714 fix_cancel_dc_q = 0;
714 715
715 reg_dc_cancel &= ~(0x001F); 716 reg_dc_cancel &= ~(0x001F);
716 reg_dc_cancel |= (_s32_to_s5(fix_cancel_dc_q) << CANCEL_DC_Q_SHIFT); 717 reg_dc_cancel |= (_s32_to_s5(fix_cancel_dc_q) << CANCEL_DC_Q_SHIFT);
717 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel); 718 hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
718 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel)); 719 PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
719 720
720 721
721 // f. 722 // f.
722 reg_mode_ctrl &= ~MASK_CALIB_START; 723 reg_mode_ctrl &= ~MASK_CALIB_START;
723 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 724 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
724 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 725 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
725 } 726 }
726 727
727 //20060612.1.a 20060718.1 Modify 728 //20060612.1.a 20060718.1 Modify
728 u8 _tx_iq_calibration_loop_winbond(hw_data_t *phw_data, 729 u8 _tx_iq_calibration_loop_winbond(hw_data_t *phw_data,
729 s32 a_2_threshold, 730 s32 a_2_threshold,
730 s32 b_2_threshold) 731 s32 b_2_threshold)
731 { 732 {
732 u32 reg_mode_ctrl; 733 u32 reg_mode_ctrl;
733 s32 iq_mag_0_tx; 734 s32 iq_mag_0_tx;
734 s32 iqcal_tone_i0; 735 s32 iqcal_tone_i0;
735 s32 iqcal_tone_q0; 736 s32 iqcal_tone_q0;
736 s32 iqcal_tone_i; 737 s32 iqcal_tone_i;
737 s32 iqcal_tone_q; 738 s32 iqcal_tone_q;
738 u32 sqsum; 739 u32 sqsum;
739 s32 rot_i_b; 740 s32 rot_i_b;
740 s32 rot_q_b; 741 s32 rot_q_b;
741 s32 tx_cal_flt_b[4]; 742 s32 tx_cal_flt_b[4];
742 s32 tx_cal[4]; 743 s32 tx_cal[4];
743 s32 tx_cal_reg[4]; 744 s32 tx_cal_reg[4];
744 s32 a_2, b_2; 745 s32 a_2, b_2;
745 s32 sin_b, sin_2b; 746 s32 sin_b, sin_2b;
746 s32 cos_b, cos_2b; 747 s32 cos_b, cos_2b;
747 s32 divisor; 748 s32 divisor;
748 s32 temp1, temp2; 749 s32 temp1, temp2;
749 u32 val; 750 u32 val;
750 u16 loop; 751 u16 loop;
751 s32 iqcal_tone_i_avg,iqcal_tone_q_avg; 752 s32 iqcal_tone_i_avg,iqcal_tone_q_avg;
752 u8 verify_count; 753 u8 verify_count;
753 int capture_time; 754 int capture_time;
754 755
755 PHY_DEBUG(("[CAL] -> _tx_iq_calibration_loop()\n")); 756 PHY_DEBUG(("[CAL] -> _tx_iq_calibration_loop()\n"));
756 PHY_DEBUG(("[CAL] ** a_2_threshold = %d\n", a_2_threshold)); 757 PHY_DEBUG(("[CAL] ** a_2_threshold = %d\n", a_2_threshold));
757 PHY_DEBUG(("[CAL] ** b_2_threshold = %d\n", b_2_threshold)); 758 PHY_DEBUG(("[CAL] ** b_2_threshold = %d\n", b_2_threshold));
758 759
759 verify_count = 0; 760 verify_count = 0;
760 761
761 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl); 762 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
762 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl)); 763 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
763 764
764 loop = LOOP_TIMES; 765 loop = LOOP_TIMES;
765 766
766 while (loop > 0) 767 while (loop > 0)
767 { 768 {
768 PHY_DEBUG(("[CAL] [%d.] <_tx_iq_calibration_loop>\n", (LOOP_TIMES-loop+1))); 769 PHY_DEBUG(("[CAL] [%d.] <_tx_iq_calibration_loop>\n", (LOOP_TIMES-loop+1)));
769 770
770 iqcal_tone_i_avg=0; 771 iqcal_tone_i_avg=0;
771 iqcal_tone_q_avg=0; 772 iqcal_tone_q_avg=0;
772 if( !hw_set_dxx_reg(phw_data, 0x3C, 0x00) ) // 20060718.1 modify 773 if( !hw_set_dxx_reg(phw_data, 0x3C, 0x00) ) // 20060718.1 modify
773 return 0; 774 return 0;
774 for(capture_time=0;capture_time<10;capture_time++) 775 for(capture_time=0;capture_time<10;capture_time++)
775 { 776 {
776 // a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" to 0x1 to 777 // a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" to 0x1 to
777 // enable "IQ alibration Mode II" 778 // enable "IQ alibration Mode II"
778 reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE); 779 reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE);
779 reg_mode_ctrl &= ~MASK_IQCAL_MODE; 780 reg_mode_ctrl &= ~MASK_IQCAL_MODE;
780 reg_mode_ctrl |= (MASK_CALIB_START|0x02); 781 reg_mode_ctrl |= (MASK_CALIB_START|0x02);
781 reg_mode_ctrl |= (MASK_CALIB_START|0x02|2<<2); 782 reg_mode_ctrl |= (MASK_CALIB_START|0x02|2<<2);
782 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 783 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
783 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 784 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
784 785
785 // b. 786 // b.
786 hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val); 787 hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);
787 PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val)); 788 PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val));
788 789
789 iqcal_tone_i0 = _s13_to_s32(val & 0x00001FFF); 790 iqcal_tone_i0 = _s13_to_s32(val & 0x00001FFF);
790 iqcal_tone_q0 = _s13_to_s32((val & 0x03FFE000) >> 13); 791 iqcal_tone_q0 = _s13_to_s32((val & 0x03FFE000) >> 13);
791 PHY_DEBUG(("[CAL] ** iqcal_tone_i0=%d, iqcal_tone_q0=%d\n", 792 PHY_DEBUG(("[CAL] ** iqcal_tone_i0=%d, iqcal_tone_q0=%d\n",
792 iqcal_tone_i0, iqcal_tone_q0)); 793 iqcal_tone_i0, iqcal_tone_q0));
793 794
794 sqsum = iqcal_tone_i0*iqcal_tone_i0 + 795 sqsum = iqcal_tone_i0*iqcal_tone_i0 +
795 iqcal_tone_q0*iqcal_tone_q0; 796 iqcal_tone_q0*iqcal_tone_q0;
796 iq_mag_0_tx = (s32) _sqrt(sqsum); 797 iq_mag_0_tx = (s32) _sqrt(sqsum);
797 PHY_DEBUG(("[CAL] ** iq_mag_0_tx=%d\n", iq_mag_0_tx)); 798 PHY_DEBUG(("[CAL] ** iq_mag_0_tx=%d\n", iq_mag_0_tx));
798 799
799 // c. Set "calib_start" to 0x0 800 // c. Set "calib_start" to 0x0
800 reg_mode_ctrl &= ~MASK_CALIB_START; 801 reg_mode_ctrl &= ~MASK_CALIB_START;
801 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 802 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
802 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 803 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
803 804
804 // d. Set iqcal_mode[1:0] to 0x3 and set "calib_start" to 0x1 to 805 // d. Set iqcal_mode[1:0] to 0x3 and set "calib_start" to 0x1 to
805 // enable "IQ alibration Mode II" 806 // enable "IQ alibration Mode II"
806 //hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val); 807 //hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val);
807 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl); 808 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
808 reg_mode_ctrl &= ~MASK_IQCAL_MODE; 809 reg_mode_ctrl &= ~MASK_IQCAL_MODE;
809 reg_mode_ctrl |= (MASK_CALIB_START|0x03); 810 reg_mode_ctrl |= (MASK_CALIB_START|0x03);
810 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 811 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
811 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 812 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
812 813
813 // e. 814 // e.
814 hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val); 815 hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);
815 PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val)); 816 PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val));
816 817
817 iqcal_tone_i = _s13_to_s32(val & 0x00001FFF); 818 iqcal_tone_i = _s13_to_s32(val & 0x00001FFF);
818 iqcal_tone_q = _s13_to_s32((val & 0x03FFE000) >> 13); 819 iqcal_tone_q = _s13_to_s32((val & 0x03FFE000) >> 13);
819 PHY_DEBUG(("[CAL] ** iqcal_tone_i = %d, iqcal_tone_q = %d\n", 820 PHY_DEBUG(("[CAL] ** iqcal_tone_i = %d, iqcal_tone_q = %d\n",
820 iqcal_tone_i, iqcal_tone_q)); 821 iqcal_tone_i, iqcal_tone_q));
821 if( capture_time == 0) 822 if( capture_time == 0)
822 { 823 {
823 continue; 824 continue;
824 } 825 }
825 else 826 else
826 { 827 {
827 iqcal_tone_i_avg=( iqcal_tone_i_avg*(capture_time-1) +iqcal_tone_i)/capture_time; 828 iqcal_tone_i_avg=( iqcal_tone_i_avg*(capture_time-1) +iqcal_tone_i)/capture_time;
828 iqcal_tone_q_avg=( iqcal_tone_q_avg*(capture_time-1) +iqcal_tone_q)/capture_time; 829 iqcal_tone_q_avg=( iqcal_tone_q_avg*(capture_time-1) +iqcal_tone_q)/capture_time;
829 } 830 }
830 } 831 }
831 832
832 iqcal_tone_i = iqcal_tone_i_avg; 833 iqcal_tone_i = iqcal_tone_i_avg;
833 iqcal_tone_q = iqcal_tone_q_avg; 834 iqcal_tone_q = iqcal_tone_q_avg;
834 835
835 836
836 rot_i_b = (iqcal_tone_i * iqcal_tone_i0 + 837 rot_i_b = (iqcal_tone_i * iqcal_tone_i0 +
837 iqcal_tone_q * iqcal_tone_q0) / 1024; 838 iqcal_tone_q * iqcal_tone_q0) / 1024;
838 rot_q_b = (iqcal_tone_i * iqcal_tone_q0 * (-1) + 839 rot_q_b = (iqcal_tone_i * iqcal_tone_q0 * (-1) +
839 iqcal_tone_q * iqcal_tone_i0) / 1024; 840 iqcal_tone_q * iqcal_tone_i0) / 1024;
840 PHY_DEBUG(("[CAL] ** rot_i_b = %d, rot_q_b = %d\n", 841 PHY_DEBUG(("[CAL] ** rot_i_b = %d, rot_q_b = %d\n",
841 rot_i_b, rot_q_b)); 842 rot_i_b, rot_q_b));
842 843
843 // f. 844 // f.
844 divisor = ((iq_mag_0_tx * iq_mag_0_tx * 2)/1024 - rot_i_b) * 2; 845 divisor = ((iq_mag_0_tx * iq_mag_0_tx * 2)/1024 - rot_i_b) * 2;
845 846
846 if (divisor == 0) 847 if (divisor == 0)
847 { 848 {
848 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> ERROR *******\n")); 849 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> ERROR *******\n"));
849 PHY_DEBUG(("[CAL] ** divisor=0 to calculate EPS and THETA !!\n")); 850 PHY_DEBUG(("[CAL] ** divisor=0 to calculate EPS and THETA !!\n"));
850 PHY_DEBUG(("[CAL] ******************************************\n")); 851 PHY_DEBUG(("[CAL] ******************************************\n"));
851 break; 852 break;
852 } 853 }
853 854
854 a_2 = (rot_i_b * 32768) / divisor; 855 a_2 = (rot_i_b * 32768) / divisor;
855 b_2 = (rot_q_b * (-32768)) / divisor; 856 b_2 = (rot_q_b * (-32768)) / divisor;
856 PHY_DEBUG(("[CAL] ***** EPSILON/2 = %d\n", a_2)); 857 PHY_DEBUG(("[CAL] ***** EPSILON/2 = %d\n", a_2));
857 PHY_DEBUG(("[CAL] ***** THETA/2 = %d\n", b_2)); 858 PHY_DEBUG(("[CAL] ***** THETA/2 = %d\n", b_2));
858 859
859 phw_data->iq_rsdl_gain_tx_d2 = a_2; 860 phw_data->iq_rsdl_gain_tx_d2 = a_2;
860 phw_data->iq_rsdl_phase_tx_d2 = b_2; 861 phw_data->iq_rsdl_phase_tx_d2 = b_2;
861 862
862 //if ((abs(a_2) < 150) && (abs(b_2) < 100)) 863 //if ((abs(a_2) < 150) && (abs(b_2) < 100))
863 //if ((abs(a_2) < 200) && (abs(b_2) < 200)) 864 //if ((abs(a_2) < 200) && (abs(b_2) < 200))
864 if ((abs(a_2) < a_2_threshold) && (abs(b_2) < b_2_threshold)) 865 if ((abs(a_2) < a_2_threshold) && (abs(b_2) < b_2_threshold))
865 { 866 {
866 verify_count++; 867 verify_count++;
867 868
868 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *************\n")); 869 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *************\n"));
869 PHY_DEBUG(("[CAL] ** VERIFY OK # %d !!\n", verify_count)); 870 PHY_DEBUG(("[CAL] ** VERIFY OK # %d !!\n", verify_count));
870 PHY_DEBUG(("[CAL] ******************************************\n")); 871 PHY_DEBUG(("[CAL] ******************************************\n"));
871 872
872 if (verify_count > 2) 873 if (verify_count > 2)
873 { 874 {
874 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n")); 875 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n"));
875 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION (EPS,THETA) OK !!\n")); 876 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION (EPS,THETA) OK !!\n"));
876 PHY_DEBUG(("[CAL] **************************************\n")); 877 PHY_DEBUG(("[CAL] **************************************\n"));
877 return 0; 878 return 0;
878 } 879 }
879 880
880 continue; 881 continue;
881 } 882 }
882 else 883 else
883 { 884 {
884 verify_count = 0; 885 verify_count = 0;
885 } 886 }
886 887
887 _sin_cos(b_2, &sin_b, &cos_b); 888 _sin_cos(b_2, &sin_b, &cos_b);
888 _sin_cos(b_2*2, &sin_2b, &cos_2b); 889 _sin_cos(b_2*2, &sin_2b, &cos_2b);
889 PHY_DEBUG(("[CAL] ** sin(b/2)=%d, cos(b/2)=%d\n", sin_b, cos_b)); 890 PHY_DEBUG(("[CAL] ** sin(b/2)=%d, cos(b/2)=%d\n", sin_b, cos_b));
890 PHY_DEBUG(("[CAL] ** sin(b)=%d, cos(b)=%d\n", sin_2b, cos_2b)); 891 PHY_DEBUG(("[CAL] ** sin(b)=%d, cos(b)=%d\n", sin_2b, cos_2b));
891 892
892 if (cos_2b == 0) 893 if (cos_2b == 0)
893 { 894 {
894 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> ERROR *******\n")); 895 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> ERROR *******\n"));
895 PHY_DEBUG(("[CAL] ** cos(b)=0 !!\n")); 896 PHY_DEBUG(("[CAL] ** cos(b)=0 !!\n"));
896 PHY_DEBUG(("[CAL] ******************************************\n")); 897 PHY_DEBUG(("[CAL] ******************************************\n"));
897 break; 898 break;
898 } 899 }
899 900
900 // 1280 * 32768 = 41943040 901 // 1280 * 32768 = 41943040
901 temp1 = (41943040/cos_2b)*cos_b; 902 temp1 = (41943040/cos_2b)*cos_b;
902 903
903 //temp2 = (41943040/cos_2b)*sin_b*(-1); 904 //temp2 = (41943040/cos_2b)*sin_b*(-1);
904 if (phw_data->revision == 0x2002) // 1st-cut 905 if (phw_data->revision == 0x2002) // 1st-cut
905 { 906 {
906 temp2 = (41943040/cos_2b)*sin_b*(-1); 907 temp2 = (41943040/cos_2b)*sin_b*(-1);
907 } 908 }
908 else // 2nd-cut 909 else // 2nd-cut
909 { 910 {
910 temp2 = (41943040*4/cos_2b)*sin_b*(-1); 911 temp2 = (41943040*4/cos_2b)*sin_b*(-1);
911 } 912 }
912 913
913 tx_cal_flt_b[0] = _floor(temp1/(32768+a_2)); 914 tx_cal_flt_b[0] = _floor(temp1/(32768+a_2));
914 tx_cal_flt_b[1] = _floor(temp2/(32768+a_2)); 915 tx_cal_flt_b[1] = _floor(temp2/(32768+a_2));
915 tx_cal_flt_b[2] = _floor(temp2/(32768-a_2)); 916 tx_cal_flt_b[2] = _floor(temp2/(32768-a_2));
916 tx_cal_flt_b[3] = _floor(temp1/(32768-a_2)); 917 tx_cal_flt_b[3] = _floor(temp1/(32768-a_2));
917 PHY_DEBUG(("[CAL] ** tx_cal_flt_b[0] = %d\n", tx_cal_flt_b[0])); 918 PHY_DEBUG(("[CAL] ** tx_cal_flt_b[0] = %d\n", tx_cal_flt_b[0]));
918 PHY_DEBUG(("[CAL] tx_cal_flt_b[1] = %d\n", tx_cal_flt_b[1])); 919 PHY_DEBUG(("[CAL] tx_cal_flt_b[1] = %d\n", tx_cal_flt_b[1]));
919 PHY_DEBUG(("[CAL] tx_cal_flt_b[2] = %d\n", tx_cal_flt_b[2])); 920 PHY_DEBUG(("[CAL] tx_cal_flt_b[2] = %d\n", tx_cal_flt_b[2]));
920 PHY_DEBUG(("[CAL] tx_cal_flt_b[3] = %d\n", tx_cal_flt_b[3])); 921 PHY_DEBUG(("[CAL] tx_cal_flt_b[3] = %d\n", tx_cal_flt_b[3]));
921 922
922 tx_cal[2] = tx_cal_flt_b[2]; 923 tx_cal[2] = tx_cal_flt_b[2];
923 tx_cal[2] = tx_cal[2] +3; 924 tx_cal[2] = tx_cal[2] +3;
924 tx_cal[1] = tx_cal[2]; 925 tx_cal[1] = tx_cal[2];
925 tx_cal[3] = tx_cal_flt_b[3] - 128; 926 tx_cal[3] = tx_cal_flt_b[3] - 128;
926 tx_cal[0] = -tx_cal[3]+1; 927 tx_cal[0] = -tx_cal[3]+1;
927 928
928 PHY_DEBUG(("[CAL] tx_cal[0] = %d\n", tx_cal[0])); 929 PHY_DEBUG(("[CAL] tx_cal[0] = %d\n", tx_cal[0]));
929 PHY_DEBUG(("[CAL] tx_cal[1] = %d\n", tx_cal[1])); 930 PHY_DEBUG(("[CAL] tx_cal[1] = %d\n", tx_cal[1]));
930 PHY_DEBUG(("[CAL] tx_cal[2] = %d\n", tx_cal[2])); 931 PHY_DEBUG(("[CAL] tx_cal[2] = %d\n", tx_cal[2]));
931 PHY_DEBUG(("[CAL] tx_cal[3] = %d\n", tx_cal[3])); 932 PHY_DEBUG(("[CAL] tx_cal[3] = %d\n", tx_cal[3]));
932 933
933 //if ((tx_cal[0] == 0) && (tx_cal[1] == 0) && 934 //if ((tx_cal[0] == 0) && (tx_cal[1] == 0) &&
934 // (tx_cal[2] == 0) && (tx_cal[3] == 0)) 935 // (tx_cal[2] == 0) && (tx_cal[3] == 0))
935 //{ 936 //{
936 // PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *************\n")); 937 // PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *************\n"));
937 // PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION COMPLETE !!\n")); 938 // PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION COMPLETE !!\n"));
938 // PHY_DEBUG(("[CAL] ******************************************\n")); 939 // PHY_DEBUG(("[CAL] ******************************************\n"));
939 // return 0; 940 // return 0;
940 //} 941 //}
941 942
942 // g. 943 // g.
943 if (phw_data->revision == 0x2002) // 1st-cut 944 if (phw_data->revision == 0x2002) // 1st-cut
944 { 945 {
945 hw_get_dxx_reg(phw_data, 0x54, &val); 946 hw_get_dxx_reg(phw_data, 0x54, &val);
946 PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val)); 947 PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val));
947 tx_cal_reg[0] = _s4_to_s32((val & 0xF0000000) >> 28); 948 tx_cal_reg[0] = _s4_to_s32((val & 0xF0000000) >> 28);
948 tx_cal_reg[1] = _s4_to_s32((val & 0x0F000000) >> 24); 949 tx_cal_reg[1] = _s4_to_s32((val & 0x0F000000) >> 24);
949 tx_cal_reg[2] = _s4_to_s32((val & 0x00F00000) >> 20); 950 tx_cal_reg[2] = _s4_to_s32((val & 0x00F00000) >> 20);
950 tx_cal_reg[3] = _s4_to_s32((val & 0x000F0000) >> 16); 951 tx_cal_reg[3] = _s4_to_s32((val & 0x000F0000) >> 16);
951 } 952 }
952 else // 2nd-cut 953 else // 2nd-cut
953 { 954 {
954 hw_get_dxx_reg(phw_data, 0x3C, &val); 955 hw_get_dxx_reg(phw_data, 0x3C, &val);
955 PHY_DEBUG(("[CAL] ** 0x3C = 0x%08X\n", val)); 956 PHY_DEBUG(("[CAL] ** 0x3C = 0x%08X\n", val));
956 tx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27); 957 tx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27);
957 tx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21); 958 tx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21);
958 tx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15); 959 tx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15);
959 tx_cal_reg[3] = _s5_to_s32((val & 0x00007C00) >> 10); 960 tx_cal_reg[3] = _s5_to_s32((val & 0x00007C00) >> 10);
960 961
961 } 962 }
962 963
963 PHY_DEBUG(("[CAL] ** tx_cal_reg[0] = %d\n", tx_cal_reg[0])); 964 PHY_DEBUG(("[CAL] ** tx_cal_reg[0] = %d\n", tx_cal_reg[0]));
964 PHY_DEBUG(("[CAL] tx_cal_reg[1] = %d\n", tx_cal_reg[1])); 965 PHY_DEBUG(("[CAL] tx_cal_reg[1] = %d\n", tx_cal_reg[1]));
965 PHY_DEBUG(("[CAL] tx_cal_reg[2] = %d\n", tx_cal_reg[2])); 966 PHY_DEBUG(("[CAL] tx_cal_reg[2] = %d\n", tx_cal_reg[2]));
966 PHY_DEBUG(("[CAL] tx_cal_reg[3] = %d\n", tx_cal_reg[3])); 967 PHY_DEBUG(("[CAL] tx_cal_reg[3] = %d\n", tx_cal_reg[3]));
967 968
968 if (phw_data->revision == 0x2002) // 1st-cut 969 if (phw_data->revision == 0x2002) // 1st-cut
969 { 970 {
970 if (((tx_cal_reg[0]==7) || (tx_cal_reg[0]==(-8))) && 971 if (((tx_cal_reg[0]==7) || (tx_cal_reg[0]==(-8))) &&
971 ((tx_cal_reg[3]==7) || (tx_cal_reg[3]==(-8)))) 972 ((tx_cal_reg[3]==7) || (tx_cal_reg[3]==(-8))))
972 { 973 {
973 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n")); 974 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n"));
974 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION SATUATION !!\n")); 975 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION SATUATION !!\n"));
975 PHY_DEBUG(("[CAL] **************************************\n")); 976 PHY_DEBUG(("[CAL] **************************************\n"));
976 break; 977 break;
977 } 978 }
978 } 979 }
979 else // 2nd-cut 980 else // 2nd-cut
980 { 981 {
981 if (((tx_cal_reg[0]==31) || (tx_cal_reg[0]==(-32))) && 982 if (((tx_cal_reg[0]==31) || (tx_cal_reg[0]==(-32))) &&
982 ((tx_cal_reg[3]==31) || (tx_cal_reg[3]==(-32)))) 983 ((tx_cal_reg[3]==31) || (tx_cal_reg[3]==(-32))))
983 { 984 {
984 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n")); 985 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration_loop> *********\n"));
985 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION SATUATION !!\n")); 986 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION SATUATION !!\n"));
986 PHY_DEBUG(("[CAL] **************************************\n")); 987 PHY_DEBUG(("[CAL] **************************************\n"));
987 break; 988 break;
988 } 989 }
989 } 990 }
990 991
991 tx_cal[0] = tx_cal[0] + tx_cal_reg[0]; 992 tx_cal[0] = tx_cal[0] + tx_cal_reg[0];
992 tx_cal[1] = tx_cal[1] + tx_cal_reg[1]; 993 tx_cal[1] = tx_cal[1] + tx_cal_reg[1];
993 tx_cal[2] = tx_cal[2] + tx_cal_reg[2]; 994 tx_cal[2] = tx_cal[2] + tx_cal_reg[2];
994 tx_cal[3] = tx_cal[3] + tx_cal_reg[3]; 995 tx_cal[3] = tx_cal[3] + tx_cal_reg[3];
995 PHY_DEBUG(("[CAL] ** apply tx_cal[0] = %d\n", tx_cal[0])); 996 PHY_DEBUG(("[CAL] ** apply tx_cal[0] = %d\n", tx_cal[0]));
996 PHY_DEBUG(("[CAL] apply tx_cal[1] = %d\n", tx_cal[1])); 997 PHY_DEBUG(("[CAL] apply tx_cal[1] = %d\n", tx_cal[1]));
997 PHY_DEBUG(("[CAL] apply tx_cal[2] = %d\n", tx_cal[2])); 998 PHY_DEBUG(("[CAL] apply tx_cal[2] = %d\n", tx_cal[2]));
998 PHY_DEBUG(("[CAL] apply tx_cal[3] = %d\n", tx_cal[3])); 999 PHY_DEBUG(("[CAL] apply tx_cal[3] = %d\n", tx_cal[3]));
999 1000
1000 if (phw_data->revision == 0x2002) // 1st-cut 1001 if (phw_data->revision == 0x2002) // 1st-cut
1001 { 1002 {
1002 val &= 0x0000FFFF; 1003 val &= 0x0000FFFF;
1003 val |= ((_s32_to_s4(tx_cal[0]) << 28)| 1004 val |= ((_s32_to_s4(tx_cal[0]) << 28)|
1004 (_s32_to_s4(tx_cal[1]) << 24)| 1005 (_s32_to_s4(tx_cal[1]) << 24)|
1005 (_s32_to_s4(tx_cal[2]) << 20)| 1006 (_s32_to_s4(tx_cal[2]) << 20)|
1006 (_s32_to_s4(tx_cal[3]) << 16)); 1007 (_s32_to_s4(tx_cal[3]) << 16));
1007 hw_set_dxx_reg(phw_data, 0x54, val); 1008 hw_set_dxx_reg(phw_data, 0x54, val);
1008 PHY_DEBUG(("[CAL] ** CALIB_DATA = 0x%08X\n", val)); 1009 PHY_DEBUG(("[CAL] ** CALIB_DATA = 0x%08X\n", val));
1009 return 0; 1010 return 0;
1010 } 1011 }
1011 else // 2nd-cut 1012 else // 2nd-cut
1012 { 1013 {
1013 val &= 0x000003FF; 1014 val &= 0x000003FF;
1014 val |= ((_s32_to_s5(tx_cal[0]) << 27)| 1015 val |= ((_s32_to_s5(tx_cal[0]) << 27)|
1015 (_s32_to_s6(tx_cal[1]) << 21)| 1016 (_s32_to_s6(tx_cal[1]) << 21)|
1016 (_s32_to_s6(tx_cal[2]) << 15)| 1017 (_s32_to_s6(tx_cal[2]) << 15)|
1017 (_s32_to_s5(tx_cal[3]) << 10)); 1018 (_s32_to_s5(tx_cal[3]) << 10));
1018 hw_set_dxx_reg(phw_data, 0x3C, val); 1019 hw_set_dxx_reg(phw_data, 0x3C, val);
1019 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION = 0x%08X\n", val)); 1020 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION = 0x%08X\n", val));
1020 return 0; 1021 return 0;
1021 } 1022 }
1022 1023
1023 // i. Set "calib_start" to 0x0 1024 // i. Set "calib_start" to 0x0
1024 reg_mode_ctrl &= ~MASK_CALIB_START; 1025 reg_mode_ctrl &= ~MASK_CALIB_START;
1025 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 1026 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
1026 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 1027 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
1027 1028
1028 loop--; 1029 loop--;
1029 } 1030 }
1030 1031
1031 return 1; 1032 return 1;
1032 } 1033 }
1033 1034
1034 void _tx_iq_calibration_winbond(hw_data_t *phw_data) 1035 void _tx_iq_calibration_winbond(hw_data_t *phw_data)
1035 { 1036 {
1036 u32 reg_agc_ctrl3; 1037 u32 reg_agc_ctrl3;
1037 #ifdef _DEBUG 1038 #ifdef _DEBUG
1038 s32 tx_cal_reg[4]; 1039 s32 tx_cal_reg[4];
1039 1040
1040 #endif 1041 #endif
1041 u32 reg_mode_ctrl; 1042 u32 reg_mode_ctrl;
1042 u32 val; 1043 u32 val;
1043 u8 result; 1044 u8 result;
1044 1045
1045 PHY_DEBUG(("[CAL] -> [4]_tx_iq_calibration()\n")); 1046 PHY_DEBUG(("[CAL] -> [4]_tx_iq_calibration()\n"));
1046 1047
1047 //0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits 1048 //0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits
1048 phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2); 1049 phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2);
1049 //0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit 1050 //0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit
1050 phy_set_rf_data(phw_data, 11, (11<<24)|0x19BDD6); // 20060612.1.a 0x1905D6); 1051 phy_set_rf_data(phw_data, 11, (11<<24)|0x19BDD6); // 20060612.1.a 0x1905D6);
1051 //0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized 1052 //0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized
1052 phy_set_rf_data(phw_data, 5, (5<<24)|0x24C60A); //0x24C60A (high temperature) 1053 phy_set_rf_data(phw_data, 5, (5<<24)|0x24C60A); //0x24C60A (high temperature)
1053 //0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized 1054 //0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized
1054 phy_set_rf_data(phw_data, 6, (6<<24)|0x34880C); // 20060612.1.a 0x06890C); 1055 phy_set_rf_data(phw_data, 6, (6<<24)|0x34880C); // 20060612.1.a 0x06890C);
1055 //0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode 1056 //0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode
1056 phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0); 1057 phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0);
1057 //; [BB-chip]: Calibration (6f).Send test pattern 1058 //; [BB-chip]: Calibration (6f).Send test pattern
1058 //; [BB-chip]: Calibration (6g). Search RXGCL optimal value 1059 //; [BB-chip]: Calibration (6g). Search RXGCL optimal value
1059 //; [BB-chip]: Calibration (6h). Caculate TX-path IQ imbalance and setting TX path IQ compensation table 1060 //; [BB-chip]: Calibration (6h). Caculate TX-path IQ imbalance and setting TX path IQ compensation table
1060 //phy_set_rf_data(phw_data, 3, (3<<24)|0x025586); 1061 //phy_set_rf_data(phw_data, 3, (3<<24)|0x025586);
1061 1062
1062 msleep(30); // 20060612.1.a 30ms delay. Add the follow 2 lines 1063 msleep(30); // 20060612.1.a 30ms delay. Add the follow 2 lines
1063 //To adjust TXVGA to fit iq_mag_0 range from 1250 ~ 1750 1064 //To adjust TXVGA to fit iq_mag_0 range from 1250 ~ 1750
1064 adjust_TXVGA_for_iq_mag( phw_data ); 1065 adjust_TXVGA_for_iq_mag( phw_data );
1065 1066
1066 // a. Disable AGC 1067 // a. Disable AGC
1067 hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3); 1068 hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3);
1068 reg_agc_ctrl3 &= ~BIT(2); 1069 reg_agc_ctrl3 &= ~BIT(2);
1069 reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX); 1070 reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
1070 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3); 1071 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
1071 1072
1072 hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val); 1073 hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val);
1073 val |= MASK_AGC_FIX_GAIN; 1074 val |= MASK_AGC_FIX_GAIN;
1074 hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val); 1075 hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val);
1075 1076
1076 result = _tx_iq_calibration_loop_winbond(phw_data, 150, 100); 1077 result = _tx_iq_calibration_loop_winbond(phw_data, 150, 100);
1077 1078
1078 if (result > 0) 1079 if (result > 0)
1079 { 1080 {
1080 if (phw_data->revision == 0x2002) // 1st-cut 1081 if (phw_data->revision == 0x2002) // 1st-cut
1081 { 1082 {
1082 hw_get_dxx_reg(phw_data, 0x54, &val); 1083 hw_get_dxx_reg(phw_data, 0x54, &val);
1083 val &= 0x0000FFFF; 1084 val &= 0x0000FFFF;
1084 hw_set_dxx_reg(phw_data, 0x54, val); 1085 hw_set_dxx_reg(phw_data, 0x54, val);
1085 } 1086 }
1086 else // 2nd-cut 1087 else // 2nd-cut
1087 { 1088 {
1088 hw_get_dxx_reg(phw_data, 0x3C, &val); 1089 hw_get_dxx_reg(phw_data, 0x3C, &val);
1089 val &= 0x000003FF; 1090 val &= 0x000003FF;
1090 hw_set_dxx_reg(phw_data, 0x3C, val); 1091 hw_set_dxx_reg(phw_data, 0x3C, val);
1091 } 1092 }
1092 1093
1093 result = _tx_iq_calibration_loop_winbond(phw_data, 300, 200); 1094 result = _tx_iq_calibration_loop_winbond(phw_data, 300, 200);
1094 1095
1095 if (result > 0) 1096 if (result > 0)
1096 { 1097 {
1097 if (phw_data->revision == 0x2002) // 1st-cut 1098 if (phw_data->revision == 0x2002) // 1st-cut
1098 { 1099 {
1099 hw_get_dxx_reg(phw_data, 0x54, &val); 1100 hw_get_dxx_reg(phw_data, 0x54, &val);
1100 val &= 0x0000FFFF; 1101 val &= 0x0000FFFF;
1101 hw_set_dxx_reg(phw_data, 0x54, val); 1102 hw_set_dxx_reg(phw_data, 0x54, val);
1102 } 1103 }
1103 else // 2nd-cut 1104 else // 2nd-cut
1104 { 1105 {
1105 hw_get_dxx_reg(phw_data, 0x3C, &val); 1106 hw_get_dxx_reg(phw_data, 0x3C, &val);
1106 val &= 0x000003FF; 1107 val &= 0x000003FF;
1107 hw_set_dxx_reg(phw_data, 0x3C, val); 1108 hw_set_dxx_reg(phw_data, 0x3C, val);
1108 } 1109 }
1109 1110
1110 result = _tx_iq_calibration_loop_winbond(phw_data, 500, 400); 1111 result = _tx_iq_calibration_loop_winbond(phw_data, 500, 400);
1111 if (result > 0) 1112 if (result > 0)
1112 { 1113 {
1113 if (phw_data->revision == 0x2002) // 1st-cut 1114 if (phw_data->revision == 0x2002) // 1st-cut
1114 { 1115 {
1115 hw_get_dxx_reg(phw_data, 0x54, &val); 1116 hw_get_dxx_reg(phw_data, 0x54, &val);
1116 val &= 0x0000FFFF; 1117 val &= 0x0000FFFF;
1117 hw_set_dxx_reg(phw_data, 0x54, val); 1118 hw_set_dxx_reg(phw_data, 0x54, val);
1118 } 1119 }
1119 else // 2nd-cut 1120 else // 2nd-cut
1120 { 1121 {
1121 hw_get_dxx_reg(phw_data, 0x3C, &val); 1122 hw_get_dxx_reg(phw_data, 0x3C, &val);
1122 val &= 0x000003FF; 1123 val &= 0x000003FF;
1123 hw_set_dxx_reg(phw_data, 0x3C, val); 1124 hw_set_dxx_reg(phw_data, 0x3C, val);
1124 } 1125 }
1125 1126
1126 1127
1127 result = _tx_iq_calibration_loop_winbond(phw_data, 700, 500); 1128 result = _tx_iq_calibration_loop_winbond(phw_data, 700, 500);
1128 1129
1129 if (result > 0) 1130 if (result > 0)
1130 { 1131 {
1131 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration> **************\n")); 1132 PHY_DEBUG(("[CAL] ** <_tx_iq_calibration> **************\n"));
1132 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION FAILURE !!\n")); 1133 PHY_DEBUG(("[CAL] ** TX_IQ_CALIBRATION FAILURE !!\n"));
1133 PHY_DEBUG(("[CAL] **************************************\n")); 1134 PHY_DEBUG(("[CAL] **************************************\n"));
1134 1135
1135 if (phw_data->revision == 0x2002) // 1st-cut 1136 if (phw_data->revision == 0x2002) // 1st-cut
1136 { 1137 {
1137 hw_get_dxx_reg(phw_data, 0x54, &val); 1138 hw_get_dxx_reg(phw_data, 0x54, &val);
1138 val &= 0x0000FFFF; 1139 val &= 0x0000FFFF;
1139 hw_set_dxx_reg(phw_data, 0x54, val); 1140 hw_set_dxx_reg(phw_data, 0x54, val);
1140 } 1141 }
1141 else // 2nd-cut 1142 else // 2nd-cut
1142 { 1143 {
1143 hw_get_dxx_reg(phw_data, 0x3C, &val); 1144 hw_get_dxx_reg(phw_data, 0x3C, &val);
1144 val &= 0x000003FF; 1145 val &= 0x000003FF;
1145 hw_set_dxx_reg(phw_data, 0x3C, val); 1146 hw_set_dxx_reg(phw_data, 0x3C, val);
1146 } 1147 }
1147 } 1148 }
1148 } 1149 }
1149 } 1150 }
1150 } 1151 }
1151 1152
1152 // i. Set "calib_start" to 0x0 1153 // i. Set "calib_start" to 0x0
1153 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl); 1154 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
1154 reg_mode_ctrl &= ~MASK_CALIB_START; 1155 reg_mode_ctrl &= ~MASK_CALIB_START;
1155 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 1156 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
1156 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 1157 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
1157 1158
1158 // g. Enable AGC 1159 // g. Enable AGC
1159 //hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val); 1160 //hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &val);
1160 reg_agc_ctrl3 |= BIT(2); 1161 reg_agc_ctrl3 |= BIT(2);
1161 reg_agc_ctrl3 &= ~(MASK_LNA_FIX_GAIN|MASK_AGC_FIX); 1162 reg_agc_ctrl3 &= ~(MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
1162 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3); 1163 hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
1163 1164
1164 #ifdef _DEBUG 1165 #ifdef _DEBUG
1165 if (phw_data->revision == 0x2002) // 1st-cut 1166 if (phw_data->revision == 0x2002) // 1st-cut
1166 { 1167 {
1167 hw_get_dxx_reg(phw_data, 0x54, &val); 1168 hw_get_dxx_reg(phw_data, 0x54, &val);
1168 PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val)); 1169 PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val));
1169 tx_cal_reg[0] = _s4_to_s32((val & 0xF0000000) >> 28); 1170 tx_cal_reg[0] = _s4_to_s32((val & 0xF0000000) >> 28);
1170 tx_cal_reg[1] = _s4_to_s32((val & 0x0F000000) >> 24); 1171 tx_cal_reg[1] = _s4_to_s32((val & 0x0F000000) >> 24);
1171 tx_cal_reg[2] = _s4_to_s32((val & 0x00F00000) >> 20); 1172 tx_cal_reg[2] = _s4_to_s32((val & 0x00F00000) >> 20);
1172 tx_cal_reg[3] = _s4_to_s32((val & 0x000F0000) >> 16); 1173 tx_cal_reg[3] = _s4_to_s32((val & 0x000F0000) >> 16);
1173 } 1174 }
1174 else // 2nd-cut 1175 else // 2nd-cut
1175 { 1176 {
1176 hw_get_dxx_reg(phw_data, 0x3C, &val); 1177 hw_get_dxx_reg(phw_data, 0x3C, &val);
1177 PHY_DEBUG(("[CAL] ** 0x3C = 0x%08X\n", val)); 1178 PHY_DEBUG(("[CAL] ** 0x3C = 0x%08X\n", val));
1178 tx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27); 1179 tx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27);
1179 tx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21); 1180 tx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21);
1180 tx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15); 1181 tx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15);
1181 tx_cal_reg[3] = _s5_to_s32((val & 0x00007C00) >> 10); 1182 tx_cal_reg[3] = _s5_to_s32((val & 0x00007C00) >> 10);
1182 1183
1183 } 1184 }
1184 1185
1185 PHY_DEBUG(("[CAL] ** tx_cal_reg[0] = %d\n", tx_cal_reg[0])); 1186 PHY_DEBUG(("[CAL] ** tx_cal_reg[0] = %d\n", tx_cal_reg[0]));
1186 PHY_DEBUG(("[CAL] tx_cal_reg[1] = %d\n", tx_cal_reg[1])); 1187 PHY_DEBUG(("[CAL] tx_cal_reg[1] = %d\n", tx_cal_reg[1]));
1187 PHY_DEBUG(("[CAL] tx_cal_reg[2] = %d\n", tx_cal_reg[2])); 1188 PHY_DEBUG(("[CAL] tx_cal_reg[2] = %d\n", tx_cal_reg[2]));
1188 PHY_DEBUG(("[CAL] tx_cal_reg[3] = %d\n", tx_cal_reg[3])); 1189 PHY_DEBUG(("[CAL] tx_cal_reg[3] = %d\n", tx_cal_reg[3]));
1189 #endif 1190 #endif
1190 1191
1191 1192
1192 // for test - BEN 1193 // for test - BEN
1193 // RF Control Override 1194 // RF Control Override
1194 } 1195 }
1195 1196
1196 ///////////////////////////////////////////////////////////////////////////////////////// 1197 /////////////////////////////////////////////////////////////////////////////////////////
1197 u8 _rx_iq_calibration_loop_winbond(hw_data_t *phw_data, u16 factor, u32 frequency) 1198 u8 _rx_iq_calibration_loop_winbond(hw_data_t *phw_data, u16 factor, u32 frequency)
1198 { 1199 {
1199 u32 reg_mode_ctrl; 1200 u32 reg_mode_ctrl;
1200 s32 iqcal_tone_i; 1201 s32 iqcal_tone_i;
1201 s32 iqcal_tone_q; 1202 s32 iqcal_tone_q;
1202 s32 iqcal_image_i; 1203 s32 iqcal_image_i;
1203 s32 iqcal_image_q; 1204 s32 iqcal_image_q;
1204 s32 rot_tone_i_b; 1205 s32 rot_tone_i_b;
1205 s32 rot_tone_q_b; 1206 s32 rot_tone_q_b;
1206 s32 rot_image_i_b; 1207 s32 rot_image_i_b;
1207 s32 rot_image_q_b; 1208 s32 rot_image_q_b;
1208 s32 rx_cal_flt_b[4]; 1209 s32 rx_cal_flt_b[4];
1209 s32 rx_cal[4]; 1210 s32 rx_cal[4];
1210 s32 rx_cal_reg[4]; 1211 s32 rx_cal_reg[4];
1211 s32 a_2, b_2; 1212 s32 a_2, b_2;
1212 s32 sin_b, sin_2b; 1213 s32 sin_b, sin_2b;
1213 s32 cos_b, cos_2b; 1214 s32 cos_b, cos_2b;
1214 s32 temp1, temp2; 1215 s32 temp1, temp2;
1215 u32 val; 1216 u32 val;
1216 u16 loop; 1217 u16 loop;
1217 1218
1218 u32 pwr_tone; 1219 u32 pwr_tone;
1219 u32 pwr_image; 1220 u32 pwr_image;
1220 u8 verify_count; 1221 u8 verify_count;
1221 1222
1222 s32 iqcal_tone_i_avg,iqcal_tone_q_avg; 1223 s32 iqcal_tone_i_avg,iqcal_tone_q_avg;
1223 s32 iqcal_image_i_avg,iqcal_image_q_avg; 1224 s32 iqcal_image_i_avg,iqcal_image_q_avg;
1224 u16 capture_time; 1225 u16 capture_time;
1225 1226
1226 PHY_DEBUG(("[CAL] -> [5]_rx_iq_calibration_loop()\n")); 1227 PHY_DEBUG(("[CAL] -> [5]_rx_iq_calibration_loop()\n"));
1227 PHY_DEBUG(("[CAL] ** factor = %d\n", factor)); 1228 PHY_DEBUG(("[CAL] ** factor = %d\n", factor));
1228 1229
1229 1230
1230 // RF Control Override 1231 // RF Control Override
1231 hw_get_cxx_reg(phw_data, 0x80, &val); 1232 hw_get_cxx_reg(phw_data, 0x80, &val);
1232 val |= BIT(19); 1233 val |= BIT(19);
1233 hw_set_cxx_reg(phw_data, 0x80, val); 1234 hw_set_cxx_reg(phw_data, 0x80, val);
1234 1235
1235 // RF_Ctrl 1236 // RF_Ctrl
1236 hw_get_cxx_reg(phw_data, 0xE4, &val); 1237 hw_get_cxx_reg(phw_data, 0xE4, &val);
1237 val |= BIT(0); 1238 val |= BIT(0);
1238 hw_set_cxx_reg(phw_data, 0xE4, val); 1239 hw_set_cxx_reg(phw_data, 0xE4, val);
1239 PHY_DEBUG(("[CAL] ** RF_CTRL(0xE4) = 0x%08X", val)); 1240 PHY_DEBUG(("[CAL] ** RF_CTRL(0xE4) = 0x%08X", val));
1240 1241
1241 hw_set_dxx_reg(phw_data, 0x58, 0x44444444); // IQ_Alpha 1242 hw_set_dxx_reg(phw_data, 0x58, 0x44444444); // IQ_Alpha
1242 1243
1243 // b. 1244 // b.
1244 1245
1245 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl); 1246 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
1246 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl)); 1247 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
1247 1248
1248 verify_count = 0; 1249 verify_count = 0;
1249 1250
1250 //for (loop = 0; loop < 1; loop++) 1251 //for (loop = 0; loop < 1; loop++)
1251 //for (loop = 0; loop < LOOP_TIMES; loop++) 1252 //for (loop = 0; loop < LOOP_TIMES; loop++)
1252 loop = LOOP_TIMES; 1253 loop = LOOP_TIMES;
1253 while (loop > 0) 1254 while (loop > 0)
1254 { 1255 {
1255 PHY_DEBUG(("[CAL] [%d.] <_rx_iq_calibration_loop>\n", (LOOP_TIMES-loop+1))); 1256 PHY_DEBUG(("[CAL] [%d.] <_rx_iq_calibration_loop>\n", (LOOP_TIMES-loop+1)));
1256 iqcal_tone_i_avg=0; 1257 iqcal_tone_i_avg=0;
1257 iqcal_tone_q_avg=0; 1258 iqcal_tone_q_avg=0;
1258 iqcal_image_i_avg=0; 1259 iqcal_image_i_avg=0;
1259 iqcal_image_q_avg=0; 1260 iqcal_image_q_avg=0;
1260 capture_time=0; 1261 capture_time=0;
1261 1262
1262 for(capture_time=0; capture_time<10; capture_time++) 1263 for(capture_time=0; capture_time<10; capture_time++)
1263 { 1264 {
1264 // i. Set "calib_start" to 0x0 1265 // i. Set "calib_start" to 0x0
1265 reg_mode_ctrl &= ~MASK_CALIB_START; 1266 reg_mode_ctrl &= ~MASK_CALIB_START;
1266 if( !hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl) )//20060718.1 modify 1267 if( !hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl) )//20060718.1 modify
1267 return 0; 1268 return 0;
1268 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 1269 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
1269 1270
1270 reg_mode_ctrl &= ~MASK_IQCAL_MODE; 1271 reg_mode_ctrl &= ~MASK_IQCAL_MODE;
1271 reg_mode_ctrl |= (MASK_CALIB_START|0x1); 1272 reg_mode_ctrl |= (MASK_CALIB_START|0x1);
1272 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 1273 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
1273 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 1274 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
1274 1275
1275 // c. 1276 // c.
1276 hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val); 1277 hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);
1277 PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val)); 1278 PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val));
1278 1279
1279 iqcal_tone_i = _s13_to_s32(val & 0x00001FFF); 1280 iqcal_tone_i = _s13_to_s32(val & 0x00001FFF);
1280 iqcal_tone_q = _s13_to_s32((val & 0x03FFE000) >> 13); 1281 iqcal_tone_q = _s13_to_s32((val & 0x03FFE000) >> 13);
1281 PHY_DEBUG(("[CAL] ** iqcal_tone_i = %d, iqcal_tone_q = %d\n", 1282 PHY_DEBUG(("[CAL] ** iqcal_tone_i = %d, iqcal_tone_q = %d\n",
1282 iqcal_tone_i, iqcal_tone_q)); 1283 iqcal_tone_i, iqcal_tone_q));
1283 1284
1284 hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val); 1285 hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
1285 PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val)); 1286 PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val));
1286 1287
1287 iqcal_image_i = _s13_to_s32(val & 0x00001FFF); 1288 iqcal_image_i = _s13_to_s32(val & 0x00001FFF);
1288 iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13); 1289 iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
1289 PHY_DEBUG(("[CAL] ** iqcal_image_i = %d, iqcal_image_q = %d\n", 1290 PHY_DEBUG(("[CAL] ** iqcal_image_i = %d, iqcal_image_q = %d\n",
1290 iqcal_image_i, iqcal_image_q)); 1291 iqcal_image_i, iqcal_image_q));
1291 if( capture_time == 0) 1292 if( capture_time == 0)
1292 { 1293 {
1293 continue; 1294 continue;
1294 } 1295 }
1295 else 1296 else
1296 { 1297 {
1297 iqcal_image_i_avg=( iqcal_image_i_avg*(capture_time-1) +iqcal_image_i)/capture_time; 1298 iqcal_image_i_avg=( iqcal_image_i_avg*(capture_time-1) +iqcal_image_i)/capture_time;
1298 iqcal_image_q_avg=( iqcal_image_q_avg*(capture_time-1) +iqcal_image_q)/capture_time; 1299 iqcal_image_q_avg=( iqcal_image_q_avg*(capture_time-1) +iqcal_image_q)/capture_time;
1299 iqcal_tone_i_avg=( iqcal_tone_i_avg*(capture_time-1) +iqcal_tone_i)/capture_time; 1300 iqcal_tone_i_avg=( iqcal_tone_i_avg*(capture_time-1) +iqcal_tone_i)/capture_time;
1300 iqcal_tone_q_avg=( iqcal_tone_q_avg*(capture_time-1) +iqcal_tone_q)/capture_time; 1301 iqcal_tone_q_avg=( iqcal_tone_q_avg*(capture_time-1) +iqcal_tone_q)/capture_time;
1301 } 1302 }
1302 } 1303 }
1303 1304
1304 1305
1305 iqcal_image_i = iqcal_image_i_avg; 1306 iqcal_image_i = iqcal_image_i_avg;
1306 iqcal_image_q = iqcal_image_q_avg; 1307 iqcal_image_q = iqcal_image_q_avg;
1307 iqcal_tone_i = iqcal_tone_i_avg; 1308 iqcal_tone_i = iqcal_tone_i_avg;
1308 iqcal_tone_q = iqcal_tone_q_avg; 1309 iqcal_tone_q = iqcal_tone_q_avg;
1309 1310
1310 // d. 1311 // d.
1311 rot_tone_i_b = (iqcal_tone_i * iqcal_tone_i + 1312 rot_tone_i_b = (iqcal_tone_i * iqcal_tone_i +
1312 iqcal_tone_q * iqcal_tone_q) / 1024; 1313 iqcal_tone_q * iqcal_tone_q) / 1024;
1313 rot_tone_q_b = (iqcal_tone_i * iqcal_tone_q * (-1) + 1314 rot_tone_q_b = (iqcal_tone_i * iqcal_tone_q * (-1) +
1314 iqcal_tone_q * iqcal_tone_i) / 1024; 1315 iqcal_tone_q * iqcal_tone_i) / 1024;
1315 rot_image_i_b = (iqcal_image_i * iqcal_tone_i - 1316 rot_image_i_b = (iqcal_image_i * iqcal_tone_i -
1316 iqcal_image_q * iqcal_tone_q) / 1024; 1317 iqcal_image_q * iqcal_tone_q) / 1024;
1317 rot_image_q_b = (iqcal_image_i * iqcal_tone_q + 1318 rot_image_q_b = (iqcal_image_i * iqcal_tone_q +
1318 iqcal_image_q * iqcal_tone_i) / 1024; 1319 iqcal_image_q * iqcal_tone_i) / 1024;
1319 1320
1320 PHY_DEBUG(("[CAL] ** rot_tone_i_b = %d\n", rot_tone_i_b)); 1321 PHY_DEBUG(("[CAL] ** rot_tone_i_b = %d\n", rot_tone_i_b));
1321 PHY_DEBUG(("[CAL] ** rot_tone_q_b = %d\n", rot_tone_q_b)); 1322 PHY_DEBUG(("[CAL] ** rot_tone_q_b = %d\n", rot_tone_q_b));
1322 PHY_DEBUG(("[CAL] ** rot_image_i_b = %d\n", rot_image_i_b)); 1323 PHY_DEBUG(("[CAL] ** rot_image_i_b = %d\n", rot_image_i_b));
1323 PHY_DEBUG(("[CAL] ** rot_image_q_b = %d\n", rot_image_q_b)); 1324 PHY_DEBUG(("[CAL] ** rot_image_q_b = %d\n", rot_image_q_b));
1324 1325
1325 // f. 1326 // f.
1326 if (rot_tone_i_b == 0) 1327 if (rot_tone_i_b == 0)
1327 { 1328 {
1328 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> ERROR *******\n")); 1329 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> ERROR *******\n"));
1329 PHY_DEBUG(("[CAL] ** rot_tone_i_b=0 to calculate EPS and THETA !!\n")); 1330 PHY_DEBUG(("[CAL] ** rot_tone_i_b=0 to calculate EPS and THETA !!\n"));
1330 PHY_DEBUG(("[CAL] ******************************************\n")); 1331 PHY_DEBUG(("[CAL] ******************************************\n"));
1331 break; 1332 break;
1332 } 1333 }
1333 1334
1334 a_2 = (rot_image_i_b * 32768) / rot_tone_i_b - 1335 a_2 = (rot_image_i_b * 32768) / rot_tone_i_b -
1335 phw_data->iq_rsdl_gain_tx_d2; 1336 phw_data->iq_rsdl_gain_tx_d2;
1336 b_2 = (rot_image_q_b * 32768) / rot_tone_i_b - 1337 b_2 = (rot_image_q_b * 32768) / rot_tone_i_b -
1337 phw_data->iq_rsdl_phase_tx_d2; 1338 phw_data->iq_rsdl_phase_tx_d2;
1338 1339
1339 PHY_DEBUG(("[CAL] ** iq_rsdl_gain_tx_d2 = %d\n", phw_data->iq_rsdl_gain_tx_d2)); 1340 PHY_DEBUG(("[CAL] ** iq_rsdl_gain_tx_d2 = %d\n", phw_data->iq_rsdl_gain_tx_d2));
1340 PHY_DEBUG(("[CAL] ** iq_rsdl_phase_tx_d2= %d\n", phw_data->iq_rsdl_phase_tx_d2)); 1341 PHY_DEBUG(("[CAL] ** iq_rsdl_phase_tx_d2= %d\n", phw_data->iq_rsdl_phase_tx_d2));
1341 PHY_DEBUG(("[CAL] ***** EPSILON/2 = %d\n", a_2)); 1342 PHY_DEBUG(("[CAL] ***** EPSILON/2 = %d\n", a_2));
1342 PHY_DEBUG(("[CAL] ***** THETA/2 = %d\n", b_2)); 1343 PHY_DEBUG(("[CAL] ***** THETA/2 = %d\n", b_2));
1343 1344
1344 _sin_cos(b_2, &sin_b, &cos_b); 1345 _sin_cos(b_2, &sin_b, &cos_b);
1345 _sin_cos(b_2*2, &sin_2b, &cos_2b); 1346 _sin_cos(b_2*2, &sin_2b, &cos_2b);
1346 PHY_DEBUG(("[CAL] ** sin(b/2)=%d, cos(b/2)=%d\n", sin_b, cos_b)); 1347 PHY_DEBUG(("[CAL] ** sin(b/2)=%d, cos(b/2)=%d\n", sin_b, cos_b));
1347 PHY_DEBUG(("[CAL] ** sin(b)=%d, cos(b)=%d\n", sin_2b, cos_2b)); 1348 PHY_DEBUG(("[CAL] ** sin(b)=%d, cos(b)=%d\n", sin_2b, cos_2b));
1348 1349
1349 if (cos_2b == 0) 1350 if (cos_2b == 0)
1350 { 1351 {
1351 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> ERROR *******\n")); 1352 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> ERROR *******\n"));
1352 PHY_DEBUG(("[CAL] ** cos(b)=0 !!\n")); 1353 PHY_DEBUG(("[CAL] ** cos(b)=0 !!\n"));
1353 PHY_DEBUG(("[CAL] ******************************************\n")); 1354 PHY_DEBUG(("[CAL] ******************************************\n"));
1354 break; 1355 break;
1355 } 1356 }
1356 1357
1357 // 1280 * 32768 = 41943040 1358 // 1280 * 32768 = 41943040
1358 temp1 = (41943040/cos_2b)*cos_b; 1359 temp1 = (41943040/cos_2b)*cos_b;
1359 1360
1360 //temp2 = (41943040/cos_2b)*sin_b*(-1); 1361 //temp2 = (41943040/cos_2b)*sin_b*(-1);
1361 if (phw_data->revision == 0x2002) // 1st-cut 1362 if (phw_data->revision == 0x2002) // 1st-cut
1362 { 1363 {
1363 temp2 = (41943040/cos_2b)*sin_b*(-1); 1364 temp2 = (41943040/cos_2b)*sin_b*(-1);
1364 } 1365 }
1365 else // 2nd-cut 1366 else // 2nd-cut
1366 { 1367 {
1367 temp2 = (41943040*4/cos_2b)*sin_b*(-1); 1368 temp2 = (41943040*4/cos_2b)*sin_b*(-1);
1368 } 1369 }
1369 1370
1370 rx_cal_flt_b[0] = _floor(temp1/(32768+a_2)); 1371 rx_cal_flt_b[0] = _floor(temp1/(32768+a_2));
1371 rx_cal_flt_b[1] = _floor(temp2/(32768-a_2)); 1372 rx_cal_flt_b[1] = _floor(temp2/(32768-a_2));
1372 rx_cal_flt_b[2] = _floor(temp2/(32768+a_2)); 1373 rx_cal_flt_b[2] = _floor(temp2/(32768+a_2));
1373 rx_cal_flt_b[3] = _floor(temp1/(32768-a_2)); 1374 rx_cal_flt_b[3] = _floor(temp1/(32768-a_2));
1374 1375
1375 PHY_DEBUG(("[CAL] ** rx_cal_flt_b[0] = %d\n", rx_cal_flt_b[0])); 1376 PHY_DEBUG(("[CAL] ** rx_cal_flt_b[0] = %d\n", rx_cal_flt_b[0]));
1376 PHY_DEBUG(("[CAL] rx_cal_flt_b[1] = %d\n", rx_cal_flt_b[1])); 1377 PHY_DEBUG(("[CAL] rx_cal_flt_b[1] = %d\n", rx_cal_flt_b[1]));
1377 PHY_DEBUG(("[CAL] rx_cal_flt_b[2] = %d\n", rx_cal_flt_b[2])); 1378 PHY_DEBUG(("[CAL] rx_cal_flt_b[2] = %d\n", rx_cal_flt_b[2]));
1378 PHY_DEBUG(("[CAL] rx_cal_flt_b[3] = %d\n", rx_cal_flt_b[3])); 1379 PHY_DEBUG(("[CAL] rx_cal_flt_b[3] = %d\n", rx_cal_flt_b[3]));
1379 1380
1380 rx_cal[0] = rx_cal_flt_b[0] - 128; 1381 rx_cal[0] = rx_cal_flt_b[0] - 128;
1381 rx_cal[1] = rx_cal_flt_b[1]; 1382 rx_cal[1] = rx_cal_flt_b[1];
1382 rx_cal[2] = rx_cal_flt_b[2]; 1383 rx_cal[2] = rx_cal_flt_b[2];
1383 rx_cal[3] = rx_cal_flt_b[3] - 128; 1384 rx_cal[3] = rx_cal_flt_b[3] - 128;
1384 PHY_DEBUG(("[CAL] ** rx_cal[0] = %d\n", rx_cal[0])); 1385 PHY_DEBUG(("[CAL] ** rx_cal[0] = %d\n", rx_cal[0]));
1385 PHY_DEBUG(("[CAL] rx_cal[1] = %d\n", rx_cal[1])); 1386 PHY_DEBUG(("[CAL] rx_cal[1] = %d\n", rx_cal[1]));
1386 PHY_DEBUG(("[CAL] rx_cal[2] = %d\n", rx_cal[2])); 1387 PHY_DEBUG(("[CAL] rx_cal[2] = %d\n", rx_cal[2]));
1387 PHY_DEBUG(("[CAL] rx_cal[3] = %d\n", rx_cal[3])); 1388 PHY_DEBUG(("[CAL] rx_cal[3] = %d\n", rx_cal[3]));
1388 1389
1389 // e. 1390 // e.
1390 pwr_tone = (iqcal_tone_i*iqcal_tone_i + iqcal_tone_q*iqcal_tone_q); 1391 pwr_tone = (iqcal_tone_i*iqcal_tone_i + iqcal_tone_q*iqcal_tone_q);
1391 pwr_image = (iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q)*factor; 1392 pwr_image = (iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q)*factor;
1392 1393
1393 PHY_DEBUG(("[CAL] ** pwr_tone = %d\n", pwr_tone)); 1394 PHY_DEBUG(("[CAL] ** pwr_tone = %d\n", pwr_tone));
1394 PHY_DEBUG(("[CAL] ** pwr_image = %d\n", pwr_image)); 1395 PHY_DEBUG(("[CAL] ** pwr_image = %d\n", pwr_image));
1395 1396
1396 if (pwr_tone > pwr_image) 1397 if (pwr_tone > pwr_image)
1397 { 1398 {
1398 verify_count++; 1399 verify_count++;
1399 1400
1400 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *************\n")); 1401 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *************\n"));
1401 PHY_DEBUG(("[CAL] ** VERIFY OK # %d !!\n", verify_count)); 1402 PHY_DEBUG(("[CAL] ** VERIFY OK # %d !!\n", verify_count));
1402 PHY_DEBUG(("[CAL] ******************************************\n")); 1403 PHY_DEBUG(("[CAL] ******************************************\n"));
1403 1404
1404 if (verify_count > 2) 1405 if (verify_count > 2)
1405 { 1406 {
1406 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n")); 1407 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n"));
1407 PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION OK !!\n")); 1408 PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION OK !!\n"));
1408 PHY_DEBUG(("[CAL] **************************************\n")); 1409 PHY_DEBUG(("[CAL] **************************************\n"));
1409 return 0; 1410 return 0;
1410 } 1411 }
1411 1412
1412 continue; 1413 continue;
1413 } 1414 }
1414 // g. 1415 // g.
1415 hw_get_dxx_reg(phw_data, 0x54, &val); 1416 hw_get_dxx_reg(phw_data, 0x54, &val);
1416 PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val)); 1417 PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val));
1417 1418
1418 if (phw_data->revision == 0x2002) // 1st-cut 1419 if (phw_data->revision == 0x2002) // 1st-cut
1419 { 1420 {
1420 rx_cal_reg[0] = _s4_to_s32((val & 0x0000F000) >> 12); 1421 rx_cal_reg[0] = _s4_to_s32((val & 0x0000F000) >> 12);
1421 rx_cal_reg[1] = _s4_to_s32((val & 0x00000F00) >> 8); 1422 rx_cal_reg[1] = _s4_to_s32((val & 0x00000F00) >> 8);
1422 rx_cal_reg[2] = _s4_to_s32((val & 0x000000F0) >> 4); 1423 rx_cal_reg[2] = _s4_to_s32((val & 0x000000F0) >> 4);
1423 rx_cal_reg[3] = _s4_to_s32((val & 0x0000000F)); 1424 rx_cal_reg[3] = _s4_to_s32((val & 0x0000000F));
1424 } 1425 }
1425 else // 2nd-cut 1426 else // 2nd-cut
1426 { 1427 {
1427 rx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27); 1428 rx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27);
1428 rx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21); 1429 rx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21);
1429 rx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15); 1430 rx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15);
1430 rx_cal_reg[3] = _s5_to_s32((val & 0x00007C00) >> 10); 1431 rx_cal_reg[3] = _s5_to_s32((val & 0x00007C00) >> 10);
1431 } 1432 }
1432 1433
1433 PHY_DEBUG(("[CAL] ** rx_cal_reg[0] = %d\n", rx_cal_reg[0])); 1434 PHY_DEBUG(("[CAL] ** rx_cal_reg[0] = %d\n", rx_cal_reg[0]));
1434 PHY_DEBUG(("[CAL] rx_cal_reg[1] = %d\n", rx_cal_reg[1])); 1435 PHY_DEBUG(("[CAL] rx_cal_reg[1] = %d\n", rx_cal_reg[1]));
1435 PHY_DEBUG(("[CAL] rx_cal_reg[2] = %d\n", rx_cal_reg[2])); 1436 PHY_DEBUG(("[CAL] rx_cal_reg[2] = %d\n", rx_cal_reg[2]));
1436 PHY_DEBUG(("[CAL] rx_cal_reg[3] = %d\n", rx_cal_reg[3])); 1437 PHY_DEBUG(("[CAL] rx_cal_reg[3] = %d\n", rx_cal_reg[3]));
1437 1438
1438 if (phw_data->revision == 0x2002) // 1st-cut 1439 if (phw_data->revision == 0x2002) // 1st-cut
1439 { 1440 {
1440 if (((rx_cal_reg[0]==7) || (rx_cal_reg[0]==(-8))) && 1441 if (((rx_cal_reg[0]==7) || (rx_cal_reg[0]==(-8))) &&
1441 ((rx_cal_reg[3]==7) || (rx_cal_reg[3]==(-8)))) 1442 ((rx_cal_reg[3]==7) || (rx_cal_reg[3]==(-8))))
1442 { 1443 {
1443 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n")); 1444 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n"));
1444 PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION SATUATION !!\n")); 1445 PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION SATUATION !!\n"));
1445 PHY_DEBUG(("[CAL] **************************************\n")); 1446 PHY_DEBUG(("[CAL] **************************************\n"));
1446 break; 1447 break;
1447 } 1448 }
1448 } 1449 }
1449 else // 2nd-cut 1450 else // 2nd-cut
1450 { 1451 {
1451 if (((rx_cal_reg[0]==31) || (rx_cal_reg[0]==(-32))) && 1452 if (((rx_cal_reg[0]==31) || (rx_cal_reg[0]==(-32))) &&
1452 ((rx_cal_reg[3]==31) || (rx_cal_reg[3]==(-32)))) 1453 ((rx_cal_reg[3]==31) || (rx_cal_reg[3]==(-32))))
1453 { 1454 {
1454 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n")); 1455 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration_loop> *********\n"));
1455 PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION SATUATION !!\n")); 1456 PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION SATUATION !!\n"));
1456 PHY_DEBUG(("[CAL] **************************************\n")); 1457 PHY_DEBUG(("[CAL] **************************************\n"));
1457 break; 1458 break;
1458 } 1459 }
1459 } 1460 }
1460 1461
1461 rx_cal[0] = rx_cal[0] + rx_cal_reg[0]; 1462 rx_cal[0] = rx_cal[0] + rx_cal_reg[0];
1462 rx_cal[1] = rx_cal[1] + rx_cal_reg[1]; 1463 rx_cal[1] = rx_cal[1] + rx_cal_reg[1];
1463 rx_cal[2] = rx_cal[2] + rx_cal_reg[2]; 1464 rx_cal[2] = rx_cal[2] + rx_cal_reg[2];
1464 rx_cal[3] = rx_cal[3] + rx_cal_reg[3]; 1465 rx_cal[3] = rx_cal[3] + rx_cal_reg[3];
1465 PHY_DEBUG(("[CAL] ** apply rx_cal[0] = %d\n", rx_cal[0])); 1466 PHY_DEBUG(("[CAL] ** apply rx_cal[0] = %d\n", rx_cal[0]));
1466 PHY_DEBUG(("[CAL] apply rx_cal[1] = %d\n", rx_cal[1])); 1467 PHY_DEBUG(("[CAL] apply rx_cal[1] = %d\n", rx_cal[1]));
1467 PHY_DEBUG(("[CAL] apply rx_cal[2] = %d\n", rx_cal[2])); 1468 PHY_DEBUG(("[CAL] apply rx_cal[2] = %d\n", rx_cal[2]));
1468 PHY_DEBUG(("[CAL] apply rx_cal[3] = %d\n", rx_cal[3])); 1469 PHY_DEBUG(("[CAL] apply rx_cal[3] = %d\n", rx_cal[3]));
1469 1470
1470 hw_get_dxx_reg(phw_data, 0x54, &val); 1471 hw_get_dxx_reg(phw_data, 0x54, &val);
1471 if (phw_data->revision == 0x2002) // 1st-cut 1472 if (phw_data->revision == 0x2002) // 1st-cut
1472 { 1473 {
1473 val &= 0x0000FFFF; 1474 val &= 0x0000FFFF;
1474 val |= ((_s32_to_s4(rx_cal[0]) << 12)| 1475 val |= ((_s32_to_s4(rx_cal[0]) << 12)|
1475 (_s32_to_s4(rx_cal[1]) << 8)| 1476 (_s32_to_s4(rx_cal[1]) << 8)|
1476 (_s32_to_s4(rx_cal[2]) << 4)| 1477 (_s32_to_s4(rx_cal[2]) << 4)|
1477 (_s32_to_s4(rx_cal[3]))); 1478 (_s32_to_s4(rx_cal[3])));
1478 hw_set_dxx_reg(phw_data, 0x54, val); 1479 hw_set_dxx_reg(phw_data, 0x54, val);
1479 } 1480 }
1480 else // 2nd-cut 1481 else // 2nd-cut
1481 { 1482 {
1482 val &= 0x000003FF; 1483 val &= 0x000003FF;
1483 val |= ((_s32_to_s5(rx_cal[0]) << 27)| 1484 val |= ((_s32_to_s5(rx_cal[0]) << 27)|
1484 (_s32_to_s6(rx_cal[1]) << 21)| 1485 (_s32_to_s6(rx_cal[1]) << 21)|
1485 (_s32_to_s6(rx_cal[2]) << 15)| 1486 (_s32_to_s6(rx_cal[2]) << 15)|
1486 (_s32_to_s5(rx_cal[3]) << 10)); 1487 (_s32_to_s5(rx_cal[3]) << 10));
1487 hw_set_dxx_reg(phw_data, 0x54, val); 1488 hw_set_dxx_reg(phw_data, 0x54, val);
1488 1489
1489 if( loop == 3 ) 1490 if( loop == 3 )
1490 return 0; 1491 return 0;
1491 } 1492 }
1492 PHY_DEBUG(("[CAL] ** CALIB_DATA = 0x%08X\n", val)); 1493 PHY_DEBUG(("[CAL] ** CALIB_DATA = 0x%08X\n", val));
1493 1494
1494 loop--; 1495 loop--;
1495 } 1496 }
1496 1497
1497 return 1; 1498 return 1;
1498 } 1499 }
1499 1500
1500 ////////////////////////////////////////////////////////// 1501 //////////////////////////////////////////////////////////
1501 1502
1502 ////////////////////////////////////////////////////////////////////////// 1503 //////////////////////////////////////////////////////////////////////////
1503 void _rx_iq_calibration_winbond(hw_data_t *phw_data, u32 frequency) 1504 void _rx_iq_calibration_winbond(hw_data_t *phw_data, u32 frequency)
1504 { 1505 {
1505 // figo 20050523 marked thsi flag for can't compile for relesase 1506 // figo 20050523 marked thsi flag for can't compile for relesase
1506 #ifdef _DEBUG 1507 #ifdef _DEBUG
1507 s32 rx_cal_reg[4]; 1508 s32 rx_cal_reg[4];
1508 u32 val; 1509 u32 val;
1509 #endif 1510 #endif
1510 1511
1511 u8 result; 1512 u8 result;
1512 1513
1513 PHY_DEBUG(("[CAL] -> [5]_rx_iq_calibration()\n")); 1514 PHY_DEBUG(("[CAL] -> [5]_rx_iq_calibration()\n"));
1514 // a. Set RFIC to "RX calibration mode" 1515 // a. Set RFIC to "RX calibration mode"
1515 //; ----- Calibration (7). RX path IQ imbalance calibration loop 1516 //; ----- Calibration (7). RX path IQ imbalance calibration loop
1516 // 0x01 0xFFBFC2 ; 3FEFF ; Calibration (7a). enable RX IQ calibration loop circuits 1517 // 0x01 0xFFBFC2 ; 3FEFF ; Calibration (7a). enable RX IQ calibration loop circuits
1517 phy_set_rf_data(phw_data, 1, (1<<24)|0xEFBFC2); 1518 phy_set_rf_data(phw_data, 1, (1<<24)|0xEFBFC2);
1518 // 0x0B 0x1A01D6 ; 06817 ; Calibration (7b). enable RX I/Q cal loop SW1 circuit 1519 // 0x0B 0x1A01D6 ; 06817 ; Calibration (7b). enable RX I/Q cal loop SW1 circuit
1519 phy_set_rf_data(phw_data, 11, (11<<24)|0x1A05D6); 1520 phy_set_rf_data(phw_data, 11, (11<<24)|0x1A05D6);
1520 //0x05 0x24848A ; 09212 ; Calibration (7c). setting TX-VGA gain (TXGCH) to 2 --> to be optimized 1521 //0x05 0x24848A ; 09212 ; Calibration (7c). setting TX-VGA gain (TXGCH) to 2 --> to be optimized
1521 phy_set_rf_data(phw_data, 5, (5<<24)| phw_data->txvga_setting_for_cal); 1522 phy_set_rf_data(phw_data, 5, (5<<24)| phw_data->txvga_setting_for_cal);
1522 //0x06 0x06840C ; 01A10 ; Calibration (7d). RXGCH=00; RXGCL=010 000 (RXVGA) --> to be optimized 1523 //0x06 0x06840C ; 01A10 ; Calibration (7d). RXGCH=00; RXGCL=010 000 (RXVGA) --> to be optimized
1523 phy_set_rf_data(phw_data, 6, (6<<24)|0x06834C); 1524 phy_set_rf_data(phw_data, 6, (6<<24)|0x06834C);
1524 //0x00 0xFFF1C0 ; 3F7C7 ; Calibration (7e). turn on IQ imbalance/Test mode 1525 //0x00 0xFFF1C0 ; 3F7C7 ; Calibration (7e). turn on IQ imbalance/Test mode
1525 phy_set_rf_data(phw_data, 0, (0<<24)|0xFFF1C0); 1526 phy_set_rf_data(phw_data, 0, (0<<24)|0xFFF1C0);
1526 1527
1527 // ; [BB-chip]: Calibration (7f). Send test pattern 1528 // ; [BB-chip]: Calibration (7f). Send test pattern
1528 // ; [BB-chip]: Calibration (7g). Search RXGCL optimal value 1529 // ; [BB-chip]: Calibration (7g). Search RXGCL optimal value
1529 // ; [BB-chip]: Calibration (7h). Caculate RX-path IQ imbalance and setting RX path IQ compensation table 1530 // ; [BB-chip]: Calibration (7h). Caculate RX-path IQ imbalance and setting RX path IQ compensation table
1530 1531
1531 result = _rx_iq_calibration_loop_winbond(phw_data, 12589, frequency); 1532 result = _rx_iq_calibration_loop_winbond(phw_data, 12589, frequency);
1532 1533
1533 if (result > 0) 1534 if (result > 0)
1534 { 1535 {
1535 _reset_rx_cal(phw_data); 1536 _reset_rx_cal(phw_data);
1536 result = _rx_iq_calibration_loop_winbond(phw_data, 7943, frequency); 1537 result = _rx_iq_calibration_loop_winbond(phw_data, 7943, frequency);
1537 1538
1538 if (result > 0) 1539 if (result > 0)
1539 { 1540 {
1540 _reset_rx_cal(phw_data); 1541 _reset_rx_cal(phw_data);
1541 result = _rx_iq_calibration_loop_winbond(phw_data, 5011, frequency); 1542 result = _rx_iq_calibration_loop_winbond(phw_data, 5011, frequency);
1542 1543
1543 if (result > 0) 1544 if (result > 0)
1544 { 1545 {
1545 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration> **************\n")); 1546 PHY_DEBUG(("[CAL] ** <_rx_iq_calibration> **************\n"));
1546 PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION FAILURE !!\n")); 1547 PHY_DEBUG(("[CAL] ** RX_IQ_CALIBRATION FAILURE !!\n"));
1547 PHY_DEBUG(("[CAL] **************************************\n")); 1548 PHY_DEBUG(("[CAL] **************************************\n"));
1548 _reset_rx_cal(phw_data); 1549 _reset_rx_cal(phw_data);
1549 } 1550 }
1550 } 1551 }
1551 } 1552 }
1552 1553
1553 #ifdef _DEBUG 1554 #ifdef _DEBUG
1554 hw_get_dxx_reg(phw_data, 0x54, &val); 1555 hw_get_dxx_reg(phw_data, 0x54, &val);
1555 PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val)); 1556 PHY_DEBUG(("[CAL] ** 0x54 = 0x%08X\n", val));
1556 1557
1557 if (phw_data->revision == 0x2002) // 1st-cut 1558 if (phw_data->revision == 0x2002) // 1st-cut
1558 { 1559 {
1559 rx_cal_reg[0] = _s4_to_s32((val & 0x0000F000) >> 12); 1560 rx_cal_reg[0] = _s4_to_s32((val & 0x0000F000) >> 12);
1560 rx_cal_reg[1] = _s4_to_s32((val & 0x00000F00) >> 8); 1561 rx_cal_reg[1] = _s4_to_s32((val & 0x00000F00) >> 8);
1561 rx_cal_reg[2] = _s4_to_s32((val & 0x000000F0) >> 4); 1562 rx_cal_reg[2] = _s4_to_s32((val & 0x000000F0) >> 4);
1562 rx_cal_reg[3] = _s4_to_s32((val & 0x0000000F)); 1563 rx_cal_reg[3] = _s4_to_s32((val & 0x0000000F));
1563 } 1564 }
1564 else // 2nd-cut 1565 else // 2nd-cut
1565 { 1566 {
1566 rx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27); 1567 rx_cal_reg[0] = _s5_to_s32((val & 0xF8000000) >> 27);
1567 rx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21); 1568 rx_cal_reg[1] = _s6_to_s32((val & 0x07E00000) >> 21);
1568 rx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15); 1569 rx_cal_reg[2] = _s6_to_s32((val & 0x001F8000) >> 15);
1569 rx_cal_reg[3] = _s5_to_s32((val & 0x00007C00) >> 10); 1570 rx_cal_reg[3] = _s5_to_s32((val & 0x00007C00) >> 10);
1570 } 1571 }
1571 1572
1572 PHY_DEBUG(("[CAL] ** rx_cal_reg[0] = %d\n", rx_cal_reg[0])); 1573 PHY_DEBUG(("[CAL] ** rx_cal_reg[0] = %d\n", rx_cal_reg[0]));
1573 PHY_DEBUG(("[CAL] rx_cal_reg[1] = %d\n", rx_cal_reg[1])); 1574 PHY_DEBUG(("[CAL] rx_cal_reg[1] = %d\n", rx_cal_reg[1]));
1574 PHY_DEBUG(("[CAL] rx_cal_reg[2] = %d\n", rx_cal_reg[2])); 1575 PHY_DEBUG(("[CAL] rx_cal_reg[2] = %d\n", rx_cal_reg[2]));
1575 PHY_DEBUG(("[CAL] rx_cal_reg[3] = %d\n", rx_cal_reg[3])); 1576 PHY_DEBUG(("[CAL] rx_cal_reg[3] = %d\n", rx_cal_reg[3]));
1576 #endif 1577 #endif
1577 1578
1578 } 1579 }
1579 1580
1580 //////////////////////////////////////////////////////////////////////// 1581 ////////////////////////////////////////////////////////////////////////
1581 void phy_calibration_winbond(hw_data_t *phw_data, u32 frequency) 1582 void phy_calibration_winbond(hw_data_t *phw_data, u32 frequency)
1582 { 1583 {
1583 u32 reg_mode_ctrl; 1584 u32 reg_mode_ctrl;
1584 u32 iq_alpha; 1585 u32 iq_alpha;
1585 1586
1586 PHY_DEBUG(("[CAL] -> phy_calibration_winbond()\n")); 1587 PHY_DEBUG(("[CAL] -> phy_calibration_winbond()\n"));
1587 1588
1588 // 20040701 1.1.25.1000 kevin 1589 // 20040701 1.1.25.1000 kevin
1589 hw_get_cxx_reg(phw_data, 0x80, &mac_ctrl); 1590 hw_get_cxx_reg(phw_data, 0x80, &mac_ctrl);
1590 hw_get_cxx_reg(phw_data, 0xE4, &rf_ctrl); 1591 hw_get_cxx_reg(phw_data, 0xE4, &rf_ctrl);
1591 hw_get_dxx_reg(phw_data, 0x58, &iq_alpha); 1592 hw_get_dxx_reg(phw_data, 0x58, &iq_alpha);
1592 1593
1593 1594
1594 1595
1595 _rxadc_dc_offset_cancellation_winbond(phw_data, frequency); 1596 _rxadc_dc_offset_cancellation_winbond(phw_data, frequency);
1596 //_txidac_dc_offset_cancellation_winbond(phw_data); 1597 //_txidac_dc_offset_cancellation_winbond(phw_data);
1597 //_txqdac_dc_offset_cacellation_winbond(phw_data); 1598 //_txqdac_dc_offset_cacellation_winbond(phw_data);
1598 1599
1599 _tx_iq_calibration_winbond(phw_data); 1600 _tx_iq_calibration_winbond(phw_data);
1600 _rx_iq_calibration_winbond(phw_data, frequency); 1601 _rx_iq_calibration_winbond(phw_data, frequency);
1601 1602
1602 //------------------------------------------------------------------------ 1603 //------------------------------------------------------------------------
1603 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl); 1604 hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
1604 reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE|MASK_CALIB_START); // set when finish 1605 reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE|MASK_CALIB_START); // set when finish
1605 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 1606 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
1606 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 1607 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
1607 1608
1608 // i. Set RFIC to "Normal mode" 1609 // i. Set RFIC to "Normal mode"
1609 hw_set_cxx_reg(phw_data, 0x80, mac_ctrl); 1610 hw_set_cxx_reg(phw_data, 0x80, mac_ctrl);
1610 hw_set_cxx_reg(phw_data, 0xE4, rf_ctrl); 1611 hw_set_cxx_reg(phw_data, 0xE4, rf_ctrl);
1611 hw_set_dxx_reg(phw_data, 0x58, iq_alpha); 1612 hw_set_dxx_reg(phw_data, 0x58, iq_alpha);
1612 1613
1613 1614
1614 //------------------------------------------------------------------------ 1615 //------------------------------------------------------------------------
1615 phy_init_rf(phw_data); 1616 phy_init_rf(phw_data);
1616 1617
1617 } 1618 }
1618 1619
1619 //=========================== 1620 //===========================
1620 void phy_set_rf_data( phw_data_t pHwData, u32 index, u32 value ) 1621 void phy_set_rf_data( phw_data_t pHwData, u32 index, u32 value )
1621 { 1622 {
1622 u32 ltmp=0; 1623 u32 ltmp=0;
1623 1624
1624 switch( pHwData->phy_type ) 1625 switch( pHwData->phy_type )
1625 { 1626 {
1626 case RF_MAXIM_2825: 1627 case RF_MAXIM_2825:
1627 case RF_MAXIM_V1: // 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331) 1628 case RF_MAXIM_V1: // 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331)
1628 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 ); 1629 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 );
1629 break; 1630 break;
1630 1631
1631 case RF_MAXIM_2827: 1632 case RF_MAXIM_2827:
1632 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 ); 1633 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 );
1633 break; 1634 break;
1634 1635
1635 case RF_MAXIM_2828: 1636 case RF_MAXIM_2828:
1636 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 ); 1637 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 );
1637 break; 1638 break;
1638 1639
1639 case RF_MAXIM_2829: 1640 case RF_MAXIM_2829:
1640 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 ); 1641 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( value, 18 );
1641 break; 1642 break;
1642 1643
1643 case RF_AIROHA_2230: 1644 case RF_AIROHA_2230:
1644 case RF_AIROHA_2230S: // 20060420 Add this 1645 case RF_AIROHA_2230S: // 20060420 Add this
1645 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( value, 20 ); 1646 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( value, 20 );
1646 break; 1647 break;
1647 1648
1648 case RF_AIROHA_7230: 1649 case RF_AIROHA_7230:
1649 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | (value&0xffffff); 1650 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | (value&0xffffff);
1650 break; 1651 break;
1651 1652
1652 case RF_WB_242: 1653 case RF_WB_242:
1653 case RF_WB_242_1: // 20060619.5 Add 1654 case RF_WB_242_1: // 20060619.5 Add
1654 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( value, 24 ); 1655 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( value, 24 );
1655 break; 1656 break;
1656 } 1657 }
1657 1658
1658 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1659 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1659 } 1660 }
1660 1661
1661 // 20060717 modify as Bruce's mail 1662 // 20060717 modify as Bruce's mail
1662 unsigned char adjust_TXVGA_for_iq_mag(hw_data_t *phw_data) 1663 unsigned char adjust_TXVGA_for_iq_mag(hw_data_t *phw_data)
1663 { 1664 {
1664 int init_txvga = 0; 1665 int init_txvga = 0;
1665 u32 reg_mode_ctrl; 1666 u32 reg_mode_ctrl;
1666 u32 val; 1667 u32 val;
1667 s32 iqcal_tone_i0; 1668 s32 iqcal_tone_i0;
1668 s32 iqcal_tone_q0; 1669 s32 iqcal_tone_q0;
1669 u32 sqsum; 1670 u32 sqsum;
1670 s32 iq_mag_0_tx; 1671 s32 iq_mag_0_tx;
1671 u8 reg_state; 1672 u8 reg_state;
1672 int current_txvga; 1673 int current_txvga;
1673 1674
1674 1675
1675 reg_state = 0; 1676 reg_state = 0;
1676 for( init_txvga=0; init_txvga<10; init_txvga++) 1677 for( init_txvga=0; init_txvga<10; init_txvga++)
1677 { 1678 {
1678 current_txvga = ( 0x24C40A|(init_txvga<<6) ); 1679 current_txvga = ( 0x24C40A|(init_txvga<<6) );
1679 phy_set_rf_data(phw_data, 5, ((5<<24)|current_txvga) ); 1680 phy_set_rf_data(phw_data, 5, ((5<<24)|current_txvga) );
1680 phw_data->txvga_setting_for_cal = current_txvga; 1681 phw_data->txvga_setting_for_cal = current_txvga;
1681 1682
1682 msleep(30); // 20060612.1.a 1683 msleep(30); // 20060612.1.a
1683 1684
1684 if( !hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl) ) // 20060718.1 modify 1685 if( !hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl) ) // 20060718.1 modify
1685 return false; 1686 return false;
1686 1687
1687 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl)); 1688 PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
1688 1689
1689 // a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" to 0x1 to 1690 // a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" to 0x1 to
1690 // enable "IQ alibration Mode II" 1691 // enable "IQ alibration Mode II"
1691 reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE); 1692 reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE);
1692 reg_mode_ctrl &= ~MASK_IQCAL_MODE; 1693 reg_mode_ctrl &= ~MASK_IQCAL_MODE;
1693 reg_mode_ctrl |= (MASK_CALIB_START|0x02); 1694 reg_mode_ctrl |= (MASK_CALIB_START|0x02);
1694 reg_mode_ctrl |= (MASK_CALIB_START|0x02|2<<2); 1695 reg_mode_ctrl |= (MASK_CALIB_START|0x02|2<<2);
1695 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl); 1696 hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
1696 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl)); 1697 PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
1697 1698
1698 udelay(1); // 20060612.1.a 1699 udelay(1); // 20060612.1.a
1699 1700
1700 udelay(300); // 20060612.1.a 1701 udelay(300); // 20060612.1.a
1701 1702
1702 // b. 1703 // b.
1703 hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val); 1704 hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);
1704 1705
1705 PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val)); 1706 PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val));
1706 udelay(300); // 20060612.1.a 1707 udelay(300); // 20060612.1.a
1707 1708
1708 iqcal_tone_i0 = _s13_to_s32(val & 0x00001FFF); 1709 iqcal_tone_i0 = _s13_to_s32(val & 0x00001FFF);
1709 iqcal_tone_q0 = _s13_to_s32((val & 0x03FFE000) >> 13); 1710 iqcal_tone_q0 = _s13_to_s32((val & 0x03FFE000) >> 13);
1710 PHY_DEBUG(("[CAL] ** iqcal_tone_i0=%d, iqcal_tone_q0=%d\n", 1711 PHY_DEBUG(("[CAL] ** iqcal_tone_i0=%d, iqcal_tone_q0=%d\n",
1711 iqcal_tone_i0, iqcal_tone_q0)); 1712 iqcal_tone_i0, iqcal_tone_q0));
1712 1713
1713 sqsum = iqcal_tone_i0*iqcal_tone_i0 + iqcal_tone_q0*iqcal_tone_q0; 1714 sqsum = iqcal_tone_i0*iqcal_tone_i0 + iqcal_tone_q0*iqcal_tone_q0;
1714 iq_mag_0_tx = (s32) _sqrt(sqsum); 1715 iq_mag_0_tx = (s32) _sqrt(sqsum);
1715 PHY_DEBUG(("[CAL] ** auto_adjust_txvga_for_iq_mag_0_tx=%d\n", iq_mag_0_tx)); 1716 PHY_DEBUG(("[CAL] ** auto_adjust_txvga_for_iq_mag_0_tx=%d\n", iq_mag_0_tx));
1716 1717
1717 if( iq_mag_0_tx>=700 && iq_mag_0_tx<=1750 ) 1718 if( iq_mag_0_tx>=700 && iq_mag_0_tx<=1750 )
1718 break; 1719 break;
1719 else if(iq_mag_0_tx > 1750) 1720 else if(iq_mag_0_tx > 1750)
1720 { 1721 {
1721 init_txvga=-2; 1722 init_txvga=-2;
1722 continue; 1723 continue;
1723 } 1724 }
1724 else 1725 else
1725 continue; 1726 continue;
1726 1727
1727 } 1728 }
1728 1729
1729 if( iq_mag_0_tx>=700 && iq_mag_0_tx<=1750 ) 1730 if( iq_mag_0_tx>=700 && iq_mag_0_tx<=1750 )
1730 return true; 1731 return true;
1731 else 1732 else
1732 return false; 1733 return false;
1733 } 1734 }
1734 1735
1735 1736
1736 1737
1737 1738
drivers/staging/winbond/phy_calibration.h
Diff comments   View file @ 80aba53
1 #ifndef __WINBOND_PHY_CALIBRATION_H
2 #define __WINBOND_PHY_CALIBRATION_H
3
4 #include "wbhal_f.h"
5
1 // 20031229 Turbo add 6 // 20031229 Turbo add
2 #define REG_AGC_CTRL1 0x1000 7 #define REG_AGC_CTRL1 0x1000
3 #define REG_AGC_CTRL2 0x1004 8 #define REG_AGC_CTRL2 0x1004
4 #define REG_AGC_CTRL3 0x1008 9 #define REG_AGC_CTRL3 0x1008
5 #define REG_AGC_CTRL4 0x100C 10 #define REG_AGC_CTRL4 0x100C
6 #define REG_AGC_CTRL5 0x1010 11 #define REG_AGC_CTRL5 0x1010
7 #define REG_AGC_CTRL6 0x1014 12 #define REG_AGC_CTRL6 0x1014
8 #define REG_AGC_CTRL7 0x1018 13 #define REG_AGC_CTRL7 0x1018
9 #define REG_AGC_CTRL8 0x101C 14 #define REG_AGC_CTRL8 0x101C
10 #define REG_AGC_CTRL9 0x1020 15 #define REG_AGC_CTRL9 0x1020
11 #define REG_AGC_CTRL10 0x1024 16 #define REG_AGC_CTRL10 0x1024
12 #define REG_CCA_CTRL 0x1028 17 #define REG_CCA_CTRL 0x1028
13 #define REG_A_ACQ_CTRL 0x102C 18 #define REG_A_ACQ_CTRL 0x102C
14 #define REG_B_ACQ_CTRL 0x1030 19 #define REG_B_ACQ_CTRL 0x1030
15 #define REG_A_TXRX_CTRL 0x1034 20 #define REG_A_TXRX_CTRL 0x1034
16 #define REG_B_TXRX_CTRL 0x1038 21 #define REG_B_TXRX_CTRL 0x1038
17 #define REG_A_TX_COEF3 0x103C 22 #define REG_A_TX_COEF3 0x103C
18 #define REG_A_TX_COEF2 0x1040 23 #define REG_A_TX_COEF2 0x1040
19 #define REG_A_TX_COEF1 0x1044 24 #define REG_A_TX_COEF1 0x1044
20 #define REG_B_TX_COEF2 0x1048 25 #define REG_B_TX_COEF2 0x1048
21 #define REG_B_TX_COEF1 0x104C 26 #define REG_B_TX_COEF1 0x104C
22 #define REG_MODE_CTRL 0x1050 27 #define REG_MODE_CTRL 0x1050
23 #define REG_CALIB_DATA 0x1054 28 #define REG_CALIB_DATA 0x1054
24 #define REG_IQ_ALPHA 0x1058 29 #define REG_IQ_ALPHA 0x1058
25 #define REG_DC_CANCEL 0x105C 30 #define REG_DC_CANCEL 0x105C
26 #define REG_WTO_READ 0x1060 31 #define REG_WTO_READ 0x1060
27 #define REG_OFFSET_READ 0x1064 32 #define REG_OFFSET_READ 0x1064
28 #define REG_CALIB_READ1 0x1068 33 #define REG_CALIB_READ1 0x1068
29 #define REG_CALIB_READ2 0x106C 34 #define REG_CALIB_READ2 0x106C
30 #define REG_A_FREQ_EST 0x1070 35 #define REG_A_FREQ_EST 0x1070
31 36
32 37
33 38
34 39
35 // 20031101 Turbo add 40 // 20031101 Turbo add
36 #define MASK_AMER_OFF_REG BIT(31) 41 #define MASK_AMER_OFF_REG BIT(31)
37 42
38 #define MASK_BMER_OFF_REG BIT(31) 43 #define MASK_BMER_OFF_REG BIT(31)
39 44
40 #define MASK_LNA_FIX_GAIN (BIT(3)|BIT(4)) 45 #define MASK_LNA_FIX_GAIN (BIT(3)|BIT(4))
41 #define MASK_AGC_FIX BIT(1) 46 #define MASK_AGC_FIX BIT(1)
42 47
43 #define MASK_AGC_FIX_GAIN 0xFF00 48 #define MASK_AGC_FIX_GAIN 0xFF00
44 49
45 #define MASK_ADC_DC_CAL_STR BIT(10) 50 #define MASK_ADC_DC_CAL_STR BIT(10)
46 #define MASK_CALIB_START BIT(4) 51 #define MASK_CALIB_START BIT(4)
47 #define MASK_IQCAL_TONE_SEL (BIT(3)|BIT(2)) 52 #define MASK_IQCAL_TONE_SEL (BIT(3)|BIT(2))
48 #define MASK_IQCAL_MODE (BIT(1)|BIT(0)) 53 #define MASK_IQCAL_MODE (BIT(1)|BIT(0))
49 54
50 #define MASK_TX_CAL_0 0xF0000000 55 #define MASK_TX_CAL_0 0xF0000000
51 #define TX_CAL_0_SHIFT 28 56 #define TX_CAL_0_SHIFT 28
52 #define MASK_TX_CAL_1 0x0F000000 57 #define MASK_TX_CAL_1 0x0F000000
53 #define TX_CAL_1_SHIFT 24 58 #define TX_CAL_1_SHIFT 24
54 #define MASK_TX_CAL_2 0x00F00000 59 #define MASK_TX_CAL_2 0x00F00000
55 #define TX_CAL_2_SHIFT 20 60 #define TX_CAL_2_SHIFT 20
56 #define MASK_TX_CAL_3 0x000F0000 61 #define MASK_TX_CAL_3 0x000F0000
57 #define TX_CAL_3_SHIFT 16 62 #define TX_CAL_3_SHIFT 16
58 #define MASK_RX_CAL_0 0x0000F000 63 #define MASK_RX_CAL_0 0x0000F000
59 #define RX_CAL_0_SHIFT 12 64 #define RX_CAL_0_SHIFT 12
60 #define MASK_RX_CAL_1 0x00000F00 65 #define MASK_RX_CAL_1 0x00000F00
61 #define RX_CAL_1_SHIFT 8 66 #define RX_CAL_1_SHIFT 8
62 #define MASK_RX_CAL_2 0x000000F0 67 #define MASK_RX_CAL_2 0x000000F0
63 #define RX_CAL_2_SHIFT 4 68 #define RX_CAL_2_SHIFT 4
64 #define MASK_RX_CAL_3 0x0000000F 69 #define MASK_RX_CAL_3 0x0000000F
65 #define RX_CAL_3_SHIFT 0 70 #define RX_CAL_3_SHIFT 0
66 71
67 #define MASK_CANCEL_DC_I 0x3E0 72 #define MASK_CANCEL_DC_I 0x3E0
68 #define CANCEL_DC_I_SHIFT 5 73 #define CANCEL_DC_I_SHIFT 5
69 #define MASK_CANCEL_DC_Q 0x01F 74 #define MASK_CANCEL_DC_Q 0x01F
70 #define CANCEL_DC_Q_SHIFT 0 75 #define CANCEL_DC_Q_SHIFT 0
71 76
72 // LA20040210 kevin 77 // LA20040210 kevin
73 //#define MASK_ADC_DC_CAL_I(x) (((x)&0x1FE00)>>9) 78 //#define MASK_ADC_DC_CAL_I(x) (((x)&0x1FE00)>>9)
74 //#define MASK_ADC_DC_CAL_Q(x) ((x)&0x1FF) 79 //#define MASK_ADC_DC_CAL_Q(x) ((x)&0x1FF)
75 #define MASK_ADC_DC_CAL_I(x) (((x)&0x0003FE00)>>9) 80 #define MASK_ADC_DC_CAL_I(x) (((x)&0x0003FE00)>>9)
76 #define MASK_ADC_DC_CAL_Q(x) ((x)&0x000001FF) 81 #define MASK_ADC_DC_CAL_Q(x) ((x)&0x000001FF)
77 82
78 // LA20040210 kevin (Turbo has wrong definition) 83 // LA20040210 kevin (Turbo has wrong definition)
79 //#define MASK_IQCAL_TONE_I 0x7FFC000 84 //#define MASK_IQCAL_TONE_I 0x7FFC000
80 //#define SHIFT_IQCAL_TONE_I(x) ((x)>>13) 85 //#define SHIFT_IQCAL_TONE_I(x) ((x)>>13)
81 //#define MASK_IQCAL_TONE_Q 0x1FFF 86 //#define MASK_IQCAL_TONE_Q 0x1FFF
82 //#define SHIFT_IQCAL_TONE_Q(x) ((x)>>0) 87 //#define SHIFT_IQCAL_TONE_Q(x) ((x)>>0)
83 #define MASK_IQCAL_TONE_I 0x00001FFF 88 #define MASK_IQCAL_TONE_I 0x00001FFF
84 #define SHIFT_IQCAL_TONE_I(x) ((x)>>0) 89 #define SHIFT_IQCAL_TONE_I(x) ((x)>>0)
85 #define MASK_IQCAL_TONE_Q 0x03FFE000 90 #define MASK_IQCAL_TONE_Q 0x03FFE000
86 #define SHIFT_IQCAL_TONE_Q(x) ((x)>>13) 91 #define SHIFT_IQCAL_TONE_Q(x) ((x)>>13)
87 92
88 // LA20040210 kevin (Turbo has wrong definition) 93 // LA20040210 kevin (Turbo has wrong definition)
89 //#define MASK_IQCAL_IMAGE_I 0x7FFC000 94 //#define MASK_IQCAL_IMAGE_I 0x7FFC000
90 //#define SHIFT_IQCAL_IMAGE_I(x) ((x)>>13) 95 //#define SHIFT_IQCAL_IMAGE_I(x) ((x)>>13)
91 //#define MASK_IQCAL_IMAGE_Q 0x1FFF 96 //#define MASK_IQCAL_IMAGE_Q 0x1FFF
92 //#define SHIFT_IQCAL_IMAGE_Q(x) ((x)>>0) 97 //#define SHIFT_IQCAL_IMAGE_Q(x) ((x)>>0)
93 98
94 //#define MASK_IQCAL_IMAGE_I 0x00001FFF 99 //#define MASK_IQCAL_IMAGE_I 0x00001FFF
95 //#define SHIFT_IQCAL_IMAGE_I(x) ((x)>>0) 100 //#define SHIFT_IQCAL_IMAGE_I(x) ((x)>>0)
96 //#define MASK_IQCAL_IMAGE_Q 0x03FFE000 101 //#define MASK_IQCAL_IMAGE_Q 0x03FFE000
97 //#define SHIFT_IQCAL_IMAGE_Q(x) ((x)>>13) 102 //#define SHIFT_IQCAL_IMAGE_Q(x) ((x)>>13)
98 103
99 void phy_set_rf_data( phw_data_t pHwData, u32 index, u32 value ); 104 void phy_set_rf_data( phw_data_t pHwData, u32 index, u32 value );
100 #define phy_init_rf( _A ) //RFSynthesizer_initial( _A ) 105 #define phy_init_rf( _A ) //RFSynthesizer_initial( _A )
106
107 #endif
101 108
drivers/staging/winbond/reg.c
Diff comments   View file @ 80aba53
1 #include "os_common.h" 1 #include "os_common.h"
2 #include "wbhal_f.h"
2 3
3 /////////////////////////////////////////////////////////////////////////////////////////////////// 4 ///////////////////////////////////////////////////////////////////////////////////////////////////
4 // Original Phy.h 5 // Original Phy.h
5 //***************************************************************************** 6 //*****************************************************************************
6 7
7 /***************************************************************************** 8 /*****************************************************************************
8 ; For MAXIM2825/6/7 Ver. 331 or more 9 ; For MAXIM2825/6/7 Ver. 331 or more
9 ; Edited by Tiger, Sep-17-2003 10 ; Edited by Tiger, Sep-17-2003
10 ; revised by Ben, Sep-18-2003 11 ; revised by Ben, Sep-18-2003
11 12
12 0x00 0x000a2 13 0x00 0x000a2
13 0x01 0x21cc0 14 0x01 0x21cc0
14 ;0x02 0x13802 15 ;0x02 0x13802
15 0x02 0x1383a 16 0x02 0x1383a
16 17
17 ;channe1 01 ; 0x03 0x30142 ; 0x04 0x0b333; 18 ;channe1 01 ; 0x03 0x30142 ; 0x04 0x0b333;
18 ;channe1 02 ;0x03 0x32141 ;0x04 0x08444; 19 ;channe1 02 ;0x03 0x32141 ;0x04 0x08444;
19 ;channe1 03 ;0x03 0x32143 ;0x04 0x0aeee; 20 ;channe1 03 ;0x03 0x32143 ;0x04 0x0aeee;
20 ;channe1 04 ;0x03 0x32142 ;0x04 0x0b333; 21 ;channe1 04 ;0x03 0x32142 ;0x04 0x0b333;
21 ;channe1 05 ;0x03 0x31141 ;0x04 0x08444; 22 ;channe1 05 ;0x03 0x31141 ;0x04 0x08444;
22 ;channe1 06 ; 23 ;channe1 06 ;
23 0x03 0x31143; 24 0x03 0x31143;
24 0x04 0x0aeee; 25 0x04 0x0aeee;
25 ;channe1 07 ;0x03 0x31142 ;0x04 0x0b333; 26 ;channe1 07 ;0x03 0x31142 ;0x04 0x0b333;
26 ;channe1 08 ;0x03 0x33141 ;0x04 0x08444; 27 ;channe1 08 ;0x03 0x33141 ;0x04 0x08444;
27 ;channe1 09 ;0x03 0x33143 ;0x04 0x0aeee; 28 ;channe1 09 ;0x03 0x33143 ;0x04 0x0aeee;
28 ;channe1 10 ;0x03 0x33142 ;0x04 0x0b333; 29 ;channe1 10 ;0x03 0x33142 ;0x04 0x0b333;
29 ;channe1 11 ;0x03 0x30941 ;0x04 0x08444; 30 ;channe1 11 ;0x03 0x30941 ;0x04 0x08444;
30 ;channe1 12 ;0x03 0x30943 ;0x04 0x0aeee; 31 ;channe1 12 ;0x03 0x30943 ;0x04 0x0aeee;
31 ;channe1 13 ;0x03 0x30942 ;0x04 0x0b333; 32 ;channe1 13 ;0x03 0x30942 ;0x04 0x0b333;
32 33
33 0x05 0x28986 34 0x05 0x28986
34 0x06 0x18008 35 0x06 0x18008
35 0x07 0x38400 36 0x07 0x38400
36 0x08 0x05100; 100 Hz DC 37 0x08 0x05100; 100 Hz DC
37 ;0x08 0x05900; 30 KHz DC 38 ;0x08 0x05900; 30 KHz DC
38 0x09 0x24f08 39 0x09 0x24f08
39 0x0a 0x17e00, 0x17ea0 40 0x0a 0x17e00, 0x17ea0
40 0x0b 0x37d80 41 0x0b 0x37d80
41 0x0c 0x0c900 // 0x0ca00 (lager power 9db than 0x0c000), 0x0c000 42 0x0c 0x0c900 // 0x0ca00 (lager power 9db than 0x0c000), 0x0c000
42 *****************************************************************************/ 43 *****************************************************************************/
43 // MAX2825 (pure b/g) 44 // MAX2825 (pure b/g)
44 u32 max2825_rf_data[] = 45 u32 max2825_rf_data[] =
45 { 46 {
46 (0x00<<18)|0x000a2, 47 (0x00<<18)|0x000a2,
47 (0x01<<18)|0x21cc0, 48 (0x01<<18)|0x21cc0,
48 (0x02<<18)|0x13806, 49 (0x02<<18)|0x13806,
49 (0x03<<18)|0x30142, 50 (0x03<<18)|0x30142,
50 (0x04<<18)|0x0b333, 51 (0x04<<18)|0x0b333,
51 (0x05<<18)|0x289A6, 52 (0x05<<18)|0x289A6,
52 (0x06<<18)|0x18008, 53 (0x06<<18)|0x18008,
53 (0x07<<18)|0x38000, 54 (0x07<<18)|0x38000,
54 (0x08<<18)|0x05100, 55 (0x08<<18)|0x05100,
55 (0x09<<18)|0x24f08, 56 (0x09<<18)|0x24f08,
56 (0x0A<<18)|0x14000, 57 (0x0A<<18)|0x14000,
57 (0x0B<<18)|0x37d80, 58 (0x0B<<18)|0x37d80,
58 (0x0C<<18)|0x0c100 // 11a: 0x0c300, 11g: 0x0c100 59 (0x0C<<18)|0x0c100 // 11a: 0x0c300, 11g: 0x0c100
59 }; 60 };
60 61
61 u32 max2825_channel_data_24[][3] = 62 u32 max2825_channel_data_24[][3] =
62 { 63 {
63 {(0x03<<18)|0x30142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 01 64 {(0x03<<18)|0x30142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 01
64 {(0x03<<18)|0x32141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 02 65 {(0x03<<18)|0x32141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 02
65 {(0x03<<18)|0x32143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 03 66 {(0x03<<18)|0x32143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 03
66 {(0x03<<18)|0x32142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 04 67 {(0x03<<18)|0x32142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 04
67 {(0x03<<18)|0x31141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 05 68 {(0x03<<18)|0x31141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 05
68 {(0x03<<18)|0x31143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 06 69 {(0x03<<18)|0x31143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 06
69 {(0x03<<18)|0x31142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 07 70 {(0x03<<18)|0x31142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 07
70 {(0x03<<18)|0x33141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 08 71 {(0x03<<18)|0x33141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 08
71 {(0x03<<18)|0x33143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 09 72 {(0x03<<18)|0x33143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 09
72 {(0x03<<18)|0x33142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 10 73 {(0x03<<18)|0x33142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 10
73 {(0x03<<18)|0x30941, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 11 74 {(0x03<<18)|0x30941, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 11
74 {(0x03<<18)|0x30943, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 12 75 {(0x03<<18)|0x30943, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 12
75 {(0x03<<18)|0x30942, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 13 76 {(0x03<<18)|0x30942, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 13
76 {(0x03<<18)|0x32941, (0x04<<18)|0x09999, (0x05<<18)|0x289A6} // 14 (2484MHz) hhmodify 77 {(0x03<<18)|0x32941, (0x04<<18)|0x09999, (0x05<<18)|0x289A6} // 14 (2484MHz) hhmodify
77 }; 78 };
78 79
79 u32 max2825_power_data_24[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100}; 80 u32 max2825_power_data_24[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100};
80 81
81 /****************************************************************************/ 82 /****************************************************************************/
82 // MAX2827 (a/b/g) 83 // MAX2827 (a/b/g)
83 u32 max2827_rf_data[] = 84 u32 max2827_rf_data[] =
84 { 85 {
85 (0x00<<18)|0x000a2, 86 (0x00<<18)|0x000a2,
86 (0x01<<18)|0x21cc0, 87 (0x01<<18)|0x21cc0,
87 (0x02<<18)|0x13806, 88 (0x02<<18)|0x13806,
88 (0x03<<18)|0x30142, 89 (0x03<<18)|0x30142,
89 (0x04<<18)|0x0b333, 90 (0x04<<18)|0x0b333,
90 (0x05<<18)|0x289A6, 91 (0x05<<18)|0x289A6,
91 (0x06<<18)|0x18008, 92 (0x06<<18)|0x18008,
92 (0x07<<18)|0x38000, 93 (0x07<<18)|0x38000,
93 (0x08<<18)|0x05100, 94 (0x08<<18)|0x05100,
94 (0x09<<18)|0x24f08, 95 (0x09<<18)|0x24f08,
95 (0x0A<<18)|0x14000, 96 (0x0A<<18)|0x14000,
96 (0x0B<<18)|0x37d80, 97 (0x0B<<18)|0x37d80,
97 (0x0C<<18)|0x0c100 // 11a: 0x0c300, 11g: 0x0c100 98 (0x0C<<18)|0x0c100 // 11a: 0x0c300, 11g: 0x0c100
98 }; 99 };
99 100
100 u32 max2827_channel_data_24[][3] = 101 u32 max2827_channel_data_24[][3] =
101 { 102 {
102 {(0x03<<18)|0x30142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 01 103 {(0x03<<18)|0x30142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 01
103 {(0x03<<18)|0x32141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 02 104 {(0x03<<18)|0x32141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 02
104 {(0x03<<18)|0x32143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 03 105 {(0x03<<18)|0x32143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 03
105 {(0x03<<18)|0x32142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 04 106 {(0x03<<18)|0x32142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 04
106 {(0x03<<18)|0x31141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 05 107 {(0x03<<18)|0x31141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 05
107 {(0x03<<18)|0x31143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 06 108 {(0x03<<18)|0x31143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 06
108 {(0x03<<18)|0x31142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 07 109 {(0x03<<18)|0x31142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 07
109 {(0x03<<18)|0x33141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 08 110 {(0x03<<18)|0x33141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 08
110 {(0x03<<18)|0x33143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 09 111 {(0x03<<18)|0x33143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 09
111 {(0x03<<18)|0x33142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 10 112 {(0x03<<18)|0x33142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 10
112 {(0x03<<18)|0x30941, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 11 113 {(0x03<<18)|0x30941, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 11
113 {(0x03<<18)|0x30943, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 12 114 {(0x03<<18)|0x30943, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 12
114 {(0x03<<18)|0x30942, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 13 115 {(0x03<<18)|0x30942, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 13
115 {(0x03<<18)|0x32941, (0x04<<18)|0x09999, (0x05<<18)|0x289A6} // 14 (2484MHz) hhmodify 116 {(0x03<<18)|0x32941, (0x04<<18)|0x09999, (0x05<<18)|0x289A6} // 14 (2484MHz) hhmodify
116 }; 117 };
117 118
118 u32 max2827_channel_data_50[][3] = 119 u32 max2827_channel_data_50[][3] =
119 { 120 {
120 {(0x03<<18)|0x33cc3, (0x04<<18)|0x08ccc, (0x05<<18)|0x2A9A6}, // channel 36 121 {(0x03<<18)|0x33cc3, (0x04<<18)|0x08ccc, (0x05<<18)|0x2A9A6}, // channel 36
121 {(0x03<<18)|0x302c0, (0x04<<18)|0x08000, (0x05<<18)|0x2A9A6}, // channel 40 122 {(0x03<<18)|0x302c0, (0x04<<18)|0x08000, (0x05<<18)|0x2A9A6}, // channel 40
122 {(0x03<<18)|0x302c2, (0x04<<18)|0x0b333, (0x05<<18)|0x2A9A6}, // channel 44 123 {(0x03<<18)|0x302c2, (0x04<<18)|0x0b333, (0x05<<18)|0x2A9A6}, // channel 44
123 {(0x03<<18)|0x322c1, (0x04<<18)|0x09999, (0x05<<18)|0x2A9A6}, // channel 48 124 {(0x03<<18)|0x322c1, (0x04<<18)|0x09999, (0x05<<18)|0x2A9A6}, // channel 48
124 {(0x03<<18)|0x312c1, (0x04<<18)|0x0a666, (0x05<<18)|0x2A9A6}, // channel 52 125 {(0x03<<18)|0x312c1, (0x04<<18)|0x0a666, (0x05<<18)|0x2A9A6}, // channel 52
125 {(0x03<<18)|0x332c3, (0x04<<18)|0x08ccc, (0x05<<18)|0x2A9A6}, // channel 56 126 {(0x03<<18)|0x332c3, (0x04<<18)|0x08ccc, (0x05<<18)|0x2A9A6}, // channel 56
126 {(0x03<<18)|0x30ac0, (0x04<<18)|0x08000, (0x05<<18)|0x2A9A6}, // channel 60 127 {(0x03<<18)|0x30ac0, (0x04<<18)|0x08000, (0x05<<18)|0x2A9A6}, // channel 60
127 {(0x03<<18)|0x30ac2, (0x04<<18)|0x0b333, (0x05<<18)|0x2A9A6} // channel 64 128 {(0x03<<18)|0x30ac2, (0x04<<18)|0x0b333, (0x05<<18)|0x2A9A6} // channel 64
128 }; 129 };
129 130
130 u32 max2827_power_data_24[] = {(0x0C<<18)|0x0C000, (0x0C<<18)|0x0D600, (0x0C<<18)|0x0C100}; 131 u32 max2827_power_data_24[] = {(0x0C<<18)|0x0C000, (0x0C<<18)|0x0D600, (0x0C<<18)|0x0C100};
131 u32 max2827_power_data_50[] = {(0x0C<<18)|0x0C400, (0x0C<<18)|0x0D500, (0x0C<<18)|0x0C300}; 132 u32 max2827_power_data_50[] = {(0x0C<<18)|0x0C400, (0x0C<<18)|0x0D500, (0x0C<<18)|0x0C300};
132 133
133 /****************************************************************************/ 134 /****************************************************************************/
134 // MAX2828 (a/b/g) 135 // MAX2828 (a/b/g)
135 u32 max2828_rf_data[] = 136 u32 max2828_rf_data[] =
136 { 137 {
137 (0x00<<18)|0x000a2, 138 (0x00<<18)|0x000a2,
138 (0x01<<18)|0x21cc0, 139 (0x01<<18)|0x21cc0,
139 (0x02<<18)|0x13806, 140 (0x02<<18)|0x13806,
140 (0x03<<18)|0x30142, 141 (0x03<<18)|0x30142,
141 (0x04<<18)|0x0b333, 142 (0x04<<18)|0x0b333,
142 (0x05<<18)|0x289A6, 143 (0x05<<18)|0x289A6,
143 (0x06<<18)|0x18008, 144 (0x06<<18)|0x18008,
144 (0x07<<18)|0x38000, 145 (0x07<<18)|0x38000,
145 (0x08<<18)|0x05100, 146 (0x08<<18)|0x05100,
146 (0x09<<18)|0x24f08, 147 (0x09<<18)|0x24f08,
147 (0x0A<<18)|0x14000, 148 (0x0A<<18)|0x14000,
148 (0x0B<<18)|0x37d80, 149 (0x0B<<18)|0x37d80,
149 (0x0C<<18)|0x0c100 // 11a: 0x0c300, 11g: 0x0c100 150 (0x0C<<18)|0x0c100 // 11a: 0x0c300, 11g: 0x0c100
150 }; 151 };
151 152
152 u32 max2828_channel_data_24[][3] = 153 u32 max2828_channel_data_24[][3] =
153 { 154 {
154 {(0x03<<18)|0x30142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 01 155 {(0x03<<18)|0x30142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 01
155 {(0x03<<18)|0x32141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 02 156 {(0x03<<18)|0x32141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 02
156 {(0x03<<18)|0x32143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 03 157 {(0x03<<18)|0x32143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 03
157 {(0x03<<18)|0x32142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 04 158 {(0x03<<18)|0x32142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 04
158 {(0x03<<18)|0x31141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 05 159 {(0x03<<18)|0x31141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 05
159 {(0x03<<18)|0x31143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 06 160 {(0x03<<18)|0x31143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 06
160 {(0x03<<18)|0x31142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 07 161 {(0x03<<18)|0x31142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 07
161 {(0x03<<18)|0x33141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 08 162 {(0x03<<18)|0x33141, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 08
162 {(0x03<<18)|0x33143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 09 163 {(0x03<<18)|0x33143, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 09
163 {(0x03<<18)|0x33142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 10 164 {(0x03<<18)|0x33142, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 10
164 {(0x03<<18)|0x30941, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 11 165 {(0x03<<18)|0x30941, (0x04<<18)|0x08444, (0x05<<18)|0x289A6}, // channe1 11
165 {(0x03<<18)|0x30943, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 12 166 {(0x03<<18)|0x30943, (0x04<<18)|0x0aeee, (0x05<<18)|0x289A6}, // channe1 12
166 {(0x03<<18)|0x30942, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 13 167 {(0x03<<18)|0x30942, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channe1 13
167 {(0x03<<18)|0x32941, (0x04<<18)|0x09999, (0x05<<18)|0x289A6} // 14 (2484MHz) hhmodify 168 {(0x03<<18)|0x32941, (0x04<<18)|0x09999, (0x05<<18)|0x289A6} // 14 (2484MHz) hhmodify
168 }; 169 };
169 170
170 u32 max2828_channel_data_50[][3] = 171 u32 max2828_channel_data_50[][3] =
171 { 172 {
172 {(0x03<<18)|0x33cc3, (0x04<<18)|0x08ccc, (0x05<<18)|0x289A6}, // channel 36 173 {(0x03<<18)|0x33cc3, (0x04<<18)|0x08ccc, (0x05<<18)|0x289A6}, // channel 36
173 {(0x03<<18)|0x302c0, (0x04<<18)|0x08000, (0x05<<18)|0x289A6}, // channel 40 174 {(0x03<<18)|0x302c0, (0x04<<18)|0x08000, (0x05<<18)|0x289A6}, // channel 40
174 {(0x03<<18)|0x302c2, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channel 44 175 {(0x03<<18)|0x302c2, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6}, // channel 44
175 {(0x03<<18)|0x322c1, (0x04<<18)|0x09999, (0x05<<18)|0x289A6}, // channel 48 176 {(0x03<<18)|0x322c1, (0x04<<18)|0x09999, (0x05<<18)|0x289A6}, // channel 48
176 {(0x03<<18)|0x312c1, (0x04<<18)|0x0a666, (0x05<<18)|0x289A6}, // channel 52 177 {(0x03<<18)|0x312c1, (0x04<<18)|0x0a666, (0x05<<18)|0x289A6}, // channel 52
177 {(0x03<<18)|0x332c3, (0x04<<18)|0x08ccc, (0x05<<18)|0x289A6}, // channel 56 178 {(0x03<<18)|0x332c3, (0x04<<18)|0x08ccc, (0x05<<18)|0x289A6}, // channel 56
178 {(0x03<<18)|0x30ac0, (0x04<<18)|0x08000, (0x05<<18)|0x289A6}, // channel 60 179 {(0x03<<18)|0x30ac0, (0x04<<18)|0x08000, (0x05<<18)|0x289A6}, // channel 60
179 {(0x03<<18)|0x30ac2, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6} // channel 64 180 {(0x03<<18)|0x30ac2, (0x04<<18)|0x0b333, (0x05<<18)|0x289A6} // channel 64
180 }; 181 };
181 182
182 u32 max2828_power_data_24[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100}; 183 u32 max2828_power_data_24[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100};
183 u32 max2828_power_data_50[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100}; 184 u32 max2828_power_data_50[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100};
184 185
185 /****************************************************************************/ 186 /****************************************************************************/
186 // LA20040728 kevin 187 // LA20040728 kevin
187 // MAX2829 (a/b/g) 188 // MAX2829 (a/b/g)
188 u32 max2829_rf_data[] = 189 u32 max2829_rf_data[] =
189 { 190 {
190 (0x00<<18)|0x000a2, 191 (0x00<<18)|0x000a2,
191 (0x01<<18)|0x23520, 192 (0x01<<18)|0x23520,
192 (0x02<<18)|0x13802, 193 (0x02<<18)|0x13802,
193 (0x03<<18)|0x30142, 194 (0x03<<18)|0x30142,
194 (0x04<<18)|0x0b333, 195 (0x04<<18)|0x0b333,
195 (0x05<<18)|0x28906, 196 (0x05<<18)|0x28906,
196 (0x06<<18)|0x18008, 197 (0x06<<18)|0x18008,
197 (0x07<<18)|0x3B500, 198 (0x07<<18)|0x3B500,
198 (0x08<<18)|0x05100, 199 (0x08<<18)|0x05100,
199 (0x09<<18)|0x24f08, 200 (0x09<<18)|0x24f08,
200 (0x0A<<18)|0x14000, 201 (0x0A<<18)|0x14000,
201 (0x0B<<18)|0x37d80, 202 (0x0B<<18)|0x37d80,
202 (0x0C<<18)|0x0F300 //TXVGA=51, (MAX-6 dB) 203 (0x0C<<18)|0x0F300 //TXVGA=51, (MAX-6 dB)
203 }; 204 };
204 205
205 u32 max2829_channel_data_24[][3] = 206 u32 max2829_channel_data_24[][3] =
206 { 207 {
207 {(3<<18)|0x30142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 01 (2412MHz) 208 {(3<<18)|0x30142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 01 (2412MHz)
208 {(3<<18)|0x32141, (4<<18)|0x08444, (5<<18)|0x289C6}, // 02 (2417MHz) 209 {(3<<18)|0x32141, (4<<18)|0x08444, (5<<18)|0x289C6}, // 02 (2417MHz)
209 {(3<<18)|0x32143, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 03 (2422MHz) 210 {(3<<18)|0x32143, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 03 (2422MHz)
210 {(3<<18)|0x32142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 04 (2427MHz) 211 {(3<<18)|0x32142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 04 (2427MHz)
211 {(3<<18)|0x31141, (4<<18)|0x08444, (5<<18)|0x289C6}, // 05 (2432MHz) 212 {(3<<18)|0x31141, (4<<18)|0x08444, (5<<18)|0x289C6}, // 05 (2432MHz)
212 {(3<<18)|0x31143, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 06 (2437MHz) 213 {(3<<18)|0x31143, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 06 (2437MHz)
213 {(3<<18)|0x31142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 07 (2442MHz) 214 {(3<<18)|0x31142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 07 (2442MHz)
214 {(3<<18)|0x33141, (4<<18)|0x08444, (5<<18)|0x289C6}, // 08 (2447MHz) 215 {(3<<18)|0x33141, (4<<18)|0x08444, (5<<18)|0x289C6}, // 08 (2447MHz)
215 {(3<<18)|0x33143, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 09 (2452MHz) 216 {(3<<18)|0x33143, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 09 (2452MHz)
216 {(3<<18)|0x33142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 10 (2457MHz) 217 {(3<<18)|0x33142, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 10 (2457MHz)
217 {(3<<18)|0x30941, (4<<18)|0x08444, (5<<18)|0x289C6}, // 11 (2462MHz) 218 {(3<<18)|0x30941, (4<<18)|0x08444, (5<<18)|0x289C6}, // 11 (2462MHz)
218 {(3<<18)|0x30943, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 12 (2467MHz) 219 {(3<<18)|0x30943, (4<<18)|0x0aeee, (5<<18)|0x289C6}, // 12 (2467MHz)
219 {(3<<18)|0x30942, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 13 (2472MHz) 220 {(3<<18)|0x30942, (4<<18)|0x0b333, (5<<18)|0x289C6}, // 13 (2472MHz)
220 {(3<<18)|0x32941, (4<<18)|0x09999, (5<<18)|0x289C6}, // 14 (2484MHz) hh-modify 221 {(3<<18)|0x32941, (4<<18)|0x09999, (5<<18)|0x289C6}, // 14 (2484MHz) hh-modify
221 }; 222 };
222 223
223 u32 max2829_channel_data_50[][4] = 224 u32 max2829_channel_data_50[][4] =
224 { 225 {
225 {36, (3<<18)|0x33cc3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 36 (5.180GHz) 226 {36, (3<<18)|0x33cc3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 36 (5.180GHz)
226 {40, (3<<18)|0x302c0, (4<<18)|0x08000, (5<<18)|0x2A946}, // 40 (5.200GHz) 227 {40, (3<<18)|0x302c0, (4<<18)|0x08000, (5<<18)|0x2A946}, // 40 (5.200GHz)
227 {44, (3<<18)|0x302c2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 44 (5.220GHz) 228 {44, (3<<18)|0x302c2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 44 (5.220GHz)
228 {48, (3<<18)|0x322c1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 48 (5.240GHz) 229 {48, (3<<18)|0x322c1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 48 (5.240GHz)
229 {52, (3<<18)|0x312c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 52 (5.260GHz) 230 {52, (3<<18)|0x312c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 52 (5.260GHz)
230 {56, (3<<18)|0x332c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 56 (5.280GHz) 231 {56, (3<<18)|0x332c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 56 (5.280GHz)
231 {60, (3<<18)|0x30ac0, (4<<18)|0x08000, (5<<18)|0x2A946}, // 60 (5.300GHz) 232 {60, (3<<18)|0x30ac0, (4<<18)|0x08000, (5<<18)|0x2A946}, // 60 (5.300GHz)
232 {64, (3<<18)|0x30ac2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 64 (5.320GHz) 233 {64, (3<<18)|0x30ac2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 64 (5.320GHz)
233 234
234 {100, (3<<18)|0x30ec0, (4<<18)|0x08000, (5<<18)|0x2A9C6}, // 100 (5.500GHz) 235 {100, (3<<18)|0x30ec0, (4<<18)|0x08000, (5<<18)|0x2A9C6}, // 100 (5.500GHz)
235 {104, (3<<18)|0x30ec2, (4<<18)|0x0b333, (5<<18)|0x2A9C6}, // 104 (5.520GHz) 236 {104, (3<<18)|0x30ec2, (4<<18)|0x0b333, (5<<18)|0x2A9C6}, // 104 (5.520GHz)
236 {108, (3<<18)|0x32ec1, (4<<18)|0x09999, (5<<18)|0x2A9C6}, // 108 (5.540GHz) 237 {108, (3<<18)|0x32ec1, (4<<18)|0x09999, (5<<18)|0x2A9C6}, // 108 (5.540GHz)
237 {112, (3<<18)|0x31ec1, (4<<18)|0x0a666, (5<<18)|0x2A9C6}, // 112 (5.560GHz) 238 {112, (3<<18)|0x31ec1, (4<<18)|0x0a666, (5<<18)|0x2A9C6}, // 112 (5.560GHz)
238 {116, (3<<18)|0x33ec3, (4<<18)|0x08ccc, (5<<18)|0x2A9C6}, // 116 (5.580GHz) 239 {116, (3<<18)|0x33ec3, (4<<18)|0x08ccc, (5<<18)|0x2A9C6}, // 116 (5.580GHz)
239 {120, (3<<18)|0x301c0, (4<<18)|0x08000, (5<<18)|0x2A9C6}, // 120 (5.600GHz) 240 {120, (3<<18)|0x301c0, (4<<18)|0x08000, (5<<18)|0x2A9C6}, // 120 (5.600GHz)
240 {124, (3<<18)|0x301c2, (4<<18)|0x0b333, (5<<18)|0x2A9C6}, // 124 (5.620GHz) 241 {124, (3<<18)|0x301c2, (4<<18)|0x0b333, (5<<18)|0x2A9C6}, // 124 (5.620GHz)
241 {128, (3<<18)|0x321c1, (4<<18)|0x09999, (5<<18)|0x2A9C6}, // 128 (5.640GHz) 242 {128, (3<<18)|0x321c1, (4<<18)|0x09999, (5<<18)|0x2A9C6}, // 128 (5.640GHz)
242 {132, (3<<18)|0x311c1, (4<<18)|0x0a666, (5<<18)|0x2A9C6}, // 132 (5.660GHz) 243 {132, (3<<18)|0x311c1, (4<<18)|0x0a666, (5<<18)|0x2A9C6}, // 132 (5.660GHz)
243 {136, (3<<18)|0x331c3, (4<<18)|0x08ccc, (5<<18)|0x2A9C6}, // 136 (5.680GHz) 244 {136, (3<<18)|0x331c3, (4<<18)|0x08ccc, (5<<18)|0x2A9C6}, // 136 (5.680GHz)
244 {140, (3<<18)|0x309c0, (4<<18)|0x08000, (5<<18)|0x2A9C6}, // 140 (5.700GHz) 245 {140, (3<<18)|0x309c0, (4<<18)|0x08000, (5<<18)|0x2A9C6}, // 140 (5.700GHz)
245 246
246 {149, (3<<18)|0x329c2, (4<<18)|0x0b333, (5<<18)|0x2A9C6}, // 149 (5.745GHz) 247 {149, (3<<18)|0x329c2, (4<<18)|0x0b333, (5<<18)|0x2A9C6}, // 149 (5.745GHz)
247 {153, (3<<18)|0x319c1, (4<<18)|0x09999, (5<<18)|0x2A9C6}, // 153 (5.765GHz) 248 {153, (3<<18)|0x319c1, (4<<18)|0x09999, (5<<18)|0x2A9C6}, // 153 (5.765GHz)
248 {157, (3<<18)|0x339c1, (4<<18)|0x0a666, (5<<18)|0x2A9C6}, // 157 (5.785GHz) 249 {157, (3<<18)|0x339c1, (4<<18)|0x0a666, (5<<18)|0x2A9C6}, // 157 (5.785GHz)
249 {161, (3<<18)|0x305c3, (4<<18)|0x08ccc, (5<<18)|0x2A9C6}, // 161 (5.805GHz) 250 {161, (3<<18)|0x305c3, (4<<18)|0x08ccc, (5<<18)|0x2A9C6}, // 161 (5.805GHz)
250 251
251 // Japan 252 // Japan
252 { 184, (3<<18)|0x308c2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 184 (4.920GHz) 253 { 184, (3<<18)|0x308c2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 184 (4.920GHz)
253 { 188, (3<<18)|0x328c1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 188 (4.940GHz) 254 { 188, (3<<18)|0x328c1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 188 (4.940GHz)
254 { 192, (3<<18)|0x318c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 192 (4.960GHz) 255 { 192, (3<<18)|0x318c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 192 (4.960GHz)
255 { 196, (3<<18)|0x338c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 196 (4.980GHz) 256 { 196, (3<<18)|0x338c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 196 (4.980GHz)
256 { 8, (3<<18)|0x324c1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 8 (5.040GHz) 257 { 8, (3<<18)|0x324c1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 8 (5.040GHz)
257 { 12, (3<<18)|0x314c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 12 (5.060GHz) 258 { 12, (3<<18)|0x314c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 12 (5.060GHz)
258 { 16, (3<<18)|0x334c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 16 (5.080GHz) 259 { 16, (3<<18)|0x334c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 16 (5.080GHz)
259 { 34, (3<<18)|0x31cc2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 34 (5.170GHz) 260 { 34, (3<<18)|0x31cc2, (4<<18)|0x0b333, (5<<18)|0x2A946}, // 34 (5.170GHz)
260 { 38, (3<<18)|0x33cc1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 38 (5.190GHz) 261 { 38, (3<<18)|0x33cc1, (4<<18)|0x09999, (5<<18)|0x2A946}, // 38 (5.190GHz)
261 { 42, (3<<18)|0x302c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 42 (5.210GHz) 262 { 42, (3<<18)|0x302c1, (4<<18)|0x0a666, (5<<18)|0x2A946}, // 42 (5.210GHz)
262 { 46, (3<<18)|0x322c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 46 (5.230GHz) 263 { 46, (3<<18)|0x322c3, (4<<18)|0x08ccc, (5<<18)|0x2A946}, // 46 (5.230GHz)
263 }; 264 };
264 265
265 /***************************************************************************** 266 /*****************************************************************************
266 ; For MAXIM2825/6/7 Ver. 317 or less 267 ; For MAXIM2825/6/7 Ver. 317 or less
267 ; Edited by Tiger, Sep-17-2003 for 2.4Ghz channels 268 ; Edited by Tiger, Sep-17-2003 for 2.4Ghz channels
268 ; Updated by Tiger, Sep-22-2003 for 5.0Ghz channels 269 ; Updated by Tiger, Sep-22-2003 for 5.0Ghz channels
269 ; Corrected by Tiger, Sep-23-2003, for 0x03 and 0x04 of 5.0Ghz channels 270 ; Corrected by Tiger, Sep-23-2003, for 0x03 and 0x04 of 5.0Ghz channels
270 271
271 0x00 0x00080 272 0x00 0x00080
272 0x01 0x214c0 273 0x01 0x214c0
273 0x02 0x13802 274 0x02 0x13802
274 275
275 ;2.4GHz Channels 276 ;2.4GHz Channels
276 ;channe1 01 (2.412GHz); 0x03 0x30143 ;0x04 0x0accc 277 ;channe1 01 (2.412GHz); 0x03 0x30143 ;0x04 0x0accc
277 ;channe1 02 (2.417GHz); 0x03 0x32140 ;0x04 0x09111 278 ;channe1 02 (2.417GHz); 0x03 0x32140 ;0x04 0x09111
278 ;channe1 03 (2.422GHz); 0x03 0x32142 ;0x04 0x0bbbb 279 ;channe1 03 (2.422GHz); 0x03 0x32142 ;0x04 0x0bbbb
279 ;channe1 04 (2.427GHz); 0x03 0x32143 ;0x04 0x0accc 280 ;channe1 04 (2.427GHz); 0x03 0x32143 ;0x04 0x0accc
280 ;channe1 05 (2.432GHz); 0x03 0x31140 ;0x04 0x09111 281 ;channe1 05 (2.432GHz); 0x03 0x31140 ;0x04 0x09111
281 ;channe1 06 (2.437GHz); 0x03 0x31142 ;0x04 0x0bbbb 282 ;channe1 06 (2.437GHz); 0x03 0x31142 ;0x04 0x0bbbb
282 ;channe1 07 (2.442GHz); 0x03 0x31143 ;0x04 0x0accc 283 ;channe1 07 (2.442GHz); 0x03 0x31143 ;0x04 0x0accc
283 ;channe1 08 (2.447GHz); 0x03 0x33140 ;0x04 0x09111 284 ;channe1 08 (2.447GHz); 0x03 0x33140 ;0x04 0x09111
284 ;channe1 09 (2.452GHz); 0x03 0x33142 ;0x04 0x0bbbb 285 ;channe1 09 (2.452GHz); 0x03 0x33142 ;0x04 0x0bbbb
285 ;channe1 10 (2.457GHz); 0x03 0x33143 ;0x04 0x0accc 286 ;channe1 10 (2.457GHz); 0x03 0x33143 ;0x04 0x0accc
286 ;channe1 11 (2.462GHz); 0x03 0x30940 ;0x04 0x09111 287 ;channe1 11 (2.462GHz); 0x03 0x30940 ;0x04 0x09111
287 ;channe1 12 (2.467GHz); 0x03 0x30942 ;0x04 0x0bbbb 288 ;channe1 12 (2.467GHz); 0x03 0x30942 ;0x04 0x0bbbb
288 ;channe1 13 (2.472GHz); 0x03 0x30943 ;0x04 0x0accc 289 ;channe1 13 (2.472GHz); 0x03 0x30943 ;0x04 0x0accc
289 290
290 ;5.0Ghz Channels 291 ;5.0Ghz Channels
291 ;channel 36 (5.180GHz); 0x03 0x33cc0 ;0x04 0x0b333 292 ;channel 36 (5.180GHz); 0x03 0x33cc0 ;0x04 0x0b333
292 ;channel 40 (5.200GHz); 0x03 0x302c0 ;0x04 0x08000 293 ;channel 40 (5.200GHz); 0x03 0x302c0 ;0x04 0x08000
293 ;channel 44 (5.220GHz); 0x03 0x302c2 ;0x04 0x0b333 294 ;channel 44 (5.220GHz); 0x03 0x302c2 ;0x04 0x0b333
294 ;channel 48 (5.240GHz); 0x03 0x322c1 ;0x04 0x09999 295 ;channel 48 (5.240GHz); 0x03 0x322c1 ;0x04 0x09999
295 ;channel 52 (5.260GHz); 0x03 0x312c1 ;0x04 0x0a666 296 ;channel 52 (5.260GHz); 0x03 0x312c1 ;0x04 0x0a666
296 ;channel 56 (5.280GHz); 0x03 0x332c3 ;0x04 0x08ccc 297 ;channel 56 (5.280GHz); 0x03 0x332c3 ;0x04 0x08ccc
297 ;channel 60 (5.300GHz); 0x03 0x30ac0 ;0x04 0x08000 298 ;channel 60 (5.300GHz); 0x03 0x30ac0 ;0x04 0x08000
298 ;channel 64 (5.320GHz); 0x03 0x30ac2 ;0x04 0x08333 299 ;channel 64 (5.320GHz); 0x03 0x30ac2 ;0x04 0x08333
299 300
300 ;2.4GHz band ;0x05 0x28986; 301 ;2.4GHz band ;0x05 0x28986;
301 ;5.0GHz band 302 ;5.0GHz band
302 0x05 0x2a986 303 0x05 0x2a986
303 304
304 0x06 0x18008 305 0x06 0x18008
305 0x07 0x38400 306 0x07 0x38400
306 0x08 0x05108 307 0x08 0x05108
307 0x09 0x27ff8 308 0x09 0x27ff8
308 0x0a 0x14000 309 0x0a 0x14000
309 0x0b 0x37f99 310 0x0b 0x37f99
310 0x0c 0x0c000 311 0x0c 0x0c000
311 *****************************************************************************/ 312 *****************************************************************************/
312 u32 maxim_317_rf_data[] = 313 u32 maxim_317_rf_data[] =
313 { 314 {
314 (0x00<<18)|0x000a2, 315 (0x00<<18)|0x000a2,
315 (0x01<<18)|0x214c0, 316 (0x01<<18)|0x214c0,
316 (0x02<<18)|0x13802, 317 (0x02<<18)|0x13802,
317 (0x03<<18)|0x30143, 318 (0x03<<18)|0x30143,
318 (0x04<<18)|0x0accc, 319 (0x04<<18)|0x0accc,
319 (0x05<<18)|0x28986, 320 (0x05<<18)|0x28986,
320 (0x06<<18)|0x18008, 321 (0x06<<18)|0x18008,
321 (0x07<<18)|0x38400, 322 (0x07<<18)|0x38400,
322 (0x08<<18)|0x05108, 323 (0x08<<18)|0x05108,
323 (0x09<<18)|0x27ff8, 324 (0x09<<18)|0x27ff8,
324 (0x0A<<18)|0x14000, 325 (0x0A<<18)|0x14000,
325 (0x0B<<18)|0x37f99, 326 (0x0B<<18)|0x37f99,
326 (0x0C<<18)|0x0c000 327 (0x0C<<18)|0x0c000
327 }; 328 };
328 329
329 u32 maxim_317_channel_data_24[][3] = 330 u32 maxim_317_channel_data_24[][3] =
330 { 331 {
331 {(0x03<<18)|0x30143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 01 332 {(0x03<<18)|0x30143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 01
332 {(0x03<<18)|0x32140, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 02 333 {(0x03<<18)|0x32140, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 02
333 {(0x03<<18)|0x32142, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 03 334 {(0x03<<18)|0x32142, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 03
334 {(0x03<<18)|0x32143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 04 335 {(0x03<<18)|0x32143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 04
335 {(0x03<<18)|0x31140, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 05 336 {(0x03<<18)|0x31140, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 05
336 {(0x03<<18)|0x31142, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 06 337 {(0x03<<18)|0x31142, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 06
337 {(0x03<<18)|0x31143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 07 338 {(0x03<<18)|0x31143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 07
338 {(0x03<<18)|0x33140, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 08 339 {(0x03<<18)|0x33140, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 08
339 {(0x03<<18)|0x33142, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 09 340 {(0x03<<18)|0x33142, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 09
340 {(0x03<<18)|0x33143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 10 341 {(0x03<<18)|0x33143, (0x04<<18)|0x0accc, (0x05<<18)|0x28986}, // channe1 10
341 {(0x03<<18)|0x30940, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 11 342 {(0x03<<18)|0x30940, (0x04<<18)|0x09111, (0x05<<18)|0x28986}, // channe1 11
342 {(0x03<<18)|0x30942, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 12 343 {(0x03<<18)|0x30942, (0x04<<18)|0x0bbbb, (0x05<<18)|0x28986}, // channe1 12
343 {(0x03<<18)|0x30943, (0x04<<18)|0x0accc, (0x05<<18)|0x28986} // channe1 13 344 {(0x03<<18)|0x30943, (0x04<<18)|0x0accc, (0x05<<18)|0x28986} // channe1 13
344 }; 345 };
345 346
346 u32 maxim_317_channel_data_50[][3] = 347 u32 maxim_317_channel_data_50[][3] =
347 { 348 {
348 {(0x03<<18)|0x33cc0, (0x04<<18)|0x0b333, (0x05<<18)|0x2a986}, // channel 36 349 {(0x03<<18)|0x33cc0, (0x04<<18)|0x0b333, (0x05<<18)|0x2a986}, // channel 36
349 {(0x03<<18)|0x302c0, (0x04<<18)|0x08000, (0x05<<18)|0x2a986}, // channel 40 350 {(0x03<<18)|0x302c0, (0x04<<18)|0x08000, (0x05<<18)|0x2a986}, // channel 40
350 {(0x03<<18)|0x302c3, (0x04<<18)|0x0accc, (0x05<<18)|0x2a986}, // channel 44 351 {(0x03<<18)|0x302c3, (0x04<<18)|0x0accc, (0x05<<18)|0x2a986}, // channel 44
351 {(0x03<<18)|0x322c1, (0x04<<18)|0x09666, (0x05<<18)|0x2a986}, // channel 48 352 {(0x03<<18)|0x322c1, (0x04<<18)|0x09666, (0x05<<18)|0x2a986}, // channel 48
352 {(0x03<<18)|0x312c2, (0x04<<18)|0x09999, (0x05<<18)|0x2a986}, // channel 52 353 {(0x03<<18)|0x312c2, (0x04<<18)|0x09999, (0x05<<18)|0x2a986}, // channel 52
353 {(0x03<<18)|0x332c0, (0x04<<18)|0x0b333, (0x05<<18)|0x2a99e}, // channel 56 354 {(0x03<<18)|0x332c0, (0x04<<18)|0x0b333, (0x05<<18)|0x2a99e}, // channel 56
354 {(0x03<<18)|0x30ac0, (0x04<<18)|0x08000, (0x05<<18)|0x2a99e}, // channel 60 355 {(0x03<<18)|0x30ac0, (0x04<<18)|0x08000, (0x05<<18)|0x2a99e}, // channel 60
355 {(0x03<<18)|0x30ac3, (0x04<<18)|0x0accc, (0x05<<18)|0x2a99e} // channel 64 356 {(0x03<<18)|0x30ac3, (0x04<<18)|0x0accc, (0x05<<18)|0x2a99e} // channel 64
356 }; 357 };
357 358
358 u32 maxim_317_power_data_24[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100}; 359 u32 maxim_317_power_data_24[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100};
359 u32 maxim_317_power_data_50[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100}; 360 u32 maxim_317_power_data_50[] = {(0x0C<<18)|0x0c000, (0x0C<<18)|0x0c100};
360 361
361 /***************************************************************************** 362 /*****************************************************************************
362 ;;AL2230 MP (Mass Production Version) 363 ;;AL2230 MP (Mass Production Version)
363 ;;RF Registers Setting for Airoha AL2230 silicon after June 1st, 2004 364 ;;RF Registers Setting for Airoha AL2230 silicon after June 1st, 2004
364 ;;Updated by Tiger Huang (June 1st, 2004) 365 ;;Updated by Tiger Huang (June 1st, 2004)
365 ;;20-bit length and LSB first 366 ;;20-bit length and LSB first
366 367
367 ;;Ch01 (2412MHz) ;0x00 0x09EFC ;0x01 0x8CCCC; 368 ;;Ch01 (2412MHz) ;0x00 0x09EFC ;0x01 0x8CCCC;
368 ;;Ch02 (2417MHz) ;0x00 0x09EFC ;0x01 0x8CCCD; 369 ;;Ch02 (2417MHz) ;0x00 0x09EFC ;0x01 0x8CCCD;
369 ;;Ch03 (2422MHz) ;0x00 0x09E7C ;0x01 0x8CCCC; 370 ;;Ch03 (2422MHz) ;0x00 0x09E7C ;0x01 0x8CCCC;
370 ;;Ch04 (2427MHz) ;0x00 0x09E7C ;0x01 0x8CCCD; 371 ;;Ch04 (2427MHz) ;0x00 0x09E7C ;0x01 0x8CCCD;
371 ;;Ch05 (2432MHz) ;0x00 0x05EFC ;0x01 0x8CCCC; 372 ;;Ch05 (2432MHz) ;0x00 0x05EFC ;0x01 0x8CCCC;
372 ;;Ch06 (2437MHz) ;0x00 0x05EFC ;0x01 0x8CCCD; 373 ;;Ch06 (2437MHz) ;0x00 0x05EFC ;0x01 0x8CCCD;
373 ;;Ch07 (2442MHz) ;0x00 0x05E7C ;0x01 0x8CCCC; 374 ;;Ch07 (2442MHz) ;0x00 0x05E7C ;0x01 0x8CCCC;
374 ;;Ch08 (2447MHz) ;0x00 0x05E7C ;0x01 0x8CCCD; 375 ;;Ch08 (2447MHz) ;0x00 0x05E7C ;0x01 0x8CCCD;
375 ;;Ch09 (2452MHz) ;0x00 0x0DEFC ;0x01 0x8CCCC; 376 ;;Ch09 (2452MHz) ;0x00 0x0DEFC ;0x01 0x8CCCC;
376 ;;Ch10 (2457MHz) ;0x00 0x0DEFC ;0x01 0x8CCCD; 377 ;;Ch10 (2457MHz) ;0x00 0x0DEFC ;0x01 0x8CCCD;
377 ;;Ch11 (2462MHz) ;0x00 0x0DE7C ;0x01 0x8CCCC; 378 ;;Ch11 (2462MHz) ;0x00 0x0DE7C ;0x01 0x8CCCC;
378 ;;Ch12 (2467MHz) ;0x00 0x0DE7C ;0x01 0x8CCCD; 379 ;;Ch12 (2467MHz) ;0x00 0x0DE7C ;0x01 0x8CCCD;
379 ;;Ch13 (2472MHz) ;0x00 0x03EFC ;0x01 0x8CCCC; 380 ;;Ch13 (2472MHz) ;0x00 0x03EFC ;0x01 0x8CCCC;
380 ;;Ch14 (2484Mhz) ;0x00 0x03E7C ;0x01 0x86666; 381 ;;Ch14 (2484Mhz) ;0x00 0x03E7C ;0x01 0x86666;
381 382
382 0x02 0x401D8; RXDCOC BW 100Hz for RXHP low 383 0x02 0x401D8; RXDCOC BW 100Hz for RXHP low
383 ;;0x02 0x481DC; RXDCOC BW 30Khz for RXHP low 384 ;;0x02 0x481DC; RXDCOC BW 30Khz for RXHP low
384 385
385 0x03 0xCFFF0 386 0x03 0xCFFF0
386 0x04 0x23800 387 0x04 0x23800
387 0x05 0xA3B72 388 0x05 0xA3B72
388 0x06 0x6DA01 389 0x06 0x6DA01
389 0x07 0xE1688 390 0x07 0xE1688
390 0x08 0x11600 391 0x08 0x11600
391 0x09 0x99E02 392 0x09 0x99E02
392 0x0A 0x5DDB0 393 0x0A 0x5DDB0
393 0x0B 0xD9900 394 0x0B 0xD9900
394 0x0C 0x3FFBD 395 0x0C 0x3FFBD
395 0x0D 0xB0000 396 0x0D 0xB0000
396 0x0F 0xF00A0 397 0x0F 0xF00A0
397 398
398 ;RF Calibration for Airoha AL2230 399 ;RF Calibration for Airoha AL2230
399 ;Edit by Ben Chang (01/30/04) 400 ;Edit by Ben Chang (01/30/04)
400 ;Updated by Tiger Huang (03/03/04) 401 ;Updated by Tiger Huang (03/03/04)
401 0x0f 0xf00a0 ; Initial Setting 402 0x0f 0xf00a0 ; Initial Setting
402 0x0f 0xf00b0 ; Activate TX DCC 403 0x0f 0xf00b0 ; Activate TX DCC
403 0x0f 0xf02a0 ; Activate Phase Calibration 404 0x0f 0xf02a0 ; Activate Phase Calibration
404 0x0f 0xf00e0 ; Activate Filter RC Calibration 405 0x0f 0xf00e0 ; Activate Filter RC Calibration
405 0x0f 0xf00a0 ; Restore Initial Setting 406 0x0f 0xf00a0 ; Restore Initial Setting
406 *****************************************************************************/ 407 *****************************************************************************/
407 408
408 u32 al2230_rf_data[] = 409 u32 al2230_rf_data[] =
409 { 410 {
410 (0x00<<20)|0x09EFC, 411 (0x00<<20)|0x09EFC,
411 (0x01<<20)|0x8CCCC, 412 (0x01<<20)|0x8CCCC,
412 (0x02<<20)|0x40058,// 20060627 Anson 0x401D8, 413 (0x02<<20)|0x40058,// 20060627 Anson 0x401D8,
413 (0x03<<20)|0xCFFF0, 414 (0x03<<20)|0xCFFF0,
414 (0x04<<20)|0x24100,// 20060627 Anson 0x23800, 415 (0x04<<20)|0x24100,// 20060627 Anson 0x23800,
415 (0x05<<20)|0xA3B2F,// 20060627 Anson 0xA3B72 416 (0x05<<20)|0xA3B2F,// 20060627 Anson 0xA3B72
416 (0x06<<20)|0x6DA01, 417 (0x06<<20)|0x6DA01,
417 (0x07<<20)|0xE3628,// 20060627 Anson 0xE1688, 418 (0x07<<20)|0xE3628,// 20060627 Anson 0xE1688,
418 (0x08<<20)|0x11600, 419 (0x08<<20)|0x11600,
419 (0x09<<20)|0x9DC02,// 20060627 Anosn 0x97602,//0x99E02, //0x9AE02 420 (0x09<<20)|0x9DC02,// 20060627 Anosn 0x97602,//0x99E02, //0x9AE02
420 (0x0A<<20)|0x5ddb0, // 941206 For QCOM interference 0x588b0,//0x5DDB0, 940601 adj 0x5aa30 for bluetooth 421 (0x0A<<20)|0x5ddb0, // 941206 For QCOM interference 0x588b0,//0x5DDB0, 940601 adj 0x5aa30 for bluetooth
421 (0x0B<<20)|0xD9900, 422 (0x0B<<20)|0xD9900,
422 (0x0C<<20)|0x3FFBD, 423 (0x0C<<20)|0x3FFBD,
423 (0x0D<<20)|0xB0000, 424 (0x0D<<20)|0xB0000,
424 (0x0F<<20)|0xF01A0 // 20060627 Anson 0xF00A0 425 (0x0F<<20)|0xF01A0 // 20060627 Anson 0xF00A0
425 }; 426 };
426 427
427 u32 al2230s_rf_data[] = 428 u32 al2230s_rf_data[] =
428 { 429 {
429 (0x00<<20)|0x09EFC, 430 (0x00<<20)|0x09EFC,
430 (0x01<<20)|0x8CCCC, 431 (0x01<<20)|0x8CCCC,
431 (0x02<<20)|0x40058,// 20060419 0x401D8, 432 (0x02<<20)|0x40058,// 20060419 0x401D8,
432 (0x03<<20)|0xCFFF0, 433 (0x03<<20)|0xCFFF0,
433 (0x04<<20)|0x24100,// 20060419 0x23800, 434 (0x04<<20)|0x24100,// 20060419 0x23800,
434 (0x05<<20)|0xA3B2F,// 20060419 0xA3B72, 435 (0x05<<20)|0xA3B2F,// 20060419 0xA3B72,
435 (0x06<<20)|0x6DA01, 436 (0x06<<20)|0x6DA01,
436 (0x07<<20)|0xE3628,// 20060419 0xE1688, 437 (0x07<<20)|0xE3628,// 20060419 0xE1688,
437 (0x08<<20)|0x11600, 438 (0x08<<20)|0x11600,
438 (0x09<<20)|0x9DC02,// 20060419 0x97602,//0x99E02, //0x9AE02 439 (0x09<<20)|0x9DC02,// 20060419 0x97602,//0x99E02, //0x9AE02
439 (0x0A<<20)|0x5DDB0,// 941206 For QCOM interference 0x588b0,//0x5DDB0, 940601 adj 0x5aa30 for bluetooth 440 (0x0A<<20)|0x5DDB0,// 941206 For QCOM interference 0x588b0,//0x5DDB0, 940601 adj 0x5aa30 for bluetooth
440 (0x0B<<20)|0xD9900, 441 (0x0B<<20)|0xD9900,
441 (0x0C<<20)|0x3FFBD, 442 (0x0C<<20)|0x3FFBD,
442 (0x0D<<20)|0xB0000, 443 (0x0D<<20)|0xB0000,
443 (0x0F<<20)|0xF01A0 // 20060419 0xF00A0 444 (0x0F<<20)|0xF01A0 // 20060419 0xF00A0
444 }; 445 };
445 446
446 u32 al2230_channel_data_24[][2] = 447 u32 al2230_channel_data_24[][2] =
447 { 448 {
448 {(0x00<<20)|0x09EFC, (0x01<<20)|0x8CCCC}, // channe1 01 449 {(0x00<<20)|0x09EFC, (0x01<<20)|0x8CCCC}, // channe1 01
449 {(0x00<<20)|0x09EFC, (0x01<<20)|0x8CCCD}, // channe1 02 450 {(0x00<<20)|0x09EFC, (0x01<<20)|0x8CCCD}, // channe1 02
450 {(0x00<<20)|0x09E7C, (0x01<<20)|0x8CCCC}, // channe1 03 451 {(0x00<<20)|0x09E7C, (0x01<<20)|0x8CCCC}, // channe1 03
451 {(0x00<<20)|0x09E7C, (0x01<<20)|0x8CCCD}, // channe1 04 452 {(0x00<<20)|0x09E7C, (0x01<<20)|0x8CCCD}, // channe1 04
452 {(0x00<<20)|0x05EFC, (0x01<<20)|0x8CCCC}, // channe1 05 453 {(0x00<<20)|0x05EFC, (0x01<<20)|0x8CCCC}, // channe1 05
453 {(0x00<<20)|0x05EFC, (0x01<<20)|0x8CCCD}, // channe1 06 454 {(0x00<<20)|0x05EFC, (0x01<<20)|0x8CCCD}, // channe1 06
454 {(0x00<<20)|0x05E7C, (0x01<<20)|0x8CCCC}, // channe1 07 455 {(0x00<<20)|0x05E7C, (0x01<<20)|0x8CCCC}, // channe1 07
455 {(0x00<<20)|0x05E7C, (0x01<<20)|0x8CCCD}, // channe1 08 456 {(0x00<<20)|0x05E7C, (0x01<<20)|0x8CCCD}, // channe1 08
456 {(0x00<<20)|0x0DEFC, (0x01<<20)|0x8CCCC}, // channe1 09 457 {(0x00<<20)|0x0DEFC, (0x01<<20)|0x8CCCC}, // channe1 09
457 {(0x00<<20)|0x0DEFC, (0x01<<20)|0x8CCCD}, // channe1 10 458 {(0x00<<20)|0x0DEFC, (0x01<<20)|0x8CCCD}, // channe1 10
458 {(0x00<<20)|0x0DE7C, (0x01<<20)|0x8CCCC}, // channe1 11 459 {(0x00<<20)|0x0DE7C, (0x01<<20)|0x8CCCC}, // channe1 11
459 {(0x00<<20)|0x0DE7C, (0x01<<20)|0x8CCCD}, // channe1 12 460 {(0x00<<20)|0x0DE7C, (0x01<<20)|0x8CCCD}, // channe1 12
460 {(0x00<<20)|0x03EFC, (0x01<<20)|0x8CCCC}, // channe1 13 461 {(0x00<<20)|0x03EFC, (0x01<<20)|0x8CCCC}, // channe1 13
461 {(0x00<<20)|0x03E7C, (0x01<<20)|0x86666} // channe1 14 462 {(0x00<<20)|0x03E7C, (0x01<<20)|0x86666} // channe1 14
462 }; 463 };
463 464
464 // Current setting. u32 airoha_power_data_24[] = {(0x09<<20)|0x90202, (0x09<<20)|0x96602, (0x09<<20)|0x97602}; 465 // Current setting. u32 airoha_power_data_24[] = {(0x09<<20)|0x90202, (0x09<<20)|0x96602, (0x09<<20)|0x97602};
465 #define AIROHA_TXVGA_LOW_INDEX 31 // Index for 0x90202 466 #define AIROHA_TXVGA_LOW_INDEX 31 // Index for 0x90202
466 #define AIROHA_TXVGA_MIDDLE_INDEX 12 // Index for 0x96602 467 #define AIROHA_TXVGA_MIDDLE_INDEX 12 // Index for 0x96602
467 #define AIROHA_TXVGA_HIGH_INDEX 8 // Index for 0x97602 1.0.24.0 1.0.28.0 468 #define AIROHA_TXVGA_HIGH_INDEX 8 // Index for 0x97602 1.0.24.0 1.0.28.0
468 /* 469 /*
469 u32 airoha_power_data_24[] = 470 u32 airoha_power_data_24[] =
470 { 471 {
471 0x9FE02, // Max - 0 dB 472 0x9FE02, // Max - 0 dB
472 0x9BE02, // Max - 1 dB 473 0x9BE02, // Max - 1 dB
473 0x9DE02, // Max - 2 dB 474 0x9DE02, // Max - 2 dB
474 0x99E02, // Max - 3 dB 475 0x99E02, // Max - 3 dB
475 0x9EE02, // Max - 4 dB 476 0x9EE02, // Max - 4 dB
476 0x9AE02, // Max - 5 dB 477 0x9AE02, // Max - 5 dB
477 0x9CE02, // Max - 6 dB 478 0x9CE02, // Max - 6 dB
478 0x98E02, // Max - 7 dB 479 0x98E02, // Max - 7 dB
479 0x97602, // Max - 8 dB 480 0x97602, // Max - 8 dB
480 0x93602, // Max - 9 dB 481 0x93602, // Max - 9 dB
481 0x95602, // Max - 10 dB 482 0x95602, // Max - 10 dB
482 0x91602, // Max - 11 dB 483 0x91602, // Max - 11 dB
483 0x96602, // Max - 12 dB 484 0x96602, // Max - 12 dB
484 0x92602, // Max - 13 dB 485 0x92602, // Max - 13 dB
485 0x94602, // Max - 14 dB 486 0x94602, // Max - 14 dB
486 0x90602, // Max - 15 dB 487 0x90602, // Max - 15 dB
487 0x97A02, // Max - 16 dB 488 0x97A02, // Max - 16 dB
488 0x93A02, // Max - 17 dB 489 0x93A02, // Max - 17 dB
489 0x95A02, // Max - 18 dB 490 0x95A02, // Max - 18 dB
490 0x91A02, // Max - 19 dB 491 0x91A02, // Max - 19 dB
491 0x96A02, // Max - 20 dB 492 0x96A02, // Max - 20 dB
492 0x92A02, // Max - 21 dB 493 0x92A02, // Max - 21 dB
493 0x94A02, // Max - 22 dB 494 0x94A02, // Max - 22 dB
494 0x90A02, // Max - 23 dB 495 0x90A02, // Max - 23 dB
495 0x97202, // Max - 24 dB 496 0x97202, // Max - 24 dB
496 0x93202, // Max - 25 dB 497 0x93202, // Max - 25 dB
497 0x95202, // Max - 26 dB 498 0x95202, // Max - 26 dB
498 0x91202, // Max - 27 dB 499 0x91202, // Max - 27 dB
499 0x96202, // Max - 28 dB 500 0x96202, // Max - 28 dB
500 0x92202, // Max - 29 dB 501 0x92202, // Max - 29 dB
501 0x94202, // Max - 30 dB 502 0x94202, // Max - 30 dB
502 0x90202 // Max - 31 dB 503 0x90202 // Max - 31 dB
503 }; 504 };
504 */ 505 */
505 506
506 // 20040927 1.1.69.1000 ybjiang 507 // 20040927 1.1.69.1000 ybjiang
507 // from John 508 // from John
508 u32 al2230_txvga_data[][2] = 509 u32 al2230_txvga_data[][2] =
509 { 510 {
510 //value , index 511 //value , index
511 {0x090202, 0}, 512 {0x090202, 0},
512 {0x094202, 2}, 513 {0x094202, 2},
513 {0x092202, 4}, 514 {0x092202, 4},
514 {0x096202, 6}, 515 {0x096202, 6},
515 {0x091202, 8}, 516 {0x091202, 8},
516 {0x095202, 10}, 517 {0x095202, 10},
517 {0x093202, 12}, 518 {0x093202, 12},
518 {0x097202, 14}, 519 {0x097202, 14},
519 {0x090A02, 16}, 520 {0x090A02, 16},
520 {0x094A02, 18}, 521 {0x094A02, 18},
521 {0x092A02, 20}, 522 {0x092A02, 20},
522 {0x096A02, 22}, 523 {0x096A02, 22},
523 {0x091A02, 24}, 524 {0x091A02, 24},
524 {0x095A02, 26}, 525 {0x095A02, 26},
525 {0x093A02, 28}, 526 {0x093A02, 28},
526 {0x097A02, 30}, 527 {0x097A02, 30},
527 {0x090602, 32}, 528 {0x090602, 32},
528 {0x094602, 34}, 529 {0x094602, 34},
529 {0x092602, 36}, 530 {0x092602, 36},
530 {0x096602, 38}, 531 {0x096602, 38},
531 {0x091602, 40}, 532 {0x091602, 40},
532 {0x095602, 42}, 533 {0x095602, 42},
533 {0x093602, 44}, 534 {0x093602, 44},
534 {0x097602, 46}, 535 {0x097602, 46},
535 {0x090E02, 48}, 536 {0x090E02, 48},
536 {0x098E02, 49}, 537 {0x098E02, 49},
537 {0x094E02, 50}, 538 {0x094E02, 50},
538 {0x09CE02, 51}, 539 {0x09CE02, 51},
539 {0x092E02, 52}, 540 {0x092E02, 52},
540 {0x09AE02, 53}, 541 {0x09AE02, 53},
541 {0x096E02, 54}, 542 {0x096E02, 54},
542 {0x09EE02, 55}, 543 {0x09EE02, 55},
543 {0x091E02, 56}, 544 {0x091E02, 56},
544 {0x099E02, 57}, 545 {0x099E02, 57},
545 {0x095E02, 58}, 546 {0x095E02, 58},
546 {0x09DE02, 59}, 547 {0x09DE02, 59},
547 {0x093E02, 60}, 548 {0x093E02, 60},
548 {0x09BE02, 61}, 549 {0x09BE02, 61},
549 {0x097E02, 62}, 550 {0x097E02, 62},
550 {0x09FE02, 63} 551 {0x09FE02, 63}
551 }; 552 };
552 553
553 //-------------------------------- 554 //--------------------------------
554 // For Airoha AL7230, 2.4Ghz band 555 // For Airoha AL7230, 2.4Ghz band
555 // Edit by Tiger, (March, 9, 2005) 556 // Edit by Tiger, (March, 9, 2005)
556 // 24bit, MSB first 557 // 24bit, MSB first
557 558
558 //channel independent registers: 559 //channel independent registers:
559 u32 al7230_rf_data_24[] = 560 u32 al7230_rf_data_24[] =
560 { 561 {
561 (0x00<<24)|0x003790, 562 (0x00<<24)|0x003790,
562 (0x01<<24)|0x133331, 563 (0x01<<24)|0x133331,
563 (0x02<<24)|0x841FF2, 564 (0x02<<24)|0x841FF2,
564 (0x03<<24)|0x3FDFA3, 565 (0x03<<24)|0x3FDFA3,
565 (0x04<<24)|0x7FD784, 566 (0x04<<24)|0x7FD784,
566 (0x05<<24)|0x802B55, 567 (0x05<<24)|0x802B55,
567 (0x06<<24)|0x56AF36, 568 (0x06<<24)|0x56AF36,
568 (0x07<<24)|0xCE0207, 569 (0x07<<24)|0xCE0207,
569 (0x08<<24)|0x6EBC08, 570 (0x08<<24)|0x6EBC08,
570 (0x09<<24)|0x221BB9, 571 (0x09<<24)|0x221BB9,
571 (0x0A<<24)|0xE0000A, 572 (0x0A<<24)|0xE0000A,
572 (0x0B<<24)|0x08071B, 573 (0x0B<<24)|0x08071B,
573 (0x0C<<24)|0x000A3C, 574 (0x0C<<24)|0x000A3C,
574 (0x0D<<24)|0xFFFFFD, 575 (0x0D<<24)|0xFFFFFD,
575 (0x0E<<24)|0x00000E, 576 (0x0E<<24)|0x00000E,
576 (0x0F<<24)|0x1ABA8F 577 (0x0F<<24)|0x1ABA8F
577 }; 578 };
578 579
579 u32 al7230_channel_data_24[][2] = 580 u32 al7230_channel_data_24[][2] =
580 { 581 {
581 {(0x00<<24)|0x003790, (0x01<<24)|0x133331}, // channe1 01 582 {(0x00<<24)|0x003790, (0x01<<24)|0x133331}, // channe1 01
582 {(0x00<<24)|0x003790, (0x01<<24)|0x1B3331}, // channe1 02 583 {(0x00<<24)|0x003790, (0x01<<24)|0x1B3331}, // channe1 02
583 {(0x00<<24)|0x003790, (0x01<<24)|0x033331}, // channe1 03 584 {(0x00<<24)|0x003790, (0x01<<24)|0x033331}, // channe1 03
584 {(0x00<<24)|0x003790, (0x01<<24)|0x0B3331}, // channe1 04 585 {(0x00<<24)|0x003790, (0x01<<24)|0x0B3331}, // channe1 04
585 {(0x00<<24)|0x0037A0, (0x01<<24)|0x133331}, // channe1 05 586 {(0x00<<24)|0x0037A0, (0x01<<24)|0x133331}, // channe1 05
586 {(0x00<<24)|0x0037A0, (0x01<<24)|0x1B3331}, // channe1 06 587 {(0x00<<24)|0x0037A0, (0x01<<24)|0x1B3331}, // channe1 06
587 {(0x00<<24)|0x0037A0, (0x01<<24)|0x033331}, // channe1 07 588 {(0x00<<24)|0x0037A0, (0x01<<24)|0x033331}, // channe1 07
588 {(0x00<<24)|0x0037A0, (0x01<<24)|0x0B3331}, // channe1 08 589 {(0x00<<24)|0x0037A0, (0x01<<24)|0x0B3331}, // channe1 08
589 {(0x00<<24)|0x0037B0, (0x01<<24)|0x133331}, // channe1 09 590 {(0x00<<24)|0x0037B0, (0x01<<24)|0x133331}, // channe1 09
590 {(0x00<<24)|0x0037B0, (0x01<<24)|0x1B3331}, // channe1 10 591 {(0x00<<24)|0x0037B0, (0x01<<24)|0x1B3331}, // channe1 10
591 {(0x00<<24)|0x0037B0, (0x01<<24)|0x033331}, // channe1 11 592 {(0x00<<24)|0x0037B0, (0x01<<24)|0x033331}, // channe1 11
592 {(0x00<<24)|0x0037B0, (0x01<<24)|0x0B3331}, // channe1 12 593 {(0x00<<24)|0x0037B0, (0x01<<24)|0x0B3331}, // channe1 12
593 {(0x00<<24)|0x0037C0, (0x01<<24)|0x133331}, // channe1 13 594 {(0x00<<24)|0x0037C0, (0x01<<24)|0x133331}, // channe1 13
594 {(0x00<<24)|0x0037C0, (0x01<<24)|0x066661} // channel 14 595 {(0x00<<24)|0x0037C0, (0x01<<24)|0x066661} // channel 14
595 }; 596 };
596 597
597 //channel independent registers: 598 //channel independent registers:
598 u32 al7230_rf_data_50[] = 599 u32 al7230_rf_data_50[] =
599 { 600 {
600 (0x00<<24)|0x0FF520, 601 (0x00<<24)|0x0FF520,
601 (0x01<<24)|0x000001, 602 (0x01<<24)|0x000001,
602 (0x02<<24)|0x451FE2, 603 (0x02<<24)|0x451FE2,
603 (0x03<<24)|0x5FDFA3, 604 (0x03<<24)|0x5FDFA3,
604 (0x04<<24)|0x6FD784, 605 (0x04<<24)|0x6FD784,
605 (0x05<<24)|0x853F55, 606 (0x05<<24)|0x853F55,
606 (0x06<<24)|0x56AF36, 607 (0x06<<24)|0x56AF36,
607 (0x07<<24)|0xCE0207, 608 (0x07<<24)|0xCE0207,
608 (0x08<<24)|0x6EBC08, 609 (0x08<<24)|0x6EBC08,
609 (0x09<<24)|0x221BB9, 610 (0x09<<24)|0x221BB9,
610 (0x0A<<24)|0xE0600A, 611 (0x0A<<24)|0xE0600A,
611 (0x0B<<24)|0x08044B, 612 (0x0B<<24)|0x08044B,
612 (0x0C<<24)|0x00143C, 613 (0x0C<<24)|0x00143C,
613 (0x0D<<24)|0xFFFFFD, 614 (0x0D<<24)|0xFFFFFD,
614 (0x0E<<24)|0x00000E, 615 (0x0E<<24)|0x00000E,
615 (0x0F<<24)|0x12BACF //5Ghz default state 616 (0x0F<<24)|0x12BACF //5Ghz default state
616 }; 617 };
617 618
618 u32 al7230_channel_data_5[][4] = 619 u32 al7230_channel_data_5[][4] =
619 { 620 {
620 //channel dependent registers: 0x00, 0x01 and 0x04 621 //channel dependent registers: 0x00, 0x01 and 0x04
621 //11J =========== 622 //11J ===========
622 {184, (0x00<<24)|0x0FF520, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 184 623 {184, (0x00<<24)|0x0FF520, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 184
623 {188, (0x00<<24)|0x0FF520, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 188 624 {188, (0x00<<24)|0x0FF520, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 188
624 {192, (0x00<<24)|0x0FF530, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 192 625 {192, (0x00<<24)|0x0FF530, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 192
625 {196, (0x00<<24)|0x0FF530, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 196 626 {196, (0x00<<24)|0x0FF530, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 196
626 {8, (0x00<<24)|0x0FF540, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 008 627 {8, (0x00<<24)|0x0FF540, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 008
627 {12, (0x00<<24)|0x0FF540, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 012 628 {12, (0x00<<24)|0x0FF540, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 012
628 {16, (0x00<<24)|0x0FF550, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 016 629 {16, (0x00<<24)|0x0FF550, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 016
629 {34, (0x00<<24)|0x0FF560, (0x01<<24)|0x055551, (0x04<<24)|0x77F784}, // channel 034 630 {34, (0x00<<24)|0x0FF560, (0x01<<24)|0x055551, (0x04<<24)|0x77F784}, // channel 034
630 {38, (0x00<<24)|0x0FF570, (0x01<<24)|0x100001, (0x04<<24)|0x77F784}, // channel 038 631 {38, (0x00<<24)|0x0FF570, (0x01<<24)|0x100001, (0x04<<24)|0x77F784}, // channel 038
631 {42, (0x00<<24)|0x0FF570, (0x01<<24)|0x1AAAA1, (0x04<<24)|0x77F784}, // channel 042 632 {42, (0x00<<24)|0x0FF570, (0x01<<24)|0x1AAAA1, (0x04<<24)|0x77F784}, // channel 042
632 {46, (0x00<<24)|0x0FF570, (0x01<<24)|0x055551, (0x04<<24)|0x77F784}, // channel 046 633 {46, (0x00<<24)|0x0FF570, (0x01<<24)|0x055551, (0x04<<24)|0x77F784}, // channel 046
633 //11 A/H ========= 634 //11 A/H =========
634 {36, (0x00<<24)|0x0FF560, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 036 635 {36, (0x00<<24)|0x0FF560, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 036
635 {40, (0x00<<24)|0x0FF570, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 040 636 {40, (0x00<<24)|0x0FF570, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 040
636 {44, (0x00<<24)|0x0FF570, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 044 637 {44, (0x00<<24)|0x0FF570, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 044
637 {48, (0x00<<24)|0x0FF570, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 048 638 {48, (0x00<<24)|0x0FF570, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 048
638 {52, (0x00<<24)|0x0FF580, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 052 639 {52, (0x00<<24)|0x0FF580, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 052
639 {56, (0x00<<24)|0x0FF580, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 056 640 {56, (0x00<<24)|0x0FF580, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 056
640 {60, (0x00<<24)|0x0FF580, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 060 641 {60, (0x00<<24)|0x0FF580, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 060
641 {64, (0x00<<24)|0x0FF590, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 064 642 {64, (0x00<<24)|0x0FF590, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 064
642 {100, (0x00<<24)|0x0FF5C0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 100 643 {100, (0x00<<24)|0x0FF5C0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 100
643 {104, (0x00<<24)|0x0FF5C0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 104 644 {104, (0x00<<24)|0x0FF5C0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 104
644 {108, (0x00<<24)|0x0FF5C0, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 108 645 {108, (0x00<<24)|0x0FF5C0, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 108
645 {112, (0x00<<24)|0x0FF5D0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 112 646 {112, (0x00<<24)|0x0FF5D0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 112
646 {116, (0x00<<24)|0x0FF5D0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 116 647 {116, (0x00<<24)|0x0FF5D0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 116
647 {120, (0x00<<24)|0x0FF5D0, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 120 648 {120, (0x00<<24)|0x0FF5D0, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 120
648 {124, (0x00<<24)|0x0FF5E0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 124 649 {124, (0x00<<24)|0x0FF5E0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 124
649 {128, (0x00<<24)|0x0FF5E0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 128 650 {128, (0x00<<24)|0x0FF5E0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 128
650 {132, (0x00<<24)|0x0FF5E0, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 132 651 {132, (0x00<<24)|0x0FF5E0, (0x01<<24)|0x0AAAA1, (0x04<<24)|0x77F784}, // channel 132
651 {136, (0x00<<24)|0x0FF5F0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 136 652 {136, (0x00<<24)|0x0FF5F0, (0x01<<24)|0x155551, (0x04<<24)|0x77F784}, // channel 136
652 {140, (0x00<<24)|0x0FF5F0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 140 653 {140, (0x00<<24)|0x0FF5F0, (0x01<<24)|0x000001, (0x04<<24)|0x67F784}, // channel 140
653 {149, (0x00<<24)|0x0FF600, (0x01<<24)|0x180001, (0x04<<24)|0x77F784}, // channel 149 654 {149, (0x00<<24)|0x0FF600, (0x01<<24)|0x180001, (0x04<<24)|0x77F784}, // channel 149
654 {153, (0x00<<24)|0x0FF600, (0x01<<24)|0x02AAA1, (0x04<<24)|0x77F784}, // channel 153 655 {153, (0x00<<24)|0x0FF600, (0x01<<24)|0x02AAA1, (0x04<<24)|0x77F784}, // channel 153
655 {157, (0x00<<24)|0x0FF600, (0x01<<24)|0x0D5551, (0x04<<24)|0x77F784}, // channel 157 656 {157, (0x00<<24)|0x0FF600, (0x01<<24)|0x0D5551, (0x04<<24)|0x77F784}, // channel 157
656 {161, (0x00<<24)|0x0FF610, (0x01<<24)|0x180001, (0x04<<24)|0x77F784}, // channel 161 657 {161, (0x00<<24)|0x0FF610, (0x01<<24)|0x180001, (0x04<<24)|0x77F784}, // channel 161
657 {165, (0x00<<24)|0x0FF610, (0x01<<24)|0x02AAA1, (0x04<<24)|0x77F784} // channel 165 658 {165, (0x00<<24)|0x0FF610, (0x01<<24)|0x02AAA1, (0x04<<24)|0x77F784} // channel 165
658 }; 659 };
659 660
660 //; RF Calibration <=== Register 0x0F 661 //; RF Calibration <=== Register 0x0F
661 //0x0F 0x1ABA8F; start from 2.4Ghz default state 662 //0x0F 0x1ABA8F; start from 2.4Ghz default state
662 //0x0F 0x9ABA8F; TXDC compensation 663 //0x0F 0x9ABA8F; TXDC compensation
663 //0x0F 0x3ABA8F; RXFIL adjustment 664 //0x0F 0x3ABA8F; RXFIL adjustment
664 //0x0F 0x1ABA8F; restore 2.4Ghz default state 665 //0x0F 0x1ABA8F; restore 2.4Ghz default state
665 666
666 //;TXVGA Mapping Table <=== Register 0x0B 667 //;TXVGA Mapping Table <=== Register 0x0B
667 u32 al7230_txvga_data[][2] = 668 u32 al7230_txvga_data[][2] =
668 { 669 {
669 {0x08040B, 0}, //TXVGA=0; 670 {0x08040B, 0}, //TXVGA=0;
670 {0x08041B, 1}, //TXVGA=1; 671 {0x08041B, 1}, //TXVGA=1;
671 {0x08042B, 2}, //TXVGA=2; 672 {0x08042B, 2}, //TXVGA=2;
672 {0x08043B, 3}, //TXVGA=3; 673 {0x08043B, 3}, //TXVGA=3;
673 {0x08044B, 4}, //TXVGA=4; 674 {0x08044B, 4}, //TXVGA=4;
674 {0x08045B, 5}, //TXVGA=5; 675 {0x08045B, 5}, //TXVGA=5;
675 {0x08046B, 6}, //TXVGA=6; 676 {0x08046B, 6}, //TXVGA=6;
676 {0x08047B, 7}, //TXVGA=7; 677 {0x08047B, 7}, //TXVGA=7;
677 {0x08048B, 8}, //TXVGA=8; 678 {0x08048B, 8}, //TXVGA=8;
678 {0x08049B, 9}, //TXVGA=9; 679 {0x08049B, 9}, //TXVGA=9;
679 {0x0804AB, 10}, //TXVGA=10; 680 {0x0804AB, 10}, //TXVGA=10;
680 {0x0804BB, 11}, //TXVGA=11; 681 {0x0804BB, 11}, //TXVGA=11;
681 {0x0804CB, 12}, //TXVGA=12; 682 {0x0804CB, 12}, //TXVGA=12;
682 {0x0804DB, 13}, //TXVGA=13; 683 {0x0804DB, 13}, //TXVGA=13;
683 {0x0804EB, 14}, //TXVGA=14; 684 {0x0804EB, 14}, //TXVGA=14;
684 {0x0804FB, 15}, //TXVGA=15; 685 {0x0804FB, 15}, //TXVGA=15;
685 {0x08050B, 16}, //TXVGA=16; 686 {0x08050B, 16}, //TXVGA=16;
686 {0x08051B, 17}, //TXVGA=17; 687 {0x08051B, 17}, //TXVGA=17;
687 {0x08052B, 18}, //TXVGA=18; 688 {0x08052B, 18}, //TXVGA=18;
688 {0x08053B, 19}, //TXVGA=19; 689 {0x08053B, 19}, //TXVGA=19;
689 {0x08054B, 20}, //TXVGA=20; 690 {0x08054B, 20}, //TXVGA=20;
690 {0x08055B, 21}, //TXVGA=21; 691 {0x08055B, 21}, //TXVGA=21;
691 {0x08056B, 22}, //TXVGA=22; 692 {0x08056B, 22}, //TXVGA=22;
692 {0x08057B, 23}, //TXVGA=23; 693 {0x08057B, 23}, //TXVGA=23;
693 {0x08058B, 24}, //TXVGA=24; 694 {0x08058B, 24}, //TXVGA=24;
694 {0x08059B, 25}, //TXVGA=25; 695 {0x08059B, 25}, //TXVGA=25;
695 {0x0805AB, 26}, //TXVGA=26; 696 {0x0805AB, 26}, //TXVGA=26;
696 {0x0805BB, 27}, //TXVGA=27; 697 {0x0805BB, 27}, //TXVGA=27;
697 {0x0805CB, 28}, //TXVGA=28; 698 {0x0805CB, 28}, //TXVGA=28;
698 {0x0805DB, 29}, //TXVGA=29; 699 {0x0805DB, 29}, //TXVGA=29;
699 {0x0805EB, 30}, //TXVGA=30; 700 {0x0805EB, 30}, //TXVGA=30;
700 {0x0805FB, 31}, //TXVGA=31; 701 {0x0805FB, 31}, //TXVGA=31;
701 {0x08060B, 32}, //TXVGA=32; 702 {0x08060B, 32}, //TXVGA=32;
702 {0x08061B, 33}, //TXVGA=33; 703 {0x08061B, 33}, //TXVGA=33;
703 {0x08062B, 34}, //TXVGA=34; 704 {0x08062B, 34}, //TXVGA=34;
704 {0x08063B, 35}, //TXVGA=35; 705 {0x08063B, 35}, //TXVGA=35;
705 {0x08064B, 36}, //TXVGA=36; 706 {0x08064B, 36}, //TXVGA=36;
706 {0x08065B, 37}, //TXVGA=37; 707 {0x08065B, 37}, //TXVGA=37;
707 {0x08066B, 38}, //TXVGA=38; 708 {0x08066B, 38}, //TXVGA=38;
708 {0x08067B, 39}, //TXVGA=39; 709 {0x08067B, 39}, //TXVGA=39;
709 {0x08068B, 40}, //TXVGA=40; 710 {0x08068B, 40}, //TXVGA=40;
710 {0x08069B, 41}, //TXVGA=41; 711 {0x08069B, 41}, //TXVGA=41;
711 {0x0806AB, 42}, //TXVGA=42; 712 {0x0806AB, 42}, //TXVGA=42;
712 {0x0806BB, 43}, //TXVGA=43; 713 {0x0806BB, 43}, //TXVGA=43;
713 {0x0806CB, 44}, //TXVGA=44; 714 {0x0806CB, 44}, //TXVGA=44;
714 {0x0806DB, 45}, //TXVGA=45; 715 {0x0806DB, 45}, //TXVGA=45;
715 {0x0806EB, 46}, //TXVGA=46; 716 {0x0806EB, 46}, //TXVGA=46;
716 {0x0806FB, 47}, //TXVGA=47; 717 {0x0806FB, 47}, //TXVGA=47;
717 {0x08070B, 48}, //TXVGA=48; 718 {0x08070B, 48}, //TXVGA=48;
718 {0x08071B, 49}, //TXVGA=49; 719 {0x08071B, 49}, //TXVGA=49;
719 {0x08072B, 50}, //TXVGA=50; 720 {0x08072B, 50}, //TXVGA=50;
720 {0x08073B, 51}, //TXVGA=51; 721 {0x08073B, 51}, //TXVGA=51;
721 {0x08074B, 52}, //TXVGA=52; 722 {0x08074B, 52}, //TXVGA=52;
722 {0x08075B, 53}, //TXVGA=53; 723 {0x08075B, 53}, //TXVGA=53;
723 {0x08076B, 54}, //TXVGA=54; 724 {0x08076B, 54}, //TXVGA=54;
724 {0x08077B, 55}, //TXVGA=55; 725 {0x08077B, 55}, //TXVGA=55;
725 {0x08078B, 56}, //TXVGA=56; 726 {0x08078B, 56}, //TXVGA=56;
726 {0x08079B, 57}, //TXVGA=57; 727 {0x08079B, 57}, //TXVGA=57;
727 {0x0807AB, 58}, //TXVGA=58; 728 {0x0807AB, 58}, //TXVGA=58;
728 {0x0807BB, 59}, //TXVGA=59; 729 {0x0807BB, 59}, //TXVGA=59;
729 {0x0807CB, 60}, //TXVGA=60; 730 {0x0807CB, 60}, //TXVGA=60;
730 {0x0807DB, 61}, //TXVGA=61; 731 {0x0807DB, 61}, //TXVGA=61;
731 {0x0807EB, 62}, //TXVGA=62; 732 {0x0807EB, 62}, //TXVGA=62;
732 {0x0807FB, 63}, //TXVGA=63; 733 {0x0807FB, 63}, //TXVGA=63;
733 }; 734 };
734 //-------------------------------- 735 //--------------------------------
735 736
736 737
737 //; W89RF242 RFIC SPI programming initial data 738 //; W89RF242 RFIC SPI programming initial data
738 //; Winbond WLAN 11g RFIC BB-SPI register -- version FA5976A rev 1.3b 739 //; Winbond WLAN 11g RFIC BB-SPI register -- version FA5976A rev 1.3b
739 //; Update Date: Ocotber 3, 2005 by PP10 Hsiang-Te Ho 740 //; Update Date: Ocotber 3, 2005 by PP10 Hsiang-Te Ho
740 //; 741 //;
741 //; Version 1.3b revision items: (Oct. 1, 2005 by HTHo) for FA5976A 742 //; Version 1.3b revision items: (Oct. 1, 2005 by HTHo) for FA5976A
742 u32 w89rf242_rf_data[] = 743 u32 w89rf242_rf_data[] =
743 { 744 {
744 (0x00<<24)|0xF86100, // 20060721 0xF86100, //; 3E184; MODA (0x00) -- Normal mode ; calibration off 745 (0x00<<24)|0xF86100, // 20060721 0xF86100, //; 3E184; MODA (0x00) -- Normal mode ; calibration off
745 (0x01<<24)|0xEFFFC2, //; 3BFFF; MODB (0x01) -- turn off RSSI, and other circuits are turned on 746 (0x01<<24)|0xEFFFC2, //; 3BFFF; MODB (0x01) -- turn off RSSI, and other circuits are turned on
746 (0x02<<24)|0x102504, //; 04094; FSET (0x02) -- default 20MHz crystal ; Icmp=1.5mA 747 (0x02<<24)|0x102504, //; 04094; FSET (0x02) -- default 20MHz crystal ; Icmp=1.5mA
747 (0x03<<24)|0x026286, //; 0098A; FCHN (0x03) -- default CH7, 2442MHz 748 (0x03<<24)|0x026286, //; 0098A; FCHN (0x03) -- default CH7, 2442MHz
748 (0x04<<24)|0x000208, // 20060612.1.a 0x0002C8, // 20050818 // 20050816 0x000388 749 (0x04<<24)|0x000208, // 20060612.1.a 0x0002C8, // 20050818 // 20050816 0x000388
749 //; 02008; FCAL (0x04) -- XTAL Freq Trim=001000 (socket board#1); FA5976AYG_v1.3C 750 //; 02008; FCAL (0x04) -- XTAL Freq Trim=001000 (socket board#1); FA5976AYG_v1.3C
750 (0x05<<24)|0x24C60A, // 20060612.1.a 0x24C58A, // 941003 0x24C48A, // 20050818.2 0x24848A, // 20050818 // 20050816 0x24C48A 751 (0x05<<24)|0x24C60A, // 20060612.1.a 0x24C58A, // 941003 0x24C48A, // 20050818.2 0x24848A, // 20050818 // 20050816 0x24C48A
751 //; 09316; GANA (0x05) -- TX VGA default (TXVGA=0x18(12)) & TXGPK=110 ; FA5976A_1.3D 752 //; 09316; GANA (0x05) -- TX VGA default (TXVGA=0x18(12)) & TXGPK=110 ; FA5976A_1.3D
752 (0x06<<24)|0x3432CC, // 941003 0x26C34C, // 20050818 0x06B40C 753 (0x06<<24)|0x3432CC, // 941003 0x26C34C, // 20050818 0x06B40C
753 //; 0D0CB; GANB (0x06) -- RXDC(DC offset) on; LNA=11; RXVGA=001011(11) ; RXFLSW=11(010001); RXGPK=00; RXGCF=00; -50dBm input 754 //; 0D0CB; GANB (0x06) -- RXDC(DC offset) on; LNA=11; RXVGA=001011(11) ; RXFLSW=11(010001); RXGPK=00; RXGCF=00; -50dBm input
754 (0x07<<24)|0x0C68CE, // 20050818.2 0x0C66CE, // 20050818 // 20050816 0x0C68CE 755 (0x07<<24)|0x0C68CE, // 20050818.2 0x0C66CE, // 20050818 // 20050816 0x0C68CE
755 //; 031A3; FILT (0x07) -- TX/RX filter with auto-tuning; TFLBW=011; RFLBW=100 756 //; 031A3; FILT (0x07) -- TX/RX filter with auto-tuning; TFLBW=011; RFLBW=100
756 (0x08<<24)|0x100010, //; 04000; TCAL (0x08) -- //for LO 757 (0x08<<24)|0x100010, //; 04000; TCAL (0x08) -- //for LO
757 (0x09<<24)|0x004012, // 20060612.1.a 0x6E4012, // 0x004012, 758 (0x09<<24)|0x004012, // 20060612.1.a 0x6E4012, // 0x004012,
758 //; 1B900; RCALA (0x09) -- FASTS=11; HPDE=01 (100nsec); SEHP=1 (select B0 pin=RXHP); RXHP=1 (Turn on RXHP function)(FA5976A_1.3C) 759 //; 1B900; RCALA (0x09) -- FASTS=11; HPDE=01 (100nsec); SEHP=1 (select B0 pin=RXHP); RXHP=1 (Turn on RXHP function)(FA5976A_1.3C)
759 (0x0A<<24)|0x704014, //; 1C100; RCALB (0x0A) 760 (0x0A<<24)|0x704014, //; 1C100; RCALB (0x0A)
760 (0x0B<<24)|0x18BDD6, // 941003 0x1805D6, // 20050818.2 0x1801D6, // 20050818 // 20050816 0x1805D6 761 (0x0B<<24)|0x18BDD6, // 941003 0x1805D6, // 20050818.2 0x1801D6, // 20050818 // 20050816 0x1805D6
761 //; 062F7; IQCAL (0x0B) -- Turn on LO phase tuner=0111 & RX-LO phase = 0111; FA5976A_1.3B (2005/09/29) 762 //; 062F7; IQCAL (0x0B) -- Turn on LO phase tuner=0111 & RX-LO phase = 0111; FA5976A_1.3B (2005/09/29)
762 (0x0C<<24)|0x575558, // 20050818.2 0x555558, // 20050818 // 20050816 0x575558 763 (0x0C<<24)|0x575558, // 20050818.2 0x555558, // 20050818 // 20050816 0x575558
763 //; 15D55 ; IBSA (0x0C) -- IFPre =11 ; TC5376A_v1.3A for corner 764 //; 15D55 ; IBSA (0x0C) -- IFPre =11 ; TC5376A_v1.3A for corner
764 (0x0D<<24)|0x55545A, // 20060612.1.a 0x55555A, 765 (0x0D<<24)|0x55545A, // 20060612.1.a 0x55555A,
765 //; 15555 ; IBSB (0x0D) 766 //; 15555 ; IBSB (0x0D)
766 (0x0E<<24)|0x5557DC, // 20060612.1.a 0x55555C, // 941003 0x5557DC, 767 (0x0E<<24)|0x5557DC, // 20060612.1.a 0x55555C, // 941003 0x5557DC,
767 //; 1555F ; IBSC (0x0E) -- IRLNA & IRLNB (PTAT & Const current)=01/01; FA5976B_1.3F (2005/11/25) 768 //; 1555F ; IBSC (0x0E) -- IRLNA & IRLNB (PTAT & Const current)=01/01; FA5976B_1.3F (2005/11/25)
768 (0x10<<24)|0x000C20, // 941003 0x000020, // 20050818 769 (0x10<<24)|0x000C20, // 941003 0x000020, // 20050818
769 //; 00030 ; TMODA (0x10) -- LNA_gain_step=0011 ; LNA=15/16dB 770 //; 00030 ; TMODA (0x10) -- LNA_gain_step=0011 ; LNA=15/16dB
770 (0x11<<24)|0x0C0022, // 941003 0x030022 // 20050818.2 0x030022 // 20050818 // 20050816 0x0C0022 771 (0x11<<24)|0x0C0022, // 941003 0x030022 // 20050818.2 0x030022 // 20050818 // 20050816 0x0C0022
771 //; 03000 ; TMODB (0x11) -- Turn ON RX-Q path Test Switch; To improve IQ path group delay (FA5976A_1.3C) 772 //; 03000 ; TMODB (0x11) -- Turn ON RX-Q path Test Switch; To improve IQ path group delay (FA5976A_1.3C)
772 (0x12<<24)|0x000024 // 20060612.1.a 0x001824 // 941003 add 773 (0x12<<24)|0x000024 // 20060612.1.a 0x001824 // 941003 add
773 //; TMODC (0x12) -- Turn OFF Tempearure sensor 774 //; TMODC (0x12) -- Turn OFF Tempearure sensor
774 }; 775 };
775 776
776 u32 w89rf242_channel_data_24[][2] = 777 u32 w89rf242_channel_data_24[][2] =
777 { 778 {
778 {(0x03<<24)|0x025B06, (0x04<<24)|0x080408}, // channe1 01 779 {(0x03<<24)|0x025B06, (0x04<<24)|0x080408}, // channe1 01
779 {(0x03<<24)|0x025C46, (0x04<<24)|0x080408}, // channe1 02 780 {(0x03<<24)|0x025C46, (0x04<<24)|0x080408}, // channe1 02
780 {(0x03<<24)|0x025D86, (0x04<<24)|0x080408}, // channe1 03 781 {(0x03<<24)|0x025D86, (0x04<<24)|0x080408}, // channe1 03
781 {(0x03<<24)|0x025EC6, (0x04<<24)|0x080408}, // channe1 04 782 {(0x03<<24)|0x025EC6, (0x04<<24)|0x080408}, // channe1 04
782 {(0x03<<24)|0x026006, (0x04<<24)|0x080408}, // channe1 05 783 {(0x03<<24)|0x026006, (0x04<<24)|0x080408}, // channe1 05
783 {(0x03<<24)|0x026146, (0x04<<24)|0x080408}, // channe1 06 784 {(0x03<<24)|0x026146, (0x04<<24)|0x080408}, // channe1 06
784 {(0x03<<24)|0x026286, (0x04<<24)|0x080408}, // channe1 07 785 {(0x03<<24)|0x026286, (0x04<<24)|0x080408}, // channe1 07
785 {(0x03<<24)|0x0263C6, (0x04<<24)|0x080408}, // channe1 08 786 {(0x03<<24)|0x0263C6, (0x04<<24)|0x080408}, // channe1 08
786 {(0x03<<24)|0x026506, (0x04<<24)|0x080408}, // channe1 09 787 {(0x03<<24)|0x026506, (0x04<<24)|0x080408}, // channe1 09
787 {(0x03<<24)|0x026646, (0x04<<24)|0x080408}, // channe1 10 788 {(0x03<<24)|0x026646, (0x04<<24)|0x080408}, // channe1 10
788 {(0x03<<24)|0x026786, (0x04<<24)|0x080408}, // channe1 11 789 {(0x03<<24)|0x026786, (0x04<<24)|0x080408}, // channe1 11
789 {(0x03<<24)|0x0268C6, (0x04<<24)|0x080408}, // channe1 12 790 {(0x03<<24)|0x0268C6, (0x04<<24)|0x080408}, // channe1 12
790 {(0x03<<24)|0x026A06, (0x04<<24)|0x080408}, // channe1 13 791 {(0x03<<24)|0x026A06, (0x04<<24)|0x080408}, // channe1 13
791 {(0x03<<24)|0x026D06, (0x04<<24)|0x080408} // channe1 14 792 {(0x03<<24)|0x026D06, (0x04<<24)|0x080408} // channe1 14
792 }; 793 };
793 794
794 u32 w89rf242_power_data_24[] = {(0x05<<24)|0x24C48A, (0x05<<24)|0x24C48A, (0x05<<24)|0x24C48A}; 795 u32 w89rf242_power_data_24[] = {(0x05<<24)|0x24C48A, (0x05<<24)|0x24C48A, (0x05<<24)|0x24C48A};
795 796
796 // 20060315.6 Enlarge for new scale 797 // 20060315.6 Enlarge for new scale
797 // 20060316.6 20060619.2.a add mapping array 798 // 20060316.6 20060619.2.a add mapping array
798 u32 w89rf242_txvga_old_mapping[][2] = 799 u32 w89rf242_txvga_old_mapping[][2] =
799 { 800 {
800 {0, 0} , // New <-> Old 801 {0, 0} , // New <-> Old
801 {1, 1} , 802 {1, 1} ,
802 {2, 2} , 803 {2, 2} ,
803 {3, 3} , 804 {3, 3} ,
804 {4, 4} , 805 {4, 4} ,
805 {6, 5} , 806 {6, 5} ,
806 {8, 6 }, 807 {8, 6 },
807 {10, 7 }, 808 {10, 7 },
808 {12, 8 }, 809 {12, 8 },
809 {14, 9 }, 810 {14, 9 },
810 {16, 10}, 811 {16, 10},
811 {18, 11}, 812 {18, 11},
812 {20, 12}, 813 {20, 12},
813 {22, 13}, 814 {22, 13},
814 {24, 14}, 815 {24, 14},
815 {26, 15}, 816 {26, 15},
816 {28, 16}, 817 {28, 16},
817 {30, 17}, 818 {30, 17},
818 {32, 18}, 819 {32, 18},
819 {34, 19}, 820 {34, 19},
820 821
821 822
822 }; 823 };
823 824
824 // 20060619.3 modify from Bruce's mail 825 // 20060619.3 modify from Bruce's mail
825 u32 w89rf242_txvga_data[][5] = 826 u32 w89rf242_txvga_data[][5] =
826 { 827 {
827 //low gain mode 828 //low gain mode
828 { (0x05<<24)|0x24C00A, 0, 0x00292315, 0x0800FEFF, 0x52523131 },// ; min gain 829 { (0x05<<24)|0x24C00A, 0, 0x00292315, 0x0800FEFF, 0x52523131 },// ; min gain
829 { (0x05<<24)|0x24C80A, 1, 0x00292315, 0x0800FEFF, 0x52523131 }, 830 { (0x05<<24)|0x24C80A, 1, 0x00292315, 0x0800FEFF, 0x52523131 },
830 { (0x05<<24)|0x24C04A, 2, 0x00292315, 0x0800FEFF, 0x52523131 },// (default) +14dBm (ANT) 831 { (0x05<<24)|0x24C04A, 2, 0x00292315, 0x0800FEFF, 0x52523131 },// (default) +14dBm (ANT)
831 { (0x05<<24)|0x24C84A, 3, 0x00292315, 0x0800FEFF, 0x52523131 }, 832 { (0x05<<24)|0x24C84A, 3, 0x00292315, 0x0800FEFF, 0x52523131 },
832 833
833 //TXVGA=0x10 834 //TXVGA=0x10
834 { (0x05<<24)|0x24C40A, 4, 0x00292315, 0x0800FEFF, 0x60603838 }, 835 { (0x05<<24)|0x24C40A, 4, 0x00292315, 0x0800FEFF, 0x60603838 },
835 { (0x05<<24)|0x24C40A, 5, 0x00262114, 0x0700FEFF, 0x65653B3B }, 836 { (0x05<<24)|0x24C40A, 5, 0x00262114, 0x0700FEFF, 0x65653B3B },
836 837
837 //TXVGA=0x11 838 //TXVGA=0x11
838 { (0x05<<24)|0x24C44A, 6, 0x00241F13, 0x0700FFFF, 0x58583333 }, 839 { (0x05<<24)|0x24C44A, 6, 0x00241F13, 0x0700FFFF, 0x58583333 },
839 { (0x05<<24)|0x24C44A, 7, 0x00292315, 0x0800FEFF, 0x5E5E3737 }, 840 { (0x05<<24)|0x24C44A, 7, 0x00292315, 0x0800FEFF, 0x5E5E3737 },
840 841
841 //TXVGA=0x12 842 //TXVGA=0x12
842 { (0x05<<24)|0x24C48A, 8, 0x00262114, 0x0700FEFF, 0x53533030 }, 843 { (0x05<<24)|0x24C48A, 8, 0x00262114, 0x0700FEFF, 0x53533030 },
843 { (0x05<<24)|0x24C48A, 9, 0x00241F13, 0x0700FFFF, 0x59593434 }, 844 { (0x05<<24)|0x24C48A, 9, 0x00241F13, 0x0700FFFF, 0x59593434 },
844 845
845 //TXVGA=0x13 846 //TXVGA=0x13
846 { (0x05<<24)|0x24C4CA, 10, 0x00292315, 0x0800FEFF, 0x52523030 }, 847 { (0x05<<24)|0x24C4CA, 10, 0x00292315, 0x0800FEFF, 0x52523030 },
847 { (0x05<<24)|0x24C4CA, 11, 0x00262114, 0x0700FEFF, 0x56563232 }, 848 { (0x05<<24)|0x24C4CA, 11, 0x00262114, 0x0700FEFF, 0x56563232 },
848 849
849 //TXVGA=0x14 850 //TXVGA=0x14
850 { (0x05<<24)|0x24C50A, 12, 0x00292315, 0x0800FEFF, 0x54543131 }, 851 { (0x05<<24)|0x24C50A, 12, 0x00292315, 0x0800FEFF, 0x54543131 },
851 { (0x05<<24)|0x24C50A, 13, 0x00262114, 0x0700FEFF, 0x58583434 }, 852 { (0x05<<24)|0x24C50A, 13, 0x00262114, 0x0700FEFF, 0x58583434 },
852 853
853 //TXVGA=0x15 854 //TXVGA=0x15
854 { (0x05<<24)|0x24C54A, 14, 0x00292315, 0x0800FEFF, 0x54543131 }, 855 { (0x05<<24)|0x24C54A, 14, 0x00292315, 0x0800FEFF, 0x54543131 },
855 { (0x05<<24)|0x24C54A, 15, 0x00262114, 0x0700FEFF, 0x59593434 }, 856 { (0x05<<24)|0x24C54A, 15, 0x00262114, 0x0700FEFF, 0x59593434 },
856 857
857 //TXVGA=0x16 858 //TXVGA=0x16
858 { (0x05<<24)|0x24C58A, 16, 0x00292315, 0x0800FEFF, 0x55553131 }, 859 { (0x05<<24)|0x24C58A, 16, 0x00292315, 0x0800FEFF, 0x55553131 },
859 { (0x05<<24)|0x24C58A, 17, 0x00292315, 0x0800FEFF, 0x5B5B3535 }, 860 { (0x05<<24)|0x24C58A, 17, 0x00292315, 0x0800FEFF, 0x5B5B3535 },
860 861
861 //TXVGA=0x17 862 //TXVGA=0x17
862 { (0x05<<24)|0x24C5CA, 18, 0x00262114, 0x0700FEFF, 0x51512F2F }, 863 { (0x05<<24)|0x24C5CA, 18, 0x00262114, 0x0700FEFF, 0x51512F2F },
863 { (0x05<<24)|0x24C5CA, 19, 0x00241F13, 0x0700FFFF, 0x55553131 }, 864 { (0x05<<24)|0x24C5CA, 19, 0x00241F13, 0x0700FFFF, 0x55553131 },
864 865
865 //TXVGA=0x18 866 //TXVGA=0x18
866 { (0x05<<24)|0x24C60A, 20, 0x00292315, 0x0800FEFF, 0x4F4F2E2E }, 867 { (0x05<<24)|0x24C60A, 20, 0x00292315, 0x0800FEFF, 0x4F4F2E2E },
867 { (0x05<<24)|0x24C60A, 21, 0x00262114, 0x0700FEFF, 0x53533030 }, 868 { (0x05<<24)|0x24C60A, 21, 0x00262114, 0x0700FEFF, 0x53533030 },
868 869
869 //TXVGA=0x19 870 //TXVGA=0x19
870 { (0x05<<24)|0x24C64A, 22, 0x00292315, 0x0800FEFF, 0x4E4E2D2D }, 871 { (0x05<<24)|0x24C64A, 22, 0x00292315, 0x0800FEFF, 0x4E4E2D2D },
871 { (0x05<<24)|0x24C64A, 23, 0x00262114, 0x0700FEFF, 0x53533030 }, 872 { (0x05<<24)|0x24C64A, 23, 0x00262114, 0x0700FEFF, 0x53533030 },
872 873
873 //TXVGA=0x1A 874 //TXVGA=0x1A
874 { (0x05<<24)|0x24C68A, 24, 0x00292315, 0x0800FEFF, 0x50502E2E }, 875 { (0x05<<24)|0x24C68A, 24, 0x00292315, 0x0800FEFF, 0x50502E2E },
875 { (0x05<<24)|0x24C68A, 25, 0x00262114, 0x0700FEFF, 0x55553131 }, 876 { (0x05<<24)|0x24C68A, 25, 0x00262114, 0x0700FEFF, 0x55553131 },
876 877
877 //TXVGA=0x1B 878 //TXVGA=0x1B
878 { (0x05<<24)|0x24C6CA, 26, 0x00262114, 0x0700FEFF, 0x53533030 }, 879 { (0x05<<24)|0x24C6CA, 26, 0x00262114, 0x0700FEFF, 0x53533030 },
879 { (0x05<<24)|0x24C6CA, 27, 0x00292315, 0x0800FEFF, 0x5A5A3434 }, 880 { (0x05<<24)|0x24C6CA, 27, 0x00292315, 0x0800FEFF, 0x5A5A3434 },
880 881
881 //TXVGA=0x1C 882 //TXVGA=0x1C
882 { (0x05<<24)|0x24C70A, 28, 0x00292315, 0x0800FEFF, 0x55553131 }, 883 { (0x05<<24)|0x24C70A, 28, 0x00292315, 0x0800FEFF, 0x55553131 },
883 { (0x05<<24)|0x24C70A, 29, 0x00292315, 0x0800FEFF, 0x5D5D3636 }, 884 { (0x05<<24)|0x24C70A, 29, 0x00292315, 0x0800FEFF, 0x5D5D3636 },
884 885
885 //TXVGA=0x1D 886 //TXVGA=0x1D
886 { (0x05<<24)|0x24C74A, 30, 0x00292315, 0x0800FEFF, 0x5F5F3737 }, 887 { (0x05<<24)|0x24C74A, 30, 0x00292315, 0x0800FEFF, 0x5F5F3737 },
887 { (0x05<<24)|0x24C74A, 31, 0x00262114, 0x0700FEFF, 0x65653B3B }, 888 { (0x05<<24)|0x24C74A, 31, 0x00262114, 0x0700FEFF, 0x65653B3B },
888 889
889 //TXVGA=0x1E 890 //TXVGA=0x1E
890 { (0x05<<24)|0x24C78A, 32, 0x00292315, 0x0800FEFF, 0x66663B3B }, 891 { (0x05<<24)|0x24C78A, 32, 0x00292315, 0x0800FEFF, 0x66663B3B },
891 { (0x05<<24)|0x24C78A, 33, 0x00262114, 0x0700FEFF, 0x70704141 }, 892 { (0x05<<24)|0x24C78A, 33, 0x00262114, 0x0700FEFF, 0x70704141 },
892 893
893 //TXVGA=0x1F 894 //TXVGA=0x1F
894 { (0x05<<24)|0x24C7CA, 34, 0x00292315, 0x0800FEFF, 0x72724242 } 895 { (0x05<<24)|0x24C7CA, 34, 0x00292315, 0x0800FEFF, 0x72724242 }
895 }; 896 };
896 897
897 /////////////////////////////////////////////////////////////////////////////////////////////////// 898 ///////////////////////////////////////////////////////////////////////////////////////////////////
898 /////////////////////////////////////////////////////////////////////////////////////////////////// 899 ///////////////////////////////////////////////////////////////////////////////////////////////////
899 /////////////////////////////////////////////////////////////////////////////////////////////////// 900 ///////////////////////////////////////////////////////////////////////////////////////////////////
900 901
901 902
902 903
903 //============================================================================================================= 904 //=============================================================================================================
904 // Uxx_ReadEthernetAddress -- 905 // Uxx_ReadEthernetAddress --
905 // 906 //
906 // Routine Description: 907 // Routine Description:
907 // Reads in the Ethernet address from the IC. 908 // Reads in the Ethernet address from the IC.
908 // 909 //
909 // Arguments: 910 // Arguments:
910 // pHwData - The pHwData structure 911 // pHwData - The pHwData structure
911 // 912 //
912 // Return Value: 913 // Return Value:
913 // 914 //
914 // The address is stored in EthernetIDAddr. 915 // The address is stored in EthernetIDAddr.
915 //============================================================================================================= 916 //=============================================================================================================
916 void 917 void
917 Uxx_ReadEthernetAddress( phw_data_t pHwData ) 918 Uxx_ReadEthernetAddress( phw_data_t pHwData )
918 { 919 {
919 u32 ltmp; 920 u32 ltmp;
920 921
921 // Reading Ethernet address from EEPROM and set into hardware due to MAC address maybe change. 922 // Reading Ethernet address from EEPROM and set into hardware due to MAC address maybe change.
922 // Only unplug and plug again can make hardware read EEPROM again. 20060727 923 // Only unplug and plug again can make hardware read EEPROM again. 20060727
923 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08000000 ); // Start EEPROM access + Read + address(0x0d) 924 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08000000 ); // Start EEPROM access + Read + address(0x0d)
924 Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp ); 925 Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp );
925 *(u16 *)pHwData->PermanentMacAddress = cpu_to_le16((u16)ltmp); //20060926 anson's endian 926 *(u16 *)pHwData->PermanentMacAddress = cpu_to_le16((u16)ltmp); //20060926 anson's endian
926 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08010000 ); // Start EEPROM access + Read + address(0x0d) 927 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08010000 ); // Start EEPROM access + Read + address(0x0d)
927 Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp ); 928 Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp );
928 *(u16 *)(pHwData->PermanentMacAddress + 2) = cpu_to_le16((u16)ltmp); //20060926 anson's endian 929 *(u16 *)(pHwData->PermanentMacAddress + 2) = cpu_to_le16((u16)ltmp); //20060926 anson's endian
929 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08020000 ); // Start EEPROM access + Read + address(0x0d) 930 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08020000 ); // Start EEPROM access + Read + address(0x0d)
930 Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp ); 931 Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp );
931 *(u16 *)(pHwData->PermanentMacAddress + 4) = cpu_to_le16((u16)ltmp); //20060926 anson's endian 932 *(u16 *)(pHwData->PermanentMacAddress + 4) = cpu_to_le16((u16)ltmp); //20060926 anson's endian
932 *(u16 *)(pHwData->PermanentMacAddress + 6) = 0; 933 *(u16 *)(pHwData->PermanentMacAddress + 6) = 0;
933 Wb35Reg_WriteSync( pHwData, 0x03e8, cpu_to_le32(*(u32 *)pHwData->PermanentMacAddress) ); //20060926 anson's endian 934 Wb35Reg_WriteSync( pHwData, 0x03e8, cpu_to_le32(*(u32 *)pHwData->PermanentMacAddress) ); //20060926 anson's endian
934 Wb35Reg_WriteSync( pHwData, 0x03ec, cpu_to_le32(*(u32 *)(pHwData->PermanentMacAddress+4)) ); //20060926 anson's endian 935 Wb35Reg_WriteSync( pHwData, 0x03ec, cpu_to_le32(*(u32 *)(pHwData->PermanentMacAddress+4)) ); //20060926 anson's endian
935 } 936 }
936 937
937 938
938 //=============================================================================================================== 939 //===============================================================================================================
939 // CardGetMulticastBit -- 940 // CardGetMulticastBit --
940 // Description: 941 // Description:
941 // For a given multicast address, returns the byte and bit in the card multicast registers that it hashes to. 942 // For a given multicast address, returns the byte and bit in the card multicast registers that it hashes to.
942 // Calls CardComputeCrc() to determine the CRC value. 943 // Calls CardComputeCrc() to determine the CRC value.
943 // Arguments: 944 // Arguments:
944 // Address - the address 945 // Address - the address
945 // Byte - the byte that it hashes to 946 // Byte - the byte that it hashes to
946 // Value - will have a 1 in the relevant bit 947 // Value - will have a 1 in the relevant bit
947 // Return Value: 948 // Return Value:
948 // None. 949 // None.
949 //============================================================================================================== 950 //==============================================================================================================
950 void CardGetMulticastBit( u8 Address[ETH_LENGTH_OF_ADDRESS], 951 void CardGetMulticastBit( u8 Address[ETH_LENGTH_OF_ADDRESS],
951 u8 *Byte, u8 *Value ) 952 u8 *Byte, u8 *Value )
952 { 953 {
953 u32 Crc; 954 u32 Crc;
954 u32 BitNumber; 955 u32 BitNumber;
955 956
956 // First compute the CRC. 957 // First compute the CRC.
957 Crc = CardComputeCrc(Address, ETH_LENGTH_OF_ADDRESS); 958 Crc = CardComputeCrc(Address, ETH_LENGTH_OF_ADDRESS);
958 959
959 // The computed CRC is bit0~31 from left to right 960 // The computed CRC is bit0~31 from left to right
960 //At first we should do right shift 25bits, and read 7bits by using '&', 2^7=128 961 //At first we should do right shift 25bits, and read 7bits by using '&', 2^7=128
961 BitNumber = (u32) ((Crc >> 26) & 0x3f); 962 BitNumber = (u32) ((Crc >> 26) & 0x3f);
962 963
963 *Byte = (u8) (BitNumber >> 3);// 900514 original (BitNumber / 8) 964 *Byte = (u8) (BitNumber >> 3);// 900514 original (BitNumber / 8)
964 *Value = (u8) ((u8)1 << (BitNumber % 8)); 965 *Value = (u8) ((u8)1 << (BitNumber % 8));
965 } 966 }
966 967
967 void Uxx_power_on_procedure( phw_data_t pHwData ) 968 void Uxx_power_on_procedure( phw_data_t pHwData )
968 { 969 {
969 u32 ltmp, loop; 970 u32 ltmp, loop;
970 971
971 if( pHwData->phy_type <= RF_MAXIM_V1 ) 972 if( pHwData->phy_type <= RF_MAXIM_V1 )
972 Wb35Reg_WriteSync( pHwData, 0x03d4, 0xffffff38 ); 973 Wb35Reg_WriteSync( pHwData, 0x03d4, 0xffffff38 );
973 else 974 else
974 { 975 {
975 Wb35Reg_WriteSync( pHwData, 0x03f4, 0xFF5807FF );// 20060721 For NEW IC 0xFF5807FF 976 Wb35Reg_WriteSync( pHwData, 0x03f4, 0xFF5807FF );// 20060721 For NEW IC 0xFF5807FF
976 977
977 // 20060511.1 Fix the following 4 steps for Rx of RF 2230 initial fail 978 // 20060511.1 Fix the following 4 steps for Rx of RF 2230 initial fail
978 Wb35Reg_WriteSync( pHwData, 0x03d4, 0x80 );// regulator on only 979 Wb35Reg_WriteSync( pHwData, 0x03d4, 0x80 );// regulator on only
979 msleep(10); // Modify 20051221.1.b 980 msleep(10); // Modify 20051221.1.b
980 Wb35Reg_WriteSync( pHwData, 0x03d4, 0xb8 );// REG_ON RF_RSTN on, and 981 Wb35Reg_WriteSync( pHwData, 0x03d4, 0xb8 );// REG_ON RF_RSTN on, and
981 msleep(10); // Modify 20051221.1.b 982 msleep(10); // Modify 20051221.1.b
982 983
983 ltmp = 0x4968; 984 ltmp = 0x4968;
984 if( (pHwData->phy_type == RF_WB_242) || 985 if( (pHwData->phy_type == RF_WB_242) ||
985 (RF_WB_242_1 == pHwData->phy_type) ) // 20060619.5 Add 986 (RF_WB_242_1 == pHwData->phy_type) ) // 20060619.5 Add
986 ltmp = 0x4468; 987 ltmp = 0x4468;
987 Wb35Reg_WriteSync( pHwData, 0x03d0, ltmp ); 988 Wb35Reg_WriteSync( pHwData, 0x03d0, ltmp );
988 989
989 Wb35Reg_WriteSync( pHwData, 0x03d4, 0xa0 );// PLL_PD REF_PD set to 0 990 Wb35Reg_WriteSync( pHwData, 0x03d4, 0xa0 );// PLL_PD REF_PD set to 0
990 991
991 msleep(20); // Modify 20051221.1.b 992 msleep(20); // Modify 20051221.1.b
992 Wb35Reg_ReadSync( pHwData, 0x03d0, &ltmp ); 993 Wb35Reg_ReadSync( pHwData, 0x03d0, &ltmp );
993 loop = 500; // Wait for 5 second 20061101 994 loop = 500; // Wait for 5 second 20061101
994 while( !(ltmp & 0x20) && loop-- ) 995 while( !(ltmp & 0x20) && loop-- )
995 { 996 {
996 msleep(10); // Modify 20051221.1.b 997 msleep(10); // Modify 20051221.1.b
997 if( !Wb35Reg_ReadSync( pHwData, 0x03d0, &ltmp ) ) 998 if( !Wb35Reg_ReadSync( pHwData, 0x03d0, &ltmp ) )
998 break; 999 break;
999 } 1000 }
1000 1001
1001 Wb35Reg_WriteSync( pHwData, 0x03d4, 0xe0 );// MLK_EN 1002 Wb35Reg_WriteSync( pHwData, 0x03d4, 0xe0 );// MLK_EN
1002 } 1003 }
1003 1004
1004 Wb35Reg_WriteSync( pHwData, 0x03b0, 1 );// Reset hardware first 1005 Wb35Reg_WriteSync( pHwData, 0x03b0, 1 );// Reset hardware first
1005 msleep(10); // Add this 20051221.1.b 1006 msleep(10); // Add this 20051221.1.b
1006 1007
1007 // Set burst write delay 1008 // Set burst write delay
1008 Wb35Reg_WriteSync( pHwData, 0x03f8, 0x7ff ); 1009 Wb35Reg_WriteSync( pHwData, 0x03f8, 0x7ff );
1009 } 1010 }
1010 1011
1011 void Set_ChanIndep_RfData_al7230_24( phw_data_t pHwData, u32 *pltmp ,char number) 1012 void Set_ChanIndep_RfData_al7230_24( phw_data_t pHwData, u32 *pltmp ,char number)
1012 { 1013 {
1013 u8 i; 1014 u8 i;
1014 1015
1015 for( i=0; i<number; i++ ) 1016 for( i=0; i<number; i++ )
1016 { 1017 {
1017 pHwData->phy_para[i] = al7230_rf_data_24[i]; 1018 pHwData->phy_para[i] = al7230_rf_data_24[i];
1018 pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_rf_data_24[i]&0xffffff); 1019 pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_rf_data_24[i]&0xffffff);
1019 } 1020 }
1020 } 1021 }
1021 1022
1022 void Set_ChanIndep_RfData_al7230_50( phw_data_t pHwData, u32 *pltmp, char number) 1023 void Set_ChanIndep_RfData_al7230_50( phw_data_t pHwData, u32 *pltmp, char number)
1023 { 1024 {
1024 u8 i; 1025 u8 i;
1025 1026
1026 for( i=0; i<number; i++ ) 1027 for( i=0; i<number; i++ )
1027 { 1028 {
1028 pHwData->phy_para[i] = al7230_rf_data_50[i]; 1029 pHwData->phy_para[i] = al7230_rf_data_50[i];
1029 pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_rf_data_50[i]&0xffffff); 1030 pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_rf_data_50[i]&0xffffff);
1030 } 1031 }
1031 } 1032 }
1032 1033
1033 1034
1034 //============================================================================================================= 1035 //=============================================================================================================
1035 // RFSynthesizer_initial -- 1036 // RFSynthesizer_initial --
1036 //============================================================================================================= 1037 //=============================================================================================================
1037 void 1038 void
1038 RFSynthesizer_initial(phw_data_t pHwData) 1039 RFSynthesizer_initial(phw_data_t pHwData)
1039 { 1040 {
1040 u32 altmp[32]; 1041 u32 altmp[32];
1041 u32 * pltmp = altmp; 1042 u32 * pltmp = altmp;
1042 u32 ltmp; 1043 u32 ltmp;
1043 u8 number=0x00; // The number of register vale 1044 u8 number=0x00; // The number of register vale
1044 u8 i; 1045 u8 i;
1045 1046
1046 // 1047 //
1047 // bit[31] SPI Enable. 1048 // bit[31] SPI Enable.
1048 // 1=perform synthesizer program operation. This bit will 1049 // 1=perform synthesizer program operation. This bit will
1049 // cleared automatically after the operation is completed. 1050 // cleared automatically after the operation is completed.
1050 // bit[30] SPI R/W Control 1051 // bit[30] SPI R/W Control
1051 // 0=write, 1=read 1052 // 0=write, 1=read
1052 // bit[29:24] SPI Data Format Length 1053 // bit[29:24] SPI Data Format Length
1053 // bit[17:4 ] RF Data bits. 1054 // bit[17:4 ] RF Data bits.
1054 // bit[3 :0 ] RF address. 1055 // bit[3 :0 ] RF address.
1055 switch( pHwData->phy_type ) 1056 switch( pHwData->phy_type )
1056 { 1057 {
1057 case RF_MAXIM_2825: 1058 case RF_MAXIM_2825:
1058 case RF_MAXIM_V1: // 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331) 1059 case RF_MAXIM_V1: // 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331)
1059 number = sizeof(max2825_rf_data)/sizeof(max2825_rf_data[0]); 1060 number = sizeof(max2825_rf_data)/sizeof(max2825_rf_data[0]);
1060 for( i=0; i<number; i++ ) 1061 for( i=0; i<number; i++ )
1061 { 1062 {
1062 pHwData->phy_para[i] = max2825_rf_data[i];// Backup Rf parameter 1063 pHwData->phy_para[i] = max2825_rf_data[i];// Backup Rf parameter
1063 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2825_rf_data[i], 18); 1064 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2825_rf_data[i], 18);
1064 } 1065 }
1065 break; 1066 break;
1066 1067
1067 case RF_MAXIM_2827: 1068 case RF_MAXIM_2827:
1068 number = sizeof(max2827_rf_data)/sizeof(max2827_rf_data[0]); 1069 number = sizeof(max2827_rf_data)/sizeof(max2827_rf_data[0]);
1069 for( i=0; i<number; i++ ) 1070 for( i=0; i<number; i++ )
1070 { 1071 {
1071 pHwData->phy_para[i] = max2827_rf_data[i]; 1072 pHwData->phy_para[i] = max2827_rf_data[i];
1072 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_rf_data[i], 18); 1073 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_rf_data[i], 18);
1073 } 1074 }
1074 break; 1075 break;
1075 1076
1076 case RF_MAXIM_2828: 1077 case RF_MAXIM_2828:
1077 number = sizeof(max2828_rf_data)/sizeof(max2828_rf_data[0]); 1078 number = sizeof(max2828_rf_data)/sizeof(max2828_rf_data[0]);
1078 for( i=0; i<number; i++ ) 1079 for( i=0; i<number; i++ )
1079 { 1080 {
1080 pHwData->phy_para[i] = max2828_rf_data[i]; 1081 pHwData->phy_para[i] = max2828_rf_data[i];
1081 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_rf_data[i], 18); 1082 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_rf_data[i], 18);
1082 } 1083 }
1083 break; 1084 break;
1084 1085
1085 case RF_MAXIM_2829: 1086 case RF_MAXIM_2829:
1086 number = sizeof(max2829_rf_data)/sizeof(max2829_rf_data[0]); 1087 number = sizeof(max2829_rf_data)/sizeof(max2829_rf_data[0]);
1087 for( i=0; i<number; i++ ) 1088 for( i=0; i<number; i++ )
1088 { 1089 {
1089 pHwData->phy_para[i] = max2829_rf_data[i]; 1090 pHwData->phy_para[i] = max2829_rf_data[i];
1090 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2829_rf_data[i], 18); 1091 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2829_rf_data[i], 18);
1091 } 1092 }
1092 break; 1093 break;
1093 1094
1094 case RF_AIROHA_2230: 1095 case RF_AIROHA_2230:
1095 number = sizeof(al2230_rf_data)/sizeof(al2230_rf_data[0]); 1096 number = sizeof(al2230_rf_data)/sizeof(al2230_rf_data[0]);
1096 for( i=0; i<number; i++ ) 1097 for( i=0; i<number; i++ )
1097 { 1098 {
1098 pHwData->phy_para[i] = al2230_rf_data[i]; 1099 pHwData->phy_para[i] = al2230_rf_data[i];
1099 pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_rf_data[i], 20); 1100 pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_rf_data[i], 20);
1100 } 1101 }
1101 break; 1102 break;
1102 1103
1103 case RF_AIROHA_2230S: 1104 case RF_AIROHA_2230S:
1104 number = sizeof(al2230s_rf_data)/sizeof(al2230s_rf_data[0]); 1105 number = sizeof(al2230s_rf_data)/sizeof(al2230s_rf_data[0]);
1105 for( i=0; i<number; i++ ) 1106 for( i=0; i<number; i++ )
1106 { 1107 {
1107 pHwData->phy_para[i] = al2230s_rf_data[i]; 1108 pHwData->phy_para[i] = al2230s_rf_data[i];
1108 pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230s_rf_data[i], 20); 1109 pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230s_rf_data[i], 20);
1109 } 1110 }
1110 break; 1111 break;
1111 1112
1112 case RF_AIROHA_7230: 1113 case RF_AIROHA_7230:
1113 1114
1114 //Start to fill RF parameters, PLL_ON should be pulled low. 1115 //Start to fill RF parameters, PLL_ON should be pulled low.
1115 Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000000 ); 1116 Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000000 );
1116 #ifdef _PE_STATE_DUMP_ 1117 #ifdef _PE_STATE_DUMP_
1117 WBDEBUG(("* PLL_ON low\n")); 1118 WBDEBUG(("* PLL_ON low\n"));
1118 #endif 1119 #endif
1119 1120
1120 number = sizeof(al7230_rf_data_24)/sizeof(al7230_rf_data_24[0]); 1121 number = sizeof(al7230_rf_data_24)/sizeof(al7230_rf_data_24[0]);
1121 Set_ChanIndep_RfData_al7230_24(pHwData, pltmp, number); 1122 Set_ChanIndep_RfData_al7230_24(pHwData, pltmp, number);
1122 break; 1123 break;
1123 1124
1124 case RF_WB_242: 1125 case RF_WB_242:
1125 case RF_WB_242_1: // 20060619.5 Add 1126 case RF_WB_242_1: // 20060619.5 Add
1126 number = sizeof(w89rf242_rf_data)/sizeof(w89rf242_rf_data[0]); 1127 number = sizeof(w89rf242_rf_data)/sizeof(w89rf242_rf_data[0]);
1127 for( i=0; i<number; i++ ) 1128 for( i=0; i<number; i++ )
1128 { 1129 {
1129 ltmp = w89rf242_rf_data[i]; 1130 ltmp = w89rf242_rf_data[i];
1130 if( i == 4 ) // Update the VCO trim from EEPROM 1131 if( i == 4 ) // Update the VCO trim from EEPROM
1131 { 1132 {
1132 ltmp &= ~0xff0; // Mask bit4 ~bit11 1133 ltmp &= ~0xff0; // Mask bit4 ~bit11
1133 ltmp |= pHwData->VCO_trim<<4; 1134 ltmp |= pHwData->VCO_trim<<4;
1134 } 1135 }
1135 1136
1136 pHwData->phy_para[i] = ltmp; 1137 pHwData->phy_para[i] = ltmp;
1137 pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( ltmp, 24); 1138 pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( ltmp, 24);
1138 } 1139 }
1139 break; 1140 break;
1140 } 1141 }
1141 1142
1142 pHwData->phy_number = number; 1143 pHwData->phy_number = number;
1143 1144
1144 // The 16 is the maximum capability of hardware. Here use 12 1145 // The 16 is the maximum capability of hardware. Here use 12
1145 if( number > 12 ) { 1146 if( number > 12 ) {
1146 //Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 12, NO_INCREMENT ); 1147 //Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 12, NO_INCREMENT );
1147 for( i=0; i<12; i++ ) // For Al2230 1148 for( i=0; i<12; i++ ) // For Al2230
1148 Wb35Reg_WriteSync( pHwData, 0x0864, pltmp[i] ); 1149 Wb35Reg_WriteSync( pHwData, 0x0864, pltmp[i] );
1149 1150
1150 pltmp += 12; 1151 pltmp += 12;
1151 number -= 12; 1152 number -= 12;
1152 } 1153 }
1153 1154
1154 // Write to register. number must less and equal than 16 1155 // Write to register. number must less and equal than 16
1155 for( i=0; i<number; i++ ) 1156 for( i=0; i<number; i++ )
1156 Wb35Reg_WriteSync( pHwData, 0x864, pltmp[i] ); 1157 Wb35Reg_WriteSync( pHwData, 0x864, pltmp[i] );
1157 1158
1158 // 20060630.1 Calibration only 1 time 1159 // 20060630.1 Calibration only 1 time
1159 if( pHwData->CalOneTime ) 1160 if( pHwData->CalOneTime )
1160 return; 1161 return;
1161 pHwData->CalOneTime = 1; 1162 pHwData->CalOneTime = 1;
1162 1163
1163 switch( pHwData->phy_type ) 1164 switch( pHwData->phy_type )
1164 { 1165 {
1165 case RF_AIROHA_2230: 1166 case RF_AIROHA_2230:
1166 1167
1167 // 20060511.1 --- Modifying the follow step for Rx issue----------------- 1168 // 20060511.1 --- Modifying the follow step for Rx issue-----------------
1168 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x07<<20)|0xE168E, 20); 1169 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x07<<20)|0xE168E, 20);
1169 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1170 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1170 msleep(10); 1171 msleep(10);
1171 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_rf_data[7], 20); 1172 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_rf_data[7], 20);
1172 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1173 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1173 msleep(10); 1174 msleep(10);
1174 1175
1175 case RF_AIROHA_2230S: // 20060420 Add this 1176 case RF_AIROHA_2230S: // 20060420 Add this
1176 1177
1177 // 20060511.1 --- Modifying the follow step for Rx issue----------------- 1178 // 20060511.1 --- Modifying the follow step for Rx issue-----------------
1178 Wb35Reg_WriteSync( pHwData, 0x03d4, 0x80 );// regulator on only 1179 Wb35Reg_WriteSync( pHwData, 0x03d4, 0x80 );// regulator on only
1179 msleep(10); // Modify 20051221.1.b 1180 msleep(10); // Modify 20051221.1.b
1180 1181
1181 Wb35Reg_WriteSync( pHwData, 0x03d4, 0xa0 );// PLL_PD REF_PD set to 0 1182 Wb35Reg_WriteSync( pHwData, 0x03d4, 0xa0 );// PLL_PD REF_PD set to 0
1182 msleep(10); // Modify 20051221.1.b 1183 msleep(10); // Modify 20051221.1.b
1183 1184
1184 Wb35Reg_WriteSync( pHwData, 0x03d4, 0xe0 );// MLK_EN 1185 Wb35Reg_WriteSync( pHwData, 0x03d4, 0xe0 );// MLK_EN
1185 Wb35Reg_WriteSync( pHwData, 0x03b0, 1 );// Reset hardware first 1186 Wb35Reg_WriteSync( pHwData, 0x03b0, 1 );// Reset hardware first
1186 msleep(10); // Add this 20051221.1.b 1187 msleep(10); // Add this 20051221.1.b
1187 //------------------------------------------------------------------------ 1188 //------------------------------------------------------------------------
1188 1189
1189 // The follow code doesn't use the burst-write mode 1190 // The follow code doesn't use the burst-write mode
1190 //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01A0); //Raise Initial Setting 1191 //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01A0); //Raise Initial Setting
1191 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01A0, 20); 1192 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01A0, 20);
1192 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1193 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1193 1194
1194 ltmp = pHwData->reg.BB5C & 0xfffff000; 1195 ltmp = pHwData->reg.BB5C & 0xfffff000;
1195 Wb35Reg_WriteSync( pHwData, 0x105c, ltmp ); 1196 Wb35Reg_WriteSync( pHwData, 0x105c, ltmp );
1196 pHwData->reg.BB50 |= 0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START);//20060315.1 modify 1197 pHwData->reg.BB50 |= 0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START);//20060315.1 modify
1197 Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50); 1198 Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50);
1198 msleep(5); 1199 msleep(5);
1199 1200
1200 //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01B0); //Activate Filter Cal. 1201 //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01B0); //Activate Filter Cal.
1201 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01B0, 20); 1202 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01B0, 20);
1202 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1203 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1203 msleep(5); 1204 msleep(5);
1204 1205
1205 //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01e0); //Activate TX DCC 1206 //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01e0); //Activate TX DCC
1206 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01E0, 20); 1207 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01E0, 20);
1207 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1208 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1208 msleep(5); 1209 msleep(5);
1209 1210
1210 //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01A0); //Resotre Initial Setting 1211 //phy_set_rf_data(phw_data, 0x0F, (0x0F<<20) | 0xF01A0); //Resotre Initial Setting
1211 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01A0, 20); 1212 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( (0x0F<<20) | 0xF01A0, 20);
1212 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1213 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1213 1214
1214 // //Force TXI(Q)P(N) to normal control 1215 // //Force TXI(Q)P(N) to normal control
1215 Wb35Reg_WriteSync( pHwData, 0x105c, pHwData->reg.BB5C ); 1216 Wb35Reg_WriteSync( pHwData, 0x105c, pHwData->reg.BB5C );
1216 pHwData->reg.BB50 &= ~0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START); 1217 pHwData->reg.BB50 &= ~0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START);
1217 Wb35Reg_WriteSync( pHwData, 0x1050, pHwData->reg.BB50); 1218 Wb35Reg_WriteSync( pHwData, 0x1050, pHwData->reg.BB50);
1218 break; 1219 break;
1219 1220
1220 case RF_AIROHA_7230: 1221 case RF_AIROHA_7230:
1221 1222
1222 //RF parameters have filled completely, PLL_ON should be 1223 //RF parameters have filled completely, PLL_ON should be
1223 //pulled high 1224 //pulled high
1224 Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000080 ); 1225 Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000080 );
1225 #ifdef _PE_STATE_DUMP_ 1226 #ifdef _PE_STATE_DUMP_
1226 WBDEBUG(("* PLL_ON high\n")); 1227 WBDEBUG(("* PLL_ON high\n"));
1227 #endif 1228 #endif
1228 1229
1229 //2.4GHz 1230 //2.4GHz
1230 //ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x1ABA8F; 1231 //ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x1ABA8F;
1231 //Wb35Reg_WriteSync pHwData, 0x0864, ltmp ); 1232 //Wb35Reg_WriteSync pHwData, 0x0864, ltmp );
1232 //msleep(1); // Sleep 1 ms 1233 //msleep(1); // Sleep 1 ms
1233 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F; 1234 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F;
1234 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1235 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1235 msleep(5); 1236 msleep(5);
1236 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F; 1237 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F;
1237 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1238 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1238 msleep(5); 1239 msleep(5);
1239 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x1ABA8F; 1240 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x1ABA8F;
1240 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1241 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1241 msleep(5); 1242 msleep(5);
1242 1243
1243 //5GHz 1244 //5GHz
1244 Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000000 ); 1245 Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000000 );
1245 #ifdef _PE_STATE_DUMP_ 1246 #ifdef _PE_STATE_DUMP_
1246 WBDEBUG(("* PLL_ON low\n")); 1247 WBDEBUG(("* PLL_ON low\n"));
1247 #endif 1248 #endif
1248 1249
1249 number = sizeof(al7230_rf_data_50)/sizeof(al7230_rf_data_50[0]); 1250 number = sizeof(al7230_rf_data_50)/sizeof(al7230_rf_data_50[0]);
1250 Set_ChanIndep_RfData_al7230_50(pHwData, pltmp, number); 1251 Set_ChanIndep_RfData_al7230_50(pHwData, pltmp, number);
1251 // Write to register. number must less and equal than 16 1252 // Write to register. number must less and equal than 16
1252 for( i=0; i<number; i++ ) 1253 for( i=0; i<number; i++ )
1253 Wb35Reg_WriteSync( pHwData, 0x0864, pltmp[i] ); 1254 Wb35Reg_WriteSync( pHwData, 0x0864, pltmp[i] );
1254 msleep(5); 1255 msleep(5);
1255 1256
1256 Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000080 ); 1257 Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000080 );
1257 #ifdef _PE_STATE_DUMP_ 1258 #ifdef _PE_STATE_DUMP_
1258 WBDEBUG(("* PLL_ON high\n")); 1259 WBDEBUG(("* PLL_ON high\n"));
1259 #endif 1260 #endif
1260 1261
1261 //ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x12BACF; 1262 //ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x12BACF;
1262 //Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1263 //Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1263 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F; 1264 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F;
1264 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1265 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1265 msleep(5); 1266 msleep(5);
1266 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F; 1267 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F;
1267 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1268 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1268 msleep(5); 1269 msleep(5);
1269 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x12BACF; 1270 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x12BACF;
1270 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1271 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1271 msleep(5); 1272 msleep(5);
1272 1273
1273 //Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000080 ); 1274 //Wb35Reg_WriteSync( pHwData, 0x03dc, 0x00000080 );
1274 //WBDEBUG(("* PLL_ON high\n")); 1275 //WBDEBUG(("* PLL_ON high\n"));
1275 break; 1276 break;
1276 1277
1277 case RF_WB_242: 1278 case RF_WB_242:
1278 case RF_WB_242_1: // 20060619.5 Add 1279 case RF_WB_242_1: // 20060619.5 Add
1279 1280
1280 // 1281 //
1281 // ; Version 1.3B revision items: for FA5976A , October 3, 2005 by HTHo 1282 // ; Version 1.3B revision items: for FA5976A , October 3, 2005 by HTHo
1282 // 1283 //
1283 ltmp = pHwData->reg.BB5C & 0xfffff000; 1284 ltmp = pHwData->reg.BB5C & 0xfffff000;
1284 Wb35Reg_WriteSync( pHwData, 0x105c, ltmp ); 1285 Wb35Reg_WriteSync( pHwData, 0x105c, ltmp );
1285 Wb35Reg_WriteSync( pHwData, 0x1058, 0 ); 1286 Wb35Reg_WriteSync( pHwData, 0x1058, 0 );
1286 pHwData->reg.BB50 |= 0x3;//(MASK_IQCAL_MODE|MASK_CALIB_START);//20060630 1287 pHwData->reg.BB50 |= 0x3;//(MASK_IQCAL_MODE|MASK_CALIB_START);//20060630
1287 Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50); 1288 Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50);
1288 1289
1289 //----- Calibration (1). VCO frequency calibration 1290 //----- Calibration (1). VCO frequency calibration
1290 //Calibration (1a.0). Synthesizer reset (HTHo corrected 2005/05/10) 1291 //Calibration (1a.0). Synthesizer reset (HTHo corrected 2005/05/10)
1291 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x0F<<24) | 0x00101E, 24); 1292 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x0F<<24) | 0x00101E, 24);
1292 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1293 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1293 msleep(5); // Sleep 5ms 1294 msleep(5); // Sleep 5ms
1294 //Calibration (1a). VCO frequency calibration mode ; waiting 2msec VCO calibration time 1295 //Calibration (1a). VCO frequency calibration mode ; waiting 2msec VCO calibration time
1295 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFE69c0, 24); 1296 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFE69c0, 24);
1296 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1297 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1297 msleep(2); // Sleep 2ms 1298 msleep(2); // Sleep 2ms
1298 1299
1299 //----- Calibration (2). TX baseband Gm-C filter auto-tuning 1300 //----- Calibration (2). TX baseband Gm-C filter auto-tuning
1300 //Calibration (2a). turn off ENCAL signal 1301 //Calibration (2a). turn off ENCAL signal
1301 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xF8EBC0, 24); 1302 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xF8EBC0, 24);
1302 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1303 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1303 //Calibration (2b.0). TX filter auto-tuning BW: TFLBW=101 (TC5376A default) 1304 //Calibration (2b.0). TX filter auto-tuning BW: TFLBW=101 (TC5376A default)
1304 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x07<<24) | 0x0C68CE, 24); 1305 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x07<<24) | 0x0C68CE, 24);
1305 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1306 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1306 //Calibration (2b). send TX reset signal (HTHo corrected May 10, 2005) 1307 //Calibration (2b). send TX reset signal (HTHo corrected May 10, 2005)
1307 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x0F<<24) | 0x00201E, 24); 1308 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x0F<<24) | 0x00201E, 24);
1308 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1309 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1309 //Calibration (2c). turn-on TX Gm-C filter auto-tuning 1310 //Calibration (2c). turn-on TX Gm-C filter auto-tuning
1310 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFCEBC0, 24); 1311 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFCEBC0, 24);
1311 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1312 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1312 udelay(150); // Sleep 150 us 1313 udelay(150); // Sleep 150 us
1313 //turn off ENCAL signal 1314 //turn off ENCAL signal
1314 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xF8EBC0, 24); 1315 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xF8EBC0, 24);
1315 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1316 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1316 1317
1317 //----- Calibration (3). RX baseband Gm-C filter auto-tuning 1318 //----- Calibration (3). RX baseband Gm-C filter auto-tuning
1318 //Calibration (3a). turn off ENCAL signal 1319 //Calibration (3a). turn off ENCAL signal
1319 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24); 1320 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
1320 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1321 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1321 //Calibration (3b.0). RX filter auto-tuning BW: RFLBW=100 (TC5376A+corner default; July 26, 2005) 1322 //Calibration (3b.0). RX filter auto-tuning BW: RFLBW=100 (TC5376A+corner default; July 26, 2005)
1322 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x07<<24) | 0x0C68CE, 24); 1323 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x07<<24) | 0x0C68CE, 24);
1323 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1324 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1324 //Calibration (3b). send RX reset signal (HTHo corrected May 10, 2005) 1325 //Calibration (3b). send RX reset signal (HTHo corrected May 10, 2005)
1325 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x0F<<24) | 0x00401E, 24); 1326 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x0F<<24) | 0x00401E, 24);
1326 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1327 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1327 //Calibration (3c). turn-on RX Gm-C filter auto-tuning 1328 //Calibration (3c). turn-on RX Gm-C filter auto-tuning
1328 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFEEDC0, 24); 1329 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFEEDC0, 24);
1329 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1330 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1330 udelay(150); // Sleep 150 us 1331 udelay(150); // Sleep 150 us
1331 //Calibration (3e). turn off ENCAL signal 1332 //Calibration (3e). turn off ENCAL signal
1332 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24); 1333 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
1333 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1334 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1334 1335
1335 //----- Calibration (4). TX LO leakage calibration 1336 //----- Calibration (4). TX LO leakage calibration
1336 //Calibration (4a). TX LO leakage calibration 1337 //Calibration (4a). TX LO leakage calibration
1337 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFD6BC0, 24); 1338 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFD6BC0, 24);
1338 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1339 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1339 udelay(150); // Sleep 150 us 1340 udelay(150); // Sleep 150 us
1340 1341
1341 //----- Calibration (5). RX DC offset calibration 1342 //----- Calibration (5). RX DC offset calibration
1342 //Calibration (5a). turn off ENCAL signal and set to RX SW DC caliration mode 1343 //Calibration (5a). turn off ENCAL signal and set to RX SW DC caliration mode
1343 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24); 1344 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
1344 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1345 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1345 //Calibration (5b). turn off AGC servo-loop & RSSI 1346 //Calibration (5b). turn off AGC servo-loop & RSSI
1346 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x01<<24) | 0xEBFFC2, 24); 1347 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x01<<24) | 0xEBFFC2, 24);
1347 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1348 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1348 1349
1349 //; for LNA=11 -------- 1350 //; for LNA=11 --------
1350 //Calibration (5c-h). RX DC offset current bias ON; & LNA=11; RXVGA=111111 1351 //Calibration (5c-h). RX DC offset current bias ON; & LNA=11; RXVGA=111111
1351 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x343FCC, 24); 1352 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x343FCC, 24);
1352 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1353 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1353 //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time 1354 //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time
1354 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24); 1355 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24);
1355 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1356 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1356 msleep(2); // Sleep 2ms 1357 msleep(2); // Sleep 2ms
1357 //Calibration (5f). turn off ENCAL signal 1358 //Calibration (5f). turn off ENCAL signal
1358 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24); 1359 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
1359 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1360 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1360 1361
1361 //; for LNA=10 -------- 1362 //; for LNA=10 --------
1362 //Calibration (5c-m). RX DC offset current bias ON; & LNA=10; RXVGA=111111 1363 //Calibration (5c-m). RX DC offset current bias ON; & LNA=10; RXVGA=111111
1363 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x342FCC, 24); 1364 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x342FCC, 24);
1364 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1365 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1365 //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time 1366 //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time
1366 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24); 1367 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24);
1367 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1368 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1368 msleep(2); // Sleep 2ms 1369 msleep(2); // Sleep 2ms
1369 //Calibration (5f). turn off ENCAL signal 1370 //Calibration (5f). turn off ENCAL signal
1370 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24); 1371 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
1371 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1372 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1372 1373
1373 //; for LNA=01 -------- 1374 //; for LNA=01 --------
1374 //Calibration (5c-m). RX DC offset current bias ON; & LNA=01; RXVGA=111111 1375 //Calibration (5c-m). RX DC offset current bias ON; & LNA=01; RXVGA=111111
1375 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x341FCC, 24); 1376 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x341FCC, 24);
1376 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1377 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1377 //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time 1378 //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time
1378 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24); 1379 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24);
1379 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1380 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1380 msleep(2); // Sleep 2ms 1381 msleep(2); // Sleep 2ms
1381 //Calibration (5f). turn off ENCAL signal 1382 //Calibration (5f). turn off ENCAL signal
1382 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24); 1383 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
1383 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1384 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1384 1385
1385 //; for LNA=00 -------- 1386 //; for LNA=00 --------
1386 //Calibration (5c-l). RX DC offset current bias ON; & LNA=00; RXVGA=111111 1387 //Calibration (5c-l). RX DC offset current bias ON; & LNA=00; RXVGA=111111
1387 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x340FCC, 24); 1388 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x06<<24) | 0x340FCC, 24);
1388 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1389 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1389 //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time 1390 //Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time
1390 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24); 1391 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFF6DC0, 24);
1391 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1392 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1392 msleep(2); // Sleep 2ms 1393 msleep(2); // Sleep 2ms
1393 //Calibration (5f). turn off ENCAL signal 1394 //Calibration (5f). turn off ENCAL signal
1394 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24); 1395 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xFAEDC0, 24);
1395 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1396 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1396 //Calibration (5g). turn on AGC servo-loop 1397 //Calibration (5g). turn on AGC servo-loop
1397 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x01<<24) | 0xEFFFC2, 24); 1398 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x01<<24) | 0xEFFFC2, 24);
1398 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1399 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1399 1400
1400 //; ----- Calibration (7). Switch RF chip to normal mode 1401 //; ----- Calibration (7). Switch RF chip to normal mode
1401 //0x00 0xF86100 ; 3E184 ; Switch RF chip to normal mode 1402 //0x00 0xF86100 ; 3E184 ; Switch RF chip to normal mode
1402 // msleep(10); // @@ 20060721 1403 // msleep(10); // @@ 20060721
1403 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xF86100, 24); 1404 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( (0x00<<24) | 0xF86100, 24);
1404 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp ); 1405 Wb35Reg_WriteSync( pHwData, 0x0864, ltmp );
1405 msleep(5); // Sleep 5 ms 1406 msleep(5); // Sleep 5 ms
1406 1407
1407 // //write back 1408 // //write back
1408 // Wb35Reg_WriteSync(pHwData, 0x105c, pHwData->reg.BB5C); 1409 // Wb35Reg_WriteSync(pHwData, 0x105c, pHwData->reg.BB5C);
1409 // pHwData->reg.BB50 &= ~0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START); // 20060315.1 fix 1410 // pHwData->reg.BB50 &= ~0x13;//(MASK_IQCAL_MODE|MASK_CALIB_START); // 20060315.1 fix
1410 // Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50); 1411 // Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50);
1411 // msleep(1); // Sleep 1 ms 1412 // msleep(1); // Sleep 1 ms
1412 break; 1413 break;
1413 } 1414 }
1414 } 1415 }
1415 1416
1416 void BBProcessor_AL7230_2400( phw_data_t pHwData) 1417 void BBProcessor_AL7230_2400( phw_data_t pHwData)
1417 { 1418 {
1418 struct wb35_reg *reg = &pHwData->reg; 1419 struct wb35_reg *reg = &pHwData->reg;
1419 u32 pltmp[12]; 1420 u32 pltmp[12];
1420 1421
1421 pltmp[0] = 0x16A8337A; // 0x16a5215f; // 0x1000 AGC_Ctrl1 1422 pltmp[0] = 0x16A8337A; // 0x16a5215f; // 0x1000 AGC_Ctrl1
1422 pltmp[1] = 0x9AFF9AA6; // 0x9aff9ca6; // 0x1004 AGC_Ctrl2 1423 pltmp[1] = 0x9AFF9AA6; // 0x9aff9ca6; // 0x1004 AGC_Ctrl2
1423 pltmp[2] = 0x55D00A04; // 0x55d00a04; // 0x1008 AGC_Ctrl3 1424 pltmp[2] = 0x55D00A04; // 0x55d00a04; // 0x1008 AGC_Ctrl3
1424 pltmp[3] = 0xFFF72031; // 0xFfFf2138; // 0x100c AGC_Ctrl4 1425 pltmp[3] = 0xFFF72031; // 0xFfFf2138; // 0x100c AGC_Ctrl4
1425 reg->BB0C = 0xFFF72031; 1426 reg->BB0C = 0xFFF72031;
1426 pltmp[4] = 0x0FacDCC5; // 0x1010 AGC_Ctrl5 // 20050927 0x0FacDCB7 1427 pltmp[4] = 0x0FacDCC5; // 0x1010 AGC_Ctrl5 // 20050927 0x0FacDCB7
1427 pltmp[5] = 0x00CAA333; // 0x00eaa333; // 0x1014 AGC_Ctrl6 1428 pltmp[5] = 0x00CAA333; // 0x00eaa333; // 0x1014 AGC_Ctrl6
1428 pltmp[6] = 0xF2211111; // 0x11111111; // 0x1018 AGC_Ctrl7 1429 pltmp[6] = 0xF2211111; // 0x11111111; // 0x1018 AGC_Ctrl7
1429 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8 1430 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
1430 pltmp[8] = 0x06443440; // 0x1020 AGC_Ctrl9 1431 pltmp[8] = 0x06443440; // 0x1020 AGC_Ctrl9
1431 pltmp[9] = 0xA8002A79; // 0xa9002A79; // 0x1024 AGC_Ctrl10 1432 pltmp[9] = 0xA8002A79; // 0xa9002A79; // 0x1024 AGC_Ctrl10
1432 pltmp[10] = 0x40000528; // 20050927 0x40000228 1433 pltmp[10] = 0x40000528; // 20050927 0x40000228
1433 pltmp[11] = 0x232D7F30; // 0x23457f30;// 0x102c A_ACQ_Ctrl 1434 pltmp[11] = 0x232D7F30; // 0x23457f30;// 0x102c A_ACQ_Ctrl
1434 reg->BB2C = 0x232D7F30; 1435 reg->BB2C = 0x232D7F30;
1435 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT ); 1436 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
1436 1437
1437 pltmp[0] = 0x00002c54; // 0x1030 B_ACQ_Ctrl 1438 pltmp[0] = 0x00002c54; // 0x1030 B_ACQ_Ctrl
1438 reg->BB30 = 0x00002c54; 1439 reg->BB30 = 0x00002c54;
1439 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl 1440 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
1440 pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl 1441 pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl
1441 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter 1442 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
1442 reg->BB3C = 0x00000000; 1443 reg->BB3C = 0x00000000;
1443 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter 1444 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
1444 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter 1445 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
1445 pltmp[6] = 0x00332C1B; // 0x00453B24; // 0x1048 11b TX RC filter 1446 pltmp[6] = 0x00332C1B; // 0x00453B24; // 0x1048 11b TX RC filter
1446 pltmp[7] = 0x0A00FEFF; // 0x0E00FEFF; // 0x104c 11b TX RC filter 1447 pltmp[7] = 0x0A00FEFF; // 0x0E00FEFF; // 0x104c 11b TX RC filter
1447 pltmp[8] = 0x2B106208; // 0x1050 MODE_Ctrl 1448 pltmp[8] = 0x2B106208; // 0x1050 MODE_Ctrl
1448 reg->BB50 = 0x2B106208; 1449 reg->BB50 = 0x2B106208;
1449 pltmp[9] = 0; // 0x1054 1450 pltmp[9] = 0; // 0x1054
1450 reg->BB54 = 0x00000000; 1451 reg->BB54 = 0x00000000;
1451 pltmp[10] = 0x52524242; // 0x64645252; // 0x1058 IQ_Alpha 1452 pltmp[10] = 0x52524242; // 0x64645252; // 0x1058 IQ_Alpha
1452 reg->BB58 = 0x52524242; 1453 reg->BB58 = 0x52524242;
1453 pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel 1454 pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
1454 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT ); 1455 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
1455 1456
1456 } 1457 }
1457 1458
1458 void BBProcessor_AL7230_5000( phw_data_t pHwData) 1459 void BBProcessor_AL7230_5000( phw_data_t pHwData)
1459 { 1460 {
1460 struct wb35_reg *reg = &pHwData->reg; 1461 struct wb35_reg *reg = &pHwData->reg;
1461 u32 pltmp[12]; 1462 u32 pltmp[12];
1462 1463
1463 pltmp[0] = 0x16AA6678; // 0x1000 AGC_Ctrl1 1464 pltmp[0] = 0x16AA6678; // 0x1000 AGC_Ctrl1
1464 pltmp[1] = 0x9AFFA0B2; // 0x1004 AGC_Ctrl2 1465 pltmp[1] = 0x9AFFA0B2; // 0x1004 AGC_Ctrl2
1465 pltmp[2] = 0x55D00A04; // 0x1008 AGC_Ctrl3 1466 pltmp[2] = 0x55D00A04; // 0x1008 AGC_Ctrl3
1466 pltmp[3] = 0xEFFF233E; // 0x100c AGC_Ctrl4 1467 pltmp[3] = 0xEFFF233E; // 0x100c AGC_Ctrl4
1467 reg->BB0C = 0xEFFF233E; 1468 reg->BB0C = 0xEFFF233E;
1468 pltmp[4] = 0x0FacDCC5; // 0x1010 AGC_Ctrl5 // 20050927 0x0FacDCB7 1469 pltmp[4] = 0x0FacDCC5; // 0x1010 AGC_Ctrl5 // 20050927 0x0FacDCB7
1469 pltmp[5] = 0x00CAA333; // 0x1014 AGC_Ctrl6 1470 pltmp[5] = 0x00CAA333; // 0x1014 AGC_Ctrl6
1470 pltmp[6] = 0xF2432111; // 0x1018 AGC_Ctrl7 1471 pltmp[6] = 0xF2432111; // 0x1018 AGC_Ctrl7
1471 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8 1472 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
1472 pltmp[8] = 0x05C43440; // 0x1020 AGC_Ctrl9 1473 pltmp[8] = 0x05C43440; // 0x1020 AGC_Ctrl9
1473 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10 1474 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
1474 pltmp[10] = 0x40000528; // 20050927 0x40000228 1475 pltmp[10] = 0x40000528; // 20050927 0x40000228
1475 pltmp[11] = 0x232FDF30;// 0x102c A_ACQ_Ctrl 1476 pltmp[11] = 0x232FDF30;// 0x102c A_ACQ_Ctrl
1476 reg->BB2C = 0x232FDF30; 1477 reg->BB2C = 0x232FDF30;
1477 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT ); 1478 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
1478 1479
1479 pltmp[0] = 0x80002C7C; // 0x1030 B_ACQ_Ctrl 1480 pltmp[0] = 0x80002C7C; // 0x1030 B_ACQ_Ctrl
1480 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl 1481 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
1481 pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl 1482 pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl
1482 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter 1483 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
1483 reg->BB3C = 0x00000000; 1484 reg->BB3C = 0x00000000;
1484 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter 1485 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
1485 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter 1486 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
1486 pltmp[6] = 0x00332C1B; // 0x1048 11b TX RC filter 1487 pltmp[6] = 0x00332C1B; // 0x1048 11b TX RC filter
1487 pltmp[7] = 0x0A00FEFF; // 0x104c 11b TX RC filter 1488 pltmp[7] = 0x0A00FEFF; // 0x104c 11b TX RC filter
1488 pltmp[8] = 0x2B107208; // 0x1050 MODE_Ctrl 1489 pltmp[8] = 0x2B107208; // 0x1050 MODE_Ctrl
1489 reg->BB50 = 0x2B107208; 1490 reg->BB50 = 0x2B107208;
1490 pltmp[9] = 0; // 0x1054 1491 pltmp[9] = 0; // 0x1054
1491 reg->BB54 = 0x00000000; 1492 reg->BB54 = 0x00000000;
1492 pltmp[10] = 0x52524242; // 0x1058 IQ_Alpha 1493 pltmp[10] = 0x52524242; // 0x1058 IQ_Alpha
1493 reg->BB58 = 0x52524242; 1494 reg->BB58 = 0x52524242;
1494 pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel 1495 pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
1495 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT ); 1496 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
1496 1497
1497 } 1498 }
1498 1499
1499 //============================================================================================================= 1500 //=============================================================================================================
1500 // BBProcessorPowerupInit -- 1501 // BBProcessorPowerupInit --
1501 // 1502 //
1502 // Description: 1503 // Description:
1503 // Initialize the Baseband processor. 1504 // Initialize the Baseband processor.
1504 // 1505 //
1505 // Arguments: 1506 // Arguments:
1506 // pHwData - Handle of the USB Device. 1507 // pHwData - Handle of the USB Device.
1507 // 1508 //
1508 // Return values: 1509 // Return values:
1509 // None. 1510 // None.
1510 //============================================================================================================= 1511 //=============================================================================================================
1511 void 1512 void
1512 BBProcessor_initial( phw_data_t pHwData ) 1513 BBProcessor_initial( phw_data_t pHwData )
1513 { 1514 {
1514 struct wb35_reg *reg = &pHwData->reg; 1515 struct wb35_reg *reg = &pHwData->reg;
1515 u32 i, pltmp[12]; 1516 u32 i, pltmp[12];
1516 1517
1517 switch( pHwData->phy_type ) 1518 switch( pHwData->phy_type )
1518 { 1519 {
1519 case RF_MAXIM_V1: // Initializng the Winbond 2nd BB(with Phy board (v1) + Maxim 331) 1520 case RF_MAXIM_V1: // Initializng the Winbond 2nd BB(with Phy board (v1) + Maxim 331)
1520 1521
1521 pltmp[0] = 0x16F47E77; // 0x1000 AGC_Ctrl1 1522 pltmp[0] = 0x16F47E77; // 0x1000 AGC_Ctrl1
1522 pltmp[1] = 0x9AFFAEA4; // 0x1004 AGC_Ctrl2 1523 pltmp[1] = 0x9AFFAEA4; // 0x1004 AGC_Ctrl2
1523 pltmp[2] = 0x55D00A04; // 0x1008 AGC_Ctrl3 1524 pltmp[2] = 0x55D00A04; // 0x1008 AGC_Ctrl3
1524 pltmp[3] = 0xEFFF1A34; // 0x100c AGC_Ctrl4 1525 pltmp[3] = 0xEFFF1A34; // 0x100c AGC_Ctrl4
1525 reg->BB0C = 0xEFFF1A34; 1526 reg->BB0C = 0xEFFF1A34;
1526 pltmp[4] = 0x0FABE0B7; // 0x1010 AGC_Ctrl5 1527 pltmp[4] = 0x0FABE0B7; // 0x1010 AGC_Ctrl5
1527 pltmp[5] = 0x00CAA332; // 0x1014 AGC_Ctrl6 1528 pltmp[5] = 0x00CAA332; // 0x1014 AGC_Ctrl6
1528 pltmp[6] = 0xF6632111; // 0x1018 AGC_Ctrl7 1529 pltmp[6] = 0xF6632111; // 0x1018 AGC_Ctrl7
1529 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8 1530 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
1530 pltmp[8] = 0x04CC3640; // 0x1020 AGC_Ctrl9 1531 pltmp[8] = 0x04CC3640; // 0x1020 AGC_Ctrl9
1531 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10 1532 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
1532 pltmp[10] = (pHwData->phy_type==3) ? 0x40000a28 : 0x40000228; // 0x1028 MAXIM_331(b31=0) + WBRF_V1(b11=1) : MAXIM_331(b31=0) + WBRF_V2(b11=0) 1533 pltmp[10] = (pHwData->phy_type==3) ? 0x40000a28 : 0x40000228; // 0x1028 MAXIM_331(b31=0) + WBRF_V1(b11=1) : MAXIM_331(b31=0) + WBRF_V2(b11=0)
1533 pltmp[11] = 0x232FDF30; // 0x102c A_ACQ_Ctrl 1534 pltmp[11] = 0x232FDF30; // 0x102c A_ACQ_Ctrl
1534 reg->BB2C = 0x232FDF30; //Modify for 33's 1.0.95.xxx version, antenna 1 1535 reg->BB2C = 0x232FDF30; //Modify for 33's 1.0.95.xxx version, antenna 1
1535 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT ); 1536 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
1536 1537
1537 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl 1538 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
1538 reg->BB30 = 0x00002C54; 1539 reg->BB30 = 0x00002C54;
1539 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl 1540 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
1540 pltmp[2] = 0x5B6C8769; // 0x1038 B_TXRX_Ctrl 1541 pltmp[2] = 0x5B6C8769; // 0x1038 B_TXRX_Ctrl
1541 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter 1542 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
1542 reg->BB3C = 0x00000000; 1543 reg->BB3C = 0x00000000;
1543 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter 1544 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
1544 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter 1545 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
1545 pltmp[6] = 0x00453B24; // 0x1048 11b TX RC filter 1546 pltmp[6] = 0x00453B24; // 0x1048 11b TX RC filter
1546 pltmp[7] = 0x0E00FEFF; // 0x104c 11b TX RC filter 1547 pltmp[7] = 0x0E00FEFF; // 0x104c 11b TX RC filter
1547 pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl 1548 pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl
1548 reg->BB50 = 0x27106208; 1549 reg->BB50 = 0x27106208;
1549 pltmp[9] = 0; // 0x1054 1550 pltmp[9] = 0; // 0x1054
1550 reg->BB54 = 0x00000000; 1551 reg->BB54 = 0x00000000;
1551 pltmp[10] = 0x64646464; // 0x1058 IQ_Alpha 1552 pltmp[10] = 0x64646464; // 0x1058 IQ_Alpha
1552 reg->BB58 = 0x64646464; 1553 reg->BB58 = 0x64646464;
1553 pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel 1554 pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
1554 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT ); 1555 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
1555 1556
1556 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 ); 1557 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
1557 break; 1558 break;
1558 1559
1559 //------------------------------------------------------------------ 1560 //------------------------------------------------------------------
1560 //[20040722 WK] 1561 //[20040722 WK]
1561 //Only for baseband version 2 1562 //Only for baseband version 2
1562 // case RF_MAXIM_317: 1563 // case RF_MAXIM_317:
1563 case RF_MAXIM_2825: 1564 case RF_MAXIM_2825:
1564 case RF_MAXIM_2827: 1565 case RF_MAXIM_2827:
1565 case RF_MAXIM_2828: 1566 case RF_MAXIM_2828:
1566 1567
1567 pltmp[0] = 0x16b47e77; // 0x1000 AGC_Ctrl1 1568 pltmp[0] = 0x16b47e77; // 0x1000 AGC_Ctrl1
1568 pltmp[1] = 0x9affaea4; // 0x1004 AGC_Ctrl2 1569 pltmp[1] = 0x9affaea4; // 0x1004 AGC_Ctrl2
1569 pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3 1570 pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3
1570 pltmp[3] = 0xefff1a34; // 0x100c AGC_Ctrl4 1571 pltmp[3] = 0xefff1a34; // 0x100c AGC_Ctrl4
1571 reg->BB0C = 0xefff1a34; 1572 reg->BB0C = 0xefff1a34;
1572 pltmp[4] = 0x0fabe0b7; // 0x1010 AGC_Ctrl5 1573 pltmp[4] = 0x0fabe0b7; // 0x1010 AGC_Ctrl5
1573 pltmp[5] = 0x00caa332; // 0x1014 AGC_Ctrl6 1574 pltmp[5] = 0x00caa332; // 0x1014 AGC_Ctrl6
1574 pltmp[6] = 0xf6632111; // 0x1018 AGC_Ctrl7 1575 pltmp[6] = 0xf6632111; // 0x1018 AGC_Ctrl7
1575 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8 1576 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
1576 pltmp[8] = 0x04CC3640; // 0x1020 AGC_Ctrl9 1577 pltmp[8] = 0x04CC3640; // 0x1020 AGC_Ctrl9
1577 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10 1578 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
1578 pltmp[10] = 0x40000528; // 0x40000128; Modify for 33's 1.0.95 1579 pltmp[10] = 0x40000528; // 0x40000128; Modify for 33's 1.0.95
1579 pltmp[11] = 0x232fdf30; // 0x102c A_ACQ_Ctrl 1580 pltmp[11] = 0x232fdf30; // 0x102c A_ACQ_Ctrl
1580 reg->BB2C = 0x232fdf30; //Modify for 33's 1.0.95.xxx version, antenna 1 1581 reg->BB2C = 0x232fdf30; //Modify for 33's 1.0.95.xxx version, antenna 1
1581 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT ); 1582 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
1582 1583
1583 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl 1584 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
1584 reg->BB30 = 0x00002C54; 1585 reg->BB30 = 0x00002C54;
1585 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl 1586 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
1586 pltmp[2] = 0x5B6C8769; // 0x1038 B_TXRX_Ctrl 1587 pltmp[2] = 0x5B6C8769; // 0x1038 B_TXRX_Ctrl
1587 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter 1588 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
1588 reg->BB3C = 0x00000000; 1589 reg->BB3C = 0x00000000;
1589 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter 1590 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
1590 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter 1591 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
1591 pltmp[6] = 0x00453B24; // 0x1048 11b TX RC filter 1592 pltmp[6] = 0x00453B24; // 0x1048 11b TX RC filter
1592 pltmp[7] = 0x0D00FDFF; // 0x104c 11b TX RC filter 1593 pltmp[7] = 0x0D00FDFF; // 0x104c 11b TX RC filter
1593 pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl 1594 pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl
1594 reg->BB50 = 0x27106208; 1595 reg->BB50 = 0x27106208;
1595 pltmp[9] = 0; // 0x1054 1596 pltmp[9] = 0; // 0x1054
1596 reg->BB54 = 0x00000000; 1597 reg->BB54 = 0x00000000;
1597 pltmp[10] = 0x64646464; // 0x1058 IQ_Alpha 1598 pltmp[10] = 0x64646464; // 0x1058 IQ_Alpha
1598 reg->BB58 = 0x64646464; 1599 reg->BB58 = 0x64646464;
1599 pltmp[11] = 0xAA28C000; // 0x105c DC_Cancel 1600 pltmp[11] = 0xAA28C000; // 0x105c DC_Cancel
1600 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT ); 1601 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
1601 1602
1602 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 ); 1603 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
1603 break; 1604 break;
1604 1605
1605 case RF_MAXIM_2829: 1606 case RF_MAXIM_2829:
1606 1607
1607 pltmp[0] = 0x16b47e77; // 0x1000 AGC_Ctrl1 1608 pltmp[0] = 0x16b47e77; // 0x1000 AGC_Ctrl1
1608 pltmp[1] = 0x9affaea4; // 0x1004 AGC_Ctrl2 1609 pltmp[1] = 0x9affaea4; // 0x1004 AGC_Ctrl2
1609 pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3 1610 pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3
1610 pltmp[3] = 0xf4ff1632; // 0xefff1a34; // 0x100c AGC_Ctrl4 Modify for 33's 1.0.95 1611 pltmp[3] = 0xf4ff1632; // 0xefff1a34; // 0x100c AGC_Ctrl4 Modify for 33's 1.0.95
1611 reg->BB0C = 0xf4ff1632; // 0xefff1a34; Modify for 33's 1.0.95 1612 reg->BB0C = 0xf4ff1632; // 0xefff1a34; Modify for 33's 1.0.95
1612 pltmp[4] = 0x0fabe0b7; // 0x1010 AGC_Ctrl5 1613 pltmp[4] = 0x0fabe0b7; // 0x1010 AGC_Ctrl5
1613 pltmp[5] = 0x00caa332; // 0x1014 AGC_Ctrl6 1614 pltmp[5] = 0x00caa332; // 0x1014 AGC_Ctrl6
1614 pltmp[6] = 0xf8632112; // 0xf6632111; // 0x1018 AGC_Ctrl7 Modify for 33's 1.0.95 1615 pltmp[6] = 0xf8632112; // 0xf6632111; // 0x1018 AGC_Ctrl7 Modify for 33's 1.0.95
1615 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8 1616 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
1616 pltmp[8] = 0x04CC3640; // 0x1020 AGC_Ctrl9 1617 pltmp[8] = 0x04CC3640; // 0x1020 AGC_Ctrl9
1617 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10 1618 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
1618 pltmp[10] = 0x40000528; // 0x40000128; modify for 33's 1.0.95 1619 pltmp[10] = 0x40000528; // 0x40000128; modify for 33's 1.0.95
1619 pltmp[11] = 0x232fdf30; // 0x102c A_ACQ_Ctrl 1620 pltmp[11] = 0x232fdf30; // 0x102c A_ACQ_Ctrl
1620 reg->BB2C = 0x232fdf30; //Modify for 33's 1.0.95.xxx version, antenna 1 1621 reg->BB2C = 0x232fdf30; //Modify for 33's 1.0.95.xxx version, antenna 1
1621 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT ); 1622 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
1622 1623
1623 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl 1624 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
1624 reg->BB30 = 0x00002C54; 1625 reg->BB30 = 0x00002C54;
1625 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl 1626 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
1626 pltmp[2] = 0x5b2c8769; // 0x5B6C8769; // 0x1038 B_TXRX_Ctrl Modify for 33's 1.0.95 1627 pltmp[2] = 0x5b2c8769; // 0x5B6C8769; // 0x1038 B_TXRX_Ctrl Modify for 33's 1.0.95
1627 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter 1628 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
1628 reg->BB3C = 0x00000000; 1629 reg->BB3C = 0x00000000;
1629 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter 1630 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
1630 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter 1631 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
1631 pltmp[6] = 0x002c2617; // 0x00453B24; // 0x1048 11b TX RC filter Modify for 33's 1.0.95 1632 pltmp[6] = 0x002c2617; // 0x00453B24; // 0x1048 11b TX RC filter Modify for 33's 1.0.95
1632 pltmp[7] = 0x0800feff; // 0x0D00FDFF; // 0x104c 11b TX RC filter Modify for 33's 1.0.95 1633 pltmp[7] = 0x0800feff; // 0x0D00FDFF; // 0x104c 11b TX RC filter Modify for 33's 1.0.95
1633 pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl 1634 pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl
1634 reg->BB50 = 0x27106208; 1635 reg->BB50 = 0x27106208;
1635 pltmp[9] = 0; // 0x1054 1636 pltmp[9] = 0; // 0x1054
1636 reg->BB54 = 0x00000000; 1637 reg->BB54 = 0x00000000;
1637 pltmp[10] = 0x64644a4a; // 0x64646464; // 0x1058 IQ_Alpha Modify for 33's 1.0.95 1638 pltmp[10] = 0x64644a4a; // 0x64646464; // 0x1058 IQ_Alpha Modify for 33's 1.0.95
1638 reg->BB58 = 0x64646464; 1639 reg->BB58 = 0x64646464;
1639 pltmp[11] = 0xAA28C000; // 0x105c DC_Cancel 1640 pltmp[11] = 0xAA28C000; // 0x105c DC_Cancel
1640 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT ); 1641 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
1641 1642
1642 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 ); 1643 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
1643 break; 1644 break;
1644 1645
1645 case RF_AIROHA_2230: 1646 case RF_AIROHA_2230:
1646 1647
1647 pltmp[0] = 0X16764A77; // 0x1000 AGC_Ctrl1 //0x16765A77 1648 pltmp[0] = 0X16764A77; // 0x1000 AGC_Ctrl1 //0x16765A77
1648 pltmp[1] = 0x9affafb2; // 0x1004 AGC_Ctrl2 1649 pltmp[1] = 0x9affafb2; // 0x1004 AGC_Ctrl2
1649 pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3 1650 pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3
1650 pltmp[3] = 0xFFFd203c; // 0xFFFb203a; // 0x100c AGC_Ctrl4 Modify for 33's 1.0.95.xxx version 1651 pltmp[3] = 0xFFFd203c; // 0xFFFb203a; // 0x100c AGC_Ctrl4 Modify for 33's 1.0.95.xxx version
1651 reg->BB0C = 0xFFFd203c; 1652 reg->BB0C = 0xFFFd203c;
1652 pltmp[4] = 0X0FBFDCc5; // 0X0FBFDCA0; // 0x1010 AGC_Ctrl5 //0x0FB2E0B7 Modify for 33's 1.0.95.xxx version 1653 pltmp[4] = 0X0FBFDCc5; // 0X0FBFDCA0; // 0x1010 AGC_Ctrl5 //0x0FB2E0B7 Modify for 33's 1.0.95.xxx version
1653 pltmp[5] = 0x00caa332; // 0x00caa333; // 0x1014 AGC_Ctrl6 Modify for 33's 1.0.95.xxx version 1654 pltmp[5] = 0x00caa332; // 0x00caa333; // 0x1014 AGC_Ctrl6 Modify for 33's 1.0.95.xxx version
1654 pltmp[6] = 0XF6632111; // 0XF1632112; // 0x1018 AGC_Ctrl7 //0xf6632112 Modify for 33's 1.0.95.xxx version 1655 pltmp[6] = 0XF6632111; // 0XF1632112; // 0x1018 AGC_Ctrl7 //0xf6632112 Modify for 33's 1.0.95.xxx version
1655 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8 1656 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
1656 pltmp[8] = 0x04C43640; // 0x1020 AGC_Ctrl9 1657 pltmp[8] = 0x04C43640; // 0x1020 AGC_Ctrl9
1657 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10 1658 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
1658 pltmp[10] = 0X40000528; //0x40000228 1659 pltmp[10] = 0X40000528; //0x40000228
1659 pltmp[11] = 0x232dfF30; // 0x232A9F30; // 0x102c A_ACQ_Ctrl //0x232a9730 1660 pltmp[11] = 0x232dfF30; // 0x232A9F30; // 0x102c A_ACQ_Ctrl //0x232a9730
1660 reg->BB2C = 0x232dfF30; //Modify for 33's 1.0.95.xxx version, antenna 1 1661 reg->BB2C = 0x232dfF30; //Modify for 33's 1.0.95.xxx version, antenna 1
1661 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT ); 1662 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
1662 1663
1663 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl 1664 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
1664 reg->BB30 = 0x00002C54; 1665 reg->BB30 = 0x00002C54;
1665 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl 1666 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
1666 pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl //0x5B6C8769 1667 pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl //0x5B6C8769
1667 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter 1668 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
1668 reg->BB3C = 0x00000000; 1669 reg->BB3C = 0x00000000;
1669 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter 1670 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
1670 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter 1671 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
1671 pltmp[6] = BB48_DEFAULT_AL2230_11G; // 0x1048 11b TX RC filter 20060613.2 1672 pltmp[6] = BB48_DEFAULT_AL2230_11G; // 0x1048 11b TX RC filter 20060613.2
1672 reg->BB48 = BB48_DEFAULT_AL2230_11G; // 20051221 ch14 20060613.2 1673 reg->BB48 = BB48_DEFAULT_AL2230_11G; // 20051221 ch14 20060613.2
1673 pltmp[7] = BB4C_DEFAULT_AL2230_11G; // 0x104c 11b TX RC filter 20060613.2 1674 pltmp[7] = BB4C_DEFAULT_AL2230_11G; // 0x104c 11b TX RC filter 20060613.2
1674 reg->BB4C = BB4C_DEFAULT_AL2230_11G; // 20060613.1 20060613.2 1675 reg->BB4C = BB4C_DEFAULT_AL2230_11G; // 20060613.1 20060613.2
1675 pltmp[8] = 0x27106200; // 0x1050 MODE_Ctrl 1676 pltmp[8] = 0x27106200; // 0x1050 MODE_Ctrl
1676 reg->BB50 = 0x27106200; 1677 reg->BB50 = 0x27106200;
1677 pltmp[9] = 0; // 0x1054 1678 pltmp[9] = 0; // 0x1054
1678 reg->BB54 = 0x00000000; 1679 reg->BB54 = 0x00000000;
1679 pltmp[10] = 0x52524242; // 0x1058 IQ_Alpha 1680 pltmp[10] = 0x52524242; // 0x1058 IQ_Alpha
1680 reg->BB58 = 0x52524242; 1681 reg->BB58 = 0x52524242;
1681 pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel 1682 pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
1682 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT ); 1683 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
1683 1684
1684 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 ); 1685 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
1685 break; 1686 break;
1686 1687
1687 case RF_AIROHA_2230S: // 20060420 Add this 1688 case RF_AIROHA_2230S: // 20060420 Add this
1688 1689
1689 pltmp[0] = 0X16764A77; // 0x1000 AGC_Ctrl1 //0x16765A77 1690 pltmp[0] = 0X16764A77; // 0x1000 AGC_Ctrl1 //0x16765A77
1690 pltmp[1] = 0x9affafb2; // 0x1004 AGC_Ctrl2 1691 pltmp[1] = 0x9affafb2; // 0x1004 AGC_Ctrl2
1691 pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3 1692 pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3
1692 pltmp[3] = 0xFFFd203c; // 0xFFFb203a; // 0x100c AGC_Ctrl4 Modify for 33's 1.0.95.xxx version 1693 pltmp[3] = 0xFFFd203c; // 0xFFFb203a; // 0x100c AGC_Ctrl4 Modify for 33's 1.0.95.xxx version
1693 reg->BB0C = 0xFFFd203c; 1694 reg->BB0C = 0xFFFd203c;
1694 pltmp[4] = 0X0FBFDCc5; // 0X0FBFDCA0; // 0x1010 AGC_Ctrl5 //0x0FB2E0B7 Modify for 33's 1.0.95.xxx version 1695 pltmp[4] = 0X0FBFDCc5; // 0X0FBFDCA0; // 0x1010 AGC_Ctrl5 //0x0FB2E0B7 Modify for 33's 1.0.95.xxx version
1695 pltmp[5] = 0x00caa332; // 0x00caa333; // 0x1014 AGC_Ctrl6 Modify for 33's 1.0.95.xxx version 1696 pltmp[5] = 0x00caa332; // 0x00caa333; // 0x1014 AGC_Ctrl6 Modify for 33's 1.0.95.xxx version
1696 pltmp[6] = 0XF6632111; // 0XF1632112; // 0x1018 AGC_Ctrl7 //0xf6632112 Modify for 33's 1.0.95.xxx version 1697 pltmp[6] = 0XF6632111; // 0XF1632112; // 0x1018 AGC_Ctrl7 //0xf6632112 Modify for 33's 1.0.95.xxx version
1697 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8 1698 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
1698 pltmp[8] = 0x04C43640; // 0x1020 AGC_Ctrl9 1699 pltmp[8] = 0x04C43640; // 0x1020 AGC_Ctrl9
1699 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10 1700 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
1700 pltmp[10] = 0X40000528; //0x40000228 1701 pltmp[10] = 0X40000528; //0x40000228
1701 pltmp[11] = 0x232dfF30; // 0x232A9F30; // 0x102c A_ACQ_Ctrl //0x232a9730 1702 pltmp[11] = 0x232dfF30; // 0x232A9F30; // 0x102c A_ACQ_Ctrl //0x232a9730
1702 reg->BB2C = 0x232dfF30; //Modify for 33's 1.0.95.xxx version, antenna 1 1703 reg->BB2C = 0x232dfF30; //Modify for 33's 1.0.95.xxx version, antenna 1
1703 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT ); 1704 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
1704 1705
1705 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl 1706 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
1706 reg->BB30 = 0x00002C54; 1707 reg->BB30 = 0x00002C54;
1707 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl 1708 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
1708 pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl //0x5B6C8769 1709 pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl //0x5B6C8769
1709 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter 1710 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
1710 reg->BB3C = 0x00000000; 1711 reg->BB3C = 0x00000000;
1711 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter 1712 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
1712 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter 1713 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
1713 pltmp[6] = BB48_DEFAULT_AL2230_11G; // 0x1048 11b TX RC filter 20060613.2 1714 pltmp[6] = BB48_DEFAULT_AL2230_11G; // 0x1048 11b TX RC filter 20060613.2
1714 reg->BB48 = BB48_DEFAULT_AL2230_11G; // 20051221 ch14 20060613.2 1715 reg->BB48 = BB48_DEFAULT_AL2230_11G; // 20051221 ch14 20060613.2
1715 pltmp[7] = BB4C_DEFAULT_AL2230_11G; // 0x104c 11b TX RC filter 20060613.2 1716 pltmp[7] = BB4C_DEFAULT_AL2230_11G; // 0x104c 11b TX RC filter 20060613.2
1716 reg->BB4C = BB4C_DEFAULT_AL2230_11G; // 20060613.1 1717 reg->BB4C = BB4C_DEFAULT_AL2230_11G; // 20060613.1
1717 pltmp[8] = 0x27106200; // 0x1050 MODE_Ctrl 1718 pltmp[8] = 0x27106200; // 0x1050 MODE_Ctrl
1718 reg->BB50 = 0x27106200; 1719 reg->BB50 = 0x27106200;
1719 pltmp[9] = 0; // 0x1054 1720 pltmp[9] = 0; // 0x1054
1720 reg->BB54 = 0x00000000; 1721 reg->BB54 = 0x00000000;
1721 pltmp[10] = 0x52523232; // 20060419 0x52524242; // 0x1058 IQ_Alpha 1722 pltmp[10] = 0x52523232; // 20060419 0x52524242; // 0x1058 IQ_Alpha
1722 reg->BB58 = 0x52523232; // 20060419 0x52524242; 1723 reg->BB58 = 0x52523232; // 20060419 0x52524242;
1723 pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel 1724 pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
1724 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT ); 1725 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
1725 1726
1726 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 ); 1727 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
1727 break; 1728 break;
1728 1729
1729 case RF_AIROHA_7230: 1730 case RF_AIROHA_7230:
1730 /* 1731 /*
1731 pltmp[0] = 0x16a84a77; // 0x1000 AGC_Ctrl1 1732 pltmp[0] = 0x16a84a77; // 0x1000 AGC_Ctrl1
1732 pltmp[1] = 0x9affafb2; // 0x1004 AGC_Ctrl2 1733 pltmp[1] = 0x9affafb2; // 0x1004 AGC_Ctrl2
1733 pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3 1734 pltmp[2] = 0x55d00a04; // 0x1008 AGC_Ctrl3
1734 pltmp[3] = 0xFFFb203a; // 0x100c AGC_Ctrl4 1735 pltmp[3] = 0xFFFb203a; // 0x100c AGC_Ctrl4
1735 reg->BB0c = 0xFFFb203a; 1736 reg->BB0c = 0xFFFb203a;
1736 pltmp[4] = 0x0FBFDCB7; // 0x1010 AGC_Ctrl5 1737 pltmp[4] = 0x0FBFDCB7; // 0x1010 AGC_Ctrl5
1737 pltmp[5] = 0x00caa333; // 0x1014 AGC_Ctrl6 1738 pltmp[5] = 0x00caa333; // 0x1014 AGC_Ctrl6
1738 pltmp[6] = 0xf6632112; // 0x1018 AGC_Ctrl7 1739 pltmp[6] = 0xf6632112; // 0x1018 AGC_Ctrl7
1739 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8 1740 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
1740 pltmp[8] = 0x04C43640; // 0x1020 AGC_Ctrl9 1741 pltmp[8] = 0x04C43640; // 0x1020 AGC_Ctrl9
1741 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10 1742 pltmp[9] = 0x00002A79; // 0x1024 AGC_Ctrl10
1742 pltmp[10] = 0x40000228; 1743 pltmp[10] = 0x40000228;
1743 pltmp[11] = 0x232A9F30;// 0x102c A_ACQ_Ctrl 1744 pltmp[11] = 0x232A9F30;// 0x102c A_ACQ_Ctrl
1744 reg->BB2c = 0x232A9F30; 1745 reg->BB2c = 0x232A9F30;
1745 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT ); 1746 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
1746 1747
1747 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl 1748 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
1748 reg->BB30 = 0x00002C54; 1749 reg->BB30 = 0x00002C54;
1749 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl 1750 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
1750 pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl 1751 pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl
1751 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter 1752 pltmp[3] = 0x00000000; // 0x103c 11a TX LS filter
1752 reg->BB3c = 0x00000000; 1753 reg->BB3c = 0x00000000;
1753 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter 1754 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
1754 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter 1755 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
1755 pltmp[6] = 0x00453B24; // 0x1048 11b TX RC filter 1756 pltmp[6] = 0x00453B24; // 0x1048 11b TX RC filter
1756 pltmp[7] = 0x0E00FEFF; // 0x104c 11b TX RC filter 1757 pltmp[7] = 0x0E00FEFF; // 0x104c 11b TX RC filter
1757 pltmp[8] = 0x27106200; // 0x1050 MODE_Ctrl 1758 pltmp[8] = 0x27106200; // 0x1050 MODE_Ctrl
1758 reg->BB50 = 0x27106200; 1759 reg->BB50 = 0x27106200;
1759 pltmp[9] = 0; // 0x1054 1760 pltmp[9] = 0; // 0x1054
1760 reg->BB54 = 0x00000000; 1761 reg->BB54 = 0x00000000;
1761 pltmp[10] = 0x64645252; // 0x1058 IQ_Alpha 1762 pltmp[10] = 0x64645252; // 0x1058 IQ_Alpha
1762 reg->BB58 = 0x64645252; 1763 reg->BB58 = 0x64645252;
1763 pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel 1764 pltmp[11] = 0xAA0AC000; // 0x105c DC_Cancel
1764 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT ); 1765 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
1765 */ 1766 */
1766 BBProcessor_AL7230_2400( pHwData ); 1767 BBProcessor_AL7230_2400( pHwData );
1767 1768
1768 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 ); 1769 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
1769 break; 1770 break;
1770 1771
1771 case RF_WB_242: 1772 case RF_WB_242:
1772 case RF_WB_242_1: // 20060619.5 Add 1773 case RF_WB_242_1: // 20060619.5 Add
1773 1774
1774 pltmp[0] = 0x16A8525D; // 0x1000 AGC_Ctrl1 1775 pltmp[0] = 0x16A8525D; // 0x1000 AGC_Ctrl1
1775 pltmp[1] = 0x9AFF9ABA; // 0x1004 AGC_Ctrl2 1776 pltmp[1] = 0x9AFF9ABA; // 0x1004 AGC_Ctrl2
1776 pltmp[2] = 0x55D00A04; // 0x1008 AGC_Ctrl3 1777 pltmp[2] = 0x55D00A04; // 0x1008 AGC_Ctrl3
1777 pltmp[3] = 0xEEE91C32; // 0x100c AGC_Ctrl4 1778 pltmp[3] = 0xEEE91C32; // 0x100c AGC_Ctrl4
1778 reg->BB0C = 0xEEE91C32; 1779 reg->BB0C = 0xEEE91C32;
1779 pltmp[4] = 0x0FACDCC5; // 0x1010 AGC_Ctrl5 1780 pltmp[4] = 0x0FACDCC5; // 0x1010 AGC_Ctrl5
1780 pltmp[5] = 0x000AA344; // 0x1014 AGC_Ctrl6 1781 pltmp[5] = 0x000AA344; // 0x1014 AGC_Ctrl6
1781 pltmp[6] = 0x22222221; // 0x1018 AGC_Ctrl7 1782 pltmp[6] = 0x22222221; // 0x1018 AGC_Ctrl7
1782 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8 1783 pltmp[7] = 0x0FA3F0ED; // 0x101c AGC_Ctrl8
1783 pltmp[8] = 0x04CC3440; // 20051018 0x03CB3440; // 0x1020 AGC_Ctrl9 20051014 0x03C33440 1784 pltmp[8] = 0x04CC3440; // 20051018 0x03CB3440; // 0x1020 AGC_Ctrl9 20051014 0x03C33440
1784 pltmp[9] = 0xA9002A79; // 0x1024 AGC_Ctrl10 1785 pltmp[9] = 0xA9002A79; // 0x1024 AGC_Ctrl10
1785 pltmp[10] = 0x40000528; // 0x1028 1786 pltmp[10] = 0x40000528; // 0x1028
1786 pltmp[11] = 0x23457F30; // 0x102c A_ACQ_Ctrl 1787 pltmp[11] = 0x23457F30; // 0x102c A_ACQ_Ctrl
1787 reg->BB2C = 0x23457F30; 1788 reg->BB2C = 0x23457F30;
1788 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT ); 1789 Wb35Reg_BurstWrite( pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT );
1789 1790
1790 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl 1791 pltmp[0] = 0x00002C54; // 0x1030 B_ACQ_Ctrl
1791 reg->BB30 = 0x00002C54; 1792 reg->BB30 = 0x00002C54;
1792 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl 1793 pltmp[1] = 0x00C0D6C5; // 0x1034 A_TXRX_Ctrl
1793 pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl 1794 pltmp[2] = 0x5B2C8769; // 0x1038 B_TXRX_Ctrl
1794 pltmp[3] = pHwData->BB3c_cal; // 0x103c 11a TX LS filter 1795 pltmp[3] = pHwData->BB3c_cal; // 0x103c 11a TX LS filter
1795 reg->BB3C = pHwData->BB3c_cal; 1796 reg->BB3C = pHwData->BB3c_cal;
1796 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter 1797 pltmp[4] = 0x00003F29; // 0x1040 11a TX LS filter
1797 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter 1798 pltmp[5] = 0x0EFEFBFE; // 0x1044 11a TX LS filter
1798 pltmp[6] = BB48_DEFAULT_WB242_11G; // 0x1048 11b TX RC filter 20060613.2 1799 pltmp[6] = BB48_DEFAULT_WB242_11G; // 0x1048 11b TX RC filter 20060613.2
1799 reg->BB48 = BB48_DEFAULT_WB242_11G; // 20060613.1 20060613.2 1800 reg->BB48 = BB48_DEFAULT_WB242_11G; // 20060613.1 20060613.2
1800 pltmp[7] = BB4C_DEFAULT_WB242_11G; // 0x104c 11b TX RC filter 20060613.2 1801 pltmp[7] = BB4C_DEFAULT_WB242_11G; // 0x104c 11b TX RC filter 20060613.2
1801 reg->BB4C = BB4C_DEFAULT_WB242_11G; // 20060613.1 20060613.2 1802 reg->BB4C = BB4C_DEFAULT_WB242_11G; // 20060613.1 20060613.2
1802 pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl 1803 pltmp[8] = 0x27106208; // 0x1050 MODE_Ctrl
1803 reg->BB50 = 0x27106208; 1804 reg->BB50 = 0x27106208;
1804 pltmp[9] = pHwData->BB54_cal; // 0x1054 1805 pltmp[9] = pHwData->BB54_cal; // 0x1054
1805 reg->BB54 = pHwData->BB54_cal; 1806 reg->BB54 = pHwData->BB54_cal;
1806 pltmp[10] = 0x52523131; // 0x1058 IQ_Alpha 1807 pltmp[10] = 0x52523131; // 0x1058 IQ_Alpha
1807 reg->BB58 = 0x52523131; 1808 reg->BB58 = 0x52523131;
1808 pltmp[11] = 0xAA0AC000; // 20060825 0xAA2AC000; // 0x105c DC_Cancel 1809 pltmp[11] = 0xAA0AC000; // 20060825 0xAA2AC000; // 0x105c DC_Cancel
1809 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT ); 1810 Wb35Reg_BurstWrite( pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT );
1810 1811
1811 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 ); 1812 Wb35Reg_Write( pHwData, 0x1070, 0x00000045 );
1812 break; 1813 break;
1813 } 1814 }
1814 1815
1815 // Fill the LNA table 1816 // Fill the LNA table
1816 reg->LNAValue[0] = (u8)(reg->BB0C & 0xff); 1817 reg->LNAValue[0] = (u8)(reg->BB0C & 0xff);
1817 reg->LNAValue[1] = 0; 1818 reg->LNAValue[1] = 0;
1818 reg->LNAValue[2] = (u8)((reg->BB0C & 0xff00)>>8); 1819 reg->LNAValue[2] = (u8)((reg->BB0C & 0xff00)>>8);
1819 reg->LNAValue[3] = 0; 1820 reg->LNAValue[3] = 0;
1820 1821
1821 // Fill SQ3 table 1822 // Fill SQ3 table
1822 for( i=0; i<MAX_SQ3_FILTER_SIZE; i++ ) 1823 for( i=0; i<MAX_SQ3_FILTER_SIZE; i++ )
1823 reg->SQ3_filter[i] = 0x2f; // half of Bit 0 ~ 6 1824 reg->SQ3_filter[i] = 0x2f; // half of Bit 0 ~ 6
1824 } 1825 }
1825 1826
1826 void set_tx_power_per_channel_max2829( phw_data_t pHwData, ChanInfo Channel) 1827 void set_tx_power_per_channel_max2829( phw_data_t pHwData, ChanInfo Channel)
1827 { 1828 {
1828 RFSynthesizer_SetPowerIndex( pHwData, 100 ); // 20060620.1 Modify 1829 RFSynthesizer_SetPowerIndex( pHwData, 100 ); // 20060620.1 Modify
1829 } 1830 }
1830 1831
1831 void set_tx_power_per_channel_al2230( phw_data_t pHwData, ChanInfo Channel ) 1832 void set_tx_power_per_channel_al2230( phw_data_t pHwData, ChanInfo Channel )
1832 { 1833 {
1833 u8 index = 100; 1834 u8 index = 100;
1834 1835
1835 if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff) // 20060620.1 Add 1836 if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff) // 20060620.1 Add
1836 index = pHwData->TxVgaFor24[Channel.ChanNo - 1]; 1837 index = pHwData->TxVgaFor24[Channel.ChanNo - 1];
1837 1838
1838 RFSynthesizer_SetPowerIndex( pHwData, index ); 1839 RFSynthesizer_SetPowerIndex( pHwData, index );
1839 } 1840 }
1840 1841
1841 void set_tx_power_per_channel_al7230( phw_data_t pHwData, ChanInfo Channel) 1842 void set_tx_power_per_channel_al7230( phw_data_t pHwData, ChanInfo Channel)
1842 { 1843 {
1843 u8 i, index = 100; 1844 u8 i, index = 100;
1844 1845
1845 switch ( Channel.band ) 1846 switch ( Channel.band )
1846 { 1847 {
1847 case BAND_TYPE_DSSS: 1848 case BAND_TYPE_DSSS:
1848 case BAND_TYPE_OFDM_24: 1849 case BAND_TYPE_OFDM_24:
1849 { 1850 {
1850 if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff) 1851 if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff)
1851 index = pHwData->TxVgaFor24[Channel.ChanNo - 1]; 1852 index = pHwData->TxVgaFor24[Channel.ChanNo - 1];
1852 } 1853 }
1853 break; 1854 break;
1854 case BAND_TYPE_OFDM_5: 1855 case BAND_TYPE_OFDM_5:
1855 { 1856 {
1856 for (i =0; i<35; i++) 1857 for (i =0; i<35; i++)
1857 { 1858 {
1858 if (Channel.ChanNo == pHwData->TxVgaFor50[i].ChanNo) 1859 if (Channel.ChanNo == pHwData->TxVgaFor50[i].ChanNo)
1859 { 1860 {
1860 if (pHwData->TxVgaFor50[i].TxVgaValue != 0xff) 1861 if (pHwData->TxVgaFor50[i].TxVgaValue != 0xff)
1861 index = pHwData->TxVgaFor50[i].TxVgaValue; 1862 index = pHwData->TxVgaFor50[i].TxVgaValue;
1862 break; 1863 break;
1863 } 1864 }
1864 } 1865 }
1865 } 1866 }
1866 break; 1867 break;
1867 } 1868 }
1868 RFSynthesizer_SetPowerIndex( pHwData, index ); 1869 RFSynthesizer_SetPowerIndex( pHwData, index );
1869 } 1870 }
1870 1871
1871 void set_tx_power_per_channel_wb242( phw_data_t pHwData, ChanInfo Channel) 1872 void set_tx_power_per_channel_wb242( phw_data_t pHwData, ChanInfo Channel)
1872 { 1873 {
1873 u8 index = 100; 1874 u8 index = 100;
1874 1875
1875 switch ( Channel.band ) 1876 switch ( Channel.band )
1876 { 1877 {
1877 case BAND_TYPE_DSSS: 1878 case BAND_TYPE_DSSS:
1878 case BAND_TYPE_OFDM_24: 1879 case BAND_TYPE_OFDM_24:
1879 { 1880 {
1880 if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff) 1881 if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff)
1881 index = pHwData->TxVgaFor24[Channel.ChanNo - 1]; 1882 index = pHwData->TxVgaFor24[Channel.ChanNo - 1];
1882 } 1883 }
1883 break; 1884 break;
1884 case BAND_TYPE_OFDM_5: 1885 case BAND_TYPE_OFDM_5:
1885 break; 1886 break;
1886 } 1887 }
1887 RFSynthesizer_SetPowerIndex( pHwData, index ); 1888 RFSynthesizer_SetPowerIndex( pHwData, index );
1888 } 1889 }
1889 1890
1890 //============================================================================================================= 1891 //=============================================================================================================
1891 // RFSynthesizer_SwitchingChannel -- 1892 // RFSynthesizer_SwitchingChannel --
1892 // 1893 //
1893 // Description: 1894 // Description:
1894 // Swithch the RF channel. 1895 // Swithch the RF channel.
1895 // 1896 //
1896 // Arguments: 1897 // Arguments:
1897 // pHwData - Handle of the USB Device. 1898 // pHwData - Handle of the USB Device.
1898 // Channel - The channel no. 1899 // Channel - The channel no.
1899 // 1900 //
1900 // Return values: 1901 // Return values:
1901 // None. 1902 // None.
1902 //============================================================================================================= 1903 //=============================================================================================================
1903 void 1904 void
1904 RFSynthesizer_SwitchingChannel( phw_data_t pHwData, ChanInfo Channel ) 1905 RFSynthesizer_SwitchingChannel( phw_data_t pHwData, ChanInfo Channel )
1905 { 1906 {
1906 struct wb35_reg *reg = &pHwData->reg; 1907 struct wb35_reg *reg = &pHwData->reg;
1907 u32 pltmp[16]; // The 16 is the maximum capability of hardware 1908 u32 pltmp[16]; // The 16 is the maximum capability of hardware
1908 u32 count, ltmp; 1909 u32 count, ltmp;
1909 u8 i, j, number; 1910 u8 i, j, number;
1910 u8 ChnlTmp; 1911 u8 ChnlTmp;
1911 1912
1912 switch( pHwData->phy_type ) 1913 switch( pHwData->phy_type )
1913 { 1914 {
1914 case RF_MAXIM_2825: 1915 case RF_MAXIM_2825:
1915 case RF_MAXIM_V1: // 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331) 1916 case RF_MAXIM_V1: // 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331)
1916 1917
1917 if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 13 1918 if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 13
1918 { 1919 {
1919 for( i=0; i<3; i++ ) 1920 for( i=0; i<3; i++ )
1920 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2825_channel_data_24[Channel.ChanNo-1][i], 18); 1921 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2825_channel_data_24[Channel.ChanNo-1][i], 18);
1921 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT ); 1922 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
1922 } 1923 }
1923 RFSynthesizer_SetPowerIndex( pHwData, 100 ); 1924 RFSynthesizer_SetPowerIndex( pHwData, 100 );
1924 break; 1925 break;
1925 1926
1926 case RF_MAXIM_2827: 1927 case RF_MAXIM_2827:
1927 1928
1928 if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 13 1929 if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 13
1929 { 1930 {
1930 for( i=0; i<3; i++ ) 1931 for( i=0; i<3; i++ )
1931 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_channel_data_24[Channel.ChanNo-1][i], 18); 1932 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_channel_data_24[Channel.ChanNo-1][i], 18);
1932 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT ); 1933 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
1933 } 1934 }
1934 else if( Channel.band == BAND_TYPE_OFDM_5 ) // channel 36 ~ 64 1935 else if( Channel.band == BAND_TYPE_OFDM_5 ) // channel 36 ~ 64
1935 { 1936 {
1936 ChnlTmp = (Channel.ChanNo - 36) / 4; 1937 ChnlTmp = (Channel.ChanNo - 36) / 4;
1937 for( i=0; i<3; i++ ) 1938 for( i=0; i<3; i++ )
1938 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_channel_data_50[ChnlTmp][i], 18); 1939 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_channel_data_50[ChnlTmp][i], 18);
1939 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT ); 1940 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
1940 } 1941 }
1941 RFSynthesizer_SetPowerIndex( pHwData, 100 ); 1942 RFSynthesizer_SetPowerIndex( pHwData, 100 );
1942 break; 1943 break;
1943 1944
1944 case RF_MAXIM_2828: 1945 case RF_MAXIM_2828:
1945 1946
1946 if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 13 1947 if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 13
1947 { 1948 {
1948 for( i=0; i<3; i++ ) 1949 for( i=0; i<3; i++ )
1949 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_channel_data_24[Channel.ChanNo-1][i], 18); 1950 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_channel_data_24[Channel.ChanNo-1][i], 18);
1950 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT ); 1951 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
1951 } 1952 }
1952 else if( Channel.band == BAND_TYPE_OFDM_5 ) // channel 36 ~ 64 1953 else if( Channel.band == BAND_TYPE_OFDM_5 ) // channel 36 ~ 64
1953 { 1954 {
1954 ChnlTmp = (Channel.ChanNo - 36) / 4; 1955 ChnlTmp = (Channel.ChanNo - 36) / 4;
1955 for ( i = 0; i < 3; i++) 1956 for ( i = 0; i < 3; i++)
1956 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_channel_data_50[ChnlTmp][i], 18); 1957 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_channel_data_50[ChnlTmp][i], 18);
1957 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT ); 1958 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
1958 } 1959 }
1959 RFSynthesizer_SetPowerIndex( pHwData, 100 ); 1960 RFSynthesizer_SetPowerIndex( pHwData, 100 );
1960 break; 1961 break;
1961 1962
1962 case RF_MAXIM_2829: 1963 case RF_MAXIM_2829:
1963 1964
1964 if( Channel.band <= BAND_TYPE_OFDM_24) 1965 if( Channel.band <= BAND_TYPE_OFDM_24)
1965 { 1966 {
1966 for( i=0; i<3; i++ ) 1967 for( i=0; i<3; i++ )
1967 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2829_channel_data_24[Channel.ChanNo-1][i], 18); 1968 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2829_channel_data_24[Channel.ChanNo-1][i], 18);
1968 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT ); 1969 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
1969 } 1970 }
1970 else if( Channel.band == BAND_TYPE_OFDM_5 ) 1971 else if( Channel.band == BAND_TYPE_OFDM_5 )
1971 { 1972 {
1972 count = sizeof(max2829_channel_data_50) / sizeof(max2829_channel_data_50[0]); 1973 count = sizeof(max2829_channel_data_50) / sizeof(max2829_channel_data_50[0]);
1973 1974
1974 for( i=0; i<count; i++ ) 1975 for( i=0; i<count; i++ )
1975 { 1976 {
1976 if( max2829_channel_data_50[i][0] == Channel.ChanNo ) 1977 if( max2829_channel_data_50[i][0] == Channel.ChanNo )
1977 { 1978 {
1978 for( j=0; j<3; j++ ) 1979 for( j=0; j<3; j++ )
1979 pltmp[j] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2829_channel_data_50[i][j+1], 18); 1980 pltmp[j] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2829_channel_data_50[i][j+1], 18);
1980 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT ); 1981 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
1981 1982
1982 if( (max2829_channel_data_50[i][3] & 0x3FFFF) == 0x2A946 ) 1983 if( (max2829_channel_data_50[i][3] & 0x3FFFF) == 0x2A946 )
1983 { 1984 {
1984 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( (5<<18)|0x2A906, 18); 1985 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( (5<<18)|0x2A906, 18);
1985 Wb35Reg_Write( pHwData, 0x0864, ltmp ); 1986 Wb35Reg_Write( pHwData, 0x0864, ltmp );
1986 } 1987 }
1987 else // 0x2A9C6 1988 else // 0x2A9C6
1988 { 1989 {
1989 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( (5<<18)|0x2A986, 18); 1990 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( (5<<18)|0x2A986, 18);
1990 Wb35Reg_Write( pHwData, 0x0864, ltmp ); 1991 Wb35Reg_Write( pHwData, 0x0864, ltmp );
1991 } 1992 }
1992 } 1993 }
1993 } 1994 }
1994 } 1995 }
1995 set_tx_power_per_channel_max2829( pHwData, Channel ); 1996 set_tx_power_per_channel_max2829( pHwData, Channel );
1996 break; 1997 break;
1997 1998
1998 case RF_AIROHA_2230: 1999 case RF_AIROHA_2230:
1999 case RF_AIROHA_2230S: // 20060420 Add this 2000 case RF_AIROHA_2230S: // 20060420 Add this
2000 2001
2001 if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 14 2002 if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 14
2002 { 2003 {
2003 for( i=0; i<2; i++ ) 2004 for( i=0; i<2; i++ )
2004 pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_channel_data_24[Channel.ChanNo-1][i], 20); 2005 pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_channel_data_24[Channel.ChanNo-1][i], 20);
2005 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 2, NO_INCREMENT ); 2006 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 2, NO_INCREMENT );
2006 } 2007 }
2007 set_tx_power_per_channel_al2230( pHwData, Channel ); 2008 set_tx_power_per_channel_al2230( pHwData, Channel );
2008 break; 2009 break;
2009 2010
2010 case RF_AIROHA_7230: 2011 case RF_AIROHA_7230:
2011 2012
2012 //Start to fill RF parameters, PLL_ON should be pulled low. 2013 //Start to fill RF parameters, PLL_ON should be pulled low.
2013 //Wb35Reg_Write( pHwData, 0x03dc, 0x00000000 ); 2014 //Wb35Reg_Write( pHwData, 0x03dc, 0x00000000 );
2014 //WBDEBUG(("* PLL_ON low\n")); 2015 //WBDEBUG(("* PLL_ON low\n"));
2015 2016
2016 //Channel independent registers 2017 //Channel independent registers
2017 if( Channel.band != pHwData->band) 2018 if( Channel.band != pHwData->band)
2018 { 2019 {
2019 if (Channel.band <= BAND_TYPE_OFDM_24) 2020 if (Channel.band <= BAND_TYPE_OFDM_24)
2020 { 2021 {
2021 //Update BB register 2022 //Update BB register
2022 BBProcessor_AL7230_2400(pHwData); 2023 BBProcessor_AL7230_2400(pHwData);
2023 2024
2024 number = sizeof(al7230_rf_data_24)/sizeof(al7230_rf_data_24[0]); 2025 number = sizeof(al7230_rf_data_24)/sizeof(al7230_rf_data_24[0]);
2025 Set_ChanIndep_RfData_al7230_24(pHwData, pltmp, number); 2026 Set_ChanIndep_RfData_al7230_24(pHwData, pltmp, number);
2026 } 2027 }
2027 else 2028 else
2028 { 2029 {
2029 //Update BB register 2030 //Update BB register
2030 BBProcessor_AL7230_5000(pHwData); 2031 BBProcessor_AL7230_5000(pHwData);
2031 2032
2032 number = sizeof(al7230_rf_data_50)/sizeof(al7230_rf_data_50[0]); 2033 number = sizeof(al7230_rf_data_50)/sizeof(al7230_rf_data_50[0]);
2033 Set_ChanIndep_RfData_al7230_50(pHwData, pltmp, number); 2034 Set_ChanIndep_RfData_al7230_50(pHwData, pltmp, number);
2034 } 2035 }
2035 2036
2036 // Write to register. number must less and equal than 16 2037 // Write to register. number must less and equal than 16
2037 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, number, NO_INCREMENT ); 2038 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, number, NO_INCREMENT );
2038 #ifdef _PE_STATE_DUMP_ 2039 #ifdef _PE_STATE_DUMP_
2039 WBDEBUG(("Band changed\n")); 2040 WBDEBUG(("Band changed\n"));
2040 #endif 2041 #endif
2041 } 2042 }
2042 2043
2043 if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 14 2044 if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 14
2044 { 2045 {
2045 for( i=0; i<2; i++ ) 2046 for( i=0; i<2; i++ )
2046 pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_channel_data_24[Channel.ChanNo-1][i]&0xffffff); 2047 pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_channel_data_24[Channel.ChanNo-1][i]&0xffffff);
2047 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 2, NO_INCREMENT ); 2048 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 2, NO_INCREMENT );
2048 } 2049 }
2049 else if( Channel.band == BAND_TYPE_OFDM_5 ) 2050 else if( Channel.band == BAND_TYPE_OFDM_5 )
2050 { 2051 {
2051 //Update Reg12 2052 //Update Reg12
2052 if ((Channel.ChanNo > 64) && (Channel.ChanNo <= 165)) 2053 if ((Channel.ChanNo > 64) && (Channel.ChanNo <= 165))
2053 { 2054 {
2054 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x00143c; 2055 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x00143c;
2055 Wb35Reg_Write( pHwData, 0x0864, ltmp ); 2056 Wb35Reg_Write( pHwData, 0x0864, ltmp );
2056 } 2057 }
2057 else //reg12 = 0x00147c at Channel 4920 ~ 5320 2058 else //reg12 = 0x00147c at Channel 4920 ~ 5320
2058 { 2059 {
2059 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x00147c; 2060 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x00147c;
2060 Wb35Reg_Write( pHwData, 0x0864, ltmp ); 2061 Wb35Reg_Write( pHwData, 0x0864, ltmp );
2061 } 2062 }
2062 2063
2063 count = sizeof(al7230_channel_data_5) / sizeof(al7230_channel_data_5[0]); 2064 count = sizeof(al7230_channel_data_5) / sizeof(al7230_channel_data_5[0]);
2064 2065
2065 for (i=0; i<count; i++) 2066 for (i=0; i<count; i++)
2066 { 2067 {
2067 if (al7230_channel_data_5[i][0] == Channel.ChanNo) 2068 if (al7230_channel_data_5[i][0] == Channel.ChanNo)
2068 { 2069 {
2069 for( j=0; j<3; j++ ) 2070 for( j=0; j<3; j++ )
2070 pltmp[j] = (1 << 31) | (0 << 30) | (24 << 24) | ( al7230_channel_data_5[i][j+1]&0xffffff); 2071 pltmp[j] = (1 << 31) | (0 << 30) | (24 << 24) | ( al7230_channel_data_5[i][j+1]&0xffffff);
2071 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT ); 2072 Wb35Reg_BurstWrite( pHwData, 0x0864, pltmp, 3, NO_INCREMENT );
2072 } 2073 }
2073 } 2074 }
2074 } 2075 }
2075 set_tx_power_per_channel_al7230(pHwData, Channel); 2076 set_tx_power_per_channel_al7230(pHwData, Channel);
2076 break; 2077 break;
2077 2078
2078 case RF_WB_242: 2079 case RF_WB_242:
2079 case RF_WB_242_1: // 20060619.5 Add 2080 case RF_WB_242_1: // 20060619.5 Add
2080 2081
2081 if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 14 2082 if( Channel.band <= BAND_TYPE_OFDM_24 ) // channel 1 ~ 14
2082 { 2083 {
2083 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( w89rf242_channel_data_24[Channel.ChanNo-1][0], 24); 2084 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( w89rf242_channel_data_24[Channel.ChanNo-1][0], 24);
2084 Wb35Reg_Write( pHwData, 0x864, ltmp ); 2085 Wb35Reg_Write( pHwData, 0x864, ltmp );
2085 } 2086 }
2086 set_tx_power_per_channel_wb242(pHwData, Channel); 2087 set_tx_power_per_channel_wb242(pHwData, Channel);
2087 break; 2088 break;
2088 } 2089 }
2089 2090
2090 if( Channel.band <= BAND_TYPE_OFDM_24 ) 2091 if( Channel.band <= BAND_TYPE_OFDM_24 )
2091 { 2092 {
2092 // BB: select 2.4 GHz, bit[12-11]=00 2093 // BB: select 2.4 GHz, bit[12-11]=00
2093 reg->BB50 &= ~(BIT(11)|BIT(12)); 2094 reg->BB50 &= ~(BIT(11)|BIT(12));
2094 Wb35Reg_Write( pHwData, 0x1050, reg->BB50 ); // MODE_Ctrl 2095 Wb35Reg_Write( pHwData, 0x1050, reg->BB50 ); // MODE_Ctrl
2095 // MAC: select 2.4 GHz, bit[5]=0 2096 // MAC: select 2.4 GHz, bit[5]=0
2096 reg->M78_ERPInformation &= ~BIT(5); 2097 reg->M78_ERPInformation &= ~BIT(5);
2097 Wb35Reg_Write( pHwData, 0x0878, reg->M78_ERPInformation ); 2098 Wb35Reg_Write( pHwData, 0x0878, reg->M78_ERPInformation );
2098 // enable 11b Baseband 2099 // enable 11b Baseband
2099 reg->BB30 &= ~BIT(31); 2100 reg->BB30 &= ~BIT(31);
2100 Wb35Reg_Write( pHwData, 0x1030, reg->BB30 ); 2101 Wb35Reg_Write( pHwData, 0x1030, reg->BB30 );
2101 } 2102 }
2102 else if( (Channel.band == BAND_TYPE_OFDM_5) ) 2103 else if( (Channel.band == BAND_TYPE_OFDM_5) )
2103 { 2104 {
2104 // BB: select 5 GHz 2105 // BB: select 5 GHz
2105 reg->BB50 &= ~(BIT(11)|BIT(12)); 2106 reg->BB50 &= ~(BIT(11)|BIT(12));
2106 if (Channel.ChanNo <=64 ) 2107 if (Channel.ChanNo <=64 )
2107 reg->BB50 |= BIT(12); // 10-5.25GHz 2108 reg->BB50 |= BIT(12); // 10-5.25GHz
2108 else if ((Channel.ChanNo >= 100) && (Channel.ChanNo <= 124)) 2109 else if ((Channel.ChanNo >= 100) && (Channel.ChanNo <= 124))
2109 reg->BB50 |= BIT(11); // 01-5.48GHz 2110 reg->BB50 |= BIT(11); // 01-5.48GHz
2110 else if ((Channel.ChanNo >=128) && (Channel.ChanNo <= 161)) 2111 else if ((Channel.ChanNo >=128) && (Channel.ChanNo <= 161))
2111 reg->BB50 |= (BIT(12)|BIT(11)); // 11-5.775GHz 2112 reg->BB50 |= (BIT(12)|BIT(11)); // 11-5.775GHz
2112 else //Chan 184 ~ 196 will use bit[12-11] = 10 in version sh-src-1.2.25 2113 else //Chan 184 ~ 196 will use bit[12-11] = 10 in version sh-src-1.2.25
2113 reg->BB50 |= BIT(12); 2114 reg->BB50 |= BIT(12);
2114 Wb35Reg_Write( pHwData, 0x1050, reg->BB50 ); // MODE_Ctrl 2115 Wb35Reg_Write( pHwData, 0x1050, reg->BB50 ); // MODE_Ctrl
2115 2116
2116 //(1) M78 should alway use 2.4G setting when using RF_AIROHA_7230 2117 //(1) M78 should alway use 2.4G setting when using RF_AIROHA_7230
2117 //(2) BB30 has been updated previously. 2118 //(2) BB30 has been updated previously.
2118 if (pHwData->phy_type != RF_AIROHA_7230) 2119 if (pHwData->phy_type != RF_AIROHA_7230)
2119 { 2120 {
2120 // MAC: select 5 GHz, bit[5]=1 2121 // MAC: select 5 GHz, bit[5]=1
2121 reg->M78_ERPInformation |= BIT(5); 2122 reg->M78_ERPInformation |= BIT(5);
2122 Wb35Reg_Write( pHwData, 0x0878, reg->M78_ERPInformation ); 2123 Wb35Reg_Write( pHwData, 0x0878, reg->M78_ERPInformation );
2123 2124
2124 // disable 11b Baseband 2125 // disable 11b Baseband
2125 reg->BB30 |= BIT(31); 2126 reg->BB30 |= BIT(31);
2126 Wb35Reg_Write( pHwData, 0x1030, reg->BB30 ); 2127 Wb35Reg_Write( pHwData, 0x1030, reg->BB30 );
2127 } 2128 }
2128 } 2129 }
2129 } 2130 }
2130 2131
2131 //Set the tx power directly from DUT GUI, not from the EEPROM. Return the current setting 2132 //Set the tx power directly from DUT GUI, not from the EEPROM. Return the current setting
2132 u8 RFSynthesizer_SetPowerIndex( phw_data_t pHwData, u8 PowerIndex ) 2133 u8 RFSynthesizer_SetPowerIndex( phw_data_t pHwData, u8 PowerIndex )
2133 { 2134 {
2134 u32 Band = pHwData->band; 2135 u32 Band = pHwData->band;
2135 u8 index=0; 2136 u8 index=0;
2136 2137
2137 if( pHwData->power_index == PowerIndex ) // 20060620.1 Add 2138 if( pHwData->power_index == PowerIndex ) // 20060620.1 Add
2138 return PowerIndex; 2139 return PowerIndex;
2139 2140
2140 if (RF_MAXIM_2825 == pHwData->phy_type) 2141 if (RF_MAXIM_2825 == pHwData->phy_type)
2141 { 2142 {
2142 // Channel 1 - 13 2143 // Channel 1 - 13
2143 index = RFSynthesizer_SetMaxim2825Power( pHwData, PowerIndex ); 2144 index = RFSynthesizer_SetMaxim2825Power( pHwData, PowerIndex );
2144 } 2145 }
2145 else if (RF_MAXIM_2827 == pHwData->phy_type) 2146 else if (RF_MAXIM_2827 == pHwData->phy_type)
2146 { 2147 {
2147 if( Band <= BAND_TYPE_OFDM_24 ) // Channel 1 - 13 2148 if( Band <= BAND_TYPE_OFDM_24 ) // Channel 1 - 13
2148 index = RFSynthesizer_SetMaxim2827_24Power( pHwData, PowerIndex ); 2149 index = RFSynthesizer_SetMaxim2827_24Power( pHwData, PowerIndex );
2149 else// if( Band == BAND_TYPE_OFDM_5 ) // Channel 36 - 64 2150 else// if( Band == BAND_TYPE_OFDM_5 ) // Channel 36 - 64
2150 index = RFSynthesizer_SetMaxim2827_50Power( pHwData, PowerIndex ); 2151 index = RFSynthesizer_SetMaxim2827_50Power( pHwData, PowerIndex );
2151 } 2152 }
2152 else if (RF_MAXIM_2828 == pHwData->phy_type) 2153 else if (RF_MAXIM_2828 == pHwData->phy_type)
2153 { 2154 {
2154 if( Band <= BAND_TYPE_OFDM_24 ) // Channel 1 - 13 2155 if( Band <= BAND_TYPE_OFDM_24 ) // Channel 1 - 13
2155 index = RFSynthesizer_SetMaxim2828_24Power( pHwData, PowerIndex ); 2156 index = RFSynthesizer_SetMaxim2828_24Power( pHwData, PowerIndex );
2156 else// if( Band == BAND_TYPE_OFDM_5 ) // Channel 36 - 64 2157 else// if( Band == BAND_TYPE_OFDM_5 ) // Channel 36 - 64
2157 index = RFSynthesizer_SetMaxim2828_50Power( pHwData, PowerIndex ); 2158 index = RFSynthesizer_SetMaxim2828_50Power( pHwData, PowerIndex );
2158 } 2159 }
2159 else if( RF_AIROHA_2230 == pHwData->phy_type ) 2160 else if( RF_AIROHA_2230 == pHwData->phy_type )
2160 { 2161 {
2161 //Power index: 0 ~ 63 // Channel 1 - 14 2162 //Power index: 0 ~ 63 // Channel 1 - 14
2162 index = RFSynthesizer_SetAiroha2230Power( pHwData, PowerIndex ); 2163 index = RFSynthesizer_SetAiroha2230Power( pHwData, PowerIndex );
2163 index = (u8)al2230_txvga_data[index][1]; 2164 index = (u8)al2230_txvga_data[index][1];
2164 } 2165 }
2165 else if( RF_AIROHA_2230S == pHwData->phy_type ) // 20060420 Add this 2166 else if( RF_AIROHA_2230S == pHwData->phy_type ) // 20060420 Add this
2166 { 2167 {
2167 //Power index: 0 ~ 63 // Channel 1 - 14 2168 //Power index: 0 ~ 63 // Channel 1 - 14
2168 index = RFSynthesizer_SetAiroha2230Power( pHwData, PowerIndex ); 2169 index = RFSynthesizer_SetAiroha2230Power( pHwData, PowerIndex );
2169 index = (u8)al2230_txvga_data[index][1]; 2170 index = (u8)al2230_txvga_data[index][1];
2170 } 2171 }
2171 else if( RF_AIROHA_7230 == pHwData->phy_type ) 2172 else if( RF_AIROHA_7230 == pHwData->phy_type )
2172 { 2173 {
2173 //Power index: 0 ~ 63 2174 //Power index: 0 ~ 63
2174 index = RFSynthesizer_SetAiroha7230Power( pHwData, PowerIndex ); 2175 index = RFSynthesizer_SetAiroha7230Power( pHwData, PowerIndex );
2175 index = (u8)al7230_txvga_data[index][1]; 2176 index = (u8)al7230_txvga_data[index][1];
2176 } 2177 }
2177 else if( (RF_WB_242 == pHwData->phy_type) || 2178 else if( (RF_WB_242 == pHwData->phy_type) ||
2178 (RF_WB_242_1 == pHwData->phy_type) ) // 20060619.5 Add 2179 (RF_WB_242_1 == pHwData->phy_type) ) // 20060619.5 Add
2179 { 2180 {
2180 //Power index: 0 ~ 19 for original. New range is 0 ~ 33 2181 //Power index: 0 ~ 19 for original. New range is 0 ~ 33
2181 index = RFSynthesizer_SetWinbond242Power( pHwData, PowerIndex ); 2182 index = RFSynthesizer_SetWinbond242Power( pHwData, PowerIndex );
2182 index = (u8)w89rf242_txvga_data[index][1]; 2183 index = (u8)w89rf242_txvga_data[index][1];
2183 } 2184 }
2184 2185
2185 pHwData->power_index = index; // Backup current 2186 pHwData->power_index = index; // Backup current
2186 return index; 2187 return index;
2187 } 2188 }
2188 2189
2189 //-- Sub function 2190 //-- Sub function
2190 u8 RFSynthesizer_SetMaxim2828_24Power( phw_data_t pHwData, u8 index ) 2191 u8 RFSynthesizer_SetMaxim2828_24Power( phw_data_t pHwData, u8 index )
2191 { 2192 {
2192 u32 PowerData; 2193 u32 PowerData;
2193 if( index > 1 ) index = 1; 2194 if( index > 1 ) index = 1;
2194 PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_power_data_24[index], 18); 2195 PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_power_data_24[index], 18);
2195 Wb35Reg_Write( pHwData, 0x0864, PowerData ); 2196 Wb35Reg_Write( pHwData, 0x0864, PowerData );
2196 return index; 2197 return index;
2197 } 2198 }
2198 //-- 2199 //--
2199 u8 RFSynthesizer_SetMaxim2828_50Power( phw_data_t pHwData, u8 index ) 2200 u8 RFSynthesizer_SetMaxim2828_50Power( phw_data_t pHwData, u8 index )
2200 { 2201 {
2201 u32 PowerData; 2202 u32 PowerData;
2202 if( index > 1 ) index = 1; 2203 if( index > 1 ) index = 1;
2203 PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_power_data_50[index], 18); 2204 PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2828_power_data_50[index], 18);
2204 Wb35Reg_Write( pHwData, 0x0864, PowerData ); 2205 Wb35Reg_Write( pHwData, 0x0864, PowerData );
2205 return index; 2206 return index;
2206 } 2207 }
2207 //-- 2208 //--
2208 u8 RFSynthesizer_SetMaxim2827_24Power( phw_data_t pHwData, u8 index ) 2209 u8 RFSynthesizer_SetMaxim2827_24Power( phw_data_t pHwData, u8 index )
2209 { 2210 {
2210 u32 PowerData; 2211 u32 PowerData;
2211 if( index > 1 ) index = 1; 2212 if( index > 1 ) index = 1;
2212 PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_power_data_24[index], 18); 2213 PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_power_data_24[index], 18);
2213 Wb35Reg_Write( pHwData, 0x0864, PowerData ); 2214 Wb35Reg_Write( pHwData, 0x0864, PowerData );
2214 return index; 2215 return index;
2215 } 2216 }
2216 //-- 2217 //--
2217 u8 RFSynthesizer_SetMaxim2827_50Power( phw_data_t pHwData, u8 index ) 2218 u8 RFSynthesizer_SetMaxim2827_50Power( phw_data_t pHwData, u8 index )
2218 { 2219 {
2219 u32 PowerData; 2220 u32 PowerData;
2220 if( index > 1 ) index = 1; 2221 if( index > 1 ) index = 1;
2221 PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_power_data_50[index], 18); 2222 PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2827_power_data_50[index], 18);
2222 Wb35Reg_Write( pHwData, 0x0864, PowerData ); 2223 Wb35Reg_Write( pHwData, 0x0864, PowerData );
2223 return index; 2224 return index;
2224 } 2225 }
2225 //-- 2226 //--
2226 u8 RFSynthesizer_SetMaxim2825Power( phw_data_t pHwData, u8 index ) 2227 u8 RFSynthesizer_SetMaxim2825Power( phw_data_t pHwData, u8 index )
2227 { 2228 {
2228 u32 PowerData; 2229 u32 PowerData;
2229 if( index > 1 ) index = 1; 2230 if( index > 1 ) index = 1;
2230 PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2825_power_data_24[index], 18); 2231 PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse( max2825_power_data_24[index], 18);
2231 Wb35Reg_Write( pHwData, 0x0864, PowerData ); 2232 Wb35Reg_Write( pHwData, 0x0864, PowerData );
2232 return index; 2233 return index;
2233 } 2234 }
2234 //-- 2235 //--
2235 u8 RFSynthesizer_SetAiroha2230Power( phw_data_t pHwData, u8 index ) 2236 u8 RFSynthesizer_SetAiroha2230Power( phw_data_t pHwData, u8 index )
2236 { 2237 {
2237 u32 PowerData; 2238 u32 PowerData;
2238 u8 i,count; 2239 u8 i,count;
2239 2240
2240 count = sizeof(al2230_txvga_data) / sizeof(al2230_txvga_data[0]); 2241 count = sizeof(al2230_txvga_data) / sizeof(al2230_txvga_data[0]);
2241 for (i=0; i<count; i++) 2242 for (i=0; i<count; i++)
2242 { 2243 {
2243 if (al2230_txvga_data[i][1] >= index) 2244 if (al2230_txvga_data[i][1] >= index)
2244 break; 2245 break;
2245 } 2246 }
2246 if (i == count) 2247 if (i == count)
2247 i--; 2248 i--;
2248 2249
2249 PowerData = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_txvga_data[i][0], 20); 2250 PowerData = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( al2230_txvga_data[i][0], 20);
2250 Wb35Reg_Write( pHwData, 0x0864, PowerData ); 2251 Wb35Reg_Write( pHwData, 0x0864, PowerData );
2251 return i; 2252 return i;
2252 } 2253 }
2253 //-- 2254 //--
2254 u8 RFSynthesizer_SetAiroha7230Power( phw_data_t pHwData, u8 index ) 2255 u8 RFSynthesizer_SetAiroha7230Power( phw_data_t pHwData, u8 index )
2255 { 2256 {
2256 u32 PowerData; 2257 u32 PowerData;
2257 u8 i,count; 2258 u8 i,count;
2258 2259
2259 //PowerData = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( airoha_power_data_24[index], 20); 2260 //PowerData = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse( airoha_power_data_24[index], 20);
2260 count = sizeof(al7230_txvga_data) / sizeof(al7230_txvga_data[0]); 2261 count = sizeof(al7230_txvga_data) / sizeof(al7230_txvga_data[0]);
2261 for (i=0; i<count; i++) 2262 for (i=0; i<count; i++)
2262 { 2263 {
2263 if (al7230_txvga_data[i][1] >= index) 2264 if (al7230_txvga_data[i][1] >= index)
2264 break; 2265 break;
2265 } 2266 }
2266 if (i == count) 2267 if (i == count)
2267 i--; 2268 i--;
2268 PowerData = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_txvga_data[i][0]&0xffffff); 2269 PowerData = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_txvga_data[i][0]&0xffffff);
2269 Wb35Reg_Write( pHwData, 0x0864, PowerData ); 2270 Wb35Reg_Write( pHwData, 0x0864, PowerData );
2270 return i; 2271 return i;
2271 } 2272 }
2272 2273
2273 u8 RFSynthesizer_SetWinbond242Power( phw_data_t pHwData, u8 index ) 2274 u8 RFSynthesizer_SetWinbond242Power( phw_data_t pHwData, u8 index )
2274 { 2275 {
2275 u32 PowerData; 2276 u32 PowerData;
2276 u8 i,count; 2277 u8 i,count;
2277 2278
2278 count = sizeof(w89rf242_txvga_data) / sizeof(w89rf242_txvga_data[0]); 2279 count = sizeof(w89rf242_txvga_data) / sizeof(w89rf242_txvga_data[0]);
2279 for (i=0; i<count; i++) 2280 for (i=0; i<count; i++)
2280 { 2281 {
2281 if (w89rf242_txvga_data[i][1] >= index) 2282 if (w89rf242_txvga_data[i][1] >= index)
2282 break; 2283 break;
2283 } 2284 }
2284 if (i == count) 2285 if (i == count)
2285 i--; 2286 i--;
2286 2287
2287 // Set TxVga into RF 2288 // Set TxVga into RF
2288 PowerData = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( w89rf242_txvga_data[i][0], 24); 2289 PowerData = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( w89rf242_txvga_data[i][0], 24);
2289 Wb35Reg_Write( pHwData, 0x0864, PowerData ); 2290 Wb35Reg_Write( pHwData, 0x0864, PowerData );
2290 2291
2291 // Update BB48 BB4C BB58 for high precision txvga 2292 // Update BB48 BB4C BB58 for high precision txvga
2292 Wb35Reg_Write( pHwData, 0x1048, w89rf242_txvga_data[i][2] ); 2293 Wb35Reg_Write( pHwData, 0x1048, w89rf242_txvga_data[i][2] );
2293 Wb35Reg_Write( pHwData, 0x104c, w89rf242_txvga_data[i][3] ); 2294 Wb35Reg_Write( pHwData, 0x104c, w89rf242_txvga_data[i][3] );
2294 Wb35Reg_Write( pHwData, 0x1058, w89rf242_txvga_data[i][4] ); 2295 Wb35Reg_Write( pHwData, 0x1058, w89rf242_txvga_data[i][4] );
2295 2296
2296 // Rf vga 0 ~ 3 for temperature compensate. It will affect the scan Bss. 2297 // Rf vga 0 ~ 3 for temperature compensate. It will affect the scan Bss.
2297 // The i value equals to 8 or 7 usually. So It's not necessary to setup this RF register. 2298 // The i value equals to 8 or 7 usually. So It's not necessary to setup this RF register.
2298 // if( i <= 3 ) 2299 // if( i <= 3 )
2299 // PowerData = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( 0x000024, 24 ); 2300 // PowerData = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( 0x000024, 24 );
2300 // else 2301 // else
2301 // PowerData = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( 0x001824, 24 ); 2302 // PowerData = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse( 0x001824, 24 );
2302 // Wb35Reg_Write( pHwData, 0x0864, PowerData ); 2303 // Wb35Reg_Write( pHwData, 0x0864, PowerData );
2303 return i; 2304 return i;
2304 } 2305 }
2305 2306
2306 //=========================================================================================================== 2307 //===========================================================================================================
2307 // Dxx_initial -- 2308 // Dxx_initial --
2308 // Mxx_initial -- 2309 // Mxx_initial --
2309 // 2310 //
2310 // Routine Description: 2311 // Routine Description:
2311 // Initial the hardware setting and module variable 2312 // Initial the hardware setting and module variable
2312 // 2313 //
2313 //=========================================================================================================== 2314 //===========================================================================================================
2314 void Dxx_initial( phw_data_t pHwData ) 2315 void Dxx_initial( phw_data_t pHwData )
2315 { 2316 {
2316 struct wb35_reg *reg = &pHwData->reg; 2317 struct wb35_reg *reg = &pHwData->reg;
2317 2318
2318 // Old IC:Single mode only. 2319 // Old IC:Single mode only.
2319 // New IC: operation decide by Software set bit[4]. 1:multiple 0: single 2320 // New IC: operation decide by Software set bit[4]. 1:multiple 0: single
2320 reg->D00_DmaControl = 0xc0000004; //Txon, Rxon, multiple Rx for new 4k DMA 2321 reg->D00_DmaControl = 0xc0000004; //Txon, Rxon, multiple Rx for new 4k DMA
2321 //Txon, Rxon, single Rx for old 8k ASIC 2322 //Txon, Rxon, single Rx for old 8k ASIC
2322 if( !HAL_USB_MODE_BURST( pHwData ) ) 2323 if( !HAL_USB_MODE_BURST( pHwData ) )
2323 reg->D00_DmaControl = 0xc0000000;//Txon, Rxon, single Rx for new 4k DMA 2324 reg->D00_DmaControl = 0xc0000000;//Txon, Rxon, single Rx for new 4k DMA
2324 2325
2325 Wb35Reg_WriteSync( pHwData, 0x0400, reg->D00_DmaControl ); 2326 Wb35Reg_WriteSync( pHwData, 0x0400, reg->D00_DmaControl );
2326 } 2327 }
2327 2328
2328 void Mxx_initial( phw_data_t pHwData ) 2329 void Mxx_initial( phw_data_t pHwData )
2329 { 2330 {
2330 struct wb35_reg *reg = &pHwData->reg; 2331 struct wb35_reg *reg = &pHwData->reg;
2331 u32 tmp; 2332 u32 tmp;
2332 u32 pltmp[11]; 2333 u32 pltmp[11];
2333 u16 i; 2334 u16 i;
2334 2335
2335 2336
2336 //====================================================== 2337 //======================================================
2337 // Initial Mxx register 2338 // Initial Mxx register
2338 //====================================================== 2339 //======================================================
2339 2340
2340 // M00 bit set 2341 // M00 bit set
2341 #ifdef _IBSS_BEACON_SEQ_STICK_ 2342 #ifdef _IBSS_BEACON_SEQ_STICK_
2342 reg->M00_MacControl = 0; // Solve beacon sequence number stop by software 2343 reg->M00_MacControl = 0; // Solve beacon sequence number stop by software
2343 #else 2344 #else
2344 reg->M00_MacControl = 0x80000000; // Solve beacon sequence number stop by hardware 2345 reg->M00_MacControl = 0x80000000; // Solve beacon sequence number stop by hardware
2345 #endif 2346 #endif
2346 2347
2347 // M24 disable enter power save, BB RxOn and enable NAV attack 2348 // M24 disable enter power save, BB RxOn and enable NAV attack
2348 reg->M24_MacControl = 0x08040042; 2349 reg->M24_MacControl = 0x08040042;
2349 pltmp[0] = reg->M24_MacControl; 2350 pltmp[0] = reg->M24_MacControl;
2350 2351
2351 pltmp[1] = 0; // Skip M28, because no initialize value is required. 2352 pltmp[1] = 0; // Skip M28, because no initialize value is required.
2352 2353
2353 // M2C CWmin and CWmax setting 2354 // M2C CWmin and CWmax setting
2354 pHwData->cwmin = DEFAULT_CWMIN; 2355 pHwData->cwmin = DEFAULT_CWMIN;
2355 pHwData->cwmax = DEFAULT_CWMAX; 2356 pHwData->cwmax = DEFAULT_CWMAX;
2356 reg->M2C_MacControl = DEFAULT_CWMIN << 10; 2357 reg->M2C_MacControl = DEFAULT_CWMIN << 10;
2357 reg->M2C_MacControl |= DEFAULT_CWMAX; 2358 reg->M2C_MacControl |= DEFAULT_CWMAX;
2358 pltmp[2] = reg->M2C_MacControl; 2359 pltmp[2] = reg->M2C_MacControl;
2359 2360
2360 // M30 BSSID 2361 // M30 BSSID
2361 pltmp[3] = *(u32 *)pHwData->bssid; 2362 pltmp[3] = *(u32 *)pHwData->bssid;
2362 2363
2363 // M34 2364 // M34
2364 pHwData->AID = DEFAULT_AID; 2365 pHwData->AID = DEFAULT_AID;
2365 tmp = *(u16 *)(pHwData->bssid+4); 2366 tmp = *(u16 *)(pHwData->bssid+4);
2366 tmp |= DEFAULT_AID << 16; 2367 tmp |= DEFAULT_AID << 16;
2367 pltmp[4] = tmp; 2368 pltmp[4] = tmp;
2368 2369
2369 // M38 2370 // M38
2370 reg->M38_MacControl = (DEFAULT_RATE_RETRY_LIMIT<<8) | (DEFAULT_LONG_RETRY_LIMIT << 4) | DEFAULT_SHORT_RETRY_LIMIT; 2371 reg->M38_MacControl = (DEFAULT_RATE_RETRY_LIMIT<<8) | (DEFAULT_LONG_RETRY_LIMIT << 4) | DEFAULT_SHORT_RETRY_LIMIT;
2371 pltmp[5] = reg->M38_MacControl; 2372 pltmp[5] = reg->M38_MacControl;
2372 2373
2373 // M3C 2374 // M3C
2374 tmp = (DEFAULT_PIFST << 26) | (DEFAULT_EIFST << 16) | (DEFAULT_DIFST << 8) | (DEFAULT_SIFST << 4) | DEFAULT_OSIFST ; 2375 tmp = (DEFAULT_PIFST << 26) | (DEFAULT_EIFST << 16) | (DEFAULT_DIFST << 8) | (DEFAULT_SIFST << 4) | DEFAULT_OSIFST ;
2375 reg->M3C_MacControl = tmp; 2376 reg->M3C_MacControl = tmp;
2376 pltmp[6] = tmp; 2377 pltmp[6] = tmp;
2377 2378
2378 // M40 2379 // M40
2379 pHwData->slot_time_select = DEFAULT_SLOT_TIME; 2380 pHwData->slot_time_select = DEFAULT_SLOT_TIME;
2380 tmp = (DEFAULT_ATIMWD << 16) | DEFAULT_SLOT_TIME; 2381 tmp = (DEFAULT_ATIMWD << 16) | DEFAULT_SLOT_TIME;
2381 reg->M40_MacControl = tmp; 2382 reg->M40_MacControl = tmp;
2382 pltmp[7] = tmp; 2383 pltmp[7] = tmp;
2383 2384
2384 // M44 2385 // M44
2385 tmp = DEFAULT_MAX_TX_MSDU_LIFE_TIME << 10; // *1024 2386 tmp = DEFAULT_MAX_TX_MSDU_LIFE_TIME << 10; // *1024
2386 reg->M44_MacControl = tmp; 2387 reg->M44_MacControl = tmp;
2387 pltmp[8] = tmp; 2388 pltmp[8] = tmp;
2388 2389
2389 // M48 2390 // M48
2390 pHwData->BeaconPeriod = DEFAULT_BEACON_INTERVAL; 2391 pHwData->BeaconPeriod = DEFAULT_BEACON_INTERVAL;
2391 pHwData->ProbeDelay = DEFAULT_PROBE_DELAY_TIME; 2392 pHwData->ProbeDelay = DEFAULT_PROBE_DELAY_TIME;
2392 tmp = (DEFAULT_BEACON_INTERVAL << 16) | DEFAULT_PROBE_DELAY_TIME; 2393 tmp = (DEFAULT_BEACON_INTERVAL << 16) | DEFAULT_PROBE_DELAY_TIME;
2393 reg->M48_MacControl = tmp; 2394 reg->M48_MacControl = tmp;
2394 pltmp[9] = tmp; 2395 pltmp[9] = tmp;
2395 2396
2396 //M4C 2397 //M4C
2397 reg->M4C_MacStatus = (DEFAULT_PROTOCOL_VERSION << 30) | (DEFAULT_MAC_POWER_STATE << 28) | (DEFAULT_DTIM_ALERT_TIME << 24); 2398 reg->M4C_MacStatus = (DEFAULT_PROTOCOL_VERSION << 30) | (DEFAULT_MAC_POWER_STATE << 28) | (DEFAULT_DTIM_ALERT_TIME << 24);
2398 pltmp[10] = reg->M4C_MacStatus; 2399 pltmp[10] = reg->M4C_MacStatus;
2399 2400
2400 // Burst write 2401 // Burst write
2401 //Wb35Reg_BurstWrite( pHwData, 0x0824, pltmp, 11, AUTO_INCREMENT ); 2402 //Wb35Reg_BurstWrite( pHwData, 0x0824, pltmp, 11, AUTO_INCREMENT );
2402 for( i=0; i<11; i++ ) 2403 for( i=0; i<11; i++ )
2403 Wb35Reg_WriteSync( pHwData, 0x0824 + i*4, pltmp[i] ); 2404 Wb35Reg_WriteSync( pHwData, 0x0824 + i*4, pltmp[i] );
2404 2405
2405 // M60 2406 // M60
2406 Wb35Reg_WriteSync( pHwData, 0x0860, 0x12481248 ); 2407 Wb35Reg_WriteSync( pHwData, 0x0860, 0x12481248 );
2407 reg->M60_MacControl = 0x12481248; 2408 reg->M60_MacControl = 0x12481248;
2408 2409
2409 // M68 2410 // M68
2410 Wb35Reg_WriteSync( pHwData, 0x0868, 0x00050900 ); // 20051018 0x000F0F00 ); // 940930 0x00131300 2411 Wb35Reg_WriteSync( pHwData, 0x0868, 0x00050900 ); // 20051018 0x000F0F00 ); // 940930 0x00131300
2411 reg->M68_MacControl = 0x00050900; 2412 reg->M68_MacControl = 0x00050900;
2412 2413
2413 // M98 2414 // M98
2414 Wb35Reg_WriteSync( pHwData, 0x0898, 0xffff8888 ); 2415 Wb35Reg_WriteSync( pHwData, 0x0898, 0xffff8888 );
2415 reg->M98_MacControl = 0xffff8888; 2416 reg->M98_MacControl = 0xffff8888;
2416 } 2417 }
2417 2418
2418 2419
2419 void Uxx_power_off_procedure( phw_data_t pHwData ) 2420 void Uxx_power_off_procedure( phw_data_t pHwData )
2420 { 2421 {
2421 // SW, PMU reset and turn off clock 2422 // SW, PMU reset and turn off clock
2422 Wb35Reg_WriteSync( pHwData, 0x03b0, 3 ); 2423 Wb35Reg_WriteSync( pHwData, 0x03b0, 3 );
2423 Wb35Reg_WriteSync( pHwData, 0x03f0, 0xf9 ); 2424 Wb35Reg_WriteSync( pHwData, 0x03f0, 0xf9 );
2424 } 2425 }
2425 2426
2426 //Decide the TxVga of every channel 2427 //Decide the TxVga of every channel
2427 void GetTxVgaFromEEPROM( phw_data_t pHwData ) 2428 void GetTxVgaFromEEPROM( phw_data_t pHwData )
2428 { 2429 {
2429 u32 i, j, ltmp; 2430 u32 i, j, ltmp;
2430 u16 Value[MAX_TXVGA_EEPROM]; 2431 u16 Value[MAX_TXVGA_EEPROM];
2431 u8 *pctmp; 2432 u8 *pctmp;
2432 u8 ctmp=0; 2433 u8 ctmp=0;
2433 2434
2434 // Get the entire TxVga setting in EEPROM 2435 // Get the entire TxVga setting in EEPROM
2435 for( i=0; i<MAX_TXVGA_EEPROM; i++ ) 2436 for( i=0; i<MAX_TXVGA_EEPROM; i++ )
2436 { 2437 {
2437 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08100000 + 0x00010000*i ); 2438 Wb35Reg_WriteSync( pHwData, 0x03b4, 0x08100000 + 0x00010000*i );
2438 Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp ); 2439 Wb35Reg_ReadSync( pHwData, 0x03b4, &ltmp );
2439 Value[i] = (u16)( ltmp & 0xffff ); // Get 16 bit available 2440 Value[i] = (u16)( ltmp & 0xffff ); // Get 16 bit available
2440 Value[i] = cpu_to_le16( Value[i] ); // [7:0]2412 [7:0]2417 .... 2441 Value[i] = cpu_to_le16( Value[i] ); // [7:0]2412 [7:0]2417 ....
2441 } 2442 }
2442 2443
2443 // Adjust the filed which fills with reserved value. 2444 // Adjust the filed which fills with reserved value.
2444 pctmp = (u8 *)Value; 2445 pctmp = (u8 *)Value;
2445 for( i=0; i<(MAX_TXVGA_EEPROM*2); i++ ) 2446 for( i=0; i<(MAX_TXVGA_EEPROM*2); i++ )
2446 { 2447 {
2447 if( pctmp[i] != 0xff ) 2448 if( pctmp[i] != 0xff )
2448 ctmp = pctmp[i]; 2449 ctmp = pctmp[i];
2449 else 2450 else
2450 pctmp[i] = ctmp; 2451 pctmp[i] = ctmp;
2451 } 2452 }
2452 2453
2453 // Adjust WB_242 to WB_242_1 TxVga scale 2454 // Adjust WB_242 to WB_242_1 TxVga scale
2454 if( pHwData->phy_type == RF_WB_242 ) 2455 if( pHwData->phy_type == RF_WB_242 )
2455 { 2456 {
2456 for( i=0; i<4; i++ ) // Only 2412 2437 2462 2484 case must be modified 2457 for( i=0; i<4; i++ ) // Only 2412 2437 2462 2484 case must be modified
2457 { 2458 {
2458 for( j=0; j<(sizeof(w89rf242_txvga_old_mapping)/sizeof(w89rf242_txvga_old_mapping[0])); j++ ) 2459 for( j=0; j<(sizeof(w89rf242_txvga_old_mapping)/sizeof(w89rf242_txvga_old_mapping[0])); j++ )
2459 { 2460 {
2460 if( pctmp[i] < (u8)w89rf242_txvga_old_mapping[j][1] ) 2461 if( pctmp[i] < (u8)w89rf242_txvga_old_mapping[j][1] )
2461 { 2462 {
2462 pctmp[i] = (u8)w89rf242_txvga_old_mapping[j][0]; 2463 pctmp[i] = (u8)w89rf242_txvga_old_mapping[j][0];
2463 break; 2464 break;
2464 } 2465 }
2465 } 2466 }
2466 2467
2467 if( j == (sizeof(w89rf242_txvga_old_mapping)/sizeof(w89rf242_txvga_old_mapping[0])) ) 2468 if( j == (sizeof(w89rf242_txvga_old_mapping)/sizeof(w89rf242_txvga_old_mapping[0])) )
2468 pctmp[i] = (u8)w89rf242_txvga_old_mapping[j-1][0]; 2469 pctmp[i] = (u8)w89rf242_txvga_old_mapping[j-1][0];
2469 } 2470 }
2470 } 2471 }
2471 2472
2472 // 20060621 Add 2473 // 20060621 Add
2473 memcpy( pHwData->TxVgaSettingInEEPROM, pctmp, MAX_TXVGA_EEPROM*2 ); //MAX_TXVGA_EEPROM is u16 count 2474 memcpy( pHwData->TxVgaSettingInEEPROM, pctmp, MAX_TXVGA_EEPROM*2 ); //MAX_TXVGA_EEPROM is u16 count
2474 EEPROMTxVgaAdjust( pHwData ); 2475 EEPROMTxVgaAdjust( pHwData );
2475 } 2476 }
2476 2477
2477 // This function will affect the TxVga parameter in HAL. If hal_set_current_channel 2478 // This function will affect the TxVga parameter in HAL. If hal_set_current_channel
2478 // or RFSynthesizer_SetPowerIndex be called, new TxVga will take effect. 2479 // or RFSynthesizer_SetPowerIndex be called, new TxVga will take effect.
2479 // TxVgaSettingInEEPROM of sHwData is an u8 array point to EEPROM contain for IS89C35 2480 // TxVgaSettingInEEPROM of sHwData is an u8 array point to EEPROM contain for IS89C35
2480 // This function will use default TxVgaSettingInEEPROM data to calculate new TxVga. 2481 // This function will use default TxVgaSettingInEEPROM data to calculate new TxVga.
2481 void EEPROMTxVgaAdjust( phw_data_t pHwData ) // 20060619.5 Add 2482 void EEPROMTxVgaAdjust( phw_data_t pHwData ) // 20060619.5 Add
2482 { 2483 {
2483 u8 * pTxVga = pHwData->TxVgaSettingInEEPROM; 2484 u8 * pTxVga = pHwData->TxVgaSettingInEEPROM;
2484 s16 i, stmp; 2485 s16 i, stmp;
2485 2486
2486 //-- 2.4G -- 20060704.2 Request from Tiger 2487 //-- 2.4G -- 20060704.2 Request from Tiger
2487 //channel 1 ~ 5 2488 //channel 1 ~ 5
2488 stmp = pTxVga[1] - pTxVga[0]; 2489 stmp = pTxVga[1] - pTxVga[0];
2489 for( i=0; i<5; i++ ) 2490 for( i=0; i<5; i++ )
2490 pHwData->TxVgaFor24[i] = pTxVga[0] + stmp*i/4; 2491 pHwData->TxVgaFor24[i] = pTxVga[0] + stmp*i/4;
2491 //channel 6 ~ 10 2492 //channel 6 ~ 10
2492 stmp = pTxVga[2] - pTxVga[1]; 2493 stmp = pTxVga[2] - pTxVga[1];
2493 for( i=5; i<10; i++ ) 2494 for( i=5; i<10; i++ )
2494 pHwData->TxVgaFor24[i] = pTxVga[1] + stmp*(i-5)/4; 2495 pHwData->TxVgaFor24[i] = pTxVga[1] + stmp*(i-5)/4;
2495 //channel 11 ~ 13 2496 //channel 11 ~ 13
2496 stmp = pTxVga[3] - pTxVga[2]; 2497 stmp = pTxVga[3] - pTxVga[2];
2497 for( i=10; i<13; i++ ) 2498 for( i=10; i<13; i++ )
2498 pHwData->TxVgaFor24[i] = pTxVga[2] + stmp*(i-10)/2; 2499 pHwData->TxVgaFor24[i] = pTxVga[2] + stmp*(i-10)/2;
2499 //channel 14 2500 //channel 14
2500 pHwData->TxVgaFor24[13] = pTxVga[3]; 2501 pHwData->TxVgaFor24[13] = pTxVga[3];
2501 2502
2502 //-- 5G -- 2503 //-- 5G --
2503 if( pHwData->phy_type == RF_AIROHA_7230 ) 2504 if( pHwData->phy_type == RF_AIROHA_7230 )
2504 { 2505 {
2505 //channel 184 2506 //channel 184
2506 pHwData->TxVgaFor50[0].ChanNo = 184; 2507 pHwData->TxVgaFor50[0].ChanNo = 184;
2507 pHwData->TxVgaFor50[0].TxVgaValue = pTxVga[4]; 2508 pHwData->TxVgaFor50[0].TxVgaValue = pTxVga[4];
2508 //channel 196 2509 //channel 196
2509 pHwData->TxVgaFor50[3].ChanNo = 196; 2510 pHwData->TxVgaFor50[3].ChanNo = 196;
2510 pHwData->TxVgaFor50[3].TxVgaValue = pTxVga[5]; 2511 pHwData->TxVgaFor50[3].TxVgaValue = pTxVga[5];
2511 //interpolate 2512 //interpolate
2512 pHwData->TxVgaFor50[1].ChanNo = 188; 2513 pHwData->TxVgaFor50[1].ChanNo = 188;
2513 pHwData->TxVgaFor50[2].ChanNo = 192; 2514 pHwData->TxVgaFor50[2].ChanNo = 192;
2514 stmp = pTxVga[5] - pTxVga[4]; 2515 stmp = pTxVga[5] - pTxVga[4];
2515 pHwData->TxVgaFor50[2].TxVgaValue = pTxVga[5] - stmp/3; 2516 pHwData->TxVgaFor50[2].TxVgaValue = pTxVga[5] - stmp/3;
2516 pHwData->TxVgaFor50[1].TxVgaValue = pTxVga[5] - stmp*2/3; 2517 pHwData->TxVgaFor50[1].TxVgaValue = pTxVga[5] - stmp*2/3;
2517 2518
2518 //channel 16 2519 //channel 16
2519 pHwData->TxVgaFor50[6].ChanNo = 16; 2520 pHwData->TxVgaFor50[6].ChanNo = 16;
2520 pHwData->TxVgaFor50[6].TxVgaValue = pTxVga[6]; 2521 pHwData->TxVgaFor50[6].TxVgaValue = pTxVga[6];
2521 pHwData->TxVgaFor50[4].ChanNo = 8; 2522 pHwData->TxVgaFor50[4].ChanNo = 8;
2522 pHwData->TxVgaFor50[4].TxVgaValue = pTxVga[6]; 2523 pHwData->TxVgaFor50[4].TxVgaValue = pTxVga[6];
2523 pHwData->TxVgaFor50[5].ChanNo = 12; 2524 pHwData->TxVgaFor50[5].ChanNo = 12;
2524 pHwData->TxVgaFor50[5].TxVgaValue = pTxVga[6]; 2525 pHwData->TxVgaFor50[5].TxVgaValue = pTxVga[6];
2525 2526
2526 //channel 36 2527 //channel 36
2527 pHwData->TxVgaFor50[8].ChanNo = 36; 2528 pHwData->TxVgaFor50[8].ChanNo = 36;
2528 pHwData->TxVgaFor50[8].TxVgaValue = pTxVga[7]; 2529 pHwData->TxVgaFor50[8].TxVgaValue = pTxVga[7];
2529 pHwData->TxVgaFor50[7].ChanNo = 34; 2530 pHwData->TxVgaFor50[7].ChanNo = 34;
2530 pHwData->TxVgaFor50[7].TxVgaValue = pTxVga[7]; 2531 pHwData->TxVgaFor50[7].TxVgaValue = pTxVga[7];
2531 pHwData->TxVgaFor50[9].ChanNo = 38; 2532 pHwData->TxVgaFor50[9].ChanNo = 38;
2532 pHwData->TxVgaFor50[9].TxVgaValue = pTxVga[7]; 2533 pHwData->TxVgaFor50[9].TxVgaValue = pTxVga[7];
2533 2534
2534 //channel 40 2535 //channel 40
2535 pHwData->TxVgaFor50[10].ChanNo = 40; 2536 pHwData->TxVgaFor50[10].ChanNo = 40;
2536 pHwData->TxVgaFor50[10].TxVgaValue = pTxVga[8]; 2537 pHwData->TxVgaFor50[10].TxVgaValue = pTxVga[8];
2537 //channel 48 2538 //channel 48
2538 pHwData->TxVgaFor50[14].ChanNo = 48; 2539 pHwData->TxVgaFor50[14].ChanNo = 48;
2539 pHwData->TxVgaFor50[14].TxVgaValue = pTxVga[9]; 2540 pHwData->TxVgaFor50[14].TxVgaValue = pTxVga[9];
2540 //interpolate 2541 //interpolate
2541 pHwData->TxVgaFor50[11].ChanNo = 42; 2542 pHwData->TxVgaFor50[11].ChanNo = 42;
2542 pHwData->TxVgaFor50[12].ChanNo = 44; 2543 pHwData->TxVgaFor50[12].ChanNo = 44;
2543 pHwData->TxVgaFor50[13].ChanNo = 46; 2544 pHwData->TxVgaFor50[13].ChanNo = 46;
2544 stmp = pTxVga[9] - pTxVga[8]; 2545 stmp = pTxVga[9] - pTxVga[8];
2545 pHwData->TxVgaFor50[13].TxVgaValue = pTxVga[9] - stmp/4; 2546 pHwData->TxVgaFor50[13].TxVgaValue = pTxVga[9] - stmp/4;
2546 pHwData->TxVgaFor50[12].TxVgaValue = pTxVga[9] - stmp*2/4; 2547 pHwData->TxVgaFor50[12].TxVgaValue = pTxVga[9] - stmp*2/4;
2547 pHwData->TxVgaFor50[11].TxVgaValue = pTxVga[9] - stmp*3/4; 2548 pHwData->TxVgaFor50[11].TxVgaValue = pTxVga[9] - stmp*3/4;
2548 2549
2549 //channel 52 2550 //channel 52
2550 pHwData->TxVgaFor50[15].ChanNo = 52; 2551 pHwData->TxVgaFor50[15].ChanNo = 52;
2551 pHwData->TxVgaFor50[15].TxVgaValue = pTxVga[10]; 2552 pHwData->TxVgaFor50[15].TxVgaValue = pTxVga[10];
2552 //channel 64 2553 //channel 64
2553 pHwData->TxVgaFor50[18].ChanNo = 64; 2554 pHwData->TxVgaFor50[18].ChanNo = 64;
2554 pHwData->TxVgaFor50[18].TxVgaValue = pTxVga[11]; 2555 pHwData->TxVgaFor50[18].TxVgaValue = pTxVga[11];
2555 //interpolate 2556 //interpolate
2556 pHwData->TxVgaFor50[16].ChanNo = 56; 2557 pHwData->TxVgaFor50[16].ChanNo = 56;
2557 pHwData->TxVgaFor50[17].ChanNo = 60; 2558 pHwData->TxVgaFor50[17].ChanNo = 60;
2558 stmp = pTxVga[11] - pTxVga[10]; 2559 stmp = pTxVga[11] - pTxVga[10];
2559 pHwData->TxVgaFor50[17].TxVgaValue = pTxVga[11] - stmp/3; 2560 pHwData->TxVgaFor50[17].TxVgaValue = pTxVga[11] - stmp/3;
2560 pHwData->TxVgaFor50[16].TxVgaValue = pTxVga[11] - stmp*2/3; 2561 pHwData->TxVgaFor50[16].TxVgaValue = pTxVga[11] - stmp*2/3;
2561 2562
2562 //channel 100 2563 //channel 100
2563 pHwData->TxVgaFor50[19].ChanNo = 100; 2564 pHwData->TxVgaFor50[19].ChanNo = 100;
2564 pHwData->TxVgaFor50[19].TxVgaValue = pTxVga[12]; 2565 pHwData->TxVgaFor50[19].TxVgaValue = pTxVga[12];
2565 //channel 112 2566 //channel 112
2566 pHwData->TxVgaFor50[22].ChanNo = 112; 2567 pHwData->TxVgaFor50[22].ChanNo = 112;
2567 pHwData->TxVgaFor50[22].TxVgaValue = pTxVga[13]; 2568 pHwData->TxVgaFor50[22].TxVgaValue = pTxVga[13];
2568 //interpolate 2569 //interpolate
2569 pHwData->TxVgaFor50[20].ChanNo = 104; 2570 pHwData->TxVgaFor50[20].ChanNo = 104;
2570 pHwData->TxVgaFor50[21].ChanNo = 108; 2571 pHwData->TxVgaFor50[21].ChanNo = 108;
2571 stmp = pTxVga[13] - pTxVga[12]; 2572 stmp = pTxVga[13] - pTxVga[12];
2572 pHwData->TxVgaFor50[21].TxVgaValue = pTxVga[13] - stmp/3; 2573 pHwData->TxVgaFor50[21].TxVgaValue = pTxVga[13] - stmp/3;
2573 pHwData->TxVgaFor50[20].TxVgaValue = pTxVga[13] - stmp*2/3; 2574 pHwData->TxVgaFor50[20].TxVgaValue = pTxVga[13] - stmp*2/3;
2574 2575
2575 //channel 128 2576 //channel 128
2576 pHwData->TxVgaFor50[26].ChanNo = 128; 2577 pHwData->TxVgaFor50[26].ChanNo = 128;
2577 pHwData->TxVgaFor50[26].TxVgaValue = pTxVga[14]; 2578 pHwData->TxVgaFor50[26].TxVgaValue = pTxVga[14];
2578 //interpolate 2579 //interpolate
2579 pHwData->TxVgaFor50[23].ChanNo = 116; 2580 pHwData->TxVgaFor50[23].ChanNo = 116;
2580 pHwData->TxVgaFor50[24].ChanNo = 120; 2581 pHwData->TxVgaFor50[24].ChanNo = 120;
2581 pHwData->TxVgaFor50[25].ChanNo = 124; 2582 pHwData->TxVgaFor50[25].ChanNo = 124;
2582 stmp = pTxVga[14] - pTxVga[13]; 2583 stmp = pTxVga[14] - pTxVga[13];
2583 pHwData->TxVgaFor50[25].TxVgaValue = pTxVga[14] - stmp/4; 2584 pHwData->TxVgaFor50[25].TxVgaValue = pTxVga[14] - stmp/4;
2584 pHwData->TxVgaFor50[24].TxVgaValue = pTxVga[14] - stmp*2/4; 2585 pHwData->TxVgaFor50[24].TxVgaValue = pTxVga[14] - stmp*2/4;
2585 pHwData->TxVgaFor50[23].TxVgaValue = pTxVga[14] - stmp*3/4; 2586 pHwData->TxVgaFor50[23].TxVgaValue = pTxVga[14] - stmp*3/4;
2586 2587
2587 //channel 140 2588 //channel 140
2588 pHwData->TxVgaFor50[29].ChanNo = 140; 2589 pHwData->TxVgaFor50[29].ChanNo = 140;
2589 pHwData->TxVgaFor50[29].TxVgaValue = pTxVga[15]; 2590 pHwData->TxVgaFor50[29].TxVgaValue = pTxVga[15];
2590 //interpolate 2591 //interpolate
2591 pHwData->TxVgaFor50[27].ChanNo = 132; 2592 pHwData->TxVgaFor50[27].ChanNo = 132;
2592 pHwData->TxVgaFor50[28].ChanNo = 136; 2593 pHwData->TxVgaFor50[28].ChanNo = 136;
2593 stmp = pTxVga[15] - pTxVga[14]; 2594 stmp = pTxVga[15] - pTxVga[14];
2594 pHwData->TxVgaFor50[28].TxVgaValue = pTxVga[15] - stmp/3; 2595 pHwData->TxVgaFor50[28].TxVgaValue = pTxVga[15] - stmp/3;
2595 pHwData->TxVgaFor50[27].TxVgaValue = pTxVga[15] - stmp*2/3; 2596 pHwData->TxVgaFor50[27].TxVgaValue = pTxVga[15] - stmp*2/3;
2596 2597
2597 //channel 149 2598 //channel 149
2598 pHwData->TxVgaFor50[30].ChanNo = 149; 2599 pHwData->TxVgaFor50[30].ChanNo = 149;
2599 pHwData->TxVgaFor50[30].TxVgaValue = pTxVga[16]; 2600 pHwData->TxVgaFor50[30].TxVgaValue = pTxVga[16];
2600 //channel 165 2601 //channel 165
2601 pHwData->TxVgaFor50[34].ChanNo = 165; 2602 pHwData->TxVgaFor50[34].ChanNo = 165;
2602 pHwData->TxVgaFor50[34].TxVgaValue = pTxVga[17]; 2603 pHwData->TxVgaFor50[34].TxVgaValue = pTxVga[17];
2603 //interpolate 2604 //interpolate
2604 pHwData->TxVgaFor50[31].ChanNo = 153; 2605 pHwData->TxVgaFor50[31].ChanNo = 153;
2605 pHwData->TxVgaFor50[32].ChanNo = 157; 2606 pHwData->TxVgaFor50[32].ChanNo = 157;
2606 pHwData->TxVgaFor50[33].ChanNo = 161; 2607 pHwData->TxVgaFor50[33].ChanNo = 161;
2607 stmp = pTxVga[17] - pTxVga[16]; 2608 stmp = pTxVga[17] - pTxVga[16];
2608 pHwData->TxVgaFor50[33].TxVgaValue = pTxVga[17] - stmp/4; 2609 pHwData->TxVgaFor50[33].TxVgaValue = pTxVga[17] - stmp/4;
2609 pHwData->TxVgaFor50[32].TxVgaValue = pTxVga[17] - stmp*2/4; 2610 pHwData->TxVgaFor50[32].TxVgaValue = pTxVga[17] - stmp*2/4;
2610 pHwData->TxVgaFor50[31].TxVgaValue = pTxVga[17] - stmp*3/4; 2611 pHwData->TxVgaFor50[31].TxVgaValue = pTxVga[17] - stmp*3/4;
2611 } 2612 }
2612 2613
2613 #ifdef _PE_STATE_DUMP_ 2614 #ifdef _PE_STATE_DUMP_
2614 WBDEBUG((" TxVgaFor24 : \n")); 2615 WBDEBUG((" TxVgaFor24 : \n"));
2615 DataDmp((u8 *)pHwData->TxVgaFor24, 14 ,0); 2616 DataDmp((u8 *)pHwData->TxVgaFor24, 14 ,0);
2616 WBDEBUG((" TxVgaFor50 : \n")); 2617 WBDEBUG((" TxVgaFor50 : \n"));
2617 DataDmp((u8 *)pHwData->TxVgaFor50, 70 ,0); 2618 DataDmp((u8 *)pHwData->TxVgaFor50, 70 ,0);
2618 #endif 2619 #endif
2619 } 2620 }
2620 2621
2621 void BBProcessor_RateChanging( phw_data_t pHwData, u8 rate ) // 20060613.1 2622 void BBProcessor_RateChanging( phw_data_t pHwData, u8 rate ) // 20060613.1
2622 { 2623 {
2623 struct wb35_reg *reg = &pHwData->reg; 2624 struct wb35_reg *reg = &pHwData->reg;
2624 unsigned char Is11bRate; 2625 unsigned char Is11bRate;
2625 2626
2626 Is11bRate = (rate % 6) ? 1 : 0; 2627 Is11bRate = (rate % 6) ? 1 : 0;
2627 switch( pHwData->phy_type ) 2628 switch( pHwData->phy_type )
2628 { 2629 {
2629 case RF_AIROHA_2230: 2630 case RF_AIROHA_2230:
2630 case RF_AIROHA_2230S: // 20060420 Add this 2631 case RF_AIROHA_2230S: // 20060420 Add this
2631 if( Is11bRate ) 2632 if( Is11bRate )
2632 { 2633 {
2633 if( (reg->BB48 != BB48_DEFAULT_AL2230_11B) && 2634 if( (reg->BB48 != BB48_DEFAULT_AL2230_11B) &&
2634 (reg->BB4C != BB4C_DEFAULT_AL2230_11B) ) 2635 (reg->BB4C != BB4C_DEFAULT_AL2230_11B) )
2635 { 2636 {
2636 Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_AL2230_11B ); 2637 Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_AL2230_11B );
2637 Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_AL2230_11B ); 2638 Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_AL2230_11B );
2638 } 2639 }
2639 } 2640 }
2640 else 2641 else
2641 { 2642 {
2642 if( (reg->BB48 != BB48_DEFAULT_AL2230_11G) && 2643 if( (reg->BB48 != BB48_DEFAULT_AL2230_11G) &&
2643 (reg->BB4C != BB4C_DEFAULT_AL2230_11G) ) 2644 (reg->BB4C != BB4C_DEFAULT_AL2230_11G) )
2644 { 2645 {
2645 Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_AL2230_11G ); 2646 Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_AL2230_11G );
2646 Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_AL2230_11G ); 2647 Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_AL2230_11G );
2647 } 2648 }
2648 } 2649 }
2649 break; 2650 break;
2650 2651
2651 case RF_WB_242: // 20060623 The fix only for old TxVGA setting 2652 case RF_WB_242: // 20060623 The fix only for old TxVGA setting
2652 if( Is11bRate ) 2653 if( Is11bRate )
2653 { 2654 {
2654 if( (reg->BB48 != BB48_DEFAULT_WB242_11B) && 2655 if( (reg->BB48 != BB48_DEFAULT_WB242_11B) &&
2655 (reg->BB4C != BB4C_DEFAULT_WB242_11B) ) 2656 (reg->BB4C != BB4C_DEFAULT_WB242_11B) )
2656 { 2657 {
2657 reg->BB48 = BB48_DEFAULT_WB242_11B; 2658 reg->BB48 = BB48_DEFAULT_WB242_11B;
2658 reg->BB4C = BB4C_DEFAULT_WB242_11B; 2659 reg->BB4C = BB4C_DEFAULT_WB242_11B;
2659 Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_WB242_11B ); 2660 Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_WB242_11B );
2660 Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_WB242_11B ); 2661 Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_WB242_11B );
2661 } 2662 }
2662 } 2663 }
2663 else 2664 else
2664 { 2665 {
2665 if( (reg->BB48 != BB48_DEFAULT_WB242_11G) && 2666 if( (reg->BB48 != BB48_DEFAULT_WB242_11G) &&
2666 (reg->BB4C != BB4C_DEFAULT_WB242_11G) ) 2667 (reg->BB4C != BB4C_DEFAULT_WB242_11G) )
2667 { 2668 {
2668 reg->BB48 = BB48_DEFAULT_WB242_11G; 2669 reg->BB48 = BB48_DEFAULT_WB242_11G;
2669 reg->BB4C = BB4C_DEFAULT_WB242_11G; 2670 reg->BB4C = BB4C_DEFAULT_WB242_11G;
2670 Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_WB242_11G ); 2671 Wb35Reg_Write( pHwData, 0x1048, BB48_DEFAULT_WB242_11G );
2671 Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_WB242_11G ); 2672 Wb35Reg_Write( pHwData, 0x104c, BB4C_DEFAULT_WB242_11G );
2672 } 2673 }
2673 } 2674 }
2674 break; 2675 break;
2675 } 2676 }
2676 } 2677 }
2677 2678
2678 2679
2679 2680
2680 2681
2681 2682
2682 2683
2683 2684
2684 2685
drivers/staging/winbond/rxisr.c
Diff comments   View file @ 80aba53
1 #include "os_common.h" 1 #include "os_common.h"
2 #include "adapter.h"
2 3
3 static void RxTimerHandler(unsigned long data) 4 static void RxTimerHandler(unsigned long data)
4 { 5 {
5 WARN_ON(1); 6 WARN_ON(1);
6 } 7 }
7 8
8 void vRxTimerInit(struct wb35_adapter *adapter) 9 void vRxTimerInit(struct wb35_adapter *adapter)
9 { 10 {
10 init_timer(&adapter->Mds.timer); 11 init_timer(&adapter->Mds.timer);
11 adapter->Mds.timer.function = RxTimerHandler; 12 adapter->Mds.timer.function = RxTimerHandler;
12 adapter->Mds.timer.data = (unsigned long) adapter; 13 adapter->Mds.timer.data = (unsigned long) adapter;
13 } 14 }
14 15
15 void vRxTimerStart(struct wb35_adapter *adapter, int timeout_value) 16 void vRxTimerStart(struct wb35_adapter *adapter, int timeout_value)
16 { 17 {
17 if (timeout_value < MIN_TIMEOUT_VAL) 18 if (timeout_value < MIN_TIMEOUT_VAL)
18 timeout_value = MIN_TIMEOUT_VAL; 19 timeout_value = MIN_TIMEOUT_VAL;
19 20
20 adapter->Mds.timer.expires = jiffies + msecs_to_jiffies(timeout_value); 21 adapter->Mds.timer.expires = jiffies + msecs_to_jiffies(timeout_value);
21 add_timer(&adapter->Mds.timer); 22 add_timer(&adapter->Mds.timer);
22 } 23 }
23 24
24 void vRxTimerStop(struct wb35_adapter *adapter) 25 void vRxTimerStop(struct wb35_adapter *adapter)
25 { 26 {
26 del_timer_sync(&adapter->Mds.timer); 27 del_timer_sync(&adapter->Mds.timer);
27 } 28 }
28 29
drivers/staging/winbond/scan_s.h
Diff comments   View file @ 80aba53
1 #ifndef __WINBOND_SCAN_S_H
2 #define __WINBOND_SCAN_S_H
3
4 #include <linux/types.h>
5 #include "localpara.h"
6
1 // 7 //
2 // SCAN task global CONSTANTS, STRUCTURES, variables 8 // SCAN task global CONSTANTS, STRUCTURES, variables
3 // 9 //
4 10
5 ////////////////////////////////////////////////////////////////////////// 11 //////////////////////////////////////////////////////////////////////////
6 //define the msg type of SCAN module 12 //define the msg type of SCAN module
7 #define SCANMSG_SCAN_REQ 0x01 13 #define SCANMSG_SCAN_REQ 0x01
8 #define SCANMSG_BEACON 0x02 14 #define SCANMSG_BEACON 0x02
9 #define SCANMSG_PROBE_RESPONSE 0x03 15 #define SCANMSG_PROBE_RESPONSE 0x03
10 #define SCANMSG_TIMEOUT 0x04 16 #define SCANMSG_TIMEOUT 0x04
11 #define SCANMSG_TXPROBE_FAIL 0x05 17 #define SCANMSG_TXPROBE_FAIL 0x05
12 #define SCANMSG_ENABLE_BGSCAN 0x06 18 #define SCANMSG_ENABLE_BGSCAN 0x06
13 #define SCANMSG_STOP_SCAN 0x07 19 #define SCANMSG_STOP_SCAN 0x07
14 20
15 // BSS Type =>conform to 21 // BSS Type =>conform to
16 // IBSS : ToDS/FromDS = 00 22 // IBSS : ToDS/FromDS = 00
17 // Infrastructure : ToDS/FromDS = 01 23 // Infrastructure : ToDS/FromDS = 01
18 #define IBSS_NET 0 24 #define IBSS_NET 0
19 #define ESS_NET 1 25 #define ESS_NET 1
20 #define ANYBSS_NET 2 26 #define ANYBSS_NET 2
21 27
22 // Scan Type 28 // Scan Type
23 #define ACTIVE_SCAN 0 29 #define ACTIVE_SCAN 0
24 #define PASSIVE_SCAN 1 30 #define PASSIVE_SCAN 1
25 31
26 /////////////////////////////////////////////////////////////////////////// 32 ///////////////////////////////////////////////////////////////////////////
27 //Global data structures, Initial Scan & Background Scan 33 //Global data structures, Initial Scan & Background Scan
28 typedef struct _SCAN_REQ_PARA //mandatory parameters for SCAN request 34 typedef struct _SCAN_REQ_PARA //mandatory parameters for SCAN request
29 { 35 {
30 u32 ScanType; //passive/active scan 36 u32 ScanType; //passive/active scan
31 37
32 CHAN_LIST sChannelList; // 86B 38 CHAN_LIST sChannelList; // 86B
33 u8 reserved_1[2]; 39 u8 reserved_1[2];
34 40
35 struct SSID_Element sSSID; // 34B. scan only for this SSID 41 struct SSID_Element sSSID; // 34B. scan only for this SSID
36 u8 reserved_2[2]; 42 u8 reserved_2[2];
37 43
38 } SCAN_REQ_PARA, *psSCAN_REQ_PARA; 44 } SCAN_REQ_PARA, *psSCAN_REQ_PARA;
39 45
40 typedef struct _SCAN_PARAMETERS 46 typedef struct _SCAN_PARAMETERS
41 { 47 {
42 u16 wState; 48 u16 wState;
43 u16 iCurrentChannelIndex; 49 u16 iCurrentChannelIndex;
44 50
45 SCAN_REQ_PARA sScanReq; 51 SCAN_REQ_PARA sScanReq;
46 52
47 u8 BSSID[MAC_ADDR_LENGTH + 2]; //scan only for this BSSID 53 u8 BSSID[MAC_ADDR_LENGTH + 2]; //scan only for this BSSID
48 54
49 u32 BssType; //scan only for this BSS type 55 u32 BssType; //scan only for this BSS type
50 56
51 //struct SSID_Element sSSID; //scan only for this SSID 57 //struct SSID_Element sSSID; //scan only for this SSID
52 u16 ProbeDelay; 58 u16 ProbeDelay;
53 u16 MinChannelTime; 59 u16 MinChannelTime;
54 60
55 u16 MaxChannelTime; 61 u16 MaxChannelTime;
56 u16 reserved_1; 62 u16 reserved_1;
57 63
58 s32 iBgScanPeriod; // XP: 5 sec 64 s32 iBgScanPeriod; // XP: 5 sec
59 65
60 u8 boBgScan; // Wb: enable BG scan, For XP, this value must be FALSE 66 u8 boBgScan; // Wb: enable BG scan, For XP, this value must be FALSE
61 u8 boFastScan; // Wb: reserved 67 u8 boFastScan; // Wb: reserved
62 u8 boCCAbusy; // Wb: HWMAC CCA busy status 68 u8 boCCAbusy; // Wb: HWMAC CCA busy status
63 u8 reserved_2; 69 u8 reserved_2;
64 70
65 struct timer_list timer; 71 struct timer_list timer;
66 72
67 u32 ScanTimeStamp; //Increase 1 per background scan(1 minute) 73 u32 ScanTimeStamp; //Increase 1 per background scan(1 minute)
68 u32 BssTimeStamp; //Increase 1 per connect status check 74 u32 BssTimeStamp; //Increase 1 per connect status check
69 u32 RxNumPerAntenna[2]; // 75 u32 RxNumPerAntenna[2]; //
70 76
71 u8 AntennaToggle; // 77 u8 AntennaToggle; //
72 u8 boInTimerHandler; 78 u8 boInTimerHandler;
73 u8 boTimerActive; // Wb: reserved 79 u8 boTimerActive; // Wb: reserved
74 u8 boSave; 80 u8 boSave;
75 81
76 u32 BScanEnable; // Background scan enable. Default is On 82 u32 BScanEnable; // Background scan enable. Default is On
77 83
78 } SCAN_PARAMETERS, *psSCAN_PARAMETERS; 84 } SCAN_PARAMETERS, *psSCAN_PARAMETERS;
79 85
80 // Encapsulate 'adapter' data structure 86 // Encapsulate 'adapter' data structure
81 #define psSCAN (&(adapter->sScanPara)) 87 #define psSCAN (&(adapter->sScanPara))
82 #define psSCANREQ (&(adapter->sScanPara.sScanReq)) 88 #define psSCANREQ (&(adapter->sScanPara.sScanReq))
83 89
84 //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 90 //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
85 // scan.h 91 // scan.h
86 // Define the related definitions of scan module 92 // Define the related definitions of scan module
87 // history -- 01/14/03' created 93 // history -- 01/14/03' created
88 // 94 //
89 //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 95 //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
90 96
91 //Define the state of scan module 97 //Define the state of scan module
92 #define SCAN_INACTIVE 0 98 #define SCAN_INACTIVE 0
93 #define WAIT_PROBE_DELAY 1 99 #define WAIT_PROBE_DELAY 1
94 #define WAIT_RESPONSE_MIN 2 100 #define WAIT_RESPONSE_MIN 2
95 #define WAIT_RESPONSE_MAX_ACTIVE 3 101 #define WAIT_RESPONSE_MAX_ACTIVE 3
96 #define WAIT_BEACON_MAX_PASSIVE 4 102 #define WAIT_BEACON_MAX_PASSIVE 4
97 #define SCAN_COMPLETE 5 103 #define SCAN_COMPLETE 5
98 #define BG_SCAN 6 104 #define BG_SCAN 6
99 #define BG_SCANNING 7 105 #define BG_SCANNING 7
100 106
101 107
102 // The value will load from EEPROM 108 // The value will load from EEPROM
103 // If 0xff is set in EEPOM, the driver will use SCAN_MAX_CHNL_TIME instead. 109 // If 0xff is set in EEPOM, the driver will use SCAN_MAX_CHNL_TIME instead.
104 // The definition is in WbHal.h 110 // The definition is in WbHal.h
105 // #define SCAN_MAX_CHNL_TIME (50) 111 // #define SCAN_MAX_CHNL_TIME (50)
106 112
107 113
108 114
109 // static functions 115 // static functions
110 116
111 //static void ScanTimerHandler(struct wb35_adapter * adapter); 117 //static void ScanTimerHandler(struct wb35_adapter * adapter);
112 //static void vScanTimerStart(struct wb35_adapter * adapter, int timeout_value); 118 //static void vScanTimerStart(struct wb35_adapter * adapter, int timeout_value);
113 //static void vScanTimerStop(struct wb35_adapter * adapter); 119 //static void vScanTimerStop(struct wb35_adapter * adapter);
120
121 #endif
114 122
drivers/staging/winbond/sme_api.c
Diff comments   View file @ 80aba53
1 //------------------------------------------------------------------------------------ 1 //------------------------------------------------------------------------------------
2 // sme_api.c 2 // sme_api.c
3 // 3 //
4 // Copyright(C) 2002 Winbond Electronics Corp. 4 // Copyright(C) 2002 Winbond Electronics Corp.
5 // 5 //
6 // 6 //
7 //------------------------------------------------------------------------------------ 7 //------------------------------------------------------------------------------------
8 #include "os_common.h" 8 #include "os_common.h"
9 #include <linux/kernel.h>
9 10
10 s8 sme_get_rssi(void *pcore_data, s32 *prssi) 11 s8 sme_get_rssi(void *pcore_data, s32 *prssi)
11 { 12 {
12 BUG(); 13 BUG();
13 return 0; 14 return 0;
14 } 15 }
15 16
drivers/staging/winbond/sme_api.h
Diff comments   View file @ 80aba53
1 /* 1 /*
2 * sme_api.h 2 * sme_api.h
3 * 3 *
4 * Copyright(C) 2002 Winbond Electronics Corp. 4 * Copyright(C) 2002 Winbond Electronics Corp.
5 * 5 *
6 * modification history 6 * modification history
7 * --------------------------------------------------------------------------- 7 * ---------------------------------------------------------------------------
8 * 1.00.001, 2003-04-21, Kevin created 8 * 1.00.001, 2003-04-21, Kevin created
9 * 1.00.002, 2003-05-14, PD43 & PE20 modified 9 * 1.00.002, 2003-05-14, PD43 & PE20 modified
10 * 10 *
11 */ 11 */
12 12
13 #ifndef __SME_API_H__ 13 #ifndef __SME_API_H__
14 #define __SME_API_H__ 14 #define __SME_API_H__
15 15
16 #include <linux/types.h>
17
18 #include "localpara.h"
19
16 /****************** INCLUDE FILES SECTION ***********************************/ 20 /****************** INCLUDE FILES SECTION ***********************************/
17 //#include "GL\gl_core.h" 21 //#include "GL\gl_core.h"
18 22
19 /****************** CONSTANT AND MACRO SECTION ******************************/ 23 /****************** CONSTANT AND MACRO SECTION ******************************/
20 #define _INLINE __inline 24 #define _INLINE __inline
21 25
22 #define MEDIA_STATE_DISCONNECTED 0 26 #define MEDIA_STATE_DISCONNECTED 0
23 #define MEDIA_STATE_CONNECTED 1 27 #define MEDIA_STATE_CONNECTED 1
24 28
25 //ARRAY CHECK 29 //ARRAY CHECK
26 #define MAX_POWER_TO_DB 32 30 #define MAX_POWER_TO_DB 32
27 31
28 /****************** TYPE DEFINITION SECTION *********************************/ 32 /****************** TYPE DEFINITION SECTION *********************************/
29 33
30 /****************** EXPORTED FUNCTION DECLARATION SECTION *******************/ 34 /****************** EXPORTED FUNCTION DECLARATION SECTION *******************/
31 35
32 // OID_802_11_BSSID 36 // OID_802_11_BSSID
33 s8 sme_get_bssid(void *pcore_data, u8 *pbssid); 37 s8 sme_get_bssid(void *pcore_data, u8 *pbssid);
34 s8 sme_get_desired_bssid(void *pcore_data, u8 *pbssid);//Not use 38 s8 sme_get_desired_bssid(void *pcore_data, u8 *pbssid);//Not use
35 s8 sme_set_desired_bssid(void *pcore_data, u8 *pbssid); 39 s8 sme_set_desired_bssid(void *pcore_data, u8 *pbssid);
36 40
37 // OID_802_11_SSID 41 // OID_802_11_SSID
38 s8 sme_get_ssid(void *pcore_data, u8 *pssid, u8 *pssid_len); 42 s8 sme_get_ssid(void *pcore_data, u8 *pssid, u8 *pssid_len);
39 s8 sme_get_desired_ssid(void *pcore_data, u8 *pssid, u8 *pssid_len);// Not use 43 s8 sme_get_desired_ssid(void *pcore_data, u8 *pssid, u8 *pssid_len);// Not use
40 s8 sme_set_desired_ssid(void *pcore_data, u8 *pssid, u8 ssid_len); 44 s8 sme_set_desired_ssid(void *pcore_data, u8 *pssid, u8 ssid_len);
41 45
42 // OID_802_11_INFRASTRUCTURE_MODE 46 // OID_802_11_INFRASTRUCTURE_MODE
43 s8 sme_get_bss_type(void *pcore_data, u8 *pbss_type); 47 s8 sme_get_bss_type(void *pcore_data, u8 *pbss_type);
44 s8 sme_get_desired_bss_type(void *pcore_data, u8 *pbss_type);//Not use 48 s8 sme_get_desired_bss_type(void *pcore_data, u8 *pbss_type);//Not use
45 s8 sme_set_desired_bss_type(void *pcore_data, u8 bss_type); 49 s8 sme_set_desired_bss_type(void *pcore_data, u8 bss_type);
46 50
47 // OID_802_11_FRAGMENTATION_THRESHOLD 51 // OID_802_11_FRAGMENTATION_THRESHOLD
48 s8 sme_get_fragment_threshold(void *pcore_data, u32 *pthreshold); 52 s8 sme_get_fragment_threshold(void *pcore_data, u32 *pthreshold);
49 s8 sme_set_fragment_threshold(void *pcore_data, u32 threshold); 53 s8 sme_set_fragment_threshold(void *pcore_data, u32 threshold);
50 54
51 // OID_802_11_RTS_THRESHOLD 55 // OID_802_11_RTS_THRESHOLD
52 s8 sme_get_rts_threshold(void *pcore_data, u32 *pthreshold); 56 s8 sme_get_rts_threshold(void *pcore_data, u32 *pthreshold);
53 s8 sme_set_rts_threshold(void *pcore_data, u32 threshold); 57 s8 sme_set_rts_threshold(void *pcore_data, u32 threshold);
54 58
55 // OID_802_11_RSSI 59 // OID_802_11_RSSI
56 s8 sme_get_rssi(void *pcore_data, s32 *prssi); 60 s8 sme_get_rssi(void *pcore_data, s32 *prssi);
57 61
58 // OID_802_11_CONFIGURATION 62 // OID_802_11_CONFIGURATION
59 s8 sme_get_beacon_period(void *pcore_data, u16 *pbeacon_period); 63 s8 sme_get_beacon_period(void *pcore_data, u16 *pbeacon_period);
60 s8 sme_set_beacon_period(void *pcore_data, u16 beacon_period); 64 s8 sme_set_beacon_period(void *pcore_data, u16 beacon_period);
61 65
62 s8 sme_get_atim_window(void *pcore_data, u16 *patim_window); 66 s8 sme_get_atim_window(void *pcore_data, u16 *patim_window);
63 s8 sme_set_atim_window(void *pcore_data, u16 atim_window); 67 s8 sme_set_atim_window(void *pcore_data, u16 atim_window);
64 68
65 s8 sme_get_current_channel(void *pcore_data, u8 *pcurrent_channel); 69 s8 sme_get_current_channel(void *pcore_data, u8 *pcurrent_channel);
66 s8 sme_get_current_band(void *pcore_data, u8 *pcurrent_band); 70 s8 sme_get_current_band(void *pcore_data, u8 *pcurrent_band);
67 s8 sme_set_current_channel(void *pcore_data, u8 current_channel); 71 s8 sme_set_current_channel(void *pcore_data, u8 current_channel);
68 72
69 // OID_802_11_BSSID_LIST 73 // OID_802_11_BSSID_LIST
70 s8 sme_get_scan_bss_count(void *pcore_data, u8 *pcount); 74 s8 sme_get_scan_bss_count(void *pcore_data, u8 *pcount);
71 s8 sme_get_scan_bss(void *pcore_data, u8 index, void **ppbss); 75 s8 sme_get_scan_bss(void *pcore_data, u8 index, void **ppbss);
72 76
73 s8 sme_get_connected_bss(void *pcore_data, void **ppbss_now); 77 s8 sme_get_connected_bss(void *pcore_data, void **ppbss_now);
74 78
75 // OID_802_11_AUTHENTICATION_MODE 79 // OID_802_11_AUTHENTICATION_MODE
76 s8 sme_get_auth_mode(void *pcore_data, u8 *pauth_mode); 80 s8 sme_get_auth_mode(void *pcore_data, u8 *pauth_mode);
77 s8 sme_set_auth_mode(void *pcore_data, u8 auth_mode); 81 s8 sme_set_auth_mode(void *pcore_data, u8 auth_mode);
78 82
79 // OID_802_11_WEP_STATUS / OID_802_11_ENCRYPTION_STATUS 83 // OID_802_11_WEP_STATUS / OID_802_11_ENCRYPTION_STATUS
80 s8 sme_get_wep_mode(void *pcore_data, u8 *pwep_mode); 84 s8 sme_get_wep_mode(void *pcore_data, u8 *pwep_mode);
81 s8 sme_set_wep_mode(void *pcore_data, u8 wep_mode); 85 s8 sme_set_wep_mode(void *pcore_data, u8 wep_mode);
82 //s8 sme_get_encryption_status(void *pcore_data, u8 *pstatus); 86 //s8 sme_get_encryption_status(void *pcore_data, u8 *pstatus);
83 //s8 sme_set_encryption_status(void *pcore_data, u8 status); 87 //s8 sme_set_encryption_status(void *pcore_data, u8 status);
84 88
85 // ??????????????????????????????????????? 89 // ???????????????????????????????????????
86 90
87 // OID_GEN_VENDOR_ID 91 // OID_GEN_VENDOR_ID
88 // OID_802_3_PERMANENT_ADDRESS 92 // OID_802_3_PERMANENT_ADDRESS
89 s8 sme_get_permanent_mac_addr(void *pcore_data, u8 *pmac_addr); 93 s8 sme_get_permanent_mac_addr(void *pcore_data, u8 *pmac_addr);
90 94
91 // OID_802_3_CURRENT_ADDRESS 95 // OID_802_3_CURRENT_ADDRESS
92 s8 sme_get_current_mac_addr(void *pcore_data, u8 *pmac_addr); 96 s8 sme_get_current_mac_addr(void *pcore_data, u8 *pmac_addr);
93 97
94 // OID_802_11_NETWORK_TYPE_IN_USE 98 // OID_802_11_NETWORK_TYPE_IN_USE
95 s8 sme_get_network_type_in_use(void *pcore_data, u8 *ptype); 99 s8 sme_get_network_type_in_use(void *pcore_data, u8 *ptype);
96 s8 sme_set_network_type_in_use(void *pcore_data, u8 type); 100 s8 sme_set_network_type_in_use(void *pcore_data, u8 type);
97 101
98 // OID_802_11_SUPPORTED_RATES 102 // OID_802_11_SUPPORTED_RATES
99 s8 sme_get_supported_rate(void *pcore_data, u8 *prates); 103 s8 sme_get_supported_rate(void *pcore_data, u8 *prates);
100 104
101 // OID_802_11_ADD_WEP 105 // OID_802_11_ADD_WEP
102 //12/29/03' wkchen 106 //12/29/03' wkchen
103 s8 sme_set_add_wep(void *pcore_data, u32 key_index, u32 key_len, 107 s8 sme_set_add_wep(void *pcore_data, u32 key_index, u32 key_len,
104 u8 *Address, u8 *key); 108 u8 *Address, u8 *key);
105 109
106 // OID_802_11_REMOVE_WEP 110 // OID_802_11_REMOVE_WEP
107 s8 sme_set_remove_wep(void *pcre_data, u32 key_index); 111 s8 sme_set_remove_wep(void *pcre_data, u32 key_index);
108 112
109 // OID_802_11_DISASSOCIATE 113 // OID_802_11_DISASSOCIATE
110 s8 sme_set_disassociate(void *pcore_data); 114 s8 sme_set_disassociate(void *pcore_data);
111 115
112 // OID_802_11_POWER_MODE 116 // OID_802_11_POWER_MODE
113 s8 sme_get_power_mode(void *pcore_data, u8 *pmode); 117 s8 sme_get_power_mode(void *pcore_data, u8 *pmode);
114 s8 sme_set_power_mode(void *pcore_data, u8 mode); 118 s8 sme_set_power_mode(void *pcore_data, u8 mode);
115 119
116 // OID_802_11_BSSID_LIST_SCAN 120 // OID_802_11_BSSID_LIST_SCAN
117 s8 sme_set_bssid_list_scan(void *pcore_data, void *pscan_para); 121 s8 sme_set_bssid_list_scan(void *pcore_data, void *pscan_para);
118 122
119 // OID_802_11_RELOAD_DEFAULTS 123 // OID_802_11_RELOAD_DEFAULTS
120 s8 sme_set_reload_defaults(void *pcore_data, u8 reload_type); 124 s8 sme_set_reload_defaults(void *pcore_data, u8 reload_type);
121 125
122 126
123 // The following SME API functions are used for WPA 127 // The following SME API functions are used for WPA
124 // 128 //
125 // Mandatory OIDs for WPA 129 // Mandatory OIDs for WPA
126 // 130 //
127 131
128 // OID_802_11_ADD_KEY 132 // OID_802_11_ADD_KEY
129 //s8 sme_set_add_key(void *pcore_data, NDIS_802_11_KEY *pkey); 133 //s8 sme_set_add_key(void *pcore_data, NDIS_802_11_KEY *pkey);
130 134
131 // OID_802_11_REMOVE_KEY 135 // OID_802_11_REMOVE_KEY
132 //s8 sme_set_remove_key(void *pcore_data, NDIS_802_11_REMOVE_KEY *pkey); 136 //s8 sme_set_remove_key(void *pcore_data, NDIS_802_11_REMOVE_KEY *pkey);
133 137
134 // OID_802_11_ASSOCIATION_INFORMATION 138 // OID_802_11_ASSOCIATION_INFORMATION
135 //s8 sme_set_association_information(void *pcore_data, 139 //s8 sme_set_association_information(void *pcore_data,
136 // NDIS_802_11_ASSOCIATION_INFORMATION *pinfo); 140 // NDIS_802_11_ASSOCIATION_INFORMATION *pinfo);
137 141
138 // OID_802_11_TEST 142 // OID_802_11_TEST
139 //s8 sme_set_test(void *pcore_data, NDIS_802_11_TEST *ptest_data); 143 //s8 sme_set_test(void *pcore_data, NDIS_802_11_TEST *ptest_data);
140 144
141 //--------------------------------------------------------------------------// 145 //--------------------------------------------------------------------------//
142 /* 146 /*
143 // The left OIDs 147 // The left OIDs
144 148
145 // OID_802_11_NETWORK_TYPES_SUPPORTED 149 // OID_802_11_NETWORK_TYPES_SUPPORTED
146 // OID_802_11_TX_POWER_LEVEL 150 // OID_802_11_TX_POWER_LEVEL
147 // OID_802_11_RSSI_TRIGGER 151 // OID_802_11_RSSI_TRIGGER
148 // OID_802_11_NUMBER_OF_ANTENNAS 152 // OID_802_11_NUMBER_OF_ANTENNAS
149 // OID_802_11_RX_ANTENNA_SELECTED 153 // OID_802_11_RX_ANTENNA_SELECTED
150 // OID_802_11_TX_ANTENNA_SELECTED 154 // OID_802_11_TX_ANTENNA_SELECTED
151 // OID_802_11_STATISTICS 155 // OID_802_11_STATISTICS
152 // OID_802_11_DESIRED_RATES 156 // OID_802_11_DESIRED_RATES
153 // OID_802_11_PRIVACY_FILTER 157 // OID_802_11_PRIVACY_FILTER
154 158
155 */ 159 */
156 160
157 /*------------------------- none-standard ----------------------------------*/ 161 /*------------------------- none-standard ----------------------------------*/
158 s8 sme_get_connect_status(void *pcore_data, u8 *pstatus); 162 s8 sme_get_connect_status(void *pcore_data, u8 *pstatus);
159 163
160 /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ 164 /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
161 //s8 sme_get_scan_type(void *pcore_data, u8 *pscan_type); 165 //s8 sme_get_scan_type(void *pcore_data, u8 *pscan_type);
162 //s8 sme_set_scan_type(void *pcore_data, u8 scan_type); 166 //s8 sme_set_scan_type(void *pcore_data, u8 scan_type);
163 167
164 //s8 sme_get_scan_channel_list(void *pcore_data, u8 *pscan_type); 168 //s8 sme_get_scan_channel_list(void *pcore_data, u8 *pscan_type);
165 //s8 sme_set_scan_channel_list(void *pcore_data, u8 scan_type); 169 //s8 sme_set_scan_channel_list(void *pcore_data, u8 scan_type);
166 170
167 171
168 void sme_get_encryption_status(void *pcore_data, u8 *EncryptStatus); 172 void sme_get_encryption_status(void *pcore_data, u8 *EncryptStatus);
169 void sme_set_encryption_status(void *pcore_data, u8 EncryptStatus); 173 void sme_set_encryption_status(void *pcore_data, u8 EncryptStatus);
170 s8 sme_add_key(void *pcore_data, 174 s8 sme_add_key(void *pcore_data,
171 u32 key_index, 175 u32 key_index,
172 u8 key_len, 176 u8 key_len,
173 u8 key_type, 177 u8 key_type,
174 u8 *key_bssid, 178 u8 *key_bssid,
175 //u8 *key_rsc, 179 //u8 *key_rsc,
176 u8 *ptx_tsc, 180 u8 *ptx_tsc,
177 u8 *prx_tsc, 181 u8 *prx_tsc,
178 u8 *key_material); 182 u8 *key_material);
179 void sme_remove_default_key(void *pcore_data, int index); 183 void sme_remove_default_key(void *pcore_data, int index);
180 void sme_remove_mapping_key(void *pcore_data, u8 *pmac_addr); 184 void sme_remove_mapping_key(void *pcore_data, u8 *pmac_addr);
181 void sme_clear_all_mapping_key(void *pcore_data); 185 void sme_clear_all_mapping_key(void *pcore_data);
182 void sme_clear_all_default_key(void *pcore_data); 186 void sme_clear_all_default_key(void *pcore_data);
183 187
184 188
185 189
186 s8 sme_set_preamble_mode(void *pcore_data, u8 mode); 190 s8 sme_set_preamble_mode(void *pcore_data, u8 mode);
187 s8 sme_get_preamble_mode(void *pcore_data, u8 *mode); 191 s8 sme_get_preamble_mode(void *pcore_data, u8 *mode);
188 s8 sme_get_preamble_type(void *pcore_data, u8 *type); 192 s8 sme_get_preamble_type(void *pcore_data, u8 *type);
189 s8 sme_set_slottime_mode(void *pcore_data, u8 mode); 193 s8 sme_set_slottime_mode(void *pcore_data, u8 mode);
190 s8 sme_get_slottime_mode(void *pcore_data, u8 *mode); 194 s8 sme_get_slottime_mode(void *pcore_data, u8 *mode);
191 s8 sme_get_slottime_type(void *pcore_data, u8 *type); 195 s8 sme_get_slottime_type(void *pcore_data, u8 *type);
192 s8 sme_set_txrate_policy(void *pcore_data, u8 policy); 196 s8 sme_set_txrate_policy(void *pcore_data, u8 policy);
193 s8 sme_get_txrate_policy(void *pcore_data, u8 *policy); 197 s8 sme_get_txrate_policy(void *pcore_data, u8 *policy);
194 s8 sme_get_cwmin_value(void *pcore_data, u8 *cwmin); 198 s8 sme_get_cwmin_value(void *pcore_data, u8 *cwmin);
195 s8 sme_get_cwmax_value(void *pcore_data, u16 *cwmax); 199 s8 sme_get_cwmax_value(void *pcore_data, u16 *cwmax);
196 s8 sme_get_ms_radio_mode(void *pcore_data, u8 * pMsRadioOff); 200 s8 sme_get_ms_radio_mode(void *pcore_data, u8 * pMsRadioOff);
197 s8 sme_set_ms_radio_mode(void *pcore_data, u8 boMsRadioOff); 201 s8 sme_set_ms_radio_mode(void *pcore_data, u8 boMsRadioOff);
198 s8 sme_get_radio_mode(void *pcore_data, psRadioOff pRadioOffData); 202 s8 sme_get_radio_mode(void *pcore_data, psRadioOff pRadioOffData);
199 s8 sme_set_radio_mode(void *pcore_data, RadioOff RadioOffData); 203 s8 sme_set_radio_mode(void *pcore_data, RadioOff RadioOffData);
200 204
201 void sme_get_tx_power_level(void *pcore_data, u32 *TxPower); 205 void sme_get_tx_power_level(void *pcore_data, u32 *TxPower);
202 u8 sme_set_tx_power_level(void *pcore_data, u32 TxPower); 206 u8 sme_set_tx_power_level(void *pcore_data, u32 TxPower);
203 void sme_get_antenna_count(void *pcore_data, u32 *AntennaCount); 207 void sme_get_antenna_count(void *pcore_data, u32 *AntennaCount);
204 void sme_get_rx_antenna(void *pcore_data, u32 *RxAntenna); 208 void sme_get_rx_antenna(void *pcore_data, u32 *RxAntenna);
205 u8 sme_set_rx_antenna(void *pcore_data, u32 RxAntenna); 209 u8 sme_set_rx_antenna(void *pcore_data, u32 RxAntenna);
206 void sme_get_tx_antenna(void *pcore_data, u32 *TxAntenna); 210 void sme_get_tx_antenna(void *pcore_data, u32 *TxAntenna);
207 s8 sme_set_tx_antenna(void *pcore_data, u32 TxAntenna); 211 s8 sme_set_tx_antenna(void *pcore_data, u32 TxAntenna);
208 s8 sme_set_IBSS_chan(void *pcore_data, ChanInfo chan); 212 s8 sme_set_IBSS_chan(void *pcore_data, ChanInfo chan);
209 213
210 //20061108 WPS 214 //20061108 WPS
211 s8 sme_set_IE_append(void *pcore_data, u8 *buffer, u16 buf_len); 215 s8 sme_set_IE_append(void *pcore_data, u8 *buffer, u16 buf_len);
212 216
213 217
214 218
215 219
216 //================== Local functions ====================== 220 //================== Local functions ======================
217 //#ifdef _HSINCHU 221 //#ifdef _HSINCHU
218 //void drv_translate_rssi(); // HW RSSI bit -> NDIS RSSI representation 222 //void drv_translate_rssi(); // HW RSSI bit -> NDIS RSSI representation
219 //void drv_translate_bss_description(); // Local bss desc -> NDIS bss desc 223 //void drv_translate_bss_description(); // Local bss desc -> NDIS bss desc
220 //void drv_translate_channel(u8 NetworkType, u8 ChannelNumber, u32 *freq); // channel number -> channel /freq. 224 //void drv_translate_channel(u8 NetworkType, u8 ChannelNumber, u32 *freq); // channel number -> channel /freq.
221 //#endif _HSINCHU 225 //#endif _HSINCHU
222 // 226 //
223 static const u32 PowerDbToMw[] = 227 static const u32 PowerDbToMw[] =
224 { 228 {
225 56, //mW, MAX - 0, 17.5 dbm 229 56, //mW, MAX - 0, 17.5 dbm
226 40, //mW, MAX - 1, 16.0 dbm 230 40, //mW, MAX - 1, 16.0 dbm
227 30, //mW, MAX - 2, 14.8 dbm 231 30, //mW, MAX - 2, 14.8 dbm
228 20, //mW, MAX - 3, 13.0 dbm 232 20, //mW, MAX - 3, 13.0 dbm
229 15, //mW, MAX - 4, 11.8 dbm 233 15, //mW, MAX - 4, 11.8 dbm
230 12, //mW, MAX - 5, 10.6 dbm 234 12, //mW, MAX - 5, 10.6 dbm
231 9, //mW, MAX - 6, 9.4 dbm 235 9, //mW, MAX - 6, 9.4 dbm
232 7, //mW, MAX - 7, 8.3 dbm 236 7, //mW, MAX - 7, 8.3 dbm
233 5, //mW, MAX - 8, 6.4 dbm 237 5, //mW, MAX - 8, 6.4 dbm
234 4, //mW, MAX - 9, 5.3 dbm 238 4, //mW, MAX - 9, 5.3 dbm
235 3, //mW, MAX - 10, 4.0 dbm 239 3, //mW, MAX - 10, 4.0 dbm
236 2, //mW, MAX - 11, ? dbm 240 2, //mW, MAX - 11, ? dbm
237 2, //mW, MAX - 12, ? dbm 241 2, //mW, MAX - 12, ? dbm
238 2, //mW, MAX - 13, ? dbm 242 2, //mW, MAX - 13, ? dbm
239 2, //mW, MAX - 14, ? dbm 243 2, //mW, MAX - 14, ? dbm
240 2, //mW, MAX - 15, ? dbm 244 2, //mW, MAX - 15, ? dbm
241 2, //mW, MAX - 16, ? dbm 245 2, //mW, MAX - 16, ? dbm
242 2, //mW, MAX - 17, ? dbm 246 2, //mW, MAX - 17, ? dbm
243 2, //mW, MAX - 18, ? dbm 247 2, //mW, MAX - 18, ? dbm
244 1, //mW, MAX - 19, ? dbm 248 1, //mW, MAX - 19, ? dbm
245 1, //mW, MAX - 20, ? dbm 249 1, //mW, MAX - 20, ? dbm
246 1, //mW, MAX - 21, ? dbm 250 1, //mW, MAX - 21, ? dbm
247 1, //mW, MAX - 22, ? dbm 251 1, //mW, MAX - 22, ? dbm
248 1, //mW, MAX - 23, ? dbm 252 1, //mW, MAX - 23, ? dbm
249 1, //mW, MAX - 24, ? dbm 253 1, //mW, MAX - 24, ? dbm
250 1, //mW, MAX - 25, ? dbm 254 1, //mW, MAX - 25, ? dbm
251 1, //mW, MAX - 26, ? dbm 255 1, //mW, MAX - 26, ? dbm
252 1, //mW, MAX - 27, ? dbm 256 1, //mW, MAX - 27, ? dbm
253 1, //mW, MAX - 28, ? dbm 257 1, //mW, MAX - 28, ? dbm
254 1, //mW, MAX - 29, ? dbm 258 1, //mW, MAX - 29, ? dbm
255 1, //mW, MAX - 30, ? dbm 259 1, //mW, MAX - 30, ? dbm
256 1 //mW, MAX - 31, ? dbm 260 1 //mW, MAX - 31, ? dbm
257 }; 261 };
258 262
259 263
260 264
261 265
262 266
263 #endif /* __SME_API_H__ */ 267 #endif /* __SME_API_H__ */
264 268
265 269
266 270
drivers/staging/winbond/sme_s.h
Diff comments   View file @ 80aba53
1 #ifndef __WINBOND_SME_S_H
2 #define __WINBOND_SME_S_H
3
4 #include <linux/types.h>
5
6 #include "mac_structures.h"
7 #include "localpara.h"
8
1 // 9 //
2 // SME_S.H - 10 // SME_S.H -
3 // SME task global CONSTANTS, STRUCTURES, variables 11 // SME task global CONSTANTS, STRUCTURES, variables
4 // 12 //
5 13
6 ////////////////////////////////////////////////////////////////////////// 14 //////////////////////////////////////////////////////////////////////////
7 //define the msg type of SME module 15 //define the msg type of SME module
8 // 0x00~0x1F : MSG from GUI dispatch 16 // 0x00~0x1F : MSG from GUI dispatch
9 // 0x20~0x3F : MSG from MLME 17 // 0x20~0x3F : MSG from MLME
10 // 0x40~0x5F : MSG from SCAN 18 // 0x40~0x5F : MSG from SCAN
11 // 0x60~0x6F : MSG from TX/RX 19 // 0x60~0x6F : MSG from TX/RX
12 // 0x70~0x7F : MSG from ROAMING 20 // 0x70~0x7F : MSG from ROAMING
13 // 0x80~0x8F : MSG from ISR 21 // 0x80~0x8F : MSG from ISR
14 // 0x90 : MSG TimeOut 22 // 0x90 : MSG TimeOut
15 23
16 // from GUI 24 // from GUI
17 #define SMEMSG_SCAN_REQ 0x01 25 #define SMEMSG_SCAN_REQ 0x01
18 //#define SMEMSG_PASSIVE_SCAN_REQ 0x02 26 //#define SMEMSG_PASSIVE_SCAN_REQ 0x02
19 #define SMEMSG_JOIN_REQ 0x03 27 #define SMEMSG_JOIN_REQ 0x03
20 #define SMEMSG_START_IBSS 0x04 28 #define SMEMSG_START_IBSS 0x04
21 #define SMEMSG_DISCONNECT_REQ 0x05 29 #define SMEMSG_DISCONNECT_REQ 0x05
22 #define SMEMSG_AUTHEN_REQ 0x06 30 #define SMEMSG_AUTHEN_REQ 0x06
23 #define SMEMSG_DEAUTHEN_REQ 0x07 31 #define SMEMSG_DEAUTHEN_REQ 0x07
24 #define SMEMSG_ASSOC_REQ 0x08 32 #define SMEMSG_ASSOC_REQ 0x08
25 #define SMEMSG_REASSOC_REQ 0x09 33 #define SMEMSG_REASSOC_REQ 0x09
26 #define SMEMSG_DISASSOC_REQ 0x0a 34 #define SMEMSG_DISASSOC_REQ 0x0a
27 #define SMEMSG_POWERSAVE_REQ 0x0b 35 #define SMEMSG_POWERSAVE_REQ 0x0b
28 36
29 37
30 // from MLME 38 // from MLME
31 #define SMEMSG_AUTHEN_CFM 0x21 39 #define SMEMSG_AUTHEN_CFM 0x21
32 #define SMEMSG_AUTHEN_IND 0x22 40 #define SMEMSG_AUTHEN_IND 0x22
33 #define SMEMSG_ASSOC_CFM 0x23 41 #define SMEMSG_ASSOC_CFM 0x23
34 #define SMEMSG_DEAUTHEN_IND 0x24 42 #define SMEMSG_DEAUTHEN_IND 0x24
35 #define SMEMSG_DISASSOC_IND 0x25 43 #define SMEMSG_DISASSOC_IND 0x25
36 // from SCAN 44 // from SCAN
37 #define SMEMSG_SCAN_CFM 0x41 45 #define SMEMSG_SCAN_CFM 0x41
38 #define SMEMSG_START_IBSS_CFM 0x42 46 #define SMEMSG_START_IBSS_CFM 0x42
39 // from MTO, function call to set SME parameters 47 // from MTO, function call to set SME parameters
40 48
41 // 0x60~0x6F : MSG from TX/RX 49 // 0x60~0x6F : MSG from TX/RX
42 //#define SMEMSG_IBSS_JOIN_UPDATE_BSSID 0x61 50 //#define SMEMSG_IBSS_JOIN_UPDATE_BSSID 0x61
43 #define SMEMSG_COUNTERMEASURE_MICFAIL_TIMEOUT 0x62 51 #define SMEMSG_COUNTERMEASURE_MICFAIL_TIMEOUT 0x62
44 #define SMEMSG_COUNTERMEASURE_BLOCK_TIMEOUT 0x63 52 #define SMEMSG_COUNTERMEASURE_BLOCK_TIMEOUT 0x63
45 // from ROAMING 53 // from ROAMING
46 #define SMEMSG_HANDOVER_JOIN_REQ 0x71 54 #define SMEMSG_HANDOVER_JOIN_REQ 0x71
47 #define SMEMSG_END_ROAMING 0x72 55 #define SMEMSG_END_ROAMING 0x72
48 #define SMEMSG_SCAN_JOIN_REQ 0x73 56 #define SMEMSG_SCAN_JOIN_REQ 0x73
49 // from ISR 57 // from ISR
50 #define SMEMSG_TSF_SYNC_IND 0x81 58 #define SMEMSG_TSF_SYNC_IND 0x81
51 // from TimeOut 59 // from TimeOut
52 #define SMEMSG_TIMEOUT 0x91 60 #define SMEMSG_TIMEOUT 0x91
53 61
54 62
55 63
56 #define MAX_PMKID_Accunt 16 64 #define MAX_PMKID_Accunt 16
57 //@added by ws 04/22/05 65 //@added by ws 04/22/05
58 #define Cipher_Disabled 0 66 #define Cipher_Disabled 0
59 #define Cipher_Wep 1 67 #define Cipher_Wep 1
60 #define Cipher_Tkip 2 68 #define Cipher_Tkip 2
61 #define Cipher_Ccmp 4 69 #define Cipher_Ccmp 4
62 70
63 71
64 /////////////////////////////////////////////////////////////////////////// 72 ///////////////////////////////////////////////////////////////////////////
65 //Constants 73 //Constants
66 74
67 /////////////////////////////////////////////////////////////////////////// 75 ///////////////////////////////////////////////////////////////////////////
68 //Global data structures 76 //Global data structures
69 77
70 #define NUMOFWEPENTRIES 64 78 #define NUMOFWEPENTRIES 64
71 79
72 typedef enum _WEPKeyMode 80 typedef enum _WEPKeyMode
73 { 81 {
74 WEPKEY_DISABLED = 0, 82 WEPKEY_DISABLED = 0,
75 WEPKEY_64 = 1, 83 WEPKEY_64 = 1,
76 WEPKEY_128 = 2 84 WEPKEY_128 = 2
77 85
78 } WEPKEYMODE, *pWEPKEYMODE; 86 } WEPKEYMODE, *pWEPKEYMODE;
79 87
80 #ifdef _WPA2_ 88 #ifdef _WPA2_
81 89
82 typedef struct _BSSInfo 90 typedef struct _BSSInfo
83 { 91 {
84 u8 PreAuthBssID[6]; 92 u8 PreAuthBssID[6];
85 PMKID pmkid_value; 93 PMKID pmkid_value;
86 }BSSID_Info; 94 }BSSID_Info;
87 95
88 typedef struct _PMKID_Table //added by ws 05/05/04 96 typedef struct _PMKID_Table //added by ws 05/05/04
89 { 97 {
90 u32 Length; 98 u32 Length;
91 u32 BSSIDInfoCount; 99 u32 BSSIDInfoCount;
92 BSSID_Info BSSIDInfo[16]; 100 BSSID_Info BSSIDInfo[16];
93 101
94 } PMKID_Table; 102 } PMKID_Table;
95 103
96 #endif //end def _WPA2_ 104 #endif //end def _WPA2_
97 105
98 #define MAX_BASIC_RATE_SET 15 106 #define MAX_BASIC_RATE_SET 15
99 #define MAX_OPT_RATE_SET MAX_BASIC_RATE_SET 107 #define MAX_OPT_RATE_SET MAX_BASIC_RATE_SET
100 108
101 109
102 typedef struct _SME_PARAMETERS 110 typedef struct _SME_PARAMETERS
103 { 111 {
104 u16 wState; 112 u16 wState;
105 u8 boDUTmode; 113 u8 boDUTmode;
106 u8 bDesiredPowerSave; 114 u8 bDesiredPowerSave;
107 115
108 // SME timer and timeout value 116 // SME timer and timeout value
109 struct timer_list timer; 117 struct timer_list timer;
110 118
111 u8 boInTimerHandler; 119 u8 boInTimerHandler;
112 u8 boAuthRetryActive; 120 u8 boAuthRetryActive;
113 u8 reserved_0[2]; 121 u8 reserved_0[2];
114 122
115 u32 AuthenRetryTimerVal; // NOTE: Assoc don't fail timeout 123 u32 AuthenRetryTimerVal; // NOTE: Assoc don't fail timeout
116 u32 JoinFailTimerVal; // 10*Beacon-Interval 124 u32 JoinFailTimerVal; // 10*Beacon-Interval
117 125
118 //Rates 126 //Rates
119 u8 BSSBasicRateSet[(MAX_BASIC_RATE_SET + 3) & ~0x03 ]; // BSS basic rate set 127 u8 BSSBasicRateSet[(MAX_BASIC_RATE_SET + 3) & ~0x03 ]; // BSS basic rate set
120 u8 OperationalRateSet[(MAX_OPT_RATE_SET + 3) & ~0x03 ]; // Operational rate set 128 u8 OperationalRateSet[(MAX_OPT_RATE_SET + 3) & ~0x03 ]; // Operational rate set
121 129
122 u8 NumOfBSSBasicRate; 130 u8 NumOfBSSBasicRate;
123 u8 NumOfOperationalRate; 131 u8 NumOfOperationalRate;
124 u8 reserved_1[2]; 132 u8 reserved_1[2];
125 133
126 u32 BasicRateBitmap; 134 u32 BasicRateBitmap;
127 u32 OpRateBitmap; 135 u32 OpRateBitmap;
128 136
129 // System parameters Set by GUI 137 // System parameters Set by GUI
130 //-------------------- start IBSS parameter ---------------------------// 138 //-------------------- start IBSS parameter ---------------------------//
131 u32 boStartIBSS; //Start IBSS toggle 139 u32 boStartIBSS; //Start IBSS toggle
132 140
133 u16 wBeaconPeriod; 141 u16 wBeaconPeriod;
134 u16 wATIM_Window; 142 u16 wATIM_Window;
135 143
136 ChanInfo IbssChan; // 2B //channel setting when start IBSS 144 ChanInfo IbssChan; // 2B //channel setting when start IBSS
137 u8 reserved_2[2]; 145 u8 reserved_2[2];
138 146
139 // Join related 147 // Join related
140 u16 wDesiredJoinBSS; // BSS index which desire to join 148 u16 wDesiredJoinBSS; // BSS index which desire to join
141 u8 boJoinReq; //Join request toggle 149 u8 boJoinReq; //Join request toggle
142 u8 bDesiredBSSType; //for Join request 150 u8 bDesiredBSSType; //for Join request
143 151
144 u16 wCapabilityInfo; // Used when invoking the MLME_Associate_request(). 152 u16 wCapabilityInfo; // Used when invoking the MLME_Associate_request().
145 u16 wNonERPcapabilityInfo; 153 u16 wNonERPcapabilityInfo;
146 154
147 struct SSID_Element sDesiredSSID; // 34 B 155 struct SSID_Element sDesiredSSID; // 34 B
148 u8 reserved_3[2]; 156 u8 reserved_3[2];
149 157
150 u8 abDesiredBSSID[MAC_ADDR_LENGTH + 2]; 158 u8 abDesiredBSSID[MAC_ADDR_LENGTH + 2];
151 159
152 u8 bJoinScanCount; // the time of scan-join action need to do 160 u8 bJoinScanCount; // the time of scan-join action need to do
153 u8 bDesiredAuthMode; // AUTH_OPEN_SYSTEM or AUTH_SHARED_KEY 161 u8 bDesiredAuthMode; // AUTH_OPEN_SYSTEM or AUTH_SHARED_KEY
154 u8 reserved_4[2]; 162 u8 reserved_4[2];
155 163
156 // Encryption parameters 164 // Encryption parameters
157 u8 _dot11PrivacyInvoked; 165 u8 _dot11PrivacyInvoked;
158 u8 _dot11PrivacyOptionImplemented; 166 u8 _dot11PrivacyOptionImplemented;
159 u8 reserved_5[2]; 167 u8 reserved_5[2];
160 168
161 //@ ws added 169 //@ ws added
162 u8 DesiredEncrypt; 170 u8 DesiredEncrypt;
163 u8 encrypt_status; //ENCRYPT_DISABLE, ENCRYPT_WEP, ENCRYPT_WEP_NOKEY, ENCRYPT_TKIP, ... 171 u8 encrypt_status; //ENCRYPT_DISABLE, ENCRYPT_WEP, ENCRYPT_WEP_NOKEY, ENCRYPT_TKIP, ...
164 u8 key_length; 172 u8 key_length;
165 u8 pairwise_key_ok; 173 u8 pairwise_key_ok;
166 174
167 u8 group_key_ok; 175 u8 group_key_ok;
168 u8 wpa_ok; // indicate the control port of 802.1x is open or close 176 u8 wpa_ok; // indicate the control port of 802.1x is open or close
169 u8 pairwise_key_type; 177 u8 pairwise_key_type;
170 u8 group_key_type; 178 u8 group_key_type;
171 179
172 u32 _dot11WEPDefaultKeyID; 180 u32 _dot11WEPDefaultKeyID;
173 181
174 u8 tx_mic_key[8]; // TODO: 0627 kevin-TKIP 182 u8 tx_mic_key[8]; // TODO: 0627 kevin-TKIP
175 u8 rx_mic_key[8]; // TODO: 0627 kevin-TKIP 183 u8 rx_mic_key[8]; // TODO: 0627 kevin-TKIP
176 u8 group_tx_mic_key[8]; 184 u8 group_tx_mic_key[8];
177 u8 group_rx_mic_key[8]; 185 u8 group_rx_mic_key[8];
178 186
179 // #ifdef _WPA_ 187 // #ifdef _WPA_
180 u8 AssocReqVarIE[200]; 188 u8 AssocReqVarIE[200];
181 u8 AssocRespVarIE[200]; 189 u8 AssocRespVarIE[200];
182 190
183 u16 AssocReqVarLen; 191 u16 AssocReqVarLen;
184 u16 AssocRespVarLen; 192 u16 AssocRespVarLen;
185 u8 boReassoc; //use assoc. or reassoc. 193 u8 boReassoc; //use assoc. or reassoc.
186 u8 reserved_6[3]; 194 u8 reserved_6[3];
187 u16 AssocRespCapability; 195 u16 AssocRespCapability;
188 u16 AssocRespStatus; 196 u16 AssocRespStatus;
189 // #endif 197 // #endif
190 198
191 #ifdef _WPA2_ 199 #ifdef _WPA2_
192 u8 PmkIdTable[256]; 200 u8 PmkIdTable[256];
193 u32 PmkidTableIndex; 201 u32 PmkidTableIndex;
194 #endif //end def _WPA2_ 202 #endif //end def _WPA2_
195 203
196 } SME_PARAMETERS, *PSME_PARAMETERS; 204 } SME_PARAMETERS, *PSME_PARAMETERS;
197 205
198 #define psSME (&(adapter->sSmePara)) 206 #define psSME (&(adapter->sSmePara))
199 207
200 #define wSMEGetCurrentSTAState(adapter) ((u16)(adapter)->sSmePara.wState) 208 #define wSMEGetCurrentSTAState(adapter) ((u16)(adapter)->sSmePara.wState)
201 209
202 210
203 211
204 //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 212 //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
205 // SmeModule.h 213 // SmeModule.h
206 // Define the related definitions of SME module 214 // Define the related definitions of SME module
207 // history -- 01/14/03' created 215 // history -- 01/14/03' created
208 // 216 //
209 //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 217 //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
210 218
211 //Define the state of SME module 219 //Define the state of SME module
212 #define DISABLED 0 220 #define DISABLED 0
213 #define INIT_SCAN 1 221 #define INIT_SCAN 1
214 #define SCAN_READY 2 222 #define SCAN_READY 2
215 #define START_IBSS 3 223 #define START_IBSS 3
216 #define JOIN_PENDING 4 224 #define JOIN_PENDING 4
217 #define JOIN_CFM 5 225 #define JOIN_CFM 5
218 #define AUTHENTICATE_PENDING 6 226 #define AUTHENTICATE_PENDING 6
219 #define AUTHENTICATED 7 227 #define AUTHENTICATED 7
220 #define CONNECTED 8 228 #define CONNECTED 8
221 //#define EAP_STARTING 9 229 //#define EAP_STARTING 9
222 //#define EAPOL_AUTHEN_PENDING 10 230 //#define EAPOL_AUTHEN_PENDING 10
223 //#define SECURE_CONNECTED 11 231 //#define SECURE_CONNECTED 11
224 232
225 233
226 // Static function 234 // Static function
235
236 #endif
227 237
drivers/staging/winbond/wbhal.c
Diff comments   View file @ 80aba53
1 #include "os_common.h" 1 #include "os_common.h"
2 #include "wbhal_f.h"
3 #include "wblinux_f.h"
2 4
3 void hal_get_ethernet_address( phw_data_t pHwData, u8 *current_address ) 5 void hal_get_ethernet_address( phw_data_t pHwData, u8 *current_address )
4 { 6 {
5 if( pHwData->SurpriseRemove ) return; 7 if( pHwData->SurpriseRemove ) return;
6 8
7 memcpy( current_address, pHwData->CurrentMacAddress, ETH_LENGTH_OF_ADDRESS ); 9 memcpy( current_address, pHwData->CurrentMacAddress, ETH_LENGTH_OF_ADDRESS );
8 } 10 }
9 11
10 void hal_set_ethernet_address( phw_data_t pHwData, u8 *current_address ) 12 void hal_set_ethernet_address( phw_data_t pHwData, u8 *current_address )
11 { 13 {
12 u32 ltmp[2]; 14 u32 ltmp[2];
13 15
14 if( pHwData->SurpriseRemove ) return; 16 if( pHwData->SurpriseRemove ) return;
15 17
16 memcpy( pHwData->CurrentMacAddress, current_address, ETH_LENGTH_OF_ADDRESS ); 18 memcpy( pHwData->CurrentMacAddress, current_address, ETH_LENGTH_OF_ADDRESS );
17 19
18 ltmp[0]= cpu_to_le32( *(u32 *)pHwData->CurrentMacAddress ); 20 ltmp[0]= cpu_to_le32( *(u32 *)pHwData->CurrentMacAddress );
19 ltmp[1]= cpu_to_le32( *(u32 *)(pHwData->CurrentMacAddress + 4) ) & 0xffff; 21 ltmp[1]= cpu_to_le32( *(u32 *)(pHwData->CurrentMacAddress + 4) ) & 0xffff;
20 22
21 Wb35Reg_BurstWrite( pHwData, 0x03e8, ltmp, 2, AUTO_INCREMENT ); 23 Wb35Reg_BurstWrite( pHwData, 0x03e8, ltmp, 2, AUTO_INCREMENT );
22 } 24 }
23 25
24 void hal_get_permanent_address( phw_data_t pHwData, u8 *pethernet_address ) 26 void hal_get_permanent_address( phw_data_t pHwData, u8 *pethernet_address )
25 { 27 {
26 if( pHwData->SurpriseRemove ) return; 28 if( pHwData->SurpriseRemove ) return;
27 29
28 memcpy( pethernet_address, pHwData->PermanentMacAddress, 6 ); 30 memcpy( pethernet_address, pHwData->PermanentMacAddress, 6 );
29 } 31 }
30 32
31 static void hal_led_control(unsigned long data) 33 static void hal_led_control(unsigned long data)
32 { 34 {
33 phw_data_t pHwData = (phw_data_t) data; 35 phw_data_t pHwData = (phw_data_t) data;
34 struct wb35_adapter * adapter = pHwData->adapter; 36 struct wb35_adapter * adapter = pHwData->adapter;
35 struct wb35_reg *reg = &pHwData->reg; 37 struct wb35_reg *reg = &pHwData->reg;
36 u32 LEDSet = (pHwData->SoftwareSet & HAL_LED_SET_MASK) >> HAL_LED_SET_SHIFT; 38 u32 LEDSet = (pHwData->SoftwareSet & HAL_LED_SET_MASK) >> HAL_LED_SET_SHIFT;
37 u8 LEDgray[20] = { 0,3,4,6,8,10,11,12,13,14,15,14,13,12,11,10,8,6,4,2 }; 39 u8 LEDgray[20] = { 0,3,4,6,8,10,11,12,13,14,15,14,13,12,11,10,8,6,4,2 };
38 u8 LEDgray2[30] = { 7,8,9,10,11,12,13,14,15,0,0,0,0,0,0,0,0,0,0,0,0,0,15,14,13,12,11,10,9,8 }; 40 u8 LEDgray2[30] = { 7,8,9,10,11,12,13,14,15,0,0,0,0,0,0,0,0,0,0,0,0,0,15,14,13,12,11,10,9,8 };
39 u32 TimeInterval = 500, ltmp, ltmp2; 41 u32 TimeInterval = 500, ltmp, ltmp2;
40 ltmp=0; 42 ltmp=0;
41 43
42 if( pHwData->SurpriseRemove ) return; 44 if( pHwData->SurpriseRemove ) return;
43 45
44 if( pHwData->LED_control ) { 46 if( pHwData->LED_control ) {
45 ltmp2 = pHwData->LED_control & 0xff; 47 ltmp2 = pHwData->LED_control & 0xff;
46 if( ltmp2 == 5 ) // 5 is WPS mode 48 if( ltmp2 == 5 ) // 5 is WPS mode
47 { 49 {
48 TimeInterval = 100; 50 TimeInterval = 100;
49 ltmp2 = (pHwData->LED_control>>8) & 0xff; 51 ltmp2 = (pHwData->LED_control>>8) & 0xff;
50 switch( ltmp2 ) 52 switch( ltmp2 )
51 { 53 {
52 case 1: // [0.2 On][0.1 Off]... 54 case 1: // [0.2 On][0.1 Off]...
53 pHwData->LED_Blinking %= 3; 55 pHwData->LED_Blinking %= 3;
54 ltmp = 0x1010; // Led 1 & 0 Green and Red 56 ltmp = 0x1010; // Led 1 & 0 Green and Red
55 if( pHwData->LED_Blinking == 2 ) // Turn off 57 if( pHwData->LED_Blinking == 2 ) // Turn off
56 ltmp = 0; 58 ltmp = 0;
57 break; 59 break;
58 case 2: // [0.1 On][0.1 Off]... 60 case 2: // [0.1 On][0.1 Off]...
59 pHwData->LED_Blinking %= 2; 61 pHwData->LED_Blinking %= 2;
60 ltmp = 0x0010; // Led 0 red color 62 ltmp = 0x0010; // Led 0 red color
61 if( pHwData->LED_Blinking ) // Turn off 63 if( pHwData->LED_Blinking ) // Turn off
62 ltmp = 0; 64 ltmp = 0;
63 break; 65 break;
64 case 3: // [0.1 On][0.1 Off][0.1 On][0.1 Off][0.1 On][0.1 Off][0.1 On][0.1 Off][0.1 On][0.1 Off][0.5 Off]... 66 case 3: // [0.1 On][0.1 Off][0.1 On][0.1 Off][0.1 On][0.1 Off][0.1 On][0.1 Off][0.1 On][0.1 Off][0.5 Off]...
65 pHwData->LED_Blinking %= 15; 67 pHwData->LED_Blinking %= 15;
66 ltmp = 0x0010; // Led 0 red color 68 ltmp = 0x0010; // Led 0 red color
67 if( (pHwData->LED_Blinking >= 9) || (pHwData->LED_Blinking%2) ) // Turn off 0.6 sec 69 if( (pHwData->LED_Blinking >= 9) || (pHwData->LED_Blinking%2) ) // Turn off 0.6 sec
68 ltmp = 0; 70 ltmp = 0;
69 break; 71 break;
70 case 4: // [300 On][ off ] 72 case 4: // [300 On][ off ]
71 ltmp = 0x1000; // Led 1 Green color 73 ltmp = 0x1000; // Led 1 Green color
72 if( pHwData->LED_Blinking >= 3000 ) 74 if( pHwData->LED_Blinking >= 3000 )
73 ltmp = 0; // led maybe on after 300sec * 32bit counter overlap. 75 ltmp = 0; // led maybe on after 300sec * 32bit counter overlap.
74 break; 76 break;
75 } 77 }
76 pHwData->LED_Blinking++; 78 pHwData->LED_Blinking++;
77 79
78 reg->U1BC_LEDConfigure = ltmp; 80 reg->U1BC_LEDConfigure = ltmp;
79 if( LEDSet != 7 ) // Only 111 mode has 2 LEDs on PCB. 81 if( LEDSet != 7 ) // Only 111 mode has 2 LEDs on PCB.
80 { 82 {
81 reg->U1BC_LEDConfigure |= (ltmp &0xff)<<8; // Copy LED result to each LED control register 83 reg->U1BC_LEDConfigure |= (ltmp &0xff)<<8; // Copy LED result to each LED control register
82 reg->U1BC_LEDConfigure |= (ltmp &0xff00)>>8; 84 reg->U1BC_LEDConfigure |= (ltmp &0xff00)>>8;
83 } 85 }
84 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); 86 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure );
85 } 87 }
86 } 88 }
87 else if( pHwData->CurrentRadioSw || pHwData->CurrentRadioHw ) // If radio off 89 else if( pHwData->CurrentRadioSw || pHwData->CurrentRadioHw ) // If radio off
88 { 90 {
89 if( reg->U1BC_LEDConfigure & 0x1010 ) 91 if( reg->U1BC_LEDConfigure & 0x1010 )
90 { 92 {
91 reg->U1BC_LEDConfigure &= ~0x1010; 93 reg->U1BC_LEDConfigure &= ~0x1010;
92 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); 94 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure );
93 } 95 }
94 } 96 }
95 else 97 else
96 { 98 {
97 switch( LEDSet ) 99 switch( LEDSet )
98 { 100 {
99 case 4: // [100] Only 1 Led be placed on PCB and use pin 21 of IC. Use LED_0 for showing 101 case 4: // [100] Only 1 Led be placed on PCB and use pin 21 of IC. Use LED_0 for showing
100 if( !pHwData->LED_LinkOn ) // Blink only if not Link On 102 if( !pHwData->LED_LinkOn ) // Blink only if not Link On
101 { 103 {
102 // Blinking if scanning is on progress 104 // Blinking if scanning is on progress
103 if( pHwData->LED_Scanning ) 105 if( pHwData->LED_Scanning )
104 { 106 {
105 if( pHwData->LED_Blinking == 0 ) 107 if( pHwData->LED_Blinking == 0 )
106 { 108 {
107 reg->U1BC_LEDConfigure |= 0x10; 109 reg->U1BC_LEDConfigure |= 0x10;
108 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_0 On 110 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_0 On
109 pHwData->LED_Blinking = 1; 111 pHwData->LED_Blinking = 1;
110 TimeInterval = 300; 112 TimeInterval = 300;
111 } 113 }
112 else 114 else
113 { 115 {
114 reg->U1BC_LEDConfigure &= ~0x10; 116 reg->U1BC_LEDConfigure &= ~0x10;
115 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_0 Off 117 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_0 Off
116 pHwData->LED_Blinking = 0; 118 pHwData->LED_Blinking = 0;
117 TimeInterval = 300; 119 TimeInterval = 300;
118 } 120 }
119 } 121 }
120 else 122 else
121 { 123 {
122 //Turn Off LED_0 124 //Turn Off LED_0
123 if( reg->U1BC_LEDConfigure & 0x10 ) 125 if( reg->U1BC_LEDConfigure & 0x10 )
124 { 126 {
125 reg->U1BC_LEDConfigure &= ~0x10; 127 reg->U1BC_LEDConfigure &= ~0x10;
126 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_0 Off 128 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_0 Off
127 } 129 }
128 } 130 }
129 } 131 }
130 else 132 else
131 { 133 {
132 // Turn On LED_0 134 // Turn On LED_0
133 if( (reg->U1BC_LEDConfigure & 0x10) == 0 ) 135 if( (reg->U1BC_LEDConfigure & 0x10) == 0 )
134 { 136 {
135 reg->U1BC_LEDConfigure |= 0x10; 137 reg->U1BC_LEDConfigure |= 0x10;
136 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_0 Off 138 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_0 Off
137 } 139 }
138 } 140 }
139 break; 141 break;
140 142
141 case 6: // [110] Only 1 Led be placed on PCB and use pin 21 of IC. Use LED_0 for showing 143 case 6: // [110] Only 1 Led be placed on PCB and use pin 21 of IC. Use LED_0 for showing
142 if( !pHwData->LED_LinkOn ) // Blink only if not Link On 144 if( !pHwData->LED_LinkOn ) // Blink only if not Link On
143 { 145 {
144 // Blinking if scanning is on progress 146 // Blinking if scanning is on progress
145 if( pHwData->LED_Scanning ) 147 if( pHwData->LED_Scanning )
146 { 148 {
147 if( pHwData->LED_Blinking == 0 ) 149 if( pHwData->LED_Blinking == 0 )
148 { 150 {
149 reg->U1BC_LEDConfigure &= ~0xf; 151 reg->U1BC_LEDConfigure &= ~0xf;
150 reg->U1BC_LEDConfigure |= 0x10; 152 reg->U1BC_LEDConfigure |= 0x10;
151 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_0 On 153 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_0 On
152 pHwData->LED_Blinking = 1; 154 pHwData->LED_Blinking = 1;
153 TimeInterval = 300; 155 TimeInterval = 300;
154 } 156 }
155 else 157 else
156 { 158 {
157 reg->U1BC_LEDConfigure &= ~0x1f; 159 reg->U1BC_LEDConfigure &= ~0x1f;
158 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_0 Off 160 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_0 Off
159 pHwData->LED_Blinking = 0; 161 pHwData->LED_Blinking = 0;
160 TimeInterval = 300; 162 TimeInterval = 300;
161 } 163 }
162 } 164 }
163 else 165 else
164 { 166 {
165 // 20060901 Gray blinking if in disconnect state and not scanning 167 // 20060901 Gray blinking if in disconnect state and not scanning
166 ltmp = reg->U1BC_LEDConfigure; 168 ltmp = reg->U1BC_LEDConfigure;
167 reg->U1BC_LEDConfigure &= ~0x1f; 169 reg->U1BC_LEDConfigure &= ~0x1f;
168 if( LEDgray2[(pHwData->LED_Blinking%30)] ) 170 if( LEDgray2[(pHwData->LED_Blinking%30)] )
169 { 171 {
170 reg->U1BC_LEDConfigure |= 0x10; 172 reg->U1BC_LEDConfigure |= 0x10;
171 reg->U1BC_LEDConfigure |= LEDgray2[ (pHwData->LED_Blinking%30) ]; 173 reg->U1BC_LEDConfigure |= LEDgray2[ (pHwData->LED_Blinking%30) ];
172 } 174 }
173 pHwData->LED_Blinking++; 175 pHwData->LED_Blinking++;
174 if( reg->U1BC_LEDConfigure != ltmp ) 176 if( reg->U1BC_LEDConfigure != ltmp )
175 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_0 Off 177 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_0 Off
176 TimeInterval = 100; 178 TimeInterval = 100;
177 } 179 }
178 } 180 }
179 else 181 else
180 { 182 {
181 // Turn On LED_0 183 // Turn On LED_0
182 if( (reg->U1BC_LEDConfigure & 0x10) == 0 ) 184 if( (reg->U1BC_LEDConfigure & 0x10) == 0 )
183 { 185 {
184 reg->U1BC_LEDConfigure |= 0x10; 186 reg->U1BC_LEDConfigure |= 0x10;
185 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_0 Off 187 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_0 Off
186 } 188 }
187 } 189 }
188 break; 190 break;
189 191
190 case 5: // [101] Only 1 Led be placed on PCB and use LED_1 for showing 192 case 5: // [101] Only 1 Led be placed on PCB and use LED_1 for showing
191 if( !pHwData->LED_LinkOn ) // Blink only if not Link On 193 if( !pHwData->LED_LinkOn ) // Blink only if not Link On
192 { 194 {
193 // Blinking if scanning is on progress 195 // Blinking if scanning is on progress
194 if( pHwData->LED_Scanning ) 196 if( pHwData->LED_Scanning )
195 { 197 {
196 if( pHwData->LED_Blinking == 0 ) 198 if( pHwData->LED_Blinking == 0 )
197 { 199 {
198 reg->U1BC_LEDConfigure |= 0x1000; 200 reg->U1BC_LEDConfigure |= 0x1000;
199 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_1 On 201 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_1 On
200 pHwData->LED_Blinking = 1; 202 pHwData->LED_Blinking = 1;
201 TimeInterval = 300; 203 TimeInterval = 300;
202 } 204 }
203 else 205 else
204 { 206 {
205 reg->U1BC_LEDConfigure &= ~0x1000; 207 reg->U1BC_LEDConfigure &= ~0x1000;
206 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_1 Off 208 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_1 Off
207 pHwData->LED_Blinking = 0; 209 pHwData->LED_Blinking = 0;
208 TimeInterval = 300; 210 TimeInterval = 300;
209 } 211 }
210 } 212 }
211 else 213 else
212 { 214 {
213 //Turn Off LED_1 215 //Turn Off LED_1
214 if( reg->U1BC_LEDConfigure & 0x1000 ) 216 if( reg->U1BC_LEDConfigure & 0x1000 )
215 { 217 {
216 reg->U1BC_LEDConfigure &= ~0x1000; 218 reg->U1BC_LEDConfigure &= ~0x1000;
217 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_1 Off 219 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_1 Off
218 } 220 }
219 } 221 }
220 } 222 }
221 else 223 else
222 { 224 {
223 // Is transmitting/receiving ?? 225 // Is transmitting/receiving ??
224 if( (OS_CURRENT_RX_BYTE( adapter ) != pHwData->RxByteCountLast ) || 226 if( (OS_CURRENT_RX_BYTE( adapter ) != pHwData->RxByteCountLast ) ||
225 (OS_CURRENT_TX_BYTE( adapter ) != pHwData->TxByteCountLast ) ) 227 (OS_CURRENT_TX_BYTE( adapter ) != pHwData->TxByteCountLast ) )
226 { 228 {
227 if( (reg->U1BC_LEDConfigure & 0x3000) != 0x3000 ) 229 if( (reg->U1BC_LEDConfigure & 0x3000) != 0x3000 )
228 { 230 {
229 reg->U1BC_LEDConfigure |= 0x3000; 231 reg->U1BC_LEDConfigure |= 0x3000;
230 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_1 On 232 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_1 On
231 } 233 }
232 234
233 // Update variable 235 // Update variable
234 pHwData->RxByteCountLast = OS_CURRENT_RX_BYTE( adapter ); 236 pHwData->RxByteCountLast = OS_CURRENT_RX_BYTE( adapter );
235 pHwData->TxByteCountLast = OS_CURRENT_TX_BYTE( adapter ); 237 pHwData->TxByteCountLast = OS_CURRENT_TX_BYTE( adapter );
236 TimeInterval = 200; 238 TimeInterval = 200;
237 } 239 }
238 else 240 else
239 { 241 {
240 // Turn On LED_1 and blinking if transmitting/receiving 242 // Turn On LED_1 and blinking if transmitting/receiving
241 if( (reg->U1BC_LEDConfigure & 0x3000) != 0x1000 ) 243 if( (reg->U1BC_LEDConfigure & 0x3000) != 0x1000 )
242 { 244 {
243 reg->U1BC_LEDConfigure &= ~0x3000; 245 reg->U1BC_LEDConfigure &= ~0x3000;
244 reg->U1BC_LEDConfigure |= 0x1000; 246 reg->U1BC_LEDConfigure |= 0x1000;
245 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_1 On 247 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); // LED_1 On
246 } 248 }
247 } 249 }
248 } 250 }
249 break; 251 break;
250 252
251 default: // Default setting. 2 LED be placed on PCB. LED_0: Link On LED_1 Active 253 default: // Default setting. 2 LED be placed on PCB. LED_0: Link On LED_1 Active
252 if( (reg->U1BC_LEDConfigure & 0x3000) != 0x3000 ) 254 if( (reg->U1BC_LEDConfigure & 0x3000) != 0x3000 )
253 { 255 {
254 reg->U1BC_LEDConfigure |= 0x3000;// LED_1 is always on and event enable 256 reg->U1BC_LEDConfigure |= 0x3000;// LED_1 is always on and event enable
255 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); 257 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure );
256 } 258 }
257 259
258 if( pHwData->LED_Blinking ) 260 if( pHwData->LED_Blinking )
259 { 261 {
260 // Gray blinking 262 // Gray blinking
261 reg->U1BC_LEDConfigure &= ~0x0f; 263 reg->U1BC_LEDConfigure &= ~0x0f;
262 reg->U1BC_LEDConfigure |= 0x10; 264 reg->U1BC_LEDConfigure |= 0x10;
263 reg->U1BC_LEDConfigure |= LEDgray[ (pHwData->LED_Blinking-1)%20 ]; 265 reg->U1BC_LEDConfigure |= LEDgray[ (pHwData->LED_Blinking-1)%20 ];
264 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); 266 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure );
265 267
266 pHwData->LED_Blinking += 2; 268 pHwData->LED_Blinking += 2;
267 if( pHwData->LED_Blinking < 40 ) 269 if( pHwData->LED_Blinking < 40 )
268 TimeInterval = 100; 270 TimeInterval = 100;
269 else 271 else
270 { 272 {
271 pHwData->LED_Blinking = 0; // Stop blinking 273 pHwData->LED_Blinking = 0; // Stop blinking
272 reg->U1BC_LEDConfigure &= ~0x0f; 274 reg->U1BC_LEDConfigure &= ~0x0f;
273 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); 275 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure );
274 } 276 }
275 break; 277 break;
276 } 278 }
277 279
278 if( pHwData->LED_LinkOn ) 280 if( pHwData->LED_LinkOn )
279 { 281 {
280 if( !(reg->U1BC_LEDConfigure & 0x10) ) // Check the LED_0 282 if( !(reg->U1BC_LEDConfigure & 0x10) ) // Check the LED_0
281 { 283 {
282 //Try to turn ON LED_0 after gray blinking 284 //Try to turn ON LED_0 after gray blinking
283 reg->U1BC_LEDConfigure |= 0x10; 285 reg->U1BC_LEDConfigure |= 0x10;
284 pHwData->LED_Blinking = 1; //Start blinking 286 pHwData->LED_Blinking = 1; //Start blinking
285 TimeInterval = 50; 287 TimeInterval = 50;
286 } 288 }
287 } 289 }
288 else 290 else
289 { 291 {
290 if( reg->U1BC_LEDConfigure & 0x10 ) // Check the LED_0 292 if( reg->U1BC_LEDConfigure & 0x10 ) // Check the LED_0
291 { 293 {
292 reg->U1BC_LEDConfigure &= ~0x10; 294 reg->U1BC_LEDConfigure &= ~0x10;
293 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure ); 295 Wb35Reg_Write( pHwData, 0x03bc, reg->U1BC_LEDConfigure );
294 } 296 }
295 } 297 }
296 break; 298 break;
297 } 299 }
298 300
299 //20060828.1 Active send null packet to avoid AP disconnect 301 //20060828.1 Active send null packet to avoid AP disconnect
300 if( pHwData->LED_LinkOn ) 302 if( pHwData->LED_LinkOn )
301 { 303 {
302 pHwData->NullPacketCount += TimeInterval; 304 pHwData->NullPacketCount += TimeInterval;
303 if( pHwData->NullPacketCount >= DEFAULT_NULL_PACKET_COUNT ) 305 if( pHwData->NullPacketCount >= DEFAULT_NULL_PACKET_COUNT )
304 { 306 {
305 pHwData->NullPacketCount = 0; 307 pHwData->NullPacketCount = 0;
306 } 308 }
307 } 309 }
308 } 310 }
309 311
310 pHwData->time_count += TimeInterval; 312 pHwData->time_count += TimeInterval;
311 Wb35Tx_CurrentTime( pHwData, pHwData->time_count ); // 20060928 add 313 Wb35Tx_CurrentTime( pHwData, pHwData->time_count ); // 20060928 add
312 pHwData->LEDTimer.expires = jiffies + msecs_to_jiffies(TimeInterval); 314 pHwData->LEDTimer.expires = jiffies + msecs_to_jiffies(TimeInterval);
313 add_timer(&pHwData->LEDTimer); 315 add_timer(&pHwData->LEDTimer);
314 } 316 }
315 317
316 318
317 u8 hal_init_hardware(phw_data_t pHwData, struct wb35_adapter * adapter) 319 u8 hal_init_hardware(phw_data_t pHwData, struct wb35_adapter * adapter)
318 { 320 {
319 u16 SoftwareSet; 321 u16 SoftwareSet;
320 pHwData->adapter = adapter; 322 pHwData->adapter = adapter;
321 323
322 // Initial the variable 324 // Initial the variable
323 pHwData->MaxReceiveLifeTime = DEFAULT_MSDU_LIFE_TIME; // Setting Rx maximum MSDU life time 325 pHwData->MaxReceiveLifeTime = DEFAULT_MSDU_LIFE_TIME; // Setting Rx maximum MSDU life time
324 pHwData->FragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD; // Setting default fragment threshold 326 pHwData->FragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD; // Setting default fragment threshold
325 327
326 pHwData->InitialResource = 1; 328 pHwData->InitialResource = 1;
327 if( Wb35Reg_initial(pHwData)) { 329 if( Wb35Reg_initial(pHwData)) {
328 pHwData->InitialResource = 2; 330 pHwData->InitialResource = 2;
329 if (Wb35Tx_initial(pHwData)) { 331 if (Wb35Tx_initial(pHwData)) {
330 pHwData->InitialResource = 3; 332 pHwData->InitialResource = 3;
331 if (Wb35Rx_initial(pHwData)) { 333 if (Wb35Rx_initial(pHwData)) {
332 pHwData->InitialResource = 4; 334 pHwData->InitialResource = 4;
333 init_timer(&pHwData->LEDTimer); 335 init_timer(&pHwData->LEDTimer);
334 pHwData->LEDTimer.function = hal_led_control; 336 pHwData->LEDTimer.function = hal_led_control;
335 pHwData->LEDTimer.data = (unsigned long) pHwData; 337 pHwData->LEDTimer.data = (unsigned long) pHwData;
336 pHwData->LEDTimer.expires = jiffies + msecs_to_jiffies(1000); 338 pHwData->LEDTimer.expires = jiffies + msecs_to_jiffies(1000);
337 add_timer(&pHwData->LEDTimer); 339 add_timer(&pHwData->LEDTimer);
338 340
339 // 341 //
340 // For restrict to vendor's hardware 342 // For restrict to vendor's hardware
341 // 343 //
342 SoftwareSet = hal_software_set( pHwData ); 344 SoftwareSet = hal_software_set( pHwData );
343 345
344 #ifdef Vendor2 346 #ifdef Vendor2
345 // Try to make sure the EEPROM contain 347 // Try to make sure the EEPROM contain
346 SoftwareSet >>= 8; 348 SoftwareSet >>= 8;
347 if( SoftwareSet != 0x82 ) 349 if( SoftwareSet != 0x82 )
348 return false; 350 return false;
349 #endif 351 #endif
350 352
351 Wb35Rx_start( pHwData ); 353 Wb35Rx_start( pHwData );
352 Wb35Tx_EP2VM_start( pHwData ); 354 Wb35Tx_EP2VM_start( pHwData );
353 355
354 return true; 356 return true;
355 } 357 }
356 } 358 }
357 } 359 }
358 360
359 pHwData->SurpriseRemove = 1; 361 pHwData->SurpriseRemove = 1;
360 return false; 362 return false;
361 } 363 }
362 364
363 365
364 void hal_halt(phw_data_t pHwData, void *ppa_data) 366 void hal_halt(phw_data_t pHwData, void *ppa_data)
365 { 367 {
366 switch( pHwData->InitialResource ) 368 switch( pHwData->InitialResource )
367 { 369 {
368 case 4: 370 case 4:
369 case 3: del_timer_sync(&pHwData->LEDTimer); 371 case 3: del_timer_sync(&pHwData->LEDTimer);
370 msleep(100); // Wait for Timer DPC exit 940623.2 372 msleep(100); // Wait for Timer DPC exit 940623.2
371 Wb35Rx_destroy( pHwData ); // Release the Rx 373 Wb35Rx_destroy( pHwData ); // Release the Rx
372 case 2: Wb35Tx_destroy( pHwData ); // Release the Tx 374 case 2: Wb35Tx_destroy( pHwData ); // Release the Tx
373 case 1: Wb35Reg_destroy( pHwData ); // Release the Wb35 Regisster resources 375 case 1: Wb35Reg_destroy( pHwData ); // Release the Wb35 Regisster resources
374 } 376 }
375 } 377 }
376 378
377 //--------------------------------------------------------------------------------------------------- 379 //---------------------------------------------------------------------------------------------------
378 void hal_set_rates(phw_data_t pHwData, u8 *pbss_rates, 380 void hal_set_rates(phw_data_t pHwData, u8 *pbss_rates,
379 u8 length, unsigned char basic_rate_set) 381 u8 length, unsigned char basic_rate_set)
380 { 382 {
381 struct wb35_reg *reg = &pHwData->reg; 383 struct wb35_reg *reg = &pHwData->reg;
382 u32 tmp, tmp1; 384 u32 tmp, tmp1;
383 u8 Rate[12]={ 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 }; 385 u8 Rate[12]={ 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 };
384 u8 SupportedRate[16]; 386 u8 SupportedRate[16];
385 u8 i, j, k, Count1, Count2, Byte; 387 u8 i, j, k, Count1, Count2, Byte;
386 388
387 if( pHwData->SurpriseRemove ) return; 389 if( pHwData->SurpriseRemove ) return;
388 390
389 if (basic_rate_set) { 391 if (basic_rate_set) {
390 reg->M28_MacControl &= ~0x000fff00; 392 reg->M28_MacControl &= ~0x000fff00;
391 tmp1 = 0x00000100; 393 tmp1 = 0x00000100;
392 } else { 394 } else {
393 reg->M28_MacControl &= ~0xfff00000; 395 reg->M28_MacControl &= ~0xfff00000;
394 tmp1 = 0x00100000; 396 tmp1 = 0x00100000;
395 } 397 }
396 398
397 tmp = 0; 399 tmp = 0;
398 for (i=0; i<length; i++) { 400 for (i=0; i<length; i++) {
399 Byte = pbss_rates[i] & 0x7f; 401 Byte = pbss_rates[i] & 0x7f;
400 for (j=0; j<12; j++) { 402 for (j=0; j<12; j++) {
401 if( Byte == Rate[j] ) 403 if( Byte == Rate[j] )
402 break; 404 break;
403 } 405 }
404 406
405 if (j < 12) 407 if (j < 12)
406 tmp |= (tmp1<<j); 408 tmp |= (tmp1<<j);
407 } 409 }
408 410
409 reg->M28_MacControl |= tmp; 411 reg->M28_MacControl |= tmp;
410 Wb35Reg_Write( pHwData, 0x0828, reg->M28_MacControl ); 412 Wb35Reg_Write( pHwData, 0x0828, reg->M28_MacControl );
411 413
412 // 930206.2.c M78 setting 414 // 930206.2.c M78 setting
413 j = k = Count1 = Count2 = 0; 415 j = k = Count1 = Count2 = 0;
414 memset( SupportedRate, 0, 16 ); 416 memset( SupportedRate, 0, 16 );
415 tmp = 0x00100000; 417 tmp = 0x00100000;
416 tmp1 = 0x00000100; 418 tmp1 = 0x00000100;
417 for (i=0; i<12; i++) { // Get the supported rate 419 for (i=0; i<12; i++) { // Get the supported rate
418 if (tmp & reg->M28_MacControl) { 420 if (tmp & reg->M28_MacControl) {
419 SupportedRate[j] = Rate[i]; 421 SupportedRate[j] = Rate[i];
420 422
421 if (tmp1 & reg->M28_MacControl) 423 if (tmp1 & reg->M28_MacControl)
422 SupportedRate[j] |= 0x80; 424 SupportedRate[j] |= 0x80;
423 425
424 if (k) 426 if (k)
425 Count2++; 427 Count2++;
426 else 428 else
427 Count1++; 429 Count1++;
428 430
429 j++; 431 j++;
430 } 432 }
431 433
432 if (i==4 && k==0) { 434 if (i==4 && k==0) {
433 if( !(reg->M28_MacControl & 0x000ff000) ) // if basic rate in 11g domain) 435 if( !(reg->M28_MacControl & 0x000ff000) ) // if basic rate in 11g domain)
434 { 436 {
435 k = 1; 437 k = 1;
436 j = 8; 438 j = 8;
437 } 439 }
438 } 440 }
439 441
440 tmp <<= 1; 442 tmp <<= 1;
441 tmp1 <<= 1; 443 tmp1 <<= 1;
442 } 444 }
443 445
444 // Fill data into support rate until buffer full 446 // Fill data into support rate until buffer full
445 //---20060926 add by anson's endian 447 //---20060926 add by anson's endian
446 for (i=0; i<4; i++) 448 for (i=0; i<4; i++)
447 *(u32 *)(SupportedRate+(i<<2)) = cpu_to_le32( *(u32 *)(SupportedRate+(i<<2)) ); 449 *(u32 *)(SupportedRate+(i<<2)) = cpu_to_le32( *(u32 *)(SupportedRate+(i<<2)) );
448 //--- end 20060926 add by anson's endian 450 //--- end 20060926 add by anson's endian
449 Wb35Reg_BurstWrite( pHwData,0x087c, (u32 *)SupportedRate, 4, AUTO_INCREMENT ); 451 Wb35Reg_BurstWrite( pHwData,0x087c, (u32 *)SupportedRate, 4, AUTO_INCREMENT );
450 reg->M7C_MacControl = ((u32 *)SupportedRate)[0]; 452 reg->M7C_MacControl = ((u32 *)SupportedRate)[0];
451 reg->M80_MacControl = ((u32 *)SupportedRate)[1]; 453 reg->M80_MacControl = ((u32 *)SupportedRate)[1];
452 reg->M84_MacControl = ((u32 *)SupportedRate)[2]; 454 reg->M84_MacControl = ((u32 *)SupportedRate)[2];
453 reg->M88_MacControl = ((u32 *)SupportedRate)[3]; 455 reg->M88_MacControl = ((u32 *)SupportedRate)[3];
454 456
455 // Fill length 457 // Fill length
456 tmp = Count1<<28 | Count2<<24; 458 tmp = Count1<<28 | Count2<<24;
457 reg->M78_ERPInformation &= ~0xff000000; 459 reg->M78_ERPInformation &= ~0xff000000;
458 reg->M78_ERPInformation |= tmp; 460 reg->M78_ERPInformation |= tmp;
459 Wb35Reg_Write( pHwData, 0x0878, reg->M78_ERPInformation ); 461 Wb35Reg_Write( pHwData, 0x0878, reg->M78_ERPInformation );
460 } 462 }
461 463
462 464
463 //--------------------------------------------------------------------------------------------------- 465 //---------------------------------------------------------------------------------------------------
464 void hal_set_beacon_period( phw_data_t pHwData, u16 beacon_period ) 466 void hal_set_beacon_period( phw_data_t pHwData, u16 beacon_period )
465 { 467 {
466 u32 tmp; 468 u32 tmp;
467 469
468 if( pHwData->SurpriseRemove ) return; 470 if( pHwData->SurpriseRemove ) return;
469 471
470 pHwData->BeaconPeriod = beacon_period; 472 pHwData->BeaconPeriod = beacon_period;
471 tmp = pHwData->BeaconPeriod << 16; 473 tmp = pHwData->BeaconPeriod << 16;
472 tmp |= pHwData->ProbeDelay; 474 tmp |= pHwData->ProbeDelay;
473 Wb35Reg_Write( pHwData, 0x0848, tmp ); 475 Wb35Reg_Write( pHwData, 0x0848, tmp );
474 } 476 }
475 477
476 478
477 void hal_set_current_channel_ex( phw_data_t pHwData, ChanInfo channel ) 479 void hal_set_current_channel_ex( phw_data_t pHwData, ChanInfo channel )
478 { 480 {
479 struct wb35_reg *reg = &pHwData->reg; 481 struct wb35_reg *reg = &pHwData->reg;
480 482
481 if( pHwData->SurpriseRemove ) 483 if( pHwData->SurpriseRemove )
482 return; 484 return;
483 485
484 printk("Going to channel: %d/%d\n", channel.band, channel.ChanNo); 486 printk("Going to channel: %d/%d\n", channel.band, channel.ChanNo);
485 487
486 RFSynthesizer_SwitchingChannel( pHwData, channel );// Switch channel 488 RFSynthesizer_SwitchingChannel( pHwData, channel );// Switch channel
487 pHwData->Channel = channel.ChanNo; 489 pHwData->Channel = channel.ChanNo;
488 pHwData->band = channel.band; 490 pHwData->band = channel.band;
489 #ifdef _PE_STATE_DUMP_ 491 #ifdef _PE_STATE_DUMP_
490 WBDEBUG(("Set channel is %d, band =%d\n", pHwData->Channel, pHwData->band)); 492 WBDEBUG(("Set channel is %d, band =%d\n", pHwData->Channel, pHwData->band));
491 #endif 493 #endif
492 reg->M28_MacControl &= ~0xff; // Clean channel information field 494 reg->M28_MacControl &= ~0xff; // Clean channel information field
493 reg->M28_MacControl |= channel.ChanNo; 495 reg->M28_MacControl |= channel.ChanNo;
494 Wb35Reg_WriteWithCallbackValue( pHwData, 0x0828, reg->M28_MacControl, 496 Wb35Reg_WriteWithCallbackValue( pHwData, 0x0828, reg->M28_MacControl,
495 (s8 *)&channel, sizeof(ChanInfo)); 497 (s8 *)&channel, sizeof(ChanInfo));
496 } 498 }
497 //--------------------------------------------------------------------------------------------------- 499 //---------------------------------------------------------------------------------------------------
498 void hal_set_current_channel( phw_data_t pHwData, ChanInfo channel ) 500 void hal_set_current_channel( phw_data_t pHwData, ChanInfo channel )
499 { 501 {
500 hal_set_current_channel_ex( pHwData, channel ); 502 hal_set_current_channel_ex( pHwData, channel );
501 } 503 }
502 //--------------------------------------------------------------------------------------------------- 504 //---------------------------------------------------------------------------------------------------
503 void hal_get_current_channel( phw_data_t pHwData, ChanInfo *channel ) 505 void hal_get_current_channel( phw_data_t pHwData, ChanInfo *channel )
504 { 506 {
505 channel->ChanNo = pHwData->Channel; 507 channel->ChanNo = pHwData->Channel;
506 channel->band = pHwData->band; 508 channel->band = pHwData->band;
507 } 509 }
508 //--------------------------------------------------------------------------------------------------- 510 //---------------------------------------------------------------------------------------------------
509 void hal_set_accept_broadcast( phw_data_t pHwData, u8 enable ) 511 void hal_set_accept_broadcast( phw_data_t pHwData, u8 enable )
510 { 512 {
511 struct wb35_reg *reg = &pHwData->reg; 513 struct wb35_reg *reg = &pHwData->reg;
512 514
513 if( pHwData->SurpriseRemove ) return; 515 if( pHwData->SurpriseRemove ) return;
514 516
515 reg->M00_MacControl &= ~0x02000000;//The HW value 517 reg->M00_MacControl &= ~0x02000000;//The HW value
516 518
517 if (enable) 519 if (enable)
518 reg->M00_MacControl |= 0x02000000;//The HW value 520 reg->M00_MacControl |= 0x02000000;//The HW value
519 521
520 Wb35Reg_Write( pHwData, 0x0800, reg->M00_MacControl ); 522 Wb35Reg_Write( pHwData, 0x0800, reg->M00_MacControl );
521 } 523 }
522 524
523 //for wep key error detection, we need to accept broadcast packets to be received temporary. 525 //for wep key error detection, we need to accept broadcast packets to be received temporary.
524 void hal_set_accept_promiscuous( phw_data_t pHwData, u8 enable) 526 void hal_set_accept_promiscuous( phw_data_t pHwData, u8 enable)
525 { 527 {
526 struct wb35_reg *reg = &pHwData->reg; 528 struct wb35_reg *reg = &pHwData->reg;
527 529
528 if (pHwData->SurpriseRemove) return; 530 if (pHwData->SurpriseRemove) return;
529 if (enable) { 531 if (enable) {
530 reg->M00_MacControl |= 0x00400000; 532 reg->M00_MacControl |= 0x00400000;
531 Wb35Reg_Write( pHwData, 0x0800, reg->M00_MacControl ); 533 Wb35Reg_Write( pHwData, 0x0800, reg->M00_MacControl );
532 } else { 534 } else {
533 reg->M00_MacControl&=~0x00400000; 535 reg->M00_MacControl&=~0x00400000;
534 Wb35Reg_Write( pHwData, 0x0800, reg->M00_MacControl ); 536 Wb35Reg_Write( pHwData, 0x0800, reg->M00_MacControl );
535 } 537 }
536 } 538 }
537 539
538 void hal_set_accept_multicast( phw_data_t pHwData, u8 enable ) 540 void hal_set_accept_multicast( phw_data_t pHwData, u8 enable )
539 { 541 {
540 struct wb35_reg *reg = &pHwData->reg; 542 struct wb35_reg *reg = &pHwData->reg;
541 543
542 if( pHwData->SurpriseRemove ) return; 544 if( pHwData->SurpriseRemove ) return;
543 545
544 reg->M00_MacControl &= ~0x01000000;//The HW value 546 reg->M00_MacControl &= ~0x01000000;//The HW value
545 if (enable) reg->M00_MacControl |= 0x01000000;//The HW value 547 if (enable) reg->M00_MacControl |= 0x01000000;//The HW value
546 Wb35Reg_Write( pHwData, 0x0800, reg->M00_MacControl ); 548 Wb35Reg_Write( pHwData, 0x0800, reg->M00_MacControl );
547 } 549 }
548 550
549 void hal_set_accept_beacon( phw_data_t pHwData, u8 enable ) 551 void hal_set_accept_beacon( phw_data_t pHwData, u8 enable )
550 { 552 {
551 struct wb35_reg *reg = &pHwData->reg; 553 struct wb35_reg *reg = &pHwData->reg;
552 554
553 if( pHwData->SurpriseRemove ) return; 555 if( pHwData->SurpriseRemove ) return;
554 556
555 // 20040108 debug 557 // 20040108 debug
556 if( !enable )//Due to SME and MLME are not suitable for 35 558 if( !enable )//Due to SME and MLME are not suitable for 35
557 return; 559 return;
558 560
559 reg->M00_MacControl &= ~0x04000000;//The HW value 561 reg->M00_MacControl &= ~0x04000000;//The HW value
560 if( enable ) 562 if( enable )
561 reg->M00_MacControl |= 0x04000000;//The HW value 563 reg->M00_MacControl |= 0x04000000;//The HW value
562 564
563 Wb35Reg_Write( pHwData, 0x0800, reg->M00_MacControl ); 565 Wb35Reg_Write( pHwData, 0x0800, reg->M00_MacControl );
564 } 566 }
565 //--------------------------------------------------------------------------------------------------- 567 //---------------------------------------------------------------------------------------------------
566 void hal_set_multicast_address( phw_data_t pHwData, u8 *address, u8 number ) 568 void hal_set_multicast_address( phw_data_t pHwData, u8 *address, u8 number )
567 { 569 {
568 struct wb35_reg *reg = &pHwData->reg; 570 struct wb35_reg *reg = &pHwData->reg;
569 u8 Byte, Bit; 571 u8 Byte, Bit;
570 572
571 if( pHwData->SurpriseRemove ) return; 573 if( pHwData->SurpriseRemove ) return;
572 574
573 //Erases and refills the card multicast registers. Used when an address 575 //Erases and refills the card multicast registers. Used when an address
574 // has been deleted and all bits must be recomputed. 576 // has been deleted and all bits must be recomputed.
575 reg->M04_MulticastAddress1 = 0; 577 reg->M04_MulticastAddress1 = 0;
576 reg->M08_MulticastAddress2 = 0; 578 reg->M08_MulticastAddress2 = 0;
577 579
578 while( number ) 580 while( number )
579 { 581 {
580 number--; 582 number--;
581 CardGetMulticastBit( (address+(number*ETH_LENGTH_OF_ADDRESS)), &Byte, &Bit); 583 CardGetMulticastBit( (address+(number*ETH_LENGTH_OF_ADDRESS)), &Byte, &Bit);
582 reg->Multicast[Byte] |= Bit; 584 reg->Multicast[Byte] |= Bit;
583 } 585 }
584 586
585 // Updating register 587 // Updating register
586 Wb35Reg_BurstWrite( pHwData, 0x0804, (u32 *)reg->Multicast, 2, AUTO_INCREMENT ); 588 Wb35Reg_BurstWrite( pHwData, 0x0804, (u32 *)reg->Multicast, 2, AUTO_INCREMENT );
587 } 589 }
588 //--------------------------------------------------------------------------------------------------- 590 //---------------------------------------------------------------------------------------------------
589 u8 hal_get_accept_beacon( phw_data_t pHwData ) 591 u8 hal_get_accept_beacon( phw_data_t pHwData )
590 { 592 {
591 struct wb35_reg *reg = &pHwData->reg; 593 struct wb35_reg *reg = &pHwData->reg;
592 594
593 if( pHwData->SurpriseRemove ) return 0; 595 if( pHwData->SurpriseRemove ) return 0;
594 596
595 if( reg->M00_MacControl & 0x04000000 ) 597 if( reg->M00_MacControl & 0x04000000 )
596 return 1; 598 return 1;
597 else 599 else
598 return 0; 600 return 0;
599 } 601 }
600 602
601 unsigned char hal_reset_hardware( phw_data_t pHwData, void* ppa ) 603 unsigned char hal_reset_hardware( phw_data_t pHwData, void* ppa )
602 { 604 {
603 // Not implement yet 605 // Not implement yet
604 return true; 606 return true;
605 } 607 }
606 608
607 void hal_stop( phw_data_t pHwData ) 609 void hal_stop( phw_data_t pHwData )
608 { 610 {
609 struct wb35_reg *reg = &pHwData->reg; 611 struct wb35_reg *reg = &pHwData->reg;
610 612
611 pHwData->Wb35Rx.rx_halt = 1; 613 pHwData->Wb35Rx.rx_halt = 1;
612 Wb35Rx_stop( pHwData ); 614 Wb35Rx_stop( pHwData );
613 615
614 pHwData->Wb35Tx.tx_halt = 1; 616 pHwData->Wb35Tx.tx_halt = 1;
615 Wb35Tx_stop( pHwData ); 617 Wb35Tx_stop( pHwData );
616 618
617 reg->D00_DmaControl &= ~0xc0000000;//Tx Off, Rx Off 619 reg->D00_DmaControl &= ~0xc0000000;//Tx Off, Rx Off
618 Wb35Reg_Write( pHwData, 0x0400, reg->D00_DmaControl ); 620 Wb35Reg_Write( pHwData, 0x0400, reg->D00_DmaControl );
619 } 621 }
620 622
621 unsigned char hal_idle(phw_data_t pHwData) 623 unsigned char hal_idle(phw_data_t pHwData)
622 { 624 {
623 struct wb35_reg *reg = &pHwData->reg; 625 struct wb35_reg *reg = &pHwData->reg;
624 PWBUSB pWbUsb = &pHwData->WbUsb; 626 PWBUSB pWbUsb = &pHwData->WbUsb;
625 627
626 if( !pHwData->SurpriseRemove && ( pWbUsb->DetectCount || reg->EP0vm_state!=VM_STOP ) ) 628 if( !pHwData->SurpriseRemove && ( pWbUsb->DetectCount || reg->EP0vm_state!=VM_STOP ) )
627 return false; 629 return false;
628 630
629 return true; 631 return true;
630 } 632 }
631 //--------------------------------------------------------------------------------------------------- 633 //---------------------------------------------------------------------------------------------------
632 void hal_set_cwmin( phw_data_t pHwData, u8 cwin_min ) 634 void hal_set_cwmin( phw_data_t pHwData, u8 cwin_min )
633 { 635 {
634 struct wb35_reg *reg = &pHwData->reg; 636 struct wb35_reg *reg = &pHwData->reg;
635 637
636 if( pHwData->SurpriseRemove ) return; 638 if( pHwData->SurpriseRemove ) return;
637 639
638 pHwData->cwmin = cwin_min; 640 pHwData->cwmin = cwin_min;
639 reg->M2C_MacControl &= ~0x7c00; //bit 10 ~ 14 641 reg->M2C_MacControl &= ~0x7c00; //bit 10 ~ 14
640 reg->M2C_MacControl |= (pHwData->cwmin<<10); 642 reg->M2C_MacControl |= (pHwData->cwmin<<10);
641 Wb35Reg_Write( pHwData, 0x082c, reg->M2C_MacControl ); 643 Wb35Reg_Write( pHwData, 0x082c, reg->M2C_MacControl );
642 } 644 }
643 645
644 s32 hal_get_rssi( phw_data_t pHwData, u32 *HalRssiArry, u8 Count ) 646 s32 hal_get_rssi( phw_data_t pHwData, u32 *HalRssiArry, u8 Count )
645 { 647 {
646 struct wb35_reg *reg = &pHwData->reg; 648 struct wb35_reg *reg = &pHwData->reg;
647 R01_DESCRIPTOR r01; 649 R01_DESCRIPTOR r01;
648 s32 ltmp = 0, tmp; 650 s32 ltmp = 0, tmp;
649 u8 i; 651 u8 i;
650 652
651 if( pHwData->SurpriseRemove ) return -200; 653 if( pHwData->SurpriseRemove ) return -200;
652 if( Count > MAX_ACC_RSSI_COUNT ) // Because the TS may use this funtion 654 if( Count > MAX_ACC_RSSI_COUNT ) // Because the TS may use this funtion
653 Count = MAX_ACC_RSSI_COUNT; 655 Count = MAX_ACC_RSSI_COUNT;
654 656
655 // RSSI = C1 + C2 * (agc_state[7:0] + offset_map(lna_state[1:0])) 657 // RSSI = C1 + C2 * (agc_state[7:0] + offset_map(lna_state[1:0]))
656 // C1 = -195, C2 = 0.66 = 85/128 658 // C1 = -195, C2 = 0.66 = 85/128
657 for (i=0; i<Count; i++) 659 for (i=0; i<Count; i++)
658 { 660 {
659 r01.value = HalRssiArry[i]; 661 r01.value = HalRssiArry[i];
660 tmp = ((( r01.R01_AGC_state + reg->LNAValue[r01.R01_LNA_state]) * 85 ) >>7 ) - 195; 662 tmp = ((( r01.R01_AGC_state + reg->LNAValue[r01.R01_LNA_state]) * 85 ) >>7 ) - 195;
661 ltmp += tmp; 663 ltmp += tmp;
662 } 664 }
663 ltmp /= Count; 665 ltmp /= Count;
664 if( pHwData->phy_type == RF_AIROHA_2230 ) ltmp -= 5; // 10; 666 if( pHwData->phy_type == RF_AIROHA_2230 ) ltmp -= 5; // 10;
665 if( pHwData->phy_type == RF_AIROHA_2230S ) ltmp -= 5; // 10; 20060420 Add this 667 if( pHwData->phy_type == RF_AIROHA_2230S ) ltmp -= 5; // 10; 20060420 Add this
666 668
667 //if( ltmp < -200 ) ltmp = -200; 669 //if( ltmp < -200 ) ltmp = -200;
668 if( ltmp < -110 ) ltmp = -110;// 1.0.24.0 For NJRC 670 if( ltmp < -110 ) ltmp = -110;// 1.0.24.0 For NJRC
669 671
670 return ltmp; 672 return ltmp;
671 } 673 }
672 //---------------------------------------------------------------------------------------------------- 674 //----------------------------------------------------------------------------------------------------
673 s32 hal_get_rssi_bss( phw_data_t pHwData, u16 idx, u8 Count ) 675 s32 hal_get_rssi_bss( phw_data_t pHwData, u16 idx, u8 Count )
674 { 676 {
675 struct wb35_reg *reg = &pHwData->reg; 677 struct wb35_reg *reg = &pHwData->reg;
676 R01_DESCRIPTOR r01; 678 R01_DESCRIPTOR r01;
677 s32 ltmp = 0, tmp; 679 s32 ltmp = 0, tmp;
678 u8 i, j; 680 u8 i, j;
679 struct wb35_adapter * adapter = pHwData->adapter; 681 struct wb35_adapter * adapter = pHwData->adapter;
680 // u32 *HalRssiArry = psBSS(idx)->HalRssi; 682 // u32 *HalRssiArry = psBSS(idx)->HalRssi;
681 683
682 if( pHwData->SurpriseRemove ) return -200; 684 if( pHwData->SurpriseRemove ) return -200;
683 if( Count > MAX_ACC_RSSI_COUNT ) // Because the TS may use this funtion 685 if( Count > MAX_ACC_RSSI_COUNT ) // Because the TS may use this funtion
684 Count = MAX_ACC_RSSI_COUNT; 686 Count = MAX_ACC_RSSI_COUNT;
685 687
686 // RSSI = C1 + C2 * (agc_state[7:0] + offset_map(lna_state[1:0])) 688 // RSSI = C1 + C2 * (agc_state[7:0] + offset_map(lna_state[1:0]))
687 // C1 = -195, C2 = 0.66 = 85/128 689 // C1 = -195, C2 = 0.66 = 85/128
688 #if 0 690 #if 0
689 for (i=0; i<Count; i++) 691 for (i=0; i<Count; i++)
690 { 692 {
691 r01.value = HalRssiArry[i]; 693 r01.value = HalRssiArry[i];
692 tmp = ((( r01.R01_AGC_state + reg->LNAValue[r01.R01_LNA_state]) * 85 ) >>7 ) - 195; 694 tmp = ((( r01.R01_AGC_state + reg->LNAValue[r01.R01_LNA_state]) * 85 ) >>7 ) - 195;
693 ltmp += tmp; 695 ltmp += tmp;
694 } 696 }
695 #else 697 #else
696 if (psBSS(idx)->HalRssiIndex == 0) 698 if (psBSS(idx)->HalRssiIndex == 0)
697 psBSS(idx)->HalRssiIndex = MAX_ACC_RSSI_COUNT; 699 psBSS(idx)->HalRssiIndex = MAX_ACC_RSSI_COUNT;
698 j = (u8)psBSS(idx)->HalRssiIndex-1; 700 j = (u8)psBSS(idx)->HalRssiIndex-1;
699 701
700 for (i=0; i<Count; i++) 702 for (i=0; i<Count; i++)
701 { 703 {
702 r01.value = psBSS(idx)->HalRssi[j]; 704 r01.value = psBSS(idx)->HalRssi[j];
703 tmp = ((( r01.R01_AGC_state + reg->LNAValue[r01.R01_LNA_state]) * 85 ) >>7 ) - 195; 705 tmp = ((( r01.R01_AGC_state + reg->LNAValue[r01.R01_LNA_state]) * 85 ) >>7 ) - 195;
704 ltmp += tmp; 706 ltmp += tmp;
705 if (j == 0) 707 if (j == 0)
706 { 708 {
707 j = MAX_ACC_RSSI_COUNT; 709 j = MAX_ACC_RSSI_COUNT;
708 } 710 }
709 j--; 711 j--;
710 } 712 }
711 #endif 713 #endif
712 ltmp /= Count; 714 ltmp /= Count;
713 if( pHwData->phy_type == RF_AIROHA_2230 ) ltmp -= 5; // 10; 715 if( pHwData->phy_type == RF_AIROHA_2230 ) ltmp -= 5; // 10;
714 if( pHwData->phy_type == RF_AIROHA_2230S ) ltmp -= 5; // 10; 20060420 Add this 716 if( pHwData->phy_type == RF_AIROHA_2230S ) ltmp -= 5; // 10; 20060420 Add this
715 717
716 //if( ltmp < -200 ) ltmp = -200; 718 //if( ltmp < -200 ) ltmp = -200;
717 if( ltmp < -110 ) ltmp = -110;// 1.0.24.0 For NJRC 719 if( ltmp < -110 ) ltmp = -110;// 1.0.24.0 For NJRC
718 720
719 return ltmp; 721 return ltmp;
720 } 722 }
721 723
722 //--------------------------------------------------------------------------- 724 //---------------------------------------------------------------------------
723 725
724 void hal_set_phy_type( phw_data_t pHwData, u8 PhyType ) 726 void hal_set_phy_type( phw_data_t pHwData, u8 PhyType )
725 { 727 {
726 pHwData->phy_type = PhyType; 728 pHwData->phy_type = PhyType;
727 } 729 }
728 730
729 void hal_get_phy_type( phw_data_t pHwData, u8 *PhyType ) 731 void hal_get_phy_type( phw_data_t pHwData, u8 *PhyType )
730 { 732 {
731 *PhyType = pHwData->phy_type; 733 *PhyType = pHwData->phy_type;
732 } 734 }
733 735
734 void hal_reset_counter( phw_data_t pHwData ) 736 void hal_reset_counter( phw_data_t pHwData )
735 { 737 {
736 pHwData->dto_tx_retry_count = 0; 738 pHwData->dto_tx_retry_count = 0;
737 pHwData->dto_tx_frag_count = 0; 739 pHwData->dto_tx_frag_count = 0;
738 memset( pHwData->tx_retry_count, 0, 8); 740 memset( pHwData->tx_retry_count, 0, 8);
739 } 741 }
740 742
741 void hal_set_radio_mode( phw_data_t pHwData, unsigned char radio_off) 743 void hal_set_radio_mode( phw_data_t pHwData, unsigned char radio_off)
742 { 744 {
743 struct wb35_reg *reg = &pHwData->reg; 745 struct wb35_reg *reg = &pHwData->reg;
744 746
745 if( pHwData->SurpriseRemove ) return; 747 if( pHwData->SurpriseRemove ) return;
746 748
747 if (radio_off) //disable Baseband receive off 749 if (radio_off) //disable Baseband receive off
748 { 750 {
749 pHwData->CurrentRadioSw = 1; // off 751 pHwData->CurrentRadioSw = 1; // off
750 reg->M24_MacControl &= 0xffffffbf; 752 reg->M24_MacControl &= 0xffffffbf;
751 } 753 }
752 else 754 else
753 { 755 {
754 pHwData->CurrentRadioSw = 0; // on 756 pHwData->CurrentRadioSw = 0; // on
755 reg->M24_MacControl |= 0x00000040; 757 reg->M24_MacControl |= 0x00000040;
756 } 758 }
757 Wb35Reg_Write( pHwData, 0x0824, reg->M24_MacControl ); 759 Wb35Reg_Write( pHwData, 0x0824, reg->M24_MacControl );
758 } 760 }
759 761
760 u8 hal_get_antenna_number( phw_data_t pHwData ) 762 u8 hal_get_antenna_number( phw_data_t pHwData )
761 { 763 {
762 struct wb35_reg *reg = &pHwData->reg; 764 struct wb35_reg *reg = &pHwData->reg;
763 765
764 if ((reg->BB2C & BIT(11)) == 0) 766 if ((reg->BB2C & BIT(11)) == 0)
765 return 0; 767 return 0;
766 else 768 else
767 return 1; 769 return 1;
768 } 770 }
769 771
770 void hal_set_antenna_number( phw_data_t pHwData, u8 number ) 772 void hal_set_antenna_number( phw_data_t pHwData, u8 number )
771 { 773 {
772 774
773 struct wb35_reg *reg = &pHwData->reg; 775 struct wb35_reg *reg = &pHwData->reg;
774 776
775 if (number == 1) { 777 if (number == 1) {
776 reg->BB2C |= BIT(11); 778 reg->BB2C |= BIT(11);
777 } else { 779 } else {
778 reg->BB2C &= ~BIT(11); 780 reg->BB2C &= ~BIT(11);
779 } 781 }
780 Wb35Reg_Write( pHwData, 0x102c, reg->BB2C ); 782 Wb35Reg_Write( pHwData, 0x102c, reg->BB2C );
781 #ifdef _PE_STATE_DUMP_ 783 #ifdef _PE_STATE_DUMP_
782 WBDEBUG(("Current antenna number : %d\n", number)); 784 WBDEBUG(("Current antenna number : %d\n", number));
783 #endif 785 #endif
784 } 786 }
785 787
786 //---------------------------------------------------------------------------------------------------- 788 //----------------------------------------------------------------------------------------------------
787 //0 : radio on; 1: radio off 789 //0 : radio on; 1: radio off
788 u8 hal_get_hw_radio_off( phw_data_t pHwData ) 790 u8 hal_get_hw_radio_off( phw_data_t pHwData )
789 { 791 {
790 struct wb35_reg *reg = &pHwData->reg; 792 struct wb35_reg *reg = &pHwData->reg;
791 793
792 if( pHwData->SurpriseRemove ) return 1; 794 if( pHwData->SurpriseRemove ) return 1;
793 795
794 //read the bit16 of register U1B0 796 //read the bit16 of register U1B0
795 Wb35Reg_Read( pHwData, 0x3b0, &reg->U1B0 ); 797 Wb35Reg_Read( pHwData, 0x3b0, &reg->U1B0 );
796 if ((reg->U1B0 & 0x00010000)) { 798 if ((reg->U1B0 & 0x00010000)) {
797 pHwData->CurrentRadioHw = 1; 799 pHwData->CurrentRadioHw = 1;
798 return 1; 800 return 1;
799 } else { 801 } else {
800 pHwData->CurrentRadioHw = 0; 802 pHwData->CurrentRadioHw = 0;
801 return 0; 803 return 0;
802 } 804 }
803 } 805 }
804 806
805 unsigned char hal_get_dxx_reg( phw_data_t pHwData, u16 number, u32 * pValue ) 807 unsigned char hal_get_dxx_reg( phw_data_t pHwData, u16 number, u32 * pValue )
806 { 808 {
807 if( number < 0x1000 ) 809 if( number < 0x1000 )
808 number += 0x1000; 810 number += 0x1000;
809 return Wb35Reg_ReadSync( pHwData, number, pValue ); 811 return Wb35Reg_ReadSync( pHwData, number, pValue );
810 } 812 }
811 813
812 unsigned char hal_set_dxx_reg( phw_data_t pHwData, u16 number, u32 value ) 814 unsigned char hal_set_dxx_reg( phw_data_t pHwData, u16 number, u32 value )
813 { 815 {
814 unsigned char ret; 816 unsigned char ret;
815 817
816 if( number < 0x1000 ) 818 if( number < 0x1000 )
817 number += 0x1000; 819 number += 0x1000;
818 ret = Wb35Reg_WriteSync( pHwData, number, value ); 820 ret = Wb35Reg_WriteSync( pHwData, number, value );
819 return ret; 821 return ret;
820 } 822 }
821 823
822 void hal_scan_status_indicate(phw_data_t pHwData, unsigned char IsOnProgress) 824 void hal_scan_status_indicate(phw_data_t pHwData, unsigned char IsOnProgress)
823 { 825 {
824 if( pHwData->SurpriseRemove ) return; 826 if( pHwData->SurpriseRemove ) return;
825 pHwData->LED_Scanning = IsOnProgress ? 1 : 0; 827 pHwData->LED_Scanning = IsOnProgress ? 1 : 0;
826 } 828 }
827 829
828 void hal_system_power_change(phw_data_t pHwData, u32 PowerState) 830 void hal_system_power_change(phw_data_t pHwData, u32 PowerState)
829 { 831 {
830 if( PowerState != 0 ) 832 if( PowerState != 0 )
831 { 833 {
832 pHwData->SurpriseRemove = 1; 834 pHwData->SurpriseRemove = 1;
833 if( pHwData->WbUsb.IsUsb20 ) 835 if( pHwData->WbUsb.IsUsb20 )
834 hal_stop( pHwData ); 836 hal_stop( pHwData );
835 } 837 }
836 else 838 else
837 { 839 {
838 if( !pHwData->WbUsb.IsUsb20 ) 840 if( !pHwData->WbUsb.IsUsb20 )
839 hal_stop( pHwData ); 841 hal_stop( pHwData );
840 } 842 }
841 } 843 }
842 844
843 void hal_surprise_remove( phw_data_t pHwData ) 845 void hal_surprise_remove( phw_data_t pHwData )
844 { 846 {
845 struct wb35_adapter * adapter = pHwData->adapter; 847 struct wb35_adapter * adapter = pHwData->adapter;
846 if (atomic_inc_return( &pHwData->SurpriseRemoveCount ) == 1) { 848 if (atomic_inc_return( &pHwData->SurpriseRemoveCount ) == 1) {
847 #ifdef _PE_STATE_DUMP_ 849 #ifdef _PE_STATE_DUMP_
848 WBDEBUG(("Calling hal_surprise_remove\n")); 850 WBDEBUG(("Calling hal_surprise_remove\n"));
849 #endif 851 #endif
850 OS_STOP( adapter ); 852 OS_STOP( adapter );
851 } 853 }
852 } 854 }
853 855
854 void hal_rate_change( phw_data_t pHwData ) // Notify the HAL rate is changing 20060613.1 856 void hal_rate_change( phw_data_t pHwData ) // Notify the HAL rate is changing 20060613.1
855 { 857 {
856 struct wb35_adapter * adapter = pHwData->adapter; 858 struct wb35_adapter * adapter = pHwData->adapter;
857 u8 rate = CURRENT_TX_RATE; 859 u8 rate = CURRENT_TX_RATE;
858 860
859 BBProcessor_RateChanging( pHwData, rate ); 861 BBProcessor_RateChanging( pHwData, rate );
860 } 862 }
861 863
862 void hal_set_rf_power(phw_data_t pHwData, u8 PowerIndex) 864 void hal_set_rf_power(phw_data_t pHwData, u8 PowerIndex)
863 { 865 {
864 RFSynthesizer_SetPowerIndex( pHwData, PowerIndex ); 866 RFSynthesizer_SetPowerIndex( pHwData, PowerIndex );
865 } 867 }
866 868
867 unsigned char hal_set_LED(phw_data_t pHwData, u32 Mode) // 20061108 for WPS led control 869 unsigned char hal_set_LED(phw_data_t pHwData, u32 Mode) // 20061108 for WPS led control
868 { 870 {
869 pHwData->LED_Blinking = 0; 871 pHwData->LED_Blinking = 0;
870 pHwData->LED_control = Mode; 872 pHwData->LED_control = Mode;
871 pHwData->LEDTimer.expires = jiffies + msecs_to_jiffies(10); 873 pHwData->LEDTimer.expires = jiffies + msecs_to_jiffies(10);
872 add_timer(&pHwData->LEDTimer); 874 add_timer(&pHwData->LEDTimer);
873 return true; 875 return true;
874 } 876 }
875 877
876 878
drivers/staging/winbond/wbhal_f.h
Diff comments   View file @ 80aba53
1 //===================================================================== 1 //=====================================================================
2 // Device related include 2 // Device related include
3 //===================================================================== 3 //=====================================================================
4 #ifdef WB_LINUX 4 #include "linux/wb35reg_f.h"
5 #include "linux/wb35reg_f.h" 5 #include "linux/wb35tx_f.h"
6 #include "linux/wb35tx_f.h" 6 #include "linux/wb35rx_f.h"
7 #include "linux/wb35rx_f.h" 7
8 #else 8 #include "adapter.h"
9 #include "wb35reg_f.h"
10 #include "wb35tx_f.h"
11 #include "wb35rx_f.h"
12 #endif
13 9
14 //==================================================================================== 10 //====================================================================================
15 // Function declaration 11 // Function declaration
16 //==================================================================================== 12 //====================================================================================
17 void hal_remove_mapping_key( phw_data_t pHwData, u8 *pmac_addr ); 13 void hal_remove_mapping_key( phw_data_t pHwData, u8 *pmac_addr );
18 void hal_remove_default_key( phw_data_t pHwData, u32 index ); 14 void hal_remove_default_key( phw_data_t pHwData, u32 index );
19 unsigned char hal_set_mapping_key( phw_data_t adapter, u8 *pmac_addr, u8 null_key, u8 wep_on, u8 *ptx_tsc, u8 *prx_tsc, u8 key_type, u8 key_len, u8 *pkey_data ); 15 unsigned char hal_set_mapping_key( phw_data_t adapter, u8 *pmac_addr, u8 null_key, u8 wep_on, u8 *ptx_tsc, u8 *prx_tsc, u8 key_type, u8 key_len, u8 *pkey_data );
20 unsigned char hal_set_default_key( phw_data_t adapter, u8 index, u8 null_key, u8 wep_on, u8 *ptx_tsc, u8 *prx_tsc, u8 key_type, u8 key_len, u8 *pkey_data ); 16 unsigned char hal_set_default_key( phw_data_t adapter, u8 index, u8 null_key, u8 wep_on, u8 *ptx_tsc, u8 *prx_tsc, u8 key_type, u8 key_len, u8 *pkey_data );
21 void hal_clear_all_default_key( phw_data_t pHwData ); 17 void hal_clear_all_default_key( phw_data_t pHwData );
22 void hal_clear_all_group_key( phw_data_t pHwData ); 18 void hal_clear_all_group_key( phw_data_t pHwData );
23 void hal_clear_all_mapping_key( phw_data_t pHwData ); 19 void hal_clear_all_mapping_key( phw_data_t pHwData );
24 void hal_clear_all_key( phw_data_t pHwData ); 20 void hal_clear_all_key( phw_data_t pHwData );
25 void hal_get_ethernet_address( phw_data_t pHwData, u8 *current_address ); 21 void hal_get_ethernet_address( phw_data_t pHwData, u8 *current_address );
26 void hal_set_ethernet_address( phw_data_t pHwData, u8 *current_address ); 22 void hal_set_ethernet_address( phw_data_t pHwData, u8 *current_address );
27 void hal_get_permanent_address( phw_data_t pHwData, u8 *pethernet_address ); 23 void hal_get_permanent_address( phw_data_t pHwData, u8 *pethernet_address );
28 unsigned char hal_init_hardware( phw_data_t pHwData, struct wb35_adapter * adapter ); 24 unsigned char hal_init_hardware( phw_data_t pHwData, struct wb35_adapter * adapter );
29 void hal_set_power_save_mode( phw_data_t pHwData, unsigned char power_save, unsigned char wakeup, unsigned char dtim ); 25 void hal_set_power_save_mode( phw_data_t pHwData, unsigned char power_save, unsigned char wakeup, unsigned char dtim );
30 void hal_get_power_save_mode( phw_data_t pHwData, u8 *pin_pwr_save ); 26 void hal_get_power_save_mode( phw_data_t pHwData, u8 *pin_pwr_save );
31 void hal_set_slot_time( phw_data_t pHwData, u8 type ); 27 void hal_set_slot_time( phw_data_t pHwData, u8 type );
32 #define hal_set_atim_window( _A, _ATM ) 28 #define hal_set_atim_window( _A, _ATM )
33 void hal_set_rates( phw_data_t pHwData, u8 *pbss_rates, u8 length, unsigned char basic_rate_set ); 29 void hal_set_rates( phw_data_t pHwData, u8 *pbss_rates, u8 length, unsigned char basic_rate_set );
34 #define hal_set_basic_rates( _A, _R, _L ) hal_set_rates( _A, _R, _L, TRUE ) 30 #define hal_set_basic_rates( _A, _R, _L ) hal_set_rates( _A, _R, _L, TRUE )
35 #define hal_set_op_rates( _A, _R, _L ) hal_set_rates( _A, _R, _L, FALSE ) 31 #define hal_set_op_rates( _A, _R, _L ) hal_set_rates( _A, _R, _L, FALSE )
36 void hal_start_bss( phw_data_t pHwData, u8 mac_op_mode ); 32 void hal_start_bss( phw_data_t pHwData, u8 mac_op_mode );
37 void hal_join_request( phw_data_t pHwData, u8 bss_type ); // 0:BSS STA 1:IBSS STA// 33 void hal_join_request( phw_data_t pHwData, u8 bss_type ); // 0:BSS STA 1:IBSS STA//
38 void hal_stop_sync_bss( phw_data_t pHwData ); 34 void hal_stop_sync_bss( phw_data_t pHwData );
39 void hal_resume_sync_bss( phw_data_t pHwData); 35 void hal_resume_sync_bss( phw_data_t pHwData);
40 void hal_set_aid( phw_data_t pHwData, u16 aid ); 36 void hal_set_aid( phw_data_t pHwData, u16 aid );
41 void hal_set_bssid( phw_data_t pHwData, u8 *pbssid ); 37 void hal_set_bssid( phw_data_t pHwData, u8 *pbssid );
42 void hal_get_bssid( phw_data_t pHwData, u8 *pbssid ); 38 void hal_get_bssid( phw_data_t pHwData, u8 *pbssid );
43 void hal_set_beacon_period( phw_data_t pHwData, u16 beacon_period ); 39 void hal_set_beacon_period( phw_data_t pHwData, u16 beacon_period );
44 void hal_set_listen_interval( phw_data_t pHwData, u16 listen_interval ); 40 void hal_set_listen_interval( phw_data_t pHwData, u16 listen_interval );
45 void hal_set_cap_info( phw_data_t pHwData, u16 capability_info ); 41 void hal_set_cap_info( phw_data_t pHwData, u16 capability_info );
46 void hal_set_ssid( phw_data_t pHwData, u8 *pssid, u8 ssid_len ); 42 void hal_set_ssid( phw_data_t pHwData, u8 *pssid, u8 ssid_len );
47 void hal_set_current_channel( phw_data_t pHwData, ChanInfo channel ); 43 void hal_set_current_channel( phw_data_t pHwData, ChanInfo channel );
48 void hal_set_current_channel_ex( phw_data_t pHwData, ChanInfo channel ); 44 void hal_set_current_channel_ex( phw_data_t pHwData, ChanInfo channel );
49 void hal_get_current_channel( phw_data_t pHwData, ChanInfo *channel ); 45 void hal_get_current_channel( phw_data_t pHwData, ChanInfo *channel );
50 void hal_set_accept_broadcast( phw_data_t pHwData, u8 enable ); 46 void hal_set_accept_broadcast( phw_data_t pHwData, u8 enable );
51 void hal_set_accept_multicast( phw_data_t pHwData, u8 enable ); 47 void hal_set_accept_multicast( phw_data_t pHwData, u8 enable );
52 void hal_set_accept_beacon( phw_data_t pHwData, u8 enable ); 48 void hal_set_accept_beacon( phw_data_t pHwData, u8 enable );
53 void hal_set_multicast_address( phw_data_t pHwData, u8 *address, u8 number ); 49 void hal_set_multicast_address( phw_data_t pHwData, u8 *address, u8 number );
54 u8 hal_get_accept_beacon( phw_data_t pHwData ); 50 u8 hal_get_accept_beacon( phw_data_t pHwData );
55 void hal_stop( phw_data_t pHwData ); 51 void hal_stop( phw_data_t pHwData );
56 void hal_halt( phw_data_t pHwData, void *ppa_data ); 52 void hal_halt( phw_data_t pHwData, void *ppa_data );
57 void hal_start_tx0( phw_data_t pHwData ); 53 void hal_start_tx0( phw_data_t pHwData );
58 void hal_set_phy_type( phw_data_t pHwData, u8 PhyType ); 54 void hal_set_phy_type( phw_data_t pHwData, u8 PhyType );
59 void hal_get_phy_type( phw_data_t pHwData, u8 *PhyType ); 55 void hal_get_phy_type( phw_data_t pHwData, u8 *PhyType );
60 unsigned char hal_reset_hardware( phw_data_t pHwData, void* ppa ); 56 unsigned char hal_reset_hardware( phw_data_t pHwData, void* ppa );
61 void hal_set_cwmin( phw_data_t pHwData, u8 cwin_min ); 57 void hal_set_cwmin( phw_data_t pHwData, u8 cwin_min );
62 #define hal_get_cwmin( _A ) ( (_A)->cwmin ) 58 #define hal_get_cwmin( _A ) ( (_A)->cwmin )
63 void hal_set_cwmax( phw_data_t pHwData, u16 cwin_max ); 59 void hal_set_cwmax( phw_data_t pHwData, u16 cwin_max );
64 #define hal_get_cwmax( _A ) ( (_A)->cwmax ) 60 #define hal_get_cwmax( _A ) ( (_A)->cwmax )
65 void hal_set_rsn_wpa( phw_data_t pHwData, u32 * RSN_IE_Bitmap , u32 * RSN_OUI_type , unsigned char bDesiredAuthMode); 61 void hal_set_rsn_wpa( phw_data_t pHwData, u32 * RSN_IE_Bitmap , u32 * RSN_OUI_type , unsigned char bDesiredAuthMode);
66 //s32 hal_get_rssi( phw_data_t pHwData, u32 HalRssi ); 62 //s32 hal_get_rssi( phw_data_t pHwData, u32 HalRssi );
67 s32 hal_get_rssi( phw_data_t pHwData, u32 *HalRssiArry, u8 Count ); 63 s32 hal_get_rssi( phw_data_t pHwData, u32 *HalRssiArry, u8 Count );
68 s32 hal_get_rssi_bss( phw_data_t pHwData, u16 idx, u8 Count ); 64 s32 hal_get_rssi_bss( phw_data_t pHwData, u16 idx, u8 Count );
69 void hal_set_connect_info( phw_data_t pHwData, unsigned char boConnect ); 65 void hal_set_connect_info( phw_data_t pHwData, unsigned char boConnect );
70 u8 hal_get_est_sq3( phw_data_t pHwData, u8 Count ); 66 u8 hal_get_est_sq3( phw_data_t pHwData, u8 Count );
71 void hal_set_rf_power( phw_data_t pHwData, u8 PowerIndex ); // 20060621 Modify 67 void hal_set_rf_power( phw_data_t pHwData, u8 PowerIndex ); // 20060621 Modify
72 void hal_reset_counter( phw_data_t pHwData ); 68 void hal_reset_counter( phw_data_t pHwData );
73 void hal_set_radio_mode( phw_data_t pHwData, unsigned char boValue); 69 void hal_set_radio_mode( phw_data_t pHwData, unsigned char boValue);
74 void hal_descriptor_indicate( phw_data_t pHwData, PDESCRIPTOR pDes ); 70 void hal_descriptor_indicate( phw_data_t pHwData, PDESCRIPTOR pDes );
75 u8 hal_get_antenna_number( phw_data_t pHwData ); 71 u8 hal_get_antenna_number( phw_data_t pHwData );
76 void hal_set_antenna_number( phw_data_t pHwData, u8 number ); 72 void hal_set_antenna_number( phw_data_t pHwData, u8 number );
77 u32 hal_get_bss_pk_cnt( phw_data_t pHwData ); 73 u32 hal_get_bss_pk_cnt( phw_data_t pHwData );
78 #define hal_get_region_from_EEPROM( _A ) ( (_A)->reg.EEPROMRegion ) 74 #define hal_get_region_from_EEPROM( _A ) ( (_A)->reg.EEPROMRegion )
79 void hal_set_accept_promiscuous ( phw_data_t pHwData, u8 enable); 75 void hal_set_accept_promiscuous ( phw_data_t pHwData, u8 enable);
80 #define hal_get_tx_buffer( _A, _B ) Wb35Tx_get_tx_buffer( _A, _B ) 76 #define hal_get_tx_buffer( _A, _B ) Wb35Tx_get_tx_buffer( _A, _B )
81 u8 hal_get_hw_radio_off ( phw_data_t pHwData ); 77 u8 hal_get_hw_radio_off ( phw_data_t pHwData );
82 #define hal_software_set( _A ) (_A->SoftwareSet) 78 #define hal_software_set( _A ) (_A->SoftwareSet)
83 #define hal_driver_init_OK( _A ) (_A->IsInitOK) 79 #define hal_driver_init_OK( _A ) (_A->IsInitOK)
84 #define hal_rssi_boundary_high( _A ) (_A->RSSI_high) 80 #define hal_rssi_boundary_high( _A ) (_A->RSSI_high)
85 #define hal_rssi_boundary_low( _A ) (_A->RSSI_low) 81 #define hal_rssi_boundary_low( _A ) (_A->RSSI_low)
86 #define hal_scan_interval( _A ) (_A->Scan_Interval) 82 #define hal_scan_interval( _A ) (_A->Scan_Interval)
87 void hal_scan_status_indicate( phw_data_t pHwData, u8 status); // 0: complete, 1: in progress 83 void hal_scan_status_indicate( phw_data_t pHwData, u8 status); // 0: complete, 1: in progress
88 void hal_system_power_change( phw_data_t pHwData, u32 PowerState ); // 20051230 -=D0 1=D1 .. 84 void hal_system_power_change( phw_data_t pHwData, u32 PowerState ); // 20051230 -=D0 1=D1 ..
89 void hal_surprise_remove( phw_data_t pHwData ); 85 void hal_surprise_remove( phw_data_t pHwData );
90 86
91 #define PHY_DEBUG( msg, args... ) 87 #define PHY_DEBUG( msg, args... )
92 88
93 89
94 90
95 void hal_rate_change( phw_data_t pHwData ); // Notify the HAL rate is changing 20060613.1 91 void hal_rate_change( phw_data_t pHwData ); // Notify the HAL rate is changing 20060613.1
96 unsigned char hal_get_dxx_reg( phw_data_t pHwData, u16 number, u32 * pValue ); 92 unsigned char hal_get_dxx_reg( phw_data_t pHwData, u16 number, u32 * pValue );
97 unsigned char hal_set_dxx_reg( phw_data_t pHwData, u16 number, u32 value ); 93 unsigned char hal_set_dxx_reg( phw_data_t pHwData, u16 number, u32 value );
98 #define hal_get_time_count( _P ) (_P->time_count/10) // return 100ms count 94 #define hal_get_time_count( _P ) (_P->time_count/10) // return 100ms count
99 #define hal_detect_error( _P ) (_P->WbUsb.DetectCount) 95 #define hal_detect_error( _P ) (_P->WbUsb.DetectCount)
100 unsigned char hal_set_LED( phw_data_t pHwData, u32 Mode ); // 20061108 for WPS led control 96 unsigned char hal_set_LED( phw_data_t pHwData, u32 Mode ); // 20061108 for WPS led control
101 97
102 //------------------------------------------------------------------------- 98 //-------------------------------------------------------------------------
103 // The follow function is unused for IS89C35 99 // The follow function is unused for IS89C35
104 //------------------------------------------------------------------------- 100 //-------------------------------------------------------------------------
105 #define hal_disable_interrupt(_A) 101 #define hal_disable_interrupt(_A)
106 #define hal_enable_interrupt(_A) 102 #define hal_enable_interrupt(_A)
107 #define hal_get_interrupt_type( _A) 103 #define hal_get_interrupt_type( _A)
108 #define hal_get_clear_interrupt(_A) 104 #define hal_get_clear_interrupt(_A)
109 #define hal_ibss_disconnect(_A) hal_stop_sync_bss(_A) 105 #define hal_ibss_disconnect(_A) hal_stop_sync_bss(_A)
110 #define hal_join_request_stop(_A) 106 #define hal_join_request_stop(_A)
111 unsigned char hal_idle( phw_data_t pHwData ); 107 unsigned char hal_idle( phw_data_t pHwData );
112 #define hw_get_cxx_reg( _A, _B, _C ) 108 #define hw_get_cxx_reg( _A, _B, _C )
113 #define hw_set_cxx_reg( _A, _B, _C ) 109 #define hw_set_cxx_reg( _A, _B, _C )
114 #define hw_get_dxx_reg( _A, _B, _C ) hal_get_dxx_reg( _A, _B, (u32 *)_C ) 110 #define hw_get_dxx_reg( _A, _B, _C ) hal_get_dxx_reg( _A, _B, (u32 *)_C )
115 #define hw_set_dxx_reg( _A, _B, _C ) hal_set_dxx_reg( _A, _B, (u32)_C ) 111 #define hw_set_dxx_reg( _A, _B, _C ) hal_set_dxx_reg( _A, _B, (u32)_C )
116 112
117 113
118 114
drivers/staging/winbond/wbhal_s.h
Diff comments   View file @ 80aba53
1 #ifndef __WINBOND_WBHAL_S_H
2 #define __WINBOND_WBHAL_S_H
3
4 #include <linux/types.h>
5
6 #include "linux/common.h"
7
1 //[20040722 WK] 8 //[20040722 WK]
2 #define HAL_LED_SET_MASK 0x001c //20060901 Extend 9 #define HAL_LED_SET_MASK 0x001c //20060901 Extend
3 #define HAL_LED_SET_SHIFT 2 10 #define HAL_LED_SET_SHIFT 2
4 11
5 //supported RF type 12 //supported RF type
6 #define RF_MAXIM_2825 0 13 #define RF_MAXIM_2825 0
7 #define RF_MAXIM_2827 1 14 #define RF_MAXIM_2827 1
8 #define RF_MAXIM_2828 2 15 #define RF_MAXIM_2828 2
9 #define RF_MAXIM_2829 3 16 #define RF_MAXIM_2829 3
10 #define RF_MAXIM_V1 15 17 #define RF_MAXIM_V1 15
11 #define RF_AIROHA_2230 16 18 #define RF_AIROHA_2230 16
12 #define RF_AIROHA_7230 17 19 #define RF_AIROHA_7230 17
13 #define RF_AIROHA_2230S 18 // 20060420 Add this 20 #define RF_AIROHA_2230S 18 // 20060420 Add this
14 // #define RF_RFMD_2959 32 // 20060626 Remove all about RFMD 21 // #define RF_RFMD_2959 32 // 20060626 Remove all about RFMD
15 #define RF_WB_242 33 22 #define RF_WB_242 33
16 #define RF_WB_242_1 34 // 20060619.5 Add 23 #define RF_WB_242_1 34 // 20060619.5 Add
17 #define RF_DECIDE_BY_INF 255 24 #define RF_DECIDE_BY_INF 255
18 25
19 //---------------------------------------------------------------- 26 //----------------------------------------------------------------
20 // The follow define connect to upper layer 27 // The follow define connect to upper layer
21 // User must modify for connection between HAL and upper layer 28 // User must modify for connection between HAL and upper layer
22 //---------------------------------------------------------------- 29 //----------------------------------------------------------------
23 30
24 31
25 32
26 33
27 ///////////////////////////////////////////////////////////////////////////////////////////////////// 34 /////////////////////////////////////////////////////////////////////////////////////////////////////
28 //================================================================================================ 35 //================================================================================================
29 // Common define 36 // Common define
30 //================================================================================================ 37 //================================================================================================
31 #define HAL_USB_MODE_BURST( _H ) (_H->SoftwareSet & 0x20 ) // Bit 5 20060901 Modify 38 #define HAL_USB_MODE_BURST( _H ) (_H->SoftwareSet & 0x20 ) // Bit 5 20060901 Modify
32 39
33 // Scan interval 40 // Scan interval
34 #define SCAN_MAX_CHNL_TIME (50) 41 #define SCAN_MAX_CHNL_TIME (50)
35 42
36 // For TxL2 Frame typr recognise 43 // For TxL2 Frame typr recognise
37 #define FRAME_TYPE_802_3_DATA 0 44 #define FRAME_TYPE_802_3_DATA 0
38 #define FRAME_TYPE_802_11_MANAGEMENT 1 45 #define FRAME_TYPE_802_11_MANAGEMENT 1
39 #define FRAME_TYPE_802_11_MANAGEMENT_CHALLENGE 2 46 #define FRAME_TYPE_802_11_MANAGEMENT_CHALLENGE 2
40 #define FRAME_TYPE_802_11_CONTROL 3 47 #define FRAME_TYPE_802_11_CONTROL 3
41 #define FRAME_TYPE_802_11_DATA 4 48 #define FRAME_TYPE_802_11_DATA 4
42 #define FRAME_TYPE_PROMISCUOUS 5 49 #define FRAME_TYPE_PROMISCUOUS 5
43 50
44 // The follow definition is used for convert the frame-------------------- 51 // The follow definition is used for convert the frame--------------------
45 #define DOT_11_SEQUENCE_OFFSET 22 //Sequence control offset 52 #define DOT_11_SEQUENCE_OFFSET 22 //Sequence control offset
46 #define DOT_3_TYPE_OFFSET 12 53 #define DOT_3_TYPE_OFFSET 12
47 #define DOT_11_MAC_HEADER_SIZE 24 54 #define DOT_11_MAC_HEADER_SIZE 24
48 #define DOT_11_SNAP_SIZE 6 55 #define DOT_11_SNAP_SIZE 6
49 #define DOT_11_TYPE_OFFSET 30 //The start offset of 802.11 Frame. Type encapsulatuin. 56 #define DOT_11_TYPE_OFFSET 30 //The start offset of 802.11 Frame. Type encapsulatuin.
50 #define DEFAULT_SIFSTIME 10 57 #define DEFAULT_SIFSTIME 10
51 #define DEFAULT_FRAGMENT_THRESHOLD 2346 // No fragment 58 #define DEFAULT_FRAGMENT_THRESHOLD 2346 // No fragment
52 #define DEFAULT_MSDU_LIFE_TIME 0xffff 59 #define DEFAULT_MSDU_LIFE_TIME 0xffff
53 60
54 #define LONG_PREAMBLE_PLUS_PLCPHEADER_TIME (144+48) 61 #define LONG_PREAMBLE_PLUS_PLCPHEADER_TIME (144+48)
55 #define SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME (72+24) 62 #define SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME (72+24)
56 #define PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION (16+4+6) 63 #define PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION (16+4+6)
57 #define Tsym 4 64 #define Tsym 4
58 65
59 // Frame Type of Bits (2, 3)--------------------------------------------- 66 // Frame Type of Bits (2, 3)---------------------------------------------
60 #define MAC_TYPE_MANAGEMENT 0x00 67 #define MAC_TYPE_MANAGEMENT 0x00
61 #define MAC_TYPE_CONTROL 0x04 68 #define MAC_TYPE_CONTROL 0x04
62 #define MAC_TYPE_DATA 0x08 69 #define MAC_TYPE_DATA 0x08
63 #define MASK_FRAGMENT_NUMBER 0x000F 70 #define MASK_FRAGMENT_NUMBER 0x000F
64 #define SEQUENCE_NUMBER_SHIFT 4 71 #define SEQUENCE_NUMBER_SHIFT 4
65 72
66 #define HAL_WOL_TYPE_WAKEUP_FRAME 0x01 73 #define HAL_WOL_TYPE_WAKEUP_FRAME 0x01
67 #define HAL_WOL_TYPE_MAGIC_PACKET 0x02 74 #define HAL_WOL_TYPE_MAGIC_PACKET 0x02
68 75
69 // 20040106 ADDED 76 // 20040106 ADDED
70 #define HAL_KEYTYPE_WEP40 0 77 #define HAL_KEYTYPE_WEP40 0
71 #define HAL_KEYTYPE_WEP104 1 78 #define HAL_KEYTYPE_WEP104 1
72 #define HAL_KEYTYPE_TKIP 2 // 128 bit key 79 #define HAL_KEYTYPE_TKIP 2 // 128 bit key
73 #define HAL_KEYTYPE_AES_CCMP 3 // 128 bit key 80 #define HAL_KEYTYPE_AES_CCMP 3 // 128 bit key
74 81
75 // For VM state 82 // For VM state
76 enum { 83 enum {
77 VM_STOP = 0, 84 VM_STOP = 0,
78 VM_RUNNING, 85 VM_RUNNING,
79 VM_COMPLETED 86 VM_COMPLETED
80 }; 87 };
81 88
82 // Be used for 802.11 mac header 89 // Be used for 802.11 mac header
83 typedef struct _MAC_FRAME_CONTROL { 90 typedef struct _MAC_FRAME_CONTROL {
84 u8 mac_frame_info; // this is a combination of the protovl version, type and subtype 91 u8 mac_frame_info; // this is a combination of the protovl version, type and subtype
85 u8 to_ds:1; 92 u8 to_ds:1;
86 u8 from_ds:1; 93 u8 from_ds:1;
87 u8 more_frag:1; 94 u8 more_frag:1;
88 u8 retry:1; 95 u8 retry:1;
89 u8 pwr_mgt:1; 96 u8 pwr_mgt:1;
90 u8 more_data:1; 97 u8 more_data:1;
91 u8 WEP:1; 98 u8 WEP:1;
92 u8 order:1; 99 u8 order:1;
93 } MAC_FRAME_CONTROL, *PMAC_FRAME_CONTROL; 100 } MAC_FRAME_CONTROL, *PMAC_FRAME_CONTROL;
94 101
95 //----------------------------------------------------- 102 //-----------------------------------------------------
96 // Normal Key table format 103 // Normal Key table format
97 //----------------------------------------------------- 104 //-----------------------------------------------------
98 // The order of KEY index is MAPPING_KEY_START_INDEX > GROUP_KEY_START_INDEX 105 // The order of KEY index is MAPPING_KEY_START_INDEX > GROUP_KEY_START_INDEX
99 #define MAX_KEY_TABLE 24 // 24 entry for storing key data 106 #define MAX_KEY_TABLE 24 // 24 entry for storing key data
100 #define GROUP_KEY_START_INDEX 4 107 #define GROUP_KEY_START_INDEX 4
101 #define MAPPING_KEY_START_INDEX 8 108 #define MAPPING_KEY_START_INDEX 8
102 typedef struct _KEY_TABLE 109 typedef struct _KEY_TABLE
103 { 110 {
104 u32 DW0_Valid:1; 111 u32 DW0_Valid:1;
105 u32 DW0_NullKey:1; 112 u32 DW0_NullKey:1;
106 u32 DW0_Security_Mode:2;//0:WEP 40 bit 1:WEP 104 bit 2:TKIP 128 bit 3:CCMP 128 bit 113 u32 DW0_Security_Mode:2;//0:WEP 40 bit 1:WEP 104 bit 2:TKIP 128 bit 3:CCMP 128 bit
107 u32 DW0_WEPON:1; 114 u32 DW0_WEPON:1;
108 u32 DW0_RESERVED:11; 115 u32 DW0_RESERVED:11;
109 u32 DW0_Address1:16; 116 u32 DW0_Address1:16;
110 117
111 u32 DW1_Address2; 118 u32 DW1_Address2;
112 119
113 u32 DW2_RxSequenceCount1; 120 u32 DW2_RxSequenceCount1;
114 121
115 u32 DW3_RxSequenceCount2:16; 122 u32 DW3_RxSequenceCount2:16;
116 u32 DW3_RESERVED:16; 123 u32 DW3_RESERVED:16;
117 124
118 u32 DW4_TxSequenceCount1; 125 u32 DW4_TxSequenceCount1;
119 126
120 u32 DW5_TxSequenceCount2:16; 127 u32 DW5_TxSequenceCount2:16;
121 u32 DW5_RESERVED:16; 128 u32 DW5_RESERVED:16;
122 129
123 } KEY_TABLE, *PKEY_TABLE; 130 } KEY_TABLE, *PKEY_TABLE;
124 131
125 //-------------------------------------------------------- 132 //--------------------------------------------------------
126 // Descriptor 133 // Descriptor
127 //-------------------------------------------------------- 134 //--------------------------------------------------------
128 #define MAX_DESCRIPTOR_BUFFER_INDEX 8 // Have to multiple of 2 135 #define MAX_DESCRIPTOR_BUFFER_INDEX 8 // Have to multiple of 2
129 //#define FLAG_ERROR_TX_MASK cpu_to_le32(0x000000bf) //20061009 marked by anson's endian 136 //#define FLAG_ERROR_TX_MASK cpu_to_le32(0x000000bf) //20061009 marked by anson's endian
130 #define FLAG_ERROR_TX_MASK 0x000000bf //20061009 anson's endian 137 #define FLAG_ERROR_TX_MASK 0x000000bf //20061009 anson's endian
131 //#define FLAG_ERROR_RX_MASK 0x00000c3f 138 //#define FLAG_ERROR_RX_MASK 0x00000c3f
132 //#define FLAG_ERROR_RX_MASK cpu_to_le32(0x0000083f) //20061009 marked by anson's endian 139 //#define FLAG_ERROR_RX_MASK cpu_to_le32(0x0000083f) //20061009 marked by anson's endian
133 //Don't care replay error, 140 //Don't care replay error,
134 //it is handled by S/W 141 //it is handled by S/W
135 #define FLAG_ERROR_RX_MASK 0x0000083f //20060926 anson's endian 142 #define FLAG_ERROR_RX_MASK 0x0000083f //20060926 anson's endian
136 143
137 #define FLAG_BAND_RX_MASK 0x10000000 //Bit 28 144 #define FLAG_BAND_RX_MASK 0x10000000 //Bit 28
138 145
139 typedef struct _R00_DESCRIPTOR 146 typedef struct _R00_DESCRIPTOR
140 { 147 {
141 union 148 union
142 { 149 {
143 u32 value; 150 u32 value;
144 #ifdef _BIG_ENDIAN_ //20060926 anson's endian 151 #ifdef _BIG_ENDIAN_ //20060926 anson's endian
145 struct 152 struct
146 { 153 {
147 u32 R00_packet_or_buffer_status:1; 154 u32 R00_packet_or_buffer_status:1;
148 u32 R00_packet_in_fifo:1; 155 u32 R00_packet_in_fifo:1;
149 u32 R00_RESERVED:2; 156 u32 R00_RESERVED:2;
150 u32 R00_receive_byte_count:12; 157 u32 R00_receive_byte_count:12;
151 u32 R00_receive_time_index:16; 158 u32 R00_receive_time_index:16;
152 }; 159 };
153 #else 160 #else
154 struct 161 struct
155 { 162 {
156 u32 R00_receive_time_index:16; 163 u32 R00_receive_time_index:16;
157 u32 R00_receive_byte_count:12; 164 u32 R00_receive_byte_count:12;
158 u32 R00_RESERVED:2; 165 u32 R00_RESERVED:2;
159 u32 R00_packet_in_fifo:1; 166 u32 R00_packet_in_fifo:1;
160 u32 R00_packet_or_buffer_status:1; 167 u32 R00_packet_or_buffer_status:1;
161 }; 168 };
162 #endif 169 #endif
163 }; 170 };
164 } R00_DESCRIPTOR, *PR00_DESCRIPTOR; 171 } R00_DESCRIPTOR, *PR00_DESCRIPTOR;
165 172
166 typedef struct _T00_DESCRIPTOR 173 typedef struct _T00_DESCRIPTOR
167 { 174 {
168 union 175 union
169 { 176 {
170 u32 value; 177 u32 value;
171 #ifdef _BIG_ENDIAN_ //20061009 anson's endian 178 #ifdef _BIG_ENDIAN_ //20061009 anson's endian
172 struct 179 struct
173 { 180 {
174 u32 T00_first_mpdu:1; // for hardware use 181 u32 T00_first_mpdu:1; // for hardware use
175 u32 T00_last_mpdu:1; // for hardware use 182 u32 T00_last_mpdu:1; // for hardware use
176 u32 T00_IsLastMpdu:1;// 0: not 1:Yes for software used 183 u32 T00_IsLastMpdu:1;// 0: not 1:Yes for software used
177 u32 T00_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS 184 u32 T00_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
178 u32 T00_RESERVED_ID:2;//3 bit ID reserved 185 u32 T00_RESERVED_ID:2;//3 bit ID reserved
179 u32 T00_tx_packet_id:4;//930519.4.e 930810.3.c 186 u32 T00_tx_packet_id:4;//930519.4.e 930810.3.c
180 u32 T00_RESERVED:4; 187 u32 T00_RESERVED:4;
181 u32 T00_header_length:6; 188 u32 T00_header_length:6;
182 u32 T00_frame_length:12; 189 u32 T00_frame_length:12;
183 }; 190 };
184 #else 191 #else
185 struct 192 struct
186 { 193 {
187 u32 T00_frame_length:12; 194 u32 T00_frame_length:12;
188 u32 T00_header_length:6; 195 u32 T00_header_length:6;
189 u32 T00_RESERVED:4; 196 u32 T00_RESERVED:4;
190 u32 T00_tx_packet_id:4;//930519.4.e 930810.3.c 197 u32 T00_tx_packet_id:4;//930519.4.e 930810.3.c
191 u32 T00_RESERVED_ID:2;//3 bit ID reserved 198 u32 T00_RESERVED_ID:2;//3 bit ID reserved
192 u32 T00_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS 199 u32 T00_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
193 u32 T00_IsLastMpdu:1;// 0: not 1:Yes for software used 200 u32 T00_IsLastMpdu:1;// 0: not 1:Yes for software used
194 u32 T00_last_mpdu:1; // for hardware use 201 u32 T00_last_mpdu:1; // for hardware use
195 u32 T00_first_mpdu:1; // for hardware use 202 u32 T00_first_mpdu:1; // for hardware use
196 }; 203 };
197 #endif 204 #endif
198 }; 205 };
199 } T00_DESCRIPTOR, *PT00_DESCRIPTOR; 206 } T00_DESCRIPTOR, *PT00_DESCRIPTOR;
200 207
201 typedef struct _R01_DESCRIPTOR 208 typedef struct _R01_DESCRIPTOR
202 { 209 {
203 union 210 union
204 { 211 {
205 u32 value; 212 u32 value;
206 #ifdef _BIG_ENDIAN_ //20060926 add by anson's endian 213 #ifdef _BIG_ENDIAN_ //20060926 add by anson's endian
207 struct 214 struct
208 { 215 {
209 u32 R01_RESERVED:3; 216 u32 R01_RESERVED:3;
210 u32 R01_mod_type:1; 217 u32 R01_mod_type:1;
211 u32 R01_pre_type:1; 218 u32 R01_pre_type:1;
212 u32 R01_data_rate:3; 219 u32 R01_data_rate:3;
213 u32 R01_AGC_state:8; 220 u32 R01_AGC_state:8;
214 u32 R01_LNA_state:2; 221 u32 R01_LNA_state:2;
215 u32 R01_decryption_method:2; 222 u32 R01_decryption_method:2;
216 u32 R01_mic_error:1; 223 u32 R01_mic_error:1;
217 u32 R01_replay:1; 224 u32 R01_replay:1;
218 u32 R01_broadcast_frame:1; 225 u32 R01_broadcast_frame:1;
219 u32 R01_multicast_frame:1; 226 u32 R01_multicast_frame:1;
220 u32 R01_directed_frame:1; 227 u32 R01_directed_frame:1;
221 u32 R01_receive_frame_antenna_selection:1; 228 u32 R01_receive_frame_antenna_selection:1;
222 u32 R01_frame_receive_during_atim_window:1; 229 u32 R01_frame_receive_during_atim_window:1;
223 u32 R01_protocol_version_error:1; 230 u32 R01_protocol_version_error:1;
224 u32 R01_authentication_frame_icv_error:1; 231 u32 R01_authentication_frame_icv_error:1;
225 u32 R01_null_key_to_authentication_frame:1; 232 u32 R01_null_key_to_authentication_frame:1;
226 u32 R01_icv_error:1; 233 u32 R01_icv_error:1;
227 u32 R01_crc_error:1; 234 u32 R01_crc_error:1;
228 }; 235 };
229 #else 236 #else
230 struct 237 struct
231 { 238 {
232 u32 R01_crc_error:1; 239 u32 R01_crc_error:1;
233 u32 R01_icv_error:1; 240 u32 R01_icv_error:1;
234 u32 R01_null_key_to_authentication_frame:1; 241 u32 R01_null_key_to_authentication_frame:1;
235 u32 R01_authentication_frame_icv_error:1; 242 u32 R01_authentication_frame_icv_error:1;
236 u32 R01_protocol_version_error:1; 243 u32 R01_protocol_version_error:1;
237 u32 R01_frame_receive_during_atim_window:1; 244 u32 R01_frame_receive_during_atim_window:1;
238 u32 R01_receive_frame_antenna_selection:1; 245 u32 R01_receive_frame_antenna_selection:1;
239 u32 R01_directed_frame:1; 246 u32 R01_directed_frame:1;
240 u32 R01_multicast_frame:1; 247 u32 R01_multicast_frame:1;
241 u32 R01_broadcast_frame:1; 248 u32 R01_broadcast_frame:1;
242 u32 R01_replay:1; 249 u32 R01_replay:1;
243 u32 R01_mic_error:1; 250 u32 R01_mic_error:1;
244 u32 R01_decryption_method:2; 251 u32 R01_decryption_method:2;
245 u32 R01_LNA_state:2; 252 u32 R01_LNA_state:2;
246 u32 R01_AGC_state:8; 253 u32 R01_AGC_state:8;
247 u32 R01_data_rate:3; 254 u32 R01_data_rate:3;
248 u32 R01_pre_type:1; 255 u32 R01_pre_type:1;
249 u32 R01_mod_type:1; 256 u32 R01_mod_type:1;
250 u32 R01_RESERVED:3; 257 u32 R01_RESERVED:3;
251 }; 258 };
252 #endif 259 #endif
253 }; 260 };
254 } R01_DESCRIPTOR, *PR01_DESCRIPTOR; 261 } R01_DESCRIPTOR, *PR01_DESCRIPTOR;
255 262
256 typedef struct _T01_DESCRIPTOR 263 typedef struct _T01_DESCRIPTOR
257 { 264 {
258 union 265 union
259 { 266 {
260 u32 value; 267 u32 value;
261 #ifdef _BIG_ENDIAN_ //20061009 anson's endian 268 #ifdef _BIG_ENDIAN_ //20061009 anson's endian
262 struct 269 struct
263 { 270 {
264 u32 T01_rts_cts_duration:16; 271 u32 T01_rts_cts_duration:16;
265 u32 T01_fall_back_rate:3; 272 u32 T01_fall_back_rate:3;
266 u32 T01_add_rts:1; 273 u32 T01_add_rts:1;
267 u32 T01_add_cts:1; 274 u32 T01_add_cts:1;
268 u32 T01_modulation_type:1; 275 u32 T01_modulation_type:1;
269 u32 T01_plcp_header_length:1; 276 u32 T01_plcp_header_length:1;
270 u32 T01_transmit_rate:3; 277 u32 T01_transmit_rate:3;
271 u32 T01_wep_id:2; 278 u32 T01_wep_id:2;
272 u32 T01_add_challenge_text:1; 279 u32 T01_add_challenge_text:1;
273 u32 T01_inhibit_crc:1; 280 u32 T01_inhibit_crc:1;
274 u32 T01_loop_back_wep_mode:1; 281 u32 T01_loop_back_wep_mode:1;
275 u32 T01_retry_abort_ebable:1; 282 u32 T01_retry_abort_ebable:1;
276 }; 283 };
277 #else 284 #else
278 struct 285 struct
279 { 286 {
280 u32 T01_retry_abort_ebable:1; 287 u32 T01_retry_abort_ebable:1;
281 u32 T01_loop_back_wep_mode:1; 288 u32 T01_loop_back_wep_mode:1;
282 u32 T01_inhibit_crc:1; 289 u32 T01_inhibit_crc:1;
283 u32 T01_add_challenge_text:1; 290 u32 T01_add_challenge_text:1;
284 u32 T01_wep_id:2; 291 u32 T01_wep_id:2;
285 u32 T01_transmit_rate:3; 292 u32 T01_transmit_rate:3;
286 u32 T01_plcp_header_length:1; 293 u32 T01_plcp_header_length:1;
287 u32 T01_modulation_type:1; 294 u32 T01_modulation_type:1;
288 u32 T01_add_cts:1; 295 u32 T01_add_cts:1;
289 u32 T01_add_rts:1; 296 u32 T01_add_rts:1;
290 u32 T01_fall_back_rate:3; 297 u32 T01_fall_back_rate:3;
291 u32 T01_rts_cts_duration:16; 298 u32 T01_rts_cts_duration:16;
292 }; 299 };
293 #endif 300 #endif
294 }; 301 };
295 } T01_DESCRIPTOR, *PT01_DESCRIPTOR; 302 } T01_DESCRIPTOR, *PT01_DESCRIPTOR;
296 303
297 typedef struct _T02_DESCRIPTOR 304 typedef struct _T02_DESCRIPTOR
298 { 305 {
299 union 306 union
300 { 307 {
301 u32 value; 308 u32 value;
302 #ifdef _BIG_ENDIAN_ //20061009 add by anson's endian 309 #ifdef _BIG_ENDIAN_ //20061009 add by anson's endian
303 struct 310 struct
304 { 311 {
305 u32 T02_IsLastMpdu:1;// The same mechanism with T00 setting 312 u32 T02_IsLastMpdu:1;// The same mechanism with T00 setting
306 u32 T02_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS 313 u32 T02_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
307 u32 T02_RESERVED_ID:2;// The same mechanism with T00 setting 314 u32 T02_RESERVED_ID:2;// The same mechanism with T00 setting
308 u32 T02_Tx_PktID:4; 315 u32 T02_Tx_PktID:4;
309 u32 T02_MPDU_Cnt:4; 316 u32 T02_MPDU_Cnt:4;
310 u32 T02_RTS_Cnt:4; 317 u32 T02_RTS_Cnt:4;
311 u32 T02_RESERVED:7; 318 u32 T02_RESERVED:7;
312 u32 T02_transmit_complete:1; 319 u32 T02_transmit_complete:1;
313 u32 T02_transmit_abort_due_to_TBTT:1; 320 u32 T02_transmit_abort_due_to_TBTT:1;
314 u32 T02_effective_transmission_rate:1; 321 u32 T02_effective_transmission_rate:1;
315 u32 T02_transmit_without_encryption_due_to_wep_on_false:1; 322 u32 T02_transmit_without_encryption_due_to_wep_on_false:1;
316 u32 T02_discard_due_to_null_wep_key:1; 323 u32 T02_discard_due_to_null_wep_key:1;
317 u32 T02_RESERVED_1:1; 324 u32 T02_RESERVED_1:1;
318 u32 T02_out_of_MaxTxMSDULiftTime:1; 325 u32 T02_out_of_MaxTxMSDULiftTime:1;
319 u32 T02_transmit_abort:1; 326 u32 T02_transmit_abort:1;
320 u32 T02_transmit_fail:1; 327 u32 T02_transmit_fail:1;
321 }; 328 };
322 #else 329 #else
323 struct 330 struct
324 { 331 {
325 u32 T02_transmit_fail:1; 332 u32 T02_transmit_fail:1;
326 u32 T02_transmit_abort:1; 333 u32 T02_transmit_abort:1;
327 u32 T02_out_of_MaxTxMSDULiftTime:1; 334 u32 T02_out_of_MaxTxMSDULiftTime:1;
328 u32 T02_RESERVED_1:1; 335 u32 T02_RESERVED_1:1;
329 u32 T02_discard_due_to_null_wep_key:1; 336 u32 T02_discard_due_to_null_wep_key:1;
330 u32 T02_transmit_without_encryption_due_to_wep_on_false:1; 337 u32 T02_transmit_without_encryption_due_to_wep_on_false:1;
331 u32 T02_effective_transmission_rate:1; 338 u32 T02_effective_transmission_rate:1;
332 u32 T02_transmit_abort_due_to_TBTT:1; 339 u32 T02_transmit_abort_due_to_TBTT:1;
333 u32 T02_transmit_complete:1; 340 u32 T02_transmit_complete:1;
334 u32 T02_RESERVED:7; 341 u32 T02_RESERVED:7;
335 u32 T02_RTS_Cnt:4; 342 u32 T02_RTS_Cnt:4;
336 u32 T02_MPDU_Cnt:4; 343 u32 T02_MPDU_Cnt:4;
337 u32 T02_Tx_PktID:4; 344 u32 T02_Tx_PktID:4;
338 u32 T02_RESERVED_ID:2;// The same mechanism with T00 setting 345 u32 T02_RESERVED_ID:2;// The same mechanism with T00 setting
339 u32 T02_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS 346 u32 T02_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
340 u32 T02_IsLastMpdu:1;// The same mechanism with T00 setting 347 u32 T02_IsLastMpdu:1;// The same mechanism with T00 setting
341 }; 348 };
342 #endif 349 #endif
343 }; 350 };
344 } T02_DESCRIPTOR, *PT02_DESCRIPTOR; 351 } T02_DESCRIPTOR, *PT02_DESCRIPTOR;
345 352
346 typedef struct _DESCRIPTOR { // Skip length = 8 DWORD 353 typedef struct _DESCRIPTOR { // Skip length = 8 DWORD
347 // ID for descriptor ---, The field doesn't be cleard in the operation of Descriptor definition 354 // ID for descriptor ---, The field doesn't be cleard in the operation of Descriptor definition
348 u8 Descriptor_ID; 355 u8 Descriptor_ID;
349 //----------------------The above region doesn't be cleared by DESCRIPTOR_RESET------ 356 //----------------------The above region doesn't be cleared by DESCRIPTOR_RESET------
350 u8 RESERVED[3]; 357 u8 RESERVED[3];
351 358
352 u16 FragmentThreshold; 359 u16 FragmentThreshold;
353 u8 InternalUsed;//Only can be used by operation of descriptor definition 360 u8 InternalUsed;//Only can be used by operation of descriptor definition
354 u8 Type;// 0: 802.3 1:802.11 data frame 2:802.11 management frame 361 u8 Type;// 0: 802.3 1:802.11 data frame 2:802.11 management frame
355 362
356 u8 PreambleMode;// 0: short 1:long 363 u8 PreambleMode;// 0: short 1:long
357 u8 TxRate; 364 u8 TxRate;
358 u8 FragmentCount; 365 u8 FragmentCount;
359 u8 EapFix; // For speed up key install 366 u8 EapFix; // For speed up key install
360 367
361 // For R00 and T00 ---------------------------------------------- 368 // For R00 and T00 ----------------------------------------------
362 union 369 union
363 { 370 {
364 R00_DESCRIPTOR R00; 371 R00_DESCRIPTOR R00;
365 T00_DESCRIPTOR T00; 372 T00_DESCRIPTOR T00;
366 }; 373 };
367 374
368 // For R01 and T01 ---------------------------------------------- 375 // For R01 and T01 ----------------------------------------------
369 union 376 union
370 { 377 {
371 R01_DESCRIPTOR R01; 378 R01_DESCRIPTOR R01;
372 T01_DESCRIPTOR T01; 379 T01_DESCRIPTOR T01;
373 }; 380 };
374 381
375 // For R02 and T02 ---------------------------------------------- 382 // For R02 and T02 ----------------------------------------------
376 union 383 union
377 { 384 {
378 u32 R02; 385 u32 R02;
379 T02_DESCRIPTOR T02; 386 T02_DESCRIPTOR T02;
380 }; 387 };
381 388
382 // For R03 and T03 ---------------------------------------------- 389 // For R03 and T03 ----------------------------------------------
383 // For software used 390 // For software used
384 union 391 union
385 { 392 {
386 u32 R03; 393 u32 R03;
387 u32 T03; 394 u32 T03;
388 struct 395 struct
389 { 396 {
390 u8 buffer_number; 397 u8 buffer_number;
391 u8 buffer_start_index; 398 u8 buffer_start_index;
392 u16 buffer_total_size; 399 u16 buffer_total_size;
393 }; 400 };
394 }; 401 };
395 402
396 // For storing the buffer 403 // For storing the buffer
397 u16 buffer_size[ MAX_DESCRIPTOR_BUFFER_INDEX ]; 404 u16 buffer_size[ MAX_DESCRIPTOR_BUFFER_INDEX ];
398 void* buffer_address[ MAX_DESCRIPTOR_BUFFER_INDEX ];//931130.4.q 405 void* buffer_address[ MAX_DESCRIPTOR_BUFFER_INDEX ];//931130.4.q
399 406
400 } DESCRIPTOR, *PDESCRIPTOR; 407 } DESCRIPTOR, *PDESCRIPTOR;
401 408
402 409
403 #define DEFAULT_NULL_PACKET_COUNT 180000 //20060828.1 Add. 180 seconds 410 #define DEFAULT_NULL_PACKET_COUNT 180000 //20060828.1 Add. 180 seconds
404 411
405 #define MAX_TXVGA_EEPROM 9 //How many word(u16) of EEPROM will be used for TxVGA 412 #define MAX_TXVGA_EEPROM 9 //How many word(u16) of EEPROM will be used for TxVGA
406 #define MAX_RF_PARAMETER 32 413 #define MAX_RF_PARAMETER 32
407 414
408 typedef struct _TXVGA_FOR_50 { 415 typedef struct _TXVGA_FOR_50 {
409 u8 ChanNo; 416 u8 ChanNo;
410 u8 TxVgaValue; 417 u8 TxVgaValue;
411 } TXVGA_FOR_50; 418 } TXVGA_FOR_50;
412 419
413 420
414 //===================================================================== 421 //=====================================================================
415 // Device related include 422 // Device related include
416 //===================================================================== 423 //=====================================================================
417 424
418 #include "linux/wbusb_s.h" 425 #include "linux/wbusb_s.h"
419 #include "linux/wb35reg_s.h" 426 #include "linux/wb35reg_s.h"
420 #include "linux/wb35tx_s.h" 427 #include "linux/wb35tx_s.h"
421 #include "linux/wb35rx_s.h" 428 #include "linux/wb35rx_s.h"
422 429
423 430
424 // For Hal using ================================================================== 431 // For Hal using ==================================================================
425 typedef struct _HW_DATA_T 432 typedef struct _HW_DATA_T
426 { 433 {
427 // For compatible with 33 434 // For compatible with 33
428 u32 revision; 435 u32 revision;
429 u32 BB3c_cal; // The value for Tx calibration comes from EEPROM 436 u32 BB3c_cal; // The value for Tx calibration comes from EEPROM
430 u32 BB54_cal; // The value for Rx calibration comes from EEPROM 437 u32 BB54_cal; // The value for Rx calibration comes from EEPROM
431 438
432 439
433 // For surprise remove 440 // For surprise remove
434 u32 SurpriseRemove; // 0: Normal 1: Surprise remove 441 u32 SurpriseRemove; // 0: Normal 1: Surprise remove
435 u8 InitialResource; 442 u8 InitialResource;
436 u8 IsKeyPreSet; 443 u8 IsKeyPreSet;
437 u8 CalOneTime; // 20060630.1 444 u8 CalOneTime; // 20060630.1
438 445
439 u8 VCO_trim; 446 u8 VCO_trim;
440 447
441 // For Fix 1'st DMA bug 448 // For Fix 1'st DMA bug
442 u32 FragCount; 449 u32 FragCount;
443 u32 DMAFix; //V1_DMA_FIX The variable can be removed if driver want to save mem space for V2. 450 u32 DMAFix; //V1_DMA_FIX The variable can be removed if driver want to save mem space for V2.
444 451
445 //======================================================================================= 452 //=======================================================================================
446 // For USB driver, hal need more variables. Due to 453 // For USB driver, hal need more variables. Due to
447 // 1. NDIS-WDM operation 454 // 1. NDIS-WDM operation
448 // 2. The SME, MLME and OLD MDS need adapter structure, but the driver under HAL doesn't 455 // 2. The SME, MLME and OLD MDS need adapter structure, but the driver under HAL doesn't
449 // have that parameter when receiving and indicating packet. 456 // have that parameter when receiving and indicating packet.
450 // The MDS must input the adapter pointer as the second parameter of hal_init_hardware. 457 // The MDS must input the adapter pointer as the second parameter of hal_init_hardware.
451 // The function usage is different than PCI driver. 458 // The function usage is different than PCI driver.
452 //======================================================================================= 459 //=======================================================================================
453 void* adapter; 460 void* adapter;
454 461
455 //=============================================== 462 //===============================================
456 // Definition for MAC address 463 // Definition for MAC address
457 //=============================================== 464 //===============================================
458 u8 PermanentMacAddress[ETH_LENGTH_OF_ADDRESS + 2]; // The Enthernet addr that are stored in EEPROM. + 2 to 8-byte alignment 465 u8 PermanentMacAddress[ETH_LENGTH_OF_ADDRESS + 2]; // The Enthernet addr that are stored in EEPROM. + 2 to 8-byte alignment
459 u8 CurrentMacAddress[ETH_LENGTH_OF_ADDRESS + 2]; // The Enthernet addr that are in used. + 2 to 8-byte alignment 466 u8 CurrentMacAddress[ETH_LENGTH_OF_ADDRESS + 2]; // The Enthernet addr that are in used. + 2 to 8-byte alignment
460 467
461 //===================================================================== 468 //=====================================================================
462 // Definition for 802.11 469 // Definition for 802.11
463 //===================================================================== 470 //=====================================================================
464 u8 *bssid_pointer; // Used by hal_get_bssid for return value 471 u8 *bssid_pointer; // Used by hal_get_bssid for return value
465 u8 bssid[8];// Only 6 byte will be used. 8 byte is required for read buffer 472 u8 bssid[8];// Only 6 byte will be used. 8 byte is required for read buffer
466 u8 ssid[32];// maximum ssid length is 32 byte 473 u8 ssid[32];// maximum ssid length is 32 byte
467 474
468 u16 AID; 475 u16 AID;
469 u8 ssid_length; 476 u8 ssid_length;
470 u8 Channel; 477 u8 Channel;
471 478
472 u16 ListenInterval; 479 u16 ListenInterval;
473 u16 CapabilityInformation; 480 u16 CapabilityInformation;
474 481
475 u16 BeaconPeriod; 482 u16 BeaconPeriod;
476 u16 ProbeDelay; 483 u16 ProbeDelay;
477 484
478 u8 bss_type;// 0: IBSS_NET or 1:ESS_NET 485 u8 bss_type;// 0: IBSS_NET or 1:ESS_NET
479 u8 preamble;// 0: short preamble, 1: long preamble 486 u8 preamble;// 0: short preamble, 1: long preamble
480 u8 slot_time_select;// 9 or 20 value 487 u8 slot_time_select;// 9 or 20 value
481 u8 phy_type;// Phy select 488 u8 phy_type;// Phy select
482 489
483 u32 phy_para[MAX_RF_PARAMETER]; 490 u32 phy_para[MAX_RF_PARAMETER];
484 u32 phy_number; 491 u32 phy_number;
485 492
486 u32 CurrentRadioSw; // 20060320.2 0:On 1:Off 493 u32 CurrentRadioSw; // 20060320.2 0:On 1:Off
487 u32 CurrentRadioHw; // 20060825 0:On 1:Off 494 u32 CurrentRadioHw; // 20060825 0:On 1:Off
488 495
489 u8 *power_save_point; // Used by hal_get_power_save_mode for return value 496 u8 *power_save_point; // Used by hal_get_power_save_mode for return value
490 u8 cwmin; 497 u8 cwmin;
491 u8 desired_power_save; 498 u8 desired_power_save;
492 u8 dtim;// Is running dtim 499 u8 dtim;// Is running dtim
493 u8 mapping_key_replace_index;//In Key table, the next index be replaced 931130.4.r 500 u8 mapping_key_replace_index;//In Key table, the next index be replaced 931130.4.r
494 501
495 u16 MaxReceiveLifeTime; 502 u16 MaxReceiveLifeTime;
496 u16 FragmentThreshold; 503 u16 FragmentThreshold;
497 u16 FragmentThreshold_tmp; 504 u16 FragmentThreshold_tmp;
498 u16 cwmax; 505 u16 cwmax;
499 506
500 u8 Key_slot[MAX_KEY_TABLE][8]; //Ownership record for key slot. For Alignment 507 u8 Key_slot[MAX_KEY_TABLE][8]; //Ownership record for key slot. For Alignment
501 u32 Key_content[MAX_KEY_TABLE][12]; // 10DW for each entry + 2 for burst command( Off and On valid bit) 508 u32 Key_content[MAX_KEY_TABLE][12]; // 10DW for each entry + 2 for burst command( Off and On valid bit)
502 u8 CurrentDefaultKeyIndex; 509 u8 CurrentDefaultKeyIndex;
503 u32 CurrentDefaultKeyLength; 510 u32 CurrentDefaultKeyLength;
504 511
505 //======================================================================== 512 //========================================================================
506 // Variable for each module 513 // Variable for each module
507 //======================================================================== 514 //========================================================================
508 WBUSB WbUsb; // Need WbUsb.h 515 WBUSB WbUsb; // Need WbUsb.h
509 struct wb35_reg reg; // Need Wb35Reg.h 516 struct wb35_reg reg; // Need Wb35Reg.h
510 WB35TX Wb35Tx; // Need Wb35Tx.h 517 WB35TX Wb35Tx; // Need Wb35Tx.h
511 WB35RX Wb35Rx; // Need Wb35Rx.h 518 WB35RX Wb35Rx; // Need Wb35Rx.h
512 519
513 struct timer_list LEDTimer;// For LED 520 struct timer_list LEDTimer;// For LED
514 521
515 u32 LEDpoint;// For LED 522 u32 LEDpoint;// For LED
516 523
517 u32 dto_tx_retry_count; // LA20040210_DTO kevin 524 u32 dto_tx_retry_count; // LA20040210_DTO kevin
518 u32 dto_tx_frag_count; // LA20040210_DTO kevin 525 u32 dto_tx_frag_count; // LA20040210_DTO kevin
519 u32 rx_ok_count[13]; // index=0: total rx ok 526 u32 rx_ok_count[13]; // index=0: total rx ok
520 //u32 rx_ok_bytes[13]; // index=0, total rx ok bytes 527 //u32 rx_ok_bytes[13]; // index=0, total rx ok bytes
521 u32 rx_err_count[13]; // index=0: total rx err 528 u32 rx_err_count[13]; // index=0: total rx err
522 529
523 //for Tx debug 530 //for Tx debug
524 u32 tx_TBTT_start_count; 531 u32 tx_TBTT_start_count;
525 u32 tx_ETR_count; 532 u32 tx_ETR_count;
526 u32 tx_WepOn_false_count; 533 u32 tx_WepOn_false_count;
527 u32 tx_Null_key_count; 534 u32 tx_Null_key_count;
528 u32 tx_retry_count[8]; 535 u32 tx_retry_count[8];
529 536
530 u8 PowerIndexFromEEPROM; // For 2412MHz 537 u8 PowerIndexFromEEPROM; // For 2412MHz
531 u8 power_index; 538 u8 power_index;
532 u8 IsWaitJoinComplete; // TRUE: set join request 539 u8 IsWaitJoinComplete; // TRUE: set join request
533 u8 band; 540 u8 band;
534 541
535 u16 SoftwareSet; 542 u16 SoftwareSet;
536 u16 Reserved_s; 543 u16 Reserved_s;
537 544
538 u32 IsInitOK; // 0: Driver starting 1: Driver init OK 545 u32 IsInitOK; // 0: Driver starting 1: Driver init OK
539 546
540 // For Phy calibration 547 // For Phy calibration
541 s32 iq_rsdl_gain_tx_d2; 548 s32 iq_rsdl_gain_tx_d2;
542 s32 iq_rsdl_phase_tx_d2; 549 s32 iq_rsdl_phase_tx_d2;
543 u32 txvga_setting_for_cal; // 20060703.1 Add 550 u32 txvga_setting_for_cal; // 20060703.1 Add
544 551
545 u8 TxVgaSettingInEEPROM[ (((MAX_TXVGA_EEPROM*2)+3) & ~0x03) ]; // 20060621 For backup EEPROM value 552 u8 TxVgaSettingInEEPROM[ (((MAX_TXVGA_EEPROM*2)+3) & ~0x03) ]; // 20060621 For backup EEPROM value
546 u8 TxVgaFor24[16]; // Max is 14, 2 for alignment 553 u8 TxVgaFor24[16]; // Max is 14, 2 for alignment
547 TXVGA_FOR_50 TxVgaFor50[36]; // 35 channels in 5G. 35x2 = 70 byte. 2 for alignments 554 TXVGA_FOR_50 TxVgaFor50[36]; // 35 channels in 5G. 35x2 = 70 byte. 2 for alignments
548 555
549 u16 Scan_Interval; 556 u16 Scan_Interval;
550 u16 RESERVED6; 557 u16 RESERVED6;
551 558
552 // LED control 559 // LED control
553 u32 LED_control; 560 u32 LED_control;
554 // LED_control 4 byte: Gray_Led_1[3] Gray_Led_0[2] Led[1] Led[0] 561 // LED_control 4 byte: Gray_Led_1[3] Gray_Led_0[2] Led[1] Led[0]
555 // Gray_Led 562 // Gray_Led
556 // For Led gray setting 563 // For Led gray setting
557 // Led 564 // Led
558 // 0: normal control, LED behavior will decide by EEPROM setting 565 // 0: normal control, LED behavior will decide by EEPROM setting
559 // 1: Turn off specific LED 566 // 1: Turn off specific LED
560 // 2: Always on specific LED 567 // 2: Always on specific LED
561 // 3: slow blinking specific LED 568 // 3: slow blinking specific LED
562 // 4: fast blinking specific LED 569 // 4: fast blinking specific LED
563 // 5: WPS led control is set. Led0 is Red, Led1 id Green 570 // 5: WPS led control is set. Led0 is Red, Led1 id Green
564 // Led[1] is parameter for WPS LED mode 571 // Led[1] is parameter for WPS LED mode
565 // // 1:InProgress 2: Error 3: Session overlap 4: Success 20061108 control 572 // // 1:InProgress 2: Error 3: Session overlap 4: Success 20061108 control
566 573
567 u32 LED_LinkOn; //Turn LED on control 574 u32 LED_LinkOn; //Turn LED on control
568 u32 LED_Scanning; // Let LED in scan process control 575 u32 LED_Scanning; // Let LED in scan process control
569 u32 LED_Blinking; // Temp variable for shining 576 u32 LED_Blinking; // Temp variable for shining
570 u32 RxByteCountLast; 577 u32 RxByteCountLast;
571 u32 TxByteCountLast; 578 u32 TxByteCountLast;
572 579
573 atomic_t SurpriseRemoveCount; 580 atomic_t SurpriseRemoveCount;
574 581
575 // For global timer 582 // For global timer
576 u32 time_count;//TICK_TIME_100ms 1 = 100ms 583 u32 time_count;//TICK_TIME_100ms 1 = 100ms
577 584
578 // For error recover 585 // For error recover
579 u32 HwStop; 586 u32 HwStop;
580 587
581 // 20060828.1 for avoid AP disconnect 588 // 20060828.1 for avoid AP disconnect
582 u32 NullPacketCount; 589 u32 NullPacketCount;
583 590
584 } hw_data_t, *phw_data_t; 591 } hw_data_t, *phw_data_t;
585 592
586 // The mapping of Rx and Tx descriptor field 593 // The mapping of Rx and Tx descriptor field
587 typedef struct _HAL_RATE 594 typedef struct _HAL_RATE
588 { 595 {
589 // DSSS 596 // DSSS
590 u32 RESERVED_0; 597 u32 RESERVED_0;
591 u32 NumRate2MS; 598 u32 NumRate2MS;
592 u32 NumRate55MS; 599 u32 NumRate55MS;
593 u32 NumRate11MS; 600 u32 NumRate11MS;
594 601
595 u32 RESERVED_1[4]; 602 u32 RESERVED_1[4];
596 603
597 u32 NumRate1M; 604 u32 NumRate1M;
598 u32 NumRate2ML; 605 u32 NumRate2ML;
599 u32 NumRate55ML; 606 u32 NumRate55ML;
600 u32 NumRate11ML; 607 u32 NumRate11ML;
601 608
602 u32 RESERVED_2[4]; 609 u32 RESERVED_2[4];
603 610
604 // OFDM 611 // OFDM
605 u32 NumRate6M; 612 u32 NumRate6M;
606 u32 NumRate9M; 613 u32 NumRate9M;
607 u32 NumRate12M; 614 u32 NumRate12M;
608 u32 NumRate18M; 615 u32 NumRate18M;
609 u32 NumRate24M; 616 u32 NumRate24M;
610 u32 NumRate36M; 617 u32 NumRate36M;
611 u32 NumRate48M; 618 u32 NumRate48M;
612 u32 NumRate54M; 619 u32 NumRate54M;
613 } HAL_RATE, *PHAL_RATE; 620 } HAL_RATE, *PHAL_RATE;
621
622 #endif
614 623
drivers/staging/winbond/wblinux.c
Diff comments   View file @ 80aba53
1 //============================================================================ 1 //============================================================================
2 // Copyright (c) 1996-2005 Winbond Electronic Corporation 2 // Copyright (c) 1996-2005 Winbond Electronic Corporation
3 // 3 //
4 // Module Name: 4 // Module Name:
5 // wblinux.c 5 // wblinux.c
6 // 6 //
7 // Abstract: 7 // Abstract:
8 // Linux releated routines 8 // Linux releated routines
9 // 9 //
10 //============================================================================ 10 //============================================================================
11 #include <linux/netdevice.h>
12
13 #include "mds_f.h"
14 #include "mto_f.h"
11 #include "os_common.h" 15 #include "os_common.h"
16 #include "wbhal_f.h"
17 #include "wblinux_f.h"
12 18
13 unsigned char 19 unsigned char
14 WBLINUX_Initial(struct wb35_adapter * adapter) 20 WBLINUX_Initial(struct wb35_adapter * adapter)
15 { 21 {
16 spin_lock_init( &adapter->SpinLock ); 22 spin_lock_init( &adapter->SpinLock );
17 return true; 23 return true;
18 } 24 }
19 25
20 void 26 void
21 WBLinux_ReceivePacket(struct wb35_adapter * adapter, PRXLAYER1 pRxLayer1) 27 WBLinux_ReceivePacket(struct wb35_adapter * adapter, PRXLAYER1 pRxLayer1)
22 { 28 {
23 BUG(); 29 BUG();
24 } 30 }
25 31
26 32
27 void 33 void
28 WBLINUX_GetNextPacket(struct wb35_adapter * adapter, PDESCRIPTOR pDes) 34 WBLINUX_GetNextPacket(struct wb35_adapter * adapter, PDESCRIPTOR pDes)
29 { 35 {
30 BUG(); 36 BUG();
31 } 37 }
32 38
33 void 39 void
34 WBLINUX_GetNextPacketCompleted(struct wb35_adapter * adapter, PDESCRIPTOR pDes) 40 WBLINUX_GetNextPacketCompleted(struct wb35_adapter * adapter, PDESCRIPTOR pDes)
35 { 41 {
36 BUG(); 42 BUG();
37 } 43 }
38 44
39 void 45 void
40 WBLINUX_Destroy(struct wb35_adapter * adapter) 46 WBLINUX_Destroy(struct wb35_adapter * adapter)
41 { 47 {
42 WBLINUX_stop( adapter ); 48 WBLINUX_stop( adapter );
43 #ifdef _PE_USB_INI_DUMP_ 49 #ifdef _PE_USB_INI_DUMP_
44 WBDEBUG(("[w35und] unregister_netdev!\n")); 50 WBDEBUG(("[w35und] unregister_netdev!\n"));
45 #endif 51 #endif
46 } 52 }
47 53
48 void 54 void
49 WBLINUX_stop( struct wb35_adapter * adapter ) 55 WBLINUX_stop( struct wb35_adapter * adapter )
50 { 56 {
51 struct sk_buff *pSkb; 57 struct sk_buff *pSkb;
52 58
53 if (atomic_inc_return(&adapter->ThreadCount) == 1) { 59 if (atomic_inc_return(&adapter->ThreadCount) == 1) {
54 // Shutdown module immediately 60 // Shutdown module immediately
55 adapter->shutdown = 1; 61 adapter->shutdown = 1;
56 62
57 while (adapter->skb_array[ adapter->skb_GetIndex ]) { 63 while (adapter->skb_array[ adapter->skb_GetIndex ]) {
58 // Trying to free the un-sending packet 64 // Trying to free the un-sending packet
59 pSkb = adapter->skb_array[ adapter->skb_GetIndex ]; 65 pSkb = adapter->skb_array[ adapter->skb_GetIndex ];
60 adapter->skb_array[ adapter->skb_GetIndex ] = NULL; 66 adapter->skb_array[ adapter->skb_GetIndex ] = NULL;
61 if( in_irq() ) 67 if( in_irq() )
62 dev_kfree_skb_irq( pSkb ); 68 dev_kfree_skb_irq( pSkb );
63 else 69 else
64 dev_kfree_skb( pSkb ); 70 dev_kfree_skb( pSkb );
65 71
66 adapter->skb_GetIndex++; 72 adapter->skb_GetIndex++;
67 adapter->skb_GetIndex %= WBLINUX_PACKET_ARRAY_SIZE; 73 adapter->skb_GetIndex %= WBLINUX_PACKET_ARRAY_SIZE;
68 } 74 }
69 75
70 #ifdef _PE_STATE_DUMP_ 76 #ifdef _PE_STATE_DUMP_
71 WBDEBUG(( "[w35und] SKB_RELEASE OK\n" )); 77 WBDEBUG(( "[w35und] SKB_RELEASE OK\n" ));
72 #endif 78 #endif
73 } 79 }
74 80
75 atomic_dec(&adapter->ThreadCount); 81 atomic_dec(&adapter->ThreadCount);
76 } 82 }
77 83
78 void 84 void
79 WbWlanHalt(struct wb35_adapter *adapter) 85 WbWlanHalt(struct wb35_adapter *adapter)
80 { 86 {
81 //--------------------- 87 //---------------------
82 adapter->sLocalPara.ShutDowned = true; 88 adapter->sLocalPara.ShutDowned = true;
83 89
84 Mds_Destroy(adapter); 90 Mds_Destroy(adapter);
85 91
86 // Turn off Rx and Tx hardware ability 92 // Turn off Rx and Tx hardware ability
87 hal_stop(&adapter->sHwData); 93 hal_stop(&adapter->sHwData);
88 #ifdef _PE_USB_INI_DUMP_ 94 #ifdef _PE_USB_INI_DUMP_
89 WBDEBUG(("[w35und] Hal_stop O.K.\n")); 95 WBDEBUG(("[w35und] Hal_stop O.K.\n"));
90 #endif 96 #endif
91 msleep(100);// Waiting Irp completed 97 msleep(100);// Waiting Irp completed
92 98
93 // Destroy the NDIS module 99 // Destroy the NDIS module
94 WBLINUX_Destroy(adapter); 100 WBLINUX_Destroy(adapter);
95 101
96 // Halt the HAL 102 // Halt the HAL
97 hal_halt(&adapter->sHwData, NULL); 103 hal_halt(&adapter->sHwData, NULL);
98 } 104 }
99 105
100 unsigned char 106 unsigned char
101 WbWLanInitialize(struct wb35_adapter *adapter) 107 WbWLanInitialize(struct wb35_adapter *adapter)
102 { 108 {
103 phw_data_t pHwData; 109 phw_data_t pHwData;
104 u8 *pMacAddr; 110 u8 *pMacAddr;
105 u8 *pMacAddr2; 111 u8 *pMacAddr2;
106 u32 InitStep = 0; 112 u32 InitStep = 0;
107 u8 EEPROM_region; 113 u8 EEPROM_region;
108 u8 HwRadioOff; 114 u8 HwRadioOff;
109 115
110 // 116 //
111 // Setting default value for Linux 117 // Setting default value for Linux
112 // 118 //
113 adapter->sLocalPara.region_INF = REGION_AUTO; 119 adapter->sLocalPara.region_INF = REGION_AUTO;
114 adapter->sLocalPara.TxRateMode = RATE_AUTO; 120 adapter->sLocalPara.TxRateMode = RATE_AUTO;
115 psLOCAL->bMacOperationMode = MODE_802_11_BG; // B/G mode 121 psLOCAL->bMacOperationMode = MODE_802_11_BG; // B/G mode
116 adapter->Mds.TxRTSThreshold = DEFAULT_RTSThreshold; 122 adapter->Mds.TxRTSThreshold = DEFAULT_RTSThreshold;
117 adapter->Mds.TxFragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD; 123 adapter->Mds.TxFragmentThreshold = DEFAULT_FRAGMENT_THRESHOLD;
118 hal_set_phy_type( &adapter->sHwData, RF_WB_242_1 ); 124 hal_set_phy_type( &adapter->sHwData, RF_WB_242_1 );
119 adapter->sLocalPara.MTUsize = MAX_ETHERNET_PACKET_SIZE; 125 adapter->sLocalPara.MTUsize = MAX_ETHERNET_PACKET_SIZE;
120 psLOCAL->bPreambleMode = AUTO_MODE; 126 psLOCAL->bPreambleMode = AUTO_MODE;
121 adapter->sLocalPara.RadioOffStatus.boSwRadioOff = false; 127 adapter->sLocalPara.RadioOffStatus.boSwRadioOff = false;
122 pHwData = &adapter->sHwData; 128 pHwData = &adapter->sHwData;
123 hal_set_phy_type( pHwData, RF_DECIDE_BY_INF ); 129 hal_set_phy_type( pHwData, RF_DECIDE_BY_INF );
124 130
125 // 131 //
126 // Initial each module and variable 132 // Initial each module and variable
127 // 133 //
128 if (!WBLINUX_Initial(adapter)) { 134 if (!WBLINUX_Initial(adapter)) {
129 #ifdef _PE_USB_INI_DUMP_ 135 #ifdef _PE_USB_INI_DUMP_
130 WBDEBUG(("[w35und]WBNDIS initialization failed\n")); 136 WBDEBUG(("[w35und]WBNDIS initialization failed\n"));
131 #endif 137 #endif
132 goto error; 138 goto error;
133 } 139 }
134 140
135 // Initial Software variable 141 // Initial Software variable
136 adapter->sLocalPara.ShutDowned = false; 142 adapter->sLocalPara.ShutDowned = false;
137 143
138 //added by ws for wep key error detection 144 //added by ws for wep key error detection
139 adapter->sLocalPara.bWepKeyError= false; 145 adapter->sLocalPara.bWepKeyError= false;
140 adapter->sLocalPara.bToSelfPacketReceived = false; 146 adapter->sLocalPara.bToSelfPacketReceived = false;
141 adapter->sLocalPara.WepKeyDetectTimerCount= 2 * 100; /// 2 seconds 147 adapter->sLocalPara.WepKeyDetectTimerCount= 2 * 100; /// 2 seconds
142 148
143 // Initial USB hal 149 // Initial USB hal
144 InitStep = 1; 150 InitStep = 1;
145 pHwData = &adapter->sHwData; 151 pHwData = &adapter->sHwData;
146 if (!hal_init_hardware(pHwData, adapter)) 152 if (!hal_init_hardware(pHwData, adapter))
147 goto error; 153 goto error;
148 154
149 EEPROM_region = hal_get_region_from_EEPROM( pHwData ); 155 EEPROM_region = hal_get_region_from_EEPROM( pHwData );
150 if (EEPROM_region != REGION_AUTO) 156 if (EEPROM_region != REGION_AUTO)
151 psLOCAL->region = EEPROM_region; 157 psLOCAL->region = EEPROM_region;
152 else { 158 else {
153 if (psLOCAL->region_INF != REGION_AUTO) 159 if (psLOCAL->region_INF != REGION_AUTO)
154 psLOCAL->region = psLOCAL->region_INF; 160 psLOCAL->region = psLOCAL->region_INF;
155 else 161 else
156 psLOCAL->region = REGION_USA; //default setting 162 psLOCAL->region = REGION_USA; //default setting
157 } 163 }
158 164
159 // Get Software setting flag from hal 165 // Get Software setting flag from hal
160 adapter->sLocalPara.boAntennaDiversity = false; 166 adapter->sLocalPara.boAntennaDiversity = false;
161 if (hal_software_set(pHwData) & 0x00000001) 167 if (hal_software_set(pHwData) & 0x00000001)
162 adapter->sLocalPara.boAntennaDiversity = true; 168 adapter->sLocalPara.boAntennaDiversity = true;
163 169
164 // 170 //
165 // For TS module 171 // For TS module
166 // 172 //
167 InitStep = 2; 173 InitStep = 2;
168 174
169 // For MDS module 175 // For MDS module
170 InitStep = 3; 176 InitStep = 3;
171 Mds_initial(adapter); 177 Mds_initial(adapter);
172 178
173 //======================================= 179 //=======================================
174 // Initialize the SME, SCAN, MLME, ROAM 180 // Initialize the SME, SCAN, MLME, ROAM
175 //======================================= 181 //=======================================
176 InitStep = 4; 182 InitStep = 4;
177 InitStep = 5; 183 InitStep = 5;
178 InitStep = 6; 184 InitStep = 6;
179 185
180 // If no user-defined address in the registry, use the addresss "burned" on the NIC instead. 186 // If no user-defined address in the registry, use the addresss "burned" on the NIC instead.
181 pMacAddr = adapter->sLocalPara.ThisMacAddress; 187 pMacAddr = adapter->sLocalPara.ThisMacAddress;
182 pMacAddr2 = adapter->sLocalPara.PermanentAddress; 188 pMacAddr2 = adapter->sLocalPara.PermanentAddress;
183 hal_get_permanent_address( pHwData, adapter->sLocalPara.PermanentAddress );// Reading ethernet address from EEPROM 189 hal_get_permanent_address( pHwData, adapter->sLocalPara.PermanentAddress );// Reading ethernet address from EEPROM
184 if (memcmp(pMacAddr, "\x00\x00\x00\x00\x00\x00", MAC_ADDR_LENGTH) == 0) 190 if (memcmp(pMacAddr, "\x00\x00\x00\x00\x00\x00", MAC_ADDR_LENGTH) == 0)
185 memcpy(pMacAddr, pMacAddr2, MAC_ADDR_LENGTH); 191 memcpy(pMacAddr, pMacAddr2, MAC_ADDR_LENGTH);
186 else { 192 else {
187 // Set the user define MAC address 193 // Set the user define MAC address
188 hal_set_ethernet_address(pHwData, adapter->sLocalPara.ThisMacAddress); 194 hal_set_ethernet_address(pHwData, adapter->sLocalPara.ThisMacAddress);
189 } 195 }
190 196
191 //get current antenna 197 //get current antenna
192 psLOCAL->bAntennaNo = hal_get_antenna_number(pHwData); 198 psLOCAL->bAntennaNo = hal_get_antenna_number(pHwData);
193 #ifdef _PE_STATE_DUMP_ 199 #ifdef _PE_STATE_DUMP_
194 WBDEBUG(("Driver init, antenna no = %d\n", psLOCAL->bAntennaNo)); 200 WBDEBUG(("Driver init, antenna no = %d\n", psLOCAL->bAntennaNo));
195 #endif 201 #endif
196 hal_get_hw_radio_off( pHwData ); 202 hal_get_hw_radio_off( pHwData );
197 203
198 // Waiting for HAL setting OK 204 // Waiting for HAL setting OK
199 while (!hal_idle(pHwData)) 205 while (!hal_idle(pHwData))
200 msleep(10); 206 msleep(10);
201 207
202 MTO_Init(adapter); 208 MTO_Init(adapter);
203 209
204 HwRadioOff = hal_get_hw_radio_off( pHwData ); 210 HwRadioOff = hal_get_hw_radio_off( pHwData );
205 psLOCAL->RadioOffStatus.boHwRadioOff = !!HwRadioOff; 211 psLOCAL->RadioOffStatus.boHwRadioOff = !!HwRadioOff;
206 212
207 hal_set_radio_mode( pHwData, (unsigned char)(psLOCAL->RadioOffStatus.boSwRadioOff || psLOCAL->RadioOffStatus.boHwRadioOff) ); 213 hal_set_radio_mode( pHwData, (unsigned char)(psLOCAL->RadioOffStatus.boSwRadioOff || psLOCAL->RadioOffStatus.boHwRadioOff) );
208 214
209 hal_driver_init_OK(pHwData) = 1; // Notify hal that the driver is ready now. 215 hal_driver_init_OK(pHwData) = 1; // Notify hal that the driver is ready now.
210 //set a tx power for reference..... 216 //set a tx power for reference.....
211 // sme_set_tx_power_level(adapter, 12); FIXME? 217 // sme_set_tx_power_level(adapter, 12); FIXME?
212 return true; 218 return true;
213 219
214 error: 220 error:
215 switch (InitStep) { 221 switch (InitStep) {
216 case 5: 222 case 5:
217 case 4: 223 case 4:
218 case 3: Mds_Destroy( adapter ); 224 case 3: Mds_Destroy( adapter );
219 case 2: 225 case 2:
220 case 1: WBLINUX_Destroy( adapter ); 226 case 1: WBLINUX_Destroy( adapter );
221 hal_halt( pHwData, NULL ); 227 hal_halt( pHwData, NULL );
222 case 0: break; 228 case 0: break;
223 } 229 }
224 230
225 return false; 231 return false;
226 } 232 }
227 233
drivers/staging/winbond/wblinux_f.h
Diff comments   View file @ 80aba53
1 #ifndef __WBLINUX_F_H
2 #define __WBLINUX_F_H
3
4 #include "adapter.h"
5 #include "mds_s.h"
6
1 //========================================================================= 7 //=========================================================================
2 // Copyright (c) 1996-2004 Winbond Electronic Corporation 8 // Copyright (c) 1996-2004 Winbond Electronic Corporation
3 // 9 //
4 // wblinux_f.h 10 // wblinux_f.h
5 // 11 //
6 void WBLinux_ReceivePacket( struct wb35_adapter *adapter, PRXLAYER1 pRxLayer1 ); 12 void WBLinux_ReceivePacket( struct wb35_adapter *adapter, PRXLAYER1 pRxLayer1 );
7 unsigned char WBLINUX_Initial( struct wb35_adapter *adapter ); 13 unsigned char WBLINUX_Initial( struct wb35_adapter *adapter );
8 int wb35_start_xmit(struct sk_buff *skb, struct net_device *netdev ); 14 int wb35_start_xmit(struct sk_buff *skb, struct net_device *netdev );
9 void WBLINUX_GetNextPacket( struct wb35_adapter *adapter, PDESCRIPTOR pDes ); 15 void WBLINUX_GetNextPacket( struct wb35_adapter *adapter, PDESCRIPTOR pDes );
10 void WBLINUX_GetNextPacketCompleted( struct wb35_adapter *adapter, PDESCRIPTOR pDes ); 16 void WBLINUX_GetNextPacketCompleted( struct wb35_adapter *adapter, PDESCRIPTOR pDes );
11 void WBLINUX_stop( struct wb35_adapter *adapter ); 17 void WBLINUX_stop( struct wb35_adapter *adapter );
12 void WBLINUX_Destroy( struct wb35_adapter *adapter ); 18 void WBLINUX_Destroy( struct wb35_adapter *adapter );
13 void wb35_set_multicast( struct net_device *netdev ); 19 void wb35_set_multicast( struct net_device *netdev );
14 struct net_device_stats * wb35_netdev_stats( struct net_device *netdev ); 20 struct net_device_stats * wb35_netdev_stats( struct net_device *netdev );
15 void WBLINUX_stop( struct wb35_adapter *adapter ); 21 void WBLINUX_stop( struct wb35_adapter *adapter );
16 void WbWlanHalt( struct wb35_adapter *adapter ); 22 void WbWlanHalt( struct wb35_adapter *adapter );
17 unsigned char WbWLanInitialize(struct wb35_adapter *adapter); 23 unsigned char WbWLanInitialize(struct wb35_adapter *adapter);
24
25 #endif
18 26