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Commit 84b5abe69ff600a559e1a1fa29f1edad707d4e2f

Authored by Russell King
Committed by Russell King
1 parent e0f205d9c6
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

[ARM] Fix i2c-pxa slave mode support 

i2c-pxa times out when trying to enable slave mode due to an
incorrect test.  Also, check that i2c->slave is non-NULL
before dereferencing it.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Showing 1 changed file with 6 additions and 2 deletions Inline Diff

drivers/i2c/busses/i2c-pxa.c
Diff comments   View file @ 84b5abe
1 /* 1 /*
2 * i2c_adap_pxa.c 2 * i2c_adap_pxa.c
3 * 3 *
4 * I2C adapter for the PXA I2C bus access. 4 * I2C adapter for the PXA I2C bus access.
5 * 5 *
6 * Copyright (C) 2002 Intrinsyc Software Inc. 6 * Copyright (C) 2002 Intrinsyc Software Inc.
7 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd. 7 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 * 12 *
13 * History: 13 * History:
14 * Apr 2002: Initial version [CS] 14 * Apr 2002: Initial version [CS]
15 * Jun 2002: Properly seperated algo/adap [FB] 15 * Jun 2002: Properly seperated algo/adap [FB]
16 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem] 16 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
17 * Jan 2003: added limited signal handling [Kai-Uwe Bloem] 17 * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
18 * Sep 2004: Major rework to ensure efficient bus handling [RMK] 18 * Sep 2004: Major rework to ensure efficient bus handling [RMK]
19 * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood] 19 * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
20 * Feb 2005: Rework slave mode handling [RMK] 20 * Feb 2005: Rework slave mode handling [RMK]
21 */ 21 */
22 #include <linux/kernel.h> 22 #include <linux/kernel.h>
23 #include <linux/module.h> 23 #include <linux/module.h>
24 #include <linux/i2c.h> 24 #include <linux/i2c.h>
25 #include <linux/i2c-id.h> 25 #include <linux/i2c-id.h>
26 #include <linux/init.h> 26 #include <linux/init.h>
27 #include <linux/time.h> 27 #include <linux/time.h>
28 #include <linux/sched.h> 28 #include <linux/sched.h>
29 #include <linux/delay.h> 29 #include <linux/delay.h>
30 #include <linux/errno.h> 30 #include <linux/errno.h>
31 #include <linux/interrupt.h> 31 #include <linux/interrupt.h>
32 #include <linux/i2c-pxa.h> 32 #include <linux/i2c-pxa.h>
33 #include <linux/platform_device.h> 33 #include <linux/platform_device.h>
34 34
35 #include <asm/hardware.h> 35 #include <asm/hardware.h>
36 #include <asm/irq.h> 36 #include <asm/irq.h>
37 #include <asm/arch/i2c.h> 37 #include <asm/arch/i2c.h>
38 #include <asm/arch/pxa-regs.h> 38 #include <asm/arch/pxa-regs.h>
39 39
40 struct pxa_i2c { 40 struct pxa_i2c {
41 spinlock_t lock; 41 spinlock_t lock;
42 wait_queue_head_t wait; 42 wait_queue_head_t wait;
43 struct i2c_msg *msg; 43 struct i2c_msg *msg;
44 unsigned int msg_num; 44 unsigned int msg_num;
45 unsigned int msg_idx; 45 unsigned int msg_idx;
46 unsigned int msg_ptr; 46 unsigned int msg_ptr;
47 unsigned int slave_addr; 47 unsigned int slave_addr;
48 48
49 struct i2c_adapter adap; 49 struct i2c_adapter adap;
50 #ifdef CONFIG_I2C_PXA_SLAVE 50 #ifdef CONFIG_I2C_PXA_SLAVE
51 struct i2c_slave_client *slave; 51 struct i2c_slave_client *slave;
52 #endif 52 #endif
53 53
54 unsigned int irqlogidx; 54 unsigned int irqlogidx;
55 u32 isrlog[32]; 55 u32 isrlog[32];
56 u32 icrlog[32]; 56 u32 icrlog[32];
57 }; 57 };
58 58
59 /* 59 /*
60 * I2C Slave mode address 60 * I2C Slave mode address
61 */ 61 */
62 #define I2C_PXA_SLAVE_ADDR 0x1 62 #define I2C_PXA_SLAVE_ADDR 0x1
63 63
64 #ifdef DEBUG 64 #ifdef DEBUG
65 65
66 struct bits { 66 struct bits {
67 u32 mask; 67 u32 mask;
68 const char *set; 68 const char *set;
69 const char *unset; 69 const char *unset;
70 }; 70 };
71 #define BIT(m, s, u) { .mask = m, .set = s, .unset = u } 71 #define BIT(m, s, u) { .mask = m, .set = s, .unset = u }
72 72
73 static inline void 73 static inline void
74 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val) 74 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
75 { 75 {
76 printk("%s %08x: ", prefix, val); 76 printk("%s %08x: ", prefix, val);
77 while (num--) { 77 while (num--) {
78 const char *str = val & bits->mask ? bits->set : bits->unset; 78 const char *str = val & bits->mask ? bits->set : bits->unset;
79 if (str) 79 if (str)
80 printk("%s ", str); 80 printk("%s ", str);
81 bits++; 81 bits++;
82 } 82 }
83 } 83 }
84 84
85 static const struct bits isr_bits[] = { 85 static const struct bits isr_bits[] = {
86 BIT(ISR_RWM, "RX", "TX"), 86 BIT(ISR_RWM, "RX", "TX"),
87 BIT(ISR_ACKNAK, "NAK", "ACK"), 87 BIT(ISR_ACKNAK, "NAK", "ACK"),
88 BIT(ISR_UB, "Bsy", "Rdy"), 88 BIT(ISR_UB, "Bsy", "Rdy"),
89 BIT(ISR_IBB, "BusBsy", "BusRdy"), 89 BIT(ISR_IBB, "BusBsy", "BusRdy"),
90 BIT(ISR_SSD, "SlaveStop", NULL), 90 BIT(ISR_SSD, "SlaveStop", NULL),
91 BIT(ISR_ALD, "ALD", NULL), 91 BIT(ISR_ALD, "ALD", NULL),
92 BIT(ISR_ITE, "TxEmpty", NULL), 92 BIT(ISR_ITE, "TxEmpty", NULL),
93 BIT(ISR_IRF, "RxFull", NULL), 93 BIT(ISR_IRF, "RxFull", NULL),
94 BIT(ISR_GCAD, "GenCall", NULL), 94 BIT(ISR_GCAD, "GenCall", NULL),
95 BIT(ISR_SAD, "SlaveAddr", NULL), 95 BIT(ISR_SAD, "SlaveAddr", NULL),
96 BIT(ISR_BED, "BusErr", NULL), 96 BIT(ISR_BED, "BusErr", NULL),
97 }; 97 };
98 98
99 static void decode_ISR(unsigned int val) 99 static void decode_ISR(unsigned int val)
100 { 100 {
101 decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val); 101 decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
102 printk("\n"); 102 printk("\n");
103 } 103 }
104 104
105 static const struct bits icr_bits[] = { 105 static const struct bits icr_bits[] = {
106 BIT(ICR_START, "START", NULL), 106 BIT(ICR_START, "START", NULL),
107 BIT(ICR_STOP, "STOP", NULL), 107 BIT(ICR_STOP, "STOP", NULL),
108 BIT(ICR_ACKNAK, "ACKNAK", NULL), 108 BIT(ICR_ACKNAK, "ACKNAK", NULL),
109 BIT(ICR_TB, "TB", NULL), 109 BIT(ICR_TB, "TB", NULL),
110 BIT(ICR_MA, "MA", NULL), 110 BIT(ICR_MA, "MA", NULL),
111 BIT(ICR_SCLE, "SCLE", "scle"), 111 BIT(ICR_SCLE, "SCLE", "scle"),
112 BIT(ICR_IUE, "IUE", "iue"), 112 BIT(ICR_IUE, "IUE", "iue"),
113 BIT(ICR_GCD, "GCD", NULL), 113 BIT(ICR_GCD, "GCD", NULL),
114 BIT(ICR_ITEIE, "ITEIE", NULL), 114 BIT(ICR_ITEIE, "ITEIE", NULL),
115 BIT(ICR_IRFIE, "IRFIE", NULL), 115 BIT(ICR_IRFIE, "IRFIE", NULL),
116 BIT(ICR_BEIE, "BEIE", NULL), 116 BIT(ICR_BEIE, "BEIE", NULL),
117 BIT(ICR_SSDIE, "SSDIE", NULL), 117 BIT(ICR_SSDIE, "SSDIE", NULL),
118 BIT(ICR_ALDIE, "ALDIE", NULL), 118 BIT(ICR_ALDIE, "ALDIE", NULL),
119 BIT(ICR_SADIE, "SADIE", NULL), 119 BIT(ICR_SADIE, "SADIE", NULL),
120 BIT(ICR_UR, "UR", "ur"), 120 BIT(ICR_UR, "UR", "ur"),
121 }; 121 };
122 122
123 static void decode_ICR(unsigned int val) 123 static void decode_ICR(unsigned int val)
124 { 124 {
125 decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val); 125 decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
126 printk("\n"); 126 printk("\n");
127 } 127 }
128 128
129 static unsigned int i2c_debug = DEBUG; 129 static unsigned int i2c_debug = DEBUG;
130 130
131 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname) 131 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
132 { 132 {
133 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno, ISR, ICR, IBMR); 133 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno, ISR, ICR, IBMR);
134 } 134 }
135 135
136 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __FUNCTION__) 136 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __FUNCTION__)
137 #else 137 #else
138 #define i2c_debug 0 138 #define i2c_debug 0
139 139
140 #define show_state(i2c) do { } while (0) 140 #define show_state(i2c) do { } while (0)
141 #define decode_ISR(val) do { } while (0) 141 #define decode_ISR(val) do { } while (0)
142 #define decode_ICR(val) do { } while (0) 142 #define decode_ICR(val) do { } while (0)
143 #endif 143 #endif
144 144
145 #define eedbg(lvl, x...) do { if ((lvl) < 1) { printk(KERN_DEBUG "" x); } } while(0) 145 #define eedbg(lvl, x...) do { if ((lvl) < 1) { printk(KERN_DEBUG "" x); } } while(0)
146 146
147 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret); 147 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
148 148
149 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why) 149 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
150 { 150 {
151 unsigned int i; 151 unsigned int i;
152 printk("i2c: error: %s\n", why); 152 printk("i2c: error: %s\n", why);
153 printk("i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n", 153 printk("i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
154 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr); 154 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
155 printk("i2c: ICR: %08x ISR: %08x\n" 155 printk("i2c: ICR: %08x ISR: %08x\n"
156 "i2c: log: ", ICR, ISR); 156 "i2c: log: ", ICR, ISR);
157 for (i = 0; i < i2c->irqlogidx; i++) 157 for (i = 0; i < i2c->irqlogidx; i++)
158 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]); 158 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
159 printk("\n"); 159 printk("\n");
160 } 160 }
161 161
162 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c) 162 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
163 { 163 {
164 return !(ICR & ICR_SCLE); 164 return !(ICR & ICR_SCLE);
165 } 165 }
166 166
167 static void i2c_pxa_abort(struct pxa_i2c *i2c) 167 static void i2c_pxa_abort(struct pxa_i2c *i2c)
168 { 168 {
169 unsigned long timeout = jiffies + HZ/4; 169 unsigned long timeout = jiffies + HZ/4;
170 170
171 if (i2c_pxa_is_slavemode(i2c)) { 171 if (i2c_pxa_is_slavemode(i2c)) {
172 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__); 172 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
173 return; 173 return;
174 } 174 }
175 175
176 while (time_before(jiffies, timeout) && (IBMR & 0x1) == 0) { 176 while (time_before(jiffies, timeout) && (IBMR & 0x1) == 0) {
177 unsigned long icr = ICR; 177 unsigned long icr = ICR;
178 178
179 icr &= ~ICR_START; 179 icr &= ~ICR_START;
180 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB; 180 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
181 181
182 ICR = icr; 182 ICR = icr;
183 183
184 show_state(i2c); 184 show_state(i2c);
185 185
186 msleep(1); 186 msleep(1);
187 } 187 }
188 188
189 ICR &= ~(ICR_MA | ICR_START | ICR_STOP); 189 ICR &= ~(ICR_MA | ICR_START | ICR_STOP);
190 } 190 }
191 191
192 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c) 192 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
193 { 193 {
194 int timeout = DEF_TIMEOUT; 194 int timeout = DEF_TIMEOUT;
195 195
196 while (timeout-- && ISR & (ISR_IBB | ISR_UB)) { 196 while (timeout-- && ISR & (ISR_IBB | ISR_UB)) {
197 if ((ISR & ISR_SAD) != 0) 197 if ((ISR & ISR_SAD) != 0)
198 timeout += 4; 198 timeout += 4;
199 199
200 msleep(2); 200 msleep(2);
201 show_state(i2c); 201 show_state(i2c);
202 } 202 }
203 203
204 if (timeout <= 0) 204 if (timeout <= 0)
205 show_state(i2c); 205 show_state(i2c);
206 206
207 return timeout <= 0 ? I2C_RETRY : 0; 207 return timeout <= 0 ? I2C_RETRY : 0;
208 } 208 }
209 209
210 static int i2c_pxa_wait_master(struct pxa_i2c *i2c) 210 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
211 { 211 {
212 unsigned long timeout = jiffies + HZ*4; 212 unsigned long timeout = jiffies + HZ*4;
213 213
214 while (time_before(jiffies, timeout)) { 214 while (time_before(jiffies, timeout)) {
215 if (i2c_debug > 1) 215 if (i2c_debug > 1)
216 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n", 216 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
217 __func__, (long)jiffies, ISR, ICR, IBMR); 217 __func__, (long)jiffies, ISR, ICR, IBMR);
218 218
219 if (ISR & ISR_SAD) { 219 if (ISR & ISR_SAD) {
220 if (i2c_debug > 0) 220 if (i2c_debug > 0)
221 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__); 221 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
222 goto out; 222 goto out;
223 } 223 }
224 224
225 /* wait for unit and bus being not busy, and we also do a 225 /* wait for unit and bus being not busy, and we also do a
226 * quick check of the i2c lines themselves to ensure they've 226 * quick check of the i2c lines themselves to ensure they've
227 * gone high... 227 * gone high...
228 */ 228 */
229 if ((ISR & (ISR_UB | ISR_IBB)) == 0 && IBMR == 3) { 229 if ((ISR & (ISR_UB | ISR_IBB)) == 0 && IBMR == 3) {
230 if (i2c_debug > 0) 230 if (i2c_debug > 0)
231 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__); 231 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
232 return 1; 232 return 1;
233 } 233 }
234 234
235 msleep(1); 235 msleep(1);
236 } 236 }
237 237
238 if (i2c_debug > 0) 238 if (i2c_debug > 0)
239 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__); 239 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
240 out: 240 out:
241 return 0; 241 return 0;
242 } 242 }
243 243
244 static int i2c_pxa_set_master(struct pxa_i2c *i2c) 244 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
245 { 245 {
246 if (i2c_debug) 246 if (i2c_debug)
247 dev_dbg(&i2c->adap.dev, "setting to bus master\n"); 247 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
248 248
249 if ((ISR & (ISR_UB | ISR_IBB)) != 0) { 249 if ((ISR & (ISR_UB | ISR_IBB)) != 0) {
250 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__); 250 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
251 if (!i2c_pxa_wait_master(i2c)) { 251 if (!i2c_pxa_wait_master(i2c)) {
252 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__); 252 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
253 return I2C_RETRY; 253 return I2C_RETRY;
254 } 254 }
255 } 255 }
256 256
257 ICR |= ICR_SCLE; 257 ICR |= ICR_SCLE;
258 return 0; 258 return 0;
259 } 259 }
260 260
261 #ifdef CONFIG_I2C_PXA_SLAVE 261 #ifdef CONFIG_I2C_PXA_SLAVE
262 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c) 262 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
263 { 263 {
264 unsigned long timeout = jiffies + HZ*1; 264 unsigned long timeout = jiffies + HZ*1;
265 265
266 /* wait for stop */ 266 /* wait for stop */
267 267
268 show_state(i2c); 268 show_state(i2c);
269 269
270 while (time_before(jiffies, timeout)) { 270 while (time_before(jiffies, timeout)) {
271 if (i2c_debug > 1) 271 if (i2c_debug > 1)
272 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n", 272 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
273 __func__, (long)jiffies, ISR, ICR, IBMR); 273 __func__, (long)jiffies, ISR, ICR, IBMR);
274 274
275 if ((ISR & (ISR_UB|ISR_IBB|ISR_SAD)) == ISR_SAD || 275 if ((ISR & (ISR_UB|ISR_IBB)) == 0 ||
276 (ISR & ISR_SAD) != 0 ||
276 (ICR & ICR_SCLE) == 0) { 277 (ICR & ICR_SCLE) == 0) {
277 if (i2c_debug > 1) 278 if (i2c_debug > 1)
278 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__); 279 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
279 return 1; 280 return 1;
280 } 281 }
281 282
282 msleep(1); 283 msleep(1);
283 } 284 }
284 285
285 if (i2c_debug > 0) 286 if (i2c_debug > 0)
286 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__); 287 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
287 return 0; 288 return 0;
288 } 289 }
289 290
290 /* 291 /*
291 * clear the hold on the bus, and take of anything else 292 * clear the hold on the bus, and take of anything else
292 * that has been configured 293 * that has been configured
293 */ 294 */
294 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode) 295 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
295 { 296 {
296 show_state(i2c); 297 show_state(i2c);
297 298
298 if (errcode < 0) { 299 if (errcode < 0) {
299 udelay(100); /* simple delay */ 300 udelay(100); /* simple delay */
300 } else { 301 } else {
301 /* we need to wait for the stop condition to end */ 302 /* we need to wait for the stop condition to end */
302 303
303 /* if we where in stop, then clear... */ 304 /* if we where in stop, then clear... */
304 if (ICR & ICR_STOP) { 305 if (ICR & ICR_STOP) {
305 udelay(100); 306 udelay(100);
306 ICR &= ~ICR_STOP; 307 ICR &= ~ICR_STOP;
307 } 308 }
308 309
309 if (!i2c_pxa_wait_slave(i2c)) { 310 if (!i2c_pxa_wait_slave(i2c)) {
310 dev_err(&i2c->adap.dev, "%s: wait timedout\n", 311 dev_err(&i2c->adap.dev, "%s: wait timedout\n",
311 __func__); 312 __func__);
312 return; 313 return;
313 } 314 }
314 } 315 }
315 316
316 ICR &= ~(ICR_STOP|ICR_ACKNAK|ICR_MA); 317 ICR &= ~(ICR_STOP|ICR_ACKNAK|ICR_MA);
317 ICR &= ~ICR_SCLE; 318 ICR &= ~ICR_SCLE;
318 319
319 if (i2c_debug) { 320 if (i2c_debug) {
320 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", ICR, ISR); 321 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", ICR, ISR);
321 decode_ICR(ICR); 322 decode_ICR(ICR);
322 } 323 }
323 } 324 }
324 #else 325 #else
325 #define i2c_pxa_set_slave(i2c, err) do { } while (0) 326 #define i2c_pxa_set_slave(i2c, err) do { } while (0)
326 #endif 327 #endif
327 328
328 static void i2c_pxa_reset(struct pxa_i2c *i2c) 329 static void i2c_pxa_reset(struct pxa_i2c *i2c)
329 { 330 {
330 pr_debug("Resetting I2C Controller Unit\n"); 331 pr_debug("Resetting I2C Controller Unit\n");
331 332
332 /* abort any transfer currently under way */ 333 /* abort any transfer currently under way */
333 i2c_pxa_abort(i2c); 334 i2c_pxa_abort(i2c);
334 335
335 /* reset according to 9.8 */ 336 /* reset according to 9.8 */
336 ICR = ICR_UR; 337 ICR = ICR_UR;
337 ISR = I2C_ISR_INIT; 338 ISR = I2C_ISR_INIT;
338 ICR &= ~ICR_UR; 339 ICR &= ~ICR_UR;
339 340
340 ISAR = i2c->slave_addr; 341 ISAR = i2c->slave_addr;
341 342
342 /* set control register values */ 343 /* set control register values */
343 ICR = I2C_ICR_INIT; 344 ICR = I2C_ICR_INIT;
344 345
345 #ifdef CONFIG_I2C_PXA_SLAVE 346 #ifdef CONFIG_I2C_PXA_SLAVE
346 dev_info(&i2c->adap.dev, "Enabling slave mode\n"); 347 dev_info(&i2c->adap.dev, "Enabling slave mode\n");
347 ICR |= ICR_SADIE | ICR_ALDIE | ICR_SSDIE; 348 ICR |= ICR_SADIE | ICR_ALDIE | ICR_SSDIE;
348 #endif 349 #endif
349 350
350 i2c_pxa_set_slave(i2c, 0); 351 i2c_pxa_set_slave(i2c, 0);
351 352
352 /* enable unit */ 353 /* enable unit */
353 ICR |= ICR_IUE; 354 ICR |= ICR_IUE;
354 udelay(100); 355 udelay(100);
355 } 356 }
356 357
357 358
358 #ifdef CONFIG_I2C_PXA_SLAVE 359 #ifdef CONFIG_I2C_PXA_SLAVE
359 /* 360 /*
360 * I2C EEPROM emulation. 361 * I2C EEPROM emulation.
361 */ 362 */
362 static struct i2c_eeprom_emu eeprom = { 363 static struct i2c_eeprom_emu eeprom = {
363 .size = I2C_EEPROM_EMU_SIZE, 364 .size = I2C_EEPROM_EMU_SIZE,
364 .watch = LIST_HEAD_INIT(eeprom.watch), 365 .watch = LIST_HEAD_INIT(eeprom.watch),
365 }; 366 };
366 367
367 struct i2c_eeprom_emu *i2c_pxa_get_eeprom(void) 368 struct i2c_eeprom_emu *i2c_pxa_get_eeprom(void)
368 { 369 {
369 return &eeprom; 370 return &eeprom;
370 } 371 }
371 372
372 int i2c_eeprom_emu_addwatcher(struct i2c_eeprom_emu *emu, void *data, 373 int i2c_eeprom_emu_addwatcher(struct i2c_eeprom_emu *emu, void *data,
373 unsigned int addr, unsigned int size, 374 unsigned int addr, unsigned int size,
374 struct i2c_eeprom_emu_watcher *watcher) 375 struct i2c_eeprom_emu_watcher *watcher)
375 { 376 {
376 struct i2c_eeprom_emu_watch *watch; 377 struct i2c_eeprom_emu_watch *watch;
377 unsigned long flags; 378 unsigned long flags;
378 379
379 if (addr + size > emu->size) 380 if (addr + size > emu->size)
380 return -EINVAL; 381 return -EINVAL;
381 382
382 watch = kmalloc(sizeof(struct i2c_eeprom_emu_watch), GFP_KERNEL); 383 watch = kmalloc(sizeof(struct i2c_eeprom_emu_watch), GFP_KERNEL);
383 if (watch) { 384 if (watch) {
384 watch->start = addr; 385 watch->start = addr;
385 watch->end = addr + size - 1; 386 watch->end = addr + size - 1;
386 watch->ops = watcher; 387 watch->ops = watcher;
387 watch->data = data; 388 watch->data = data;
388 389
389 local_irq_save(flags); 390 local_irq_save(flags);
390 list_add(&watch->node, &emu->watch); 391 list_add(&watch->node, &emu->watch);
391 local_irq_restore(flags); 392 local_irq_restore(flags);
392 } 393 }
393 394
394 return watch ? 0 : -ENOMEM; 395 return watch ? 0 : -ENOMEM;
395 } 396 }
396 397
397 void i2c_eeprom_emu_delwatcher(struct i2c_eeprom_emu *emu, void *data, 398 void i2c_eeprom_emu_delwatcher(struct i2c_eeprom_emu *emu, void *data,
398 struct i2c_eeprom_emu_watcher *watcher) 399 struct i2c_eeprom_emu_watcher *watcher)
399 { 400 {
400 struct i2c_eeprom_emu_watch *watch, *n; 401 struct i2c_eeprom_emu_watch *watch, *n;
401 unsigned long flags; 402 unsigned long flags;
402 403
403 list_for_each_entry_safe(watch, n, &emu->watch, node) { 404 list_for_each_entry_safe(watch, n, &emu->watch, node) {
404 if (watch->ops == watcher && watch->data == data) { 405 if (watch->ops == watcher && watch->data == data) {
405 local_irq_save(flags); 406 local_irq_save(flags);
406 list_del(&watch->node); 407 list_del(&watch->node);
407 local_irq_restore(flags); 408 local_irq_restore(flags);
408 kfree(watch); 409 kfree(watch);
409 } 410 }
410 } 411 }
411 } 412 }
412 413
413 static void i2c_eeprom_emu_event(void *ptr, i2c_slave_event_t event) 414 static void i2c_eeprom_emu_event(void *ptr, i2c_slave_event_t event)
414 { 415 {
415 struct i2c_eeprom_emu *emu = ptr; 416 struct i2c_eeprom_emu *emu = ptr;
416 417
417 eedbg(3, "i2c_eeprom_emu_event: %d\n", event); 418 eedbg(3, "i2c_eeprom_emu_event: %d\n", event);
418 419
419 switch (event) { 420 switch (event) {
420 case I2C_SLAVE_EVENT_START_WRITE: 421 case I2C_SLAVE_EVENT_START_WRITE:
421 emu->seen_start = 1; 422 emu->seen_start = 1;
422 eedbg(2, "i2c_eeprom: write initiated\n"); 423 eedbg(2, "i2c_eeprom: write initiated\n");
423 break; 424 break;
424 425
425 case I2C_SLAVE_EVENT_START_READ: 426 case I2C_SLAVE_EVENT_START_READ:
426 emu->seen_start = 0; 427 emu->seen_start = 0;
427 eedbg(2, "i2c_eeprom: read initiated\n"); 428 eedbg(2, "i2c_eeprom: read initiated\n");
428 break; 429 break;
429 430
430 case I2C_SLAVE_EVENT_STOP: 431 case I2C_SLAVE_EVENT_STOP:
431 emu->seen_start = 0; 432 emu->seen_start = 0;
432 eedbg(2, "i2c_eeprom: received stop\n"); 433 eedbg(2, "i2c_eeprom: received stop\n");
433 break; 434 break;
434 435
435 default: 436 default:
436 eedbg(0, "i2c_eeprom: unhandled event\n"); 437 eedbg(0, "i2c_eeprom: unhandled event\n");
437 break; 438 break;
438 } 439 }
439 } 440 }
440 441
441 static int i2c_eeprom_emu_read(void *ptr) 442 static int i2c_eeprom_emu_read(void *ptr)
442 { 443 {
443 struct i2c_eeprom_emu *emu = ptr; 444 struct i2c_eeprom_emu *emu = ptr;
444 int ret; 445 int ret;
445 446
446 ret = emu->bytes[emu->ptr]; 447 ret = emu->bytes[emu->ptr];
447 emu->ptr = (emu->ptr + 1) % emu->size; 448 emu->ptr = (emu->ptr + 1) % emu->size;
448 449
449 return ret; 450 return ret;
450 } 451 }
451 452
452 static void i2c_eeprom_emu_write(void *ptr, unsigned int val) 453 static void i2c_eeprom_emu_write(void *ptr, unsigned int val)
453 { 454 {
454 struct i2c_eeprom_emu *emu = ptr; 455 struct i2c_eeprom_emu *emu = ptr;
455 struct i2c_eeprom_emu_watch *watch; 456 struct i2c_eeprom_emu_watch *watch;
456 457
457 if (emu->seen_start != 0) { 458 if (emu->seen_start != 0) {
458 eedbg(2, "i2c_eeprom_emu_write: setting ptr %02x\n", val); 459 eedbg(2, "i2c_eeprom_emu_write: setting ptr %02x\n", val);
459 emu->ptr = val; 460 emu->ptr = val;
460 emu->seen_start = 0; 461 emu->seen_start = 0;
461 return; 462 return;
462 } 463 }
463 464
464 emu->bytes[emu->ptr] = val; 465 emu->bytes[emu->ptr] = val;
465 466
466 eedbg(1, "i2c_eeprom_emu_write: ptr=0x%02x, val=0x%02x\n", 467 eedbg(1, "i2c_eeprom_emu_write: ptr=0x%02x, val=0x%02x\n",
467 emu->ptr, val); 468 emu->ptr, val);
468 469
469 list_for_each_entry(watch, &emu->watch, node) { 470 list_for_each_entry(watch, &emu->watch, node) {
470 if (!watch->ops || !watch->ops->write) 471 if (!watch->ops || !watch->ops->write)
471 continue; 472 continue;
472 if (watch->start <= emu->ptr && watch->end >= emu->ptr) 473 if (watch->start <= emu->ptr && watch->end >= emu->ptr)
473 watch->ops->write(watch->data, emu->ptr, val); 474 watch->ops->write(watch->data, emu->ptr, val);
474 } 475 }
475 476
476 emu->ptr = (emu->ptr + 1) % emu->size; 477 emu->ptr = (emu->ptr + 1) % emu->size;
477 } 478 }
478 479
479 struct i2c_slave_client eeprom_client = { 480 struct i2c_slave_client eeprom_client = {
480 .data = &eeprom, 481 .data = &eeprom,
481 .event = i2c_eeprom_emu_event, 482 .event = i2c_eeprom_emu_event,
482 .read = i2c_eeprom_emu_read, 483 .read = i2c_eeprom_emu_read,
483 .write = i2c_eeprom_emu_write 484 .write = i2c_eeprom_emu_write
484 }; 485 };
485 486
486 /* 487 /*
487 * PXA I2C Slave mode 488 * PXA I2C Slave mode
488 */ 489 */
489 490
490 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr) 491 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
491 { 492 {
492 if (isr & ISR_BED) { 493 if (isr & ISR_BED) {
493 /* what should we do here? */ 494 /* what should we do here? */
494 } else { 495 } else {
495 int ret = i2c->slave->read(i2c->slave->data); 496 int ret = 0;
497
498 if (i2c->slave != NULL)
499 ret = i2c->slave->read(i2c->slave->data);
496 500
497 IDBR = ret; 501 IDBR = ret;
498 ICR |= ICR_TB; /* allow next byte */ 502 ICR |= ICR_TB; /* allow next byte */
499 } 503 }
500 } 504 }
501 505
502 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) 506 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
503 { 507 {
504 unsigned int byte = IDBR; 508 unsigned int byte = IDBR;
505 509
506 if (i2c->slave != NULL) 510 if (i2c->slave != NULL)
507 i2c->slave->write(i2c->slave->data, byte); 511 i2c->slave->write(i2c->slave->data, byte);
508 512
509 ICR |= ICR_TB; 513 ICR |= ICR_TB;
510 } 514 }
511 515
512 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) 516 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
513 { 517 {
514 int timeout; 518 int timeout;
515 519
516 if (i2c_debug > 0) 520 if (i2c_debug > 0)
517 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n", 521 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
518 (isr & ISR_RWM) ? 'r' : 't'); 522 (isr & ISR_RWM) ? 'r' : 't');
519 523
520 if (i2c->slave != NULL) 524 if (i2c->slave != NULL)
521 i2c->slave->event(i2c->slave->data, 525 i2c->slave->event(i2c->slave->data,
522 (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE); 526 (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
523 527
524 /* 528 /*
525 * slave could interrupt in the middle of us generating a 529 * slave could interrupt in the middle of us generating a
526 * start condition... if this happens, we'd better back off 530 * start condition... if this happens, we'd better back off
527 * and stop holding the poor thing up 531 * and stop holding the poor thing up
528 */ 532 */
529 ICR &= ~(ICR_START|ICR_STOP); 533 ICR &= ~(ICR_START|ICR_STOP);
530 ICR |= ICR_TB; 534 ICR |= ICR_TB;
531 535
532 timeout = 0x10000; 536 timeout = 0x10000;
533 537
534 while (1) { 538 while (1) {
535 if ((IBMR & 2) == 2) 539 if ((IBMR & 2) == 2)
536 break; 540 break;
537 541
538 timeout--; 542 timeout--;
539 543
540 if (timeout <= 0) { 544 if (timeout <= 0) {
541 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n"); 545 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
542 break; 546 break;
543 } 547 }
544 } 548 }
545 549
546 ICR &= ~ICR_SCLE; 550 ICR &= ~ICR_SCLE;
547 } 551 }
548 552
549 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) 553 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
550 { 554 {
551 if (i2c_debug > 2) 555 if (i2c_debug > 2)
552 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n"); 556 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
553 557
554 if (i2c->slave != NULL) 558 if (i2c->slave != NULL)
555 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP); 559 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
556 560
557 if (i2c_debug > 2) 561 if (i2c_debug > 2)
558 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n"); 562 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
559 563
560 /* 564 /*
561 * If we have a master-mode message waiting, 565 * If we have a master-mode message waiting,
562 * kick it off now that the slave has completed. 566 * kick it off now that the slave has completed.
563 */ 567 */
564 if (i2c->msg) 568 if (i2c->msg)
565 i2c_pxa_master_complete(i2c, I2C_RETRY); 569 i2c_pxa_master_complete(i2c, I2C_RETRY);
566 } 570 }
567 #else 571 #else
568 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr) 572 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
569 { 573 {
570 if (isr & ISR_BED) { 574 if (isr & ISR_BED) {
571 /* what should we do here? */ 575 /* what should we do here? */
572 } else { 576 } else {
573 IDBR = 0; 577 IDBR = 0;
574 ICR |= ICR_TB; 578 ICR |= ICR_TB;
575 } 579 }
576 } 580 }
577 581
578 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) 582 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
579 { 583 {
580 ICR |= ICR_TB | ICR_ACKNAK; 584 ICR |= ICR_TB | ICR_ACKNAK;
581 } 585 }
582 586
583 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) 587 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
584 { 588 {
585 int timeout; 589 int timeout;
586 590
587 /* 591 /*
588 * slave could interrupt in the middle of us generating a 592 * slave could interrupt in the middle of us generating a
589 * start condition... if this happens, we'd better back off 593 * start condition... if this happens, we'd better back off
590 * and stop holding the poor thing up 594 * and stop holding the poor thing up
591 */ 595 */
592 ICR &= ~(ICR_START|ICR_STOP); 596 ICR &= ~(ICR_START|ICR_STOP);
593 ICR |= ICR_TB | ICR_ACKNAK; 597 ICR |= ICR_TB | ICR_ACKNAK;
594 598
595 timeout = 0x10000; 599 timeout = 0x10000;
596 600
597 while (1) { 601 while (1) {
598 if ((IBMR & 2) == 2) 602 if ((IBMR & 2) == 2)
599 break; 603 break;
600 604
601 timeout--; 605 timeout--;
602 606
603 if (timeout <= 0) { 607 if (timeout <= 0) {
604 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n"); 608 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
605 break; 609 break;
606 } 610 }
607 } 611 }
608 612
609 ICR &= ~ICR_SCLE; 613 ICR &= ~ICR_SCLE;
610 } 614 }
611 615
612 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) 616 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
613 { 617 {
614 if (i2c->msg) 618 if (i2c->msg)
615 i2c_pxa_master_complete(i2c, I2C_RETRY); 619 i2c_pxa_master_complete(i2c, I2C_RETRY);
616 } 620 }
617 #endif 621 #endif
618 622
619 /* 623 /*
620 * PXA I2C Master mode 624 * PXA I2C Master mode
621 */ 625 */
622 626
623 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg) 627 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
624 { 628 {
625 unsigned int addr = (msg->addr & 0x7f) << 1; 629 unsigned int addr = (msg->addr & 0x7f) << 1;
626 630
627 if (msg->flags & I2C_M_RD) 631 if (msg->flags & I2C_M_RD)
628 addr |= 1; 632 addr |= 1;
629 633
630 return addr; 634 return addr;
631 } 635 }
632 636
633 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c) 637 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
634 { 638 {
635 u32 icr; 639 u32 icr;
636 640
637 /* 641 /*
638 * Step 1: target slave address into IDBR 642 * Step 1: target slave address into IDBR
639 */ 643 */
640 IDBR = i2c_pxa_addr_byte(i2c->msg); 644 IDBR = i2c_pxa_addr_byte(i2c->msg);
641 645
642 /* 646 /*
643 * Step 2: initiate the write. 647 * Step 2: initiate the write.
644 */ 648 */
645 icr = ICR & ~(ICR_STOP | ICR_ALDIE); 649 icr = ICR & ~(ICR_STOP | ICR_ALDIE);
646 ICR = icr | ICR_START | ICR_TB; 650 ICR = icr | ICR_START | ICR_TB;
647 } 651 }
648 652
649 /* 653 /*
650 * We are protected by the adapter bus mutex. 654 * We are protected by the adapter bus mutex.
651 */ 655 */
652 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num) 656 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
653 { 657 {
654 long timeout; 658 long timeout;
655 int ret; 659 int ret;
656 660
657 /* 661 /*
658 * Wait for the bus to become free. 662 * Wait for the bus to become free.
659 */ 663 */
660 ret = i2c_pxa_wait_bus_not_busy(i2c); 664 ret = i2c_pxa_wait_bus_not_busy(i2c);
661 if (ret) { 665 if (ret) {
662 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n"); 666 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
663 goto out; 667 goto out;
664 } 668 }
665 669
666 /* 670 /*
667 * Set master mode. 671 * Set master mode.
668 */ 672 */
669 ret = i2c_pxa_set_master(i2c); 673 ret = i2c_pxa_set_master(i2c);
670 if (ret) { 674 if (ret) {
671 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret); 675 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
672 goto out; 676 goto out;
673 } 677 }
674 678
675 spin_lock_irq(&i2c->lock); 679 spin_lock_irq(&i2c->lock);
676 680
677 i2c->msg = msg; 681 i2c->msg = msg;
678 i2c->msg_num = num; 682 i2c->msg_num = num;
679 i2c->msg_idx = 0; 683 i2c->msg_idx = 0;
680 i2c->msg_ptr = 0; 684 i2c->msg_ptr = 0;
681 i2c->irqlogidx = 0; 685 i2c->irqlogidx = 0;
682 686
683 i2c_pxa_start_message(i2c); 687 i2c_pxa_start_message(i2c);
684 688
685 spin_unlock_irq(&i2c->lock); 689 spin_unlock_irq(&i2c->lock);
686 690
687 /* 691 /*
688 * The rest of the processing occurs in the interrupt handler. 692 * The rest of the processing occurs in the interrupt handler.
689 */ 693 */
690 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); 694 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
691 695
692 /* 696 /*
693 * We place the return code in i2c->msg_idx. 697 * We place the return code in i2c->msg_idx.
694 */ 698 */
695 ret = i2c->msg_idx; 699 ret = i2c->msg_idx;
696 700
697 if (timeout == 0) 701 if (timeout == 0)
698 i2c_pxa_scream_blue_murder(i2c, "timeout"); 702 i2c_pxa_scream_blue_murder(i2c, "timeout");
699 703
700 out: 704 out:
701 return ret; 705 return ret;
702 } 706 }
703 707
704 /* 708 /*
705 * i2c_pxa_master_complete - complete the message and wake up. 709 * i2c_pxa_master_complete - complete the message and wake up.
706 */ 710 */
707 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret) 711 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
708 { 712 {
709 i2c->msg_ptr = 0; 713 i2c->msg_ptr = 0;
710 i2c->msg = NULL; 714 i2c->msg = NULL;
711 i2c->msg_idx ++; 715 i2c->msg_idx ++;
712 i2c->msg_num = 0; 716 i2c->msg_num = 0;
713 if (ret) 717 if (ret)
714 i2c->msg_idx = ret; 718 i2c->msg_idx = ret;
715 wake_up(&i2c->wait); 719 wake_up(&i2c->wait);
716 } 720 }
717 721
718 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr) 722 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
719 { 723 {
720 u32 icr = ICR & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); 724 u32 icr = ICR & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
721 725
722 again: 726 again:
723 /* 727 /*
724 * If ISR_ALD is set, we lost arbitration. 728 * If ISR_ALD is set, we lost arbitration.
725 */ 729 */
726 if (isr & ISR_ALD) { 730 if (isr & ISR_ALD) {
727 /* 731 /*
728 * Do we need to do anything here? The PXA docs 732 * Do we need to do anything here? The PXA docs
729 * are vague about what happens. 733 * are vague about what happens.
730 */ 734 */
731 i2c_pxa_scream_blue_murder(i2c, "ALD set"); 735 i2c_pxa_scream_blue_murder(i2c, "ALD set");
732 736
733 /* 737 /*
734 * We ignore this error. We seem to see spurious ALDs 738 * We ignore this error. We seem to see spurious ALDs
735 * for seemingly no reason. If we handle them as I think 739 * for seemingly no reason. If we handle them as I think
736 * they should, we end up causing an I2C error, which 740 * they should, we end up causing an I2C error, which
737 * is painful for some systems. 741 * is painful for some systems.
738 */ 742 */
739 return; /* ignore */ 743 return; /* ignore */
740 } 744 }
741 745
742 if (isr & ISR_BED) { 746 if (isr & ISR_BED) {
743 int ret = BUS_ERROR; 747 int ret = BUS_ERROR;
744 748
745 /* 749 /*
746 * I2C bus error - either the device NAK'd us, or 750 * I2C bus error - either the device NAK'd us, or
747 * something more serious happened. If we were NAK'd 751 * something more serious happened. If we were NAK'd
748 * on the initial address phase, we can retry. 752 * on the initial address phase, we can retry.
749 */ 753 */
750 if (isr & ISR_ACKNAK) { 754 if (isr & ISR_ACKNAK) {
751 if (i2c->msg_ptr == 0 && i2c->msg_idx == 0) 755 if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
752 ret = I2C_RETRY; 756 ret = I2C_RETRY;
753 else 757 else
754 ret = XFER_NAKED; 758 ret = XFER_NAKED;
755 } 759 }
756 i2c_pxa_master_complete(i2c, ret); 760 i2c_pxa_master_complete(i2c, ret);
757 } else if (isr & ISR_RWM) { 761 } else if (isr & ISR_RWM) {
758 /* 762 /*
759 * Read mode. We have just sent the address byte, and 763 * Read mode. We have just sent the address byte, and
760 * now we must initiate the transfer. 764 * now we must initiate the transfer.
761 */ 765 */
762 if (i2c->msg_ptr == i2c->msg->len - 1 && 766 if (i2c->msg_ptr == i2c->msg->len - 1 &&
763 i2c->msg_idx == i2c->msg_num - 1) 767 i2c->msg_idx == i2c->msg_num - 1)
764 icr |= ICR_STOP | ICR_ACKNAK; 768 icr |= ICR_STOP | ICR_ACKNAK;
765 769
766 icr |= ICR_ALDIE | ICR_TB; 770 icr |= ICR_ALDIE | ICR_TB;
767 } else if (i2c->msg_ptr < i2c->msg->len) { 771 } else if (i2c->msg_ptr < i2c->msg->len) {
768 /* 772 /*
769 * Write mode. Write the next data byte. 773 * Write mode. Write the next data byte.
770 */ 774 */
771 IDBR = i2c->msg->buf[i2c->msg_ptr++]; 775 IDBR = i2c->msg->buf[i2c->msg_ptr++];
772 776
773 icr |= ICR_ALDIE | ICR_TB; 777 icr |= ICR_ALDIE | ICR_TB;
774 778
775 /* 779 /*
776 * If this is the last byte of the last message, send 780 * If this is the last byte of the last message, send
777 * a STOP. 781 * a STOP.
778 */ 782 */
779 if (i2c->msg_ptr == i2c->msg->len && 783 if (i2c->msg_ptr == i2c->msg->len &&
780 i2c->msg_idx == i2c->msg_num - 1) 784 i2c->msg_idx == i2c->msg_num - 1)
781 icr |= ICR_STOP; 785 icr |= ICR_STOP;
782 } else if (i2c->msg_idx < i2c->msg_num - 1) { 786 } else if (i2c->msg_idx < i2c->msg_num - 1) {
783 /* 787 /*
784 * Next segment of the message. 788 * Next segment of the message.
785 */ 789 */
786 i2c->msg_ptr = 0; 790 i2c->msg_ptr = 0;
787 i2c->msg_idx ++; 791 i2c->msg_idx ++;
788 i2c->msg++; 792 i2c->msg++;
789 793
790 /* 794 /*
791 * If we aren't doing a repeated start and address, 795 * If we aren't doing a repeated start and address,
792 * go back and try to send the next byte. Note that 796 * go back and try to send the next byte. Note that
793 * we do not support switching the R/W direction here. 797 * we do not support switching the R/W direction here.
794 */ 798 */
795 if (i2c->msg->flags & I2C_M_NOSTART) 799 if (i2c->msg->flags & I2C_M_NOSTART)
796 goto again; 800 goto again;
797 801
798 /* 802 /*
799 * Write the next address. 803 * Write the next address.
800 */ 804 */
801 IDBR = i2c_pxa_addr_byte(i2c->msg); 805 IDBR = i2c_pxa_addr_byte(i2c->msg);
802 806
803 /* 807 /*
804 * And trigger a repeated start, and send the byte. 808 * And trigger a repeated start, and send the byte.
805 */ 809 */
806 icr &= ~ICR_ALDIE; 810 icr &= ~ICR_ALDIE;
807 icr |= ICR_START | ICR_TB; 811 icr |= ICR_START | ICR_TB;
808 } else { 812 } else {
809 if (i2c->msg->len == 0) { 813 if (i2c->msg->len == 0) {
810 /* 814 /*
811 * Device probes have a message length of zero 815 * Device probes have a message length of zero
812 * and need the bus to be reset before it can 816 * and need the bus to be reset before it can
813 * be used again. 817 * be used again.
814 */ 818 */
815 i2c_pxa_reset(i2c); 819 i2c_pxa_reset(i2c);
816 } 820 }
817 i2c_pxa_master_complete(i2c, 0); 821 i2c_pxa_master_complete(i2c, 0);
818 } 822 }
819 823
820 i2c->icrlog[i2c->irqlogidx-1] = icr; 824 i2c->icrlog[i2c->irqlogidx-1] = icr;
821 825
822 ICR = icr; 826 ICR = icr;
823 show_state(i2c); 827 show_state(i2c);
824 } 828 }
825 829
826 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr) 830 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
827 { 831 {
828 u32 icr = ICR & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); 832 u32 icr = ICR & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
829 833
830 /* 834 /*
831 * Read the byte. 835 * Read the byte.
832 */ 836 */
833 i2c->msg->buf[i2c->msg_ptr++] = IDBR; 837 i2c->msg->buf[i2c->msg_ptr++] = IDBR;
834 838
835 if (i2c->msg_ptr < i2c->msg->len) { 839 if (i2c->msg_ptr < i2c->msg->len) {
836 /* 840 /*
837 * If this is the last byte of the last 841 * If this is the last byte of the last
838 * message, send a STOP. 842 * message, send a STOP.
839 */ 843 */
840 if (i2c->msg_ptr == i2c->msg->len - 1) 844 if (i2c->msg_ptr == i2c->msg->len - 1)
841 icr |= ICR_STOP | ICR_ACKNAK; 845 icr |= ICR_STOP | ICR_ACKNAK;
842 846
843 icr |= ICR_ALDIE | ICR_TB; 847 icr |= ICR_ALDIE | ICR_TB;
844 } else { 848 } else {
845 i2c_pxa_master_complete(i2c, 0); 849 i2c_pxa_master_complete(i2c, 0);
846 } 850 }
847 851
848 i2c->icrlog[i2c->irqlogidx-1] = icr; 852 i2c->icrlog[i2c->irqlogidx-1] = icr;
849 853
850 ICR = icr; 854 ICR = icr;
851 } 855 }
852 856
853 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id) 857 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
854 { 858 {
855 struct pxa_i2c *i2c = dev_id; 859 struct pxa_i2c *i2c = dev_id;
856 u32 isr = ISR; 860 u32 isr = ISR;
857 861
858 if (i2c_debug > 2 && 0) { 862 if (i2c_debug > 2 && 0) {
859 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n", 863 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
860 __func__, isr, ICR, IBMR); 864 __func__, isr, ICR, IBMR);
861 decode_ISR(isr); 865 decode_ISR(isr);
862 } 866 }
863 867
864 if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog)) 868 if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
865 i2c->isrlog[i2c->irqlogidx++] = isr; 869 i2c->isrlog[i2c->irqlogidx++] = isr;
866 870
867 show_state(i2c); 871 show_state(i2c);
868 872
869 /* 873 /*
870 * Always clear all pending IRQs. 874 * Always clear all pending IRQs.
871 */ 875 */
872 ISR = isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED); 876 ISR = isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED);
873 877
874 if (isr & ISR_SAD) 878 if (isr & ISR_SAD)
875 i2c_pxa_slave_start(i2c, isr); 879 i2c_pxa_slave_start(i2c, isr);
876 if (isr & ISR_SSD) 880 if (isr & ISR_SSD)
877 i2c_pxa_slave_stop(i2c); 881 i2c_pxa_slave_stop(i2c);
878 882
879 if (i2c_pxa_is_slavemode(i2c)) { 883 if (i2c_pxa_is_slavemode(i2c)) {
880 if (isr & ISR_ITE) 884 if (isr & ISR_ITE)
881 i2c_pxa_slave_txempty(i2c, isr); 885 i2c_pxa_slave_txempty(i2c, isr);
882 if (isr & ISR_IRF) 886 if (isr & ISR_IRF)
883 i2c_pxa_slave_rxfull(i2c, isr); 887 i2c_pxa_slave_rxfull(i2c, isr);
884 } else if (i2c->msg) { 888 } else if (i2c->msg) {
885 if (isr & ISR_ITE) 889 if (isr & ISR_ITE)
886 i2c_pxa_irq_txempty(i2c, isr); 890 i2c_pxa_irq_txempty(i2c, isr);
887 if (isr & ISR_IRF) 891 if (isr & ISR_IRF)
888 i2c_pxa_irq_rxfull(i2c, isr); 892 i2c_pxa_irq_rxfull(i2c, isr);
889 } else { 893 } else {
890 i2c_pxa_scream_blue_murder(i2c, "spurious irq"); 894 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
891 } 895 }
892 896
893 return IRQ_HANDLED; 897 return IRQ_HANDLED;
894 } 898 }
895 899
896 900
897 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 901 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
898 { 902 {
899 struct pxa_i2c *i2c = adap->algo_data; 903 struct pxa_i2c *i2c = adap->algo_data;
900 int ret, i; 904 int ret, i;
901 905
902 /* If the I2C controller is disabled we need to reset it (probably due 906 /* If the I2C controller is disabled we need to reset it (probably due
903 to a suspend/resume destroying state). We do this here as we can then 907 to a suspend/resume destroying state). We do this here as we can then
904 avoid worrying about resuming the controller before its users. */ 908 avoid worrying about resuming the controller before its users. */
905 if (!(ICR & ICR_IUE)) 909 if (!(ICR & ICR_IUE))
906 i2c_pxa_reset(i2c); 910 i2c_pxa_reset(i2c);
907 911
908 for (i = adap->retries; i >= 0; i--) { 912 for (i = adap->retries; i >= 0; i--) {
909 ret = i2c_pxa_do_xfer(i2c, msgs, num); 913 ret = i2c_pxa_do_xfer(i2c, msgs, num);
910 if (ret != I2C_RETRY) 914 if (ret != I2C_RETRY)
911 goto out; 915 goto out;
912 916
913 if (i2c_debug) 917 if (i2c_debug)
914 dev_dbg(&adap->dev, "Retrying transmission\n"); 918 dev_dbg(&adap->dev, "Retrying transmission\n");
915 udelay(100); 919 udelay(100);
916 } 920 }
917 i2c_pxa_scream_blue_murder(i2c, "exhausted retries"); 921 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
918 ret = -EREMOTEIO; 922 ret = -EREMOTEIO;
919 out: 923 out:
920 i2c_pxa_set_slave(i2c, ret); 924 i2c_pxa_set_slave(i2c, ret);
921 return ret; 925 return ret;
922 } 926 }
923 927
924 static u32 i2c_pxa_functionality(struct i2c_adapter *adap) 928 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
925 { 929 {
926 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 930 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
927 } 931 }
928 932
929 static const struct i2c_algorithm i2c_pxa_algorithm = { 933 static const struct i2c_algorithm i2c_pxa_algorithm = {
930 .master_xfer = i2c_pxa_xfer, 934 .master_xfer = i2c_pxa_xfer,
931 .functionality = i2c_pxa_functionality, 935 .functionality = i2c_pxa_functionality,
932 }; 936 };
933 937
934 static struct pxa_i2c i2c_pxa = { 938 static struct pxa_i2c i2c_pxa = {
935 .lock = SPIN_LOCK_UNLOCKED, 939 .lock = SPIN_LOCK_UNLOCKED,
936 .wait = __WAIT_QUEUE_HEAD_INITIALIZER(i2c_pxa.wait), 940 .wait = __WAIT_QUEUE_HEAD_INITIALIZER(i2c_pxa.wait),
937 .adap = { 941 .adap = {
938 .owner = THIS_MODULE, 942 .owner = THIS_MODULE,
939 .algo = &i2c_pxa_algorithm, 943 .algo = &i2c_pxa_algorithm,
940 .name = "pxa2xx-i2c", 944 .name = "pxa2xx-i2c",
941 .retries = 5, 945 .retries = 5,
942 }, 946 },
943 }; 947 };
944 948
945 static int i2c_pxa_probe(struct platform_device *dev) 949 static int i2c_pxa_probe(struct platform_device *dev)
946 { 950 {
947 struct pxa_i2c *i2c = &i2c_pxa; 951 struct pxa_i2c *i2c = &i2c_pxa;
948 #ifdef CONFIG_I2C_PXA_SLAVE 952 #ifdef CONFIG_I2C_PXA_SLAVE
949 struct i2c_pxa_platform_data *plat = dev->dev.platform_data; 953 struct i2c_pxa_platform_data *plat = dev->dev.platform_data;
950 #endif 954 #endif
951 int ret; 955 int ret;
952 956
953 #ifdef CONFIG_PXA27x 957 #ifdef CONFIG_PXA27x
954 pxa_gpio_mode(GPIO117_I2CSCL_MD); 958 pxa_gpio_mode(GPIO117_I2CSCL_MD);
955 pxa_gpio_mode(GPIO118_I2CSDA_MD); 959 pxa_gpio_mode(GPIO118_I2CSDA_MD);
956 udelay(100); 960 udelay(100);
957 #endif 961 #endif
958 962
959 i2c->slave_addr = I2C_PXA_SLAVE_ADDR; 963 i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
960 964
961 #ifdef CONFIG_I2C_PXA_SLAVE 965 #ifdef CONFIG_I2C_PXA_SLAVE
962 i2c->slave = &eeprom_client; 966 i2c->slave = &eeprom_client;
963 if (plat) { 967 if (plat) {
964 i2c->slave_addr = plat->slave_addr; 968 i2c->slave_addr = plat->slave_addr;
965 if (plat->slave) 969 if (plat->slave)
966 i2c->slave = plat->slave; 970 i2c->slave = plat->slave;
967 } 971 }
968 #endif 972 #endif
969 973
970 pxa_set_cken(CKEN14_I2C, 1); 974 pxa_set_cken(CKEN14_I2C, 1);
971 ret = request_irq(IRQ_I2C, i2c_pxa_handler, IRQF_DISABLED, 975 ret = request_irq(IRQ_I2C, i2c_pxa_handler, IRQF_DISABLED,
972 "pxa2xx-i2c", i2c); 976 "pxa2xx-i2c", i2c);
973 if (ret) 977 if (ret)
974 goto out; 978 goto out;
975 979
976 i2c_pxa_reset(i2c); 980 i2c_pxa_reset(i2c);
977 981
978 i2c->adap.algo_data = i2c; 982 i2c->adap.algo_data = i2c;
979 i2c->adap.dev.parent = &dev->dev; 983 i2c->adap.dev.parent = &dev->dev;
980 984
981 ret = i2c_add_adapter(&i2c->adap); 985 ret = i2c_add_adapter(&i2c->adap);
982 if (ret < 0) { 986 if (ret < 0) {
983 printk(KERN_INFO "I2C: Failed to add bus\n"); 987 printk(KERN_INFO "I2C: Failed to add bus\n");
984 goto err_irq; 988 goto err_irq;
985 } 989 }
986 990
987 platform_set_drvdata(dev, i2c); 991 platform_set_drvdata(dev, i2c);
988 992
989 #ifdef CONFIG_I2C_PXA_SLAVE 993 #ifdef CONFIG_I2C_PXA_SLAVE
990 printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n", 994 printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",
991 i2c->adap.dev.bus_id, i2c->slave_addr); 995 i2c->adap.dev.bus_id, i2c->slave_addr);
992 #else 996 #else
993 printk(KERN_INFO "I2C: %s: PXA I2C adapter\n", 997 printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",
994 i2c->adap.dev.bus_id); 998 i2c->adap.dev.bus_id);
995 #endif 999 #endif
996 return 0; 1000 return 0;
997 1001
998 err_irq: 1002 err_irq:
999 free_irq(IRQ_I2C, i2c); 1003 free_irq(IRQ_I2C, i2c);
1000 out: 1004 out:
1001 return ret; 1005 return ret;
1002 } 1006 }
1003 1007
1004 static int i2c_pxa_remove(struct platform_device *dev) 1008 static int i2c_pxa_remove(struct platform_device *dev)
1005 { 1009 {
1006 struct pxa_i2c *i2c = platform_get_drvdata(dev); 1010 struct pxa_i2c *i2c = platform_get_drvdata(dev);
1007 1011
1008 platform_set_drvdata(dev, NULL); 1012 platform_set_drvdata(dev, NULL);
1009 1013
1010 i2c_del_adapter(&i2c->adap); 1014 i2c_del_adapter(&i2c->adap);
1011 free_irq(IRQ_I2C, i2c); 1015 free_irq(IRQ_I2C, i2c);
1012 pxa_set_cken(CKEN14_I2C, 0); 1016 pxa_set_cken(CKEN14_I2C, 0);
1013 1017
1014 return 0; 1018 return 0;
1015 } 1019 }
1016 1020
1017 static struct platform_driver i2c_pxa_driver = { 1021 static struct platform_driver i2c_pxa_driver = {
1018 .probe = i2c_pxa_probe, 1022 .probe = i2c_pxa_probe,
1019 .remove = i2c_pxa_remove, 1023 .remove = i2c_pxa_remove,
1020 .driver = { 1024 .driver = {
1021 .name = "pxa2xx-i2c", 1025 .name = "pxa2xx-i2c",
1022 }, 1026 },
1023 }; 1027 };
1024 1028
1025 static int __init i2c_adap_pxa_init(void) 1029 static int __init i2c_adap_pxa_init(void)
1026 { 1030 {
1027 return platform_driver_register(&i2c_pxa_driver); 1031 return platform_driver_register(&i2c_pxa_driver);
1028 } 1032 }
1029 1033
1030 static void i2c_adap_pxa_exit(void) 1034 static void i2c_adap_pxa_exit(void)
1031 { 1035 {
1032 return platform_driver_unregister(&i2c_pxa_driver); 1036 return platform_driver_unregister(&i2c_pxa_driver);
1033 } 1037 }
1034 1038
1035 MODULE_LICENSE("GPL"); 1039 MODULE_LICENSE("GPL");
1036 1040
1037 module_init(i2c_adap_pxa_init); 1041 module_init(i2c_adap_pxa_init);
1038 module_exit(i2c_adap_pxa_exit); 1042 module_exit(i2c_adap_pxa_exit);
1039 1043