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Commit 863cb9bad8f992a9c171e90552045eac77808e84

Authored by Ralf Baechle 2010-09-18 00:07:48 +0800

Exists in master and in 7 other branches

MIPS: GIC: Remove dependencies from Malta files.

This prevents the GIC code from being reusable sanely.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Showing 4 changed files with 5 additions and 5 deletions Inline Diff

arch/mips/include/asm/gic.h
arch/mips/include/asm/mips-boards/maltaint.h
arch/mips/kernel/irq-gic.c
arch/mips/mti-malta/malta-int.c

arch/mips/include/asm/gic.h

Diff comments View file @ 863cb9b

 /*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  *
  * GIC Register Definitions
  *
  */
 #ifndef _ASM_GICREGS_H
 #define _ASM_GICREGS_H
 #undef	GICISBYTELITTLEENDIAN
 /* Constants */
 #define GIC_POL_POS			1
 #define GIC_POL_NEG			0
 #define GIC_TRIG_EDGE			1
 #define GIC_TRIG_LEVEL			0
 #define GIC_NUM_INTRS			(24 + NR_CPUS * 2)
 #define MSK(n) ((1 << (n)) - 1)
 #define REG32(addr)		(*(volatile unsigned int *) (addr))
 #define REG(base, offs)		REG32((unsigned long)(base) + offs##_##OFS)
 #define REGP(base, phys)	REG32((unsigned long)(base) + (phys))
 /* Accessors */
 #define GIC_REG(segment, offset) \
 	REG32(_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
 #define GIC_REG_ADDR(segment, offset) \
 	REG32(_gic_base + segment##_##SECTION_OFS + offset)
 #define GIC_ABS_REG(segment, offset) \
        (_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
 #define GIC_REG_ABS_ADDR(segment, offset) \
        (_gic_base + segment##_##SECTION_OFS + offset)
 #ifdef GICISBYTELITTLEENDIAN
 #define GICREAD(reg, data)	(data) = (reg), (data) = le32_to_cpu(data)
 #define GICWRITE(reg, data)	(reg) = cpu_to_le32(data)
 #define GICBIS(reg, bits)			\
 	({unsigned int data;			\
 		GICREAD(reg, data);		\
 		data |= bits;			\
 		GICWRITE(reg, data);		\
 	})
 #else
 #define GICREAD(reg, data)	(data) = (reg)
 #define GICWRITE(reg, data)	(reg) = (data)
 #define GICBIS(reg, bits)	(reg) |= (bits)
 #endif
 /* GIC Address Space */
 #define SHARED_SECTION_OFS		0x0000
 #define SHARED_SECTION_SIZE		0x8000
 #define VPE_LOCAL_SECTION_OFS		0x8000
 #define VPE_LOCAL_SECTION_SIZE		0x4000
 #define VPE_OTHER_SECTION_OFS		0xc000
 #define VPE_OTHER_SECTION_SIZE		0x4000
 #define USM_VISIBLE_SECTION_OFS		0x10000
 #define USM_VISIBLE_SECTION_SIZE	0x10000
 /* Register Map for Shared Section */
 #define	GIC_SH_CONFIG_OFS		0x0000
 /* Shared Global Counter */
 #define GIC_SH_COUNTER_31_00_OFS	0x0010
 #define GIC_SH_COUNTER_63_32_OFS	0x0014
 #define GIC_SH_REVISIONID_OFS		0x0020
 /* Interrupt Polarity */
 #define GIC_SH_POL_31_0_OFS		0x0100
 #define GIC_SH_POL_63_32_OFS		0x0104
 #define GIC_SH_POL_95_64_OFS		0x0108
 #define GIC_SH_POL_127_96_OFS		0x010c
 #define GIC_SH_POL_159_128_OFS		0x0110
 #define GIC_SH_POL_191_160_OFS		0x0114
 #define GIC_SH_POL_223_192_OFS		0x0118
 #define GIC_SH_POL_255_224_OFS		0x011c
 /* Edge/Level Triggering */
 #define GIC_SH_TRIG_31_0_OFS		0x0180
 #define GIC_SH_TRIG_63_32_OFS		0x0184
 #define GIC_SH_TRIG_95_64_OFS		0x0188
 #define GIC_SH_TRIG_127_96_OFS		0x018c
 #define GIC_SH_TRIG_159_128_OFS		0x0190
 #define GIC_SH_TRIG_191_160_OFS		0x0194
 #define GIC_SH_TRIG_223_192_OFS		0x0198
 #define GIC_SH_TRIG_255_224_OFS		0x019c
 /* Dual Edge Triggering */
 #define GIC_SH_DUAL_31_0_OFS		0x0200
 #define GIC_SH_DUAL_63_32_OFS		0x0204
 #define GIC_SH_DUAL_95_64_OFS		0x0208
 #define GIC_SH_DUAL_127_96_OFS		0x020c
 #define GIC_SH_DUAL_159_128_OFS		0x0210
 #define GIC_SH_DUAL_191_160_OFS		0x0214
 #define GIC_SH_DUAL_223_192_OFS		0x0218
 #define GIC_SH_DUAL_255_224_OFS		0x021c
 /* Set/Clear corresponding bit in Edge Detect Register */
 #define GIC_SH_WEDGE_OFS		0x0280
 /* Reset Mask - Disables Interrupt */
 #define GIC_SH_RMASK_31_0_OFS		0x0300
 #define GIC_SH_RMASK_63_32_OFS		0x0304
 #define GIC_SH_RMASK_95_64_OFS		0x0308
 #define GIC_SH_RMASK_127_96_OFS		0x030c
 #define GIC_SH_RMASK_159_128_OFS	0x0310
 #define GIC_SH_RMASK_191_160_OFS	0x0314
 #define GIC_SH_RMASK_223_192_OFS	0x0318
 #define GIC_SH_RMASK_255_224_OFS	0x031c
 /* Set Mask (WO) - Enables Interrupt */
 #define GIC_SH_SMASK_31_0_OFS		0x0380
 #define GIC_SH_SMASK_63_32_OFS		0x0384
 #define GIC_SH_SMASK_95_64_OFS		0x0388
 #define GIC_SH_SMASK_127_96_OFS		0x038c
 #define GIC_SH_SMASK_159_128_OFS	0x0390
 #define GIC_SH_SMASK_191_160_OFS	0x0394
 #define GIC_SH_SMASK_223_192_OFS	0x0398
 #define GIC_SH_SMASK_255_224_OFS	0x039c
 /* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
 #define GIC_SH_MASK_31_0_OFS		0x0400
 #define GIC_SH_MASK_63_32_OFS		0x0404
 #define GIC_SH_MASK_95_64_OFS		0x0408
 #define GIC_SH_MASK_127_96_OFS		0x040c
 #define GIC_SH_MASK_159_128_OFS		0x0410
 #define GIC_SH_MASK_191_160_OFS		0x0414
 #define GIC_SH_MASK_223_192_OFS		0x0418
 #define GIC_SH_MASK_255_224_OFS		0x041c
 /* Pending Global Interrupts (RO) */
 #define GIC_SH_PEND_31_0_OFS		0x0480
 #define GIC_SH_PEND_63_32_OFS		0x0484
 #define GIC_SH_PEND_95_64_OFS		0x0488
 #define GIC_SH_PEND_127_96_OFS		0x048c
 #define GIC_SH_PEND_159_128_OFS		0x0490
 #define GIC_SH_PEND_191_160_OFS		0x0494
 #define GIC_SH_PEND_223_192_OFS		0x0498
 #define GIC_SH_PEND_255_224_OFS		0x049c
 #define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS	0x0500
 /* Maps Interrupt X to a Pin */
 #define GIC_SH_MAP_TO_PIN(intr) \
 	(GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
 #define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS	0x2000
 /* Maps Interrupt X to a VPE */
 #define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
 	(GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4))
 #define GIC_SH_MAP_TO_VPE_REG_BIT(vpe)	(1 << ((vpe) % 32))
 /* Convert an interrupt number to a byte offset/bit for multi-word registers */
 #define GIC_INTR_OFS(intr) (((intr) / 32)*4)
 #define GIC_INTR_BIT(intr) ((intr) % 32)
 /* Polarity : Reset Value is always 0 */
 #define GIC_SH_SET_POLARITY_OFS		0x0100
 #define GIC_SET_POLARITY(intr, pol) \
 	GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + \
 		GIC_INTR_OFS(intr)), (pol) << GIC_INTR_BIT(intr))
 /* Triggering : Reset Value is always 0 */
 #define GIC_SH_SET_TRIGGER_OFS		0x0180
 #define GIC_SET_TRIGGER(intr, trig) \
 	GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + \
 		GIC_INTR_OFS(intr)), (trig) << GIC_INTR_BIT(intr))
 /* Mask manipulation */
 #define GIC_SH_SMASK_OFS		0x0380
 #define GIC_SET_INTR_MASK(intr) \
 	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + \
 		GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
 #define GIC_SH_RMASK_OFS		0x0300
 #define GIC_CLR_INTR_MASK(intr) \
 	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + \
 		GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
 /* Register Map for Local Section */
 #define GIC_VPE_CTL_OFS			0x0000
 #define GIC_VPE_PEND_OFS		0x0004
 #define GIC_VPE_MASK_OFS		0x0008
 #define GIC_VPE_RMASK_OFS		0x000c
 #define GIC_VPE_SMASK_OFS		0x0010
 #define GIC_VPE_WD_MAP_OFS		0x0040
 #define GIC_VPE_COMPARE_MAP_OFS		0x0044
 #define GIC_VPE_TIMER_MAP_OFS		0x0048
 #define GIC_VPE_PERFCTR_MAP_OFS		0x0050
 #define GIC_VPE_SWINT0_MAP_OFS		0x0054
 #define GIC_VPE_SWINT1_MAP_OFS		0x0058
 #define GIC_VPE_OTHER_ADDR_OFS		0x0080
 #define GIC_VPE_WD_CONFIG0_OFS		0x0090
 #define GIC_VPE_WD_COUNT0_OFS		0x0094
 #define GIC_VPE_WD_INITIAL0_OFS		0x0098
 #define GIC_VPE_COMPARE_LO_OFS		0x00a0
 #define GIC_VPE_COMPARE_HI		0x00a4
 #define GIC_VPE_EIC_SHADOW_SET_BASE	0x0100
 #define GIC_VPE_EIC_SS(intr) \
 	(GIC_EIC_SHADOW_SET_BASE + (4 * intr))
 #define GIC_VPE_EIC_VEC_BASE		0x0800
 #define GIC_VPE_EIC_VEC(intr) \
 	(GIC_VPE_EIC_VEC_BASE + (4 * intr))
 #define GIC_VPE_TENABLE_NMI_OFS		0x1000
 #define GIC_VPE_TENABLE_YQ_OFS		0x1004
 #define GIC_VPE_TENABLE_INT_31_0_OFS	0x1080
 #define GIC_VPE_TENABLE_INT_63_32_OFS	0x1084
 /* User Mode Visible Section Register Map */
 #define GIC_UMV_SH_COUNTER_31_00_OFS	0x0000
 #define GIC_UMV_SH_COUNTER_63_32_OFS	0x0004
 /* Masks */
 #define GIC_SH_CONFIG_COUNTSTOP_SHF	28
 #define GIC_SH_CONFIG_COUNTSTOP_MSK	(MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
 #define GIC_SH_CONFIG_COUNTBITS_SHF	24
 #define GIC_SH_CONFIG_COUNTBITS_MSK	(MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)
 #define GIC_SH_CONFIG_NUMINTRS_SHF	16
 #define GIC_SH_CONFIG_NUMINTRS_MSK	(MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)
 #define GIC_SH_CONFIG_NUMVPES_SHF	0
 #define GIC_SH_CONFIG_NUMVPES_MSK	(MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF)
 #define GIC_SH_WEDGE_SET(intr)		(intr | (0x1 << 31))
 #define GIC_SH_WEDGE_CLR(intr)		(intr & ~(0x1 << 31))
 #define GIC_MAP_TO_PIN_SHF		31
 #define GIC_MAP_TO_PIN_MSK		(MSK(1) << GIC_MAP_TO_PIN_SHF)
 #define GIC_MAP_TO_NMI_SHF		30
 #define GIC_MAP_TO_NMI_MSK		(MSK(1) << GIC_MAP_TO_NMI_SHF)
 #define GIC_MAP_TO_YQ_SHF		29
 #define GIC_MAP_TO_YQ_MSK		(MSK(1) << GIC_MAP_TO_YQ_SHF)
 #define GIC_MAP_SHF			0
 #define GIC_MAP_MSK			(MSK(6) << GIC_MAP_SHF)
 /* GIC_VPE_CTL Masks */
 #define GIC_VPE_CTL_PERFCNT_RTBL_SHF	2
 #define GIC_VPE_CTL_PERFCNT_RTBL_MSK	(MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF)
 #define GIC_VPE_CTL_TIMER_RTBL_SHF	1
 #define GIC_VPE_CTL_TIMER_RTBL_MSK	(MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF)
 #define GIC_VPE_CTL_EIC_MODE_SHF	0
 #define GIC_VPE_CTL_EIC_MODE_MSK	(MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF)
 /* GIC_VPE_PEND Masks */
 #define GIC_VPE_PEND_WD_SHF		0
 #define GIC_VPE_PEND_WD_MSK		(MSK(1) << GIC_VPE_PEND_WD_SHF)
 #define GIC_VPE_PEND_CMP_SHF		1
 #define GIC_VPE_PEND_CMP_MSK		(MSK(1) << GIC_VPE_PEND_CMP_SHF)
 #define GIC_VPE_PEND_TIMER_SHF		2
 #define GIC_VPE_PEND_TIMER_MSK		(MSK(1) << GIC_VPE_PEND_TIMER_SHF)
 #define GIC_VPE_PEND_PERFCOUNT_SHF	3
 #define GIC_VPE_PEND_PERFCOUNT_MSK	(MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF)
 #define GIC_VPE_PEND_SWINT0_SHF		4
 #define GIC_VPE_PEND_SWINT0_MSK		(MSK(1) << GIC_VPE_PEND_SWINT0_SHF)
 #define GIC_VPE_PEND_SWINT1_SHF		5
 #define GIC_VPE_PEND_SWINT1_MSK		(MSK(1) << GIC_VPE_PEND_SWINT1_SHF)
 /* GIC_VPE_RMASK Masks */
 #define GIC_VPE_RMASK_WD_SHF		0
 #define GIC_VPE_RMASK_WD_MSK		(MSK(1) << GIC_VPE_RMASK_WD_SHF)
 #define GIC_VPE_RMASK_CMP_SHF		1
 #define GIC_VPE_RMASK_CMP_MSK		(MSK(1) << GIC_VPE_RMASK_CMP_SHF)
 #define GIC_VPE_RMASK_TIMER_SHF		2
 #define GIC_VPE_RMASK_TIMER_MSK		(MSK(1) << GIC_VPE_RMASK_TIMER_SHF)
 #define GIC_VPE_RMASK_PERFCNT_SHF	3
 #define GIC_VPE_RMASK_PERFCNT_MSK	(MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF)
 #define GIC_VPE_RMASK_SWINT0_SHF	4
 #define GIC_VPE_RMASK_SWINT0_MSK	(MSK(1) << GIC_VPE_RMASK_SWINT0_SHF)
 #define GIC_VPE_RMASK_SWINT1_SHF	5
 #define GIC_VPE_RMASK_SWINT1_MSK	(MSK(1) << GIC_VPE_RMASK_SWINT1_SHF)
 /* GIC_VPE_SMASK Masks */
 #define GIC_VPE_SMASK_WD_SHF		0
 #define GIC_VPE_SMASK_WD_MSK		(MSK(1) << GIC_VPE_SMASK_WD_SHF)
 #define GIC_VPE_SMASK_CMP_SHF		1
 #define GIC_VPE_SMASK_CMP_MSK		(MSK(1) << GIC_VPE_SMASK_CMP_SHF)
 #define GIC_VPE_SMASK_TIMER_SHF		2
 #define GIC_VPE_SMASK_TIMER_MSK		(MSK(1) << GIC_VPE_SMASK_TIMER_SHF)
 #define GIC_VPE_SMASK_PERFCNT_SHF	3
 #define GIC_VPE_SMASK_PERFCNT_MSK	(MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF)
 #define GIC_VPE_SMASK_SWINT0_SHF	4
 #define GIC_VPE_SMASK_SWINT0_MSK	(MSK(1) << GIC_VPE_SMASK_SWINT0_SHF)
 #define GIC_VPE_SMASK_SWINT1_SHF	5
 #define GIC_VPE_SMASK_SWINT1_MSK	(MSK(1) << GIC_VPE_SMASK_SWINT1_SHF)
 /*
  * Set the Mapping of Interrupt X to a VPE.
  */
 #define GIC_SH_MAP_TO_VPE_SMASK(intr, vpe) \
 	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe)), \
 		 GIC_SH_MAP_TO_VPE_REG_BIT(vpe))
 struct gic_pcpu_mask {
        DECLARE_BITMAP(pcpu_mask, GIC_NUM_INTRS);
 };
 struct gic_pending_regs {
        DECLARE_BITMAP(pending, GIC_NUM_INTRS);
 };
 struct gic_intrmask_regs {
        DECLARE_BITMAP(intrmask, GIC_NUM_INTRS);
 };
 /*
  * Interrupt Meta-data specification. The ipiflag helps
  * in building ipi_map.
  */
 struct gic_intr_map {
 	unsigned int cpunum;	/* Directed to this CPU */
+#define GIC_UNUSED		0xdead			/* Dummy data */
 	unsigned int pin;	/* Directed to this Pin */
 	unsigned int polarity;	/* Polarity : +/-	*/
 	unsigned int trigtype;	/* Trigger  : Edge/Levl */
 	unsigned int flags;	/* Misc flags	*/
 #define GIC_FLAG_IPI           0x01
 #define GIC_FLAG_TRANSPARENT   0x02
 };
 extern void gic_init(unsigned long gic_base_addr,
 	unsigned long gic_addrspace_size, struct gic_intr_map *intrmap,
 	unsigned int intrmap_size, unsigned int irqbase);
 extern unsigned int gic_get_int(void);
 extern void gic_send_ipi(unsigned int intr);
 extern unsigned int plat_ipi_call_int_xlate(unsigned int);
 extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
 #endif /* _ASM_GICREGS_H */

arch/mips/include/asm/mips-boards/maltaint.h

Diff comments View file @ 863cb9b

 /*
  * Carsten Langgaard, carstenl@mips.com
  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  *
  * ########################################################################
  *
  *  This program is free software; you can distribute it and/or modify it
  *  under the terms of the GNU General Public License (Version 2) as
  *  published by the Free Software Foundation.
  *
  *  This program is distributed in the hope it will be useful, but WITHOUT
  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  *  for more details.
  *
  *  You should have received a copy of the GNU General Public License along
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  *
  * ########################################################################
  *
  * Defines for the Malta interrupt controller.
  *
  */
 #ifndef _MIPS_MALTAINT_H
 #define _MIPS_MALTAINT_H
 #include <irq.h>
 /*
  * Interrupts 0..15 are used for Malta ISA compatible interrupts
  */
 #define MALTA_INT_BASE		0
 /* CPU interrupt offsets */
 #define MIPSCPU_INT_SW0		0
 #define MIPSCPU_INT_SW1		1
 #define MIPSCPU_INT_MB0		2
 #define MIPSCPU_INT_I8259A	MIPSCPU_INT_MB0
 #define MIPSCPU_INT_MB1		3
 #define MIPSCPU_INT_SMI		MIPSCPU_INT_MB1
 #define MIPSCPU_INT_IPI0	MIPSCPU_INT_MB1	/* GIC IPI */
 #define MIPSCPU_INT_MB2		4
 #define MIPSCPU_INT_IPI1	MIPSCPU_INT_MB2	/* GIC IPI */
 #define MIPSCPU_INT_MB3		5
 #define MIPSCPU_INT_COREHI	MIPSCPU_INT_MB3
 #define MIPSCPU_INT_MB4		6
 #define MIPSCPU_INT_CORELO	MIPSCPU_INT_MB4
 /*
  * Interrupts 64..127 are used for Soc-it Classic interrupts
  */
 #define MSC01C_INT_BASE		64
 /* SOC-it Classic interrupt offsets */
 #define MSC01C_INT_TMR		0
 #define MSC01C_INT_PCI		1
 /*
  * Interrupts 64..127 are used for Soc-it EIC interrupts
  */
 #define MSC01E_INT_BASE		64
 /* SOC-it EIC interrupt offsets */
 #define MSC01E_INT_SW0		1
 #define MSC01E_INT_SW1		2
 #define MSC01E_INT_MB0		3
 #define MSC01E_INT_I8259A	MSC01E_INT_MB0
 #define MSC01E_INT_MB1		4
 #define MSC01E_INT_SMI		MSC01E_INT_MB1
 #define MSC01E_INT_MB2		5
 #define MSC01E_INT_MB3		6
 #define MSC01E_INT_COREHI	MSC01E_INT_MB3
 #define MSC01E_INT_MB4		7
 #define MSC01E_INT_CORELO	MSC01E_INT_MB4
 #define MSC01E_INT_TMR		8
 #define MSC01E_INT_PCI		9
 #define MSC01E_INT_PERFCTR	10
 #define MSC01E_INT_CPUCTR	11
 /* GIC's Nomenclature for Core Interrupt Pins on the Malta */
 #define GIC_CPU_INT0		0 /* Core Interrupt 2 	*/
 #define GIC_CPU_INT1		1 /* .			*/
 #define GIC_CPU_INT2		2 /* .			*/
 #define GIC_CPU_INT3		3 /* .			*/
 #define GIC_CPU_INT4		4 /* .			*/
 #define GIC_CPU_INT5		5 /* Core Interrupt 5   */
 #define GIC_EXT_INTR(x)		x
-/* Dummy data */
-#define X			0xdead
 /* External Interrupts used for IPI */
 #define GIC_IPI_EXT_INTR_RESCHED_VPE0	16
 #define GIC_IPI_EXT_INTR_CALLFNC_VPE0	17
 #define GIC_IPI_EXT_INTR_RESCHED_VPE1	18
 #define GIC_IPI_EXT_INTR_CALLFNC_VPE1	19
 #define GIC_IPI_EXT_INTR_RESCHED_VPE2	20
 #define GIC_IPI_EXT_INTR_CALLFNC_VPE2	21
 #define GIC_IPI_EXT_INTR_RESCHED_VPE3	22
 #define GIC_IPI_EXT_INTR_CALLFNC_VPE3	23
 #define MIPS_GIC_IRQ_BASE	(MIPS_CPU_IRQ_BASE + 8)
 #ifndef __ASSEMBLY__
 extern void maltaint_init(void);
 #endif
 #endif /* !(_MIPS_MALTAINT_H) */

arch/mips/kernel/irq-gic.c

Diff comments View file @ 863cb9b

 #undef DEBUG
 #include <linux/bitmap.h>
 #include <linux/init.h>
 #include <linux/smp.h>
 #include <asm/io.h>
 #include <asm/gic.h>
 #include <asm/gcmpregs.h>
-#include <asm/mips-boards/maltaint.h>
 #include <asm/irq.h>
 #include <linux/hardirq.h>
 #include <asm-generic/bitops/find.h>
 static unsigned long _gic_base;
 static unsigned int _irqbase;
 static unsigned int gic_irq_flags[GIC_NUM_INTRS];
 #define GIC_IRQ_FLAG_EDGE      0x0001
 struct gic_pcpu_mask pcpu_masks[NR_CPUS];
 static struct gic_pending_regs pending_regs[NR_CPUS];
 static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
 void gic_send_ipi(unsigned int intr)
 {
 	pr_debug("CPU%d: %s status %08x\n", smp_processor_id(), __func__,
 		 read_c0_status());
 	GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr);
 }
 /* This is Malta specific and needs to be exported */
 static void __init vpe_local_setup(unsigned int numvpes)
 {
 	int i;
 	unsigned long timer_interrupt = 5, perf_interrupt = 5;
 	unsigned int vpe_ctl;
 	/*
 	 * Setup the default performance counter timer interrupts
 	 * for all VPEs
 	 */
 	for (i = 0; i < numvpes; i++) {
 		GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
 		/* Are Interrupts locally routable? */
 		GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_CTL), vpe_ctl);
 		if (vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK)
 			GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
 				 GIC_MAP_TO_PIN_MSK | timer_interrupt);
 		if (vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK)
 			GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
 				 GIC_MAP_TO_PIN_MSK | perf_interrupt);
 	}
 }
 unsigned int gic_get_int(void)
 {
 	unsigned int i;
 	unsigned long *pending, *intrmask, *pcpu_mask;
 	unsigned long *pending_abs, *intrmask_abs;
 	/* Get per-cpu bitmaps */
 	pending = pending_regs[smp_processor_id()].pending;
 	intrmask = intrmask_regs[smp_processor_id()].intrmask;
 	pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
 	pending_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
 							 GIC_SH_PEND_31_0_OFS);
 	intrmask_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
 							  GIC_SH_MASK_31_0_OFS);
 	for (i = 0; i < BITS_TO_LONGS(GIC_NUM_INTRS); i++) {
 		GICREAD(*pending_abs, pending[i]);
 		GICREAD(*intrmask_abs, intrmask[i]);
 		pending_abs++;
 		intrmask_abs++;
 	}
 	bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS);
 	bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS);
 	i = find_first_bit(pending, GIC_NUM_INTRS);
 	pr_debug("CPU%d: %s pend=%d\n", smp_processor_id(), __func__, i);
 	return i;
 }
 static unsigned int gic_irq_startup(unsigned int irq)
 {
 	irq -= _irqbase;
 	pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
 	GIC_SET_INTR_MASK(irq);
 	return 0;
 }
 static void gic_irq_ack(unsigned int irq)
 {
 	irq -= _irqbase;
 	pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
 	GIC_CLR_INTR_MASK(irq);
 	if (gic_irq_flags[irq] & GIC_IRQ_FLAG_EDGE)
 		GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
 }
 static void gic_mask_irq(unsigned int irq)
 {
 	irq -= _irqbase;
 	pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
 	GIC_CLR_INTR_MASK(irq);
 }
 static void gic_unmask_irq(unsigned int irq)
 {
 	irq -= _irqbase;
 	pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
 	GIC_SET_INTR_MASK(irq);
 }
 #ifdef CONFIG_SMP
 static DEFINE_SPINLOCK(gic_lock);
 static int gic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
 {
 	cpumask_t	tmp = CPU_MASK_NONE;
 	unsigned long	flags;
 	int		i;
 	irq -= _irqbase;
 	pr_debug(KERN_DEBUG "%s(%d) called\n", __func__, irq);
 	cpumask_and(&tmp, cpumask, cpu_online_mask);
 	if (cpus_empty(tmp))
 		return -1;
 	/* Assumption : cpumask refers to a single CPU */
 	spin_lock_irqsave(&gic_lock, flags);
 	for (;;) {
 		/* Re-route this IRQ */
 		GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
 		/* Update the pcpu_masks */
 		for (i = 0; i < NR_CPUS; i++)
 			clear_bit(irq, pcpu_masks[i].pcpu_mask);
 		set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);
 	}
 	cpumask_copy(irq_desc[irq].affinity, cpumask);
 	spin_unlock_irqrestore(&gic_lock, flags);
 	return 0;
 }
 #endif
 static struct irq_chip gic_irq_controller = {
 	.name		=	"MIPS GIC",
 	.startup	=	gic_irq_startup,
 	.ack		=	gic_irq_ack,
 	.mask		=	gic_mask_irq,
 	.mask_ack	=	gic_mask_irq,
 	.unmask		=	gic_unmask_irq,
 	.eoi		=	gic_unmask_irq,
 #ifdef CONFIG_SMP
 	.set_affinity	=	gic_set_affinity,
 #endif
 };
 static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
 	unsigned int pin, unsigned int polarity, unsigned int trigtype,
 	unsigned int flags)
 {
 	/* Setup Intr to Pin mapping */
 	if (pin & GIC_MAP_TO_NMI_MSK) {
 		GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
 		/* FIXME: hack to route NMI to all cpu's */
 		for (cpu = 0; cpu < NR_CPUS; cpu += 32) {
 			GICWRITE(GIC_REG_ADDR(SHARED,
 					  GIC_SH_MAP_TO_VPE_REG_OFF(intr, cpu)),
 				 0xffffffff);
 		}
 	} else {
 		GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)),
 			 GIC_MAP_TO_PIN_MSK | pin);
 		/* Setup Intr to CPU mapping */
 		GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
 	}
 	/* Setup Intr Polarity */
 	GIC_SET_POLARITY(intr, polarity);
 	/* Setup Intr Trigger Type */
 	GIC_SET_TRIGGER(intr, trigtype);
 	/* Init Intr Masks */
 	GIC_CLR_INTR_MASK(intr);
 	/* Initialise per-cpu Interrupt software masks */
 	if (flags & GIC_FLAG_IPI)
 		set_bit(intr, pcpu_masks[cpu].pcpu_mask);
 	if (flags & GIC_FLAG_TRANSPARENT)
 		GIC_SET_INTR_MASK(intr);
 	if (trigtype == GIC_TRIG_EDGE)
 		gic_irq_flags[intr] |= GIC_IRQ_FLAG_EDGE;
 }
 static void __init gic_basic_init(int numintrs, int numvpes,
 			struct gic_intr_map *intrmap, int mapsize)
 {
 	unsigned int i, cpu;
 	/* Setup defaults */
 	for (i = 0; i < numintrs; i++) {
 		GIC_SET_POLARITY(i, GIC_POL_POS);
 		GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
 		GIC_CLR_INTR_MASK(i);
 		if (i < GIC_NUM_INTRS)
 			gic_irq_flags[i] = 0;
 	}
 	/* Setup specifics */
 	for (i = 0; i < mapsize; i++) {
 		cpu = intrmap[i].cpunum;
-		if (cpu == X)
+		if (cpu == GIC_UNUSED)
 			continue;
 		if (cpu == 0 && i != 0 && intrmap[i].flags == 0)
 			continue;
 		gic_setup_intr(i,
 			intrmap[i].cpunum,
 			intrmap[i].pin,
 			intrmap[i].polarity,
 			intrmap[i].trigtype,
 			intrmap[i].flags);
 	}
 	vpe_local_setup(numvpes);
 	for (i = _irqbase; i < (_irqbase + numintrs); i++)
 		set_irq_chip(i, &gic_irq_controller);
 }
 void __init gic_init(unsigned long gic_base_addr,
 		     unsigned long gic_addrspace_size,
 		     struct gic_intr_map *intr_map, unsigned int intr_map_size,
 		     unsigned int irqbase)
 {
 	unsigned int gicconfig;
 	int numvpes, numintrs;
 	_gic_base = (unsigned long) ioremap_nocache(gic_base_addr,
 						    gic_addrspace_size);
 	_irqbase = irqbase;
 	GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
 	numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
 		   GIC_SH_CONFIG_NUMINTRS_SHF;
 	numintrs = ((numintrs + 1) * 8);
 	numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
 		  GIC_SH_CONFIG_NUMVPES_SHF;
 	pr_debug("%s called\n", __func__);
 	gic_basic_init(numintrs, numvpes, intr_map, intr_map_size);
 }

arch/mips/mti-malta/malta-int.c

Diff comments View file @ 863cb9b

 /*
  * Carsten Langgaard, carstenl@mips.com
  * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
  * Copyright (C) 2001 Ralf Baechle
  *
  *  This program is free software; you can distribute it and/or modify it
  *  under the terms of the GNU General Public License (Version 2) as
  *  published by the Free Software Foundation.
  *
  *  This program is distributed in the hope it will be useful, but WITHOUT
  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  *  for more details.
  *
  *  You should have received a copy of the GNU General Public License along
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  *
  * Routines for generic manipulation of the interrupts found on the MIPS
  * Malta board.
  * The interrupt controller is located in the South Bridge a PIIX4 device
  * with two internal 82C95 interrupt controllers.
  */
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/sched.h>
 #include <linux/smp.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/kernel_stat.h>
 #include <linux/kernel.h>
 #include <linux/random.h>
 #include <asm/traps.h>
 #include <asm/i8259.h>
 #include <asm/irq_cpu.h>
 #include <asm/irq_regs.h>
 #include <asm/mips-boards/malta.h>
 #include <asm/mips-boards/maltaint.h>
 #include <asm/mips-boards/piix4.h>
 #include <asm/gt64120.h>
 #include <asm/mips-boards/generic.h>
 #include <asm/mips-boards/msc01_pci.h>
 #include <asm/msc01_ic.h>
 #include <asm/gic.h>
 #include <asm/gcmpregs.h>
 int gcmp_present = -1;
 int gic_present;
 static unsigned long _msc01_biu_base;
 static unsigned long _gcmp_base;
 static unsigned int ipi_map[NR_CPUS];
 static DEFINE_RAW_SPINLOCK(mips_irq_lock);
 static inline int mips_pcibios_iack(void)
 {
 	int irq;
 	u32 dummy;
 	/*
 	 * Determine highest priority pending interrupt by performing
 	 * a PCI Interrupt Acknowledge cycle.
 	 */
 	switch (mips_revision_sconid) {
 	case MIPS_REVISION_SCON_SOCIT:
 	case MIPS_REVISION_SCON_ROCIT:
 	case MIPS_REVISION_SCON_SOCITSC:
 	case MIPS_REVISION_SCON_SOCITSCP:
 		MSC_READ(MSC01_PCI_IACK, irq);
 		irq &= 0xff;
 		break;
 	case MIPS_REVISION_SCON_GT64120:
 		irq = GT_READ(GT_PCI0_IACK_OFS);
 		irq &= 0xff;
 		break;
 	case MIPS_REVISION_SCON_BONITO:
 		/* The following will generate a PCI IACK cycle on the
 		 * Bonito controller. It's a little bit kludgy, but it
 		 * was the easiest way to implement it in hardware at
 		 * the given time.
 		 */
 		BONITO_PCIMAP_CFG = 0x20000;
 		/* Flush Bonito register block */
 		dummy = BONITO_PCIMAP_CFG;
 		iob();    /* sync */
 		irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);
 		iob();    /* sync */
 		irq &= 0xff;
 		BONITO_PCIMAP_CFG = 0;
 		break;
 	default:
 		printk(KERN_WARNING "Unknown system controller.\n");
 		return -1;
 	}
 	return irq;
 }
 static inline int get_int(void)
 {
 	unsigned long flags;
 	int irq;
 	raw_spin_lock_irqsave(&mips_irq_lock, flags);
 	irq = mips_pcibios_iack();
 	/*
 	 * The only way we can decide if an interrupt is spurious
 	 * is by checking the 8259 registers.  This needs a spinlock
 	 * on an SMP system,  so leave it up to the generic code...
 	 */
 	raw_spin_unlock_irqrestore(&mips_irq_lock, flags);
 	return irq;
 }
 static void malta_hw0_irqdispatch(void)
 {
 	int irq;
 	irq = get_int();
 	if (irq < 0) {
 		/* interrupt has already been cleared */
 		return;
 	}
 	do_IRQ(MALTA_INT_BASE + irq);
 }
 static void malta_ipi_irqdispatch(void)
 {
 	int irq;
 	irq = gic_get_int();
 	if (irq < 0)
 		return;  /* interrupt has already been cleared */
 	do_IRQ(MIPS_GIC_IRQ_BASE + irq);
 }
 static void corehi_irqdispatch(void)
 {
 	unsigned int intedge, intsteer, pcicmd, pcibadaddr;
 	unsigned int pcimstat, intisr, inten, intpol;
 	unsigned int intrcause, datalo, datahi;
 	struct pt_regs *regs = get_irq_regs();
 	printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n");
 	printk(KERN_EMERG "epc   : %08lx\nStatus: %08lx\n"
 			"Cause : %08lx\nbadVaddr : %08lx\n",
 			regs->cp0_epc, regs->cp0_status,
 			regs->cp0_cause, regs->cp0_badvaddr);
 	/* Read all the registers and then print them as there is a
 	   problem with interspersed printk's upsetting the Bonito controller.
 	   Do it for the others too.
 	*/
 	switch (mips_revision_sconid) {
 	case MIPS_REVISION_SCON_SOCIT:
 	case MIPS_REVISION_SCON_ROCIT:
 	case MIPS_REVISION_SCON_SOCITSC:
 	case MIPS_REVISION_SCON_SOCITSCP:
 		ll_msc_irq();
 		break;
 	case MIPS_REVISION_SCON_GT64120:
 		intrcause = GT_READ(GT_INTRCAUSE_OFS);
 		datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
 		datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
 		printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause);
 		printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n",
 				datahi, datalo);
 		break;
 	case MIPS_REVISION_SCON_BONITO:
 		pcibadaddr = BONITO_PCIBADADDR;
 		pcimstat = BONITO_PCIMSTAT;
 		intisr = BONITO_INTISR;
 		inten = BONITO_INTEN;
 		intpol = BONITO_INTPOL;
 		intedge = BONITO_INTEDGE;
 		intsteer = BONITO_INTSTEER;
 		pcicmd = BONITO_PCICMD;
 		printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr);
 		printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten);
 		printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol);
 		printk(KERN_EMERG "BONITO_INTEDGE = %08x\n", intedge);
 		printk(KERN_EMERG "BONITO_INTSTEER = %08x\n", intsteer);
 		printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd);
 		printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr);
 		printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat);
 		break;
 	}
 	die("CoreHi interrupt", regs);
 }
 static inline int clz(unsigned long x)
 {
 	__asm__(
 	"	.set	push					\n"
 	"	.set	mips32					\n"
 	"	clz	%0, %1					\n"
 	"	.set	pop					\n"
 	: "=r" (x)
 	: "r" (x));
 	return x;
 }
 /*
  * Version of ffs that only looks at bits 12..15.
  */
 static inline unsigned int irq_ffs(unsigned int pending)
 {
 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
 	return -clz(pending) + 31 - CAUSEB_IP;
 #else
 	unsigned int a0 = 7;
 	unsigned int t0;
 	t0 = pending & 0xf000;
 	t0 = t0 < 1;
 	t0 = t0 << 2;
 	a0 = a0 - t0;
 	pending = pending << t0;
 	t0 = pending & 0xc000;
 	t0 = t0 < 1;
 	t0 = t0 << 1;
 	a0 = a0 - t0;
 	pending = pending << t0;
 	t0 = pending & 0x8000;
 	t0 = t0 < 1;
 	/* t0 = t0 << 2; */
 	a0 = a0 - t0;
 	/* pending = pending << t0; */
 	return a0;
 #endif
 }
 /*
  * IRQs on the Malta board look basically (barring software IRQs which we
  * don't use at all and all external interrupt sources are combined together
  * on hardware interrupt 0 (MIPS IRQ 2)) like:
  *
  *	MIPS IRQ	Source
  *      --------        ------
  *             0	Software (ignored)
  *             1        Software (ignored)
  *             2        Combined hardware interrupt (hw0)
  *             3        Hardware (ignored)
  *             4        Hardware (ignored)
  *             5        Hardware (ignored)
  *             6        Hardware (ignored)
  *             7        R4k timer (what we use)
  *
  * We handle the IRQ according to _our_ priority which is:
  *
  * Highest ----     R4k Timer
  * Lowest  ----     Combined hardware interrupt
  *
  * then we just return, if multiple IRQs are pending then we will just take
  * another exception, big deal.
  */
 asmlinkage void plat_irq_dispatch(void)
 {
 	unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
 	int irq;
 	irq = irq_ffs(pending);
 	if (irq == MIPSCPU_INT_I8259A)
 		malta_hw0_irqdispatch();
 	else if (gic_present && ((1 << irq) & ipi_map[smp_processor_id()]))
 		malta_ipi_irqdispatch();
 	else if (irq >= 0)
 		do_IRQ(MIPS_CPU_IRQ_BASE + irq);
 	else
 		spurious_interrupt();
 }
 #ifdef CONFIG_MIPS_MT_SMP
 #define GIC_MIPS_CPU_IPI_RESCHED_IRQ	3
 #define GIC_MIPS_CPU_IPI_CALL_IRQ	4
 #define MIPS_CPU_IPI_RESCHED_IRQ 0	/* SW int 0 for resched */
 #define C_RESCHED C_SW0
 #define MIPS_CPU_IPI_CALL_IRQ 1		/* SW int 1 for resched */
 #define C_CALL C_SW1
 static int cpu_ipi_resched_irq, cpu_ipi_call_irq;
 static void ipi_resched_dispatch(void)
 {
 	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
 }
 static void ipi_call_dispatch(void)
 {
 	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
 }
 static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
 {
 	return IRQ_HANDLED;
 }
 static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
 {
 	smp_call_function_interrupt();
 	return IRQ_HANDLED;
 }
 static struct irqaction irq_resched = {
 	.handler	= ipi_resched_interrupt,
 	.flags		= IRQF_DISABLED|IRQF_PERCPU,
 	.name		= "IPI_resched"
 };
 static struct irqaction irq_call = {
 	.handler	= ipi_call_interrupt,
 	.flags		= IRQF_DISABLED|IRQF_PERCPU,
 	.name		= "IPI_call"
 };
 #endif /* CONFIG_MIPS_MT_SMP */
 static int gic_resched_int_base;
 static int gic_call_int_base;
 #define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
 #define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
 unsigned int plat_ipi_call_int_xlate(unsigned int cpu)
 {
 	return GIC_CALL_INT(cpu);
 }
 unsigned int plat_ipi_resched_int_xlate(unsigned int cpu)
 {
 	return GIC_RESCHED_INT(cpu);
 }
 static struct irqaction i8259irq = {
 	.handler = no_action,
 	.name = "XT-PIC cascade"
 };
 static struct irqaction corehi_irqaction = {
 	.handler = no_action,
 	.name = "CoreHi"
 };
 static msc_irqmap_t __initdata msc_irqmap[] = {
 	{MSC01C_INT_TMR,		MSC01_IRQ_EDGE, 0},
 	{MSC01C_INT_PCI,		MSC01_IRQ_LEVEL, 0},
 };
 static int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap);
 static msc_irqmap_t __initdata msc_eicirqmap[] = {
 	{MSC01E_INT_SW0,		MSC01_IRQ_LEVEL, 0},
 	{MSC01E_INT_SW1,		MSC01_IRQ_LEVEL, 0},
 	{MSC01E_INT_I8259A,		MSC01_IRQ_LEVEL, 0},
 	{MSC01E_INT_SMI,		MSC01_IRQ_LEVEL, 0},
 	{MSC01E_INT_COREHI,		MSC01_IRQ_LEVEL, 0},
 	{MSC01E_INT_CORELO,		MSC01_IRQ_LEVEL, 0},
 	{MSC01E_INT_TMR,		MSC01_IRQ_EDGE, 0},
 	{MSC01E_INT_PCI,		MSC01_IRQ_LEVEL, 0},
 	{MSC01E_INT_PERFCTR,		MSC01_IRQ_LEVEL, 0},
 	{MSC01E_INT_CPUCTR,		MSC01_IRQ_LEVEL, 0}
 };
 static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
 /*
  * This GIC specific tabular array defines the association between External
  * Interrupts and CPUs/Core Interrupts. The nature of the External
  * Interrupts is also defined here - polarity/trigger.
  */
 #define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK
+#define X GIC_UNUSED
 static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
 	{ X, X,		   X,		X,		0 },
 	{ X, X,		   X,	 	X,		0 },
 	{ X, X,		   X,		X,		0 },
 	{ 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
 	{ 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
 	{ 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
 	{ 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
 	{ 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
 	{ 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
 	{ 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
 	{ X, X,		   X,		X,		0 },
 	{ X, X,		   X,		X,		0 },
 	{ 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
 	{ 0, GIC_CPU_NMI,  GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
 	{ 0, GIC_CPU_NMI,  GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
 	{ X, X,		   X,		X,	        0 },
 	/* The remainder of this table is initialised by fill_ipi_map */
 };
+#undef X
 /*
  * GCMP needs to be detected before any SMP initialisation
  */
 int __init gcmp_probe(unsigned long addr, unsigned long size)
 {
 	if (mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) {
 		gcmp_present = 0;
 		return gcmp_present;
 	}
 	if (gcmp_present >= 0)
 		return gcmp_present;
 	_gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ);
 	_msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ);
 	gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR;
 	if (gcmp_present)
 		pr_debug("GCMP present\n");
 	return gcmp_present;
 }
 /* Return the number of IOCU's present */
 int __init gcmp_niocu(void)
 {
   return gcmp_present ?
     (GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >> GCMP_GCB_GC_NUMIOCU_SHF :
     0;
 }
 /* Set GCMP region attributes */
 void __init gcmp_setregion(int region, unsigned long base,
 			   unsigned long mask, int type)
 {
 	GCMPGCBn(CMxBASE, region) = base;
 	GCMPGCBn(CMxMASK, region) = mask | type;
 }
 #if defined(CONFIG_MIPS_MT_SMP)
 static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin)
 {
 	int intr = baseintr + cpu;
 	gic_intr_map[intr].cpunum = cpu;
 	gic_intr_map[intr].pin = cpupin;
 	gic_intr_map[intr].polarity = GIC_POL_POS;
 	gic_intr_map[intr].trigtype = GIC_TRIG_EDGE;
 	gic_intr_map[intr].flags = GIC_FLAG_IPI;
 	ipi_map[cpu] |= (1 << (cpupin + 2));
 }
 static void __init fill_ipi_map(void)
 {
 	int cpu;
 	for (cpu = 0; cpu < NR_CPUS; cpu++) {
 		fill_ipi_map1(gic_resched_int_base, cpu, GIC_CPU_INT1);
 		fill_ipi_map1(gic_call_int_base, cpu, GIC_CPU_INT2);
 	}
 }
 #endif
 void __init arch_init_ipiirq(int irq, struct irqaction *action)
 {
 	setup_irq(irq, action);
 	set_irq_handler(irq, handle_percpu_irq);
 }
 void __init arch_init_irq(void)
 {
 	init_i8259_irqs();
 	if (!cpu_has_veic)
 		mips_cpu_irq_init();
 	if (gcmp_present)  {
 		GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK;
 		gic_present = 1;
 	} else {
 		if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) {
 			_msc01_biu_base = (unsigned long)
 					ioremap_nocache(MSC01_BIU_REG_BASE,
 						MSC01_BIU_ADDRSPACE_SZ);
 			gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) &
 					MSC01_SC_CFG_GICPRES_MSK) >>
 					MSC01_SC_CFG_GICPRES_SHF;
 		}
 	}
 	if (gic_present)
 		pr_debug("GIC present\n");
 	switch (mips_revision_sconid) {
 	case MIPS_REVISION_SCON_SOCIT:
 	case MIPS_REVISION_SCON_ROCIT:
 		if (cpu_has_veic)
 			init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
 					MSC01E_INT_BASE, msc_eicirqmap,
 					msc_nr_eicirqs);
 		else
 			init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
 					MSC01C_INT_BASE, msc_irqmap,
 					msc_nr_irqs);
 		break;
 	case MIPS_REVISION_SCON_SOCITSC:
 	case MIPS_REVISION_SCON_SOCITSCP:
 		if (cpu_has_veic)
 			init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
 					MSC01E_INT_BASE, msc_eicirqmap,
 					msc_nr_eicirqs);
 		else
 			init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
 					MSC01C_INT_BASE, msc_irqmap,
 					msc_nr_irqs);
 	}
 	if (cpu_has_veic) {
 		set_vi_handler(MSC01E_INT_I8259A, malta_hw0_irqdispatch);
 		set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch);
 		setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
 		setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
 	} else if (cpu_has_vint) {
 		set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
 		set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch);
 #ifdef CONFIG_MIPS_MT_SMTC
 		setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq,
 			(0x100 << MIPSCPU_INT_I8259A));
 		setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
 			&corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
 		/*
 		 * Temporary hack to ensure that the subsidiary device
 		 * interrupts coing in via the i8259A, but associated
 		 * with low IRQ numbers, will restore the Status.IM
 		 * value associated with the i8259A.
 		 */
 		{
 			int i;
 			for (i = 0; i < 16; i++)
 				irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A);
 		}
 #else /* Not SMTC */
 		setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
 		setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
 						&corehi_irqaction);
 #endif /* CONFIG_MIPS_MT_SMTC */
 	} else {
 		setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
 		setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
 						&corehi_irqaction);
 	}
 	if (gic_present) {
 		/* FIXME */
 		int i;
 #if defined(CONFIG_MIPS_MT_SMP)
 		gic_call_int_base = GIC_NUM_INTRS - NR_CPUS;
 		gic_resched_int_base = gic_call_int_base - NR_CPUS;
 		fill_ipi_map();
 #endif
 		gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
 				ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
 		if (!gcmp_present) {
 			/* Enable the GIC */
 			i = REG(_msc01_biu_base, MSC01_SC_CFG);
 			REG(_msc01_biu_base, MSC01_SC_CFG) =
 				(i | (0x1 << MSC01_SC_CFG_GICENA_SHF));
 			pr_debug("GIC Enabled\n");
 		}
 #if defined(CONFIG_MIPS_MT_SMP)
 		/* set up ipi interrupts */
 		if (cpu_has_vint) {
 			set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch);
 			set_vi_handler(MIPSCPU_INT_IPI1, malta_ipi_irqdispatch);
 		}
 		/* Argh.. this really needs sorting out.. */
 		printk("CPU%d: status register was %08x\n", smp_processor_id(), read_c0_status());
 		write_c0_status(read_c0_status() | STATUSF_IP3 | STATUSF_IP4);
 		printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status());
 		write_c0_status(0x1100dc00);
 		printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status());
 		for (i = 0; i < NR_CPUS; i++) {
 			arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
 					 GIC_RESCHED_INT(i), &irq_resched);
 			arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
 					 GIC_CALL_INT(i), &irq_call);
 		}
 #endif
 	} else {
 #if defined(CONFIG_MIPS_MT_SMP)
 		/* set up ipi interrupts */
 		if (cpu_has_veic) {
 			set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch);
 			set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch);
 			cpu_ipi_resched_irq = MSC01E_INT_SW0;
 			cpu_ipi_call_irq = MSC01E_INT_SW1;
 		} else {
 			if (cpu_has_vint) {
 				set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
 				set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
 			}
 			cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
 			cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ;
 		}
 		arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched);
 		arch_init_ipiirq(cpu_ipi_call_irq, &irq_call);
 #endif
 	}
 }
 void malta_be_init(void)
 {
 	if (gcmp_present) {
 		/* Could change CM error mask register */
 	}
 }
 static char *tr[8] = {
 	"mem",	"gcr",	"gic",	"mmio",
 	"0x04",	"0x05",	"0x06",	"0x07"
 };
 static char *mcmd[32] = {
 	[0x00] = "0x00",
 	[0x01] = "Legacy Write",
 	[0x02] = "Legacy Read",
 	[0x03] = "0x03",
 	[0x04] = "0x04",
 	[0x05] = "0x05",
 	[0x06] = "0x06",
 	[0x07] = "0x07",
 	[0x08] = "Coherent Read Own",
 	[0x09] = "Coherent Read Share",
 	[0x0a] = "Coherent Read Discard",
 	[0x0b] = "Coherent Ready Share Always",
 	[0x0c] = "Coherent Upgrade",
 	[0x0d] = "Coherent Writeback",
 	[0x0e] = "0x0e",
 	[0x0f] = "0x0f",
 	[0x10] = "Coherent Copyback",
 	[0x11] = "Coherent Copyback Invalidate",
 	[0x12] = "Coherent Invalidate",
 	[0x13] = "Coherent Write Invalidate",
 	[0x14] = "Coherent Completion Sync",
 	[0x15] = "0x15",
 	[0x16] = "0x16",
 	[0x17] = "0x17",
 	[0x18] = "0x18",
 	[0x19] = "0x19",
 	[0x1a] = "0x1a",
 	[0x1b] = "0x1b",
 	[0x1c] = "0x1c",
 	[0x1d] = "0x1d",
 	[0x1e] = "0x1e",
 	[0x1f] = "0x1f"
 };
 static char *core[8] = {
 	"Invalid/OK", 	"Invalid/Data",
 	"Shared/OK",	"Shared/Data",
 	"Modified/OK",	"Modified/Data",
 	"Exclusive/OK",	"Exclusive/Data"
 };
 static char *causes[32] = {
 	"None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR",
 	"COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07",
 	"0x08", "0x09", "0x0a", "0x0b",
 	"0x0c", "0x0d", "0x0e", "0x0f",
 	"0x10", "0x11", "0x12", "0x13",
 	"0x14", "0x15", "0x16", "INTVN_WR_ERR",
 	"INTVN_RD_ERR", "0x19", "0x1a", "0x1b",
 	"0x1c", "0x1d", "0x1e", "0x1f"
 };
 int malta_be_handler(struct pt_regs *regs, int is_fixup)
 {
 	/* This duplicates the handling in do_be which seems wrong */
 	int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
 	if (gcmp_present) {
 		unsigned long cm_error = GCMPGCB(GCMEC);
 		unsigned long cm_addr = GCMPGCB(GCMEA);
 		unsigned long cm_other = GCMPGCB(GCMEO);
 		unsigned long cause, ocause;
 		char buf[256];
 		cause = (cm_error & GCMP_GCB_GMEC_ERROR_TYPE_MSK);
 		if (cause != 0) {
 			cause >>= GCMP_GCB_GMEC_ERROR_TYPE_SHF;
 			if (cause < 16) {
 				unsigned long cca_bits = (cm_error >> 15) & 7;
 				unsigned long tr_bits = (cm_error >> 12) & 7;
 				unsigned long mcmd_bits = (cm_error >> 7) & 0x1f;
 				unsigned long stag_bits = (cm_error >> 3) & 15;
 				unsigned long sport_bits = (cm_error >> 0) & 7;
 				snprintf(buf, sizeof(buf),
 					 "CCA=%lu TR=%s MCmd=%s STag=%lu "
 					 "SPort=%lu\n",
 					 cca_bits, tr[tr_bits], mcmd[mcmd_bits],
 					 stag_bits, sport_bits);
 			} else {
 				/* glob state & sresp together */
 				unsigned long c3_bits = (cm_error >> 18) & 7;
 				unsigned long c2_bits = (cm_error >> 15) & 7;
 				unsigned long c1_bits = (cm_error >> 12) & 7;
 				unsigned long c0_bits = (cm_error >> 9) & 7;
 				unsigned long sc_bit = (cm_error >> 8) & 1;
 				unsigned long mcmd_bits = (cm_error >> 3) & 0x1f;
 				unsigned long sport_bits = (cm_error >> 0) & 7;
 				snprintf(buf, sizeof(buf),
 					 "C3=%s C2=%s C1=%s C0=%s SC=%s "
 					 "MCmd=%s SPort=%lu\n",
 					 core[c3_bits], core[c2_bits],
 					 core[c1_bits], core[c0_bits],
 					 sc_bit ? "True" : "False",
 					 mcmd[mcmd_bits], sport_bits);
 			}
 			ocause = (cm_other & GCMP_GCB_GMEO_ERROR_2ND_MSK) >>
 				 GCMP_GCB_GMEO_ERROR_2ND_SHF;
 			printk("CM_ERROR=%08lx %s <%s>\n", cm_error,
 			       causes[cause], buf);
 			printk("CM_ADDR =%08lx\n", cm_addr);
 			printk("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]);
 			/* reprime cause register */
 			GCMPGCB(GCMEC) = 0;
 		}
 	}
 	return retval;
 }