Doug / smarc-fsl-linux-kernel

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/*

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/*

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* arch/powerpc/kernel/mpic.c

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* arch/powerpc/kernel/mpic.c

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*

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*

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* Driver for interrupt controllers following the OpenPIC standard, the

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* Driver for interrupt controllers following the OpenPIC standard, the

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* common implementation beeing IBM's MPIC. This driver also can deal

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* common implementation beeing IBM's MPIC. This driver also can deal

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* with various broken implementations of this HW.

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* with various broken implementations of this HW.

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*

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*

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*

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*

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* This file is subject to the terms and conditions of the GNU General Public

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* This file is subject to the terms and conditions of the GNU General Public

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* License. See the file COPYING in the main directory of this archive

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* License. See the file COPYING in the main directory of this archive

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* for more details.

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* for more details.

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*/

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*/

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#undef DEBUG

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#undef DEBUG

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#undef DEBUG_IPI

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#undef DEBUG_IPI

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#undef DEBUG_IRQ

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#undef DEBUG_IRQ

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#undef DEBUG_LOW

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#undef DEBUG_LOW

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#include <linux/types.h>

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#include <linux/types.h>

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#include <linux/kernel.h>

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#include <linux/kernel.h>

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#include <linux/init.h>

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#include <linux/init.h>

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#include <linux/irq.h>

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#include <linux/irq.h>

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#include <linux/smp.h>

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#include <linux/smp.h>

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#include <linux/interrupt.h>

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#include <linux/interrupt.h>

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#include <linux/bootmem.h>

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#include <linux/bootmem.h>

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#include <linux/spinlock.h>

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#include <linux/spinlock.h>

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#include <linux/pci.h>

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#include <linux/pci.h>

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#include <linux/slab.h>

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#include <linux/slab.h>

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#include <asm/ptrace.h>

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#include <asm/ptrace.h>

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#include <asm/signal.h>

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#include <asm/signal.h>

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#include <asm/io.h>

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#include <asm/io.h>

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#include <asm/pgtable.h>

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#include <asm/pgtable.h>

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#include <asm/irq.h>

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#include <asm/irq.h>

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#include <asm/machdep.h>

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#include <asm/machdep.h>

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#include <asm/mpic.h>

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#include <asm/mpic.h>

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#include <asm/smp.h>

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#include <asm/smp.h>

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#include "mpic.h"

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#include "mpic.h"

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#ifdef DEBUG

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#ifdef DEBUG

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#define DBG(fmt...) printk(fmt)

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#define DBG(fmt...) printk(fmt)

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#else

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#else

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#define DBG(fmt...)

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#define DBG(fmt...)

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#endif

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#endif

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static struct mpic *mpics;

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static struct mpic *mpics;

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static struct mpic *mpic_primary;

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static struct mpic *mpic_primary;

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static DEFINE_RAW_SPINLOCK(mpic_lock);

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static DEFINE_RAW_SPINLOCK(mpic_lock);

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#ifdef CONFIG_PPC32 /* XXX for now */

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#ifdef CONFIG_PPC32 /* XXX for now */

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#ifdef CONFIG_IRQ_ALL_CPUS

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#ifdef CONFIG_IRQ_ALL_CPUS

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#define distribute_irqs (1)

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#define distribute_irqs (1)

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#else

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#else

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#define distribute_irqs (0)

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#define distribute_irqs (0)

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#endif

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#endif

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#endif

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#endif

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#ifdef CONFIG_MPIC_WEIRD

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#ifdef CONFIG_MPIC_WEIRD

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static u32 mpic_infos[][MPIC_IDX_END] = {

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static u32 mpic_infos[][MPIC_IDX_END] = {

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[0] = { /* Original OpenPIC compatible MPIC */

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[0] = { /* Original OpenPIC compatible MPIC */

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MPIC_GREG_BASE,

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MPIC_GREG_BASE,

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MPIC_GREG_FEATURE_0,

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MPIC_GREG_FEATURE_0,

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MPIC_GREG_GLOBAL_CONF_0,

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MPIC_GREG_GLOBAL_CONF_0,

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MPIC_GREG_VENDOR_ID,

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MPIC_GREG_VENDOR_ID,

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MPIC_GREG_IPI_VECTOR_PRI_0,

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MPIC_GREG_IPI_VECTOR_PRI_0,

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MPIC_GREG_IPI_STRIDE,

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MPIC_GREG_IPI_STRIDE,

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MPIC_GREG_SPURIOUS,

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MPIC_GREG_SPURIOUS,

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MPIC_GREG_TIMER_FREQ,

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MPIC_GREG_TIMER_FREQ,

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MPIC_TIMER_BASE,

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MPIC_TIMER_BASE,

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MPIC_TIMER_STRIDE,

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MPIC_TIMER_STRIDE,

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MPIC_TIMER_CURRENT_CNT,

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MPIC_TIMER_CURRENT_CNT,

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MPIC_TIMER_BASE_CNT,

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MPIC_TIMER_BASE_CNT,

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MPIC_TIMER_VECTOR_PRI,

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MPIC_TIMER_VECTOR_PRI,

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MPIC_TIMER_DESTINATION,

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MPIC_TIMER_DESTINATION,

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MPIC_CPU_BASE,

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MPIC_CPU_BASE,

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MPIC_CPU_STRIDE,

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MPIC_CPU_STRIDE,

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MPIC_CPU_IPI_DISPATCH_0,

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MPIC_CPU_IPI_DISPATCH_0,

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MPIC_CPU_IPI_DISPATCH_STRIDE,

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MPIC_CPU_IPI_DISPATCH_STRIDE,

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MPIC_CPU_CURRENT_TASK_PRI,

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MPIC_CPU_CURRENT_TASK_PRI,

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MPIC_CPU_WHOAMI,

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MPIC_CPU_WHOAMI,

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MPIC_CPU_INTACK,

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MPIC_CPU_INTACK,

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MPIC_CPU_EOI,

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MPIC_CPU_EOI,

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MPIC_CPU_MCACK,

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MPIC_CPU_MCACK,

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MPIC_IRQ_BASE,

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MPIC_IRQ_BASE,

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MPIC_IRQ_STRIDE,

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MPIC_IRQ_STRIDE,

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MPIC_IRQ_VECTOR_PRI,

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MPIC_IRQ_VECTOR_PRI,

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MPIC_VECPRI_VECTOR_MASK,

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MPIC_VECPRI_VECTOR_MASK,

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MPIC_VECPRI_POLARITY_POSITIVE,

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MPIC_VECPRI_POLARITY_POSITIVE,

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MPIC_VECPRI_POLARITY_NEGATIVE,

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MPIC_VECPRI_POLARITY_NEGATIVE,

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MPIC_VECPRI_SENSE_LEVEL,

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MPIC_VECPRI_SENSE_LEVEL,

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MPIC_VECPRI_SENSE_EDGE,

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MPIC_VECPRI_SENSE_EDGE,

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MPIC_VECPRI_POLARITY_MASK,

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MPIC_VECPRI_POLARITY_MASK,

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MPIC_VECPRI_SENSE_MASK,

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MPIC_VECPRI_SENSE_MASK,

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MPIC_IRQ_DESTINATION

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MPIC_IRQ_DESTINATION

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},

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},

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[1] = { /* Tsi108/109 PIC */

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[1] = { /* Tsi108/109 PIC */

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TSI108_GREG_BASE,

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TSI108_GREG_BASE,

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TSI108_GREG_FEATURE_0,

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TSI108_GREG_FEATURE_0,

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TSI108_GREG_GLOBAL_CONF_0,

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TSI108_GREG_GLOBAL_CONF_0,

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TSI108_GREG_VENDOR_ID,

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TSI108_GREG_VENDOR_ID,

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TSI108_GREG_IPI_VECTOR_PRI_0,

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TSI108_GREG_IPI_VECTOR_PRI_0,

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TSI108_GREG_IPI_STRIDE,

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TSI108_GREG_IPI_STRIDE,

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TSI108_GREG_SPURIOUS,

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TSI108_GREG_SPURIOUS,

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TSI108_GREG_TIMER_FREQ,

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TSI108_GREG_TIMER_FREQ,

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TSI108_TIMER_BASE,

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TSI108_TIMER_BASE,

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TSI108_TIMER_STRIDE,

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TSI108_TIMER_STRIDE,

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TSI108_TIMER_CURRENT_CNT,

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TSI108_TIMER_CURRENT_CNT,

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TSI108_TIMER_BASE_CNT,

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TSI108_TIMER_BASE_CNT,

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TSI108_TIMER_VECTOR_PRI,

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TSI108_TIMER_VECTOR_PRI,

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TSI108_TIMER_DESTINATION,

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TSI108_TIMER_DESTINATION,

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TSI108_CPU_BASE,

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TSI108_CPU_BASE,

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TSI108_CPU_STRIDE,

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TSI108_CPU_STRIDE,

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TSI108_CPU_IPI_DISPATCH_0,

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TSI108_CPU_IPI_DISPATCH_0,

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TSI108_CPU_IPI_DISPATCH_STRIDE,

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TSI108_CPU_IPI_DISPATCH_STRIDE,

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TSI108_CPU_CURRENT_TASK_PRI,

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TSI108_CPU_CURRENT_TASK_PRI,

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TSI108_CPU_WHOAMI,

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TSI108_CPU_WHOAMI,

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TSI108_CPU_INTACK,

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TSI108_CPU_INTACK,

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TSI108_CPU_EOI,

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TSI108_CPU_EOI,

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TSI108_CPU_MCACK,

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TSI108_CPU_MCACK,

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TSI108_IRQ_BASE,

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TSI108_IRQ_BASE,

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TSI108_IRQ_STRIDE,

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TSI108_IRQ_STRIDE,

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TSI108_IRQ_VECTOR_PRI,

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TSI108_IRQ_VECTOR_PRI,

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TSI108_VECPRI_VECTOR_MASK,

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TSI108_VECPRI_VECTOR_MASK,

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TSI108_VECPRI_POLARITY_POSITIVE,

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TSI108_VECPRI_POLARITY_POSITIVE,

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TSI108_VECPRI_POLARITY_NEGATIVE,

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TSI108_VECPRI_POLARITY_NEGATIVE,

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TSI108_VECPRI_SENSE_LEVEL,

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TSI108_VECPRI_SENSE_LEVEL,

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TSI108_VECPRI_SENSE_EDGE,

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TSI108_VECPRI_SENSE_EDGE,

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TSI108_VECPRI_POLARITY_MASK,

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TSI108_VECPRI_POLARITY_MASK,

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TSI108_VECPRI_SENSE_MASK,

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TSI108_VECPRI_SENSE_MASK,

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TSI108_IRQ_DESTINATION

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TSI108_IRQ_DESTINATION

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},

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},

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};

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};

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#define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]

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#define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]

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#else /* CONFIG_MPIC_WEIRD */

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#else /* CONFIG_MPIC_WEIRD */

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#define MPIC_INFO(name) MPIC_##name

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#define MPIC_INFO(name) MPIC_##name

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#endif /* CONFIG_MPIC_WEIRD */

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#endif /* CONFIG_MPIC_WEIRD */

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/*

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/*

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* Register accessor functions

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* Register accessor functions

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*/

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*/

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static inline u32 _mpic_read(enum mpic_reg_type type,

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static inline u32 _mpic_read(enum mpic_reg_type type,

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struct mpic_reg_bank *rb,

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struct mpic_reg_bank *rb,

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unsigned int reg)

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unsigned int reg)

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{

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{

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switch(type) {

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switch(type) {

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#ifdef CONFIG_PPC_DCR

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#ifdef CONFIG_PPC_DCR

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case mpic_access_dcr:

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case mpic_access_dcr:

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return dcr_read(rb->dhost, reg);

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return dcr_read(rb->dhost, reg);

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#endif

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#endif

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case mpic_access_mmio_be:

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case mpic_access_mmio_be:

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return in_be32(rb->base + (reg >> 2));

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return in_be32(rb->base + (reg >> 2));

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case mpic_access_mmio_le:

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case mpic_access_mmio_le:

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default:

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default:

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return in_le32(rb->base + (reg >> 2));

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return in_le32(rb->base + (reg >> 2));

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}

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}

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}

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}

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static inline void _mpic_write(enum mpic_reg_type type,

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static inline void _mpic_write(enum mpic_reg_type type,

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struct mpic_reg_bank *rb,

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struct mpic_reg_bank *rb,

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unsigned int reg, u32 value)

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unsigned int reg, u32 value)

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{

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{

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switch(type) {

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switch(type) {

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#ifdef CONFIG_PPC_DCR

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#ifdef CONFIG_PPC_DCR

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case mpic_access_dcr:

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case mpic_access_dcr:

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dcr_write(rb->dhost, reg, value);

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dcr_write(rb->dhost, reg, value);

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break;

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break;

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#endif

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#endif

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case mpic_access_mmio_be:

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case mpic_access_mmio_be:

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out_be32(rb->base + (reg >> 2), value);

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out_be32(rb->base + (reg >> 2), value);

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break;

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break;

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case mpic_access_mmio_le:

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case mpic_access_mmio_le:

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default:

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default:

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out_le32(rb->base + (reg >> 2), value);

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out_le32(rb->base + (reg >> 2), value);

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break;

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break;

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}

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}

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}

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}

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static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)

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static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)

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{

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{

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enum mpic_reg_type type = mpic->reg_type;

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enum mpic_reg_type type = mpic->reg_type;

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unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +

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unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +

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(ipi * MPIC_INFO(GREG_IPI_STRIDE));

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(ipi * MPIC_INFO(GREG_IPI_STRIDE));

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if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)

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if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)

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type = mpic_access_mmio_be;

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type = mpic_access_mmio_be;

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return _mpic_read(type, &mpic->gregs, offset);

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return _mpic_read(type, &mpic->gregs, offset);

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}

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}

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static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)

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static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)

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{

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{

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unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +

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unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +

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(ipi * MPIC_INFO(GREG_IPI_STRIDE));

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(ipi * MPIC_INFO(GREG_IPI_STRIDE));

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_mpic_write(mpic->reg_type, &mpic->gregs, offset, value);

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_mpic_write(mpic->reg_type, &mpic->gregs, offset, value);

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}

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}

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static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)

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static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)

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{

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{

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unsigned int cpu = 0;

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unsigned int cpu = 0;

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if (mpic->flags & MPIC_PRIMARY)

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if (mpic->flags & MPIC_PRIMARY)

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cpu = hard_smp_processor_id();

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cpu = hard_smp_processor_id();

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return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);

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return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);

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}

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}

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static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)

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static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)

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{

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{

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unsigned int cpu = 0;

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unsigned int cpu = 0;

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if (mpic->flags & MPIC_PRIMARY)

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if (mpic->flags & MPIC_PRIMARY)

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cpu = hard_smp_processor_id();

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cpu = hard_smp_processor_id();

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_mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);

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_mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);

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}

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}

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static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)

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static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)

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{

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{

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unsigned int isu = src_no >> mpic->isu_shift;

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unsigned int isu = src_no >> mpic->isu_shift;

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unsigned int idx = src_no & mpic->isu_mask;

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unsigned int idx = src_no & mpic->isu_mask;

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unsigned int val;

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unsigned int val;

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val = _mpic_read(mpic->reg_type, &mpic->isus[isu],

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val = _mpic_read(mpic->reg_type, &mpic->isus[isu],

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reg + (idx * MPIC_INFO(IRQ_STRIDE)));

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reg + (idx * MPIC_INFO(IRQ_STRIDE)));

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#ifdef CONFIG_MPIC_BROKEN_REGREAD

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#ifdef CONFIG_MPIC_BROKEN_REGREAD

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if (reg == 0)

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if (reg == 0)

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val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |

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val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |

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mpic->isu_reg0_shadow[src_no];

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mpic->isu_reg0_shadow[src_no];

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#endif

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#endif

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return val;

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return val;

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}

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}

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static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,

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static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,

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unsigned int reg, u32 value)

247

unsigned int reg, u32 value)

248

{

248

{

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unsigned int isu = src_no >> mpic->isu_shift;

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unsigned int isu = src_no >> mpic->isu_shift;

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unsigned int idx = src_no & mpic->isu_mask;

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unsigned int idx = src_no & mpic->isu_mask;

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252

_mpic_write(mpic->reg_type, &mpic->isus[isu],

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_mpic_write(mpic->reg_type, &mpic->isus[isu],

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reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);

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reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);

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255

#ifdef CONFIG_MPIC_BROKEN_REGREAD

255

#ifdef CONFIG_MPIC_BROKEN_REGREAD

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if (reg == 0)

256

if (reg == 0)

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mpic->isu_reg0_shadow[src_no] =

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mpic->isu_reg0_shadow[src_no] =

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value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);

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value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);

259

#endif

259

#endif

260

}

260

}

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#define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))

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#define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))

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#define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))

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#define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))

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#define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))

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#define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))

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#define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))

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#define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))

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#define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))

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#define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))

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#define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))

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#define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))

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#define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))

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#define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))

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#define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))

269

#define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))

270

271

272

/*

272

/*

273

* Low level utility functions

273

* Low level utility functions

274

*/

274

*/

275

276

277

static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,

277

static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,

278

struct mpic_reg_bank *rb, unsigned int offset,

278

struct mpic_reg_bank *rb, unsigned int offset,

279

unsigned int size)

279

unsigned int size)

280

{

280

{

281

rb->base = ioremap(phys_addr + offset, size);

281

rb->base = ioremap(phys_addr + offset, size);

282

BUG_ON(rb->base == NULL);

282

BUG_ON(rb->base == NULL);

283

}

283

}

284

285

#ifdef CONFIG_PPC_DCR

285

#ifdef CONFIG_PPC_DCR

286

static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node,

286

static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node,

287

struct mpic_reg_bank *rb,

287

struct mpic_reg_bank *rb,

288

unsigned int offset, unsigned int size)

288

unsigned int offset, unsigned int size)

289

{

289

{

290

const u32 *dbasep;

290

const u32 *dbasep;

291

292

dbasep = of_get_property(node, "dcr-reg", NULL);

292

dbasep = of_get_property(node, "dcr-reg", NULL);

293

294

rb->dhost = dcr_map(node, *dbasep + offset, size);

294

rb->dhost = dcr_map(node, *dbasep + offset, size);

295

BUG_ON(!DCR_MAP_OK(rb->dhost));

295

BUG_ON(!DCR_MAP_OK(rb->dhost));

296

}

296

}

297

298

static inline void mpic_map(struct mpic *mpic, struct device_node *node,

298

static inline void mpic_map(struct mpic *mpic, struct device_node *node,

299

phys_addr_t phys_addr, struct mpic_reg_bank *rb,

299

phys_addr_t phys_addr, struct mpic_reg_bank *rb,

300

unsigned int offset, unsigned int size)

300

unsigned int offset, unsigned int size)

301

{

301

{

302

if (mpic->flags & MPIC_USES_DCR)

302

if (mpic->flags & MPIC_USES_DCR)

303

_mpic_map_dcr(mpic, node, rb, offset, size);

303

_mpic_map_dcr(mpic, node, rb, offset, size);

304

else

304

else

305

_mpic_map_mmio(mpic, phys_addr, rb, offset, size);

305

_mpic_map_mmio(mpic, phys_addr, rb, offset, size);

306

}

306

}

307

#else /* CONFIG_PPC_DCR */

307

#else /* CONFIG_PPC_DCR */

308

#define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)

308

#define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)

309

#endif /* !CONFIG_PPC_DCR */

309

#endif /* !CONFIG_PPC_DCR */

310

311

312

313

/* Check if we have one of those nice broken MPICs with a flipped endian on

313

/* Check if we have one of those nice broken MPICs with a flipped endian on

314

* reads from IPI registers

314

* reads from IPI registers

315

*/

315

*/

316

static void __init mpic_test_broken_ipi(struct mpic *mpic)

316

static void __init mpic_test_broken_ipi(struct mpic *mpic)

317

{

317

{

318

u32 r;

318

u32 r;

319

320

mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);

320

mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);

321

r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));

321

r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));

322

323

if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {

323

if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {

324

printk(KERN_INFO "mpic: Detected reversed IPI registers\n");

324

printk(KERN_INFO "mpic: Detected reversed IPI registers\n");

325

mpic->flags |= MPIC_BROKEN_IPI;

325

mpic->flags |= MPIC_BROKEN_IPI;

326

}

326

}

327

}

327

}

328

329

#ifdef CONFIG_MPIC_U3_HT_IRQS

329

#ifdef CONFIG_MPIC_U3_HT_IRQS

330

331

/* Test if an interrupt is sourced from HyperTransport (used on broken U3s)

331

/* Test if an interrupt is sourced from HyperTransport (used on broken U3s)

332

* to force the edge setting on the MPIC and do the ack workaround.

332

* to force the edge setting on the MPIC and do the ack workaround.

333

*/

333

*/

334

static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)

334

static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)

335

{

335

{

336

if (source >= 128 || !mpic->fixups)

336

if (source >= 128 || !mpic->fixups)

337

return 0;

337

return 0;

338

return mpic->fixups[source].base != NULL;

338

return mpic->fixups[source].base != NULL;

339

}

339

}

340

341

342

static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)

342

static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)

343

{

343

{

344

struct mpic_irq_fixup *fixup = &mpic->fixups[source];

344

struct mpic_irq_fixup *fixup = &mpic->fixups[source];

345

346

if (fixup->applebase) {

346

if (fixup->applebase) {

347

unsigned int soff = (fixup->index >> 3) & ~3;

347

unsigned int soff = (fixup->index >> 3) & ~3;

348

unsigned int mask = 1U << (fixup->index & 0x1f);

348

unsigned int mask = 1U << (fixup->index & 0x1f);

349

writel(mask, fixup->applebase + soff);

349

writel(mask, fixup->applebase + soff);

350

} else {

350

} else {

351

raw_spin_lock(&mpic->fixup_lock);

351

raw_spin_lock(&mpic->fixup_lock);

352

writeb(0x11 + 2 * fixup->index, fixup->base + 2);

352

writeb(0x11 + 2 * fixup->index, fixup->base + 2);

353

writel(fixup->data, fixup->base + 4);

353

writel(fixup->data, fixup->base + 4);

354

raw_spin_unlock(&mpic->fixup_lock);

354

raw_spin_unlock(&mpic->fixup_lock);

355

}

355

}

356

}

356

}

357

358

static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,

358

static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,

359

unsigned int irqflags)

359

unsigned int irqflags)

360

{

360

{

361

struct mpic_irq_fixup *fixup = &mpic->fixups[source];

361

struct mpic_irq_fixup *fixup = &mpic->fixups[source];

362

unsigned long flags;

362

unsigned long flags;

363

u32 tmp;

363

u32 tmp;

364

365

if (fixup->base == NULL)

365

if (fixup->base == NULL)

366

return;

366

return;

367

368

DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n",

368

DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n",

369

source, irqflags, fixup->index);

369

source, irqflags, fixup->index);

370

raw_spin_lock_irqsave(&mpic->fixup_lock, flags);

370

raw_spin_lock_irqsave(&mpic->fixup_lock, flags);

371

/* Enable and configure */

371

/* Enable and configure */

372

writeb(0x10 + 2 * fixup->index, fixup->base + 2);

372

writeb(0x10 + 2 * fixup->index, fixup->base + 2);

373

tmp = readl(fixup->base + 4);

373

tmp = readl(fixup->base + 4);

374

tmp &= ~(0x23U);

374

tmp &= ~(0x23U);

375

if (irqflags & IRQ_LEVEL)

375

if (irqflags & IRQ_LEVEL)

376

tmp |= 0x22;

376

tmp |= 0x22;

377

writel(tmp, fixup->base + 4);

377

writel(tmp, fixup->base + 4);

378

raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);

378

raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);

379

380

#ifdef CONFIG_PM

380

#ifdef CONFIG_PM

381

/* use the lowest bit inverted to the actual HW,

381

/* use the lowest bit inverted to the actual HW,

382

* set if this fixup was enabled, clear otherwise */

382

* set if this fixup was enabled, clear otherwise */

383

mpic->save_data[source].fixup_data = tmp | 1;

383

mpic->save_data[source].fixup_data = tmp | 1;

384

#endif

384

#endif

385

}

385

}

386

387

static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source,

387

static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source,

388

unsigned int irqflags)

388

unsigned int irqflags)

389

{

389

{

390

struct mpic_irq_fixup *fixup = &mpic->fixups[source];

390

struct mpic_irq_fixup *fixup = &mpic->fixups[source];

391

unsigned long flags;

391

unsigned long flags;

392

u32 tmp;

392

u32 tmp;

393

394

if (fixup->base == NULL)

394

if (fixup->base == NULL)

395

return;

395

return;

396

397

DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags);

397

DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags);

398

399

/* Disable */

399

/* Disable */

400

raw_spin_lock_irqsave(&mpic->fixup_lock, flags);

400

raw_spin_lock_irqsave(&mpic->fixup_lock, flags);

401

writeb(0x10 + 2 * fixup->index, fixup->base + 2);

401

writeb(0x10 + 2 * fixup->index, fixup->base + 2);

402

tmp = readl(fixup->base + 4);

402

tmp = readl(fixup->base + 4);

403

tmp |= 1;

403

tmp |= 1;

404

writel(tmp, fixup->base + 4);

404

writel(tmp, fixup->base + 4);

405

raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);

405

raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);

406

407

#ifdef CONFIG_PM

407

#ifdef CONFIG_PM

408

/* use the lowest bit inverted to the actual HW,

408

/* use the lowest bit inverted to the actual HW,

409

* set if this fixup was enabled, clear otherwise */

409

* set if this fixup was enabled, clear otherwise */

410

mpic->save_data[source].fixup_data = tmp & ~1;

410

mpic->save_data[source].fixup_data = tmp & ~1;

411

#endif

411

#endif

412

}

412

}

413

414

#ifdef CONFIG_PCI_MSI

414

#ifdef CONFIG_PCI_MSI

415

static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,

415

static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,

416

unsigned int devfn)

416

unsigned int devfn)

417

{

417

{

418

u8 __iomem *base;

418

u8 __iomem *base;

419

u8 pos, flags;

419

u8 pos, flags;

420

u64 addr = 0;

420

u64 addr = 0;

421

422

for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;

422

for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;

423

pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {

423

pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {

424

u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);

424

u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);

425

if (id == PCI_CAP_ID_HT) {

425

if (id == PCI_CAP_ID_HT) {

426

id = readb(devbase + pos + 3);

426

id = readb(devbase + pos + 3);

427

if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)

427

if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)

428

break;

428

break;

429

}

429

}

430

}

430

}

431

432

if (pos == 0)

432

if (pos == 0)

433

return;

433

return;

434

435

base = devbase + pos;

435

base = devbase + pos;

436

437

flags = readb(base + HT_MSI_FLAGS);

437

flags = readb(base + HT_MSI_FLAGS);

438

if (!(flags & HT_MSI_FLAGS_FIXED)) {

438

if (!(flags & HT_MSI_FLAGS_FIXED)) {

439

addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;

439

addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;

440

addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);

440

addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);

441

}

441

}

442

443

printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",

443

printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",

444

PCI_SLOT(devfn), PCI_FUNC(devfn),

444

PCI_SLOT(devfn), PCI_FUNC(devfn),

445

flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);

445

flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);

446

447

if (!(flags & HT_MSI_FLAGS_ENABLE))

447

if (!(flags & HT_MSI_FLAGS_ENABLE))

448

writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);

448

writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);

449

}

449

}

450

#else

450

#else

451

static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,

451

static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,

452

unsigned int devfn)

452

unsigned int devfn)

453

{

453

{

454

return;

454

return;

455

}

455

}

456

#endif

456

#endif

457

458

static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,

458

static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,

459

unsigned int devfn, u32 vdid)

459

unsigned int devfn, u32 vdid)

460

{

460

{

461

int i, irq, n;

461

int i, irq, n;

462

u8 __iomem *base;

462

u8 __iomem *base;

463

u32 tmp;

463

u32 tmp;

464

u8 pos;

464

u8 pos;

465

466

for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;

466

for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;

467

pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {

467

pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {

468

u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);

468

u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);

469

if (id == PCI_CAP_ID_HT) {

469

if (id == PCI_CAP_ID_HT) {

470

id = readb(devbase + pos + 3);

470

id = readb(devbase + pos + 3);

471

if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)

471

if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)

472

break;

472

break;

473

}

473

}

474

}

474

}

475

if (pos == 0)

475

if (pos == 0)

476

return;

476

return;

477

478

base = devbase + pos;

478

base = devbase + pos;

479

writeb(0x01, base + 2);

479

writeb(0x01, base + 2);

480

n = (readl(base + 4) >> 16) & 0xff;

480

n = (readl(base + 4) >> 16) & 0xff;

481

482

printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"

482

printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"

483

" has %d irqs\n",

483

" has %d irqs\n",

484

devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);

484

devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);

485

486

for (i = 0; i <= n; i++) {

486

for (i = 0; i <= n; i++) {

487

writeb(0x10 + 2 * i, base + 2);

487

writeb(0x10 + 2 * i, base + 2);

488

tmp = readl(base + 4);

488

tmp = readl(base + 4);

489

irq = (tmp >> 16) & 0xff;

489

irq = (tmp >> 16) & 0xff;

490

DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);

490

DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);

491

/* mask it , will be unmasked later */

491

/* mask it , will be unmasked later */

492

tmp |= 0x1;

492

tmp |= 0x1;

493

writel(tmp, base + 4);

493

writel(tmp, base + 4);

494

mpic->fixups[irq].index = i;

494

mpic->fixups[irq].index = i;

495

mpic->fixups[irq].base = base;

495

mpic->fixups[irq].base = base;

496

/* Apple HT PIC has a non-standard way of doing EOIs */

496

/* Apple HT PIC has a non-standard way of doing EOIs */

497

if ((vdid & 0xffff) == 0x106b)

497

if ((vdid & 0xffff) == 0x106b)

498

mpic->fixups[irq].applebase = devbase + 0x60;

498

mpic->fixups[irq].applebase = devbase + 0x60;

499

else

499

else

500

mpic->fixups[irq].applebase = NULL;

500

mpic->fixups[irq].applebase = NULL;

501

writeb(0x11 + 2 * i, base + 2);

501

writeb(0x11 + 2 * i, base + 2);

502

mpic->fixups[irq].data = readl(base + 4) | 0x80000000;

502

mpic->fixups[irq].data = readl(base + 4) | 0x80000000;

503

}

503

}

504

}

504

}

505

506

507

static void __init mpic_scan_ht_pics(struct mpic *mpic)

507

static void __init mpic_scan_ht_pics(struct mpic *mpic)

508

{

508

{

509

unsigned int devfn;

509

unsigned int devfn;

510

u8 __iomem *cfgspace;

510

u8 __iomem *cfgspace;

511

512

printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");

512

printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");

513

514

/* Allocate fixups array */

514

/* Allocate fixups array */

515

mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);

515

mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);

516

BUG_ON(mpic->fixups == NULL);

516

BUG_ON(mpic->fixups == NULL);

517

518

/* Init spinlock */

518

/* Init spinlock */

519

raw_spin_lock_init(&mpic->fixup_lock);

519

raw_spin_lock_init(&mpic->fixup_lock);

520

521

/* Map U3 config space. We assume all IO-APICs are on the primary bus

521

/* Map U3 config space. We assume all IO-APICs are on the primary bus

522

* so we only need to map 64kB.

522

* so we only need to map 64kB.

523

*/

523

*/

524

cfgspace = ioremap(0xf2000000, 0x10000);

524

cfgspace = ioremap(0xf2000000, 0x10000);

525

BUG_ON(cfgspace == NULL);

525

BUG_ON(cfgspace == NULL);

526

527

/* Now we scan all slots. We do a very quick scan, we read the header

527

/* Now we scan all slots. We do a very quick scan, we read the header

528

* type, vendor ID and device ID only, that's plenty enough

528

* type, vendor ID and device ID only, that's plenty enough

529

*/

529

*/

530

for (devfn = 0; devfn < 0x100; devfn++) {

530

for (devfn = 0; devfn < 0x100; devfn++) {

531

u8 __iomem *devbase = cfgspace + (devfn << 8);

531

u8 __iomem *devbase = cfgspace + (devfn << 8);

532

u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);

532

u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);

533

u32 l = readl(devbase + PCI_VENDOR_ID);

533

u32 l = readl(devbase + PCI_VENDOR_ID);

534

u16 s;

534

u16 s;

535

536

DBG("devfn %x, l: %x\n", devfn, l);

536

DBG("devfn %x, l: %x\n", devfn, l);

537

538

/* If no device, skip */

538

/* If no device, skip */

539

if (l == 0xffffffff || l == 0x00000000 ||

539

if (l == 0xffffffff || l == 0x00000000 ||

540

l == 0x0000ffff || l == 0xffff0000)

540

l == 0x0000ffff || l == 0xffff0000)

541

goto next;

541

goto next;

542

/* Check if is supports capability lists */

542

/* Check if is supports capability lists */

543

s = readw(devbase + PCI_STATUS);

543

s = readw(devbase + PCI_STATUS);

544

if (!(s & PCI_STATUS_CAP_LIST))

544

if (!(s & PCI_STATUS_CAP_LIST))

545

goto next;

545

goto next;

546

547

mpic_scan_ht_pic(mpic, devbase, devfn, l);

547

mpic_scan_ht_pic(mpic, devbase, devfn, l);

548

mpic_scan_ht_msi(mpic, devbase, devfn);

548

mpic_scan_ht_msi(mpic, devbase, devfn);

549

550

/* next device, if function 0 */

551

/* next device, if function 0 */

552

if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)

552

if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)

553

devfn += 7;

553

devfn += 7;

554

}

554

}

555

}

555

}

556

557

#else /* CONFIG_MPIC_U3_HT_IRQS */

557

#else /* CONFIG_MPIC_U3_HT_IRQS */

558

559

static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)

559

static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)

560

{

560

{

561

return 0;

561

return 0;

562

}

562

}

563

564

static void __init mpic_scan_ht_pics(struct mpic *mpic)

564

static void __init mpic_scan_ht_pics(struct mpic *mpic)

565

{

565

{

566

}

566

}

567

568

#endif /* CONFIG_MPIC_U3_HT_IRQS */

568

#endif /* CONFIG_MPIC_U3_HT_IRQS */

569

570

#ifdef CONFIG_SMP

570

#ifdef CONFIG_SMP

571

static int irq_choose_cpu(const struct cpumask *mask)

571

static int irq_choose_cpu(const struct cpumask *mask)

572

{

572

{

573

int cpuid;

573

int cpuid;

574

575

if (cpumask_equal(mask, cpu_all_mask)) {

575

if (cpumask_equal(mask, cpu_all_mask)) {

576

static int irq_rover = 0;

576

static int irq_rover = 0;

577

static DEFINE_RAW_SPINLOCK(irq_rover_lock);

577

static DEFINE_RAW_SPINLOCK(irq_rover_lock);

578

unsigned long flags;

578

unsigned long flags;

579

580

/* Round-robin distribution... */

580

/* Round-robin distribution... */

581

do_round_robin:

581

do_round_robin:

582

raw_spin_lock_irqsave(&irq_rover_lock, flags);

582

raw_spin_lock_irqsave(&irq_rover_lock, flags);

583

584

irq_rover = cpumask_next(irq_rover, cpu_online_mask);

584

irq_rover = cpumask_next(irq_rover, cpu_online_mask);

585

if (irq_rover >= nr_cpu_ids)

585

if (irq_rover >= nr_cpu_ids)

586

irq_rover = cpumask_first(cpu_online_mask);

586

irq_rover = cpumask_first(cpu_online_mask);

587

588

cpuid = irq_rover;

588

cpuid = irq_rover;

589

590

raw_spin_unlock_irqrestore(&irq_rover_lock, flags);

590

raw_spin_unlock_irqrestore(&irq_rover_lock, flags);

591

} else {

591

} else {

592

cpuid = cpumask_first_and(mask, cpu_online_mask);

592

cpuid = cpumask_first_and(mask, cpu_online_mask);

593

if (cpuid >= nr_cpu_ids)

593

if (cpuid >= nr_cpu_ids)

594

goto do_round_robin;

594

goto do_round_robin;

595

}

595

}

596

597

return get_hard_smp_processor_id(cpuid);

597

return get_hard_smp_processor_id(cpuid);

598

}

598

}

599

#else

599

#else

600

static int irq_choose_cpu(const struct cpumask *mask)

600

static int irq_choose_cpu(const struct cpumask *mask)

601

{

601

{

602

return hard_smp_processor_id();

602

return hard_smp_processor_id();

603

}

603

}

604

#endif

604

#endif

605

606

#define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)

606

#define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)

607

608

/* Find an mpic associated with a given linux interrupt */

608

/* Find an mpic associated with a given linux interrupt */

609

static struct mpic *mpic_find(unsigned int irq)

609

static struct mpic *mpic_find(unsigned int irq)

610

{

610

{

611

if (irq < NUM_ISA_INTERRUPTS)

611

if (irq < NUM_ISA_INTERRUPTS)

612

return NULL;

612

return NULL;

613

614

return irq_to_desc(irq)->chip_data;

614

return irq_to_desc(irq)->chip_data;

615

}

615

}

616

617

/* Determine if the linux irq is an IPI */

617

/* Determine if the linux irq is an IPI */

618

static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)

618

static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)

619

{

619

{

620

unsigned int src = mpic_irq_to_hw(irq);

620

unsigned int src = mpic_irq_to_hw(irq);

621

622

return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);

622

return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);

623

}

623

}

624

625

626

/* Convert a cpu mask from logical to physical cpu numbers. */

626

/* Convert a cpu mask from logical to physical cpu numbers. */

627

static inline u32 mpic_physmask(u32 cpumask)

627

static inline u32 mpic_physmask(u32 cpumask)

628

{

628

{

629

int i;

629

int i;

630

u32 mask = 0;

630

u32 mask = 0;

631

632

for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)

632

for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)

633

mask |= (cpumask & 1) << get_hard_smp_processor_id(i);

633

mask |= (cpumask & 1) << get_hard_smp_processor_id(i);

634

return mask;

634

return mask;

635

}

635

}

636

637

#ifdef CONFIG_SMP

637

#ifdef CONFIG_SMP

638

/* Get the mpic structure from the IPI number */

638

/* Get the mpic structure from the IPI number */

639

static inline struct mpic * mpic_from_ipi(unsigned int ipi)

639

static inline struct mpic * mpic_from_ipi(unsigned int ipi)

640

{

640

{

641

return irq_to_desc(ipi)->chip_data;

641

return irq_to_desc(ipi)->chip_data;

642

}

642

}

643

#endif

643

#endif

644

645

/* Get the mpic structure from the irq number */

645

/* Get the mpic structure from the irq number */

646

static inline struct mpic * mpic_from_irq(unsigned int irq)

646

static inline struct mpic * mpic_from_irq(unsigned int irq)

647

{

647

{

648

return irq_to_desc(irq)->chip_data;

648

return irq_to_desc(irq)->chip_data;

649

}

649

}

650

651

/* Send an EOI */

651

/* Send an EOI */

652

static inline void mpic_eoi(struct mpic *mpic)

652

static inline void mpic_eoi(struct mpic *mpic)

653

{

653

{

654

mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);

654

mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);

655

(void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));

655

(void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));

656

}

656

}

657

658

/*

658

/*

659

* Linux descriptor level callbacks

659

* Linux descriptor level callbacks

660

*/

660

*/

661

662

663

void mpic_unmask_irq(unsigned int irq)

663

void mpic_unmask_irq(unsigned int irq)

664

{

664

{

665

unsigned int loops = 100000;

665

unsigned int loops = 100000;

666

struct mpic *mpic = mpic_from_irq(irq);

666

struct mpic *mpic = mpic_from_irq(irq);

667

unsigned int src = mpic_irq_to_hw(irq);

667

unsigned int src = mpic_irq_to_hw(irq);

668

669

DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);

669

DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);

670

671

mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),

671

mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),

672

mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &

672

mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &

673

~MPIC_VECPRI_MASK);

673

~MPIC_VECPRI_MASK);

674

/* make sure mask gets to controller before we return to user */

674

/* make sure mask gets to controller before we return to user */

675

do {

675

do {

676

if (!loops--) {

676

if (!loops--) {

677

printk(KERN_ERR "mpic_enable_irq timeout\n");

677

printk(KERN_ERR "%s: timeout on hwirq %u\n",

678

__func__, src);

678

break;

679

break;

679

}

680

}

680

} while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);

681

} while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);

681

}

682

}

682

683

void mpic_mask_irq(unsigned int irq)

684

void mpic_mask_irq(unsigned int irq)

684

{

685

{

685

unsigned int loops = 100000;

686

unsigned int loops = 100000;

686

struct mpic *mpic = mpic_from_irq(irq);

687

struct mpic *mpic = mpic_from_irq(irq);

687

unsigned int src = mpic_irq_to_hw(irq);

688

unsigned int src = mpic_irq_to_hw(irq);

688

689

DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);

690

DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);

690

691

mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),

692

mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),

692

mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |

693

mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |

693

MPIC_VECPRI_MASK);

694

MPIC_VECPRI_MASK);

694

695

/* make sure mask gets to controller before we return to user */

696

/* make sure mask gets to controller before we return to user */

696

do {

697

do {

697

if (!loops--) {

698

if (!loops--) {

698

printk(KERN_ERR "mpic_enable_irq timeout\n");

699

printk(KERN_ERR "%s: timeout on hwirq %u\n",

700

__func__, src);

699

break;

701

break;

700

}

702

}

701

} while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));

703

} while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));

702

}

704

}

703

705

704

void mpic_end_irq(unsigned int irq)

706

void mpic_end_irq(unsigned int irq)

705

{

707

{

706

struct mpic *mpic = mpic_from_irq(irq);

708

struct mpic *mpic = mpic_from_irq(irq);

707

709

708

#ifdef DEBUG_IRQ

710

#ifdef DEBUG_IRQ

709

DBG("%s: end_irq: %d\n", mpic->name, irq);

711

DBG("%s: end_irq: %d\n", mpic->name, irq);

710

#endif

712

#endif

711

/* We always EOI on end_irq() even for edge interrupts since that

713

/* We always EOI on end_irq() even for edge interrupts since that

712

* should only lower the priority, the MPIC should have properly

714

* should only lower the priority, the MPIC should have properly

713

* latched another edge interrupt coming in anyway

715

* latched another edge interrupt coming in anyway

714

*/

716

*/

715

717

716

mpic_eoi(mpic);

718

mpic_eoi(mpic);

717

}

719

}

718

720

719

#ifdef CONFIG_MPIC_U3_HT_IRQS

721

#ifdef CONFIG_MPIC_U3_HT_IRQS

720

722

721

static void mpic_unmask_ht_irq(unsigned int irq)

723

static void mpic_unmask_ht_irq(unsigned int irq)

722

{

724

{

723

struct mpic *mpic = mpic_from_irq(irq);

725

struct mpic *mpic = mpic_from_irq(irq);

724

unsigned int src = mpic_irq_to_hw(irq);

726

unsigned int src = mpic_irq_to_hw(irq);

725

727

726

mpic_unmask_irq(irq);

728

mpic_unmask_irq(irq);

727

729

728

if (irq_to_desc(irq)->status & IRQ_LEVEL)

730

if (irq_to_desc(irq)->status & IRQ_LEVEL)

729

mpic_ht_end_irq(mpic, src);

731

mpic_ht_end_irq(mpic, src);

730

}

732

}

731

733

732

static unsigned int mpic_startup_ht_irq(unsigned int irq)

734

static unsigned int mpic_startup_ht_irq(unsigned int irq)

733

{

735

{

734

struct mpic *mpic = mpic_from_irq(irq);

736

struct mpic *mpic = mpic_from_irq(irq);

735

unsigned int src = mpic_irq_to_hw(irq);

737

unsigned int src = mpic_irq_to_hw(irq);

736

738

737

mpic_unmask_irq(irq);

739

mpic_unmask_irq(irq);

738

mpic_startup_ht_interrupt(mpic, src, irq_to_desc(irq)->status);

740

mpic_startup_ht_interrupt(mpic, src, irq_to_desc(irq)->status);

739

741

740

return 0;

742

return 0;

741

}

743

}

742

744

743

static void mpic_shutdown_ht_irq(unsigned int irq)

745

static void mpic_shutdown_ht_irq(unsigned int irq)

744

{

746

{

745

struct mpic *mpic = mpic_from_irq(irq);

747

struct mpic *mpic = mpic_from_irq(irq);

746

unsigned int src = mpic_irq_to_hw(irq);

748

unsigned int src = mpic_irq_to_hw(irq);

747

749

748

mpic_shutdown_ht_interrupt(mpic, src, irq_to_desc(irq)->status);

750

mpic_shutdown_ht_interrupt(mpic, src, irq_to_desc(irq)->status);

749

mpic_mask_irq(irq);

751

mpic_mask_irq(irq);

750

}

752

}

751

753

752

static void mpic_end_ht_irq(unsigned int irq)

754

static void mpic_end_ht_irq(unsigned int irq)

753

{

755

{

754

struct mpic *mpic = mpic_from_irq(irq);

756

struct mpic *mpic = mpic_from_irq(irq);

755

unsigned int src = mpic_irq_to_hw(irq);

757

unsigned int src = mpic_irq_to_hw(irq);

756

758

757

#ifdef DEBUG_IRQ

759

#ifdef DEBUG_IRQ

758

DBG("%s: end_irq: %d\n", mpic->name, irq);

760

DBG("%s: end_irq: %d\n", mpic->name, irq);

759

#endif

761

#endif

760

/* We always EOI on end_irq() even for edge interrupts since that

762

/* We always EOI on end_irq() even for edge interrupts since that

761

* should only lower the priority, the MPIC should have properly

763

* should only lower the priority, the MPIC should have properly

762

* latched another edge interrupt coming in anyway

764

* latched another edge interrupt coming in anyway

763

*/

765

*/

764

766

765

if (irq_to_desc(irq)->status & IRQ_LEVEL)

767

if (irq_to_desc(irq)->status & IRQ_LEVEL)

766

mpic_ht_end_irq(mpic, src);

768

mpic_ht_end_irq(mpic, src);

767

mpic_eoi(mpic);

769

mpic_eoi(mpic);

768

}

770

}

769

#endif /* !CONFIG_MPIC_U3_HT_IRQS */

771

#endif /* !CONFIG_MPIC_U3_HT_IRQS */

770

772

771

#ifdef CONFIG_SMP

773

#ifdef CONFIG_SMP

772

774

773

static void mpic_unmask_ipi(unsigned int irq)

775

static void mpic_unmask_ipi(unsigned int irq)

774

{

776

{

775

struct mpic *mpic = mpic_from_ipi(irq);

777

struct mpic *mpic = mpic_from_ipi(irq);

776

unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0];

778

unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0];

777

779

778

DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);

780

DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);

779

mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);

781

mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);

780

}

782

}

781

783

782

static void mpic_mask_ipi(unsigned int irq)

784

static void mpic_mask_ipi(unsigned int irq)

783

{

785

{

784

/* NEVER disable an IPI... that's just plain wrong! */

786

/* NEVER disable an IPI... that's just plain wrong! */

785

}

787

}

786

788

787

static void mpic_end_ipi(unsigned int irq)

789

static void mpic_end_ipi(unsigned int irq)

788

{

790

{

789

struct mpic *mpic = mpic_from_ipi(irq);

791

struct mpic *mpic = mpic_from_ipi(irq);

790

792

791

/*

793

/*

792

* IPIs are marked IRQ_PER_CPU. This has the side effect of

794

* IPIs are marked IRQ_PER_CPU. This has the side effect of

793

* preventing the IRQ_PENDING/IRQ_INPROGRESS logic from

795

* preventing the IRQ_PENDING/IRQ_INPROGRESS logic from

794

* applying to them. We EOI them late to avoid re-entering.

796

* applying to them. We EOI them late to avoid re-entering.

795

* We mark IPI's with IRQF_DISABLED as they must run with

797

* We mark IPI's with IRQF_DISABLED as they must run with

796

* irqs disabled.

798

* irqs disabled.

797

*/

799

*/

798

mpic_eoi(mpic);

800

mpic_eoi(mpic);

799

}

801

}

800

802

801

#endif /* CONFIG_SMP */

803

#endif /* CONFIG_SMP */

802

804

803

int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask)

805

int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask)

804

{

806

{

805

struct mpic *mpic = mpic_from_irq(irq);

807

struct mpic *mpic = mpic_from_irq(irq);

806

unsigned int src = mpic_irq_to_hw(irq);

808

unsigned int src = mpic_irq_to_hw(irq);

807

809

808

if (mpic->flags & MPIC_SINGLE_DEST_CPU) {

810

if (mpic->flags & MPIC_SINGLE_DEST_CPU) {

809

int cpuid = irq_choose_cpu(cpumask);

811

int cpuid = irq_choose_cpu(cpumask);

810

812

811

mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);

813

mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);

812

} else {

814

} else {

813

cpumask_var_t tmp;

815

cpumask_var_t tmp;

814

816

815

alloc_cpumask_var(&tmp, GFP_KERNEL);

817

alloc_cpumask_var(&tmp, GFP_KERNEL);

816

818

817

cpumask_and(tmp, cpumask, cpu_online_mask);

819

cpumask_and(tmp, cpumask, cpu_online_mask);

818

820

819

mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),

821

mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),

820

mpic_physmask(cpumask_bits(tmp)[0]));

822

mpic_physmask(cpumask_bits(tmp)[0]));

821

823

822

free_cpumask_var(tmp);

824

free_cpumask_var(tmp);

823

}

825

}

824

826

825

return 0;

827

return 0;

826

}

828

}

827

829

828

static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)

830

static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)

829

{

831

{

830

/* Now convert sense value */

832

/* Now convert sense value */

831

switch(type & IRQ_TYPE_SENSE_MASK) {

833

switch(type & IRQ_TYPE_SENSE_MASK) {

832

case IRQ_TYPE_EDGE_RISING:

834

case IRQ_TYPE_EDGE_RISING:

833

return MPIC_INFO(VECPRI_SENSE_EDGE) |

835

return MPIC_INFO(VECPRI_SENSE_EDGE) |

834

MPIC_INFO(VECPRI_POLARITY_POSITIVE);

836

MPIC_INFO(VECPRI_POLARITY_POSITIVE);

835

case IRQ_TYPE_EDGE_FALLING:

837

case IRQ_TYPE_EDGE_FALLING:

836

case IRQ_TYPE_EDGE_BOTH:

838

case IRQ_TYPE_EDGE_BOTH:

837

return MPIC_INFO(VECPRI_SENSE_EDGE) |

839

return MPIC_INFO(VECPRI_SENSE_EDGE) |

838

MPIC_INFO(VECPRI_POLARITY_NEGATIVE);

840

MPIC_INFO(VECPRI_POLARITY_NEGATIVE);

839

case IRQ_TYPE_LEVEL_HIGH:

841

case IRQ_TYPE_LEVEL_HIGH:

840

return MPIC_INFO(VECPRI_SENSE_LEVEL) |

842

return MPIC_INFO(VECPRI_SENSE_LEVEL) |

841

MPIC_INFO(VECPRI_POLARITY_POSITIVE);

843

MPIC_INFO(VECPRI_POLARITY_POSITIVE);

842

case IRQ_TYPE_LEVEL_LOW:

844

case IRQ_TYPE_LEVEL_LOW:

843

default:

845

default:

844

return MPIC_INFO(VECPRI_SENSE_LEVEL) |

846

return MPIC_INFO(VECPRI_SENSE_LEVEL) |

845

MPIC_INFO(VECPRI_POLARITY_NEGATIVE);

847

MPIC_INFO(VECPRI_POLARITY_NEGATIVE);

846

}

848

}

847

}

849

}

848

850

849

int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)

851

int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)

850

{

852

{

851

struct mpic *mpic = mpic_from_irq(virq);

853

struct mpic *mpic = mpic_from_irq(virq);

852

unsigned int src = mpic_irq_to_hw(virq);

854

unsigned int src = mpic_irq_to_hw(virq);

853

struct irq_desc *desc = irq_to_desc(virq);

855

struct irq_desc *desc = irq_to_desc(virq);

854

unsigned int vecpri, vold, vnew;

856

unsigned int vecpri, vold, vnew;

855

857

856

DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",

858

DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",

857

mpic, virq, src, flow_type);

859

mpic, virq, src, flow_type);

858

860

859

if (src >= mpic->irq_count)

861

if (src >= mpic->irq_count)

860

return -EINVAL;

862

return -EINVAL;

861

863

862

if (flow_type == IRQ_TYPE_NONE)

864

if (flow_type == IRQ_TYPE_NONE)

863

if (mpic->senses && src < mpic->senses_count)

865

if (mpic->senses && src < mpic->senses_count)

864

flow_type = mpic->senses[src];

866

flow_type = mpic->senses[src];

865

if (flow_type == IRQ_TYPE_NONE)

867

if (flow_type == IRQ_TYPE_NONE)

866

flow_type = IRQ_TYPE_LEVEL_LOW;

868

flow_type = IRQ_TYPE_LEVEL_LOW;

867

869

868

desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);

870

desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);

869

desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;

871

desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;

870

if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))

872

if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))

871

desc->status |= IRQ_LEVEL;

873

desc->status |= IRQ_LEVEL;

872

874

873

if (mpic_is_ht_interrupt(mpic, src))

875

if (mpic_is_ht_interrupt(mpic, src))

874

vecpri = MPIC_VECPRI_POLARITY_POSITIVE |

876

vecpri = MPIC_VECPRI_POLARITY_POSITIVE |

875

MPIC_VECPRI_SENSE_EDGE;

877

MPIC_VECPRI_SENSE_EDGE;

876

else

878

else

877

vecpri = mpic_type_to_vecpri(mpic, flow_type);

879

vecpri = mpic_type_to_vecpri(mpic, flow_type);

878

880

879

vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));

881

vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));

880

vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |

882

vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |

881

MPIC_INFO(VECPRI_SENSE_MASK));

883

MPIC_INFO(VECPRI_SENSE_MASK));

882

vnew |= vecpri;

884

vnew |= vecpri;

883

if (vold != vnew)

885

if (vold != vnew)

884

mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);

886

mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);

885

887

886

return 0;

888

return 0;

887

}

889

}

888

890

889

void mpic_set_vector(unsigned int virq, unsigned int vector)

891

void mpic_set_vector(unsigned int virq, unsigned int vector)

890

{

892

{

891

struct mpic *mpic = mpic_from_irq(virq);

893

struct mpic *mpic = mpic_from_irq(virq);

892

unsigned int src = mpic_irq_to_hw(virq);

894

unsigned int src = mpic_irq_to_hw(virq);

893

unsigned int vecpri;

895

unsigned int vecpri;

894

896

895

DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",

897

DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",

896

mpic, virq, src, vector);

898

mpic, virq, src, vector);

897

899

898

if (src >= mpic->irq_count)

900

if (src >= mpic->irq_count)

899

return;

901

return;

900

902

901

vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));

903

vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));

902

vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);

904

vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);

903

vecpri |= vector;

905

vecpri |= vector;

904

mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);

906

mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);

905

}

907

}

906

908

907

static struct irq_chip mpic_irq_chip = {

909

static struct irq_chip mpic_irq_chip = {

908

.mask = mpic_mask_irq,

910

.mask = mpic_mask_irq,

909

.unmask = mpic_unmask_irq,

911

.unmask = mpic_unmask_irq,

910

.eoi = mpic_end_irq,

912

.eoi = mpic_end_irq,

911

.set_type = mpic_set_irq_type,

913

.set_type = mpic_set_irq_type,

912

};

914

};

913

915

914

#ifdef CONFIG_SMP

916

#ifdef CONFIG_SMP

915

static struct irq_chip mpic_ipi_chip = {

917

static struct irq_chip mpic_ipi_chip = {

916

.mask = mpic_mask_ipi,

918

.mask = mpic_mask_ipi,

917

.unmask = mpic_unmask_ipi,

919

.unmask = mpic_unmask_ipi,

918

.eoi = mpic_end_ipi,

920

.eoi = mpic_end_ipi,

919

};

921

};

920

#endif /* CONFIG_SMP */

922

#endif /* CONFIG_SMP */

921

923

922

#ifdef CONFIG_MPIC_U3_HT_IRQS

924

#ifdef CONFIG_MPIC_U3_HT_IRQS

923

static struct irq_chip mpic_irq_ht_chip = {

925

static struct irq_chip mpic_irq_ht_chip = {

924

.startup = mpic_startup_ht_irq,

926

.startup = mpic_startup_ht_irq,

925

.shutdown = mpic_shutdown_ht_irq,

927

.shutdown = mpic_shutdown_ht_irq,

926

.mask = mpic_mask_irq,

928

.mask = mpic_mask_irq,

927

.unmask = mpic_unmask_ht_irq,

929

.unmask = mpic_unmask_ht_irq,

928

.eoi = mpic_end_ht_irq,

930

.eoi = mpic_end_ht_irq,

929

.set_type = mpic_set_irq_type,

931

.set_type = mpic_set_irq_type,

930

};

932

};

931

#endif /* CONFIG_MPIC_U3_HT_IRQS */

933

#endif /* CONFIG_MPIC_U3_HT_IRQS */

932

934

933

935

934

static int mpic_host_match(struct irq_host *h, struct device_node *node)

936

static int mpic_host_match(struct irq_host *h, struct device_node *node)

935

{

937

{

936

/* Exact match, unless mpic node is NULL */

938

/* Exact match, unless mpic node is NULL */

937

return h->of_node == NULL || h->of_node == node;

939

return h->of_node == NULL || h->of_node == node;

938

}

940

}

939

941

940

static int mpic_host_map(struct irq_host *h, unsigned int virq,

942

static int mpic_host_map(struct irq_host *h, unsigned int virq,

941

irq_hw_number_t hw)

943

irq_hw_number_t hw)

942

{

944

{

943

struct mpic *mpic = h->host_data;

945

struct mpic *mpic = h->host_data;

944

struct irq_chip *chip;

946

struct irq_chip *chip;

945

947

946

DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);

948

DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);

947

949

948

if (hw == mpic->spurious_vec)

950

if (hw == mpic->spurious_vec)

949

return -EINVAL;

951

return -EINVAL;

950

if (mpic->protected && test_bit(hw, mpic->protected))

952

if (mpic->protected && test_bit(hw, mpic->protected))

951

return -EINVAL;

953

return -EINVAL;

952

954

953

#ifdef CONFIG_SMP

955

#ifdef CONFIG_SMP

954

else if (hw >= mpic->ipi_vecs[0]) {

956

else if (hw >= mpic->ipi_vecs[0]) {

955

WARN_ON(!(mpic->flags & MPIC_PRIMARY));

957

WARN_ON(!(mpic->flags & MPIC_PRIMARY));

956

958

957

DBG("mpic: mapping as IPI\n");

959

DBG("mpic: mapping as IPI\n");

958

set_irq_chip_data(virq, mpic);

960

set_irq_chip_data(virq, mpic);

959

set_irq_chip_and_handler(virq, &mpic->hc_ipi,

961

set_irq_chip_and_handler(virq, &mpic->hc_ipi,

960

handle_percpu_irq);

962

handle_percpu_irq);

961

return 0;

963

return 0;

962

}

964

}

963

#endif /* CONFIG_SMP */

965

#endif /* CONFIG_SMP */

964

966

965

if (hw >= mpic->irq_count)

967

if (hw >= mpic->irq_count)

966

return -EINVAL;

968

return -EINVAL;

967

969

968

mpic_msi_reserve_hwirq(mpic, hw);

970

mpic_msi_reserve_hwirq(mpic, hw);

969

971

970

/* Default chip */

972

/* Default chip */

971

chip = &mpic->hc_irq;

973

chip = &mpic->hc_irq;

972

974

973

#ifdef CONFIG_MPIC_U3_HT_IRQS

975

#ifdef CONFIG_MPIC_U3_HT_IRQS

974

/* Check for HT interrupts, override vecpri */

976

/* Check for HT interrupts, override vecpri */

975

if (mpic_is_ht_interrupt(mpic, hw))

977

if (mpic_is_ht_interrupt(mpic, hw))

976

chip = &mpic->hc_ht_irq;

978

chip = &mpic->hc_ht_irq;

977

#endif /* CONFIG_MPIC_U3_HT_IRQS */

979

#endif /* CONFIG_MPIC_U3_HT_IRQS */

978

980

979

DBG("mpic: mapping to irq chip @%p\n", chip);

981

DBG("mpic: mapping to irq chip @%p\n", chip);

980

982

981

set_irq_chip_data(virq, mpic);

983

set_irq_chip_data(virq, mpic);

982

set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq);

984

set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq);

983

985

984

/* Set default irq type */

986

/* Set default irq type */

985

set_irq_type(virq, IRQ_TYPE_NONE);

987

set_irq_type(virq, IRQ_TYPE_NONE);

986

988

987

return 0;

989

return 0;

988

}

990

}

989

991

990

static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,

992

static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,

991

const u32 *intspec, unsigned int intsize,

993

const u32 *intspec, unsigned int intsize,

992

irq_hw_number_t *out_hwirq, unsigned int *out_flags)

994

irq_hw_number_t *out_hwirq, unsigned int *out_flags)

993

995

994

{

996

{

995

static unsigned char map_mpic_senses[4] = {

997

static unsigned char map_mpic_senses[4] = {

996

IRQ_TYPE_EDGE_RISING,

998

IRQ_TYPE_EDGE_RISING,

997

IRQ_TYPE_LEVEL_LOW,

999

IRQ_TYPE_LEVEL_LOW,

998

IRQ_TYPE_LEVEL_HIGH,

1000

IRQ_TYPE_LEVEL_HIGH,

999

IRQ_TYPE_EDGE_FALLING,

1001

IRQ_TYPE_EDGE_FALLING,

1000

};

1002

};

1001

1003

1002

*out_hwirq = intspec[0];

1004

*out_hwirq = intspec[0];

1003

if (intsize > 1) {

1005

if (intsize > 1) {

1004

u32 mask = 0x3;

1006

u32 mask = 0x3;

1005

1007

1006

/* Apple invented a new race of encoding on machines with

1008

/* Apple invented a new race of encoding on machines with

1007

* an HT APIC. They encode, among others, the index within

1009

* an HT APIC. They encode, among others, the index within

1008

* the HT APIC. We don't care about it here since thankfully,

1010

* the HT APIC. We don't care about it here since thankfully,

1009

* it appears that they have the APIC already properly

1011

* it appears that they have the APIC already properly

1010

* configured, and thus our current fixup code that reads the

1012

* configured, and thus our current fixup code that reads the

1011

* APIC config works fine. However, we still need to mask out

1013

* APIC config works fine. However, we still need to mask out

1012

* bits in the specifier to make sure we only get bit 0 which

1014

* bits in the specifier to make sure we only get bit 0 which

1013

* is the level/edge bit (the only sense bit exposed by Apple),

1015

* is the level/edge bit (the only sense bit exposed by Apple),

1014

* as their bit 1 means something else.

1016

* as their bit 1 means something else.

1015

*/

1017

*/

1016

if (machine_is(powermac))

1018

if (machine_is(powermac))

1017

mask = 0x1;

1019

mask = 0x1;

1018

*out_flags = map_mpic_senses[intspec[1] & mask];

1020

*out_flags = map_mpic_senses[intspec[1] & mask];

1019

} else

1021

} else

1020

*out_flags = IRQ_TYPE_NONE;

1022

*out_flags = IRQ_TYPE_NONE;

1021

1023

1022

DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",

1024

DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",

1023

intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);

1025

intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);

1024

1026

1025

return 0;

1027

return 0;

1026

}

1028

}

1027

1029

1028

static struct irq_host_ops mpic_host_ops = {

1030

static struct irq_host_ops mpic_host_ops = {

1029

.match = mpic_host_match,

1031

.match = mpic_host_match,

1030

.map = mpic_host_map,

1032

.map = mpic_host_map,

1031

.xlate = mpic_host_xlate,

1033

.xlate = mpic_host_xlate,

1032

};

1034

};

1033

1035

1034

/*

1036

/*

1035

* Exported functions

1037

* Exported functions

1036

*/

1038

*/

1037

1039

1038

struct mpic * __init mpic_alloc(struct device_node *node,

1040

struct mpic * __init mpic_alloc(struct device_node *node,

1039

phys_addr_t phys_addr,

1041

phys_addr_t phys_addr,

1040

unsigned int flags,

1042

unsigned int flags,

1041

unsigned int isu_size,

1043

unsigned int isu_size,

1042

unsigned int irq_count,

1044

unsigned int irq_count,

1043

const char *name)

1045

const char *name)

1044

{

1046

{

1045

struct mpic *mpic;

1047

struct mpic *mpic;

1046

u32 greg_feature;

1048

u32 greg_feature;

1047

const char *vers;

1049

const char *vers;

1048

int i;

1050

int i;

1049

int intvec_top;

1051

int intvec_top;

1050

u64 paddr = phys_addr;

1052

u64 paddr = phys_addr;

1051

1053

1052

mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);

1054

mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);

1053

if (mpic == NULL)

1055

if (mpic == NULL)

1054

return NULL;

1056

return NULL;

1055

1057

1056

mpic->name = name;

1058

mpic->name = name;

1057

1059

1058

mpic->hc_irq = mpic_irq_chip;

1060

mpic->hc_irq = mpic_irq_chip;

1059

mpic->hc_irq.name = name;

1061

mpic->hc_irq.name = name;

1060

if (flags & MPIC_PRIMARY)

1062

if (flags & MPIC_PRIMARY)

1061

mpic->hc_irq.set_affinity = mpic_set_affinity;

1063

mpic->hc_irq.set_affinity = mpic_set_affinity;

1062

#ifdef CONFIG_MPIC_U3_HT_IRQS

1064

#ifdef CONFIG_MPIC_U3_HT_IRQS

1063

mpic->hc_ht_irq = mpic_irq_ht_chip;

1065

mpic->hc_ht_irq = mpic_irq_ht_chip;

1064

mpic->hc_ht_irq.name = name;

1066

mpic->hc_ht_irq.name = name;

1065

if (flags & MPIC_PRIMARY)

1067

if (flags & MPIC_PRIMARY)

1066

mpic->hc_ht_irq.set_affinity = mpic_set_affinity;

1068

mpic->hc_ht_irq.set_affinity = mpic_set_affinity;

1067

#endif /* CONFIG_MPIC_U3_HT_IRQS */

1069

#endif /* CONFIG_MPIC_U3_HT_IRQS */

1068

1070

1069

#ifdef CONFIG_SMP

1071

#ifdef CONFIG_SMP

1070

mpic->hc_ipi = mpic_ipi_chip;

1072

mpic->hc_ipi = mpic_ipi_chip;

1071

mpic->hc_ipi.name = name;

1073

mpic->hc_ipi.name = name;

1072

#endif /* CONFIG_SMP */

1074

#endif /* CONFIG_SMP */

1073

1075

1074

mpic->flags = flags;

1076

mpic->flags = flags;

1075

mpic->isu_size = isu_size;

1077

mpic->isu_size = isu_size;

1076

mpic->irq_count = irq_count;

1078

mpic->irq_count = irq_count;

1077

mpic->num_sources = 0; /* so far */

1079

mpic->num_sources = 0; /* so far */

1078

1080

1079

if (flags & MPIC_LARGE_VECTORS)

1081

if (flags & MPIC_LARGE_VECTORS)

1080

intvec_top = 2047;

1082

intvec_top = 2047;

1081

else

1083

else

1082

intvec_top = 255;

1084

intvec_top = 255;

1083

1085

1084

mpic->timer_vecs[0] = intvec_top - 8;

1086

mpic->timer_vecs[0] = intvec_top - 8;

1085

mpic->timer_vecs[1] = intvec_top - 7;

1087

mpic->timer_vecs[1] = intvec_top - 7;

1086

mpic->timer_vecs[2] = intvec_top - 6;

1088

mpic->timer_vecs[2] = intvec_top - 6;

1087

mpic->timer_vecs[3] = intvec_top - 5;

1089

mpic->timer_vecs[3] = intvec_top - 5;

1088

mpic->ipi_vecs[0] = intvec_top - 4;

1090

mpic->ipi_vecs[0] = intvec_top - 4;

1089

mpic->ipi_vecs[1] = intvec_top - 3;

1091

mpic->ipi_vecs[1] = intvec_top - 3;

1090

mpic->ipi_vecs[2] = intvec_top - 2;

1092

mpic->ipi_vecs[2] = intvec_top - 2;

1091

mpic->ipi_vecs[3] = intvec_top - 1;

1093

mpic->ipi_vecs[3] = intvec_top - 1;

1092

mpic->spurious_vec = intvec_top;

1094

mpic->spurious_vec = intvec_top;

1093

1095

1094

/* Check for "big-endian" in device-tree */

1096

/* Check for "big-endian" in device-tree */

1095

if (node && of_get_property(node, "big-endian", NULL) != NULL)

1097

if (node && of_get_property(node, "big-endian", NULL) != NULL)

1096

mpic->flags |= MPIC_BIG_ENDIAN;

1098

mpic->flags |= MPIC_BIG_ENDIAN;

1097

1099

1098

/* Look for protected sources */

1100

/* Look for protected sources */

1099

if (node) {

1101

if (node) {

1100

int psize;

1102

int psize;

1101

unsigned int bits, mapsize;

1103

unsigned int bits, mapsize;

1102

const u32 *psrc =

1104

const u32 *psrc =

1103

of_get_property(node, "protected-sources", &psize);

1105

of_get_property(node, "protected-sources", &psize);

1104

if (psrc) {

1106

if (psrc) {

1105

psize /= 4;

1107

psize /= 4;

1106

bits = intvec_top + 1;

1108

bits = intvec_top + 1;

1107

mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long);

1109

mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long);

1108

mpic->protected = kzalloc(mapsize, GFP_KERNEL);

1110

mpic->protected = kzalloc(mapsize, GFP_KERNEL);

1109

BUG_ON(mpic->protected == NULL);

1111

BUG_ON(mpic->protected == NULL);

1110

for (i = 0; i < psize; i++) {

1112

for (i = 0; i < psize; i++) {

1111

if (psrc[i] > intvec_top)

1113

if (psrc[i] > intvec_top)

1112

continue;

1114

continue;

1113

__set_bit(psrc[i], mpic->protected);

1115

__set_bit(psrc[i], mpic->protected);

1114

}

1116

}

1115

}

1117

}

1116

}

1118

}

1117

1119

1118

#ifdef CONFIG_MPIC_WEIRD

1120

#ifdef CONFIG_MPIC_WEIRD

1119

mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];

1121

mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];

1120

#endif

1122

#endif

1121

1123

1122

/* default register type */

1124

/* default register type */

1123

mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?

1125

mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?

1124

mpic_access_mmio_be : mpic_access_mmio_le;

1126

mpic_access_mmio_be : mpic_access_mmio_le;

1125

1127

1126

/* If no physical address is passed in, a device-node is mandatory */

1128

/* If no physical address is passed in, a device-node is mandatory */

1127

BUG_ON(paddr == 0 && node == NULL);

1129

BUG_ON(paddr == 0 && node == NULL);

1128

1130

1129

/* If no physical address passed in, check if it's dcr based */

1131

/* If no physical address passed in, check if it's dcr based */

1130

if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) {

1132

if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) {

1131

#ifdef CONFIG_PPC_DCR

1133

#ifdef CONFIG_PPC_DCR

1132

mpic->flags |= MPIC_USES_DCR;

1134

mpic->flags |= MPIC_USES_DCR;

1133

mpic->reg_type = mpic_access_dcr;

1135

mpic->reg_type = mpic_access_dcr;

1134

#else

1136

#else

1135

BUG();

1137

BUG();

1136

#endif /* CONFIG_PPC_DCR */

1138

#endif /* CONFIG_PPC_DCR */

1137

}

1139

}

1138

1140

1139

/* If the MPIC is not DCR based, and no physical address was passed

1141

/* If the MPIC is not DCR based, and no physical address was passed

1140

* in, try to obtain one

1142

* in, try to obtain one

1141

*/

1143

*/

1142

if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {

1144

if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {

1143

const u32 *reg = of_get_property(node, "reg", NULL);

1145

const u32 *reg = of_get_property(node, "reg", NULL);

1144

BUG_ON(reg == NULL);

1146

BUG_ON(reg == NULL);

1145

paddr = of_translate_address(node, reg);

1147

paddr = of_translate_address(node, reg);

1146

BUG_ON(paddr == OF_BAD_ADDR);

1148

BUG_ON(paddr == OF_BAD_ADDR);

1147

}

1149

}

1148

1150

1149

/* Map the global registers */

1151

/* Map the global registers */

1150

mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);

1152

mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);

1151

mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);

1153

mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);

1152

1154

1153

/* Reset */

1155

/* Reset */

1154

if (flags & MPIC_WANTS_RESET) {

1156

if (flags & MPIC_WANTS_RESET) {

1155

mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),

1157

mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),

1156

mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))

1158

mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))

1157

| MPIC_GREG_GCONF_RESET);

1159

| MPIC_GREG_GCONF_RESET);

1158

while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))

1160

while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))

1159

& MPIC_GREG_GCONF_RESET)

1161

& MPIC_GREG_GCONF_RESET)

1160

mb();

1162

mb();

1161

}

1163

}

1162

1164

1163

/* CoreInt */

1165

/* CoreInt */

1164

if (flags & MPIC_ENABLE_COREINT)

1166

if (flags & MPIC_ENABLE_COREINT)

1165

mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),

1167

mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),

1166

mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))

1168

mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))

1167

| MPIC_GREG_GCONF_COREINT);

1169

| MPIC_GREG_GCONF_COREINT);

1168

1170

1169

if (flags & MPIC_ENABLE_MCK)

1171

if (flags & MPIC_ENABLE_MCK)

1170

mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),

1172

mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),

1171

mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))

1173

mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))

1172

| MPIC_GREG_GCONF_MCK);

1174

| MPIC_GREG_GCONF_MCK);

1173

1175

1174

/* Read feature register, calculate num CPUs and, for non-ISU

1176

/* Read feature register, calculate num CPUs and, for non-ISU

1175

* MPICs, num sources as well. On ISU MPICs, sources are counted

1177

* MPICs, num sources as well. On ISU MPICs, sources are counted

1176

* as ISUs are added

1178

* as ISUs are added

1177

*/

1179

*/

1178

greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));

1180

greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));

1179

mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK)

1181

mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK)

1180

>> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;

1182

>> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;

1181

if (isu_size == 0) {

1183

if (isu_size == 0) {

1182

if (flags & MPIC_BROKEN_FRR_NIRQS)

1184

if (flags & MPIC_BROKEN_FRR_NIRQS)

1183

mpic->num_sources = mpic->irq_count;

1185

mpic->num_sources = mpic->irq_count;

1184

else

1186

else

1185

mpic->num_sources =

1187

mpic->num_sources =

1186

((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)

1188

((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)

1187

>> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;

1189

>> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;

1188

}

1190

}

1189

1191

1190

/* Map the per-CPU registers */

1192

/* Map the per-CPU registers */

1191

for (i = 0; i < mpic->num_cpus; i++) {

1193

for (i = 0; i < mpic->num_cpus; i++) {

1192

mpic_map(mpic, node, paddr, &mpic->cpuregs[i],

1194

mpic_map(mpic, node, paddr, &mpic->cpuregs[i],

1193

MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),

1195

MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),

1194

0x1000);

1196

0x1000);

1195

}

1197

}

1196

1198

1197

/* Initialize main ISU if none provided */

1199

/* Initialize main ISU if none provided */

1198

if (mpic->isu_size == 0) {

1200

if (mpic->isu_size == 0) {

1199

mpic->isu_size = mpic->num_sources;

1201

mpic->isu_size = mpic->num_sources;

1200

mpic_map(mpic, node, paddr, &mpic->isus[0],

1202

mpic_map(mpic, node, paddr, &mpic->isus[0],

1201

MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);

1203

MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);

1202

}

1204

}

1203

mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);

1205

mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);

1204

mpic->isu_mask = (1 << mpic->isu_shift) - 1;

1206

mpic->isu_mask = (1 << mpic->isu_shift) - 1;

1205

1207

1206

mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,

1208

mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,

1207

isu_size ? isu_size : mpic->num_sources,

1209

isu_size ? isu_size : mpic->num_sources,

1208

&mpic_host_ops,

1210

&mpic_host_ops,

1209

flags & MPIC_LARGE_VECTORS ? 2048 : 256);

1211

flags & MPIC_LARGE_VECTORS ? 2048 : 256);

1210

if (mpic->irqhost == NULL)

1212

if (mpic->irqhost == NULL)

1211

return NULL;

1213

return NULL;

1212

1214

1213

mpic->irqhost->host_data = mpic;

1215

mpic->irqhost->host_data = mpic;

1214

1216

1215

/* Display version */

1217

/* Display version */

1216

switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {

1218

switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {

1217

case 1:

1219

case 1:

1218

vers = "1.0";

1220

vers = "1.0";

1219

break;

1221

break;

1220

case 2:

1222

case 2:

1221

vers = "1.2";

1223

vers = "1.2";

1222

break;

1224

break;

1223

case 3:

1225

case 3:

1224

vers = "1.3";

1226

vers = "1.3";

1225

break;

1227

break;

1226

default:

1228

default:

1227

vers = "<unknown>";

1229

vers = "<unknown>";

1228

break;

1230

break;

1229

}

1231

}

1230

printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"

1232

printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"

1231

" max %d CPUs\n",

1233

" max %d CPUs\n",

1232

name, vers, (unsigned long long)paddr, mpic->num_cpus);

1234

name, vers, (unsigned long long)paddr, mpic->num_cpus);

1233

printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",

1235

printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",

1234

mpic->isu_size, mpic->isu_shift, mpic->isu_mask);

1236

mpic->isu_size, mpic->isu_shift, mpic->isu_mask);

1235

1237

1236

mpic->next = mpics;

1238

mpic->next = mpics;

1237

mpics = mpic;

1239

mpics = mpic;

1238

1240

1239

if (flags & MPIC_PRIMARY) {

1241

if (flags & MPIC_PRIMARY) {

1240

mpic_primary = mpic;

1242

mpic_primary = mpic;

1241

irq_set_default_host(mpic->irqhost);

1243

irq_set_default_host(mpic->irqhost);

1242

}

1244

}

1243

1245

1244

return mpic;

1246

return mpic;

1245

}

1247

}

1246

1248

1247

void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,

1249

void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,

1248

phys_addr_t paddr)

1250

phys_addr_t paddr)

1249

{

1251

{

1250

unsigned int isu_first = isu_num * mpic->isu_size;

1252

unsigned int isu_first = isu_num * mpic->isu_size;

1251

1253

1252

BUG_ON(isu_num >= MPIC_MAX_ISU);

1254

BUG_ON(isu_num >= MPIC_MAX_ISU);

1253

1255

1254

mpic_map(mpic, mpic->irqhost->of_node,

1256

mpic_map(mpic, mpic->irqhost->of_node,

1255

paddr, &mpic->isus[isu_num], 0,

1257

paddr, &mpic->isus[isu_num], 0,

1256

MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);

1258

MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);

1257

1259

1258

if ((isu_first + mpic->isu_size) > mpic->num_sources)

1260

if ((isu_first + mpic->isu_size) > mpic->num_sources)

1259

mpic->num_sources = isu_first + mpic->isu_size;

1261

mpic->num_sources = isu_first + mpic->isu_size;

1260

}

1262

}

1261

1263

1262

void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)

1264

void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)

1263

{

1265

{

1264

mpic->senses = senses;

1266

mpic->senses = senses;

1265

mpic->senses_count = count;

1267

mpic->senses_count = count;

1266

}

1268

}

1267

1269

1268

void __init mpic_init(struct mpic *mpic)

1270

void __init mpic_init(struct mpic *mpic)

1269

{

1271

{

1270

int i;

1272

int i;

1271

int cpu;

1273

int cpu;

1272

1274

1273

BUG_ON(mpic->num_sources == 0);

1275

BUG_ON(mpic->num_sources == 0);

1274

1276

1275

printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);

1277

printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);

1276

1278

1277

/* Set current processor priority to max */

1279

/* Set current processor priority to max */

1278

mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);

1280

mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);

1279

1281

1280

/* Initialize timers: just disable them all */

1282

/* Initialize timers: just disable them all */

1281

for (i = 0; i < 4; i++) {

1283

for (i = 0; i < 4; i++) {

1282

mpic_write(mpic->tmregs,

1284

mpic_write(mpic->tmregs,

1283

i * MPIC_INFO(TIMER_STRIDE) +

1285

i * MPIC_INFO(TIMER_STRIDE) +

1284

MPIC_INFO(TIMER_DESTINATION), 0);

1286

MPIC_INFO(TIMER_DESTINATION), 0);

1285

mpic_write(mpic->tmregs,

1287

mpic_write(mpic->tmregs,

1286

i * MPIC_INFO(TIMER_STRIDE) +

1288

i * MPIC_INFO(TIMER_STRIDE) +

1287

MPIC_INFO(TIMER_VECTOR_PRI),

1289

MPIC_INFO(TIMER_VECTOR_PRI),

1288

MPIC_VECPRI_MASK |

1290

MPIC_VECPRI_MASK |

1289

(mpic->timer_vecs[0] + i));

1291

(mpic->timer_vecs[0] + i));

1290

}

1292

}

1291

1293

1292

/* Initialize IPIs to our reserved vectors and mark them disabled for now */

1294

/* Initialize IPIs to our reserved vectors and mark them disabled for now */

1293

mpic_test_broken_ipi(mpic);

1295

mpic_test_broken_ipi(mpic);

1294

for (i = 0; i < 4; i++) {

1296

for (i = 0; i < 4; i++) {

1295

mpic_ipi_write(i,

1297

mpic_ipi_write(i,

1296

MPIC_VECPRI_MASK |

1298

MPIC_VECPRI_MASK |

1297

(10 << MPIC_VECPRI_PRIORITY_SHIFT) |

1299

(10 << MPIC_VECPRI_PRIORITY_SHIFT) |

1298

(mpic->ipi_vecs[0] + i));

1300

(mpic->ipi_vecs[0] + i));

1299

}

1301

}

1300

1302

1301

/* Initialize interrupt sources */

1303

/* Initialize interrupt sources */

1302

if (mpic->irq_count == 0)

1304

if (mpic->irq_count == 0)

1303

mpic->irq_count = mpic->num_sources;

1305

mpic->irq_count = mpic->num_sources;

1304

1306

1305

/* Do the HT PIC fixups on U3 broken mpic */

1307

/* Do the HT PIC fixups on U3 broken mpic */

1306

DBG("MPIC flags: %x\n", mpic->flags);

1308

DBG("MPIC flags: %x\n", mpic->flags);

1307

if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {

1309

if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {

1308

mpic_scan_ht_pics(mpic);

1310

mpic_scan_ht_pics(mpic);

1309

mpic_u3msi_init(mpic);

1311

mpic_u3msi_init(mpic);

1310

}

1312

}

1311

1313

1312

mpic_pasemi_msi_init(mpic);

1314

mpic_pasemi_msi_init(mpic);

1313

1315

1314

if (mpic->flags & MPIC_PRIMARY)

1316

if (mpic->flags & MPIC_PRIMARY)

1315

cpu = hard_smp_processor_id();

1317

cpu = hard_smp_processor_id();

1316

else

1318

else

1317

cpu = 0;

1319

cpu = 0;

1318

1320

1319

for (i = 0; i < mpic->num_sources; i++) {

1321

for (i = 0; i < mpic->num_sources; i++) {

1320

/* start with vector = source number, and masked */

1322

/* start with vector = source number, and masked */

1321

u32 vecpri = MPIC_VECPRI_MASK | i |

1323

u32 vecpri = MPIC_VECPRI_MASK | i |

1322

(8 << MPIC_VECPRI_PRIORITY_SHIFT);

1324

(8 << MPIC_VECPRI_PRIORITY_SHIFT);

1323

1325

1324

/* check if protected */

1326

/* check if protected */

1325

if (mpic->protected && test_bit(i, mpic->protected))

1327

if (mpic->protected && test_bit(i, mpic->protected))

1326

continue;

1328

continue;

1327

/* init hw */

1329

/* init hw */

1328

mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);

1330

mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);

1329

mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);

1331

mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);

1330

}

1332

}

1331

1333

1332

/* Init spurious vector */

1334

/* Init spurious vector */

1333

mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);

1335

mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);

1334

1336

1335

/* Disable 8259 passthrough, if supported */

1337

/* Disable 8259 passthrough, if supported */

1336

if (!(mpic->flags & MPIC_NO_PTHROU_DIS))

1338

if (!(mpic->flags & MPIC_NO_PTHROU_DIS))

1337

mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),

1339

mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),

1338

mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))

1340

mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))

1339

| MPIC_GREG_GCONF_8259_PTHROU_DIS);

1341

| MPIC_GREG_GCONF_8259_PTHROU_DIS);

1340

1342

1341

if (mpic->flags & MPIC_NO_BIAS)

1343

if (mpic->flags & MPIC_NO_BIAS)

1342

mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),

1344

mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),

1343

mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))

1345

mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))

1344

| MPIC_GREG_GCONF_NO_BIAS);

1346

| MPIC_GREG_GCONF_NO_BIAS);

1345

1347

1346

/* Set current processor priority to 0 */

1348

/* Set current processor priority to 0 */

1347

mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);

1349

mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);

1348

1350

1349

#ifdef CONFIG_PM

1351

#ifdef CONFIG_PM

1350

/* allocate memory to save mpic state */

1352

/* allocate memory to save mpic state */

1351

mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),

1353

mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),

1352

GFP_KERNEL);

1354

GFP_KERNEL);

1353

BUG_ON(mpic->save_data == NULL);

1355

BUG_ON(mpic->save_data == NULL);

1354

#endif

1356

#endif

1355

}

1357

}

1356

1358

1357

void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)

1359

void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)

1358

{

1360

{

1359

u32 v;

1361

u32 v;

1360

1362

1361

v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);

1363

v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);

1362

v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;

1364

v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;

1363

v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);

1365

v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);

1364

mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);

1366

mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);

1365

}

1367

}

1366

1368

1367

void __init mpic_set_serial_int(struct mpic *mpic, int enable)

1369

void __init mpic_set_serial_int(struct mpic *mpic, int enable)

1368

{

1370

{

1369

unsigned long flags;

1371

unsigned long flags;

1370

u32 v;

1372

u32 v;

1371

1373

1372

raw_spin_lock_irqsave(&mpic_lock, flags);

1374

raw_spin_lock_irqsave(&mpic_lock, flags);

1373

v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);

1375

v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);

1374

if (enable)

1376

if (enable)

1375

v |= MPIC_GREG_GLOBAL_CONF_1_SIE;

1377

v |= MPIC_GREG_GLOBAL_CONF_1_SIE;

1376

else

1378

else

1377

v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;

1379

v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;

1378

mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);

1380

mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);

1379

raw_spin_unlock_irqrestore(&mpic_lock, flags);

1381

raw_spin_unlock_irqrestore(&mpic_lock, flags);

1380

}

1382

}

1381

1383

1382

void mpic_irq_set_priority(unsigned int irq, unsigned int pri)

1384

void mpic_irq_set_priority(unsigned int irq, unsigned int pri)

1383

{

1385

{

1384

struct mpic *mpic = mpic_find(irq);

1386

struct mpic *mpic = mpic_find(irq);

1385

unsigned int src = mpic_irq_to_hw(irq);

1387

unsigned int src = mpic_irq_to_hw(irq);

1386

unsigned long flags;

1388

unsigned long flags;

1387

u32 reg;

1389

u32 reg;

1388

1390

1389

if (!mpic)

1391

if (!mpic)

1390

return;

1392

return;

1391

1393

1392

raw_spin_lock_irqsave(&mpic_lock, flags);

1394

raw_spin_lock_irqsave(&mpic_lock, flags);

1393

if (mpic_is_ipi(mpic, irq)) {

1395

if (mpic_is_ipi(mpic, irq)) {

1394

reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &

1396

reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &

1395

~MPIC_VECPRI_PRIORITY_MASK;

1397

~MPIC_VECPRI_PRIORITY_MASK;

1396

mpic_ipi_write(src - mpic->ipi_vecs[0],

1398

mpic_ipi_write(src - mpic->ipi_vecs[0],

1397

reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));

1399

reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));

1398

} else {

1400

} else {

1399

reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))

1401

reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))

1400

& ~MPIC_VECPRI_PRIORITY_MASK;

1402

& ~MPIC_VECPRI_PRIORITY_MASK;

1401

mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),

1403

mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),

1402

reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));

1404

reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));

1403

}

1405

}

1404

raw_spin_unlock_irqrestore(&mpic_lock, flags);

1406

raw_spin_unlock_irqrestore(&mpic_lock, flags);

1405

}

1407

}

1406

1408

1407

void mpic_setup_this_cpu(void)

1409

void mpic_setup_this_cpu(void)

1408

{

1410

{

1409

#ifdef CONFIG_SMP

1411

#ifdef CONFIG_SMP

1410

struct mpic *mpic = mpic_primary;

1412

struct mpic *mpic = mpic_primary;

1411

unsigned long flags;

1413

unsigned long flags;

1412

u32 msk = 1 << hard_smp_processor_id();

1414

u32 msk = 1 << hard_smp_processor_id();

1413

unsigned int i;

1415

unsigned int i;

1414

1416

1415

BUG_ON(mpic == NULL);

1417

BUG_ON(mpic == NULL);

1416

1418

1417

DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());

1419

DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());

1418

1420

1419

raw_spin_lock_irqsave(&mpic_lock, flags);

1421

raw_spin_lock_irqsave(&mpic_lock, flags);

1420

1422

1421

/* let the mpic know we want intrs. default affinity is 0xffffffff

1423

/* let the mpic know we want intrs. default affinity is 0xffffffff

1422

* until changed via /proc. That's how it's done on x86. If we want

1424

* until changed via /proc. That's how it's done on x86. If we want

1423

* it differently, then we should make sure we also change the default

1425

* it differently, then we should make sure we also change the default

1424

* values of irq_desc[].affinity in irq.c.

1426

* values of irq_desc[].affinity in irq.c.

1425

*/

1427

*/

1426

if (distribute_irqs) {

1428

if (distribute_irqs) {

1427

for (i = 0; i < mpic->num_sources ; i++)

1429

for (i = 0; i < mpic->num_sources ; i++)

1428

mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),

1430

mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),

1429

mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);

1431

mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);

1430

}

1432

}

1431

1433

1432

/* Set current processor priority to 0 */

1434

/* Set current processor priority to 0 */

1433

mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);

1435

mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);

1434

1436

1435

raw_spin_unlock_irqrestore(&mpic_lock, flags);

1437

raw_spin_unlock_irqrestore(&mpic_lock, flags);

1436

#endif /* CONFIG_SMP */

1438

#endif /* CONFIG_SMP */

1437

}

1439

}

1438

1440

1439

int mpic_cpu_get_priority(void)

1441

int mpic_cpu_get_priority(void)

1440

{

1442

{

1441

struct mpic *mpic = mpic_primary;

1443

struct mpic *mpic = mpic_primary;

1442

1444

1443

return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));

1445

return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));

1444

}

1446

}

1445

1447

1446

void mpic_cpu_set_priority(int prio)

1448

void mpic_cpu_set_priority(int prio)

1447

{

1449

{

1448

struct mpic *mpic = mpic_primary;

1450

struct mpic *mpic = mpic_primary;

1449

1451

1450

prio &= MPIC_CPU_TASKPRI_MASK;

1452

prio &= MPIC_CPU_TASKPRI_MASK;

1451

mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);

1453

mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);

1452

}

1454

}

1453

1455

1454

void mpic_teardown_this_cpu(int secondary)

1456

void mpic_teardown_this_cpu(int secondary)

1455

{

1457

{

1456

struct mpic *mpic = mpic_primary;

1458

struct mpic *mpic = mpic_primary;

1457

unsigned long flags;

1459

unsigned long flags;

1458

u32 msk = 1 << hard_smp_processor_id();

1460

u32 msk = 1 << hard_smp_processor_id();

1459

unsigned int i;

1461

unsigned int i;

1460

1462

1461

BUG_ON(mpic == NULL);

1463

BUG_ON(mpic == NULL);

1462

1464

1463

DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());

1465

DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());

1464

raw_spin_lock_irqsave(&mpic_lock, flags);

1466

raw_spin_lock_irqsave(&mpic_lock, flags);

1465

1467

1466

/* let the mpic know we don't want intrs. */

1468

/* let the mpic know we don't want intrs. */

1467

for (i = 0; i < mpic->num_sources ; i++)

1469

for (i = 0; i < mpic->num_sources ; i++)

1468

mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),

1470

mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),

1469

mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);

1471

mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);

1470

1472

1471

/* Set current processor priority to max */

1473

/* Set current processor priority to max */

1472

mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);

1474

mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);

1473

/* We need to EOI the IPI since not all platforms reset the MPIC

1475

/* We need to EOI the IPI since not all platforms reset the MPIC

1474

* on boot and new interrupts wouldn't get delivered otherwise.

1476

* on boot and new interrupts wouldn't get delivered otherwise.

1475

*/

1477

*/

1476

mpic_eoi(mpic);

1478

mpic_eoi(mpic);

1477

1479

1478

raw_spin_unlock_irqrestore(&mpic_lock, flags);

1480

raw_spin_unlock_irqrestore(&mpic_lock, flags);

1479

}

1481

}

1480

1482

1481

1483

1482

static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)

1484

static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)

1483

{

1485

{

1484

u32 src;

1486

u32 src;

1485

1487

1486

src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);

1488

src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);

1487

#ifdef DEBUG_LOW

1489

#ifdef DEBUG_LOW

1488

DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);

1490

DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);

1489

#endif

1491

#endif

1490

if (unlikely(src == mpic->spurious_vec)) {

1492

if (unlikely(src == mpic->spurious_vec)) {

1491

if (mpic->flags & MPIC_SPV_EOI)

1493

if (mpic->flags & MPIC_SPV_EOI)

1492

mpic_eoi(mpic);

1494

mpic_eoi(mpic);

1493

return NO_IRQ;

1495

return NO_IRQ;

1494

}

1496

}

1495

if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {

1497

if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {

1496

if (printk_ratelimit())

1498

if (printk_ratelimit())

1497

printk(KERN_WARNING "%s: Got protected source %d !\n",

1499

printk(KERN_WARNING "%s: Got protected source %d !\n",

1498

mpic->name, (int)src);

1500

mpic->name, (int)src);

1499

mpic_eoi(mpic);

1501

mpic_eoi(mpic);

1500

return NO_IRQ;

1502

return NO_IRQ;

1501

}

1503

}

1502

1504

1503

return irq_linear_revmap(mpic->irqhost, src);

1505

return irq_linear_revmap(mpic->irqhost, src);

1504

}

1506

}

1505

1507

1506

unsigned int mpic_get_one_irq(struct mpic *mpic)

1508

unsigned int mpic_get_one_irq(struct mpic *mpic)

1507

{

1509

{

1508

return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));

1510

return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));

1509

}

1511

}

1510

1512

1511

unsigned int mpic_get_irq(void)

1513

unsigned int mpic_get_irq(void)

1512

{

1514

{

1513

struct mpic *mpic = mpic_primary;

1515

struct mpic *mpic = mpic_primary;

1514

1516

1515

BUG_ON(mpic == NULL);

1517

BUG_ON(mpic == NULL);

1516

1518

1517

return mpic_get_one_irq(mpic);

1519

return mpic_get_one_irq(mpic);

1518

}

1520

}

1519

1521

1520

unsigned int mpic_get_coreint_irq(void)

1522

unsigned int mpic_get_coreint_irq(void)

1521

{

1523

{

1522

#ifdef CONFIG_BOOKE

1524

#ifdef CONFIG_BOOKE

1523

struct mpic *mpic = mpic_primary;

1525

struct mpic *mpic = mpic_primary;

1524

u32 src;

1526

u32 src;

1525

1527

1526

BUG_ON(mpic == NULL);

1528

BUG_ON(mpic == NULL);

1527

1529

1528

src = mfspr(SPRN_EPR);

1530

src = mfspr(SPRN_EPR);

1529

1531

1530

if (unlikely(src == mpic->spurious_vec)) {

1532

if (unlikely(src == mpic->spurious_vec)) {

1531

if (mpic->flags & MPIC_SPV_EOI)

1533

if (mpic->flags & MPIC_SPV_EOI)

1532

mpic_eoi(mpic);

1534

mpic_eoi(mpic);

1533

return NO_IRQ;

1535

return NO_IRQ;

1534

}

1536

}

1535

if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {

1537

if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {

1536

if (printk_ratelimit())

1538

if (printk_ratelimit())

1537

printk(KERN_WARNING "%s: Got protected source %d !\n",

1539

printk(KERN_WARNING "%s: Got protected source %d !\n",

1538

mpic->name, (int)src);

1540

mpic->name, (int)src);

1539

return NO_IRQ;

1541

return NO_IRQ;

1540

}

1542

}

1541

1543

1542

return irq_linear_revmap(mpic->irqhost, src);

1544

return irq_linear_revmap(mpic->irqhost, src);

1543

#else

1545

#else

1544

return NO_IRQ;

1546

return NO_IRQ;

1545

#endif

1547

#endif

1546

}

1548

}

1547

1549

1548

unsigned int mpic_get_mcirq(void)

1550

unsigned int mpic_get_mcirq(void)

1549

{

1551

{

1550

struct mpic *mpic = mpic_primary;

1552

struct mpic *mpic = mpic_primary;

1551

1553

1552

BUG_ON(mpic == NULL);

1554

BUG_ON(mpic == NULL);

1553

1555

1554

return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));

1556

return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));

1555

}

1557

}

1556

1558

1557

#ifdef CONFIG_SMP

1559

#ifdef CONFIG_SMP

1558

void mpic_request_ipis(void)

1560

void mpic_request_ipis(void)

1559

{

1561

{

1560

struct mpic *mpic = mpic_primary;

1562

struct mpic *mpic = mpic_primary;

1561

int i;

1563

int i;

1562

BUG_ON(mpic == NULL);

1564

BUG_ON(mpic == NULL);

1563

1565

1564

printk(KERN_INFO "mpic: requesting IPIs...\n");

1566

printk(KERN_INFO "mpic: requesting IPIs...\n");

1565

1567

1566

for (i = 0; i < 4; i++) {

1568

for (i = 0; i < 4; i++) {

1567

unsigned int vipi = irq_create_mapping(mpic->irqhost,

1569

unsigned int vipi = irq_create_mapping(mpic->irqhost,

1568

mpic->ipi_vecs[0] + i);

1570

mpic->ipi_vecs[0] + i);

1569

if (vipi == NO_IRQ) {

1571

if (vipi == NO_IRQ) {

1570

printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);

1572

printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);

1571

continue;

1573

continue;

1572

}

1574

}

1573

smp_request_message_ipi(vipi, i);

1575

smp_request_message_ipi(vipi, i);

1574

}

1576

}

1575

}

1577

}

1576

1578

1577

static void mpic_send_ipi(unsigned int ipi_no, const struct cpumask *cpu_mask)

1579

static void mpic_send_ipi(unsigned int ipi_no, const struct cpumask *cpu_mask)

1578

{

1580

{

1579

struct mpic *mpic = mpic_primary;

1581

struct mpic *mpic = mpic_primary;

1580

1582

1581

BUG_ON(mpic == NULL);

1583

BUG_ON(mpic == NULL);

1582

1584

1583

#ifdef DEBUG_IPI

1585

#ifdef DEBUG_IPI

1584

DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);

1586

DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);

1585

#endif

1587

#endif

1586

1588

1587

mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +

1589

mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +

1588

ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),

1590

ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),

1589

mpic_physmask(cpumask_bits(cpu_mask)[0]));

1591

mpic_physmask(cpumask_bits(cpu_mask)[0]));

1590

}

1592

}

1591

1593

1592

void smp_mpic_message_pass(int target, int msg)

1594

void smp_mpic_message_pass(int target, int msg)

1593

{

1595

{

1594

cpumask_var_t tmp;

1596

cpumask_var_t tmp;

1595

1597

1596

/* make sure we're sending something that translates to an IPI */

1598

/* make sure we're sending something that translates to an IPI */

1597

if ((unsigned int)msg > 3) {

1599

if ((unsigned int)msg > 3) {

1598

printk("SMP %d: smp_message_pass: unknown msg %d\n",

1600

printk("SMP %d: smp_message_pass: unknown msg %d\n",

1599

smp_processor_id(), msg);

1601

smp_processor_id(), msg);

1600

return;

1602

return;

1601

}

1603

}

1602

switch (target) {

1604

switch (target) {

1603

case MSG_ALL:

1605

case MSG_ALL:

1604

mpic_send_ipi(msg, cpu_online_mask);

1606

mpic_send_ipi(msg, cpu_online_mask);

1605

break;

1607

break;

1606

case MSG_ALL_BUT_SELF:

1608

case MSG_ALL_BUT_SELF:

1607

alloc_cpumask_var(&tmp, GFP_NOWAIT);

1609

alloc_cpumask_var(&tmp, GFP_NOWAIT);

1608

cpumask_andnot(tmp, cpu_online_mask,

1610

cpumask_andnot(tmp, cpu_online_mask,

1609

cpumask_of(smp_processor_id()));

1611

cpumask_of(smp_processor_id()));

1610

mpic_send_ipi(msg, tmp);

1612

mpic_send_ipi(msg, tmp);

1611

free_cpumask_var(tmp);

1613

free_cpumask_var(tmp);

1612

break;

1614

break;

1613

default:

1615

default:

1614

mpic_send_ipi(msg, cpumask_of(target));

1616

mpic_send_ipi(msg, cpumask_of(target));

1615

break;

1617

break;

1616

}

1618

}

1617

}

1619

}

1618

1620

1619

int __init smp_mpic_probe(void)

1621

int __init smp_mpic_probe(void)

1620

{

1622

{

1621

int nr_cpus;

1623

int nr_cpus;

1622

1624

1623

DBG("smp_mpic_probe()...\n");

1625

DBG("smp_mpic_probe()...\n");

1624

1626

1625

nr_cpus = cpumask_weight(cpu_possible_mask);

1627

nr_cpus = cpumask_weight(cpu_possible_mask);

1626

1628

1627

DBG("nr_cpus: %d\n", nr_cpus);

1629

DBG("nr_cpus: %d\n", nr_cpus);

1628

1630

1629

if (nr_cpus > 1)

1631

if (nr_cpus > 1)

1630

mpic_request_ipis();

1632

mpic_request_ipis();

1631

1633

1632

return nr_cpus;

1634

return nr_cpus;

1633

}

1635

}

1634

1636

1635

void __devinit smp_mpic_setup_cpu(int cpu)

1637

void __devinit smp_mpic_setup_cpu(int cpu)

1636

{

1638

{

1637

mpic_setup_this_cpu();

1639

mpic_setup_this_cpu();

1638

}

1640

}

1639

1641

1640

void mpic_reset_core(int cpu)

1642

void mpic_reset_core(int cpu)

1641

{

1643

{

1642

struct mpic *mpic = mpic_primary;

1644

struct mpic *mpic = mpic_primary;

1643

u32 pir;

1645

u32 pir;

1644

int cpuid = get_hard_smp_processor_id(cpu);

1646

int cpuid = get_hard_smp_processor_id(cpu);

1645

1647

1646

/* Set target bit for core reset */

1648

/* Set target bit for core reset */

1647

pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));

1649

pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));

1648

pir |= (1 << cpuid);

1650

pir |= (1 << cpuid);

1649

mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);

1651

mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);

1650

mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));

1652

mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));

1651

1653

1652

/* Restore target bit after reset complete */

1654

/* Restore target bit after reset complete */

1653

pir &= ~(1 << cpuid);

1655

pir &= ~(1 << cpuid);

1654

mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);

1656

mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);

1655

mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));

1657

mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));

1656

}

1658

}

1657

#endif /* CONFIG_SMP */

1659

#endif /* CONFIG_SMP */

1658

1660

1659

#ifdef CONFIG_PM

1661

#ifdef CONFIG_PM

1660

static int mpic_suspend(struct sys_device *dev, pm_message_t state)

1662

static int mpic_suspend(struct sys_device *dev, pm_message_t state)

1661

{

1663

{

1662

struct mpic *mpic = container_of(dev, struct mpic, sysdev);

1664

struct mpic *mpic = container_of(dev, struct mpic, sysdev);

1663

int i;

1665

int i;

1664

1666

1665

for (i = 0; i < mpic->num_sources; i++) {

1667

for (i = 0; i < mpic->num_sources; i++) {

1666

mpic->save_data[i].vecprio =

1668

mpic->save_data[i].vecprio =

1667

mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));

1669

mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));

1668

mpic->save_data[i].dest =

1670

mpic->save_data[i].dest =

1669

mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));

1671

mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));

1670

}

1672

}

1671

1673

1672

return 0;

1674

return 0;

1673

}

1675

}

1674

1676

1675

static int mpic_resume(struct sys_device *dev)

1677

static int mpic_resume(struct sys_device *dev)

1676

{

1678

{

1677

struct mpic *mpic = container_of(dev, struct mpic, sysdev);

1679

struct mpic *mpic = container_of(dev, struct mpic, sysdev);

1678

int i;

1680

int i;

1679

1681

1680

for (i = 0; i < mpic->num_sources; i++) {

1682

for (i = 0; i < mpic->num_sources; i++) {

1681

mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),

1683

mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),

1682

mpic->save_data[i].vecprio);

1684

mpic->save_data[i].vecprio);

1683

mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),

1685

mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),

1684

mpic->save_data[i].dest);

1686

mpic->save_data[i].dest);

1685

1687

1686

#ifdef CONFIG_MPIC_U3_HT_IRQS

1688

#ifdef CONFIG_MPIC_U3_HT_IRQS

1687

if (mpic->fixups) {

1689

if (mpic->fixups) {

1688

struct mpic_irq_fixup *fixup = &mpic->fixups[i];

1690

struct mpic_irq_fixup *fixup = &mpic->fixups[i];

1689

1691

1690

if (fixup->base) {

1692

if (fixup->base) {

1691

/* we use the lowest bit in an inverted meaning */

1693

/* we use the lowest bit in an inverted meaning */

1692

if ((mpic->save_data[i].fixup_data & 1) == 0)

1694

if ((mpic->save_data[i].fixup_data & 1) == 0)

1693

continue;

1695

continue;

1694

1696

1695

/* Enable and configure */

1697

/* Enable and configure */

1696

writeb(0x10 + 2 * fixup->index, fixup->base + 2);

1698

writeb(0x10 + 2 * fixup->index, fixup->base + 2);

1697

1699

1698

writel(mpic->save_data[i].fixup_data & ~1,

1700

writel(mpic->save_data[i].fixup_data & ~1,

1699

fixup->base + 4);

1701

fixup->base + 4);

1700

}

1702

}

1701

}

1703

}

1702

#endif

1704

#endif

1703

} /* end for loop */

1705

} /* end for loop */

1704

1706

1705

return 0;

1707

return 0;

1706

}

1708

}

1707

#endif

1709

#endif

1708

1710

1709

static struct sysdev_class mpic_sysclass = {

1711

static struct sysdev_class mpic_sysclass = {

1710

#ifdef CONFIG_PM

1712

#ifdef CONFIG_PM

1711

.resume = mpic_resume,

1713

.resume = mpic_resume,

1712

.suspend = mpic_suspend,

1714

.suspend = mpic_suspend,

1713

#endif

1715

#endif

1714

.name = "mpic",

1716

.name = "mpic",

1715

};

1717

};

1716

1718

1717

static int mpic_init_sys(void)

1719

static int mpic_init_sys(void)

1718

{

1720

{

1719

struct mpic *mpic = mpics;

1721

struct mpic *mpic = mpics;

1720

int error, id = 0;

1722

int error, id = 0;

1721

1723

1722

error = sysdev_class_register(&mpic_sysclass);

1724

error = sysdev_class_register(&mpic_sysclass);

1723

1725

1724

while (mpic && !error) {

1726

while (mpic && !error) {

1725

mpic->sysdev.cls = &mpic_sysclass;

1727

mpic->sysdev.cls = &mpic_sysclass;

1726

mpic->sysdev.id = id++;

1728

mpic->sysdev.id = id++;

1727

error = sysdev_register(&mpic->sysdev);

1729

error = sysdev_register(&mpic->sysdev);

1728

mpic = mpic->next;

1730

mpic = mpic->next;

1729

}

1731

}

1730

return error;

1732

return error;

1731

}

1733

}

1732

1734

1733

device_initcall(mpic_init_sys);

1735

device_initcall(mpic_init_sys);

1734

1736

GITLAB

powerpc/mpic: Fix mask/unmask timeout message

 /*
  *  arch/powerpc/kernel/mpic.c
  *
  *  Driver for interrupt controllers following the OpenPIC standard, the
  *  common implementation beeing IBM's MPIC. This driver also can deal
  *  with various broken implementations of this HW.
  *
  *  Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
  *
  *  This file is subject to the terms and conditions of the GNU General Public
  *  License.  See the file COPYING in the main directory of this archive
  *  for more details.
  */
 #undef DEBUG
 #undef DEBUG_IPI
 #undef DEBUG_IRQ
 #undef DEBUG_LOW
 #include <linux/types.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/smp.h>
 #include <linux/interrupt.h>
 #include <linux/bootmem.h>
 #include <linux/spinlock.h>
 #include <linux/pci.h>
 #include <linux/slab.h>
 #include <asm/ptrace.h>
 #include <asm/signal.h>
 #include <asm/io.h>
 #include <asm/pgtable.h>
 #include <asm/irq.h>
 #include <asm/machdep.h>
 #include <asm/mpic.h>
 #include <asm/smp.h>
 #include "mpic.h"
 #ifdef DEBUG
 #define DBG(fmt...) printk(fmt)
 #else
 #define DBG(fmt...)
 #endif
 static struct mpic *mpics;
 static struct mpic *mpic_primary;
 static DEFINE_RAW_SPINLOCK(mpic_lock);
 #ifdef CONFIG_PPC32	/* XXX for now */
 #ifdef CONFIG_IRQ_ALL_CPUS
 #define distribute_irqs	(1)
 #else
 #define distribute_irqs	(0)
 #endif
 #endif
 #ifdef CONFIG_MPIC_WEIRD
 static u32 mpic_infos[][MPIC_IDX_END] = {
 	[0] = {	/* Original OpenPIC compatible MPIC */
 		MPIC_GREG_BASE,
 		MPIC_GREG_FEATURE_0,
 		MPIC_GREG_GLOBAL_CONF_0,
 		MPIC_GREG_VENDOR_ID,
 		MPIC_GREG_IPI_VECTOR_PRI_0,
 		MPIC_GREG_IPI_STRIDE,
 		MPIC_GREG_SPURIOUS,
 		MPIC_GREG_TIMER_FREQ,
 		MPIC_TIMER_BASE,
 		MPIC_TIMER_STRIDE,
 		MPIC_TIMER_CURRENT_CNT,
 		MPIC_TIMER_BASE_CNT,
 		MPIC_TIMER_VECTOR_PRI,
 		MPIC_TIMER_DESTINATION,
 		MPIC_CPU_BASE,
 		MPIC_CPU_STRIDE,
 		MPIC_CPU_IPI_DISPATCH_0,
 		MPIC_CPU_IPI_DISPATCH_STRIDE,
 		MPIC_CPU_CURRENT_TASK_PRI,
 		MPIC_CPU_WHOAMI,
 		MPIC_CPU_INTACK,
 		MPIC_CPU_EOI,
 		MPIC_CPU_MCACK,
 		MPIC_IRQ_BASE,
 		MPIC_IRQ_STRIDE,
 		MPIC_IRQ_VECTOR_PRI,
 		MPIC_VECPRI_VECTOR_MASK,
 		MPIC_VECPRI_POLARITY_POSITIVE,
 		MPIC_VECPRI_POLARITY_NEGATIVE,
 		MPIC_VECPRI_SENSE_LEVEL,
 		MPIC_VECPRI_SENSE_EDGE,
 		MPIC_VECPRI_POLARITY_MASK,
 		MPIC_VECPRI_SENSE_MASK,
 		MPIC_IRQ_DESTINATION
 	},
 	[1] = {	/* Tsi108/109 PIC */
 		TSI108_GREG_BASE,
 		TSI108_GREG_FEATURE_0,
 		TSI108_GREG_GLOBAL_CONF_0,
 		TSI108_GREG_VENDOR_ID,
 		TSI108_GREG_IPI_VECTOR_PRI_0,
 		TSI108_GREG_IPI_STRIDE,
 		TSI108_GREG_SPURIOUS,
 		TSI108_GREG_TIMER_FREQ,
 		TSI108_TIMER_BASE,
 		TSI108_TIMER_STRIDE,
 		TSI108_TIMER_CURRENT_CNT,
 		TSI108_TIMER_BASE_CNT,
 		TSI108_TIMER_VECTOR_PRI,
 		TSI108_TIMER_DESTINATION,
 		TSI108_CPU_BASE,
 		TSI108_CPU_STRIDE,
 		TSI108_CPU_IPI_DISPATCH_0,
 		TSI108_CPU_IPI_DISPATCH_STRIDE,
 		TSI108_CPU_CURRENT_TASK_PRI,
 		TSI108_CPU_WHOAMI,
 		TSI108_CPU_INTACK,
 		TSI108_CPU_EOI,
 		TSI108_CPU_MCACK,
 		TSI108_IRQ_BASE,
 		TSI108_IRQ_STRIDE,
 		TSI108_IRQ_VECTOR_PRI,
 		TSI108_VECPRI_VECTOR_MASK,
 		TSI108_VECPRI_POLARITY_POSITIVE,
 		TSI108_VECPRI_POLARITY_NEGATIVE,
 		TSI108_VECPRI_SENSE_LEVEL,
 		TSI108_VECPRI_SENSE_EDGE,
 		TSI108_VECPRI_POLARITY_MASK,
 		TSI108_VECPRI_SENSE_MASK,
 		TSI108_IRQ_DESTINATION
 	},
 };
 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
 #else /* CONFIG_MPIC_WEIRD */
 #define MPIC_INFO(name) MPIC_##name
 #endif /* CONFIG_MPIC_WEIRD */
 /*
  * Register accessor functions
  */
 static inline u32 _mpic_read(enum mpic_reg_type type,
 			     struct mpic_reg_bank *rb,
 			     unsigned int reg)
 {
 	switch(type) {
 #ifdef CONFIG_PPC_DCR
 	case mpic_access_dcr:
 		return dcr_read(rb->dhost, reg);
 #endif
 	case mpic_access_mmio_be:
 		return in_be32(rb->base + (reg >> 2));
 	case mpic_access_mmio_le:
 	default:
 		return in_le32(rb->base + (reg >> 2));
 	}
 }
 static inline void _mpic_write(enum mpic_reg_type type,
 			       struct mpic_reg_bank *rb,
  			       unsigned int reg, u32 value)
 {
 	switch(type) {
 #ifdef CONFIG_PPC_DCR
 	case mpic_access_dcr:
 		dcr_write(rb->dhost, reg, value);
 		break;
 #endif
 	case mpic_access_mmio_be:
 		out_be32(rb->base + (reg >> 2), value);
 		break;
 	case mpic_access_mmio_le:
 	default:
 		out_le32(rb->base + (reg >> 2), value);
 		break;
 	}
 }
 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
 {
 	enum mpic_reg_type type = mpic->reg_type;
 	unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
 			      (ipi * MPIC_INFO(GREG_IPI_STRIDE));
 	if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
 		type = mpic_access_mmio_be;
 	return _mpic_read(type, &mpic->gregs, offset);
 }
 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
 {
 	unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
 			      (ipi * MPIC_INFO(GREG_IPI_STRIDE));
 	_mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
 }
 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
 {
 	unsigned int cpu = 0;
 	if (mpic->flags & MPIC_PRIMARY)
 		cpu = hard_smp_processor_id();
 	return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
 }
 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
 {
 	unsigned int cpu = 0;
 	if (mpic->flags & MPIC_PRIMARY)
 		cpu = hard_smp_processor_id();
 	_mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
 }
 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
 {
 	unsigned int	isu = src_no >> mpic->isu_shift;
 	unsigned int	idx = src_no & mpic->isu_mask;
 	unsigned int	val;
 	val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
 			 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
 #ifdef CONFIG_MPIC_BROKEN_REGREAD
 	if (reg == 0)
 		val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
 			mpic->isu_reg0_shadow[src_no];
 #endif
 	return val;
 }
 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
 				   unsigned int reg, u32 value)
 {
 	unsigned int	isu = src_no >> mpic->isu_shift;
 	unsigned int	idx = src_no & mpic->isu_mask;
 	_mpic_write(mpic->reg_type, &mpic->isus[isu],
 		    reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
 #ifdef CONFIG_MPIC_BROKEN_REGREAD
 	if (reg == 0)
 		mpic->isu_reg0_shadow[src_no] =
 			value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
 #endif
 }
 #define mpic_read(b,r)		_mpic_read(mpic->reg_type,&(b),(r))
 #define mpic_write(b,r,v)	_mpic_write(mpic->reg_type,&(b),(r),(v))
 #define mpic_ipi_read(i)	_mpic_ipi_read(mpic,(i))
 #define mpic_ipi_write(i,v)	_mpic_ipi_write(mpic,(i),(v))
 #define mpic_cpu_read(i)	_mpic_cpu_read(mpic,(i))
 #define mpic_cpu_write(i,v)	_mpic_cpu_write(mpic,(i),(v))
 #define mpic_irq_read(s,r)	_mpic_irq_read(mpic,(s),(r))
 #define mpic_irq_write(s,r,v)	_mpic_irq_write(mpic,(s),(r),(v))
 /*
  * Low level utility functions
  */
 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
 			   struct mpic_reg_bank *rb, unsigned int offset,
 			   unsigned int size)
 {
 	rb->base = ioremap(phys_addr + offset, size);
 	BUG_ON(rb->base == NULL);
 }
 #ifdef CONFIG_PPC_DCR
 static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node,
 			  struct mpic_reg_bank *rb,
 			  unsigned int offset, unsigned int size)
 {
 	const u32 *dbasep;
 	dbasep = of_get_property(node, "dcr-reg", NULL);
 	rb->dhost = dcr_map(node, *dbasep + offset, size);
 	BUG_ON(!DCR_MAP_OK(rb->dhost));
 }
 static inline void mpic_map(struct mpic *mpic, struct device_node *node,
 			    phys_addr_t phys_addr, struct mpic_reg_bank *rb,
 			    unsigned int offset, unsigned int size)
 {
 	if (mpic->flags & MPIC_USES_DCR)
 		_mpic_map_dcr(mpic, node, rb, offset, size);
 	else
 		_mpic_map_mmio(mpic, phys_addr, rb, offset, size);
 }
 #else /* CONFIG_PPC_DCR */
 #define mpic_map(m,n,p,b,o,s)	_mpic_map_mmio(m,p,b,o,s)
 #endif /* !CONFIG_PPC_DCR */
 /* Check if we have one of those nice broken MPICs with a flipped endian on
  * reads from IPI registers
  */
 static void __init mpic_test_broken_ipi(struct mpic *mpic)
 {
 	u32 r;
 	mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
 	r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
 	if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
 		printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
 		mpic->flags |= MPIC_BROKEN_IPI;
 	}
 }
 #ifdef CONFIG_MPIC_U3_HT_IRQS
 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
  * to force the edge setting on the MPIC and do the ack workaround.
  */
 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
 {
 	if (source >= 128 || !mpic->fixups)
 		return 0;
 	return mpic->fixups[source].base != NULL;
 }
 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
 {
 	struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 	if (fixup->applebase) {
 		unsigned int soff = (fixup->index >> 3) & ~3;
 		unsigned int mask = 1U << (fixup->index & 0x1f);
 		writel(mask, fixup->applebase + soff);
 	} else {
 		raw_spin_lock(&mpic->fixup_lock);
 		writeb(0x11 + 2 * fixup->index, fixup->base + 2);
 		writel(fixup->data, fixup->base + 4);
 		raw_spin_unlock(&mpic->fixup_lock);
 	}
 }
 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
 				      unsigned int irqflags)
 {
 	struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 	unsigned long flags;
 	u32 tmp;
 	if (fixup->base == NULL)
 		return;
 	DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n",
 	    source, irqflags, fixup->index);
 	raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
 	/* Enable and configure */
 	writeb(0x10 + 2 * fixup->index, fixup->base + 2);
 	tmp = readl(fixup->base + 4);
 	tmp &= ~(0x23U);
 	if (irqflags & IRQ_LEVEL)
 		tmp |= 0x22;
 	writel(tmp, fixup->base + 4);
 	raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
 #ifdef CONFIG_PM
 	/* use the lowest bit inverted to the actual HW,
 	 * set if this fixup was enabled, clear otherwise */
 	mpic->save_data[source].fixup_data = tmp | 1;
 #endif
 }
 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source,
 				       unsigned int irqflags)
 {
 	struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 	unsigned long flags;
 	u32 tmp;
 	if (fixup->base == NULL)
 		return;
 	DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags);
 	/* Disable */
 	raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
 	writeb(0x10 + 2 * fixup->index, fixup->base + 2);
 	tmp = readl(fixup->base + 4);
 	tmp |= 1;
 	writel(tmp, fixup->base + 4);
 	raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
 #ifdef CONFIG_PM
 	/* use the lowest bit inverted to the actual HW,
 	 * set if this fixup was enabled, clear otherwise */
 	mpic->save_data[source].fixup_data = tmp & ~1;
 #endif
 }
 #ifdef CONFIG_PCI_MSI
 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
 				    unsigned int devfn)
 {
 	u8 __iomem *base;
 	u8 pos, flags;
 	u64 addr = 0;
 	for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
 	     pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
 		u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
 		if (id == PCI_CAP_ID_HT) {
 			id = readb(devbase + pos + 3);
 			if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
 				break;
 		}
 	}
 	if (pos == 0)
 		return;
 	base = devbase + pos;
 	flags = readb(base + HT_MSI_FLAGS);
 	if (!(flags & HT_MSI_FLAGS_FIXED)) {
 		addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
 		addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
 	}
 	printk(KERN_DEBUG "mpic:   - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
 		PCI_SLOT(devfn), PCI_FUNC(devfn),
 		flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
 	if (!(flags & HT_MSI_FLAGS_ENABLE))
 		writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
 }
 #else
 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
 				    unsigned int devfn)
 {
 	return;
 }
 #endif
 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
 				    unsigned int devfn, u32 vdid)
 {
 	int i, irq, n;
 	u8 __iomem *base;
 	u32 tmp;
 	u8 pos;
 	for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
 	     pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
 		u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
 		if (id == PCI_CAP_ID_HT) {
 			id = readb(devbase + pos + 3);
 			if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
 				break;
 		}
 	}
 	if (pos == 0)
 		return;
 	base = devbase + pos;
 	writeb(0x01, base + 2);
 	n = (readl(base + 4) >> 16) & 0xff;
 	printk(KERN_INFO "mpic:   - HT:%02x.%x [0x%02x] vendor %04x device %04x"
 	       " has %d irqs\n",
 	       devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
 	for (i = 0; i <= n; i++) {
 		writeb(0x10 + 2 * i, base + 2);
 		tmp = readl(base + 4);
 		irq = (tmp >> 16) & 0xff;
 		DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
 		/* mask it , will be unmasked later */
 		tmp |= 0x1;
 		writel(tmp, base + 4);
 		mpic->fixups[irq].index = i;
 		mpic->fixups[irq].base = base;
 		/* Apple HT PIC has a non-standard way of doing EOIs */
 		if ((vdid & 0xffff) == 0x106b)
 			mpic->fixups[irq].applebase = devbase + 0x60;
 		else
 			mpic->fixups[irq].applebase = NULL;
 		writeb(0x11 + 2 * i, base + 2);
 		mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
 	}
 }
 static void __init mpic_scan_ht_pics(struct mpic *mpic)
 {
 	unsigned int devfn;
 	u8 __iomem *cfgspace;
 	printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
 	/* Allocate fixups array */
 	mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);
 	BUG_ON(mpic->fixups == NULL);
 	/* Init spinlock */
 	raw_spin_lock_init(&mpic->fixup_lock);
 	/* Map U3 config space. We assume all IO-APICs are on the primary bus
 	 * so we only need to map 64kB.
 	 */
 	cfgspace = ioremap(0xf2000000, 0x10000);
 	BUG_ON(cfgspace == NULL);
 	/* Now we scan all slots. We do a very quick scan, we read the header
 	 * type, vendor ID and device ID only, that's plenty enough
 	 */
 	for (devfn = 0; devfn < 0x100; devfn++) {
 		u8 __iomem *devbase = cfgspace + (devfn << 8);
 		u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
 		u32 l = readl(devbase + PCI_VENDOR_ID);
 		u16 s;
 		DBG("devfn %x, l: %x\n", devfn, l);
 		/* If no device, skip */
 		if (l == 0xffffffff || l == 0x00000000 ||
 		    l == 0x0000ffff || l == 0xffff0000)
 			goto next;
 		/* Check if is supports capability lists */
 		s = readw(devbase + PCI_STATUS);
 		if (!(s & PCI_STATUS_CAP_LIST))
 			goto next;
 		mpic_scan_ht_pic(mpic, devbase, devfn, l);
 		mpic_scan_ht_msi(mpic, devbase, devfn);
 	next:
 		/* next device, if function 0 */
 		if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
 			devfn += 7;
 	}
 }
 #else /* CONFIG_MPIC_U3_HT_IRQS */
 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
 {
 	return 0;
 }
 static void __init mpic_scan_ht_pics(struct mpic *mpic)
 {
 }
 #endif /* CONFIG_MPIC_U3_HT_IRQS */
 #ifdef CONFIG_SMP
 static int irq_choose_cpu(const struct cpumask *mask)
 {
 	int cpuid;
 	if (cpumask_equal(mask, cpu_all_mask)) {
 		static int irq_rover = 0;
 		static DEFINE_RAW_SPINLOCK(irq_rover_lock);
 		unsigned long flags;
 		/* Round-robin distribution... */
 	do_round_robin:
 		raw_spin_lock_irqsave(&irq_rover_lock, flags);
 		irq_rover = cpumask_next(irq_rover, cpu_online_mask);
 		if (irq_rover >= nr_cpu_ids)
 			irq_rover = cpumask_first(cpu_online_mask);
 		cpuid = irq_rover;
 		raw_spin_unlock_irqrestore(&irq_rover_lock, flags);
 	} else {
 		cpuid = cpumask_first_and(mask, cpu_online_mask);
 		if (cpuid >= nr_cpu_ids)
 			goto do_round_robin;
 	}
 	return get_hard_smp_processor_id(cpuid);
 }
 #else
 static int irq_choose_cpu(const struct cpumask *mask)
 {
 	return hard_smp_processor_id();
 }
 #endif
 #define mpic_irq_to_hw(virq)	((unsigned int)irq_map[virq].hwirq)
 /* Find an mpic associated with a given linux interrupt */
 static struct mpic *mpic_find(unsigned int irq)
 {
 	if (irq < NUM_ISA_INTERRUPTS)
 		return NULL;
 	return irq_to_desc(irq)->chip_data;
 }
 /* Determine if the linux irq is an IPI */
 static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
 {
 	unsigned int src = mpic_irq_to_hw(irq);
 	return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
 }
 /* Convert a cpu mask from logical to physical cpu numbers. */
 static inline u32 mpic_physmask(u32 cpumask)
 {
 	int i;
 	u32 mask = 0;
 	for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
 		mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
 	return mask;
 }
 #ifdef CONFIG_SMP
 /* Get the mpic structure from the IPI number */
 static inline struct mpic * mpic_from_ipi(unsigned int ipi)
 {
 	return irq_to_desc(ipi)->chip_data;
 }
 #endif
 /* Get the mpic structure from the irq number */
 static inline struct mpic * mpic_from_irq(unsigned int irq)
 {
 	return irq_to_desc(irq)->chip_data;
 }
 /* Send an EOI */
 static inline void mpic_eoi(struct mpic *mpic)
 {
 	mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
 	(void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
 }
 /*
  * Linux descriptor level callbacks
  */
 void mpic_unmask_irq(unsigned int irq)
 {
 	unsigned int loops = 100000;
 	struct mpic *mpic = mpic_from_irq(irq);
 	unsigned int src = mpic_irq_to_hw(irq);
 	DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
 	mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
 		       mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
 		       ~MPIC_VECPRI_MASK);
 	/* make sure mask gets to controller before we return to user */
 	do {
 		if (!loops--) {
-			printk(KERN_ERR "mpic_enable_irq timeout\n");
+			printk(KERN_ERR "%s: timeout on hwirq %u\n",
+			       __func__, src);
 			break;
 		}
 	} while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
 }
 void mpic_mask_irq(unsigned int irq)
 {
 	unsigned int loops = 100000;
 	struct mpic *mpic = mpic_from_irq(irq);
 	unsigned int src = mpic_irq_to_hw(irq);
 	DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
 	mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
 		       mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
 		       MPIC_VECPRI_MASK);
 	/* make sure mask gets to controller before we return to user */
 	do {
 		if (!loops--) {
-			printk(KERN_ERR "mpic_enable_irq timeout\n");
+			printk(KERN_ERR "%s: timeout on hwirq %u\n",
+			       __func__, src);
 			break;
 		}
 	} while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
 }
 void mpic_end_irq(unsigned int irq)
 {
 	struct mpic *mpic = mpic_from_irq(irq);
 #ifdef DEBUG_IRQ
 	DBG("%s: end_irq: %d\n", mpic->name, irq);
 #endif
 	/* We always EOI on end_irq() even for edge interrupts since that
 	 * should only lower the priority, the MPIC should have properly
 	 * latched another edge interrupt coming in anyway
 	 */
 	mpic_eoi(mpic);
 }
 #ifdef CONFIG_MPIC_U3_HT_IRQS
 static void mpic_unmask_ht_irq(unsigned int irq)
 {
 	struct mpic *mpic = mpic_from_irq(irq);
 	unsigned int src = mpic_irq_to_hw(irq);
 	mpic_unmask_irq(irq);
 	if (irq_to_desc(irq)->status & IRQ_LEVEL)
 		mpic_ht_end_irq(mpic, src);
 }
 static unsigned int mpic_startup_ht_irq(unsigned int irq)
 {
 	struct mpic *mpic = mpic_from_irq(irq);
 	unsigned int src = mpic_irq_to_hw(irq);
 	mpic_unmask_irq(irq);
 	mpic_startup_ht_interrupt(mpic, src, irq_to_desc(irq)->status);
 	return 0;
 }
 static void mpic_shutdown_ht_irq(unsigned int irq)
 {
 	struct mpic *mpic = mpic_from_irq(irq);
 	unsigned int src = mpic_irq_to_hw(irq);
 	mpic_shutdown_ht_interrupt(mpic, src, irq_to_desc(irq)->status);
 	mpic_mask_irq(irq);
 }
 static void mpic_end_ht_irq(unsigned int irq)
 {
 	struct mpic *mpic = mpic_from_irq(irq);
 	unsigned int src = mpic_irq_to_hw(irq);
 #ifdef DEBUG_IRQ
 	DBG("%s: end_irq: %d\n", mpic->name, irq);
 #endif
 	/* We always EOI on end_irq() even for edge interrupts since that
 	 * should only lower the priority, the MPIC should have properly
 	 * latched another edge interrupt coming in anyway
 	 */
 	if (irq_to_desc(irq)->status & IRQ_LEVEL)
 		mpic_ht_end_irq(mpic, src);
 	mpic_eoi(mpic);
 }
 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
 #ifdef CONFIG_SMP
 static void mpic_unmask_ipi(unsigned int irq)
 {
 	struct mpic *mpic = mpic_from_ipi(irq);
 	unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0];
 	DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);
 	mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
 }
 static void mpic_mask_ipi(unsigned int irq)
 {
 	/* NEVER disable an IPI... that's just plain wrong! */
 }
 static void mpic_end_ipi(unsigned int irq)
 {
 	struct mpic *mpic = mpic_from_ipi(irq);
 	/*
 	 * IPIs are marked IRQ_PER_CPU. This has the side effect of
 	 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
 	 * applying to them. We EOI them late to avoid re-entering.
 	 * We mark IPI's with IRQF_DISABLED as they must run with
 	 * irqs disabled.
 	 */
 	mpic_eoi(mpic);
 }
 #endif /* CONFIG_SMP */
 int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
 {
 	struct mpic *mpic = mpic_from_irq(irq);
 	unsigned int src = mpic_irq_to_hw(irq);
 	if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
 		int cpuid = irq_choose_cpu(cpumask);
 		mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
 	} else {
 		cpumask_var_t tmp;
 		alloc_cpumask_var(&tmp, GFP_KERNEL);
 		cpumask_and(tmp, cpumask, cpu_online_mask);
 		mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
 			       mpic_physmask(cpumask_bits(tmp)[0]));
 		free_cpumask_var(tmp);
 	}
 	return 0;
 }
 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
 {
 	/* Now convert sense value */
 	switch(type & IRQ_TYPE_SENSE_MASK) {
 	case IRQ_TYPE_EDGE_RISING:
 		return MPIC_INFO(VECPRI_SENSE_EDGE) |
 		       MPIC_INFO(VECPRI_POLARITY_POSITIVE);
 	case IRQ_TYPE_EDGE_FALLING:
 	case IRQ_TYPE_EDGE_BOTH:
 		return MPIC_INFO(VECPRI_SENSE_EDGE) |
 		       MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
 	case IRQ_TYPE_LEVEL_HIGH:
 		return MPIC_INFO(VECPRI_SENSE_LEVEL) |
 		       MPIC_INFO(VECPRI_POLARITY_POSITIVE);
 	case IRQ_TYPE_LEVEL_LOW:
 	default:
 		return MPIC_INFO(VECPRI_SENSE_LEVEL) |
 		       MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
 	}
 }
 int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
 {
 	struct mpic *mpic = mpic_from_irq(virq);
 	unsigned int src = mpic_irq_to_hw(virq);
 	struct irq_desc *desc = irq_to_desc(virq);
 	unsigned int vecpri, vold, vnew;
 	DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
 	    mpic, virq, src, flow_type);
 	if (src >= mpic->irq_count)
 		return -EINVAL;
 	if (flow_type == IRQ_TYPE_NONE)
 		if (mpic->senses && src < mpic->senses_count)
 			flow_type = mpic->senses[src];
 	if (flow_type == IRQ_TYPE_NONE)
 		flow_type = IRQ_TYPE_LEVEL_LOW;
 	desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
 	desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
 	if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
 		desc->status |= IRQ_LEVEL;
 	if (mpic_is_ht_interrupt(mpic, src))
 		vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
 			MPIC_VECPRI_SENSE_EDGE;
 	else
 		vecpri = mpic_type_to_vecpri(mpic, flow_type);
 	vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
 	vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
 			MPIC_INFO(VECPRI_SENSE_MASK));
 	vnew |= vecpri;
 	if (vold != vnew)
 		mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
 	return 0;
 }
 void mpic_set_vector(unsigned int virq, unsigned int vector)
 {
 	struct mpic *mpic = mpic_from_irq(virq);
 	unsigned int src = mpic_irq_to_hw(virq);
 	unsigned int vecpri;
 	DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
 	    mpic, virq, src, vector);
 	if (src >= mpic->irq_count)
 		return;
 	vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
 	vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
 	vecpri |= vector;
 	mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
 }
 static struct irq_chip mpic_irq_chip = {
 	.mask		= mpic_mask_irq,
 	.unmask		= mpic_unmask_irq,
 	.eoi		= mpic_end_irq,
 	.set_type	= mpic_set_irq_type,
 };
 #ifdef CONFIG_SMP
 static struct irq_chip mpic_ipi_chip = {
 	.mask		= mpic_mask_ipi,
 	.unmask		= mpic_unmask_ipi,
 	.eoi		= mpic_end_ipi,
 };
 #endif /* CONFIG_SMP */
 #ifdef CONFIG_MPIC_U3_HT_IRQS
 static struct irq_chip mpic_irq_ht_chip = {
 	.startup	= mpic_startup_ht_irq,
 	.shutdown	= mpic_shutdown_ht_irq,
 	.mask		= mpic_mask_irq,
 	.unmask		= mpic_unmask_ht_irq,
 	.eoi		= mpic_end_ht_irq,
 	.set_type	= mpic_set_irq_type,
 };
 #endif /* CONFIG_MPIC_U3_HT_IRQS */
 static int mpic_host_match(struct irq_host *h, struct device_node *node)
 {
 	/* Exact match, unless mpic node is NULL */
 	return h->of_node == NULL || h->of_node == node;
 }
 static int mpic_host_map(struct irq_host *h, unsigned int virq,
 			 irq_hw_number_t hw)
 {
 	struct mpic *mpic = h->host_data;
 	struct irq_chip *chip;
 	DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
 	if (hw == mpic->spurious_vec)
 		return -EINVAL;
 	if (mpic->protected && test_bit(hw, mpic->protected))
 		return -EINVAL;
 #ifdef CONFIG_SMP
 	else if (hw >= mpic->ipi_vecs[0]) {
 		WARN_ON(!(mpic->flags & MPIC_PRIMARY));
 		DBG("mpic: mapping as IPI\n");
 		set_irq_chip_data(virq, mpic);
 		set_irq_chip_and_handler(virq, &mpic->hc_ipi,
 					 handle_percpu_irq);
 		return 0;
 	}
 #endif /* CONFIG_SMP */
 	if (hw >= mpic->irq_count)
 		return -EINVAL;
 	mpic_msi_reserve_hwirq(mpic, hw);
 	/* Default chip */
 	chip = &mpic->hc_irq;
 #ifdef CONFIG_MPIC_U3_HT_IRQS
 	/* Check for HT interrupts, override vecpri */
 	if (mpic_is_ht_interrupt(mpic, hw))
 		chip = &mpic->hc_ht_irq;
 #endif /* CONFIG_MPIC_U3_HT_IRQS */
 	DBG("mpic: mapping to irq chip @%p\n", chip);
 	set_irq_chip_data(virq, mpic);
 	set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq);
 	/* Set default irq type */
 	set_irq_type(virq, IRQ_TYPE_NONE);
 	return 0;
 }
 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
 			   const u32 *intspec, unsigned int intsize,
 			   irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 {
 	static unsigned char map_mpic_senses[4] = {
 		IRQ_TYPE_EDGE_RISING,
 		IRQ_TYPE_LEVEL_LOW,
 		IRQ_TYPE_LEVEL_HIGH,
 		IRQ_TYPE_EDGE_FALLING,
 	};
 	*out_hwirq = intspec[0];
 	if (intsize > 1) {
 		u32 mask = 0x3;
 		/* Apple invented a new race of encoding on machines with
 		 * an HT APIC. They encode, among others, the index within
 		 * the HT APIC. We don't care about it here since thankfully,
 		 * it appears that they have the APIC already properly
 		 * configured, and thus our current fixup code that reads the
 		 * APIC config works fine. However, we still need to mask out
 		 * bits in the specifier to make sure we only get bit 0 which
 		 * is the level/edge bit (the only sense bit exposed by Apple),
 		 * as their bit 1 means something else.
 		 */
 		if (machine_is(powermac))
 			mask = 0x1;
 		*out_flags = map_mpic_senses[intspec[1] & mask];
 	} else
 		*out_flags = IRQ_TYPE_NONE;
 	DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
 	    intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
 	return 0;
 }
 static struct irq_host_ops mpic_host_ops = {
 	.match = mpic_host_match,
 	.map = mpic_host_map,
 	.xlate = mpic_host_xlate,
 };
 /*
  * Exported functions
  */
 struct mpic * __init mpic_alloc(struct device_node *node,
 				phys_addr_t phys_addr,
 				unsigned int flags,
 				unsigned int isu_size,
 				unsigned int irq_count,
 				const char *name)
 {
 	struct mpic	*mpic;
 	u32		greg_feature;
 	const char	*vers;
 	int		i;
 	int		intvec_top;
 	u64		paddr = phys_addr;
 	mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
 	if (mpic == NULL)
 		return NULL;
 	mpic->name = name;
 	mpic->hc_irq = mpic_irq_chip;
 	mpic->hc_irq.name = name;
 	if (flags & MPIC_PRIMARY)
 		mpic->hc_irq.set_affinity = mpic_set_affinity;
 #ifdef CONFIG_MPIC_U3_HT_IRQS
 	mpic->hc_ht_irq = mpic_irq_ht_chip;
 	mpic->hc_ht_irq.name = name;
 	if (flags & MPIC_PRIMARY)
 		mpic->hc_ht_irq.set_affinity = mpic_set_affinity;
 #endif /* CONFIG_MPIC_U3_HT_IRQS */
 #ifdef CONFIG_SMP
 	mpic->hc_ipi = mpic_ipi_chip;
 	mpic->hc_ipi.name = name;
 #endif /* CONFIG_SMP */
 	mpic->flags = flags;
 	mpic->isu_size = isu_size;
 	mpic->irq_count = irq_count;
 	mpic->num_sources = 0; /* so far */
 	if (flags & MPIC_LARGE_VECTORS)
 		intvec_top = 2047;
 	else
 		intvec_top = 255;
 	mpic->timer_vecs[0] = intvec_top - 8;
 	mpic->timer_vecs[1] = intvec_top - 7;
 	mpic->timer_vecs[2] = intvec_top - 6;
 	mpic->timer_vecs[3] = intvec_top - 5;
 	mpic->ipi_vecs[0]   = intvec_top - 4;
 	mpic->ipi_vecs[1]   = intvec_top - 3;
 	mpic->ipi_vecs[2]   = intvec_top - 2;
 	mpic->ipi_vecs[3]   = intvec_top - 1;
 	mpic->spurious_vec  = intvec_top;
 	/* Check for "big-endian" in device-tree */
 	if (node && of_get_property(node, "big-endian", NULL) != NULL)
 		mpic->flags |= MPIC_BIG_ENDIAN;
 	/* Look for protected sources */
 	if (node) {
 		int psize;
 		unsigned int bits, mapsize;
 		const u32 *psrc =
 			of_get_property(node, "protected-sources", &psize);
 		if (psrc) {
 			psize /= 4;
 			bits = intvec_top + 1;
 			mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long);
 			mpic->protected = kzalloc(mapsize, GFP_KERNEL);
 			BUG_ON(mpic->protected == NULL);
 			for (i = 0; i < psize; i++) {
 				if (psrc[i] > intvec_top)
 					continue;
 				__set_bit(psrc[i], mpic->protected);
 			}
 		}
 	}
 #ifdef CONFIG_MPIC_WEIRD
 	mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
 #endif
 	/* default register type */
 	mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
 		mpic_access_mmio_be : mpic_access_mmio_le;
 	/* If no physical address is passed in, a device-node is mandatory */
 	BUG_ON(paddr == 0 && node == NULL);
 	/* If no physical address passed in, check if it's dcr based */
 	if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) {
 #ifdef CONFIG_PPC_DCR
 		mpic->flags |= MPIC_USES_DCR;
 		mpic->reg_type = mpic_access_dcr;
 #else
 		BUG();
 #endif /* CONFIG_PPC_DCR */
 	}
 	/* If the MPIC is not DCR based, and no physical address was passed
 	 * in, try to obtain one
 	 */
 	if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
 		const u32 *reg = of_get_property(node, "reg", NULL);
 		BUG_ON(reg == NULL);
 		paddr = of_translate_address(node, reg);
 		BUG_ON(paddr == OF_BAD_ADDR);
 	}
 	/* Map the global registers */
 	mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
 	mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
 	/* Reset */
 	if (flags & MPIC_WANTS_RESET) {
 		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
 			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
 			   | MPIC_GREG_GCONF_RESET);
 		while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
 		       & MPIC_GREG_GCONF_RESET)
 			mb();
 	}
 	/* CoreInt */
 	if (flags & MPIC_ENABLE_COREINT)
 		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
 			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
 			   | MPIC_GREG_GCONF_COREINT);
 	if (flags & MPIC_ENABLE_MCK)
 		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
 			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
 			   | MPIC_GREG_GCONF_MCK);
 	/* Read feature register, calculate num CPUs and, for non-ISU
 	 * MPICs, num sources as well. On ISU MPICs, sources are counted
 	 * as ISUs are added
 	 */
 	greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
 	mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK)
 			  >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
 	if (isu_size == 0) {
 		if (flags & MPIC_BROKEN_FRR_NIRQS)
 			mpic->num_sources = mpic->irq_count;
 		else
 			mpic->num_sources =
 				((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
 				 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
 	}
 	/* Map the per-CPU registers */
 	for (i = 0; i < mpic->num_cpus; i++) {
 		mpic_map(mpic, node, paddr, &mpic->cpuregs[i],
 			 MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),
 			 0x1000);
 	}
 	/* Initialize main ISU if none provided */
 	if (mpic->isu_size == 0) {
 		mpic->isu_size = mpic->num_sources;
 		mpic_map(mpic, node, paddr, &mpic->isus[0],
 			 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
 	}
 	mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
 	mpic->isu_mask = (1 << mpic->isu_shift) - 1;
 	mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
 				       isu_size ? isu_size : mpic->num_sources,
 				       &mpic_host_ops,
 				       flags & MPIC_LARGE_VECTORS ? 2048 : 256);
 	if (mpic->irqhost == NULL)
 		return NULL;
 	mpic->irqhost->host_data = mpic;
 	/* Display version */
 	switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
 	case 1:
 		vers = "1.0";
 		break;
 	case 2:
 		vers = "1.2";
 		break;
 	case 3:
 		vers = "1.3";
 		break;
 	default:
 		vers = "<unknown>";
 		break;
 	}
 	printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
 	       " max %d CPUs\n",
 	       name, vers, (unsigned long long)paddr, mpic->num_cpus);
 	printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
 	       mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
 	mpic->next = mpics;
 	mpics = mpic;
 	if (flags & MPIC_PRIMARY) {
 		mpic_primary = mpic;
 		irq_set_default_host(mpic->irqhost);
 	}
 	return mpic;
 }
 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
 			    phys_addr_t paddr)
 {
 	unsigned int isu_first = isu_num * mpic->isu_size;
 	BUG_ON(isu_num >= MPIC_MAX_ISU);
 	mpic_map(mpic, mpic->irqhost->of_node,
 		 paddr, &mpic->isus[isu_num], 0,
 		 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
 	if ((isu_first + mpic->isu_size) > mpic->num_sources)
 		mpic->num_sources = isu_first + mpic->isu_size;
 }
 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
 {
 	mpic->senses = senses;
 	mpic->senses_count = count;
 }
 void __init mpic_init(struct mpic *mpic)
 {
 	int i;
 	int cpu;
 	BUG_ON(mpic->num_sources == 0);
 	printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
 	/* Set current processor priority to max */
 	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
 	/* Initialize timers: just disable them all */
 	for (i = 0; i < 4; i++) {
 		mpic_write(mpic->tmregs,
 			   i * MPIC_INFO(TIMER_STRIDE) +
 			   MPIC_INFO(TIMER_DESTINATION), 0);
 		mpic_write(mpic->tmregs,
 			   i * MPIC_INFO(TIMER_STRIDE) +
 			   MPIC_INFO(TIMER_VECTOR_PRI),
 			   MPIC_VECPRI_MASK |
 			   (mpic->timer_vecs[0] + i));
 	}
 	/* Initialize IPIs to our reserved vectors and mark them disabled for now */
 	mpic_test_broken_ipi(mpic);
 	for (i = 0; i < 4; i++) {
 		mpic_ipi_write(i,
 			       MPIC_VECPRI_MASK |
 			       (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
 			       (mpic->ipi_vecs[0] + i));
 	}
 	/* Initialize interrupt sources */
 	if (mpic->irq_count == 0)
 		mpic->irq_count = mpic->num_sources;
 	/* Do the HT PIC fixups on U3 broken mpic */
 	DBG("MPIC flags: %x\n", mpic->flags);
 	if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {
 		mpic_scan_ht_pics(mpic);
 		mpic_u3msi_init(mpic);
 	}
 	mpic_pasemi_msi_init(mpic);
 	if (mpic->flags & MPIC_PRIMARY)
 		cpu = hard_smp_processor_id();
 	else
 		cpu = 0;
 	for (i = 0; i < mpic->num_sources; i++) {
 		/* start with vector = source number, and masked */
 		u32 vecpri = MPIC_VECPRI_MASK | i |
 			(8 << MPIC_VECPRI_PRIORITY_SHIFT);
 		/* check if protected */
 		if (mpic->protected && test_bit(i, mpic->protected))
 			continue;
 		/* init hw */
 		mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
 		mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
 	}
 	/* Init spurious vector */
 	mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
 	/* Disable 8259 passthrough, if supported */
 	if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
 		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
 			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
 			   | MPIC_GREG_GCONF_8259_PTHROU_DIS);
 	if (mpic->flags & MPIC_NO_BIAS)
 		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
 			mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
 			| MPIC_GREG_GCONF_NO_BIAS);
 	/* Set current processor priority to 0 */
 	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
 #ifdef CONFIG_PM
 	/* allocate memory to save mpic state */
 	mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),
 				  GFP_KERNEL);
 	BUG_ON(mpic->save_data == NULL);
 #endif
 }
 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
 {
 	u32 v;
 	v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
 	v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
 	v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
 	mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
 }
 void __init mpic_set_serial_int(struct mpic *mpic, int enable)
 {
 	unsigned long flags;
 	u32 v;
 	raw_spin_lock_irqsave(&mpic_lock, flags);
 	v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
 	if (enable)
 		v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
 	else
 		v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
 	mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
 	raw_spin_unlock_irqrestore(&mpic_lock, flags);
 }
 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
 {
 	struct mpic *mpic = mpic_find(irq);
 	unsigned int src = mpic_irq_to_hw(irq);
 	unsigned long flags;
 	u32 reg;
 	if (!mpic)
 		return;
 	raw_spin_lock_irqsave(&mpic_lock, flags);
 	if (mpic_is_ipi(mpic, irq)) {
 		reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
 			~MPIC_VECPRI_PRIORITY_MASK;
 		mpic_ipi_write(src - mpic->ipi_vecs[0],
 			       reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
 	} else {
 		reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
 			& ~MPIC_VECPRI_PRIORITY_MASK;
 		mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
 			       reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
 	}
 	raw_spin_unlock_irqrestore(&mpic_lock, flags);
 }
 void mpic_setup_this_cpu(void)
 {
 #ifdef CONFIG_SMP
 	struct mpic *mpic = mpic_primary;
 	unsigned long flags;
 	u32 msk = 1 << hard_smp_processor_id();
 	unsigned int i;
 	BUG_ON(mpic == NULL);
 	DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
 	raw_spin_lock_irqsave(&mpic_lock, flags);
  	/* let the mpic know we want intrs. default affinity is 0xffffffff
 	 * until changed via /proc. That's how it's done on x86. If we want
 	 * it differently, then we should make sure we also change the default
 	 * values of irq_desc[].affinity in irq.c.
  	 */
 	if (distribute_irqs) {
 	 	for (i = 0; i < mpic->num_sources ; i++)
 			mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
 				mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
 	}
 	/* Set current processor priority to 0 */
 	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
 	raw_spin_unlock_irqrestore(&mpic_lock, flags);
 #endif /* CONFIG_SMP */
 }
 int mpic_cpu_get_priority(void)
 {
 	struct mpic *mpic = mpic_primary;
 	return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
 }
 void mpic_cpu_set_priority(int prio)
 {
 	struct mpic *mpic = mpic_primary;
 	prio &= MPIC_CPU_TASKPRI_MASK;
 	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
 }
 void mpic_teardown_this_cpu(int secondary)
 {
 	struct mpic *mpic = mpic_primary;
 	unsigned long flags;
 	u32 msk = 1 << hard_smp_processor_id();
 	unsigned int i;
 	BUG_ON(mpic == NULL);
 	DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
 	raw_spin_lock_irqsave(&mpic_lock, flags);
 	/* let the mpic know we don't want intrs.  */
 	for (i = 0; i < mpic->num_sources ; i++)
 		mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
 			mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
 	/* Set current processor priority to max */
 	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
 	/* We need to EOI the IPI since not all platforms reset the MPIC
 	 * on boot and new interrupts wouldn't get delivered otherwise.
 	 */
 	mpic_eoi(mpic);
 	raw_spin_unlock_irqrestore(&mpic_lock, flags);
 }
 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
 {
 	u32 src;
 	src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
 #ifdef DEBUG_LOW
 	DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
 #endif
 	if (unlikely(src == mpic->spurious_vec)) {
 		if (mpic->flags & MPIC_SPV_EOI)
 			mpic_eoi(mpic);
 		return NO_IRQ;
 	}
 	if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
 		if (printk_ratelimit())
 			printk(KERN_WARNING "%s: Got protected source %d !\n",
 			       mpic->name, (int)src);
 		mpic_eoi(mpic);
 		return NO_IRQ;
 	}
 	return irq_linear_revmap(mpic->irqhost, src);
 }
 unsigned int mpic_get_one_irq(struct mpic *mpic)
 {
 	return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
 }
 unsigned int mpic_get_irq(void)
 {
 	struct mpic *mpic = mpic_primary;
 	BUG_ON(mpic == NULL);
 	return mpic_get_one_irq(mpic);
 }
 unsigned int mpic_get_coreint_irq(void)
 {
 #ifdef CONFIG_BOOKE
 	struct mpic *mpic = mpic_primary;
 	u32 src;
 	BUG_ON(mpic == NULL);
 	src = mfspr(SPRN_EPR);
 	if (unlikely(src == mpic->spurious_vec)) {
 		if (mpic->flags & MPIC_SPV_EOI)
 			mpic_eoi(mpic);
 		return NO_IRQ;
 	}
 	if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
 		if (printk_ratelimit())
 			printk(KERN_WARNING "%s: Got protected source %d !\n",
 			       mpic->name, (int)src);
 		return NO_IRQ;
 	}
 	return irq_linear_revmap(mpic->irqhost, src);
 #else
 	return NO_IRQ;
 #endif
 }
 unsigned int mpic_get_mcirq(void)
 {
 	struct mpic *mpic = mpic_primary;
 	BUG_ON(mpic == NULL);
 	return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
 }
 #ifdef CONFIG_SMP
 void mpic_request_ipis(void)
 {
 	struct mpic *mpic = mpic_primary;
 	int i;
 	BUG_ON(mpic == NULL);
 	printk(KERN_INFO "mpic: requesting IPIs...\n");
 	for (i = 0; i < 4; i++) {
 		unsigned int vipi = irq_create_mapping(mpic->irqhost,
 						       mpic->ipi_vecs[0] + i);
 		if (vipi == NO_IRQ) {
 			printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
 			continue;
 		}
 		smp_request_message_ipi(vipi, i);
 	}
 }
 static void mpic_send_ipi(unsigned int ipi_no, const struct cpumask *cpu_mask)
 {
 	struct mpic *mpic = mpic_primary;
 	BUG_ON(mpic == NULL);
 #ifdef DEBUG_IPI
 	DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
 #endif
 	mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
 		       ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
 		       mpic_physmask(cpumask_bits(cpu_mask)[0]));
 }
 void smp_mpic_message_pass(int target, int msg)
 {
 	cpumask_var_t tmp;
 	/* make sure we're sending something that translates to an IPI */
 	if ((unsigned int)msg > 3) {
 		printk("SMP %d: smp_message_pass: unknown msg %d\n",
 		       smp_processor_id(), msg);
 		return;
 	}
 	switch (target) {
 	case MSG_ALL:
 		mpic_send_ipi(msg, cpu_online_mask);
 		break;
 	case MSG_ALL_BUT_SELF:
 		alloc_cpumask_var(&tmp, GFP_NOWAIT);
 		cpumask_andnot(tmp, cpu_online_mask,
 			       cpumask_of(smp_processor_id()));
 		mpic_send_ipi(msg, tmp);
 		free_cpumask_var(tmp);
 		break;
 	default:
 		mpic_send_ipi(msg, cpumask_of(target));
 		break;
 	}
 }
 int __init smp_mpic_probe(void)
 {
 	int nr_cpus;
 	DBG("smp_mpic_probe()...\n");
 	nr_cpus = cpumask_weight(cpu_possible_mask);
 	DBG("nr_cpus: %d\n", nr_cpus);
 	if (nr_cpus > 1)
 		mpic_request_ipis();
 	return nr_cpus;
 }
 void __devinit smp_mpic_setup_cpu(int cpu)
 {
 	mpic_setup_this_cpu();
 }
 void mpic_reset_core(int cpu)
 {
 	struct mpic *mpic = mpic_primary;
 	u32 pir;
 	int cpuid = get_hard_smp_processor_id(cpu);
 	/* Set target bit for core reset */
 	pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
 	pir |= (1 << cpuid);
 	mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
 	mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
 	/* Restore target bit after reset complete */
 	pir &= ~(1 << cpuid);
 	mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
 	mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
 }
 #endif /* CONFIG_SMP */
 #ifdef CONFIG_PM
 static int mpic_suspend(struct sys_device *dev, pm_message_t state)
 {
 	struct mpic *mpic = container_of(dev, struct mpic, sysdev);
 	int i;
 	for (i = 0; i < mpic->num_sources; i++) {
 		mpic->save_data[i].vecprio =
 			mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
 		mpic->save_data[i].dest =
 			mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
 	}
 	return 0;
 }
 static int mpic_resume(struct sys_device *dev)
 {
 	struct mpic *mpic = container_of(dev, struct mpic, sysdev);
 	int i;
 	for (i = 0; i < mpic->num_sources; i++) {
 		mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
 			       mpic->save_data[i].vecprio);
 		mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
 			       mpic->save_data[i].dest);
 #ifdef CONFIG_MPIC_U3_HT_IRQS
 	if (mpic->fixups) {
 		struct mpic_irq_fixup *fixup = &mpic->fixups[i];
 		if (fixup->base) {
 			/* we use the lowest bit in an inverted meaning */
 			if ((mpic->save_data[i].fixup_data & 1) == 0)
 				continue;
 			/* Enable and configure */
 			writeb(0x10 + 2 * fixup->index, fixup->base + 2);
 			writel(mpic->save_data[i].fixup_data & ~1,
 			       fixup->base + 4);
 		}
 	}
 #endif
 	} /* end for loop */
 	return 0;
 }
 #endif
 static struct sysdev_class mpic_sysclass = {
 #ifdef CONFIG_PM
 	.resume = mpic_resume,
 	.suspend = mpic_suspend,
 #endif
 	.name = "mpic",
 };
 static int mpic_init_sys(void)
 {
 	struct mpic *mpic = mpics;
 	int error, id = 0;
 	error = sysdev_class_register(&mpic_sysclass);
 	while (mpic && !error) {
 		mpic->sysdev.cls = &mpic_sysclass;
 		mpic->sysdev.id = id++;
 		error = sysdev_register(&mpic->sysdev);
 		mpic = mpic->next;
 	}
 	return error;
 }
 device_initcall(mpic_init_sys);