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Commit 8dd523118bfbcaca5b67923ff6ee546e04a4db64

Authored by Ben Dooks
Committed by Russell King
1 parent 330d57fb98
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

[ARM] 3136/1: Anubis - fix map_desc initialisers 

Patch from Ben Dooks

Fix the map_desc initialisers for the Simtec Anubis
board to match the new initialiser scheme.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Showing 1 changed file with 42 additions and 9 deletions Inline Diff

arch/arm/mach-s3c2410/mach-anubis.c
Diff comments   View file @ 8dd5231
1 /* linux/arch/arm/mach-s3c2410/mach-anubis.c 1 /* linux/arch/arm/mach-s3c2410/mach-anubis.c
2 * 2 *
3 * Copyright (c) 2003-2005 Simtec Electronics 3 * Copyright (c) 2003-2005 Simtec Electronics
4 * http://armlinux.simtec.co.uk/ 4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk> 5 * Ben Dooks <ben@simtec.co.uk>
6 * 6 *
7 * 7 *
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 * 12 *
13 * Modifications: 13 * Modifications:
14 * 02-May-2005 BJD Copied from mach-bast.c 14 * 02-May-2005 BJD Copied from mach-bast.c
15 * 20-Sep-2005 BJD Added static to non-exported items 15 * 20-Sep-2005 BJD Added static to non-exported items
16 */ 16 */
17 17
18 #include <linux/kernel.h> 18 #include <linux/kernel.h>
19 #include <linux/types.h> 19 #include <linux/types.h>
20 #include <linux/interrupt.h> 20 #include <linux/interrupt.h>
21 #include <linux/list.h> 21 #include <linux/list.h>
22 #include <linux/timer.h> 22 #include <linux/timer.h>
23 #include <linux/init.h> 23 #include <linux/init.h>
24 #include <linux/platform_device.h> 24 #include <linux/platform_device.h>
25 25
26 #include <asm/mach/arch.h> 26 #include <asm/mach/arch.h>
27 #include <asm/mach/map.h> 27 #include <asm/mach/map.h>
28 #include <asm/mach/irq.h> 28 #include <asm/mach/irq.h>
29 29
30 #include <asm/arch/anubis-map.h> 30 #include <asm/arch/anubis-map.h>
31 #include <asm/arch/anubis-irq.h> 31 #include <asm/arch/anubis-irq.h>
32 #include <asm/arch/anubis-cpld.h> 32 #include <asm/arch/anubis-cpld.h>
33 33
34 #include <asm/hardware.h> 34 #include <asm/hardware.h>
35 #include <asm/io.h> 35 #include <asm/io.h>
36 #include <asm/irq.h> 36 #include <asm/irq.h>
37 #include <asm/mach-types.h> 37 #include <asm/mach-types.h>
38 38
39 #include <asm/arch/regs-serial.h> 39 #include <asm/arch/regs-serial.h>
40 #include <asm/arch/regs-gpio.h> 40 #include <asm/arch/regs-gpio.h>
41 #include <asm/arch/regs-mem.h> 41 #include <asm/arch/regs-mem.h>
42 #include <asm/arch/regs-lcd.h> 42 #include <asm/arch/regs-lcd.h>
43 #include <asm/arch/nand.h> 43 #include <asm/arch/nand.h>
44 44
45 #include <linux/mtd/mtd.h> 45 #include <linux/mtd/mtd.h>
46 #include <linux/mtd/nand.h> 46 #include <linux/mtd/nand.h>
47 #include <linux/mtd/nand_ecc.h> 47 #include <linux/mtd/nand_ecc.h>
48 #include <linux/mtd/partitions.h> 48 #include <linux/mtd/partitions.h>
49 49
50 #include "clock.h" 50 #include "clock.h"
51 #include "devs.h" 51 #include "devs.h"
52 #include "cpu.h" 52 #include "cpu.h"
53 53
54 #define COPYRIGHT ", (c) 2005 Simtec Electronics" 54 #define COPYRIGHT ", (c) 2005 Simtec Electronics"
55 55
56 static struct map_desc anubis_iodesc[] __initdata = { 56 static struct map_desc anubis_iodesc[] __initdata = {
57 /* ISA IO areas */ 57 /* ISA IO areas */
58 58
59 { (u32)S3C24XX_VA_ISA_BYTE, 0x0, SZ_16M, MT_DEVICE }, 59 {
60 { (u32)S3C24XX_VA_ISA_WORD, 0x0, SZ_16M, MT_DEVICE }, 60 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
61 .pfn = __phys_to_pfn(0x0),
62 .length = SZ_4M,
63 .type = MT_DEVICE
64 }, {
65 .virtual = (u32)S3C24XX_VA_ISA_WORD,
66 .pfn = __phys_to_pfn(0x0),
67 .length = SZ_4M, MT_DEVICE
68 },
61 69
62 /* we could possibly compress the next set down into a set of smaller tables 70 /* we could possibly compress the next set down into a set of smaller tables
63 * pagetables, but that would mean using an L2 section, and it still means 71 * pagetables, but that would mean using an L2 section, and it still means
64 * we cannot actually feed the same register to an LDR due to 16K spacing 72 * we cannot actually feed the same register to an LDR due to 16K spacing
65 */ 73 */
66 74
67 /* CPLD control registers */ 75 /* CPLD control registers */
68 76
69 { (u32)ANUBIS_VA_CTRL1, ANUBIS_PA_CTRL1, SZ_4K, MT_DEVICE }, 77 {
70 { (u32)ANUBIS_VA_CTRL2, ANUBIS_PA_CTRL2, SZ_4K, MT_DEVICE }, 78 .virtual = (u32)ANUBIS_VA_CTRL1,
79 .pfn = __phys_to_pfn(ANUBIS_PA_CTRL1),
80 .length = SZ_4K,
81 .type = MT_DEVICE
82 }, {
83 .virtual = (u32)ANUBIS_VA_CTRL2,
84 .pfn = __phys_to_pfn(ANUBIS_PA_CTRL2),
85 .length = SZ_4K,
86 .type =MT_DEVICE
87 },
71 88
72 /* IDE drives */ 89 /* IDE drives */
73 90
74 { (u32)ANUBIS_IDEPRI, S3C2410_CS3, SZ_1M, MT_DEVICE }, 91 {
75 { (u32)ANUBIS_IDEPRIAUX, S3C2410_CS3+(1<<26), SZ_1M, MT_DEVICE }, 92 .virtual = (u32)ANUBIS_IDEPRI,
76 93 .pfn = __phys_to_pfn(S3C2410_CS3),
77 { (u32)ANUBIS_IDESEC, S3C2410_CS4, SZ_1M, MT_DEVICE }, 94 .length = SZ_1M,
78 { (u32)ANUBIS_IDESECAUX, S3C2410_CS4+(1<<26), SZ_1M, MT_DEVICE }, 95 .type = MT_DEVICE
96 }, {
97 .virtual = (u32)ANUBIS_IDEPRIAUX,
98 .pfn = __phys_to_pfn(S3C2410_CS3+(1<<26)),
99 .length = SZ_1M,
100 .type = MT_DEVICE
101 }, {
102 .virtual = (u32)ANUBIS_IDESEC,
103 .pfn = __phys_to_pfn(S3C2410_CS4),
104 .length = SZ_1M,
105 .type = MT_DEVICE
106 }, {
107 .virtual = (u32)ANUBIS_IDESECAUX,
108 .pfn = __phys_to_pfn(S3C2410_CS4+(1<<26)),
109 .length = SZ_1M,
110 .type = MT_DEVICE
111 },
79 }; 112 };
80 113
81 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK 114 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
82 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB 115 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
83 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE 116 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
84 117
85 static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = { 118 static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
86 [0] = { 119 [0] = {
87 .name = "uclk", 120 .name = "uclk",
88 .divisor = 1, 121 .divisor = 1,
89 .min_baud = 0, 122 .min_baud = 0,
90 .max_baud = 0, 123 .max_baud = 0,
91 }, 124 },
92 [1] = { 125 [1] = {
93 .name = "pclk", 126 .name = "pclk",
94 .divisor = 1, 127 .divisor = 1,
95 .min_baud = 0, 128 .min_baud = 0,
96 .max_baud = 0. 129 .max_baud = 0.
97 } 130 }
98 }; 131 };
99 132
100 133
101 static struct s3c2410_uartcfg anubis_uartcfgs[] = { 134 static struct s3c2410_uartcfg anubis_uartcfgs[] = {
102 [0] = { 135 [0] = {
103 .hwport = 0, 136 .hwport = 0,
104 .flags = 0, 137 .flags = 0,
105 .ucon = UCON, 138 .ucon = UCON,
106 .ulcon = ULCON, 139 .ulcon = ULCON,
107 .ufcon = UFCON, 140 .ufcon = UFCON,
108 .clocks = anubis_serial_clocks, 141 .clocks = anubis_serial_clocks,
109 .clocks_size = ARRAY_SIZE(anubis_serial_clocks) 142 .clocks_size = ARRAY_SIZE(anubis_serial_clocks)
110 }, 143 },
111 [1] = { 144 [1] = {
112 .hwport = 2, 145 .hwport = 2,
113 .flags = 0, 146 .flags = 0,
114 .ucon = UCON, 147 .ucon = UCON,
115 .ulcon = ULCON, 148 .ulcon = ULCON,
116 .ufcon = UFCON, 149 .ufcon = UFCON,
117 .clocks = anubis_serial_clocks, 150 .clocks = anubis_serial_clocks,
118 .clocks_size = ARRAY_SIZE(anubis_serial_clocks) 151 .clocks_size = ARRAY_SIZE(anubis_serial_clocks)
119 }, 152 },
120 }; 153 };
121 154
122 /* NAND Flash on Anubis board */ 155 /* NAND Flash on Anubis board */
123 156
124 static int external_map[] = { 2 }; 157 static int external_map[] = { 2 };
125 static int chip0_map[] = { 0 }; 158 static int chip0_map[] = { 0 };
126 static int chip1_map[] = { 1 }; 159 static int chip1_map[] = { 1 };
127 160
128 static struct mtd_partition anubis_default_nand_part[] = { 161 static struct mtd_partition anubis_default_nand_part[] = {
129 [0] = { 162 [0] = {
130 .name = "Boot Agent", 163 .name = "Boot Agent",
131 .size = SZ_16K, 164 .size = SZ_16K,
132 .offset = 0 165 .offset = 0
133 }, 166 },
134 [1] = { 167 [1] = {
135 .name = "/boot", 168 .name = "/boot",
136 .size = SZ_4M - SZ_16K, 169 .size = SZ_4M - SZ_16K,
137 .offset = SZ_16K, 170 .offset = SZ_16K,
138 }, 171 },
139 [2] = { 172 [2] = {
140 .name = "user1", 173 .name = "user1",
141 .offset = SZ_4M, 174 .offset = SZ_4M,
142 .size = SZ_32M - SZ_4M, 175 .size = SZ_32M - SZ_4M,
143 }, 176 },
144 [3] = { 177 [3] = {
145 .name = "user2", 178 .name = "user2",
146 .offset = SZ_32M, 179 .offset = SZ_32M,
147 .size = MTDPART_SIZ_FULL, 180 .size = MTDPART_SIZ_FULL,
148 } 181 }
149 }; 182 };
150 183
151 /* the Anubis has 3 selectable slots for nand-flash, the two 184 /* the Anubis has 3 selectable slots for nand-flash, the two
152 * on-board chip areas, as well as the external slot. 185 * on-board chip areas, as well as the external slot.
153 * 186 *
154 * Note, there is no current hot-plug support for the External 187 * Note, there is no current hot-plug support for the External
155 * socket. 188 * socket.
156 */ 189 */
157 190
158 static struct s3c2410_nand_set anubis_nand_sets[] = { 191 static struct s3c2410_nand_set anubis_nand_sets[] = {
159 [1] = { 192 [1] = {
160 .name = "External", 193 .name = "External",
161 .nr_chips = 1, 194 .nr_chips = 1,
162 .nr_map = external_map, 195 .nr_map = external_map,
163 .nr_partitions = ARRAY_SIZE(anubis_default_nand_part), 196 .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
164 .partitions = anubis_default_nand_part 197 .partitions = anubis_default_nand_part
165 }, 198 },
166 [0] = { 199 [0] = {
167 .name = "chip0", 200 .name = "chip0",
168 .nr_chips = 1, 201 .nr_chips = 1,
169 .nr_map = chip0_map, 202 .nr_map = chip0_map,
170 .nr_partitions = ARRAY_SIZE(anubis_default_nand_part), 203 .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
171 .partitions = anubis_default_nand_part 204 .partitions = anubis_default_nand_part
172 }, 205 },
173 [2] = { 206 [2] = {
174 .name = "chip1", 207 .name = "chip1",
175 .nr_chips = 1, 208 .nr_chips = 1,
176 .nr_map = chip1_map, 209 .nr_map = chip1_map,
177 .nr_partitions = ARRAY_SIZE(anubis_default_nand_part), 210 .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
178 .partitions = anubis_default_nand_part 211 .partitions = anubis_default_nand_part
179 }, 212 },
180 }; 213 };
181 214
182 static void anubis_nand_select(struct s3c2410_nand_set *set, int slot) 215 static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
183 { 216 {
184 unsigned int tmp; 217 unsigned int tmp;
185 218
186 slot = set->nr_map[slot] & 3; 219 slot = set->nr_map[slot] & 3;
187 220
188 pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n", 221 pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
189 slot, set, set->nr_map); 222 slot, set, set->nr_map);
190 223
191 tmp = __raw_readb(ANUBIS_VA_CTRL1); 224 tmp = __raw_readb(ANUBIS_VA_CTRL1);
192 tmp &= ~ANUBIS_CTRL1_NANDSEL; 225 tmp &= ~ANUBIS_CTRL1_NANDSEL;
193 tmp |= slot; 226 tmp |= slot;
194 227
195 pr_debug("anubis_nand: ctrl1 now %02x\n", tmp); 228 pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);
196 229
197 __raw_writeb(tmp, ANUBIS_VA_CTRL1); 230 __raw_writeb(tmp, ANUBIS_VA_CTRL1);
198 } 231 }
199 232
200 static struct s3c2410_platform_nand anubis_nand_info = { 233 static struct s3c2410_platform_nand anubis_nand_info = {
201 .tacls = 25, 234 .tacls = 25,
202 .twrph0 = 80, 235 .twrph0 = 80,
203 .twrph1 = 80, 236 .twrph1 = 80,
204 .nr_sets = ARRAY_SIZE(anubis_nand_sets), 237 .nr_sets = ARRAY_SIZE(anubis_nand_sets),
205 .sets = anubis_nand_sets, 238 .sets = anubis_nand_sets,
206 .select_chip = anubis_nand_select, 239 .select_chip = anubis_nand_select,
207 }; 240 };
208 241
209 242
210 /* Standard Anubis devices */ 243 /* Standard Anubis devices */
211 244
212 static struct platform_device *anubis_devices[] __initdata = { 245 static struct platform_device *anubis_devices[] __initdata = {
213 &s3c_device_usb, 246 &s3c_device_usb,
214 &s3c_device_wdt, 247 &s3c_device_wdt,
215 &s3c_device_adc, 248 &s3c_device_adc,
216 &s3c_device_i2c, 249 &s3c_device_i2c,
217 &s3c_device_rtc, 250 &s3c_device_rtc,
218 &s3c_device_nand, 251 &s3c_device_nand,
219 }; 252 };
220 253
221 static struct clk *anubis_clocks[] = { 254 static struct clk *anubis_clocks[] = {
222 &s3c24xx_dclk0, 255 &s3c24xx_dclk0,
223 &s3c24xx_dclk1, 256 &s3c24xx_dclk1,
224 &s3c24xx_clkout0, 257 &s3c24xx_clkout0,
225 &s3c24xx_clkout1, 258 &s3c24xx_clkout1,
226 &s3c24xx_uclk, 259 &s3c24xx_uclk,
227 }; 260 };
228 261
229 static struct s3c24xx_board anubis_board __initdata = { 262 static struct s3c24xx_board anubis_board __initdata = {
230 .devices = anubis_devices, 263 .devices = anubis_devices,
231 .devices_count = ARRAY_SIZE(anubis_devices), 264 .devices_count = ARRAY_SIZE(anubis_devices),
232 .clocks = anubis_clocks, 265 .clocks = anubis_clocks,
233 .clocks_count = ARRAY_SIZE(anubis_clocks) 266 .clocks_count = ARRAY_SIZE(anubis_clocks)
234 }; 267 };
235 268
236 static void __init anubis_map_io(void) 269 static void __init anubis_map_io(void)
237 { 270 {
238 /* initialise the clocks */ 271 /* initialise the clocks */
239 272
240 s3c24xx_dclk0.parent = NULL; 273 s3c24xx_dclk0.parent = NULL;
241 s3c24xx_dclk0.rate = 12*1000*1000; 274 s3c24xx_dclk0.rate = 12*1000*1000;
242 275
243 s3c24xx_dclk1.parent = NULL; 276 s3c24xx_dclk1.parent = NULL;
244 s3c24xx_dclk1.rate = 24*1000*1000; 277 s3c24xx_dclk1.rate = 24*1000*1000;
245 278
246 s3c24xx_clkout0.parent = &s3c24xx_dclk0; 279 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
247 s3c24xx_clkout1.parent = &s3c24xx_dclk1; 280 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
248 281
249 s3c24xx_uclk.parent = &s3c24xx_clkout1; 282 s3c24xx_uclk.parent = &s3c24xx_clkout1;
250 283
251 s3c_device_nand.dev.platform_data = &anubis_nand_info; 284 s3c_device_nand.dev.platform_data = &anubis_nand_info;
252 285
253 s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc)); 286 s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
254 s3c24xx_init_clocks(0); 287 s3c24xx_init_clocks(0);
255 s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs)); 288 s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
256 s3c24xx_set_board(&anubis_board); 289 s3c24xx_set_board(&anubis_board);
257 290
258 /* ensure that the GPIO is setup */ 291 /* ensure that the GPIO is setup */
259 s3c2410_gpio_setpin(S3C2410_GPA0, 1); 292 s3c2410_gpio_setpin(S3C2410_GPA0, 1);
260 } 293 }
261 294
262 MACHINE_START(ANUBIS, "Simtec-Anubis") 295 MACHINE_START(ANUBIS, "Simtec-Anubis")
263 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */ 296 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
264 .phys_ram = S3C2410_SDRAM_PA, 297 .phys_ram = S3C2410_SDRAM_PA,
265 .phys_io = S3C2410_PA_UART, 298 .phys_io = S3C2410_PA_UART,
266 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, 299 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
267 .boot_params = S3C2410_SDRAM_PA + 0x100, 300 .boot_params = S3C2410_SDRAM_PA + 0x100,
268 .map_io = anubis_map_io, 301 .map_io = anubis_map_io,
269 .init_irq = s3c24xx_init_irq, 302 .init_irq = s3c24xx_init_irq,
270 .timer = &s3c24xx_timer, 303 .timer = &s3c24xx_timer,
271 MACHINE_END 304 MACHINE_END
272 305