Doug / smarc-fsl-linux-kernel | Embedian Git Server

Commit 8e65e2f07c1fdbd952570591bf78316aeed1c74a

Authored by Bradley Grove 2013-10-02 02:26:02 +0800

Committed by James Bottomley 2013-10-25 16:58:59 +0800

Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch

[SCSI] esas2r: Fixes for big-endian platforms

In esas2r_format_init_msg(), sgl_page_size and epoch_time params
are converted to little endian and the firmware version read from
the hba is converted to cpu endianess.

In esas2r_rq_init_request, correct and simplify the construction
of the SCSI handle.

These fixes are the result of testing on a PPC64 machine.

Signed-off-by: Bradley Grove <bgrove@attotech.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>

Showing 2 changed files with 9 additions and 9 deletions Inline Diff

drivers/scsi/esas2r/esas2r.h
drivers/scsi/esas2r/esas2r_init.c

drivers/scsi/esas2r/esas2r.h

Diff comments View file @ 8e65e2f

1	/*	1	/*
2	* linux/drivers/scsi/esas2r/esas2r.h	2	* linux/drivers/scsi/esas2r/esas2r.h
3	* For use with ATTO ExpressSAS R6xx SAS/SATA RAID controllers	3	* For use with ATTO ExpressSAS R6xx SAS/SATA RAID controllers
4	*	4	*
5	* Copyright (c) 2001-2013 ATTO Technology, Inc.	5	* Copyright (c) 2001-2013 ATTO Technology, Inc.
6	* (mailto:linuxdrivers@attotech.com)	6	* (mailto:linuxdrivers@attotech.com)
7	*	7	*
8	* This program is free software; you can redistribute it and/or	8	* This program is free software; you can redistribute it and/or
9	* modify it under the terms of the GNU General Public License	9	* modify it under the terms of the GNU General Public License
10	* as published by the Free Software Foundation; either version 2	10	* as published by the Free Software Foundation; either version 2
11	* of the License, or (at your option) any later version.	11	* of the License, or (at your option) any later version.
12	*	12	*
13	* This program is distributed in the hope that it will be useful,	13	* This program is distributed in the hope that it will be useful,
14	* but WITHOUT ANY WARRANTY; without even the implied warranty of	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16	* GNU General Public License for more details.	16	* GNU General Public License for more details.
17	*	17	*
18	* NO WARRANTY	18	* NO WARRANTY
19	* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR	19	* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
20	* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT	20	* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
21	* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,	21	* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
22	* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is	22	* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
23	* solely responsible for determining the appropriateness of using and	23	* solely responsible for determining the appropriateness of using and
24	* distributing the Program and assumes all risks associated with its	24	* distributing the Program and assumes all risks associated with its
25	* exercise of rights under this Agreement, including but not limited to	25	* exercise of rights under this Agreement, including but not limited to
26	* the risks and costs of program errors, damage to or loss of data,	26	* the risks and costs of program errors, damage to or loss of data,
27	* programs or equipment, and unavailability or interruption of operations.	27	* programs or equipment, and unavailability or interruption of operations.
28	*	28	*
29	* DISCLAIMER OF LIABILITY	29	* DISCLAIMER OF LIABILITY
30	* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY	30	* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
31	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL	31	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32	* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND	32	* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
33	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR	33	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
34	* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE	34	* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
35	* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED	35	* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
36	* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES	36	* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
37	*	37	*
38	* You should have received a copy of the GNU General Public License	38	* You should have received a copy of the GNU General Public License
39	* along with this program; if not, write to the Free Software	39	* along with this program; if not, write to the Free Software
40	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,	40	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
41	* USA.	41	* USA.
42	*/	42	*/
43		43
44	#include <linux/kernel.h>	44	#include <linux/kernel.h>
45	#include <linux/delay.h>	45	#include <linux/delay.h>
46	#include <linux/pci.h>	46	#include <linux/pci.h>
47	#include <linux/proc_fs.h>	47	#include <linux/proc_fs.h>
48	#include <linux/workqueue.h>	48	#include <linux/workqueue.h>
49	#include <linux/interrupt.h>	49	#include <linux/interrupt.h>
50	#include <linux/module.h>	50	#include <linux/module.h>
51	#include <linux/vmalloc.h>	51	#include <linux/vmalloc.h>
52	#include <scsi/scsi.h>	52	#include <scsi/scsi.h>
53	#include <scsi/scsi_host.h>	53	#include <scsi/scsi_host.h>
54	#include <scsi/scsi_cmnd.h>	54	#include <scsi/scsi_cmnd.h>
55	#include <scsi/scsi_device.h>	55	#include <scsi/scsi_device.h>
56	#include <scsi/scsi_eh.h>	56	#include <scsi/scsi_eh.h>
57	#include <scsi/scsi_tcq.h>	57	#include <scsi/scsi_tcq.h>
58		58
59	#include "esas2r_log.h"	59	#include "esas2r_log.h"
60	#include "atioctl.h"	60	#include "atioctl.h"
61	#include "atvda.h"	61	#include "atvda.h"
62		62
63	#ifndef ESAS2R_H	63	#ifndef ESAS2R_H
64	#define ESAS2R_H	64	#define ESAS2R_H
65		65
66	/* Global Variables */	66	/* Global Variables */
67	extern struct esas2r_adapter *esas2r_adapters[];	67	extern struct esas2r_adapter *esas2r_adapters[];
68	extern u8 *esas2r_buffered_ioctl;	68	extern u8 *esas2r_buffered_ioctl;
69	extern dma_addr_t esas2r_buffered_ioctl_addr;	69	extern dma_addr_t esas2r_buffered_ioctl_addr;
70	extern u32 esas2r_buffered_ioctl_size;	70	extern u32 esas2r_buffered_ioctl_size;
71	extern struct pci_dev *esas2r_buffered_ioctl_pcid;	71	extern struct pci_dev *esas2r_buffered_ioctl_pcid;
72	#define SGL_PG_SZ_MIN 64	72	#define SGL_PG_SZ_MIN 64
73	#define SGL_PG_SZ_MAX 1024	73	#define SGL_PG_SZ_MAX 1024
74	extern int sgl_page_size;	74	extern int sgl_page_size;
75	#define NUM_SGL_MIN 8	75	#define NUM_SGL_MIN 8
76	#define NUM_SGL_MAX 2048	76	#define NUM_SGL_MAX 2048
77	extern int num_sg_lists;	77	extern int num_sg_lists;
78	#define NUM_REQ_MIN 4	78	#define NUM_REQ_MIN 4
79	#define NUM_REQ_MAX 256	79	#define NUM_REQ_MAX 256
80	extern int num_requests;	80	extern int num_requests;
81	#define NUM_AE_MIN 2	81	#define NUM_AE_MIN 2
82	#define NUM_AE_MAX 8	82	#define NUM_AE_MAX 8
83	extern int num_ae_requests;	83	extern int num_ae_requests;
84	extern int cmd_per_lun;	84	extern int cmd_per_lun;
85	extern int can_queue;	85	extern int can_queue;
86	extern int esas2r_max_sectors;	86	extern int esas2r_max_sectors;
87	extern int sg_tablesize;	87	extern int sg_tablesize;
88	extern int interrupt_mode;	88	extern int interrupt_mode;
89	extern int num_io_requests;	89	extern int num_io_requests;
90		90
91	/* Macro defintions */	91	/* Macro defintions */
92	#define ESAS2R_MAX_ID 255	92	#define ESAS2R_MAX_ID 255
93	#define MAX_ADAPTERS 32	93	#define MAX_ADAPTERS 32
94	#define ESAS2R_DRVR_NAME "esas2r"	94	#define ESAS2R_DRVR_NAME "esas2r"
95	#define ESAS2R_LONGNAME "ATTO ExpressSAS 6GB RAID Adapter"	95	#define ESAS2R_LONGNAME "ATTO ExpressSAS 6GB RAID Adapter"
96	#define ESAS2R_MAX_DEVICES 32	96	#define ESAS2R_MAX_DEVICES 32
97	#define ATTONODE_NAME "ATTONode"	97	#define ATTONODE_NAME "ATTONode"
98	#define ESAS2R_MAJOR_REV 1	98	#define ESAS2R_MAJOR_REV 1
99	#define ESAS2R_MINOR_REV 00	99	#define ESAS2R_MINOR_REV 00
100	#define ESAS2R_VERSION_STR DEFINED_NUM_TO_STR(ESAS2R_MAJOR_REV) "." \	100	#define ESAS2R_VERSION_STR DEFINED_NUM_TO_STR(ESAS2R_MAJOR_REV) "." \
101	DEFINED_NUM_TO_STR(ESAS2R_MINOR_REV)	101	DEFINED_NUM_TO_STR(ESAS2R_MINOR_REV)
102	#define ESAS2R_COPYRIGHT_YEARS "2001-2013"	102	#define ESAS2R_COPYRIGHT_YEARS "2001-2013"
103	#define ESAS2R_DEFAULT_SGL_PAGE_SIZE 384	103	#define ESAS2R_DEFAULT_SGL_PAGE_SIZE 384
104	#define ESAS2R_DEFAULT_CMD_PER_LUN 64	104	#define ESAS2R_DEFAULT_CMD_PER_LUN 64
105	#define ESAS2R_DEFAULT_NUM_SG_LISTS 1024	105	#define ESAS2R_DEFAULT_NUM_SG_LISTS 1024
106	#define DEFINED_NUM_TO_STR(num) NUM_TO_STR(num)	106	#define DEFINED_NUM_TO_STR(num) NUM_TO_STR(num)
107	#define NUM_TO_STR(num) #num	107	#define NUM_TO_STR(num) #num
108		108
109	#define ESAS2R_SGL_ALIGN 16	109	#define ESAS2R_SGL_ALIGN 16
110	#define ESAS2R_LIST_ALIGN 16	110	#define ESAS2R_LIST_ALIGN 16
111	#define ESAS2R_LIST_EXTRA ESAS2R_NUM_EXTRA	111	#define ESAS2R_LIST_EXTRA ESAS2R_NUM_EXTRA
112	#define ESAS2R_DATA_BUF_LEN 256	112	#define ESAS2R_DATA_BUF_LEN 256
113	#define ESAS2R_DEFAULT_TMO 5000	113	#define ESAS2R_DEFAULT_TMO 5000
114	#define ESAS2R_DISC_BUF_LEN 512	114	#define ESAS2R_DISC_BUF_LEN 512
115	#define ESAS2R_FWCOREDUMP_SZ 0x80000	115	#define ESAS2R_FWCOREDUMP_SZ 0x80000
116	#define ESAS2R_NUM_PHYS 8	116	#define ESAS2R_NUM_PHYS 8
117	#define ESAS2R_TARG_ID_INV 0xFFFF	117	#define ESAS2R_TARG_ID_INV 0xFFFF
118	#define ESAS2R_INT_STS_MASK MU_INTSTAT_MASK	118	#define ESAS2R_INT_STS_MASK MU_INTSTAT_MASK
119	#define ESAS2R_INT_ENB_MASK MU_INTSTAT_MASK	119	#define ESAS2R_INT_ENB_MASK MU_INTSTAT_MASK
120	#define ESAS2R_INT_DIS_MASK 0	120	#define ESAS2R_INT_DIS_MASK 0
121	#define ESAS2R_MAX_TARGETS 256	121	#define ESAS2R_MAX_TARGETS 256
122	#define ESAS2R_KOBJ_NAME_LEN 20	122	#define ESAS2R_KOBJ_NAME_LEN 20
123		123
124	/* u16 (WORD) component macros */	124	/* u16 (WORD) component macros */
125	#define LOBYTE(w) ((u8)(u16)(w))	125	#define LOBYTE(w) ((u8)(u16)(w))
126	#define HIBYTE(w) ((u8)(((u16)(w)) >> 8))	126	#define HIBYTE(w) ((u8)(((u16)(w)) >> 8))
127	#define MAKEWORD(lo, hi) ((u16)((u8)(lo) \| ((u16)(u8)(hi) << 8)))	127	#define MAKEWORD(lo, hi) ((u16)((u8)(lo) \| ((u16)(u8)(hi) << 8)))
128		128
129	/* u32 (DWORD) component macros */	129	/* u32 (DWORD) component macros */
130	#define LOWORD(d) ((u16)(u32)(d))	130	#define LOWORD(d) ((u16)(u32)(d))
131	#define HIWORD(d) ((u16)(((u32)(d)) >> 16))	131	#define HIWORD(d) ((u16)(((u32)(d)) >> 16))
132	#define MAKEDWORD(lo, hi) ((u32)((u16)(lo) \| ((u32)(u16)(hi) << 16)))	132	#define MAKEDWORD(lo, hi) ((u32)((u16)(lo) \| ((u32)(u16)(hi) << 16)))
133		133
134	/* macro to get the lowest nonzero bit of a value */	134	/* macro to get the lowest nonzero bit of a value */
135	#define LOBIT(x) ((x) & (0 - (x)))	135	#define LOBIT(x) ((x) & (0 - (x)))
136		136
137	/* These functions are provided to access the chip's control registers.	137	/* These functions are provided to access the chip's control registers.
138	* The register is specified by its byte offset from the register base	138	* The register is specified by its byte offset from the register base
139	* for the adapter.	139	* for the adapter.
140	*/	140	*/
141	#define esas2r_read_register_dword(a, reg) \	141	#define esas2r_read_register_dword(a, reg) \
142	readl((void __iomem *)a->regs + (reg) + MW_REG_OFFSET_HWREG)	142	readl((void __iomem *)a->regs + (reg) + MW_REG_OFFSET_HWREG)
143		143
144	#define esas2r_write_register_dword(a, reg, data) \	144	#define esas2r_write_register_dword(a, reg, data) \
145	writel(data, (void __iomem *)(a->regs + (reg) + MW_REG_OFFSET_HWREG))	145	writel(data, (void __iomem *)(a->regs + (reg) + MW_REG_OFFSET_HWREG))
146		146
147	#define esas2r_flush_register_dword(a, r) esas2r_read_register_dword(a, r)	147	#define esas2r_flush_register_dword(a, r) esas2r_read_register_dword(a, r)
148		148
149	/* This function is provided to access the chip's data window. The	149	/* This function is provided to access the chip's data window. The
150	* register is specified by its byte offset from the window base	150	* register is specified by its byte offset from the window base
151	* for the adapter.	151	* for the adapter.
152	*/	152	*/
153	#define esas2r_read_data_byte(a, reg) \	153	#define esas2r_read_data_byte(a, reg) \
154	readb((void __iomem *)a->data_window + (reg))	154	readb((void __iomem *)a->data_window + (reg))
155		155
156	/* ATTO vendor and device Ids */	156	/* ATTO vendor and device Ids */
157	#define ATTO_VENDOR_ID 0x117C	157	#define ATTO_VENDOR_ID 0x117C
158	#define ATTO_DID_INTEL_IOP348 0x002C	158	#define ATTO_DID_INTEL_IOP348 0x002C
159	#define ATTO_DID_MV_88RC9580 0x0049	159	#define ATTO_DID_MV_88RC9580 0x0049
160	#define ATTO_DID_MV_88RC9580TS 0x0066	160	#define ATTO_DID_MV_88RC9580TS 0x0066
161	#define ATTO_DID_MV_88RC9580TSE 0x0067	161	#define ATTO_DID_MV_88RC9580TSE 0x0067
162	#define ATTO_DID_MV_88RC9580TL 0x0068	162	#define ATTO_DID_MV_88RC9580TL 0x0068
163		163
164	/* ATTO subsystem device Ids */	164	/* ATTO subsystem device Ids */
165	#define ATTO_SSDID_TBT 0x4000	165	#define ATTO_SSDID_TBT 0x4000
166	#define ATTO_TSSC_3808 0x4066	166	#define ATTO_TSSC_3808 0x4066
167	#define ATTO_TSSC_3808E 0x4067	167	#define ATTO_TSSC_3808E 0x4067
168	#define ATTO_TLSH_1068 0x4068	168	#define ATTO_TLSH_1068 0x4068
169	#define ATTO_ESAS_R680 0x0049	169	#define ATTO_ESAS_R680 0x0049
170	#define ATTO_ESAS_R608 0x004A	170	#define ATTO_ESAS_R608 0x004A
171	#define ATTO_ESAS_R60F 0x004B	171	#define ATTO_ESAS_R60F 0x004B
172	#define ATTO_ESAS_R6F0 0x004C	172	#define ATTO_ESAS_R6F0 0x004C
173	#define ATTO_ESAS_R644 0x004D	173	#define ATTO_ESAS_R644 0x004D
174	#define ATTO_ESAS_R648 0x004E	174	#define ATTO_ESAS_R648 0x004E
175		175
176	/*	176	/*
177	* flash definitions & structures	177	* flash definitions & structures
178	* define the code types	178	* define the code types
179	*/	179	*/
180	#define FBT_CPYR 0xAA00	180	#define FBT_CPYR 0xAA00
181	#define FBT_SETUP 0xAA02	181	#define FBT_SETUP 0xAA02
182	#define FBT_FLASH_VER 0xAA04	182	#define FBT_FLASH_VER 0xAA04
183		183
184	/* offsets to various locations in flash */	184	/* offsets to various locations in flash */
185	#define FLS_OFFSET_BOOT (u32)(0x00700000)	185	#define FLS_OFFSET_BOOT (u32)(0x00700000)
186	#define FLS_OFFSET_NVR (u32)(0x007C0000)	186	#define FLS_OFFSET_NVR (u32)(0x007C0000)
187	#define FLS_OFFSET_CPYR FLS_OFFSET_NVR	187	#define FLS_OFFSET_CPYR FLS_OFFSET_NVR
188	#define FLS_LENGTH_BOOT (FLS_OFFSET_CPYR - FLS_OFFSET_BOOT)	188	#define FLS_LENGTH_BOOT (FLS_OFFSET_CPYR - FLS_OFFSET_BOOT)
189	#define FLS_BLOCK_SIZE (u32)(0x00020000)	189	#define FLS_BLOCK_SIZE (u32)(0x00020000)
190	#define FI_NVR_2KB 0x0800	190	#define FI_NVR_2KB 0x0800
191	#define FI_NVR_8KB 0x2000	191	#define FI_NVR_8KB 0x2000
192	#define FM_BUF_SZ 0x800	192	#define FM_BUF_SZ 0x800
193		193
194	/*	194	/*
195	* marvell frey (88R9580) register definitions	195	* marvell frey (88R9580) register definitions
196	* chip revision identifiers	196	* chip revision identifiers
197	*/	197	*/
198	#define MVR_FREY_B2 0xB2	198	#define MVR_FREY_B2 0xB2
199		199
200	/*	200	/*
201	* memory window definitions. window 0 is the data window with definitions	201	* memory window definitions. window 0 is the data window with definitions
202	* of MW_DATA_XXX. window 1 is the register window with definitions of	202	* of MW_DATA_XXX. window 1 is the register window with definitions of
203	* MW_REG_XXX.	203	* MW_REG_XXX.
204	*/	204	*/
205	#define MW_REG_WINDOW_SIZE (u32)(0x00040000)	205	#define MW_REG_WINDOW_SIZE (u32)(0x00040000)
206	#define MW_REG_OFFSET_HWREG (u32)(0x00000000)	206	#define MW_REG_OFFSET_HWREG (u32)(0x00000000)
207	#define MW_REG_OFFSET_PCI (u32)(0x00008000)	207	#define MW_REG_OFFSET_PCI (u32)(0x00008000)
208	#define MW_REG_PCI_HWREG_DELTA (MW_REG_OFFSET_PCI - MW_REG_OFFSET_HWREG)	208	#define MW_REG_PCI_HWREG_DELTA (MW_REG_OFFSET_PCI - MW_REG_OFFSET_HWREG)
209	#define MW_DATA_WINDOW_SIZE (u32)(0x00020000)	209	#define MW_DATA_WINDOW_SIZE (u32)(0x00020000)
210	#define MW_DATA_ADDR_SER_FLASH (u32)(0xEC000000)	210	#define MW_DATA_ADDR_SER_FLASH (u32)(0xEC000000)
211	#define MW_DATA_ADDR_SRAM (u32)(0xF4000000)	211	#define MW_DATA_ADDR_SRAM (u32)(0xF4000000)
212	#define MW_DATA_ADDR_PAR_FLASH (u32)(0xFC000000)	212	#define MW_DATA_ADDR_PAR_FLASH (u32)(0xFC000000)
213		213
214	/*	214	/*
215	* the following registers are for the communication	215	* the following registers are for the communication
216	* list interface (AKA message unit (MU))	216	* list interface (AKA message unit (MU))
217	*/	217	*/
218	#define MU_IN_LIST_ADDR_LO (u32)(0x00004000)	218	#define MU_IN_LIST_ADDR_LO (u32)(0x00004000)
219	#define MU_IN_LIST_ADDR_HI (u32)(0x00004004)	219	#define MU_IN_LIST_ADDR_HI (u32)(0x00004004)
220		220
221	#define MU_IN_LIST_WRITE (u32)(0x00004018)	221	#define MU_IN_LIST_WRITE (u32)(0x00004018)
222	#define MU_ILW_TOGGLE (u32)(0x00004000)	222	#define MU_ILW_TOGGLE (u32)(0x00004000)
223		223
224	#define MU_IN_LIST_READ (u32)(0x0000401C)	224	#define MU_IN_LIST_READ (u32)(0x0000401C)
225	#define MU_ILR_TOGGLE (u32)(0x00004000)	225	#define MU_ILR_TOGGLE (u32)(0x00004000)
226	#define MU_ILIC_LIST (u32)(0x0000000F)	226	#define MU_ILIC_LIST (u32)(0x0000000F)
227	#define MU_ILIC_LIST_F0 (u32)(0x00000000)	227	#define MU_ILIC_LIST_F0 (u32)(0x00000000)
228	#define MU_ILIC_DEST (u32)(0x00000F00)	228	#define MU_ILIC_DEST (u32)(0x00000F00)
229	#define MU_ILIC_DEST_DDR (u32)(0x00000200)	229	#define MU_ILIC_DEST_DDR (u32)(0x00000200)
230	#define MU_IN_LIST_IFC_CONFIG (u32)(0x00004028)	230	#define MU_IN_LIST_IFC_CONFIG (u32)(0x00004028)
231		231
232	#define MU_IN_LIST_CONFIG (u32)(0x0000402C)	232	#define MU_IN_LIST_CONFIG (u32)(0x0000402C)
233	#define MU_ILC_ENABLE (u32)(0x00000001)	233	#define MU_ILC_ENABLE (u32)(0x00000001)
234	#define MU_ILC_ENTRY_MASK (u32)(0x000000F0)	234	#define MU_ILC_ENTRY_MASK (u32)(0x000000F0)
235	#define MU_ILC_ENTRY_4_DW (u32)(0x00000020)	235	#define MU_ILC_ENTRY_4_DW (u32)(0x00000020)
236	#define MU_ILC_DYNAMIC_SRC (u32)(0x00008000)	236	#define MU_ILC_DYNAMIC_SRC (u32)(0x00008000)
237	#define MU_ILC_NUMBER_MASK (u32)(0x7FFF0000)	237	#define MU_ILC_NUMBER_MASK (u32)(0x7FFF0000)
238	#define MU_ILC_NUMBER_SHIFT 16	238	#define MU_ILC_NUMBER_SHIFT 16
239		239
240	#define MU_OUT_LIST_ADDR_LO (u32)(0x00004050)	240	#define MU_OUT_LIST_ADDR_LO (u32)(0x00004050)
241	#define MU_OUT_LIST_ADDR_HI (u32)(0x00004054)	241	#define MU_OUT_LIST_ADDR_HI (u32)(0x00004054)
242		242
243	#define MU_OUT_LIST_COPY_PTR_LO (u32)(0x00004058)	243	#define MU_OUT_LIST_COPY_PTR_LO (u32)(0x00004058)
244	#define MU_OUT_LIST_COPY_PTR_HI (u32)(0x0000405C)	244	#define MU_OUT_LIST_COPY_PTR_HI (u32)(0x0000405C)
245		245
246	#define MU_OUT_LIST_WRITE (u32)(0x00004068)	246	#define MU_OUT_LIST_WRITE (u32)(0x00004068)
247	#define MU_OLW_TOGGLE (u32)(0x00004000)	247	#define MU_OLW_TOGGLE (u32)(0x00004000)
248		248
249	#define MU_OUT_LIST_COPY (u32)(0x0000406C)	249	#define MU_OUT_LIST_COPY (u32)(0x0000406C)
250	#define MU_OLC_TOGGLE (u32)(0x00004000)	250	#define MU_OLC_TOGGLE (u32)(0x00004000)
251	#define MU_OLC_WRT_PTR (u32)(0x00003FFF)	251	#define MU_OLC_WRT_PTR (u32)(0x00003FFF)
252		252
253	#define MU_OUT_LIST_IFC_CONFIG (u32)(0x00004078)	253	#define MU_OUT_LIST_IFC_CONFIG (u32)(0x00004078)
254	#define MU_OLIC_LIST (u32)(0x0000000F)	254	#define MU_OLIC_LIST (u32)(0x0000000F)
255	#define MU_OLIC_LIST_F0 (u32)(0x00000000)	255	#define MU_OLIC_LIST_F0 (u32)(0x00000000)
256	#define MU_OLIC_SOURCE (u32)(0x00000F00)	256	#define MU_OLIC_SOURCE (u32)(0x00000F00)
257	#define MU_OLIC_SOURCE_DDR (u32)(0x00000200)	257	#define MU_OLIC_SOURCE_DDR (u32)(0x00000200)
258		258
259	#define MU_OUT_LIST_CONFIG (u32)(0x0000407C)	259	#define MU_OUT_LIST_CONFIG (u32)(0x0000407C)
260	#define MU_OLC_ENABLE (u32)(0x00000001)	260	#define MU_OLC_ENABLE (u32)(0x00000001)
261	#define MU_OLC_ENTRY_MASK (u32)(0x000000F0)	261	#define MU_OLC_ENTRY_MASK (u32)(0x000000F0)
262	#define MU_OLC_ENTRY_4_DW (u32)(0x00000020)	262	#define MU_OLC_ENTRY_4_DW (u32)(0x00000020)
263	#define MU_OLC_NUMBER_MASK (u32)(0x7FFF0000)	263	#define MU_OLC_NUMBER_MASK (u32)(0x7FFF0000)
264	#define MU_OLC_NUMBER_SHIFT 16	264	#define MU_OLC_NUMBER_SHIFT 16
265		265
266	#define MU_OUT_LIST_INT_STAT (u32)(0x00004088)	266	#define MU_OUT_LIST_INT_STAT (u32)(0x00004088)
267	#define MU_OLIS_INT (u32)(0x00000001)	267	#define MU_OLIS_INT (u32)(0x00000001)
268		268
269	#define MU_OUT_LIST_INT_MASK (u32)(0x0000408C)	269	#define MU_OUT_LIST_INT_MASK (u32)(0x0000408C)
270	#define MU_OLIS_MASK (u32)(0x00000001)	270	#define MU_OLIS_MASK (u32)(0x00000001)
271		271
272	/*	272	/*
273	* the maximum size of the communication lists is two greater than the	273	* the maximum size of the communication lists is two greater than the
274	* maximum amount of VDA requests. the extra are to prevent queue overflow.	274	* maximum amount of VDA requests. the extra are to prevent queue overflow.
275	*/	275	*/
276	#define ESAS2R_MAX_NUM_REQS 256	276	#define ESAS2R_MAX_NUM_REQS 256
277	#define ESAS2R_NUM_EXTRA 2	277	#define ESAS2R_NUM_EXTRA 2
278	#define ESAS2R_MAX_COMM_LIST_SIZE (ESAS2R_MAX_NUM_REQS + ESAS2R_NUM_EXTRA)	278	#define ESAS2R_MAX_COMM_LIST_SIZE (ESAS2R_MAX_NUM_REQS + ESAS2R_NUM_EXTRA)
279		279
280	/*	280	/*
281	* the following registers are for the CPU interface	281	* the following registers are for the CPU interface
282	*/	282	*/
283	#define MU_CTL_STATUS_IN (u32)(0x00010108)	283	#define MU_CTL_STATUS_IN (u32)(0x00010108)
284	#define MU_CTL_IN_FULL_RST (u32)(0x00000020)	284	#define MU_CTL_IN_FULL_RST (u32)(0x00000020)
285	#define MU_CTL_STATUS_IN_B2 (u32)(0x00010130)	285	#define MU_CTL_STATUS_IN_B2 (u32)(0x00010130)
286	#define MU_CTL_IN_FULL_RST2 (u32)(0x80000000)	286	#define MU_CTL_IN_FULL_RST2 (u32)(0x80000000)
287	#define MU_DOORBELL_IN (u32)(0x00010460)	287	#define MU_DOORBELL_IN (u32)(0x00010460)
288	#define DRBL_RESET_BUS (u32)(0x00000002)	288	#define DRBL_RESET_BUS (u32)(0x00000002)
289	#define DRBL_PAUSE_AE (u32)(0x00000004)	289	#define DRBL_PAUSE_AE (u32)(0x00000004)
290	#define DRBL_RESUME_AE (u32)(0x00000008)	290	#define DRBL_RESUME_AE (u32)(0x00000008)
291	#define DRBL_MSG_IFC_DOWN (u32)(0x00000010)	291	#define DRBL_MSG_IFC_DOWN (u32)(0x00000010)
292	#define DRBL_FLASH_REQ (u32)(0x00000020)	292	#define DRBL_FLASH_REQ (u32)(0x00000020)
293	#define DRBL_FLASH_DONE (u32)(0x00000040)	293	#define DRBL_FLASH_DONE (u32)(0x00000040)
294	#define DRBL_FORCE_INT (u32)(0x00000080)	294	#define DRBL_FORCE_INT (u32)(0x00000080)
295	#define DRBL_MSG_IFC_INIT (u32)(0x00000100)	295	#define DRBL_MSG_IFC_INIT (u32)(0x00000100)
296	#define DRBL_POWER_DOWN (u32)(0x00000200)	296	#define DRBL_POWER_DOWN (u32)(0x00000200)
297	#define DRBL_DRV_VER_1 (u32)(0x00010000)	297	#define DRBL_DRV_VER_1 (u32)(0x00010000)
298	#define DRBL_DRV_VER DRBL_DRV_VER_1	298	#define DRBL_DRV_VER DRBL_DRV_VER_1
299	#define MU_DOORBELL_IN_ENB (u32)(0x00010464)	299	#define MU_DOORBELL_IN_ENB (u32)(0x00010464)
300	#define MU_DOORBELL_OUT (u32)(0x00010480)	300	#define MU_DOORBELL_OUT (u32)(0x00010480)
301	#define DRBL_PANIC_REASON_MASK (u32)(0x00F00000)	301	#define DRBL_PANIC_REASON_MASK (u32)(0x00F00000)
302	#define DRBL_UNUSED_HANDLER (u32)(0x00100000)	302	#define DRBL_UNUSED_HANDLER (u32)(0x00100000)
303	#define DRBL_UNDEF_INSTR (u32)(0x00200000)	303	#define DRBL_UNDEF_INSTR (u32)(0x00200000)
304	#define DRBL_PREFETCH_ABORT (u32)(0x00300000)	304	#define DRBL_PREFETCH_ABORT (u32)(0x00300000)
305	#define DRBL_DATA_ABORT (u32)(0x00400000)	305	#define DRBL_DATA_ABORT (u32)(0x00400000)
306	#define DRBL_JUMP_TO_ZERO (u32)(0x00500000)	306	#define DRBL_JUMP_TO_ZERO (u32)(0x00500000)
307	#define DRBL_FW_RESET (u32)(0x00080000)	307	#define DRBL_FW_RESET (u32)(0x00080000)
308	#define DRBL_FW_VER_MSK (u32)(0x00070000)	308	#define DRBL_FW_VER_MSK (u32)(0x00070000)
309	#define DRBL_FW_VER_0 (u32)(0x00000000)	309	#define DRBL_FW_VER_0 (u32)(0x00000000)
310	#define DRBL_FW_VER_1 (u32)(0x00010000)	310	#define DRBL_FW_VER_1 (u32)(0x00010000)
311	#define DRBL_FW_VER DRBL_FW_VER_1	311	#define DRBL_FW_VER DRBL_FW_VER_1
312	#define MU_DOORBELL_OUT_ENB (u32)(0x00010484)	312	#define MU_DOORBELL_OUT_ENB (u32)(0x00010484)
313	#define DRBL_ENB_MASK (u32)(0x00F803FF)	313	#define DRBL_ENB_MASK (u32)(0x00F803FF)
314	#define MU_INT_STATUS_OUT (u32)(0x00010200)	314	#define MU_INT_STATUS_OUT (u32)(0x00010200)
315	#define MU_INTSTAT_POST_OUT (u32)(0x00000010)	315	#define MU_INTSTAT_POST_OUT (u32)(0x00000010)
316	#define MU_INTSTAT_DRBL_IN (u32)(0x00000100)	316	#define MU_INTSTAT_DRBL_IN (u32)(0x00000100)
317	#define MU_INTSTAT_DRBL (u32)(0x00001000)	317	#define MU_INTSTAT_DRBL (u32)(0x00001000)
318	#define MU_INTSTAT_MASK (u32)(0x00001010)	318	#define MU_INTSTAT_MASK (u32)(0x00001010)
319	#define MU_INT_MASK_OUT (u32)(0x0001020C)	319	#define MU_INT_MASK_OUT (u32)(0x0001020C)
320		320
321	/* PCI express registers accessed via window 1 */	321	/* PCI express registers accessed via window 1 */
322	#define MVR_PCI_WIN1_REMAP (u32)(0x00008438)	322	#define MVR_PCI_WIN1_REMAP (u32)(0x00008438)
323	#define MVRPW1R_ENABLE (u32)(0x00000001)	323	#define MVRPW1R_ENABLE (u32)(0x00000001)
324		324
325		325
326	/* structures */	326	/* structures */
327		327
328	/* inbound list dynamic source entry */	328	/* inbound list dynamic source entry */
329	struct esas2r_inbound_list_source_entry {	329	struct esas2r_inbound_list_source_entry {
330	u64 address;	330	u64 address;
331	u32 length;	331	u32 length;
332	#define HWILSE_INTERFACE_F0 0x00000000	332	#define HWILSE_INTERFACE_F0 0x00000000
333	u32 reserved;	333	u32 reserved;
334	};	334	};
335		335
336	/* PCI data structure in expansion ROM images */	336	/* PCI data structure in expansion ROM images */
337	struct __packed esas2r_boot_header {	337	struct __packed esas2r_boot_header {
338	char signature[4];	338	char signature[4];
339	u16 vendor_id;	339	u16 vendor_id;
340	u16 device_id;	340	u16 device_id;
341	u16 VPD;	341	u16 VPD;
342	u16 struct_length;	342	u16 struct_length;
343	u8 struct_revision;	343	u8 struct_revision;
344	u8 class_code[3];	344	u8 class_code[3];
345	u16 image_length;	345	u16 image_length;
346	u16 code_revision;	346	u16 code_revision;
347	u8 code_type;	347	u8 code_type;
348	#define CODE_TYPE_PC 0	348	#define CODE_TYPE_PC 0
349	#define CODE_TYPE_OPEN 1	349	#define CODE_TYPE_OPEN 1
350	#define CODE_TYPE_EFI 3	350	#define CODE_TYPE_EFI 3
351	u8 indicator;	351	u8 indicator;
352	#define INDICATOR_LAST 0x80	352	#define INDICATOR_LAST 0x80
353	u8 reserved[2];	353	u8 reserved[2];
354	};	354	};
355		355
356	struct __packed esas2r_boot_image {	356	struct __packed esas2r_boot_image {
357	u16 signature;	357	u16 signature;
358	u8 reserved[22];	358	u8 reserved[22];
359	u16 header_offset;	359	u16 header_offset;
360	u16 pnp_offset;	360	u16 pnp_offset;
361	};	361	};
362		362
363	struct __packed esas2r_pc_image {	363	struct __packed esas2r_pc_image {
364	u16 signature;	364	u16 signature;
365	u8 length;	365	u8 length;
366	u8 entry_point[3];	366	u8 entry_point[3];
367	u8 checksum;	367	u8 checksum;
368	u16 image_end;	368	u16 image_end;
369	u16 min_size;	369	u16 min_size;
370	u8 rom_flags;	370	u8 rom_flags;
371	u8 reserved[12];	371	u8 reserved[12];
372	u16 header_offset;	372	u16 header_offset;
373	u16 pnp_offset;	373	u16 pnp_offset;
374	struct esas2r_boot_header boot_image;	374	struct esas2r_boot_header boot_image;
375	};	375	};
376		376
377	struct __packed esas2r_efi_image {	377	struct __packed esas2r_efi_image {
378	u16 signature;	378	u16 signature;
379	u16 length;	379	u16 length;
380	u32 efi_signature;	380	u32 efi_signature;
381	#define EFI_ROM_SIG 0x00000EF1	381	#define EFI_ROM_SIG 0x00000EF1
382	u16 image_type;	382	u16 image_type;
383	#define EFI_IMAGE_APP 10	383	#define EFI_IMAGE_APP 10
384	#define EFI_IMAGE_BSD 11	384	#define EFI_IMAGE_BSD 11
385	#define EFI_IMAGE_RTD 12	385	#define EFI_IMAGE_RTD 12
386	u16 machine_type;	386	u16 machine_type;
387	#define EFI_MACHINE_IA32 0x014c	387	#define EFI_MACHINE_IA32 0x014c
388	#define EFI_MACHINE_IA64 0x0200	388	#define EFI_MACHINE_IA64 0x0200
389	#define EFI_MACHINE_X64 0x8664	389	#define EFI_MACHINE_X64 0x8664
390	#define EFI_MACHINE_EBC 0x0EBC	390	#define EFI_MACHINE_EBC 0x0EBC
391	u16 compression;	391	u16 compression;
392	#define EFI_UNCOMPRESSED 0x0000	392	#define EFI_UNCOMPRESSED 0x0000
393	#define EFI_COMPRESSED 0x0001	393	#define EFI_COMPRESSED 0x0001
394	u8 reserved[8];	394	u8 reserved[8];
395	u16 efi_offset;	395	u16 efi_offset;
396	u16 header_offset;	396	u16 header_offset;
397	u16 reserved2;	397	u16 reserved2;
398	struct esas2r_boot_header boot_image;	398	struct esas2r_boot_header boot_image;
399	};	399	};
400		400
401	struct esas2r_adapter;	401	struct esas2r_adapter;
402	struct esas2r_sg_context;	402	struct esas2r_sg_context;
403	struct esas2r_request;	403	struct esas2r_request;
404		404
405	typedef void (RQCALLBK) (struct esas2r_adapter a,	405	typedef void (RQCALLBK) (struct esas2r_adapter a,
406	struct esas2r_request *rq);	406	struct esas2r_request *rq);
407	typedef bool (RQBUILDSGL) (struct esas2r_adapter a,	407	typedef bool (RQBUILDSGL) (struct esas2r_adapter a,
408	struct esas2r_sg_context *sgc);	408	struct esas2r_sg_context *sgc);
409		409
410	struct esas2r_component_header {	410	struct esas2r_component_header {
411	u8 img_type;	411	u8 img_type;
412	#define CH_IT_FW 0x00	412	#define CH_IT_FW 0x00
413	#define CH_IT_NVR 0x01	413	#define CH_IT_NVR 0x01
414	#define CH_IT_BIOS 0x02	414	#define CH_IT_BIOS 0x02
415	#define CH_IT_MAC 0x03	415	#define CH_IT_MAC 0x03
416	#define CH_IT_CFG 0x04	416	#define CH_IT_CFG 0x04
417	#define CH_IT_EFI 0x05	417	#define CH_IT_EFI 0x05
418	u8 status;	418	u8 status;
419	#define CH_STAT_PENDING 0xff	419	#define CH_STAT_PENDING 0xff
420	#define CH_STAT_FAILED 0x00	420	#define CH_STAT_FAILED 0x00
421	#define CH_STAT_SUCCESS 0x01	421	#define CH_STAT_SUCCESS 0x01
422	#define CH_STAT_RETRY 0x02	422	#define CH_STAT_RETRY 0x02
423	#define CH_STAT_INVALID 0x03	423	#define CH_STAT_INVALID 0x03
424	u8 pad[2];	424	u8 pad[2];
425	u32 version;	425	u32 version;
426	u32 length;	426	u32 length;
427	u32 image_offset;	427	u32 image_offset;
428	};	428	};
429		429
430	#define FI_REL_VER_SZ 16	430	#define FI_REL_VER_SZ 16
431		431
432	struct esas2r_flash_img_v0 {	432	struct esas2r_flash_img_v0 {
433	u8 fi_version;	433	u8 fi_version;
434	#define FI_VERSION_0 00	434	#define FI_VERSION_0 00
435	u8 status;	435	u8 status;
436	u8 adap_typ;	436	u8 adap_typ;
437	u8 action;	437	u8 action;
438	u32 length;	438	u32 length;
439	u16 checksum;	439	u16 checksum;
440	u16 driver_error;	440	u16 driver_error;
441	u16 flags;	441	u16 flags;
442	u16 num_comps;	442	u16 num_comps;
443	#define FI_NUM_COMPS_V0 5	443	#define FI_NUM_COMPS_V0 5
444	u8 rel_version[FI_REL_VER_SZ];	444	u8 rel_version[FI_REL_VER_SZ];
445	struct esas2r_component_header cmp_hdr[FI_NUM_COMPS_V0];	445	struct esas2r_component_header cmp_hdr[FI_NUM_COMPS_V0];
446	u8 scratch_buf[FM_BUF_SZ];	446	u8 scratch_buf[FM_BUF_SZ];
447	};	447	};
448		448
449	struct esas2r_flash_img {	449	struct esas2r_flash_img {
450	u8 fi_version;	450	u8 fi_version;
451	#define FI_VERSION_1 01	451	#define FI_VERSION_1 01
452	u8 status;	452	u8 status;
453	#define FI_STAT_SUCCESS 0x00	453	#define FI_STAT_SUCCESS 0x00
454	#define FI_STAT_FAILED 0x01	454	#define FI_STAT_FAILED 0x01
455	#define FI_STAT_REBOOT 0x02	455	#define FI_STAT_REBOOT 0x02
456	#define FI_STAT_ADAPTYP 0x03	456	#define FI_STAT_ADAPTYP 0x03
457	#define FI_STAT_INVALID 0x04	457	#define FI_STAT_INVALID 0x04
458	#define FI_STAT_CHKSUM 0x05	458	#define FI_STAT_CHKSUM 0x05
459	#define FI_STAT_LENGTH 0x06	459	#define FI_STAT_LENGTH 0x06
460	#define FI_STAT_UNKNOWN 0x07	460	#define FI_STAT_UNKNOWN 0x07
461	#define FI_STAT_IMG_VER 0x08	461	#define FI_STAT_IMG_VER 0x08
462	#define FI_STAT_BUSY 0x09	462	#define FI_STAT_BUSY 0x09
463	#define FI_STAT_DUAL 0x0A	463	#define FI_STAT_DUAL 0x0A
464	#define FI_STAT_MISSING 0x0B	464	#define FI_STAT_MISSING 0x0B
465	#define FI_STAT_UNSUPP 0x0C	465	#define FI_STAT_UNSUPP 0x0C
466	#define FI_STAT_ERASE 0x0D	466	#define FI_STAT_ERASE 0x0D
467	#define FI_STAT_FLASH 0x0E	467	#define FI_STAT_FLASH 0x0E
468	#define FI_STAT_DEGRADED 0x0F	468	#define FI_STAT_DEGRADED 0x0F
469	u8 adap_typ;	469	u8 adap_typ;
470	#define FI_AT_UNKNWN 0xFF	470	#define FI_AT_UNKNWN 0xFF
471	#define FI_AT_SUN_LAKE 0x0B	471	#define FI_AT_SUN_LAKE 0x0B
472	#define FI_AT_MV_9580 0x0F	472	#define FI_AT_MV_9580 0x0F
473	u8 action;	473	u8 action;
474	#define FI_ACT_DOWN 0x00	474	#define FI_ACT_DOWN 0x00
475	#define FI_ACT_UP 0x01	475	#define FI_ACT_UP 0x01
476	#define FI_ACT_UPSZ 0x02	476	#define FI_ACT_UPSZ 0x02
477	#define FI_ACT_MAX 0x02	477	#define FI_ACT_MAX 0x02
478	#define FI_ACT_DOWN1 0x80	478	#define FI_ACT_DOWN1 0x80
479	u32 length;	479	u32 length;
480	u16 checksum;	480	u16 checksum;
481	u16 driver_error;	481	u16 driver_error;
482	u16 flags;	482	u16 flags;
483	#define FI_FLG_NVR_DEF 0x0001	483	#define FI_FLG_NVR_DEF 0x0001
484	u16 num_comps;	484	u16 num_comps;
485	#define FI_NUM_COMPS_V1 6	485	#define FI_NUM_COMPS_V1 6
486	u8 rel_version[FI_REL_VER_SZ];	486	u8 rel_version[FI_REL_VER_SZ];
487	struct esas2r_component_header cmp_hdr[FI_NUM_COMPS_V1];	487	struct esas2r_component_header cmp_hdr[FI_NUM_COMPS_V1];
488	u8 scratch_buf[FM_BUF_SZ];	488	u8 scratch_buf[FM_BUF_SZ];
489	};	489	};
490		490
491	/* definitions for flash script (FS) commands */	491	/* definitions for flash script (FS) commands */
492	struct esas2r_ioctlfs_command {	492	struct esas2r_ioctlfs_command {
493	u8 command;	493	u8 command;
494	#define ESAS2R_FS_CMD_ERASE 0	494	#define ESAS2R_FS_CMD_ERASE 0
495	#define ESAS2R_FS_CMD_READ 1	495	#define ESAS2R_FS_CMD_READ 1
496	#define ESAS2R_FS_CMD_BEGINW 2	496	#define ESAS2R_FS_CMD_BEGINW 2
497	#define ESAS2R_FS_CMD_WRITE 3	497	#define ESAS2R_FS_CMD_WRITE 3
498	#define ESAS2R_FS_CMD_COMMIT 4	498	#define ESAS2R_FS_CMD_COMMIT 4
499	#define ESAS2R_FS_CMD_CANCEL 5	499	#define ESAS2R_FS_CMD_CANCEL 5
500	u8 checksum;	500	u8 checksum;
501	u8 reserved[2];	501	u8 reserved[2];
502	u32 flash_addr;	502	u32 flash_addr;
503	u32 length;	503	u32 length;
504	u32 image_offset;	504	u32 image_offset;
505	};	505	};
506		506
507	struct esas2r_ioctl_fs {	507	struct esas2r_ioctl_fs {
508	u8 version;	508	u8 version;
509	#define ESAS2R_FS_VER 0	509	#define ESAS2R_FS_VER 0
510	u8 status;	510	u8 status;
511	u8 driver_error;	511	u8 driver_error;
512	u8 adap_type;	512	u8 adap_type;
513	#define ESAS2R_FS_AT_ESASRAID2 3	513	#define ESAS2R_FS_AT_ESASRAID2 3
514	#define ESAS2R_FS_AT_TSSASRAID2 4	514	#define ESAS2R_FS_AT_TSSASRAID2 4
515	#define ESAS2R_FS_AT_TSSASRAID2E 5	515	#define ESAS2R_FS_AT_TSSASRAID2E 5
516	#define ESAS2R_FS_AT_TLSASHBA 6	516	#define ESAS2R_FS_AT_TLSASHBA 6
517	u8 driver_ver;	517	u8 driver_ver;
518	u8 reserved[11];	518	u8 reserved[11];
519	struct esas2r_ioctlfs_command command;	519	struct esas2r_ioctlfs_command command;
520	u8 data[1];	520	u8 data[1];
521	};	521	};
522		522
523	struct esas2r_sas_nvram {	523	struct esas2r_sas_nvram {
524	u8 signature[4];	524	u8 signature[4];
525	u8 version;	525	u8 version;
526	#define SASNVR_VERSION_0 0x00	526	#define SASNVR_VERSION_0 0x00
527	#define SASNVR_VERSION SASNVR_VERSION_0	527	#define SASNVR_VERSION SASNVR_VERSION_0
528	u8 checksum;	528	u8 checksum;
529	#define SASNVR_CKSUM_SEED 0x5A	529	#define SASNVR_CKSUM_SEED 0x5A
530	u8 max_lun_for_target;	530	u8 max_lun_for_target;
531	u8 pci_latency;	531	u8 pci_latency;
532	#define SASNVR_PCILAT_DIS 0x00	532	#define SASNVR_PCILAT_DIS 0x00
533	#define SASNVR_PCILAT_MIN 0x10	533	#define SASNVR_PCILAT_MIN 0x10
534	#define SASNVR_PCILAT_MAX 0xF8	534	#define SASNVR_PCILAT_MAX 0xF8
535	u8 options1;	535	u8 options1;
536	#define SASNVR1_BOOT_DRVR 0x01	536	#define SASNVR1_BOOT_DRVR 0x01
537	#define SASNVR1_BOOT_SCAN 0x02	537	#define SASNVR1_BOOT_SCAN 0x02
538	#define SASNVR1_DIS_PCI_MWI 0x04	538	#define SASNVR1_DIS_PCI_MWI 0x04
539	#define SASNVR1_FORCE_ORD_Q 0x08	539	#define SASNVR1_FORCE_ORD_Q 0x08
540	#define SASNVR1_CACHELINE_0 0x10	540	#define SASNVR1_CACHELINE_0 0x10
541	#define SASNVR1_DIS_DEVSORT 0x20	541	#define SASNVR1_DIS_DEVSORT 0x20
542	#define SASNVR1_PWR_MGT_EN 0x40	542	#define SASNVR1_PWR_MGT_EN 0x40
543	#define SASNVR1_WIDEPORT 0x80	543	#define SASNVR1_WIDEPORT 0x80
544	u8 options2;	544	u8 options2;
545	#define SASNVR2_SINGLE_BUS 0x01	545	#define SASNVR2_SINGLE_BUS 0x01
546	#define SASNVR2_SLOT_BIND 0x02	546	#define SASNVR2_SLOT_BIND 0x02
547	#define SASNVR2_EXP_PROG 0x04	547	#define SASNVR2_EXP_PROG 0x04
548	#define SASNVR2_CMDTHR_LUN 0x08	548	#define SASNVR2_CMDTHR_LUN 0x08
549	#define SASNVR2_HEARTBEAT 0x10	549	#define SASNVR2_HEARTBEAT 0x10
550	#define SASNVR2_INT_CONNECT 0x20	550	#define SASNVR2_INT_CONNECT 0x20
551	#define SASNVR2_SW_MUX_CTRL 0x40	551	#define SASNVR2_SW_MUX_CTRL 0x40
552	#define SASNVR2_DISABLE_NCQ 0x80	552	#define SASNVR2_DISABLE_NCQ 0x80
553	u8 int_coalescing;	553	u8 int_coalescing;
554	#define SASNVR_COAL_DIS 0x00	554	#define SASNVR_COAL_DIS 0x00
555	#define SASNVR_COAL_LOW 0x01	555	#define SASNVR_COAL_LOW 0x01
556	#define SASNVR_COAL_MED 0x02	556	#define SASNVR_COAL_MED 0x02
557	#define SASNVR_COAL_HI 0x03	557	#define SASNVR_COAL_HI 0x03
558	u8 cmd_throttle;	558	u8 cmd_throttle;
559	#define SASNVR_CMDTHR_NONE 0x00	559	#define SASNVR_CMDTHR_NONE 0x00
560	u8 dev_wait_time;	560	u8 dev_wait_time;
561	u8 dev_wait_count;	561	u8 dev_wait_count;
562	u8 spin_up_delay;	562	u8 spin_up_delay;
563	#define SASNVR_SPINUP_MAX 0x14	563	#define SASNVR_SPINUP_MAX 0x14
564	u8 ssp_align_rate;	564	u8 ssp_align_rate;
565	u8 sas_addr[8];	565	u8 sas_addr[8];
566	u8 phy_speed[16];	566	u8 phy_speed[16];
567	#define SASNVR_SPEED_AUTO 0x00	567	#define SASNVR_SPEED_AUTO 0x00
568	#define SASNVR_SPEED_1_5GB 0x01	568	#define SASNVR_SPEED_1_5GB 0x01
569	#define SASNVR_SPEED_3GB 0x02	569	#define SASNVR_SPEED_3GB 0x02
570	#define SASNVR_SPEED_6GB 0x03	570	#define SASNVR_SPEED_6GB 0x03
571	#define SASNVR_SPEED_12GB 0x04	571	#define SASNVR_SPEED_12GB 0x04
572	u8 phy_mux[16];	572	u8 phy_mux[16];
573	#define SASNVR_MUX_DISABLED 0x00	573	#define SASNVR_MUX_DISABLED 0x00
574	#define SASNVR_MUX_1_5GB 0x01	574	#define SASNVR_MUX_1_5GB 0x01
575	#define SASNVR_MUX_3GB 0x02	575	#define SASNVR_MUX_3GB 0x02
576	#define SASNVR_MUX_6GB 0x03	576	#define SASNVR_MUX_6GB 0x03
577	u8 phy_flags[16];	577	u8 phy_flags[16];
578	#define SASNVR_PHF_DISABLED 0x01	578	#define SASNVR_PHF_DISABLED 0x01
579	#define SASNVR_PHF_RD_ONLY 0x02	579	#define SASNVR_PHF_RD_ONLY 0x02
580	u8 sort_type;	580	u8 sort_type;
581	#define SASNVR_SORT_SAS_ADDR 0x00	581	#define SASNVR_SORT_SAS_ADDR 0x00
582	#define SASNVR_SORT_H308_CONN 0x01	582	#define SASNVR_SORT_H308_CONN 0x01
583	#define SASNVR_SORT_PHY_ID 0x02	583	#define SASNVR_SORT_PHY_ID 0x02
584	#define SASNVR_SORT_SLOT_ID 0x03	584	#define SASNVR_SORT_SLOT_ID 0x03
585	u8 dpm_reqcmd_lmt;	585	u8 dpm_reqcmd_lmt;
586	u8 dpm_stndby_time;	586	u8 dpm_stndby_time;
587	u8 dpm_active_time;	587	u8 dpm_active_time;
588	u8 phy_target_id[16];	588	u8 phy_target_id[16];
589	#define SASNVR_PTI_DISABLED 0xFF	589	#define SASNVR_PTI_DISABLED 0xFF
590	u8 virt_ses_mode;	590	u8 virt_ses_mode;
591	#define SASNVR_VSMH_DISABLED 0x00	591	#define SASNVR_VSMH_DISABLED 0x00
592	u8 read_write_mode;	592	u8 read_write_mode;
593	#define SASNVR_RWM_DEFAULT 0x00	593	#define SASNVR_RWM_DEFAULT 0x00
594	u8 link_down_to;	594	u8 link_down_to;
595	u8 reserved[0xA1];	595	u8 reserved[0xA1];
596	};	596	};
597		597
598	typedef u32 (PGETPHYSADDR) (struct esas2r_sg_context sgc, u64 *addr);	598	typedef u32 (PGETPHYSADDR) (struct esas2r_sg_context sgc, u64 *addr);
599		599
600	struct esas2r_sg_context {	600	struct esas2r_sg_context {
601	struct esas2r_adapter *adapter;	601	struct esas2r_adapter *adapter;
602	struct esas2r_request *first_req;	602	struct esas2r_request *first_req;
603	u32 length;	603	u32 length;
604	u8 *cur_offset;	604	u8 *cur_offset;
605	PGETPHYSADDR get_phys_addr;	605	PGETPHYSADDR get_phys_addr;
606	union {	606	union {
607	struct {	607	struct {
608	struct atto_vda_sge *curr;	608	struct atto_vda_sge *curr;
609	struct atto_vda_sge *last;	609	struct atto_vda_sge *last;
610	struct atto_vda_sge *limit;	610	struct atto_vda_sge *limit;
611	struct atto_vda_sge *chain;	611	struct atto_vda_sge *chain;
612	} a64;	612	} a64;
613	struct {	613	struct {
614	struct atto_physical_region_description *curr;	614	struct atto_physical_region_description *curr;
615	struct atto_physical_region_description *chain;	615	struct atto_physical_region_description *chain;
616	u32 sgl_max_cnt;	616	u32 sgl_max_cnt;
617	u32 sge_cnt;	617	u32 sge_cnt;
618	} prd;	618	} prd;
619	} sge;	619	} sge;
620	struct scatterlist *cur_sgel;	620	struct scatterlist *cur_sgel;
621	u8 *exp_offset;	621	u8 *exp_offset;
622	int num_sgel;	622	int num_sgel;
623	int sgel_count;	623	int sgel_count;
624	};	624	};
625		625
626	struct esas2r_target {	626	struct esas2r_target {
627	u8 flags;	627	u8 flags;
628	#define TF_PASS_THRU 0x01	628	#define TF_PASS_THRU 0x01
629	#define TF_USED 0x02	629	#define TF_USED 0x02
630	u8 new_target_state;	630	u8 new_target_state;
631	u8 target_state;	631	u8 target_state;
632	u8 buffered_target_state;	632	u8 buffered_target_state;
633	#define TS_NOT_PRESENT 0x00	633	#define TS_NOT_PRESENT 0x00
634	#define TS_PRESENT 0x05	634	#define TS_PRESENT 0x05
635	#define TS_LUN_CHANGE 0x06	635	#define TS_LUN_CHANGE 0x06
636	#define TS_INVALID 0xFF	636	#define TS_INVALID 0xFF
637	u32 block_size;	637	u32 block_size;
638	u32 inter_block;	638	u32 inter_block;
639	u32 inter_byte;	639	u32 inter_byte;
640	u16 virt_targ_id;	640	u16 virt_targ_id;
641	u16 phys_targ_id;	641	u16 phys_targ_id;
642	u8 identifier_len;	642	u8 identifier_len;
643	u64 sas_addr;	643	u64 sas_addr;
644	u8 identifier[60];	644	u8 identifier[60];
645	struct atto_vda_ae_lu lu_event;	645	struct atto_vda_ae_lu lu_event;
646	};	646	};
647		647
648	struct esas2r_request {	648	struct esas2r_request {
649	struct list_head comp_list;	649	struct list_head comp_list;
650	struct list_head req_list;	650	struct list_head req_list;
651	union atto_vda_req *vrq;	651	union atto_vda_req *vrq;
652	struct esas2r_mem_desc *vrq_md;	652	struct esas2r_mem_desc *vrq_md;
653	union {	653	union {
654	void *data_buf;	654	void *data_buf;
655	union atto_vda_rsp_data *vda_rsp_data;	655	union atto_vda_rsp_data *vda_rsp_data;
656	};	656	};
657	u8 *sense_buf;	657	u8 *sense_buf;
658	struct list_head sg_table_head;	658	struct list_head sg_table_head;
659	struct esas2r_mem_desc *sg_table;	659	struct esas2r_mem_desc *sg_table;
660	u32 timeout;	660	u32 timeout;
661	#define RQ_TIMEOUT_S1 0xFFFFFFFF	661	#define RQ_TIMEOUT_S1 0xFFFFFFFF
662	#define RQ_TIMEOUT_S2 0xFFFFFFFE	662	#define RQ_TIMEOUT_S2 0xFFFFFFFE
663	#define RQ_MAX_TIMEOUT 0xFFFFFFFD	663	#define RQ_MAX_TIMEOUT 0xFFFFFFFD
664	u16 target_id;	664	u16 target_id;
665	u8 req_type;	665	u8 req_type;
666	#define RT_INI_REQ 0x01	666	#define RT_INI_REQ 0x01
667	#define RT_DISC_REQ 0x02	667	#define RT_DISC_REQ 0x02
668	u8 sense_len;	668	u8 sense_len;
669	union atto_vda_func_rsp func_rsp;	669	union atto_vda_func_rsp func_rsp;
670	RQCALLBK comp_cb;	670	RQCALLBK comp_cb;
671	RQCALLBK interrupt_cb;	671	RQCALLBK interrupt_cb;
672	void *interrupt_cx;	672	void *interrupt_cx;
673	u8 flags;	673	u8 flags;
674	#define RF_1ST_IBLK_BASE 0x04	674	#define RF_1ST_IBLK_BASE 0x04
675	#define RF_FAILURE_OK 0x08	675	#define RF_FAILURE_OK 0x08
676	u8 req_stat;	676	u8 req_stat;
677	u16 vda_req_sz;	677	u16 vda_req_sz;
678	#define RQ_SIZE_DEFAULT 0	678	#define RQ_SIZE_DEFAULT 0
679	u64 lba;	679	u64 lba;
680	RQCALLBK aux_req_cb;	680	RQCALLBK aux_req_cb;
681	void *aux_req_cx;	681	void *aux_req_cx;
682	u32 blk_len;	682	u32 blk_len;
683	u32 max_blk_len;	683	u32 max_blk_len;
684	union {	684	union {
685	struct scsi_cmnd *cmd;	685	struct scsi_cmnd *cmd;
686	u8 *task_management_status_ptr;	686	u8 *task_management_status_ptr;
687	};	687	};
688	};	688	};
689		689
690	struct esas2r_flash_context {	690	struct esas2r_flash_context {
691	struct esas2r_flash_img *fi;	691	struct esas2r_flash_img *fi;
692	RQCALLBK interrupt_cb;	692	RQCALLBK interrupt_cb;
693	u8 *sgc_offset;	693	u8 *sgc_offset;
694	u8 *scratch;	694	u8 *scratch;
695	u32 fi_hdr_len;	695	u32 fi_hdr_len;
696	u8 task;	696	u8 task;
697	#define FMTSK_ERASE_BOOT 0	697	#define FMTSK_ERASE_BOOT 0
698	#define FMTSK_WRTBIOS 1	698	#define FMTSK_WRTBIOS 1
699	#define FMTSK_READBIOS 2	699	#define FMTSK_READBIOS 2
700	#define FMTSK_WRTMAC 3	700	#define FMTSK_WRTMAC 3
701	#define FMTSK_READMAC 4	701	#define FMTSK_READMAC 4
702	#define FMTSK_WRTEFI 5	702	#define FMTSK_WRTEFI 5
703	#define FMTSK_READEFI 6	703	#define FMTSK_READEFI 6
704	#define FMTSK_WRTCFG 7	704	#define FMTSK_WRTCFG 7
705	#define FMTSK_READCFG 8	705	#define FMTSK_READCFG 8
706	u8 func;	706	u8 func;
707	u16 num_comps;	707	u16 num_comps;
708	u32 cmp_len;	708	u32 cmp_len;
709	u32 flsh_addr;	709	u32 flsh_addr;
710	u32 curr_len;	710	u32 curr_len;
711	u8 comp_typ;	711	u8 comp_typ;
712	struct esas2r_sg_context sgc;	712	struct esas2r_sg_context sgc;
713	};	713	};
714		714
715	struct esas2r_disc_context {	715	struct esas2r_disc_context {
716	u8 disc_evt;	716	u8 disc_evt;
717	#define DCDE_DEV_CHANGE 0x01	717	#define DCDE_DEV_CHANGE 0x01
718	#define DCDE_DEV_SCAN 0x02	718	#define DCDE_DEV_SCAN 0x02
719	u8 state;	719	u8 state;
720	#define DCS_DEV_RMV 0x00	720	#define DCS_DEV_RMV 0x00
721	#define DCS_DEV_ADD 0x01	721	#define DCS_DEV_ADD 0x01
722	#define DCS_BLOCK_DEV_SCAN 0x02	722	#define DCS_BLOCK_DEV_SCAN 0x02
723	#define DCS_RAID_GRP_INFO 0x03	723	#define DCS_RAID_GRP_INFO 0x03
724	#define DCS_PART_INFO 0x04	724	#define DCS_PART_INFO 0x04
725	#define DCS_PT_DEV_INFO 0x05	725	#define DCS_PT_DEV_INFO 0x05
726	#define DCS_PT_DEV_ADDR 0x06	726	#define DCS_PT_DEV_ADDR 0x06
727	#define DCS_DISC_DONE 0xFF	727	#define DCS_DISC_DONE 0xFF
728	u16 flags;	728	u16 flags;
729	#define DCF_DEV_CHANGE 0x0001	729	#define DCF_DEV_CHANGE 0x0001
730	#define DCF_DEV_SCAN 0x0002	730	#define DCF_DEV_SCAN 0x0002
731	#define DCF_POLLED 0x8000	731	#define DCF_POLLED 0x8000
732	u32 interleave;	732	u32 interleave;
733	u32 block_size;	733	u32 block_size;
734	u16 dev_ix;	734	u16 dev_ix;
735	u8 part_num;	735	u8 part_num;
736	u8 raid_grp_ix;	736	u8 raid_grp_ix;
737	char raid_grp_name[16];	737	char raid_grp_name[16];
738	struct esas2r_target *curr_targ;	738	struct esas2r_target *curr_targ;
739	u16 curr_virt_id;	739	u16 curr_virt_id;
740	u16 curr_phys_id;	740	u16 curr_phys_id;
741	u8 scan_gen;	741	u8 scan_gen;
742	u8 dev_addr_type;	742	u8 dev_addr_type;
743	u64 sas_addr;	743	u64 sas_addr;
744	};	744	};
745		745
746	struct esas2r_mem_desc {	746	struct esas2r_mem_desc {
747	struct list_head next_desc;	747	struct list_head next_desc;
748	void *virt_addr;	748	void *virt_addr;
749	u64 phys_addr;	749	u64 phys_addr;
750	void *pad;	750	void *pad;
751	void *esas2r_data;	751	void *esas2r_data;
752	u32 esas2r_param;	752	u32 esas2r_param;
753	u32 size;	753	u32 size;
754	};	754	};
755		755
756	enum fw_event_type {	756	enum fw_event_type {
757	fw_event_null,	757	fw_event_null,
758	fw_event_lun_change,	758	fw_event_lun_change,
759	fw_event_present,	759	fw_event_present,
760	fw_event_not_present,	760	fw_event_not_present,
761	fw_event_vda_ae	761	fw_event_vda_ae
762	};	762	};
763		763
764	struct esas2r_vda_ae {	764	struct esas2r_vda_ae {
765	u32 signature;	765	u32 signature;
766	#define ESAS2R_VDA_EVENT_SIG 0x4154544F	766	#define ESAS2R_VDA_EVENT_SIG 0x4154544F
767	u8 bus_number;	767	u8 bus_number;
768	u8 devfn;	768	u8 devfn;
769	u8 pad[2];	769	u8 pad[2];
770	union atto_vda_ae vda_ae;	770	union atto_vda_ae vda_ae;
771	};	771	};
772		772
773	struct esas2r_fw_event_work {	773	struct esas2r_fw_event_work {
774	struct list_head list;	774	struct list_head list;
775	struct delayed_work work;	775	struct delayed_work work;
776	struct esas2r_adapter *a;	776	struct esas2r_adapter *a;
777	enum fw_event_type type;	777	enum fw_event_type type;
778	u8 data[sizeof(struct esas2r_vda_ae)];	778	u8 data[sizeof(struct esas2r_vda_ae)];
779	};	779	};
780		780
781	enum state {	781	enum state {
782	FW_INVALID_ST,	782	FW_INVALID_ST,
783	FW_STATUS_ST,	783	FW_STATUS_ST,
784	FW_COMMAND_ST	784	FW_COMMAND_ST
785	};	785	};
786		786
787	struct esas2r_firmware {	787	struct esas2r_firmware {
788	enum state state;	788	enum state state;
789	struct esas2r_flash_img header;	789	struct esas2r_flash_img header;
790	u8 *data;	790	u8 *data;
791	u64 phys;	791	u64 phys;
792	int orig_len;	792	int orig_len;
793	void *header_buff;	793	void *header_buff;
794	u64 header_buff_phys;	794	u64 header_buff_phys;
795	};	795	};
796		796
797	struct esas2r_adapter {	797	struct esas2r_adapter {
798	struct esas2r_target targetdb[ESAS2R_MAX_TARGETS];	798	struct esas2r_target targetdb[ESAS2R_MAX_TARGETS];
799	struct esas2r_target *targetdb_end;	799	struct esas2r_target *targetdb_end;
800	unsigned char *regs;	800	unsigned char *regs;
801	unsigned char *data_window;	801	unsigned char *data_window;
802	long flags;	802	long flags;
803	#define AF_PORT_CHANGE 0	803	#define AF_PORT_CHANGE 0
804	#define AF_CHPRST_NEEDED 1	804	#define AF_CHPRST_NEEDED 1
805	#define AF_CHPRST_PENDING 2	805	#define AF_CHPRST_PENDING 2
806	#define AF_CHPRST_DETECTED 3	806	#define AF_CHPRST_DETECTED 3
807	#define AF_BUSRST_NEEDED 4	807	#define AF_BUSRST_NEEDED 4
808	#define AF_BUSRST_PENDING 5	808	#define AF_BUSRST_PENDING 5
809	#define AF_BUSRST_DETECTED 6	809	#define AF_BUSRST_DETECTED 6
810	#define AF_DISABLED 7	810	#define AF_DISABLED 7
811	#define AF_FLASH_LOCK 8	811	#define AF_FLASH_LOCK 8
812	#define AF_OS_RESET 9	812	#define AF_OS_RESET 9
813	#define AF_FLASHING 10	813	#define AF_FLASHING 10
814	#define AF_POWER_MGT 11	814	#define AF_POWER_MGT 11
815	#define AF_NVR_VALID 12	815	#define AF_NVR_VALID 12
816	#define AF_DEGRADED_MODE 13	816	#define AF_DEGRADED_MODE 13
817	#define AF_DISC_PENDING 14	817	#define AF_DISC_PENDING 14
818	#define AF_TASKLET_SCHEDULED 15	818	#define AF_TASKLET_SCHEDULED 15
819	#define AF_HEARTBEAT 16	819	#define AF_HEARTBEAT 16
820	#define AF_HEARTBEAT_ENB 17	820	#define AF_HEARTBEAT_ENB 17
821	#define AF_NOT_PRESENT 18	821	#define AF_NOT_PRESENT 18
822	#define AF_CHPRST_STARTED 19	822	#define AF_CHPRST_STARTED 19
823	#define AF_FIRST_INIT 20	823	#define AF_FIRST_INIT 20
824	#define AF_POWER_DOWN 21	824	#define AF_POWER_DOWN 21
825	#define AF_DISC_IN_PROG 22	825	#define AF_DISC_IN_PROG 22
826	#define AF_COMM_LIST_TOGGLE 23	826	#define AF_COMM_LIST_TOGGLE 23
827	#define AF_LEGACY_SGE_MODE 24	827	#define AF_LEGACY_SGE_MODE 24
828	#define AF_DISC_POLLED 25	828	#define AF_DISC_POLLED 25
829	long flags2;	829	long flags2;
830	#define AF2_SERIAL_FLASH 0	830	#define AF2_SERIAL_FLASH 0
831	#define AF2_DEV_SCAN 1	831	#define AF2_DEV_SCAN 1
832	#define AF2_DEV_CNT_OK 2	832	#define AF2_DEV_CNT_OK 2
833	#define AF2_COREDUMP_AVAIL 3	833	#define AF2_COREDUMP_AVAIL 3
834	#define AF2_COREDUMP_SAVED 4	834	#define AF2_COREDUMP_SAVED 4
835	#define AF2_VDA_POWER_DOWN 5	835	#define AF2_VDA_POWER_DOWN 5
836	#define AF2_THUNDERLINK 6	836	#define AF2_THUNDERLINK 6
837	#define AF2_THUNDERBOLT 7	837	#define AF2_THUNDERBOLT 7
838	#define AF2_INIT_DONE 8	838	#define AF2_INIT_DONE 8
839	#define AF2_INT_PENDING 9	839	#define AF2_INT_PENDING 9
840	#define AF2_TIMER_TICK 10	840	#define AF2_TIMER_TICK 10
841	#define AF2_IRQ_CLAIMED 11	841	#define AF2_IRQ_CLAIMED 11
842	#define AF2_MSI_ENABLED 12	842	#define AF2_MSI_ENABLED 12
843	atomic_t disable_cnt;	843	atomic_t disable_cnt;
844	atomic_t dis_ints_cnt;	844	atomic_t dis_ints_cnt;
845	u32 int_stat;	845	u32 int_stat;
846	u32 int_mask;	846	u32 int_mask;
847	u32 volatile *outbound_copy;	847	u32 volatile *outbound_copy;
848	struct list_head avail_request;	848	struct list_head avail_request;
849	spinlock_t request_lock;	849	spinlock_t request_lock;
850	spinlock_t sg_list_lock;	850	spinlock_t sg_list_lock;
851	spinlock_t queue_lock;	851	spinlock_t queue_lock;
852	spinlock_t mem_lock;	852	spinlock_t mem_lock;
853	struct list_head free_sg_list_head;	853	struct list_head free_sg_list_head;
854	struct esas2r_mem_desc *sg_list_mds;	854	struct esas2r_mem_desc *sg_list_mds;
855	struct list_head active_list;	855	struct list_head active_list;
856	struct list_head defer_list;	856	struct list_head defer_list;
857	struct esas2r_request **req_table;	857	struct esas2r_request **req_table;
858	union {	858	union {
859	u16 prev_dev_cnt;	859	u16 prev_dev_cnt;
860	u32 heartbeat_time;	860	u32 heartbeat_time;
861	#define ESAS2R_HEARTBEAT_TIME (3000)	861	#define ESAS2R_HEARTBEAT_TIME (3000)
862	};	862	};
863	u32 chip_uptime;	863	u32 chip_uptime;
864	#define ESAS2R_CHP_UPTIME_MAX (60000)	864	#define ESAS2R_CHP_UPTIME_MAX (60000)
865	#define ESAS2R_CHP_UPTIME_CNT (20000)	865	#define ESAS2R_CHP_UPTIME_CNT (20000)
866	u64 uncached_phys;	866	u64 uncached_phys;
867	u8 *uncached;	867	u8 *uncached;
868	struct esas2r_sas_nvram *nvram;	868	struct esas2r_sas_nvram *nvram;
869	struct esas2r_request general_req;	869	struct esas2r_request general_req;
870	u8 init_msg;	870	u8 init_msg;
871	#define ESAS2R_INIT_MSG_START 1	871	#define ESAS2R_INIT_MSG_START 1
872	#define ESAS2R_INIT_MSG_INIT 2	872	#define ESAS2R_INIT_MSG_INIT 2
873	#define ESAS2R_INIT_MSG_GET_INIT 3	873	#define ESAS2R_INIT_MSG_GET_INIT 3
874	#define ESAS2R_INIT_MSG_REINIT 4	874	#define ESAS2R_INIT_MSG_REINIT 4
875	u16 cmd_ref_no;	875	u16 cmd_ref_no;
876	u32 fw_version;	876	u32 fw_version;
877	u32 fw_build;	877	u32 fw_build;
878	u32 chip_init_time;	878	u32 chip_init_time;
879	#define ESAS2R_CHPRST_TIME (180000)	879	#define ESAS2R_CHPRST_TIME (180000)
880	#define ESAS2R_CHPRST_WAIT_TIME (2000)	880	#define ESAS2R_CHPRST_WAIT_TIME (2000)
881	u32 last_tick_time;	881	u32 last_tick_time;
882	u32 window_base;	882	u32 window_base;
883	RQBUILDSGL build_sgl;	883	RQBUILDSGL build_sgl;
884	struct esas2r_request *first_ae_req;	884	struct esas2r_request *first_ae_req;
885	u32 list_size;	885	u32 list_size;
886	u32 last_write;	886	u32 last_write;
887	u32 last_read;	887	u32 last_read;
888	u16 max_vdareq_size;	888	u16 max_vdareq_size;
889	u16 disc_wait_cnt;	889	u16 disc_wait_cnt;
890	struct esas2r_mem_desc inbound_list_md;	890	struct esas2r_mem_desc inbound_list_md;
891	struct esas2r_mem_desc outbound_list_md;	891	struct esas2r_mem_desc outbound_list_md;
892	struct esas2r_disc_context disc_ctx;	892	struct esas2r_disc_context disc_ctx;
893	u8 *disc_buffer;	893	u8 *disc_buffer;
894	u32 disc_start_time;	894	u32 disc_start_time;
895	u32 disc_wait_time;	895	u32 disc_wait_time;
896	u32 flash_ver;	896	u32 flash_ver;
897	char flash_rev[16];	897	char flash_rev[16];
898	char fw_rev[16];	898	char fw_rev[16];
899	char image_type[16];	899	char image_type[16];
900	struct esas2r_flash_context flash_context;	900	struct esas2r_flash_context flash_context;
901	u32 num_targets_backend;	901	u32 num_targets_backend;
902	u32 ioctl_tunnel;	902	u32 ioctl_tunnel;
903	struct tasklet_struct tasklet;	903	struct tasklet_struct tasklet;
904	struct pci_dev *pcid;	904	struct pci_dev *pcid;
905	struct Scsi_Host *host;	905	struct Scsi_Host *host;
906	unsigned int index;	906	unsigned int index;
907	char name[32];	907	char name[32];
908	struct timer_list timer;	908	struct timer_list timer;
909	struct esas2r_firmware firmware;	909	struct esas2r_firmware firmware;
910	wait_queue_head_t nvram_waiter;	910	wait_queue_head_t nvram_waiter;
911	int nvram_command_done;	911	int nvram_command_done;
912	wait_queue_head_t fm_api_waiter;	912	wait_queue_head_t fm_api_waiter;
913	int fm_api_command_done;	913	int fm_api_command_done;
914	wait_queue_head_t vda_waiter;	914	wait_queue_head_t vda_waiter;
915	int vda_command_done;	915	int vda_command_done;
916	u8 *vda_buffer;	916	u8 *vda_buffer;
917	u64 ppvda_buffer;	917	u64 ppvda_buffer;
918	#define VDA_BUFFER_HEADER_SZ (offsetof(struct atto_ioctl_vda, data))	918	#define VDA_BUFFER_HEADER_SZ (offsetof(struct atto_ioctl_vda, data))
919	#define VDA_MAX_BUFFER_SIZE (0x40000 + VDA_BUFFER_HEADER_SZ)	919	#define VDA_MAX_BUFFER_SIZE (0x40000 + VDA_BUFFER_HEADER_SZ)
920	wait_queue_head_t fs_api_waiter;	920	wait_queue_head_t fs_api_waiter;
921	int fs_api_command_done;	921	int fs_api_command_done;
922	u64 ppfs_api_buffer;	922	u64 ppfs_api_buffer;
923	u8 *fs_api_buffer;	923	u8 *fs_api_buffer;
924	u32 fs_api_buffer_size;	924	u32 fs_api_buffer_size;
925	wait_queue_head_t buffered_ioctl_waiter;	925	wait_queue_head_t buffered_ioctl_waiter;
926	int buffered_ioctl_done;	926	int buffered_ioctl_done;
927	int uncached_size;	927	int uncached_size;
928	struct workqueue_struct *fw_event_q;	928	struct workqueue_struct *fw_event_q;
929	struct list_head fw_event_list;	929	struct list_head fw_event_list;
930	spinlock_t fw_event_lock;	930	spinlock_t fw_event_lock;
931	u8 fw_events_off; /* if '1', then ignore events */	931	u8 fw_events_off; /* if '1', then ignore events */
932	char fw_event_q_name[ESAS2R_KOBJ_NAME_LEN];	932	char fw_event_q_name[ESAS2R_KOBJ_NAME_LEN];
933	/*	933	/*
934	* intr_mode stores the interrupt mode currently being used by this	934	* intr_mode stores the interrupt mode currently being used by this
935	* adapter. it is based on the interrupt_mode module parameter, but	935	* adapter. it is based on the interrupt_mode module parameter, but
936	* can be changed based on the ability (or not) to utilize the	936	* can be changed based on the ability (or not) to utilize the
937	* mode requested by the parameter.	937	* mode requested by the parameter.
938	*/	938	*/
939	int intr_mode;	939	int intr_mode;
940	#define INTR_MODE_LEGACY 0	940	#define INTR_MODE_LEGACY 0
941	#define INTR_MODE_MSI 1	941	#define INTR_MODE_MSI 1
942	#define INTR_MODE_MSIX 2	942	#define INTR_MODE_MSIX 2
943	struct esas2r_sg_context fm_api_sgc;	943	struct esas2r_sg_context fm_api_sgc;
944	u8 *save_offset;	944	u8 *save_offset;
945	struct list_head vrq_mds_head;	945	struct list_head vrq_mds_head;
946	struct esas2r_mem_desc *vrq_mds;	946	struct esas2r_mem_desc *vrq_mds;
947	int num_vrqs;	947	int num_vrqs;
948	struct semaphore fm_api_semaphore;	948	struct semaphore fm_api_semaphore;
949	struct semaphore fs_api_semaphore;	949	struct semaphore fs_api_semaphore;
950	struct semaphore nvram_semaphore;	950	struct semaphore nvram_semaphore;
951	struct atto_ioctl *local_atto_ioctl;	951	struct atto_ioctl *local_atto_ioctl;
952	u8 fw_coredump_buff[ESAS2R_FWCOREDUMP_SZ];	952	u8 fw_coredump_buff[ESAS2R_FWCOREDUMP_SZ];
953	unsigned int sysfs_fw_created:1;	953	unsigned int sysfs_fw_created:1;
954	unsigned int sysfs_fs_created:1;	954	unsigned int sysfs_fs_created:1;
955	unsigned int sysfs_vda_created:1;	955	unsigned int sysfs_vda_created:1;
956	unsigned int sysfs_hw_created:1;	956	unsigned int sysfs_hw_created:1;
957	unsigned int sysfs_live_nvram_created:1;	957	unsigned int sysfs_live_nvram_created:1;
958	unsigned int sysfs_default_nvram_created:1;	958	unsigned int sysfs_default_nvram_created:1;
959	};	959	};
960		960
961	/*	961	/*
962	* Function Declarations	962	* Function Declarations
963	* SCSI functions	963	* SCSI functions
964	*/	964	*/
965	int esas2r_release(struct Scsi_Host *);	965	int esas2r_release(struct Scsi_Host *);
966	const char esas2r_info(struct Scsi_Host );	966	const char esas2r_info(struct Scsi_Host );
967	int esas2r_write_params(struct esas2r_adapter a, struct esas2r_request rq,	967	int esas2r_write_params(struct esas2r_adapter a, struct esas2r_request rq,
968	struct esas2r_sas_nvram *data);	968	struct esas2r_sas_nvram *data);
969	int esas2r_ioctl_handler(void hostdata, int cmd, void __user arg);	969	int esas2r_ioctl_handler(void hostdata, int cmd, void __user arg);
970	int esas2r_ioctl(struct scsi_device dev, int cmd, void __user arg);	970	int esas2r_ioctl(struct scsi_device dev, int cmd, void __user arg);
971	u8 handle_hba_ioctl(struct esas2r_adapter *a,	971	u8 handle_hba_ioctl(struct esas2r_adapter *a,
972	struct atto_ioctl *ioctl_hba);	972	struct atto_ioctl *ioctl_hba);
973	int esas2r_queuecommand(struct Scsi_Host host, struct scsi_cmnd cmd);	973	int esas2r_queuecommand(struct Scsi_Host host, struct scsi_cmnd cmd);
974	int esas2r_show_info(struct seq_file m, struct Scsi_Host sh);	974	int esas2r_show_info(struct seq_file m, struct Scsi_Host sh);
975	int esas2r_slave_alloc(struct scsi_device *dev);	975	int esas2r_slave_alloc(struct scsi_device *dev);
976	int esas2r_slave_configure(struct scsi_device *dev);	976	int esas2r_slave_configure(struct scsi_device *dev);
977	void esas2r_slave_destroy(struct scsi_device *dev);	977	void esas2r_slave_destroy(struct scsi_device *dev);
978	int esas2r_change_queue_depth(struct scsi_device *dev, int depth, int reason);	978	int esas2r_change_queue_depth(struct scsi_device *dev, int depth, int reason);
979	int esas2r_change_queue_type(struct scsi_device *dev, int type);	979	int esas2r_change_queue_type(struct scsi_device *dev, int type);
980	long esas2r_proc_ioctl(struct file *fp, unsigned int cmd, unsigned long arg);	980	long esas2r_proc_ioctl(struct file *fp, unsigned int cmd, unsigned long arg);
981		981
982	/* SCSI error handler (eh) functions */	982	/* SCSI error handler (eh) functions */
983	int esas2r_eh_abort(struct scsi_cmnd *cmd);	983	int esas2r_eh_abort(struct scsi_cmnd *cmd);
984	int esas2r_device_reset(struct scsi_cmnd *cmd);	984	int esas2r_device_reset(struct scsi_cmnd *cmd);
985	int esas2r_host_reset(struct scsi_cmnd *cmd);	985	int esas2r_host_reset(struct scsi_cmnd *cmd);
986	int esas2r_bus_reset(struct scsi_cmnd *cmd);	986	int esas2r_bus_reset(struct scsi_cmnd *cmd);
987	int esas2r_target_reset(struct scsi_cmnd *cmd);	987	int esas2r_target_reset(struct scsi_cmnd *cmd);
988		988
989	/* Internal functions */	989	/* Internal functions */
990	int esas2r_init_adapter(struct Scsi_Host host, struct pci_dev pcid,	990	int esas2r_init_adapter(struct Scsi_Host host, struct pci_dev pcid,
991	int index);	991	int index);
992	int esas2r_cleanup(struct Scsi_Host *host);	992	int esas2r_cleanup(struct Scsi_Host *host);
993	int esas2r_read_fw(struct esas2r_adapter a, char buf, long off, int count);	993	int esas2r_read_fw(struct esas2r_adapter a, char buf, long off, int count);
994	int esas2r_write_fw(struct esas2r_adapter a, const char buf, long off,	994	int esas2r_write_fw(struct esas2r_adapter a, const char buf, long off,
995	int count);	995	int count);
996	int esas2r_read_vda(struct esas2r_adapter a, char buf, long off, int count);	996	int esas2r_read_vda(struct esas2r_adapter a, char buf, long off, int count);
997	int esas2r_write_vda(struct esas2r_adapter a, const char buf, long off,	997	int esas2r_write_vda(struct esas2r_adapter a, const char buf, long off,
998	int count);	998	int count);
999	int esas2r_read_fs(struct esas2r_adapter a, char buf, long off, int count);	999	int esas2r_read_fs(struct esas2r_adapter a, char buf, long off, int count);
1000	int esas2r_write_fs(struct esas2r_adapter a, const char buf, long off,	1000	int esas2r_write_fs(struct esas2r_adapter a, const char buf, long off,
1001	int count);	1001	int count);
1002	void esas2r_adapter_tasklet(unsigned long context);	1002	void esas2r_adapter_tasklet(unsigned long context);
1003	irqreturn_t esas2r_interrupt(int irq, void *dev_id);	1003	irqreturn_t esas2r_interrupt(int irq, void *dev_id);
1004	irqreturn_t esas2r_msi_interrupt(int irq, void *dev_id);	1004	irqreturn_t esas2r_msi_interrupt(int irq, void *dev_id);
1005	void esas2r_kickoff_timer(struct esas2r_adapter *a);	1005	void esas2r_kickoff_timer(struct esas2r_adapter *a);
1006	int esas2r_suspend(struct pci_dev *pcid, pm_message_t state);	1006	int esas2r_suspend(struct pci_dev *pcid, pm_message_t state);
1007	int esas2r_resume(struct pci_dev *pcid);	1007	int esas2r_resume(struct pci_dev *pcid);
1008	void esas2r_fw_event_off(struct esas2r_adapter *a);	1008	void esas2r_fw_event_off(struct esas2r_adapter *a);
1009	void esas2r_fw_event_on(struct esas2r_adapter *a);	1009	void esas2r_fw_event_on(struct esas2r_adapter *a);
1010	bool esas2r_nvram_write(struct esas2r_adapter a, struct esas2r_request rq,	1010	bool esas2r_nvram_write(struct esas2r_adapter a, struct esas2r_request rq,
1011	struct esas2r_sas_nvram *nvram);	1011	struct esas2r_sas_nvram *nvram);
1012	void esas2r_nvram_get_defaults(struct esas2r_adapter *a,	1012	void esas2r_nvram_get_defaults(struct esas2r_adapter *a,
1013	struct esas2r_sas_nvram *nvram);	1013	struct esas2r_sas_nvram *nvram);
1014	void esas2r_complete_request_cb(struct esas2r_adapter *a,	1014	void esas2r_complete_request_cb(struct esas2r_adapter *a,
1015	struct esas2r_request *rq);	1015	struct esas2r_request *rq);
1016	void esas2r_reset_detected(struct esas2r_adapter *a);	1016	void esas2r_reset_detected(struct esas2r_adapter *a);
1017	void esas2r_target_state_changed(struct esas2r_adapter *ha, u16 targ_id,	1017	void esas2r_target_state_changed(struct esas2r_adapter *ha, u16 targ_id,
1018	u8 state);	1018	u8 state);
1019	int esas2r_req_status_to_error(u8 req_stat);	1019	int esas2r_req_status_to_error(u8 req_stat);
1020	void esas2r_kill_adapter(int i);	1020	void esas2r_kill_adapter(int i);
1021	void esas2r_free_request(struct esas2r_adapter a, struct esas2r_request rq);	1021	void esas2r_free_request(struct esas2r_adapter a, struct esas2r_request rq);
1022	struct esas2r_request esas2r_alloc_request(struct esas2r_adapter a);	1022	struct esas2r_request esas2r_alloc_request(struct esas2r_adapter a);
1023	u32 esas2r_get_uncached_size(struct esas2r_adapter *a);	1023	u32 esas2r_get_uncached_size(struct esas2r_adapter *a);
1024	bool esas2r_init_adapter_struct(struct esas2r_adapter *a,	1024	bool esas2r_init_adapter_struct(struct esas2r_adapter *a,
1025	void **uncached_area);	1025	void **uncached_area);
1026	bool esas2r_check_adapter(struct esas2r_adapter *a);	1026	bool esas2r_check_adapter(struct esas2r_adapter *a);
1027	bool esas2r_init_adapter_hw(struct esas2r_adapter *a, bool init_poll);	1027	bool esas2r_init_adapter_hw(struct esas2r_adapter *a, bool init_poll);
1028	void esas2r_start_request(struct esas2r_adapter a, struct esas2r_request rq);	1028	void esas2r_start_request(struct esas2r_adapter a, struct esas2r_request rq);
1029	bool esas2r_send_task_mgmt(struct esas2r_adapter *a,	1029	bool esas2r_send_task_mgmt(struct esas2r_adapter *a,
1030	struct esas2r_request *rqaux, u8 task_mgt_func);	1030	struct esas2r_request *rqaux, u8 task_mgt_func);
1031	void esas2r_do_tasklet_tasks(struct esas2r_adapter *a);	1031	void esas2r_do_tasklet_tasks(struct esas2r_adapter *a);
1032	void esas2r_adapter_interrupt(struct esas2r_adapter *a);	1032	void esas2r_adapter_interrupt(struct esas2r_adapter *a);
1033	void esas2r_do_deferred_processes(struct esas2r_adapter *a);	1033	void esas2r_do_deferred_processes(struct esas2r_adapter *a);
1034	void esas2r_reset_bus(struct esas2r_adapter *a);	1034	void esas2r_reset_bus(struct esas2r_adapter *a);
1035	void esas2r_reset_adapter(struct esas2r_adapter *a);	1035	void esas2r_reset_adapter(struct esas2r_adapter *a);
1036	void esas2r_timer_tick(struct esas2r_adapter *a);	1036	void esas2r_timer_tick(struct esas2r_adapter *a);
1037	const char esas2r_get_model_name(struct esas2r_adapter a);	1037	const char esas2r_get_model_name(struct esas2r_adapter a);
1038	const char esas2r_get_model_name_short(struct esas2r_adapter a);	1038	const char esas2r_get_model_name_short(struct esas2r_adapter a);
1039	u32 esas2r_stall_execution(struct esas2r_adapter *a, u32 start_time,	1039	u32 esas2r_stall_execution(struct esas2r_adapter *a, u32 start_time,
1040	u32 *delay);	1040	u32 *delay);
1041	void esas2r_build_flash_req(struct esas2r_adapter *a,	1041	void esas2r_build_flash_req(struct esas2r_adapter *a,
1042	struct esas2r_request *rq,	1042	struct esas2r_request *rq,
1043	u8 sub_func,	1043	u8 sub_func,
1044	u8 cksum,	1044	u8 cksum,
1045	u32 addr,	1045	u32 addr,
1046	u32 length);	1046	u32 length);
1047	void esas2r_build_mgt_req(struct esas2r_adapter *a,	1047	void esas2r_build_mgt_req(struct esas2r_adapter *a,
1048	struct esas2r_request *rq,	1048	struct esas2r_request *rq,
1049	u8 sub_func,	1049	u8 sub_func,
1050	u8 scan_gen,	1050	u8 scan_gen,
1051	u16 dev_index,	1051	u16 dev_index,
1052	u32 length,	1052	u32 length,
1053	void *data);	1053	void *data);
1054	void esas2r_build_ae_req(struct esas2r_adapter a, struct esas2r_request rq);	1054	void esas2r_build_ae_req(struct esas2r_adapter a, struct esas2r_request rq);
1055	void esas2r_build_cli_req(struct esas2r_adapter *a,	1055	void esas2r_build_cli_req(struct esas2r_adapter *a,
1056	struct esas2r_request *rq,	1056	struct esas2r_request *rq,
1057	u32 length,	1057	u32 length,
1058	u32 cmd_rsp_len);	1058	u32 cmd_rsp_len);
1059	void esas2r_build_ioctl_req(struct esas2r_adapter *a,	1059	void esas2r_build_ioctl_req(struct esas2r_adapter *a,
1060	struct esas2r_request *rq,	1060	struct esas2r_request *rq,
1061	u32 length,	1061	u32 length,
1062	u8 sub_func);	1062	u8 sub_func);
1063	void esas2r_build_cfg_req(struct esas2r_adapter *a,	1063	void esas2r_build_cfg_req(struct esas2r_adapter *a,
1064	struct esas2r_request *rq,	1064	struct esas2r_request *rq,
1065	u8 sub_func,	1065	u8 sub_func,
1066	u32 length,	1066	u32 length,
1067	void *data);	1067	void *data);
1068	void esas2r_power_down(struct esas2r_adapter *a);	1068	void esas2r_power_down(struct esas2r_adapter *a);
1069	bool esas2r_power_up(struct esas2r_adapter *a, bool init_poll);	1069	bool esas2r_power_up(struct esas2r_adapter *a, bool init_poll);
1070	void esas2r_wait_request(struct esas2r_adapter a, struct esas2r_request rq);	1070	void esas2r_wait_request(struct esas2r_adapter a, struct esas2r_request rq);
1071	u32 esas2r_map_data_window(struct esas2r_adapter *a, u32 addr_lo);	1071	u32 esas2r_map_data_window(struct esas2r_adapter *a, u32 addr_lo);
1072	bool esas2r_process_fs_ioctl(struct esas2r_adapter *a,	1072	bool esas2r_process_fs_ioctl(struct esas2r_adapter *a,
1073	struct esas2r_ioctl_fs *fs,	1073	struct esas2r_ioctl_fs *fs,
1074	struct esas2r_request *rq,	1074	struct esas2r_request *rq,
1075	struct esas2r_sg_context *sgc);	1075	struct esas2r_sg_context *sgc);
1076	bool esas2r_read_flash_block(struct esas2r_adapter a, void to, u32 from,	1076	bool esas2r_read_flash_block(struct esas2r_adapter a, void to, u32 from,
1077	u32 size);	1077	u32 size);
1078	bool esas2r_read_mem_block(struct esas2r_adapter a, void to, u32 from,	1078	bool esas2r_read_mem_block(struct esas2r_adapter a, void to, u32 from,
1079	u32 size);	1079	u32 size);
1080	bool esas2r_fm_api(struct esas2r_adapter a, struct esas2r_flash_img fi,	1080	bool esas2r_fm_api(struct esas2r_adapter a, struct esas2r_flash_img fi,
1081	struct esas2r_request rq, struct esas2r_sg_context sgc);	1081	struct esas2r_request rq, struct esas2r_sg_context sgc);
1082	void esas2r_force_interrupt(struct esas2r_adapter *a);	1082	void esas2r_force_interrupt(struct esas2r_adapter *a);
1083	void esas2r_local_start_request(struct esas2r_adapter *a,	1083	void esas2r_local_start_request(struct esas2r_adapter *a,
1084	struct esas2r_request *rq);	1084	struct esas2r_request *rq);
1085	void esas2r_process_adapter_reset(struct esas2r_adapter *a);	1085	void esas2r_process_adapter_reset(struct esas2r_adapter *a);
1086	void esas2r_complete_request(struct esas2r_adapter *a,	1086	void esas2r_complete_request(struct esas2r_adapter *a,
1087	struct esas2r_request *rq);	1087	struct esas2r_request *rq);
1088	void esas2r_dummy_complete(struct esas2r_adapter *a,	1088	void esas2r_dummy_complete(struct esas2r_adapter *a,
1089	struct esas2r_request *rq);	1089	struct esas2r_request *rq);
1090	void esas2r_ae_complete(struct esas2r_adapter a, struct esas2r_request rq);	1090	void esas2r_ae_complete(struct esas2r_adapter a, struct esas2r_request rq);
1091	void esas2r_start_vda_request(struct esas2r_adapter *a,	1091	void esas2r_start_vda_request(struct esas2r_adapter *a,
1092	struct esas2r_request *rq);	1092	struct esas2r_request *rq);
1093	bool esas2r_read_flash_rev(struct esas2r_adapter *a);	1093	bool esas2r_read_flash_rev(struct esas2r_adapter *a);
1094	bool esas2r_read_image_type(struct esas2r_adapter *a);	1094	bool esas2r_read_image_type(struct esas2r_adapter *a);
1095	bool esas2r_nvram_read_direct(struct esas2r_adapter *a);	1095	bool esas2r_nvram_read_direct(struct esas2r_adapter *a);
1096	bool esas2r_nvram_validate(struct esas2r_adapter *a);	1096	bool esas2r_nvram_validate(struct esas2r_adapter *a);
1097	void esas2r_nvram_set_defaults(struct esas2r_adapter *a);	1097	void esas2r_nvram_set_defaults(struct esas2r_adapter *a);
1098	bool esas2r_print_flash_rev(struct esas2r_adapter *a);	1098	bool esas2r_print_flash_rev(struct esas2r_adapter *a);
1099	void esas2r_send_reset_ae(struct esas2r_adapter *a, bool pwr_mgt);	1099	void esas2r_send_reset_ae(struct esas2r_adapter *a, bool pwr_mgt);
1100	bool esas2r_init_msgs(struct esas2r_adapter *a);	1100	bool esas2r_init_msgs(struct esas2r_adapter *a);
1101	bool esas2r_is_adapter_present(struct esas2r_adapter *a);	1101	bool esas2r_is_adapter_present(struct esas2r_adapter *a);
1102	void esas2r_nuxi_mgt_data(u8 function, void *data);	1102	void esas2r_nuxi_mgt_data(u8 function, void *data);
1103	void esas2r_nuxi_cfg_data(u8 function, void *data);	1103	void esas2r_nuxi_cfg_data(u8 function, void *data);
1104	void esas2r_nuxi_ae_data(union atto_vda_ae *ae);	1104	void esas2r_nuxi_ae_data(union atto_vda_ae *ae);
1105	void esas2r_reset_chip(struct esas2r_adapter *a);	1105	void esas2r_reset_chip(struct esas2r_adapter *a);
1106	void esas2r_log_request_failure(struct esas2r_adapter *a,	1106	void esas2r_log_request_failure(struct esas2r_adapter *a,
1107	struct esas2r_request *rq);	1107	struct esas2r_request *rq);
1108	void esas2r_polled_interrupt(struct esas2r_adapter *a);	1108	void esas2r_polled_interrupt(struct esas2r_adapter *a);
1109	bool esas2r_ioreq_aborted(struct esas2r_adapter a, struct esas2r_request rq,	1109	bool esas2r_ioreq_aborted(struct esas2r_adapter a, struct esas2r_request rq,
1110	u8 status);	1110	u8 status);
1111	bool esas2r_build_sg_list_sge(struct esas2r_adapter *a,	1111	bool esas2r_build_sg_list_sge(struct esas2r_adapter *a,
1112	struct esas2r_sg_context *sgc);	1112	struct esas2r_sg_context *sgc);
1113	bool esas2r_build_sg_list_prd(struct esas2r_adapter *a,	1113	bool esas2r_build_sg_list_prd(struct esas2r_adapter *a,
1114	struct esas2r_sg_context *sgc);	1114	struct esas2r_sg_context *sgc);
1115	void esas2r_targ_db_initialize(struct esas2r_adapter *a);	1115	void esas2r_targ_db_initialize(struct esas2r_adapter *a);
1116	void esas2r_targ_db_remove_all(struct esas2r_adapter *a, bool notify);	1116	void esas2r_targ_db_remove_all(struct esas2r_adapter *a, bool notify);
1117	void esas2r_targ_db_report_changes(struct esas2r_adapter *a);	1117	void esas2r_targ_db_report_changes(struct esas2r_adapter *a);
1118	struct esas2r_target esas2r_targ_db_add_raid(struct esas2r_adapter a,	1118	struct esas2r_target esas2r_targ_db_add_raid(struct esas2r_adapter a,
1119	struct esas2r_disc_context *dc);	1119	struct esas2r_disc_context *dc);
1120	struct esas2r_target esas2r_targ_db_add_pthru(struct esas2r_adapter a,	1120	struct esas2r_target esas2r_targ_db_add_pthru(struct esas2r_adapter a,
1121	struct esas2r_disc_context *dc,	1121	struct esas2r_disc_context *dc,
1122	u8 *ident,	1122	u8 *ident,
1123	u8 ident_len);	1123	u8 ident_len);
1124	void esas2r_targ_db_remove(struct esas2r_adapter a, struct esas2r_target t);	1124	void esas2r_targ_db_remove(struct esas2r_adapter a, struct esas2r_target t);
1125	struct esas2r_target esas2r_targ_db_find_by_sas_addr(struct esas2r_adapter a,	1125	struct esas2r_target esas2r_targ_db_find_by_sas_addr(struct esas2r_adapter a,
1126	u64 *sas_addr);	1126	u64 *sas_addr);
1127	struct esas2r_target esas2r_targ_db_find_by_ident(struct esas2r_adapter a,	1127	struct esas2r_target esas2r_targ_db_find_by_ident(struct esas2r_adapter a,
1128	void *identifier,	1128	void *identifier,
1129	u8 ident_len);	1129	u8 ident_len);
1130	u16 esas2r_targ_db_find_next_present(struct esas2r_adapter *a, u16 target_id);	1130	u16 esas2r_targ_db_find_next_present(struct esas2r_adapter *a, u16 target_id);
1131	struct esas2r_target esas2r_targ_db_find_by_virt_id(struct esas2r_adapter a,	1131	struct esas2r_target esas2r_targ_db_find_by_virt_id(struct esas2r_adapter a,
1132	u16 virt_id);	1132	u16 virt_id);
1133	u16 esas2r_targ_db_get_tgt_cnt(struct esas2r_adapter *a);	1133	u16 esas2r_targ_db_get_tgt_cnt(struct esas2r_adapter *a);
1134	void esas2r_disc_initialize(struct esas2r_adapter *a);	1134	void esas2r_disc_initialize(struct esas2r_adapter *a);
1135	void esas2r_disc_start_waiting(struct esas2r_adapter *a);	1135	void esas2r_disc_start_waiting(struct esas2r_adapter *a);
1136	void esas2r_disc_check_for_work(struct esas2r_adapter *a);	1136	void esas2r_disc_check_for_work(struct esas2r_adapter *a);
1137	void esas2r_disc_check_complete(struct esas2r_adapter *a);	1137	void esas2r_disc_check_complete(struct esas2r_adapter *a);
1138	void esas2r_disc_queue_event(struct esas2r_adapter *a, u8 disc_evt);	1138	void esas2r_disc_queue_event(struct esas2r_adapter *a, u8 disc_evt);
1139	bool esas2r_disc_start_port(struct esas2r_adapter *a);	1139	bool esas2r_disc_start_port(struct esas2r_adapter *a);
1140	void esas2r_disc_local_start_request(struct esas2r_adapter *a,	1140	void esas2r_disc_local_start_request(struct esas2r_adapter *a,
1141	struct esas2r_request *rq);	1141	struct esas2r_request *rq);
1142	bool esas2r_set_degraded_mode(struct esas2r_adapter a, char error_str);	1142	bool esas2r_set_degraded_mode(struct esas2r_adapter a, char error_str);
1143	bool esas2r_process_vda_ioctl(struct esas2r_adapter *a,	1143	bool esas2r_process_vda_ioctl(struct esas2r_adapter *a,
1144	struct atto_ioctl_vda *vi,	1144	struct atto_ioctl_vda *vi,
1145	struct esas2r_request *rq,	1145	struct esas2r_request *rq,
1146	struct esas2r_sg_context *sgc);	1146	struct esas2r_sg_context *sgc);
1147	void esas2r_queue_fw_event(struct esas2r_adapter *a,	1147	void esas2r_queue_fw_event(struct esas2r_adapter *a,
1148	enum fw_event_type type,	1148	enum fw_event_type type,
1149	void *data,	1149	void *data,
1150	int data_sz);	1150	int data_sz);
1151		1151
1152	/* Inline functions */	1152	/* Inline functions */
1153		1153
1154	/* Allocate a chip scatter/gather list entry */	1154	/* Allocate a chip scatter/gather list entry */
1155	static inline struct esas2r_mem_desc esas2r_alloc_sgl(struct esas2r_adapter a)	1155	static inline struct esas2r_mem_desc esas2r_alloc_sgl(struct esas2r_adapter a)
1156	{	1156	{
1157	unsigned long flags;	1157	unsigned long flags;
1158	struct list_head *sgl;	1158	struct list_head *sgl;
1159	struct esas2r_mem_desc *result = NULL;	1159	struct esas2r_mem_desc *result = NULL;
1160		1160
1161	spin_lock_irqsave(&a->sg_list_lock, flags);	1161	spin_lock_irqsave(&a->sg_list_lock, flags);
1162	if (likely(!list_empty(&a->free_sg_list_head))) {	1162	if (likely(!list_empty(&a->free_sg_list_head))) {
1163	sgl = a->free_sg_list_head.next;	1163	sgl = a->free_sg_list_head.next;
1164	result = list_entry(sgl, struct esas2r_mem_desc, next_desc);	1164	result = list_entry(sgl, struct esas2r_mem_desc, next_desc);
1165	list_del_init(sgl);	1165	list_del_init(sgl);
1166	}	1166	}
1167	spin_unlock_irqrestore(&a->sg_list_lock, flags);	1167	spin_unlock_irqrestore(&a->sg_list_lock, flags);
1168		1168
1169	return result;	1169	return result;
1170	}	1170	}
1171		1171
1172	/* Initialize a scatter/gather context */	1172	/* Initialize a scatter/gather context */
1173	static inline void esas2r_sgc_init(struct esas2r_sg_context *sgc,	1173	static inline void esas2r_sgc_init(struct esas2r_sg_context *sgc,
1174	struct esas2r_adapter *a,	1174	struct esas2r_adapter *a,
1175	struct esas2r_request *rq,	1175	struct esas2r_request *rq,
1176	struct atto_vda_sge *first)	1176	struct atto_vda_sge *first)
1177	{	1177	{
1178	sgc->adapter = a;	1178	sgc->adapter = a;
1179	sgc->first_req = rq;	1179	sgc->first_req = rq;
1180		1180
1181	/*	1181	/*
1182	* set the limit pointer such that an SGE pointer above this value	1182	* set the limit pointer such that an SGE pointer above this value
1183	* would be the first one to overflow the SGL.	1183	* would be the first one to overflow the SGL.
1184	*/	1184	*/
1185	sgc->sge.a64.limit = (struct atto_vda_sge )((u8 )rq->vrq	1185	sgc->sge.a64.limit = (struct atto_vda_sge )((u8 )rq->vrq
1186	+ (sizeof(union	1186	+ (sizeof(union
1187	atto_vda_req) /	1187	atto_vda_req) /
1188	8)	1188	8)
1189	- sizeof(struct	1189	- sizeof(struct
1190	atto_vda_sge));	1190	atto_vda_sge));
1191	if (first) {	1191	if (first) {
1192	sgc->sge.a64.last =	1192	sgc->sge.a64.last =
1193	sgc->sge.a64.curr = first;	1193	sgc->sge.a64.curr = first;
1194	rq->vrq->scsi.sg_list_offset = (u8)	1194	rq->vrq->scsi.sg_list_offset = (u8)
1195	((u8 *)first -	1195	((u8 *)first -
1196	(u8 *)rq->vrq);	1196	(u8 *)rq->vrq);
1197	} else {	1197	} else {
1198	sgc->sge.a64.last =	1198	sgc->sge.a64.last =
1199	sgc->sge.a64.curr = &rq->vrq->scsi.u.sge[0];	1199	sgc->sge.a64.curr = &rq->vrq->scsi.u.sge[0];
1200	rq->vrq->scsi.sg_list_offset =	1200	rq->vrq->scsi.sg_list_offset =
1201	(u8)offsetof(struct atto_vda_scsi_req, u.sge);	1201	(u8)offsetof(struct atto_vda_scsi_req, u.sge);
1202	}	1202	}
1203	sgc->sge.a64.chain = NULL;	1203	sgc->sge.a64.chain = NULL;
1204	}	1204	}
1205		1205
1206	static inline void esas2r_rq_init_request(struct esas2r_request *rq,	1206	static inline void esas2r_rq_init_request(struct esas2r_request *rq,
1207	struct esas2r_adapter *a)	1207	struct esas2r_adapter *a)
1208	{	1208	{
1209	union atto_vda_req *vrq = rq->vrq;	1209	union atto_vda_req *vrq = rq->vrq;
1210	u32 handle;
1211		1210
1212	INIT_LIST_HEAD(&rq->sg_table_head);	1211	INIT_LIST_HEAD(&rq->sg_table_head);
1213	rq->data_buf = (void *)(vrq + 1);	1212	rq->data_buf = (void *)(vrq + 1);
1214	rq->interrupt_cb = NULL;	1213	rq->interrupt_cb = NULL;
1215	rq->comp_cb = esas2r_complete_request_cb;	1214	rq->comp_cb = esas2r_complete_request_cb;
1216	rq->flags = 0;	1215	rq->flags = 0;
1217	rq->timeout = 0;	1216	rq->timeout = 0;
1218	rq->req_stat = RS_PENDING;	1217	rq->req_stat = RS_PENDING;
1219	rq->req_type = RT_INI_REQ;	1218	rq->req_type = RT_INI_REQ;
1220		1219
1221	/* clear the outbound response */	1220	/* clear the outbound response */
1222	rq->func_rsp.dwords[0] = 0;	1221	rq->func_rsp.dwords[0] = 0;
1223	rq->func_rsp.dwords[1] = 0;	1222	rq->func_rsp.dwords[1] = 0;
1224		1223
1225	/*	1224	/*
1226	* clear the size of the VDA request. esas2r_build_sg_list() will	1225	* clear the size of the VDA request. esas2r_build_sg_list() will
1227	* only allow the size of the request to grow. there are some	1226	* only allow the size of the request to grow. there are some
1228	* management requests that go through there twice and the second	1227	* management requests that go through there twice and the second
1229	* time through sets a smaller request size. if this is not modified	1228	* time through sets a smaller request size. if this is not modified
1230	* at all we'll set it to the size of the entire VDA request.	1229	* at all we'll set it to the size of the entire VDA request.
1231	*/	1230	*/
1232	rq->vda_req_sz = RQ_SIZE_DEFAULT;	1231	rq->vda_req_sz = RQ_SIZE_DEFAULT;
1233		1232
1234	/* req_table entry should be NULL at this point - if not, halt */	1233	/* req_table entry should be NULL at this point - if not, halt */
1235		1234
1236	if (a->req_table[LOWORD(vrq->scsi.handle)])	1235	if (a->req_table[LOWORD(vrq->scsi.handle)])
1237	esas2r_bugon();	1236	esas2r_bugon();
1238		1237
1239	/* fill in the table for this handle so we can get back to the	1238	/* fill in the table for this handle so we can get back to the
1240	* request.	1239	* request.
1241	*/	1240	*/
1242	a->req_table[LOWORD(vrq->scsi.handle)] = rq;	1241	a->req_table[LOWORD(vrq->scsi.handle)] = rq;
1243		1242
1244	/*	1243	/*
1245	* add a reference number to the handle to make it unique (until it	1244	* add a reference number to the handle to make it unique (until it
1246	* wraps of course) while preserving the upper word	1245	* wraps of course) while preserving the least significant word
1247	*/	1246	*/
1248		1247	vrq->scsi.handle = (a->cmd_ref_no++ << 16) \| (u16)vrq->scsi.handle;
1249	handle = be32_to_cpu(vrq->scsi.handle) & 0xFFFF0000;
1250	vrq->scsi.handle = cpu_to_be32(handle + a->cmd_ref_no++);
1251		1248
1252	/*	1249	/*
1253	* the following formats a SCSI request. the caller can override as	1250	* the following formats a SCSI request. the caller can override as
1254	* necessary. clear_vda_request can be called to clear the VDA	1251	* necessary. clear_vda_request can be called to clear the VDA
1255	* request for another type of request.	1252	* request for another type of request.
1256	*/	1253	*/
1257	vrq->scsi.function = VDA_FUNC_SCSI;	1254	vrq->scsi.function = VDA_FUNC_SCSI;
1258	vrq->scsi.sense_len = SENSE_DATA_SZ;	1255	vrq->scsi.sense_len = SENSE_DATA_SZ;
1259		1256
1260	/* clear out sg_list_offset and chain_offset */	1257	/* clear out sg_list_offset and chain_offset */
1261	vrq->scsi.sg_list_offset = 0;	1258	vrq->scsi.sg_list_offset = 0;
1262	vrq->scsi.chain_offset = 0;	1259	vrq->scsi.chain_offset = 0;
1263	vrq->scsi.flags = 0;	1260	vrq->scsi.flags = 0;
1264	vrq->scsi.reserved = 0;	1261	vrq->scsi.reserved = 0;
1265		1262
1266	/* set the sense buffer to be the data payload buffer */	1263	/* set the sense buffer to be the data payload buffer */
1267	vrq->scsi.ppsense_buf	1264	vrq->scsi.ppsense_buf
1268	= cpu_to_le64(rq->vrq_md->phys_addr +	1265	= cpu_to_le64(rq->vrq_md->phys_addr +
1269	sizeof(union atto_vda_req));	1266	sizeof(union atto_vda_req));
1270	}	1267	}
1271		1268
1272	static inline void esas2r_rq_free_sg_lists(struct esas2r_request *rq,	1269	static inline void esas2r_rq_free_sg_lists(struct esas2r_request *rq,
1273	struct esas2r_adapter *a)	1270	struct esas2r_adapter *a)
1274	{	1271	{
1275	unsigned long flags;	1272	unsigned long flags;
1276		1273
1277	if (list_empty(&rq->sg_table_head))	1274	if (list_empty(&rq->sg_table_head))
1278	return;	1275	return;
1279		1276
1280	spin_lock_irqsave(&a->sg_list_lock, flags);	1277	spin_lock_irqsave(&a->sg_list_lock, flags);
1281	list_splice_tail_init(&rq->sg_table_head, &a->free_sg_list_head);	1278	list_splice_tail_init(&rq->sg_table_head, &a->free_sg_list_head);
1282	spin_unlock_irqrestore(&a->sg_list_lock, flags);	1279	spin_unlock_irqrestore(&a->sg_list_lock, flags);
1283	}	1280	}
1284		1281
1285	static inline void esas2r_rq_destroy_request(struct esas2r_request *rq,	1282	static inline void esas2r_rq_destroy_request(struct esas2r_request *rq,
1286	struct esas2r_adapter *a)	1283	struct esas2r_adapter *a)
1287		1284
1288	{	1285	{
1289	esas2r_rq_free_sg_lists(rq, a);	1286	esas2r_rq_free_sg_lists(rq, a);
1290	a->req_table[LOWORD(rq->vrq->scsi.handle)] = NULL;	1287	a->req_table[LOWORD(rq->vrq->scsi.handle)] = NULL;
1291	rq->data_buf = NULL;	1288	rq->data_buf = NULL;
1292	}	1289	}
1293		1290
1294	static inline bool esas2r_is_tasklet_pending(struct esas2r_adapter *a)	1291	static inline bool esas2r_is_tasklet_pending(struct esas2r_adapter *a)
1295	{	1292	{
1296		1293
1297	return test_bit(AF_BUSRST_NEEDED, &a->flags) \|\|	1294	return test_bit(AF_BUSRST_NEEDED, &a->flags) \|\|
1298	test_bit(AF_BUSRST_DETECTED, &a->flags) \|\|	1295	test_bit(AF_BUSRST_DETECTED, &a->flags) \|\|
1299	test_bit(AF_CHPRST_NEEDED, &a->flags) \|\|	1296	test_bit(AF_CHPRST_NEEDED, &a->flags) \|\|
1300	test_bit(AF_CHPRST_DETECTED, &a->flags) \|\|	1297	test_bit(AF_CHPRST_DETECTED, &a->flags) \|\|
1301	test_bit(AF_PORT_CHANGE, &a->flags);	1298	test_bit(AF_PORT_CHANGE, &a->flags);
1302		1299
1303	}	1300	}
1304		1301
1305	/*	1302	/*
1306	* Build the scatter/gather list for an I/O request according to the	1303	* Build the scatter/gather list for an I/O request according to the
1307	* specifications placed in the esas2r_sg_context. The caller must initialize	1304	* specifications placed in the esas2r_sg_context. The caller must initialize
1308	* struct esas2r_sg_context prior to the initial call by calling	1305	* struct esas2r_sg_context prior to the initial call by calling
1309	* esas2r_sgc_init()	1306	* esas2r_sgc_init()
1310	*/	1307	*/
1311	static inline bool esas2r_build_sg_list(struct esas2r_adapter *a,	1308	static inline bool esas2r_build_sg_list(struct esas2r_adapter *a,
1312	struct esas2r_request *rq,	1309	struct esas2r_request *rq,
1313	struct esas2r_sg_context *sgc)	1310	struct esas2r_sg_context *sgc)
1314	{	1311	{
1315	if (unlikely(le32_to_cpu(rq->vrq->scsi.length) == 0))	1312	if (unlikely(le32_to_cpu(rq->vrq->scsi.length) == 0))
1316	return true;	1313	return true;
1317		1314
1318	return (*a->build_sgl)(a, sgc);	1315	return (*a->build_sgl)(a, sgc);
1319	}	1316	}
1320		1317
1321	static inline void esas2r_disable_chip_interrupts(struct esas2r_adapter *a)	1318	static inline void esas2r_disable_chip_interrupts(struct esas2r_adapter *a)
1322	{	1319	{
1323	if (atomic_inc_return(&a->dis_ints_cnt) == 1)	1320	if (atomic_inc_return(&a->dis_ints_cnt) == 1)
1324	esas2r_write_register_dword(a, MU_INT_MASK_OUT,	1321	esas2r_write_register_dword(a, MU_INT_MASK_OUT,
1325	ESAS2R_INT_DIS_MASK);	1322	ESAS2R_INT_DIS_MASK);
1326	}	1323	}
1327		1324
1328	static inline void esas2r_enable_chip_interrupts(struct esas2r_adapter *a)	1325	static inline void esas2r_enable_chip_interrupts(struct esas2r_adapter *a)
1329	{	1326	{
1330	if (atomic_dec_return(&a->dis_ints_cnt) == 0)	1327	if (atomic_dec_return(&a->dis_ints_cnt) == 0)
1331	esas2r_write_register_dword(a, MU_INT_MASK_OUT,	1328	esas2r_write_register_dword(a, MU_INT_MASK_OUT,
1332	ESAS2R_INT_ENB_MASK);	1329	ESAS2R_INT_ENB_MASK);
1333	}	1330	}
1334		1331
1335	/* Schedule a TASKLET to perform non-interrupt tasks that may require delays	1332	/* Schedule a TASKLET to perform non-interrupt tasks that may require delays
1336	* or long completion times.	1333	* or long completion times.
1337	*/	1334	*/
1338	static inline void esas2r_schedule_tasklet(struct esas2r_adapter *a)	1335	static inline void esas2r_schedule_tasklet(struct esas2r_adapter *a)
1339	{	1336	{
1340	/* make sure we don't schedule twice */	1337	/* make sure we don't schedule twice */
1341	if (!test_and_set_bit(AF_TASKLET_SCHEDULED, &a->flags))	1338	if (!test_and_set_bit(AF_TASKLET_SCHEDULED, &a->flags))
1342	tasklet_hi_schedule(&a->tasklet);	1339	tasklet_hi_schedule(&a->tasklet);
1343	}	1340	}
1344		1341
1345	static inline void esas2r_enable_heartbeat(struct esas2r_adapter *a)	1342	static inline void esas2r_enable_heartbeat(struct esas2r_adapter *a)
1346	{	1343	{
1347	if (!test_bit(AF_DEGRADED_MODE, &a->flags) &&	1344	if (!test_bit(AF_DEGRADED_MODE, &a->flags) &&
1348	!test_bit(AF_CHPRST_PENDING, &a->flags) &&	1345	!test_bit(AF_CHPRST_PENDING, &a->flags) &&
1349	(a->nvram->options2 & SASNVR2_HEARTBEAT))	1346	(a->nvram->options2 & SASNVR2_HEARTBEAT))
1350	set_bit(AF_HEARTBEAT_ENB, &a->flags);	1347	set_bit(AF_HEARTBEAT_ENB, &a->flags);
1351	else	1348	else
1352	clear_bit(AF_HEARTBEAT_ENB, &a->flags);	1349	clear_bit(AF_HEARTBEAT_ENB, &a->flags);
1353	}	1350	}
1354		1351
1355	static inline void esas2r_disable_heartbeat(struct esas2r_adapter *a)	1352	static inline void esas2r_disable_heartbeat(struct esas2r_adapter *a)
1356	{	1353	{
1357	clear_bit(AF_HEARTBEAT_ENB, &a->flags);	1354	clear_bit(AF_HEARTBEAT_ENB, &a->flags);
1358	clear_bit(AF_HEARTBEAT, &a->flags);	1355	clear_bit(AF_HEARTBEAT, &a->flags);
1359	}	1356	}
1360		1357
1361	/* Set the initial state for resetting the adapter on the next pass through	1358	/* Set the initial state for resetting the adapter on the next pass through
1362	* esas2r_do_deferred.	1359	* esas2r_do_deferred.
1363	*/	1360	*/
1364	static inline void esas2r_local_reset_adapter(struct esas2r_adapter *a)	1361	static inline void esas2r_local_reset_adapter(struct esas2r_adapter *a)
1365	{	1362	{
1366	esas2r_disable_heartbeat(a);	1363	esas2r_disable_heartbeat(a);
1367		1364
1368	set_bit(AF_CHPRST_NEEDED, &a->flags);	1365	set_bit(AF_CHPRST_NEEDED, &a->flags);
1369	set_bit(AF_CHPRST_PENDING, &a->flags);	1366	set_bit(AF_CHPRST_PENDING, &a->flags);
1370	set_bit(AF_DISC_PENDING, &a->flags);	1367	set_bit(AF_DISC_PENDING, &a->flags);
1371	}	1368	}
1372		1369
1373	/* See if an interrupt is pending on the adapter. */	1370	/* See if an interrupt is pending on the adapter. */
1374	static inline bool esas2r_adapter_interrupt_pending(struct esas2r_adapter *a)	1371	static inline bool esas2r_adapter_interrupt_pending(struct esas2r_adapter *a)
1375	{	1372	{
1376	u32 intstat;	1373	u32 intstat;
1377		1374
1378	if (a->int_mask == 0)	1375	if (a->int_mask == 0)
1379	return false;	1376	return false;
1380		1377
1381	intstat = esas2r_read_register_dword(a, MU_INT_STATUS_OUT);	1378	intstat = esas2r_read_register_dword(a, MU_INT_STATUS_OUT);
1382		1379
1383	if ((intstat & a->int_mask) == 0)	1380	if ((intstat & a->int_mask) == 0)
1384	return false;	1381	return false;
1385		1382
1386	esas2r_disable_chip_interrupts(a);	1383	esas2r_disable_chip_interrupts(a);
1387		1384
1388	a->int_stat = intstat;	1385	a->int_stat = intstat;
1389	a->int_mask = 0;	1386	a->int_mask = 0;
1390		1387
1391	return true;	1388	return true;
1392	}	1389	}
1393		1390
1394	static inline u16 esas2r_targ_get_id(struct esas2r_target *t,	1391	static inline u16 esas2r_targ_get_id(struct esas2r_target *t,
1395	struct esas2r_adapter *a)	1392	struct esas2r_adapter *a)
1396	{	1393	{
1397	return (u16)(uintptr_t)(t - a->targetdb);	1394	return (u16)(uintptr_t)(t - a->targetdb);
1398	}	1395	}
1399		1396
1400	/* Build and start an asynchronous event request */	1397	/* Build and start an asynchronous event request */
1401	static inline void esas2r_start_ae_request(struct esas2r_adapter *a,	1398	static inline void esas2r_start_ae_request(struct esas2r_adapter *a,
1402	struct esas2r_request *rq)	1399	struct esas2r_request *rq)
1403	{	1400	{
1404	unsigned long flags;	1401	unsigned long flags;
1405		1402
1406	esas2r_build_ae_req(a, rq);	1403	esas2r_build_ae_req(a, rq);
1407		1404
1408	spin_lock_irqsave(&a->queue_lock, flags);	1405	spin_lock_irqsave(&a->queue_lock, flags);
1409	esas2r_start_vda_request(a, rq);	1406	esas2r_start_vda_request(a, rq);
1410	spin_unlock_irqrestore(&a->queue_lock, flags);	1407	spin_unlock_irqrestore(&a->queue_lock, flags);
1411	}	1408	}
1412		1409
1413	static inline void esas2r_comp_list_drain(struct esas2r_adapter *a,	1410	static inline void esas2r_comp_list_drain(struct esas2r_adapter *a,
1414	struct list_head *comp_list)	1411	struct list_head *comp_list)
1415	{	1412	{
1416	struct esas2r_request *rq;	1413	struct esas2r_request *rq;
1417	struct list_head element, next;	1414	struct list_head element, next;
1418		1415
1419	list_for_each_safe(element, next, comp_list) {	1416	list_for_each_safe(element, next, comp_list) {
1420	rq = list_entry(element, struct esas2r_request, comp_list);	1417	rq = list_entry(element, struct esas2r_request, comp_list);
1421	list_del_init(element);	1418	list_del_init(element);
1422	esas2r_complete_request(a, rq);	1419	esas2r_complete_request(a, rq);
1423	}	1420	}
1424	}	1421	}
1425		1422
1426	/* sysfs handlers */	1423	/* sysfs handlers */
1427	extern struct bin_attribute bin_attr_fw;	1424	extern struct bin_attribute bin_attr_fw;
1428	extern struct bin_attribute bin_attr_fs;	1425	extern struct bin_attribute bin_attr_fs;
1429	extern struct bin_attribute bin_attr_vda;	1426	extern struct bin_attribute bin_attr_vda;
1430	extern struct bin_attribute bin_attr_hw;	1427	extern struct bin_attribute bin_attr_hw;
1431	extern struct bin_attribute bin_attr_live_nvram;	1428	extern struct bin_attribute bin_attr_live_nvram;
1432	extern struct bin_attribute bin_attr_default_nvram;	1429	extern struct bin_attribute bin_attr_default_nvram;
1433		1430
1434	#endif /* ESAS2R_H */	1431	#endif /* ESAS2R_H */
1435		1432

drivers/scsi/esas2r/esas2r_init.c

Diff comments View file @ 8e65e2f

 /*
  *  linux/drivers/scsi/esas2r/esas2r_init.c
  *      For use with ATTO ExpressSAS R6xx SAS/SATA RAID controllers
  *
  *  Copyright (c) 2001-2013 ATTO Technology, Inc.
  *  (mailto:linuxdrivers@attotech.com)mpt3sas/mpt3sas_trigger_diag.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * as published by the Free Software Foundation; either version 2
  * of the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * NO WARRANTY
  * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
  * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
  * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
  * solely responsible for determining the appropriateness of using and
  * distributing the Program and assumes all risks associated with its
  * exercise of rights under this Agreement, including but not limited to
  * the risks and costs of program errors, damage to or loss of data,
  * programs or equipment, and unavailability or interruption of operations.
  *
  * DISCLAIMER OF LIABILITY
  * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
  * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301,
  * USA.
  */
 #include "esas2r.h"
 static bool esas2r_initmem_alloc(struct esas2r_adapter *a,
 				 struct esas2r_mem_desc *mem_desc,
 				 u32 align)
 {
 	mem_desc->esas2r_param = mem_desc->size + align;
 	mem_desc->virt_addr = NULL;
 	mem_desc->phys_addr = 0;
 	mem_desc->esas2r_data = dma_alloc_coherent(&a->pcid->dev,
 						   (size_t)mem_desc->
 						   esas2r_param,
 						   (dma_addr_t *)&mem_desc->
 						   phys_addr,
 						   GFP_KERNEL);
 	if (mem_desc->esas2r_data == NULL) {
 		esas2r_log(ESAS2R_LOG_CRIT,
 			   "failed to allocate %lu bytes of consistent memory!",
 			   (long
 			    unsigned
 			    int)mem_desc->esas2r_param);
 		return false;
 	}
 	mem_desc->virt_addr = PTR_ALIGN(mem_desc->esas2r_data, align);
 	mem_desc->phys_addr = ALIGN(mem_desc->phys_addr, align);
 	memset(mem_desc->virt_addr, 0, mem_desc->size);
 	return true;
 }
 static void esas2r_initmem_free(struct esas2r_adapter *a,
 				struct esas2r_mem_desc *mem_desc)
 {
 	if (mem_desc->virt_addr == NULL)
 		return;
 	/*
 	 * Careful!  phys_addr and virt_addr may have been adjusted from the
 	 * original allocation in order to return the desired alignment.  That
 	 * means we have to use the original address (in esas2r_data) and size
 	 * (esas2r_param) and calculate the original physical address based on
 	 * the difference between the requested and actual allocation size.
 	 */
 	if (mem_desc->phys_addr) {
 		int unalign = ((u8 *)mem_desc->virt_addr) -
 			      ((u8 *)mem_desc->esas2r_data);
 		dma_free_coherent(&a->pcid->dev,
 				  (size_t)mem_desc->esas2r_param,
 				  mem_desc->esas2r_data,
 				  (dma_addr_t)(mem_desc->phys_addr - unalign));
 	} else {
 		kfree(mem_desc->esas2r_data);
 	}
 	mem_desc->virt_addr = NULL;
 }
 static bool alloc_vda_req(struct esas2r_adapter *a,
 			  struct esas2r_request *rq)
 {
 	struct esas2r_mem_desc *memdesc = kzalloc(
 		sizeof(struct esas2r_mem_desc), GFP_KERNEL);
 	if (memdesc == NULL) {
 		esas2r_hdebug("could not alloc mem for vda request memdesc\n");
 		return false;
 	}
 	memdesc->size = sizeof(union atto_vda_req) +
 			ESAS2R_DATA_BUF_LEN;
 	if (!esas2r_initmem_alloc(a, memdesc, 256)) {
 		esas2r_hdebug("could not alloc mem for vda request\n");
 		kfree(memdesc);
 		return false;
 	}
 	a->num_vrqs++;
 	list_add(&memdesc->next_desc, &a->vrq_mds_head);
 	rq->vrq_md = memdesc;
 	rq->vrq = (union atto_vda_req *)memdesc->virt_addr;
 	rq->vrq->scsi.handle = a->num_vrqs;
 	return true;
 }
 static void esas2r_unmap_regions(struct esas2r_adapter *a)
 {
 	if (a->regs)
 		iounmap((void __iomem *)a->regs);
 	a->regs = NULL;
 	pci_release_region(a->pcid, 2);
 	if (a->data_window)
 		iounmap((void __iomem *)a->data_window);
 	a->data_window = NULL;
 	pci_release_region(a->pcid, 0);
 }
 static int esas2r_map_regions(struct esas2r_adapter *a)
 {
 	int error;
 	a->regs = NULL;
 	a->data_window = NULL;
 	error = pci_request_region(a->pcid, 2, a->name);
 	if (error != 0) {
 		esas2r_log(ESAS2R_LOG_CRIT,
 			   "pci_request_region(2) failed, error %d",
 			   error);
 		return error;
 	}
 	a->regs = (void __force *)ioremap(pci_resource_start(a->pcid, 2),
 					  pci_resource_len(a->pcid, 2));
 	if (a->regs == NULL) {
 		esas2r_log(ESAS2R_LOG_CRIT,
 			   "ioremap failed for regs mem region\n");
 		pci_release_region(a->pcid, 2);
 		return -EFAULT;
 	}
 	error = pci_request_region(a->pcid, 0, a->name);
 	if (error != 0) {
 		esas2r_log(ESAS2R_LOG_CRIT,
 			   "pci_request_region(2) failed, error %d",
 			   error);
 		esas2r_unmap_regions(a);
 		return error;
 	}
 	a->data_window = (void __force *)ioremap(pci_resource_start(a->pcid,
 								    0),
 						 pci_resource_len(a->pcid, 0));
 	if (a->data_window == NULL) {
 		esas2r_log(ESAS2R_LOG_CRIT,
 			   "ioremap failed for data_window mem region\n");
 		esas2r_unmap_regions(a);
 		return -EFAULT;
 	}
 	return 0;
 }
 static void esas2r_setup_interrupts(struct esas2r_adapter *a, int intr_mode)
 {
 	int i;
 	/* Set up interrupt mode based on the requested value */
 	switch (intr_mode) {
 	case INTR_MODE_LEGACY:
 use_legacy_interrupts:
 		a->intr_mode = INTR_MODE_LEGACY;
 		break;
 	case INTR_MODE_MSI:
 		i = pci_enable_msi(a->pcid);
 		if (i != 0) {
 			esas2r_log(ESAS2R_LOG_WARN,
 				   "failed to enable MSI for adapter %d, "
 				   "falling back to legacy interrupts "
 				   "(err=%d)", a->index,
 				   i);
 			goto use_legacy_interrupts;
 		}
 		a->intr_mode = INTR_MODE_MSI;
 		set_bit(AF2_MSI_ENABLED, &a->flags2);
 		break;
 	default:
 		esas2r_log(ESAS2R_LOG_WARN,
 			   "unknown interrupt_mode %d requested, "
 			   "falling back to legacy interrupt",
 			   interrupt_mode);
 		goto use_legacy_interrupts;
 	}
 }
 static void esas2r_claim_interrupts(struct esas2r_adapter *a)
 {
 	unsigned long flags = IRQF_DISABLED;
 	if (a->intr_mode == INTR_MODE_LEGACY)
 		flags |= IRQF_SHARED;
 	esas2r_log(ESAS2R_LOG_INFO,
 		   "esas2r_claim_interrupts irq=%d (%p, %s, %x)",
 		   a->pcid->irq, a, a->name, flags);
 	if (request_irq(a->pcid->irq,
 			(a->intr_mode ==
 			 INTR_MODE_LEGACY) ? esas2r_interrupt :
 			esas2r_msi_interrupt,
 			flags,
 			a->name,
 			a)) {
 		esas2r_log(ESAS2R_LOG_CRIT, "unable to request IRQ %02X",
 			   a->pcid->irq);
 		return;
 	}
 	set_bit(AF2_IRQ_CLAIMED, &a->flags2);
 	esas2r_log(ESAS2R_LOG_INFO,
 		   "claimed IRQ %d flags: 0x%lx",
 		   a->pcid->irq, flags);
 }
 int esas2r_init_adapter(struct Scsi_Host *host, struct pci_dev *pcid,
 			int index)
 {
 	struct esas2r_adapter *a;
 	u64 bus_addr = 0;
 	int i;
 	void *next_uncached;
 	struct esas2r_request *first_request, *last_request;
 	if (index >= MAX_ADAPTERS) {
 		esas2r_log(ESAS2R_LOG_CRIT,
 			   "tried to init invalid adapter index %u!",
 			   index);
 		return 0;
 	}
 	if (esas2r_adapters[index]) {
 		esas2r_log(ESAS2R_LOG_CRIT,
 			   "tried to init existing adapter index %u!",
 			   index);
 		return 0;
 	}
 	a = (struct esas2r_adapter *)host->hostdata;
 	memset(a, 0, sizeof(struct esas2r_adapter));
 	a->pcid = pcid;
 	a->host = host;
 	if (sizeof(dma_addr_t) > 4) {
 		const uint64_t required_mask = dma_get_required_mask
 						       (&pcid->dev);
 		if (required_mask > DMA_BIT_MASK(32)
 		    && !pci_set_dma_mask(pcid, DMA_BIT_MASK(64))
 		    && !pci_set_consistent_dma_mask(pcid,
 						    DMA_BIT_MASK(64))) {
 			esas2r_log_dev(ESAS2R_LOG_INFO,
 				       &(a->pcid->dev),
 				       "64-bit PCI addressing enabled\n");
 		} else if (!pci_set_dma_mask(pcid, DMA_BIT_MASK(32))
 			   && !pci_set_consistent_dma_mask(pcid,
 							   DMA_BIT_MASK(32))) {
 			esas2r_log_dev(ESAS2R_LOG_INFO,
 				       &(a->pcid->dev),
 				       "32-bit PCI addressing enabled\n");
 		} else {
 			esas2r_log(ESAS2R_LOG_CRIT,
 				   "failed to set DMA mask");
 			esas2r_kill_adapter(index);
 			return 0;
 		}
 	} else {
 		if (!pci_set_dma_mask(pcid, DMA_BIT_MASK(32))
 		    && !pci_set_consistent_dma_mask(pcid,
 						    DMA_BIT_MASK(32))) {
 			esas2r_log_dev(ESAS2R_LOG_INFO,
 				       &(a->pcid->dev),
 				       "32-bit PCI addressing enabled\n");
 		} else {
 			esas2r_log(ESAS2R_LOG_CRIT,
 				   "failed to set DMA mask");
 			esas2r_kill_adapter(index);
 			return 0;
 		}
 	}
 	esas2r_adapters[index] = a;
 	sprintf(a->name, ESAS2R_DRVR_NAME "_%02d", index);
 	esas2r_debug("new adapter %p, name %s", a, a->name);
 	spin_lock_init(&a->request_lock);
 	spin_lock_init(&a->fw_event_lock);
 	sema_init(&a->fm_api_semaphore, 1);
 	sema_init(&a->fs_api_semaphore, 1);
 	sema_init(&a->nvram_semaphore, 1);
 	esas2r_fw_event_off(a);
 	snprintf(a->fw_event_q_name, ESAS2R_KOBJ_NAME_LEN, "esas2r/%d",
 		 a->index);
 	a->fw_event_q = create_singlethread_workqueue(a->fw_event_q_name);
 	init_waitqueue_head(&a->buffered_ioctl_waiter);
 	init_waitqueue_head(&a->nvram_waiter);
 	init_waitqueue_head(&a->fm_api_waiter);
 	init_waitqueue_head(&a->fs_api_waiter);
 	init_waitqueue_head(&a->vda_waiter);
 	INIT_LIST_HEAD(&a->general_req.req_list);
 	INIT_LIST_HEAD(&a->active_list);
 	INIT_LIST_HEAD(&a->defer_list);
 	INIT_LIST_HEAD(&a->free_sg_list_head);
 	INIT_LIST_HEAD(&a->avail_request);
 	INIT_LIST_HEAD(&a->vrq_mds_head);
 	INIT_LIST_HEAD(&a->fw_event_list);
 	first_request = (struct esas2r_request *)((u8 *)(a + 1));
 	for (last_request = first_request, i = 1; i < num_requests;
 	     last_request++, i++) {
 		INIT_LIST_HEAD(&last_request->req_list);
 		list_add_tail(&last_request->comp_list, &a->avail_request);
 		if (!alloc_vda_req(a, last_request)) {
 			esas2r_log(ESAS2R_LOG_CRIT,
 				   "failed to allocate a VDA request!");
 			esas2r_kill_adapter(index);
 			return 0;
 		}
 	}
 	esas2r_debug("requests: %p to %p (%d, %d)", first_request,
 		     last_request,
 		     sizeof(*first_request),
 		     num_requests);
 	if (esas2r_map_regions(a) != 0) {
 		esas2r_log(ESAS2R_LOG_CRIT, "could not map PCI regions!");
 		esas2r_kill_adapter(index);
 		return 0;
 	}
 	a->index = index;
 	/* interrupts will be disabled until we are done with init */
 	atomic_inc(&a->dis_ints_cnt);
 	atomic_inc(&a->disable_cnt);
 	set_bit(AF_CHPRST_PENDING, &a->flags);
 	set_bit(AF_DISC_PENDING, &a->flags);
 	set_bit(AF_FIRST_INIT, &a->flags);
 	set_bit(AF_LEGACY_SGE_MODE, &a->flags);
 	a->init_msg = ESAS2R_INIT_MSG_START;
 	a->max_vdareq_size = 128;
 	a->build_sgl = esas2r_build_sg_list_sge;
 	esas2r_setup_interrupts(a, interrupt_mode);
 	a->uncached_size = esas2r_get_uncached_size(a);
 	a->uncached = dma_alloc_coherent(&pcid->dev,
 					 (size_t)a->uncached_size,
 					 (dma_addr_t *)&bus_addr,
 					 GFP_KERNEL);
 	if (a->uncached == NULL) {
 		esas2r_log(ESAS2R_LOG_CRIT,
 			   "failed to allocate %d bytes of consistent memory!",
 			   a->uncached_size);
 		esas2r_kill_adapter(index);
 		return 0;
 	}
 	a->uncached_phys = bus_addr;
 	esas2r_debug("%d bytes uncached memory allocated @ %p (%x:%x)",
 		     a->uncached_size,
 		     a->uncached,
 		     upper_32_bits(bus_addr),
 		     lower_32_bits(bus_addr));
 	memset(a->uncached, 0, a->uncached_size);
 	next_uncached = a->uncached;
 	if (!esas2r_init_adapter_struct(a,
 					&next_uncached)) {
 		esas2r_log(ESAS2R_LOG_CRIT,
 			   "failed to initialize adapter structure (2)!");
 		esas2r_kill_adapter(index);
 		return 0;
 	}
 	tasklet_init(&a->tasklet,
 		     esas2r_adapter_tasklet,
 		     (unsigned long)a);
 	/*
 	 * Disable chip interrupts to prevent spurious interrupts
 	 * until we claim the IRQ.
 	 */
 	esas2r_disable_chip_interrupts(a);
 	esas2r_check_adapter(a);
 	if (!esas2r_init_adapter_hw(a, true))
 		esas2r_log(ESAS2R_LOG_CRIT, "failed to initialize hardware!");
 	else
 		esas2r_debug("esas2r_init_adapter ok");
 	esas2r_claim_interrupts(a);
 	if (test_bit(AF2_IRQ_CLAIMED, &a->flags2))
 		esas2r_enable_chip_interrupts(a);
 	set_bit(AF2_INIT_DONE, &a->flags2);
 	if (!test_bit(AF_DEGRADED_MODE, &a->flags))
 		esas2r_kickoff_timer(a);
 	esas2r_debug("esas2r_init_adapter done for %p (%d)",
 		     a, a->disable_cnt);
 	return 1;
 }
 static void esas2r_adapter_power_down(struct esas2r_adapter *a,
 				      int power_management)
 {
 	struct esas2r_mem_desc *memdesc, *next;
 	if ((test_bit(AF2_INIT_DONE, &a->flags2))
 	    &&  (!test_bit(AF_DEGRADED_MODE, &a->flags))) {
 		if (!power_management) {
 			del_timer_sync(&a->timer);
 			tasklet_kill(&a->tasklet);
 		}
 		esas2r_power_down(a);
 		/*
 		 * There are versions of firmware that do not handle the sync
 		 * cache command correctly.  Stall here to ensure that the
 		 * cache is lazily flushed.
 		 */
 		mdelay(500);
 		esas2r_debug("chip halted");
 	}
 	/* Remove sysfs binary files */
 	if (a->sysfs_fw_created) {
 		sysfs_remove_bin_file(&a->host->shost_dev.kobj, &bin_attr_fw);
 		a->sysfs_fw_created = 0;
 	}
 	if (a->sysfs_fs_created) {
 		sysfs_remove_bin_file(&a->host->shost_dev.kobj, &bin_attr_fs);
 		a->sysfs_fs_created = 0;
 	}
 	if (a->sysfs_vda_created) {
 		sysfs_remove_bin_file(&a->host->shost_dev.kobj, &bin_attr_vda);
 		a->sysfs_vda_created = 0;
 	}
 	if (a->sysfs_hw_created) {
 		sysfs_remove_bin_file(&a->host->shost_dev.kobj, &bin_attr_hw);
 		a->sysfs_hw_created = 0;
 	}
 	if (a->sysfs_live_nvram_created) {
 		sysfs_remove_bin_file(&a->host->shost_dev.kobj,
 				      &bin_attr_live_nvram);
 		a->sysfs_live_nvram_created = 0;
 	}
 	if (a->sysfs_default_nvram_created) {
 		sysfs_remove_bin_file(&a->host->shost_dev.kobj,
 				      &bin_attr_default_nvram);
 		a->sysfs_default_nvram_created = 0;
 	}
 	/* Clean up interrupts */
 	if (test_bit(AF2_IRQ_CLAIMED, &a->flags2)) {
 		esas2r_log_dev(ESAS2R_LOG_INFO,
 			       &(a->pcid->dev),
 			       "free_irq(%d) called", a->pcid->irq);
 		free_irq(a->pcid->irq, a);
 		esas2r_debug("IRQ released");
 		clear_bit(AF2_IRQ_CLAIMED, &a->flags2);
 	}
 	if (test_bit(AF2_MSI_ENABLED, &a->flags2)) {
 		pci_disable_msi(a->pcid);
 		clear_bit(AF2_MSI_ENABLED, &a->flags2);
 		esas2r_debug("MSI disabled");
 	}
 	if (a->inbound_list_md.virt_addr)
 		esas2r_initmem_free(a, &a->inbound_list_md);
 	if (a->outbound_list_md.virt_addr)
 		esas2r_initmem_free(a, &a->outbound_list_md);
 	list_for_each_entry_safe(memdesc, next, &a->free_sg_list_head,
 				 next_desc) {
 		esas2r_initmem_free(a, memdesc);
 	}
 	/* Following frees everything allocated via alloc_vda_req */
 	list_for_each_entry_safe(memdesc, next, &a->vrq_mds_head, next_desc) {
 		esas2r_initmem_free(a, memdesc);
 		list_del(&memdesc->next_desc);
 		kfree(memdesc);
 	}
 	kfree(a->first_ae_req);
 	a->first_ae_req = NULL;
 	kfree(a->sg_list_mds);
 	a->sg_list_mds = NULL;
 	kfree(a->req_table);
 	a->req_table = NULL;
 	if (a->regs) {
 		esas2r_unmap_regions(a);
 		a->regs = NULL;
 		a->data_window = NULL;
 		esas2r_debug("regions unmapped");
 	}
 }
 /* Release/free allocated resources for specified adapters. */
 void esas2r_kill_adapter(int i)
 {
 	struct esas2r_adapter *a = esas2r_adapters[i];
 	if (a) {
 		unsigned long flags;
 		struct workqueue_struct *wq;
 		esas2r_debug("killing adapter %p [%d] ", a, i);
 		esas2r_fw_event_off(a);
 		esas2r_adapter_power_down(a, 0);
 		if (esas2r_buffered_ioctl &&
 		    (a->pcid == esas2r_buffered_ioctl_pcid)) {
 			dma_free_coherent(&a->pcid->dev,
 					  (size_t)esas2r_buffered_ioctl_size,
 					  esas2r_buffered_ioctl,
 					  esas2r_buffered_ioctl_addr);
 			esas2r_buffered_ioctl = NULL;
 		}
 		if (a->vda_buffer) {
 			dma_free_coherent(&a->pcid->dev,
 					  (size_t)VDA_MAX_BUFFER_SIZE,
 					  a->vda_buffer,
 					  (dma_addr_t)a->ppvda_buffer);
 			a->vda_buffer = NULL;
 		}
 		if (a->fs_api_buffer) {
 			dma_free_coherent(&a->pcid->dev,
 					  (size_t)a->fs_api_buffer_size,
 					  a->fs_api_buffer,
 					  (dma_addr_t)a->ppfs_api_buffer);
 			a->fs_api_buffer = NULL;
 		}
 		kfree(a->local_atto_ioctl);
 		a->local_atto_ioctl = NULL;
 		spin_lock_irqsave(&a->fw_event_lock, flags);
 		wq = a->fw_event_q;
 		a->fw_event_q = NULL;
 		spin_unlock_irqrestore(&a->fw_event_lock, flags);
 		if (wq)
 			destroy_workqueue(wq);
 		if (a->uncached) {
 			dma_free_coherent(&a->pcid->dev,
 					  (size_t)a->uncached_size,
 					  a->uncached,
 					  (dma_addr_t)a->uncached_phys);
 			a->uncached = NULL;
 			esas2r_debug("uncached area freed");
 		}
 		esas2r_log_dev(ESAS2R_LOG_INFO,
 			       &(a->pcid->dev),
 			       "pci_disable_device() called.  msix_enabled: %d "
 			       "msi_enabled: %d irq: %d pin: %d",
 			       a->pcid->msix_enabled,
 			       a->pcid->msi_enabled,
 			       a->pcid->irq,
 			       a->pcid->pin);
 		esas2r_log_dev(ESAS2R_LOG_INFO,
 			       &(a->pcid->dev),
 			       "before pci_disable_device() enable_cnt: %d",
 			       a->pcid->enable_cnt.counter);
 		pci_disable_device(a->pcid);
 		esas2r_log_dev(ESAS2R_LOG_INFO,
 			       &(a->pcid->dev),
 			       "after pci_disable_device() enable_cnt: %d",
 			       a->pcid->enable_cnt.counter);
 		esas2r_log_dev(ESAS2R_LOG_INFO,
 			       &(a->pcid->dev),
 			       "pci_set_drv_data(%p, NULL) called",
 			       a->pcid);
 		pci_set_drvdata(a->pcid, NULL);
 		esas2r_adapters[i] = NULL;
 		if (test_bit(AF2_INIT_DONE, &a->flags2)) {
 			clear_bit(AF2_INIT_DONE, &a->flags2);
 			set_bit(AF_DEGRADED_MODE, &a->flags);
 			esas2r_log_dev(ESAS2R_LOG_INFO,
 				       &(a->host->shost_gendev),
 				       "scsi_remove_host() called");
 			scsi_remove_host(a->host);
 			esas2r_log_dev(ESAS2R_LOG_INFO,
 				       &(a->host->shost_gendev),
 				       "scsi_host_put() called");
 			scsi_host_put(a->host);
 		}
 	}
 }
 int esas2r_cleanup(struct Scsi_Host *host)
 {
 	struct esas2r_adapter *a;
 	int index;
 	if (host == NULL) {
 		int i;
 		esas2r_debug("esas2r_cleanup everything");
 		for (i = 0; i < MAX_ADAPTERS; i++)
 			esas2r_kill_adapter(i);
 		return -1;
 	}
 	esas2r_debug("esas2r_cleanup called for host %p", host);
 	a = (struct esas2r_adapter *)host->hostdata;
 	index = a->index;
 	esas2r_kill_adapter(index);
 	return index;
 }
 int esas2r_suspend(struct pci_dev *pdev, pm_message_t state)
 {
 	struct Scsi_Host *host = pci_get_drvdata(pdev);
 	u32 device_state;
 	struct esas2r_adapter *a = (struct esas2r_adapter *)host->hostdata;
 	esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev), "suspending adapter()");
 	if (!a)
 		return -ENODEV;
 	esas2r_adapter_power_down(a, 1);
 	device_state = pci_choose_state(pdev, state);
 	esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
 		       "pci_save_state() called");
 	pci_save_state(pdev);
 	esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
 		       "pci_disable_device() called");
 	pci_disable_device(pdev);
 	esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
 		       "pci_set_power_state() called");
 	pci_set_power_state(pdev, device_state);
 	esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev), "esas2r_suspend(): 0");
 	return 0;
 }
 int esas2r_resume(struct pci_dev *pdev)
 {
 	struct Scsi_Host *host = pci_get_drvdata(pdev);
 	struct esas2r_adapter *a = (struct esas2r_adapter *)host->hostdata;
 	int rez;
 	esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev), "resuming adapter()");
 	esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
 		       "pci_set_power_state(PCI_D0) "
 		       "called");
 	pci_set_power_state(pdev, PCI_D0);
 	esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
 		       "pci_enable_wake(PCI_D0, 0) "
 		       "called");
 	pci_enable_wake(pdev, PCI_D0, 0);
 	esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
 		       "pci_restore_state() called");
 	pci_restore_state(pdev);
 	esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
 		       "pci_enable_device() called");
 	rez = pci_enable_device(pdev);
 	pci_set_master(pdev);
 	if (!a) {
 		rez = -ENODEV;
 		goto error_exit;
 	}
 	if (esas2r_map_regions(a) != 0) {
 		esas2r_log(ESAS2R_LOG_CRIT, "could not re-map PCI regions!");
 		rez = -ENOMEM;
 		goto error_exit;
 	}
 	/* Set up interupt mode */
 	esas2r_setup_interrupts(a, a->intr_mode);
 	/*
 	 * Disable chip interrupts to prevent spurious interrupts until we
 	 * claim the IRQ.
 	 */
 	esas2r_disable_chip_interrupts(a);
 	if (!esas2r_power_up(a, true)) {
 		esas2r_debug("yikes, esas2r_power_up failed");
 		rez = -ENOMEM;
 		goto error_exit;
 	}
 	esas2r_claim_interrupts(a);
 	if (test_bit(AF2_IRQ_CLAIMED, &a->flags2)) {
 		/*
 		 * Now that system interrupt(s) are claimed, we can enable
 		 * chip interrupts.
 		 */
 		esas2r_enable_chip_interrupts(a);
 		esas2r_kickoff_timer(a);
 	} else {
 		esas2r_debug("yikes, unable to claim IRQ");
 		esas2r_log(ESAS2R_LOG_CRIT, "could not re-claim IRQ!");
 		rez = -ENOMEM;
 		goto error_exit;
 	}
 error_exit:
 	esas2r_log_dev(ESAS2R_LOG_CRIT, &(pdev->dev), "esas2r_resume(): %d",
 		       rez);
 	return rez;
 }
 bool esas2r_set_degraded_mode(struct esas2r_adapter *a, char *error_str)
 {
 	set_bit(AF_DEGRADED_MODE, &a->flags);
 	esas2r_log(ESAS2R_LOG_CRIT,
 		   "setting adapter to degraded mode: %s\n", error_str);
 	return false;
 }
 u32 esas2r_get_uncached_size(struct esas2r_adapter *a)
 {
 	return sizeof(struct esas2r_sas_nvram)
 	       + ALIGN(ESAS2R_DISC_BUF_LEN, 8)
 	       + ALIGN(sizeof(u32), 8) /* outbound list copy pointer */
 	       + 8
 	       + (num_sg_lists * (u16)sgl_page_size)
 	       + ALIGN((num_requests + num_ae_requests + 1 +
 			ESAS2R_LIST_EXTRA) *
 		       sizeof(struct esas2r_inbound_list_source_entry),
 		       8)
 	       + ALIGN((num_requests + num_ae_requests + 1 +
 			ESAS2R_LIST_EXTRA) *
 		       sizeof(struct atto_vda_ob_rsp), 8)
 	       + 256; /* VDA request and buffer align */
 }
 static void esas2r_init_pci_cfg_space(struct esas2r_adapter *a)
 {
 	int pcie_cap_reg;
 	pcie_cap_reg = pci_find_capability(a->pcid, PCI_CAP_ID_EXP);
 	if (0xffff & pcie_cap_reg) {
 		u16 devcontrol;
 		pci_read_config_word(a->pcid, pcie_cap_reg + PCI_EXP_DEVCTL,
 				     &devcontrol);
 		if ((devcontrol & PCI_EXP_DEVCTL_READRQ) > 0x2000) {
 			esas2r_log(ESAS2R_LOG_INFO,
 				   "max read request size > 512B");
 			devcontrol &= ~PCI_EXP_DEVCTL_READRQ;
 			devcontrol |= 0x2000;
 			pci_write_config_word(a->pcid,
 					      pcie_cap_reg + PCI_EXP_DEVCTL,
 					      devcontrol);
 		}
 	}
 }
 /*
  * Determine the organization of the uncached data area and
  * finish initializing the adapter structure
  */
 bool esas2r_init_adapter_struct(struct esas2r_adapter *a,
 				void **uncached_area)
 {
 	u32 i;
 	u8 *high;
 	struct esas2r_inbound_list_source_entry *element;
 	struct esas2r_request *rq;
 	struct esas2r_mem_desc *sgl;
 	spin_lock_init(&a->sg_list_lock);
 	spin_lock_init(&a->mem_lock);
 	spin_lock_init(&a->queue_lock);
 	a->targetdb_end = &a->targetdb[ESAS2R_MAX_TARGETS];
 	if (!alloc_vda_req(a, &a->general_req)) {
 		esas2r_hdebug(
 			"failed to allocate a VDA request for the general req!");
 		return false;
 	}
 	/* allocate requests for asynchronous events */
 	a->first_ae_req =
 		kzalloc(num_ae_requests * sizeof(struct esas2r_request),
 			GFP_KERNEL);
 	if (a->first_ae_req == NULL) {
 		esas2r_log(ESAS2R_LOG_CRIT,
 			   "failed to allocate memory for asynchronous events");
 		return false;
 	}
 	/* allocate the S/G list memory descriptors */
 	a->sg_list_mds = kzalloc(
 		num_sg_lists * sizeof(struct esas2r_mem_desc), GFP_KERNEL);
 	if (a->sg_list_mds == NULL) {
 		esas2r_log(ESAS2R_LOG_CRIT,
 			   "failed to allocate memory for s/g list descriptors");
 		return false;
 	}
 	/* allocate the request table */
 	a->req_table =
 		kzalloc((num_requests + num_ae_requests +
 			 1) * sizeof(struct esas2r_request *), GFP_KERNEL);
 	if (a->req_table == NULL) {
 		esas2r_log(ESAS2R_LOG_CRIT,
 			   "failed to allocate memory for the request table");
 		return false;
 	}
 	/* initialize PCI configuration space */
 	esas2r_init_pci_cfg_space(a);
 	/*
 	 * the thunder_stream boards all have a serial flash part that has a
 	 * different base address on the AHB bus.
 	 */
 	if ((a->pcid->subsystem_vendor == ATTO_VENDOR_ID)
 	    && (a->pcid->subsystem_device & ATTO_SSDID_TBT))
 		a->flags2 |= AF2_THUNDERBOLT;
 	if (test_bit(AF2_THUNDERBOLT, &a->flags2))
 		a->flags2 |= AF2_SERIAL_FLASH;
 	if (a->pcid->subsystem_device == ATTO_TLSH_1068)
 		a->flags2 |= AF2_THUNDERLINK;
 	/* Uncached Area */
 	high = (u8 *)*uncached_area;
 	/* initialize the scatter/gather table pages */
 	for (i = 0, sgl = a->sg_list_mds; i < num_sg_lists; i++, sgl++) {
 		sgl->size = sgl_page_size;
 		list_add_tail(&sgl->next_desc, &a->free_sg_list_head);
 		if (!esas2r_initmem_alloc(a, sgl, ESAS2R_SGL_ALIGN)) {
 			/* Allow the driver to load if the minimum count met. */
 			if (i < NUM_SGL_MIN)
 				return false;
 			break;
 		}
 	}
 	/* compute the size of the lists */
 	a->list_size = num_requests + ESAS2R_LIST_EXTRA;
 	/* allocate the inbound list */
 	a->inbound_list_md.size = a->list_size *
 				  sizeof(struct
 					 esas2r_inbound_list_source_entry);
 	if (!esas2r_initmem_alloc(a, &a->inbound_list_md, ESAS2R_LIST_ALIGN)) {
 		esas2r_hdebug("failed to allocate IB list");
 		return false;
 	}
 	/* allocate the outbound list */
 	a->outbound_list_md.size = a->list_size *
 				   sizeof(struct atto_vda_ob_rsp);
 	if (!esas2r_initmem_alloc(a, &a->outbound_list_md,
 				  ESAS2R_LIST_ALIGN)) {
 		esas2r_hdebug("failed to allocate IB list");
 		return false;
 	}
 	/* allocate the NVRAM structure */
 	a->nvram = (struct esas2r_sas_nvram *)high;
 	high += sizeof(struct esas2r_sas_nvram);
 	/* allocate the discovery buffer */
 	a->disc_buffer = high;
 	high += ESAS2R_DISC_BUF_LEN;
 	high = PTR_ALIGN(high, 8);
 	/* allocate the outbound list copy pointer */
 	a->outbound_copy = (u32 volatile *)high;
 	high += sizeof(u32);
 	if (!test_bit(AF_NVR_VALID, &a->flags))
 		esas2r_nvram_set_defaults(a);
 	/* update the caller's uncached memory area pointer */
 	*uncached_area = (void *)high;
 	/* initialize the allocated memory */
 	if (test_bit(AF_FIRST_INIT, &a->flags)) {
 		memset(a->req_table, 0,
 		       (num_requests + num_ae_requests +
 			1) * sizeof(struct esas2r_request *));
 		esas2r_targ_db_initialize(a);
 		/* prime parts of the inbound list */
 		element =
 			(struct esas2r_inbound_list_source_entry *)a->
 			inbound_list_md.
 			virt_addr;
 		for (i = 0; i < a->list_size; i++) {
 			element->address = 0;
 			element->reserved = 0;
 			element->length = cpu_to_le32(HWILSE_INTERFACE_F0
 						      | (sizeof(union
 								atto_vda_req)
 							 /
 							 sizeof(u32)));
 			element++;
 		}
 		/* init the AE requests */
 		for (rq = a->first_ae_req, i = 0; i < num_ae_requests; rq++,
 		     i++) {
 			INIT_LIST_HEAD(&rq->req_list);
 			if (!alloc_vda_req(a, rq)) {
 				esas2r_hdebug(
 					"failed to allocate a VDA request!");
 				return false;
 			}
 			esas2r_rq_init_request(rq, a);
 			/* override the completion function */
 			rq->comp_cb = esas2r_ae_complete;
 		}
 	}
 	return true;
 }
 /* This code will verify that the chip is operational. */
 bool esas2r_check_adapter(struct esas2r_adapter *a)
 {
 	u32 starttime;
 	u32 doorbell;
 	u64 ppaddr;
 	u32 dw;
 	/*
 	 * if the chip reset detected flag is set, we can bypass a bunch of
 	 * stuff.
 	 */
 	if (test_bit(AF_CHPRST_DETECTED, &a->flags))
 		goto skip_chip_reset;
 	/*
 	 * BEFORE WE DO ANYTHING, disable the chip interrupts!  the boot driver
 	 * may have left them enabled or we may be recovering from a fault.
 	 */
 	esas2r_write_register_dword(a, MU_INT_MASK_OUT, ESAS2R_INT_DIS_MASK);
 	esas2r_flush_register_dword(a, MU_INT_MASK_OUT);
 	/*
 	 * wait for the firmware to become ready by forcing an interrupt and
 	 * waiting for a response.
 	 */
 	starttime = jiffies_to_msecs(jiffies);
 	while (true) {
 		esas2r_force_interrupt(a);
 		doorbell = esas2r_read_register_dword(a, MU_DOORBELL_OUT);
 		if (doorbell == 0xFFFFFFFF) {
 			/*
 			 * Give the firmware up to two seconds to enable
 			 * register access after a reset.
 			 */
 			if ((jiffies_to_msecs(jiffies) - starttime) > 2000)
 				return esas2r_set_degraded_mode(a,
 								"unable to access registers");
 		} else if (doorbell & DRBL_FORCE_INT) {
 			u32 ver = (doorbell & DRBL_FW_VER_MSK);
 			/*
 			 * This driver supports version 0 and version 1 of
 			 * the API
 			 */
 			esas2r_write_register_dword(a, MU_DOORBELL_OUT,
 						    doorbell);
 			if (ver == DRBL_FW_VER_0) {
 				set_bit(AF_LEGACY_SGE_MODE, &a->flags);
 				a->max_vdareq_size = 128;
 				a->build_sgl = esas2r_build_sg_list_sge;
 			} else if (ver == DRBL_FW_VER_1) {
 				clear_bit(AF_LEGACY_SGE_MODE, &a->flags);
 				a->max_vdareq_size = 1024;
 				a->build_sgl = esas2r_build_sg_list_prd;
 			} else {
 				return esas2r_set_degraded_mode(a,
 								"unknown firmware version");
 			}
 			break;
 		}
 		schedule_timeout_interruptible(msecs_to_jiffies(100));
 		if ((jiffies_to_msecs(jiffies) - starttime) > 180000) {
 			esas2r_hdebug("FW ready TMO");
 			esas2r_bugon();
 			return esas2r_set_degraded_mode(a,
 							"firmware start has timed out");
 		}
 	}
 	/* purge any asynchronous events since we will repost them later */
 	esas2r_write_register_dword(a, MU_DOORBELL_IN, DRBL_MSG_IFC_DOWN);
 	starttime = jiffies_to_msecs(jiffies);
 	while (true) {
 		doorbell = esas2r_read_register_dword(a, MU_DOORBELL_OUT);
 		if (doorbell & DRBL_MSG_IFC_DOWN) {
 			esas2r_write_register_dword(a, MU_DOORBELL_OUT,
 						    doorbell);
 			break;
 		}
 		schedule_timeout_interruptible(msecs_to_jiffies(50));
 		if ((jiffies_to_msecs(jiffies) - starttime) > 3000) {
 			esas2r_hdebug("timeout waiting for interface down");
 			break;
 		}
 	}
 skip_chip_reset:
 	/*
 	 * first things first, before we go changing any of these registers
 	 * disable the communication lists.
 	 */
 	dw = esas2r_read_register_dword(a, MU_IN_LIST_CONFIG);
 	dw &= ~MU_ILC_ENABLE;
 	esas2r_write_register_dword(a, MU_IN_LIST_CONFIG, dw);
 	dw = esas2r_read_register_dword(a, MU_OUT_LIST_CONFIG);
 	dw &= ~MU_OLC_ENABLE;
 	esas2r_write_register_dword(a, MU_OUT_LIST_CONFIG, dw);
 	/* configure the communication list addresses */
 	ppaddr = a->inbound_list_md.phys_addr;
 	esas2r_write_register_dword(a, MU_IN_LIST_ADDR_LO,
 				    lower_32_bits(ppaddr));
 	esas2r_write_register_dword(a, MU_IN_LIST_ADDR_HI,
 				    upper_32_bits(ppaddr));
 	ppaddr = a->outbound_list_md.phys_addr;
 	esas2r_write_register_dword(a, MU_OUT_LIST_ADDR_LO,
 				    lower_32_bits(ppaddr));
 	esas2r_write_register_dword(a, MU_OUT_LIST_ADDR_HI,
 				    upper_32_bits(ppaddr));
 	ppaddr = a->uncached_phys +
 		 ((u8 *)a->outbound_copy - a->uncached);
 	esas2r_write_register_dword(a, MU_OUT_LIST_COPY_PTR_LO,
 				    lower_32_bits(ppaddr));
 	esas2r_write_register_dword(a, MU_OUT_LIST_COPY_PTR_HI,
 				    upper_32_bits(ppaddr));
 	/* reset the read and write pointers */
 	*a->outbound_copy =
 		a->last_write =
 			a->last_read = a->list_size - 1;
 	set_bit(AF_COMM_LIST_TOGGLE, &a->flags);
 	esas2r_write_register_dword(a, MU_IN_LIST_WRITE, MU_ILW_TOGGLE |
 				    a->last_write);
 	esas2r_write_register_dword(a, MU_OUT_LIST_COPY, MU_OLC_TOGGLE |
 				    a->last_write);
 	esas2r_write_register_dword(a, MU_IN_LIST_READ, MU_ILR_TOGGLE |
 				    a->last_write);
 	esas2r_write_register_dword(a, MU_OUT_LIST_WRITE,
 				    MU_OLW_TOGGLE | a->last_write);
 	/* configure the interface select fields */
 	dw = esas2r_read_register_dword(a, MU_IN_LIST_IFC_CONFIG);
 	dw &= ~(MU_ILIC_LIST | MU_ILIC_DEST);
 	esas2r_write_register_dword(a, MU_IN_LIST_IFC_CONFIG,
 				    (dw | MU_ILIC_LIST_F0 | MU_ILIC_DEST_DDR));
 	dw = esas2r_read_register_dword(a, MU_OUT_LIST_IFC_CONFIG);
 	dw &= ~(MU_OLIC_LIST | MU_OLIC_SOURCE);
 	esas2r_write_register_dword(a, MU_OUT_LIST_IFC_CONFIG,
 				    (dw | MU_OLIC_LIST_F0 |
 				     MU_OLIC_SOURCE_DDR));
 	/* finish configuring the communication lists */
 	dw = esas2r_read_register_dword(a, MU_IN_LIST_CONFIG);
 	dw &= ~(MU_ILC_ENTRY_MASK | MU_ILC_NUMBER_MASK);
 	dw |= MU_ILC_ENTRY_4_DW | MU_ILC_DYNAMIC_SRC
 	      | (a->list_size << MU_ILC_NUMBER_SHIFT);
 	esas2r_write_register_dword(a, MU_IN_LIST_CONFIG, dw);
 	dw = esas2r_read_register_dword(a, MU_OUT_LIST_CONFIG);
 	dw &= ~(MU_OLC_ENTRY_MASK | MU_OLC_NUMBER_MASK);
 	dw |= MU_OLC_ENTRY_4_DW | (a->list_size << MU_OLC_NUMBER_SHIFT);
 	esas2r_write_register_dword(a, MU_OUT_LIST_CONFIG, dw);
 	/*
 	 * notify the firmware that we're done setting up the communication
 	 * list registers.  wait here until the firmware is done configuring
 	 * its lists.  it will signal that it is done by enabling the lists.
 	 */
 	esas2r_write_register_dword(a, MU_DOORBELL_IN, DRBL_MSG_IFC_INIT);
 	starttime = jiffies_to_msecs(jiffies);
 	while (true) {
 		doorbell = esas2r_read_register_dword(a, MU_DOORBELL_OUT);
 		if (doorbell & DRBL_MSG_IFC_INIT) {
 			esas2r_write_register_dword(a, MU_DOORBELL_OUT,
 						    doorbell);
 			break;
 		}
 		schedule_timeout_interruptible(msecs_to_jiffies(100));
 		if ((jiffies_to_msecs(jiffies) - starttime) > 3000) {
 			esas2r_hdebug(
 				"timeout waiting for communication list init");
 			esas2r_bugon();
 			return esas2r_set_degraded_mode(a,
 							"timeout waiting for communication list init");
 		}
 	}
 	/*
 	 * flag whether the firmware supports the power down doorbell.  we
 	 * determine this by reading the inbound doorbell enable mask.
 	 */
 	doorbell = esas2r_read_register_dword(a, MU_DOORBELL_IN_ENB);
 	if (doorbell & DRBL_POWER_DOWN)
 		set_bit(AF2_VDA_POWER_DOWN, &a->flags2);
 	else
 		clear_bit(AF2_VDA_POWER_DOWN, &a->flags2);
 	/*
 	 * enable assertion of outbound queue and doorbell interrupts in the
 	 * main interrupt cause register.
 	 */
 	esas2r_write_register_dword(a, MU_OUT_LIST_INT_MASK, MU_OLIS_MASK);
 	esas2r_write_register_dword(a, MU_DOORBELL_OUT_ENB, DRBL_ENB_MASK);
 	return true;
 }
 /* Process the initialization message just completed and format the next one. */
 static bool esas2r_format_init_msg(struct esas2r_adapter *a,
 				   struct esas2r_request *rq)
 {
 	u32 msg = a->init_msg;
 	struct atto_vda_cfg_init *ci;
 	a->init_msg = 0;
 	switch (msg) {
 	case ESAS2R_INIT_MSG_START:
 	case ESAS2R_INIT_MSG_REINIT:
 	{
 		struct timeval now;
 		do_gettimeofday(&now);
 		esas2r_hdebug("CFG init");
 		esas2r_build_cfg_req(a,
 				     rq,
 				     VDA_CFG_INIT,
 				     0,
 				     NULL);
 		ci = (struct atto_vda_cfg_init *)&rq->vrq->cfg.data.init;
-		ci->sgl_page_size = sgl_page_size;
+		ci->sgl_page_size = cpu_to_le32(sgl_page_size);
-		ci->epoch_time = now.tv_sec;
+		ci->epoch_time = cpu_to_le32(now.tv_sec);
 		rq->flags |= RF_FAILURE_OK;
 		a->init_msg = ESAS2R_INIT_MSG_INIT;
 		break;
 	}
 	case ESAS2R_INIT_MSG_INIT:
 		if (rq->req_stat == RS_SUCCESS) {
 			u32 major;
 			u32 minor;
+			u16 fw_release;
 			a->fw_version = le16_to_cpu(
 				rq->func_rsp.cfg_rsp.vda_version);
 			a->fw_build = rq->func_rsp.cfg_rsp.fw_build;
-			major = LOBYTE(rq->func_rsp.cfg_rsp.fw_release);
+			fw_release = le16_to_cpu(
-			minor = HIBYTE(rq->func_rsp.cfg_rsp.fw_release);
+				rq->func_rsp.cfg_rsp.fw_release);
+			major = LOBYTE(fw_release);
+			minor = HIBYTE(fw_release);
 			a->fw_version += (major << 16) + (minor << 24);
 		} else {
 			esas2r_hdebug("FAILED");
 		}
 		/*
 		 * the 2.71 and earlier releases of R6xx firmware did not error
 		 * unsupported config requests correctly.
 		 */
 		if ((test_bit(AF2_THUNDERBOLT, &a->flags2))
 		    || (be32_to_cpu(a->fw_version) > 0x00524702)) {
 			esas2r_hdebug("CFG get init");
 			esas2r_build_cfg_req(a,
 					     rq,
 					     VDA_CFG_GET_INIT2,
 					     sizeof(struct atto_vda_cfg_init),
 					     NULL);
 			rq->vrq->cfg.sg_list_offset = offsetof(
 				struct atto_vda_cfg_req,
 				data.sge);
 			rq->vrq->cfg.data.prde.ctl_len =
 				cpu_to_le32(sizeof(struct atto_vda_cfg_init));
 			rq->vrq->cfg.data.prde.address = cpu_to_le64(
 				rq->vrq_md->phys_addr +
 				sizeof(union atto_vda_req));
 			rq->flags |= RF_FAILURE_OK;
 			a->init_msg = ESAS2R_INIT_MSG_GET_INIT;
 			break;
 		}
 	case ESAS2R_INIT_MSG_GET_INIT:
 		if (msg == ESAS2R_INIT_MSG_GET_INIT) {
 			ci = (struct atto_vda_cfg_init *)rq->data_buf;
 			if (rq->req_stat == RS_SUCCESS) {
 				a->num_targets_backend =
 					le32_to_cpu(ci->num_targets_backend);
 				a->ioctl_tunnel =
 					le32_to_cpu(ci->ioctl_tunnel);
 			} else {
 				esas2r_hdebug("FAILED");
 			}
 		}
 	/* fall through */
 	default:
 		rq->req_stat = RS_SUCCESS;
 		return false;
 	}
 	return true;
 }
 /*
  * Perform initialization messages via the request queue.  Messages are
  * performed with interrupts disabled.
  */
 bool esas2r_init_msgs(struct esas2r_adapter *a)
 {
 	bool success = true;
 	struct esas2r_request *rq = &a->general_req;
 	esas2r_rq_init_request(rq, a);
 	rq->comp_cb = esas2r_dummy_complete;
 	if (a->init_msg == 0)
 		a->init_msg = ESAS2R_INIT_MSG_REINIT;
 	while (a->init_msg) {
 		if (esas2r_format_init_msg(a, rq)) {
 			unsigned long flags;
 			while (true) {
 				spin_lock_irqsave(&a->queue_lock, flags);
 				esas2r_start_vda_request(a, rq);
 				spin_unlock_irqrestore(&a->queue_lock, flags);
 				esas2r_wait_request(a, rq);
 				if (rq->req_stat != RS_PENDING)
 					break;
 			}
 		}
 		if (rq->req_stat == RS_SUCCESS
 		    || ((rq->flags & RF_FAILURE_OK)
 			&& rq->req_stat != RS_TIMEOUT))
 			continue;
 		esas2r_log(ESAS2R_LOG_CRIT, "init message %x failed (%x, %x)",
 			   a->init_msg, rq->req_stat, rq->flags);
 		a->init_msg = ESAS2R_INIT_MSG_START;
 		success = false;
 		break;
 	}
 	esas2r_rq_destroy_request(rq, a);
 	return success;
 }
 /* Initialize the adapter chip */
 bool esas2r_init_adapter_hw(struct esas2r_adapter *a, bool init_poll)
 {
 	bool rslt = false;
 	struct esas2r_request *rq;
 	u32 i;
 	if (test_bit(AF_DEGRADED_MODE, &a->flags))
 		goto exit;
 	if (!test_bit(AF_NVR_VALID, &a->flags)) {
 		if (!esas2r_nvram_read_direct(a))
 			esas2r_log(ESAS2R_LOG_WARN,
 				   "invalid/missing NVRAM parameters");
 	}
 	if (!esas2r_init_msgs(a)) {
 		esas2r_set_degraded_mode(a, "init messages failed");
 		goto exit;
 	}
 	/* The firmware is ready. */
 	clear_bit(AF_DEGRADED_MODE, &a->flags);
 	clear_bit(AF_CHPRST_PENDING, &a->flags);
 	/* Post all the async event requests */
 	for (i = 0, rq = a->first_ae_req; i < num_ae_requests; i++, rq++)
 		esas2r_start_ae_request(a, rq);
 	if (!a->flash_rev[0])
 		esas2r_read_flash_rev(a);
 	if (!a->image_type[0])
 		esas2r_read_image_type(a);
 	if (a->fw_version == 0)
 		a->fw_rev[0] = 0;
 	else
 		sprintf(a->fw_rev, "%1d.%02d",
 			(int)LOBYTE(HIWORD(a->fw_version)),
 			(int)HIBYTE(HIWORD(a->fw_version)));
 	esas2r_hdebug("firmware revision: %s", a->fw_rev);
 	if (test_bit(AF_CHPRST_DETECTED, &a->flags)
 	    && (test_bit(AF_FIRST_INIT, &a->flags))) {
 		esas2r_enable_chip_interrupts(a);
 		return true;
 	}
 	/* initialize discovery */
 	esas2r_disc_initialize(a);
 	/*
 	 * wait for the device wait time to expire here if requested.  this is
 	 * usually requested during initial driver load and possibly when
 	 * resuming from a low power state.  deferred device waiting will use
 	 * interrupts.  chip reset recovery always defers device waiting to
 	 * avoid being in a TASKLET too long.
 	 */
 	if (init_poll) {
 		u32 currtime = a->disc_start_time;
 		u32 nexttick = 100;
 		u32 deltatime;
 		/*
 		 * Block Tasklets from getting scheduled and indicate this is
 		 * polled discovery.
 		 */
 		set_bit(AF_TASKLET_SCHEDULED, &a->flags);
 		set_bit(AF_DISC_POLLED, &a->flags);
 		/*
 		 * Temporarily bring the disable count to zero to enable
 		 * deferred processing.  Note that the count is already zero
 		 * after the first initialization.
 		 */
 		if (test_bit(AF_FIRST_INIT, &a->flags))
 			atomic_dec(&a->disable_cnt);
 		while (test_bit(AF_DISC_PENDING, &a->flags)) {
 			schedule_timeout_interruptible(msecs_to_jiffies(100));
 			/*
 			 * Determine the need for a timer tick based on the
 			 * delta time between this and the last iteration of
 			 * this loop.  We don't use the absolute time because
 			 * then we would have to worry about when nexttick
 			 * wraps and currtime hasn't yet.
 			 */
 			deltatime = jiffies_to_msecs(jiffies) - currtime;
 			currtime += deltatime;
 			/*
 			 * Process any waiting discovery as long as the chip is
 			 * up.  If a chip reset happens during initial polling,
 			 * we have to make sure the timer tick processes the
 			 * doorbell indicating the firmware is ready.
 			 */
 			if (!test_bit(AF_CHPRST_PENDING, &a->flags))
 				esas2r_disc_check_for_work(a);
 			/* Simulate a timer tick. */
 			if (nexttick <= deltatime) {
 				/* Time for a timer tick */
 				nexttick += 100;
 				esas2r_timer_tick(a);
 			}
 			if (nexttick > deltatime)
 				nexttick -= deltatime;
 			/* Do any deferred processing */
 			if (esas2r_is_tasklet_pending(a))
 				esas2r_do_tasklet_tasks(a);
 		}
 		if (test_bit(AF_FIRST_INIT, &a->flags))
 			atomic_inc(&a->disable_cnt);
 		clear_bit(AF_DISC_POLLED, &a->flags);
 		clear_bit(AF_TASKLET_SCHEDULED, &a->flags);
 	}
 	esas2r_targ_db_report_changes(a);
 	/*
 	 * For cases where (a) the initialization messages processing may
 	 * handle an interrupt for a port event and a discovery is waiting, but
 	 * we are not waiting for devices, or (b) the device wait time has been
 	 * exhausted but there is still discovery pending, start any leftover
 	 * discovery in interrupt driven mode.
 	 */
 	esas2r_disc_start_waiting(a);
 	/* Enable chip interrupts */
 	a->int_mask = ESAS2R_INT_STS_MASK;
 	esas2r_enable_chip_interrupts(a);
 	esas2r_enable_heartbeat(a);
 	rslt = true;
 exit:
 	/*
 	 * Regardless of whether initialization was successful, certain things
 	 * need to get done before we exit.
 	 */
 	if (test_bit(AF_CHPRST_DETECTED, &a->flags) &&
 	    test_bit(AF_FIRST_INIT, &a->flags)) {
 		/*
 		 * Reinitialization was performed during the first
 		 * initialization.  Only clear the chip reset flag so the
 		 * original device polling is not cancelled.
 		 */
 		if (!rslt)
 			clear_bit(AF_CHPRST_PENDING, &a->flags);
 	} else {
 		/* First initialization or a subsequent re-init is complete. */
 		if (!rslt) {
 			clear_bit(AF_CHPRST_PENDING, &a->flags);
 			clear_bit(AF_DISC_PENDING, &a->flags);
 		}
 		/* Enable deferred processing after the first initialization. */
 		if (test_bit(AF_FIRST_INIT, &a->flags)) {
 			clear_bit(AF_FIRST_INIT, &a->flags);
 			if (atomic_dec_return(&a->disable_cnt) == 0)
 				esas2r_do_deferred_processes(a);
 		}
 	}
 	return rslt;
 }
 void esas2r_reset_adapter(struct esas2r_adapter *a)
 {
 	set_bit(AF_OS_RESET, &a->flags);
 	esas2r_local_reset_adapter(a);
 	esas2r_schedule_tasklet(a);
 }
 void esas2r_reset_chip(struct esas2r_adapter *a)
 {
 	if (!esas2r_is_adapter_present(a))
 		return;
 	/*
 	 * Before we reset the chip, save off the VDA core dump.  The VDA core
 	 * dump is located in the upper 512KB of the onchip SRAM.  Make sure
 	 * to not overwrite a previous crash that was saved.
 	 */
 	if (test_bit(AF2_COREDUMP_AVAIL, &a->flags2) &&
 	    !test_bit(AF2_COREDUMP_SAVED, &a->flags2)) {
 		esas2r_read_mem_block(a,
 				      a->fw_coredump_buff,
 				      MW_DATA_ADDR_SRAM + 0x80000,
 				      ESAS2R_FWCOREDUMP_SZ);
 		set_bit(AF2_COREDUMP_SAVED, &a->flags2);
 	}
 	clear_bit(AF2_COREDUMP_AVAIL, &a->flags2);
 	/* Reset the chip */
 	if (a->pcid->revision == MVR_FREY_B2)
 		esas2r_write_register_dword(a, MU_CTL_STATUS_IN_B2,
 					    MU_CTL_IN_FULL_RST2);
 	else
 		esas2r_write_register_dword(a, MU_CTL_STATUS_IN,
 					    MU_CTL_IN_FULL_RST);
 	/* Stall a little while to let the reset condition clear */
 	mdelay(10);
 }
 static void esas2r_power_down_notify_firmware(struct esas2r_adapter *a)
 {
 	u32 starttime;
 	u32 doorbell;
 	esas2r_write_register_dword(a, MU_DOORBELL_IN, DRBL_POWER_DOWN);
 	starttime = jiffies_to_msecs(jiffies);
 	while (true) {
 		doorbell = esas2r_read_register_dword(a, MU_DOORBELL_OUT);
 		if (doorbell & DRBL_POWER_DOWN) {
 			esas2r_write_register_dword(a, MU_DOORBELL_OUT,
 						    doorbell);
 			break;
 		}
 		schedule_timeout_interruptible(msecs_to_jiffies(100));
 		if ((jiffies_to_msecs(jiffies) - starttime) > 30000) {
 			esas2r_hdebug("Timeout waiting for power down");
 			break;
 		}
 	}
 }
 /*
  * Perform power management processing including managing device states, adapter
  * states, interrupts, and I/O.
  */
 void esas2r_power_down(struct esas2r_adapter *a)
 {
 	set_bit(AF_POWER_MGT, &a->flags);
 	set_bit(AF_POWER_DOWN, &a->flags);
 	if (!test_bit(AF_DEGRADED_MODE, &a->flags)) {
 		u32 starttime;
 		u32 doorbell;
 		/*
 		 * We are currently running OK and will be reinitializing later.
 		 * increment the disable count to coordinate with
 		 * esas2r_init_adapter.  We don't have to do this in degraded
 		 * mode since we never enabled interrupts in the first place.
 		 */
 		esas2r_disable_chip_interrupts(a);
 		esas2r_disable_heartbeat(a);
 		/* wait for any VDA activity to clear before continuing */
 		esas2r_write_register_dword(a, MU_DOORBELL_IN,
 					    DRBL_MSG_IFC_DOWN);
 		starttime = jiffies_to_msecs(jiffies);
 		while (true) {
 			doorbell =
 				esas2r_read_register_dword(a, MU_DOORBELL_OUT);
 			if (doorbell & DRBL_MSG_IFC_DOWN) {
 				esas2r_write_register_dword(a, MU_DOORBELL_OUT,
 							    doorbell);
 				break;
 			}
 			schedule_timeout_interruptible(msecs_to_jiffies(100));
 			if ((jiffies_to_msecs(jiffies) - starttime) > 3000) {
 				esas2r_hdebug(
 					"timeout waiting for interface down");
 				break;
 			}
 		}
 		/*
 		 * For versions of firmware that support it tell them the driver
 		 * is powering down.
 		 */
 		if (test_bit(AF2_VDA_POWER_DOWN, &a->flags2))
 			esas2r_power_down_notify_firmware(a);
 	}
 	/* Suspend I/O processing. */
 	set_bit(AF_OS_RESET, &a->flags);
 	set_bit(AF_DISC_PENDING, &a->flags);
 	set_bit(AF_CHPRST_PENDING, &a->flags);
 	esas2r_process_adapter_reset(a);
 	/* Remove devices now that I/O is cleaned up. */
 	a->prev_dev_cnt = esas2r_targ_db_get_tgt_cnt(a);
 	esas2r_targ_db_remove_all(a, false);
 }
 /*
  * Perform power management processing including managing device states, adapter
  * states, interrupts, and I/O.
  */
 bool esas2r_power_up(struct esas2r_adapter *a, bool init_poll)
 {
 	bool ret;
 	clear_bit(AF_POWER_DOWN, &a->flags);
 	esas2r_init_pci_cfg_space(a);
 	set_bit(AF_FIRST_INIT, &a->flags);
 	atomic_inc(&a->disable_cnt);
 	/* reinitialize the adapter */
 	ret = esas2r_check_adapter(a);
 	if (!esas2r_init_adapter_hw(a, init_poll))
 		ret = false;
 	/* send the reset asynchronous event */
 	esas2r_send_reset_ae(a, true);
 	/* clear this flag after initialization. */
 	clear_bit(AF_POWER_MGT, &a->flags);
 	return ret;
 }
 bool esas2r_is_adapter_present(struct esas2r_adapter *a)
 {
 	if (test_bit(AF_NOT_PRESENT, &a->flags))
 		return false;
 	if (esas2r_read_register_dword(a, MU_DOORBELL_OUT) == 0xFFFFFFFF) {
 		set_bit(AF_NOT_PRESENT, &a->flags);
 		return false;
 	}
 	return true;
 }
 const char *esas2r_get_model_name(struct esas2r_adapter *a)
 {
 	switch (a->pcid->subsystem_device) {
 	case ATTO_ESAS_R680:
 		return "ATTO ExpressSAS R680";
 	case ATTO_ESAS_R608:
 		return "ATTO ExpressSAS R608";
 	case ATTO_ESAS_R60F:
 		return "ATTO ExpressSAS R60F";
 	case ATTO_ESAS_R6F0:
 		return "ATTO ExpressSAS R6F0";
 	case ATTO_ESAS_R644:
 		return "ATTO ExpressSAS R644";
 	case ATTO_ESAS_R648:
 		return "ATTO ExpressSAS R648";
 	case ATTO_TSSC_3808:
 		return "ATTO ThunderStream SC 3808D";
 	case ATTO_TSSC_3808E:
 		return "ATTO ThunderStream SC 3808E";
 	case ATTO_TLSH_1068:
 		return "ATTO ThunderLink SH 1068";
 	}
 	return "ATTO SAS Controller";
 }
 const char *esas2r_get_model_name_short(struct esas2r_adapter *a)
 {
 	switch (a->pcid->subsystem_device) {
 	case ATTO_ESAS_R680:
 		return "R680";
 	case ATTO_ESAS_R608:
 		return "R608";
 	case ATTO_ESAS_R60F:
 		return "R60F";
 	case ATTO_ESAS_R6F0:
 		return "R6F0";
 	case ATTO_ESAS_R644:
 		return "R644";
 	case ATTO_ESAS_R648:
 		return "R648";
 	case ATTO_TSSC_3808:
 		return "SC 3808D";
 	case ATTO_TSSC_3808E:
 		return "SC 3808E";
 	case ATTO_TLSH_1068:
 		return "SH 1068";
 	}
 	return "unknown";
 }