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Commit 8ec136d0f3d6376ce347255fb3d29708f28cc00a

Authored by Wolfram Sang
Committed by Linus Walleij
1 parent 4fdf774fc9
Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch imx_3.14.28_1.0.0_ga

drivers/pinctrl/spear: don't check resource with devm_ioremap_resource 

devm_ioremap_resource does sanity checks on the given resource. No need to
duplicate this in the driver.

Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Showing 1 changed file with 1 additions and 6 deletions Inline Diff

drivers/pinctrl/spear/pinctrl-plgpio.c
Diff comments   View file @ 8ec136d
1 /* 1 /*
2 * SPEAr platform PLGPIO driver 2 * SPEAr platform PLGPIO driver
3 * 3 *
4 * Copyright (C) 2012 ST Microelectronics 4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@linaro.org> 5 * Viresh Kumar <viresh.kumar@linaro.org>
6 * 6 *
7 * This file is licensed under the terms of the GNU General Public 7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any 8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied. 9 * warranty of any kind, whether express or implied.
10 */ 10 */
11 11
12 #include <linux/clk.h> 12 #include <linux/clk.h>
13 #include <linux/err.h> 13 #include <linux/err.h>
14 #include <linux/gpio.h> 14 #include <linux/gpio.h>
15 #include <linux/io.h> 15 #include <linux/io.h>
16 #include <linux/irq.h> 16 #include <linux/irq.h>
17 #include <linux/irqdomain.h> 17 #include <linux/irqdomain.h>
18 #include <linux/irqchip/chained_irq.h> 18 #include <linux/irqchip/chained_irq.h>
19 #include <linux/module.h> 19 #include <linux/module.h>
20 #include <linux/pinctrl/consumer.h> 20 #include <linux/pinctrl/consumer.h>
21 #include <linux/platform_device.h> 21 #include <linux/platform_device.h>
22 #include <linux/pm.h> 22 #include <linux/pm.h>
23 #include <linux/spinlock.h> 23 #include <linux/spinlock.h>
24 24
25 #define MAX_GPIO_PER_REG 32 25 #define MAX_GPIO_PER_REG 32
26 #define PIN_OFFSET(pin) (pin % MAX_GPIO_PER_REG) 26 #define PIN_OFFSET(pin) (pin % MAX_GPIO_PER_REG)
27 #define REG_OFFSET(base, reg, pin) (base + reg + (pin / MAX_GPIO_PER_REG) \ 27 #define REG_OFFSET(base, reg, pin) (base + reg + (pin / MAX_GPIO_PER_REG) \
28 * sizeof(int *)) 28 * sizeof(int *))
29 29
30 /* 30 /*
31 * plgpio pins in all machines are not one to one mapped, bitwise with registers 31 * plgpio pins in all machines are not one to one mapped, bitwise with registers
32 * bits. These set of macros define register masks for which below functions 32 * bits. These set of macros define register masks for which below functions
33 * (pin_to_offset and offset_to_pin) are required to be called. 33 * (pin_to_offset and offset_to_pin) are required to be called.
34 */ 34 */
35 #define PTO_ENB_REG 0x001 35 #define PTO_ENB_REG 0x001
36 #define PTO_WDATA_REG 0x002 36 #define PTO_WDATA_REG 0x002
37 #define PTO_DIR_REG 0x004 37 #define PTO_DIR_REG 0x004
38 #define PTO_IE_REG 0x008 38 #define PTO_IE_REG 0x008
39 #define PTO_RDATA_REG 0x010 39 #define PTO_RDATA_REG 0x010
40 #define PTO_MIS_REG 0x020 40 #define PTO_MIS_REG 0x020
41 41
42 struct plgpio_regs { 42 struct plgpio_regs {
43 u32 enb; /* enable register */ 43 u32 enb; /* enable register */
44 u32 wdata; /* write data register */ 44 u32 wdata; /* write data register */
45 u32 dir; /* direction set register */ 45 u32 dir; /* direction set register */
46 u32 rdata; /* read data register */ 46 u32 rdata; /* read data register */
47 u32 ie; /* interrupt enable register */ 47 u32 ie; /* interrupt enable register */
48 u32 mis; /* mask interrupt status register */ 48 u32 mis; /* mask interrupt status register */
49 u32 eit; /* edge interrupt type */ 49 u32 eit; /* edge interrupt type */
50 }; 50 };
51 51
52 /* 52 /*
53 * struct plgpio: plgpio driver specific structure 53 * struct plgpio: plgpio driver specific structure
54 * 54 *
55 * lock: lock for guarding gpio registers 55 * lock: lock for guarding gpio registers
56 * base: base address of plgpio block 56 * base: base address of plgpio block
57 * irq_base: irq number of plgpio0 57 * irq_base: irq number of plgpio0
58 * chip: gpio framework specific chip information structure 58 * chip: gpio framework specific chip information structure
59 * p2o: function ptr for pin to offset conversion. This is required only for 59 * p2o: function ptr for pin to offset conversion. This is required only for
60 * machines where mapping b/w pin and offset is not 1-to-1. 60 * machines where mapping b/w pin and offset is not 1-to-1.
61 * o2p: function ptr for offset to pin conversion. This is required only for 61 * o2p: function ptr for offset to pin conversion. This is required only for
62 * machines where mapping b/w pin and offset is not 1-to-1. 62 * machines where mapping b/w pin and offset is not 1-to-1.
63 * p2o_regs: mask of registers for which p2o and o2p are applicable 63 * p2o_regs: mask of registers for which p2o and o2p are applicable
64 * regs: register offsets 64 * regs: register offsets
65 * csave_regs: context save registers for standby/sleep/hibernate cases 65 * csave_regs: context save registers for standby/sleep/hibernate cases
66 */ 66 */
67 struct plgpio { 67 struct plgpio {
68 spinlock_t lock; 68 spinlock_t lock;
69 void __iomem *base; 69 void __iomem *base;
70 struct clk *clk; 70 struct clk *clk;
71 unsigned irq_base; 71 unsigned irq_base;
72 struct irq_domain *irq_domain; 72 struct irq_domain *irq_domain;
73 struct gpio_chip chip; 73 struct gpio_chip chip;
74 int (*p2o)(int pin); /* pin_to_offset */ 74 int (*p2o)(int pin); /* pin_to_offset */
75 int (*o2p)(int offset); /* offset_to_pin */ 75 int (*o2p)(int offset); /* offset_to_pin */
76 u32 p2o_regs; 76 u32 p2o_regs;
77 struct plgpio_regs regs; 77 struct plgpio_regs regs;
78 #ifdef CONFIG_PM_SLEEP 78 #ifdef CONFIG_PM_SLEEP
79 struct plgpio_regs *csave_regs; 79 struct plgpio_regs *csave_regs;
80 #endif 80 #endif
81 }; 81 };
82 82
83 /* register manipulation inline functions */ 83 /* register manipulation inline functions */
84 static inline u32 is_plgpio_set(void __iomem *base, u32 pin, u32 reg) 84 static inline u32 is_plgpio_set(void __iomem *base, u32 pin, u32 reg)
85 { 85 {
86 u32 offset = PIN_OFFSET(pin); 86 u32 offset = PIN_OFFSET(pin);
87 void __iomem *reg_off = REG_OFFSET(base, reg, pin); 87 void __iomem *reg_off = REG_OFFSET(base, reg, pin);
88 u32 val = readl_relaxed(reg_off); 88 u32 val = readl_relaxed(reg_off);
89 89
90 return !!(val & (1 << offset)); 90 return !!(val & (1 << offset));
91 } 91 }
92 92
93 static inline void plgpio_reg_set(void __iomem *base, u32 pin, u32 reg) 93 static inline void plgpio_reg_set(void __iomem *base, u32 pin, u32 reg)
94 { 94 {
95 u32 offset = PIN_OFFSET(pin); 95 u32 offset = PIN_OFFSET(pin);
96 void __iomem *reg_off = REG_OFFSET(base, reg, pin); 96 void __iomem *reg_off = REG_OFFSET(base, reg, pin);
97 u32 val = readl_relaxed(reg_off); 97 u32 val = readl_relaxed(reg_off);
98 98
99 writel_relaxed(val | (1 << offset), reg_off); 99 writel_relaxed(val | (1 << offset), reg_off);
100 } 100 }
101 101
102 static inline void plgpio_reg_reset(void __iomem *base, u32 pin, u32 reg) 102 static inline void plgpio_reg_reset(void __iomem *base, u32 pin, u32 reg)
103 { 103 {
104 u32 offset = PIN_OFFSET(pin); 104 u32 offset = PIN_OFFSET(pin);
105 void __iomem *reg_off = REG_OFFSET(base, reg, pin); 105 void __iomem *reg_off = REG_OFFSET(base, reg, pin);
106 u32 val = readl_relaxed(reg_off); 106 u32 val = readl_relaxed(reg_off);
107 107
108 writel_relaxed(val & ~(1 << offset), reg_off); 108 writel_relaxed(val & ~(1 << offset), reg_off);
109 } 109 }
110 110
111 /* gpio framework specific routines */ 111 /* gpio framework specific routines */
112 static int plgpio_direction_input(struct gpio_chip *chip, unsigned offset) 112 static int plgpio_direction_input(struct gpio_chip *chip, unsigned offset)
113 { 113 {
114 struct plgpio *plgpio = container_of(chip, struct plgpio, chip); 114 struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
115 unsigned long flags; 115 unsigned long flags;
116 116
117 /* get correct offset for "offset" pin */ 117 /* get correct offset for "offset" pin */
118 if (plgpio->p2o && (plgpio->p2o_regs & PTO_DIR_REG)) { 118 if (plgpio->p2o && (plgpio->p2o_regs & PTO_DIR_REG)) {
119 offset = plgpio->p2o(offset); 119 offset = plgpio->p2o(offset);
120 if (offset == -1) 120 if (offset == -1)
121 return -EINVAL; 121 return -EINVAL;
122 } 122 }
123 123
124 spin_lock_irqsave(&plgpio->lock, flags); 124 spin_lock_irqsave(&plgpio->lock, flags);
125 plgpio_reg_set(plgpio->base, offset, plgpio->regs.dir); 125 plgpio_reg_set(plgpio->base, offset, plgpio->regs.dir);
126 spin_unlock_irqrestore(&plgpio->lock, flags); 126 spin_unlock_irqrestore(&plgpio->lock, flags);
127 127
128 return 0; 128 return 0;
129 } 129 }
130 130
131 static int plgpio_direction_output(struct gpio_chip *chip, unsigned offset, 131 static int plgpio_direction_output(struct gpio_chip *chip, unsigned offset,
132 int value) 132 int value)
133 { 133 {
134 struct plgpio *plgpio = container_of(chip, struct plgpio, chip); 134 struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
135 unsigned long flags; 135 unsigned long flags;
136 unsigned dir_offset = offset, wdata_offset = offset, tmp; 136 unsigned dir_offset = offset, wdata_offset = offset, tmp;
137 137
138 /* get correct offset for "offset" pin */ 138 /* get correct offset for "offset" pin */
139 if (plgpio->p2o && (plgpio->p2o_regs & (PTO_DIR_REG | PTO_WDATA_REG))) { 139 if (plgpio->p2o && (plgpio->p2o_regs & (PTO_DIR_REG | PTO_WDATA_REG))) {
140 tmp = plgpio->p2o(offset); 140 tmp = plgpio->p2o(offset);
141 if (tmp == -1) 141 if (tmp == -1)
142 return -EINVAL; 142 return -EINVAL;
143 143
144 if (plgpio->p2o_regs & PTO_DIR_REG) 144 if (plgpio->p2o_regs & PTO_DIR_REG)
145 dir_offset = tmp; 145 dir_offset = tmp;
146 if (plgpio->p2o_regs & PTO_WDATA_REG) 146 if (plgpio->p2o_regs & PTO_WDATA_REG)
147 wdata_offset = tmp; 147 wdata_offset = tmp;
148 } 148 }
149 149
150 spin_lock_irqsave(&plgpio->lock, flags); 150 spin_lock_irqsave(&plgpio->lock, flags);
151 if (value) 151 if (value)
152 plgpio_reg_set(plgpio->base, wdata_offset, 152 plgpio_reg_set(plgpio->base, wdata_offset,
153 plgpio->regs.wdata); 153 plgpio->regs.wdata);
154 else 154 else
155 plgpio_reg_reset(plgpio->base, wdata_offset, 155 plgpio_reg_reset(plgpio->base, wdata_offset,
156 plgpio->regs.wdata); 156 plgpio->regs.wdata);
157 157
158 plgpio_reg_reset(plgpio->base, dir_offset, plgpio->regs.dir); 158 plgpio_reg_reset(plgpio->base, dir_offset, plgpio->regs.dir);
159 spin_unlock_irqrestore(&plgpio->lock, flags); 159 spin_unlock_irqrestore(&plgpio->lock, flags);
160 160
161 return 0; 161 return 0;
162 } 162 }
163 163
164 static int plgpio_get_value(struct gpio_chip *chip, unsigned offset) 164 static int plgpio_get_value(struct gpio_chip *chip, unsigned offset)
165 { 165 {
166 struct plgpio *plgpio = container_of(chip, struct plgpio, chip); 166 struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
167 167
168 if (offset >= chip->ngpio) 168 if (offset >= chip->ngpio)
169 return -EINVAL; 169 return -EINVAL;
170 170
171 /* get correct offset for "offset" pin */ 171 /* get correct offset for "offset" pin */
172 if (plgpio->p2o && (plgpio->p2o_regs & PTO_RDATA_REG)) { 172 if (plgpio->p2o && (plgpio->p2o_regs & PTO_RDATA_REG)) {
173 offset = plgpio->p2o(offset); 173 offset = plgpio->p2o(offset);
174 if (offset == -1) 174 if (offset == -1)
175 return -EINVAL; 175 return -EINVAL;
176 } 176 }
177 177
178 return is_plgpio_set(plgpio->base, offset, plgpio->regs.rdata); 178 return is_plgpio_set(plgpio->base, offset, plgpio->regs.rdata);
179 } 179 }
180 180
181 static void plgpio_set_value(struct gpio_chip *chip, unsigned offset, int value) 181 static void plgpio_set_value(struct gpio_chip *chip, unsigned offset, int value)
182 { 182 {
183 struct plgpio *plgpio = container_of(chip, struct plgpio, chip); 183 struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
184 184
185 if (offset >= chip->ngpio) 185 if (offset >= chip->ngpio)
186 return; 186 return;
187 187
188 /* get correct offset for "offset" pin */ 188 /* get correct offset for "offset" pin */
189 if (plgpio->p2o && (plgpio->p2o_regs & PTO_WDATA_REG)) { 189 if (plgpio->p2o && (plgpio->p2o_regs & PTO_WDATA_REG)) {
190 offset = plgpio->p2o(offset); 190 offset = plgpio->p2o(offset);
191 if (offset == -1) 191 if (offset == -1)
192 return; 192 return;
193 } 193 }
194 194
195 if (value) 195 if (value)
196 plgpio_reg_set(plgpio->base, offset, plgpio->regs.wdata); 196 plgpio_reg_set(plgpio->base, offset, plgpio->regs.wdata);
197 else 197 else
198 plgpio_reg_reset(plgpio->base, offset, plgpio->regs.wdata); 198 plgpio_reg_reset(plgpio->base, offset, plgpio->regs.wdata);
199 } 199 }
200 200
201 static int plgpio_request(struct gpio_chip *chip, unsigned offset) 201 static int plgpio_request(struct gpio_chip *chip, unsigned offset)
202 { 202 {
203 struct plgpio *plgpio = container_of(chip, struct plgpio, chip); 203 struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
204 int gpio = chip->base + offset; 204 int gpio = chip->base + offset;
205 unsigned long flags; 205 unsigned long flags;
206 int ret = 0; 206 int ret = 0;
207 207
208 if (offset >= chip->ngpio) 208 if (offset >= chip->ngpio)
209 return -EINVAL; 209 return -EINVAL;
210 210
211 ret = pinctrl_request_gpio(gpio); 211 ret = pinctrl_request_gpio(gpio);
212 if (ret) 212 if (ret)
213 return ret; 213 return ret;
214 214
215 if (!IS_ERR(plgpio->clk)) { 215 if (!IS_ERR(plgpio->clk)) {
216 ret = clk_enable(plgpio->clk); 216 ret = clk_enable(plgpio->clk);
217 if (ret) 217 if (ret)
218 goto err0; 218 goto err0;
219 } 219 }
220 220
221 if (plgpio->regs.enb == -1) 221 if (plgpio->regs.enb == -1)
222 return 0; 222 return 0;
223 223
224 /* 224 /*
225 * put gpio in IN mode before enabling it. This make enabling gpio safe 225 * put gpio in IN mode before enabling it. This make enabling gpio safe
226 */ 226 */
227 ret = plgpio_direction_input(chip, offset); 227 ret = plgpio_direction_input(chip, offset);
228 if (ret) 228 if (ret)
229 goto err1; 229 goto err1;
230 230
231 /* get correct offset for "offset" pin */ 231 /* get correct offset for "offset" pin */
232 if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) { 232 if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) {
233 offset = plgpio->p2o(offset); 233 offset = plgpio->p2o(offset);
234 if (offset == -1) { 234 if (offset == -1) {
235 ret = -EINVAL; 235 ret = -EINVAL;
236 goto err1; 236 goto err1;
237 } 237 }
238 } 238 }
239 239
240 spin_lock_irqsave(&plgpio->lock, flags); 240 spin_lock_irqsave(&plgpio->lock, flags);
241 plgpio_reg_set(plgpio->base, offset, plgpio->regs.enb); 241 plgpio_reg_set(plgpio->base, offset, plgpio->regs.enb);
242 spin_unlock_irqrestore(&plgpio->lock, flags); 242 spin_unlock_irqrestore(&plgpio->lock, flags);
243 return 0; 243 return 0;
244 244
245 err1: 245 err1:
246 if (!IS_ERR(plgpio->clk)) 246 if (!IS_ERR(plgpio->clk))
247 clk_disable(plgpio->clk); 247 clk_disable(plgpio->clk);
248 err0: 248 err0:
249 pinctrl_free_gpio(gpio); 249 pinctrl_free_gpio(gpio);
250 return ret; 250 return ret;
251 } 251 }
252 252
253 static void plgpio_free(struct gpio_chip *chip, unsigned offset) 253 static void plgpio_free(struct gpio_chip *chip, unsigned offset)
254 { 254 {
255 struct plgpio *plgpio = container_of(chip, struct plgpio, chip); 255 struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
256 int gpio = chip->base + offset; 256 int gpio = chip->base + offset;
257 unsigned long flags; 257 unsigned long flags;
258 258
259 if (offset >= chip->ngpio) 259 if (offset >= chip->ngpio)
260 return; 260 return;
261 261
262 if (plgpio->regs.enb == -1) 262 if (plgpio->regs.enb == -1)
263 goto disable_clk; 263 goto disable_clk;
264 264
265 /* get correct offset for "offset" pin */ 265 /* get correct offset for "offset" pin */
266 if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) { 266 if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) {
267 offset = plgpio->p2o(offset); 267 offset = plgpio->p2o(offset);
268 if (offset == -1) 268 if (offset == -1)
269 return; 269 return;
270 } 270 }
271 271
272 spin_lock_irqsave(&plgpio->lock, flags); 272 spin_lock_irqsave(&plgpio->lock, flags);
273 plgpio_reg_reset(plgpio->base, offset, plgpio->regs.enb); 273 plgpio_reg_reset(plgpio->base, offset, plgpio->regs.enb);
274 spin_unlock_irqrestore(&plgpio->lock, flags); 274 spin_unlock_irqrestore(&plgpio->lock, flags);
275 275
276 disable_clk: 276 disable_clk:
277 if (!IS_ERR(plgpio->clk)) 277 if (!IS_ERR(plgpio->clk))
278 clk_disable(plgpio->clk); 278 clk_disable(plgpio->clk);
279 279
280 pinctrl_free_gpio(gpio); 280 pinctrl_free_gpio(gpio);
281 } 281 }
282 282
283 static int plgpio_to_irq(struct gpio_chip *chip, unsigned offset) 283 static int plgpio_to_irq(struct gpio_chip *chip, unsigned offset)
284 { 284 {
285 struct plgpio *plgpio = container_of(chip, struct plgpio, chip); 285 struct plgpio *plgpio = container_of(chip, struct plgpio, chip);
286 286
287 if (IS_ERR_VALUE(plgpio->irq_base)) 287 if (IS_ERR_VALUE(plgpio->irq_base))
288 return -EINVAL; 288 return -EINVAL;
289 289
290 return irq_find_mapping(plgpio->irq_domain, offset); 290 return irq_find_mapping(plgpio->irq_domain, offset);
291 } 291 }
292 292
293 /* PLGPIO IRQ */ 293 /* PLGPIO IRQ */
294 static void plgpio_irq_disable(struct irq_data *d) 294 static void plgpio_irq_disable(struct irq_data *d)
295 { 295 {
296 struct plgpio *plgpio = irq_data_get_irq_chip_data(d); 296 struct plgpio *plgpio = irq_data_get_irq_chip_data(d);
297 int offset = d->irq - plgpio->irq_base; 297 int offset = d->irq - plgpio->irq_base;
298 unsigned long flags; 298 unsigned long flags;
299 299
300 /* get correct offset for "offset" pin */ 300 /* get correct offset for "offset" pin */
301 if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) { 301 if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) {
302 offset = plgpio->p2o(offset); 302 offset = plgpio->p2o(offset);
303 if (offset == -1) 303 if (offset == -1)
304 return; 304 return;
305 } 305 }
306 306
307 spin_lock_irqsave(&plgpio->lock, flags); 307 spin_lock_irqsave(&plgpio->lock, flags);
308 plgpio_reg_set(plgpio->base, offset, plgpio->regs.ie); 308 plgpio_reg_set(plgpio->base, offset, plgpio->regs.ie);
309 spin_unlock_irqrestore(&plgpio->lock, flags); 309 spin_unlock_irqrestore(&plgpio->lock, flags);
310 } 310 }
311 311
312 static void plgpio_irq_enable(struct irq_data *d) 312 static void plgpio_irq_enable(struct irq_data *d)
313 { 313 {
314 struct plgpio *plgpio = irq_data_get_irq_chip_data(d); 314 struct plgpio *plgpio = irq_data_get_irq_chip_data(d);
315 int offset = d->irq - plgpio->irq_base; 315 int offset = d->irq - plgpio->irq_base;
316 unsigned long flags; 316 unsigned long flags;
317 317
318 /* get correct offset for "offset" pin */ 318 /* get correct offset for "offset" pin */
319 if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) { 319 if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) {
320 offset = plgpio->p2o(offset); 320 offset = plgpio->p2o(offset);
321 if (offset == -1) 321 if (offset == -1)
322 return; 322 return;
323 } 323 }
324 324
325 spin_lock_irqsave(&plgpio->lock, flags); 325 spin_lock_irqsave(&plgpio->lock, flags);
326 plgpio_reg_reset(plgpio->base, offset, plgpio->regs.ie); 326 plgpio_reg_reset(plgpio->base, offset, plgpio->regs.ie);
327 spin_unlock_irqrestore(&plgpio->lock, flags); 327 spin_unlock_irqrestore(&plgpio->lock, flags);
328 } 328 }
329 329
330 static int plgpio_irq_set_type(struct irq_data *d, unsigned trigger) 330 static int plgpio_irq_set_type(struct irq_data *d, unsigned trigger)
331 { 331 {
332 struct plgpio *plgpio = irq_data_get_irq_chip_data(d); 332 struct plgpio *plgpio = irq_data_get_irq_chip_data(d);
333 int offset = d->irq - plgpio->irq_base; 333 int offset = d->irq - plgpio->irq_base;
334 void __iomem *reg_off; 334 void __iomem *reg_off;
335 unsigned int supported_type = 0, val; 335 unsigned int supported_type = 0, val;
336 336
337 if (offset >= plgpio->chip.ngpio) 337 if (offset >= plgpio->chip.ngpio)
338 return -EINVAL; 338 return -EINVAL;
339 339
340 if (plgpio->regs.eit == -1) 340 if (plgpio->regs.eit == -1)
341 supported_type = IRQ_TYPE_LEVEL_HIGH; 341 supported_type = IRQ_TYPE_LEVEL_HIGH;
342 else 342 else
343 supported_type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 343 supported_type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
344 344
345 if (!(trigger & supported_type)) 345 if (!(trigger & supported_type))
346 return -EINVAL; 346 return -EINVAL;
347 347
348 if (plgpio->regs.eit == -1) 348 if (plgpio->regs.eit == -1)
349 return 0; 349 return 0;
350 350
351 reg_off = REG_OFFSET(plgpio->base, plgpio->regs.eit, offset); 351 reg_off = REG_OFFSET(plgpio->base, plgpio->regs.eit, offset);
352 val = readl_relaxed(reg_off); 352 val = readl_relaxed(reg_off);
353 353
354 offset = PIN_OFFSET(offset); 354 offset = PIN_OFFSET(offset);
355 if (trigger & IRQ_TYPE_EDGE_RISING) 355 if (trigger & IRQ_TYPE_EDGE_RISING)
356 writel_relaxed(val | (1 << offset), reg_off); 356 writel_relaxed(val | (1 << offset), reg_off);
357 else 357 else
358 writel_relaxed(val & ~(1 << offset), reg_off); 358 writel_relaxed(val & ~(1 << offset), reg_off);
359 359
360 return 0; 360 return 0;
361 } 361 }
362 362
363 static struct irq_chip plgpio_irqchip = { 363 static struct irq_chip plgpio_irqchip = {
364 .name = "PLGPIO", 364 .name = "PLGPIO",
365 .irq_enable = plgpio_irq_enable, 365 .irq_enable = plgpio_irq_enable,
366 .irq_disable = plgpio_irq_disable, 366 .irq_disable = plgpio_irq_disable,
367 .irq_set_type = plgpio_irq_set_type, 367 .irq_set_type = plgpio_irq_set_type,
368 }; 368 };
369 369
370 static void plgpio_irq_handler(unsigned irq, struct irq_desc *desc) 370 static void plgpio_irq_handler(unsigned irq, struct irq_desc *desc)
371 { 371 {
372 struct plgpio *plgpio = irq_get_handler_data(irq); 372 struct plgpio *plgpio = irq_get_handler_data(irq);
373 struct irq_chip *irqchip = irq_desc_get_chip(desc); 373 struct irq_chip *irqchip = irq_desc_get_chip(desc);
374 int regs_count, count, pin, offset, i = 0; 374 int regs_count, count, pin, offset, i = 0;
375 unsigned long pending; 375 unsigned long pending;
376 376
377 count = plgpio->chip.ngpio; 377 count = plgpio->chip.ngpio;
378 regs_count = DIV_ROUND_UP(count, MAX_GPIO_PER_REG); 378 regs_count = DIV_ROUND_UP(count, MAX_GPIO_PER_REG);
379 379
380 chained_irq_enter(irqchip, desc); 380 chained_irq_enter(irqchip, desc);
381 /* check all plgpio MIS registers for a possible interrupt */ 381 /* check all plgpio MIS registers for a possible interrupt */
382 for (; i < regs_count; i++) { 382 for (; i < regs_count; i++) {
383 pending = readl_relaxed(plgpio->base + plgpio->regs.mis + 383 pending = readl_relaxed(plgpio->base + plgpio->regs.mis +
384 i * sizeof(int *)); 384 i * sizeof(int *));
385 if (!pending) 385 if (!pending)
386 continue; 386 continue;
387 387
388 /* clear interrupts */ 388 /* clear interrupts */
389 writel_relaxed(~pending, plgpio->base + plgpio->regs.mis + 389 writel_relaxed(~pending, plgpio->base + plgpio->regs.mis +
390 i * sizeof(int *)); 390 i * sizeof(int *));
391 /* 391 /*
392 * clear extra bits in last register having gpios < MAX/REG 392 * clear extra bits in last register having gpios < MAX/REG
393 * ex: Suppose there are max 102 plgpios. then last register 393 * ex: Suppose there are max 102 plgpios. then last register
394 * must have only (102 - MAX_GPIO_PER_REG * 3) = 6 relevant bits 394 * must have only (102 - MAX_GPIO_PER_REG * 3) = 6 relevant bits
395 * so, we must not take other 28 bits into consideration for 395 * so, we must not take other 28 bits into consideration for
396 * checking interrupt. so clear those bits. 396 * checking interrupt. so clear those bits.
397 */ 397 */
398 count = count - i * MAX_GPIO_PER_REG; 398 count = count - i * MAX_GPIO_PER_REG;
399 if (count < MAX_GPIO_PER_REG) 399 if (count < MAX_GPIO_PER_REG)
400 pending &= (1 << count) - 1; 400 pending &= (1 << count) - 1;
401 401
402 for_each_set_bit(offset, &pending, MAX_GPIO_PER_REG) { 402 for_each_set_bit(offset, &pending, MAX_GPIO_PER_REG) {
403 /* get correct pin for "offset" */ 403 /* get correct pin for "offset" */
404 if (plgpio->o2p && (plgpio->p2o_regs & PTO_MIS_REG)) { 404 if (plgpio->o2p && (plgpio->p2o_regs & PTO_MIS_REG)) {
405 pin = plgpio->o2p(offset); 405 pin = plgpio->o2p(offset);
406 if (pin == -1) 406 if (pin == -1)
407 continue; 407 continue;
408 } else 408 } else
409 pin = offset; 409 pin = offset;
410 410
411 /* get correct irq line number */ 411 /* get correct irq line number */
412 pin = i * MAX_GPIO_PER_REG + pin; 412 pin = i * MAX_GPIO_PER_REG + pin;
413 generic_handle_irq(plgpio_to_irq(&plgpio->chip, pin)); 413 generic_handle_irq(plgpio_to_irq(&plgpio->chip, pin));
414 } 414 }
415 } 415 }
416 chained_irq_exit(irqchip, desc); 416 chained_irq_exit(irqchip, desc);
417 } 417 }
418 418
419 /* 419 /*
420 * pin to offset and offset to pin converter functions 420 * pin to offset and offset to pin converter functions
421 * 421 *
422 * In spear310 there is inconsistency among bit positions in plgpio regiseters, 422 * In spear310 there is inconsistency among bit positions in plgpio regiseters,
423 * for different plgpio pins. For example: for pin 27, bit offset is 23, pin 423 * for different plgpio pins. For example: for pin 27, bit offset is 23, pin
424 * 28-33 are not supported, pin 95 has offset bit 95, bit 100 has offset bit 1 424 * 28-33 are not supported, pin 95 has offset bit 95, bit 100 has offset bit 1
425 */ 425 */
426 static int spear310_p2o(int pin) 426 static int spear310_p2o(int pin)
427 { 427 {
428 int offset = pin; 428 int offset = pin;
429 429
430 if (pin <= 27) 430 if (pin <= 27)
431 offset += 4; 431 offset += 4;
432 else if (pin <= 33) 432 else if (pin <= 33)
433 offset = -1; 433 offset = -1;
434 else if (pin <= 97) 434 else if (pin <= 97)
435 offset -= 2; 435 offset -= 2;
436 else if (pin <= 101) 436 else if (pin <= 101)
437 offset = 101 - pin; 437 offset = 101 - pin;
438 else 438 else
439 offset = -1; 439 offset = -1;
440 440
441 return offset; 441 return offset;
442 } 442 }
443 443
444 int spear310_o2p(int offset) 444 int spear310_o2p(int offset)
445 { 445 {
446 if (offset <= 3) 446 if (offset <= 3)
447 return 101 - offset; 447 return 101 - offset;
448 else if (offset <= 31) 448 else if (offset <= 31)
449 return offset - 4; 449 return offset - 4;
450 else 450 else
451 return offset + 2; 451 return offset + 2;
452 } 452 }
453 453
454 static int plgpio_probe_dt(struct platform_device *pdev, struct plgpio *plgpio) 454 static int plgpio_probe_dt(struct platform_device *pdev, struct plgpio *plgpio)
455 { 455 {
456 struct device_node *np = pdev->dev.of_node; 456 struct device_node *np = pdev->dev.of_node;
457 int ret = -EINVAL; 457 int ret = -EINVAL;
458 u32 val; 458 u32 val;
459 459
460 if (of_machine_is_compatible("st,spear310")) { 460 if (of_machine_is_compatible("st,spear310")) {
461 plgpio->p2o = spear310_p2o; 461 plgpio->p2o = spear310_p2o;
462 plgpio->o2p = spear310_o2p; 462 plgpio->o2p = spear310_o2p;
463 plgpio->p2o_regs = PTO_WDATA_REG | PTO_DIR_REG | PTO_IE_REG | 463 plgpio->p2o_regs = PTO_WDATA_REG | PTO_DIR_REG | PTO_IE_REG |
464 PTO_RDATA_REG | PTO_MIS_REG; 464 PTO_RDATA_REG | PTO_MIS_REG;
465 } 465 }
466 466
467 if (!of_property_read_u32(np, "st-plgpio,ngpio", &val)) { 467 if (!of_property_read_u32(np, "st-plgpio,ngpio", &val)) {
468 plgpio->chip.ngpio = val; 468 plgpio->chip.ngpio = val;
469 } else { 469 } else {
470 dev_err(&pdev->dev, "DT: Invalid ngpio field\n"); 470 dev_err(&pdev->dev, "DT: Invalid ngpio field\n");
471 goto end; 471 goto end;
472 } 472 }
473 473
474 if (!of_property_read_u32(np, "st-plgpio,enb-reg", &val)) 474 if (!of_property_read_u32(np, "st-plgpio,enb-reg", &val))
475 plgpio->regs.enb = val; 475 plgpio->regs.enb = val;
476 else 476 else
477 plgpio->regs.enb = -1; 477 plgpio->regs.enb = -1;
478 478
479 if (!of_property_read_u32(np, "st-plgpio,wdata-reg", &val)) { 479 if (!of_property_read_u32(np, "st-plgpio,wdata-reg", &val)) {
480 plgpio->regs.wdata = val; 480 plgpio->regs.wdata = val;
481 } else { 481 } else {
482 dev_err(&pdev->dev, "DT: Invalid wdata reg\n"); 482 dev_err(&pdev->dev, "DT: Invalid wdata reg\n");
483 goto end; 483 goto end;
484 } 484 }
485 485
486 if (!of_property_read_u32(np, "st-plgpio,dir-reg", &val)) { 486 if (!of_property_read_u32(np, "st-plgpio,dir-reg", &val)) {
487 plgpio->regs.dir = val; 487 plgpio->regs.dir = val;
488 } else { 488 } else {
489 dev_err(&pdev->dev, "DT: Invalid dir reg\n"); 489 dev_err(&pdev->dev, "DT: Invalid dir reg\n");
490 goto end; 490 goto end;
491 } 491 }
492 492
493 if (!of_property_read_u32(np, "st-plgpio,ie-reg", &val)) { 493 if (!of_property_read_u32(np, "st-plgpio,ie-reg", &val)) {
494 plgpio->regs.ie = val; 494 plgpio->regs.ie = val;
495 } else { 495 } else {
496 dev_err(&pdev->dev, "DT: Invalid ie reg\n"); 496 dev_err(&pdev->dev, "DT: Invalid ie reg\n");
497 goto end; 497 goto end;
498 } 498 }
499 499
500 if (!of_property_read_u32(np, "st-plgpio,rdata-reg", &val)) { 500 if (!of_property_read_u32(np, "st-plgpio,rdata-reg", &val)) {
501 plgpio->regs.rdata = val; 501 plgpio->regs.rdata = val;
502 } else { 502 } else {
503 dev_err(&pdev->dev, "DT: Invalid rdata reg\n"); 503 dev_err(&pdev->dev, "DT: Invalid rdata reg\n");
504 goto end; 504 goto end;
505 } 505 }
506 506
507 if (!of_property_read_u32(np, "st-plgpio,mis-reg", &val)) { 507 if (!of_property_read_u32(np, "st-plgpio,mis-reg", &val)) {
508 plgpio->regs.mis = val; 508 plgpio->regs.mis = val;
509 } else { 509 } else {
510 dev_err(&pdev->dev, "DT: Invalid mis reg\n"); 510 dev_err(&pdev->dev, "DT: Invalid mis reg\n");
511 goto end; 511 goto end;
512 } 512 }
513 513
514 if (!of_property_read_u32(np, "st-plgpio,eit-reg", &val)) 514 if (!of_property_read_u32(np, "st-plgpio,eit-reg", &val))
515 plgpio->regs.eit = val; 515 plgpio->regs.eit = val;
516 else 516 else
517 plgpio->regs.eit = -1; 517 plgpio->regs.eit = -1;
518 518
519 return 0; 519 return 0;
520 520
521 end: 521 end:
522 return ret; 522 return ret;
523 } 523 }
524 static int plgpio_probe(struct platform_device *pdev) 524 static int plgpio_probe(struct platform_device *pdev)
525 { 525 {
526 struct device_node *np = pdev->dev.of_node; 526 struct device_node *np = pdev->dev.of_node;
527 struct plgpio *plgpio; 527 struct plgpio *plgpio;
528 struct resource *res; 528 struct resource *res;
529 int ret, irq, i; 529 int ret, irq, i;
530 530
531 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
532 if (!res) {
533 dev_err(&pdev->dev, "invalid IORESOURCE_MEM\n");
534 return -EBUSY;
535 }
536
537 plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL); 531 plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL);
538 if (!plgpio) { 532 if (!plgpio) {
539 dev_err(&pdev->dev, "memory allocation fail\n"); 533 dev_err(&pdev->dev, "memory allocation fail\n");
540 return -ENOMEM; 534 return -ENOMEM;
541 } 535 }
542 536
537 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
543 plgpio->base = devm_ioremap_resource(&pdev->dev, res); 538 plgpio->base = devm_ioremap_resource(&pdev->dev, res);
544 if (IS_ERR(plgpio->base)) 539 if (IS_ERR(plgpio->base))
545 return PTR_ERR(plgpio->base); 540 return PTR_ERR(plgpio->base);
546 541
547 ret = plgpio_probe_dt(pdev, plgpio); 542 ret = plgpio_probe_dt(pdev, plgpio);
548 if (ret) { 543 if (ret) {
549 dev_err(&pdev->dev, "DT probe failed\n"); 544 dev_err(&pdev->dev, "DT probe failed\n");
550 return ret; 545 return ret;
551 } 546 }
552 547
553 plgpio->clk = devm_clk_get(&pdev->dev, NULL); 548 plgpio->clk = devm_clk_get(&pdev->dev, NULL);
554 if (IS_ERR(plgpio->clk)) 549 if (IS_ERR(plgpio->clk))
555 dev_warn(&pdev->dev, "clk_get() failed, work without it\n"); 550 dev_warn(&pdev->dev, "clk_get() failed, work without it\n");
556 551
557 #ifdef CONFIG_PM_SLEEP 552 #ifdef CONFIG_PM_SLEEP
558 plgpio->csave_regs = devm_kzalloc(&pdev->dev, 553 plgpio->csave_regs = devm_kzalloc(&pdev->dev,
559 sizeof(*plgpio->csave_regs) * 554 sizeof(*plgpio->csave_regs) *
560 DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG), 555 DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG),
561 GFP_KERNEL); 556 GFP_KERNEL);
562 if (!plgpio->csave_regs) { 557 if (!plgpio->csave_regs) {
563 dev_err(&pdev->dev, "csave registers memory allocation fail\n"); 558 dev_err(&pdev->dev, "csave registers memory allocation fail\n");
564 return -ENOMEM; 559 return -ENOMEM;
565 } 560 }
566 #endif 561 #endif
567 562
568 platform_set_drvdata(pdev, plgpio); 563 platform_set_drvdata(pdev, plgpio);
569 spin_lock_init(&plgpio->lock); 564 spin_lock_init(&plgpio->lock);
570 565
571 plgpio->irq_base = -1; 566 plgpio->irq_base = -1;
572 plgpio->chip.base = -1; 567 plgpio->chip.base = -1;
573 plgpio->chip.request = plgpio_request; 568 plgpio->chip.request = plgpio_request;
574 plgpio->chip.free = plgpio_free; 569 plgpio->chip.free = plgpio_free;
575 plgpio->chip.direction_input = plgpio_direction_input; 570 plgpio->chip.direction_input = plgpio_direction_input;
576 plgpio->chip.direction_output = plgpio_direction_output; 571 plgpio->chip.direction_output = plgpio_direction_output;
577 plgpio->chip.get = plgpio_get_value; 572 plgpio->chip.get = plgpio_get_value;
578 plgpio->chip.set = plgpio_set_value; 573 plgpio->chip.set = plgpio_set_value;
579 plgpio->chip.to_irq = plgpio_to_irq; 574 plgpio->chip.to_irq = plgpio_to_irq;
580 plgpio->chip.label = dev_name(&pdev->dev); 575 plgpio->chip.label = dev_name(&pdev->dev);
581 plgpio->chip.dev = &pdev->dev; 576 plgpio->chip.dev = &pdev->dev;
582 plgpio->chip.owner = THIS_MODULE; 577 plgpio->chip.owner = THIS_MODULE;
583 578
584 if (!IS_ERR(plgpio->clk)) { 579 if (!IS_ERR(plgpio->clk)) {
585 ret = clk_prepare(plgpio->clk); 580 ret = clk_prepare(plgpio->clk);
586 if (ret) { 581 if (ret) {
587 dev_err(&pdev->dev, "clk prepare failed\n"); 582 dev_err(&pdev->dev, "clk prepare failed\n");
588 return ret; 583 return ret;
589 } 584 }
590 } 585 }
591 586
592 ret = gpiochip_add(&plgpio->chip); 587 ret = gpiochip_add(&plgpio->chip);
593 if (ret) { 588 if (ret) {
594 dev_err(&pdev->dev, "unable to add gpio chip\n"); 589 dev_err(&pdev->dev, "unable to add gpio chip\n");
595 goto unprepare_clk; 590 goto unprepare_clk;
596 } 591 }
597 592
598 irq = platform_get_irq(pdev, 0); 593 irq = platform_get_irq(pdev, 0);
599 if (irq < 0) { 594 if (irq < 0) {
600 dev_info(&pdev->dev, "irqs not supported\n"); 595 dev_info(&pdev->dev, "irqs not supported\n");
601 return 0; 596 return 0;
602 } 597 }
603 598
604 plgpio->irq_base = irq_alloc_descs(-1, 0, plgpio->chip.ngpio, 0); 599 plgpio->irq_base = irq_alloc_descs(-1, 0, plgpio->chip.ngpio, 0);
605 if (IS_ERR_VALUE(plgpio->irq_base)) { 600 if (IS_ERR_VALUE(plgpio->irq_base)) {
606 /* we would not support irq for gpio */ 601 /* we would not support irq for gpio */
607 dev_warn(&pdev->dev, "couldn't allocate irq base\n"); 602 dev_warn(&pdev->dev, "couldn't allocate irq base\n");
608 return 0; 603 return 0;
609 } 604 }
610 605
611 plgpio->irq_domain = irq_domain_add_legacy(np, plgpio->chip.ngpio, 606 plgpio->irq_domain = irq_domain_add_legacy(np, plgpio->chip.ngpio,
612 plgpio->irq_base, 0, &irq_domain_simple_ops, NULL); 607 plgpio->irq_base, 0, &irq_domain_simple_ops, NULL);
613 if (WARN_ON(!plgpio->irq_domain)) { 608 if (WARN_ON(!plgpio->irq_domain)) {
614 dev_err(&pdev->dev, "irq domain init failed\n"); 609 dev_err(&pdev->dev, "irq domain init failed\n");
615 irq_free_descs(plgpio->irq_base, plgpio->chip.ngpio); 610 irq_free_descs(plgpio->irq_base, plgpio->chip.ngpio);
616 ret = -ENXIO; 611 ret = -ENXIO;
617 goto remove_gpiochip; 612 goto remove_gpiochip;
618 } 613 }
619 614
620 irq_set_chained_handler(irq, plgpio_irq_handler); 615 irq_set_chained_handler(irq, plgpio_irq_handler);
621 for (i = 0; i < plgpio->chip.ngpio; i++) { 616 for (i = 0; i < plgpio->chip.ngpio; i++) {
622 irq_set_chip_and_handler(i + plgpio->irq_base, &plgpio_irqchip, 617 irq_set_chip_and_handler(i + plgpio->irq_base, &plgpio_irqchip,
623 handle_simple_irq); 618 handle_simple_irq);
624 set_irq_flags(i + plgpio->irq_base, IRQF_VALID); 619 set_irq_flags(i + plgpio->irq_base, IRQF_VALID);
625 irq_set_chip_data(i + plgpio->irq_base, plgpio); 620 irq_set_chip_data(i + plgpio->irq_base, plgpio);
626 } 621 }
627 622
628 irq_set_handler_data(irq, plgpio); 623 irq_set_handler_data(irq, plgpio);
629 dev_info(&pdev->dev, "PLGPIO registered with IRQs\n"); 624 dev_info(&pdev->dev, "PLGPIO registered with IRQs\n");
630 625
631 return 0; 626 return 0;
632 627
633 remove_gpiochip: 628 remove_gpiochip:
634 dev_info(&pdev->dev, "Remove gpiochip\n"); 629 dev_info(&pdev->dev, "Remove gpiochip\n");
635 if (gpiochip_remove(&plgpio->chip)) 630 if (gpiochip_remove(&plgpio->chip))
636 dev_err(&pdev->dev, "unable to remove gpiochip\n"); 631 dev_err(&pdev->dev, "unable to remove gpiochip\n");
637 unprepare_clk: 632 unprepare_clk:
638 if (!IS_ERR(plgpio->clk)) 633 if (!IS_ERR(plgpio->clk))
639 clk_unprepare(plgpio->clk); 634 clk_unprepare(plgpio->clk);
640 635
641 return ret; 636 return ret;
642 } 637 }
643 638
644 #ifdef CONFIG_PM_SLEEP 639 #ifdef CONFIG_PM_SLEEP
645 static int plgpio_suspend(struct device *dev) 640 static int plgpio_suspend(struct device *dev)
646 { 641 {
647 struct plgpio *plgpio = dev_get_drvdata(dev); 642 struct plgpio *plgpio = dev_get_drvdata(dev);
648 int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG); 643 int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG);
649 void __iomem *off; 644 void __iomem *off;
650 645
651 for (i = 0; i < reg_count; i++) { 646 for (i = 0; i < reg_count; i++) {
652 off = plgpio->base + i * sizeof(int *); 647 off = plgpio->base + i * sizeof(int *);
653 648
654 if (plgpio->regs.enb != -1) 649 if (plgpio->regs.enb != -1)
655 plgpio->csave_regs[i].enb = 650 plgpio->csave_regs[i].enb =
656 readl_relaxed(plgpio->regs.enb + off); 651 readl_relaxed(plgpio->regs.enb + off);
657 if (plgpio->regs.eit != -1) 652 if (plgpio->regs.eit != -1)
658 plgpio->csave_regs[i].eit = 653 plgpio->csave_regs[i].eit =
659 readl_relaxed(plgpio->regs.eit + off); 654 readl_relaxed(plgpio->regs.eit + off);
660 plgpio->csave_regs[i].wdata = readl_relaxed(plgpio->regs.wdata + 655 plgpio->csave_regs[i].wdata = readl_relaxed(plgpio->regs.wdata +
661 off); 656 off);
662 plgpio->csave_regs[i].dir = readl_relaxed(plgpio->regs.dir + 657 plgpio->csave_regs[i].dir = readl_relaxed(plgpio->regs.dir +
663 off); 658 off);
664 plgpio->csave_regs[i].ie = readl_relaxed(plgpio->regs.ie + off); 659 plgpio->csave_regs[i].ie = readl_relaxed(plgpio->regs.ie + off);
665 } 660 }
666 661
667 return 0; 662 return 0;
668 } 663 }
669 664
670 /* 665 /*
671 * This is used to correct the values in end registers. End registers contain 666 * This is used to correct the values in end registers. End registers contain
672 * extra bits that might be used for other purpose in platform. So, we shouldn't 667 * extra bits that might be used for other purpose in platform. So, we shouldn't
673 * overwrite these bits. This macro, reads given register again, preserves other 668 * overwrite these bits. This macro, reads given register again, preserves other
674 * bit values (non-plgpio bits), and retain captured value (plgpio bits). 669 * bit values (non-plgpio bits), and retain captured value (plgpio bits).
675 */ 670 */
676 #define plgpio_prepare_reg(__reg, _off, _mask, _tmp) \ 671 #define plgpio_prepare_reg(__reg, _off, _mask, _tmp) \
677 { \ 672 { \
678 _tmp = readl_relaxed(plgpio->regs.__reg + _off); \ 673 _tmp = readl_relaxed(plgpio->regs.__reg + _off); \
679 _tmp &= ~_mask; \ 674 _tmp &= ~_mask; \
680 plgpio->csave_regs[i].__reg = \ 675 plgpio->csave_regs[i].__reg = \
681 _tmp | (plgpio->csave_regs[i].__reg & _mask); \ 676 _tmp | (plgpio->csave_regs[i].__reg & _mask); \
682 } 677 }
683 678
684 static int plgpio_resume(struct device *dev) 679 static int plgpio_resume(struct device *dev)
685 { 680 {
686 struct plgpio *plgpio = dev_get_drvdata(dev); 681 struct plgpio *plgpio = dev_get_drvdata(dev);
687 int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG); 682 int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG);
688 void __iomem *off; 683 void __iomem *off;
689 u32 mask, tmp; 684 u32 mask, tmp;
690 685
691 for (i = 0; i < reg_count; i++) { 686 for (i = 0; i < reg_count; i++) {
692 off = plgpio->base + i * sizeof(int *); 687 off = plgpio->base + i * sizeof(int *);
693 688
694 if (i == reg_count - 1) { 689 if (i == reg_count - 1) {
695 mask = (1 << (plgpio->chip.ngpio - i * 690 mask = (1 << (plgpio->chip.ngpio - i *
696 MAX_GPIO_PER_REG)) - 1; 691 MAX_GPIO_PER_REG)) - 1;
697 692
698 if (plgpio->regs.enb != -1) 693 if (plgpio->regs.enb != -1)
699 plgpio_prepare_reg(enb, off, mask, tmp); 694 plgpio_prepare_reg(enb, off, mask, tmp);
700 695
701 if (plgpio->regs.eit != -1) 696 if (plgpio->regs.eit != -1)
702 plgpio_prepare_reg(eit, off, mask, tmp); 697 plgpio_prepare_reg(eit, off, mask, tmp);
703 698
704 plgpio_prepare_reg(wdata, off, mask, tmp); 699 plgpio_prepare_reg(wdata, off, mask, tmp);
705 plgpio_prepare_reg(dir, off, mask, tmp); 700 plgpio_prepare_reg(dir, off, mask, tmp);
706 plgpio_prepare_reg(ie, off, mask, tmp); 701 plgpio_prepare_reg(ie, off, mask, tmp);
707 } 702 }
708 703
709 writel_relaxed(plgpio->csave_regs[i].wdata, plgpio->regs.wdata + 704 writel_relaxed(plgpio->csave_regs[i].wdata, plgpio->regs.wdata +
710 off); 705 off);
711 writel_relaxed(plgpio->csave_regs[i].dir, plgpio->regs.dir + 706 writel_relaxed(plgpio->csave_regs[i].dir, plgpio->regs.dir +
712 off); 707 off);
713 708
714 if (plgpio->regs.eit != -1) 709 if (plgpio->regs.eit != -1)
715 writel_relaxed(plgpio->csave_regs[i].eit, 710 writel_relaxed(plgpio->csave_regs[i].eit,
716 plgpio->regs.eit + off); 711 plgpio->regs.eit + off);
717 712
718 writel_relaxed(plgpio->csave_regs[i].ie, plgpio->regs.ie + off); 713 writel_relaxed(plgpio->csave_regs[i].ie, plgpio->regs.ie + off);
719 714
720 if (plgpio->regs.enb != -1) 715 if (plgpio->regs.enb != -1)
721 writel_relaxed(plgpio->csave_regs[i].enb, 716 writel_relaxed(plgpio->csave_regs[i].enb,
722 plgpio->regs.enb + off); 717 plgpio->regs.enb + off);
723 } 718 }
724 719
725 return 0; 720 return 0;
726 } 721 }
727 #endif 722 #endif
728 723
729 static SIMPLE_DEV_PM_OPS(plgpio_dev_pm_ops, plgpio_suspend, plgpio_resume); 724 static SIMPLE_DEV_PM_OPS(plgpio_dev_pm_ops, plgpio_suspend, plgpio_resume);
730 725
731 static const struct of_device_id plgpio_of_match[] = { 726 static const struct of_device_id plgpio_of_match[] = {
732 { .compatible = "st,spear-plgpio" }, 727 { .compatible = "st,spear-plgpio" },
733 {} 728 {}
734 }; 729 };
735 MODULE_DEVICE_TABLE(of, plgpio_of_match); 730 MODULE_DEVICE_TABLE(of, plgpio_of_match);
736 731
737 static struct platform_driver plgpio_driver = { 732 static struct platform_driver plgpio_driver = {
738 .probe = plgpio_probe, 733 .probe = plgpio_probe,
739 .driver = { 734 .driver = {
740 .owner = THIS_MODULE, 735 .owner = THIS_MODULE,
741 .name = "spear-plgpio", 736 .name = "spear-plgpio",
742 .pm = &plgpio_dev_pm_ops, 737 .pm = &plgpio_dev_pm_ops,
743 .of_match_table = of_match_ptr(plgpio_of_match), 738 .of_match_table = of_match_ptr(plgpio_of_match),
744 }, 739 },
745 }; 740 };
746 741
747 static int __init plgpio_init(void) 742 static int __init plgpio_init(void)
748 { 743 {
749 return platform_driver_register(&plgpio_driver); 744 return platform_driver_register(&plgpio_driver);
750 } 745 }
751 subsys_initcall(plgpio_init); 746 subsys_initcall(plgpio_init);
752 747
753 MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>"); 748 MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>");
754 MODULE_DESCRIPTION("ST Microlectronics SPEAr PLGPIO driver"); 749 MODULE_DESCRIPTION("ST Microlectronics SPEAr PLGPIO driver");
755 MODULE_LICENSE("GPL"); 750 MODULE_LICENSE("GPL");