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Commit 911a62d42365076209e2c327e7688db296e35d62

Authored by Venkatesh Pallipadi 2005-09-04 06:56:31 +0800

Committed by Linus Torvalds 2005-09-05 15:06:10 +0800

Exists in master and in 7 other branches

[PATCH] x86: sutomatically enable bigsmp when we have more than 8 CPUs

i386 generic subarchitecture requires explicit dmi strings or command line
to enable bigsmp mode.  The patch below removes that restriction, and uses
bigsmp as soon as it finds more than 8 logical CPUs, Intel processors and
xAPIC support.

Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

Showing 8 changed files with 47 additions and 2 deletions Inline Diff

arch/i386/kernel/acpi/boot.c
arch/i386/kernel/mpparse.c
arch/i386/kernel/setup.c
arch/i386/mach-generic/bigsmp.c
arch/i386/mach-generic/probe.c
include/asm-i386/apicdef.h
include/asm-i386/mach-generic/mach_apic.h
include/asm-i386/mpspec.h

arch/i386/kernel/acpi/boot.c

Diff comments View file @ 911a62d

 /*
  *  boot.c - Architecture-Specific Low-Level ACPI Boot Support
  *
  *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
  *  Copyright (C) 2001 Jun Nakajima <jun.nakajima@intel.com>
  *
  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *  the Free Software Foundation; either version 2 of the License, or
  *  (at your option) any later version.
  *
  *  This program is distributed in the hope that it will be useful,
  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  *  GNU General Public License for more details.
  *
  *  You should have received a copy of the GNU General Public License
  *  along with this program; if not, write to the Free Software
  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  *
  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  */
 #include <linux/init.h>
 #include <linux/config.h>
 #include <linux/acpi.h>
 #include <linux/efi.h>
 #include <linux/irq.h>
 #include <linux/module.h>
 #include <linux/dmi.h>
 #include <asm/pgtable.h>
 #include <asm/io_apic.h>
 #include <asm/apic.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mpspec.h>
 #ifdef	CONFIG_X86_64
 static inline void  acpi_madt_oem_check(char *oem_id, char *oem_table_id) { }
 extern void __init clustered_apic_check(void);
 static inline int ioapic_setup_disabled(void) { return 0; }
 #include <asm/proto.h>
 #else	/* X86 */
 #ifdef	CONFIG_X86_LOCAL_APIC
 #include <mach_apic.h>
 #include <mach_mpparse.h>
 #endif	/* CONFIG_X86_LOCAL_APIC */
 #endif	/* X86 */
 #define BAD_MADT_ENTRY(entry, end) (					    \
 		(!entry) || (unsigned long)entry + sizeof(*entry) > end ||  \
 		((acpi_table_entry_header *)entry)->length != sizeof(*entry))
 #define PREFIX			"ACPI: "
 #ifdef CONFIG_ACPI_PCI
 int acpi_noirq __initdata;	/* skip ACPI IRQ initialization */
 int acpi_pci_disabled __initdata; /* skip ACPI PCI scan and IRQ initialization */
 #else
 int acpi_noirq __initdata = 1;
 int acpi_pci_disabled __initdata = 1;
 #endif
 int acpi_ht __initdata = 1;	/* enable HT */
 int acpi_lapic;
 int acpi_ioapic;
 int acpi_strict;
 EXPORT_SYMBOL(acpi_strict);
 acpi_interrupt_flags acpi_sci_flags __initdata;
 int acpi_sci_override_gsi __initdata;
 int acpi_skip_timer_override __initdata;
 #ifdef CONFIG_X86_LOCAL_APIC
 static u64 acpi_lapic_addr __initdata = APIC_DEFAULT_PHYS_BASE;
 #endif
 #ifndef __HAVE_ARCH_CMPXCHG
 #warning ACPI uses CMPXCHG, i486 and later hardware
 #endif
 #define MAX_MADT_ENTRIES	256
 u8 x86_acpiid_to_apicid[MAX_MADT_ENTRIES] =
 			{ [0 ... MAX_MADT_ENTRIES-1] = 0xff };
 EXPORT_SYMBOL(x86_acpiid_to_apicid);
 /* --------------------------------------------------------------------------
                               Boot-time Configuration
    -------------------------------------------------------------------------- */
 /*
  * The default interrupt routing model is PIC (8259).  This gets
  * overriden if IOAPICs are enumerated (below).
  */
 enum acpi_irq_model_id		acpi_irq_model = ACPI_IRQ_MODEL_PIC;
 #ifdef	CONFIG_X86_64
 /* rely on all ACPI tables being in the direct mapping */
 char *__acpi_map_table(unsigned long phys_addr, unsigned long size)
 {
 	if (!phys_addr || !size)
 	return NULL;
 	if (phys_addr < (end_pfn_map << PAGE_SHIFT))
 		return __va(phys_addr);
 	return NULL;
 }
 #else
 /*
  * Temporarily use the virtual area starting from FIX_IO_APIC_BASE_END,
  * to map the target physical address. The problem is that set_fixmap()
  * provides a single page, and it is possible that the page is not
  * sufficient.
  * By using this area, we can map up to MAX_IO_APICS pages temporarily,
  * i.e. until the next __va_range() call.
  *
  * Important Safety Note:  The fixed I/O APIC page numbers are *subtracted*
  * from the fixed base.  That's why we start at FIX_IO_APIC_BASE_END and
  * count idx down while incrementing the phys address.
  */
 char *__acpi_map_table(unsigned long phys, unsigned long size)
 {
 	unsigned long base, offset, mapped_size;
 	int idx;
 	if (phys + size < 8*1024*1024)
 		return __va(phys);
 	offset = phys & (PAGE_SIZE - 1);
 	mapped_size = PAGE_SIZE - offset;
 	set_fixmap(FIX_ACPI_END, phys);
 	base = fix_to_virt(FIX_ACPI_END);
 	/*
 	 * Most cases can be covered by the below.
 	 */
 	idx = FIX_ACPI_END;
 	while (mapped_size < size) {
 		if (--idx < FIX_ACPI_BEGIN)
 			return NULL;	/* cannot handle this */
 		phys += PAGE_SIZE;
 		set_fixmap(idx, phys);
 		mapped_size += PAGE_SIZE;
 	}
 	return ((unsigned char *) base + offset);
 }
 #endif
 #ifdef CONFIG_PCI_MMCONFIG
 /* The physical address of the MMCONFIG aperture.  Set from ACPI tables. */
 struct acpi_table_mcfg_config *pci_mmcfg_config;
 int pci_mmcfg_config_num;
 int __init acpi_parse_mcfg(unsigned long phys_addr, unsigned long size)
 {
 	struct acpi_table_mcfg *mcfg;
 	unsigned long i;
 	int config_size;
 	if (!phys_addr || !size)
 		return -EINVAL;
 	mcfg = (struct acpi_table_mcfg *) __acpi_map_table(phys_addr, size);
 	if (!mcfg) {
 		printk(KERN_WARNING PREFIX "Unable to map MCFG\n");
 		return -ENODEV;
 	}
 	/* how many config structures do we have */
 	pci_mmcfg_config_num = 0;
 	i = size - sizeof(struct acpi_table_mcfg);
 	while (i >= sizeof(struct acpi_table_mcfg_config)) {
 		++pci_mmcfg_config_num;
 		i -= sizeof(struct acpi_table_mcfg_config);
 	};
 	if (pci_mmcfg_config_num == 0) {
 		printk(KERN_ERR PREFIX "MMCONFIG has no entries\n");
 		return -ENODEV;
 	}
 	config_size = pci_mmcfg_config_num * sizeof(*pci_mmcfg_config);
 	pci_mmcfg_config = kmalloc(config_size, GFP_KERNEL);
 	if (!pci_mmcfg_config) {
 		printk(KERN_WARNING PREFIX
 		       "No memory for MCFG config tables\n");
 		return -ENOMEM;
 	}
 	memcpy(pci_mmcfg_config, &mcfg->config, config_size);
 	for (i = 0; i < pci_mmcfg_config_num; ++i) {
 		if (mcfg->config[i].base_reserved) {
 			printk(KERN_ERR PREFIX
 			       "MMCONFIG not in low 4GB of memory\n");
 			return -ENODEV;
 		}
 	}
 	return 0;
 }
 #endif /* CONFIG_PCI_MMCONFIG */
 #ifdef CONFIG_X86_LOCAL_APIC
 static int __init
 acpi_parse_madt (
 	unsigned long		phys_addr,
 	unsigned long		size)
 {
 	struct acpi_table_madt	*madt = NULL;
 	if (!phys_addr || !size)
 		return -EINVAL;
 	madt = (struct acpi_table_madt *) __acpi_map_table(phys_addr, size);
 	if (!madt) {
 		printk(KERN_WARNING PREFIX "Unable to map MADT\n");
 		return -ENODEV;
 	}
 	if (madt->lapic_address) {
 		acpi_lapic_addr = (u64) madt->lapic_address;
 		printk(KERN_DEBUG PREFIX "Local APIC address 0x%08x\n",
 			madt->lapic_address);
 	}
 	acpi_madt_oem_check(madt->header.oem_id, madt->header.oem_table_id);
 	return 0;
 }
 static int __init
 acpi_parse_lapic (
 	acpi_table_entry_header *header, const unsigned long end)
 {
 	struct acpi_table_lapic	*processor = NULL;
 	processor = (struct acpi_table_lapic*) header;
 	if (BAD_MADT_ENTRY(processor, end))
 		return -EINVAL;
 	acpi_table_print_madt_entry(header);
 	/* no utility in registering a disabled processor */
 	if (processor->flags.enabled == 0)
 		return 0;
 	x86_acpiid_to_apicid[processor->acpi_id] = processor->id;
 	mp_register_lapic (
 		processor->id,					   /* APIC ID */
 		processor->flags.enabled);			  /* Enabled? */
 	return 0;
 }
 static int __init
 acpi_parse_lapic_addr_ovr (
 	acpi_table_entry_header *header, const unsigned long end)
 {
 	struct acpi_table_lapic_addr_ovr *lapic_addr_ovr = NULL;
 	lapic_addr_ovr = (struct acpi_table_lapic_addr_ovr*) header;
 	if (BAD_MADT_ENTRY(lapic_addr_ovr, end))
 		return -EINVAL;
 	acpi_lapic_addr = lapic_addr_ovr->address;
 	return 0;
 }
 static int __init
 acpi_parse_lapic_nmi (
 	acpi_table_entry_header *header, const unsigned long end)
 {
 	struct acpi_table_lapic_nmi *lapic_nmi = NULL;
 	lapic_nmi = (struct acpi_table_lapic_nmi*) header;
 	if (BAD_MADT_ENTRY(lapic_nmi, end))
 		return -EINVAL;
 	acpi_table_print_madt_entry(header);
 	if (lapic_nmi->lint != 1)
 		printk(KERN_WARNING PREFIX "NMI not connected to LINT 1!\n");
 	return 0;
 }
 #endif /*CONFIG_X86_LOCAL_APIC*/
 #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_ACPI_INTERPRETER)
 static int __init
 acpi_parse_ioapic (
 	acpi_table_entry_header *header, const unsigned long end)
 {
 	struct acpi_table_ioapic *ioapic = NULL;
 	ioapic = (struct acpi_table_ioapic*) header;
 	if (BAD_MADT_ENTRY(ioapic, end))
 		return -EINVAL;
 	acpi_table_print_madt_entry(header);
 	mp_register_ioapic (
 		ioapic->id,
 		ioapic->address,
 		ioapic->global_irq_base);
 	return 0;
 }
 /*
  * Parse Interrupt Source Override for the ACPI SCI
  */
 static void
 acpi_sci_ioapic_setup(u32 gsi, u16 polarity, u16 trigger)
 {
 	if (trigger == 0)	/* compatible SCI trigger is level */
 		trigger = 3;
 	if (polarity == 0)	/* compatible SCI polarity is low */
 		polarity = 3;
 	/* Command-line over-ride via acpi_sci= */
 	if (acpi_sci_flags.trigger)
 		trigger = acpi_sci_flags.trigger;
 	if (acpi_sci_flags.polarity)
 		polarity = acpi_sci_flags.polarity;
 	/*
  	 * mp_config_acpi_legacy_irqs() already setup IRQs < 16
 	 * If GSI is < 16, this will update its flags,
 	 * else it will create a new mp_irqs[] entry.
 	 */
 	mp_override_legacy_irq(gsi, polarity, trigger, gsi);
 	/*
 	 * stash over-ride to indicate we've been here
 	 * and for later update of acpi_fadt
 	 */
 	acpi_sci_override_gsi = gsi;
 	return;
 }
 static int __init
 acpi_parse_int_src_ovr (
 	acpi_table_entry_header *header, const unsigned long end)
 {
 	struct acpi_table_int_src_ovr *intsrc = NULL;
 	intsrc = (struct acpi_table_int_src_ovr*) header;
 	if (BAD_MADT_ENTRY(intsrc, end))
 		return -EINVAL;
 	acpi_table_print_madt_entry(header);
 	if (intsrc->bus_irq == acpi_fadt.sci_int) {
 		acpi_sci_ioapic_setup(intsrc->global_irq,
 			intsrc->flags.polarity, intsrc->flags.trigger);
 		return 0;
 	}
 	if (acpi_skip_timer_override &&
 		intsrc->bus_irq == 0 && intsrc->global_irq == 2) {
 			printk(PREFIX "BIOS IRQ0 pin2 override ignored.\n");
 			return 0;
 	}
 	mp_override_legacy_irq (
 		intsrc->bus_irq,
 		intsrc->flags.polarity,
 		intsrc->flags.trigger,
 		intsrc->global_irq);
 	return 0;
 }
 static int __init
 acpi_parse_nmi_src (
 	acpi_table_entry_header *header, const unsigned long end)
 {
 	struct acpi_table_nmi_src *nmi_src = NULL;
 	nmi_src = (struct acpi_table_nmi_src*) header;
 	if (BAD_MADT_ENTRY(nmi_src, end))
 		return -EINVAL;
 	acpi_table_print_madt_entry(header);
 	/* TBD: Support nimsrc entries? */
 	return 0;
 }
 #endif /* CONFIG_X86_IO_APIC */
 #ifdef	CONFIG_ACPI_BUS
 /*
  * acpi_pic_sci_set_trigger()
  *
  * use ELCR to set PIC-mode trigger type for SCI
  *
  * If a PIC-mode SCI is not recognized or gives spurious IRQ7's
  * it may require Edge Trigger -- use "acpi_sci=edge"
  *
  * Port 0x4d0-4d1 are ECLR1 and ECLR2, the Edge/Level Control Registers
  * for the 8259 PIC.  bit[n] = 1 means irq[n] is Level, otherwise Edge.
  * ECLR1 is IRQ's 0-7 (IRQ 0, 1, 2 must be 0)
  * ECLR2 is IRQ's 8-15 (IRQ 8, 13 must be 0)
  */
 void __init
 acpi_pic_sci_set_trigger(unsigned int irq, u16 trigger)
 {
 	unsigned int mask = 1 << irq;
 	unsigned int old, new;
 	/* Real old ELCR mask */
 	old = inb(0x4d0) | (inb(0x4d1) << 8);
 	/*
 	 * If we use ACPI to set PCI irq's, then we should clear ELCR
 	 * since we will set it correctly as we enable the PCI irq
 	 * routing.
 	 */
 	new = acpi_noirq ? old : 0;
 	/*
 	 * Update SCI information in the ELCR, it isn't in the PCI
 	 * routing tables..
 	 */
 	switch (trigger) {
 	case 1:	/* Edge - clear */
 		new &= ~mask;
 		break;
 	case 3: /* Level - set */
 		new |= mask;
 		break;
 	}
 	if (old == new)
 		return;
 	printk(PREFIX "setting ELCR to %04x (from %04x)\n", new, old);
 	outb(new, 0x4d0);
 	outb(new >> 8, 0x4d1);
 }
 #endif /* CONFIG_ACPI_BUS */
 int acpi_gsi_to_irq(u32 gsi, unsigned int *irq)
 {
 #ifdef CONFIG_X86_IO_APIC
 	if (use_pci_vector() && !platform_legacy_irq(gsi))
  		*irq = IO_APIC_VECTOR(gsi);
 	else
 #endif
 		*irq = gsi;
 	return 0;
 }
 unsigned int acpi_register_gsi(u32 gsi, int edge_level, int active_high_low)
 {
 	unsigned int irq;
 	unsigned int plat_gsi = gsi;
 #ifdef CONFIG_PCI
 	/*
 	 * Make sure all (legacy) PCI IRQs are set as level-triggered.
 	 */
 	if (acpi_irq_model == ACPI_IRQ_MODEL_PIC) {
 		extern void eisa_set_level_irq(unsigned int irq);
 		if (edge_level == ACPI_LEVEL_SENSITIVE)
 				eisa_set_level_irq(gsi);
 	}
 #endif
 #ifdef CONFIG_X86_IO_APIC
 	if (acpi_irq_model == ACPI_IRQ_MODEL_IOAPIC) {
 		plat_gsi = mp_register_gsi(gsi, edge_level, active_high_low);
 	}
 #endif
 	acpi_gsi_to_irq(plat_gsi, &irq);
 	return irq;
 }
 EXPORT_SYMBOL(acpi_register_gsi);
 /*
  *  ACPI based hotplug support for CPU
  */
 #ifdef CONFIG_ACPI_HOTPLUG_CPU
 int
 acpi_map_lsapic(acpi_handle handle, int *pcpu)
 {
 	/* TBD */
 	return -EINVAL;
 }
 EXPORT_SYMBOL(acpi_map_lsapic);
 int
 acpi_unmap_lsapic(int cpu)
 {
 	/* TBD */
 	return -EINVAL;
 }
 EXPORT_SYMBOL(acpi_unmap_lsapic);
 #endif /* CONFIG_ACPI_HOTPLUG_CPU */
 int
 acpi_register_ioapic(acpi_handle handle, u64 phys_addr, u32 gsi_base)
 {
 	/* TBD */
 	return -EINVAL;
 }
 EXPORT_SYMBOL(acpi_register_ioapic);
 int
 acpi_unregister_ioapic(acpi_handle handle, u32 gsi_base)
 {
 	/* TBD */
 	return -EINVAL;
 }
 EXPORT_SYMBOL(acpi_unregister_ioapic);
 static unsigned long __init
 acpi_scan_rsdp (
 	unsigned long		start,
 	unsigned long		length)
 {
 	unsigned long		offset = 0;
 	unsigned long		sig_len = sizeof("RSD PTR ") - 1;
 	/*
 	 * Scan all 16-byte boundaries of the physical memory region for the
 	 * RSDP signature.
 	 */
 	for (offset = 0; offset < length; offset += 16) {
 		if (strncmp((char *) (start + offset), "RSD PTR ", sig_len))
 			continue;
 		return (start + offset);
 	}
 	return 0;
 }
 static int __init acpi_parse_sbf(unsigned long phys_addr, unsigned long size)
 {
 	struct acpi_table_sbf *sb;
 	if (!phys_addr || !size)
 	return -EINVAL;
 	sb = (struct acpi_table_sbf *) __acpi_map_table(phys_addr, size);
 	if (!sb) {
 		printk(KERN_WARNING PREFIX "Unable to map SBF\n");
 		return -ENODEV;
 	}
 	sbf_port = sb->sbf_cmos; /* Save CMOS port */
 	return 0;
 }
 #ifdef CONFIG_HPET_TIMER
 static int __init acpi_parse_hpet(unsigned long phys, unsigned long size)
 {
 	struct acpi_table_hpet *hpet_tbl;
 	if (!phys || !size)
 		return -EINVAL;
 	hpet_tbl = (struct acpi_table_hpet *) __acpi_map_table(phys, size);
 	if (!hpet_tbl) {
 		printk(KERN_WARNING PREFIX "Unable to map HPET\n");
 		return -ENODEV;
 	}
 	if (hpet_tbl->addr.space_id != ACPI_SPACE_MEM) {
 		printk(KERN_WARNING PREFIX "HPET timers must be located in "
 		       "memory.\n");
 		return -1;
 	}
 #ifdef	CONFIG_X86_64
         vxtime.hpet_address = hpet_tbl->addr.addrl |
                 ((long) hpet_tbl->addr.addrh << 32);
         printk(KERN_INFO PREFIX "HPET id: %#x base: %#lx\n",
                hpet_tbl->id, vxtime.hpet_address);
 #else	/* X86 */
 	{
 		extern unsigned long hpet_address;
 		hpet_address = hpet_tbl->addr.addrl;
 		printk(KERN_INFO PREFIX "HPET id: %#x base: %#lx\n",
 			hpet_tbl->id, hpet_address);
 	}
 #endif	/* X86 */
 	return 0;
 }
 #else
 #define	acpi_parse_hpet	NULL
 #endif
 #ifdef CONFIG_X86_PM_TIMER
 extern u32 pmtmr_ioport;
 #endif
 static int __init acpi_parse_fadt(unsigned long phys, unsigned long size)
 {
 	struct fadt_descriptor_rev2 *fadt = NULL;
 	fadt = (struct fadt_descriptor_rev2*) __acpi_map_table(phys,size);
 	if(!fadt) {
 		printk(KERN_WARNING PREFIX "Unable to map FADT\n");
 		return 0;
 	}
 #ifdef	CONFIG_ACPI_INTERPRETER
 	/* initialize sci_int early for INT_SRC_OVR MADT parsing */
 	acpi_fadt.sci_int = fadt->sci_int;
 #endif
 #ifdef CONFIG_ACPI_BUS
 	/* initialize rev and apic_phys_dest_mode for x86_64 genapic */
 	acpi_fadt.revision = fadt->revision;
 	acpi_fadt.force_apic_physical_destination_mode = fadt->force_apic_physical_destination_mode;
 #endif
 #ifdef CONFIG_X86_PM_TIMER
 	/* detect the location of the ACPI PM Timer */
 	if (fadt->revision >= FADT2_REVISION_ID) {
 		/* FADT rev. 2 */
 		if (fadt->xpm_tmr_blk.address_space_id != ACPI_ADR_SPACE_SYSTEM_IO)
 			return 0;
 		pmtmr_ioport = fadt->xpm_tmr_blk.address;
 	} else {
 		/* FADT rev. 1 */
 		pmtmr_ioport = fadt->V1_pm_tmr_blk;
 	}
 	if (pmtmr_ioport)
 		printk(KERN_INFO PREFIX "PM-Timer IO Port: %#x\n", pmtmr_ioport);
 #endif
 	return 0;
 }
 unsigned long __init
 acpi_find_rsdp (void)
 {
 	unsigned long		rsdp_phys = 0;
 	if (efi_enabled) {
 		if (efi.acpi20)
 			return __pa(efi.acpi20);
 		else if (efi.acpi)
 			return __pa(efi.acpi);
 	}
 	/*
 	 * Scan memory looking for the RSDP signature. First search EBDA (low
 	 * memory) paragraphs and then search upper memory (E0000-FFFFF).
 	 */
 	rsdp_phys = acpi_scan_rsdp (0, 0x400);
 	if (!rsdp_phys)
 		rsdp_phys = acpi_scan_rsdp (0xE0000, 0x20000);
 	return rsdp_phys;
 }
 #ifdef	CONFIG_X86_LOCAL_APIC
 /*
  * Parse LAPIC entries in MADT
  * returns 0 on success, < 0 on error
  */
 static int __init
 acpi_parse_madt_lapic_entries(void)
 {
 	int count;
 	/*
 	 * Note that the LAPIC address is obtained from the MADT (32-bit value)
 	 * and (optionally) overriden by a LAPIC_ADDR_OVR entry (64-bit value).
 	 */
 	count = acpi_table_parse_madt(ACPI_MADT_LAPIC_ADDR_OVR, acpi_parse_lapic_addr_ovr, 0);
 	if (count < 0) {
 		printk(KERN_ERR PREFIX "Error parsing LAPIC address override entry\n");
 		return count;
 	}
 	mp_register_lapic_address(acpi_lapic_addr);
 	count = acpi_table_parse_madt(ACPI_MADT_LAPIC, acpi_parse_lapic,
 				       MAX_APICS);
 	if (!count) {
 		printk(KERN_ERR PREFIX "No LAPIC entries present\n");
 		/* TBD: Cleanup to allow fallback to MPS */
 		return -ENODEV;
 	}
 	else if (count < 0) {
 		printk(KERN_ERR PREFIX "Error parsing LAPIC entry\n");
 		/* TBD: Cleanup to allow fallback to MPS */
 		return count;
 	}
 	count = acpi_table_parse_madt(ACPI_MADT_LAPIC_NMI, acpi_parse_lapic_nmi, 0);
 	if (count < 0) {
 		printk(KERN_ERR PREFIX "Error parsing LAPIC NMI entry\n");
 		/* TBD: Cleanup to allow fallback to MPS */
 		return count;
 	}
 	return 0;
 }
 #endif /* CONFIG_X86_LOCAL_APIC */
 #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_ACPI_INTERPRETER)
 /*
  * Parse IOAPIC related entries in MADT
  * returns 0 on success, < 0 on error
  */
 static int __init
 acpi_parse_madt_ioapic_entries(void)
 {
 	int count;
 	/*
 	 * ACPI interpreter is required to complete interrupt setup,
 	 * so if it is off, don't enumerate the io-apics with ACPI.
 	 * If MPS is present, it will handle them,
 	 * otherwise the system will stay in PIC mode
 	 */
 	if (acpi_disabled || acpi_noirq) {
 		return -ENODEV;
         }
 	/*
  	 * if "noapic" boot option, don't look for IO-APICs
 	 */
 	if (skip_ioapic_setup) {
 		printk(KERN_INFO PREFIX "Skipping IOAPIC probe "
 			"due to 'noapic' option.\n");
 		return -ENODEV;
 	}
 	count = acpi_table_parse_madt(ACPI_MADT_IOAPIC, acpi_parse_ioapic, MAX_IO_APICS);
 	if (!count) {
 		printk(KERN_ERR PREFIX "No IOAPIC entries present\n");
 		return -ENODEV;
 	}
 	else if (count < 0) {
 		printk(KERN_ERR PREFIX "Error parsing IOAPIC entry\n");
 		return count;
 	}
 	count = acpi_table_parse_madt(ACPI_MADT_INT_SRC_OVR, acpi_parse_int_src_ovr, NR_IRQ_VECTORS);
 	if (count < 0) {
 		printk(KERN_ERR PREFIX "Error parsing interrupt source overrides entry\n");
 		/* TBD: Cleanup to allow fallback to MPS */
 		return count;
 	}
 	/*
 	 * If BIOS did not supply an INT_SRC_OVR for the SCI
 	 * pretend we got one so we can set the SCI flags.
 	 */
 	if (!acpi_sci_override_gsi)
 		acpi_sci_ioapic_setup(acpi_fadt.sci_int, 0, 0);
 	/* Fill in identity legacy mapings where no override */
 	mp_config_acpi_legacy_irqs();
 	count = acpi_table_parse_madt(ACPI_MADT_NMI_SRC, acpi_parse_nmi_src, NR_IRQ_VECTORS);
 	if (count < 0) {
 		printk(KERN_ERR PREFIX "Error parsing NMI SRC entry\n");
 		/* TBD: Cleanup to allow fallback to MPS */
 		return count;
 	}
 	return 0;
 }
 #else
 static inline int acpi_parse_madt_ioapic_entries(void)
 {
 	return -1;
 }
 #endif /* !(CONFIG_X86_IO_APIC && CONFIG_ACPI_INTERPRETER) */
 static void __init
 acpi_process_madt(void)
 {
 #ifdef CONFIG_X86_LOCAL_APIC
 	int count, error;
 	count = acpi_table_parse(ACPI_APIC, acpi_parse_madt);
 	if (count >= 1) {
 		/*
 		 * Parse MADT LAPIC entries
 		 */
 		error = acpi_parse_madt_lapic_entries();
 		if (!error) {
 			acpi_lapic = 1;
+#ifdef CONFIG_X86_GENERICARCH
+			generic_bigsmp_probe();
+#endif
 			/*
 			 * Parse MADT IO-APIC entries
 			 */
 			error = acpi_parse_madt_ioapic_entries();
 			if (!error) {
 				acpi_irq_model = ACPI_IRQ_MODEL_IOAPIC;
 				acpi_irq_balance_set(NULL);
 				acpi_ioapic = 1;
 				smp_found_config = 1;
 				clustered_apic_check();
 			}
 		}
 		if (error == -EINVAL) {
 			/*
 			 * Dell Precision Workstation 410, 610 come here.
 			 */
 			printk(KERN_ERR PREFIX "Invalid BIOS MADT, disabling ACPI\n");
 			disable_acpi();
 		}
 	}
 #endif
 	return;
 }
 extern int acpi_force;
 #ifdef __i386__
 #ifdef	CONFIG_ACPI_PCI
 static int __init disable_acpi_irq(struct dmi_system_id *d)
 {
 	if (!acpi_force) {
 		printk(KERN_NOTICE "%s detected: force use of acpi=noirq\n",
 		       d->ident);
 		acpi_noirq_set();
 	}
 	return 0;
 }
 static int __init disable_acpi_pci(struct dmi_system_id *d)
 {
 	if (!acpi_force) {
 		printk(KERN_NOTICE "%s detected: force use of pci=noacpi\n",
 		       d->ident);
 		acpi_disable_pci();
 	}
 	return 0;
 }
 #endif
 static int __init dmi_disable_acpi(struct dmi_system_id *d)
 {
 	if (!acpi_force) {
 		printk(KERN_NOTICE "%s detected: acpi off\n",d->ident);
 		disable_acpi();
 	} else {
 		printk(KERN_NOTICE
 		       "Warning: DMI blacklist says broken, but acpi forced\n");
 	}
 	return 0;
 }
 /*
  * Limit ACPI to CPU enumeration for HT
  */
 static int __init force_acpi_ht(struct dmi_system_id *d)
 {
 	if (!acpi_force) {
 		printk(KERN_NOTICE "%s detected: force use of acpi=ht\n", d->ident);
 		disable_acpi();
 		acpi_ht = 1;
 	} else {
 		printk(KERN_NOTICE
 		       "Warning: acpi=force overrules DMI blacklist: acpi=ht\n");
 	}
 	return 0;
 }
 /*
  * If your system is blacklisted here, but you find that acpi=force
  * works for you, please contact acpi-devel@sourceforge.net
  */
 static struct dmi_system_id __initdata acpi_dmi_table[] = {
 	/*
 	 * Boxes that need ACPI disabled
 	 */
 	{
 		.callback = dmi_disable_acpi,
 		.ident = "IBM Thinkpad",
 		.matches = {
 			DMI_MATCH(DMI_BOARD_VENDOR, "IBM"),
 			DMI_MATCH(DMI_BOARD_NAME, "2629H1G"),
 		},
 	},
 	/*
 	 * Boxes that need acpi=ht
 	 */
 	{
 		.callback = force_acpi_ht,
 		.ident = "FSC Primergy T850",
 		.matches = {
 			DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU SIEMENS"),
 			DMI_MATCH(DMI_PRODUCT_NAME, "PRIMERGY T850"),
 		},
 	},
 	{
 		.callback = force_acpi_ht,
 		.ident = "DELL GX240",
 		.matches = {
 			DMI_MATCH(DMI_BOARD_VENDOR, "Dell Computer Corporation"),
 			DMI_MATCH(DMI_BOARD_NAME, "OptiPlex GX240"),
 		},
 	},
 	{
 		.callback = force_acpi_ht,
 		.ident = "HP VISUALIZE NT Workstation",
 		.matches = {
 			DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 			DMI_MATCH(DMI_PRODUCT_NAME, "HP VISUALIZE NT Workstation"),
 		},
 	},
 	{
 		.callback = force_acpi_ht,
 		.ident = "Compaq Workstation W8000",
 		.matches = {
 			DMI_MATCH(DMI_SYS_VENDOR, "Compaq"),
 			DMI_MATCH(DMI_PRODUCT_NAME, "Workstation W8000"),
 		},
 	},
 	{
 		.callback = force_acpi_ht,
 		.ident = "ASUS P4B266",
 		.matches = {
 			DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 			DMI_MATCH(DMI_BOARD_NAME, "P4B266"),
 		},
 	},
 	{
 		.callback = force_acpi_ht,
 		.ident = "ASUS P2B-DS",
 		.matches = {
 			DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 			DMI_MATCH(DMI_BOARD_NAME, "P2B-DS"),
 		},
 	},
 	{
 		.callback = force_acpi_ht,
 		.ident = "ASUS CUR-DLS",
 		.matches = {
 			DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 			DMI_MATCH(DMI_BOARD_NAME, "CUR-DLS"),
 		},
 	},
 	{
 		.callback = force_acpi_ht,
 		.ident = "ABIT i440BX-W83977",
 		.matches = {
 			DMI_MATCH(DMI_BOARD_VENDOR, "ABIT <http://www.abit.com>"),
 			DMI_MATCH(DMI_BOARD_NAME, "i440BX-W83977 (BP6)"),
 		},
 	},
 	{
 		.callback = force_acpi_ht,
 		.ident = "IBM Bladecenter",
 		.matches = {
 			DMI_MATCH(DMI_BOARD_VENDOR, "IBM"),
 			DMI_MATCH(DMI_BOARD_NAME, "IBM eServer BladeCenter HS20"),
 		},
 	},
 	{
 		.callback = force_acpi_ht,
 		.ident = "IBM eServer xSeries 360",
 		.matches = {
 			DMI_MATCH(DMI_BOARD_VENDOR, "IBM"),
 			DMI_MATCH(DMI_BOARD_NAME, "eServer xSeries 360"),
 		},
 	},
 	{
 		.callback = force_acpi_ht,
 		.ident = "IBM eserver xSeries 330",
 		.matches = {
 			DMI_MATCH(DMI_BOARD_VENDOR, "IBM"),
 			DMI_MATCH(DMI_BOARD_NAME, "eserver xSeries 330"),
 		},
 	},
 	{
 		.callback = force_acpi_ht,
 		.ident = "IBM eserver xSeries 440",
 		.matches = {
 			DMI_MATCH(DMI_BOARD_VENDOR, "IBM"),
 			DMI_MATCH(DMI_PRODUCT_NAME, "eserver xSeries 440"),
 		},
 	},
 #ifdef	CONFIG_ACPI_PCI
 	/*
 	 * Boxes that need ACPI PCI IRQ routing disabled
 	 */
 	{
 		.callback = disable_acpi_irq,
 		.ident = "ASUS A7V",
 		.matches = {
 			DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC"),
 			DMI_MATCH(DMI_BOARD_NAME, "<A7V>"),
 			/* newer BIOS, Revision 1011, does work */
 			DMI_MATCH(DMI_BIOS_VERSION, "ASUS A7V ACPI BIOS Revision 1007"),
 		},
 	},
 	/*
 	 * Boxes that need ACPI PCI IRQ routing and PCI scan disabled
 	 */
 	{	/* _BBN 0 bug */
 		.callback = disable_acpi_pci,
 		.ident = "ASUS PR-DLS",
 		.matches = {
 			DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 			DMI_MATCH(DMI_BOARD_NAME, "PR-DLS"),
 			DMI_MATCH(DMI_BIOS_VERSION, "ASUS PR-DLS ACPI BIOS Revision 1010"),
 			DMI_MATCH(DMI_BIOS_DATE, "03/21/2003")
 		},
 	},
 	{
 		.callback = disable_acpi_pci,
 		.ident = "Acer TravelMate 36x Laptop",
 		.matches = {
 			DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
  			DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"),
 		},
 	},
 #endif
 	{ }
 };
 #endif	/* __i386__ */
 /*
  * acpi_boot_table_init() and acpi_boot_init()
  *  called from setup_arch(), always.
  *	1. checksums all tables
  *	2. enumerates lapics
  *	3. enumerates io-apics
  *
  * acpi_table_init() is separate to allow reading SRAT without
  * other side effects.
  *
  * side effects of acpi_boot_init:
  *	acpi_lapic = 1 if LAPIC found
  *	acpi_ioapic = 1 if IOAPIC found
  *	if (acpi_lapic && acpi_ioapic) smp_found_config = 1;
  *	if acpi_blacklisted() acpi_disabled = 1;
  *	acpi_irq_model=...
  *	...
  *
  * return value: (currently ignored)
  *	0: success
  *	!0: failure
  */
 int __init
 acpi_boot_table_init(void)
 {
 	int error;
 #ifdef __i386__
 	dmi_check_system(acpi_dmi_table);
 #endif
 	/*
 	 * If acpi_disabled, bail out
 	 * One exception: acpi=ht continues far enough to enumerate LAPICs
 	 */
 	if (acpi_disabled && !acpi_ht)
 		 return 1;
 	/*
 	 * Initialize the ACPI boot-time table parser.
 	 */
 	error = acpi_table_init();
 	if (error) {
 		disable_acpi();
 		return error;
 	}
 #ifdef __i386__
 	check_acpi_pci();
 #endif
 	acpi_table_parse(ACPI_BOOT, acpi_parse_sbf);
 	/*
 	 * blacklist may disable ACPI entirely
 	 */
 	error = acpi_blacklisted();
 	if (error) {
 		if (acpi_force) {
 			printk(KERN_WARNING PREFIX "acpi=force override\n");
 		} else {
 			printk(KERN_WARNING PREFIX "Disabling ACPI support\n");
 			disable_acpi();
 			return error;
 		}
 	}
 	return 0;
 }
 int __init acpi_boot_init(void)
 {
 	/*
 	 * If acpi_disabled, bail out
 	 * One exception: acpi=ht continues far enough to enumerate LAPICs
 	 */
 	if (acpi_disabled && !acpi_ht)
 		 return 1;
 	acpi_table_parse(ACPI_BOOT, acpi_parse_sbf);
 	/*
 	 * set sci_int and PM timer address
 	 */
 	acpi_table_parse(ACPI_FADT, acpi_parse_fadt);
 	/*
 	 * Process the Multiple APIC Description Table (MADT), if present
 	 */
 	acpi_process_madt();
 	acpi_table_parse(ACPI_HPET, acpi_parse_hpet);
 	return 0;
 }

arch/i386/kernel/mpparse.c

Diff comments View file @ 911a62d

 /*
  *	Intel Multiprocessor Specification 1.1 and 1.4
  *	compliant MP-table parsing routines.
  *
  *	(c) 1995 Alan Cox, Building #3 <alan@redhat.com>
  *	(c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
  *
  *	Fixes
  *		Erich Boleyn	:	MP v1.4 and additional changes.
  *		Alan Cox	:	Added EBDA scanning
  *		Ingo Molnar	:	various cleanups and rewrites
  *		Maciej W. Rozycki:	Bits for default MP configurations
  *		Paul Diefenbaugh:	Added full ACPI support
  */
 #include <linux/mm.h>
 #include <linux/irq.h>
 #include <linux/init.h>
 #include <linux/acpi.h>
 #include <linux/delay.h>
 #include <linux/config.h>
 #include <linux/bootmem.h>
 #include <linux/smp_lock.h>
 #include <linux/kernel_stat.h>
 #include <linux/mc146818rtc.h>
 #include <linux/bitops.h>
 #include <asm/smp.h>
 #include <asm/acpi.h>
 #include <asm/mtrr.h>
 #include <asm/mpspec.h>
 #include <asm/io_apic.h>
 #include <mach_apic.h>
 #include <mach_mpparse.h>
 #include <bios_ebda.h>
 /* Have we found an MP table */
 int smp_found_config;
 unsigned int __initdata maxcpus = NR_CPUS;
 /*
  * Various Linux-internal data structures created from the
  * MP-table.
  */
 int apic_version [MAX_APICS];
 int mp_bus_id_to_type [MAX_MP_BUSSES];
 int mp_bus_id_to_node [MAX_MP_BUSSES];
 int mp_bus_id_to_local [MAX_MP_BUSSES];
 int quad_local_to_mp_bus_id [NR_CPUS/4][4];
 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
 static int mp_current_pci_id;
 /* I/O APIC entries */
 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
 /* # of MP IRQ source entries */
 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
 /* MP IRQ source entries */
 int mp_irq_entries;
 int nr_ioapics;
 int pic_mode;
 unsigned long mp_lapic_addr;
+unsigned int def_to_bigsmp = 0;
 /* Processor that is doing the boot up */
 unsigned int boot_cpu_physical_apicid = -1U;
 /* Internal processor count */
 static unsigned int __initdata num_processors;
 /* Bitmask of physically existing CPUs */
 physid_mask_t phys_cpu_present_map;
 u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
 /*
  * Intel MP BIOS table parsing routines:
  */
 /*
  * Checksum an MP configuration block.
  */
 static int __init mpf_checksum(unsigned char *mp, int len)
 {
 	int sum = 0;
 	while (len--)
 		sum += *mp++;
 	return sum & 0xFF;
 }
 /*
  * Have to match translation table entries to main table entries by counter
  * hence the mpc_record variable .... can't see a less disgusting way of
  * doing this ....
  */
 static int mpc_record;
 static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __initdata;
 #ifdef CONFIG_X86_NUMAQ
 static int MP_valid_apicid(int apicid, int version)
 {
 	return hweight_long(apicid & 0xf) == 1 && (apicid >> 4) != 0xf;
 }
 #else
 static int MP_valid_apicid(int apicid, int version)
 {
 	if (version >= 0x14)
 		return apicid < 0xff;
 	else
 		return apicid < 0xf;
 }
 #endif
 static void __init MP_processor_info (struct mpc_config_processor *m)
 {
  	int ver, apicid;
 	physid_mask_t tmp;
 	if (!(m->mpc_cpuflag & CPU_ENABLED))
 		return;
 	apicid = mpc_apic_id(m, translation_table[mpc_record]);
 	if (m->mpc_featureflag&(1<<0))
 		Dprintk("    Floating point unit present.\n");
 	if (m->mpc_featureflag&(1<<7))
 		Dprintk("    Machine Exception supported.\n");
 	if (m->mpc_featureflag&(1<<8))
 		Dprintk("    64 bit compare & exchange supported.\n");
 	if (m->mpc_featureflag&(1<<9))
 		Dprintk("    Internal APIC present.\n");
 	if (m->mpc_featureflag&(1<<11))
 		Dprintk("    SEP present.\n");
 	if (m->mpc_featureflag&(1<<12))
 		Dprintk("    MTRR  present.\n");
 	if (m->mpc_featureflag&(1<<13))
 		Dprintk("    PGE  present.\n");
 	if (m->mpc_featureflag&(1<<14))
 		Dprintk("    MCA  present.\n");
 	if (m->mpc_featureflag&(1<<15))
 		Dprintk("    CMOV  present.\n");
 	if (m->mpc_featureflag&(1<<16))
 		Dprintk("    PAT  present.\n");
 	if (m->mpc_featureflag&(1<<17))
 		Dprintk("    PSE  present.\n");
 	if (m->mpc_featureflag&(1<<18))
 		Dprintk("    PSN  present.\n");
 	if (m->mpc_featureflag&(1<<19))
 		Dprintk("    Cache Line Flush Instruction present.\n");
 	/* 20 Reserved */
 	if (m->mpc_featureflag&(1<<21))
 		Dprintk("    Debug Trace and EMON Store present.\n");
 	if (m->mpc_featureflag&(1<<22))
 		Dprintk("    ACPI Thermal Throttle Registers  present.\n");
 	if (m->mpc_featureflag&(1<<23))
 		Dprintk("    MMX  present.\n");
 	if (m->mpc_featureflag&(1<<24))
 		Dprintk("    FXSR  present.\n");
 	if (m->mpc_featureflag&(1<<25))
 		Dprintk("    XMM  present.\n");
 	if (m->mpc_featureflag&(1<<26))
 		Dprintk("    Willamette New Instructions  present.\n");
 	if (m->mpc_featureflag&(1<<27))
 		Dprintk("    Self Snoop  present.\n");
 	if (m->mpc_featureflag&(1<<28))
 		Dprintk("    HT  present.\n");
 	if (m->mpc_featureflag&(1<<29))
 		Dprintk("    Thermal Monitor present.\n");
 	/* 30, 31 Reserved */
 	if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
 		Dprintk("    Bootup CPU\n");
 		boot_cpu_physical_apicid = m->mpc_apicid;
 	}
 	if (num_processors >= NR_CPUS) {
 		printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
 			"  Processor ignored.\n", NR_CPUS);
 		return;
 	}
 	if (num_processors >= maxcpus) {
 		printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
 			" Processor ignored.\n", maxcpus);
 		return;
 	}
 	num_processors++;
 	ver = m->mpc_apicver;
 	if (!MP_valid_apicid(apicid, ver)) {
 		printk(KERN_WARNING "Processor #%d INVALID. (Max ID: %d).\n",
 			m->mpc_apicid, MAX_APICS);
 		--num_processors;
 		return;
 	}
 	tmp = apicid_to_cpu_present(apicid);
 	physids_or(phys_cpu_present_map, phys_cpu_present_map, tmp);
 	/*
 	 * Validate version
 	 */
 	if (ver == 0x0) {
 		printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! fixing up to 0x10. (tell your hw vendor)\n", m->mpc_apicid);
 		ver = 0x10;
 	}
 	apic_version[m->mpc_apicid] = ver;
+	if ((num_processors > 8) &&
+	    APIC_XAPIC(ver) &&
+	    (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL))
+		def_to_bigsmp = 1;
+	else
+		def_to_bigsmp = 0;
 	bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
 }
 static void __init MP_bus_info (struct mpc_config_bus *m)
 {
 	char str[7];
 	memcpy(str, m->mpc_bustype, 6);
 	str[6] = 0;
 	mpc_oem_bus_info(m, str, translation_table[mpc_record]);
 	if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
 		mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
 	} else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
 		mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
 	} else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
 		mpc_oem_pci_bus(m, translation_table[mpc_record]);
 		mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
 		mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
 		mp_current_pci_id++;
 	} else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
 		mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
 	} else if (strncmp(str, BUSTYPE_NEC98, sizeof(BUSTYPE_NEC98)-1) == 0) {
 		mp_bus_id_to_type[m->mpc_busid] = MP_BUS_NEC98;
 	} else {
 		printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
 	}
 }
 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
 {
 	if (!(m->mpc_flags & MPC_APIC_USABLE))
 		return;
 	printk(KERN_INFO "I/O APIC #%d Version %d at 0x%lX.\n",
 		m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
 	if (nr_ioapics >= MAX_IO_APICS) {
 		printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n",
 			MAX_IO_APICS, nr_ioapics);
 		panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
 	}
 	if (!m->mpc_apicaddr) {
 		printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
 			" found in MP table, skipping!\n");
 		return;
 	}
 	mp_ioapics[nr_ioapics] = *m;
 	nr_ioapics++;
 }
 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
 {
 	mp_irqs [mp_irq_entries] = *m;
 	Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
 		" IRQ %02x, APIC ID %x, APIC INT %02x\n",
 			m->mpc_irqtype, m->mpc_irqflag & 3,
 			(m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
 			m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
 	if (++mp_irq_entries == MAX_IRQ_SOURCES)
 		panic("Max # of irq sources exceeded!!\n");
 }
 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
 {
 	Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
 		" IRQ %02x, APIC ID %x, APIC LINT %02x\n",
 			m->mpc_irqtype, m->mpc_irqflag & 3,
 			(m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
 			m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
 	/*
 	 * Well it seems all SMP boards in existence
 	 * use ExtINT/LVT1 == LINT0 and
 	 * NMI/LVT2 == LINT1 - the following check
 	 * will show us if this assumptions is false.
 	 * Until then we do not have to add baggage.
 	 */
 	if ((m->mpc_irqtype == mp_ExtINT) &&
 		(m->mpc_destapiclint != 0))
 			BUG();
 	if ((m->mpc_irqtype == mp_NMI) &&
 		(m->mpc_destapiclint != 1))
 			BUG();
 }
 #ifdef CONFIG_X86_NUMAQ
 static void __init MP_translation_info (struct mpc_config_translation *m)
 {
 	printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
 	if (mpc_record >= MAX_MPC_ENTRY)
 		printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
 	else
 		translation_table[mpc_record] = m; /* stash this for later */
 	if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
 		node_set_online(m->trans_quad);
 }
 /*
  * Read/parse the MPC oem tables
  */
 static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
 	unsigned short oemsize)
 {
 	int count = sizeof (*oemtable); /* the header size */
 	unsigned char *oemptr = ((unsigned char *)oemtable)+count;
 	mpc_record = 0;
 	printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
 	if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
 	{
 		printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
 			oemtable->oem_signature[0],
 			oemtable->oem_signature[1],
 			oemtable->oem_signature[2],
 			oemtable->oem_signature[3]);
 		return;
 	}
 	if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
 	{
 		printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
 		return;
 	}
 	while (count < oemtable->oem_length) {
 		switch (*oemptr) {
 			case MP_TRANSLATION:
 			{
 				struct mpc_config_translation *m=
 					(struct mpc_config_translation *)oemptr;
 				MP_translation_info(m);
 				oemptr += sizeof(*m);
 				count += sizeof(*m);
 				++mpc_record;
 				break;
 			}
 			default:
 			{
 				printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
 				return;
 			}
 		}
        }
 }
 static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
 		char *productid)
 {
 	if (strncmp(oem, "IBM NUMA", 8))
 		printk("Warning!  May not be a NUMA-Q system!\n");
 	if (mpc->mpc_oemptr)
 		smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
 				mpc->mpc_oemsize);
 }
 #endif	/* CONFIG_X86_NUMAQ */
 /*
  * Read/parse the MPC
  */
 static int __init smp_read_mpc(struct mp_config_table *mpc)
 {
 	char str[16];
 	char oem[10];
 	int count=sizeof(*mpc);
 	unsigned char *mpt=((unsigned char *)mpc)+count;
 	if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
 		printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
 			*(u32 *)mpc->mpc_signature);
 		return 0;
 	}
 	if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
 		printk(KERN_ERR "SMP mptable: checksum error!\n");
 		return 0;
 	}
 	if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
 		printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
 			mpc->mpc_spec);
 		return 0;
 	}
 	if (!mpc->mpc_lapic) {
 		printk(KERN_ERR "SMP mptable: null local APIC address!\n");
 		return 0;
 	}
 	memcpy(oem,mpc->mpc_oem,8);
 	oem[8]=0;
 	printk(KERN_INFO "OEM ID: %s ",oem);
 	memcpy(str,mpc->mpc_productid,12);
 	str[12]=0;
 	printk("Product ID: %s ",str);
 	mps_oem_check(mpc, oem, str);
 	printk("APIC at: 0x%lX\n",mpc->mpc_lapic);
 	/*
 	 * Save the local APIC address (it might be non-default) -- but only
 	 * if we're not using ACPI.
 	 */
 	if (!acpi_lapic)
 		mp_lapic_addr = mpc->mpc_lapic;
 	/*
 	 *	Now process the configuration blocks.
 	 */
 	mpc_record = 0;
 	while (count < mpc->mpc_length) {
 		switch(*mpt) {
 			case MP_PROCESSOR:
 			{
 				struct mpc_config_processor *m=
 					(struct mpc_config_processor *)mpt;
 				/* ACPI may have already provided this data */
 				if (!acpi_lapic)
 					MP_processor_info(m);
 				mpt += sizeof(*m);
 				count += sizeof(*m);
 				break;
 			}
 			case MP_BUS:
 			{
 				struct mpc_config_bus *m=
 					(struct mpc_config_bus *)mpt;
 				MP_bus_info(m);
 				mpt += sizeof(*m);
 				count += sizeof(*m);
 				break;
 			}
 			case MP_IOAPIC:
 			{
 				struct mpc_config_ioapic *m=
 					(struct mpc_config_ioapic *)mpt;
 				MP_ioapic_info(m);
 				mpt+=sizeof(*m);
 				count+=sizeof(*m);
 				break;
 			}
 			case MP_INTSRC:
 			{
 				struct mpc_config_intsrc *m=
 					(struct mpc_config_intsrc *)mpt;
 				MP_intsrc_info(m);
 				mpt+=sizeof(*m);
 				count+=sizeof(*m);
 				break;
 			}
 			case MP_LINTSRC:
 			{
 				struct mpc_config_lintsrc *m=
 					(struct mpc_config_lintsrc *)mpt;
 				MP_lintsrc_info(m);
 				mpt+=sizeof(*m);
 				count+=sizeof(*m);
 				break;
 			}
 			default:
 			{
 				count = mpc->mpc_length;
 				break;
 			}
 		}
 		++mpc_record;
 	}
 	clustered_apic_check();
 	if (!num_processors)
 		printk(KERN_ERR "SMP mptable: no processors registered!\n");
 	return num_processors;
 }
 static int __init ELCR_trigger(unsigned int irq)
 {
 	unsigned int port;
 	port = 0x4d0 + (irq >> 3);
 	return (inb(port) >> (irq & 7)) & 1;
 }
 static void __init construct_default_ioirq_mptable(int mpc_default_type)
 {
 	struct mpc_config_intsrc intsrc;
 	int i;
 	int ELCR_fallback = 0;
 	intsrc.mpc_type = MP_INTSRC;
 	intsrc.mpc_irqflag = 0;			/* conforming */
 	intsrc.mpc_srcbus = 0;
 	intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
 	intsrc.mpc_irqtype = mp_INT;
 	/*
 	 *  If true, we have an ISA/PCI system with no IRQ entries
 	 *  in the MP table. To prevent the PCI interrupts from being set up
 	 *  incorrectly, we try to use the ELCR. The sanity check to see if
 	 *  there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
 	 *  never be level sensitive, so we simply see if the ELCR agrees.
 	 *  If it does, we assume it's valid.
 	 */
 	if (mpc_default_type == 5) {
 		printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
 		if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
 			printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
 		else {
 			printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
 			ELCR_fallback = 1;
 		}
 	}
 	for (i = 0; i < 16; i++) {
 		switch (mpc_default_type) {
 		case 2:
 			if (i == 0 || i == 13)
 				continue;	/* IRQ0 & IRQ13 not connected */
 			/* fall through */
 		default:
 			if (i == 2)
 				continue;	/* IRQ2 is never connected */
 		}
 		if (ELCR_fallback) {
 			/*
 			 *  If the ELCR indicates a level-sensitive interrupt, we
 			 *  copy that information over to the MP table in the
 			 *  irqflag field (level sensitive, active high polarity).
 			 */
 			if (ELCR_trigger(i))
 				intsrc.mpc_irqflag = 13;
 			else
 				intsrc.mpc_irqflag = 0;
 		}
 		intsrc.mpc_srcbusirq = i;
 		intsrc.mpc_dstirq = i ? i : 2;		/* IRQ0 to INTIN2 */
 		MP_intsrc_info(&intsrc);
 	}
 	intsrc.mpc_irqtype = mp_ExtINT;
 	intsrc.mpc_srcbusirq = 0;
 	intsrc.mpc_dstirq = 0;				/* 8259A to INTIN0 */
 	MP_intsrc_info(&intsrc);
 }
 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
 {
 	struct mpc_config_processor processor;
 	struct mpc_config_bus bus;
 	struct mpc_config_ioapic ioapic;
 	struct mpc_config_lintsrc lintsrc;
 	int linttypes[2] = { mp_ExtINT, mp_NMI };
 	int i;
 	/*
 	 * local APIC has default address
 	 */
 	mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
 	/*
 	 * 2 CPUs, numbered 0 & 1.
 	 */
 	processor.mpc_type = MP_PROCESSOR;
 	/* Either an integrated APIC or a discrete 82489DX. */
 	processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
 	processor.mpc_cpuflag = CPU_ENABLED;
 	processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
 				   (boot_cpu_data.x86_model << 4) |
 				   boot_cpu_data.x86_mask;
 	processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
 	processor.mpc_reserved[0] = 0;
 	processor.mpc_reserved[1] = 0;
 	for (i = 0; i < 2; i++) {
 		processor.mpc_apicid = i;
 		MP_processor_info(&processor);
 	}
 	bus.mpc_type = MP_BUS;
 	bus.mpc_busid = 0;
 	switch (mpc_default_type) {
 		default:
 			printk("???\n");
 			printk(KERN_ERR "Unknown standard configuration %d\n",
 				mpc_default_type);
 			/* fall through */
 		case 1:
 		case 5:
 			memcpy(bus.mpc_bustype, "ISA   ", 6);
 			break;
 		case 2:
 		case 6:
 		case 3:
 			memcpy(bus.mpc_bustype, "EISA  ", 6);
 			break;
 		case 4:
 		case 7:
 			memcpy(bus.mpc_bustype, "MCA   ", 6);
 	}
 	MP_bus_info(&bus);
 	if (mpc_default_type > 4) {
 		bus.mpc_busid = 1;
 		memcpy(bus.mpc_bustype, "PCI   ", 6);
 		MP_bus_info(&bus);
 	}
 	ioapic.mpc_type = MP_IOAPIC;
 	ioapic.mpc_apicid = 2;
 	ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
 	ioapic.mpc_flags = MPC_APIC_USABLE;
 	ioapic.mpc_apicaddr = 0xFEC00000;
 	MP_ioapic_info(&ioapic);
 	/*
 	 * We set up most of the low 16 IO-APIC pins according to MPS rules.
 	 */
 	construct_default_ioirq_mptable(mpc_default_type);
 	lintsrc.mpc_type = MP_LINTSRC;
 	lintsrc.mpc_irqflag = 0;		/* conforming */
 	lintsrc.mpc_srcbusid = 0;
 	lintsrc.mpc_srcbusirq = 0;
 	lintsrc.mpc_destapic = MP_APIC_ALL;
 	for (i = 0; i < 2; i++) {
 		lintsrc.mpc_irqtype = linttypes[i];
 		lintsrc.mpc_destapiclint = i;
 		MP_lintsrc_info(&lintsrc);
 	}
 }
 static struct intel_mp_floating *mpf_found;
 /*
  * Scan the memory blocks for an SMP configuration block.
  */
 void __init get_smp_config (void)
 {
 	struct intel_mp_floating *mpf = mpf_found;
 	/*
 	 * ACPI may be used to obtain the entire SMP configuration or just to
 	 * enumerate/configure processors (CONFIG_ACPI_BOOT).  Note that
 	 * ACPI supports both logical (e.g. Hyper-Threading) and physical
 	 * processors, where MPS only supports physical.
 	 */
 	if (acpi_lapic && acpi_ioapic) {
 		printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
 		return;
 	}
 	else if (acpi_lapic)
 		printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
 	printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
 	if (mpf->mpf_feature2 & (1<<7)) {
 		printk(KERN_INFO "    IMCR and PIC compatibility mode.\n");
 		pic_mode = 1;
 	} else {
 		printk(KERN_INFO "    Virtual Wire compatibility mode.\n");
 		pic_mode = 0;
 	}
 	/*
 	 * Now see if we need to read further.
 	 */
 	if (mpf->mpf_feature1 != 0) {
 		printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
 		construct_default_ISA_mptable(mpf->mpf_feature1);
 	} else if (mpf->mpf_physptr) {
 		/*
 		 * Read the physical hardware table.  Anything here will
 		 * override the defaults.
 		 */
 		if (!smp_read_mpc((void *)mpf->mpf_physptr)) {
 			smp_found_config = 0;
 			printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
 			printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
 			return;
 		}
 		/*
 		 * If there are no explicit MP IRQ entries, then we are
 		 * broken.  We set up most of the low 16 IO-APIC pins to
 		 * ISA defaults and hope it will work.
 		 */
 		if (!mp_irq_entries) {
 			struct mpc_config_bus bus;
 			printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
 			bus.mpc_type = MP_BUS;
 			bus.mpc_busid = 0;
 			memcpy(bus.mpc_bustype, "ISA   ", 6);
 			MP_bus_info(&bus);
 			construct_default_ioirq_mptable(0);
 		}
 	} else
 		BUG();
 	printk(KERN_INFO "Processors: %d\n", num_processors);
 	/*
 	 * Only use the first configuration found.
 	 */
 }
 static int __init smp_scan_config (unsigned long base, unsigned long length)
 {
 	unsigned long *bp = phys_to_virt(base);
 	struct intel_mp_floating *mpf;
 	Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
 	if (sizeof(*mpf) != 16)
 		printk("Error: MPF size\n");
 	while (length > 0) {
 		mpf = (struct intel_mp_floating *)bp;
 		if ((*bp == SMP_MAGIC_IDENT) &&
 			(mpf->mpf_length == 1) &&
 			!mpf_checksum((unsigned char *)bp, 16) &&
 			((mpf->mpf_specification == 1)
 				|| (mpf->mpf_specification == 4)) ) {
 			smp_found_config = 1;
 			printk(KERN_INFO "found SMP MP-table at %08lx\n",
 						virt_to_phys(mpf));
 			reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE);
 			if (mpf->mpf_physptr) {
 				/*
 				 * We cannot access to MPC table to compute
 				 * table size yet, as only few megabytes from
 				 * the bottom is mapped now.
 				 * PC-9800's MPC table places on the very last
 				 * of physical memory; so that simply reserving
 				 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
 				 * in reserve_bootmem.
 				 */
 				unsigned long size = PAGE_SIZE;
 				unsigned long end = max_low_pfn * PAGE_SIZE;
 				if (mpf->mpf_physptr + size > end)
 					size = end - mpf->mpf_physptr;
 				reserve_bootmem(mpf->mpf_physptr, size);
 			}
 			mpf_found = mpf;
 			return 1;
 		}
 		bp += 4;
 		length -= 16;
 	}
 	return 0;
 }
 void __init find_smp_config (void)
 {
 	unsigned int address;
 	/*
 	 * FIXME: Linux assumes you have 640K of base ram..
 	 * this continues the error...
 	 *
 	 * 1) Scan the bottom 1K for a signature
 	 * 2) Scan the top 1K of base RAM
 	 * 3) Scan the 64K of bios
 	 */
 	if (smp_scan_config(0x0,0x400) ||
 		smp_scan_config(639*0x400,0x400) ||
 			smp_scan_config(0xF0000,0x10000))
 		return;
 	/*
 	 * If it is an SMP machine we should know now, unless the
 	 * configuration is in an EISA/MCA bus machine with an
 	 * extended bios data area.
 	 *
 	 * there is a real-mode segmented pointer pointing to the
 	 * 4K EBDA area at 0x40E, calculate and scan it here.
 	 *
 	 * NOTE! There are Linux loaders that will corrupt the EBDA
 	 * area, and as such this kind of SMP config may be less
 	 * trustworthy, simply because the SMP table may have been
 	 * stomped on during early boot. These loaders are buggy and
 	 * should be fixed.
 	 *
 	 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
 	 */
 	address = get_bios_ebda();
 	if (address)
 		smp_scan_config(address, 0x400);
 }
 /* --------------------------------------------------------------------------
                             ACPI-based MP Configuration
    -------------------------------------------------------------------------- */
 #ifdef CONFIG_ACPI_BOOT
 void __init mp_register_lapic_address (
 	u64			address)
 {
 	mp_lapic_addr = (unsigned long) address;
 	set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
 	if (boot_cpu_physical_apicid == -1U)
 		boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
 	Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
 }
 void __init mp_register_lapic (
 	u8			id,
 	u8			enabled)
 {
 	struct mpc_config_processor processor;
 	int			boot_cpu = 0;
 	if (MAX_APICS - id <= 0) {
 		printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
 			id, MAX_APICS);
 		return;
 	}
 	if (id == boot_cpu_physical_apicid)
 		boot_cpu = 1;
 	processor.mpc_type = MP_PROCESSOR;
 	processor.mpc_apicid = id;
 	processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
 	processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
 	processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
 	processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
 		(boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
 	processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
 	processor.mpc_reserved[0] = 0;
 	processor.mpc_reserved[1] = 0;
 	MP_processor_info(&processor);
 }
 #if defined(CONFIG_X86_IO_APIC) && (defined(CONFIG_ACPI_INTERPRETER) || defined(CONFIG_ACPI_BOOT))
 #define MP_ISA_BUS		0
 #define MP_MAX_IOAPIC_PIN	127
 static struct mp_ioapic_routing {
 	int			apic_id;
 	int			gsi_base;
 	int			gsi_end;
 	u32			pin_programmed[4];
 } mp_ioapic_routing[MAX_IO_APICS];
 static int mp_find_ioapic (
 	int			gsi)
 {
 	int			i = 0;
 	/* Find the IOAPIC that manages this GSI. */
 	for (i = 0; i < nr_ioapics; i++) {
 		if ((gsi >= mp_ioapic_routing[i].gsi_base)
 			&& (gsi <= mp_ioapic_routing[i].gsi_end))
 			return i;
 	}
 	printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
 	return -1;
 }
 void __init mp_register_ioapic (
 	u8			id,
 	u32			address,
 	u32			gsi_base)
 {
 	int			idx = 0;
 	if (nr_ioapics >= MAX_IO_APICS) {
 		printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
 			"(found %d)\n", MAX_IO_APICS, nr_ioapics);
 		panic("Recompile kernel with bigger MAX_IO_APICS!\n");
 	}
 	if (!address) {
 		printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
 			" found in MADT table, skipping!\n");
 		return;
 	}
 	idx = nr_ioapics++;
 	mp_ioapics[idx].mpc_type = MP_IOAPIC;
 	mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
 	mp_ioapics[idx].mpc_apicaddr = address;
 	set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
 	if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 < 15))
 		mp_ioapics[idx].mpc_apicid = io_apic_get_unique_id(idx, id);
 	else
 		mp_ioapics[idx].mpc_apicid = id;
 	mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
 	/*
 	 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
 	 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
 	 */
 	mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
 	mp_ioapic_routing[idx].gsi_base = gsi_base;
 	mp_ioapic_routing[idx].gsi_end = gsi_base +
 		io_apic_get_redir_entries(idx);
 	printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%lx, "
 		"GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
 		mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
 		mp_ioapic_routing[idx].gsi_base,
 		mp_ioapic_routing[idx].gsi_end);
 	return;
 }
 void __init mp_override_legacy_irq (
 	u8			bus_irq,
 	u8			polarity,
 	u8			trigger,
 	u32			gsi)
 {
 	struct mpc_config_intsrc intsrc;
 	int			ioapic = -1;
 	int			pin = -1;
 	/*
 	 * Convert 'gsi' to 'ioapic.pin'.
 	 */
 	ioapic = mp_find_ioapic(gsi);
 	if (ioapic < 0)
 		return;
 	pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
 	/*
 	 * TBD: This check is for faulty timer entries, where the override
 	 *      erroneously sets the trigger to level, resulting in a HUGE
 	 *      increase of timer interrupts!
 	 */
 	if ((bus_irq == 0) && (trigger == 3))
 		trigger = 1;
 	intsrc.mpc_type = MP_INTSRC;
 	intsrc.mpc_irqtype = mp_INT;
 	intsrc.mpc_irqflag = (trigger << 2) | polarity;
 	intsrc.mpc_srcbus = MP_ISA_BUS;
 	intsrc.mpc_srcbusirq = bus_irq;				       /* IRQ */
 	intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;	   /* APIC ID */
 	intsrc.mpc_dstirq = pin;				    /* INTIN# */
 	Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
 		intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
 		(intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
 		intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
 	mp_irqs[mp_irq_entries] = intsrc;
 	if (++mp_irq_entries == MAX_IRQ_SOURCES)
 		panic("Max # of irq sources exceeded!\n");
 	return;
 }
 int es7000_plat;
 void __init mp_config_acpi_legacy_irqs (void)
 {
 	struct mpc_config_intsrc intsrc;
 	int			i = 0;
 	int			ioapic = -1;
 	/*
 	 * Fabricate the legacy ISA bus (bus #31).
 	 */
 	mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
 	Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
 	/*
 	 * Older generations of ES7000 have no legacy identity mappings
 	 */
 	if (es7000_plat == 1)
 		return;
 	/*
 	 * Locate the IOAPIC that manages the ISA IRQs (0-15).
 	 */
 	ioapic = mp_find_ioapic(0);
 	if (ioapic < 0)
 		return;
 	intsrc.mpc_type = MP_INTSRC;
 	intsrc.mpc_irqflag = 0;					/* Conforming */
 	intsrc.mpc_srcbus = MP_ISA_BUS;
 	intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
 	/*
 	 * Use the default configuration for the IRQs 0-15.  Unless
 	 * overriden by (MADT) interrupt source override entries.
 	 */
 	for (i = 0; i < 16; i++) {
 		int idx;
 		for (idx = 0; idx < mp_irq_entries; idx++) {
 			struct mpc_config_intsrc *irq = mp_irqs + idx;
 			/* Do we already have a mapping for this ISA IRQ? */
 			if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
 				break;
 			/* Do we already have a mapping for this IOAPIC pin */
 			if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
 				(irq->mpc_dstirq == i))
 				break;
 		}
 		if (idx != mp_irq_entries) {
 			printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
 			continue;			/* IRQ already used */
 		}
 		intsrc.mpc_irqtype = mp_INT;
 		intsrc.mpc_srcbusirq = i;		   /* Identity mapped */
 		intsrc.mpc_dstirq = i;
 		Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
 			"%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
 			(intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
 			intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
 			intsrc.mpc_dstirq);
 		mp_irqs[mp_irq_entries] = intsrc;
 		if (++mp_irq_entries == MAX_IRQ_SOURCES)
 			panic("Max # of irq sources exceeded!\n");
 	}
 }
 #define MAX_GSI_NUM	4096
 int mp_register_gsi (u32 gsi, int edge_level, int active_high_low)
 {
 	int			ioapic = -1;
 	int			ioapic_pin = 0;
 	int			idx, bit = 0;
 	static int		pci_irq = 16;
 	/*
 	 * Mapping between Global System Interrups, which
 	 * represent all possible interrupts, and IRQs
 	 * assigned to actual devices.
 	 */
 	static int		gsi_to_irq[MAX_GSI_NUM];
 #ifdef CONFIG_ACPI_BUS
 	/* Don't set up the ACPI SCI because it's already set up */
 	if (acpi_fadt.sci_int == gsi)
 		return gsi;
 #endif
 	ioapic = mp_find_ioapic(gsi);
 	if (ioapic < 0) {
 		printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
 		return gsi;
 	}
 	ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
 	if (ioapic_renumber_irq)
 		gsi = ioapic_renumber_irq(ioapic, gsi);
 	/*
 	 * Avoid pin reprogramming.  PRTs typically include entries
 	 * with redundant pin->gsi mappings (but unique PCI devices);
 	 * we only program the IOAPIC on the first.
 	 */
 	bit = ioapic_pin % 32;
 	idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
 	if (idx > 3) {
 		printk(KERN_ERR "Invalid reference to IOAPIC pin "
 			"%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
 			ioapic_pin);
 		return gsi;
 	}
 	if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
 		Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
 			mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
 		return gsi_to_irq[gsi];
 	}
 	mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
 	if (edge_level) {
 		/*
 		 * For PCI devices assign IRQs in order, avoiding gaps
 		 * due to unused I/O APIC pins.
 		 */
 		int irq = gsi;
 		if (gsi < MAX_GSI_NUM) {
 			if (gsi > 15)
 				gsi = pci_irq++;
 #ifdef CONFIG_ACPI_BUS
 			/*
 			 * Don't assign IRQ used by ACPI SCI
 			 */
 			if (gsi == acpi_fadt.sci_int)
 				gsi = pci_irq++;
 #endif
 			gsi_to_irq[irq] = gsi;
 		} else {
 			printk(KERN_ERR "GSI %u is too high\n", gsi);
 			return gsi;
 		}
 	}
 	io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
 		    edge_level == ACPI_EDGE_SENSITIVE ? 0 : 1,
 		    active_high_low == ACPI_ACTIVE_HIGH ? 0 : 1);
 	return gsi;
 }
 #endif /*CONFIG_X86_IO_APIC && (CONFIG_ACPI_INTERPRETER || CONFIG_ACPI_BOOT)*/
 #endif /*CONFIG_ACPI_BOOT*/

arch/i386/kernel/setup.c

Diff comments View file @ 911a62d

 /*
  *  linux/arch/i386/kernel/setup.c
  *
  *  Copyright (C) 1995  Linus Torvalds
  *
  *  Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
  *
  *  Memory region support
  *	David Parsons <orc@pell.chi.il.us>, July-August 1999
  *
  *  Added E820 sanitization routine (removes overlapping memory regions);
  *  Brian Moyle <bmoyle@mvista.com>, February 2001
  *
  * Moved CPU detection code to cpu/${cpu}.c
  *    Patrick Mochel <mochel@osdl.org>, March 2002
  *
  *  Provisions for empty E820 memory regions (reported by certain BIOSes).
  *  Alex Achenbach <xela@slit.de>, December 2002.
  *
  */
 /*
  * This file handles the architecture-dependent parts of initialization
  */
 #include <linux/config.h>
 #include <linux/sched.h>
 #include <linux/mm.h>
 #include <linux/mmzone.h>
 #include <linux/tty.h>
 #include <linux/ioport.h>
 #include <linux/acpi.h>
 #include <linux/apm_bios.h>
 #include <linux/initrd.h>
 #include <linux/bootmem.h>
 #include <linux/seq_file.h>
 #include <linux/console.h>
 #include <linux/mca.h>
 #include <linux/root_dev.h>
 #include <linux/highmem.h>
 #include <linux/module.h>
 #include <linux/efi.h>
 #include <linux/init.h>
 #include <linux/edd.h>
 #include <linux/nodemask.h>
 #include <linux/kexec.h>
 #include <linux/crash_dump.h>
 #include <video/edid.h>
 #include <asm/apic.h>
 #include <asm/e820.h>
 #include <asm/mpspec.h>
 #include <asm/setup.h>
 #include <asm/arch_hooks.h>
 #include <asm/sections.h>
 #include <asm/io_apic.h>
 #include <asm/ist.h>
 #include <asm/io.h>
 #include "setup_arch_pre.h"
 #include <bios_ebda.h>
 /* Forward Declaration. */
 void __init find_max_pfn(void);
 /* This value is set up by the early boot code to point to the value
    immediately after the boot time page tables.  It contains a *physical*
    address, and must not be in the .bss segment! */
 unsigned long init_pg_tables_end __initdata = ~0UL;
 int disable_pse __devinitdata = 0;
 /*
  * Machine setup..
  */
 #ifdef CONFIG_EFI
 int efi_enabled = 0;
 EXPORT_SYMBOL(efi_enabled);
 #endif
 /* cpu data as detected by the assembly code in head.S */
 struct cpuinfo_x86 new_cpu_data __initdata = { 0, 0, 0, 0, -1, 1, 0, 0, -1 };
 /* common cpu data for all cpus */
 struct cpuinfo_x86 boot_cpu_data = { 0, 0, 0, 0, -1, 1, 0, 0, -1 };
 EXPORT_SYMBOL(boot_cpu_data);
 unsigned long mmu_cr4_features;
 #ifdef	CONFIG_ACPI_INTERPRETER
 	int acpi_disabled = 0;
 #else
 	int acpi_disabled = 1;
 #endif
 EXPORT_SYMBOL(acpi_disabled);
 #ifdef	CONFIG_ACPI_BOOT
 int __initdata acpi_force = 0;
 extern acpi_interrupt_flags	acpi_sci_flags;
 #endif
 /* for MCA, but anyone else can use it if they want */
 unsigned int machine_id;
 #ifdef CONFIG_MCA
 EXPORT_SYMBOL(machine_id);
 #endif
 unsigned int machine_submodel_id;
 unsigned int BIOS_revision;
 unsigned int mca_pentium_flag;
 /* For PCI or other memory-mapped resources */
 unsigned long pci_mem_start = 0x10000000;
 #ifdef CONFIG_PCI
 EXPORT_SYMBOL(pci_mem_start);
 #endif
 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
 int bootloader_type;
 /* user-defined highmem size */
 static unsigned int highmem_pages = -1;
 /*
  * Setup options
  */
 struct drive_info_struct { char dummy[32]; } drive_info;
 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_HD) || \
     defined(CONFIG_BLK_DEV_IDE_MODULE) || defined(CONFIG_BLK_DEV_HD_MODULE)
 EXPORT_SYMBOL(drive_info);
 #endif
 struct screen_info screen_info;
 #ifdef CONFIG_VT
 EXPORT_SYMBOL(screen_info);
 #endif
 struct apm_info apm_info;
 EXPORT_SYMBOL(apm_info);
 struct sys_desc_table_struct {
 	unsigned short length;
 	unsigned char table[0];
 };
 struct edid_info edid_info;
 struct ist_info ist_info;
 #if defined(CONFIG_X86_SPEEDSTEP_SMI) || \
 	defined(CONFIG_X86_SPEEDSTEP_SMI_MODULE)
 EXPORT_SYMBOL(ist_info);
 #endif
 struct e820map e820;
 extern void early_cpu_init(void);
 extern void dmi_scan_machine(void);
 extern void generic_apic_probe(char *);
 extern int root_mountflags;
 unsigned long saved_videomode;
 #define RAMDISK_IMAGE_START_MASK  	0x07FF
 #define RAMDISK_PROMPT_FLAG		0x8000
 #define RAMDISK_LOAD_FLAG		0x4000
 static char command_line[COMMAND_LINE_SIZE];
 unsigned char __initdata boot_params[PARAM_SIZE];
 static struct resource data_resource = {
 	.name	= "Kernel data",
 	.start	= 0,
 	.end	= 0,
 	.flags	= IORESOURCE_BUSY | IORESOURCE_MEM
 };
 static struct resource code_resource = {
 	.name	= "Kernel code",
 	.start	= 0,
 	.end	= 0,
 	.flags	= IORESOURCE_BUSY | IORESOURCE_MEM
 };
 static struct resource system_rom_resource = {
 	.name	= "System ROM",
 	.start	= 0xf0000,
 	.end	= 0xfffff,
 	.flags	= IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
 };
 static struct resource extension_rom_resource = {
 	.name	= "Extension ROM",
 	.start	= 0xe0000,
 	.end	= 0xeffff,
 	.flags	= IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
 };
 static struct resource adapter_rom_resources[] = { {
 	.name 	= "Adapter ROM",
 	.start	= 0xc8000,
 	.end	= 0,
 	.flags	= IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
 }, {
 	.name 	= "Adapter ROM",
 	.start	= 0,
 	.end	= 0,
 	.flags	= IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
 }, {
 	.name 	= "Adapter ROM",
 	.start	= 0,
 	.end	= 0,
 	.flags	= IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
 }, {
 	.name 	= "Adapter ROM",
 	.start	= 0,
 	.end	= 0,
 	.flags	= IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
 }, {
 	.name 	= "Adapter ROM",
 	.start	= 0,
 	.end	= 0,
 	.flags	= IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
 }, {
 	.name 	= "Adapter ROM",
 	.start	= 0,
 	.end	= 0,
 	.flags	= IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
 } };
 #define ADAPTER_ROM_RESOURCES \
 	(sizeof adapter_rom_resources / sizeof adapter_rom_resources[0])
 static struct resource video_rom_resource = {
 	.name 	= "Video ROM",
 	.start	= 0xc0000,
 	.end	= 0xc7fff,
 	.flags	= IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM
 };
 static struct resource video_ram_resource = {
 	.name	= "Video RAM area",
 	.start	= 0xa0000,
 	.end	= 0xbffff,
 	.flags	= IORESOURCE_BUSY | IORESOURCE_MEM
 };
 static struct resource standard_io_resources[] = { {
 	.name	= "dma1",
 	.start	= 0x0000,
 	.end	= 0x001f,
 	.flags	= IORESOURCE_BUSY | IORESOURCE_IO
 }, {
 	.name	= "pic1",
 	.start	= 0x0020,
 	.end	= 0x0021,
 	.flags	= IORESOURCE_BUSY | IORESOURCE_IO
 }, {
 	.name   = "timer0",
 	.start	= 0x0040,
 	.end    = 0x0043,
 	.flags  = IORESOURCE_BUSY | IORESOURCE_IO
 }, {
 	.name   = "timer1",
 	.start  = 0x0050,
 	.end    = 0x0053,
 	.flags	= IORESOURCE_BUSY | IORESOURCE_IO
 }, {
 	.name	= "keyboard",
 	.start	= 0x0060,
 	.end	= 0x006f,
 	.flags	= IORESOURCE_BUSY | IORESOURCE_IO
 }, {
 	.name	= "dma page reg",
 	.start	= 0x0080,
 	.end	= 0x008f,
 	.flags	= IORESOURCE_BUSY | IORESOURCE_IO
 }, {
 	.name	= "pic2",
 	.start	= 0x00a0,
 	.end	= 0x00a1,
 	.flags	= IORESOURCE_BUSY | IORESOURCE_IO
 }, {
 	.name	= "dma2",
 	.start	= 0x00c0,
 	.end	= 0x00df,
 	.flags	= IORESOURCE_BUSY | IORESOURCE_IO
 }, {
 	.name	= "fpu",
 	.start	= 0x00f0,
 	.end	= 0x00ff,
 	.flags	= IORESOURCE_BUSY | IORESOURCE_IO
 } };
 #define STANDARD_IO_RESOURCES \
 	(sizeof standard_io_resources / sizeof standard_io_resources[0])
 #define romsignature(x) (*(unsigned short *)(x) == 0xaa55)
 static int __init romchecksum(unsigned char *rom, unsigned long length)
 {
 	unsigned char *p, sum = 0;
 	for (p = rom; p < rom + length; p++)
 		sum += *p;
 	return sum == 0;
 }
 static void __init probe_roms(void)
 {
 	unsigned long start, length, upper;
 	unsigned char *rom;
 	int	      i;
 	/* video rom */
 	upper = adapter_rom_resources[0].start;
 	for (start = video_rom_resource.start; start < upper; start += 2048) {
 		rom = isa_bus_to_virt(start);
 		if (!romsignature(rom))
 			continue;
 		video_rom_resource.start = start;
 		/* 0 < length <= 0x7f * 512, historically */
 		length = rom[2] * 512;
 		/* if checksum okay, trust length byte */
 		if (length && romchecksum(rom, length))
 			video_rom_resource.end = start + length - 1;
 		request_resource(&iomem_resource, &video_rom_resource);
 		break;
 	}
 	start = (video_rom_resource.end + 1 + 2047) & ~2047UL;
 	if (start < upper)
 		start = upper;
 	/* system rom */
 	request_resource(&iomem_resource, &system_rom_resource);
 	upper = system_rom_resource.start;
 	/* check for extension rom (ignore length byte!) */
 	rom = isa_bus_to_virt(extension_rom_resource.start);
 	if (romsignature(rom)) {
 		length = extension_rom_resource.end - extension_rom_resource.start + 1;
 		if (romchecksum(rom, length)) {
 			request_resource(&iomem_resource, &extension_rom_resource);
 			upper = extension_rom_resource.start;
 		}
 	}
 	/* check for adapter roms on 2k boundaries */
 	for (i = 0; i < ADAPTER_ROM_RESOURCES && start < upper; start += 2048) {
 		rom = isa_bus_to_virt(start);
 		if (!romsignature(rom))
 			continue;
 		/* 0 < length <= 0x7f * 512, historically */
 		length = rom[2] * 512;
 		/* but accept any length that fits if checksum okay */
 		if (!length || start + length > upper || !romchecksum(rom, length))
 			continue;
 		adapter_rom_resources[i].start = start;
 		adapter_rom_resources[i].end = start + length - 1;
 		request_resource(&iomem_resource, &adapter_rom_resources[i]);
 		start = adapter_rom_resources[i++].end & ~2047UL;
 	}
 }
 static void __init limit_regions(unsigned long long size)
 {
 	unsigned long long current_addr = 0;
 	int i;
 	if (efi_enabled) {
 		efi_memory_desc_t *md;
 		void *p;
 		for (p = memmap.map, i = 0; p < memmap.map_end;
 			p += memmap.desc_size, i++) {
 			md = p;
 			current_addr = md->phys_addr + (md->num_pages << 12);
 			if (md->type == EFI_CONVENTIONAL_MEMORY) {
 				if (current_addr >= size) {
 					md->num_pages -=
 						(((current_addr-size) + PAGE_SIZE-1) >> PAGE_SHIFT);
 					memmap.nr_map = i + 1;
 					return;
 				}
 			}
 		}
 	}
 	for (i = 0; i < e820.nr_map; i++) {
 		if (e820.map[i].type == E820_RAM) {
 			current_addr = e820.map[i].addr + e820.map[i].size;
 			if (current_addr >= size) {
 				e820.map[i].size -= current_addr-size;
 				e820.nr_map = i + 1;
 				return;
 			}
 		}
 	}
 }
 static void __init add_memory_region(unsigned long long start,
                                   unsigned long long size, int type)
 {
 	int x;
 	if (!efi_enabled) {
        		x = e820.nr_map;
 		if (x == E820MAX) {
 		    printk(KERN_ERR "Ooops! Too many entries in the memory map!\n");
 		    return;
 		}
 		e820.map[x].addr = start;
 		e820.map[x].size = size;
 		e820.map[x].type = type;
 		e820.nr_map++;
 	}
 } /* add_memory_region */
 #define E820_DEBUG	1
 static void __init print_memory_map(char *who)
 {
 	int i;
 	for (i = 0; i < e820.nr_map; i++) {
 		printk(" %s: %016Lx - %016Lx ", who,
 			e820.map[i].addr,
 			e820.map[i].addr + e820.map[i].size);
 		switch (e820.map[i].type) {
 		case E820_RAM:	printk("(usable)\n");
 				break;
 		case E820_RESERVED:
 				printk("(reserved)\n");
 				break;
 		case E820_ACPI:
 				printk("(ACPI data)\n");
 				break;
 		case E820_NVS:
 				printk("(ACPI NVS)\n");
 				break;
 		default:	printk("type %lu\n", e820.map[i].type);
 				break;
 		}
 	}
 }
 /*
  * Sanitize the BIOS e820 map.
  *
  * Some e820 responses include overlapping entries.  The following
  * replaces the original e820 map with a new one, removing overlaps.
  *
  */
 struct change_member {
 	struct e820entry *pbios; /* pointer to original bios entry */
 	unsigned long long addr; /* address for this change point */
 };
 static struct change_member change_point_list[2*E820MAX] __initdata;
 static struct change_member *change_point[2*E820MAX] __initdata;
 static struct e820entry *overlap_list[E820MAX] __initdata;
 static struct e820entry new_bios[E820MAX] __initdata;
 static int __init sanitize_e820_map(struct e820entry * biosmap, char * pnr_map)
 {
 	struct change_member *change_tmp;
 	unsigned long current_type, last_type;
 	unsigned long long last_addr;
 	int chgidx, still_changing;
 	int overlap_entries;
 	int new_bios_entry;
 	int old_nr, new_nr, chg_nr;
 	int i;
 	/*
 		Visually we're performing the following (1,2,3,4 = memory types)...
 		Sample memory map (w/overlaps):
 		   ____22__________________
 		   ______________________4_
 		   ____1111________________
 		   _44_____________________
 		   11111111________________
 		   ____________________33__
 		   ___________44___________
 		   __________33333_________
 		   ______________22________
 		   ___________________2222_
 		   _________111111111______
 		   _____________________11_
 		   _________________4______
 		Sanitized equivalent (no overlap):
 		   1_______________________
 		   _44_____________________
 		   ___1____________________
 		   ____22__________________
 		   ______11________________
 		   _________1______________
 		   __________3_____________
 		   ___________44___________
 		   _____________33_________
 		   _______________2________
 		   ________________1_______
 		   _________________4______
 		   ___________________2____
 		   ____________________33__
 		   ______________________4_
 	*/
 	/* if there's only one memory region, don't bother */
 	if (*pnr_map < 2)
 		return -1;
 	old_nr = *pnr_map;
 	/* bail out if we find any unreasonable addresses in bios map */
 	for (i=0; i<old_nr; i++)
 		if (biosmap[i].addr + biosmap[i].size < biosmap[i].addr)
 			return -1;
 	/* create pointers for initial change-point information (for sorting) */
 	for (i=0; i < 2*old_nr; i++)
 		change_point[i] = &change_point_list[i];
 	/* record all known change-points (starting and ending addresses),
 	   omitting those that are for empty memory regions */
 	chgidx = 0;
 	for (i=0; i < old_nr; i++)	{
 		if (biosmap[i].size != 0) {
 			change_point[chgidx]->addr = biosmap[i].addr;
 			change_point[chgidx++]->pbios = &biosmap[i];
 			change_point[chgidx]->addr = biosmap[i].addr + biosmap[i].size;
 			change_point[chgidx++]->pbios = &biosmap[i];
 		}
 	}
 	chg_nr = chgidx;    	/* true number of change-points */
 	/* sort change-point list by memory addresses (low -> high) */
 	still_changing = 1;
 	while (still_changing)	{
 		still_changing = 0;
 		for (i=1; i < chg_nr; i++)  {
 			/* if <current_addr> > <last_addr>, swap */
 			/* or, if current=<start_addr> & last=<end_addr>, swap */
 			if ((change_point[i]->addr < change_point[i-1]->addr) ||
 				((change_point[i]->addr == change_point[i-1]->addr) &&
 				 (change_point[i]->addr == change_point[i]->pbios->addr) &&
 				 (change_point[i-1]->addr != change_point[i-1]->pbios->addr))
 			   )
 			{
 				change_tmp = change_point[i];
 				change_point[i] = change_point[i-1];
 				change_point[i-1] = change_tmp;
 				still_changing=1;
 			}
 		}
 	}
 	/* create a new bios memory map, removing overlaps */
 	overlap_entries=0;	 /* number of entries in the overlap table */
 	new_bios_entry=0;	 /* index for creating new bios map entries */
 	last_type = 0;		 /* start with undefined memory type */
 	last_addr = 0;		 /* start with 0 as last starting address */
 	/* loop through change-points, determining affect on the new bios map */
 	for (chgidx=0; chgidx < chg_nr; chgidx++)
 	{
 		/* keep track of all overlapping bios entries */
 		if (change_point[chgidx]->addr == change_point[chgidx]->pbios->addr)
 		{
 			/* add map entry to overlap list (> 1 entry implies an overlap) */
 			overlap_list[overlap_entries++]=change_point[chgidx]->pbios;
 		}
 		else
 		{
 			/* remove entry from list (order independent, so swap with last) */
 			for (i=0; i<overlap_entries; i++)
 			{
 				if (overlap_list[i] == change_point[chgidx]->pbios)
 					overlap_list[i] = overlap_list[overlap_entries-1];
 			}
 			overlap_entries--;
 		}
 		/* if there are overlapping entries, decide which "type" to use */
 		/* (larger value takes precedence -- 1=usable, 2,3,4,4+=unusable) */
 		current_type = 0;
 		for (i=0; i<overlap_entries; i++)
 			if (overlap_list[i]->type > current_type)
 				current_type = overlap_list[i]->type;
 		/* continue building up new bios map based on this information */
 		if (current_type != last_type)	{
 			if (last_type != 0)	 {
 				new_bios[new_bios_entry].size =
 					change_point[chgidx]->addr - last_addr;
 				/* move forward only if the new size was non-zero */
 				if (new_bios[new_bios_entry].size != 0)
 					if (++new_bios_entry >= E820MAX)
 						break; 	/* no more space left for new bios entries */
 			}
 			if (current_type != 0)	{
 				new_bios[new_bios_entry].addr = change_point[chgidx]->addr;
 				new_bios[new_bios_entry].type = current_type;
 				last_addr=change_point[chgidx]->addr;
 			}
 			last_type = current_type;
 		}
 	}
 	new_nr = new_bios_entry;   /* retain count for new bios entries */
 	/* copy new bios mapping into original location */
 	memcpy(biosmap, new_bios, new_nr*sizeof(struct e820entry));
 	*pnr_map = new_nr;
 	return 0;
 }
 /*
  * Copy the BIOS e820 map into a safe place.
  *
  * Sanity-check it while we're at it..
  *
  * If we're lucky and live on a modern system, the setup code
  * will have given us a memory map that we can use to properly
  * set up memory.  If we aren't, we'll fake a memory map.
  *
  * We check to see that the memory map contains at least 2 elements
  * before we'll use it, because the detection code in setup.S may
  * not be perfect and most every PC known to man has two memory
  * regions: one from 0 to 640k, and one from 1mb up.  (The IBM
  * thinkpad 560x, for example, does not cooperate with the memory
  * detection code.)
  */
 static int __init copy_e820_map(struct e820entry * biosmap, int nr_map)
 {
 	/* Only one memory region (or negative)? Ignore it */
 	if (nr_map < 2)
 		return -1;
 	do {
 		unsigned long long start = biosmap->addr;
 		unsigned long long size = biosmap->size;
 		unsigned long long end = start + size;
 		unsigned long type = biosmap->type;
 		/* Overflow in 64 bits? Ignore the memory map. */
 		if (start > end)
 			return -1;
 		/*
 		 * Some BIOSes claim RAM in the 640k - 1M region.
 		 * Not right. Fix it up.
 		 */
 		if (type == E820_RAM) {
 			if (start < 0x100000ULL && end > 0xA0000ULL) {
 				if (start < 0xA0000ULL)
 					add_memory_region(start, 0xA0000ULL-start, type);
 				if (end <= 0x100000ULL)
 					continue;
 				start = 0x100000ULL;
 				size = end - start;
 			}
 		}
 		add_memory_region(start, size, type);
 	} while (biosmap++,--nr_map);
 	return 0;
 }
 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
 struct edd edd;
 #ifdef CONFIG_EDD_MODULE
 EXPORT_SYMBOL(edd);
 #endif
 /**
  * copy_edd() - Copy the BIOS EDD information
  *              from boot_params into a safe place.
  *
  */
 static inline void copy_edd(void)
 {
      memcpy(edd.mbr_signature, EDD_MBR_SIGNATURE, sizeof(edd.mbr_signature));
      memcpy(edd.edd_info, EDD_BUF, sizeof(edd.edd_info));
      edd.mbr_signature_nr = EDD_MBR_SIG_NR;
      edd.edd_info_nr = EDD_NR;
 }
 #else
 static inline void copy_edd(void)
 {
 }
 #endif
 /*
  * Do NOT EVER look at the BIOS memory size location.
  * It does not work on many machines.
  */
 #define LOWMEMSIZE()	(0x9f000)
 static void __init parse_cmdline_early (char ** cmdline_p)
 {
 	char c = ' ', *to = command_line, *from = saved_command_line;
 	int len = 0;
 	int userdef = 0;
 	/* Save unparsed command line copy for /proc/cmdline */
 	saved_command_line[COMMAND_LINE_SIZE-1] = '\0';
 	for (;;) {
 		if (c != ' ')
 			goto next_char;
 		/*
 		 * "mem=nopentium" disables the 4MB page tables.
 		 * "mem=XXX[kKmM]" defines a memory region from HIGH_MEM
 		 * to <mem>, overriding the bios size.
 		 * "memmap=XXX[KkmM]@XXX[KkmM]" defines a memory region from
 		 * <start> to <start>+<mem>, overriding the bios size.
 		 *
 		 * HPA tells me bootloaders need to parse mem=, so no new
 		 * option should be mem=  [also see Documentation/i386/boot.txt]
 		 */
 		if (!memcmp(from, "mem=", 4)) {
 			if (to != command_line)
 				to--;
 			if (!memcmp(from+4, "nopentium", 9)) {
 				from += 9+4;
 				clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability);
 				disable_pse = 1;
 			} else {
 				/* If the user specifies memory size, we
 				 * limit the BIOS-provided memory map to
 				 * that size. exactmap can be used to specify
 				 * the exact map. mem=number can be used to
 				 * trim the existing memory map.
 				 */
 				unsigned long long mem_size;
 				mem_size = memparse(from+4, &from);
 				limit_regions(mem_size);
 				userdef=1;
 			}
 		}
 		else if (!memcmp(from, "memmap=", 7)) {
 			if (to != command_line)
 				to--;
 			if (!memcmp(from+7, "exactmap", 8)) {
 #ifdef CONFIG_CRASH_DUMP
 				/* If we are doing a crash dump, we
 				 * still need to know the real mem
 				 * size before original memory map is
 				 * reset.
 				 */
 				find_max_pfn();
 				saved_max_pfn = max_pfn;
 #endif
 				from += 8+7;
 				e820.nr_map = 0;
 				userdef = 1;
 			} else {
 				/* If the user specifies memory size, we
 				 * limit the BIOS-provided memory map to
 				 * that size. exactmap can be used to specify
 				 * the exact map. mem=number can be used to
 				 * trim the existing memory map.
 				 */
 				unsigned long long start_at, mem_size;
 				mem_size = memparse(from+7, &from);
 				if (*from == '@') {
 					start_at = memparse(from+1, &from);
 					add_memory_region(start_at, mem_size, E820_RAM);
 				} else if (*from == '#') {
 					start_at = memparse(from+1, &from);
 					add_memory_region(start_at, mem_size, E820_ACPI);
 				} else if (*from == '$') {
 					start_at = memparse(from+1, &from);
 					add_memory_region(start_at, mem_size, E820_RESERVED);
 				} else {
 					limit_regions(mem_size);
 					userdef=1;
 				}
 			}
 		}
 		else if (!memcmp(from, "noexec=", 7))
 			noexec_setup(from + 7);
 #ifdef  CONFIG_X86_SMP
 		/*
 		 * If the BIOS enumerates physical processors before logical,
 		 * maxcpus=N at enumeration-time can be used to disable HT.
 		 */
 		else if (!memcmp(from, "maxcpus=", 8)) {
 			extern unsigned int maxcpus;
 			maxcpus = simple_strtoul(from + 8, NULL, 0);
 		}
 #endif
 #ifdef CONFIG_ACPI_BOOT
 		/* "acpi=off" disables both ACPI table parsing and interpreter */
 		else if (!memcmp(from, "acpi=off", 8)) {
 			disable_acpi();
 		}
 		/* acpi=force to over-ride black-list */
 		else if (!memcmp(from, "acpi=force", 10)) {
 			acpi_force = 1;
 			acpi_ht = 1;
 			acpi_disabled = 0;
 		}
 		/* acpi=strict disables out-of-spec workarounds */
 		else if (!memcmp(from, "acpi=strict", 11)) {
 			acpi_strict = 1;
 		}
 		/* Limit ACPI just to boot-time to enable HT */
 		else if (!memcmp(from, "acpi=ht", 7)) {
 			if (!acpi_force)
 				disable_acpi();
 			acpi_ht = 1;
 		}
 		/* "pci=noacpi" disable ACPI IRQ routing and PCI scan */
 		else if (!memcmp(from, "pci=noacpi", 10)) {
 			acpi_disable_pci();
 		}
 		/* "acpi=noirq" disables ACPI interrupt routing */
 		else if (!memcmp(from, "acpi=noirq", 10)) {
 			acpi_noirq_set();
 		}
 		else if (!memcmp(from, "acpi_sci=edge", 13))
 			acpi_sci_flags.trigger =  1;
 		else if (!memcmp(from, "acpi_sci=level", 14))
 			acpi_sci_flags.trigger = 3;
 		else if (!memcmp(from, "acpi_sci=high", 13))
 			acpi_sci_flags.polarity = 1;
 		else if (!memcmp(from, "acpi_sci=low", 12))
 			acpi_sci_flags.polarity = 3;
 #ifdef CONFIG_X86_IO_APIC
 		else if (!memcmp(from, "acpi_skip_timer_override", 24))
 			acpi_skip_timer_override = 1;
 #endif
 #ifdef CONFIG_X86_LOCAL_APIC
 		/* disable IO-APIC */
 		else if (!memcmp(from, "noapic", 6))
 			disable_ioapic_setup();
 #endif /* CONFIG_X86_LOCAL_APIC */
 #endif /* CONFIG_ACPI_BOOT */
 #ifdef CONFIG_X86_LOCAL_APIC
 		/* enable local APIC */
 		else if (!memcmp(from, "lapic", 5))
 			lapic_enable();
 		/* disable local APIC */
 		else if (!memcmp(from, "nolapic", 6))
 			lapic_disable();
 #endif /* CONFIG_X86_LOCAL_APIC */
 #ifdef CONFIG_KEXEC
 		/* crashkernel=size@addr specifies the location to reserve for
 		 * a crash kernel.  By reserving this memory we guarantee
 		 * that linux never set's it up as a DMA target.
 		 * Useful for holding code to do something appropriate
 		 * after a kernel panic.
 		 */
 		else if (!memcmp(from, "crashkernel=", 12)) {
 			unsigned long size, base;
 			size = memparse(from+12, &from);
 			if (*from == '@') {
 				base = memparse(from+1, &from);
 				/* FIXME: Do I want a sanity check
 				 * to validate the memory range?
 				 */
 				crashk_res.start = base;
 				crashk_res.end   = base + size - 1;
 			}
 		}
 #endif
 #ifdef CONFIG_CRASH_DUMP
 		/* elfcorehdr= specifies the location of elf core header
 		 * stored by the crashed kernel.
 		 */
 		else if (!memcmp(from, "elfcorehdr=", 11))
 			elfcorehdr_addr = memparse(from+11, &from);
 #endif
 		/*
 		 * highmem=size forces highmem to be exactly 'size' bytes.
 		 * This works even on boxes that have no highmem otherwise.
 		 * This also works to reduce highmem size on bigger boxes.
 		 */
 		else if (!memcmp(from, "highmem=", 8))
 			highmem_pages = memparse(from+8, &from) >> PAGE_SHIFT;
 		/*
 		 * vmalloc=size forces the vmalloc area to be exactly 'size'
 		 * bytes. This can be used to increase (or decrease) the
 		 * vmalloc area - the default is 128m.
 		 */
 		else if (!memcmp(from, "vmalloc=", 8))
 			__VMALLOC_RESERVE = memparse(from+8, &from);
 	next_char:
 		c = *(from++);
 		if (!c)
 			break;
 		if (COMMAND_LINE_SIZE <= ++len)
 			break;
 		*(to++) = c;
 	}
 	*to = '\0';
 	*cmdline_p = command_line;
 	if (userdef) {
 		printk(KERN_INFO "user-defined physical RAM map:\n");
 		print_memory_map("user");
 	}
 }
 /*
  * Callback for efi_memory_walk.
  */
 static int __init
 efi_find_max_pfn(unsigned long start, unsigned long end, void *arg)
 {
 	unsigned long *max_pfn = arg, pfn;
 	if (start < end) {
 		pfn = PFN_UP(end -1);
 		if (pfn > *max_pfn)
 			*max_pfn = pfn;
 	}
 	return 0;
 }
 /*
  * Find the highest page frame number we have available
  */
 void __init find_max_pfn(void)
 {
 	int i;
 	max_pfn = 0;
 	if (efi_enabled) {
 		efi_memmap_walk(efi_find_max_pfn, &max_pfn);
 		return;
 	}
 	for (i = 0; i < e820.nr_map; i++) {
 		unsigned long start, end;
 		/* RAM? */
 		if (e820.map[i].type != E820_RAM)
 			continue;
 		start = PFN_UP(e820.map[i].addr);
 		end = PFN_DOWN(e820.map[i].addr + e820.map[i].size);
 		if (start >= end)
 			continue;
 		if (end > max_pfn)
 			max_pfn = end;
 	}
 }
 /*
  * Determine low and high memory ranges:
  */
 unsigned long __init find_max_low_pfn(void)
 {
 	unsigned long max_low_pfn;
 	max_low_pfn = max_pfn;
 	if (max_low_pfn > MAXMEM_PFN) {
 		if (highmem_pages == -1)
 			highmem_pages = max_pfn - MAXMEM_PFN;
 		if (highmem_pages + MAXMEM_PFN < max_pfn)
 			max_pfn = MAXMEM_PFN + highmem_pages;
 		if (highmem_pages + MAXMEM_PFN > max_pfn) {
 			printk("only %luMB highmem pages available, ignoring highmem size of %uMB.\n", pages_to_mb(max_pfn - MAXMEM_PFN), pages_to_mb(highmem_pages));
 			highmem_pages = 0;
 		}
 		max_low_pfn = MAXMEM_PFN;
 #ifndef CONFIG_HIGHMEM
 		/* Maximum memory usable is what is directly addressable */
 		printk(KERN_WARNING "Warning only %ldMB will be used.\n",
 					MAXMEM>>20);
 		if (max_pfn > MAX_NONPAE_PFN)
 			printk(KERN_WARNING "Use a PAE enabled kernel.\n");
 		else
 			printk(KERN_WARNING "Use a HIGHMEM enabled kernel.\n");
 		max_pfn = MAXMEM_PFN;
 #else /* !CONFIG_HIGHMEM */
 #ifndef CONFIG_X86_PAE
 		if (max_pfn > MAX_NONPAE_PFN) {
 			max_pfn = MAX_NONPAE_PFN;
 			printk(KERN_WARNING "Warning only 4GB will be used.\n");
 			printk(KERN_WARNING "Use a PAE enabled kernel.\n");
 		}
 #endif /* !CONFIG_X86_PAE */
 #endif /* !CONFIG_HIGHMEM */
 	} else {
 		if (highmem_pages == -1)
 			highmem_pages = 0;
 #ifdef CONFIG_HIGHMEM
 		if (highmem_pages >= max_pfn) {
 			printk(KERN_ERR "highmem size specified (%uMB) is bigger than pages available (%luMB)!.\n", pages_to_mb(highmem_pages), pages_to_mb(max_pfn));
 			highmem_pages = 0;
 		}
 		if (highmem_pages) {
 			if (max_low_pfn-highmem_pages < 64*1024*1024/PAGE_SIZE){
 				printk(KERN_ERR "highmem size %uMB results in smaller than 64MB lowmem, ignoring it.\n", pages_to_mb(highmem_pages));
 				highmem_pages = 0;
 			}
 			max_low_pfn -= highmem_pages;
 		}
 #else
 		if (highmem_pages)
 			printk(KERN_ERR "ignoring highmem size on non-highmem kernel!\n");
 #endif
 	}
 	return max_low_pfn;
 }
 /*
  * Free all available memory for boot time allocation.  Used
  * as a callback function by efi_memory_walk()
  */
 static int __init
 free_available_memory(unsigned long start, unsigned long end, void *arg)
 {
 	/* check max_low_pfn */
 	if (start >= ((max_low_pfn + 1) << PAGE_SHIFT))
 		return 0;
 	if (end >= ((max_low_pfn + 1) << PAGE_SHIFT))
 		end = (max_low_pfn + 1) << PAGE_SHIFT;
 	if (start < end)
 		free_bootmem(start, end - start);
 	return 0;
 }
 /*
  * Register fully available low RAM pages with the bootmem allocator.
  */
 static void __init register_bootmem_low_pages(unsigned long max_low_pfn)
 {
 	int i;
 	if (efi_enabled) {
 		efi_memmap_walk(free_available_memory, NULL);
 		return;
 	}
 	for (i = 0; i < e820.nr_map; i++) {
 		unsigned long curr_pfn, last_pfn, size;
 		/*
 		 * Reserve usable low memory
 		 */
 		if (e820.map[i].type != E820_RAM)
 			continue;
 		/*
 		 * We are rounding up the start address of usable memory:
 		 */
 		curr_pfn = PFN_UP(e820.map[i].addr);
 		if (curr_pfn >= max_low_pfn)
 			continue;
 		/*
 		 * ... and at the end of the usable range downwards:
 		 */
 		last_pfn = PFN_DOWN(e820.map[i].addr + e820.map[i].size);
 		if (last_pfn > max_low_pfn)
 			last_pfn = max_low_pfn;
 		/*
 		 * .. finally, did all the rounding and playing
 		 * around just make the area go away?
 		 */
 		if (last_pfn <= curr_pfn)
 			continue;
 		size = last_pfn - curr_pfn;
 		free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
 	}
 }
 /*
  * workaround for Dell systems that neglect to reserve EBDA
  */
 static void __init reserve_ebda_region(void)
 {
 	unsigned int addr;
 	addr = get_bios_ebda();
 	if (addr)
 		reserve_bootmem(addr, PAGE_SIZE);
 }
 #ifndef CONFIG_NEED_MULTIPLE_NODES
 void __init setup_bootmem_allocator(void);
 static unsigned long __init setup_memory(void)
 {
 	/*
 	 * partially used pages are not usable - thus
 	 * we are rounding upwards:
 	 */
 	min_low_pfn = PFN_UP(init_pg_tables_end);
 	find_max_pfn();
 	max_low_pfn = find_max_low_pfn();
 #ifdef CONFIG_HIGHMEM
 	highstart_pfn = highend_pfn = max_pfn;
 	if (max_pfn > max_low_pfn) {
 		highstart_pfn = max_low_pfn;
 	}
 	printk(KERN_NOTICE "%ldMB HIGHMEM available.\n",
 		pages_to_mb(highend_pfn - highstart_pfn));
 #endif
 	printk(KERN_NOTICE "%ldMB LOWMEM available.\n",
 			pages_to_mb(max_low_pfn));
 	setup_bootmem_allocator();
 	return max_low_pfn;
 }
 void __init zone_sizes_init(void)
 {
 	unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
 	unsigned int max_dma, low;
 	max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
 	low = max_low_pfn;
 	if (low < max_dma)
 		zones_size[ZONE_DMA] = low;
 	else {
 		zones_size[ZONE_DMA] = max_dma;
 		zones_size[ZONE_NORMAL] = low - max_dma;
 #ifdef CONFIG_HIGHMEM
 		zones_size[ZONE_HIGHMEM] = highend_pfn - low;
 #endif
 	}
 	free_area_init(zones_size);
 }
 #else
 extern unsigned long __init setup_memory(void);
 extern void zone_sizes_init(void);
 #endif /* !CONFIG_NEED_MULTIPLE_NODES */
 void __init setup_bootmem_allocator(void)
 {
 	unsigned long bootmap_size;
 	/*
 	 * Initialize the boot-time allocator (with low memory only):
 	 */
 	bootmap_size = init_bootmem(min_low_pfn, max_low_pfn);
 	register_bootmem_low_pages(max_low_pfn);
 	/*
 	 * Reserve the bootmem bitmap itself as well. We do this in two
 	 * steps (first step was init_bootmem()) because this catches
 	 * the (very unlikely) case of us accidentally initializing the
 	 * bootmem allocator with an invalid RAM area.
 	 */
 	reserve_bootmem(__PHYSICAL_START, (PFN_PHYS(min_low_pfn) +
 			 bootmap_size + PAGE_SIZE-1) - (__PHYSICAL_START));
 	/*
 	 * reserve physical page 0 - it's a special BIOS page on many boxes,
 	 * enabling clean reboots, SMP operation, laptop functions.
 	 */
 	reserve_bootmem(0, PAGE_SIZE);
 	/* reserve EBDA region, it's a 4K region */
 	reserve_ebda_region();
     /* could be an AMD 768MPX chipset. Reserve a page  before VGA to prevent
        PCI prefetch into it (errata #56). Usually the page is reserved anyways,
        unless you have no PS/2 mouse plugged in. */
 	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
 	    boot_cpu_data.x86 == 6)
 	     reserve_bootmem(0xa0000 - 4096, 4096);
 #ifdef CONFIG_SMP
 	/*
 	 * But first pinch a few for the stack/trampoline stuff
 	 * FIXME: Don't need the extra page at 4K, but need to fix
 	 * trampoline before removing it. (see the GDT stuff)
 	 */
 	reserve_bootmem(PAGE_SIZE, PAGE_SIZE);
 #endif
 #ifdef CONFIG_ACPI_SLEEP
 	/*
 	 * Reserve low memory region for sleep support.
 	 */
 	acpi_reserve_bootmem();
 #endif
 #ifdef CONFIG_X86_FIND_SMP_CONFIG
 	/*
 	 * Find and reserve possible boot-time SMP configuration:
 	 */
 	find_smp_config();
 #endif
 #ifdef CONFIG_BLK_DEV_INITRD
 	if (LOADER_TYPE && INITRD_START) {
 		if (INITRD_START + INITRD_SIZE <= (max_low_pfn << PAGE_SHIFT)) {
 			reserve_bootmem(INITRD_START, INITRD_SIZE);
 			initrd_start =
 				INITRD_START ? INITRD_START + PAGE_OFFSET : 0;
 			initrd_end = initrd_start+INITRD_SIZE;
 		}
 		else {
 			printk(KERN_ERR "initrd extends beyond end of memory "
 			    "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
 			    INITRD_START + INITRD_SIZE,
 			    max_low_pfn << PAGE_SHIFT);
 			initrd_start = 0;
 		}
 	}
 #endif
 #ifdef CONFIG_KEXEC
 	if (crashk_res.start != crashk_res.end)
 		reserve_bootmem(crashk_res.start,
 			crashk_res.end - crashk_res.start + 1);
 #endif
 }
 /*
  * The node 0 pgdat is initialized before all of these because
  * it's needed for bootmem.  node>0 pgdats have their virtual
  * space allocated before the pagetables are in place to access
  * them, so they can't be cleared then.
  *
  * This should all compile down to nothing when NUMA is off.
  */
 void __init remapped_pgdat_init(void)
 {
 	int nid;
 	for_each_online_node(nid) {
 		if (nid != 0)
 			memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
 	}
 }
 /*
  * Request address space for all standard RAM and ROM resources
  * and also for regions reported as reserved by the e820.
  */
 static void __init
 legacy_init_iomem_resources(struct resource *code_resource, struct resource *data_resource)
 {
 	int i;
 	probe_roms();
 	for (i = 0; i < e820.nr_map; i++) {
 		struct resource *res;
 		if (e820.map[i].addr + e820.map[i].size > 0x100000000ULL)
 			continue;
 		res = alloc_bootmem_low(sizeof(struct resource));
 		switch (e820.map[i].type) {
 		case E820_RAM:	res->name = "System RAM"; break;
 		case E820_ACPI:	res->name = "ACPI Tables"; break;
 		case E820_NVS:	res->name = "ACPI Non-volatile Storage"; break;
 		default:	res->name = "reserved";
 		}
 		res->start = e820.map[i].addr;
 		res->end = res->start + e820.map[i].size - 1;
 		res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
 		request_resource(&iomem_resource, res);
 		if (e820.map[i].type == E820_RAM) {
 			/*
 			 *  We don't know which RAM region contains kernel data,
 			 *  so we try it repeatedly and let the resource manager
 			 *  test it.
 			 */
 			request_resource(res, code_resource);
 			request_resource(res, data_resource);
 #ifdef CONFIG_KEXEC
 			request_resource(res, &crashk_res);
 #endif
 		}
 	}
 }
 /*
  * Request address space for all standard resources
  */
 static void __init register_memory(void)
 {
 	unsigned long gapstart, gapsize;
 	unsigned long long last;
 	int	      i;
 	if (efi_enabled)
 		efi_initialize_iomem_resources(&code_resource, &data_resource);
 	else
 		legacy_init_iomem_resources(&code_resource, &data_resource);
 	/* EFI systems may still have VGA */
 	request_resource(&iomem_resource, &video_ram_resource);
 	/* request I/O space for devices used on all i[345]86 PCs */
 	for (i = 0; i < STANDARD_IO_RESOURCES; i++)
 		request_resource(&ioport_resource, &standard_io_resources[i]);
 	/*
 	 * Search for the bigest gap in the low 32 bits of the e820
 	 * memory space.
 	 */
 	last = 0x100000000ull;
 	gapstart = 0x10000000;
 	gapsize = 0x400000;
 	i = e820.nr_map;
 	while (--i >= 0) {
 		unsigned long long start = e820.map[i].addr;
 		unsigned long long end = start + e820.map[i].size;
 		/*
 		 * Since "last" is at most 4GB, we know we'll
 		 * fit in 32 bits if this condition is true
 		 */
 		if (last > end) {
 			unsigned long gap = last - end;
 			if (gap > gapsize) {
 				gapsize = gap;
 				gapstart = end;
 			}
 		}
 		if (start < last)
 			last = start;
 	}
 	/*
 	 * Start allocating dynamic PCI memory a bit into the gap,
 	 * aligned up to the nearest megabyte.
 	 *
 	 * Question: should we try to pad it up a bit (do something
 	 * like " + (gapsize >> 3)" in there too?). We now have the
 	 * technology.
 	 */
 	pci_mem_start = (gapstart + 0xfffff) & ~0xfffff;
 	printk("Allocating PCI resources starting at %08lx (gap: %08lx:%08lx)\n",
 		pci_mem_start, gapstart, gapsize);
 }
 /* Use inline assembly to define this because the nops are defined
    as inline assembly strings in the include files and we cannot
    get them easily into strings. */
 asm("\t.data\nintelnops: "
     GENERIC_NOP1 GENERIC_NOP2 GENERIC_NOP3 GENERIC_NOP4 GENERIC_NOP5 GENERIC_NOP6
     GENERIC_NOP7 GENERIC_NOP8);
 asm("\t.data\nk8nops: "
     K8_NOP1 K8_NOP2 K8_NOP3 K8_NOP4 K8_NOP5 K8_NOP6
     K8_NOP7 K8_NOP8);
 asm("\t.data\nk7nops: "
     K7_NOP1 K7_NOP2 K7_NOP3 K7_NOP4 K7_NOP5 K7_NOP6
     K7_NOP7 K7_NOP8);
 extern unsigned char intelnops[], k8nops[], k7nops[];
 static unsigned char *intel_nops[ASM_NOP_MAX+1] = {
      NULL,
      intelnops,
      intelnops + 1,
      intelnops + 1 + 2,
      intelnops + 1 + 2 + 3,
      intelnops + 1 + 2 + 3 + 4,
      intelnops + 1 + 2 + 3 + 4 + 5,
      intelnops + 1 + 2 + 3 + 4 + 5 + 6,
      intelnops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
 };
 static unsigned char *k8_nops[ASM_NOP_MAX+1] = {
      NULL,
      k8nops,
      k8nops + 1,
      k8nops + 1 + 2,
      k8nops + 1 + 2 + 3,
      k8nops + 1 + 2 + 3 + 4,
      k8nops + 1 + 2 + 3 + 4 + 5,
      k8nops + 1 + 2 + 3 + 4 + 5 + 6,
      k8nops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
 };
 static unsigned char *k7_nops[ASM_NOP_MAX+1] = {
      NULL,
      k7nops,
      k7nops + 1,
      k7nops + 1 + 2,
      k7nops + 1 + 2 + 3,
      k7nops + 1 + 2 + 3 + 4,
      k7nops + 1 + 2 + 3 + 4 + 5,
      k7nops + 1 + 2 + 3 + 4 + 5 + 6,
      k7nops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
 };
 static struct nop {
      int cpuid;
      unsigned char **noptable;
 } noptypes[] = {
      { X86_FEATURE_K8, k8_nops },
      { X86_FEATURE_K7, k7_nops },
      { -1, NULL }
 };
 /* Replace instructions with better alternatives for this CPU type.
    This runs before SMP is initialized to avoid SMP problems with
    self modifying code. This implies that assymetric systems where
    APs have less capabilities than the boot processor are not handled.
    Tough. Make sure you disable such features by hand. */
 void apply_alternatives(void *start, void *end)
 {
 	struct alt_instr *a;
 	int diff, i, k;
         unsigned char **noptable = intel_nops;
 	for (i = 0; noptypes[i].cpuid >= 0; i++) {
 		if (boot_cpu_has(noptypes[i].cpuid)) {
 			noptable = noptypes[i].noptable;
 			break;
 		}
 	}
 	for (a = start; (void *)a < end; a++) {
 		if (!boot_cpu_has(a->cpuid))
 			continue;
 		BUG_ON(a->replacementlen > a->instrlen);
 		memcpy(a->instr, a->replacement, a->replacementlen);
 		diff = a->instrlen - a->replacementlen;
 		/* Pad the rest with nops */
 		for (i = a->replacementlen; diff > 0; diff -= k, i += k) {
 			k = diff;
 			if (k > ASM_NOP_MAX)
 				k = ASM_NOP_MAX;
 			memcpy(a->instr + i, noptable[k], k);
 		}
 	}
 }
 void __init alternative_instructions(void)
 {
 	extern struct alt_instr __alt_instructions[], __alt_instructions_end[];
 	apply_alternatives(__alt_instructions, __alt_instructions_end);
 }
 static char * __init machine_specific_memory_setup(void);
 #ifdef CONFIG_MCA
 static void set_mca_bus(int x)
 {
 	MCA_bus = x;
 }
 #else
 static void set_mca_bus(int x) { }
 #endif
 /*
  * Determine if we were loaded by an EFI loader.  If so, then we have also been
  * passed the efi memmap, systab, etc., so we should use these data structures
  * for initialization.  Note, the efi init code path is determined by the
  * global efi_enabled. This allows the same kernel image to be used on existing
  * systems (with a traditional BIOS) as well as on EFI systems.
  */
 void __init setup_arch(char **cmdline_p)
 {
 	unsigned long max_low_pfn;
 	memcpy(&boot_cpu_data, &new_cpu_data, sizeof(new_cpu_data));
 	pre_setup_arch_hook();
 	early_cpu_init();
 	/*
 	 * FIXME: This isn't an official loader_type right
 	 * now but does currently work with elilo.
 	 * If we were configured as an EFI kernel, check to make
 	 * sure that we were loaded correctly from elilo and that
 	 * the system table is valid.  If not, then initialize normally.
 	 */
 #ifdef CONFIG_EFI
 	if ((LOADER_TYPE == 0x50) && EFI_SYSTAB)
 		efi_enabled = 1;
 #endif
  	ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
  	drive_info = DRIVE_INFO;
  	screen_info = SCREEN_INFO;
 	edid_info = EDID_INFO;
 	apm_info.bios = APM_BIOS_INFO;
 	ist_info = IST_INFO;
 	saved_videomode = VIDEO_MODE;
 	if( SYS_DESC_TABLE.length != 0 ) {
 		set_mca_bus(SYS_DESC_TABLE.table[3] & 0x2);
 		machine_id = SYS_DESC_TABLE.table[0];
 		machine_submodel_id = SYS_DESC_TABLE.table[1];
 		BIOS_revision = SYS_DESC_TABLE.table[2];
 	}
 	bootloader_type = LOADER_TYPE;
 #ifdef CONFIG_BLK_DEV_RAM
 	rd_image_start = RAMDISK_FLAGS & RAMDISK_IMAGE_START_MASK;
 	rd_prompt = ((RAMDISK_FLAGS & RAMDISK_PROMPT_FLAG) != 0);
 	rd_doload = ((RAMDISK_FLAGS & RAMDISK_LOAD_FLAG) != 0);
 #endif
 	ARCH_SETUP
 	if (efi_enabled)
 		efi_init();
 	else {
 		printk(KERN_INFO "BIOS-provided physical RAM map:\n");
 		print_memory_map(machine_specific_memory_setup());
 	}
 	copy_edd();
 	if (!MOUNT_ROOT_RDONLY)
 		root_mountflags &= ~MS_RDONLY;
 	init_mm.start_code = (unsigned long) _text;
 	init_mm.end_code = (unsigned long) _etext;
 	init_mm.end_data = (unsigned long) _edata;
 	init_mm.brk = init_pg_tables_end + PAGE_OFFSET;
 	code_resource.start = virt_to_phys(_text);
 	code_resource.end = virt_to_phys(_etext)-1;
 	data_resource.start = virt_to_phys(_etext);
 	data_resource.end = virt_to_phys(_edata)-1;
 	parse_cmdline_early(cmdline_p);
 	max_low_pfn = setup_memory();
 	/*
 	 * NOTE: before this point _nobody_ is allowed to allocate
 	 * any memory using the bootmem allocator.  Although the
 	 * alloctor is now initialised only the first 8Mb of the kernel
 	 * virtual address space has been mapped.  All allocations before
 	 * paging_init() has completed must use the alloc_bootmem_low_pages()
 	 * variant (which allocates DMA'able memory) and care must be taken
 	 * not to exceed the 8Mb limit.
 	 */
 #ifdef CONFIG_SMP
 	smp_alloc_memory(); /* AP processor realmode stacks in low memory*/
 #endif
 	paging_init();
 	remapped_pgdat_init();
 	sparse_init();
 	zone_sizes_init();
 	/*
 	 * NOTE: at this point the bootmem allocator is fully available.
 	 */
 #ifdef CONFIG_EARLY_PRINTK
 	{
 		char *s = strstr(*cmdline_p, "earlyprintk=");
 		if (s) {
 			extern void setup_early_printk(char *);
 			setup_early_printk(s);
 			printk("early console enabled\n");
 		}
 	}
 #endif
 	dmi_scan_machine();
 #ifdef CONFIG_X86_GENERICARCH
 	generic_apic_probe(*cmdline_p);
 #endif
 	if (efi_enabled)
 		efi_map_memmap();
 #ifdef CONFIG_ACPI_BOOT
 	/*
 	 * Parse the ACPI tables for possible boot-time SMP configuration.
 	 */
 	acpi_boot_table_init();
 	acpi_boot_init();
-#endif
+#if defined(CONFIG_SMP) && defined(CONFIG_X86_PC)
+	if (def_to_bigsmp)
+		printk(KERN_WARNING "More than 8 CPUs detected and "
+			"CONFIG_X86_PC cannot handle it.\nUse "
+			"CONFIG_X86_GENERICARCH or CONFIG_X86_BIGSMP.\n");
+#endif
+#endif
 #ifdef CONFIG_X86_LOCAL_APIC
 	if (smp_found_config)
 		get_smp_config();
 #endif
 	register_memory();
 #ifdef CONFIG_VT
 #if defined(CONFIG_VGA_CONSOLE)
 	if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
 		conswitchp = &vga_con;
 #elif defined(CONFIG_DUMMY_CONSOLE)
 	conswitchp = &dummy_con;
 #endif
 #endif
 }
 #include "setup_arch_post.h"
 /*
  * Local Variables:
  * mode:c
  * c-file-style:"k&r"
  * c-basic-offset:8
  * End:
  */

arch/i386/mach-generic/bigsmp.c

Diff comments View file @ 911a62d

 /*
  * APIC driver for "bigsmp" XAPIC machines with more than 8 virtual CPUs.
  * Drives the local APIC in "clustered mode".
  */
 #define APIC_DEFINITION 1
 #include <linux/config.h>
 #include <linux/threads.h>
 #include <linux/cpumask.h>
 #include <asm/mpspec.h>
 #include <asm/genapic.h>
 #include <asm/fixmap.h>
 #include <asm/apicdef.h>
 #include <linux/kernel.h>
 #include <linux/smp.h>
 #include <linux/init.h>
 #include <linux/dmi.h>
 #include <asm/mach-bigsmp/mach_apic.h>
 #include <asm/mach-bigsmp/mach_apicdef.h>
 #include <asm/mach-bigsmp/mach_ipi.h>
 #include <asm/mach-default/mach_mpparse.h>
 static int dmi_bigsmp; /* can be set by dmi scanners */
 static __init int hp_ht_bigsmp(struct dmi_system_id *d)
 {
 #ifdef CONFIG_X86_GENERICARCH
 	printk(KERN_NOTICE "%s detected: force use of apic=bigsmp\n", d->ident);
 	dmi_bigsmp = 1;
 #endif
 	return 0;
 }
 static struct dmi_system_id __initdata bigsmp_dmi_table[] = {
 	{ hp_ht_bigsmp, "HP ProLiant DL760 G2", {
 		DMI_MATCH(DMI_BIOS_VENDOR, "HP"),
 		DMI_MATCH(DMI_BIOS_VERSION, "P44-"),
 	}},
 	{ hp_ht_bigsmp, "HP ProLiant DL740", {
 		DMI_MATCH(DMI_BIOS_VENDOR, "HP"),
 		DMI_MATCH(DMI_BIOS_VERSION, "P47-"),
 	 }},
 	 { }
 };
 static __init int probe_bigsmp(void)
 {
-	dmi_check_system(bigsmp_dmi_table);
+	if (def_to_bigsmp)
+        	dmi_bigsmp = 1;
+	else
+		dmi_check_system(bigsmp_dmi_table);
 	return dmi_bigsmp;
 }
 struct genapic apic_bigsmp = APIC_INIT("bigsmp", probe_bigsmp);

arch/i386/mach-generic/probe.c

Diff comments View file @ 911a62d

 /* Copyright 2003 Andi Kleen, SuSE Labs.
  * Subject to the GNU Public License, v.2
  *
  * Generic x86 APIC driver probe layer.
  */
 #include <linux/config.h>
 #include <linux/threads.h>
 #include <linux/cpumask.h>
 #include <linux/string.h>
 #include <linux/kernel.h>
 #include <linux/ctype.h>
 #include <linux/init.h>
 #include <asm/fixmap.h>
 #include <asm/mpspec.h>
 #include <asm/apicdef.h>
 #include <asm/genapic.h>
 extern struct genapic apic_summit;
 extern struct genapic apic_bigsmp;
 extern struct genapic apic_es7000;
 extern struct genapic apic_default;
 struct genapic *genapic = &apic_default;
 struct genapic *apic_probe[] __initdata = {
 	&apic_summit,
 	&apic_bigsmp,
 	&apic_es7000,
 	&apic_default,	/* must be last */
 	NULL,
 };
+static int cmdline_apic;
+void __init generic_bigsmp_probe(void)
+{
+	/*
+	 * This routine is used to switch to bigsmp mode when
+	 * - There is no apic= option specified by the user
+	 * - generic_apic_probe() has choosen apic_default as the sub_arch
+	 * - we find more than 8 CPUs in acpi LAPIC listing with xAPIC support
+	 */
+	if (!cmdline_apic && genapic == &apic_default)
+		if (apic_bigsmp.probe()) {
+			genapic = &apic_bigsmp;
+			printk(KERN_INFO "Overriding APIC driver with %s\n",
+			       genapic->name);
+		}
+}
 void __init generic_apic_probe(char *command_line)
 {
 	char *s;
 	int i;
 	int changed = 0;
 	s = strstr(command_line, "apic=");
 	if (s && (s == command_line || isspace(s[-1]))) {
 		char *p = strchr(s, ' '), old;
 		if (!p)
 			p = strchr(s, '\0');
 		old = *p;
 		*p = 0;
 		for (i = 0; !changed && apic_probe[i]; i++) {
 			if (!strcmp(apic_probe[i]->name, s+5)) {
 				changed = 1;
 				genapic = apic_probe[i];
 			}
 		}
 		if (!changed)
 			printk(KERN_ERR "Unknown genapic `%s' specified.\n", s);
 		*p = old;
+		cmdline_apic = changed;
 	}
 	for (i = 0; !changed && apic_probe[i]; i++) {
 		if (apic_probe[i]->probe()) {
 			changed = 1;
 			genapic = apic_probe[i];
 		}
 	}
 	/* Not visible without early console */
 	if (!changed)
 		panic("Didn't find an APIC driver");
 	printk(KERN_INFO "Using APIC driver %s\n", genapic->name);
 }
 /* These functions can switch the APIC even after the initial ->probe() */
 int __init mps_oem_check(struct mp_config_table *mpc, char *oem, char *productid)
 {
 	int i;
 	for (i = 0; apic_probe[i]; ++i) {
 		if (apic_probe[i]->mps_oem_check(mpc,oem,productid)) {
 			genapic = apic_probe[i];
 			printk(KERN_INFO "Switched to APIC driver `%s'.\n",
 			       genapic->name);
 			return 1;
 		}
 	}
 	return 0;
 }
 int __init acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 {
 	int i;
 	for (i = 0; apic_probe[i]; ++i) {
 		if (apic_probe[i]->acpi_madt_oem_check(oem_id, oem_table_id)) {
 			genapic = apic_probe[i];
 			printk(KERN_INFO "Switched to APIC driver `%s'.\n",
 			       genapic->name);
 			return 1;
 		}
 	}
 	return 0;
 }
 int hard_smp_processor_id(void)
 {
 	return genapic->get_apic_id(*(unsigned long *)(APIC_BASE+APIC_ID));
 }

include/asm-i386/apicdef.h

Diff comments View file @ 911a62d

 #ifndef __ASM_APICDEF_H
 #define __ASM_APICDEF_H
 /*
  * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
  *
  * Alan Cox <Alan.Cox@linux.org>, 1995.
  * Ingo Molnar <mingo@redhat.com>, 1999, 2000
  */
 #define		APIC_DEFAULT_PHYS_BASE	0xfee00000
 #define		APIC_ID		0x20
 #define		APIC_LVR	0x30
 #define			APIC_LVR_MASK		0xFF00FF
 #define			GET_APIC_VERSION(x)	((x)&0xFF)
 #define			GET_APIC_MAXLVT(x)	(((x)>>16)&0xFF)
 #define			APIC_INTEGRATED(x)	((x)&0xF0)
+#define			APIC_XAPIC(x)		((x) >= 0x14)
 #define		APIC_TASKPRI	0x80
 #define			APIC_TPRI_MASK		0xFF
 #define		APIC_ARBPRI	0x90
 #define			APIC_ARBPRI_MASK	0xFF
 #define		APIC_PROCPRI	0xA0
 #define		APIC_EOI	0xB0
 #define			APIC_EIO_ACK		0x0		/* Write this to the EOI register */
 #define		APIC_RRR	0xC0
 #define		APIC_LDR	0xD0
 #define			APIC_LDR_MASK		(0xFF<<24)
 #define			GET_APIC_LOGICAL_ID(x)	(((x)>>24)&0xFF)
 #define			SET_APIC_LOGICAL_ID(x)	(((x)<<24))
 #define			APIC_ALL_CPUS		0xFF
 #define		APIC_DFR	0xE0
 #define			APIC_DFR_CLUSTER		0x0FFFFFFFul
 #define			APIC_DFR_FLAT			0xFFFFFFFFul
 #define		APIC_SPIV	0xF0
 #define			APIC_SPIV_FOCUS_DISABLED	(1<<9)
 #define			APIC_SPIV_APIC_ENABLED		(1<<8)
 #define		APIC_ISR	0x100
 #define		APIC_TMR	0x180
 #define 	APIC_IRR	0x200
 #define 	APIC_ESR	0x280
 #define			APIC_ESR_SEND_CS	0x00001
 #define			APIC_ESR_RECV_CS	0x00002
 #define			APIC_ESR_SEND_ACC	0x00004
 #define			APIC_ESR_RECV_ACC	0x00008
 #define			APIC_ESR_SENDILL	0x00020
 #define			APIC_ESR_RECVILL	0x00040
 #define			APIC_ESR_ILLREGA	0x00080
 #define		APIC_ICR	0x300
 #define			APIC_DEST_SELF		0x40000
 #define			APIC_DEST_ALLINC	0x80000
 #define			APIC_DEST_ALLBUT	0xC0000
 #define			APIC_ICR_RR_MASK	0x30000
 #define			APIC_ICR_RR_INVALID	0x00000
 #define			APIC_ICR_RR_INPROG	0x10000
 #define			APIC_ICR_RR_VALID	0x20000
 #define			APIC_INT_LEVELTRIG	0x08000
 #define			APIC_INT_ASSERT		0x04000
 #define			APIC_ICR_BUSY		0x01000
 #define			APIC_DEST_LOGICAL	0x00800
 #define			APIC_DM_FIXED		0x00000
 #define			APIC_DM_LOWEST		0x00100
 #define			APIC_DM_SMI		0x00200
 #define			APIC_DM_REMRD		0x00300
 #define			APIC_DM_NMI		0x00400
 #define			APIC_DM_INIT		0x00500
 #define			APIC_DM_STARTUP		0x00600
 #define			APIC_DM_EXTINT		0x00700
 #define			APIC_VECTOR_MASK	0x000FF
 #define		APIC_ICR2	0x310
 #define			GET_APIC_DEST_FIELD(x)	(((x)>>24)&0xFF)
 #define			SET_APIC_DEST_FIELD(x)	((x)<<24)
 #define		APIC_LVTT	0x320
 #define		APIC_LVTTHMR	0x330
 #define		APIC_LVTPC	0x340
 #define		APIC_LVT0	0x350
 #define			APIC_LVT_TIMER_BASE_MASK	(0x3<<18)
 #define			GET_APIC_TIMER_BASE(x)		(((x)>>18)&0x3)
 #define			SET_APIC_TIMER_BASE(x)		(((x)<<18))
 #define			APIC_TIMER_BASE_CLKIN		0x0
 #define			APIC_TIMER_BASE_TMBASE		0x1
 #define			APIC_TIMER_BASE_DIV		0x2
 #define			APIC_LVT_TIMER_PERIODIC		(1<<17)
 #define			APIC_LVT_MASKED			(1<<16)
 #define			APIC_LVT_LEVEL_TRIGGER		(1<<15)
 #define			APIC_LVT_REMOTE_IRR		(1<<14)
 #define			APIC_INPUT_POLARITY		(1<<13)
 #define			APIC_SEND_PENDING		(1<<12)
 #define			APIC_MODE_MASK			0x700
 #define			GET_APIC_DELIVERY_MODE(x)	(((x)>>8)&0x7)
 #define			SET_APIC_DELIVERY_MODE(x,y)	(((x)&~0x700)|((y)<<8))
 #define				APIC_MODE_FIXED		0x0
 #define				APIC_MODE_NMI		0x4
 #define				APIC_MODE_EXTINT	0x7
 #define 	APIC_LVT1	0x360
 #define		APIC_LVTERR	0x370
 #define		APIC_TMICT	0x380
 #define		APIC_TMCCT	0x390
 #define		APIC_TDCR	0x3E0
 #define			APIC_TDR_DIV_TMBASE	(1<<2)
 #define			APIC_TDR_DIV_1		0xB
 #define			APIC_TDR_DIV_2		0x0
 #define			APIC_TDR_DIV_4		0x1
 #define			APIC_TDR_DIV_8		0x2
 #define			APIC_TDR_DIV_16		0x3
 #define			APIC_TDR_DIV_32		0x8
 #define			APIC_TDR_DIV_64		0x9
 #define			APIC_TDR_DIV_128	0xA
 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
 #define MAX_IO_APICS 64
 /*
  * the local APIC register structure, memory mapped. Not terribly well
  * tested, but we might eventually use this one in the future - the
  * problem why we cannot use it right now is the P5 APIC, it has an
  * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
  */
 #define u32 unsigned int
 #define lapic ((volatile struct local_apic *)APIC_BASE)
 struct local_apic {
 /*000*/	struct { u32 __reserved[4]; } __reserved_01;
 /*010*/	struct { u32 __reserved[4]; } __reserved_02;
 /*020*/	struct { /* APIC ID Register */
 		u32   __reserved_1	: 24,
 			phys_apic_id	:  4,
 			__reserved_2	:  4;
 		u32 __reserved[3];
 	} id;
 /*030*/	const
 	struct { /* APIC Version Register */
 		u32   version		:  8,
 			__reserved_1	:  8,
 			max_lvt		:  8,
 			__reserved_2	:  8;
 		u32 __reserved[3];
 	} version;
 /*040*/	struct { u32 __reserved[4]; } __reserved_03;
 /*050*/	struct { u32 __reserved[4]; } __reserved_04;
 /*060*/	struct { u32 __reserved[4]; } __reserved_05;
 /*070*/	struct { u32 __reserved[4]; } __reserved_06;
 /*080*/	struct { /* Task Priority Register */
 		u32   priority	:  8,
 			__reserved_1	: 24;
 		u32 __reserved_2[3];
 	} tpr;
 /*090*/	const
 	struct { /* Arbitration Priority Register */
 		u32   priority	:  8,
 			__reserved_1	: 24;
 		u32 __reserved_2[3];
 	} apr;
 /*0A0*/	const
 	struct { /* Processor Priority Register */
 		u32   priority	:  8,
 			__reserved_1	: 24;
 		u32 __reserved_2[3];
 	} ppr;
 /*0B0*/	struct { /* End Of Interrupt Register */
 		u32   eoi;
 		u32 __reserved[3];
 	} eoi;
 /*0C0*/	struct { u32 __reserved[4]; } __reserved_07;
 /*0D0*/	struct { /* Logical Destination Register */
 		u32   __reserved_1	: 24,
 			logical_dest	:  8;
 		u32 __reserved_2[3];
 	} ldr;
 /*0E0*/	struct { /* Destination Format Register */
 		u32   __reserved_1	: 28,
 			model		:  4;
 		u32 __reserved_2[3];
 	} dfr;
 /*0F0*/	struct { /* Spurious Interrupt Vector Register */
 		u32	spurious_vector	:  8,
 			apic_enabled	:  1,
 			focus_cpu	:  1,
 			__reserved_2	: 22;
 		u32 __reserved_3[3];
 	} svr;
 /*100*/	struct { /* In Service Register */
 /*170*/		u32 bitfield;
 		u32 __reserved[3];
 	} isr [8];
 /*180*/	struct { /* Trigger Mode Register */
 /*1F0*/		u32 bitfield;
 		u32 __reserved[3];
 	} tmr [8];
 /*200*/	struct { /* Interrupt Request Register */
 /*270*/		u32 bitfield;
 		u32 __reserved[3];
 	} irr [8];
 /*280*/	union { /* Error Status Register */
 		struct {
 			u32   send_cs_error			:  1,
 				receive_cs_error		:  1,
 				send_accept_error		:  1,
 				receive_accept_error		:  1,
 				__reserved_1			:  1,
 				send_illegal_vector		:  1,
 				receive_illegal_vector		:  1,
 				illegal_register_address	:  1,
 				__reserved_2			: 24;
 			u32 __reserved_3[3];
 		} error_bits;
 		struct {
 			u32 errors;
 			u32 __reserved_3[3];
 		} all_errors;
 	} esr;
 /*290*/	struct { u32 __reserved[4]; } __reserved_08;
 /*2A0*/	struct { u32 __reserved[4]; } __reserved_09;
 /*2B0*/	struct { u32 __reserved[4]; } __reserved_10;
 /*2C0*/	struct { u32 __reserved[4]; } __reserved_11;
 /*2D0*/	struct { u32 __reserved[4]; } __reserved_12;
 /*2E0*/	struct { u32 __reserved[4]; } __reserved_13;
 /*2F0*/	struct { u32 __reserved[4]; } __reserved_14;
 /*300*/	struct { /* Interrupt Command Register 1 */
 		u32   vector			:  8,
 			delivery_mode		:  3,
 			destination_mode	:  1,
 			delivery_status		:  1,
 			__reserved_1		:  1,
 			level			:  1,
 			trigger			:  1,
 			__reserved_2		:  2,
 			shorthand		:  2,
 			__reserved_3		:  12;
 		u32 __reserved_4[3];
 	} icr1;
 /*310*/	struct { /* Interrupt Command Register 2 */
 		union {
 			u32   __reserved_1	: 24,
 				phys_dest	:  4,
 				__reserved_2	:  4;
 			u32   __reserved_3	: 24,
 				logical_dest	:  8;
 		} dest;
 		u32 __reserved_4[3];
 	} icr2;
 /*320*/	struct { /* LVT - Timer */
 		u32   vector		:  8,
 			__reserved_1	:  4,
 			delivery_status	:  1,
 			__reserved_2	:  3,
 			mask		:  1,
 			timer_mode	:  1,
 			__reserved_3	: 14;
 		u32 __reserved_4[3];
 	} lvt_timer;
 /*330*/	struct { /* LVT - Thermal Sensor */
 		u32  vector		:  8,
 			delivery_mode	:  3,
 			__reserved_1	:  1,
 			delivery_status	:  1,
 			__reserved_2	:  3,
 			mask		:  1,
 			__reserved_3	: 15;
 		u32 __reserved_4[3];
 	} lvt_thermal;
 /*340*/	struct { /* LVT - Performance Counter */
 		u32   vector		:  8,
 			delivery_mode	:  3,
 			__reserved_1	:  1,
 			delivery_status	:  1,
 			__reserved_2	:  3,
 			mask		:  1,
 			__reserved_3	: 15;
 		u32 __reserved_4[3];
 	} lvt_pc;
 /*350*/	struct { /* LVT - LINT0 */
 		u32   vector		:  8,
 			delivery_mode	:  3,
 			__reserved_1	:  1,
 			delivery_status	:  1,
 			polarity	:  1,
 			remote_irr	:  1,
 			trigger		:  1,
 			mask		:  1,
 			__reserved_2	: 15;
 		u32 __reserved_3[3];
 	} lvt_lint0;
 /*360*/	struct { /* LVT - LINT1 */
 		u32   vector		:  8,
 			delivery_mode	:  3,
 			__reserved_1	:  1,
 			delivery_status	:  1,
 			polarity	:  1,
 			remote_irr	:  1,
 			trigger		:  1,
 			mask		:  1,
 			__reserved_2	: 15;
 		u32 __reserved_3[3];
 	} lvt_lint1;
 /*370*/	struct { /* LVT - Error */
 		u32   vector		:  8,
 			__reserved_1	:  4,
 			delivery_status	:  1,
 			__reserved_2	:  3,
 			mask		:  1,
 			__reserved_3	: 15;
 		u32 __reserved_4[3];
 	} lvt_error;
 /*380*/	struct { /* Timer Initial Count Register */
 		u32   initial_count;
 		u32 __reserved_2[3];
 	} timer_icr;
 /*390*/	const
 	struct { /* Timer Current Count Register */
 		u32   curr_count;
 		u32 __reserved_2[3];
 	} timer_ccr;
 /*3A0*/	struct { u32 __reserved[4]; } __reserved_16;
 /*3B0*/	struct { u32 __reserved[4]; } __reserved_17;
 /*3C0*/	struct { u32 __reserved[4]; } __reserved_18;
 /*3D0*/	struct { u32 __reserved[4]; } __reserved_19;
 /*3E0*/	struct { /* Timer Divide Configuration Register */
 		u32   divisor		:  4,
 			__reserved_1	: 28;
 		u32 __reserved_2[3];
 	} timer_dcr;
 /*3F0*/	struct { u32 __reserved[4]; } __reserved_20;
 } __attribute__ ((packed));
 #undef u32
 #endif

include/asm-i386/mach-generic/mach_apic.h

Diff comments View file @ 911a62d

 #ifndef __ASM_MACH_APIC_H
 #define __ASM_MACH_APIC_H
 #include <asm/genapic.h>
 #define esr_disable (genapic->ESR_DISABLE)
 #define NO_BALANCE_IRQ (genapic->no_balance_irq)
 #define INT_DELIVERY_MODE (genapic->int_delivery_mode)
 #define INT_DEST_MODE (genapic->int_dest_mode)
 #undef APIC_DEST_LOGICAL
 #define APIC_DEST_LOGICAL (genapic->apic_destination_logical)
 #define TARGET_CPUS	  (genapic->target_cpus())
 #define apic_id_registered (genapic->apic_id_registered)
 #define init_apic_ldr (genapic->init_apic_ldr)
 #define ioapic_phys_id_map (genapic->ioapic_phys_id_map)
 #define clustered_apic_check (genapic->clustered_apic_check)
 #define multi_timer_check (genapic->multi_timer_check)
 #define apicid_to_node (genapic->apicid_to_node)
 #define cpu_to_logical_apicid (genapic->cpu_to_logical_apicid)
 #define cpu_present_to_apicid (genapic->cpu_present_to_apicid)
 #define apicid_to_cpu_present (genapic->apicid_to_cpu_present)
 #define mpc_apic_id (genapic->mpc_apic_id)
 #define setup_portio_remap (genapic->setup_portio_remap)
 #define check_apicid_present (genapic->check_apicid_present)
 #define check_phys_apicid_present (genapic->check_phys_apicid_present)
 #define check_apicid_used (genapic->check_apicid_used)
 #define cpu_mask_to_apicid (genapic->cpu_mask_to_apicid)
 #define enable_apic_mode (genapic->enable_apic_mode)
 #define phys_pkg_id (genapic->phys_pkg_id)
+extern void generic_bigsmp_probe(void);
 #endif /* __ASM_MACH_APIC_H */

include/asm-i386/mpspec.h

Diff comments View file @ 911a62d

 #ifndef __ASM_MPSPEC_H
 #define __ASM_MPSPEC_H
 #include <linux/cpumask.h>
 #include <asm/mpspec_def.h>
 #include <mach_mpspec.h>
 extern int mp_bus_id_to_type [MAX_MP_BUSSES];
 extern int mp_bus_id_to_node [MAX_MP_BUSSES];
 extern int mp_bus_id_to_local [MAX_MP_BUSSES];
 extern int quad_local_to_mp_bus_id [NR_CPUS/4][4];
 extern int mp_bus_id_to_pci_bus [MAX_MP_BUSSES];
+extern unsigned int def_to_bigsmp;
 extern unsigned int boot_cpu_physical_apicid;
 extern int smp_found_config;
 extern void find_smp_config (void);
 extern void get_smp_config (void);
 extern int nr_ioapics;
 extern int apic_version [MAX_APICS];
 extern int mp_bus_id_to_type [MAX_MP_BUSSES];
 extern int mp_irq_entries;
 extern struct mpc_config_intsrc mp_irqs [MAX_IRQ_SOURCES];
 extern int mpc_default_type;
 extern int mp_bus_id_to_pci_bus [MAX_MP_BUSSES];
 extern unsigned long mp_lapic_addr;
 extern int pic_mode;
 extern int using_apic_timer;
 #ifdef CONFIG_ACPI_BOOT
 extern void mp_register_lapic (u8 id, u8 enabled);
 extern void mp_register_lapic_address (u64 address);
 extern void mp_register_ioapic (u8 id, u32 address, u32 gsi_base);
 extern void mp_override_legacy_irq (u8 bus_irq, u8 polarity, u8 trigger, u32 gsi);
 extern void mp_config_acpi_legacy_irqs (void);
 extern int mp_register_gsi (u32 gsi, int edge_level, int active_high_low);
 #endif /*CONFIG_ACPI_BOOT*/
 #define PHYSID_ARRAY_SIZE	BITS_TO_LONGS(MAX_APICS)
 struct physid_mask
 {
 	unsigned long mask[PHYSID_ARRAY_SIZE];
 };
 typedef struct physid_mask physid_mask_t;
 #define physid_set(physid, map)			set_bit(physid, (map).mask)
 #define physid_clear(physid, map)		clear_bit(physid, (map).mask)
 #define physid_isset(physid, map)		test_bit(physid, (map).mask)
 #define physid_test_and_set(physid, map)	test_and_set_bit(physid, (map).mask)
 #define physids_and(dst, src1, src2)		bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
 #define physids_or(dst, src1, src2)		bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
 #define physids_clear(map)			bitmap_zero((map).mask, MAX_APICS)
 #define physids_complement(dst, src)		bitmap_complement((dst).mask,(src).mask, MAX_APICS)
 #define physids_empty(map)			bitmap_empty((map).mask, MAX_APICS)
 #define physids_equal(map1, map2)		bitmap_equal((map1).mask, (map2).mask, MAX_APICS)
 #define physids_weight(map)			bitmap_weight((map).mask, MAX_APICS)
 #define physids_shift_right(d, s, n)		bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS)
 #define physids_shift_left(d, s, n)		bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS)
 #define physids_coerce(map)			((map).mask[0])
 #define physids_promote(physids)						\
 	({									\
 		physid_mask_t __physid_mask = PHYSID_MASK_NONE;			\
 		__physid_mask.mask[0] = physids;				\
 		__physid_mask;							\
 	})
 #define physid_mask_of_physid(physid)						\
 	({									\
 		physid_mask_t __physid_mask = PHYSID_MASK_NONE;			\
 		physid_set(physid, __physid_mask);				\
 		__physid_mask;							\
 	})
 #define PHYSID_MASK_ALL		{ {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
 #define PHYSID_MASK_NONE	{ {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
 extern physid_mask_t phys_cpu_present_map;
 #endif