Doug / smarc-fsl-linux-kernel

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/*

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/*

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* Permedia2 framebuffer driver.

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* Permedia2 framebuffer driver.

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*

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*

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* 2.5/2.6 driver:

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* 2.5/2.6 driver:

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*

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*

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* based on 2.4 driver:

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* based on 2.4 driver:

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*

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*

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* and additional input from James Simmon's port of Hannu Mallat's tdfx

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* and additional input from James Simmon's port of Hannu Mallat's tdfx

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* driver.

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* driver.

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*

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*

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* I have a Creative Graphics Blaster Exxtreme card - pm2fb on x86. I

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* I have a Creative Graphics Blaster Exxtreme card - pm2fb on x86. I

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* have no access to other pm2fb implementations. Sparc (and thus

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* have no access to other pm2fb implementations. Sparc (and thus

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* hopefully other big-endian) devices now work, thanks to a lot of

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* hopefully other big-endian) devices now work, thanks to a lot of

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* testing work by Ron Murray. I have no access to CVision hardware,

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* testing work by Ron Murray. I have no access to CVision hardware,

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* and therefore for now I am omitting the CVision code.

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* and therefore for now I am omitting the CVision code.

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*

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*

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* Multiple boards support has been on the TODO list for ages.

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* Multiple boards support has been on the TODO list for ages.

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* Don't expect this to change.

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* Don't expect this to change.

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*

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*

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* This file is subject to the terms and conditions of the GNU General Public

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* This file is subject to the terms and conditions of the GNU General Public

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* License. See the file COPYING in the main directory of this archive for

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* License. See the file COPYING in the main directory of this archive for

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* more details.

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* more details.

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*

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*

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*

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*

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*/

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*/

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#include <linux/config.h>

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#include <linux/config.h>

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#include <linux/module.h>

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#include <linux/module.h>

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#include <linux/moduleparam.h>

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#include <linux/moduleparam.h>

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#include <linux/kernel.h>

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#include <linux/kernel.h>

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#include <linux/errno.h>

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#include <linux/errno.h>

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#include <linux/string.h>

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#include <linux/string.h>

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#include <linux/mm.h>

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#include <linux/mm.h>

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#include <linux/tty.h>

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#include <linux/tty.h>

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#include <linux/slab.h>

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#include <linux/slab.h>

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#include <linux/delay.h>

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#include <linux/delay.h>

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#include <linux/fb.h>

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#include <linux/fb.h>

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#include <linux/init.h>

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#include <linux/init.h>

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#include <linux/pci.h>

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#include <linux/pci.h>

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#include <video/permedia2.h>

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#include <video/permedia2.h>

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#include <video/cvisionppc.h>

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#include <video/cvisionppc.h>

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#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)

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#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)

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#error "The endianness of the target host has not been defined."

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#error "The endianness of the target host has not been defined."

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#endif

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#endif

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#if !defined(CONFIG_PCI)

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#if !defined(CONFIG_PCI)

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#error "Only generic PCI cards supported."

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#error "Only generic PCI cards supported."

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#endif

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#endif

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#undef PM2FB_MASTER_DEBUG

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#undef PM2FB_MASTER_DEBUG

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#ifdef PM2FB_MASTER_DEBUG

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#ifdef PM2FB_MASTER_DEBUG

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#define DPRINTK(a,b...) printk(KERN_DEBUG "pm2fb: %s: " a, __FUNCTION__ , ## b)

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#define DPRINTK(a,b...) printk(KERN_DEBUG "pm2fb: %s: " a, __FUNCTION__ , ## b)

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#else

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#else

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#define DPRINTK(a,b...)

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#define DPRINTK(a,b...)

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#endif

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#endif

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/*

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/*

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* Driver data

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* Driver data

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*/

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*/

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static char *mode __devinitdata = NULL;

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static char *mode __devinitdata = NULL;

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/*

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/*

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* The XFree GLINT driver will (I think to implement hardware cursor

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* The XFree GLINT driver will (I think to implement hardware cursor

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* support on TVP4010 and similar where there is no RAMDAC - see

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* support on TVP4010 and similar where there is no RAMDAC - see

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* comment in set_video) always request +ve sync regardless of what

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* comment in set_video) always request +ve sync regardless of what

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* the mode requires. This screws me because I have a Sun

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* the mode requires. This screws me because I have a Sun

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* fixed-frequency monitor which absolutely has to have -ve sync. So

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* fixed-frequency monitor which absolutely has to have -ve sync. So

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* these flags allow the user to specify that requests for +ve sync

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* these flags allow the user to specify that requests for +ve sync

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* should be silently turned in -ve sync.

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* should be silently turned in -ve sync.

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*/

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*/

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static int lowhsync __devinitdata = 0;

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static int lowhsync __devinitdata = 0;

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static int lowvsync __devinitdata = 0;

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static int lowvsync __devinitdata = 0;

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/*

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/*

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* The hardware state of the graphics card that isn't part of the

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* The hardware state of the graphics card that isn't part of the

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* screeninfo.

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* screeninfo.

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*/

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*/

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struct pm2fb_par

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struct pm2fb_par

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{

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{

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pm2type_t type; /* Board type */

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pm2type_t type; /* Board type */

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u32 fb_size; /* framebuffer memory size */

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u32 fb_size; /* framebuffer memory size */

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unsigned char __iomem *v_fb; /* virtual address of frame buffer */

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unsigned char __iomem *v_fb; /* virtual address of frame buffer */

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unsigned char __iomem *v_regs;/* virtual address of p_regs */

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unsigned char __iomem *v_regs;/* virtual address of p_regs */

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u32 memclock; /* memclock */

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u32 memclock; /* memclock */

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u32 video; /* video flags before blanking */

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u32 video; /* video flags before blanking */

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u32 mem_config; /* MemConfig reg at probe */

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u32 mem_config; /* MemConfig reg at probe */

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u32 mem_control; /* MemControl reg at probe */

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u32 mem_control; /* MemControl reg at probe */

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u32 boot_address; /* BootAddress reg at probe */

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u32 boot_address; /* BootAddress reg at probe */

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};

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};

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/*

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/*

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* Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo

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* Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo

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* if we don't use modedb.

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* if we don't use modedb.

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*/

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*/

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static struct fb_fix_screeninfo pm2fb_fix __devinitdata = {

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static struct fb_fix_screeninfo pm2fb_fix __devinitdata = {

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.id = "",

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.id = "",

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.type = FB_TYPE_PACKED_PIXELS,

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.type = FB_TYPE_PACKED_PIXELS,

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.visual = FB_VISUAL_PSEUDOCOLOR,

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.visual = FB_VISUAL_PSEUDOCOLOR,

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.xpanstep = 1,

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.xpanstep = 1,

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.ypanstep = 1,

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.ypanstep = 1,

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.ywrapstep = 0,

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.ywrapstep = 0,

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.accel = FB_ACCEL_NONE,

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.accel = FB_ACCEL_NONE,

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};

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};

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/*

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/*

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* Default video mode. In case the modedb doesn't work.

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* Default video mode. In case the modedb doesn't work.

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*/

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*/

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static struct fb_var_screeninfo pm2fb_var __devinitdata = {

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static struct fb_var_screeninfo pm2fb_var __devinitdata = {

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/* "640x480, 8 bpp @ 60 Hz */

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/* "640x480, 8 bpp @ 60 Hz */

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.xres = 640,

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.xres = 640,

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.yres = 480,

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.yres = 480,

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.xres_virtual = 640,

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.xres_virtual = 640,

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.yres_virtual = 480,

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.yres_virtual = 480,

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.bits_per_pixel =8,

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.bits_per_pixel =8,

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.red = {0, 8, 0},

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.red = {0, 8, 0},

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.blue = {0, 8, 0},

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.blue = {0, 8, 0},

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.green = {0, 8, 0},

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.green = {0, 8, 0},

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.activate = FB_ACTIVATE_NOW,

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.activate = FB_ACTIVATE_NOW,

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.height = -1,

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.height = -1,

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.width = -1,

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.width = -1,

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.accel_flags = 0,

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.accel_flags = 0,

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.pixclock = 39721,

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.pixclock = 39721,

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.left_margin = 40,

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.left_margin = 40,

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.right_margin = 24,

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.right_margin = 24,

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.upper_margin = 32,

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.upper_margin = 32,

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.lower_margin = 11,

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.lower_margin = 11,

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.hsync_len = 96,

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.hsync_len = 96,

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.vsync_len = 2,

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.vsync_len = 2,

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.vmode = FB_VMODE_NONINTERLACED

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.vmode = FB_VMODE_NONINTERLACED

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};

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};

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/*

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/*

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* Utility functions

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* Utility functions

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*/

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*/

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static inline u32 RD32(unsigned char __iomem *base, s32 off)

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static inline u32 RD32(unsigned char __iomem *base, s32 off)

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{

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{

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return fb_readl(base + off);

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return fb_readl(base + off);

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}

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}

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static inline void WR32(unsigned char __iomem *base, s32 off, u32 v)

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static inline void WR32(unsigned char __iomem *base, s32 off, u32 v)

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{

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{

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fb_writel(v, base + off);

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fb_writel(v, base + off);

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}

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}

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static inline u32 pm2_RD(struct pm2fb_par* p, s32 off)

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static inline u32 pm2_RD(struct pm2fb_par* p, s32 off)

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{

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{

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return RD32(p->v_regs, off);

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return RD32(p->v_regs, off);

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}

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}

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static inline void pm2_WR(struct pm2fb_par* p, s32 off, u32 v)

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static inline void pm2_WR(struct pm2fb_par* p, s32 off, u32 v)

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{

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{

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WR32(p->v_regs, off, v);

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WR32(p->v_regs, off, v);

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}

159

}

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static inline u32 pm2_RDAC_RD(struct pm2fb_par* p, s32 idx)

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static inline u32 pm2_RDAC_RD(struct pm2fb_par* p, s32 idx)

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{

162

{

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int index = PM2R_RD_INDEXED_DATA;

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int index = PM2R_RD_INDEXED_DATA;

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switch (p->type) {

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switch (p->type) {

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case PM2_TYPE_PERMEDIA2:

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case PM2_TYPE_PERMEDIA2:

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pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);

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pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);

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break;

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break;

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case PM2_TYPE_PERMEDIA2V:

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case PM2_TYPE_PERMEDIA2V:

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pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);

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pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);

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index = PM2VR_RD_INDEXED_DATA;

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index = PM2VR_RD_INDEXED_DATA;

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break;

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break;

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}

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}

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mb();

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mb();

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return pm2_RD(p, index);

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return pm2_RD(p, index);

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}

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}

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static inline void pm2_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)

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static inline void pm2_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)

178

{

178

{

179

int index = PM2R_RD_INDEXED_DATA;

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int index = PM2R_RD_INDEXED_DATA;

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switch (p->type) {

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switch (p->type) {

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case PM2_TYPE_PERMEDIA2:

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case PM2_TYPE_PERMEDIA2:

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pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);

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pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);

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break;

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break;

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case PM2_TYPE_PERMEDIA2V:

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case PM2_TYPE_PERMEDIA2V:

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pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);

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pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);

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index = PM2VR_RD_INDEXED_DATA;

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index = PM2VR_RD_INDEXED_DATA;

187

break;

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break;

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}

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}

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mb();

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mb();

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pm2_WR(p, index, v);

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pm2_WR(p, index, v);

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}

191

}

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static inline void pm2v_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)

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static inline void pm2v_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)

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{

194

{

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pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);

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pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);

196

mb();

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mb();

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pm2_WR(p, PM2VR_RD_INDEXED_DATA, v);

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pm2_WR(p, PM2VR_RD_INDEXED_DATA, v);

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}

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}

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#ifdef CONFIG_FB_PM2_FIFO_DISCONNECT

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#ifdef CONFIG_FB_PM2_FIFO_DISCONNECT

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#define WAIT_FIFO(p,a)

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#define WAIT_FIFO(p,a)

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#else

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#else

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static inline void WAIT_FIFO(struct pm2fb_par* p, u32 a)

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static inline void WAIT_FIFO(struct pm2fb_par* p, u32 a)

204

{

204

{

205

while( pm2_RD(p, PM2R_IN_FIFO_SPACE) < a );

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while( pm2_RD(p, PM2R_IN_FIFO_SPACE) < a );

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mb();

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mb();

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}

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}

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#endif

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#endif

209

210

/*

210

/*

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* partial products for the supported horizontal resolutions.

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* partial products for the supported horizontal resolutions.

212

*/

212

*/

213

#define PACKPP(p0,p1,p2) (((p2) << 6) | ((p1) << 3) | (p0))

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#define PACKPP(p0,p1,p2) (((p2) << 6) | ((p1) << 3) | (p0))

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static const struct {

214

static const struct {

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u16 width;

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u16 width;

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u16 pp;

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u16 pp;

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} pp_table[] = {

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} pp_table[] = {

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{ 32, PACKPP(1, 0, 0) }, { 64, PACKPP(1, 1, 0) },

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{ 32, PACKPP(1, 0, 0) }, { 64, PACKPP(1, 1, 0) },

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{ 96, PACKPP(1, 1, 1) }, { 128, PACKPP(2, 1, 1) },

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{ 96, PACKPP(1, 1, 1) }, { 128, PACKPP(2, 1, 1) },

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{ 160, PACKPP(2, 2, 1) }, { 192, PACKPP(2, 2, 2) },

220

{ 160, PACKPP(2, 2, 1) }, { 192, PACKPP(2, 2, 2) },

221

{ 224, PACKPP(3, 2, 1) }, { 256, PACKPP(3, 2, 2) },

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{ 224, PACKPP(3, 2, 1) }, { 256, PACKPP(3, 2, 2) },

222

{ 288, PACKPP(3, 3, 1) }, { 320, PACKPP(3, 3, 2) },

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{ 288, PACKPP(3, 3, 1) }, { 320, PACKPP(3, 3, 2) },

223

{ 384, PACKPP(3, 3, 3) }, { 416, PACKPP(4, 3, 1) },

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{ 384, PACKPP(3, 3, 3) }, { 416, PACKPP(4, 3, 1) },

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{ 448, PACKPP(4, 3, 2) }, { 512, PACKPP(4, 3, 3) },

224

{ 448, PACKPP(4, 3, 2) }, { 512, PACKPP(4, 3, 3) },

225

{ 544, PACKPP(4, 4, 1) }, { 576, PACKPP(4, 4, 2) },

225

{ 544, PACKPP(4, 4, 1) }, { 576, PACKPP(4, 4, 2) },

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{ 640, PACKPP(4, 4, 3) }, { 768, PACKPP(4, 4, 4) },

226

{ 640, PACKPP(4, 4, 3) }, { 768, PACKPP(4, 4, 4) },

227

{ 800, PACKPP(5, 4, 1) }, { 832, PACKPP(5, 4, 2) },

227

{ 800, PACKPP(5, 4, 1) }, { 832, PACKPP(5, 4, 2) },

228

{ 896, PACKPP(5, 4, 3) }, { 1024, PACKPP(5, 4, 4) },

228

{ 896, PACKPP(5, 4, 3) }, { 1024, PACKPP(5, 4, 4) },

229

{ 1056, PACKPP(5, 5, 1) }, { 1088, PACKPP(5, 5, 2) },

229

{ 1056, PACKPP(5, 5, 1) }, { 1088, PACKPP(5, 5, 2) },

230

{ 1152, PACKPP(5, 5, 3) }, { 1280, PACKPP(5, 5, 4) },

230

{ 1152, PACKPP(5, 5, 3) }, { 1280, PACKPP(5, 5, 4) },

231

{ 1536, PACKPP(5, 5, 5) }, { 1568, PACKPP(6, 5, 1) },

231

{ 1536, PACKPP(5, 5, 5) }, { 1568, PACKPP(6, 5, 1) },

232

{ 1600, PACKPP(6, 5, 2) }, { 1664, PACKPP(6, 5, 3) },

232

{ 1600, PACKPP(6, 5, 2) }, { 1664, PACKPP(6, 5, 3) },

233

{ 1792, PACKPP(6, 5, 4) }, { 2048, PACKPP(6, 5, 5) },

233

{ 1792, PACKPP(6, 5, 4) }, { 2048, PACKPP(6, 5, 5) },

234

{ 0, 0 } };

234

{ 0, 0 } };

235

236

static u32 partprod(u32 xres)

236

static u32 partprod(u32 xres)

237

{

237

{

238

int i;

238

int i;

239

240

for (i = 0; pp_table[i].width && pp_table[i].width != xres; i++)

240

for (i = 0; pp_table[i].width && pp_table[i].width != xres; i++)

241

;

241

;

242

if ( pp_table[i].width == 0 )

242

if ( pp_table[i].width == 0 )

243

DPRINTK("invalid width %u\n", xres);

243

DPRINTK("invalid width %u\n", xres);

244

return pp_table[i].pp;

244

return pp_table[i].pp;

245

}

245

}

246

247

static u32 to3264(u32 timing, int bpp, int is64)

247

static u32 to3264(u32 timing, int bpp, int is64)

248

{

248

{

249

switch (bpp) {

249

switch (bpp) {

250

case 8:

250

case 8:

251

timing >>= 2 + is64;

251

timing >>= 2 + is64;

252

break;

252

break;

253

case 16:

253

case 16:

254

timing >>= 1 + is64;

254

timing >>= 1 + is64;

255

break;

255

break;

256

case 24:

256

case 24:

257

timing = (timing * 3) >> (2 + is64);

257

timing = (timing * 3) >> (2 + is64);

258

break;

258

break;

259

case 32:

259

case 32:

260

if (is64)

260

if (is64)

261

timing >>= 1;

261

timing >>= 1;

262

break;

262

break;

263

}

263

}

264

return timing;

264

return timing;

265

}

265

}

266

267

static void pm2_mnp(u32 clk, unsigned char* mm, unsigned char* nn,

267

static void pm2_mnp(u32 clk, unsigned char* mm, unsigned char* nn,

268

unsigned char* pp)

268

unsigned char* pp)

269

{

269

{

270

unsigned char m;

270

unsigned char m;

271

unsigned char n;

271

unsigned char n;

272

unsigned char p;

272

unsigned char p;

273

u32 f;

273

u32 f;

274

s32 curr;

274

s32 curr;

275

s32 delta = 100000;

275

s32 delta = 100000;

276

277

*mm = *nn = *pp = 0;

277

*mm = *nn = *pp = 0;

278

for (n = 2; n < 15; n++) {

278

for (n = 2; n < 15; n++) {

279

for (m = 2; m; m++) {

279

for (m = 2; m; m++) {

280

f = PM2_REFERENCE_CLOCK * m / n;

280

f = PM2_REFERENCE_CLOCK * m / n;

281

if (f >= 150000 && f <= 300000) {

281

if (f >= 150000 && f <= 300000) {

282

for ( p = 0; p < 5; p++, f >>= 1) {

282

for ( p = 0; p < 5; p++, f >>= 1) {

283

curr = ( clk > f ) ? clk - f : f - clk;

283

curr = ( clk > f ) ? clk - f : f - clk;

284

if ( curr < delta ) {

284

if ( curr < delta ) {

285

delta=curr;

285

delta=curr;

286

*mm=m;

286

*mm=m;

287

*nn=n;

287

*nn=n;

288

*pp=p;

288

*pp=p;

289

}

289

}

290

}

290

}

291

}

291

}

292

}

292

}

293

}

293

}

294

}

294

}

295

296

static void pm2v_mnp(u32 clk, unsigned char* mm, unsigned char* nn,

296

static void pm2v_mnp(u32 clk, unsigned char* mm, unsigned char* nn,

297

unsigned char* pp)

297

unsigned char* pp)

298

{

298

{

299

unsigned char m;

299

unsigned char m;

300

unsigned char n;

300

unsigned char n;

301

unsigned char p;

301

unsigned char p;

302

u32 f;

302

u32 f;

303

s32 delta = 1000;

303

s32 delta = 1000;

304

305

*mm = *nn = *pp = 0;

305

*mm = *nn = *pp = 0;

306

for (n = 1; n; n++) {

306

for (n = 1; n; n++) {

307

for ( m = 1; m; m++) {

307

for ( m = 1; m; m++) {

308

for ( p = 0; p < 2; p++) {

308

for ( p = 0; p < 2; p++) {

309

f = PM2_REFERENCE_CLOCK * n / (m * (1 << (p + 1)));

309

f = PM2_REFERENCE_CLOCK * n / (m * (1 << (p + 1)));

310

if ( clk > f - delta && clk < f + delta ) {

310

if ( clk > f - delta && clk < f + delta ) {

311

delta = ( clk > f ) ? clk - f : f - clk;

311

delta = ( clk > f ) ? clk - f : f - clk;

312

*mm=m;

312

*mm=m;

313

*nn=n;

313

*nn=n;

314

*pp=p;

314

*pp=p;

315

}

315

}

316

}

316

}

317

}

317

}

318

}

318

}

319

}

319

}

320

321

static void clear_palette(struct pm2fb_par* p) {

321

static void clear_palette(struct pm2fb_par* p) {

322

int i=256;

322

int i=256;

323

324

WAIT_FIFO(p, 1);

324

WAIT_FIFO(p, 1);

325

pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, 0);

325

pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, 0);

326

wmb();

326

wmb();

327

while (i--) {

327

while (i--) {

328

WAIT_FIFO(p, 3);

328

WAIT_FIFO(p, 3);

329

pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);

329

pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);

330

pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);

330

pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);

331

pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);

331

pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);

332

}

332

}

333

}

333

}

334

335

static void reset_card(struct pm2fb_par* p)

335

static void reset_card(struct pm2fb_par* p)

336

{

336

{

337

if (p->type == PM2_TYPE_PERMEDIA2V)

337

if (p->type == PM2_TYPE_PERMEDIA2V)

338

pm2_WR(p, PM2VR_RD_INDEX_HIGH, 0);

338

pm2_WR(p, PM2VR_RD_INDEX_HIGH, 0);

339

pm2_WR(p, PM2R_RESET_STATUS, 0);

339

pm2_WR(p, PM2R_RESET_STATUS, 0);

340

mb();

340

mb();

341

while (pm2_RD(p, PM2R_RESET_STATUS) & PM2F_BEING_RESET)

341

while (pm2_RD(p, PM2R_RESET_STATUS) & PM2F_BEING_RESET)

342

;

342

;

343

mb();

343

mb();

344

#ifdef CONFIG_FB_PM2_FIFO_DISCONNECT

344

#ifdef CONFIG_FB_PM2_FIFO_DISCONNECT

345

DPRINTK("FIFO disconnect enabled\n");

345

DPRINTK("FIFO disconnect enabled\n");

346

pm2_WR(p, PM2R_FIFO_DISCON, 1);

346

pm2_WR(p, PM2R_FIFO_DISCON, 1);

347

mb();

347

mb();

348

#endif

348

#endif

349

350

/* Restore stashed memory config information from probe */

350

/* Restore stashed memory config information from probe */

351

WAIT_FIFO(p, 3);

351

WAIT_FIFO(p, 3);

352

pm2_WR(p, PM2R_MEM_CONTROL, p->mem_control);

352

pm2_WR(p, PM2R_MEM_CONTROL, p->mem_control);

353

pm2_WR(p, PM2R_BOOT_ADDRESS, p->boot_address);

353

pm2_WR(p, PM2R_BOOT_ADDRESS, p->boot_address);

354

wmb();

354

wmb();

355

pm2_WR(p, PM2R_MEM_CONFIG, p->mem_config);

355

pm2_WR(p, PM2R_MEM_CONFIG, p->mem_config);

356

}

356

}

357

358

static void reset_config(struct pm2fb_par* p)

358

static void reset_config(struct pm2fb_par* p)

359

{

359

{

360

WAIT_FIFO(p, 52);

360

WAIT_FIFO(p, 52);

361

pm2_WR(p, PM2R_CHIP_CONFIG, pm2_RD(p, PM2R_CHIP_CONFIG)&

361

pm2_WR(p, PM2R_CHIP_CONFIG, pm2_RD(p, PM2R_CHIP_CONFIG)&

362

~(PM2F_VGA_ENABLE|PM2F_VGA_FIXED));

362

~(PM2F_VGA_ENABLE|PM2F_VGA_FIXED));

363

pm2_WR(p, PM2R_BYPASS_WRITE_MASK, ~(0L));

363

pm2_WR(p, PM2R_BYPASS_WRITE_MASK, ~(0L));

364

pm2_WR(p, PM2R_FRAMEBUFFER_WRITE_MASK, ~(0L));

364

pm2_WR(p, PM2R_FRAMEBUFFER_WRITE_MASK, ~(0L));

365

pm2_WR(p, PM2R_FIFO_CONTROL, 0);

365

pm2_WR(p, PM2R_FIFO_CONTROL, 0);

366

pm2_WR(p, PM2R_APERTURE_ONE, 0);

366

pm2_WR(p, PM2R_APERTURE_ONE, 0);

367

pm2_WR(p, PM2R_APERTURE_TWO, 0);

367

pm2_WR(p, PM2R_APERTURE_TWO, 0);

368

pm2_WR(p, PM2R_RASTERIZER_MODE, 0);

368

pm2_WR(p, PM2R_RASTERIZER_MODE, 0);

369

pm2_WR(p, PM2R_DELTA_MODE, PM2F_DELTA_ORDER_RGB);

369

pm2_WR(p, PM2R_DELTA_MODE, PM2F_DELTA_ORDER_RGB);

370

pm2_WR(p, PM2R_LB_READ_FORMAT, 0);

370

pm2_WR(p, PM2R_LB_READ_FORMAT, 0);

371

pm2_WR(p, PM2R_LB_WRITE_FORMAT, 0);

371

pm2_WR(p, PM2R_LB_WRITE_FORMAT, 0);

372

pm2_WR(p, PM2R_LB_READ_MODE, 0);

372

pm2_WR(p, PM2R_LB_READ_MODE, 0);

373

pm2_WR(p, PM2R_LB_SOURCE_OFFSET, 0);

373

pm2_WR(p, PM2R_LB_SOURCE_OFFSET, 0);

374

pm2_WR(p, PM2R_FB_SOURCE_OFFSET, 0);

374

pm2_WR(p, PM2R_FB_SOURCE_OFFSET, 0);

375

pm2_WR(p, PM2R_FB_PIXEL_OFFSET, 0);

375

pm2_WR(p, PM2R_FB_PIXEL_OFFSET, 0);

376

pm2_WR(p, PM2R_FB_WINDOW_BASE, 0);

376

pm2_WR(p, PM2R_FB_WINDOW_BASE, 0);

377

pm2_WR(p, PM2R_LB_WINDOW_BASE, 0);

377

pm2_WR(p, PM2R_LB_WINDOW_BASE, 0);

378

pm2_WR(p, PM2R_FB_SOFT_WRITE_MASK, ~(0L));

378

pm2_WR(p, PM2R_FB_SOFT_WRITE_MASK, ~(0L));

379

pm2_WR(p, PM2R_FB_HARD_WRITE_MASK, ~(0L));

379

pm2_WR(p, PM2R_FB_HARD_WRITE_MASK, ~(0L));

380

pm2_WR(p, PM2R_FB_READ_PIXEL, 0);

380

pm2_WR(p, PM2R_FB_READ_PIXEL, 0);

381

pm2_WR(p, PM2R_DITHER_MODE, 0);

381

pm2_WR(p, PM2R_DITHER_MODE, 0);

382

pm2_WR(p, PM2R_AREA_STIPPLE_MODE, 0);

382

pm2_WR(p, PM2R_AREA_STIPPLE_MODE, 0);

383

pm2_WR(p, PM2R_DEPTH_MODE, 0);

383

pm2_WR(p, PM2R_DEPTH_MODE, 0);

384

pm2_WR(p, PM2R_STENCIL_MODE, 0);

384

pm2_WR(p, PM2R_STENCIL_MODE, 0);

385

pm2_WR(p, PM2R_TEXTURE_ADDRESS_MODE, 0);

385

pm2_WR(p, PM2R_TEXTURE_ADDRESS_MODE, 0);

386

pm2_WR(p, PM2R_TEXTURE_READ_MODE, 0);

386

pm2_WR(p, PM2R_TEXTURE_READ_MODE, 0);

387

pm2_WR(p, PM2R_TEXEL_LUT_MODE, 0);

387

pm2_WR(p, PM2R_TEXEL_LUT_MODE, 0);

388

pm2_WR(p, PM2R_YUV_MODE, 0);

388

pm2_WR(p, PM2R_YUV_MODE, 0);

389

pm2_WR(p, PM2R_COLOR_DDA_MODE, 0);

389

pm2_WR(p, PM2R_COLOR_DDA_MODE, 0);

390

pm2_WR(p, PM2R_TEXTURE_COLOR_MODE, 0);

390

pm2_WR(p, PM2R_TEXTURE_COLOR_MODE, 0);

391

pm2_WR(p, PM2R_FOG_MODE, 0);

391

pm2_WR(p, PM2R_FOG_MODE, 0);

392

pm2_WR(p, PM2R_ALPHA_BLEND_MODE, 0);

392

pm2_WR(p, PM2R_ALPHA_BLEND_MODE, 0);

393

pm2_WR(p, PM2R_LOGICAL_OP_MODE, 0);

393

pm2_WR(p, PM2R_LOGICAL_OP_MODE, 0);

394

pm2_WR(p, PM2R_STATISTICS_MODE, 0);

394

pm2_WR(p, PM2R_STATISTICS_MODE, 0);

395

pm2_WR(p, PM2R_SCISSOR_MODE, 0);

395

pm2_WR(p, PM2R_SCISSOR_MODE, 0);

396

pm2_WR(p, PM2R_FILTER_MODE, PM2F_SYNCHRONIZATION);

396

pm2_WR(p, PM2R_FILTER_MODE, PM2F_SYNCHRONIZATION);

397

switch (p->type) {

397

switch (p->type) {

398

case PM2_TYPE_PERMEDIA2:

398

case PM2_TYPE_PERMEDIA2:

399

pm2_RDAC_WR(p, PM2I_RD_MODE_CONTROL, 0); /* no overlay */

399

pm2_RDAC_WR(p, PM2I_RD_MODE_CONTROL, 0); /* no overlay */

400

pm2_RDAC_WR(p, PM2I_RD_CURSOR_CONTROL, 0);

400

pm2_RDAC_WR(p, PM2I_RD_CURSOR_CONTROL, 0);

401

pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, PM2F_RD_PALETTE_WIDTH_8);

401

pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, PM2F_RD_PALETTE_WIDTH_8);

402

break;

402

break;

403

case PM2_TYPE_PERMEDIA2V:

403

case PM2_TYPE_PERMEDIA2V:

404

pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1); /* 8bit */

404

pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1); /* 8bit */

405

break;

405

break;

406

}

406

}

407

pm2_RDAC_WR(p, PM2I_RD_COLOR_KEY_CONTROL, 0);

407

pm2_RDAC_WR(p, PM2I_RD_COLOR_KEY_CONTROL, 0);

408

pm2_RDAC_WR(p, PM2I_RD_OVERLAY_KEY, 0);

408

pm2_RDAC_WR(p, PM2I_RD_OVERLAY_KEY, 0);

409

pm2_RDAC_WR(p, PM2I_RD_RED_KEY, 0);

409

pm2_RDAC_WR(p, PM2I_RD_RED_KEY, 0);

410

pm2_RDAC_WR(p, PM2I_RD_GREEN_KEY, 0);

410

pm2_RDAC_WR(p, PM2I_RD_GREEN_KEY, 0);

411

pm2_RDAC_WR(p, PM2I_RD_BLUE_KEY, 0);

411

pm2_RDAC_WR(p, PM2I_RD_BLUE_KEY, 0);

412

}

412

}

413

414

static void set_aperture(struct pm2fb_par* p, u32 depth)

414

static void set_aperture(struct pm2fb_par* p, u32 depth)

415

{

415

{

416

/*

416

/*

417

* The hardware is little-endian. When used in big-endian

417

* The hardware is little-endian. When used in big-endian

418

* hosts, the on-chip aperture settings are used where

418

* hosts, the on-chip aperture settings are used where

419

* possible to translate from host to card byte order.

419

* possible to translate from host to card byte order.

420

*/

420

*/

421

WAIT_FIFO(p, 4);

421

WAIT_FIFO(p, 4);

422

#ifdef __LITTLE_ENDIAN

422

#ifdef __LITTLE_ENDIAN

423

pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);

423

pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);

424

#else

424

#else

425

switch (depth) {

425

switch (depth) {

426

case 24: /* RGB->BGR */

426

case 24: /* RGB->BGR */

427

/*

427

/*

428

* We can't use the aperture to translate host to

428

* We can't use the aperture to translate host to

429

* card byte order here, so we switch to BGR mode

429

* card byte order here, so we switch to BGR mode

430

* in pm2fb_set_par().

430

* in pm2fb_set_par().

431

*/

431

*/

432

case 8: /* B->B */

432

case 8: /* B->B */

433

pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);

433

pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);

434

break;

434

break;

435

case 16: /* HL->LH */

435

case 16: /* HL->LH */

436

pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_HALFWORDSWAP);

436

pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_HALFWORDSWAP);

437

break;

437

break;

438

case 32: /* RGBA->ABGR */

438

case 32: /* RGBA->ABGR */

439

pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_BYTESWAP);

439

pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_BYTESWAP);

440

break;

440

break;

441

}

441

}

442

#endif

442

#endif

443

444

// We don't use aperture two, so this may be superflous

444

// We don't use aperture two, so this may be superflous

445

pm2_WR(p, PM2R_APERTURE_TWO, PM2F_APERTURE_STANDARD);

445

pm2_WR(p, PM2R_APERTURE_TWO, PM2F_APERTURE_STANDARD);

446

}

446

}

447

448

static void set_color(struct pm2fb_par* p, unsigned char regno,

448

static void set_color(struct pm2fb_par* p, unsigned char regno,

449

unsigned char r, unsigned char g, unsigned char b)

449

unsigned char r, unsigned char g, unsigned char b)

450

{

450

{

451

WAIT_FIFO(p, 4);

451

WAIT_FIFO(p, 4);

452

pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, regno);

452

pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, regno);

453

wmb();

453

wmb();

454

pm2_WR(p, PM2R_RD_PALETTE_DATA, r);

454

pm2_WR(p, PM2R_RD_PALETTE_DATA, r);

455

wmb();

455

wmb();

456

pm2_WR(p, PM2R_RD_PALETTE_DATA, g);

456

pm2_WR(p, PM2R_RD_PALETTE_DATA, g);

457

wmb();

457

wmb();

458

pm2_WR(p, PM2R_RD_PALETTE_DATA, b);

458

pm2_WR(p, PM2R_RD_PALETTE_DATA, b);

459

}

459

}

460

461

static void set_memclock(struct pm2fb_par* par, u32 clk)

461

static void set_memclock(struct pm2fb_par* par, u32 clk)

462

{

462

{

463

int i;

463

int i;

464

unsigned char m, n, p;

464

unsigned char m, n, p;

465

466

pm2_mnp(clk, &m, &n, &p);

466

pm2_mnp(clk, &m, &n, &p);

467

WAIT_FIFO(par, 10);

467

WAIT_FIFO(par, 10);

468

pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6);

468

pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6);

469

wmb();

469

wmb();

470

pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m);

470

pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m);

471

pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n);

471

pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n);

472

wmb();

472

wmb();

473

pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p);

473

pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p);

474

wmb();

474

wmb();

475

pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS);

475

pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS);

476

rmb();

476

rmb();

477

for (i = 256;

477

for (i = 256;

478

i && !(pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED);

478

i && !(pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED);

479

i--)

479

i--)

480

;

480

;

481

}

481

}

482

483

static void set_pixclock(struct pm2fb_par* par, u32 clk)

483

static void set_pixclock(struct pm2fb_par* par, u32 clk)

484

{

484

{

485

int i;

485

int i;

486

unsigned char m, n, p;

486

unsigned char m, n, p;

487

488

switch (par->type) {

488

switch (par->type) {

489

case PM2_TYPE_PERMEDIA2:

489

case PM2_TYPE_PERMEDIA2:

490

pm2_mnp(clk, &m, &n, &p);

490

pm2_mnp(clk, &m, &n, &p);

491

WAIT_FIFO(par, 8);

491

WAIT_FIFO(par, 8);

492

pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 0);

492

pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 0);

493

wmb();

493

wmb();

494

pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A1, m);

494

pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A1, m);

495

pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A2, n);

495

pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A2, n);

496

wmb();

496

wmb();

497

pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 8|p);

497

pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 8|p);

498

wmb();

498

wmb();

499

pm2_RDAC_RD(par, PM2I_RD_PIXEL_CLOCK_STATUS);

499

pm2_RDAC_RD(par, PM2I_RD_PIXEL_CLOCK_STATUS);

500

rmb();

500

rmb();

501

for (i = 256;

501

for (i = 256;

502

i && !(pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED);

502

i && !(pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED);

503

i--)

503

i--)

504

;

504

;

505

break;

505

break;

506

case PM2_TYPE_PERMEDIA2V:

506

case PM2_TYPE_PERMEDIA2V:

507

pm2v_mnp(clk/2, &m, &n, &p);

507

pm2v_mnp(clk/2, &m, &n, &p);

508

WAIT_FIFO(par, 8);

508

WAIT_FIFO(par, 8);

509

pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CLK0_PRESCALE >> 8);

509

pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CLK0_PRESCALE >> 8);

510

pm2v_RDAC_WR(par, PM2VI_RD_CLK0_PRESCALE, m);

510

pm2v_RDAC_WR(par, PM2VI_RD_CLK0_PRESCALE, m);

511

pm2v_RDAC_WR(par, PM2VI_RD_CLK0_FEEDBACK, n);

511

pm2v_RDAC_WR(par, PM2VI_RD_CLK0_FEEDBACK, n);

512

pm2v_RDAC_WR(par, PM2VI_RD_CLK0_POSTSCALE, p);

512

pm2v_RDAC_WR(par, PM2VI_RD_CLK0_POSTSCALE, p);

513

pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);

513

pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);

514

break;

514

break;

515

}

515

}

516

}

516

}

517

518

static void set_video(struct pm2fb_par* p, u32 video) {

518

static void set_video(struct pm2fb_par* p, u32 video) {

519

u32 tmp;

519

u32 tmp;

520

u32 vsync;

520

u32 vsync;

521

522

vsync = video;

522

vsync = video;

523

524

DPRINTK("video = 0x%x\n", video);

524

DPRINTK("video = 0x%x\n", video);

525

526

/*

526

/*

527

* The hardware cursor needs +vsync to recognise vert retrace.

527

* The hardware cursor needs +vsync to recognise vert retrace.

528

* We may not be using the hardware cursor, but the X Glint

528

* We may not be using the hardware cursor, but the X Glint

529

* driver may well. So always set +hsync/+vsync and then set

529

* driver may well. So always set +hsync/+vsync and then set

530

* the RAMDAC to invert the sync if necessary.

530

* the RAMDAC to invert the sync if necessary.

531

*/

531

*/

532

vsync &= ~(PM2F_HSYNC_MASK|PM2F_VSYNC_MASK);

532

vsync &= ~(PM2F_HSYNC_MASK|PM2F_VSYNC_MASK);

533

vsync |= PM2F_HSYNC_ACT_HIGH|PM2F_VSYNC_ACT_HIGH;

533

vsync |= PM2F_HSYNC_ACT_HIGH|PM2F_VSYNC_ACT_HIGH;

534

535

WAIT_FIFO(p, 5);

535

WAIT_FIFO(p, 5);

536

pm2_WR(p, PM2R_VIDEO_CONTROL, vsync);

536

pm2_WR(p, PM2R_VIDEO_CONTROL, vsync);

537

538

switch (p->type) {

538

switch (p->type) {

539

case PM2_TYPE_PERMEDIA2:

539

case PM2_TYPE_PERMEDIA2:

540

tmp = PM2F_RD_PALETTE_WIDTH_8;

540

tmp = PM2F_RD_PALETTE_WIDTH_8;

541

if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)

541

if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)

542

tmp |= 4; /* invert hsync */

542

tmp |= 4; /* invert hsync */

543

if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)

543

if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)

544

tmp |= 8; /* invert vsync */

544

tmp |= 8; /* invert vsync */

545

pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, tmp);

545

pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, tmp);

546

break;

546

break;

547

case PM2_TYPE_PERMEDIA2V:

547

case PM2_TYPE_PERMEDIA2V:

548

tmp = 0;

548

tmp = 0;

549

if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)

549

if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)

550

tmp |= 1; /* invert hsync */

550

tmp |= 1; /* invert hsync */

551

if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)

551

if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)

552

tmp |= 4; /* invert vsync */

552

tmp |= 4; /* invert vsync */

553

pm2v_RDAC_WR(p, PM2VI_RD_SYNC_CONTROL, tmp);

553

pm2v_RDAC_WR(p, PM2VI_RD_SYNC_CONTROL, tmp);

554

pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1);

554

pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1);

555

break;

555

break;

556

}

556

}

557

}

557

}

558

559

/*

559

/*

560

*

560

*

561

*/

561

*/

562

563

/**

563

/**

564

* pm2fb_check_var - Optional function. Validates a var passed in.

564

* pm2fb_check_var - Optional function. Validates a var passed in.

565

* @var: frame buffer variable screen structure

565

* @var: frame buffer variable screen structure

566

* @info: frame buffer structure that represents a single frame buffer

566

* @info: frame buffer structure that represents a single frame buffer

567

*

567

*

568

* Checks to see if the hardware supports the state requested by

568

* Checks to see if the hardware supports the state requested by

569

* var passed in.

569

* var passed in.

570

*

570

*

571

* Returns negative errno on error, or zero on success.

571

* Returns negative errno on error, or zero on success.

572

*/

572

*/

573

static int pm2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)

573

static int pm2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)

574

{

574

{

575

u32 lpitch;

575

u32 lpitch;

576

577

if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&

577

if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&

578

var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {

578

var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {

579

DPRINTK("depth not supported: %u\n", var->bits_per_pixel);

579

DPRINTK("depth not supported: %u\n", var->bits_per_pixel);

580

return -EINVAL;

580

return -EINVAL;

581

}

581

}

582

583

if (var->xres != var->xres_virtual) {

583

if (var->xres != var->xres_virtual) {

584

DPRINTK("virtual x resolution != physical x resolution not supported\n");

584

DPRINTK("virtual x resolution != physical x resolution not supported\n");

585

return -EINVAL;

585

return -EINVAL;

586

}

586

}

587

588

if (var->yres > var->yres_virtual) {

588

if (var->yres > var->yres_virtual) {

589

DPRINTK("virtual y resolution < physical y resolution not possible\n");

589

DPRINTK("virtual y resolution < physical y resolution not possible\n");

590

return -EINVAL;

590

return -EINVAL;

591

}

591

}

592

593

if (var->xoffset) {

593

if (var->xoffset) {

594

DPRINTK("xoffset not supported\n");

594

DPRINTK("xoffset not supported\n");

595

return -EINVAL;

595

return -EINVAL;

596

}

596

}

597

598

if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {

598

if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {

599

DPRINTK("interlace not supported\n");

599

DPRINTK("interlace not supported\n");

600

return -EINVAL;

600

return -EINVAL;

601

}

601

}

602

603

var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */

603

var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */

604

lpitch = var->xres * ((var->bits_per_pixel + 7)>>3);

604

lpitch = var->xres * ((var->bits_per_pixel + 7)>>3);

605

606

if (var->xres < 320 || var->xres > 1600) {

606

if (var->xres < 320 || var->xres > 1600) {

607

DPRINTK("width not supported: %u\n", var->xres);

607

DPRINTK("width not supported: %u\n", var->xres);

608

return -EINVAL;

608

return -EINVAL;

609

}

609

}

610

611

if (var->yres < 200 || var->yres > 1200) {

611

if (var->yres < 200 || var->yres > 1200) {

612

DPRINTK("height not supported: %u\n", var->yres);

612

DPRINTK("height not supported: %u\n", var->yres);

613

return -EINVAL;

613

return -EINVAL;

614

}

614

}

615

616

if (lpitch * var->yres_virtual > info->fix.smem_len) {

616

if (lpitch * var->yres_virtual > info->fix.smem_len) {

617

DPRINTK("no memory for screen (%ux%ux%u)\n",

617

DPRINTK("no memory for screen (%ux%ux%u)\n",

618

var->xres, var->yres_virtual, var->bits_per_pixel);

618

var->xres, var->yres_virtual, var->bits_per_pixel);

619

return -EINVAL;

619

return -EINVAL;

620

}

620

}

621

622

if (PICOS2KHZ(var->pixclock) > PM2_MAX_PIXCLOCK) {

622

if (PICOS2KHZ(var->pixclock) > PM2_MAX_PIXCLOCK) {

623

DPRINTK("pixclock too high (%ldKHz)\n", PICOS2KHZ(var->pixclock));

623

DPRINTK("pixclock too high (%ldKHz)\n", PICOS2KHZ(var->pixclock));

624

return -EINVAL;

624

return -EINVAL;

625

}

625

}

626

627

switch(var->bits_per_pixel) {

627

switch(var->bits_per_pixel) {

628

case 8:

628

case 8:

629

var->red.length = var->green.length = var->blue.length = 8;

629

var->red.length = var->green.length = var->blue.length = 8;

630

break;

630

break;

631

case 16:

631

case 16:

632

var->red.offset = 11;

632

var->red.offset = 11;

633

var->red.length = 5;

633

var->red.length = 5;

634

var->green.offset = 5;

634

var->green.offset = 5;

635

var->green.length = 6;

635

var->green.length = 6;

636

var->blue.offset = 0;

636

var->blue.offset = 0;

637

var->blue.length = 5;

637

var->blue.length = 5;

638

break;

638

break;

639

case 32:

639

case 32:

640

var->transp.offset = 24;

640

var->transp.offset = 24;

641

var->transp.length = 8;

641

var->transp.length = 8;

642

var->red.offset = 16;

642

var->red.offset = 16;

643

var->green.offset = 8;

643

var->green.offset = 8;

644

var->blue.offset = 0;

644

var->blue.offset = 0;

645

var->red.length = var->green.length = var->blue.length = 8;

645

var->red.length = var->green.length = var->blue.length = 8;

646

break;

646

break;

647

case 24:

647

case 24:

648

#ifdef __BIG_ENDIAN

648

#ifdef __BIG_ENDIAN

649

var->red.offset = 0;

649

var->red.offset = 0;

650

var->blue.offset = 16;

650

var->blue.offset = 16;

651

#else

651

#else

652

var->red.offset = 16;

652

var->red.offset = 16;

653

var->blue.offset = 0;

653

var->blue.offset = 0;

654

#endif

654

#endif

655

var->green.offset = 8;

655

var->green.offset = 8;

656

var->red.length = var->green.length = var->blue.length = 8;

656

var->red.length = var->green.length = var->blue.length = 8;

657

break;

657

break;

658

}

658

}

659

var->height = var->width = -1;

659

var->height = var->width = -1;

660

661

var->accel_flags = 0; /* Can't mmap if this is on */

661

var->accel_flags = 0; /* Can't mmap if this is on */

662

663

DPRINTK("Checking graphics mode at %dx%d depth %d\n",

663

DPRINTK("Checking graphics mode at %dx%d depth %d\n",

664

var->xres, var->yres, var->bits_per_pixel);

664

var->xres, var->yres, var->bits_per_pixel);

665

return 0;

665

return 0;

666

}

666

}

667

668

/**

668

/**

669

* pm2fb_set_par - Alters the hardware state.

669

* pm2fb_set_par - Alters the hardware state.

670

* @info: frame buffer structure that represents a single frame buffer

670

* @info: frame buffer structure that represents a single frame buffer

671

*

671

*

672

* Using the fb_var_screeninfo in fb_info we set the resolution of the

672

* Using the fb_var_screeninfo in fb_info we set the resolution of the

673

* this particular framebuffer.

673

* this particular framebuffer.

674

*/

674

*/

675

static int pm2fb_set_par(struct fb_info *info)

675

static int pm2fb_set_par(struct fb_info *info)

676

{

676

{

677

struct pm2fb_par *par = (struct pm2fb_par *) info->par;

677

struct pm2fb_par *par = (struct pm2fb_par *) info->par;

678

u32 pixclock;

678

u32 pixclock;

679

u32 width, height, depth;

679

u32 width, height, depth;

680

u32 hsstart, hsend, hbend, htotal;

680

u32 hsstart, hsend, hbend, htotal;

681

u32 vsstart, vsend, vbend, vtotal;

681

u32 vsstart, vsend, vbend, vtotal;

682

u32 stride;

682

u32 stride;

683

u32 base;

683

u32 base;

684

u32 video = 0;

684

u32 video = 0;

685

u32 clrmode = PM2F_RD_COLOR_MODE_RGB | PM2F_RD_GUI_ACTIVE;

685

u32 clrmode = PM2F_RD_COLOR_MODE_RGB | PM2F_RD_GUI_ACTIVE;

686

u32 txtmap = 0;

686

u32 txtmap = 0;

687

u32 pixsize = 0;

687

u32 pixsize = 0;

688

u32 clrformat = 0;

688

u32 clrformat = 0;

689

u32 xres;

689

u32 xres;

690

int data64;

690

int data64;

691

692

reset_card(par);

692

reset_card(par);

693

reset_config(par);

693

reset_config(par);

694

clear_palette(par);

694

clear_palette(par);

695

if ( par->memclock )

695

if ( par->memclock )

696

set_memclock(par, par->memclock);

696

set_memclock(par, par->memclock);

697

698

width = (info->var.xres_virtual + 7) & ~7;

698

width = (info->var.xres_virtual + 7) & ~7;

699

height = info->var.yres_virtual;

699

height = info->var.yres_virtual;

700

depth = (info->var.bits_per_pixel + 7) & ~7;

700

depth = (info->var.bits_per_pixel + 7) & ~7;

701

depth = (depth > 32) ? 32 : depth;

701

depth = (depth > 32) ? 32 : depth;

702

data64 = depth > 8 || par->type == PM2_TYPE_PERMEDIA2V;

702

data64 = depth > 8 || par->type == PM2_TYPE_PERMEDIA2V;

703

704

xres = (info->var.xres + 31) & ~31;

704

xres = (info->var.xres + 31) & ~31;

705

pixclock = PICOS2KHZ(info->var.pixclock);

705

pixclock = PICOS2KHZ(info->var.pixclock);

706

if (pixclock > PM2_MAX_PIXCLOCK) {

706

if (pixclock > PM2_MAX_PIXCLOCK) {

707

DPRINTK("pixclock too high (%uKHz)\n", pixclock);

707

DPRINTK("pixclock too high (%uKHz)\n", pixclock);

708

return -EINVAL;

708

return -EINVAL;

709

}

709

}

710

711

hsstart = to3264(info->var.right_margin, depth, data64);

711

hsstart = to3264(info->var.right_margin, depth, data64);

712

hsend = hsstart + to3264(info->var.hsync_len, depth, data64);

712

hsend = hsstart + to3264(info->var.hsync_len, depth, data64);

713

hbend = hsend + to3264(info->var.left_margin, depth, data64);

713

hbend = hsend + to3264(info->var.left_margin, depth, data64);

714

htotal = to3264(xres, depth, data64) + hbend - 1;

714

htotal = to3264(xres, depth, data64) + hbend - 1;

715

vsstart = (info->var.lower_margin)

715

vsstart = (info->var.lower_margin)

716

? info->var.lower_margin - 1

716

? info->var.lower_margin - 1

717

: 0; /* FIXME! */

717

: 0; /* FIXME! */

718

vsend = info->var.lower_margin + info->var.vsync_len - 1;

718

vsend = info->var.lower_margin + info->var.vsync_len - 1;

719

vbend = info->var.lower_margin + info->var.vsync_len + info->var.upper_margin;

719

vbend = info->var.lower_margin + info->var.vsync_len + info->var.upper_margin;

720

vtotal = info->var.yres + vbend - 1;

720

vtotal = info->var.yres + vbend - 1;

721

stride = to3264(width, depth, 1);

721

stride = to3264(width, depth, 1);

722

base = to3264(info->var.yoffset * xres + info->var.xoffset, depth, 1);

722

base = to3264(info->var.yoffset * xres + info->var.xoffset, depth, 1);

723

if (data64)

723

if (data64)

724

video |= PM2F_DATA_64_ENABLE;

724

video |= PM2F_DATA_64_ENABLE;

725

726

if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) {

726

if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) {

727

if (lowhsync) {

727

if (lowhsync) {

728

DPRINTK("ignoring +hsync, using -hsync.\n");

728

DPRINTK("ignoring +hsync, using -hsync.\n");

729

video |= PM2F_HSYNC_ACT_LOW;

729

video |= PM2F_HSYNC_ACT_LOW;

730

} else

730

} else

731

video |= PM2F_HSYNC_ACT_HIGH;

731

video |= PM2F_HSYNC_ACT_HIGH;

732

}

732

}

733

else

733

else

734

video |= PM2F_HSYNC_ACT_LOW;

734

video |= PM2F_HSYNC_ACT_LOW;

735

if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) {

735

if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) {

736

if (lowvsync) {

736

if (lowvsync) {

737

DPRINTK("ignoring +vsync, using -vsync.\n");

737

DPRINTK("ignoring +vsync, using -vsync.\n");

738

video |= PM2F_VSYNC_ACT_LOW;

738

video |= PM2F_VSYNC_ACT_LOW;

739

} else

739

} else

740

video |= PM2F_VSYNC_ACT_HIGH;

740

video |= PM2F_VSYNC_ACT_HIGH;

741

}

741

}

742

else

742

else

743

video |= PM2F_VSYNC_ACT_LOW;

743

video |= PM2F_VSYNC_ACT_LOW;

744

if ((info->var.vmode & FB_VMODE_MASK)==FB_VMODE_INTERLACED) {

744

if ((info->var.vmode & FB_VMODE_MASK)==FB_VMODE_INTERLACED) {

745

DPRINTK("interlaced not supported\n");

745

DPRINTK("interlaced not supported\n");

746

return -EINVAL;

746

return -EINVAL;

747

}

747

}

748

if ((info->var.vmode & FB_VMODE_MASK)==FB_VMODE_DOUBLE)

748

if ((info->var.vmode & FB_VMODE_MASK)==FB_VMODE_DOUBLE)

749

video |= PM2F_LINE_DOUBLE;

749

video |= PM2F_LINE_DOUBLE;

750

if ((info->var.activate & FB_ACTIVATE_MASK)==FB_ACTIVATE_NOW)

750

if ((info->var.activate & FB_ACTIVATE_MASK)==FB_ACTIVATE_NOW)

751

video |= PM2F_VIDEO_ENABLE;

751

video |= PM2F_VIDEO_ENABLE;

752

par->video = video;

752

par->video = video;

753

754

info->fix.visual =

754

info->fix.visual =

755

(depth == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;

755

(depth == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;

756

info->fix.line_length = info->var.xres * depth / 8;

756

info->fix.line_length = info->var.xres * depth / 8;

757

info->cmap.len = 256;

757

info->cmap.len = 256;

758

759

/*

759

/*

760

* Settings calculated. Now write them out.

760

* Settings calculated. Now write them out.

761

*/

761

*/

762

if (par->type == PM2_TYPE_PERMEDIA2V) {

762

if (par->type == PM2_TYPE_PERMEDIA2V) {

763

WAIT_FIFO(par, 1);

763

WAIT_FIFO(par, 1);

764

pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);

764

pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);

765

}

765

}

766

767

set_aperture(par, depth);

767

set_aperture(par, depth);

768

769

mb();

769

mb();

770

WAIT_FIFO(par, 19);

770

WAIT_FIFO(par, 19);

771

pm2_RDAC_WR(par, PM2I_RD_COLOR_KEY_CONTROL,

771

pm2_RDAC_WR(par, PM2I_RD_COLOR_KEY_CONTROL,

772

( depth == 8 ) ? 0 : PM2F_COLOR_KEY_TEST_OFF);

772

( depth == 8 ) ? 0 : PM2F_COLOR_KEY_TEST_OFF);

773

switch (depth) {

773

switch (depth) {

774

case 8:

774

case 8:

775

pm2_WR(par, PM2R_FB_READ_PIXEL, 0);

775

pm2_WR(par, PM2R_FB_READ_PIXEL, 0);

776

clrformat = 0x0e;

776

clrformat = 0x0e;

777

break;

777

break;

778

case 16:

778

case 16:

779

pm2_WR(par, PM2R_FB_READ_PIXEL, 1);

779

pm2_WR(par, PM2R_FB_READ_PIXEL, 1);

780

clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB565;

780

clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB565;

781

txtmap = PM2F_TEXTEL_SIZE_16;

781

txtmap = PM2F_TEXTEL_SIZE_16;

782

pixsize = 1;

782

pixsize = 1;

783

clrformat = 0x70;

783

clrformat = 0x70;

784

break;

784

break;

785

case 32:

785

case 32:

786

pm2_WR(par, PM2R_FB_READ_PIXEL, 2);

786

pm2_WR(par, PM2R_FB_READ_PIXEL, 2);

787

clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGBA8888;

787

clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGBA8888;

788

txtmap = PM2F_TEXTEL_SIZE_32;

788

txtmap = PM2F_TEXTEL_SIZE_32;

789

pixsize = 2;

789

pixsize = 2;

790

clrformat = 0x20;

790

clrformat = 0x20;

791

break;

791

break;

792

case 24:

792

case 24:

793

pm2_WR(par, PM2R_FB_READ_PIXEL, 4);

793

pm2_WR(par, PM2R_FB_READ_PIXEL, 4);

794

clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB888;

794

clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB888;

795

txtmap = PM2F_TEXTEL_SIZE_24;

795

txtmap = PM2F_TEXTEL_SIZE_24;

796

pixsize = 4;

796

pixsize = 4;

797

clrformat = 0x20;

797

clrformat = 0x20;

798

break;

798

break;

799

}

799

}

800

pm2_WR(par, PM2R_FB_WRITE_MODE, PM2F_FB_WRITE_ENABLE);

800

pm2_WR(par, PM2R_FB_WRITE_MODE, PM2F_FB_WRITE_ENABLE);

801

pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres));

801

pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres));

802

pm2_WR(par, PM2R_LB_READ_MODE, partprod(xres));

802

pm2_WR(par, PM2R_LB_READ_MODE, partprod(xres));

803

pm2_WR(par, PM2R_TEXTURE_MAP_FORMAT, txtmap | partprod(xres));

803

pm2_WR(par, PM2R_TEXTURE_MAP_FORMAT, txtmap | partprod(xres));

804

pm2_WR(par, PM2R_H_TOTAL, htotal);

804

pm2_WR(par, PM2R_H_TOTAL, htotal);

805

pm2_WR(par, PM2R_HS_START, hsstart);

805

pm2_WR(par, PM2R_HS_START, hsstart);

806

pm2_WR(par, PM2R_HS_END, hsend);

806

pm2_WR(par, PM2R_HS_END, hsend);

807

pm2_WR(par, PM2R_HG_END, hbend);

807

pm2_WR(par, PM2R_HG_END, hbend);

808

pm2_WR(par, PM2R_HB_END, hbend);

808

pm2_WR(par, PM2R_HB_END, hbend);

809

pm2_WR(par, PM2R_V_TOTAL, vtotal);

809

pm2_WR(par, PM2R_V_TOTAL, vtotal);

810

pm2_WR(par, PM2R_VS_START, vsstart);

810

pm2_WR(par, PM2R_VS_START, vsstart);

811

pm2_WR(par, PM2R_VS_END, vsend);

811

pm2_WR(par, PM2R_VS_END, vsend);

812

pm2_WR(par, PM2R_VB_END, vbend);

812

pm2_WR(par, PM2R_VB_END, vbend);

813

pm2_WR(par, PM2R_SCREEN_STRIDE, stride);

813

pm2_WR(par, PM2R_SCREEN_STRIDE, stride);

814

wmb();

814

wmb();

815

pm2_WR(par, PM2R_WINDOW_ORIGIN, 0);

815

pm2_WR(par, PM2R_WINDOW_ORIGIN, 0);

816

pm2_WR(par, PM2R_SCREEN_SIZE, (height << 16) | width);

816

pm2_WR(par, PM2R_SCREEN_SIZE, (height << 16) | width);

817

pm2_WR(par, PM2R_SCISSOR_MODE, PM2F_SCREEN_SCISSOR_ENABLE);

817

pm2_WR(par, PM2R_SCISSOR_MODE, PM2F_SCREEN_SCISSOR_ENABLE);

818

wmb();

818

wmb();

819

pm2_WR(par, PM2R_SCREEN_BASE, base);

819

pm2_WR(par, PM2R_SCREEN_BASE, base);

820

wmb();

820

wmb();

821

set_video(par, video);

821

set_video(par, video);

822

WAIT_FIFO(par, 4);

822

WAIT_FIFO(par, 4);

823

switch (par->type) {

823

switch (par->type) {

824

case PM2_TYPE_PERMEDIA2:

824

case PM2_TYPE_PERMEDIA2:

825

pm2_RDAC_WR(par, PM2I_RD_COLOR_MODE, clrmode);

825

pm2_RDAC_WR(par, PM2I_RD_COLOR_MODE, clrmode);

826

break;

826

break;

827

case PM2_TYPE_PERMEDIA2V:

827

case PM2_TYPE_PERMEDIA2V:

828

pm2v_RDAC_WR(par, PM2VI_RD_PIXEL_SIZE, pixsize);

828

pm2v_RDAC_WR(par, PM2VI_RD_PIXEL_SIZE, pixsize);

829

pm2v_RDAC_WR(par, PM2VI_RD_COLOR_FORMAT, clrformat);

829

pm2v_RDAC_WR(par, PM2VI_RD_COLOR_FORMAT, clrformat);

830

break;

830

break;

831

}

831

}

832

set_pixclock(par, pixclock);

832

set_pixclock(par, pixclock);

833

DPRINTK("Setting graphics mode at %dx%d depth %d\n",

833

DPRINTK("Setting graphics mode at %dx%d depth %d\n",

834

info->var.xres, info->var.yres, info->var.bits_per_pixel);

834

info->var.xres, info->var.yres, info->var.bits_per_pixel);

835

return 0;

835

return 0;

836

}

836

}

837

838

/**

838

/**

839

* pm2fb_setcolreg - Sets a color register.

839

* pm2fb_setcolreg - Sets a color register.

840

* @regno: boolean, 0 copy local, 1 get_user() function

840

* @regno: boolean, 0 copy local, 1 get_user() function

841

* @red: frame buffer colormap structure

841

* @red: frame buffer colormap structure

842

* @green: The green value which can be up to 16 bits wide

842

* @green: The green value which can be up to 16 bits wide

843

* @blue: The blue value which can be up to 16 bits wide.

843

* @blue: The blue value which can be up to 16 bits wide.

844

* @transp: If supported the alpha value which can be up to 16 bits wide.

844

* @transp: If supported the alpha value which can be up to 16 bits wide.

845

* @info: frame buffer info structure

845

* @info: frame buffer info structure

846

*

846

*

847

* Set a single color register. The values supplied have a 16 bit

847

* Set a single color register. The values supplied have a 16 bit

848

* magnitude which needs to be scaled in this function for the hardware.

848

* magnitude which needs to be scaled in this function for the hardware.

849

* Pretty much a direct lift from tdfxfb.c.

849

* Pretty much a direct lift from tdfxfb.c.

850

*

850

*

851

* Returns negative errno on error, or zero on success.

851

* Returns negative errno on error, or zero on success.

852

*/

852

*/

853

static int pm2fb_setcolreg(unsigned regno, unsigned red, unsigned green,

853

static int pm2fb_setcolreg(unsigned regno, unsigned red, unsigned green,

854

unsigned blue, unsigned transp,

854

unsigned blue, unsigned transp,

855

struct fb_info *info)

855

struct fb_info *info)

856

{

856

{

857

struct pm2fb_par *par = (struct pm2fb_par *) info->par;

857

struct pm2fb_par *par = (struct pm2fb_par *) info->par;

858

859

if (regno >= info->cmap.len) /* no. of hw registers */

859

if (regno >= info->cmap.len) /* no. of hw registers */

860

return 1;

860

return 1;

861

/*

861

/*

862

* Program hardware... do anything you want with transp

862

* Program hardware... do anything you want with transp

863

*/

863

*/

864

865

/* grayscale works only partially under directcolor */

865

/* grayscale works only partially under directcolor */

866

if (info->var.grayscale) {

866

if (info->var.grayscale) {

867

/* grayscale = 0.30*R + 0.59*G + 0.11*B */

867

/* grayscale = 0.30*R + 0.59*G + 0.11*B */

868

red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;

868

red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;

869

}

869

}

870

871

/* Directcolor:

871

/* Directcolor:

872

* var->{color}.offset contains start of bitfield

872

* var->{color}.offset contains start of bitfield

873

* var->{color}.length contains length of bitfield

873

* var->{color}.length contains length of bitfield

874

* {hardwarespecific} contains width of DAC

874

* {hardwarespecific} contains width of DAC

875

* cmap[X] is programmed to

875

* cmap[X] is programmed to

876

* (X << red.offset) | (X << green.offset) | (X << blue.offset)

876

* (X << red.offset) | (X << green.offset) | (X << blue.offset)

877

* RAMDAC[X] is programmed to (red, green, blue)

877

* RAMDAC[X] is programmed to (red, green, blue)

878

*

878

*

879

* Pseudocolor:

879

* Pseudocolor:

880

* uses offset = 0 && length = DAC register width.

880

* uses offset = 0 && length = DAC register width.

881

* var->{color}.offset is 0

881

* var->{color}.offset is 0

882

* var->{color}.length contains widht of DAC

882

* var->{color}.length contains widht of DAC

883

* cmap is not used

883

* cmap is not used

884

* DAC[X] is programmed to (red, green, blue)

884

* DAC[X] is programmed to (red, green, blue)

885

* Truecolor:

885

* Truecolor:

886

* does not use RAMDAC (usually has 3 of them).

886

* does not use RAMDAC (usually has 3 of them).

887

* var->{color}.offset contains start of bitfield

887

* var->{color}.offset contains start of bitfield

888

* var->{color}.length contains length of bitfield

888

* var->{color}.length contains length of bitfield

889

* cmap is programmed to

889

* cmap is programmed to

890

* (red << red.offset) | (green << green.offset) |

890

* (red << red.offset) | (green << green.offset) |

891

* (blue << blue.offset) | (transp << transp.offset)

891

* (blue << blue.offset) | (transp << transp.offset)

892

* RAMDAC does not exist

892

* RAMDAC does not exist

893

*/

893

*/

894

#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)

894

#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)

895

switch (info->fix.visual) {

895

switch (info->fix.visual) {

896

case FB_VISUAL_TRUECOLOR:

896

case FB_VISUAL_TRUECOLOR:

897

case FB_VISUAL_PSEUDOCOLOR:

897

case FB_VISUAL_PSEUDOCOLOR:

898

red = CNVT_TOHW(red, info->var.red.length);

898

red = CNVT_TOHW(red, info->var.red.length);

899

green = CNVT_TOHW(green, info->var.green.length);

899

green = CNVT_TOHW(green, info->var.green.length);

900

blue = CNVT_TOHW(blue, info->var.blue.length);

900

blue = CNVT_TOHW(blue, info->var.blue.length);

901

transp = CNVT_TOHW(transp, info->var.transp.length);

901

transp = CNVT_TOHW(transp, info->var.transp.length);

902

break;

902

break;

903

case FB_VISUAL_DIRECTCOLOR:

903

case FB_VISUAL_DIRECTCOLOR:

904

/* example here assumes 8 bit DAC. Might be different

904

/* example here assumes 8 bit DAC. Might be different

905

* for your hardware */

905

* for your hardware */

906

red = CNVT_TOHW(red, 8);

906

red = CNVT_TOHW(red, 8);

907

green = CNVT_TOHW(green, 8);

907

green = CNVT_TOHW(green, 8);

908

blue = CNVT_TOHW(blue, 8);

908

blue = CNVT_TOHW(blue, 8);

909

/* hey, there is bug in transp handling... */

909

/* hey, there is bug in transp handling... */

910

transp = CNVT_TOHW(transp, 8);

910

transp = CNVT_TOHW(transp, 8);

911

break;

911

break;

912

}

912

}

913

#undef CNVT_TOHW

913

#undef CNVT_TOHW

914

/* Truecolor has hardware independent palette */

914

/* Truecolor has hardware independent palette */

915

if (info->fix.visual == FB_VISUAL_TRUECOLOR) {

915

if (info->fix.visual == FB_VISUAL_TRUECOLOR) {

916

u32 v;

916

u32 v;

917

918

if (regno >= 16)

918

if (regno >= 16)

919

return 1;

919

return 1;

920

921

v = (red << info->var.red.offset) |

921

v = (red << info->var.red.offset) |

922

(green << info->var.green.offset) |

922

(green << info->var.green.offset) |

923

(blue << info->var.blue.offset) |

923

(blue << info->var.blue.offset) |

924

(transp << info->var.transp.offset);

924

(transp << info->var.transp.offset);

925

926

switch (info->var.bits_per_pixel) {

926

switch (info->var.bits_per_pixel) {

927

case 8:

927

case 8:

928

break;

928

break;

929

case 16:

929

case 16:

930

case 24:

930

case 24:

931

case 32:

931

case 32:

932

((u32*)(info->pseudo_palette))[regno] = v;

932

((u32*)(info->pseudo_palette))[regno] = v;

933

break;

933

break;

934

}

934

}

935

return 0;

935

return 0;

936

}

936

}

937

else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)

937

else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)

938

set_color(par, regno, red, green, blue);

938

set_color(par, regno, red, green, blue);

939

940

return 0;

940

return 0;

941

}

941

}

942

943

/**

943

/**

944

* pm2fb_pan_display - Pans the display.

944

* pm2fb_pan_display - Pans the display.

945

* @var: frame buffer variable screen structure

945

* @var: frame buffer variable screen structure

946

* @info: frame buffer structure that represents a single frame buffer

946

* @info: frame buffer structure that represents a single frame buffer

947

*

947

*

948

* Pan (or wrap, depending on the `vmode' field) the display using the

948

* Pan (or wrap, depending on the `vmode' field) the display using the

949

* `xoffset' and `yoffset' fields of the `var' structure.

949

* `xoffset' and `yoffset' fields of the `var' structure.

950

* If the values don't fit, return -EINVAL.

950

* If the values don't fit, return -EINVAL.

951

*

951

*

952

* Returns negative errno on error, or zero on success.

952

* Returns negative errno on error, or zero on success.

953

*

953

*

954

*/

954

*/

955

static int pm2fb_pan_display(struct fb_var_screeninfo *var,

955

static int pm2fb_pan_display(struct fb_var_screeninfo *var,

956

struct fb_info *info)

956

struct fb_info *info)

957

{

957

{

958

struct pm2fb_par *p = (struct pm2fb_par *) info->par;

958

struct pm2fb_par *p = (struct pm2fb_par *) info->par;

959

u32 base;

959

u32 base;

960

u32 depth;

960

u32 depth;

961

u32 xres;

961

u32 xres;

962

963

xres = (var->xres + 31) & ~31;

963

xres = (var->xres + 31) & ~31;

964

depth = (var->bits_per_pixel + 7) & ~7;

964

depth = (var->bits_per_pixel + 7) & ~7;

965

depth = (depth > 32) ? 32 : depth;

965

depth = (depth > 32) ? 32 : depth;

966

base = to3264(var->yoffset * xres + var->xoffset, depth, 1);

966

base = to3264(var->yoffset * xres + var->xoffset, depth, 1);

967

WAIT_FIFO(p, 1);

967

WAIT_FIFO(p, 1);

968

pm2_WR(p, PM2R_SCREEN_BASE, base);

968

pm2_WR(p, PM2R_SCREEN_BASE, base);

969

return 0;

969

return 0;

970

}

970

}

971

972

/**

972

/**

973

* pm2fb_blank - Blanks the display.

973

* pm2fb_blank - Blanks the display.

974

* @blank_mode: the blank mode we want.

974

* @blank_mode: the blank mode we want.

975

* @info: frame buffer structure that represents a single frame buffer

975

* @info: frame buffer structure that represents a single frame buffer

976

*

976

*

977

* Blank the screen if blank_mode != 0, else unblank. Return 0 if

977

* Blank the screen if blank_mode != 0, else unblank. Return 0 if

978

* blanking succeeded, != 0 if un-/blanking failed due to e.g. a

978

* blanking succeeded, != 0 if un-/blanking failed due to e.g. a

979

* video mode which doesn't support it. Implements VESA suspend

979

* video mode which doesn't support it. Implements VESA suspend

980

* and powerdown modes on hardware that supports disabling hsync/vsync:

980

* and powerdown modes on hardware that supports disabling hsync/vsync:

981

* blank_mode == 2: suspend vsync

981

* blank_mode == 2: suspend vsync

982

* blank_mode == 3: suspend hsync

982

* blank_mode == 3: suspend hsync

983

* blank_mode == 4: powerdown

983

* blank_mode == 4: powerdown

984

*

984

*

985

* Returns negative errno on error, or zero on success.

985

* Returns negative errno on error, or zero on success.

986

*

986

*

987

*/

987

*/

988

static int pm2fb_blank(int blank_mode, struct fb_info *info)

988

static int pm2fb_blank(int blank_mode, struct fb_info *info)

989

{

989

{

990

struct pm2fb_par *par = (struct pm2fb_par *) info->par;

990

struct pm2fb_par *par = (struct pm2fb_par *) info->par;

991

u32 video = par->video;

991

u32 video = par->video;

992

993

DPRINTK("blank_mode %d\n", blank_mode);

993

DPRINTK("blank_mode %d\n", blank_mode);

994

995

switch (blank_mode) {

995

switch (blank_mode) {

996

case FB_BLANK_UNBLANK:

996

case FB_BLANK_UNBLANK:

997

/* Screen: On */

997

/* Screen: On */

998

video |= PM2F_VIDEO_ENABLE;

998

video |= PM2F_VIDEO_ENABLE;

999

break;

999

break;

1000

case FB_BLANK_NORMAL:

1000

case FB_BLANK_NORMAL:

1001

/* Screen: Off */

1001

/* Screen: Off */

1002

video &= ~PM2F_VIDEO_ENABLE;

1002

video &= ~PM2F_VIDEO_ENABLE;

1003

break;

1003

break;

1004

case FB_BLANK_VSYNC_SUSPEND:

1004

case FB_BLANK_VSYNC_SUSPEND:

1005

/* VSync: Off */

1005

/* VSync: Off */

1006

video &= ~(PM2F_VSYNC_MASK | PM2F_BLANK_LOW );

1006

video &= ~(PM2F_VSYNC_MASK | PM2F_BLANK_LOW );

1007

break;

1007

break;

1008

case FB_BLANK_HSYNC_SUSPEND:

1008

case FB_BLANK_HSYNC_SUSPEND:

1009

/* HSync: Off */

1009

/* HSync: Off */

1010

video &= ~(PM2F_HSYNC_MASK | PM2F_BLANK_LOW );

1010

video &= ~(PM2F_HSYNC_MASK | PM2F_BLANK_LOW );

1011

break;

1011

break;

1012

case FB_BLANK_POWERDOWN:

1012

case FB_BLANK_POWERDOWN:

1013

/* HSync: Off, VSync: Off */

1013

/* HSync: Off, VSync: Off */

1014

video &= ~(PM2F_VSYNC_MASK | PM2F_HSYNC_MASK| PM2F_BLANK_LOW);

1014

video &= ~(PM2F_VSYNC_MASK | PM2F_HSYNC_MASK| PM2F_BLANK_LOW);

1015

break;

1015

break;

1016

}

1016

}

1017

set_video(par, video);

1017

set_video(par, video);

1018

return 0;

1018

return 0;

1019

}

1019

}

1020

1021

/* ------------ Hardware Independent Functions ------------ */

1021

/* ------------ Hardware Independent Functions ------------ */

1022

1023

/*

1023

/*

1024

* Frame buffer operations

1024

* Frame buffer operations

1025

*/

1025

*/

1026

1027

static struct fb_ops pm2fb_ops = {

1027

static struct fb_ops pm2fb_ops = {

1028

.owner = THIS_MODULE,

1028

.owner = THIS_MODULE,

1029

.fb_check_var = pm2fb_check_var,

1029

.fb_check_var = pm2fb_check_var,

1030

.fb_set_par = pm2fb_set_par,

1030

.fb_set_par = pm2fb_set_par,

1031

.fb_setcolreg = pm2fb_setcolreg,

1031

.fb_setcolreg = pm2fb_setcolreg,

1032

.fb_blank = pm2fb_blank,

1032

.fb_blank = pm2fb_blank,

1033

.fb_pan_display = pm2fb_pan_display,

1033

.fb_pan_display = pm2fb_pan_display,

1034

.fb_fillrect = cfb_fillrect,

1034

.fb_fillrect = cfb_fillrect,

1035

.fb_copyarea = cfb_copyarea,

1035

.fb_copyarea = cfb_copyarea,

1036

.fb_imageblit = cfb_imageblit,

1036

.fb_imageblit = cfb_imageblit,

1037

};

1037

};

1038

1039

/*

1039

/*

1040

* PCI stuff

1040

* PCI stuff

1041

*/

1041

*/

1042

1043

1044

/**

1044

/**

1045

* Device initialisation

1045

* Device initialisation

1046

*

1046

*

1047

* Initialise and allocate resource for PCI device.

1047

* Initialise and allocate resource for PCI device.

1048

*

1048

*

1049

* @param pdev PCI device.

1049

* @param pdev PCI device.

1050

* @param id PCI device ID.

1050

* @param id PCI device ID.

1051

*/

1051

*/

1052

static int __devinit pm2fb_probe(struct pci_dev *pdev,

1052

static int __devinit pm2fb_probe(struct pci_dev *pdev,

1053

const struct pci_device_id *id)

1053

const struct pci_device_id *id)

1054

{

1054

{

1055

struct pm2fb_par *default_par;

1055

struct pm2fb_par *default_par;

1056

struct fb_info *info;

1056

struct fb_info *info;

1057

int size, err;

1057

int size, err;

1058

int err_retval = -ENXIO;

1058

int err_retval = -ENXIO;

1059

1060

err = pci_enable_device(pdev);

1060

err = pci_enable_device(pdev);

1061

if ( err ) {

1061

if ( err ) {

1062

printk(KERN_WARNING "pm2fb: Can't enable pdev: %d\n", err);

1062

printk(KERN_WARNING "pm2fb: Can't enable pdev: %d\n", err);

1063

return err;

1063

return err;

1064

}

1064

}

1065

1066

size = sizeof(struct pm2fb_par) + 256 * sizeof(u32);

1066

size = sizeof(struct pm2fb_par) + 256 * sizeof(u32);

1067

info = framebuffer_alloc(size, &pdev->dev);

1067

info = framebuffer_alloc(size, &pdev->dev);

1068

if ( !info )

1068

if ( !info )

1069

return -ENOMEM;

1069

return -ENOMEM;

1070

default_par = (struct pm2fb_par *) info->par;

1070

default_par = (struct pm2fb_par *) info->par;

1071

1072

switch (pdev->device) {

1072

switch (pdev->device) {

1073

case PCI_DEVICE_ID_TI_TVP4020:

1073

case PCI_DEVICE_ID_TI_TVP4020:

1074

strcpy(pm2fb_fix.id, "TVP4020");

1074

strcpy(pm2fb_fix.id, "TVP4020");

1075

default_par->type = PM2_TYPE_PERMEDIA2;

1075

default_par->type = PM2_TYPE_PERMEDIA2;

1076

break;

1076

break;

1077

case PCI_DEVICE_ID_3DLABS_PERMEDIA2:

1077

case PCI_DEVICE_ID_3DLABS_PERMEDIA2:

1078

strcpy(pm2fb_fix.id, "Permedia2");

1078

strcpy(pm2fb_fix.id, "Permedia2");

1079

default_par->type = PM2_TYPE_PERMEDIA2;

1079

default_par->type = PM2_TYPE_PERMEDIA2;

1080

break;

1080

break;

1081

case PCI_DEVICE_ID_3DLABS_PERMEDIA2V:

1081

case PCI_DEVICE_ID_3DLABS_PERMEDIA2V:

1082

strcpy(pm2fb_fix.id, "Permedia2v");

1082

strcpy(pm2fb_fix.id, "Permedia2v");

1083

default_par->type = PM2_TYPE_PERMEDIA2V;

1083

default_par->type = PM2_TYPE_PERMEDIA2V;

1084

break;

1084

break;

1085

}

1085

}

1086

1087

pm2fb_fix.mmio_start = pci_resource_start(pdev, 0);

1087

pm2fb_fix.mmio_start = pci_resource_start(pdev, 0);

1088

pm2fb_fix.mmio_len = PM2_REGS_SIZE;

1088

pm2fb_fix.mmio_len = PM2_REGS_SIZE;

1089

1090

#if defined(__BIG_ENDIAN)

1090

#if defined(__BIG_ENDIAN)

1091

/*

1091

/*

1092

* PM2 has a 64k register file, mapped twice in 128k. Lower

1092

* PM2 has a 64k register file, mapped twice in 128k. Lower

1093

* map is little-endian, upper map is big-endian.

1093

* map is little-endian, upper map is big-endian.

1094

*/

1094

*/

1095

pm2fb_fix.mmio_start += PM2_REGS_SIZE;

1095

pm2fb_fix.mmio_start += PM2_REGS_SIZE;

1096

DPRINTK("Adjusting register base for big-endian.\n");

1096

DPRINTK("Adjusting register base for big-endian.\n");

1097

#endif

1097

#endif

1098

DPRINTK("Register base at 0x%lx\n", pm2fb_fix.mmio_start);

1098

DPRINTK("Register base at 0x%lx\n", pm2fb_fix.mmio_start);

1099

1100

/* Registers - request region and map it. */

1100

/* Registers - request region and map it. */

1101

if ( !request_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len,

1101

if ( !request_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len,

1102

"pm2fb regbase") ) {

1102

"pm2fb regbase") ) {

1103

printk(KERN_WARNING "pm2fb: Can't reserve regbase.\n");

1103

printk(KERN_WARNING "pm2fb: Can't reserve regbase.\n");

1104

goto err_exit_neither;

1104

goto err_exit_neither;

1105

}

1105

}

1106

default_par->v_regs =

1106

default_par->v_regs =

1107

ioremap_nocache(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);

1107

ioremap_nocache(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);

1108

if ( !default_par->v_regs ) {

1108

if ( !default_par->v_regs ) {

1109

printk(KERN_WARNING "pm2fb: Can't remap %s register area.\n",

1109

printk(KERN_WARNING "pm2fb: Can't remap %s register area.\n",

1110

pm2fb_fix.id);

1110

pm2fb_fix.id);

1111

release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);

1111

release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);

1112

goto err_exit_neither;

1112

goto err_exit_neither;

1113

}

1113

}

1114

1115

/* Stash away memory register info for use when we reset the board */

1115

/* Stash away memory register info for use when we reset the board */

1116

default_par->mem_control = pm2_RD(default_par, PM2R_MEM_CONTROL);

1116

default_par->mem_control = pm2_RD(default_par, PM2R_MEM_CONTROL);

1117

default_par->boot_address = pm2_RD(default_par, PM2R_BOOT_ADDRESS);

1117

default_par->boot_address = pm2_RD(default_par, PM2R_BOOT_ADDRESS);

1118

default_par->mem_config = pm2_RD(default_par, PM2R_MEM_CONFIG);

1118

default_par->mem_config = pm2_RD(default_par, PM2R_MEM_CONFIG);

1119

DPRINTK("MemControl 0x%x BootAddress 0x%x MemConfig 0x%x\n",

1119

DPRINTK("MemControl 0x%x BootAddress 0x%x MemConfig 0x%x\n",

1120

default_par->mem_control, default_par->boot_address,

1120

default_par->mem_control, default_par->boot_address,

1121

default_par->mem_config);

1121

default_par->mem_config);

1122

1123

if(default_par->mem_control == 0 &&

1124

default_par->boot_address == 0x31 &&

1125

default_par->mem_config == 0x259fffff &&

1126

pdev->subsystem_vendor == 0x1048 &&

1127

pdev->subsystem_device == 0x0a31) {

1128

DPRINTK("subsystem_vendor: %04x, subsystem_device: %04x\n",

1129

pdev->subsystem_vendor, pdev->subsystem_device);

1130

DPRINTK("We have not been initialized by VGA BIOS "

1131

"and are running on an Elsa Winner 2000 Office\n");

1132

DPRINTK("Initializing card timings manually...\n");

1133

default_par->mem_control=0;

1134

default_par->boot_address=0x20;

1135

default_par->mem_config=0xe6002021;

1136

default_par->memclock=100000;

1137

}

1138

1123

/* Now work out how big lfb is going to be. */

1139

/* Now work out how big lfb is going to be. */

1124

switch(default_par->mem_config & PM2F_MEM_CONFIG_RAM_MASK) {

1140

switch(default_par->mem_config & PM2F_MEM_CONFIG_RAM_MASK) {

1125

case PM2F_MEM_BANKS_1:

1141

case PM2F_MEM_BANKS_1:

1126

default_par->fb_size=0x200000;

1142

default_par->fb_size=0x200000;

1127

break;

1143

break;

1128

case PM2F_MEM_BANKS_2:

1144

case PM2F_MEM_BANKS_2:

1129

default_par->fb_size=0x400000;

1145

default_par->fb_size=0x400000;

1130

break;

1146

break;

1131

case PM2F_MEM_BANKS_3:

1147

case PM2F_MEM_BANKS_3:

1132

default_par->fb_size=0x600000;

1148

default_par->fb_size=0x600000;

1133

break;

1149

break;

1134

case PM2F_MEM_BANKS_4:

1150

case PM2F_MEM_BANKS_4:

1135

default_par->fb_size=0x800000;

1151

default_par->fb_size=0x800000;

1136

break;

1152

break;

1137

}

1153

}

1138

default_par->memclock = CVPPC_MEMCLOCK;

1154

default_par->memclock = CVPPC_MEMCLOCK;

1139

pm2fb_fix.smem_start = pci_resource_start(pdev, 1);

1155

pm2fb_fix.smem_start = pci_resource_start(pdev, 1);

1140

pm2fb_fix.smem_len = default_par->fb_size;

1156

pm2fb_fix.smem_len = default_par->fb_size;

1141

1157

1142

/* Linear frame buffer - request region and map it. */

1158

/* Linear frame buffer - request region and map it. */

1143

if ( !request_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len,

1159

if ( !request_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len,

1144

"pm2fb smem") ) {

1160

"pm2fb smem") ) {

1145

printk(KERN_WARNING "pm2fb: Can't reserve smem.\n");

1161

printk(KERN_WARNING "pm2fb: Can't reserve smem.\n");

1146

goto err_exit_mmio;

1162

goto err_exit_mmio;

1147

}

1163

}

1148

info->screen_base = default_par->v_fb =

1164

info->screen_base = default_par->v_fb =

1149

ioremap_nocache(pm2fb_fix.smem_start, pm2fb_fix.smem_len);

1165

ioremap_nocache(pm2fb_fix.smem_start, pm2fb_fix.smem_len);

1150

if ( !default_par->v_fb ) {

1166

if ( !default_par->v_fb ) {

1151

printk(KERN_WARNING "pm2fb: Can't ioremap smem area.\n");

1167

printk(KERN_WARNING "pm2fb: Can't ioremap smem area.\n");

1152

release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);

1168

release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);

1153

goto err_exit_mmio;

1169

goto err_exit_mmio;

1154

}

1170

}

1155

1171

1156

info->fbops = &pm2fb_ops;

1172

info->fbops = &pm2fb_ops;

1157

info->fix = pm2fb_fix;

1173

info->fix = pm2fb_fix;

1158

info->pseudo_palette = (void *)(default_par + 1);

1174

info->pseudo_palette = (void *)(default_par + 1);

1159

info->flags = FBINFO_DEFAULT |

1175

info->flags = FBINFO_DEFAULT |

1160

FBINFO_HWACCEL_YPAN;

1176

FBINFO_HWACCEL_YPAN;

1161

1177

1162

if (!mode)

1178

if (!mode)

1163

mode = "640x480@60";

1179

mode = "640x480@60";

1164

1180

1165

err = fb_find_mode(&info->var, info, mode, NULL, 0, NULL, 8);

1181

err = fb_find_mode(&info->var, info, mode, NULL, 0, NULL, 8);

1166

if (!err || err == 4)

1182

if (!err || err == 4)

1167

info->var = pm2fb_var;

1183

info->var = pm2fb_var;

1168

1184

1169

if (fb_alloc_cmap(&info->cmap, 256, 0) < 0)

1185

if (fb_alloc_cmap(&info->cmap, 256, 0) < 0)

1170

goto err_exit_all;

1186

goto err_exit_all;

1171

1187

1172

if (register_framebuffer(info) < 0)

1188

if (register_framebuffer(info) < 0)

1173

goto err_exit_both;

1189

goto err_exit_both;

1174

1190

1175

printk(KERN_INFO "fb%d: %s frame buffer device, memory = %dK.\n",

1191

printk(KERN_INFO "fb%d: %s frame buffer device, memory = %dK.\n",

1176

info->node, info->fix.id, default_par->fb_size / 1024);

1192

info->node, info->fix.id, default_par->fb_size / 1024);

1177

1193

1178

/*

1194

/*

1179

* Our driver data

1195

* Our driver data

1180

*/

1196

*/

1181

pci_set_drvdata(pdev, info);

1197

pci_set_drvdata(pdev, info);

1182

1198

1183

return 0;

1199

return 0;

1184

1200

1185

err_exit_all:

1201

err_exit_all:

1186

fb_dealloc_cmap(&info->cmap);

1202

fb_dealloc_cmap(&info->cmap);

1187

err_exit_both:

1203

err_exit_both:

1188

iounmap(info->screen_base);

1204

iounmap(info->screen_base);

1189

release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);

1205

release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);

1190

err_exit_mmio:

1206

err_exit_mmio:

1191

iounmap(default_par->v_regs);

1207

iounmap(default_par->v_regs);

1192

release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);

1208

release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);

1193

err_exit_neither:

1209

err_exit_neither:

1194

framebuffer_release(info);

1210

framebuffer_release(info);

1195

return err_retval;

1211

return err_retval;

1196

}

1212

}

1197

1213

1198

/**

1214

/**

1199

* Device removal.

1215

* Device removal.

1200

*

1216

*

1201

* Release all device resources.

1217

* Release all device resources.

1202

*

1218

*

1203

* @param pdev PCI device to clean up.

1219

* @param pdev PCI device to clean up.

1204

*/

1220

*/

1205

static void __devexit pm2fb_remove(struct pci_dev *pdev)

1221

static void __devexit pm2fb_remove(struct pci_dev *pdev)

1206

{

1222

{

1207

struct fb_info* info = pci_get_drvdata(pdev);

1223

struct fb_info* info = pci_get_drvdata(pdev);

1208

struct fb_fix_screeninfo* fix = &info->fix;

1224

struct fb_fix_screeninfo* fix = &info->fix;

1209

struct pm2fb_par *par = info->par;

1225

struct pm2fb_par *par = info->par;

1210

1226

1211

unregister_framebuffer(info);

1227

unregister_framebuffer(info);

1212

1228

1213

iounmap(info->screen_base);

1229

iounmap(info->screen_base);

1214

release_mem_region(fix->smem_start, fix->smem_len);

1230

release_mem_region(fix->smem_start, fix->smem_len);

1215

iounmap(par->v_regs);

1231

iounmap(par->v_regs);

1216

release_mem_region(fix->mmio_start, fix->mmio_len);

1232

release_mem_region(fix->mmio_start, fix->mmio_len);

1217

1233

1218

pci_set_drvdata(pdev, NULL);

1234

pci_set_drvdata(pdev, NULL);

1219

kfree(info);

1235

kfree(info);

1220

}

1236

}

1221

1237

1222

static struct pci_device_id pm2fb_id_table[] = {

1238

static struct pci_device_id pm2fb_id_table[] = {

1223

{ PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TVP4020,

1239

{ PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TVP4020,

1224

PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,

1240

PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,

1225

0xff0000, 0 },

1241

0xff0000, 0 },

1226

{ PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2,

1242

{ PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2,

1227

PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,

1243

PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,

1228

0xff0000, 0 },

1244

0xff0000, 0 },

1229

{ PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,

1245

{ PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,

1230

PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,

1246

PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,

1231

0xff0000, 0 },

1247

0xff0000, 0 },

1232

{ 0, }

1248

{ 0, }

1233

};

1249

};

1234

1250

1235

static struct pci_driver pm2fb_driver = {

1251

static struct pci_driver pm2fb_driver = {

1236

.name = "pm2fb",

1252

.name = "pm2fb",

1237

.id_table = pm2fb_id_table,

1253

.id_table = pm2fb_id_table,

1238

.probe = pm2fb_probe,

1254

.probe = pm2fb_probe,

1239

.remove = __devexit_p(pm2fb_remove),

1255

.remove = __devexit_p(pm2fb_remove),

1240

};

1256

};

1241

1257

1242

MODULE_DEVICE_TABLE(pci, pm2fb_id_table);

1258

MODULE_DEVICE_TABLE(pci, pm2fb_id_table);

1243

1259

1244

1260

1245

#ifndef MODULE

1261

#ifndef MODULE

1246

/**

1262

/**

1247

* Parse user speficied options.

1263

* Parse user speficied options.

1248

*

1264

*

1249

* This is, comma-separated options following `video=pm2fb:'.

1265

* This is, comma-separated options following `video=pm2fb:'.

1250

*/

1266

*/

1251

static int __init pm2fb_setup(char *options)

1267

static int __init pm2fb_setup(char *options)

1252

{

1268

{

1253

char* this_opt;

1269

char* this_opt;

1254

1270

1255

if (!options || !*options)

1271

if (!options || !*options)

1256

return 0;

1272

return 0;

1257

1273

1258

while ((this_opt = strsep(&options, ",")) != NULL) {

1274

while ((this_opt = strsep(&options, ",")) != NULL) {

1259

if (!*this_opt)

1275

if (!*this_opt)

1260

continue;

1276

continue;

1261

if(!strcmp(this_opt, "lowhsync")) {

1277

if(!strcmp(this_opt, "lowhsync")) {

1262

lowhsync = 1;

1278

lowhsync = 1;

1263

} else if(!strcmp(this_opt, "lowvsync")) {

1279

} else if(!strcmp(this_opt, "lowvsync")) {

1264

lowvsync = 1;

1280

lowvsync = 1;

1265

} else {

1281

} else {

1266

mode = this_opt;

1282

mode = this_opt;

1267

}

1283

}

1268

}

1284

}

1269

return 0;

1285

return 0;

1270

}

1286

}

1271

#endif

1287

#endif

1272

1288

1273

1289

1274

static int __init pm2fb_init(void)

1290

static int __init pm2fb_init(void)

1275

{

1291

{

1276

#ifndef MODULE

1292

#ifndef MODULE

1277

char *option = NULL;

1293

char *option = NULL;

1278

1294

1279

if (fb_get_options("pm2fb", &option))

1295

if (fb_get_options("pm2fb", &option))

1280

return -ENODEV;

1296

return -ENODEV;

1281

pm2fb_setup(option);

1297

pm2fb_setup(option);

1282

#endif

1298

#endif

1283

1299

1284

return pci_register_driver(&pm2fb_driver);

1300

return pci_register_driver(&pm2fb_driver);

1285

}

1301

}

1286

1302

1287

module_init(pm2fb_init);

1303

module_init(pm2fb_init);

1288

1304

1289

#ifdef MODULE

1305

#ifdef MODULE

1290

/*

1306

/*

1291

* Cleanup

1307

* Cleanup

1292

*/

1308

*/

1293

1309

1294

static void __exit pm2fb_exit(void)

1310

static void __exit pm2fb_exit(void)

1295

{

1311

{

1296

pci_unregister_driver(&pm2fb_driver);

1312

pci_unregister_driver(&pm2fb_driver);

1297

}

1313

}

1298

#endif

1314

#endif

1299

1315

1300

#ifdef MODULE

1316

#ifdef MODULE

1301

module_exit(pm2fb_exit);

1317

module_exit(pm2fb_exit);

1302

1318

1303

module_param(mode, charp, 0);

1319

module_param(mode, charp, 0);

1304

MODULE_PARM_DESC(mode, "Preferred video mode e.g. '648x480-8@60'");

1320

MODULE_PARM_DESC(mode, "Preferred video mode e.g. '648x480-8@60'");

1305

module_param(lowhsync, bool, 0);

1321

module_param(lowhsync, bool, 0);

1306

MODULE_PARM_DESC(lowhsync, "Force horizontal sync low regardless of mode");

1322

MODULE_PARM_DESC(lowhsync, "Force horizontal sync low regardless of mode");

1307

module_param(lowvsync, bool, 0);

1323

module_param(lowvsync, bool, 0);

1308

MODULE_PARM_DESC(lowvsync, "Force vertical sync low regardless of mode");

1324

MODULE_PARM_DESC(lowvsync, "Force vertical sync low regardless of mode");

1309

1325

1310

MODULE_AUTHOR("Jim Hague <jim.hague@acm.org>");

1326

MODULE_AUTHOR("Jim Hague <jim.hague@acm.org>");

1311

MODULE_DESCRIPTION("Permedia2 framebuffer device driver");

1327

MODULE_DESCRIPTION("Permedia2 framebuffer device driver");

1312

MODULE_LICENSE("GPL");

1328

MODULE_LICENSE("GPL");

1313

#endif

1329

#endif

1314

1330

GITLAB

[PATCH] pm2fb: Manual configuration of timings for Elsa Winner 2000 Office

 /*
  * Permedia2 framebuffer driver.
  *
  * 2.5/2.6 driver:
  * Copyright (c) 2003 Jim Hague (jim.hague@acm.org)
  *
  * based on 2.4 driver:
  * Copyright (c) 1998-2000 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
  * Copyright (c) 1999 Jakub Jelinek (jakub@redhat.com)
  *
  * and additional input from James Simmon's port of Hannu Mallat's tdfx
  * driver.
  *
  * I have a Creative Graphics Blaster Exxtreme card - pm2fb on x86.  I
  * have no access to other pm2fb implementations. Sparc (and thus
  * hopefully other big-endian) devices now work, thanks to a lot of
  * testing work by Ron Murray. I have no access to CVision hardware,
  * and therefore for now I am omitting the CVision code.
  *
  * Multiple boards support has been on the TODO list for ages.
  * Don't expect this to change.
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License. See the file COPYING in the main directory of this archive for
  * more details.
  *
  *
  */
 #include <linux/config.h>
 #include <linux/module.h>
 #include <linux/moduleparam.h>
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/string.h>
 #include <linux/mm.h>
 #include <linux/tty.h>
 #include <linux/slab.h>
 #include <linux/delay.h>
 #include <linux/fb.h>
 #include <linux/init.h>
 #include <linux/pci.h>
 #include <video/permedia2.h>
 #include <video/cvisionppc.h>
 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
 #error	"The endianness of the target host has not been defined."
 #endif
 #if !defined(CONFIG_PCI)
 #error "Only generic PCI cards supported."
 #endif
 #undef PM2FB_MASTER_DEBUG
 #ifdef PM2FB_MASTER_DEBUG
 #define DPRINTK(a,b...)	printk(KERN_DEBUG "pm2fb: %s: " a, __FUNCTION__ , ## b)
 #else
 #define DPRINTK(a,b...)
 #endif
 /*
  * Driver data
  */
 static char *mode __devinitdata = NULL;
 /*
  * The XFree GLINT driver will (I think to implement hardware cursor
  * support on TVP4010 and similar where there is no RAMDAC - see
  * comment in set_video) always request +ve sync regardless of what
  * the mode requires. This screws me because I have a Sun
  * fixed-frequency monitor which absolutely has to have -ve sync. So
  * these flags allow the user to specify that requests for +ve sync
  * should be silently turned in -ve sync.
  */
 static int lowhsync __devinitdata = 0;
 static int lowvsync __devinitdata = 0;
 /*
  * The hardware state of the graphics card that isn't part of the
  * screeninfo.
  */
 struct pm2fb_par
 {
 	pm2type_t	type;		/* Board type */
 	u32		fb_size;	/* framebuffer memory size */
 	unsigned char	__iomem *v_fb;  /* virtual address of frame buffer */
 	unsigned char	__iomem *v_regs;/* virtual address of p_regs */
 	u32 	   	memclock;	/* memclock */
 	u32		video;		/* video flags before blanking */
 	u32		mem_config;	/* MemConfig reg at probe */
 	u32		mem_control;	/* MemControl reg at probe */
 	u32		boot_address;	/* BootAddress reg at probe */
 };
 /*
  * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
  * if we don't use modedb.
  */
 static struct fb_fix_screeninfo pm2fb_fix __devinitdata = {
 	.id =		"",
 	.type =		FB_TYPE_PACKED_PIXELS,
 	.visual =	FB_VISUAL_PSEUDOCOLOR,
 	.xpanstep =	1,
 	.ypanstep =	1,
 	.ywrapstep =	0,
 	.accel =	FB_ACCEL_NONE,
 };
 /*
  * Default video mode. In case the modedb doesn't work.
  */
 static struct fb_var_screeninfo pm2fb_var __devinitdata = {
 	/* "640x480, 8 bpp @ 60 Hz */
 	.xres =		640,
 	.yres =		480,
 	.xres_virtual =	640,
 	.yres_virtual =	480,
 	.bits_per_pixel =8,
 	.red =		{0, 8, 0},
 	.blue =		{0, 8, 0},
 	.green =	{0, 8, 0},
 	.activate =	FB_ACTIVATE_NOW,
 	.height =	-1,
 	.width =	-1,
 	.accel_flags =	0,
 	.pixclock =	39721,
 	.left_margin =	40,
 	.right_margin =	24,
 	.upper_margin =	32,
 	.lower_margin =	11,
 	.hsync_len =	96,
 	.vsync_len =	2,
 	.vmode =	FB_VMODE_NONINTERLACED
 };
 /*
  * Utility functions
  */
 static inline u32 RD32(unsigned char __iomem *base, s32 off)
 {
 	return fb_readl(base + off);
 }
 static inline void WR32(unsigned char __iomem *base, s32 off, u32 v)
 {
 	fb_writel(v, base + off);
 }
 static inline u32 pm2_RD(struct pm2fb_par* p, s32 off)
 {
 	return RD32(p->v_regs, off);
 }
 static inline void pm2_WR(struct pm2fb_par* p, s32 off, u32 v)
 {
 	WR32(p->v_regs, off, v);
 }
 static inline u32 pm2_RDAC_RD(struct pm2fb_par* p, s32 idx)
 {
 	int index = PM2R_RD_INDEXED_DATA;
 	switch (p->type) {
 	case PM2_TYPE_PERMEDIA2:
 		pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
 		break;
 	case PM2_TYPE_PERMEDIA2V:
 		pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
 		index = PM2VR_RD_INDEXED_DATA;
 		break;
 	}
 	mb();
 	return pm2_RD(p, index);
 }
 static inline void pm2_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
 {
 	int index = PM2R_RD_INDEXED_DATA;
 	switch (p->type) {
 	case PM2_TYPE_PERMEDIA2:
 		pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
 		break;
 	case PM2_TYPE_PERMEDIA2V:
 		pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
 		index = PM2VR_RD_INDEXED_DATA;
 		break;
 	}
 	mb();
 	pm2_WR(p, index, v);
 }
 static inline void pm2v_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
 {
 	pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
 	mb();
 	pm2_WR(p, PM2VR_RD_INDEXED_DATA, v);
 }
 #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
 #define WAIT_FIFO(p,a)
 #else
 static inline void WAIT_FIFO(struct pm2fb_par* p, u32 a)
 {
 	while( pm2_RD(p, PM2R_IN_FIFO_SPACE) < a );
 	mb();
 }
 #endif
 /*
  * partial products for the supported horizontal resolutions.
  */
 #define PACKPP(p0,p1,p2)	(((p2) << 6) | ((p1) << 3) | (p0))
 static const struct {
 	u16 width;
 	u16 pp;
 } pp_table[] = {
 	{ 32,	PACKPP(1, 0, 0) }, { 64,	PACKPP(1, 1, 0) },
 	{ 96,	PACKPP(1, 1, 1) }, { 128,	PACKPP(2, 1, 1) },
 	{ 160,	PACKPP(2, 2, 1) }, { 192,	PACKPP(2, 2, 2) },
 	{ 224,	PACKPP(3, 2, 1) }, { 256,	PACKPP(3, 2, 2) },
 	{ 288,	PACKPP(3, 3, 1) }, { 320,	PACKPP(3, 3, 2) },
 	{ 384,	PACKPP(3, 3, 3) }, { 416,	PACKPP(4, 3, 1) },
 	{ 448,	PACKPP(4, 3, 2) }, { 512,	PACKPP(4, 3, 3) },
 	{ 544,	PACKPP(4, 4, 1) }, { 576,	PACKPP(4, 4, 2) },
 	{ 640,	PACKPP(4, 4, 3) }, { 768,	PACKPP(4, 4, 4) },
 	{ 800,	PACKPP(5, 4, 1) }, { 832,	PACKPP(5, 4, 2) },
 	{ 896,	PACKPP(5, 4, 3) }, { 1024,	PACKPP(5, 4, 4) },
 	{ 1056,	PACKPP(5, 5, 1) }, { 1088,	PACKPP(5, 5, 2) },
 	{ 1152,	PACKPP(5, 5, 3) }, { 1280,	PACKPP(5, 5, 4) },
 	{ 1536,	PACKPP(5, 5, 5) }, { 1568,	PACKPP(6, 5, 1) },
 	{ 1600,	PACKPP(6, 5, 2) }, { 1664,	PACKPP(6, 5, 3) },
 	{ 1792,	PACKPP(6, 5, 4) }, { 2048,	PACKPP(6, 5, 5) },
 	{ 0,	0 } };
 static u32 partprod(u32 xres)
 {
 	int i;
 	for (i = 0; pp_table[i].width && pp_table[i].width != xres; i++)
 		;
 	if ( pp_table[i].width == 0 )
 		DPRINTK("invalid width %u\n", xres);
 	return pp_table[i].pp;
 }
 static u32 to3264(u32 timing, int bpp, int is64)
 {
 	switch (bpp) {
 	case 8:
 		timing >>= 2 + is64;
 		break;
 	case 16:
 		timing >>= 1 + is64;
 		break;
 	case 24:
 		timing = (timing * 3) >> (2 + is64);
 		break;
 	case 32:
 		if (is64)
 			timing >>= 1;
 		break;
 	}
 	return timing;
 }
 static void pm2_mnp(u32 clk, unsigned char* mm, unsigned char* nn,
 		    unsigned char* pp)
 {
 	unsigned char m;
 	unsigned char n;
 	unsigned char p;
 	u32 f;
 	s32 curr;
 	s32 delta = 100000;
 	*mm = *nn = *pp = 0;
 	for (n = 2; n < 15; n++) {
 		for (m = 2; m; m++) {
 			f = PM2_REFERENCE_CLOCK * m / n;
 			if (f >= 150000 && f <= 300000) {
 				for ( p = 0; p < 5; p++, f >>= 1) {
 					curr = ( clk > f ) ? clk - f : f - clk;
 					if ( curr < delta ) {
 						delta=curr;
 						*mm=m;
 						*nn=n;
 						*pp=p;
 					}
 				}
 			}
 		}
 	}
 }
 static void pm2v_mnp(u32 clk, unsigned char* mm, unsigned char* nn,
 		     unsigned char* pp)
 {
 	unsigned char m;
 	unsigned char n;
 	unsigned char p;
 	u32 f;
 	s32 delta = 1000;
 	*mm = *nn = *pp = 0;
 	for (n = 1; n; n++) {
 		for ( m = 1; m; m++) {
 			for ( p = 0; p < 2; p++) {
 				f = PM2_REFERENCE_CLOCK * n / (m * (1 << (p + 1)));
 				if ( clk > f - delta && clk < f + delta ) {
 					delta = ( clk > f ) ? clk - f : f - clk;
 					*mm=m;
 					*nn=n;
 					*pp=p;
 				}
 			}
 		}
 	}
 }
 static void clear_palette(struct pm2fb_par* p) {
 	int i=256;
 	WAIT_FIFO(p, 1);
 	pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, 0);
 	wmb();
 	while (i--) {
 		WAIT_FIFO(p, 3);
 		pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
 		pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
 		pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
 	}
 }
 static void reset_card(struct pm2fb_par* p)
 {
 	if (p->type == PM2_TYPE_PERMEDIA2V)
 		pm2_WR(p, PM2VR_RD_INDEX_HIGH, 0);
 	pm2_WR(p, PM2R_RESET_STATUS, 0);
 	mb();
 	while (pm2_RD(p, PM2R_RESET_STATUS) & PM2F_BEING_RESET)
 		;
 	mb();
 #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
 	DPRINTK("FIFO disconnect enabled\n");
 	pm2_WR(p, PM2R_FIFO_DISCON, 1);
 	mb();
 #endif
 	/* Restore stashed memory config information from probe */
 	WAIT_FIFO(p, 3);
 	pm2_WR(p, PM2R_MEM_CONTROL, p->mem_control);
 	pm2_WR(p, PM2R_BOOT_ADDRESS, p->boot_address);
 	wmb();
 	pm2_WR(p, PM2R_MEM_CONFIG, p->mem_config);
 }
 static void reset_config(struct pm2fb_par* p)
 {
 	WAIT_FIFO(p, 52);
 	pm2_WR(p, PM2R_CHIP_CONFIG, pm2_RD(p, PM2R_CHIP_CONFIG)&
 	       ~(PM2F_VGA_ENABLE|PM2F_VGA_FIXED));
 	pm2_WR(p, PM2R_BYPASS_WRITE_MASK, ~(0L));
 	pm2_WR(p, PM2R_FRAMEBUFFER_WRITE_MASK, ~(0L));
 	pm2_WR(p, PM2R_FIFO_CONTROL, 0);
 	pm2_WR(p, PM2R_APERTURE_ONE, 0);
 	pm2_WR(p, PM2R_APERTURE_TWO, 0);
 	pm2_WR(p, PM2R_RASTERIZER_MODE, 0);
 	pm2_WR(p, PM2R_DELTA_MODE, PM2F_DELTA_ORDER_RGB);
 	pm2_WR(p, PM2R_LB_READ_FORMAT, 0);
 	pm2_WR(p, PM2R_LB_WRITE_FORMAT, 0);
 	pm2_WR(p, PM2R_LB_READ_MODE, 0);
 	pm2_WR(p, PM2R_LB_SOURCE_OFFSET, 0);
 	pm2_WR(p, PM2R_FB_SOURCE_OFFSET, 0);
 	pm2_WR(p, PM2R_FB_PIXEL_OFFSET, 0);
 	pm2_WR(p, PM2R_FB_WINDOW_BASE, 0);
 	pm2_WR(p, PM2R_LB_WINDOW_BASE, 0);
 	pm2_WR(p, PM2R_FB_SOFT_WRITE_MASK, ~(0L));
 	pm2_WR(p, PM2R_FB_HARD_WRITE_MASK, ~(0L));
 	pm2_WR(p, PM2R_FB_READ_PIXEL, 0);
 	pm2_WR(p, PM2R_DITHER_MODE, 0);
 	pm2_WR(p, PM2R_AREA_STIPPLE_MODE, 0);
 	pm2_WR(p, PM2R_DEPTH_MODE, 0);
 	pm2_WR(p, PM2R_STENCIL_MODE, 0);
 	pm2_WR(p, PM2R_TEXTURE_ADDRESS_MODE, 0);
 	pm2_WR(p, PM2R_TEXTURE_READ_MODE, 0);
 	pm2_WR(p, PM2R_TEXEL_LUT_MODE, 0);
 	pm2_WR(p, PM2R_YUV_MODE, 0);
 	pm2_WR(p, PM2R_COLOR_DDA_MODE, 0);
 	pm2_WR(p, PM2R_TEXTURE_COLOR_MODE, 0);
 	pm2_WR(p, PM2R_FOG_MODE, 0);
 	pm2_WR(p, PM2R_ALPHA_BLEND_MODE, 0);
 	pm2_WR(p, PM2R_LOGICAL_OP_MODE, 0);
 	pm2_WR(p, PM2R_STATISTICS_MODE, 0);
 	pm2_WR(p, PM2R_SCISSOR_MODE, 0);
 	pm2_WR(p, PM2R_FILTER_MODE, PM2F_SYNCHRONIZATION);
 	switch (p->type) {
 	case PM2_TYPE_PERMEDIA2:
 		pm2_RDAC_WR(p, PM2I_RD_MODE_CONTROL, 0); /* no overlay */
 		pm2_RDAC_WR(p, PM2I_RD_CURSOR_CONTROL, 0);
 		pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, PM2F_RD_PALETTE_WIDTH_8);
 		break;
 	case PM2_TYPE_PERMEDIA2V:
 		pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1); /* 8bit */
 		break;
 	}
 	pm2_RDAC_WR(p, PM2I_RD_COLOR_KEY_CONTROL, 0);
 	pm2_RDAC_WR(p, PM2I_RD_OVERLAY_KEY, 0);
 	pm2_RDAC_WR(p, PM2I_RD_RED_KEY, 0);
 	pm2_RDAC_WR(p, PM2I_RD_GREEN_KEY, 0);
 	pm2_RDAC_WR(p, PM2I_RD_BLUE_KEY, 0);
 }
 static void set_aperture(struct pm2fb_par* p, u32 depth)
 {
 	/*
 	 * The hardware is little-endian. When used in big-endian
 	 * hosts, the on-chip aperture settings are used where
 	 * possible to translate from host to card byte order.
 	 */
 	WAIT_FIFO(p, 4);
 #ifdef __LITTLE_ENDIAN
 	pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
 #else
 	switch (depth) {
 	case 24:	/* RGB->BGR */
 		/*
 		 * We can't use the aperture to translate host to
 		 * card byte order here, so we switch to BGR mode
 		 * in pm2fb_set_par().
 		 */
 	case 8:		/* B->B */
 		pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
 		break;
 	case 16:	/* HL->LH */
 		pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_HALFWORDSWAP);
 		break;
 	case 32:	/* RGBA->ABGR */
 		pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_BYTESWAP);
 		break;
 	}
 #endif
 	// We don't use aperture two, so this may be superflous
 	pm2_WR(p, PM2R_APERTURE_TWO, PM2F_APERTURE_STANDARD);
 }
 static void set_color(struct pm2fb_par* p, unsigned char regno,
 		      unsigned char r, unsigned char g, unsigned char b)
 {
 	WAIT_FIFO(p, 4);
 	pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, regno);
 	wmb();
 	pm2_WR(p, PM2R_RD_PALETTE_DATA, r);
 	wmb();
 	pm2_WR(p, PM2R_RD_PALETTE_DATA, g);
 	wmb();
 	pm2_WR(p, PM2R_RD_PALETTE_DATA, b);
 }
 static void set_memclock(struct pm2fb_par* par, u32 clk)
 {
 	int i;
 	unsigned char m, n, p;
 	pm2_mnp(clk, &m, &n, &p);
 	WAIT_FIFO(par, 10);
 	pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6);
 	wmb();
 	pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m);
 	pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n);
 	wmb();
 	pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p);
 	wmb();
 	pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS);
 	rmb();
 	for (i = 256;
 	     i && !(pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED);
 	     i--)
 		;
 }
 static void set_pixclock(struct pm2fb_par* par, u32 clk)
 {
 	int i;
 	unsigned char m, n, p;
 	switch (par->type) {
 	case PM2_TYPE_PERMEDIA2:
 		pm2_mnp(clk, &m, &n, &p);
 		WAIT_FIFO(par, 8);
 		pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 0);
 		wmb();
 		pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A1, m);
 		pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A2, n);
 		wmb();
 		pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 8|p);
 		wmb();
 		pm2_RDAC_RD(par, PM2I_RD_PIXEL_CLOCK_STATUS);
 		rmb();
 		for (i = 256;
 		     i && !(pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED);
 		     i--)
 			;
 		break;
 	case PM2_TYPE_PERMEDIA2V:
 		pm2v_mnp(clk/2, &m, &n, &p);
 		WAIT_FIFO(par, 8);
 		pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CLK0_PRESCALE >> 8);
 		pm2v_RDAC_WR(par, PM2VI_RD_CLK0_PRESCALE, m);
 		pm2v_RDAC_WR(par, PM2VI_RD_CLK0_FEEDBACK, n);
 		pm2v_RDAC_WR(par, PM2VI_RD_CLK0_POSTSCALE, p);
 		pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
 		break;
 	}
 }
 static void set_video(struct pm2fb_par* p, u32 video) {
 	u32 tmp;
 	u32 vsync;
 	vsync = video;
 	DPRINTK("video = 0x%x\n", video);
 	/*
 	 * The hardware cursor needs +vsync to recognise vert retrace.
 	 * We may not be using the hardware cursor, but the X Glint
 	 * driver may well. So always set +hsync/+vsync and then set
 	 * the RAMDAC to invert the sync if necessary.
 	 */
 	vsync &= ~(PM2F_HSYNC_MASK|PM2F_VSYNC_MASK);
 	vsync |= PM2F_HSYNC_ACT_HIGH|PM2F_VSYNC_ACT_HIGH;
 	WAIT_FIFO(p, 5);
 	pm2_WR(p, PM2R_VIDEO_CONTROL, vsync);
 	switch (p->type) {
 	case PM2_TYPE_PERMEDIA2:
 		tmp = PM2F_RD_PALETTE_WIDTH_8;
 		if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
 			tmp |= 4; /* invert hsync */
 		if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
 			tmp |= 8; /* invert vsync */
 		pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, tmp);
 		break;
 	case PM2_TYPE_PERMEDIA2V:
 		tmp = 0;
 		if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
 			tmp |= 1; /* invert hsync */
 		if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
 			tmp |= 4; /* invert vsync */
 		pm2v_RDAC_WR(p, PM2VI_RD_SYNC_CONTROL, tmp);
 		pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1);
 		break;
 	}
 }
 /*
  *
  */
 /**
  *      pm2fb_check_var - Optional function. Validates a var passed in.
  *      @var: frame buffer variable screen structure
  *      @info: frame buffer structure that represents a single frame buffer
  *
  *	Checks to see if the hardware supports the state requested by
  *	var passed in.
  *
  *	Returns negative errno on error, or zero on success.
  */
 static int pm2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 {
 	u32 lpitch;
 	if (var->bits_per_pixel != 8  && var->bits_per_pixel != 16 &&
 	    var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
 		DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
 		return -EINVAL;
 	}
 	if (var->xres != var->xres_virtual) {
 		DPRINTK("virtual x resolution != physical x resolution not supported\n");
 		return -EINVAL;
 	}
 	if (var->yres > var->yres_virtual) {
 		DPRINTK("virtual y resolution < physical y resolution not possible\n");
 		return -EINVAL;
 	}
 	if (var->xoffset) {
 		DPRINTK("xoffset not supported\n");
 		return -EINVAL;
 	}
 	if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
 		DPRINTK("interlace not supported\n");
 		return -EINVAL;
 	}
 	var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
 	lpitch = var->xres * ((var->bits_per_pixel + 7)>>3);
 	if (var->xres < 320 || var->xres > 1600) {
 		DPRINTK("width not supported: %u\n", var->xres);
 		return -EINVAL;
 	}
 	if (var->yres < 200 || var->yres > 1200) {
 		DPRINTK("height not supported: %u\n", var->yres);
 		return -EINVAL;
 	}
 	if (lpitch * var->yres_virtual > info->fix.smem_len) {
 		DPRINTK("no memory for screen (%ux%ux%u)\n",
 			var->xres, var->yres_virtual, var->bits_per_pixel);
 		return -EINVAL;
 	}
 	if (PICOS2KHZ(var->pixclock) > PM2_MAX_PIXCLOCK) {
 		DPRINTK("pixclock too high (%ldKHz)\n", PICOS2KHZ(var->pixclock));
 		return -EINVAL;
 	}
 	switch(var->bits_per_pixel) {
 	case 8:
 		var->red.length = var->green.length = var->blue.length = 8;
 		break;
 	case 16:
 		var->red.offset   = 11;
 		var->red.length   = 5;
 		var->green.offset = 5;
 		var->green.length = 6;
 		var->blue.offset  = 0;
 		var->blue.length  = 5;
 		break;
 	case 32:
 		var->transp.offset = 24;
 		var->transp.length = 8;
 		var->red.offset	  = 16;
 		var->green.offset = 8;
 		var->blue.offset  = 0;
 		var->red.length = var->green.length = var->blue.length = 8;
 		break;
 	case 24:
 #ifdef __BIG_ENDIAN
 		var->red.offset   = 0;
 		var->blue.offset  = 16;
 #else
 		var->red.offset   = 16;
 		var->blue.offset  = 0;
 #endif
 		var->green.offset = 8;
 		var->red.length = var->green.length = var->blue.length = 8;
 		break;
 	}
 	var->height = var->width = -1;
 	var->accel_flags = 0;	/* Can't mmap if this is on */
 	DPRINTK("Checking graphics mode at %dx%d depth %d\n",
 		var->xres, var->yres, var->bits_per_pixel);
 	return 0;
 }
 /**
  *      pm2fb_set_par - Alters the hardware state.
  *      @info: frame buffer structure that represents a single frame buffer
  *
  *	Using the fb_var_screeninfo in fb_info we set the resolution of the
  *	this particular framebuffer.
  */
 static int pm2fb_set_par(struct fb_info *info)
 {
 	struct pm2fb_par *par = (struct pm2fb_par *) info->par;
 	u32 pixclock;
 	u32 width, height, depth;
 	u32 hsstart, hsend, hbend, htotal;
 	u32 vsstart, vsend, vbend, vtotal;
 	u32 stride;
 	u32 base;
 	u32 video = 0;
 	u32 clrmode = PM2F_RD_COLOR_MODE_RGB | PM2F_RD_GUI_ACTIVE;
 	u32 txtmap = 0;
 	u32 pixsize = 0;
 	u32 clrformat = 0;
 	u32 xres;
 	int data64;
 	reset_card(par);
 	reset_config(par);
 	clear_palette(par);
 	if ( par->memclock )
 		set_memclock(par, par->memclock);
 	width = (info->var.xres_virtual + 7) & ~7;
 	height = info->var.yres_virtual;
 	depth = (info->var.bits_per_pixel + 7) & ~7;
 	depth = (depth > 32) ? 32 : depth;
 	data64 = depth > 8 || par->type == PM2_TYPE_PERMEDIA2V;
 	xres = (info->var.xres + 31) & ~31;
 	pixclock = PICOS2KHZ(info->var.pixclock);
 	if (pixclock > PM2_MAX_PIXCLOCK) {
 		DPRINTK("pixclock too high (%uKHz)\n", pixclock);
 		return -EINVAL;
 	}
 	hsstart = to3264(info->var.right_margin, depth, data64);
 	hsend = hsstart + to3264(info->var.hsync_len, depth, data64);
 	hbend = hsend + to3264(info->var.left_margin, depth, data64);
 	htotal = to3264(xres, depth, data64) + hbend - 1;
 	vsstart = (info->var.lower_margin)
 		? info->var.lower_margin - 1
 		: 0;	/* FIXME! */
 	vsend = info->var.lower_margin + info->var.vsync_len - 1;
 	vbend = info->var.lower_margin + info->var.vsync_len + info->var.upper_margin;
 	vtotal = info->var.yres + vbend - 1;
 	stride = to3264(width, depth, 1);
 	base = to3264(info->var.yoffset * xres + info->var.xoffset, depth, 1);
 	if (data64)
 		video |= PM2F_DATA_64_ENABLE;
 	if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) {
 		if (lowhsync) {
 			DPRINTK("ignoring +hsync, using -hsync.\n");
 			video |= PM2F_HSYNC_ACT_LOW;
 		} else
 			video |= PM2F_HSYNC_ACT_HIGH;
 	}
 	else
 		video |= PM2F_HSYNC_ACT_LOW;
 	if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) {
 		if (lowvsync) {
 			DPRINTK("ignoring +vsync, using -vsync.\n");
 			video |= PM2F_VSYNC_ACT_LOW;
 		} else
 			video |= PM2F_VSYNC_ACT_HIGH;
 	}
 	else
 		video |= PM2F_VSYNC_ACT_LOW;
 	if ((info->var.vmode & FB_VMODE_MASK)==FB_VMODE_INTERLACED) {
 		DPRINTK("interlaced not supported\n");
 		return -EINVAL;
 	}
 	if ((info->var.vmode & FB_VMODE_MASK)==FB_VMODE_DOUBLE)
 		video |= PM2F_LINE_DOUBLE;
 	if ((info->var.activate & FB_ACTIVATE_MASK)==FB_ACTIVATE_NOW)
 		video |= PM2F_VIDEO_ENABLE;
 	par->video = video;
 	info->fix.visual =
 		(depth == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
 	info->fix.line_length = info->var.xres * depth / 8;
 	info->cmap.len = 256;
 	/*
 	 * Settings calculated. Now write them out.
 	 */
 	if (par->type == PM2_TYPE_PERMEDIA2V) {
 		WAIT_FIFO(par, 1);
 		pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
 	}
 	set_aperture(par, depth);
 	mb();
 	WAIT_FIFO(par, 19);
 	pm2_RDAC_WR(par, PM2I_RD_COLOR_KEY_CONTROL,
 		    ( depth == 8 ) ? 0 : PM2F_COLOR_KEY_TEST_OFF);
 	switch (depth) {
 	case 8:
 		pm2_WR(par, PM2R_FB_READ_PIXEL, 0);
 		clrformat = 0x0e;
 		break;
 	case 16:
 		pm2_WR(par, PM2R_FB_READ_PIXEL, 1);
 		clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB565;
 		txtmap = PM2F_TEXTEL_SIZE_16;
 		pixsize = 1;
 		clrformat = 0x70;
 		break;
 	case 32:
 		pm2_WR(par, PM2R_FB_READ_PIXEL, 2);
 		clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGBA8888;
 		txtmap = PM2F_TEXTEL_SIZE_32;
 		pixsize = 2;
 		clrformat = 0x20;
 		break;
 	case 24:
 		pm2_WR(par, PM2R_FB_READ_PIXEL, 4);
 		clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB888;
 		txtmap = PM2F_TEXTEL_SIZE_24;
 		pixsize = 4;
 		clrformat = 0x20;
 		break;
 	}
 	pm2_WR(par, PM2R_FB_WRITE_MODE, PM2F_FB_WRITE_ENABLE);
 	pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres));
 	pm2_WR(par, PM2R_LB_READ_MODE, partprod(xres));
 	pm2_WR(par, PM2R_TEXTURE_MAP_FORMAT, txtmap | partprod(xres));
 	pm2_WR(par, PM2R_H_TOTAL, htotal);
 	pm2_WR(par, PM2R_HS_START, hsstart);
 	pm2_WR(par, PM2R_HS_END, hsend);
 	pm2_WR(par, PM2R_HG_END, hbend);
 	pm2_WR(par, PM2R_HB_END, hbend);
 	pm2_WR(par, PM2R_V_TOTAL, vtotal);
 	pm2_WR(par, PM2R_VS_START, vsstart);
 	pm2_WR(par, PM2R_VS_END, vsend);
 	pm2_WR(par, PM2R_VB_END, vbend);
 	pm2_WR(par, PM2R_SCREEN_STRIDE, stride);
 	wmb();
 	pm2_WR(par, PM2R_WINDOW_ORIGIN, 0);
 	pm2_WR(par, PM2R_SCREEN_SIZE, (height << 16) | width);
 	pm2_WR(par, PM2R_SCISSOR_MODE, PM2F_SCREEN_SCISSOR_ENABLE);
 	wmb();
 	pm2_WR(par, PM2R_SCREEN_BASE, base);
 	wmb();
 	set_video(par, video);
 	WAIT_FIFO(par, 4);
 	switch (par->type) {
 	case PM2_TYPE_PERMEDIA2:
 		pm2_RDAC_WR(par, PM2I_RD_COLOR_MODE, clrmode);
 		break;
 	case PM2_TYPE_PERMEDIA2V:
 		pm2v_RDAC_WR(par, PM2VI_RD_PIXEL_SIZE, pixsize);
 		pm2v_RDAC_WR(par, PM2VI_RD_COLOR_FORMAT, clrformat);
 		break;
 	}
 	set_pixclock(par, pixclock);
 	DPRINTK("Setting graphics mode at %dx%d depth %d\n",
 		info->var.xres, info->var.yres, info->var.bits_per_pixel);
 	return 0;
 }
 /**
  *  	pm2fb_setcolreg - Sets a color register.
  *      @regno: boolean, 0 copy local, 1 get_user() function
  *      @red: frame buffer colormap structure
  *	@green: The green value which can be up to 16 bits wide
  *	@blue:  The blue value which can be up to 16 bits wide.
  *	@transp: If supported the alpha value which can be up to 16 bits wide.
  *      @info: frame buffer info structure
  *
  *  	Set a single color register. The values supplied have a 16 bit
  *  	magnitude which needs to be scaled in this function for the hardware.
  *	Pretty much a direct lift from tdfxfb.c.
  *
  *	Returns negative errno on error, or zero on success.
  */
 static int pm2fb_setcolreg(unsigned regno, unsigned red, unsigned green,
 			   unsigned blue, unsigned transp,
 			   struct fb_info *info)
 {
 	struct pm2fb_par *par = (struct pm2fb_par *) info->par;
 	if (regno >= info->cmap.len)  /* no. of hw registers */
 		return 1;
 	/*
 	 * Program hardware... do anything you want with transp
 	 */
 	/* grayscale works only partially under directcolor */
 	if (info->var.grayscale) {
 		/* grayscale = 0.30*R + 0.59*G + 0.11*B */
 		red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
 	}
 	/* Directcolor:
 	 *   var->{color}.offset contains start of bitfield
 	 *   var->{color}.length contains length of bitfield
 	 *   {hardwarespecific} contains width of DAC
 	 *   cmap[X] is programmed to
 	 *   (X << red.offset) | (X << green.offset) | (X << blue.offset)
 	 *   RAMDAC[X] is programmed to (red, green, blue)
 	 *
 	 * Pseudocolor:
 	 *    uses offset = 0 && length = DAC register width.
 	 *    var->{color}.offset is 0
 	 *    var->{color}.length contains widht of DAC
 	 *    cmap is not used
 	 *    DAC[X] is programmed to (red, green, blue)
 	 * Truecolor:
 	 *    does not use RAMDAC (usually has 3 of them).
 	 *    var->{color}.offset contains start of bitfield
 	 *    var->{color}.length contains length of bitfield
 	 *    cmap is programmed to
 	 *    (red << red.offset) | (green << green.offset) |
 	 *    (blue << blue.offset) | (transp << transp.offset)
 	 *    RAMDAC does not exist
 	 */
 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
 	switch (info->fix.visual) {
 	case FB_VISUAL_TRUECOLOR:
 	case FB_VISUAL_PSEUDOCOLOR:
 		red = CNVT_TOHW(red, info->var.red.length);
 		green = CNVT_TOHW(green, info->var.green.length);
 		blue = CNVT_TOHW(blue, info->var.blue.length);
 		transp = CNVT_TOHW(transp, info->var.transp.length);
 		break;
 	case FB_VISUAL_DIRECTCOLOR:
 		/* example here assumes 8 bit DAC. Might be different
 		 * for your hardware */
 		red = CNVT_TOHW(red, 8);
 		green = CNVT_TOHW(green, 8);
 		blue = CNVT_TOHW(blue, 8);
 		/* hey, there is bug in transp handling... */
 		transp = CNVT_TOHW(transp, 8);
 		break;
 	}
 #undef CNVT_TOHW
 	/* Truecolor has hardware independent palette */
 	if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
 		u32 v;
 		if (regno >= 16)
 			return 1;
 		v = (red << info->var.red.offset) |
 			(green << info->var.green.offset) |
 			(blue << info->var.blue.offset) |
 			(transp << info->var.transp.offset);
 		switch (info->var.bits_per_pixel) {
 		case 8:
 			break;
    		case 16:
 		case 24:
 		case 32:
            		((u32*)(info->pseudo_palette))[regno] = v;
 			break;
 		}
 		return 0;
 	}
 	else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
 		set_color(par, regno, red, green, blue);
 	return 0;
 }
 /**
  *      pm2fb_pan_display - Pans the display.
  *      @var: frame buffer variable screen structure
  *      @info: frame buffer structure that represents a single frame buffer
  *
  *	Pan (or wrap, depending on the `vmode' field) the display using the
  *  	`xoffset' and `yoffset' fields of the `var' structure.
  *  	If the values don't fit, return -EINVAL.
  *
  *      Returns negative errno on error, or zero on success.
  *
  */
 static int pm2fb_pan_display(struct fb_var_screeninfo *var,
 			     struct fb_info *info)
 {
 	struct pm2fb_par *p = (struct pm2fb_par *) info->par;
 	u32 base;
 	u32 depth;
 	u32 xres;
 	xres = (var->xres + 31) & ~31;
 	depth = (var->bits_per_pixel + 7) & ~7;
 	depth = (depth > 32) ? 32 : depth;
 	base = to3264(var->yoffset * xres + var->xoffset, depth, 1);
 	WAIT_FIFO(p, 1);
 	pm2_WR(p, PM2R_SCREEN_BASE, base);
 	return 0;
 }
 /**
  *      pm2fb_blank - Blanks the display.
  *      @blank_mode: the blank mode we want.
  *      @info: frame buffer structure that represents a single frame buffer
  *
  *      Blank the screen if blank_mode != 0, else unblank. Return 0 if
  *      blanking succeeded, != 0 if un-/blanking failed due to e.g. a
  *      video mode which doesn't support it. Implements VESA suspend
  *      and powerdown modes on hardware that supports disabling hsync/vsync:
  *      blank_mode == 2: suspend vsync
  *      blank_mode == 3: suspend hsync
  *      blank_mode == 4: powerdown
  *
  *      Returns negative errno on error, or zero on success.
  *
  */
 static int pm2fb_blank(int blank_mode, struct fb_info *info)
 {
 	struct pm2fb_par *par = (struct pm2fb_par *) info->par;
 	u32 video = par->video;
 	DPRINTK("blank_mode %d\n", blank_mode);
 	switch (blank_mode) {
 	case FB_BLANK_UNBLANK:
 		/* Screen: On */
 		video |= PM2F_VIDEO_ENABLE;
 		break;
 	case FB_BLANK_NORMAL:
 		/* Screen: Off */
 		video &= ~PM2F_VIDEO_ENABLE;
 		break;
 	case FB_BLANK_VSYNC_SUSPEND:
 		/* VSync: Off */
 		video &= ~(PM2F_VSYNC_MASK | PM2F_BLANK_LOW );
 		break;
 	case FB_BLANK_HSYNC_SUSPEND:
 		/* HSync: Off */
 		video &= ~(PM2F_HSYNC_MASK | PM2F_BLANK_LOW );
 		break;
 	case FB_BLANK_POWERDOWN:
 		/* HSync: Off, VSync: Off */
 		video &= ~(PM2F_VSYNC_MASK | PM2F_HSYNC_MASK| PM2F_BLANK_LOW);
 		break;
 	}
 	set_video(par, video);
 	return 0;
 }
 /* ------------ Hardware Independent Functions ------------ */
 /*
  *  Frame buffer operations
  */
 static struct fb_ops pm2fb_ops = {
 	.owner		= THIS_MODULE,
 	.fb_check_var	= pm2fb_check_var,
 	.fb_set_par	= pm2fb_set_par,
 	.fb_setcolreg	= pm2fb_setcolreg,
 	.fb_blank	= pm2fb_blank,
 	.fb_pan_display	= pm2fb_pan_display,
 	.fb_fillrect	= cfb_fillrect,
 	.fb_copyarea	= cfb_copyarea,
 	.fb_imageblit	= cfb_imageblit,
 };
 /*
  * PCI stuff
  */
 /**
  * Device initialisation
  *
  * Initialise and allocate resource for PCI device.
  *
  * @param	pdev	PCI device.
  * @param	id	PCI device ID.
  */
 static int __devinit pm2fb_probe(struct pci_dev *pdev,
 				 const struct pci_device_id *id)
 {
 	struct pm2fb_par *default_par;
 	struct fb_info *info;
 	int size, err;
 	int err_retval = -ENXIO;
 	err = pci_enable_device(pdev);
 	if ( err ) {
 		printk(KERN_WARNING "pm2fb: Can't enable pdev: %d\n", err);
 		return err;
 	}
 	size = sizeof(struct pm2fb_par) + 256 * sizeof(u32);
 	info = framebuffer_alloc(size, &pdev->dev);
 	if ( !info )
 		return -ENOMEM;
 	default_par = (struct pm2fb_par *) info->par;
 	switch (pdev->device) {
 	case  PCI_DEVICE_ID_TI_TVP4020:
 		strcpy(pm2fb_fix.id, "TVP4020");
 		default_par->type = PM2_TYPE_PERMEDIA2;
 		break;
 	case  PCI_DEVICE_ID_3DLABS_PERMEDIA2:
 		strcpy(pm2fb_fix.id, "Permedia2");
 		default_par->type = PM2_TYPE_PERMEDIA2;
 		break;
 	case  PCI_DEVICE_ID_3DLABS_PERMEDIA2V:
 		strcpy(pm2fb_fix.id, "Permedia2v");
 		default_par->type = PM2_TYPE_PERMEDIA2V;
 		break;
 	}
 	pm2fb_fix.mmio_start = pci_resource_start(pdev, 0);
 	pm2fb_fix.mmio_len = PM2_REGS_SIZE;
 #if defined(__BIG_ENDIAN)
 	/*
 	 * PM2 has a 64k register file, mapped twice in 128k. Lower
 	 * map is little-endian, upper map is big-endian.
 	 */
 	pm2fb_fix.mmio_start += PM2_REGS_SIZE;
 	DPRINTK("Adjusting register base for big-endian.\n");
 #endif
 	DPRINTK("Register base at 0x%lx\n", pm2fb_fix.mmio_start);
 	/* Registers - request region and map it. */
 	if ( !request_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len,
 				 "pm2fb regbase") ) {
 		printk(KERN_WARNING "pm2fb: Can't reserve regbase.\n");
 		goto err_exit_neither;
 	}
 	default_par->v_regs =
 		ioremap_nocache(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
 	if ( !default_par->v_regs ) {
 		printk(KERN_WARNING "pm2fb: Can't remap %s register area.\n",
 		       pm2fb_fix.id);
 		release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
 		goto err_exit_neither;
 	}
 	/* Stash away memory register info for use when we reset the board */
 	default_par->mem_control = pm2_RD(default_par, PM2R_MEM_CONTROL);
 	default_par->boot_address = pm2_RD(default_par, PM2R_BOOT_ADDRESS);
 	default_par->mem_config = pm2_RD(default_par, PM2R_MEM_CONFIG);
 	DPRINTK("MemControl 0x%x BootAddress 0x%x MemConfig 0x%x\n",
 		default_par->mem_control, default_par->boot_address,
 		default_par->mem_config);
+	if(default_par->mem_control == 0 &&
+		default_par->boot_address == 0x31 &&
+		default_par->mem_config == 0x259fffff &&
+		pdev->subsystem_vendor == 0x1048 &&
+		pdev->subsystem_device == 0x0a31) {
+		DPRINTK("subsystem_vendor: %04x, subsystem_device: %04x\n",
+			pdev->subsystem_vendor, pdev->subsystem_device);
+		DPRINTK("We have not been initialized by VGA BIOS "
+			"and are running on an Elsa Winner 2000 Office\n");
+		DPRINTK("Initializing card timings manually...\n");
+		default_par->mem_control=0;
+		default_par->boot_address=0x20;
+		default_par->mem_config=0xe6002021;
+		default_par->memclock=100000;
+	}
 	/* Now work out how big lfb is going to be. */
 	switch(default_par->mem_config & PM2F_MEM_CONFIG_RAM_MASK) {
 	case PM2F_MEM_BANKS_1:
 		default_par->fb_size=0x200000;
 		break;
 	case PM2F_MEM_BANKS_2:
 		default_par->fb_size=0x400000;
 		break;
 	case PM2F_MEM_BANKS_3:
 		default_par->fb_size=0x600000;
 		break;
 	case PM2F_MEM_BANKS_4:
 		default_par->fb_size=0x800000;
 		break;
 	}
 	default_par->memclock = CVPPC_MEMCLOCK;
 	pm2fb_fix.smem_start = pci_resource_start(pdev, 1);
 	pm2fb_fix.smem_len = default_par->fb_size;
 	/* Linear frame buffer - request region and map it. */
 	if ( !request_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len,
 				 "pm2fb smem") ) {
 		printk(KERN_WARNING "pm2fb: Can't reserve smem.\n");
 		goto err_exit_mmio;
 	}
 	info->screen_base = default_par->v_fb =
 		ioremap_nocache(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
 	if ( !default_par->v_fb ) {
 		printk(KERN_WARNING "pm2fb: Can't ioremap smem area.\n");
 		release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
 		goto err_exit_mmio;
 	}
 	info->fbops		= &pm2fb_ops;
 	info->fix		= pm2fb_fix;
 	info->pseudo_palette	= (void *)(default_par + 1);
 	info->flags		= FBINFO_DEFAULT |
                                   FBINFO_HWACCEL_YPAN;
 	if (!mode)
 		mode = "640x480@60";
 	err = fb_find_mode(&info->var, info, mode, NULL, 0, NULL, 8);
 	if (!err || err == 4)
 		info->var = pm2fb_var;
 	if (fb_alloc_cmap(&info->cmap, 256, 0) < 0)
 		goto err_exit_all;
 	if (register_framebuffer(info) < 0)
 		goto err_exit_both;
 	printk(KERN_INFO "fb%d: %s frame buffer device, memory = %dK.\n",
 	       info->node, info->fix.id, default_par->fb_size / 1024);
 	/*
 	 * Our driver data
 	 */
 	pci_set_drvdata(pdev, info);
 	return 0;
  err_exit_all:
 	fb_dealloc_cmap(&info->cmap);
  err_exit_both:
 	iounmap(info->screen_base);
 	release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
  err_exit_mmio:
 	iounmap(default_par->v_regs);
 	release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
  err_exit_neither:
 	framebuffer_release(info);
 	return err_retval;
 }
 /**
  * Device removal.
  *
  * Release all device resources.
  *
  * @param	pdev	PCI device to clean up.
  */
 static void __devexit pm2fb_remove(struct pci_dev *pdev)
 {
 	struct fb_info* info = pci_get_drvdata(pdev);
 	struct fb_fix_screeninfo* fix = &info->fix;
 	struct pm2fb_par *par = info->par;
 	unregister_framebuffer(info);
 	iounmap(info->screen_base);
 	release_mem_region(fix->smem_start, fix->smem_len);
 	iounmap(par->v_regs);
 	release_mem_region(fix->mmio_start, fix->mmio_len);
 	pci_set_drvdata(pdev, NULL);
 	kfree(info);
 }
 static struct pci_device_id pm2fb_id_table[] = {
 	{ PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TVP4020,
 	  PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
 	  0xff0000, 0 },
 	{ PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2,
 	  PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
 	  0xff0000, 0 },
 	{ PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
 	  PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
 	  0xff0000, 0 },
 	{ 0, }
 };
 static struct pci_driver pm2fb_driver = {
 	.name		= "pm2fb",
 	.id_table 	= pm2fb_id_table,
 	.probe 		= pm2fb_probe,
 	.remove 	= __devexit_p(pm2fb_remove),
 };
 MODULE_DEVICE_TABLE(pci, pm2fb_id_table);
 #ifndef MODULE
 /**
  * Parse user speficied options.
  *
  * This is, comma-separated options following `video=pm2fb:'.
  */
 static int __init pm2fb_setup(char *options)
 {
 	char* this_opt;
 	if (!options || !*options)
 		return 0;
 	while ((this_opt = strsep(&options, ",")) != NULL) {
 		if (!*this_opt)
 			continue;
 		if(!strcmp(this_opt, "lowhsync")) {
 			lowhsync = 1;
 		} else if(!strcmp(this_opt, "lowvsync")) {
 			lowvsync = 1;
 		} else {
 			mode = this_opt;
 		}
 	}
 	return 0;
 }
 #endif
 static int __init pm2fb_init(void)
 {
 #ifndef MODULE
 	char *option = NULL;
 	if (fb_get_options("pm2fb", &option))
 		return -ENODEV;
 	pm2fb_setup(option);
 #endif
 	return pci_register_driver(&pm2fb_driver);
 }
 module_init(pm2fb_init);
 #ifdef MODULE
 /*
  *  Cleanup
  */
 static void __exit pm2fb_exit(void)
 {
 	pci_unregister_driver(&pm2fb_driver);
 }
 #endif
 #ifdef MODULE
 module_exit(pm2fb_exit);
 module_param(mode, charp, 0);
 MODULE_PARM_DESC(mode, "Preferred video mode e.g. '648x480-8@60'");
 module_param(lowhsync, bool, 0);
 MODULE_PARM_DESC(lowhsync, "Force horizontal sync low regardless of mode");
 module_param(lowvsync, bool, 0);
 MODULE_PARM_DESC(lowvsync, "Force vertical sync low regardless of mode");
 MODULE_AUTHOR("Jim Hague <jim.hague@acm.org>");
 MODULE_DESCRIPTION("Permedia2 framebuffer device driver");
 MODULE_LICENSE("GPL");
 #endif