Doug / smarc-fsl-linux-kernel

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Commit 95360fd63606918167a5365b770a6d28d333f0ed

Authored by Linus Torvalds
2 parents 8f446a7a06 e6ca4ae895
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

Merge tag 'boards' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM soc board specific updates from Olof Johansson:
 "Misc board updates:
   - Greg added a handful of boards to KS8695 (since he has stepped up
     to maintain it).
   - Qualcomm has added DT-only board support for a couple of their
     newer SoCs.
   - misc other updates for Samsung and Freescale boards."

Fix up trivial conflict in arch/arm/mach-shmobile/board-armadillo800eva.c
due to gpio device data being added next to hdmi device data that got moved.

* tag 'boards' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: msm: Allow 8960 and 8660 to compile together
  ARM: msm: Allow msm_iomap-8x60 and msm_iomap-8960 to coexist
  ARM: EXYNOS: Add generic PWM lookup support for SMDKV310
  ARM: EXYNOS: Add generic PWM lookup support for SMDK4X12
  ARM: EXYNOS: Use generic pwm driver in Origen board
  ARM: shmobile: armadillo800eva: Add support RTC
  ARM: ks8695: add board support for the OpenGear boards based on the KS8695
  ARM: ks8695: add board support for the SnapGear boards based on the KS8695
  ARM: dts: Add heartbeat gpio-leds support to Origen
  ARM: dts: Use active low flag for gpio-keys on Origen
  ARM: shmobile: marzen: enable thermal sensor
  ARM: shmobile: marzen: fixup regulator id for smsc911x
  ARM: shmobile: marzen: add SDHI0 support
  ARM: mmp: enable debug uart port in defconfig
  ARM: mmp: implement DEBUG_LL port choice
  ARM: S3C64XX: Register audio platform devices for Bells on Cragganmore
  ARM: S3C64XX: Update configuration for WM5102 module on Cragganmore
  ARM: mx27pdk: Add audio support
  ARM: ttc_dkb: add nand support

Showing 26 changed files Inline Diff

arch/arm/Kconfig.debug
Diff comments   View file @ 95360fd
1 menu "Kernel hacking" 1 menu "Kernel hacking"
2 2
3 source "lib/Kconfig.debug" 3 source "lib/Kconfig.debug"
4 4
5 config STRICT_DEVMEM 5 config STRICT_DEVMEM
6 bool "Filter access to /dev/mem" 6 bool "Filter access to /dev/mem"
7 depends on MMU 7 depends on MMU
8 ---help--- 8 ---help---
9 If this option is disabled, you allow userspace (root) access to all 9 If this option is disabled, you allow userspace (root) access to all
10 of memory, including kernel and userspace memory. Accidental 10 of memory, including kernel and userspace memory. Accidental
11 access to this is obviously disastrous, but specific access can 11 access to this is obviously disastrous, but specific access can
12 be used by people debugging the kernel. 12 be used by people debugging the kernel.
13 13
14 If this option is switched on, the /dev/mem file only allows 14 If this option is switched on, the /dev/mem file only allows
15 userspace access to memory mapped peripherals. 15 userspace access to memory mapped peripherals.
16 16
17 If in doubt, say Y. 17 If in doubt, say Y.
18 18
19 # RMK wants arm kernels compiled with frame pointers or stack unwinding. 19 # RMK wants arm kernels compiled with frame pointers or stack unwinding.
20 # If you know what you are doing and are willing to live without stack 20 # If you know what you are doing and are willing to live without stack
21 # traces, you can get a slightly smaller kernel by setting this option to 21 # traces, you can get a slightly smaller kernel by setting this option to
22 # n, but then RMK will have to kill you ;). 22 # n, but then RMK will have to kill you ;).
23 config FRAME_POINTER 23 config FRAME_POINTER
24 bool 24 bool
25 depends on !THUMB2_KERNEL 25 depends on !THUMB2_KERNEL
26 default y if !ARM_UNWIND || FUNCTION_GRAPH_TRACER 26 default y if !ARM_UNWIND || FUNCTION_GRAPH_TRACER
27 help 27 help
28 If you say N here, the resulting kernel will be slightly smaller and 28 If you say N here, the resulting kernel will be slightly smaller and
29 faster. However, if neither FRAME_POINTER nor ARM_UNWIND are enabled, 29 faster. However, if neither FRAME_POINTER nor ARM_UNWIND are enabled,
30 when a problem occurs with the kernel, the information that is 30 when a problem occurs with the kernel, the information that is
31 reported is severely limited. 31 reported is severely limited.
32 32
33 config ARM_UNWIND 33 config ARM_UNWIND
34 bool "Enable stack unwinding support (EXPERIMENTAL)" 34 bool "Enable stack unwinding support (EXPERIMENTAL)"
35 depends on AEABI && EXPERIMENTAL 35 depends on AEABI && EXPERIMENTAL
36 default y 36 default y
37 help 37 help
38 This option enables stack unwinding support in the kernel 38 This option enables stack unwinding support in the kernel
39 using the information automatically generated by the 39 using the information automatically generated by the
40 compiler. The resulting kernel image is slightly bigger but 40 compiler. The resulting kernel image is slightly bigger but
41 the performance is not affected. Currently, this feature 41 the performance is not affected. Currently, this feature
42 only works with EABI compilers. If unsure say Y. 42 only works with EABI compilers. If unsure say Y.
43 43
44 config OLD_MCOUNT 44 config OLD_MCOUNT
45 bool 45 bool
46 depends on FUNCTION_TRACER && FRAME_POINTER 46 depends on FUNCTION_TRACER && FRAME_POINTER
47 default y 47 default y
48 48
49 config DEBUG_USER 49 config DEBUG_USER
50 bool "Verbose user fault messages" 50 bool "Verbose user fault messages"
51 help 51 help
52 When a user program crashes due to an exception, the kernel can 52 When a user program crashes due to an exception, the kernel can
53 print a brief message explaining what the problem was. This is 53 print a brief message explaining what the problem was. This is
54 sometimes helpful for debugging but serves no purpose on a 54 sometimes helpful for debugging but serves no purpose on a
55 production system. Most people should say N here. 55 production system. Most people should say N here.
56 56
57 In addition, you need to pass user_debug=N on the kernel command 57 In addition, you need to pass user_debug=N on the kernel command
58 line to enable this feature. N consists of the sum of: 58 line to enable this feature. N consists of the sum of:
59 59
60 1 - undefined instruction events 60 1 - undefined instruction events
61 2 - system calls 61 2 - system calls
62 4 - invalid data aborts 62 4 - invalid data aborts
63 8 - SIGSEGV faults 63 8 - SIGSEGV faults
64 16 - SIGBUS faults 64 16 - SIGBUS faults
65 65
66 # These options are only for real kernel hackers who want to get their hands dirty. 66 # These options are only for real kernel hackers who want to get their hands dirty.
67 config DEBUG_LL 67 config DEBUG_LL
68 bool "Kernel low-level debugging functions (read help!)" 68 bool "Kernel low-level debugging functions (read help!)"
69 depends on DEBUG_KERNEL 69 depends on DEBUG_KERNEL
70 help 70 help
71 Say Y here to include definitions of printascii, printch, printhex 71 Say Y here to include definitions of printascii, printch, printhex
72 in the kernel. This is helpful if you are debugging code that 72 in the kernel. This is helpful if you are debugging code that
73 executes before the console is initialized. 73 executes before the console is initialized.
74 74
75 Note that selecting this option will limit the kernel to a single 75 Note that selecting this option will limit the kernel to a single
76 UART definition, as specified below. Attempting to boot the kernel 76 UART definition, as specified below. Attempting to boot the kernel
77 image on a different platform *will not work*, so this option should 77 image on a different platform *will not work*, so this option should
78 not be enabled for kernels that are intended to be portable. 78 not be enabled for kernels that are intended to be portable.
79 79
80 choice 80 choice
81 prompt "Kernel low-level debugging port" 81 prompt "Kernel low-level debugging port"
82 depends on DEBUG_LL 82 depends on DEBUG_LL
83 83
84 config AT91_DEBUG_LL_DBGU0 84 config AT91_DEBUG_LL_DBGU0
85 bool "Kernel low-level debugging on rm9200, 9260/9g20, 9261/9g10 and 9rl" 85 bool "Kernel low-level debugging on rm9200, 9260/9g20, 9261/9g10 and 9rl"
86 depends on HAVE_AT91_DBGU0 86 depends on HAVE_AT91_DBGU0
87 87
88 config AT91_DEBUG_LL_DBGU1 88 config AT91_DEBUG_LL_DBGU1
89 bool "Kernel low-level debugging on 9263 and 9g45" 89 bool "Kernel low-level debugging on 9263 and 9g45"
90 depends on HAVE_AT91_DBGU1 90 depends on HAVE_AT91_DBGU1
91 91
92 config DEBUG_CLPS711X_UART1 92 config DEBUG_CLPS711X_UART1
93 bool "Kernel low-level debugging messages via UART1" 93 bool "Kernel low-level debugging messages via UART1"
94 depends on ARCH_CLPS711X 94 depends on ARCH_CLPS711X
95 help 95 help
96 Say Y here if you want the debug print routines to direct 96 Say Y here if you want the debug print routines to direct
97 their output to the first serial port on these devices. 97 their output to the first serial port on these devices.
98 98
99 config DEBUG_CLPS711X_UART2 99 config DEBUG_CLPS711X_UART2
100 bool "Kernel low-level debugging messages via UART2" 100 bool "Kernel low-level debugging messages via UART2"
101 depends on ARCH_CLPS711X 101 depends on ARCH_CLPS711X
102 help 102 help
103 Say Y here if you want the debug print routines to direct 103 Say Y here if you want the debug print routines to direct
104 their output to the second serial port on these devices. 104 their output to the second serial port on these devices.
105 105
106 config DEBUG_DAVINCI_DA8XX_UART1 106 config DEBUG_DAVINCI_DA8XX_UART1
107 bool "Kernel low-level debugging on DaVinci DA8XX using UART1" 107 bool "Kernel low-level debugging on DaVinci DA8XX using UART1"
108 depends on ARCH_DAVINCI_DA8XX 108 depends on ARCH_DAVINCI_DA8XX
109 help 109 help
110 Say Y here if you want the debug print routines to direct 110 Say Y here if you want the debug print routines to direct
111 their output to UART1 serial port on DaVinci DA8XX devices. 111 their output to UART1 serial port on DaVinci DA8XX devices.
112 112
113 config DEBUG_DAVINCI_DA8XX_UART2 113 config DEBUG_DAVINCI_DA8XX_UART2
114 bool "Kernel low-level debugging on DaVinci DA8XX using UART2" 114 bool "Kernel low-level debugging on DaVinci DA8XX using UART2"
115 depends on ARCH_DAVINCI_DA8XX 115 depends on ARCH_DAVINCI_DA8XX
116 help 116 help
117 Say Y here if you want the debug print routines to direct 117 Say Y here if you want the debug print routines to direct
118 their output to UART2 serial port on DaVinci DA8XX devices. 118 their output to UART2 serial port on DaVinci DA8XX devices.
119 119
120 config DEBUG_DAVINCI_DMx_UART0 120 config DEBUG_DAVINCI_DMx_UART0
121 bool "Kernel low-level debugging on DaVinci DMx using UART0" 121 bool "Kernel low-level debugging on DaVinci DMx using UART0"
122 depends on ARCH_DAVINCI_DMx 122 depends on ARCH_DAVINCI_DMx
123 help 123 help
124 Say Y here if you want the debug print routines to direct 124 Say Y here if you want the debug print routines to direct
125 their output to UART0 serial port on DaVinci DMx devices. 125 their output to UART0 serial port on DaVinci DMx devices.
126 126
127 config DEBUG_DAVINCI_TNETV107X_UART1 127 config DEBUG_DAVINCI_TNETV107X_UART1
128 bool "Kernel low-level debugging on DaVinci TNETV107x using UART1" 128 bool "Kernel low-level debugging on DaVinci TNETV107x using UART1"
129 depends on ARCH_DAVINCI_TNETV107X 129 depends on ARCH_DAVINCI_TNETV107X
130 help 130 help
131 Say Y here if you want the debug print routines to direct 131 Say Y here if you want the debug print routines to direct
132 their output to UART1 serial port on DaVinci TNETV107X 132 their output to UART1 serial port on DaVinci TNETV107X
133 devices. 133 devices.
134 134
135 config DEBUG_DC21285_PORT 135 config DEBUG_DC21285_PORT
136 bool "Kernel low-level debugging messages via footbridge serial port" 136 bool "Kernel low-level debugging messages via footbridge serial port"
137 depends on FOOTBRIDGE 137 depends on FOOTBRIDGE
138 help 138 help
139 Say Y here if you want the debug print routines to direct 139 Say Y here if you want the debug print routines to direct
140 their output to the serial port in the DC21285 (Footbridge). 140 their output to the serial port in the DC21285 (Footbridge).
141 141
142 config DEBUG_FOOTBRIDGE_COM1 142 config DEBUG_FOOTBRIDGE_COM1
143 bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1" 143 bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1"
144 depends on FOOTBRIDGE 144 depends on FOOTBRIDGE
145 help 145 help
146 Say Y here if you want the debug print routines to direct 146 Say Y here if you want the debug print routines to direct
147 their output to the 8250 at PCI COM1. 147 their output to the 8250 at PCI COM1.
148 148
149 config DEBUG_HIGHBANK_UART 149 config DEBUG_HIGHBANK_UART
150 bool "Kernel low-level debugging messages via Highbank UART" 150 bool "Kernel low-level debugging messages via Highbank UART"
151 depends on ARCH_HIGHBANK 151 depends on ARCH_HIGHBANK
152 help 152 help
153 Say Y here if you want the debug print routines to direct 153 Say Y here if you want the debug print routines to direct
154 their output to the UART on Highbank based devices. 154 their output to the UART on Highbank based devices.
155 155
156 config DEBUG_IMX1_UART 156 config DEBUG_IMX1_UART
157 bool "i.MX1 Debug UART" 157 bool "i.MX1 Debug UART"
158 depends on SOC_IMX1 158 depends on SOC_IMX1
159 help 159 help
160 Say Y here if you want kernel low-level debugging support 160 Say Y here if you want kernel low-level debugging support
161 on i.MX1. 161 on i.MX1.
162 162
163 config DEBUG_IMX23_UART 163 config DEBUG_IMX23_UART
164 bool "i.MX23 Debug UART" 164 bool "i.MX23 Debug UART"
165 depends on SOC_IMX23 165 depends on SOC_IMX23
166 help 166 help
167 Say Y here if you want kernel low-level debugging support 167 Say Y here if you want kernel low-level debugging support
168 on i.MX23. 168 on i.MX23.
169 169
170 config DEBUG_IMX25_UART 170 config DEBUG_IMX25_UART
171 bool "i.MX25 Debug UART" 171 bool "i.MX25 Debug UART"
172 depends on SOC_IMX25 172 depends on SOC_IMX25
173 help 173 help
174 Say Y here if you want kernel low-level debugging support 174 Say Y here if you want kernel low-level debugging support
175 on i.MX25. 175 on i.MX25.
176 176
177 config DEBUG_IMX21_IMX27_UART 177 config DEBUG_IMX21_IMX27_UART
178 bool "i.MX21 and i.MX27 Debug UART" 178 bool "i.MX21 and i.MX27 Debug UART"
179 depends on SOC_IMX21 || SOC_IMX27 179 depends on SOC_IMX21 || SOC_IMX27
180 help 180 help
181 Say Y here if you want kernel low-level debugging support 181 Say Y here if you want kernel low-level debugging support
182 on i.MX21 or i.MX27. 182 on i.MX21 or i.MX27.
183 183
184 config DEBUG_IMX28_UART 184 config DEBUG_IMX28_UART
185 bool "i.MX28 Debug UART" 185 bool "i.MX28 Debug UART"
186 depends on SOC_IMX28 186 depends on SOC_IMX28
187 help 187 help
188 Say Y here if you want kernel low-level debugging support 188 Say Y here if you want kernel low-level debugging support
189 on i.MX28. 189 on i.MX28.
190 190
191 config DEBUG_IMX31_IMX35_UART 191 config DEBUG_IMX31_IMX35_UART
192 bool "i.MX31 and i.MX35 Debug UART" 192 bool "i.MX31 and i.MX35 Debug UART"
193 depends on SOC_IMX31 || SOC_IMX35 193 depends on SOC_IMX31 || SOC_IMX35
194 help 194 help
195 Say Y here if you want kernel low-level debugging support 195 Say Y here if you want kernel low-level debugging support
196 on i.MX31 or i.MX35. 196 on i.MX31 or i.MX35.
197 197
198 config DEBUG_IMX51_UART 198 config DEBUG_IMX51_UART
199 bool "i.MX51 Debug UART" 199 bool "i.MX51 Debug UART"
200 depends on SOC_IMX51 200 depends on SOC_IMX51
201 help 201 help
202 Say Y here if you want kernel low-level debugging support 202 Say Y here if you want kernel low-level debugging support
203 on i.MX51. 203 on i.MX51.
204 204
205 config DEBUG_IMX50_IMX53_UART 205 config DEBUG_IMX50_IMX53_UART
206 bool "i.MX50 and i.MX53 Debug UART" 206 bool "i.MX50 and i.MX53 Debug UART"
207 depends on SOC_IMX50 || SOC_IMX53 207 depends on SOC_IMX50 || SOC_IMX53
208 help 208 help
209 Say Y here if you want kernel low-level debugging support 209 Say Y here if you want kernel low-level debugging support
210 on i.MX50 or i.MX53. 210 on i.MX50 or i.MX53.
211 211
212 config DEBUG_IMX6Q_UART2 212 config DEBUG_IMX6Q_UART2
213 bool "i.MX6Q Debug UART2" 213 bool "i.MX6Q Debug UART2"
214 depends on SOC_IMX6Q 214 depends on SOC_IMX6Q
215 help 215 help
216 Say Y here if you want kernel low-level debugging support 216 Say Y here if you want kernel low-level debugging support
217 on i.MX6Q UART2. This is correct for e.g. the SabreLite 217 on i.MX6Q UART2. This is correct for e.g. the SabreLite
218 board. 218 board.
219 219
220 config DEBUG_IMX6Q_UART4 220 config DEBUG_IMX6Q_UART4
221 bool "i.MX6Q Debug UART4" 221 bool "i.MX6Q Debug UART4"
222 depends on SOC_IMX6Q 222 depends on SOC_IMX6Q
223 help 223 help
224 Say Y here if you want kernel low-level debugging support 224 Say Y here if you want kernel low-level debugging support
225 on i.MX6Q UART4. 225 on i.MX6Q UART4.
226 226
227 config DEBUG_MMP_UART2
228 bool "Kernel low-level debugging message via MMP UART2"
229 depends on ARCH_MMP
230 help
231 Say Y here if you want kernel low-level debugging support
232 on MMP UART2.
233
234 config DEBUG_MMP_UART3
235 bool "Kernel low-level debugging message via MMP UART3"
236 depends on ARCH_MMP
237 help
238 Say Y here if you want kernel low-level debugging support
239 on MMP UART3.
240
227 config DEBUG_MSM_UART1 241 config DEBUG_MSM_UART1
228 bool "Kernel low-level debugging messages via MSM UART1" 242 bool "Kernel low-level debugging messages via MSM UART1"
229 depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50 243 depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
230 help 244 help
231 Say Y here if you want the debug print routines to direct 245 Say Y here if you want the debug print routines to direct
232 their output to the first serial port on MSM devices. 246 their output to the first serial port on MSM devices.
233 247
234 config DEBUG_MSM_UART2 248 config DEBUG_MSM_UART2
235 bool "Kernel low-level debugging messages via MSM UART2" 249 bool "Kernel low-level debugging messages via MSM UART2"
236 depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50 250 depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
237 help 251 help
238 Say Y here if you want the debug print routines to direct 252 Say Y here if you want the debug print routines to direct
239 their output to the second serial port on MSM devices. 253 their output to the second serial port on MSM devices.
240 254
241 config DEBUG_MSM_UART3 255 config DEBUG_MSM_UART3
242 bool "Kernel low-level debugging messages via MSM UART3" 256 bool "Kernel low-level debugging messages via MSM UART3"
243 depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50 257 depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
244 help 258 help
245 Say Y here if you want the debug print routines to direct 259 Say Y here if you want the debug print routines to direct
246 their output to the third serial port on MSM devices. 260 their output to the third serial port on MSM devices.
247 261
248 config DEBUG_MSM8660_UART 262 config DEBUG_MSM8660_UART
249 bool "Kernel low-level debugging messages via MSM 8660 UART" 263 bool "Kernel low-level debugging messages via MSM 8660 UART"
250 depends on ARCH_MSM8X60 264 depends on ARCH_MSM8X60
251 select MSM_HAS_DEBUG_UART_HS 265 select MSM_HAS_DEBUG_UART_HS
252 help 266 help
253 Say Y here if you want the debug print routines to direct 267 Say Y here if you want the debug print routines to direct
254 their output to the serial port on MSM 8660 devices. 268 their output to the serial port on MSM 8660 devices.
255 269
256 config DEBUG_MSM8960_UART 270 config DEBUG_MSM8960_UART
257 bool "Kernel low-level debugging messages via MSM 8960 UART" 271 bool "Kernel low-level debugging messages via MSM 8960 UART"
258 depends on ARCH_MSM8960 272 depends on ARCH_MSM8960
259 select MSM_HAS_DEBUG_UART_HS 273 select MSM_HAS_DEBUG_UART_HS
260 help 274 help
261 Say Y here if you want the debug print routines to direct 275 Say Y here if you want the debug print routines to direct
262 their output to the serial port on MSM 8960 devices. 276 their output to the serial port on MSM 8960 devices.
263 277
264 config DEBUG_REALVIEW_STD_PORT 278 config DEBUG_REALVIEW_STD_PORT
265 bool "RealView Default UART" 279 bool "RealView Default UART"
266 depends on ARCH_REALVIEW 280 depends on ARCH_REALVIEW
267 help 281 help
268 Say Y here if you want the debug print routines to direct 282 Say Y here if you want the debug print routines to direct
269 their output to the serial port on RealView EB, PB11MP, PBA8 283 their output to the serial port on RealView EB, PB11MP, PBA8
270 and PBX platforms. 284 and PBX platforms.
271 285
272 config DEBUG_REALVIEW_PB1176_PORT 286 config DEBUG_REALVIEW_PB1176_PORT
273 bool "RealView PB1176 UART" 287 bool "RealView PB1176 UART"
274 depends on MACH_REALVIEW_PB1176 288 depends on MACH_REALVIEW_PB1176
275 help 289 help
276 Say Y here if you want the debug print routines to direct 290 Say Y here if you want the debug print routines to direct
277 their output to the standard serial port on the RealView 291 their output to the standard serial port on the RealView
278 PB1176 platform. 292 PB1176 platform.
279 293
280 config DEBUG_S3C_UART0 294 config DEBUG_S3C_UART0
281 depends on PLAT_SAMSUNG 295 depends on PLAT_SAMSUNG
282 bool "Use S3C UART 0 for low-level debug" 296 bool "Use S3C UART 0 for low-level debug"
283 help 297 help
284 Say Y here if you want the debug print routines to direct 298 Say Y here if you want the debug print routines to direct
285 their output to UART 0. The port must have been initialised 299 their output to UART 0. The port must have been initialised
286 by the boot-loader before use. 300 by the boot-loader before use.
287 301
288 The uncompressor code port configuration is now handled 302 The uncompressor code port configuration is now handled
289 by CONFIG_S3C_LOWLEVEL_UART_PORT. 303 by CONFIG_S3C_LOWLEVEL_UART_PORT.
290 304
291 config DEBUG_S3C_UART1 305 config DEBUG_S3C_UART1
292 depends on PLAT_SAMSUNG 306 depends on PLAT_SAMSUNG
293 bool "Use S3C UART 1 for low-level debug" 307 bool "Use S3C UART 1 for low-level debug"
294 help 308 help
295 Say Y here if you want the debug print routines to direct 309 Say Y here if you want the debug print routines to direct
296 their output to UART 1. The port must have been initialised 310 their output to UART 1. The port must have been initialised
297 by the boot-loader before use. 311 by the boot-loader before use.
298 312
299 The uncompressor code port configuration is now handled 313 The uncompressor code port configuration is now handled
300 by CONFIG_S3C_LOWLEVEL_UART_PORT. 314 by CONFIG_S3C_LOWLEVEL_UART_PORT.
301 315
302 config DEBUG_S3C_UART2 316 config DEBUG_S3C_UART2
303 depends on PLAT_SAMSUNG 317 depends on PLAT_SAMSUNG
304 bool "Use S3C UART 2 for low-level debug" 318 bool "Use S3C UART 2 for low-level debug"
305 help 319 help
306 Say Y here if you want the debug print routines to direct 320 Say Y here if you want the debug print routines to direct
307 their output to UART 2. The port must have been initialised 321 their output to UART 2. The port must have been initialised
308 by the boot-loader before use. 322 by the boot-loader before use.
309 323
310 The uncompressor code port configuration is now handled 324 The uncompressor code port configuration is now handled
311 by CONFIG_S3C_LOWLEVEL_UART_PORT. 325 by CONFIG_S3C_LOWLEVEL_UART_PORT.
312 326
313 config DEBUG_VEXPRESS_UART0_DETECT 327 config DEBUG_VEXPRESS_UART0_DETECT
314 bool "Autodetect UART0 on Versatile Express Cortex-A core tiles" 328 bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
315 depends on ARCH_VEXPRESS && CPU_CP15_MMU 329 depends on ARCH_VEXPRESS && CPU_CP15_MMU
316 help 330 help
317 This option enables a simple heuristic which tries to determine 331 This option enables a simple heuristic which tries to determine
318 the motherboard's memory map variant (original or RS1) and then 332 the motherboard's memory map variant (original or RS1) and then
319 choose the relevant UART0 base address. 333 choose the relevant UART0 base address.
320 334
321 Note that this will only work with standard A-class core tiles, 335 Note that this will only work with standard A-class core tiles,
322 and may fail with non-standard SMM or custom software models. 336 and may fail with non-standard SMM or custom software models.
323 337
324 config DEBUG_VEXPRESS_UART0_CA9 338 config DEBUG_VEXPRESS_UART0_CA9
325 bool "Use PL011 UART0 at 0x10009000 (V2P-CA9 core tile)" 339 bool "Use PL011 UART0 at 0x10009000 (V2P-CA9 core tile)"
326 depends on ARCH_VEXPRESS 340 depends on ARCH_VEXPRESS
327 help 341 help
328 This option selects UART0 at 0x10009000. Except for custom models, 342 This option selects UART0 at 0x10009000. Except for custom models,
329 this applies only to the V2P-CA9 tile. 343 this applies only to the V2P-CA9 tile.
330 344
331 config DEBUG_VEXPRESS_UART0_RS1 345 config DEBUG_VEXPRESS_UART0_RS1
332 bool "Use PL011 UART0 at 0x1c090000 (RS1 complaint tiles)" 346 bool "Use PL011 UART0 at 0x1c090000 (RS1 complaint tiles)"
333 depends on ARCH_VEXPRESS 347 depends on ARCH_VEXPRESS
334 help 348 help
335 This option selects UART0 at 0x1c090000. This applies to most 349 This option selects UART0 at 0x1c090000. This applies to most
336 of the tiles using the RS1 memory map, including all new A-class 350 of the tiles using the RS1 memory map, including all new A-class
337 core tiles, FPGA-based SMMs and software models. 351 core tiles, FPGA-based SMMs and software models.
338 352
339 config DEBUG_LL_UART_NONE 353 config DEBUG_LL_UART_NONE
340 bool "No low-level debugging UART" 354 bool "No low-level debugging UART"
341 help 355 help
342 Say Y here if your platform doesn't provide a UART option 356 Say Y here if your platform doesn't provide a UART option
343 below. This relies on your platform choosing the right UART 357 below. This relies on your platform choosing the right UART
344 definition internally in order for low-level debugging to 358 definition internally in order for low-level debugging to
345 work. 359 work.
346 360
347 config DEBUG_ICEDCC 361 config DEBUG_ICEDCC
348 bool "Kernel low-level debugging via EmbeddedICE DCC channel" 362 bool "Kernel low-level debugging via EmbeddedICE DCC channel"
349 help 363 help
350 Say Y here if you want the debug print routines to direct 364 Say Y here if you want the debug print routines to direct
351 their output to the EmbeddedICE macrocell's DCC channel using 365 their output to the EmbeddedICE macrocell's DCC channel using
352 co-processor 14. This is known to work on the ARM9 style ICE 366 co-processor 14. This is known to work on the ARM9 style ICE
353 channel and on the XScale with the PEEDI. 367 channel and on the XScale with the PEEDI.
354 368
355 Note that the system will appear to hang during boot if there 369 Note that the system will appear to hang during boot if there
356 is nothing connected to read from the DCC. 370 is nothing connected to read from the DCC.
357 371
358 config DEBUG_SEMIHOSTING 372 config DEBUG_SEMIHOSTING
359 bool "Kernel low-level debug output via semihosting I/O" 373 bool "Kernel low-level debug output via semihosting I/O"
360 help 374 help
361 Semihosting enables code running on an ARM target to use 375 Semihosting enables code running on an ARM target to use
362 the I/O facilities on a host debugger/emulator through a 376 the I/O facilities on a host debugger/emulator through a
363 simple SVC call. The host debugger or emulator must have 377 simple SVC call. The host debugger or emulator must have
364 semihosting enabled for the special svc call to be trapped 378 semihosting enabled for the special svc call to be trapped
365 otherwise the kernel will crash. 379 otherwise the kernel will crash.
366 380
367 This is known to work with OpenOCD, as well as 381 This is known to work with OpenOCD, as well as
368 ARM's Fast Models, or any other controlling environment 382 ARM's Fast Models, or any other controlling environment
369 that implements semihosting. 383 that implements semihosting.
370 384
371 For more details about semihosting, please see 385 For more details about semihosting, please see
372 chapter 8 of DUI0203I_rvct_developer_guide.pdf from ARM Ltd. 386 chapter 8 of DUI0203I_rvct_developer_guide.pdf from ARM Ltd.
373 387
374 endchoice 388 endchoice
375 389
376 config EARLY_PRINTK 390 config EARLY_PRINTK
377 bool "Early printk" 391 bool "Early printk"
378 depends on DEBUG_LL 392 depends on DEBUG_LL
379 help 393 help
380 Say Y here if you want to have an early console using the 394 Say Y here if you want to have an early console using the
381 kernel low-level debugging functions. Add earlyprintk to your 395 kernel low-level debugging functions. Add earlyprintk to your
382 kernel parameters to enable this console. 396 kernel parameters to enable this console.
383 397
384 config OC_ETM 398 config OC_ETM
385 bool "On-chip ETM and ETB" 399 bool "On-chip ETM and ETB"
386 depends on ARM_AMBA 400 depends on ARM_AMBA
387 help 401 help
388 Enables the on-chip embedded trace macrocell and embedded trace 402 Enables the on-chip embedded trace macrocell and embedded trace
389 buffer driver that will allow you to collect traces of the 403 buffer driver that will allow you to collect traces of the
390 kernel code. 404 kernel code.
391 405
392 config ARM_KPROBES_TEST 406 config ARM_KPROBES_TEST
393 tristate "Kprobes test module" 407 tristate "Kprobes test module"
394 depends on KPROBES && MODULES 408 depends on KPROBES && MODULES
395 help 409 help
396 Perform tests of kprobes API and instruction set simulation. 410 Perform tests of kprobes API and instruction set simulation.
397 411
398 config PID_IN_CONTEXTIDR 412 config PID_IN_CONTEXTIDR
399 bool "Write the current PID to the CONTEXTIDR register" 413 bool "Write the current PID to the CONTEXTIDR register"
400 depends on CPU_COPY_V6 414 depends on CPU_COPY_V6
401 help 415 help
402 Enabling this option causes the kernel to write the current PID to 416 Enabling this option causes the kernel to write the current PID to
403 the PROCID field of the CONTEXTIDR register, at the expense of some 417 the PROCID field of the CONTEXTIDR register, at the expense of some
404 additional instructions during context switch. Say Y here only if you 418 additional instructions during context switch. Say Y here only if you
405 are planning to use hardware trace tools with this kernel. 419 are planning to use hardware trace tools with this kernel.
406 420
407 endmenu 421 endmenu
408 422
arch/arm/boot/dts/exynos4210-origen.dts
Diff comments   View file @ 95360fd
1 /* 1 /*
2 * Samsung's Exynos4210 based Origen board device tree source 2 * Samsung's Exynos4210 based Origen board device tree source
3 * 3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com 5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd. 6 * Copyright (c) 2010-2011 Linaro Ltd.
7 * www.linaro.org 7 * www.linaro.org
8 * 8 *
9 * Device tree source file for Insignal's Origen board which is based on 9 * Device tree source file for Insignal's Origen board which is based on
10 * Samsung's Exynos4210 SoC. 10 * Samsung's Exynos4210 SoC.
11 * 11 *
12 * This program is free software; you can redistribute it and/or modify 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as 13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation. 14 * published by the Free Software Foundation.
15 */ 15 */
16 16
17 /dts-v1/; 17 /dts-v1/;
18 /include/ "exynos4210.dtsi" 18 /include/ "exynos4210.dtsi"
19 19
20 / { 20 / {
21 model = "Insignal Origen evaluation board based on Exynos4210"; 21 model = "Insignal Origen evaluation board based on Exynos4210";
22 compatible = "insignal,origen", "samsung,exynos4210"; 22 compatible = "insignal,origen", "samsung,exynos4210";
23 23
24 memory { 24 memory {
25 reg = <0x40000000 0x40000000>; 25 reg = <0x40000000 0x40000000>;
26 }; 26 };
27 27
28 chosen { 28 chosen {
29 bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; 29 bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
30 }; 30 };
31 31
32 sdhci@12530000 { 32 sdhci@12530000 {
33 samsung,sdhci-bus-width = <4>; 33 samsung,sdhci-bus-width = <4>;
34 linux,mmc_cap_4_bit_data; 34 linux,mmc_cap_4_bit_data;
35 samsung,sdhci-cd-internal; 35 samsung,sdhci-cd-internal;
36 gpio-cd = <&gpk2 2 2 3 3>; 36 gpio-cd = <&gpk2 2 2 3 3>;
37 gpios = <&gpk2 0 2 0 3>, 37 gpios = <&gpk2 0 2 0 3>,
38 <&gpk2 1 2 0 3>, 38 <&gpk2 1 2 0 3>,
39 <&gpk2 3 2 3 3>, 39 <&gpk2 3 2 3 3>,
40 <&gpk2 4 2 3 3>, 40 <&gpk2 4 2 3 3>,
41 <&gpk2 5 2 3 3>, 41 <&gpk2 5 2 3 3>,
42 <&gpk2 6 2 3 3>; 42 <&gpk2 6 2 3 3>;
43 }; 43 };
44 44
45 sdhci@12510000 { 45 sdhci@12510000 {
46 samsung,sdhci-bus-width = <4>; 46 samsung,sdhci-bus-width = <4>;
47 linux,mmc_cap_4_bit_data; 47 linux,mmc_cap_4_bit_data;
48 samsung,sdhci-cd-internal; 48 samsung,sdhci-cd-internal;
49 gpio-cd = <&gpk0 2 2 3 3>; 49 gpio-cd = <&gpk0 2 2 3 3>;
50 gpios = <&gpk0 0 2 0 3>, 50 gpios = <&gpk0 0 2 0 3>,
51 <&gpk0 1 2 0 3>, 51 <&gpk0 1 2 0 3>,
52 <&gpk0 3 2 3 3>, 52 <&gpk0 3 2 3 3>,
53 <&gpk0 4 2 3 3>, 53 <&gpk0 4 2 3 3>,
54 <&gpk0 5 2 3 3>, 54 <&gpk0 5 2 3 3>,
55 <&gpk0 6 2 3 3>; 55 <&gpk0 6 2 3 3>;
56 }; 56 };
57 57
58 gpio_keys { 58 gpio_keys {
59 compatible = "gpio-keys"; 59 compatible = "gpio-keys";
60 #address-cells = <1>; 60 #address-cells = <1>;
61 #size-cells = <0>; 61 #size-cells = <0>;
62 62
63 up { 63 up {
64 label = "Up"; 64 label = "Up";
65 gpios = <&gpx2 0 0 0 2>; 65 gpios = <&gpx2 0 0 0x10000 2>;
66 linux,code = <103>; 66 linux,code = <103>;
67 }; 67 };
68 68
69 down { 69 down {
70 label = "Down"; 70 label = "Down";
71 gpios = <&gpx2 1 0 0 2>; 71 gpios = <&gpx2 1 0 0x10000 2>;
72 linux,code = <108>; 72 linux,code = <108>;
73 }; 73 };
74 74
75 back { 75 back {
76 label = "Back"; 76 label = "Back";
77 gpios = <&gpx1 7 0 0 2>; 77 gpios = <&gpx1 7 0 0x10000 2>;
78 linux,code = <158>; 78 linux,code = <158>;
79 }; 79 };
80 80
81 home { 81 home {
82 label = "Home"; 82 label = "Home";
83 gpios = <&gpx1 6 0 0 2>; 83 gpios = <&gpx1 6 0 0x10000 2>;
84 linux,code = <102>; 84 linux,code = <102>;
85 }; 85 };
86 86
87 menu { 87 menu {
88 label = "Menu"; 88 label = "Menu";
89 gpios = <&gpx1 5 0 0 2>; 89 gpios = <&gpx1 5 0 0x10000 2>;
90 linux,code = <139>; 90 linux,code = <139>;
91 };
92 };
93
94 leds {
95 compatible = "gpio-leds";
96 status {
97 gpios = <&gpx1 3 0 0x10000 2>;
98 linux,default-trigger = "heartbeat";
91 }; 99 };
92 }; 100 };
93 101
94 keypad@100A0000 { 102 keypad@100A0000 {
95 status = "disabled"; 103 status = "disabled";
96 }; 104 };
97 105
98 sdhci@12520000 { 106 sdhci@12520000 {
99 status = "disabled"; 107 status = "disabled";
100 }; 108 };
101 109
102 sdhci@12540000 { 110 sdhci@12540000 {
103 status = "disabled"; 111 status = "disabled";
104 }; 112 };
105 113
106 i2c@13860000 { 114 i2c@13860000 {
107 status = "disabled"; 115 status = "disabled";
108 }; 116 };
109 117
110 i2c@13870000 { 118 i2c@13870000 {
111 status = "disabled"; 119 status = "disabled";
112 }; 120 };
113 121
114 i2c@13880000 { 122 i2c@13880000 {
115 status = "disabled"; 123 status = "disabled";
116 }; 124 };
117 125
118 i2c@13890000 { 126 i2c@13890000 {
119 status = "disabled"; 127 status = "disabled";
120 }; 128 };
121 129
122 i2c@138A0000 { 130 i2c@138A0000 {
123 status = "disabled"; 131 status = "disabled";
124 }; 132 };
125 133
126 i2c@138B0000 { 134 i2c@138B0000 {
127 status = "disabled"; 135 status = "disabled";
128 }; 136 };
129 137
130 i2c@138C0000 { 138 i2c@138C0000 {
131 status = "disabled"; 139 status = "disabled";
132 }; 140 };
133 141
134 i2c@138D0000 { 142 i2c@138D0000 {
135 status = "disabled"; 143 status = "disabled";
136 }; 144 };
137 145
138 spi_0: spi@13920000 { 146 spi_0: spi@13920000 {
139 status = "disabled"; 147 status = "disabled";
140 }; 148 };
141 149
142 spi_1: spi@13930000 { 150 spi_1: spi@13930000 {
143 status = "disabled"; 151 status = "disabled";
144 }; 152 };
145 153
146 spi_2: spi@13940000 { 154 spi_2: spi@13940000 {
147 status = "disabled"; 155 status = "disabled";
148 }; 156 };
149 }; 157 };
150 158
arch/arm/configs/armadillo800eva_defconfig
Diff comments   View file @ 95360fd
1 CONFIG_EXPERIMENTAL=y 1 CONFIG_EXPERIMENTAL=y
2 CONFIG_SYSVIPC=y 2 CONFIG_SYSVIPC=y
3 CONFIG_IKCONFIG=y 3 CONFIG_IKCONFIG=y
4 CONFIG_IKCONFIG_PROC=y 4 CONFIG_IKCONFIG_PROC=y
5 CONFIG_LOG_BUF_SHIFT=16 5 CONFIG_LOG_BUF_SHIFT=16
6 # CONFIG_UTS_NS is not set 6 # CONFIG_UTS_NS is not set
7 # CONFIG_IPC_NS is not set 7 # CONFIG_IPC_NS is not set
8 # CONFIG_PID_NS is not set 8 # CONFIG_PID_NS is not set
9 CONFIG_CC_OPTIMIZE_FOR_SIZE=y 9 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
10 CONFIG_SLAB=y 10 CONFIG_SLAB=y
11 CONFIG_MODULES=y 11 CONFIG_MODULES=y
12 CONFIG_MODULE_UNLOAD=y 12 CONFIG_MODULE_UNLOAD=y
13 CONFIG_MODULE_FORCE_UNLOAD=y 13 CONFIG_MODULE_FORCE_UNLOAD=y
14 # CONFIG_BLK_DEV_BSG is not set 14 # CONFIG_BLK_DEV_BSG is not set
15 # CONFIG_IOSCHED_DEADLINE is not set 15 # CONFIG_IOSCHED_DEADLINE is not set
16 # CONFIG_IOSCHED_CFQ is not set 16 # CONFIG_IOSCHED_CFQ is not set
17 CONFIG_ARCH_SHMOBILE=y 17 CONFIG_ARCH_SHMOBILE=y
18 CONFIG_ARCH_R8A7740=y 18 CONFIG_ARCH_R8A7740=y
19 CONFIG_MACH_ARMADILLO800EVA=y 19 CONFIG_MACH_ARMADILLO800EVA=y
20 # CONFIG_SH_TIMER_TMU is not set 20 # CONFIG_SH_TIMER_TMU is not set
21 CONFIG_ARM_THUMB=y 21 CONFIG_ARM_THUMB=y
22 CONFIG_CPU_BPREDICT_DISABLE=y 22 CONFIG_CPU_BPREDICT_DISABLE=y
23 # CONFIG_CACHE_L2X0 is not set 23 # CONFIG_CACHE_L2X0 is not set
24 CONFIG_ARM_ERRATA_430973=y 24 CONFIG_ARM_ERRATA_430973=y
25 CONFIG_ARM_ERRATA_458693=y 25 CONFIG_ARM_ERRATA_458693=y
26 CONFIG_ARM_ERRATA_460075=y 26 CONFIG_ARM_ERRATA_460075=y
27 CONFIG_ARM_ERRATA_720789=y 27 CONFIG_ARM_ERRATA_720789=y
28 CONFIG_ARM_ERRATA_743622=y 28 CONFIG_ARM_ERRATA_743622=y
29 CONFIG_ARM_ERRATA_751472=y 29 CONFIG_ARM_ERRATA_751472=y
30 CONFIG_ARM_ERRATA_754322=y 30 CONFIG_ARM_ERRATA_754322=y
31 CONFIG_AEABI=y 31 CONFIG_AEABI=y
32 # CONFIG_OABI_COMPAT is not set 32 # CONFIG_OABI_COMPAT is not set
33 CONFIG_FORCE_MAX_ZONEORDER=13 33 CONFIG_FORCE_MAX_ZONEORDER=13
34 CONFIG_ZBOOT_ROM_TEXT=0x0 34 CONFIG_ZBOOT_ROM_TEXT=0x0
35 CONFIG_ZBOOT_ROM_BSS=0x0 35 CONFIG_ZBOOT_ROM_BSS=0x0
36 CONFIG_CMDLINE="console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096 rw" 36 CONFIG_CMDLINE="console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096 rw"
37 CONFIG_CMDLINE_FORCE=y 37 CONFIG_CMDLINE_FORCE=y
38 CONFIG_KEXEC=y 38 CONFIG_KEXEC=y
39 CONFIG_VFP=y 39 CONFIG_VFP=y
40 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set 40 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
41 # CONFIG_SUSPEND is not set 41 # CONFIG_SUSPEND is not set
42 CONFIG_NET=y 42 CONFIG_NET=y
43 CONFIG_PACKET=y 43 CONFIG_PACKET=y
44 CONFIG_UNIX=y 44 CONFIG_UNIX=y
45 CONFIG_INET=y 45 CONFIG_INET=y
46 CONFIG_IP_PNP=y 46 CONFIG_IP_PNP=y
47 CONFIG_IP_PNP_DHCP=y 47 CONFIG_IP_PNP_DHCP=y
48 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set 48 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
49 # CONFIG_INET_XFRM_MODE_TUNNEL is not set 49 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
50 # CONFIG_INET_XFRM_MODE_BEET is not set 50 # CONFIG_INET_XFRM_MODE_BEET is not set
51 # CONFIG_INET_LRO is not set 51 # CONFIG_INET_LRO is not set
52 # CONFIG_INET_DIAG is not set 52 # CONFIG_INET_DIAG is not set
53 # CONFIG_IPV6 is not set 53 # CONFIG_IPV6 is not set
54 # CONFIG_WIRELESS is not set 54 # CONFIG_WIRELESS is not set
55 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 55 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
56 CONFIG_SCSI=y 56 CONFIG_SCSI=y
57 CONFIG_BLK_DEV_SD=y 57 CONFIG_BLK_DEV_SD=y
58 CONFIG_MD=y 58 CONFIG_MD=y
59 CONFIG_BLK_DEV_DM=y 59 CONFIG_BLK_DEV_DM=y
60 CONFIG_NETDEVICES=y 60 CONFIG_NETDEVICES=y
61 # CONFIG_NET_VENDOR_BROADCOM is not set 61 # CONFIG_NET_VENDOR_BROADCOM is not set
62 # CONFIG_NET_VENDOR_CHELSIO is not set 62 # CONFIG_NET_VENDOR_CHELSIO is not set
63 # CONFIG_NET_VENDOR_CIRRUS is not set 63 # CONFIG_NET_VENDOR_CIRRUS is not set
64 # CONFIG_NET_VENDOR_FARADAY is not set 64 # CONFIG_NET_VENDOR_FARADAY is not set
65 # CONFIG_NET_VENDOR_INTEL is not set 65 # CONFIG_NET_VENDOR_INTEL is not set
66 # CONFIG_NET_VENDOR_MARVELL is not set 66 # CONFIG_NET_VENDOR_MARVELL is not set
67 # CONFIG_NET_VENDOR_MICREL is not set 67 # CONFIG_NET_VENDOR_MICREL is not set
68 # CONFIG_NET_VENDOR_NATSEMI is not set 68 # CONFIG_NET_VENDOR_NATSEMI is not set
69 CONFIG_SH_ETH=y 69 CONFIG_SH_ETH=y
70 # CONFIG_NET_VENDOR_SEEQ is not set 70 # CONFIG_NET_VENDOR_SEEQ is not set
71 # CONFIG_NET_VENDOR_SMSC is not set 71 # CONFIG_NET_VENDOR_SMSC is not set
72 # CONFIG_NET_VENDOR_STMICRO is not set 72 # CONFIG_NET_VENDOR_STMICRO is not set
73 # CONFIG_WLAN is not set 73 # CONFIG_WLAN is not set
74 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set 74 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
75 CONFIG_INPUT_EVDEV=y 75 CONFIG_INPUT_EVDEV=y
76 # CONFIG_KEYBOARD_ATKBD is not set 76 # CONFIG_KEYBOARD_ATKBD is not set
77 CONFIG_KEYBOARD_GPIO=y 77 CONFIG_KEYBOARD_GPIO=y
78 # CONFIG_INPUT_MOUSE is not set 78 # CONFIG_INPUT_MOUSE is not set
79 CONFIG_INPUT_TOUCHSCREEN=y 79 CONFIG_INPUT_TOUCHSCREEN=y
80 CONFIG_TOUCHSCREEN_ST1232=y 80 CONFIG_TOUCHSCREEN_ST1232=y
81 # CONFIG_SERIO is not set 81 # CONFIG_SERIO is not set
82 # CONFIG_LEGACY_PTYS is not set 82 # CONFIG_LEGACY_PTYS is not set
83 CONFIG_SERIAL_SH_SCI=y 83 CONFIG_SERIAL_SH_SCI=y
84 CONFIG_SERIAL_SH_SCI_NR_UARTS=8 84 CONFIG_SERIAL_SH_SCI_NR_UARTS=8
85 CONFIG_SERIAL_SH_SCI_CONSOLE=y 85 CONFIG_SERIAL_SH_SCI_CONSOLE=y
86 # CONFIG_HW_RANDOM is not set 86 # CONFIG_HW_RANDOM is not set
87 CONFIG_I2C=y 87 CONFIG_I2C=y
88 CONFIG_I2C_GPIO=y
88 CONFIG_I2C_SH_MOBILE=y 89 CONFIG_I2C_SH_MOBILE=y
89 # CONFIG_HWMON is not set 90 # CONFIG_HWMON is not set
90 CONFIG_MEDIA_SUPPORT=y 91 CONFIG_MEDIA_SUPPORT=y
91 CONFIG_VIDEO_DEV=y 92 CONFIG_VIDEO_DEV=y
92 # CONFIG_RC_CORE is not set 93 # CONFIG_RC_CORE is not set
93 # CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set 94 # CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
94 # CONFIG_V4L_USB_DRIVERS is not set 95 # CONFIG_V4L_USB_DRIVERS is not set
95 CONFIG_V4L_PLATFORM_DRIVERS=y 96 CONFIG_V4L_PLATFORM_DRIVERS=y
96 CONFIG_SOC_CAMERA=y 97 CONFIG_SOC_CAMERA=y
97 CONFIG_SOC_CAMERA_MT9T112=y 98 CONFIG_SOC_CAMERA_MT9T112=y
98 CONFIG_VIDEO_SH_MOBILE_CEU=y 99 CONFIG_VIDEO_SH_MOBILE_CEU=y
99 # CONFIG_RADIO_ADAPTERS is not set 100 # CONFIG_RADIO_ADAPTERS is not set
100 CONFIG_FB=y 101 CONFIG_FB=y
101 CONFIG_FB_SH_MOBILE_LCDC=y 102 CONFIG_FB_SH_MOBILE_LCDC=y
102 CONFIG_FB_SH_MOBILE_HDMI=y 103 CONFIG_FB_SH_MOBILE_HDMI=y
103 CONFIG_LCD_CLASS_DEVICE=y 104 CONFIG_LCD_CLASS_DEVICE=y
104 CONFIG_FRAMEBUFFER_CONSOLE=y 105 CONFIG_FRAMEBUFFER_CONSOLE=y
105 CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y 106 CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
106 CONFIG_LOGO=y 107 CONFIG_LOGO=y
107 # CONFIG_LOGO_LINUX_MONO is not set 108 # CONFIG_LOGO_LINUX_MONO is not set
108 # CONFIG_LOGO_LINUX_VGA16 is not set 109 # CONFIG_LOGO_LINUX_VGA16 is not set
109 # CONFIG_SND_SUPPORT_OLD_API is not set 110 # CONFIG_SND_SUPPORT_OLD_API is not set
110 # CONFIG_SND_VERBOSE_PROCFS is not set 111 # CONFIG_SND_VERBOSE_PROCFS is not set
111 # CONFIG_SND_DRIVERS is not set 112 # CONFIG_SND_DRIVERS is not set
112 # CONFIG_SND_ARM is not set 113 # CONFIG_SND_ARM is not set
113 CONFIG_SND_SOC_SH4_FSI=y 114 CONFIG_SND_SOC_SH4_FSI=y
114 # CONFIG_HID_SUPPORT is not set 115 # CONFIG_HID_SUPPORT is not set
115 CONFIG_USB=y 116 CONFIG_USB=y
116 CONFIG_USB_RENESAS_USBHS=y 117 CONFIG_USB_RENESAS_USBHS=y
117 CONFIG_USB_GADGET=y 118 CONFIG_USB_GADGET=y
118 CONFIG_USB_RENESAS_USBHS_UDC=y 119 CONFIG_USB_RENESAS_USBHS_UDC=y
119 CONFIG_USB_ETH=m 120 CONFIG_USB_ETH=m
120 CONFIG_MMC=y 121 CONFIG_MMC=y
121 CONFIG_MMC_SDHI=y 122 CONFIG_MMC_SDHI=y
122 CONFIG_MMC_SH_MMCIF=y 123 CONFIG_MMC_SH_MMCIF=y
124 CONFIG_RTC_CLASS=y
125 CONFIG_RTC_DRV_S35390A=y
123 CONFIG_DMADEVICES=y 126 CONFIG_DMADEVICES=y
124 CONFIG_SH_DMAE=y 127 CONFIG_SH_DMAE=y
125 CONFIG_UIO=y 128 CONFIG_UIO=y
126 CONFIG_UIO_PDRV_GENIRQ=y 129 CONFIG_UIO_PDRV_GENIRQ=y
127 # CONFIG_DNOTIFY is not set 130 # CONFIG_DNOTIFY is not set
128 CONFIG_MSDOS_FS=y 131 CONFIG_MSDOS_FS=y
129 CONFIG_VFAT_FS=y 132 CONFIG_VFAT_FS=y
130 CONFIG_TMPFS=y 133 CONFIG_TMPFS=y
131 # CONFIG_MISC_FILESYSTEMS is not set 134 # CONFIG_MISC_FILESYSTEMS is not set
132 CONFIG_NFS_FS=y 135 CONFIG_NFS_FS=y
133 CONFIG_NFS_V3_ACL=y 136 CONFIG_NFS_V3_ACL=y
134 CONFIG_NFS_V4=y 137 CONFIG_NFS_V4=y
135 CONFIG_NFS_V4_1=y 138 CONFIG_NFS_V4_1=y
136 CONFIG_ROOT_NFS=y 139 CONFIG_ROOT_NFS=y
137 CONFIG_NLS_CODEPAGE_437=y 140 CONFIG_NLS_CODEPAGE_437=y
138 CONFIG_NLS_ISO8859_1=y 141 CONFIG_NLS_ISO8859_1=y
139 # CONFIG_ENABLE_WARN_DEPRECATED is not set 142 # CONFIG_ENABLE_WARN_DEPRECATED is not set
140 # CONFIG_ENABLE_MUST_CHECK is not set 143 # CONFIG_ENABLE_MUST_CHECK is not set
141 # CONFIG_ARM_UNWIND is not set 144 # CONFIG_ARM_UNWIND is not set
142 CONFIG_CRYPTO=y 145 CONFIG_CRYPTO=y
143 CONFIG_CRYPTO_CBC=y 146 CONFIG_CRYPTO_CBC=y
144 CONFIG_CRYPTO_MD5=y 147 CONFIG_CRYPTO_MD5=y
145 CONFIG_CRYPTO_DES=y 148 CONFIG_CRYPTO_DES=y
146 CONFIG_CRYPTO_ANSI_CPRNG=y 149 CONFIG_CRYPTO_ANSI_CPRNG=y
147 CONFIG_XZ_DEC=y 150 CONFIG_XZ_DEC=y
148 151
arch/arm/configs/marzen_defconfig
Diff comments   View file @ 95360fd
1 # CONFIG_ARM_PATCH_PHYS_VIRT is not set 1 # CONFIG_ARM_PATCH_PHYS_VIRT is not set
2 CONFIG_EXPERIMENTAL=y 2 CONFIG_EXPERIMENTAL=y
3 CONFIG_KERNEL_LZMA=y 3 CONFIG_KERNEL_LZMA=y
4 CONFIG_IKCONFIG=y 4 CONFIG_IKCONFIG=y
5 CONFIG_IKCONFIG_PROC=y 5 CONFIG_IKCONFIG_PROC=y
6 CONFIG_LOG_BUF_SHIFT=16 6 CONFIG_LOG_BUF_SHIFT=16
7 CONFIG_SYSCTL_SYSCALL=y 7 CONFIG_SYSCTL_SYSCALL=y
8 CONFIG_EMBEDDED=y 8 CONFIG_EMBEDDED=y
9 CONFIG_SLAB=y 9 CONFIG_SLAB=y
10 # CONFIG_BLOCK is not set 10 # CONFIG_BLOCK is not set
11 CONFIG_ARCH_SHMOBILE=y 11 CONFIG_ARCH_SHMOBILE=y
12 CONFIG_ARCH_R8A7779=y 12 CONFIG_ARCH_R8A7779=y
13 CONFIG_MACH_MARZEN=y 13 CONFIG_MACH_MARZEN=y
14 CONFIG_MEMORY_START=0x60000000 14 CONFIG_MEMORY_START=0x60000000
15 CONFIG_MEMORY_SIZE=0x10000000 15 CONFIG_MEMORY_SIZE=0x10000000
16 CONFIG_SHMOBILE_TIMER_HZ=1024 16 CONFIG_SHMOBILE_TIMER_HZ=1024
17 # CONFIG_SH_TIMER_CMT is not set 17 # CONFIG_SH_TIMER_CMT is not set
18 # CONFIG_SWP_EMULATE is not set 18 # CONFIG_SWP_EMULATE is not set
19 CONFIG_ARM_ERRATA_430973=y 19 CONFIG_ARM_ERRATA_430973=y
20 CONFIG_ARM_ERRATA_458693=y 20 CONFIG_ARM_ERRATA_458693=y
21 CONFIG_ARM_ERRATA_460075=y 21 CONFIG_ARM_ERRATA_460075=y
22 CONFIG_ARM_ERRATA_743622=y 22 CONFIG_ARM_ERRATA_743622=y
23 CONFIG_ARM_ERRATA_754322=y 23 CONFIG_ARM_ERRATA_754322=y
24 CONFIG_NO_HZ=y 24 CONFIG_NO_HZ=y
25 CONFIG_SMP=y 25 CONFIG_SMP=y
26 # CONFIG_ARM_CPU_TOPOLOGY is not set 26 # CONFIG_ARM_CPU_TOPOLOGY is not set
27 CONFIG_AEABI=y 27 CONFIG_AEABI=y
28 # CONFIG_OABI_COMPAT is not set 28 # CONFIG_OABI_COMPAT is not set
29 CONFIG_HIGHMEM=y 29 CONFIG_HIGHMEM=y
30 CONFIG_ZBOOT_ROM_TEXT=0x0 30 CONFIG_ZBOOT_ROM_TEXT=0x0
31 CONFIG_ZBOOT_ROM_BSS=0x0 31 CONFIG_ZBOOT_ROM_BSS=0x0
32 CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel" 32 CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel"
33 CONFIG_CMDLINE_FORCE=y 33 CONFIG_CMDLINE_FORCE=y
34 CONFIG_KEXEC=y 34 CONFIG_KEXEC=y
35 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set 35 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
36 CONFIG_PM_RUNTIME=y 36 CONFIG_PM_RUNTIME=y
37 CONFIG_NET=y 37 CONFIG_NET=y
38 CONFIG_INET=y 38 CONFIG_INET=y
39 # CONFIG_IPV6 is not set 39 # CONFIG_IPV6 is not set
40 # CONFIG_WIRELESS is not set 40 # CONFIG_WIRELESS is not set
41 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 41 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
42 CONFIG_DEVTMPFS=y 42 CONFIG_DEVTMPFS=y
43 CONFIG_DEVTMPFS_MOUNT=y 43 CONFIG_DEVTMPFS_MOUNT=y
44 # CONFIG_STANDALONE is not set 44 # CONFIG_STANDALONE is not set
45 # CONFIG_PREVENT_FIRMWARE_BUILD is not set 45 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
46 # CONFIG_FW_LOADER is not set 46 # CONFIG_FW_LOADER is not set
47 CONFIG_NETDEVICES=y 47 CONFIG_NETDEVICES=y
48 # CONFIG_NET_VENDOR_BROADCOM is not set 48 # CONFIG_NET_VENDOR_BROADCOM is not set
49 # CONFIG_NET_VENDOR_FARADAY is not set 49 # CONFIG_NET_VENDOR_FARADAY is not set
50 # CONFIG_NET_VENDOR_INTEL is not set 50 # CONFIG_NET_VENDOR_INTEL is not set
51 # CONFIG_NET_VENDOR_MICREL is not set 51 # CONFIG_NET_VENDOR_MICREL is not set
52 # CONFIG_NET_VENDOR_NATSEMI is not set 52 # CONFIG_NET_VENDOR_NATSEMI is not set
53 # CONFIG_NET_VENDOR_SEEQ is not set 53 # CONFIG_NET_VENDOR_SEEQ is not set
54 CONFIG_SMC911X=y 54 CONFIG_SMC911X=y
55 CONFIG_SMSC911X=y 55 CONFIG_SMSC911X=y
56 # CONFIG_NET_VENDOR_STMICRO is not set 56 # CONFIG_NET_VENDOR_STMICRO is not set
57 # CONFIG_WLAN is not set 57 # CONFIG_WLAN is not set
58 # CONFIG_INPUT_MOUSEDEV is not set 58 # CONFIG_INPUT_MOUSEDEV is not set
59 # CONFIG_INPUT_KEYBOARD is not set 59 # CONFIG_INPUT_KEYBOARD is not set
60 # CONFIG_INPUT_MOUSE is not set 60 # CONFIG_INPUT_MOUSE is not set
61 # CONFIG_SERIO is not set 61 # CONFIG_SERIO is not set
62 # CONFIG_VT is not set 62 # CONFIG_VT is not set
63 # CONFIG_LEGACY_PTYS is not set 63 # CONFIG_LEGACY_PTYS is not set
64 # CONFIG_DEVKMEM is not set 64 # CONFIG_DEVKMEM is not set
65 CONFIG_SERIAL_SH_SCI=y 65 CONFIG_SERIAL_SH_SCI=y
66 CONFIG_SERIAL_SH_SCI_NR_UARTS=6 66 CONFIG_SERIAL_SH_SCI_NR_UARTS=6
67 CONFIG_SERIAL_SH_SCI_CONSOLE=y 67 CONFIG_SERIAL_SH_SCI_CONSOLE=y
68 # CONFIG_HW_RANDOM is not set 68 # CONFIG_HW_RANDOM is not set
69 CONFIG_GPIO_SYSFS=y 69 CONFIG_GPIO_SYSFS=y
70 # CONFIG_HWMON is not set 70 # CONFIG_HWMON is not set
71 CONFIG_THERMAL=y
72 CONFIG_RCAR_THERMAL=y
71 CONFIG_SSB=y 73 CONFIG_SSB=y
72 # CONFIG_HID_SUPPORT is not set 74 # CONFIG_HID_SUPPORT is not set
73 # CONFIG_USB_SUPPORT is not set 75 # CONFIG_USB_SUPPORT is not set
74 CONFIG_UIO=y 76 CONFIG_UIO=y
75 CONFIG_UIO_PDRV_GENIRQ=y 77 CONFIG_UIO_PDRV_GENIRQ=y
76 # CONFIG_IOMMU_SUPPORT is not set 78 # CONFIG_IOMMU_SUPPORT is not set
77 # CONFIG_FILE_LOCKING is not set 79 # CONFIG_FILE_LOCKING is not set
78 # CONFIG_DNOTIFY is not set 80 # CONFIG_DNOTIFY is not set
79 # CONFIG_INOTIFY_USER is not set 81 # CONFIG_INOTIFY_USER is not set
80 CONFIG_TMPFS=y 82 CONFIG_TMPFS=y
81 # CONFIG_MISC_FILESYSTEMS is not set 83 # CONFIG_MISC_FILESYSTEMS is not set
82 CONFIG_MAGIC_SYSRQ=y 84 CONFIG_MAGIC_SYSRQ=y
83 CONFIG_DEBUG_INFO=y 85 CONFIG_DEBUG_INFO=y
84 CONFIG_DEBUG_INFO_REDUCED=y 86 CONFIG_DEBUG_INFO_REDUCED=y
85 # CONFIG_FTRACE is not set 87 # CONFIG_FTRACE is not set
86 CONFIG_DEBUG_USER=y 88 CONFIG_DEBUG_USER=y
87 CONFIG_AVERAGE=y 89 CONFIG_AVERAGE=y
88 90
arch/arm/configs/mmp2_defconfig
Diff comments   View file @ 95360fd
1 CONFIG_EXPERIMENTAL=y 1 CONFIG_EXPERIMENTAL=y
2 CONFIG_SYSVIPC=y 2 CONFIG_SYSVIPC=y
3 CONFIG_LOG_BUF_SHIFT=14 3 CONFIG_LOG_BUF_SHIFT=14
4 CONFIG_SYSFS_DEPRECATED_V2=y 4 CONFIG_SYSFS_DEPRECATED_V2=y
5 CONFIG_SLAB=y 5 CONFIG_SLAB=y
6 CONFIG_MODULES=y 6 CONFIG_MODULES=y
7 CONFIG_MODULE_UNLOAD=y 7 CONFIG_MODULE_UNLOAD=y
8 CONFIG_MODULE_FORCE_UNLOAD=y 8 CONFIG_MODULE_FORCE_UNLOAD=y
9 # CONFIG_BLK_DEV_BSG is not set 9 # CONFIG_BLK_DEV_BSG is not set
10 CONFIG_ARCH_MMP=y 10 CONFIG_ARCH_MMP=y
11 CONFIG_MACH_BROWNSTONE=y 11 CONFIG_MACH_BROWNSTONE=y
12 CONFIG_MACH_FLINT=y 12 CONFIG_MACH_FLINT=y
13 CONFIG_MACH_MARVELL_JASPER=y 13 CONFIG_MACH_MARVELL_JASPER=y
14 CONFIG_HIGH_RES_TIMERS=y 14 CONFIG_HIGH_RES_TIMERS=y
15 CONFIG_PREEMPT=y 15 CONFIG_PREEMPT=y
16 CONFIG_AEABI=y 16 CONFIG_AEABI=y
17 CONFIG_ZBOOT_ROM_TEXT=0x0 17 CONFIG_ZBOOT_ROM_TEXT=0x0
18 CONFIG_ZBOOT_ROM_BSS=0x0 18 CONFIG_ZBOOT_ROM_BSS=0x0
19 CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on console=ttyS2,38400 mem=128M user_debug=255" 19 CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on console=ttyS2,38400 mem=128M user_debug=255 earlyprintk"
20 CONFIG_VFP=y 20 CONFIG_VFP=y
21 CONFIG_NET=y 21 CONFIG_NET=y
22 CONFIG_PACKET=y 22 CONFIG_PACKET=y
23 CONFIG_UNIX=y 23 CONFIG_UNIX=y
24 CONFIG_INET=y 24 CONFIG_INET=y
25 CONFIG_IP_PNP=y 25 CONFIG_IP_PNP=y
26 # CONFIG_INET_LRO is not set 26 # CONFIG_INET_LRO is not set
27 # CONFIG_IPV6 is not set 27 # CONFIG_IPV6 is not set
28 # CONFIG_STANDALONE is not set 28 # CONFIG_STANDALONE is not set
29 # CONFIG_PREVENT_FIRMWARE_BUILD is not set 29 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
30 CONFIG_MTD=y 30 CONFIG_MTD=y
31 CONFIG_MTD_CMDLINE_PARTS=y 31 CONFIG_MTD_CMDLINE_PARTS=y
32 CONFIG_MTD_BLOCK=y 32 CONFIG_MTD_BLOCK=y
33 CONFIG_MTD_NAND=y 33 CONFIG_MTD_NAND=y
34 CONFIG_MTD_ONENAND=y 34 CONFIG_MTD_ONENAND=y
35 CONFIG_MTD_ONENAND_GENERIC=y 35 CONFIG_MTD_ONENAND_GENERIC=y
36 # CONFIG_BLK_DEV is not set 36 # CONFIG_BLK_DEV is not set
37 # CONFIG_MISC_DEVICES is not set 37 # CONFIG_MISC_DEVICES is not set
38 CONFIG_NETDEVICES=y 38 CONFIG_NETDEVICES=y
39 CONFIG_NET_ETHERNET=y 39 CONFIG_NET_ETHERNET=y
40 CONFIG_SMC91X=y 40 CONFIG_SMC91X=y
41 # CONFIG_NETDEV_1000 is not set 41 # CONFIG_NETDEV_1000 is not set
42 # CONFIG_NETDEV_10000 is not set 42 # CONFIG_NETDEV_10000 is not set
43 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set 43 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
44 # CONFIG_INPUT_KEYBOARD is not set 44 # CONFIG_INPUT_KEYBOARD is not set
45 # CONFIG_INPUT_MOUSE is not set 45 # CONFIG_INPUT_MOUSE is not set
46 # CONFIG_SERIO is not set 46 # CONFIG_SERIO is not set
47 CONFIG_SERIAL_PXA=y 47 CONFIG_SERIAL_PXA=y
48 CONFIG_SERIAL_PXA_CONSOLE=y 48 CONFIG_SERIAL_PXA_CONSOLE=y
49 # CONFIG_LEGACY_PTYS is not set 49 # CONFIG_LEGACY_PTYS is not set
50 # CONFIG_HW_RANDOM is not set 50 # CONFIG_HW_RANDOM is not set
51 CONFIG_I2C=y 51 CONFIG_I2C=y
52 CONFIG_I2C_PXA=y 52 CONFIG_I2C_PXA=y
53 # CONFIG_HWMON is not set 53 # CONFIG_HWMON is not set
54 CONFIG_MFD_MAX8925=y 54 CONFIG_MFD_MAX8925=y
55 CONFIG_REGULATOR=y 55 CONFIG_REGULATOR=y
56 CONFIG_REGULATOR_MAX8649=y 56 CONFIG_REGULATOR_MAX8649=y
57 CONFIG_REGULATOR_MAX8925=y 57 CONFIG_REGULATOR_MAX8925=y
58 CONFIG_BACKLIGHT_LCD_SUPPORT=y 58 CONFIG_BACKLIGHT_LCD_SUPPORT=y
59 CONFIG_LCD_CLASS_DEVICE=y 59 CONFIG_LCD_CLASS_DEVICE=y
60 CONFIG_BACKLIGHT_CLASS_DEVICE=y 60 CONFIG_BACKLIGHT_CLASS_DEVICE=y
61 CONFIG_BACKLIGHT_MAX8925=y 61 CONFIG_BACKLIGHT_MAX8925=y
62 # CONFIG_VGA_CONSOLE is not set 62 # CONFIG_VGA_CONSOLE is not set
63 # CONFIG_HID_SUPPORT is not set 63 # CONFIG_HID_SUPPORT is not set
64 # CONFIG_USB_SUPPORT is not set 64 # CONFIG_USB_SUPPORT is not set
65 CONFIG_RTC_CLASS=y 65 CONFIG_RTC_CLASS=y
66 CONFIG_RTC_DRV_MAX8925=y 66 CONFIG_RTC_DRV_MAX8925=y
67 CONFIG_MMC=y 67 CONFIG_MMC=y
68 # CONFIG_DNOTIFY is not set 68 # CONFIG_DNOTIFY is not set
69 CONFIG_INOTIFY=y 69 CONFIG_INOTIFY=y
70 CONFIG_TMPFS=y 70 CONFIG_TMPFS=y
71 CONFIG_TMPFS_POSIX_ACL=y 71 CONFIG_TMPFS_POSIX_ACL=y
72 CONFIG_EXT2_FS=y 72 CONFIG_EXT2_FS=y
73 CONFIG_EXT3_FS=y 73 CONFIG_EXT3_FS=y
74 CONFIG_EXT4_FS=y 74 CONFIG_EXT4_FS=y
75 CONFIG_MSDOS_FS=y 75 CONFIG_MSDOS_FS=y
76 CONFIG_FAT_DEFAULT_CODEPAGE=437 76 CONFIG_FAT_DEFAULT_CODEPAGE=437
77 CONFIG_JFFS2_FS=y 77 CONFIG_JFFS2_FS=y
78 CONFIG_CRAMFS=y 78 CONFIG_CRAMFS=y
79 CONFIG_NFS_FS=y 79 CONFIG_NFS_FS=y
80 CONFIG_NFS_V3=y 80 CONFIG_NFS_V3=y
81 CONFIG_NFS_V3_ACL=y 81 CONFIG_NFS_V3_ACL=y
82 CONFIG_NFS_V4=y 82 CONFIG_NFS_V4=y
83 CONFIG_ROOT_NFS=y 83 CONFIG_ROOT_NFS=y
84 CONFIG_PRINTK_TIME=y 84 CONFIG_PRINTK_TIME=y
85 CONFIG_MAGIC_SYSRQ=y 85 CONFIG_MAGIC_SYSRQ=y
86 CONFIG_DEBUG_FS=y 86 CONFIG_DEBUG_FS=y
87 CONFIG_DEBUG_KERNEL=y 87 CONFIG_DEBUG_KERNEL=y
88 # CONFIG_DEBUG_PREEMPT is not set 88 # CONFIG_DEBUG_PREEMPT is not set
89 CONFIG_DEBUG_INFO=y 89 CONFIG_DEBUG_INFO=y
90 # CONFIG_RCU_CPU_STALL_DETECTOR is not set 90 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
91 # CONFIG_DYNAMIC_DEBUG is not set 91 # CONFIG_DYNAMIC_DEBUG is not set
92 CONFIG_DEBUG_USER=y 92 CONFIG_DEBUG_USER=y
93 CONFIG_DEBUG_LL=y
94 CONFIG_DEBUG_MMP_UART3=y
95 CONFIG_EARLY_PRINTK=y
93 CONFIG_DEBUG_ERRORS=y 96 CONFIG_DEBUG_ERRORS=y
94 # CONFIG_CRYPTO_ANSI_CPRNG is not set 97 # CONFIG_CRYPTO_ANSI_CPRNG is not set
95 CONFIG_CRC_CCITT=y 98 CONFIG_CRC_CCITT=y
96 99
arch/arm/configs/pxa910_defconfig
Diff comments   View file @ 95360fd
1 CONFIG_EXPERIMENTAL=y 1 CONFIG_EXPERIMENTAL=y
2 CONFIG_SYSVIPC=y 2 CONFIG_SYSVIPC=y
3 CONFIG_LOG_BUF_SHIFT=14 3 CONFIG_LOG_BUF_SHIFT=14
4 CONFIG_SYSFS_DEPRECATED_V2=y 4 CONFIG_SYSFS_DEPRECATED_V2=y
5 CONFIG_BLK_DEV_INITRD=y 5 CONFIG_BLK_DEV_INITRD=y
6 CONFIG_SLAB=y 6 CONFIG_SLAB=y
7 CONFIG_MODULES=y 7 CONFIG_MODULES=y
8 CONFIG_MODULE_UNLOAD=y 8 CONFIG_MODULE_UNLOAD=y
9 CONFIG_MODULE_FORCE_UNLOAD=y 9 CONFIG_MODULE_FORCE_UNLOAD=y
10 # CONFIG_BLK_DEV_BSG is not set 10 # CONFIG_BLK_DEV_BSG is not set
11 CONFIG_ARCH_MMP=y 11 CONFIG_ARCH_MMP=y
12 CONFIG_MACH_TAVOREVB=y 12 CONFIG_MACH_TAVOREVB=y
13 CONFIG_MACH_TTC_DKB=y 13 CONFIG_MACH_TTC_DKB=y
14 CONFIG_NO_HZ=y 14 CONFIG_NO_HZ=y
15 CONFIG_HIGH_RES_TIMERS=y 15 CONFIG_HIGH_RES_TIMERS=y
16 CONFIG_PREEMPT=y 16 CONFIG_PREEMPT=y
17 CONFIG_AEABI=y 17 CONFIG_AEABI=y
18 CONFIG_ZBOOT_ROM_TEXT=0x0 18 CONFIG_ZBOOT_ROM_TEXT=0x0
19 CONFIG_ZBOOT_ROM_BSS=0x0 19 CONFIG_ZBOOT_ROM_BSS=0x0
20 CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.2.100:/nfsroot/ ip=192.168.2.101:192.168.2.100::255.255.255.0::eth0:on console=ttyS0,115200 mem=128M" 20 CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.2.100:/nfsroot/ ip=192.168.2.101:192.168.2.100::255.255.255.0::eth0:on console=ttyS0,115200 mem=128M earlyprintk"
21 CONFIG_FPE_NWFPE=y 21 CONFIG_FPE_NWFPE=y
22 CONFIG_NET=y 22 CONFIG_NET=y
23 CONFIG_PACKET=y 23 CONFIG_PACKET=y
24 CONFIG_UNIX=y 24 CONFIG_UNIX=y
25 CONFIG_INET=y 25 CONFIG_INET=y
26 CONFIG_IP_PNP=y 26 CONFIG_IP_PNP=y
27 # CONFIG_INET_LRO is not set 27 # CONFIG_INET_LRO is not set
28 # CONFIG_IPV6 is not set 28 # CONFIG_IPV6 is not set
29 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 29 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
30 # CONFIG_STANDALONE is not set 30 # CONFIG_STANDALONE is not set
31 # CONFIG_PREVENT_FIRMWARE_BUILD is not set 31 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
32 # CONFIG_BLK_DEV is not set 32 # CONFIG_BLK_DEV is not set
33 # CONFIG_MISC_DEVICES is not set 33 # CONFIG_MISC_DEVICES is not set
34 CONFIG_NETDEVICES=y 34 CONFIG_NETDEVICES=y
35 CONFIG_NET_ETHERNET=y 35 CONFIG_NET_ETHERNET=y
36 CONFIG_SMC91X=y 36 CONFIG_SMC91X=y
37 # CONFIG_NETDEV_1000 is not set 37 # CONFIG_NETDEV_1000 is not set
38 # CONFIG_NETDEV_10000 is not set 38 # CONFIG_NETDEV_10000 is not set
39 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set 39 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
40 # CONFIG_INPUT_KEYBOARD is not set 40 # CONFIG_INPUT_KEYBOARD is not set
41 # CONFIG_INPUT_MOUSE is not set 41 # CONFIG_INPUT_MOUSE is not set
42 # CONFIG_SERIO is not set 42 # CONFIG_SERIO is not set
43 CONFIG_SERIAL_PXA=y 43 CONFIG_SERIAL_PXA=y
44 CONFIG_SERIAL_PXA_CONSOLE=y 44 CONFIG_SERIAL_PXA_CONSOLE=y
45 # CONFIG_LEGACY_PTYS is not set 45 # CONFIG_LEGACY_PTYS is not set
46 # CONFIG_HW_RANDOM is not set 46 # CONFIG_HW_RANDOM is not set
47 # CONFIG_HWMON is not set 47 # CONFIG_HWMON is not set
48 # CONFIG_VGA_CONSOLE is not set 48 # CONFIG_VGA_CONSOLE is not set
49 # CONFIG_HID_SUPPORT is not set 49 # CONFIG_HID_SUPPORT is not set
50 # CONFIG_USB_SUPPORT is not set 50 # CONFIG_USB_SUPPORT is not set
51 CONFIG_INOTIFY=y 51 CONFIG_INOTIFY=y
52 CONFIG_TMPFS=y 52 CONFIG_TMPFS=y
53 CONFIG_TMPFS_POSIX_ACL=y 53 CONFIG_TMPFS_POSIX_ACL=y
54 CONFIG_CRAMFS=y 54 CONFIG_CRAMFS=y
55 CONFIG_NFS_FS=y 55 CONFIG_NFS_FS=y
56 CONFIG_NFS_V3=y 56 CONFIG_NFS_V3=y
57 CONFIG_NFS_V3_ACL=y 57 CONFIG_NFS_V3_ACL=y
58 CONFIG_NFS_V4=y 58 CONFIG_NFS_V4=y
59 CONFIG_ROOT_NFS=y 59 CONFIG_ROOT_NFS=y
60 CONFIG_PRINTK_TIME=y 60 CONFIG_PRINTK_TIME=y
61 CONFIG_MAGIC_SYSRQ=y 61 CONFIG_MAGIC_SYSRQ=y
62 CONFIG_DEBUG_KERNEL=y 62 CONFIG_DEBUG_KERNEL=y
63 # CONFIG_DEBUG_PREEMPT is not set 63 # CONFIG_DEBUG_PREEMPT is not set
64 CONFIG_DEBUG_INFO=y 64 CONFIG_DEBUG_INFO=y
65 # CONFIG_RCU_CPU_STALL_DETECTOR is not set 65 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
66 CONFIG_DEBUG_USER=y 66 CONFIG_DEBUG_USER=y
67 CONFIG_DEBUG_ERRORS=y 67 CONFIG_DEBUG_ERRORS=y
68 CONFIG_DEBUG_LL=y 68 CONFIG_DEBUG_LL=y
69 CONFIG_DEBUG_MMP_UART2=y
70 CONFIG_EARLY_PRINTK=y
69 # CONFIG_CRYPTO_ANSI_CPRNG is not set 71 # CONFIG_CRYPTO_ANSI_CPRNG is not set
70 CONFIG_CRC_CCITT=y 72 CONFIG_CRC_CCITT=y
71 73
arch/arm/mach-exynos/Kconfig
Diff comments   View file @ 95360fd
1 # arch/arm/mach-exynos/Kconfig 1 # arch/arm/mach-exynos/Kconfig
2 # 2 #
3 # Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 3 # Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 # http://www.samsung.com/ 4 # http://www.samsung.com/
5 # 5 #
6 # Licensed under GPLv2 6 # Licensed under GPLv2
7 7
8 # Configuration options for the EXYNOS4 8 # Configuration options for the EXYNOS4
9 9
10 if ARCH_EXYNOS 10 if ARCH_EXYNOS
11 11
12 menu "SAMSUNG EXYNOS SoCs Support" 12 menu "SAMSUNG EXYNOS SoCs Support"
13 13
14 config ARCH_EXYNOS4 14 config ARCH_EXYNOS4
15 bool "SAMSUNG EXYNOS4" 15 bool "SAMSUNG EXYNOS4"
16 default y 16 default y
17 select HAVE_SMP 17 select HAVE_SMP
18 select MIGHT_HAVE_CACHE_L2X0 18 select MIGHT_HAVE_CACHE_L2X0
19 help 19 help
20 Samsung EXYNOS4 SoCs based systems 20 Samsung EXYNOS4 SoCs based systems
21 21
22 config ARCH_EXYNOS5 22 config ARCH_EXYNOS5
23 bool "SAMSUNG EXYNOS5" 23 bool "SAMSUNG EXYNOS5"
24 select HAVE_SMP 24 select HAVE_SMP
25 help 25 help
26 Samsung EXYNOS5 (Cortex-A15) SoC based systems 26 Samsung EXYNOS5 (Cortex-A15) SoC based systems
27 27
28 comment "EXYNOS SoCs" 28 comment "EXYNOS SoCs"
29 29
30 config CPU_EXYNOS4210 30 config CPU_EXYNOS4210
31 bool "SAMSUNG EXYNOS4210" 31 bool "SAMSUNG EXYNOS4210"
32 default y 32 default y
33 depends on ARCH_EXYNOS4 33 depends on ARCH_EXYNOS4
34 select SAMSUNG_DMADEV 34 select SAMSUNG_DMADEV
35 select ARM_CPU_SUSPEND if PM 35 select ARM_CPU_SUSPEND if PM
36 select S5P_PM if PM 36 select S5P_PM if PM
37 select S5P_SLEEP if PM 37 select S5P_SLEEP if PM
38 select PM_GENERIC_DOMAINS 38 select PM_GENERIC_DOMAINS
39 help 39 help
40 Enable EXYNOS4210 CPU support 40 Enable EXYNOS4210 CPU support
41 41
42 config SOC_EXYNOS4212 42 config SOC_EXYNOS4212
43 bool "SAMSUNG EXYNOS4212" 43 bool "SAMSUNG EXYNOS4212"
44 default y 44 default y
45 depends on ARCH_EXYNOS4 45 depends on ARCH_EXYNOS4
46 select SAMSUNG_DMADEV 46 select SAMSUNG_DMADEV
47 select S5P_PM if PM 47 select S5P_PM if PM
48 select S5P_SLEEP if PM 48 select S5P_SLEEP if PM
49 help 49 help
50 Enable EXYNOS4212 SoC support 50 Enable EXYNOS4212 SoC support
51 51
52 config SOC_EXYNOS4412 52 config SOC_EXYNOS4412
53 bool "SAMSUNG EXYNOS4412" 53 bool "SAMSUNG EXYNOS4412"
54 default y 54 default y
55 depends on ARCH_EXYNOS4 55 depends on ARCH_EXYNOS4
56 select SAMSUNG_DMADEV 56 select SAMSUNG_DMADEV
57 help 57 help
58 Enable EXYNOS4412 SoC support 58 Enable EXYNOS4412 SoC support
59 59
60 config SOC_EXYNOS5250 60 config SOC_EXYNOS5250
61 bool "SAMSUNG EXYNOS5250" 61 bool "SAMSUNG EXYNOS5250"
62 default y 62 default y
63 depends on ARCH_EXYNOS5 63 depends on ARCH_EXYNOS5
64 select SAMSUNG_DMADEV 64 select SAMSUNG_DMADEV
65 select S5P_PM if PM 65 select S5P_PM if PM
66 select S5P_SLEEP if PM 66 select S5P_SLEEP if PM
67 help 67 help
68 Enable EXYNOS5250 SoC support 68 Enable EXYNOS5250 SoC support
69 69
70 config EXYNOS4_MCT 70 config EXYNOS4_MCT
71 bool 71 bool
72 default y 72 default y
73 help 73 help
74 Use MCT (Multi Core Timer) as kernel timers 74 Use MCT (Multi Core Timer) as kernel timers
75 75
76 config EXYNOS_DEV_DMA 76 config EXYNOS_DEV_DMA
77 bool 77 bool
78 help 78 help
79 Compile in amba device definitions for DMA controller 79 Compile in amba device definitions for DMA controller
80 80
81 config EXYNOS4_DEV_AHCI 81 config EXYNOS4_DEV_AHCI
82 bool 82 bool
83 help 83 help
84 Compile in platform device definitions for AHCI 84 Compile in platform device definitions for AHCI
85 85
86 config EXYNOS_DEV_DRM 86 config EXYNOS_DEV_DRM
87 bool 87 bool
88 help 88 help
89 Compile in platform device definitions for core DRM device 89 Compile in platform device definitions for core DRM device
90 90
91 config EXYNOS4_SETUP_FIMD0 91 config EXYNOS4_SETUP_FIMD0
92 bool 92 bool
93 help 93 help
94 Common setup code for FIMD0. 94 Common setup code for FIMD0.
95 95
96 config EXYNOS_DEV_SYSMMU 96 config EXYNOS_DEV_SYSMMU
97 bool 97 bool
98 help 98 help
99 Common setup code for SYSTEM MMU in EXYNOS platforms 99 Common setup code for SYSTEM MMU in EXYNOS platforms
100 100
101 config EXYNOS4_DEV_DWMCI 101 config EXYNOS4_DEV_DWMCI
102 bool 102 bool
103 help 103 help
104 Compile in platform device definitions for DWMCI 104 Compile in platform device definitions for DWMCI
105 105
106 config EXYNOS4_DEV_USB_OHCI 106 config EXYNOS4_DEV_USB_OHCI
107 bool 107 bool
108 help 108 help
109 Compile in platform device definition for USB OHCI 109 Compile in platform device definition for USB OHCI
110 110
111 config EXYNOS4_SETUP_I2C1 111 config EXYNOS4_SETUP_I2C1
112 bool 112 bool
113 help 113 help
114 Common setup code for i2c bus 1. 114 Common setup code for i2c bus 1.
115 115
116 config EXYNOS4_SETUP_I2C2 116 config EXYNOS4_SETUP_I2C2
117 bool 117 bool
118 help 118 help
119 Common setup code for i2c bus 2. 119 Common setup code for i2c bus 2.
120 120
121 config EXYNOS4_SETUP_I2C3 121 config EXYNOS4_SETUP_I2C3
122 bool 122 bool
123 help 123 help
124 Common setup code for i2c bus 3. 124 Common setup code for i2c bus 3.
125 125
126 config EXYNOS4_SETUP_I2C4 126 config EXYNOS4_SETUP_I2C4
127 bool 127 bool
128 help 128 help
129 Common setup code for i2c bus 4. 129 Common setup code for i2c bus 4.
130 130
131 config EXYNOS4_SETUP_I2C5 131 config EXYNOS4_SETUP_I2C5
132 bool 132 bool
133 help 133 help
134 Common setup code for i2c bus 5. 134 Common setup code for i2c bus 5.
135 135
136 config EXYNOS4_SETUP_I2C6 136 config EXYNOS4_SETUP_I2C6
137 bool 137 bool
138 help 138 help
139 Common setup code for i2c bus 6. 139 Common setup code for i2c bus 6.
140 140
141 config EXYNOS4_SETUP_I2C7 141 config EXYNOS4_SETUP_I2C7
142 bool 142 bool
143 help 143 help
144 Common setup code for i2c bus 7. 144 Common setup code for i2c bus 7.
145 145
146 config EXYNOS4_SETUP_KEYPAD 146 config EXYNOS4_SETUP_KEYPAD
147 bool 147 bool
148 help 148 help
149 Common setup code for keypad. 149 Common setup code for keypad.
150 150
151 config EXYNOS4_SETUP_SDHCI 151 config EXYNOS4_SETUP_SDHCI
152 bool 152 bool
153 select EXYNOS4_SETUP_SDHCI_GPIO 153 select EXYNOS4_SETUP_SDHCI_GPIO
154 help 154 help
155 Internal helper functions for EXYNOS4 based SDHCI systems. 155 Internal helper functions for EXYNOS4 based SDHCI systems.
156 156
157 config EXYNOS4_SETUP_SDHCI_GPIO 157 config EXYNOS4_SETUP_SDHCI_GPIO
158 bool 158 bool
159 help 159 help
160 Common setup code for SDHCI gpio. 160 Common setup code for SDHCI gpio.
161 161
162 config EXYNOS4_SETUP_FIMC 162 config EXYNOS4_SETUP_FIMC
163 bool 163 bool
164 help 164 help
165 Common setup code for the camera interfaces. 165 Common setup code for the camera interfaces.
166 166
167 config EXYNOS4_SETUP_USB_PHY 167 config EXYNOS4_SETUP_USB_PHY
168 bool 168 bool
169 help 169 help
170 Common setup code for USB PHY controller 170 Common setup code for USB PHY controller
171 171
172 config EXYNOS_SETUP_SPI 172 config EXYNOS_SETUP_SPI
173 bool 173 bool
174 help 174 help
175 Common setup code for SPI GPIO configurations. 175 Common setup code for SPI GPIO configurations.
176 176
177 # machine support 177 # machine support
178 178
179 if ARCH_EXYNOS4 179 if ARCH_EXYNOS4
180 180
181 comment "EXYNOS4210 Boards" 181 comment "EXYNOS4210 Boards"
182 182
183 config MACH_SMDKC210 183 config MACH_SMDKC210
184 bool "SMDKC210" 184 bool "SMDKC210"
185 select MACH_SMDKV310 185 select MACH_SMDKV310
186 help 186 help
187 Machine support for Samsung SMDKC210 187 Machine support for Samsung SMDKC210
188 188
189 config MACH_SMDKV310 189 config MACH_SMDKV310
190 bool "SMDKV310" 190 bool "SMDKV310"
191 select CPU_EXYNOS4210 191 select CPU_EXYNOS4210
192 select S5P_DEV_FIMD0 192 select S5P_DEV_FIMD0
193 select S3C_DEV_RTC 193 select S3C_DEV_RTC
194 select S3C_DEV_WDT 194 select S3C_DEV_WDT
195 select S3C_DEV_I2C1 195 select S3C_DEV_I2C1
196 select S5P_DEV_FIMC0 196 select S5P_DEV_FIMC0
197 select S5P_DEV_FIMC1 197 select S5P_DEV_FIMC1
198 select S5P_DEV_FIMC2 198 select S5P_DEV_FIMC2
199 select S5P_DEV_FIMC3 199 select S5P_DEV_FIMC3
200 select S5P_DEV_G2D 200 select S5P_DEV_G2D
201 select S5P_DEV_I2C_HDMIPHY 201 select S5P_DEV_I2C_HDMIPHY
202 select S5P_DEV_JPEG 202 select S5P_DEV_JPEG
203 select S5P_DEV_MFC 203 select S5P_DEV_MFC
204 select S5P_DEV_TV 204 select S5P_DEV_TV
205 select S5P_DEV_USB_EHCI 205 select S5P_DEV_USB_EHCI
206 select S3C_DEV_HSMMC 206 select S3C_DEV_HSMMC
207 select S3C_DEV_HSMMC1 207 select S3C_DEV_HSMMC1
208 select S3C_DEV_HSMMC2 208 select S3C_DEV_HSMMC2
209 select S3C_DEV_HSMMC3 209 select S3C_DEV_HSMMC3
210 select S3C_DEV_USB_HSOTG 210 select S3C_DEV_USB_HSOTG
211 select SAMSUNG_DEV_BACKLIGHT 211 select SAMSUNG_DEV_BACKLIGHT
212 select EXYNOS_DEV_DRM 212 select EXYNOS_DEV_DRM
213 select EXYNOS_DEV_SYSMMU 213 select EXYNOS_DEV_SYSMMU
214 select EXYNOS4_DEV_AHCI 214 select EXYNOS4_DEV_AHCI
215 select SAMSUNG_DEV_KEYPAD 215 select SAMSUNG_DEV_KEYPAD
216 select EXYNOS_DEV_DMA 216 select EXYNOS_DEV_DMA
217 select SAMSUNG_DEV_PWM 217 select SAMSUNG_DEV_PWM
218 select EXYNOS4_DEV_USB_OHCI 218 select EXYNOS4_DEV_USB_OHCI
219 select EXYNOS4_SETUP_FIMD0 219 select EXYNOS4_SETUP_FIMD0
220 select EXYNOS4_SETUP_I2C1 220 select EXYNOS4_SETUP_I2C1
221 select EXYNOS4_SETUP_KEYPAD 221 select EXYNOS4_SETUP_KEYPAD
222 select EXYNOS4_SETUP_SDHCI 222 select EXYNOS4_SETUP_SDHCI
223 select EXYNOS4_SETUP_USB_PHY 223 select EXYNOS4_SETUP_USB_PHY
224 select S3C24XX_PWM
224 help 225 help
225 Machine support for Samsung SMDKV310 226 Machine support for Samsung SMDKV310
226 227
227 config MACH_ARMLEX4210 228 config MACH_ARMLEX4210
228 bool "ARMLEX4210" 229 bool "ARMLEX4210"
229 select CPU_EXYNOS4210 230 select CPU_EXYNOS4210
230 select S3C_DEV_RTC 231 select S3C_DEV_RTC
231 select S3C_DEV_WDT 232 select S3C_DEV_WDT
232 select S3C_DEV_HSMMC 233 select S3C_DEV_HSMMC
233 select S3C_DEV_HSMMC2 234 select S3C_DEV_HSMMC2
234 select S3C_DEV_HSMMC3 235 select S3C_DEV_HSMMC3
235 select EXYNOS4_DEV_AHCI 236 select EXYNOS4_DEV_AHCI
236 select EXYNOS_DEV_DMA 237 select EXYNOS_DEV_DMA
237 select EXYNOS4_SETUP_SDHCI 238 select EXYNOS4_SETUP_SDHCI
238 help 239 help
239 Machine support for Samsung ARMLEX4210 based on EXYNOS4210 240 Machine support for Samsung ARMLEX4210 based on EXYNOS4210
240 241
241 config MACH_UNIVERSAL_C210 242 config MACH_UNIVERSAL_C210
242 bool "Mobile UNIVERSAL_C210 Board" 243 bool "Mobile UNIVERSAL_C210 Board"
243 select CPU_EXYNOS4210 244 select CPU_EXYNOS4210
244 select S5P_HRT 245 select S5P_HRT
245 select CLKSRC_MMIO 246 select CLKSRC_MMIO
246 select HAVE_SCHED_CLOCK 247 select HAVE_SCHED_CLOCK
247 select S5P_GPIO_INT 248 select S5P_GPIO_INT
248 select S5P_DEV_FIMC0 249 select S5P_DEV_FIMC0
249 select S5P_DEV_FIMC1 250 select S5P_DEV_FIMC1
250 select S5P_DEV_FIMC2 251 select S5P_DEV_FIMC2
251 select S5P_DEV_FIMC3 252 select S5P_DEV_FIMC3
252 select S5P_DEV_G2D 253 select S5P_DEV_G2D
253 select S5P_DEV_CSIS0 254 select S5P_DEV_CSIS0
254 select S5P_DEV_JPEG 255 select S5P_DEV_JPEG
255 select S5P_DEV_FIMD0 256 select S5P_DEV_FIMD0
256 select S3C_DEV_HSMMC 257 select S3C_DEV_HSMMC
257 select S3C_DEV_HSMMC2 258 select S3C_DEV_HSMMC2
258 select S3C_DEV_HSMMC3 259 select S3C_DEV_HSMMC3
259 select S3C_DEV_I2C1 260 select S3C_DEV_I2C1
260 select S3C_DEV_I2C3 261 select S3C_DEV_I2C3
261 select S3C_DEV_I2C5 262 select S3C_DEV_I2C5
262 select S3C_DEV_USB_HSOTG 263 select S3C_DEV_USB_HSOTG
263 select S5P_DEV_I2C_HDMIPHY 264 select S5P_DEV_I2C_HDMIPHY
264 select S5P_DEV_MFC 265 select S5P_DEV_MFC
265 select S5P_DEV_ONENAND 266 select S5P_DEV_ONENAND
266 select S5P_DEV_TV 267 select S5P_DEV_TV
267 select EXYNOS_DEV_SYSMMU 268 select EXYNOS_DEV_SYSMMU
268 select EXYNOS_DEV_DMA 269 select EXYNOS_DEV_DMA
269 select EXYNOS_DEV_DRM 270 select EXYNOS_DEV_DRM
270 select EXYNOS4_SETUP_FIMD0 271 select EXYNOS4_SETUP_FIMD0
271 select EXYNOS4_SETUP_I2C1 272 select EXYNOS4_SETUP_I2C1
272 select EXYNOS4_SETUP_I2C3 273 select EXYNOS4_SETUP_I2C3
273 select EXYNOS4_SETUP_I2C5 274 select EXYNOS4_SETUP_I2C5
274 select EXYNOS4_SETUP_SDHCI 275 select EXYNOS4_SETUP_SDHCI
275 select EXYNOS4_SETUP_FIMC 276 select EXYNOS4_SETUP_FIMC
276 select S5P_SETUP_MIPIPHY 277 select S5P_SETUP_MIPIPHY
277 select EXYNOS4_SETUP_USB_PHY 278 select EXYNOS4_SETUP_USB_PHY
278 help 279 help
279 Machine support for Samsung Mobile Universal S5PC210 Reference 280 Machine support for Samsung Mobile Universal S5PC210 Reference
280 Board. 281 Board.
281 282
282 config MACH_NURI 283 config MACH_NURI
283 bool "Mobile NURI Board" 284 bool "Mobile NURI Board"
284 select CPU_EXYNOS4210 285 select CPU_EXYNOS4210
285 select S5P_GPIO_INT 286 select S5P_GPIO_INT
286 select S3C_DEV_WDT 287 select S3C_DEV_WDT
287 select S3C_DEV_RTC 288 select S3C_DEV_RTC
288 select S5P_DEV_FIMD0 289 select S5P_DEV_FIMD0
289 select S3C_DEV_HSMMC 290 select S3C_DEV_HSMMC
290 select S3C_DEV_HSMMC2 291 select S3C_DEV_HSMMC2
291 select S3C_DEV_HSMMC3 292 select S3C_DEV_HSMMC3
292 select S3C_DEV_I2C1 293 select S3C_DEV_I2C1
293 select S3C_DEV_I2C3 294 select S3C_DEV_I2C3
294 select S3C_DEV_I2C5 295 select S3C_DEV_I2C5
295 select S3C_DEV_I2C6 296 select S3C_DEV_I2C6
296 select S3C_DEV_USB_HSOTG 297 select S3C_DEV_USB_HSOTG
297 select S5P_DEV_CSIS0 298 select S5P_DEV_CSIS0
298 select S5P_DEV_JPEG 299 select S5P_DEV_JPEG
299 select S5P_DEV_FIMC0 300 select S5P_DEV_FIMC0
300 select S5P_DEV_FIMC1 301 select S5P_DEV_FIMC1
301 select S5P_DEV_FIMC2 302 select S5P_DEV_FIMC2
302 select S5P_DEV_FIMC3 303 select S5P_DEV_FIMC3
303 select S5P_DEV_G2D 304 select S5P_DEV_G2D
304 select S5P_DEV_MFC 305 select S5P_DEV_MFC
305 select S5P_DEV_USB_EHCI 306 select S5P_DEV_USB_EHCI
306 select S5P_SETUP_MIPIPHY 307 select S5P_SETUP_MIPIPHY
307 select EXYNOS_DEV_DMA 308 select EXYNOS_DEV_DMA
308 select EXYNOS_DEV_DRM 309 select EXYNOS_DEV_DRM
309 select EXYNOS4_SETUP_FIMC 310 select EXYNOS4_SETUP_FIMC
310 select EXYNOS4_SETUP_FIMD0 311 select EXYNOS4_SETUP_FIMD0
311 select EXYNOS4_SETUP_I2C1 312 select EXYNOS4_SETUP_I2C1
312 select EXYNOS4_SETUP_I2C3 313 select EXYNOS4_SETUP_I2C3
313 select EXYNOS4_SETUP_I2C5 314 select EXYNOS4_SETUP_I2C5
314 select EXYNOS4_SETUP_I2C6 315 select EXYNOS4_SETUP_I2C6
315 select EXYNOS4_SETUP_SDHCI 316 select EXYNOS4_SETUP_SDHCI
316 select EXYNOS4_SETUP_USB_PHY 317 select EXYNOS4_SETUP_USB_PHY
317 select S5P_SETUP_MIPIPHY 318 select S5P_SETUP_MIPIPHY
318 select SAMSUNG_DEV_PWM 319 select SAMSUNG_DEV_PWM
319 select SAMSUNG_DEV_ADC 320 select SAMSUNG_DEV_ADC
320 help 321 help
321 Machine support for Samsung Mobile NURI Board. 322 Machine support for Samsung Mobile NURI Board.
322 323
323 config MACH_ORIGEN 324 config MACH_ORIGEN
324 bool "ORIGEN" 325 bool "ORIGEN"
325 select CPU_EXYNOS4210 326 select CPU_EXYNOS4210
326 select S3C_DEV_RTC 327 select S3C_DEV_RTC
327 select S3C_DEV_WDT 328 select S3C_DEV_WDT
328 select S3C_DEV_HSMMC 329 select S3C_DEV_HSMMC
329 select S3C_DEV_HSMMC2 330 select S3C_DEV_HSMMC2
330 select S3C_DEV_USB_HSOTG 331 select S3C_DEV_USB_HSOTG
331 select S5P_DEV_FIMC0 332 select S5P_DEV_FIMC0
332 select S5P_DEV_FIMC1 333 select S5P_DEV_FIMC1
333 select S5P_DEV_FIMC2 334 select S5P_DEV_FIMC2
334 select S5P_DEV_FIMC3 335 select S5P_DEV_FIMC3
335 select S5P_DEV_FIMD0 336 select S5P_DEV_FIMD0
336 select S5P_DEV_G2D 337 select S5P_DEV_G2D
337 select S5P_DEV_I2C_HDMIPHY 338 select S5P_DEV_I2C_HDMIPHY
338 select S5P_DEV_JPEG 339 select S5P_DEV_JPEG
339 select S5P_DEV_MFC 340 select S5P_DEV_MFC
340 select S5P_DEV_TV 341 select S5P_DEV_TV
341 select S5P_DEV_USB_EHCI 342 select S5P_DEV_USB_EHCI
342 select SAMSUNG_DEV_BACKLIGHT 343 select SAMSUNG_DEV_BACKLIGHT
343 select SAMSUNG_DEV_PWM 344 select SAMSUNG_DEV_PWM
344 select EXYNOS_DEV_DRM 345 select EXYNOS_DEV_DRM
345 select EXYNOS_DEV_SYSMMU 346 select EXYNOS_DEV_SYSMMU
346 select EXYNOS_DEV_DMA 347 select EXYNOS_DEV_DMA
347 select EXYNOS4_DEV_USB_OHCI 348 select EXYNOS4_DEV_USB_OHCI
348 select EXYNOS4_SETUP_FIMD0 349 select EXYNOS4_SETUP_FIMD0
349 select EXYNOS4_SETUP_SDHCI 350 select EXYNOS4_SETUP_SDHCI
350 select EXYNOS4_SETUP_USB_PHY 351 select EXYNOS4_SETUP_USB_PHY
352 select S3C24XX_PWM
351 help 353 help
352 Machine support for ORIGEN based on Samsung EXYNOS4210 354 Machine support for ORIGEN based on Samsung EXYNOS4210
353 355
354 comment "EXYNOS4212 Boards" 356 comment "EXYNOS4212 Boards"
355 357
356 config MACH_SMDK4212 358 config MACH_SMDK4212
357 bool "SMDK4212" 359 bool "SMDK4212"
358 select SOC_EXYNOS4212 360 select SOC_EXYNOS4212
359 select S3C_DEV_HSMMC2 361 select S3C_DEV_HSMMC2
360 select S3C_DEV_HSMMC3 362 select S3C_DEV_HSMMC3
361 select S3C_DEV_I2C1 363 select S3C_DEV_I2C1
362 select S3C_DEV_I2C3 364 select S3C_DEV_I2C3
363 select S3C_DEV_I2C7 365 select S3C_DEV_I2C7
364 select S3C_DEV_RTC 366 select S3C_DEV_RTC
365 select S3C_DEV_USB_HSOTG 367 select S3C_DEV_USB_HSOTG
366 select S3C_DEV_WDT 368 select S3C_DEV_WDT
367 select S5P_DEV_FIMC0 369 select S5P_DEV_FIMC0
368 select S5P_DEV_FIMC1 370 select S5P_DEV_FIMC1
369 select S5P_DEV_FIMC2 371 select S5P_DEV_FIMC2
370 select S5P_DEV_FIMC3 372 select S5P_DEV_FIMC3
371 select S5P_DEV_FIMD0 373 select S5P_DEV_FIMD0
372 select S5P_DEV_MFC 374 select S5P_DEV_MFC
373 select SAMSUNG_DEV_BACKLIGHT 375 select SAMSUNG_DEV_BACKLIGHT
374 select SAMSUNG_DEV_KEYPAD 376 select SAMSUNG_DEV_KEYPAD
375 select SAMSUNG_DEV_PWM 377 select SAMSUNG_DEV_PWM
376 select EXYNOS_DEV_SYSMMU 378 select EXYNOS_DEV_SYSMMU
377 select EXYNOS_DEV_DMA 379 select EXYNOS_DEV_DMA
378 select EXYNOS_DEV_DRM 380 select EXYNOS_DEV_DRM
379 select EXYNOS4_SETUP_FIMD0 381 select EXYNOS4_SETUP_FIMD0
380 select EXYNOS4_SETUP_I2C1 382 select EXYNOS4_SETUP_I2C1
381 select EXYNOS4_SETUP_I2C3 383 select EXYNOS4_SETUP_I2C3
382 select EXYNOS4_SETUP_I2C7 384 select EXYNOS4_SETUP_I2C7
383 select EXYNOS4_SETUP_KEYPAD 385 select EXYNOS4_SETUP_KEYPAD
384 select EXYNOS4_SETUP_SDHCI 386 select EXYNOS4_SETUP_SDHCI
385 select EXYNOS4_SETUP_USB_PHY 387 select EXYNOS4_SETUP_USB_PHY
388 select S3C24XX_PWM
386 help 389 help
387 Machine support for Samsung SMDK4212 390 Machine support for Samsung SMDK4212
388 391
389 comment "EXYNOS4412 Boards" 392 comment "EXYNOS4412 Boards"
390 393
391 config MACH_SMDK4412 394 config MACH_SMDK4412
392 bool "SMDK4412" 395 bool "SMDK4412"
393 select SOC_EXYNOS4412 396 select SOC_EXYNOS4412
394 select MACH_SMDK4212 397 select MACH_SMDK4212
395 help 398 help
396 Machine support for Samsung SMDK4412 399 Machine support for Samsung SMDK4412
397 endif 400 endif
398 401
399 comment "Flattened Device Tree based board for EXYNOS SoCs" 402 comment "Flattened Device Tree based board for EXYNOS SoCs"
400 403
401 config MACH_EXYNOS4_DT 404 config MACH_EXYNOS4_DT
402 bool "Samsung Exynos4 Machine using device tree" 405 bool "Samsung Exynos4 Machine using device tree"
403 depends on ARCH_EXYNOS4 406 depends on ARCH_EXYNOS4
404 select CPU_EXYNOS4210 407 select CPU_EXYNOS4210
405 select USE_OF 408 select USE_OF
406 select ARM_AMBA 409 select ARM_AMBA
407 select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD 410 select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
408 select PINCTRL 411 select PINCTRL
409 select PINCTRL_EXYNOS4 412 select PINCTRL_EXYNOS4
410 help 413 help
411 Machine support for Samsung Exynos4 machine with device tree enabled. 414 Machine support for Samsung Exynos4 machine with device tree enabled.
412 Select this if a fdt blob is available for the Exynos4 SoC based board. 415 Select this if a fdt blob is available for the Exynos4 SoC based board.
413 Note: This is under development and not all peripherals can be supported 416 Note: This is under development and not all peripherals can be supported
414 with this machine file. 417 with this machine file.
415 418
416 config MACH_EXYNOS5_DT 419 config MACH_EXYNOS5_DT
417 bool "SAMSUNG EXYNOS5 Machine using device tree" 420 bool "SAMSUNG EXYNOS5 Machine using device tree"
418 depends on ARCH_EXYNOS5 421 depends on ARCH_EXYNOS5
419 select SOC_EXYNOS5250 422 select SOC_EXYNOS5250
420 select USE_OF 423 select USE_OF
421 select ARM_AMBA 424 select ARM_AMBA
422 help 425 help
423 Machine support for Samsung EXYNOS5 machine with device tree enabled. 426 Machine support for Samsung EXYNOS5 machine with device tree enabled.
424 Select this if a fdt blob is available for the EXYNOS5 SoC based board. 427 Select this if a fdt blob is available for the EXYNOS5 SoC based board.
425 428
426 if ARCH_EXYNOS4 429 if ARCH_EXYNOS4
427 430
428 comment "Configuration for HSMMC 8-bit bus width" 431 comment "Configuration for HSMMC 8-bit bus width"
429 432
430 config EXYNOS4_SDHCI_CH0_8BIT 433 config EXYNOS4_SDHCI_CH0_8BIT
431 bool "Channel 0 with 8-bit bus" 434 bool "Channel 0 with 8-bit bus"
432 help 435 help
433 Support HSMMC Channel 0 8-bit bus. 436 Support HSMMC Channel 0 8-bit bus.
434 If selected, Channel 1 is disabled. 437 If selected, Channel 1 is disabled.
435 438
436 config EXYNOS4_SDHCI_CH2_8BIT 439 config EXYNOS4_SDHCI_CH2_8BIT
437 bool "Channel 2 with 8-bit bus" 440 bool "Channel 2 with 8-bit bus"
438 help 441 help
439 Support HSMMC Channel 2 8-bit bus. 442 Support HSMMC Channel 2 8-bit bus.
440 If selected, Channel 3 is disabled. 443 If selected, Channel 3 is disabled.
441 endif 444 endif
442 445
443 endmenu 446 endmenu
444 447
445 endif 448 endif
446 449
arch/arm/mach-exynos/mach-origen.c
Diff comments   View file @ 95360fd
1 /* linux/arch/arm/mach-exynos4/mach-origen.c 1 /* linux/arch/arm/mach-exynos4/mach-origen.c
2 * 2 *
3 * Copyright (c) 2011 Insignal Co., Ltd. 3 * Copyright (c) 2011 Insignal Co., Ltd.
4 * http://www.insignal.co.kr/ 4 * http://www.insignal.co.kr/
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11 #include <linux/serial_core.h> 11 #include <linux/serial_core.h>
12 #include <linux/leds.h> 12 #include <linux/leds.h>
13 #include <linux/gpio.h> 13 #include <linux/gpio.h>
14 #include <linux/mmc/host.h> 14 #include <linux/mmc/host.h>
15 #include <linux/platform_device.h> 15 #include <linux/platform_device.h>
16 #include <linux/io.h> 16 #include <linux/io.h>
17 #include <linux/input.h> 17 #include <linux/input.h>
18 #include <linux/pwm.h>
18 #include <linux/pwm_backlight.h> 19 #include <linux/pwm_backlight.h>
19 #include <linux/gpio_keys.h> 20 #include <linux/gpio_keys.h>
20 #include <linux/i2c.h> 21 #include <linux/i2c.h>
21 #include <linux/regulator/machine.h> 22 #include <linux/regulator/machine.h>
22 #include <linux/mfd/max8997.h> 23 #include <linux/mfd/max8997.h>
23 #include <linux/lcd.h> 24 #include <linux/lcd.h>
24 #include <linux/rfkill-gpio.h> 25 #include <linux/rfkill-gpio.h>
25 #include <linux/platform_data/s3c-hsotg.h> 26 #include <linux/platform_data/s3c-hsotg.h>
26 27
27 #include <asm/mach/arch.h> 28 #include <asm/mach/arch.h>
28 #include <asm/hardware/gic.h> 29 #include <asm/hardware/gic.h>
29 #include <asm/mach-types.h> 30 #include <asm/mach-types.h>
30 31
31 #include <video/platform_lcd.h> 32 #include <video/platform_lcd.h>
32 33
33 #include <plat/regs-serial.h> 34 #include <plat/regs-serial.h>
34 #include <plat/regs-fb-v4.h> 35 #include <plat/regs-fb-v4.h>
35 #include <plat/cpu.h> 36 #include <plat/cpu.h>
36 #include <plat/devs.h> 37 #include <plat/devs.h>
37 #include <plat/sdhci.h> 38 #include <plat/sdhci.h>
38 #include <plat/iic.h> 39 #include <plat/iic.h>
39 #include <plat/ehci.h> 40 #include <plat/ehci.h>
40 #include <plat/clock.h> 41 #include <plat/clock.h>
41 #include <plat/gpio-cfg.h> 42 #include <plat/gpio-cfg.h>
42 #include <plat/backlight.h> 43 #include <plat/backlight.h>
43 #include <plat/fb.h> 44 #include <plat/fb.h>
44 #include <plat/mfc.h> 45 #include <plat/mfc.h>
45 #include <plat/hdmi.h> 46 #include <plat/hdmi.h>
46 47
47 #include <mach/ohci.h> 48 #include <mach/ohci.h>
48 #include <mach/map.h> 49 #include <mach/map.h>
49 50
50 #include <drm/exynos_drm.h> 51 #include <drm/exynos_drm.h>
51 #include "common.h" 52 #include "common.h"
52 53
53 /* Following are default values for UCON, ULCON and UFCON UART registers */ 54 /* Following are default values for UCON, ULCON and UFCON UART registers */
54 #define ORIGEN_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 55 #define ORIGEN_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
55 S3C2410_UCON_RXILEVEL | \ 56 S3C2410_UCON_RXILEVEL | \
56 S3C2410_UCON_TXIRQMODE | \ 57 S3C2410_UCON_TXIRQMODE | \
57 S3C2410_UCON_RXIRQMODE | \ 58 S3C2410_UCON_RXIRQMODE | \
58 S3C2410_UCON_RXFIFO_TOI | \ 59 S3C2410_UCON_RXFIFO_TOI | \
59 S3C2443_UCON_RXERR_IRQEN) 60 S3C2443_UCON_RXERR_IRQEN)
60 61
61 #define ORIGEN_ULCON_DEFAULT S3C2410_LCON_CS8 62 #define ORIGEN_ULCON_DEFAULT S3C2410_LCON_CS8
62 63
63 #define ORIGEN_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ 64 #define ORIGEN_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
64 S5PV210_UFCON_TXTRIG4 | \ 65 S5PV210_UFCON_TXTRIG4 | \
65 S5PV210_UFCON_RXTRIG4) 66 S5PV210_UFCON_RXTRIG4)
66 67
67 static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = { 68 static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = {
68 [0] = { 69 [0] = {
69 .hwport = 0, 70 .hwport = 0,
70 .flags = 0, 71 .flags = 0,
71 .ucon = ORIGEN_UCON_DEFAULT, 72 .ucon = ORIGEN_UCON_DEFAULT,
72 .ulcon = ORIGEN_ULCON_DEFAULT, 73 .ulcon = ORIGEN_ULCON_DEFAULT,
73 .ufcon = ORIGEN_UFCON_DEFAULT, 74 .ufcon = ORIGEN_UFCON_DEFAULT,
74 }, 75 },
75 [1] = { 76 [1] = {
76 .hwport = 1, 77 .hwport = 1,
77 .flags = 0, 78 .flags = 0,
78 .ucon = ORIGEN_UCON_DEFAULT, 79 .ucon = ORIGEN_UCON_DEFAULT,
79 .ulcon = ORIGEN_ULCON_DEFAULT, 80 .ulcon = ORIGEN_ULCON_DEFAULT,
80 .ufcon = ORIGEN_UFCON_DEFAULT, 81 .ufcon = ORIGEN_UFCON_DEFAULT,
81 }, 82 },
82 [2] = { 83 [2] = {
83 .hwport = 2, 84 .hwport = 2,
84 .flags = 0, 85 .flags = 0,
85 .ucon = ORIGEN_UCON_DEFAULT, 86 .ucon = ORIGEN_UCON_DEFAULT,
86 .ulcon = ORIGEN_ULCON_DEFAULT, 87 .ulcon = ORIGEN_ULCON_DEFAULT,
87 .ufcon = ORIGEN_UFCON_DEFAULT, 88 .ufcon = ORIGEN_UFCON_DEFAULT,
88 }, 89 },
89 [3] = { 90 [3] = {
90 .hwport = 3, 91 .hwport = 3,
91 .flags = 0, 92 .flags = 0,
92 .ucon = ORIGEN_UCON_DEFAULT, 93 .ucon = ORIGEN_UCON_DEFAULT,
93 .ulcon = ORIGEN_ULCON_DEFAULT, 94 .ulcon = ORIGEN_ULCON_DEFAULT,
94 .ufcon = ORIGEN_UFCON_DEFAULT, 95 .ufcon = ORIGEN_UFCON_DEFAULT,
95 }, 96 },
96 }; 97 };
97 98
98 static struct regulator_consumer_supply __initdata ldo3_consumer[] = { 99 static struct regulator_consumer_supply __initdata ldo3_consumer[] = {
99 REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */ 100 REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */
100 REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), /* HDMI */ 101 REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), /* HDMI */
101 REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), /* HDMI */ 102 REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), /* HDMI */
102 }; 103 };
103 static struct regulator_consumer_supply __initdata ldo6_consumer[] = { 104 static struct regulator_consumer_supply __initdata ldo6_consumer[] = {
104 REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */ 105 REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */
105 }; 106 };
106 static struct regulator_consumer_supply __initdata ldo7_consumer[] = { 107 static struct regulator_consumer_supply __initdata ldo7_consumer[] = {
107 REGULATOR_SUPPLY("avdd", "alc5625"), /* Realtek ALC5625 */ 108 REGULATOR_SUPPLY("avdd", "alc5625"), /* Realtek ALC5625 */
108 }; 109 };
109 static struct regulator_consumer_supply __initdata ldo8_consumer[] = { 110 static struct regulator_consumer_supply __initdata ldo8_consumer[] = {
110 REGULATOR_SUPPLY("vdd", "s5p-adc"), /* ADC */ 111 REGULATOR_SUPPLY("vdd", "s5p-adc"), /* ADC */
111 REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"), /* HDMI */ 112 REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"), /* HDMI */
112 }; 113 };
113 static struct regulator_consumer_supply __initdata ldo9_consumer[] = { 114 static struct regulator_consumer_supply __initdata ldo9_consumer[] = {
114 REGULATOR_SUPPLY("dvdd", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */ 115 REGULATOR_SUPPLY("dvdd", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
115 }; 116 };
116 static struct regulator_consumer_supply __initdata ldo11_consumer[] = { 117 static struct regulator_consumer_supply __initdata ldo11_consumer[] = {
117 REGULATOR_SUPPLY("dvdd", "alc5625"), /* Realtek ALC5625 */ 118 REGULATOR_SUPPLY("dvdd", "alc5625"), /* Realtek ALC5625 */
118 }; 119 };
119 static struct regulator_consumer_supply __initdata ldo14_consumer[] = { 120 static struct regulator_consumer_supply __initdata ldo14_consumer[] = {
120 REGULATOR_SUPPLY("avdd18", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */ 121 REGULATOR_SUPPLY("avdd18", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
121 }; 122 };
122 static struct regulator_consumer_supply __initdata ldo17_consumer[] = { 123 static struct regulator_consumer_supply __initdata ldo17_consumer[] = {
123 REGULATOR_SUPPLY("vdd33", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */ 124 REGULATOR_SUPPLY("vdd33", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
124 }; 125 };
125 static struct regulator_consumer_supply __initdata buck1_consumer[] = { 126 static struct regulator_consumer_supply __initdata buck1_consumer[] = {
126 REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */ 127 REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
127 }; 128 };
128 static struct regulator_consumer_supply __initdata buck2_consumer[] = { 129 static struct regulator_consumer_supply __initdata buck2_consumer[] = {
129 REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */ 130 REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */
130 }; 131 };
131 static struct regulator_consumer_supply __initdata buck3_consumer[] = { 132 static struct regulator_consumer_supply __initdata buck3_consumer[] = {
132 REGULATOR_SUPPLY("vdd_g3d", "mali_drm"), /* G3D */ 133 REGULATOR_SUPPLY("vdd_g3d", "mali_drm"), /* G3D */
133 }; 134 };
134 static struct regulator_consumer_supply __initdata buck7_consumer[] = { 135 static struct regulator_consumer_supply __initdata buck7_consumer[] = {
135 REGULATOR_SUPPLY("vcc", "platform-lcd"), /* LCD */ 136 REGULATOR_SUPPLY("vcc", "platform-lcd"), /* LCD */
136 }; 137 };
137 138
138 static struct regulator_init_data __initdata max8997_ldo1_data = { 139 static struct regulator_init_data __initdata max8997_ldo1_data = {
139 .constraints = { 140 .constraints = {
140 .name = "VDD_ABB_3.3V", 141 .name = "VDD_ABB_3.3V",
141 .min_uV = 3300000, 142 .min_uV = 3300000,
142 .max_uV = 3300000, 143 .max_uV = 3300000,
143 .apply_uV = 1, 144 .apply_uV = 1,
144 .state_mem = { 145 .state_mem = {
145 .disabled = 1, 146 .disabled = 1,
146 }, 147 },
147 }, 148 },
148 }; 149 };
149 150
150 static struct regulator_init_data __initdata max8997_ldo2_data = { 151 static struct regulator_init_data __initdata max8997_ldo2_data = {
151 .constraints = { 152 .constraints = {
152 .name = "VDD_ALIVE_1.1V", 153 .name = "VDD_ALIVE_1.1V",
153 .min_uV = 1100000, 154 .min_uV = 1100000,
154 .max_uV = 1100000, 155 .max_uV = 1100000,
155 .apply_uV = 1, 156 .apply_uV = 1,
156 .always_on = 1, 157 .always_on = 1,
157 .state_mem = { 158 .state_mem = {
158 .enabled = 1, 159 .enabled = 1,
159 }, 160 },
160 }, 161 },
161 }; 162 };
162 163
163 static struct regulator_init_data __initdata max8997_ldo3_data = { 164 static struct regulator_init_data __initdata max8997_ldo3_data = {
164 .constraints = { 165 .constraints = {
165 .name = "VMIPI_1.1V", 166 .name = "VMIPI_1.1V",
166 .min_uV = 1100000, 167 .min_uV = 1100000,
167 .max_uV = 1100000, 168 .max_uV = 1100000,
168 .apply_uV = 1, 169 .apply_uV = 1,
169 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 170 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
170 .state_mem = { 171 .state_mem = {
171 .disabled = 1, 172 .disabled = 1,
172 }, 173 },
173 }, 174 },
174 .num_consumer_supplies = ARRAY_SIZE(ldo3_consumer), 175 .num_consumer_supplies = ARRAY_SIZE(ldo3_consumer),
175 .consumer_supplies = ldo3_consumer, 176 .consumer_supplies = ldo3_consumer,
176 }; 177 };
177 178
178 static struct regulator_init_data __initdata max8997_ldo4_data = { 179 static struct regulator_init_data __initdata max8997_ldo4_data = {
179 .constraints = { 180 .constraints = {
180 .name = "VDD_RTC_1.8V", 181 .name = "VDD_RTC_1.8V",
181 .min_uV = 1800000, 182 .min_uV = 1800000,
182 .max_uV = 1800000, 183 .max_uV = 1800000,
183 .apply_uV = 1, 184 .apply_uV = 1,
184 .always_on = 1, 185 .always_on = 1,
185 .state_mem = { 186 .state_mem = {
186 .disabled = 1, 187 .disabled = 1,
187 }, 188 },
188 }, 189 },
189 }; 190 };
190 191
191 static struct regulator_init_data __initdata max8997_ldo6_data = { 192 static struct regulator_init_data __initdata max8997_ldo6_data = {
192 .constraints = { 193 .constraints = {
193 .name = "VMIPI_1.8V", 194 .name = "VMIPI_1.8V",
194 .min_uV = 1800000, 195 .min_uV = 1800000,
195 .max_uV = 1800000, 196 .max_uV = 1800000,
196 .apply_uV = 1, 197 .apply_uV = 1,
197 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 198 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
198 .state_mem = { 199 .state_mem = {
199 .disabled = 1, 200 .disabled = 1,
200 }, 201 },
201 }, 202 },
202 .num_consumer_supplies = ARRAY_SIZE(ldo6_consumer), 203 .num_consumer_supplies = ARRAY_SIZE(ldo6_consumer),
203 .consumer_supplies = ldo6_consumer, 204 .consumer_supplies = ldo6_consumer,
204 }; 205 };
205 206
206 static struct regulator_init_data __initdata max8997_ldo7_data = { 207 static struct regulator_init_data __initdata max8997_ldo7_data = {
207 .constraints = { 208 .constraints = {
208 .name = "VDD_AUD_1.8V", 209 .name = "VDD_AUD_1.8V",
209 .min_uV = 1800000, 210 .min_uV = 1800000,
210 .max_uV = 1800000, 211 .max_uV = 1800000,
211 .apply_uV = 1, 212 .apply_uV = 1,
212 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 213 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
213 .state_mem = { 214 .state_mem = {
214 .disabled = 1, 215 .disabled = 1,
215 }, 216 },
216 }, 217 },
217 .num_consumer_supplies = ARRAY_SIZE(ldo7_consumer), 218 .num_consumer_supplies = ARRAY_SIZE(ldo7_consumer),
218 .consumer_supplies = ldo7_consumer, 219 .consumer_supplies = ldo7_consumer,
219 }; 220 };
220 221
221 static struct regulator_init_data __initdata max8997_ldo8_data = { 222 static struct regulator_init_data __initdata max8997_ldo8_data = {
222 .constraints = { 223 .constraints = {
223 .name = "VADC_3.3V", 224 .name = "VADC_3.3V",
224 .min_uV = 3300000, 225 .min_uV = 3300000,
225 .max_uV = 3300000, 226 .max_uV = 3300000,
226 .apply_uV = 1, 227 .apply_uV = 1,
227 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 228 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
228 .state_mem = { 229 .state_mem = {
229 .disabled = 1, 230 .disabled = 1,
230 }, 231 },
231 }, 232 },
232 .num_consumer_supplies = ARRAY_SIZE(ldo8_consumer), 233 .num_consumer_supplies = ARRAY_SIZE(ldo8_consumer),
233 .consumer_supplies = ldo8_consumer, 234 .consumer_supplies = ldo8_consumer,
234 }; 235 };
235 236
236 static struct regulator_init_data __initdata max8997_ldo9_data = { 237 static struct regulator_init_data __initdata max8997_ldo9_data = {
237 .constraints = { 238 .constraints = {
238 .name = "DVDD_SWB_2.8V", 239 .name = "DVDD_SWB_2.8V",
239 .min_uV = 2800000, 240 .min_uV = 2800000,
240 .max_uV = 2800000, 241 .max_uV = 2800000,
241 .apply_uV = 1, 242 .apply_uV = 1,
242 .always_on = 1, 243 .always_on = 1,
243 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 244 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
244 .state_mem = { 245 .state_mem = {
245 .disabled = 1, 246 .disabled = 1,
246 }, 247 },
247 }, 248 },
248 .num_consumer_supplies = ARRAY_SIZE(ldo9_consumer), 249 .num_consumer_supplies = ARRAY_SIZE(ldo9_consumer),
249 .consumer_supplies = ldo9_consumer, 250 .consumer_supplies = ldo9_consumer,
250 }; 251 };
251 252
252 static struct regulator_init_data __initdata max8997_ldo10_data = { 253 static struct regulator_init_data __initdata max8997_ldo10_data = {
253 .constraints = { 254 .constraints = {
254 .name = "VDD_PLL_1.1V", 255 .name = "VDD_PLL_1.1V",
255 .min_uV = 1100000, 256 .min_uV = 1100000,
256 .max_uV = 1100000, 257 .max_uV = 1100000,
257 .apply_uV = 1, 258 .apply_uV = 1,
258 .always_on = 1, 259 .always_on = 1,
259 .state_mem = { 260 .state_mem = {
260 .disabled = 1, 261 .disabled = 1,
261 }, 262 },
262 }, 263 },
263 }; 264 };
264 265
265 static struct regulator_init_data __initdata max8997_ldo11_data = { 266 static struct regulator_init_data __initdata max8997_ldo11_data = {
266 .constraints = { 267 .constraints = {
267 .name = "VDD_AUD_3V", 268 .name = "VDD_AUD_3V",
268 .min_uV = 3000000, 269 .min_uV = 3000000,
269 .max_uV = 3000000, 270 .max_uV = 3000000,
270 .apply_uV = 1, 271 .apply_uV = 1,
271 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 272 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
272 .state_mem = { 273 .state_mem = {
273 .disabled = 1, 274 .disabled = 1,
274 }, 275 },
275 }, 276 },
276 .num_consumer_supplies = ARRAY_SIZE(ldo11_consumer), 277 .num_consumer_supplies = ARRAY_SIZE(ldo11_consumer),
277 .consumer_supplies = ldo11_consumer, 278 .consumer_supplies = ldo11_consumer,
278 }; 279 };
279 280
280 static struct regulator_init_data __initdata max8997_ldo14_data = { 281 static struct regulator_init_data __initdata max8997_ldo14_data = {
281 .constraints = { 282 .constraints = {
282 .name = "AVDD18_SWB_1.8V", 283 .name = "AVDD18_SWB_1.8V",
283 .min_uV = 1800000, 284 .min_uV = 1800000,
284 .max_uV = 1800000, 285 .max_uV = 1800000,
285 .apply_uV = 1, 286 .apply_uV = 1,
286 .always_on = 1, 287 .always_on = 1,
287 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 288 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
288 .state_mem = { 289 .state_mem = {
289 .disabled = 1, 290 .disabled = 1,
290 }, 291 },
291 }, 292 },
292 .num_consumer_supplies = ARRAY_SIZE(ldo14_consumer), 293 .num_consumer_supplies = ARRAY_SIZE(ldo14_consumer),
293 .consumer_supplies = ldo14_consumer, 294 .consumer_supplies = ldo14_consumer,
294 }; 295 };
295 296
296 static struct regulator_init_data __initdata max8997_ldo17_data = { 297 static struct regulator_init_data __initdata max8997_ldo17_data = {
297 .constraints = { 298 .constraints = {
298 .name = "VDD_SWB_3.3V", 299 .name = "VDD_SWB_3.3V",
299 .min_uV = 3300000, 300 .min_uV = 3300000,
300 .max_uV = 3300000, 301 .max_uV = 3300000,
301 .apply_uV = 1, 302 .apply_uV = 1,
302 .always_on = 1, 303 .always_on = 1,
303 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 304 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
304 .state_mem = { 305 .state_mem = {
305 .disabled = 1, 306 .disabled = 1,
306 }, 307 },
307 }, 308 },
308 .num_consumer_supplies = ARRAY_SIZE(ldo17_consumer), 309 .num_consumer_supplies = ARRAY_SIZE(ldo17_consumer),
309 .consumer_supplies = ldo17_consumer, 310 .consumer_supplies = ldo17_consumer,
310 }; 311 };
311 312
312 static struct regulator_init_data __initdata max8997_ldo21_data = { 313 static struct regulator_init_data __initdata max8997_ldo21_data = {
313 .constraints = { 314 .constraints = {
314 .name = "VDD_MIF_1.2V", 315 .name = "VDD_MIF_1.2V",
315 .min_uV = 1200000, 316 .min_uV = 1200000,
316 .max_uV = 1200000, 317 .max_uV = 1200000,
317 .apply_uV = 1, 318 .apply_uV = 1,
318 .always_on = 1, 319 .always_on = 1,
319 .state_mem = { 320 .state_mem = {
320 .disabled = 1, 321 .disabled = 1,
321 }, 322 },
322 }, 323 },
323 }; 324 };
324 325
325 static struct regulator_init_data __initdata max8997_buck1_data = { 326 static struct regulator_init_data __initdata max8997_buck1_data = {
326 .constraints = { 327 .constraints = {
327 .name = "VDD_ARM_1.2V", 328 .name = "VDD_ARM_1.2V",
328 .min_uV = 950000, 329 .min_uV = 950000,
329 .max_uV = 1350000, 330 .max_uV = 1350000,
330 .always_on = 1, 331 .always_on = 1,
331 .boot_on = 1, 332 .boot_on = 1,
332 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, 333 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
333 .state_mem = { 334 .state_mem = {
334 .disabled = 1, 335 .disabled = 1,
335 }, 336 },
336 }, 337 },
337 .num_consumer_supplies = ARRAY_SIZE(buck1_consumer), 338 .num_consumer_supplies = ARRAY_SIZE(buck1_consumer),
338 .consumer_supplies = buck1_consumer, 339 .consumer_supplies = buck1_consumer,
339 }; 340 };
340 341
341 static struct regulator_init_data __initdata max8997_buck2_data = { 342 static struct regulator_init_data __initdata max8997_buck2_data = {
342 .constraints = { 343 .constraints = {
343 .name = "VDD_INT_1.1V", 344 .name = "VDD_INT_1.1V",
344 .min_uV = 900000, 345 .min_uV = 900000,
345 .max_uV = 1100000, 346 .max_uV = 1100000,
346 .always_on = 1, 347 .always_on = 1,
347 .boot_on = 1, 348 .boot_on = 1,
348 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, 349 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
349 .state_mem = { 350 .state_mem = {
350 .disabled = 1, 351 .disabled = 1,
351 }, 352 },
352 }, 353 },
353 .num_consumer_supplies = ARRAY_SIZE(buck2_consumer), 354 .num_consumer_supplies = ARRAY_SIZE(buck2_consumer),
354 .consumer_supplies = buck2_consumer, 355 .consumer_supplies = buck2_consumer,
355 }; 356 };
356 357
357 static struct regulator_init_data __initdata max8997_buck3_data = { 358 static struct regulator_init_data __initdata max8997_buck3_data = {
358 .constraints = { 359 .constraints = {
359 .name = "VDD_G3D_1.1V", 360 .name = "VDD_G3D_1.1V",
360 .min_uV = 900000, 361 .min_uV = 900000,
361 .max_uV = 1100000, 362 .max_uV = 1100000,
362 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | 363 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
363 REGULATOR_CHANGE_STATUS, 364 REGULATOR_CHANGE_STATUS,
364 .state_mem = { 365 .state_mem = {
365 .disabled = 1, 366 .disabled = 1,
366 }, 367 },
367 }, 368 },
368 .num_consumer_supplies = ARRAY_SIZE(buck3_consumer), 369 .num_consumer_supplies = ARRAY_SIZE(buck3_consumer),
369 .consumer_supplies = buck3_consumer, 370 .consumer_supplies = buck3_consumer,
370 }; 371 };
371 372
372 static struct regulator_init_data __initdata max8997_buck5_data = { 373 static struct regulator_init_data __initdata max8997_buck5_data = {
373 .constraints = { 374 .constraints = {
374 .name = "VDDQ_M1M2_1.2V", 375 .name = "VDDQ_M1M2_1.2V",
375 .min_uV = 1200000, 376 .min_uV = 1200000,
376 .max_uV = 1200000, 377 .max_uV = 1200000,
377 .apply_uV = 1, 378 .apply_uV = 1,
378 .always_on = 1, 379 .always_on = 1,
379 .state_mem = { 380 .state_mem = {
380 .disabled = 1, 381 .disabled = 1,
381 }, 382 },
382 }, 383 },
383 }; 384 };
384 385
385 static struct regulator_init_data __initdata max8997_buck7_data = { 386 static struct regulator_init_data __initdata max8997_buck7_data = {
386 .constraints = { 387 .constraints = {
387 .name = "VDD_LCD_3.3V", 388 .name = "VDD_LCD_3.3V",
388 .min_uV = 3300000, 389 .min_uV = 3300000,
389 .max_uV = 3300000, 390 .max_uV = 3300000,
390 .boot_on = 1, 391 .boot_on = 1,
391 .apply_uV = 1, 392 .apply_uV = 1,
392 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 393 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
393 .state_mem = { 394 .state_mem = {
394 .disabled = 1 395 .disabled = 1
395 }, 396 },
396 }, 397 },
397 .num_consumer_supplies = ARRAY_SIZE(buck7_consumer), 398 .num_consumer_supplies = ARRAY_SIZE(buck7_consumer),
398 .consumer_supplies = buck7_consumer, 399 .consumer_supplies = buck7_consumer,
399 }; 400 };
400 401
401 static struct max8997_regulator_data __initdata origen_max8997_regulators[] = { 402 static struct max8997_regulator_data __initdata origen_max8997_regulators[] = {
402 { MAX8997_LDO1, &max8997_ldo1_data }, 403 { MAX8997_LDO1, &max8997_ldo1_data },
403 { MAX8997_LDO2, &max8997_ldo2_data }, 404 { MAX8997_LDO2, &max8997_ldo2_data },
404 { MAX8997_LDO3, &max8997_ldo3_data }, 405 { MAX8997_LDO3, &max8997_ldo3_data },
405 { MAX8997_LDO4, &max8997_ldo4_data }, 406 { MAX8997_LDO4, &max8997_ldo4_data },
406 { MAX8997_LDO6, &max8997_ldo6_data }, 407 { MAX8997_LDO6, &max8997_ldo6_data },
407 { MAX8997_LDO7, &max8997_ldo7_data }, 408 { MAX8997_LDO7, &max8997_ldo7_data },
408 { MAX8997_LDO8, &max8997_ldo8_data }, 409 { MAX8997_LDO8, &max8997_ldo8_data },
409 { MAX8997_LDO9, &max8997_ldo9_data }, 410 { MAX8997_LDO9, &max8997_ldo9_data },
410 { MAX8997_LDO10, &max8997_ldo10_data }, 411 { MAX8997_LDO10, &max8997_ldo10_data },
411 { MAX8997_LDO11, &max8997_ldo11_data }, 412 { MAX8997_LDO11, &max8997_ldo11_data },
412 { MAX8997_LDO14, &max8997_ldo14_data }, 413 { MAX8997_LDO14, &max8997_ldo14_data },
413 { MAX8997_LDO17, &max8997_ldo17_data }, 414 { MAX8997_LDO17, &max8997_ldo17_data },
414 { MAX8997_LDO21, &max8997_ldo21_data }, 415 { MAX8997_LDO21, &max8997_ldo21_data },
415 { MAX8997_BUCK1, &max8997_buck1_data }, 416 { MAX8997_BUCK1, &max8997_buck1_data },
416 { MAX8997_BUCK2, &max8997_buck2_data }, 417 { MAX8997_BUCK2, &max8997_buck2_data },
417 { MAX8997_BUCK3, &max8997_buck3_data }, 418 { MAX8997_BUCK3, &max8997_buck3_data },
418 { MAX8997_BUCK5, &max8997_buck5_data }, 419 { MAX8997_BUCK5, &max8997_buck5_data },
419 { MAX8997_BUCK7, &max8997_buck7_data }, 420 { MAX8997_BUCK7, &max8997_buck7_data },
420 }; 421 };
421 422
422 static struct max8997_platform_data __initdata origen_max8997_pdata = { 423 static struct max8997_platform_data __initdata origen_max8997_pdata = {
423 .num_regulators = ARRAY_SIZE(origen_max8997_regulators), 424 .num_regulators = ARRAY_SIZE(origen_max8997_regulators),
424 .regulators = origen_max8997_regulators, 425 .regulators = origen_max8997_regulators,
425 426
426 .wakeup = true, 427 .wakeup = true,
427 .buck1_gpiodvs = false, 428 .buck1_gpiodvs = false,
428 .buck2_gpiodvs = false, 429 .buck2_gpiodvs = false,
429 .buck5_gpiodvs = false, 430 .buck5_gpiodvs = false,
430 431
431 .ignore_gpiodvs_side_effect = true, 432 .ignore_gpiodvs_side_effect = true,
432 .buck125_default_idx = 0x0, 433 .buck125_default_idx = 0x0,
433 434
434 .buck125_gpios[0] = EXYNOS4_GPX0(0), 435 .buck125_gpios[0] = EXYNOS4_GPX0(0),
435 .buck125_gpios[1] = EXYNOS4_GPX0(1), 436 .buck125_gpios[1] = EXYNOS4_GPX0(1),
436 .buck125_gpios[2] = EXYNOS4_GPX0(2), 437 .buck125_gpios[2] = EXYNOS4_GPX0(2),
437 438
438 .buck1_voltage[0] = 1350000, 439 .buck1_voltage[0] = 1350000,
439 .buck1_voltage[1] = 1300000, 440 .buck1_voltage[1] = 1300000,
440 .buck1_voltage[2] = 1250000, 441 .buck1_voltage[2] = 1250000,
441 .buck1_voltage[3] = 1200000, 442 .buck1_voltage[3] = 1200000,
442 .buck1_voltage[4] = 1150000, 443 .buck1_voltage[4] = 1150000,
443 .buck1_voltage[5] = 1100000, 444 .buck1_voltage[5] = 1100000,
444 .buck1_voltage[6] = 1000000, 445 .buck1_voltage[6] = 1000000,
445 .buck1_voltage[7] = 950000, 446 .buck1_voltage[7] = 950000,
446 447
447 .buck2_voltage[0] = 1100000, 448 .buck2_voltage[0] = 1100000,
448 .buck2_voltage[1] = 1100000, 449 .buck2_voltage[1] = 1100000,
449 .buck2_voltage[2] = 1100000, 450 .buck2_voltage[2] = 1100000,
450 .buck2_voltage[3] = 1100000, 451 .buck2_voltage[3] = 1100000,
451 .buck2_voltage[4] = 1000000, 452 .buck2_voltage[4] = 1000000,
452 .buck2_voltage[5] = 1000000, 453 .buck2_voltage[5] = 1000000,
453 .buck2_voltage[6] = 1000000, 454 .buck2_voltage[6] = 1000000,
454 .buck2_voltage[7] = 1000000, 455 .buck2_voltage[7] = 1000000,
455 456
456 .buck5_voltage[0] = 1200000, 457 .buck5_voltage[0] = 1200000,
457 .buck5_voltage[1] = 1200000, 458 .buck5_voltage[1] = 1200000,
458 .buck5_voltage[2] = 1200000, 459 .buck5_voltage[2] = 1200000,
459 .buck5_voltage[3] = 1200000, 460 .buck5_voltage[3] = 1200000,
460 .buck5_voltage[4] = 1200000, 461 .buck5_voltage[4] = 1200000,
461 .buck5_voltage[5] = 1200000, 462 .buck5_voltage[5] = 1200000,
462 .buck5_voltage[6] = 1200000, 463 .buck5_voltage[6] = 1200000,
463 .buck5_voltage[7] = 1200000, 464 .buck5_voltage[7] = 1200000,
464 }; 465 };
465 466
466 /* I2C0 */ 467 /* I2C0 */
467 static struct i2c_board_info i2c0_devs[] __initdata = { 468 static struct i2c_board_info i2c0_devs[] __initdata = {
468 { 469 {
469 I2C_BOARD_INFO("max8997", (0xCC >> 1)), 470 I2C_BOARD_INFO("max8997", (0xCC >> 1)),
470 .platform_data = &origen_max8997_pdata, 471 .platform_data = &origen_max8997_pdata,
471 .irq = IRQ_EINT(4), 472 .irq = IRQ_EINT(4),
472 }, 473 },
473 }; 474 };
474 475
475 static struct s3c_sdhci_platdata origen_hsmmc0_pdata __initdata = { 476 static struct s3c_sdhci_platdata origen_hsmmc0_pdata __initdata = {
476 .cd_type = S3C_SDHCI_CD_INTERNAL, 477 .cd_type = S3C_SDHCI_CD_INTERNAL,
477 }; 478 };
478 479
479 static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = { 480 static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = {
480 .cd_type = S3C_SDHCI_CD_INTERNAL, 481 .cd_type = S3C_SDHCI_CD_INTERNAL,
481 }; 482 };
482 483
483 /* USB EHCI */ 484 /* USB EHCI */
484 static struct s5p_ehci_platdata origen_ehci_pdata; 485 static struct s5p_ehci_platdata origen_ehci_pdata;
485 486
486 static void __init origen_ehci_init(void) 487 static void __init origen_ehci_init(void)
487 { 488 {
488 struct s5p_ehci_platdata *pdata = &origen_ehci_pdata; 489 struct s5p_ehci_platdata *pdata = &origen_ehci_pdata;
489 490
490 s5p_ehci_set_platdata(pdata); 491 s5p_ehci_set_platdata(pdata);
491 } 492 }
492 493
493 /* USB OHCI */ 494 /* USB OHCI */
494 static struct exynos4_ohci_platdata origen_ohci_pdata; 495 static struct exynos4_ohci_platdata origen_ohci_pdata;
495 496
496 static void __init origen_ohci_init(void) 497 static void __init origen_ohci_init(void)
497 { 498 {
498 struct exynos4_ohci_platdata *pdata = &origen_ohci_pdata; 499 struct exynos4_ohci_platdata *pdata = &origen_ohci_pdata;
499 500
500 exynos4_ohci_set_platdata(pdata); 501 exynos4_ohci_set_platdata(pdata);
501 } 502 }
502 503
503 /* USB OTG */ 504 /* USB OTG */
504 static struct s3c_hsotg_plat origen_hsotg_pdata; 505 static struct s3c_hsotg_plat origen_hsotg_pdata;
505 506
506 static struct gpio_led origen_gpio_leds[] = { 507 static struct gpio_led origen_gpio_leds[] = {
507 { 508 {
508 .name = "origen::status1", 509 .name = "origen::status1",
509 .default_trigger = "heartbeat", 510 .default_trigger = "heartbeat",
510 .gpio = EXYNOS4_GPX1(3), 511 .gpio = EXYNOS4_GPX1(3),
511 .active_low = 1, 512 .active_low = 1,
512 }, 513 },
513 { 514 {
514 .name = "origen::status2", 515 .name = "origen::status2",
515 .default_trigger = "mmc0", 516 .default_trigger = "mmc0",
516 .gpio = EXYNOS4_GPX1(4), 517 .gpio = EXYNOS4_GPX1(4),
517 .active_low = 1, 518 .active_low = 1,
518 }, 519 },
519 }; 520 };
520 521
521 static struct gpio_led_platform_data origen_gpio_led_info = { 522 static struct gpio_led_platform_data origen_gpio_led_info = {
522 .leds = origen_gpio_leds, 523 .leds = origen_gpio_leds,
523 .num_leds = ARRAY_SIZE(origen_gpio_leds), 524 .num_leds = ARRAY_SIZE(origen_gpio_leds),
524 }; 525 };
525 526
526 static struct platform_device origen_leds_gpio = { 527 static struct platform_device origen_leds_gpio = {
527 .name = "leds-gpio", 528 .name = "leds-gpio",
528 .id = -1, 529 .id = -1,
529 .dev = { 530 .dev = {
530 .platform_data = &origen_gpio_led_info, 531 .platform_data = &origen_gpio_led_info,
531 }, 532 },
532 }; 533 };
533 534
534 static struct gpio_keys_button origen_gpio_keys_table[] = { 535 static struct gpio_keys_button origen_gpio_keys_table[] = {
535 { 536 {
536 .code = KEY_MENU, 537 .code = KEY_MENU,
537 .gpio = EXYNOS4_GPX1(5), 538 .gpio = EXYNOS4_GPX1(5),
538 .desc = "gpio-keys: KEY_MENU", 539 .desc = "gpio-keys: KEY_MENU",
539 .type = EV_KEY, 540 .type = EV_KEY,
540 .active_low = 1, 541 .active_low = 1,
541 .wakeup = 1, 542 .wakeup = 1,
542 .debounce_interval = 1, 543 .debounce_interval = 1,
543 }, { 544 }, {
544 .code = KEY_HOME, 545 .code = KEY_HOME,
545 .gpio = EXYNOS4_GPX1(6), 546 .gpio = EXYNOS4_GPX1(6),
546 .desc = "gpio-keys: KEY_HOME", 547 .desc = "gpio-keys: KEY_HOME",
547 .type = EV_KEY, 548 .type = EV_KEY,
548 .active_low = 1, 549 .active_low = 1,
549 .wakeup = 1, 550 .wakeup = 1,
550 .debounce_interval = 1, 551 .debounce_interval = 1,
551 }, { 552 }, {
552 .code = KEY_BACK, 553 .code = KEY_BACK,
553 .gpio = EXYNOS4_GPX1(7), 554 .gpio = EXYNOS4_GPX1(7),
554 .desc = "gpio-keys: KEY_BACK", 555 .desc = "gpio-keys: KEY_BACK",
555 .type = EV_KEY, 556 .type = EV_KEY,
556 .active_low = 1, 557 .active_low = 1,
557 .wakeup = 1, 558 .wakeup = 1,
558 .debounce_interval = 1, 559 .debounce_interval = 1,
559 }, { 560 }, {
560 .code = KEY_UP, 561 .code = KEY_UP,
561 .gpio = EXYNOS4_GPX2(0), 562 .gpio = EXYNOS4_GPX2(0),
562 .desc = "gpio-keys: KEY_UP", 563 .desc = "gpio-keys: KEY_UP",
563 .type = EV_KEY, 564 .type = EV_KEY,
564 .active_low = 1, 565 .active_low = 1,
565 .wakeup = 1, 566 .wakeup = 1,
566 .debounce_interval = 1, 567 .debounce_interval = 1,
567 }, { 568 }, {
568 .code = KEY_DOWN, 569 .code = KEY_DOWN,
569 .gpio = EXYNOS4_GPX2(1), 570 .gpio = EXYNOS4_GPX2(1),
570 .desc = "gpio-keys: KEY_DOWN", 571 .desc = "gpio-keys: KEY_DOWN",
571 .type = EV_KEY, 572 .type = EV_KEY,
572 .active_low = 1, 573 .active_low = 1,
573 .wakeup = 1, 574 .wakeup = 1,
574 .debounce_interval = 1, 575 .debounce_interval = 1,
575 }, 576 },
576 }; 577 };
577 578
578 static struct gpio_keys_platform_data origen_gpio_keys_data = { 579 static struct gpio_keys_platform_data origen_gpio_keys_data = {
579 .buttons = origen_gpio_keys_table, 580 .buttons = origen_gpio_keys_table,
580 .nbuttons = ARRAY_SIZE(origen_gpio_keys_table), 581 .nbuttons = ARRAY_SIZE(origen_gpio_keys_table),
581 }; 582 };
582 583
583 static struct platform_device origen_device_gpiokeys = { 584 static struct platform_device origen_device_gpiokeys = {
584 .name = "gpio-keys", 585 .name = "gpio-keys",
585 .dev = { 586 .dev = {
586 .platform_data = &origen_gpio_keys_data, 587 .platform_data = &origen_gpio_keys_data,
587 }, 588 },
588 }; 589 };
589 590
590 static void lcd_hv070wsa_set_power(struct plat_lcd_data *pd, unsigned int power) 591 static void lcd_hv070wsa_set_power(struct plat_lcd_data *pd, unsigned int power)
591 { 592 {
592 int ret; 593 int ret;
593 594
594 if (power) 595 if (power)
595 ret = gpio_request_one(EXYNOS4_GPE3(4), 596 ret = gpio_request_one(EXYNOS4_GPE3(4),
596 GPIOF_OUT_INIT_HIGH, "GPE3_4"); 597 GPIOF_OUT_INIT_HIGH, "GPE3_4");
597 else 598 else
598 ret = gpio_request_one(EXYNOS4_GPE3(4), 599 ret = gpio_request_one(EXYNOS4_GPE3(4),
599 GPIOF_OUT_INIT_LOW, "GPE3_4"); 600 GPIOF_OUT_INIT_LOW, "GPE3_4");
600 601
601 gpio_free(EXYNOS4_GPE3(4)); 602 gpio_free(EXYNOS4_GPE3(4));
602 603
603 if (ret) 604 if (ret)
604 pr_err("failed to request gpio for LCD power: %d\n", ret); 605 pr_err("failed to request gpio for LCD power: %d\n", ret);
605 } 606 }
606 607
607 static struct plat_lcd_data origen_lcd_hv070wsa_data = { 608 static struct plat_lcd_data origen_lcd_hv070wsa_data = {
608 .set_power = lcd_hv070wsa_set_power, 609 .set_power = lcd_hv070wsa_set_power,
609 }; 610 };
610 611
611 static struct platform_device origen_lcd_hv070wsa = { 612 static struct platform_device origen_lcd_hv070wsa = {
612 .name = "platform-lcd", 613 .name = "platform-lcd",
613 .dev.parent = &s5p_device_fimd0.dev, 614 .dev.parent = &s5p_device_fimd0.dev,
614 .dev.platform_data = &origen_lcd_hv070wsa_data, 615 .dev.platform_data = &origen_lcd_hv070wsa_data,
615 }; 616 };
616 617
618 static struct pwm_lookup origen_pwm_lookup[] = {
619 PWM_LOOKUP("s3c24xx-pwm.0", 0, "pwm-backlight.0", NULL),
620 };
621
617 #ifdef CONFIG_DRM_EXYNOS 622 #ifdef CONFIG_DRM_EXYNOS
618 static struct exynos_drm_fimd_pdata drm_fimd_pdata = { 623 static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
619 .panel = { 624 .panel = {
620 .timing = { 625 .timing = {
621 .left_margin = 64, 626 .left_margin = 64,
622 .right_margin = 16, 627 .right_margin = 16,
623 .upper_margin = 64, 628 .upper_margin = 64,
624 .lower_margin = 16, 629 .lower_margin = 16,
625 .hsync_len = 48, 630 .hsync_len = 48,
626 .vsync_len = 3, 631 .vsync_len = 3,
627 .xres = 1024, 632 .xres = 1024,
628 .yres = 600, 633 .yres = 600,
629 }, 634 },
630 }, 635 },
631 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, 636 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
632 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC | 637 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
633 VIDCON1_INV_VCLK, 638 VIDCON1_INV_VCLK,
634 .default_win = 0, 639 .default_win = 0,
635 .bpp = 32, 640 .bpp = 32,
636 }; 641 };
637 #else 642 #else
638 static struct s3c_fb_pd_win origen_fb_win0 = { 643 static struct s3c_fb_pd_win origen_fb_win0 = {
639 .xres = 1024, 644 .xres = 1024,
640 .yres = 600, 645 .yres = 600,
641 .max_bpp = 32, 646 .max_bpp = 32,
642 .default_bpp = 24, 647 .default_bpp = 24,
643 .virtual_x = 1024, 648 .virtual_x = 1024,
644 .virtual_y = 2 * 600, 649 .virtual_y = 2 * 600,
645 }; 650 };
646 651
647 static struct fb_videomode origen_lcd_timing = { 652 static struct fb_videomode origen_lcd_timing = {
648 .left_margin = 64, 653 .left_margin = 64,
649 .right_margin = 16, 654 .right_margin = 16,
650 .upper_margin = 64, 655 .upper_margin = 64,
651 .lower_margin = 16, 656 .lower_margin = 16,
652 .hsync_len = 48, 657 .hsync_len = 48,
653 .vsync_len = 3, 658 .vsync_len = 3,
654 .xres = 1024, 659 .xres = 1024,
655 .yres = 600, 660 .yres = 600,
656 }; 661 };
657 662
658 static struct s3c_fb_platdata origen_lcd_pdata __initdata = { 663 static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
659 .win[0] = &origen_fb_win0, 664 .win[0] = &origen_fb_win0,
660 .vtiming = &origen_lcd_timing, 665 .vtiming = &origen_lcd_timing,
661 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, 666 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
662 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC | 667 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
663 VIDCON1_INV_VCLK, 668 VIDCON1_INV_VCLK,
664 .setup_gpio = exynos4_fimd0_gpio_setup_24bpp, 669 .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
665 }; 670 };
666 #endif 671 #endif
667 672
668 /* Bluetooth rfkill gpio platform data */ 673 /* Bluetooth rfkill gpio platform data */
669 static struct rfkill_gpio_platform_data origen_bt_pdata = { 674 static struct rfkill_gpio_platform_data origen_bt_pdata = {
670 .reset_gpio = EXYNOS4_GPX2(2), 675 .reset_gpio = EXYNOS4_GPX2(2),
671 .shutdown_gpio = -1, 676 .shutdown_gpio = -1,
672 .type = RFKILL_TYPE_BLUETOOTH, 677 .type = RFKILL_TYPE_BLUETOOTH,
673 .name = "origen-bt", 678 .name = "origen-bt",
674 }; 679 };
675 680
676 /* Bluetooth Platform device */ 681 /* Bluetooth Platform device */
677 static struct platform_device origen_device_bluetooth = { 682 static struct platform_device origen_device_bluetooth = {
678 .name = "rfkill_gpio", 683 .name = "rfkill_gpio",
679 .id = -1, 684 .id = -1,
680 .dev = { 685 .dev = {
681 .platform_data = &origen_bt_pdata, 686 .platform_data = &origen_bt_pdata,
682 }, 687 },
683 }; 688 };
684 689
685 static struct platform_device *origen_devices[] __initdata = { 690 static struct platform_device *origen_devices[] __initdata = {
686 &s3c_device_hsmmc2, 691 &s3c_device_hsmmc2,
687 &s3c_device_hsmmc0, 692 &s3c_device_hsmmc0,
688 &s3c_device_i2c0, 693 &s3c_device_i2c0,
689 &s3c_device_rtc, 694 &s3c_device_rtc,
690 &s3c_device_usb_hsotg, 695 &s3c_device_usb_hsotg,
691 &s3c_device_wdt, 696 &s3c_device_wdt,
692 &s5p_device_ehci, 697 &s5p_device_ehci,
693 &s5p_device_fimc0, 698 &s5p_device_fimc0,
694 &s5p_device_fimc1, 699 &s5p_device_fimc1,
695 &s5p_device_fimc2, 700 &s5p_device_fimc2,
696 &s5p_device_fimc3, 701 &s5p_device_fimc3,
697 &s5p_device_fimc_md, 702 &s5p_device_fimc_md,
698 &s5p_device_fimd0, 703 &s5p_device_fimd0,
699 &s5p_device_g2d, 704 &s5p_device_g2d,
700 &s5p_device_hdmi, 705 &s5p_device_hdmi,
701 &s5p_device_i2c_hdmiphy, 706 &s5p_device_i2c_hdmiphy,
702 &s5p_device_jpeg, 707 &s5p_device_jpeg,
703 &s5p_device_mfc, 708 &s5p_device_mfc,
704 &s5p_device_mfc_l, 709 &s5p_device_mfc_l,
705 &s5p_device_mfc_r, 710 &s5p_device_mfc_r,
706 &s5p_device_mixer, 711 &s5p_device_mixer,
707 #ifdef CONFIG_DRM_EXYNOS 712 #ifdef CONFIG_DRM_EXYNOS
708 &exynos_device_drm, 713 &exynos_device_drm,
709 #endif 714 #endif
710 &exynos4_device_ohci, 715 &exynos4_device_ohci,
711 &origen_device_gpiokeys, 716 &origen_device_gpiokeys,
712 &origen_lcd_hv070wsa, 717 &origen_lcd_hv070wsa,
713 &origen_leds_gpio, 718 &origen_leds_gpio,
714 &origen_device_bluetooth, 719 &origen_device_bluetooth,
715 }; 720 };
716 721
717 /* LCD Backlight data */ 722 /* LCD Backlight data */
718 static struct samsung_bl_gpio_info origen_bl_gpio_info = { 723 static struct samsung_bl_gpio_info origen_bl_gpio_info = {
719 .no = EXYNOS4_GPD0(0), 724 .no = EXYNOS4_GPD0(0),
720 .func = S3C_GPIO_SFN(2), 725 .func = S3C_GPIO_SFN(2),
721 }; 726 };
722 727
723 static struct platform_pwm_backlight_data origen_bl_data = { 728 static struct platform_pwm_backlight_data origen_bl_data = {
724 .pwm_id = 0, 729 .pwm_id = 0,
725 .pwm_period_ns = 1000, 730 .pwm_period_ns = 1000,
726 }; 731 };
727 732
728 static void __init origen_bt_setup(void) 733 static void __init origen_bt_setup(void)
729 { 734 {
730 gpio_request(EXYNOS4_GPA0(0), "GPIO BT_UART"); 735 gpio_request(EXYNOS4_GPA0(0), "GPIO BT_UART");
731 /* 4 UART Pins configuration */ 736 /* 4 UART Pins configuration */
732 s3c_gpio_cfgrange_nopull(EXYNOS4_GPA0(0), 4, S3C_GPIO_SFN(2)); 737 s3c_gpio_cfgrange_nopull(EXYNOS4_GPA0(0), 4, S3C_GPIO_SFN(2));
733 /* Setup BT Reset, this gpio will be requesed by rfkill-gpio */ 738 /* Setup BT Reset, this gpio will be requesed by rfkill-gpio */
734 s3c_gpio_cfgpin(EXYNOS4_GPX2(2), S3C_GPIO_OUTPUT); 739 s3c_gpio_cfgpin(EXYNOS4_GPX2(2), S3C_GPIO_OUTPUT);
735 s3c_gpio_setpull(EXYNOS4_GPX2(2), S3C_GPIO_PULL_NONE); 740 s3c_gpio_setpull(EXYNOS4_GPX2(2), S3C_GPIO_PULL_NONE);
736 } 741 }
737 742
738 /* I2C module and id for HDMIPHY */ 743 /* I2C module and id for HDMIPHY */
739 static struct i2c_board_info hdmiphy_info = { 744 static struct i2c_board_info hdmiphy_info = {
740 I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38), 745 I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38),
741 }; 746 };
742 747
743 static void s5p_tv_setup(void) 748 static void s5p_tv_setup(void)
744 { 749 {
745 /* Direct HPD to HDMI chip */ 750 /* Direct HPD to HDMI chip */
746 gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"); 751 gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
747 s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3)); 752 s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
748 s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE); 753 s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
749 } 754 }
750 755
751 static void __init origen_map_io(void) 756 static void __init origen_map_io(void)
752 { 757 {
753 exynos_init_io(NULL, 0); 758 exynos_init_io(NULL, 0);
754 s3c24xx_init_clocks(clk_xusbxti.rate); 759 s3c24xx_init_clocks(clk_xusbxti.rate);
755 s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs)); 760 s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
756 } 761 }
757 762
758 static void __init origen_power_init(void) 763 static void __init origen_power_init(void)
759 { 764 {
760 gpio_request(EXYNOS4_GPX0(4), "PMIC_IRQ"); 765 gpio_request(EXYNOS4_GPX0(4), "PMIC_IRQ");
761 s3c_gpio_cfgpin(EXYNOS4_GPX0(4), S3C_GPIO_SFN(0xf)); 766 s3c_gpio_cfgpin(EXYNOS4_GPX0(4), S3C_GPIO_SFN(0xf));
762 s3c_gpio_setpull(EXYNOS4_GPX0(4), S3C_GPIO_PULL_NONE); 767 s3c_gpio_setpull(EXYNOS4_GPX0(4), S3C_GPIO_PULL_NONE);
763 } 768 }
764 769
765 static void __init origen_reserve(void) 770 static void __init origen_reserve(void)
766 { 771 {
767 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20); 772 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
768 } 773 }
769 774
770 static void __init origen_machine_init(void) 775 static void __init origen_machine_init(void)
771 { 776 {
772 origen_power_init(); 777 origen_power_init();
773 778
774 s3c_i2c0_set_platdata(NULL); 779 s3c_i2c0_set_platdata(NULL);
775 i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs)); 780 i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
776 781
777 /* 782 /*
778 * Since sdhci instance 2 can contain a bootable media, 783 * Since sdhci instance 2 can contain a bootable media,
779 * sdhci instance 0 is registered after instance 2. 784 * sdhci instance 0 is registered after instance 2.
780 */ 785 */
781 s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata); 786 s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata);
782 s3c_sdhci0_set_platdata(&origen_hsmmc0_pdata); 787 s3c_sdhci0_set_platdata(&origen_hsmmc0_pdata);
783 788
784 origen_ehci_init(); 789 origen_ehci_init();
785 origen_ohci_init(); 790 origen_ohci_init();
786 s3c_hsotg_set_platdata(&origen_hsotg_pdata); 791 s3c_hsotg_set_platdata(&origen_hsotg_pdata);
787 792
788 s5p_tv_setup(); 793 s5p_tv_setup();
789 s5p_i2c_hdmiphy_set_platdata(NULL); 794 s5p_i2c_hdmiphy_set_platdata(NULL);
790 s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0); 795 s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0);
791 796
792 #ifdef CONFIG_DRM_EXYNOS 797 #ifdef CONFIG_DRM_EXYNOS
793 s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata; 798 s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
794 exynos4_fimd0_gpio_setup_24bpp(); 799 exynos4_fimd0_gpio_setup_24bpp();
795 #else 800 #else
796 s5p_fimd0_set_platdata(&origen_lcd_pdata); 801 s5p_fimd0_set_platdata(&origen_lcd_pdata);
797 #endif 802 #endif
798 803
799 platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices)); 804 platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices));
800 805
806 pwm_add_table(origen_pwm_lookup, ARRAY_SIZE(origen_pwm_lookup));
801 samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data); 807 samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data);
802 808
803 origen_bt_setup(); 809 origen_bt_setup();
804 } 810 }
805 811
806 MACHINE_START(ORIGEN, "ORIGEN") 812 MACHINE_START(ORIGEN, "ORIGEN")
807 /* Maintainer: JeongHyeon Kim <jhkim@insignal.co.kr> */ 813 /* Maintainer: JeongHyeon Kim <jhkim@insignal.co.kr> */
808 .atag_offset = 0x100, 814 .atag_offset = 0x100,
809 .init_irq = exynos4_init_irq, 815 .init_irq = exynos4_init_irq,
810 .map_io = origen_map_io, 816 .map_io = origen_map_io,
811 .handle_irq = gic_handle_irq, 817 .handle_irq = gic_handle_irq,
812 .init_machine = origen_machine_init, 818 .init_machine = origen_machine_init,
813 .init_late = exynos_init_late, 819 .init_late = exynos_init_late,
814 .timer = &exynos4_timer, 820 .timer = &exynos4_timer,
815 .reserve = &origen_reserve, 821 .reserve = &origen_reserve,
816 .restart = exynos4_restart, 822 .restart = exynos4_restart,
817 MACHINE_END 823 MACHINE_END
818 824
arch/arm/mach-exynos/mach-smdk4x12.c
Diff comments   View file @ 95360fd
1 /* 1 /*
2 * linux/arch/arm/mach-exynos4/mach-smdk4x12.c 2 * linux/arch/arm/mach-exynos4/mach-smdk4x12.c
3 * 3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com 5 * http://www.samsung.com
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12 #include <linux/gpio.h> 12 #include <linux/gpio.h>
13 #include <linux/i2c.h> 13 #include <linux/i2c.h>
14 #include <linux/input.h> 14 #include <linux/input.h>
15 #include <linux/io.h> 15 #include <linux/io.h>
16 #include <linux/lcd.h> 16 #include <linux/lcd.h>
17 #include <linux/mfd/max8997.h> 17 #include <linux/mfd/max8997.h>
18 #include <linux/mmc/host.h> 18 #include <linux/mmc/host.h>
19 #include <linux/platform_device.h> 19 #include <linux/platform_device.h>
20 #include <linux/pwm.h>
20 #include <linux/pwm_backlight.h> 21 #include <linux/pwm_backlight.h>
21 #include <linux/regulator/machine.h> 22 #include <linux/regulator/machine.h>
22 #include <linux/serial_core.h> 23 #include <linux/serial_core.h>
23 #include <linux/platform_data/s3c-hsotg.h> 24 #include <linux/platform_data/s3c-hsotg.h>
24 25
25 #include <asm/mach/arch.h> 26 #include <asm/mach/arch.h>
26 #include <asm/hardware/gic.h> 27 #include <asm/hardware/gic.h>
27 #include <asm/mach-types.h> 28 #include <asm/mach-types.h>
28 29
29 #include <plat/backlight.h> 30 #include <plat/backlight.h>
30 #include <plat/clock.h> 31 #include <plat/clock.h>
31 #include <plat/cpu.h> 32 #include <plat/cpu.h>
32 #include <plat/devs.h> 33 #include <plat/devs.h>
33 #include <plat/fb.h> 34 #include <plat/fb.h>
34 #include <plat/gpio-cfg.h> 35 #include <plat/gpio-cfg.h>
35 #include <plat/iic.h> 36 #include <plat/iic.h>
36 #include <plat/keypad.h> 37 #include <plat/keypad.h>
37 #include <plat/mfc.h> 38 #include <plat/mfc.h>
38 #include <plat/regs-fb.h> 39 #include <plat/regs-fb.h>
39 #include <plat/regs-serial.h> 40 #include <plat/regs-serial.h>
40 #include <plat/sdhci.h> 41 #include <plat/sdhci.h>
41 42
42 #include <mach/map.h> 43 #include <mach/map.h>
43 44
44 #include <drm/exynos_drm.h> 45 #include <drm/exynos_drm.h>
45 #include "common.h" 46 #include "common.h"
46 47
47 /* Following are default values for UCON, ULCON and UFCON UART registers */ 48 /* Following are default values for UCON, ULCON and UFCON UART registers */
48 #define SMDK4X12_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 49 #define SMDK4X12_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
49 S3C2410_UCON_RXILEVEL | \ 50 S3C2410_UCON_RXILEVEL | \
50 S3C2410_UCON_TXIRQMODE | \ 51 S3C2410_UCON_TXIRQMODE | \
51 S3C2410_UCON_RXIRQMODE | \ 52 S3C2410_UCON_RXIRQMODE | \
52 S3C2410_UCON_RXFIFO_TOI | \ 53 S3C2410_UCON_RXFIFO_TOI | \
53 S3C2443_UCON_RXERR_IRQEN) 54 S3C2443_UCON_RXERR_IRQEN)
54 55
55 #define SMDK4X12_ULCON_DEFAULT S3C2410_LCON_CS8 56 #define SMDK4X12_ULCON_DEFAULT S3C2410_LCON_CS8
56 57
57 #define SMDK4X12_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ 58 #define SMDK4X12_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
58 S5PV210_UFCON_TXTRIG4 | \ 59 S5PV210_UFCON_TXTRIG4 | \
59 S5PV210_UFCON_RXTRIG4) 60 S5PV210_UFCON_RXTRIG4)
60 61
61 static struct s3c2410_uartcfg smdk4x12_uartcfgs[] __initdata = { 62 static struct s3c2410_uartcfg smdk4x12_uartcfgs[] __initdata = {
62 [0] = { 63 [0] = {
63 .hwport = 0, 64 .hwport = 0,
64 .flags = 0, 65 .flags = 0,
65 .ucon = SMDK4X12_UCON_DEFAULT, 66 .ucon = SMDK4X12_UCON_DEFAULT,
66 .ulcon = SMDK4X12_ULCON_DEFAULT, 67 .ulcon = SMDK4X12_ULCON_DEFAULT,
67 .ufcon = SMDK4X12_UFCON_DEFAULT, 68 .ufcon = SMDK4X12_UFCON_DEFAULT,
68 }, 69 },
69 [1] = { 70 [1] = {
70 .hwport = 1, 71 .hwport = 1,
71 .flags = 0, 72 .flags = 0,
72 .ucon = SMDK4X12_UCON_DEFAULT, 73 .ucon = SMDK4X12_UCON_DEFAULT,
73 .ulcon = SMDK4X12_ULCON_DEFAULT, 74 .ulcon = SMDK4X12_ULCON_DEFAULT,
74 .ufcon = SMDK4X12_UFCON_DEFAULT, 75 .ufcon = SMDK4X12_UFCON_DEFAULT,
75 }, 76 },
76 [2] = { 77 [2] = {
77 .hwport = 2, 78 .hwport = 2,
78 .flags = 0, 79 .flags = 0,
79 .ucon = SMDK4X12_UCON_DEFAULT, 80 .ucon = SMDK4X12_UCON_DEFAULT,
80 .ulcon = SMDK4X12_ULCON_DEFAULT, 81 .ulcon = SMDK4X12_ULCON_DEFAULT,
81 .ufcon = SMDK4X12_UFCON_DEFAULT, 82 .ufcon = SMDK4X12_UFCON_DEFAULT,
82 }, 83 },
83 [3] = { 84 [3] = {
84 .hwport = 3, 85 .hwport = 3,
85 .flags = 0, 86 .flags = 0,
86 .ucon = SMDK4X12_UCON_DEFAULT, 87 .ucon = SMDK4X12_UCON_DEFAULT,
87 .ulcon = SMDK4X12_ULCON_DEFAULT, 88 .ulcon = SMDK4X12_ULCON_DEFAULT,
88 .ufcon = SMDK4X12_UFCON_DEFAULT, 89 .ufcon = SMDK4X12_UFCON_DEFAULT,
89 }, 90 },
90 }; 91 };
91 92
92 static struct s3c_sdhci_platdata smdk4x12_hsmmc2_pdata __initdata = { 93 static struct s3c_sdhci_platdata smdk4x12_hsmmc2_pdata __initdata = {
93 .cd_type = S3C_SDHCI_CD_INTERNAL, 94 .cd_type = S3C_SDHCI_CD_INTERNAL,
94 #ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT 95 #ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
95 .max_width = 8, 96 .max_width = 8,
96 .host_caps = MMC_CAP_8_BIT_DATA, 97 .host_caps = MMC_CAP_8_BIT_DATA,
97 #endif 98 #endif
98 }; 99 };
99 100
100 static struct s3c_sdhci_platdata smdk4x12_hsmmc3_pdata __initdata = { 101 static struct s3c_sdhci_platdata smdk4x12_hsmmc3_pdata __initdata = {
101 .cd_type = S3C_SDHCI_CD_INTERNAL, 102 .cd_type = S3C_SDHCI_CD_INTERNAL,
102 }; 103 };
103 104
104 static struct regulator_consumer_supply max8997_buck1 = 105 static struct regulator_consumer_supply max8997_buck1 =
105 REGULATOR_SUPPLY("vdd_arm", NULL); 106 REGULATOR_SUPPLY("vdd_arm", NULL);
106 107
107 static struct regulator_consumer_supply max8997_buck2 = 108 static struct regulator_consumer_supply max8997_buck2 =
108 REGULATOR_SUPPLY("vdd_int", NULL); 109 REGULATOR_SUPPLY("vdd_int", NULL);
109 110
110 static struct regulator_consumer_supply max8997_buck3 = 111 static struct regulator_consumer_supply max8997_buck3 =
111 REGULATOR_SUPPLY("vdd_g3d", NULL); 112 REGULATOR_SUPPLY("vdd_g3d", NULL);
112 113
113 static struct regulator_init_data max8997_buck1_data = { 114 static struct regulator_init_data max8997_buck1_data = {
114 .constraints = { 115 .constraints = {
115 .name = "VDD_ARM_SMDK4X12", 116 .name = "VDD_ARM_SMDK4X12",
116 .min_uV = 925000, 117 .min_uV = 925000,
117 .max_uV = 1350000, 118 .max_uV = 1350000,
118 .always_on = 1, 119 .always_on = 1,
119 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, 120 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
120 .state_mem = { 121 .state_mem = {
121 .disabled = 1, 122 .disabled = 1,
122 }, 123 },
123 }, 124 },
124 .num_consumer_supplies = 1, 125 .num_consumer_supplies = 1,
125 .consumer_supplies = &max8997_buck1, 126 .consumer_supplies = &max8997_buck1,
126 }; 127 };
127 128
128 static struct regulator_init_data max8997_buck2_data = { 129 static struct regulator_init_data max8997_buck2_data = {
129 .constraints = { 130 .constraints = {
130 .name = "VDD_INT_SMDK4X12", 131 .name = "VDD_INT_SMDK4X12",
131 .min_uV = 950000, 132 .min_uV = 950000,
132 .max_uV = 1150000, 133 .max_uV = 1150000,
133 .always_on = 1, 134 .always_on = 1,
134 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, 135 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
135 .state_mem = { 136 .state_mem = {
136 .disabled = 1, 137 .disabled = 1,
137 }, 138 },
138 }, 139 },
139 .num_consumer_supplies = 1, 140 .num_consumer_supplies = 1,
140 .consumer_supplies = &max8997_buck2, 141 .consumer_supplies = &max8997_buck2,
141 }; 142 };
142 143
143 static struct regulator_init_data max8997_buck3_data = { 144 static struct regulator_init_data max8997_buck3_data = {
144 .constraints = { 145 .constraints = {
145 .name = "VDD_G3D_SMDK4X12", 146 .name = "VDD_G3D_SMDK4X12",
146 .min_uV = 950000, 147 .min_uV = 950000,
147 .max_uV = 1150000, 148 .max_uV = 1150000,
148 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | 149 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
149 REGULATOR_CHANGE_STATUS, 150 REGULATOR_CHANGE_STATUS,
150 .state_mem = { 151 .state_mem = {
151 .disabled = 1, 152 .disabled = 1,
152 }, 153 },
153 }, 154 },
154 .num_consumer_supplies = 1, 155 .num_consumer_supplies = 1,
155 .consumer_supplies = &max8997_buck3, 156 .consumer_supplies = &max8997_buck3,
156 }; 157 };
157 158
158 static struct max8997_regulator_data smdk4x12_max8997_regulators[] = { 159 static struct max8997_regulator_data smdk4x12_max8997_regulators[] = {
159 { MAX8997_BUCK1, &max8997_buck1_data }, 160 { MAX8997_BUCK1, &max8997_buck1_data },
160 { MAX8997_BUCK2, &max8997_buck2_data }, 161 { MAX8997_BUCK2, &max8997_buck2_data },
161 { MAX8997_BUCK3, &max8997_buck3_data }, 162 { MAX8997_BUCK3, &max8997_buck3_data },
162 }; 163 };
163 164
164 static struct max8997_platform_data smdk4x12_max8997_pdata = { 165 static struct max8997_platform_data smdk4x12_max8997_pdata = {
165 .num_regulators = ARRAY_SIZE(smdk4x12_max8997_regulators), 166 .num_regulators = ARRAY_SIZE(smdk4x12_max8997_regulators),
166 .regulators = smdk4x12_max8997_regulators, 167 .regulators = smdk4x12_max8997_regulators,
167 168
168 .buck1_voltage[0] = 1100000, /* 1.1V */ 169 .buck1_voltage[0] = 1100000, /* 1.1V */
169 .buck1_voltage[1] = 1100000, /* 1.1V */ 170 .buck1_voltage[1] = 1100000, /* 1.1V */
170 .buck1_voltage[2] = 1100000, /* 1.1V */ 171 .buck1_voltage[2] = 1100000, /* 1.1V */
171 .buck1_voltage[3] = 1100000, /* 1.1V */ 172 .buck1_voltage[3] = 1100000, /* 1.1V */
172 .buck1_voltage[4] = 1100000, /* 1.1V */ 173 .buck1_voltage[4] = 1100000, /* 1.1V */
173 .buck1_voltage[5] = 1100000, /* 1.1V */ 174 .buck1_voltage[5] = 1100000, /* 1.1V */
174 .buck1_voltage[6] = 1000000, /* 1.0V */ 175 .buck1_voltage[6] = 1000000, /* 1.0V */
175 .buck1_voltage[7] = 950000, /* 0.95V */ 176 .buck1_voltage[7] = 950000, /* 0.95V */
176 177
177 .buck2_voltage[0] = 1100000, /* 1.1V */ 178 .buck2_voltage[0] = 1100000, /* 1.1V */
178 .buck2_voltage[1] = 1000000, /* 1.0V */ 179 .buck2_voltage[1] = 1000000, /* 1.0V */
179 .buck2_voltage[2] = 950000, /* 0.95V */ 180 .buck2_voltage[2] = 950000, /* 0.95V */
180 .buck2_voltage[3] = 900000, /* 0.9V */ 181 .buck2_voltage[3] = 900000, /* 0.9V */
181 .buck2_voltage[4] = 1100000, /* 1.1V */ 182 .buck2_voltage[4] = 1100000, /* 1.1V */
182 .buck2_voltage[5] = 1000000, /* 1.0V */ 183 .buck2_voltage[5] = 1000000, /* 1.0V */
183 .buck2_voltage[6] = 950000, /* 0.95V */ 184 .buck2_voltage[6] = 950000, /* 0.95V */
184 .buck2_voltage[7] = 900000, /* 0.9V */ 185 .buck2_voltage[7] = 900000, /* 0.9V */
185 186
186 .buck5_voltage[0] = 1100000, /* 1.1V */ 187 .buck5_voltage[0] = 1100000, /* 1.1V */
187 .buck5_voltage[1] = 1100000, /* 1.1V */ 188 .buck5_voltage[1] = 1100000, /* 1.1V */
188 .buck5_voltage[2] = 1100000, /* 1.1V */ 189 .buck5_voltage[2] = 1100000, /* 1.1V */
189 .buck5_voltage[3] = 1100000, /* 1.1V */ 190 .buck5_voltage[3] = 1100000, /* 1.1V */
190 .buck5_voltage[4] = 1100000, /* 1.1V */ 191 .buck5_voltage[4] = 1100000, /* 1.1V */
191 .buck5_voltage[5] = 1100000, /* 1.1V */ 192 .buck5_voltage[5] = 1100000, /* 1.1V */
192 .buck5_voltage[6] = 1100000, /* 1.1V */ 193 .buck5_voltage[6] = 1100000, /* 1.1V */
193 .buck5_voltage[7] = 1100000, /* 1.1V */ 194 .buck5_voltage[7] = 1100000, /* 1.1V */
194 }; 195 };
195 196
196 static struct i2c_board_info smdk4x12_i2c_devs0[] __initdata = { 197 static struct i2c_board_info smdk4x12_i2c_devs0[] __initdata = {
197 { 198 {
198 I2C_BOARD_INFO("max8997", 0x66), 199 I2C_BOARD_INFO("max8997", 0x66),
199 .platform_data = &smdk4x12_max8997_pdata, 200 .platform_data = &smdk4x12_max8997_pdata,
200 } 201 }
201 }; 202 };
202 203
203 static struct i2c_board_info smdk4x12_i2c_devs1[] __initdata = { 204 static struct i2c_board_info smdk4x12_i2c_devs1[] __initdata = {
204 { I2C_BOARD_INFO("wm8994", 0x1a), } 205 { I2C_BOARD_INFO("wm8994", 0x1a), }
205 }; 206 };
206 207
207 static struct i2c_board_info smdk4x12_i2c_devs3[] __initdata = { 208 static struct i2c_board_info smdk4x12_i2c_devs3[] __initdata = {
208 /* nothing here yet */ 209 /* nothing here yet */
209 }; 210 };
210 211
211 static struct i2c_board_info smdk4x12_i2c_devs7[] __initdata = { 212 static struct i2c_board_info smdk4x12_i2c_devs7[] __initdata = {
212 /* nothing here yet */ 213 /* nothing here yet */
213 }; 214 };
214 215
215 static struct samsung_bl_gpio_info smdk4x12_bl_gpio_info = { 216 static struct samsung_bl_gpio_info smdk4x12_bl_gpio_info = {
216 .no = EXYNOS4_GPD0(1), 217 .no = EXYNOS4_GPD0(1),
217 .func = S3C_GPIO_SFN(2), 218 .func = S3C_GPIO_SFN(2),
218 }; 219 };
219 220
220 static struct platform_pwm_backlight_data smdk4x12_bl_data = { 221 static struct platform_pwm_backlight_data smdk4x12_bl_data = {
221 .pwm_id = 1, 222 .pwm_id = 1,
222 .pwm_period_ns = 1000, 223 .pwm_period_ns = 1000,
223 }; 224 };
224 225
226 static struct pwm_lookup smdk4x12_pwm_lookup[] = {
227 PWM_LOOKUP("s3c24xx-pwm.1", 0, "pwm-backlight.0", NULL),
228 };
229
225 static uint32_t smdk4x12_keymap[] __initdata = { 230 static uint32_t smdk4x12_keymap[] __initdata = {
226 /* KEY(row, col, keycode) */ 231 /* KEY(row, col, keycode) */
227 KEY(1, 3, KEY_1), KEY(1, 4, KEY_2), KEY(1, 5, KEY_3), 232 KEY(1, 3, KEY_1), KEY(1, 4, KEY_2), KEY(1, 5, KEY_3),
228 KEY(1, 6, KEY_4), KEY(1, 7, KEY_5), 233 KEY(1, 6, KEY_4), KEY(1, 7, KEY_5),
229 KEY(2, 5, KEY_D), KEY(2, 6, KEY_A), KEY(2, 7, KEY_B), 234 KEY(2, 5, KEY_D), KEY(2, 6, KEY_A), KEY(2, 7, KEY_B),
230 KEY(0, 7, KEY_E), KEY(0, 5, KEY_C) 235 KEY(0, 7, KEY_E), KEY(0, 5, KEY_C)
231 }; 236 };
232 237
233 static struct matrix_keymap_data smdk4x12_keymap_data __initdata = { 238 static struct matrix_keymap_data smdk4x12_keymap_data __initdata = {
234 .keymap = smdk4x12_keymap, 239 .keymap = smdk4x12_keymap,
235 .keymap_size = ARRAY_SIZE(smdk4x12_keymap), 240 .keymap_size = ARRAY_SIZE(smdk4x12_keymap),
236 }; 241 };
237 242
238 static struct samsung_keypad_platdata smdk4x12_keypad_data __initdata = { 243 static struct samsung_keypad_platdata smdk4x12_keypad_data __initdata = {
239 .keymap_data = &smdk4x12_keymap_data, 244 .keymap_data = &smdk4x12_keymap_data,
240 .rows = 3, 245 .rows = 3,
241 .cols = 8, 246 .cols = 8,
242 }; 247 };
243 248
244 #ifdef CONFIG_DRM_EXYNOS 249 #ifdef CONFIG_DRM_EXYNOS
245 static struct exynos_drm_fimd_pdata drm_fimd_pdata = { 250 static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
246 .panel = { 251 .panel = {
247 .timing = { 252 .timing = {
248 .left_margin = 8, 253 .left_margin = 8,
249 .right_margin = 8, 254 .right_margin = 8,
250 .upper_margin = 6, 255 .upper_margin = 6,
251 .lower_margin = 6, 256 .lower_margin = 6,
252 .hsync_len = 6, 257 .hsync_len = 6,
253 .vsync_len = 4, 258 .vsync_len = 4,
254 .xres = 480, 259 .xres = 480,
255 .yres = 800, 260 .yres = 800,
256 }, 261 },
257 }, 262 },
258 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, 263 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
259 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, 264 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
260 .default_win = 0, 265 .default_win = 0,
261 .bpp = 32, 266 .bpp = 32,
262 }; 267 };
263 #else 268 #else
264 static struct s3c_fb_pd_win smdk4x12_fb_win0 = { 269 static struct s3c_fb_pd_win smdk4x12_fb_win0 = {
265 .xres = 480, 270 .xres = 480,
266 .yres = 800, 271 .yres = 800,
267 .virtual_x = 480, 272 .virtual_x = 480,
268 .virtual_y = 800 * 2, 273 .virtual_y = 800 * 2,
269 .max_bpp = 32, 274 .max_bpp = 32,
270 .default_bpp = 24, 275 .default_bpp = 24,
271 }; 276 };
272 277
273 static struct fb_videomode smdk4x12_lcd_timing = { 278 static struct fb_videomode smdk4x12_lcd_timing = {
274 .left_margin = 8, 279 .left_margin = 8,
275 .right_margin = 8, 280 .right_margin = 8,
276 .upper_margin = 6, 281 .upper_margin = 6,
277 .lower_margin = 6, 282 .lower_margin = 6,
278 .hsync_len = 6, 283 .hsync_len = 6,
279 .vsync_len = 4, 284 .vsync_len = 4,
280 .xres = 480, 285 .xres = 480,
281 .yres = 800, 286 .yres = 800,
282 }; 287 };
283 288
284 static struct s3c_fb_platdata smdk4x12_lcd_pdata __initdata = { 289 static struct s3c_fb_platdata smdk4x12_lcd_pdata __initdata = {
285 .win[0] = &smdk4x12_fb_win0, 290 .win[0] = &smdk4x12_fb_win0,
286 .vtiming = &smdk4x12_lcd_timing, 291 .vtiming = &smdk4x12_lcd_timing,
287 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, 292 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
288 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, 293 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
289 .setup_gpio = exynos4_fimd0_gpio_setup_24bpp, 294 .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
290 }; 295 };
291 #endif 296 #endif
292 297
293 /* USB OTG */ 298 /* USB OTG */
294 static struct s3c_hsotg_plat smdk4x12_hsotg_pdata; 299 static struct s3c_hsotg_plat smdk4x12_hsotg_pdata;
295 300
296 static struct platform_device *smdk4x12_devices[] __initdata = { 301 static struct platform_device *smdk4x12_devices[] __initdata = {
297 &s3c_device_hsmmc2, 302 &s3c_device_hsmmc2,
298 &s3c_device_hsmmc3, 303 &s3c_device_hsmmc3,
299 &s3c_device_i2c0, 304 &s3c_device_i2c0,
300 &s3c_device_i2c1, 305 &s3c_device_i2c1,
301 &s3c_device_i2c3, 306 &s3c_device_i2c3,
302 &s3c_device_i2c7, 307 &s3c_device_i2c7,
303 &s3c_device_rtc, 308 &s3c_device_rtc,
304 &s3c_device_usb_hsotg, 309 &s3c_device_usb_hsotg,
305 &s3c_device_wdt, 310 &s3c_device_wdt,
306 &s5p_device_fimc0, 311 &s5p_device_fimc0,
307 &s5p_device_fimc1, 312 &s5p_device_fimc1,
308 &s5p_device_fimc2, 313 &s5p_device_fimc2,
309 &s5p_device_fimc3, 314 &s5p_device_fimc3,
310 &s5p_device_fimc_md, 315 &s5p_device_fimc_md,
311 &s5p_device_fimd0, 316 &s5p_device_fimd0,
312 &s5p_device_mfc, 317 &s5p_device_mfc,
313 &s5p_device_mfc_l, 318 &s5p_device_mfc_l,
314 &s5p_device_mfc_r, 319 &s5p_device_mfc_r,
315 #ifdef CONFIG_DRM_EXYNOS 320 #ifdef CONFIG_DRM_EXYNOS
316 &exynos_device_drm, 321 &exynos_device_drm,
317 #endif 322 #endif
318 &samsung_device_keypad, 323 &samsung_device_keypad,
319 }; 324 };
320 325
321 static void __init smdk4x12_map_io(void) 326 static void __init smdk4x12_map_io(void)
322 { 327 {
323 exynos_init_io(NULL, 0); 328 exynos_init_io(NULL, 0);
324 s3c24xx_init_clocks(clk_xusbxti.rate); 329 s3c24xx_init_clocks(clk_xusbxti.rate);
325 s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs)); 330 s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
326 } 331 }
327 332
328 static void __init smdk4x12_reserve(void) 333 static void __init smdk4x12_reserve(void)
329 { 334 {
330 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20); 335 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
331 } 336 }
332 337
333 static void __init smdk4x12_machine_init(void) 338 static void __init smdk4x12_machine_init(void)
334 { 339 {
335 s3c_i2c0_set_platdata(NULL); 340 s3c_i2c0_set_platdata(NULL);
336 i2c_register_board_info(0, smdk4x12_i2c_devs0, 341 i2c_register_board_info(0, smdk4x12_i2c_devs0,
337 ARRAY_SIZE(smdk4x12_i2c_devs0)); 342 ARRAY_SIZE(smdk4x12_i2c_devs0));
338 343
339 s3c_i2c1_set_platdata(NULL); 344 s3c_i2c1_set_platdata(NULL);
340 i2c_register_board_info(1, smdk4x12_i2c_devs1, 345 i2c_register_board_info(1, smdk4x12_i2c_devs1,
341 ARRAY_SIZE(smdk4x12_i2c_devs1)); 346 ARRAY_SIZE(smdk4x12_i2c_devs1));
342 347
343 s3c_i2c3_set_platdata(NULL); 348 s3c_i2c3_set_platdata(NULL);
344 i2c_register_board_info(3, smdk4x12_i2c_devs3, 349 i2c_register_board_info(3, smdk4x12_i2c_devs3,
345 ARRAY_SIZE(smdk4x12_i2c_devs3)); 350 ARRAY_SIZE(smdk4x12_i2c_devs3));
346 351
347 s3c_i2c7_set_platdata(NULL); 352 s3c_i2c7_set_platdata(NULL);
348 i2c_register_board_info(7, smdk4x12_i2c_devs7, 353 i2c_register_board_info(7, smdk4x12_i2c_devs7,
349 ARRAY_SIZE(smdk4x12_i2c_devs7)); 354 ARRAY_SIZE(smdk4x12_i2c_devs7));
350 355
351 samsung_bl_set(&smdk4x12_bl_gpio_info, &smdk4x12_bl_data); 356 samsung_bl_set(&smdk4x12_bl_gpio_info, &smdk4x12_bl_data);
357 pwm_add_table(smdk4x12_pwm_lookup, ARRAY_SIZE(smdk4x12_pwm_lookup));
352 358
353 samsung_keypad_set_platdata(&smdk4x12_keypad_data); 359 samsung_keypad_set_platdata(&smdk4x12_keypad_data);
354 360
355 s3c_sdhci2_set_platdata(&smdk4x12_hsmmc2_pdata); 361 s3c_sdhci2_set_platdata(&smdk4x12_hsmmc2_pdata);
356 s3c_sdhci3_set_platdata(&smdk4x12_hsmmc3_pdata); 362 s3c_sdhci3_set_platdata(&smdk4x12_hsmmc3_pdata);
357 363
358 s3c_hsotg_set_platdata(&smdk4x12_hsotg_pdata); 364 s3c_hsotg_set_platdata(&smdk4x12_hsotg_pdata);
359 365
360 #ifdef CONFIG_DRM_EXYNOS 366 #ifdef CONFIG_DRM_EXYNOS
361 s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata; 367 s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
362 exynos4_fimd0_gpio_setup_24bpp(); 368 exynos4_fimd0_gpio_setup_24bpp();
363 #else 369 #else
364 s5p_fimd0_set_platdata(&smdk4x12_lcd_pdata); 370 s5p_fimd0_set_platdata(&smdk4x12_lcd_pdata);
365 #endif 371 #endif
366 372
367 platform_add_devices(smdk4x12_devices, ARRAY_SIZE(smdk4x12_devices)); 373 platform_add_devices(smdk4x12_devices, ARRAY_SIZE(smdk4x12_devices));
368 } 374 }
369 375
370 MACHINE_START(SMDK4212, "SMDK4212") 376 MACHINE_START(SMDK4212, "SMDK4212")
371 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ 377 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
372 .atag_offset = 0x100, 378 .atag_offset = 0x100,
373 .init_irq = exynos4_init_irq, 379 .init_irq = exynos4_init_irq,
374 .map_io = smdk4x12_map_io, 380 .map_io = smdk4x12_map_io,
375 .handle_irq = gic_handle_irq, 381 .handle_irq = gic_handle_irq,
376 .init_machine = smdk4x12_machine_init, 382 .init_machine = smdk4x12_machine_init,
377 .timer = &exynos4_timer, 383 .timer = &exynos4_timer,
378 .restart = exynos4_restart, 384 .restart = exynos4_restart,
379 .reserve = &smdk4x12_reserve, 385 .reserve = &smdk4x12_reserve,
380 MACHINE_END 386 MACHINE_END
381 387
382 MACHINE_START(SMDK4412, "SMDK4412") 388 MACHINE_START(SMDK4412, "SMDK4412")
383 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ 389 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
384 /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */ 390 /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
385 .atag_offset = 0x100, 391 .atag_offset = 0x100,
386 .init_irq = exynos4_init_irq, 392 .init_irq = exynos4_init_irq,
387 .map_io = smdk4x12_map_io, 393 .map_io = smdk4x12_map_io,
388 .handle_irq = gic_handle_irq, 394 .handle_irq = gic_handle_irq,
389 .init_machine = smdk4x12_machine_init, 395 .init_machine = smdk4x12_machine_init,
390 .init_late = exynos_init_late, 396 .init_late = exynos_init_late,
391 .timer = &exynos4_timer, 397 .timer = &exynos4_timer,
392 .restart = exynos4_restart, 398 .restart = exynos4_restart,
393 .reserve = &smdk4x12_reserve, 399 .reserve = &smdk4x12_reserve,
394 MACHINE_END 400 MACHINE_END
395 401
arch/arm/mach-exynos/mach-smdkv310.c
Diff comments   View file @ 95360fd
1 /* linux/arch/arm/mach-exynos4/mach-smdkv310.c 1 /* linux/arch/arm/mach-exynos4/mach-smdkv310.c
2 * 2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11 #include <linux/serial_core.h> 11 #include <linux/serial_core.h>
12 #include <linux/delay.h> 12 #include <linux/delay.h>
13 #include <linux/gpio.h> 13 #include <linux/gpio.h>
14 #include <linux/lcd.h> 14 #include <linux/lcd.h>
15 #include <linux/mmc/host.h> 15 #include <linux/mmc/host.h>
16 #include <linux/platform_device.h> 16 #include <linux/platform_device.h>
17 #include <linux/smsc911x.h> 17 #include <linux/smsc911x.h>
18 #include <linux/io.h> 18 #include <linux/io.h>
19 #include <linux/i2c.h> 19 #include <linux/i2c.h>
20 #include <linux/input.h> 20 #include <linux/input.h>
21 #include <linux/pwm.h>
21 #include <linux/pwm_backlight.h> 22 #include <linux/pwm_backlight.h>
22 #include <linux/platform_data/s3c-hsotg.h> 23 #include <linux/platform_data/s3c-hsotg.h>
23 24
24 #include <asm/mach/arch.h> 25 #include <asm/mach/arch.h>
25 #include <asm/hardware/gic.h> 26 #include <asm/hardware/gic.h>
26 #include <asm/mach-types.h> 27 #include <asm/mach-types.h>
27 28
28 #include <video/platform_lcd.h> 29 #include <video/platform_lcd.h>
29 #include <plat/regs-serial.h> 30 #include <plat/regs-serial.h>
30 #include <plat/regs-srom.h> 31 #include <plat/regs-srom.h>
31 #include <plat/regs-fb-v4.h> 32 #include <plat/regs-fb-v4.h>
32 #include <plat/cpu.h> 33 #include <plat/cpu.h>
33 #include <plat/devs.h> 34 #include <plat/devs.h>
34 #include <plat/fb.h> 35 #include <plat/fb.h>
35 #include <plat/keypad.h> 36 #include <plat/keypad.h>
36 #include <plat/sdhci.h> 37 #include <plat/sdhci.h>
37 #include <plat/iic.h> 38 #include <plat/iic.h>
38 #include <plat/gpio-cfg.h> 39 #include <plat/gpio-cfg.h>
39 #include <plat/backlight.h> 40 #include <plat/backlight.h>
40 #include <plat/mfc.h> 41 #include <plat/mfc.h>
41 #include <plat/ehci.h> 42 #include <plat/ehci.h>
42 #include <plat/clock.h> 43 #include <plat/clock.h>
43 #include <plat/hdmi.h> 44 #include <plat/hdmi.h>
44 45
45 #include <mach/map.h> 46 #include <mach/map.h>
46 #include <mach/ohci.h> 47 #include <mach/ohci.h>
47 48
48 #include <drm/exynos_drm.h> 49 #include <drm/exynos_drm.h>
49 #include "common.h" 50 #include "common.h"
50 51
51 /* Following are default values for UCON, ULCON and UFCON UART registers */ 52 /* Following are default values for UCON, ULCON and UFCON UART registers */
52 #define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 53 #define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
53 S3C2410_UCON_RXILEVEL | \ 54 S3C2410_UCON_RXILEVEL | \
54 S3C2410_UCON_TXIRQMODE | \ 55 S3C2410_UCON_TXIRQMODE | \
55 S3C2410_UCON_RXIRQMODE | \ 56 S3C2410_UCON_RXIRQMODE | \
56 S3C2410_UCON_RXFIFO_TOI | \ 57 S3C2410_UCON_RXFIFO_TOI | \
57 S3C2443_UCON_RXERR_IRQEN) 58 S3C2443_UCON_RXERR_IRQEN)
58 59
59 #define SMDKV310_ULCON_DEFAULT S3C2410_LCON_CS8 60 #define SMDKV310_ULCON_DEFAULT S3C2410_LCON_CS8
60 61
61 #define SMDKV310_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ 62 #define SMDKV310_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
62 S5PV210_UFCON_TXTRIG4 | \ 63 S5PV210_UFCON_TXTRIG4 | \
63 S5PV210_UFCON_RXTRIG4) 64 S5PV210_UFCON_RXTRIG4)
64 65
65 static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = { 66 static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
66 [0] = { 67 [0] = {
67 .hwport = 0, 68 .hwport = 0,
68 .flags = 0, 69 .flags = 0,
69 .ucon = SMDKV310_UCON_DEFAULT, 70 .ucon = SMDKV310_UCON_DEFAULT,
70 .ulcon = SMDKV310_ULCON_DEFAULT, 71 .ulcon = SMDKV310_ULCON_DEFAULT,
71 .ufcon = SMDKV310_UFCON_DEFAULT, 72 .ufcon = SMDKV310_UFCON_DEFAULT,
72 }, 73 },
73 [1] = { 74 [1] = {
74 .hwport = 1, 75 .hwport = 1,
75 .flags = 0, 76 .flags = 0,
76 .ucon = SMDKV310_UCON_DEFAULT, 77 .ucon = SMDKV310_UCON_DEFAULT,
77 .ulcon = SMDKV310_ULCON_DEFAULT, 78 .ulcon = SMDKV310_ULCON_DEFAULT,
78 .ufcon = SMDKV310_UFCON_DEFAULT, 79 .ufcon = SMDKV310_UFCON_DEFAULT,
79 }, 80 },
80 [2] = { 81 [2] = {
81 .hwport = 2, 82 .hwport = 2,
82 .flags = 0, 83 .flags = 0,
83 .ucon = SMDKV310_UCON_DEFAULT, 84 .ucon = SMDKV310_UCON_DEFAULT,
84 .ulcon = SMDKV310_ULCON_DEFAULT, 85 .ulcon = SMDKV310_ULCON_DEFAULT,
85 .ufcon = SMDKV310_UFCON_DEFAULT, 86 .ufcon = SMDKV310_UFCON_DEFAULT,
86 }, 87 },
87 [3] = { 88 [3] = {
88 .hwport = 3, 89 .hwport = 3,
89 .flags = 0, 90 .flags = 0,
90 .ucon = SMDKV310_UCON_DEFAULT, 91 .ucon = SMDKV310_UCON_DEFAULT,
91 .ulcon = SMDKV310_ULCON_DEFAULT, 92 .ulcon = SMDKV310_ULCON_DEFAULT,
92 .ufcon = SMDKV310_UFCON_DEFAULT, 93 .ufcon = SMDKV310_UFCON_DEFAULT,
93 }, 94 },
94 }; 95 };
95 96
96 static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = { 97 static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
97 .cd_type = S3C_SDHCI_CD_INTERNAL, 98 .cd_type = S3C_SDHCI_CD_INTERNAL,
98 #ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT 99 #ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
99 .max_width = 8, 100 .max_width = 8,
100 .host_caps = MMC_CAP_8_BIT_DATA, 101 .host_caps = MMC_CAP_8_BIT_DATA,
101 #endif 102 #endif
102 }; 103 };
103 104
104 static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = { 105 static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
105 .cd_type = S3C_SDHCI_CD_GPIO, 106 .cd_type = S3C_SDHCI_CD_GPIO,
106 .ext_cd_gpio = EXYNOS4_GPK0(2), 107 .ext_cd_gpio = EXYNOS4_GPK0(2),
107 .ext_cd_gpio_invert = 1, 108 .ext_cd_gpio_invert = 1,
108 }; 109 };
109 110
110 static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = { 111 static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
111 .cd_type = S3C_SDHCI_CD_INTERNAL, 112 .cd_type = S3C_SDHCI_CD_INTERNAL,
112 #ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT 113 #ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
113 .max_width = 8, 114 .max_width = 8,
114 .host_caps = MMC_CAP_8_BIT_DATA, 115 .host_caps = MMC_CAP_8_BIT_DATA,
115 #endif 116 #endif
116 }; 117 };
117 118
118 static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = { 119 static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
119 .cd_type = S3C_SDHCI_CD_GPIO, 120 .cd_type = S3C_SDHCI_CD_GPIO,
120 .ext_cd_gpio = EXYNOS4_GPK2(2), 121 .ext_cd_gpio = EXYNOS4_GPK2(2),
121 .ext_cd_gpio_invert = 1, 122 .ext_cd_gpio_invert = 1,
122 }; 123 };
123 124
124 static void lcd_lte480wv_set_power(struct plat_lcd_data *pd, 125 static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
125 unsigned int power) 126 unsigned int power)
126 { 127 {
127 if (power) { 128 if (power) {
128 #if !defined(CONFIG_BACKLIGHT_PWM) 129 #if !defined(CONFIG_BACKLIGHT_PWM)
129 gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0"); 130 gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
130 gpio_free(EXYNOS4_GPD0(1)); 131 gpio_free(EXYNOS4_GPD0(1));
131 #endif 132 #endif
132 /* fire nRESET on power up */ 133 /* fire nRESET on power up */
133 gpio_request_one(EXYNOS4_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0"); 134 gpio_request_one(EXYNOS4_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0");
134 mdelay(100); 135 mdelay(100);
135 136
136 gpio_set_value(EXYNOS4_GPX0(6), 0); 137 gpio_set_value(EXYNOS4_GPX0(6), 0);
137 mdelay(10); 138 mdelay(10);
138 139
139 gpio_set_value(EXYNOS4_GPX0(6), 1); 140 gpio_set_value(EXYNOS4_GPX0(6), 1);
140 mdelay(10); 141 mdelay(10);
141 142
142 gpio_free(EXYNOS4_GPX0(6)); 143 gpio_free(EXYNOS4_GPX0(6));
143 } else { 144 } else {
144 #if !defined(CONFIG_BACKLIGHT_PWM) 145 #if !defined(CONFIG_BACKLIGHT_PWM)
145 gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0"); 146 gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
146 gpio_free(EXYNOS4_GPD0(1)); 147 gpio_free(EXYNOS4_GPD0(1));
147 #endif 148 #endif
148 } 149 }
149 } 150 }
150 151
151 static struct plat_lcd_data smdkv310_lcd_lte480wv_data = { 152 static struct plat_lcd_data smdkv310_lcd_lte480wv_data = {
152 .set_power = lcd_lte480wv_set_power, 153 .set_power = lcd_lte480wv_set_power,
153 }; 154 };
154 155
155 static struct platform_device smdkv310_lcd_lte480wv = { 156 static struct platform_device smdkv310_lcd_lte480wv = {
156 .name = "platform-lcd", 157 .name = "platform-lcd",
157 .dev.parent = &s5p_device_fimd0.dev, 158 .dev.parent = &s5p_device_fimd0.dev,
158 .dev.platform_data = &smdkv310_lcd_lte480wv_data, 159 .dev.platform_data = &smdkv310_lcd_lte480wv_data,
159 }; 160 };
160 161
161 #ifdef CONFIG_DRM_EXYNOS 162 #ifdef CONFIG_DRM_EXYNOS
162 static struct exynos_drm_fimd_pdata drm_fimd_pdata = { 163 static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
163 .panel = { 164 .panel = {
164 .timing = { 165 .timing = {
165 .left_margin = 13, 166 .left_margin = 13,
166 .right_margin = 8, 167 .right_margin = 8,
167 .upper_margin = 7, 168 .upper_margin = 7,
168 .lower_margin = 5, 169 .lower_margin = 5,
169 .hsync_len = 3, 170 .hsync_len = 3,
170 .vsync_len = 1, 171 .vsync_len = 1,
171 .xres = 800, 172 .xres = 800,
172 .yres = 480, 173 .yres = 480,
173 }, 174 },
174 }, 175 },
175 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, 176 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
176 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, 177 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
177 .default_win = 0, 178 .default_win = 0,
178 .bpp = 32, 179 .bpp = 32,
179 }; 180 };
180 #else 181 #else
181 static struct s3c_fb_pd_win smdkv310_fb_win0 = { 182 static struct s3c_fb_pd_win smdkv310_fb_win0 = {
182 .max_bpp = 32, 183 .max_bpp = 32,
183 .default_bpp = 24, 184 .default_bpp = 24,
184 .xres = 800, 185 .xres = 800,
185 .yres = 480, 186 .yres = 480,
186 }; 187 };
187 188
188 static struct fb_videomode smdkv310_lcd_timing = { 189 static struct fb_videomode smdkv310_lcd_timing = {
189 .left_margin = 13, 190 .left_margin = 13,
190 .right_margin = 8, 191 .right_margin = 8,
191 .upper_margin = 7, 192 .upper_margin = 7,
192 .lower_margin = 5, 193 .lower_margin = 5,
193 .hsync_len = 3, 194 .hsync_len = 3,
194 .vsync_len = 1, 195 .vsync_len = 1,
195 .xres = 800, 196 .xres = 800,
196 .yres = 480, 197 .yres = 480,
197 }; 198 };
198 199
199 static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = { 200 static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = {
200 .win[0] = &smdkv310_fb_win0, 201 .win[0] = &smdkv310_fb_win0,
201 .vtiming = &smdkv310_lcd_timing, 202 .vtiming = &smdkv310_lcd_timing,
202 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, 203 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
203 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, 204 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
204 .setup_gpio = exynos4_fimd0_gpio_setup_24bpp, 205 .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
205 }; 206 };
206 #endif 207 #endif
207 208
208 static struct resource smdkv310_smsc911x_resources[] = { 209 static struct resource smdkv310_smsc911x_resources[] = {
209 [0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(1), SZ_64K), 210 [0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(1), SZ_64K),
210 [1] = DEFINE_RES_NAMED(IRQ_EINT(5), 1, NULL, IORESOURCE_IRQ \ 211 [1] = DEFINE_RES_NAMED(IRQ_EINT(5), 1, NULL, IORESOURCE_IRQ \
211 | IRQF_TRIGGER_LOW), 212 | IRQF_TRIGGER_LOW),
212 }; 213 };
213 214
214 static struct smsc911x_platform_config smsc9215_config = { 215 static struct smsc911x_platform_config smsc9215_config = {
215 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, 216 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
216 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, 217 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
217 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY, 218 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
218 .phy_interface = PHY_INTERFACE_MODE_MII, 219 .phy_interface = PHY_INTERFACE_MODE_MII,
219 .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67}, 220 .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
220 }; 221 };
221 222
222 static struct platform_device smdkv310_smsc911x = { 223 static struct platform_device smdkv310_smsc911x = {
223 .name = "smsc911x", 224 .name = "smsc911x",
224 .id = -1, 225 .id = -1,
225 .num_resources = ARRAY_SIZE(smdkv310_smsc911x_resources), 226 .num_resources = ARRAY_SIZE(smdkv310_smsc911x_resources),
226 .resource = smdkv310_smsc911x_resources, 227 .resource = smdkv310_smsc911x_resources,
227 .dev = { 228 .dev = {
228 .platform_data = &smsc9215_config, 229 .platform_data = &smsc9215_config,
229 }, 230 },
230 }; 231 };
231 232
232 static uint32_t smdkv310_keymap[] __initdata = { 233 static uint32_t smdkv310_keymap[] __initdata = {
233 /* KEY(row, col, keycode) */ 234 /* KEY(row, col, keycode) */
234 KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3), 235 KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
235 KEY(0, 6, KEY_4), KEY(0, 7, KEY_5), 236 KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
236 KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C), 237 KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
237 KEY(1, 6, KEY_D), KEY(1, 7, KEY_E) 238 KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
238 }; 239 };
239 240
240 static struct matrix_keymap_data smdkv310_keymap_data __initdata = { 241 static struct matrix_keymap_data smdkv310_keymap_data __initdata = {
241 .keymap = smdkv310_keymap, 242 .keymap = smdkv310_keymap,
242 .keymap_size = ARRAY_SIZE(smdkv310_keymap), 243 .keymap_size = ARRAY_SIZE(smdkv310_keymap),
243 }; 244 };
244 245
245 static struct samsung_keypad_platdata smdkv310_keypad_data __initdata = { 246 static struct samsung_keypad_platdata smdkv310_keypad_data __initdata = {
246 .keymap_data = &smdkv310_keymap_data, 247 .keymap_data = &smdkv310_keymap_data,
247 .rows = 2, 248 .rows = 2,
248 .cols = 8, 249 .cols = 8,
249 }; 250 };
250 251
251 static struct i2c_board_info i2c_devs1[] __initdata = { 252 static struct i2c_board_info i2c_devs1[] __initdata = {
252 {I2C_BOARD_INFO("wm8994", 0x1a),}, 253 {I2C_BOARD_INFO("wm8994", 0x1a),},
253 }; 254 };
254 255
255 /* USB EHCI */ 256 /* USB EHCI */
256 static struct s5p_ehci_platdata smdkv310_ehci_pdata; 257 static struct s5p_ehci_platdata smdkv310_ehci_pdata;
257 258
258 static void __init smdkv310_ehci_init(void) 259 static void __init smdkv310_ehci_init(void)
259 { 260 {
260 struct s5p_ehci_platdata *pdata = &smdkv310_ehci_pdata; 261 struct s5p_ehci_platdata *pdata = &smdkv310_ehci_pdata;
261 262
262 s5p_ehci_set_platdata(pdata); 263 s5p_ehci_set_platdata(pdata);
263 } 264 }
264 265
265 /* USB OHCI */ 266 /* USB OHCI */
266 static struct exynos4_ohci_platdata smdkv310_ohci_pdata; 267 static struct exynos4_ohci_platdata smdkv310_ohci_pdata;
267 268
268 static void __init smdkv310_ohci_init(void) 269 static void __init smdkv310_ohci_init(void)
269 { 270 {
270 struct exynos4_ohci_platdata *pdata = &smdkv310_ohci_pdata; 271 struct exynos4_ohci_platdata *pdata = &smdkv310_ohci_pdata;
271 272
272 exynos4_ohci_set_platdata(pdata); 273 exynos4_ohci_set_platdata(pdata);
273 } 274 }
274 275
275 /* USB OTG */ 276 /* USB OTG */
276 static struct s3c_hsotg_plat smdkv310_hsotg_pdata; 277 static struct s3c_hsotg_plat smdkv310_hsotg_pdata;
277 278
278 /* Audio device */ 279 /* Audio device */
279 static struct platform_device smdkv310_device_audio = { 280 static struct platform_device smdkv310_device_audio = {
280 .name = "smdk-audio", 281 .name = "smdk-audio",
281 .id = -1, 282 .id = -1,
282 }; 283 };
283 284
284 static struct platform_device *smdkv310_devices[] __initdata = { 285 static struct platform_device *smdkv310_devices[] __initdata = {
285 &s3c_device_hsmmc0, 286 &s3c_device_hsmmc0,
286 &s3c_device_hsmmc1, 287 &s3c_device_hsmmc1,
287 &s3c_device_hsmmc2, 288 &s3c_device_hsmmc2,
288 &s3c_device_hsmmc3, 289 &s3c_device_hsmmc3,
289 &s3c_device_i2c1, 290 &s3c_device_i2c1,
290 &s5p_device_i2c_hdmiphy, 291 &s5p_device_i2c_hdmiphy,
291 &s3c_device_rtc, 292 &s3c_device_rtc,
292 &s3c_device_usb_hsotg, 293 &s3c_device_usb_hsotg,
293 &s3c_device_wdt, 294 &s3c_device_wdt,
294 &s5p_device_ehci, 295 &s5p_device_ehci,
295 &s5p_device_fimc0, 296 &s5p_device_fimc0,
296 &s5p_device_fimc1, 297 &s5p_device_fimc1,
297 &s5p_device_fimc2, 298 &s5p_device_fimc2,
298 &s5p_device_fimc3, 299 &s5p_device_fimc3,
299 &s5p_device_fimc_md, 300 &s5p_device_fimc_md,
300 &s5p_device_g2d, 301 &s5p_device_g2d,
301 &s5p_device_jpeg, 302 &s5p_device_jpeg,
302 #ifdef CONFIG_DRM_EXYNOS 303 #ifdef CONFIG_DRM_EXYNOS
303 &exynos_device_drm, 304 &exynos_device_drm,
304 #endif 305 #endif
305 &exynos4_device_ac97, 306 &exynos4_device_ac97,
306 &exynos4_device_i2s0, 307 &exynos4_device_i2s0,
307 &exynos4_device_ohci, 308 &exynos4_device_ohci,
308 &samsung_device_keypad, 309 &samsung_device_keypad,
309 &s5p_device_mfc, 310 &s5p_device_mfc,
310 &s5p_device_mfc_l, 311 &s5p_device_mfc_l,
311 &s5p_device_mfc_r, 312 &s5p_device_mfc_r,
312 &exynos4_device_spdif, 313 &exynos4_device_spdif,
313 &samsung_asoc_dma, 314 &samsung_asoc_dma,
314 &samsung_asoc_idma, 315 &samsung_asoc_idma,
315 &s5p_device_fimd0, 316 &s5p_device_fimd0,
316 &smdkv310_device_audio, 317 &smdkv310_device_audio,
317 &smdkv310_lcd_lte480wv, 318 &smdkv310_lcd_lte480wv,
318 &smdkv310_smsc911x, 319 &smdkv310_smsc911x,
319 &exynos4_device_ahci, 320 &exynos4_device_ahci,
320 &s5p_device_hdmi, 321 &s5p_device_hdmi,
321 &s5p_device_mixer, 322 &s5p_device_mixer,
322 }; 323 };
323 324
324 static void __init smdkv310_smsc911x_init(void) 325 static void __init smdkv310_smsc911x_init(void)
325 { 326 {
326 u32 cs1; 327 u32 cs1;
327 328
328 /* configure nCS1 width to 16 bits */ 329 /* configure nCS1 width to 16 bits */
329 cs1 = __raw_readl(S5P_SROM_BW) & 330 cs1 = __raw_readl(S5P_SROM_BW) &
330 ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT); 331 ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
331 cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) | 332 cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
332 (1 << S5P_SROM_BW__WAITENABLE__SHIFT) | 333 (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
333 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) << 334 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
334 S5P_SROM_BW__NCS1__SHIFT; 335 S5P_SROM_BW__NCS1__SHIFT;
335 __raw_writel(cs1, S5P_SROM_BW); 336 __raw_writel(cs1, S5P_SROM_BW);
336 337
337 /* set timing for nCS1 suitable for ethernet chip */ 338 /* set timing for nCS1 suitable for ethernet chip */
338 __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) | 339 __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
339 (0x9 << S5P_SROM_BCX__TACP__SHIFT) | 340 (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
340 (0xc << S5P_SROM_BCX__TCAH__SHIFT) | 341 (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
341 (0x1 << S5P_SROM_BCX__TCOH__SHIFT) | 342 (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
342 (0x6 << S5P_SROM_BCX__TACC__SHIFT) | 343 (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
343 (0x1 << S5P_SROM_BCX__TCOS__SHIFT) | 344 (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
344 (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1); 345 (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
345 } 346 }
346 347
347 /* LCD Backlight data */ 348 /* LCD Backlight data */
348 static struct samsung_bl_gpio_info smdkv310_bl_gpio_info = { 349 static struct samsung_bl_gpio_info smdkv310_bl_gpio_info = {
349 .no = EXYNOS4_GPD0(1), 350 .no = EXYNOS4_GPD0(1),
350 .func = S3C_GPIO_SFN(2), 351 .func = S3C_GPIO_SFN(2),
351 }; 352 };
352 353
353 static struct platform_pwm_backlight_data smdkv310_bl_data = { 354 static struct platform_pwm_backlight_data smdkv310_bl_data = {
354 .pwm_id = 1, 355 .pwm_id = 1,
355 .pwm_period_ns = 1000, 356 .pwm_period_ns = 1000,
356 }; 357 };
357 358
358 /* I2C module and id for HDMIPHY */ 359 /* I2C module and id for HDMIPHY */
359 static struct i2c_board_info hdmiphy_info = { 360 static struct i2c_board_info hdmiphy_info = {
360 I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38), 361 I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38),
361 }; 362 };
362 363
364 static struct pwm_lookup smdkv310_pwm_lookup[] = {
365 PWM_LOOKUP("s3c24xx-pwm.1", 0, "pwm-backlight.0", NULL),
366 };
367
363 static void s5p_tv_setup(void) 368 static void s5p_tv_setup(void)
364 { 369 {
365 /* direct HPD to HDMI chip */ 370 /* direct HPD to HDMI chip */
366 WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug")); 371 WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"));
367 s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3)); 372 s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
368 s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE); 373 s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
369 } 374 }
370 375
371 static void __init smdkv310_map_io(void) 376 static void __init smdkv310_map_io(void)
372 { 377 {
373 exynos_init_io(NULL, 0); 378 exynos_init_io(NULL, 0);
374 s3c24xx_init_clocks(clk_xusbxti.rate); 379 s3c24xx_init_clocks(clk_xusbxti.rate);
375 s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs)); 380 s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
376 } 381 }
377 382
378 static void __init smdkv310_reserve(void) 383 static void __init smdkv310_reserve(void)
379 { 384 {
380 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20); 385 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
381 } 386 }
382 387
383 static void __init smdkv310_machine_init(void) 388 static void __init smdkv310_machine_init(void)
384 { 389 {
385 s3c_i2c1_set_platdata(NULL); 390 s3c_i2c1_set_platdata(NULL);
386 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); 391 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
387 392
388 smdkv310_smsc911x_init(); 393 smdkv310_smsc911x_init();
389 394
390 s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata); 395 s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata);
391 s3c_sdhci1_set_platdata(&smdkv310_hsmmc1_pdata); 396 s3c_sdhci1_set_platdata(&smdkv310_hsmmc1_pdata);
392 s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata); 397 s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
393 s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata); 398 s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
394 399
395 s5p_tv_setup(); 400 s5p_tv_setup();
396 s5p_i2c_hdmiphy_set_platdata(NULL); 401 s5p_i2c_hdmiphy_set_platdata(NULL);
397 s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0); 402 s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0);
398 403
399 samsung_keypad_set_platdata(&smdkv310_keypad_data); 404 samsung_keypad_set_platdata(&smdkv310_keypad_data);
400 405
401 samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data); 406 samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data);
407 pwm_add_table(smdkv310_pwm_lookup, ARRAY_SIZE(smdkv310_pwm_lookup));
408
402 #ifdef CONFIG_DRM_EXYNOS 409 #ifdef CONFIG_DRM_EXYNOS
403 s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata; 410 s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
404 exynos4_fimd0_gpio_setup_24bpp(); 411 exynos4_fimd0_gpio_setup_24bpp();
405 #else 412 #else
406 s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata); 413 s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata);
407 #endif 414 #endif
408 415
409 smdkv310_ehci_init(); 416 smdkv310_ehci_init();
410 smdkv310_ohci_init(); 417 smdkv310_ohci_init();
411 s3c_hsotg_set_platdata(&smdkv310_hsotg_pdata); 418 s3c_hsotg_set_platdata(&smdkv310_hsotg_pdata);
412 419
413 platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices)); 420 platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
414 } 421 }
415 422
416 MACHINE_START(SMDKV310, "SMDKV310") 423 MACHINE_START(SMDKV310, "SMDKV310")
417 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ 424 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
418 /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */ 425 /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
419 .atag_offset = 0x100, 426 .atag_offset = 0x100,
420 .init_irq = exynos4_init_irq, 427 .init_irq = exynos4_init_irq,
421 .map_io = smdkv310_map_io, 428 .map_io = smdkv310_map_io,
422 .handle_irq = gic_handle_irq, 429 .handle_irq = gic_handle_irq,
423 .init_machine = smdkv310_machine_init, 430 .init_machine = smdkv310_machine_init,
424 .timer = &exynos4_timer, 431 .timer = &exynos4_timer,
425 .reserve = &smdkv310_reserve, 432 .reserve = &smdkv310_reserve,
426 .restart = exynos4_restart, 433 .restart = exynos4_restart,
427 MACHINE_END 434 MACHINE_END
428 435
429 MACHINE_START(SMDKC210, "SMDKC210") 436 MACHINE_START(SMDKC210, "SMDKC210")
430 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ 437 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
431 .atag_offset = 0x100, 438 .atag_offset = 0x100,
432 .init_irq = exynos4_init_irq, 439 .init_irq = exynos4_init_irq,
433 .map_io = smdkv310_map_io, 440 .map_io = smdkv310_map_io,
434 .handle_irq = gic_handle_irq, 441 .handle_irq = gic_handle_irq,
435 .init_machine = smdkv310_machine_init, 442 .init_machine = smdkv310_machine_init,
436 .init_late = exynos_init_late, 443 .init_late = exynos_init_late,
437 .timer = &exynos4_timer, 444 .timer = &exynos4_timer,
438 .reserve = &smdkv310_reserve, 445 .reserve = &smdkv310_reserve,
439 .restart = exynos4_restart, 446 .restart = exynos4_restart,
440 MACHINE_END 447 MACHINE_END
441 448
arch/arm/mach-imx/Kconfig
Diff comments   View file @ 95360fd
1 config HAVE_IMX_GPC 1 config HAVE_IMX_GPC
2 bool 2 bool
3 3
4 config HAVE_IMX_MMDC 4 config HAVE_IMX_MMDC
5 bool 5 bool
6 6
7 config HAVE_IMX_SRC 7 config HAVE_IMX_SRC
8 bool 8 bool
9 9
10 config ARCH_MX1 10 config ARCH_MX1
11 bool 11 bool
12 12
13 config MACH_MX21 13 config MACH_MX21
14 bool 14 bool
15 15
16 config ARCH_MX25 16 config ARCH_MX25
17 bool 17 bool
18 18
19 config MACH_MX27 19 config MACH_MX27
20 bool 20 bool
21 21
22 config ARCH_MX5 22 config ARCH_MX5
23 bool 23 bool
24 24
25 config ARCH_MX50 25 config ARCH_MX50
26 bool 26 bool
27 27
28 config ARCH_MX51 28 config ARCH_MX51
29 bool 29 bool
30 30
31 config ARCH_MX53 31 config ARCH_MX53
32 bool 32 bool
33 33
34 config SOC_IMX1 34 config SOC_IMX1
35 bool 35 bool
36 select ARCH_MX1 36 select ARCH_MX1
37 select COMMON_CLK 37 select COMMON_CLK
38 select CPU_ARM920T 38 select CPU_ARM920T
39 select IMX_HAVE_IOMUX_V1 39 select IMX_HAVE_IOMUX_V1
40 select MXC_AVIC 40 select MXC_AVIC
41 41
42 config SOC_IMX21 42 config SOC_IMX21
43 bool 43 bool
44 select MACH_MX21 44 select MACH_MX21
45 select CPU_ARM926T 45 select CPU_ARM926T
46 select COMMON_CLK 46 select COMMON_CLK
47 select IMX_HAVE_IOMUX_V1 47 select IMX_HAVE_IOMUX_V1
48 select MXC_AVIC 48 select MXC_AVIC
49 49
50 config SOC_IMX25 50 config SOC_IMX25
51 bool 51 bool
52 select ARCH_MX25 52 select ARCH_MX25
53 select COMMON_CLK 53 select COMMON_CLK
54 select CPU_ARM926T 54 select CPU_ARM926T
55 select HAVE_CAN_FLEXCAN if CAN 55 select HAVE_CAN_FLEXCAN if CAN
56 select ARCH_MXC_IOMUX_V3 56 select ARCH_MXC_IOMUX_V3
57 select MXC_AVIC 57 select MXC_AVIC
58 58
59 config SOC_IMX27 59 config SOC_IMX27
60 bool 60 bool
61 select MACH_MX27 61 select MACH_MX27
62 select CPU_ARM926T 62 select CPU_ARM926T
63 select COMMON_CLK 63 select COMMON_CLK
64 select IMX_HAVE_IOMUX_V1 64 select IMX_HAVE_IOMUX_V1
65 select MXC_AVIC 65 select MXC_AVIC
66 66
67 config SOC_IMX31 67 config SOC_IMX31
68 bool 68 bool
69 select CPU_V6 69 select CPU_V6
70 select IMX_HAVE_PLATFORM_MXC_RNGA 70 select IMX_HAVE_PLATFORM_MXC_RNGA
71 select MXC_AVIC 71 select MXC_AVIC
72 select COMMON_CLK 72 select COMMON_CLK
73 select SMP_ON_UP if SMP 73 select SMP_ON_UP if SMP
74 74
75 config SOC_IMX35 75 config SOC_IMX35
76 bool 76 bool
77 select CPU_V6K 77 select CPU_V6K
78 select ARCH_MXC_IOMUX_V3 78 select ARCH_MXC_IOMUX_V3
79 select COMMON_CLK 79 select COMMON_CLK
80 select HAVE_EPIT 80 select HAVE_EPIT
81 select MXC_AVIC 81 select MXC_AVIC
82 select SMP_ON_UP if SMP 82 select SMP_ON_UP if SMP
83 select HAVE_CAN_FLEXCAN if CAN 83 select HAVE_CAN_FLEXCAN if CAN
84 84
85 config SOC_IMX5 85 config SOC_IMX5
86 select CPU_V7 86 select CPU_V7
87 select MXC_TZIC 87 select MXC_TZIC
88 select COMMON_CLK 88 select COMMON_CLK
89 select ARCH_MXC_IOMUX_V3 89 select ARCH_MXC_IOMUX_V3
90 select ARCH_HAS_CPUFREQ 90 select ARCH_HAS_CPUFREQ
91 select ARCH_MX5 91 select ARCH_MX5
92 bool 92 bool
93 93
94 config SOC_IMX50 94 config SOC_IMX50
95 bool 95 bool
96 select SOC_IMX5 96 select SOC_IMX5
97 select ARCH_MX50 97 select ARCH_MX50
98 98
99 config SOC_IMX51 99 config SOC_IMX51
100 bool 100 bool
101 select SOC_IMX5 101 select SOC_IMX5
102 select ARCH_MX5 102 select ARCH_MX5
103 select ARCH_MX51 103 select ARCH_MX51
104 select PINCTRL 104 select PINCTRL
105 select PINCTRL_IMX51 105 select PINCTRL_IMX51
106 106
107 if ARCH_IMX_V4_V5 107 if ARCH_IMX_V4_V5
108 108
109 comment "MX1 platforms:" 109 comment "MX1 platforms:"
110 config MACH_MXLADS 110 config MACH_MXLADS
111 bool 111 bool
112 112
113 config ARCH_MX1ADS 113 config ARCH_MX1ADS
114 bool "MX1ADS platform" 114 bool "MX1ADS platform"
115 select MACH_MXLADS 115 select MACH_MXLADS
116 select SOC_IMX1 116 select SOC_IMX1
117 select IMX_HAVE_PLATFORM_IMX_I2C 117 select IMX_HAVE_PLATFORM_IMX_I2C
118 select IMX_HAVE_PLATFORM_IMX_UART 118 select IMX_HAVE_PLATFORM_IMX_UART
119 help 119 help
120 Say Y here if you are using Motorola MX1ADS/MXLADS boards 120 Say Y here if you are using Motorola MX1ADS/MXLADS boards
121 121
122 config MACH_SCB9328 122 config MACH_SCB9328
123 bool "Synertronixx scb9328" 123 bool "Synertronixx scb9328"
124 select IMX_HAVE_PLATFORM_IMX_UART 124 select IMX_HAVE_PLATFORM_IMX_UART
125 help 125 help
126 Say Y here if you are using a Synertronixx scb9328 board 126 Say Y here if you are using a Synertronixx scb9328 board
127 127
128 config MACH_APF9328 128 config MACH_APF9328
129 bool "APF9328" 129 bool "APF9328"
130 select SOC_IMX1 130 select SOC_IMX1
131 select IMX_HAVE_PLATFORM_IMX_I2C 131 select IMX_HAVE_PLATFORM_IMX_I2C
132 select IMX_HAVE_PLATFORM_IMX_UART 132 select IMX_HAVE_PLATFORM_IMX_UART
133 help 133 help
134 Say Yes here if you are using the Armadeus APF9328 development board 134 Say Yes here if you are using the Armadeus APF9328 development board
135 135
136 comment "MX21 platforms:" 136 comment "MX21 platforms:"
137 137
138 config MACH_MX21ADS 138 config MACH_MX21ADS
139 bool "MX21ADS platform" 139 bool "MX21ADS platform"
140 select SOC_IMX21 140 select SOC_IMX21
141 select IMX_HAVE_PLATFORM_IMX_FB 141 select IMX_HAVE_PLATFORM_IMX_FB
142 select IMX_HAVE_PLATFORM_IMX_UART 142 select IMX_HAVE_PLATFORM_IMX_UART
143 select IMX_HAVE_PLATFORM_MXC_MMC 143 select IMX_HAVE_PLATFORM_MXC_MMC
144 select IMX_HAVE_PLATFORM_MXC_NAND 144 select IMX_HAVE_PLATFORM_MXC_NAND
145 help 145 help
146 Include support for MX21ADS platform. This includes specific 146 Include support for MX21ADS platform. This includes specific
147 configurations for the board and its peripherals. 147 configurations for the board and its peripherals.
148 148
149 comment "MX25 platforms:" 149 comment "MX25 platforms:"
150 150
151 config MACH_MX25_3DS 151 config MACH_MX25_3DS
152 bool "Support MX25PDK (3DS) Platform" 152 bool "Support MX25PDK (3DS) Platform"
153 select SOC_IMX25 153 select SOC_IMX25
154 select IMX_HAVE_PLATFORM_FLEXCAN 154 select IMX_HAVE_PLATFORM_FLEXCAN
155 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 155 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
156 select IMX_HAVE_PLATFORM_IMX2_WDT 156 select IMX_HAVE_PLATFORM_IMX2_WDT
157 select IMX_HAVE_PLATFORM_IMXDI_RTC 157 select IMX_HAVE_PLATFORM_IMXDI_RTC
158 select IMX_HAVE_PLATFORM_IMX_I2C 158 select IMX_HAVE_PLATFORM_IMX_I2C
159 select IMX_HAVE_PLATFORM_IMX_FB 159 select IMX_HAVE_PLATFORM_IMX_FB
160 select IMX_HAVE_PLATFORM_IMX_KEYPAD 160 select IMX_HAVE_PLATFORM_IMX_KEYPAD
161 select IMX_HAVE_PLATFORM_IMX_UART 161 select IMX_HAVE_PLATFORM_IMX_UART
162 select IMX_HAVE_PLATFORM_MXC_EHCI 162 select IMX_HAVE_PLATFORM_MXC_EHCI
163 select IMX_HAVE_PLATFORM_MXC_NAND 163 select IMX_HAVE_PLATFORM_MXC_NAND
164 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 164 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
165 165
166 config MACH_EUKREA_CPUIMX25SD 166 config MACH_EUKREA_CPUIMX25SD
167 bool "Support Eukrea CPUIMX25 Platform" 167 bool "Support Eukrea CPUIMX25 Platform"
168 select SOC_IMX25 168 select SOC_IMX25
169 select IMX_HAVE_PLATFORM_FLEXCAN 169 select IMX_HAVE_PLATFORM_FLEXCAN
170 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 170 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
171 select IMX_HAVE_PLATFORM_IMX2_WDT 171 select IMX_HAVE_PLATFORM_IMX2_WDT
172 select IMX_HAVE_PLATFORM_IMXDI_RTC 172 select IMX_HAVE_PLATFORM_IMXDI_RTC
173 select IMX_HAVE_PLATFORM_IMX_FB 173 select IMX_HAVE_PLATFORM_IMX_FB
174 select IMX_HAVE_PLATFORM_IMX_I2C 174 select IMX_HAVE_PLATFORM_IMX_I2C
175 select IMX_HAVE_PLATFORM_IMX_UART 175 select IMX_HAVE_PLATFORM_IMX_UART
176 select IMX_HAVE_PLATFORM_MXC_EHCI 176 select IMX_HAVE_PLATFORM_MXC_EHCI
177 select IMX_HAVE_PLATFORM_MXC_NAND 177 select IMX_HAVE_PLATFORM_MXC_NAND
178 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 178 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
179 select MXC_ULPI if USB_ULPI 179 select MXC_ULPI if USB_ULPI
180 180
181 choice 181 choice
182 prompt "Baseboard" 182 prompt "Baseboard"
183 depends on MACH_EUKREA_CPUIMX25SD 183 depends on MACH_EUKREA_CPUIMX25SD
184 default MACH_EUKREA_MBIMXSD25_BASEBOARD 184 default MACH_EUKREA_MBIMXSD25_BASEBOARD
185 185
186 config MACH_EUKREA_MBIMXSD25_BASEBOARD 186 config MACH_EUKREA_MBIMXSD25_BASEBOARD
187 bool "Eukrea MBIMXSD development board" 187 bool "Eukrea MBIMXSD development board"
188 select IMX_HAVE_PLATFORM_GPIO_KEYS 188 select IMX_HAVE_PLATFORM_GPIO_KEYS
189 select IMX_HAVE_PLATFORM_IMX_SSI 189 select IMX_HAVE_PLATFORM_IMX_SSI
190 select IMX_HAVE_PLATFORM_SPI_IMX 190 select IMX_HAVE_PLATFORM_SPI_IMX
191 select LEDS_GPIO_REGISTER 191 select LEDS_GPIO_REGISTER
192 help 192 help
193 This adds board specific devices that can be found on Eukrea's 193 This adds board specific devices that can be found on Eukrea's
194 MBIMXSD evaluation board. 194 MBIMXSD evaluation board.
195 195
196 endchoice 196 endchoice
197 197
198 comment "MX27 platforms:" 198 comment "MX27 platforms:"
199 199
200 config MACH_MX27ADS 200 config MACH_MX27ADS
201 bool "MX27ADS platform" 201 bool "MX27ADS platform"
202 select SOC_IMX27 202 select SOC_IMX27
203 select IMX_HAVE_PLATFORM_IMX_FB 203 select IMX_HAVE_PLATFORM_IMX_FB
204 select IMX_HAVE_PLATFORM_IMX_I2C 204 select IMX_HAVE_PLATFORM_IMX_I2C
205 select IMX_HAVE_PLATFORM_IMX_UART 205 select IMX_HAVE_PLATFORM_IMX_UART
206 select IMX_HAVE_PLATFORM_MXC_MMC 206 select IMX_HAVE_PLATFORM_MXC_MMC
207 select IMX_HAVE_PLATFORM_MXC_NAND 207 select IMX_HAVE_PLATFORM_MXC_NAND
208 select IMX_HAVE_PLATFORM_MXC_W1 208 select IMX_HAVE_PLATFORM_MXC_W1
209 help 209 help
210 Include support for MX27ADS platform. This includes specific 210 Include support for MX27ADS platform. This includes specific
211 configurations for the board and its peripherals. 211 configurations for the board and its peripherals.
212 212
213 config MACH_PCM038 213 config MACH_PCM038
214 bool "Phytec phyCORE-i.MX27 CPU module (pcm038)" 214 bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
215 select SOC_IMX27 215 select SOC_IMX27
216 select IMX_HAVE_PLATFORM_IMX2_WDT 216 select IMX_HAVE_PLATFORM_IMX2_WDT
217 select IMX_HAVE_PLATFORM_IMX_I2C 217 select IMX_HAVE_PLATFORM_IMX_I2C
218 select IMX_HAVE_PLATFORM_IMX_UART 218 select IMX_HAVE_PLATFORM_IMX_UART
219 select IMX_HAVE_PLATFORM_MXC_EHCI 219 select IMX_HAVE_PLATFORM_MXC_EHCI
220 select IMX_HAVE_PLATFORM_MXC_NAND 220 select IMX_HAVE_PLATFORM_MXC_NAND
221 select IMX_HAVE_PLATFORM_MXC_W1 221 select IMX_HAVE_PLATFORM_MXC_W1
222 select IMX_HAVE_PLATFORM_SPI_IMX 222 select IMX_HAVE_PLATFORM_SPI_IMX
223 select MXC_ULPI if USB_ULPI 223 select MXC_ULPI if USB_ULPI
224 help 224 help
225 Include support for phyCORE-i.MX27 (aka pcm038) platform. This 225 Include support for phyCORE-i.MX27 (aka pcm038) platform. This
226 includes specific configurations for the module and its peripherals. 226 includes specific configurations for the module and its peripherals.
227 227
228 choice 228 choice
229 prompt "Baseboard" 229 prompt "Baseboard"
230 depends on MACH_PCM038 230 depends on MACH_PCM038
231 default MACH_PCM970_BASEBOARD 231 default MACH_PCM970_BASEBOARD
232 232
233 config MACH_PCM970_BASEBOARD 233 config MACH_PCM970_BASEBOARD
234 bool "PHYTEC PCM970 development board" 234 bool "PHYTEC PCM970 development board"
235 select IMX_HAVE_PLATFORM_IMX_FB 235 select IMX_HAVE_PLATFORM_IMX_FB
236 select IMX_HAVE_PLATFORM_MXC_MMC 236 select IMX_HAVE_PLATFORM_MXC_MMC
237 help 237 help
238 This adds board specific devices that can be found on Phytec's 238 This adds board specific devices that can be found on Phytec's
239 PCM970 evaluation board. 239 PCM970 evaluation board.
240 240
241 endchoice 241 endchoice
242 242
243 config MACH_CPUIMX27 243 config MACH_CPUIMX27
244 bool "Eukrea CPUIMX27 module" 244 bool "Eukrea CPUIMX27 module"
245 select SOC_IMX27 245 select SOC_IMX27
246 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 246 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
247 select IMX_HAVE_PLATFORM_IMX2_WDT 247 select IMX_HAVE_PLATFORM_IMX2_WDT
248 select IMX_HAVE_PLATFORM_IMX_I2C 248 select IMX_HAVE_PLATFORM_IMX_I2C
249 select IMX_HAVE_PLATFORM_IMX_UART 249 select IMX_HAVE_PLATFORM_IMX_UART
250 select IMX_HAVE_PLATFORM_MXC_EHCI 250 select IMX_HAVE_PLATFORM_MXC_EHCI
251 select IMX_HAVE_PLATFORM_MXC_NAND 251 select IMX_HAVE_PLATFORM_MXC_NAND
252 select IMX_HAVE_PLATFORM_MXC_W1 252 select IMX_HAVE_PLATFORM_MXC_W1
253 select MXC_ULPI if USB_ULPI 253 select MXC_ULPI if USB_ULPI
254 help 254 help
255 Include support for Eukrea CPUIMX27 platform. This includes 255 Include support for Eukrea CPUIMX27 platform. This includes
256 specific configurations for the module and its peripherals. 256 specific configurations for the module and its peripherals.
257 257
258 config MACH_EUKREA_CPUIMX27_USESDHC2 258 config MACH_EUKREA_CPUIMX27_USESDHC2
259 bool "CPUIMX27 integrates SDHC2 module" 259 bool "CPUIMX27 integrates SDHC2 module"
260 depends on MACH_CPUIMX27 260 depends on MACH_CPUIMX27
261 select IMX_HAVE_PLATFORM_MXC_MMC 261 select IMX_HAVE_PLATFORM_MXC_MMC
262 help 262 help
263 This adds support for the internal SDHC2 used on CPUIMX27 263 This adds support for the internal SDHC2 used on CPUIMX27
264 for wifi or eMMC. 264 for wifi or eMMC.
265 265
266 config MACH_EUKREA_CPUIMX27_USEUART4 266 config MACH_EUKREA_CPUIMX27_USEUART4
267 bool "CPUIMX27 integrates UART4 module" 267 bool "CPUIMX27 integrates UART4 module"
268 depends on MACH_CPUIMX27 268 depends on MACH_CPUIMX27
269 help 269 help
270 This adds support for the internal UART4 used on CPUIMX27 270 This adds support for the internal UART4 used on CPUIMX27
271 for bluetooth. 271 for bluetooth.
272 272
273 choice 273 choice
274 prompt "Baseboard" 274 prompt "Baseboard"
275 depends on MACH_CPUIMX27 275 depends on MACH_CPUIMX27
276 default MACH_EUKREA_MBIMX27_BASEBOARD 276 default MACH_EUKREA_MBIMX27_BASEBOARD
277 277
278 config MACH_EUKREA_MBIMX27_BASEBOARD 278 config MACH_EUKREA_MBIMX27_BASEBOARD
279 bool "Eukrea MBIMX27 development board" 279 bool "Eukrea MBIMX27 development board"
280 select IMX_HAVE_PLATFORM_IMX_FB 280 select IMX_HAVE_PLATFORM_IMX_FB
281 select IMX_HAVE_PLATFORM_IMX_KEYPAD 281 select IMX_HAVE_PLATFORM_IMX_KEYPAD
282 select IMX_HAVE_PLATFORM_IMX_SSI 282 select IMX_HAVE_PLATFORM_IMX_SSI
283 select IMX_HAVE_PLATFORM_IMX_UART 283 select IMX_HAVE_PLATFORM_IMX_UART
284 select IMX_HAVE_PLATFORM_MXC_MMC 284 select IMX_HAVE_PLATFORM_MXC_MMC
285 select IMX_HAVE_PLATFORM_SPI_IMX 285 select IMX_HAVE_PLATFORM_SPI_IMX
286 select LEDS_GPIO_REGISTER 286 select LEDS_GPIO_REGISTER
287 help 287 help
288 This adds board specific devices that can be found on Eukrea's 288 This adds board specific devices that can be found on Eukrea's
289 MBIMX27 evaluation board. 289 MBIMX27 evaluation board.
290 290
291 endchoice 291 endchoice
292 292
293 config MACH_MX27_3DS 293 config MACH_MX27_3DS
294 bool "MX27PDK platform" 294 bool "MX27PDK platform"
295 select SOC_IMX27 295 select SOC_IMX27
296 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 296 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
297 select IMX_HAVE_PLATFORM_IMX2_WDT 297 select IMX_HAVE_PLATFORM_IMX2_WDT
298 select IMX_HAVE_PLATFORM_IMX_FB 298 select IMX_HAVE_PLATFORM_IMX_FB
299 select IMX_HAVE_PLATFORM_IMX_I2C 299 select IMX_HAVE_PLATFORM_IMX_I2C
300 select IMX_HAVE_PLATFORM_IMX_KEYPAD 300 select IMX_HAVE_PLATFORM_IMX_KEYPAD
301 select IMX_HAVE_PLATFORM_IMX_SSI
301 select IMX_HAVE_PLATFORM_IMX_UART 302 select IMX_HAVE_PLATFORM_IMX_UART
302 select IMX_HAVE_PLATFORM_MX2_CAMERA 303 select IMX_HAVE_PLATFORM_MX2_CAMERA
303 select IMX_HAVE_PLATFORM_MXC_EHCI 304 select IMX_HAVE_PLATFORM_MXC_EHCI
304 select IMX_HAVE_PLATFORM_MXC_MMC 305 select IMX_HAVE_PLATFORM_MXC_MMC
305 select IMX_HAVE_PLATFORM_SPI_IMX 306 select IMX_HAVE_PLATFORM_SPI_IMX
306 select MXC_DEBUG_BOARD 307 select MXC_DEBUG_BOARD
307 select MXC_ULPI if USB_ULPI 308 select MXC_ULPI if USB_ULPI
308 help 309 help
309 Include support for MX27PDK platform. This includes specific 310 Include support for MX27PDK platform. This includes specific
310 configurations for the board and its peripherals. 311 configurations for the board and its peripherals.
311 312
312 config MACH_IMX27_VISSTRIM_M10 313 config MACH_IMX27_VISSTRIM_M10
313 bool "Vista Silicon i.MX27 Visstrim_m10" 314 bool "Vista Silicon i.MX27 Visstrim_m10"
314 select SOC_IMX27 315 select SOC_IMX27
315 select IMX_HAVE_PLATFORM_GPIO_KEYS 316 select IMX_HAVE_PLATFORM_GPIO_KEYS
316 select IMX_HAVE_PLATFORM_IMX_I2C 317 select IMX_HAVE_PLATFORM_IMX_I2C
317 select IMX_HAVE_PLATFORM_IMX_SSI 318 select IMX_HAVE_PLATFORM_IMX_SSI
318 select IMX_HAVE_PLATFORM_IMX_UART 319 select IMX_HAVE_PLATFORM_IMX_UART
319 select IMX_HAVE_PLATFORM_MX2_CAMERA 320 select IMX_HAVE_PLATFORM_MX2_CAMERA
320 select IMX_HAVE_PLATFORM_MXC_EHCI 321 select IMX_HAVE_PLATFORM_MXC_EHCI
321 select IMX_HAVE_PLATFORM_MXC_MMC 322 select IMX_HAVE_PLATFORM_MXC_MMC
322 select LEDS_GPIO_REGISTER 323 select LEDS_GPIO_REGISTER
323 help 324 help
324 Include support for Visstrim_m10 platform and its different variants. 325 Include support for Visstrim_m10 platform and its different variants.
325 This includes specific configurations for the board and its 326 This includes specific configurations for the board and its
326 peripherals. 327 peripherals.
327 328
328 config MACH_IMX27LITE 329 config MACH_IMX27LITE
329 bool "LogicPD MX27 LITEKIT platform" 330 bool "LogicPD MX27 LITEKIT platform"
330 select SOC_IMX27 331 select SOC_IMX27
331 select IMX_HAVE_PLATFORM_IMX_UART 332 select IMX_HAVE_PLATFORM_IMX_UART
332 select IMX_HAVE_PLATFORM_IMX_SSI 333 select IMX_HAVE_PLATFORM_IMX_SSI
333 help 334 help
334 Include support for MX27 LITEKIT platform. This includes specific 335 Include support for MX27 LITEKIT platform. This includes specific
335 configurations for the board and its peripherals. 336 configurations for the board and its peripherals.
336 337
337 config MACH_PCA100 338 config MACH_PCA100
338 bool "Phytec phyCARD-s (pca100)" 339 bool "Phytec phyCARD-s (pca100)"
339 select SOC_IMX27 340 select SOC_IMX27
340 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 341 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
341 select IMX_HAVE_PLATFORM_IMX2_WDT 342 select IMX_HAVE_PLATFORM_IMX2_WDT
342 select IMX_HAVE_PLATFORM_IMX_FB 343 select IMX_HAVE_PLATFORM_IMX_FB
343 select IMX_HAVE_PLATFORM_IMX_I2C 344 select IMX_HAVE_PLATFORM_IMX_I2C
344 select IMX_HAVE_PLATFORM_IMX_SSI 345 select IMX_HAVE_PLATFORM_IMX_SSI
345 select IMX_HAVE_PLATFORM_IMX_UART 346 select IMX_HAVE_PLATFORM_IMX_UART
346 select IMX_HAVE_PLATFORM_MXC_EHCI 347 select IMX_HAVE_PLATFORM_MXC_EHCI
347 select IMX_HAVE_PLATFORM_MXC_MMC 348 select IMX_HAVE_PLATFORM_MXC_MMC
348 select IMX_HAVE_PLATFORM_MXC_NAND 349 select IMX_HAVE_PLATFORM_MXC_NAND
349 select IMX_HAVE_PLATFORM_MXC_W1 350 select IMX_HAVE_PLATFORM_MXC_W1
350 select IMX_HAVE_PLATFORM_SPI_IMX 351 select IMX_HAVE_PLATFORM_SPI_IMX
351 select MXC_ULPI if USB_ULPI 352 select MXC_ULPI if USB_ULPI
352 help 353 help
353 Include support for phyCARD-s (aka pca100) platform. This 354 Include support for phyCARD-s (aka pca100) platform. This
354 includes specific configurations for the module and its peripherals. 355 includes specific configurations for the module and its peripherals.
355 356
356 config MACH_MXT_TD60 357 config MACH_MXT_TD60
357 bool "Maxtrack i-MXT TD60" 358 bool "Maxtrack i-MXT TD60"
358 select SOC_IMX27 359 select SOC_IMX27
359 select IMX_HAVE_PLATFORM_IMX_FB 360 select IMX_HAVE_PLATFORM_IMX_FB
360 select IMX_HAVE_PLATFORM_IMX_I2C 361 select IMX_HAVE_PLATFORM_IMX_I2C
361 select IMX_HAVE_PLATFORM_IMX_UART 362 select IMX_HAVE_PLATFORM_IMX_UART
362 select IMX_HAVE_PLATFORM_MXC_MMC 363 select IMX_HAVE_PLATFORM_MXC_MMC
363 select IMX_HAVE_PLATFORM_MXC_NAND 364 select IMX_HAVE_PLATFORM_MXC_NAND
364 help 365 help
365 Include support for i-MXT (aka td60) platform. This 366 Include support for i-MXT (aka td60) platform. This
366 includes specific configurations for the module and its peripherals. 367 includes specific configurations for the module and its peripherals.
367 368
368 config MACH_IMX27IPCAM 369 config MACH_IMX27IPCAM
369 bool "IMX27 IPCAM platform" 370 bool "IMX27 IPCAM platform"
370 select SOC_IMX27 371 select SOC_IMX27
371 select IMX_HAVE_PLATFORM_IMX2_WDT 372 select IMX_HAVE_PLATFORM_IMX2_WDT
372 select IMX_HAVE_PLATFORM_IMX_UART 373 select IMX_HAVE_PLATFORM_IMX_UART
373 help 374 help
374 Include support for IMX27 IPCAM platform. This includes specific 375 Include support for IMX27 IPCAM platform. This includes specific
375 configurations for the board and its peripherals. 376 configurations for the board and its peripherals.
376 377
377 config MACH_IMX27_DT 378 config MACH_IMX27_DT
378 bool "Support i.MX27 platforms from device tree" 379 bool "Support i.MX27 platforms from device tree"
379 select SOC_IMX27 380 select SOC_IMX27
380 help 381 help
381 Include support for Freescale i.MX27 based platforms 382 Include support for Freescale i.MX27 based platforms
382 using the device tree for discovery 383 using the device tree for discovery
383 384
384 endif 385 endif
385 386
386 if ARCH_IMX_V6_V7 387 if ARCH_IMX_V6_V7
387 388
388 comment "MX31 platforms:" 389 comment "MX31 platforms:"
389 390
390 config MACH_MX31ADS 391 config MACH_MX31ADS
391 bool "Support MX31ADS platforms" 392 bool "Support MX31ADS platforms"
392 select SOC_IMX31 393 select SOC_IMX31
393 select IMX_HAVE_PLATFORM_IMX_I2C 394 select IMX_HAVE_PLATFORM_IMX_I2C
394 select IMX_HAVE_PLATFORM_IMX_SSI 395 select IMX_HAVE_PLATFORM_IMX_SSI
395 select IMX_HAVE_PLATFORM_IMX_UART 396 select IMX_HAVE_PLATFORM_IMX_UART
396 default y 397 default y
397 help 398 help
398 Include support for MX31ADS platform. This includes specific 399 Include support for MX31ADS platform. This includes specific
399 configurations for the board and its peripherals. 400 configurations for the board and its peripherals.
400 401
401 config MACH_MX31ADS_WM1133_EV1 402 config MACH_MX31ADS_WM1133_EV1
402 bool "Support Wolfson Microelectronics 1133-EV1 module" 403 bool "Support Wolfson Microelectronics 1133-EV1 module"
403 depends on MACH_MX31ADS 404 depends on MACH_MX31ADS
404 depends on MFD_WM8350_I2C 405 depends on MFD_WM8350_I2C
405 depends on REGULATOR_WM8350 406 depends on REGULATOR_WM8350
406 select MFD_WM8350_CONFIG_MODE_0 407 select MFD_WM8350_CONFIG_MODE_0
407 select MFD_WM8352_CONFIG_MODE_0 408 select MFD_WM8352_CONFIG_MODE_0
408 help 409 help
409 Include support for the Wolfson Microelectronics 1133-EV1 PMU 410 Include support for the Wolfson Microelectronics 1133-EV1 PMU
410 and audio module for the MX31ADS platform. 411 and audio module for the MX31ADS platform.
411 412
412 config MACH_MX31LILLY 413 config MACH_MX31LILLY
413 bool "Support MX31 LILLY-1131 platforms (INCO startec)" 414 bool "Support MX31 LILLY-1131 platforms (INCO startec)"
414 select SOC_IMX31 415 select SOC_IMX31
415 select IMX_HAVE_PLATFORM_IMX_UART 416 select IMX_HAVE_PLATFORM_IMX_UART
416 select IMX_HAVE_PLATFORM_IPU_CORE 417 select IMX_HAVE_PLATFORM_IPU_CORE
417 select IMX_HAVE_PLATFORM_MXC_EHCI 418 select IMX_HAVE_PLATFORM_MXC_EHCI
418 select IMX_HAVE_PLATFORM_MXC_MMC 419 select IMX_HAVE_PLATFORM_MXC_MMC
419 select IMX_HAVE_PLATFORM_SPI_IMX 420 select IMX_HAVE_PLATFORM_SPI_IMX
420 select MXC_ULPI if USB_ULPI 421 select MXC_ULPI if USB_ULPI
421 help 422 help
422 Include support for mx31 based LILLY1131 modules. This includes 423 Include support for mx31 based LILLY1131 modules. This includes
423 specific configurations for the board and its peripherals. 424 specific configurations for the board and its peripherals.
424 425
425 config MACH_MX31LITE 426 config MACH_MX31LITE
426 bool "Support MX31 LITEKIT (LogicPD)" 427 bool "Support MX31 LITEKIT (LogicPD)"
427 select SOC_IMX31 428 select SOC_IMX31
428 select MXC_ULPI if USB_ULPI 429 select MXC_ULPI if USB_ULPI
429 select IMX_HAVE_PLATFORM_IMX2_WDT 430 select IMX_HAVE_PLATFORM_IMX2_WDT
430 select IMX_HAVE_PLATFORM_IMX_UART 431 select IMX_HAVE_PLATFORM_IMX_UART
431 select IMX_HAVE_PLATFORM_MXC_EHCI 432 select IMX_HAVE_PLATFORM_MXC_EHCI
432 select IMX_HAVE_PLATFORM_MXC_MMC 433 select IMX_HAVE_PLATFORM_MXC_MMC
433 select IMX_HAVE_PLATFORM_MXC_NAND 434 select IMX_HAVE_PLATFORM_MXC_NAND
434 select IMX_HAVE_PLATFORM_MXC_RTC 435 select IMX_HAVE_PLATFORM_MXC_RTC
435 select IMX_HAVE_PLATFORM_SPI_IMX 436 select IMX_HAVE_PLATFORM_SPI_IMX
436 select LEDS_GPIO_REGISTER 437 select LEDS_GPIO_REGISTER
437 help 438 help
438 Include support for MX31 LITEKIT platform. This includes specific 439 Include support for MX31 LITEKIT platform. This includes specific
439 configurations for the board and its peripherals. 440 configurations for the board and its peripherals.
440 441
441 config MACH_PCM037 442 config MACH_PCM037
442 bool "Support Phytec pcm037 (i.MX31) platforms" 443 bool "Support Phytec pcm037 (i.MX31) platforms"
443 select SOC_IMX31 444 select SOC_IMX31
444 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 445 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
445 select IMX_HAVE_PLATFORM_IMX2_WDT 446 select IMX_HAVE_PLATFORM_IMX2_WDT
446 select IMX_HAVE_PLATFORM_IMX_I2C 447 select IMX_HAVE_PLATFORM_IMX_I2C
447 select IMX_HAVE_PLATFORM_IMX_UART 448 select IMX_HAVE_PLATFORM_IMX_UART
448 select IMX_HAVE_PLATFORM_IPU_CORE 449 select IMX_HAVE_PLATFORM_IPU_CORE
449 select IMX_HAVE_PLATFORM_MXC_EHCI 450 select IMX_HAVE_PLATFORM_MXC_EHCI
450 select IMX_HAVE_PLATFORM_MXC_MMC 451 select IMX_HAVE_PLATFORM_MXC_MMC
451 select IMX_HAVE_PLATFORM_MXC_NAND 452 select IMX_HAVE_PLATFORM_MXC_NAND
452 select IMX_HAVE_PLATFORM_MXC_W1 453 select IMX_HAVE_PLATFORM_MXC_W1
453 select MXC_ULPI if USB_ULPI 454 select MXC_ULPI if USB_ULPI
454 help 455 help
455 Include support for Phytec pcm037 platform. This includes 456 Include support for Phytec pcm037 platform. This includes
456 specific configurations for the board and its peripherals. 457 specific configurations for the board and its peripherals.
457 458
458 config MACH_PCM037_EET 459 config MACH_PCM037_EET
459 bool "Support pcm037 EET board extensions" 460 bool "Support pcm037 EET board extensions"
460 depends on MACH_PCM037 461 depends on MACH_PCM037
461 select IMX_HAVE_PLATFORM_GPIO_KEYS 462 select IMX_HAVE_PLATFORM_GPIO_KEYS
462 select IMX_HAVE_PLATFORM_SPI_IMX 463 select IMX_HAVE_PLATFORM_SPI_IMX
463 help 464 help
464 Add support for PCM037 EET baseboard extensions. If you are using the 465 Add support for PCM037 EET baseboard extensions. If you are using the
465 OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel 466 OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel
466 command-line parameter. 467 command-line parameter.
467 468
468 config MACH_MX31_3DS 469 config MACH_MX31_3DS
469 bool "Support MX31PDK (3DS)" 470 bool "Support MX31PDK (3DS)"
470 select SOC_IMX31 471 select SOC_IMX31
471 select MXC_DEBUG_BOARD 472 select MXC_DEBUG_BOARD
472 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 473 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
473 select IMX_HAVE_PLATFORM_IMX2_WDT 474 select IMX_HAVE_PLATFORM_IMX2_WDT
474 select IMX_HAVE_PLATFORM_IMX_I2C 475 select IMX_HAVE_PLATFORM_IMX_I2C
475 select IMX_HAVE_PLATFORM_IMX_KEYPAD 476 select IMX_HAVE_PLATFORM_IMX_KEYPAD
476 select IMX_HAVE_PLATFORM_IMX_SSI 477 select IMX_HAVE_PLATFORM_IMX_SSI
477 select IMX_HAVE_PLATFORM_IMX_UART 478 select IMX_HAVE_PLATFORM_IMX_UART
478 select IMX_HAVE_PLATFORM_IPU_CORE 479 select IMX_HAVE_PLATFORM_IPU_CORE
479 select IMX_HAVE_PLATFORM_MXC_EHCI 480 select IMX_HAVE_PLATFORM_MXC_EHCI
480 select IMX_HAVE_PLATFORM_MXC_MMC 481 select IMX_HAVE_PLATFORM_MXC_MMC
481 select IMX_HAVE_PLATFORM_MXC_NAND 482 select IMX_HAVE_PLATFORM_MXC_NAND
482 select IMX_HAVE_PLATFORM_SPI_IMX 483 select IMX_HAVE_PLATFORM_SPI_IMX
483 select MXC_ULPI if USB_ULPI 484 select MXC_ULPI if USB_ULPI
484 help 485 help
485 Include support for MX31PDK (3DS) platform. This includes specific 486 Include support for MX31PDK (3DS) platform. This includes specific
486 configurations for the board and its peripherals. 487 configurations for the board and its peripherals.
487 488
488 config MACH_MX31_3DS_MXC_NAND_USE_BBT 489 config MACH_MX31_3DS_MXC_NAND_USE_BBT
489 bool "Make the MXC NAND driver use the in flash Bad Block Table" 490 bool "Make the MXC NAND driver use the in flash Bad Block Table"
490 depends on MACH_MX31_3DS 491 depends on MACH_MX31_3DS
491 depends on MTD_NAND_MXC 492 depends on MTD_NAND_MXC
492 help 493 help
493 Enable this if you want that the MXC NAND driver uses the in flash 494 Enable this if you want that the MXC NAND driver uses the in flash
494 Bad Block Table to know what blocks are bad instead of scanning the 495 Bad Block Table to know what blocks are bad instead of scanning the
495 entire flash looking for bad block markers. 496 entire flash looking for bad block markers.
496 497
497 config MACH_MX31MOBOARD 498 config MACH_MX31MOBOARD
498 bool "Support mx31moboard platforms (EPFL Mobots group)" 499 bool "Support mx31moboard platforms (EPFL Mobots group)"
499 select SOC_IMX31 500 select SOC_IMX31
500 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 501 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
501 select IMX_HAVE_PLATFORM_IMX2_WDT 502 select IMX_HAVE_PLATFORM_IMX2_WDT
502 select IMX_HAVE_PLATFORM_IMX_I2C 503 select IMX_HAVE_PLATFORM_IMX_I2C
503 select IMX_HAVE_PLATFORM_IMX_SSI 504 select IMX_HAVE_PLATFORM_IMX_SSI
504 select IMX_HAVE_PLATFORM_IMX_UART 505 select IMX_HAVE_PLATFORM_IMX_UART
505 select IMX_HAVE_PLATFORM_IPU_CORE 506 select IMX_HAVE_PLATFORM_IPU_CORE
506 select IMX_HAVE_PLATFORM_MXC_EHCI 507 select IMX_HAVE_PLATFORM_MXC_EHCI
507 select IMX_HAVE_PLATFORM_MXC_MMC 508 select IMX_HAVE_PLATFORM_MXC_MMC
508 select IMX_HAVE_PLATFORM_SPI_IMX 509 select IMX_HAVE_PLATFORM_SPI_IMX
509 select LEDS_GPIO_REGISTER 510 select LEDS_GPIO_REGISTER
510 select MXC_ULPI if USB_ULPI 511 select MXC_ULPI if USB_ULPI
511 help 512 help
512 Include support for mx31moboard platform. This includes specific 513 Include support for mx31moboard platform. This includes specific
513 configurations for the board and its peripherals. 514 configurations for the board and its peripherals.
514 515
515 config MACH_QONG 516 config MACH_QONG
516 bool "Support Dave/DENX QongEVB-LITE platform" 517 bool "Support Dave/DENX QongEVB-LITE platform"
517 select SOC_IMX31 518 select SOC_IMX31
518 select IMX_HAVE_PLATFORM_IMX_UART 519 select IMX_HAVE_PLATFORM_IMX_UART
519 select IMX_HAVE_PLATFORM_IMX2_WDT 520 select IMX_HAVE_PLATFORM_IMX2_WDT
520 help 521 help
521 Include support for Dave/DENX QongEVB-LITE platform. This includes 522 Include support for Dave/DENX QongEVB-LITE platform. This includes
522 specific configurations for the board and its peripherals. 523 specific configurations for the board and its peripherals.
523 524
524 config MACH_ARMADILLO5X0 525 config MACH_ARMADILLO5X0
525 bool "Support Atmark Armadillo-500 Development Base Board" 526 bool "Support Atmark Armadillo-500 Development Base Board"
526 select SOC_IMX31 527 select SOC_IMX31
527 select IMX_HAVE_PLATFORM_GPIO_KEYS 528 select IMX_HAVE_PLATFORM_GPIO_KEYS
528 select IMX_HAVE_PLATFORM_IMX_I2C 529 select IMX_HAVE_PLATFORM_IMX_I2C
529 select IMX_HAVE_PLATFORM_IMX_UART 530 select IMX_HAVE_PLATFORM_IMX_UART
530 select IMX_HAVE_PLATFORM_IPU_CORE 531 select IMX_HAVE_PLATFORM_IPU_CORE
531 select IMX_HAVE_PLATFORM_MXC_EHCI 532 select IMX_HAVE_PLATFORM_MXC_EHCI
532 select IMX_HAVE_PLATFORM_MXC_MMC 533 select IMX_HAVE_PLATFORM_MXC_MMC
533 select IMX_HAVE_PLATFORM_MXC_NAND 534 select IMX_HAVE_PLATFORM_MXC_NAND
534 select MXC_ULPI if USB_ULPI 535 select MXC_ULPI if USB_ULPI
535 help 536 help
536 Include support for Atmark Armadillo-500 platform. This includes 537 Include support for Atmark Armadillo-500 platform. This includes
537 specific configurations for the board and its peripherals. 538 specific configurations for the board and its peripherals.
538 539
539 config MACH_KZM_ARM11_01 540 config MACH_KZM_ARM11_01
540 bool "Support KZM-ARM11-01(Kyoto Microcomputer)" 541 bool "Support KZM-ARM11-01(Kyoto Microcomputer)"
541 select SOC_IMX31 542 select SOC_IMX31
542 select IMX_HAVE_PLATFORM_IMX_UART 543 select IMX_HAVE_PLATFORM_IMX_UART
543 help 544 help
544 Include support for KZM-ARM11-01. This includes specific 545 Include support for KZM-ARM11-01. This includes specific
545 configurations for the board and its peripherals. 546 configurations for the board and its peripherals.
546 547
547 config MACH_BUG 548 config MACH_BUG
548 bool "Support Buglabs BUGBase platform" 549 bool "Support Buglabs BUGBase platform"
549 select SOC_IMX31 550 select SOC_IMX31
550 select IMX_HAVE_PLATFORM_IMX_UART 551 select IMX_HAVE_PLATFORM_IMX_UART
551 default y 552 default y
552 help 553 help
553 Include support for BUGBase 1.3 platform. This includes specific 554 Include support for BUGBase 1.3 platform. This includes specific
554 configurations for the board and its peripherals. 555 configurations for the board and its peripherals.
555 556
556 config MACH_IMX31_DT 557 config MACH_IMX31_DT
557 bool "Support i.MX31 platforms from device tree" 558 bool "Support i.MX31 platforms from device tree"
558 select SOC_IMX31 559 select SOC_IMX31
559 help 560 help
560 Include support for Freescale i.MX31 based platforms 561 Include support for Freescale i.MX31 based platforms
561 using the device tree for discovery. 562 using the device tree for discovery.
562 563
563 comment "MX35 platforms:" 564 comment "MX35 platforms:"
564 565
565 config MACH_PCM043 566 config MACH_PCM043
566 bool "Support Phytec pcm043 (i.MX35) platforms" 567 bool "Support Phytec pcm043 (i.MX35) platforms"
567 select SOC_IMX35 568 select SOC_IMX35
568 select IMX_HAVE_PLATFORM_FLEXCAN 569 select IMX_HAVE_PLATFORM_FLEXCAN
569 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 570 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
570 select IMX_HAVE_PLATFORM_IMX2_WDT 571 select IMX_HAVE_PLATFORM_IMX2_WDT
571 select IMX_HAVE_PLATFORM_IMX_I2C 572 select IMX_HAVE_PLATFORM_IMX_I2C
572 select IMX_HAVE_PLATFORM_IMX_SSI 573 select IMX_HAVE_PLATFORM_IMX_SSI
573 select IMX_HAVE_PLATFORM_IMX_UART 574 select IMX_HAVE_PLATFORM_IMX_UART
574 select IMX_HAVE_PLATFORM_IPU_CORE 575 select IMX_HAVE_PLATFORM_IPU_CORE
575 select IMX_HAVE_PLATFORM_MXC_EHCI 576 select IMX_HAVE_PLATFORM_MXC_EHCI
576 select IMX_HAVE_PLATFORM_MXC_NAND 577 select IMX_HAVE_PLATFORM_MXC_NAND
577 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 578 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
578 select MXC_ULPI if USB_ULPI 579 select MXC_ULPI if USB_ULPI
579 help 580 help
580 Include support for Phytec pcm043 platform. This includes 581 Include support for Phytec pcm043 platform. This includes
581 specific configurations for the board and its peripherals. 582 specific configurations for the board and its peripherals.
582 583
583 config MACH_MX35_3DS 584 config MACH_MX35_3DS
584 bool "Support MX35PDK platform" 585 bool "Support MX35PDK platform"
585 select SOC_IMX35 586 select SOC_IMX35
586 select MXC_DEBUG_BOARD 587 select MXC_DEBUG_BOARD
587 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 588 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
588 select IMX_HAVE_PLATFORM_IMX2_WDT 589 select IMX_HAVE_PLATFORM_IMX2_WDT
589 select IMX_HAVE_PLATFORM_IMX_FB 590 select IMX_HAVE_PLATFORM_IMX_FB
590 select IMX_HAVE_PLATFORM_IMX_I2C 591 select IMX_HAVE_PLATFORM_IMX_I2C
591 select IMX_HAVE_PLATFORM_IMX_UART 592 select IMX_HAVE_PLATFORM_IMX_UART
592 select IMX_HAVE_PLATFORM_IPU_CORE 593 select IMX_HAVE_PLATFORM_IPU_CORE
593 select IMX_HAVE_PLATFORM_MXC_EHCI 594 select IMX_HAVE_PLATFORM_MXC_EHCI
594 select IMX_HAVE_PLATFORM_MXC_NAND 595 select IMX_HAVE_PLATFORM_MXC_NAND
595 select IMX_HAVE_PLATFORM_MXC_RTC 596 select IMX_HAVE_PLATFORM_MXC_RTC
596 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 597 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
597 help 598 help
598 Include support for MX35PDK platform. This includes specific 599 Include support for MX35PDK platform. This includes specific
599 configurations for the board and its peripherals. 600 configurations for the board and its peripherals.
600 601
601 config MACH_EUKREA_CPUIMX35SD 602 config MACH_EUKREA_CPUIMX35SD
602 bool "Support Eukrea CPUIMX35 Platform" 603 bool "Support Eukrea CPUIMX35 Platform"
603 select SOC_IMX35 604 select SOC_IMX35
604 select IMX_HAVE_PLATFORM_FLEXCAN 605 select IMX_HAVE_PLATFORM_FLEXCAN
605 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 606 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
606 select IMX_HAVE_PLATFORM_IMX2_WDT 607 select IMX_HAVE_PLATFORM_IMX2_WDT
607 select IMX_HAVE_PLATFORM_IMX_I2C 608 select IMX_HAVE_PLATFORM_IMX_I2C
608 select IMX_HAVE_PLATFORM_IMX_UART 609 select IMX_HAVE_PLATFORM_IMX_UART
609 select IMX_HAVE_PLATFORM_MXC_EHCI 610 select IMX_HAVE_PLATFORM_MXC_EHCI
610 select IMX_HAVE_PLATFORM_MXC_NAND 611 select IMX_HAVE_PLATFORM_MXC_NAND
611 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 612 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
612 select MXC_ULPI if USB_ULPI 613 select MXC_ULPI if USB_ULPI
613 help 614 help
614 Include support for Eukrea CPUIMX35 platform. This includes 615 Include support for Eukrea CPUIMX35 platform. This includes
615 specific configurations for the board and its peripherals. 616 specific configurations for the board and its peripherals.
616 617
617 choice 618 choice
618 prompt "Baseboard" 619 prompt "Baseboard"
619 depends on MACH_EUKREA_CPUIMX35SD 620 depends on MACH_EUKREA_CPUIMX35SD
620 default MACH_EUKREA_MBIMXSD35_BASEBOARD 621 default MACH_EUKREA_MBIMXSD35_BASEBOARD
621 622
622 config MACH_EUKREA_MBIMXSD35_BASEBOARD 623 config MACH_EUKREA_MBIMXSD35_BASEBOARD
623 bool "Eukrea MBIMXSD development board" 624 bool "Eukrea MBIMXSD development board"
624 select IMX_HAVE_PLATFORM_GPIO_KEYS 625 select IMX_HAVE_PLATFORM_GPIO_KEYS
625 select IMX_HAVE_PLATFORM_IMX_SSI 626 select IMX_HAVE_PLATFORM_IMX_SSI
626 select IMX_HAVE_PLATFORM_IPU_CORE 627 select IMX_HAVE_PLATFORM_IPU_CORE
627 select IMX_HAVE_PLATFORM_SPI_IMX 628 select IMX_HAVE_PLATFORM_SPI_IMX
628 select LEDS_GPIO_REGISTER 629 select LEDS_GPIO_REGISTER
629 help 630 help
630 This adds board specific devices that can be found on Eukrea's 631 This adds board specific devices that can be found on Eukrea's
631 MBIMXSD evaluation board. 632 MBIMXSD evaluation board.
632 633
633 endchoice 634 endchoice
634 635
635 config MACH_VPR200 636 config MACH_VPR200
636 bool "Support VPR200 platform" 637 bool "Support VPR200 platform"
637 select SOC_IMX35 638 select SOC_IMX35
638 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 639 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
639 select IMX_HAVE_PLATFORM_GPIO_KEYS 640 select IMX_HAVE_PLATFORM_GPIO_KEYS
640 select IMX_HAVE_PLATFORM_IMX2_WDT 641 select IMX_HAVE_PLATFORM_IMX2_WDT
641 select IMX_HAVE_PLATFORM_IMX_UART 642 select IMX_HAVE_PLATFORM_IMX_UART
642 select IMX_HAVE_PLATFORM_IMX_I2C 643 select IMX_HAVE_PLATFORM_IMX_I2C
643 select IMX_HAVE_PLATFORM_IPU_CORE 644 select IMX_HAVE_PLATFORM_IPU_CORE
644 select IMX_HAVE_PLATFORM_MXC_EHCI 645 select IMX_HAVE_PLATFORM_MXC_EHCI
645 select IMX_HAVE_PLATFORM_MXC_NAND 646 select IMX_HAVE_PLATFORM_MXC_NAND
646 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 647 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
647 help 648 help
648 Include support for VPR200 platform. This includes specific 649 Include support for VPR200 platform. This includes specific
649 configurations for the board and its peripherals. 650 configurations for the board and its peripherals.
650 651
651 comment "i.MX5 platforms:" 652 comment "i.MX5 platforms:"
652 653
653 config MACH_MX50_RDP 654 config MACH_MX50_RDP
654 bool "Support MX50 reference design platform" 655 bool "Support MX50 reference design platform"
655 depends on BROKEN 656 depends on BROKEN
656 select SOC_IMX50 657 select SOC_IMX50
657 select IMX_HAVE_PLATFORM_IMX_I2C 658 select IMX_HAVE_PLATFORM_IMX_I2C
658 select IMX_HAVE_PLATFORM_IMX_UART 659 select IMX_HAVE_PLATFORM_IMX_UART
659 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 660 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
660 select IMX_HAVE_PLATFORM_SPI_IMX 661 select IMX_HAVE_PLATFORM_SPI_IMX
661 help 662 help
662 Include support for MX50 reference design platform (RDP) board. This 663 Include support for MX50 reference design platform (RDP) board. This
663 includes specific configurations for the board and its peripherals. 664 includes specific configurations for the board and its peripherals.
664 665
665 comment "i.MX51 machines:" 666 comment "i.MX51 machines:"
666 667
667 config MACH_IMX51_DT 668 config MACH_IMX51_DT
668 bool "Support i.MX51 platforms from device tree" 669 bool "Support i.MX51 platforms from device tree"
669 select SOC_IMX51 670 select SOC_IMX51
670 select MACH_MX51_BABBAGE 671 select MACH_MX51_BABBAGE
671 help 672 help
672 Include support for Freescale i.MX51 based platforms 673 Include support for Freescale i.MX51 based platforms
673 using the device tree for discovery 674 using the device tree for discovery
674 675
675 config MACH_MX51_BABBAGE 676 config MACH_MX51_BABBAGE
676 bool "Support MX51 BABBAGE platforms" 677 bool "Support MX51 BABBAGE platforms"
677 select SOC_IMX51 678 select SOC_IMX51
678 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 679 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
679 select IMX_HAVE_PLATFORM_IMX2_WDT 680 select IMX_HAVE_PLATFORM_IMX2_WDT
680 select IMX_HAVE_PLATFORM_IMX_I2C 681 select IMX_HAVE_PLATFORM_IMX_I2C
681 select IMX_HAVE_PLATFORM_IMX_UART 682 select IMX_HAVE_PLATFORM_IMX_UART
682 select IMX_HAVE_PLATFORM_MXC_EHCI 683 select IMX_HAVE_PLATFORM_MXC_EHCI
683 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 684 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
684 select IMX_HAVE_PLATFORM_SPI_IMX 685 select IMX_HAVE_PLATFORM_SPI_IMX
685 help 686 help
686 Include support for MX51 Babbage platform, also known as MX51EVK in 687 Include support for MX51 Babbage platform, also known as MX51EVK in
687 u-boot. This includes specific configurations for the board and its 688 u-boot. This includes specific configurations for the board and its
688 peripherals. 689 peripherals.
689 690
690 config MACH_MX51_3DS 691 config MACH_MX51_3DS
691 bool "Support MX51PDK (3DS)" 692 bool "Support MX51PDK (3DS)"
692 select SOC_IMX51 693 select SOC_IMX51
693 select IMX_HAVE_PLATFORM_IMX2_WDT 694 select IMX_HAVE_PLATFORM_IMX2_WDT
694 select IMX_HAVE_PLATFORM_IMX_KEYPAD 695 select IMX_HAVE_PLATFORM_IMX_KEYPAD
695 select IMX_HAVE_PLATFORM_IMX_UART 696 select IMX_HAVE_PLATFORM_IMX_UART
696 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 697 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
697 select IMX_HAVE_PLATFORM_SPI_IMX 698 select IMX_HAVE_PLATFORM_SPI_IMX
698 select MXC_DEBUG_BOARD 699 select MXC_DEBUG_BOARD
699 help 700 help
700 Include support for MX51PDK (3DS) platform. This includes specific 701 Include support for MX51PDK (3DS) platform. This includes specific
701 configurations for the board and its peripherals. 702 configurations for the board and its peripherals.
702 703
703 config MACH_EUKREA_CPUIMX51SD 704 config MACH_EUKREA_CPUIMX51SD
704 bool "Support Eukrea CPUIMX51SD module" 705 bool "Support Eukrea CPUIMX51SD module"
705 select SOC_IMX51 706 select SOC_IMX51
706 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 707 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
707 select IMX_HAVE_PLATFORM_IMX_I2C 708 select IMX_HAVE_PLATFORM_IMX_I2C
708 select IMX_HAVE_PLATFORM_IMX_UART 709 select IMX_HAVE_PLATFORM_IMX_UART
709 select IMX_HAVE_PLATFORM_IMX2_WDT 710 select IMX_HAVE_PLATFORM_IMX2_WDT
710 select IMX_HAVE_PLATFORM_MXC_EHCI 711 select IMX_HAVE_PLATFORM_MXC_EHCI
711 select IMX_HAVE_PLATFORM_MXC_NAND 712 select IMX_HAVE_PLATFORM_MXC_NAND
712 select IMX_HAVE_PLATFORM_SPI_IMX 713 select IMX_HAVE_PLATFORM_SPI_IMX
713 help 714 help
714 Include support for Eukrea CPUIMX51SD platform. This includes 715 Include support for Eukrea CPUIMX51SD platform. This includes
715 specific configurations for the module and its peripherals. 716 specific configurations for the module and its peripherals.
716 717
717 choice 718 choice
718 prompt "Baseboard" 719 prompt "Baseboard"
719 depends on MACH_EUKREA_CPUIMX51SD 720 depends on MACH_EUKREA_CPUIMX51SD
720 default MACH_EUKREA_MBIMXSD51_BASEBOARD 721 default MACH_EUKREA_MBIMXSD51_BASEBOARD
721 722
722 config MACH_EUKREA_MBIMXSD51_BASEBOARD 723 config MACH_EUKREA_MBIMXSD51_BASEBOARD
723 prompt "Eukrea MBIMXSD development board" 724 prompt "Eukrea MBIMXSD development board"
724 bool 725 bool
725 select IMX_HAVE_PLATFORM_IMX_SSI 726 select IMX_HAVE_PLATFORM_IMX_SSI
726 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 727 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
727 select LEDS_GPIO_REGISTER 728 select LEDS_GPIO_REGISTER
728 help 729 help
729 This adds board specific devices that can be found on Eukrea's 730 This adds board specific devices that can be found on Eukrea's
730 MBIMXSD evaluation board. 731 MBIMXSD evaluation board.
731 732
732 endchoice 733 endchoice
733 734
734 comment "Device tree only" 735 comment "Device tree only"
735 736
736 config SOC_IMX53 737 config SOC_IMX53
737 bool "i.MX53 support" 738 bool "i.MX53 support"
738 select SOC_IMX5 739 select SOC_IMX5
739 select ARCH_MX5 740 select ARCH_MX5
740 select ARCH_MX53 741 select ARCH_MX53
741 select HAVE_CAN_FLEXCAN if CAN 742 select HAVE_CAN_FLEXCAN if CAN
742 select PINCTRL 743 select PINCTRL
743 select PINCTRL_IMX53 744 select PINCTRL_IMX53
744 745
745 help 746 help
746 This enables support for Freescale i.MX53 processor. 747 This enables support for Freescale i.MX53 processor.
747 748
748 config SOC_IMX6Q 749 config SOC_IMX6Q
749 bool "i.MX6 Quad support" 750 bool "i.MX6 Quad support"
750 select ARM_CPU_SUSPEND if PM 751 select ARM_CPU_SUSPEND if PM
751 select ARM_GIC 752 select ARM_GIC
752 select COMMON_CLK 753 select COMMON_CLK
753 select CPU_V7 754 select CPU_V7
754 select HAVE_ARM_SCU 755 select HAVE_ARM_SCU
755 select HAVE_CAN_FLEXCAN if CAN 756 select HAVE_CAN_FLEXCAN if CAN
756 select HAVE_IMX_GPC 757 select HAVE_IMX_GPC
757 select HAVE_IMX_MMDC 758 select HAVE_IMX_MMDC
758 select HAVE_IMX_SRC 759 select HAVE_IMX_SRC
759 select HAVE_SMP 760 select HAVE_SMP
760 select MFD_ANATOP 761 select MFD_ANATOP
761 select PINCTRL 762 select PINCTRL
762 select PINCTRL_IMX6Q 763 select PINCTRL_IMX6Q
763 764
764 help 765 help
765 This enables support for Freescale i.MX6 Quad processor. 766 This enables support for Freescale i.MX6 Quad processor.
766 767
767 endif 768 endif
768 769
arch/arm/mach-imx/mach-mx27_3ds.c
Diff comments   View file @ 95360fd
1 /* 1 /*
2 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 * 3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com> 4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or 8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version. 9 * (at your option) any later version.
10 * 10 *
11 * This program is distributed in the hope that it will be useful, 11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 */ 15 */
16 16
17 /* 17 /*
18 * This machine is known as: 18 * This machine is known as:
19 * - i.MX27 3-Stack Development System 19 * - i.MX27 3-Stack Development System
20 * - i.MX27 Platform Development Kit (i.MX27 PDK) 20 * - i.MX27 Platform Development Kit (i.MX27 PDK)
21 */ 21 */
22 22
23 #include <linux/platform_device.h> 23 #include <linux/platform_device.h>
24 #include <linux/gpio.h> 24 #include <linux/gpio.h>
25 #include <linux/irq.h> 25 #include <linux/irq.h>
26 #include <linux/usb/otg.h> 26 #include <linux/usb/otg.h>
27 #include <linux/usb/ulpi.h> 27 #include <linux/usb/ulpi.h>
28 #include <linux/delay.h> 28 #include <linux/delay.h>
29 #include <linux/mfd/mc13783.h> 29 #include <linux/mfd/mc13783.h>
30 #include <linux/spi/spi.h> 30 #include <linux/spi/spi.h>
31 #include <linux/regulator/machine.h> 31 #include <linux/regulator/machine.h>
32 #include <linux/spi/l4f00242t03.h> 32 #include <linux/spi/l4f00242t03.h>
33 33
34 #include <media/soc_camera.h> 34 #include <media/soc_camera.h>
35 35
36 #include <asm/mach-types.h> 36 #include <asm/mach-types.h>
37 #include <asm/mach/arch.h> 37 #include <asm/mach/arch.h>
38 #include <asm/mach/time.h> 38 #include <asm/mach/time.h>
39 #include <mach/hardware.h> 39 #include <mach/hardware.h>
40 #include <mach/common.h> 40 #include <mach/common.h>
41 #include <mach/iomux-mx27.h> 41 #include <mach/iomux-mx27.h>
42 #include <mach/ulpi.h> 42 #include <mach/ulpi.h>
43 #include <mach/3ds_debugboard.h> 43 #include <mach/3ds_debugboard.h>
44 44
45 #include "devices-imx27.h" 45 #include "devices-imx27.h"
46 46
47 #define SD1_EN_GPIO IMX_GPIO_NR(2, 25) 47 #define SD1_EN_GPIO IMX_GPIO_NR(2, 25)
48 #define OTG_PHY_RESET_GPIO IMX_GPIO_NR(2, 23) 48 #define OTG_PHY_RESET_GPIO IMX_GPIO_NR(2, 23)
49 #define SPI2_SS0 IMX_GPIO_NR(4, 21) 49 #define SPI2_SS0 IMX_GPIO_NR(4, 21)
50 #define PMIC_INT IMX_GPIO_NR(3, 14) 50 #define PMIC_INT IMX_GPIO_NR(3, 14)
51 #define SPI1_SS0 IMX_GPIO_NR(4, 28) 51 #define SPI1_SS0 IMX_GPIO_NR(4, 28)
52 #define SD1_CD IMX_GPIO_NR(2, 26) 52 #define SD1_CD IMX_GPIO_NR(2, 26)
53 #define LCD_RESET IMX_GPIO_NR(1, 3) 53 #define LCD_RESET IMX_GPIO_NR(1, 3)
54 #define LCD_ENABLE IMX_GPIO_NR(1, 31) 54 #define LCD_ENABLE IMX_GPIO_NR(1, 31)
55 #define CSI_PWRDWN IMX_GPIO_NR(4, 19) 55 #define CSI_PWRDWN IMX_GPIO_NR(4, 19)
56 #define CSI_RESET IMX_GPIO_NR(3, 6) 56 #define CSI_RESET IMX_GPIO_NR(3, 6)
57 57
58 static const int mx27pdk_pins[] __initconst = { 58 static const int mx27pdk_pins[] __initconst = {
59 /* UART1 */ 59 /* UART1 */
60 PE12_PF_UART1_TXD, 60 PE12_PF_UART1_TXD,
61 PE13_PF_UART1_RXD, 61 PE13_PF_UART1_RXD,
62 PE14_PF_UART1_CTS, 62 PE14_PF_UART1_CTS,
63 PE15_PF_UART1_RTS, 63 PE15_PF_UART1_RTS,
64 /* FEC */ 64 /* FEC */
65 PD0_AIN_FEC_TXD0, 65 PD0_AIN_FEC_TXD0,
66 PD1_AIN_FEC_TXD1, 66 PD1_AIN_FEC_TXD1,
67 PD2_AIN_FEC_TXD2, 67 PD2_AIN_FEC_TXD2,
68 PD3_AIN_FEC_TXD3, 68 PD3_AIN_FEC_TXD3,
69 PD4_AOUT_FEC_RX_ER, 69 PD4_AOUT_FEC_RX_ER,
70 PD5_AOUT_FEC_RXD1, 70 PD5_AOUT_FEC_RXD1,
71 PD6_AOUT_FEC_RXD2, 71 PD6_AOUT_FEC_RXD2,
72 PD7_AOUT_FEC_RXD3, 72 PD7_AOUT_FEC_RXD3,
73 PD8_AF_FEC_MDIO, 73 PD8_AF_FEC_MDIO,
74 PD9_AIN_FEC_MDC, 74 PD9_AIN_FEC_MDC,
75 PD10_AOUT_FEC_CRS, 75 PD10_AOUT_FEC_CRS,
76 PD11_AOUT_FEC_TX_CLK, 76 PD11_AOUT_FEC_TX_CLK,
77 PD12_AOUT_FEC_RXD0, 77 PD12_AOUT_FEC_RXD0,
78 PD13_AOUT_FEC_RX_DV, 78 PD13_AOUT_FEC_RX_DV,
79 PD14_AOUT_FEC_RX_CLK, 79 PD14_AOUT_FEC_RX_CLK,
80 PD15_AOUT_FEC_COL, 80 PD15_AOUT_FEC_COL,
81 PD16_AIN_FEC_TX_ER, 81 PD16_AIN_FEC_TX_ER,
82 PF23_AIN_FEC_TX_EN, 82 PF23_AIN_FEC_TX_EN,
83 /* SDHC1 */ 83 /* SDHC1 */
84 PE18_PF_SD1_D0, 84 PE18_PF_SD1_D0,
85 PE19_PF_SD1_D1, 85 PE19_PF_SD1_D1,
86 PE20_PF_SD1_D2, 86 PE20_PF_SD1_D2,
87 PE21_PF_SD1_D3, 87 PE21_PF_SD1_D3,
88 PE22_PF_SD1_CMD, 88 PE22_PF_SD1_CMD,
89 PE23_PF_SD1_CLK, 89 PE23_PF_SD1_CLK,
90 SD1_EN_GPIO | GPIO_GPIO | GPIO_OUT, 90 SD1_EN_GPIO | GPIO_GPIO | GPIO_OUT,
91 /* OTG */ 91 /* OTG */
92 OTG_PHY_RESET_GPIO | GPIO_GPIO | GPIO_OUT, 92 OTG_PHY_RESET_GPIO | GPIO_GPIO | GPIO_OUT,
93 PC7_PF_USBOTG_DATA5, 93 PC7_PF_USBOTG_DATA5,
94 PC8_PF_USBOTG_DATA6, 94 PC8_PF_USBOTG_DATA6,
95 PC9_PF_USBOTG_DATA0, 95 PC9_PF_USBOTG_DATA0,
96 PC10_PF_USBOTG_DATA2, 96 PC10_PF_USBOTG_DATA2,
97 PC11_PF_USBOTG_DATA1, 97 PC11_PF_USBOTG_DATA1,
98 PC12_PF_USBOTG_DATA4, 98 PC12_PF_USBOTG_DATA4,
99 PC13_PF_USBOTG_DATA3, 99 PC13_PF_USBOTG_DATA3,
100 PE0_PF_USBOTG_NXT, 100 PE0_PF_USBOTG_NXT,
101 PE1_PF_USBOTG_STP, 101 PE1_PF_USBOTG_STP,
102 PE2_PF_USBOTG_DIR, 102 PE2_PF_USBOTG_DIR,
103 PE24_PF_USBOTG_CLK, 103 PE24_PF_USBOTG_CLK,
104 PE25_PF_USBOTG_DATA7, 104 PE25_PF_USBOTG_DATA7,
105 /* CSPI1 */ 105 /* CSPI1 */
106 PD31_PF_CSPI1_MOSI, 106 PD31_PF_CSPI1_MOSI,
107 PD30_PF_CSPI1_MISO, 107 PD30_PF_CSPI1_MISO,
108 PD29_PF_CSPI1_SCLK, 108 PD29_PF_CSPI1_SCLK,
109 PD25_PF_CSPI1_RDY, 109 PD25_PF_CSPI1_RDY,
110 SPI1_SS0 | GPIO_GPIO | GPIO_OUT, 110 SPI1_SS0 | GPIO_GPIO | GPIO_OUT,
111 /* CSPI2 */ 111 /* CSPI2 */
112 PD22_PF_CSPI2_SCLK, 112 PD22_PF_CSPI2_SCLK,
113 PD23_PF_CSPI2_MISO, 113 PD23_PF_CSPI2_MISO,
114 PD24_PF_CSPI2_MOSI, 114 PD24_PF_CSPI2_MOSI,
115 SPI2_SS0 | GPIO_GPIO | GPIO_OUT, 115 SPI2_SS0 | GPIO_GPIO | GPIO_OUT,
116 /* I2C1 */ 116 /* I2C1 */
117 PD17_PF_I2C_DATA, 117 PD17_PF_I2C_DATA,
118 PD18_PF_I2C_CLK, 118 PD18_PF_I2C_CLK,
119 /* PMIC INT */ 119 /* PMIC INT */
120 PMIC_INT | GPIO_GPIO | GPIO_IN, 120 PMIC_INT | GPIO_GPIO | GPIO_IN,
121 /* LCD */ 121 /* LCD */
122 PA5_PF_LSCLK, 122 PA5_PF_LSCLK,
123 PA6_PF_LD0, 123 PA6_PF_LD0,
124 PA7_PF_LD1, 124 PA7_PF_LD1,
125 PA8_PF_LD2, 125 PA8_PF_LD2,
126 PA9_PF_LD3, 126 PA9_PF_LD3,
127 PA10_PF_LD4, 127 PA10_PF_LD4,
128 PA11_PF_LD5, 128 PA11_PF_LD5,
129 PA12_PF_LD6, 129 PA12_PF_LD6,
130 PA13_PF_LD7, 130 PA13_PF_LD7,
131 PA14_PF_LD8, 131 PA14_PF_LD8,
132 PA15_PF_LD9, 132 PA15_PF_LD9,
133 PA16_PF_LD10, 133 PA16_PF_LD10,
134 PA17_PF_LD11, 134 PA17_PF_LD11,
135 PA18_PF_LD12, 135 PA18_PF_LD12,
136 PA19_PF_LD13, 136 PA19_PF_LD13,
137 PA20_PF_LD14, 137 PA20_PF_LD14,
138 PA21_PF_LD15, 138 PA21_PF_LD15,
139 PA22_PF_LD16, 139 PA22_PF_LD16,
140 PA23_PF_LD17, 140 PA23_PF_LD17,
141 PA28_PF_HSYNC, 141 PA28_PF_HSYNC,
142 PA29_PF_VSYNC, 142 PA29_PF_VSYNC,
143 PA30_PF_CONTRAST, 143 PA30_PF_CONTRAST,
144 LCD_ENABLE | GPIO_GPIO | GPIO_OUT, 144 LCD_ENABLE | GPIO_GPIO | GPIO_OUT,
145 LCD_RESET | GPIO_GPIO | GPIO_OUT, 145 LCD_RESET | GPIO_GPIO | GPIO_OUT,
146 /* CSI */ 146 /* CSI */
147 PB10_PF_CSI_D0, 147 PB10_PF_CSI_D0,
148 PB11_PF_CSI_D1, 148 PB11_PF_CSI_D1,
149 PB12_PF_CSI_D2, 149 PB12_PF_CSI_D2,
150 PB13_PF_CSI_D3, 150 PB13_PF_CSI_D3,
151 PB14_PF_CSI_D4, 151 PB14_PF_CSI_D4,
152 PB15_PF_CSI_MCLK, 152 PB15_PF_CSI_MCLK,
153 PB16_PF_CSI_PIXCLK, 153 PB16_PF_CSI_PIXCLK,
154 PB17_PF_CSI_D5, 154 PB17_PF_CSI_D5,
155 PB18_PF_CSI_D6, 155 PB18_PF_CSI_D6,
156 PB19_PF_CSI_D7, 156 PB19_PF_CSI_D7,
157 PB20_PF_CSI_VSYNC, 157 PB20_PF_CSI_VSYNC,
158 PB21_PF_CSI_HSYNC, 158 PB21_PF_CSI_HSYNC,
159 CSI_PWRDWN | GPIO_GPIO | GPIO_OUT, 159 CSI_PWRDWN | GPIO_GPIO | GPIO_OUT,
160 CSI_RESET | GPIO_GPIO | GPIO_OUT, 160 CSI_RESET | GPIO_GPIO | GPIO_OUT,
161 /* SSI4 */
162 PC16_PF_SSI4_FS,
163 PC17_PF_SSI4_RXD,
164 PC18_PF_SSI4_TXD,
165 PC19_PF_SSI4_CLK,
161 }; 166 };
162 167
163 static struct gpio mx27_3ds_camera_gpios[] = { 168 static struct gpio mx27_3ds_camera_gpios[] = {
164 { CSI_PWRDWN, GPIOF_OUT_INIT_HIGH, "camera-power" }, 169 { CSI_PWRDWN, GPIOF_OUT_INIT_HIGH, "camera-power" },
165 { CSI_RESET, GPIOF_OUT_INIT_HIGH, "camera-reset" }, 170 { CSI_RESET, GPIOF_OUT_INIT_HIGH, "camera-reset" },
166 }; 171 };
167 172
168 static const struct imxuart_platform_data uart_pdata __initconst = { 173 static const struct imxuart_platform_data uart_pdata __initconst = {
169 .flags = IMXUART_HAVE_RTSCTS, 174 .flags = IMXUART_HAVE_RTSCTS,
170 }; 175 };
171 176
172 /* 177 /*
173 * Matrix keyboard 178 * Matrix keyboard
174 */ 179 */
175 180
176 static const uint32_t mx27_3ds_keymap[] = { 181 static const uint32_t mx27_3ds_keymap[] = {
177 KEY(0, 0, KEY_UP), 182 KEY(0, 0, KEY_UP),
178 KEY(0, 1, KEY_DOWN), 183 KEY(0, 1, KEY_DOWN),
179 KEY(1, 0, KEY_RIGHT), 184 KEY(1, 0, KEY_RIGHT),
180 KEY(1, 1, KEY_LEFT), 185 KEY(1, 1, KEY_LEFT),
181 KEY(1, 2, KEY_ENTER), 186 KEY(1, 2, KEY_ENTER),
182 KEY(2, 0, KEY_F6), 187 KEY(2, 0, KEY_F6),
183 KEY(2, 1, KEY_F8), 188 KEY(2, 1, KEY_F8),
184 KEY(2, 2, KEY_F9), 189 KEY(2, 2, KEY_F9),
185 KEY(2, 3, KEY_F10), 190 KEY(2, 3, KEY_F10),
186 }; 191 };
187 192
188 static const struct matrix_keymap_data mx27_3ds_keymap_data __initconst = { 193 static const struct matrix_keymap_data mx27_3ds_keymap_data __initconst = {
189 .keymap = mx27_3ds_keymap, 194 .keymap = mx27_3ds_keymap,
190 .keymap_size = ARRAY_SIZE(mx27_3ds_keymap), 195 .keymap_size = ARRAY_SIZE(mx27_3ds_keymap),
191 }; 196 };
192 197
193 static int mx27_3ds_sdhc1_init(struct device *dev, irq_handler_t detect_irq, 198 static int mx27_3ds_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
194 void *data) 199 void *data)
195 { 200 {
196 return request_irq(gpio_to_irq(SD1_CD), detect_irq, 201 return request_irq(gpio_to_irq(SD1_CD), detect_irq,
197 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, "sdhc1-card-detect", data); 202 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, "sdhc1-card-detect", data);
198 } 203 }
199 204
200 static void mx27_3ds_sdhc1_exit(struct device *dev, void *data) 205 static void mx27_3ds_sdhc1_exit(struct device *dev, void *data)
201 { 206 {
202 free_irq(gpio_to_irq(SD1_CD), data); 207 free_irq(gpio_to_irq(SD1_CD), data);
203 } 208 }
204 209
205 static const struct imxmmc_platform_data sdhc1_pdata __initconst = { 210 static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
206 .init = mx27_3ds_sdhc1_init, 211 .init = mx27_3ds_sdhc1_init,
207 .exit = mx27_3ds_sdhc1_exit, 212 .exit = mx27_3ds_sdhc1_exit,
208 }; 213 };
209 214
210 static void mx27_3ds_sdhc1_enable_level_translator(void) 215 static void mx27_3ds_sdhc1_enable_level_translator(void)
211 { 216 {
212 /* Turn on TXB0108 OE pin */ 217 /* Turn on TXB0108 OE pin */
213 gpio_request(SD1_EN_GPIO, "sd1_enable"); 218 gpio_request(SD1_EN_GPIO, "sd1_enable");
214 gpio_direction_output(SD1_EN_GPIO, 1); 219 gpio_direction_output(SD1_EN_GPIO, 1);
215 } 220 }
216 221
217 222
218 static int otg_phy_init(void) 223 static int otg_phy_init(void)
219 { 224 {
220 gpio_request(OTG_PHY_RESET_GPIO, "usb-otg-reset"); 225 gpio_request(OTG_PHY_RESET_GPIO, "usb-otg-reset");
221 gpio_direction_output(OTG_PHY_RESET_GPIO, 0); 226 gpio_direction_output(OTG_PHY_RESET_GPIO, 0);
222 mdelay(1); 227 mdelay(1);
223 gpio_set_value(OTG_PHY_RESET_GPIO, 1); 228 gpio_set_value(OTG_PHY_RESET_GPIO, 1);
224 return 0; 229 return 0;
225 } 230 }
226 231
227 static int mx27_3ds_otg_init(struct platform_device *pdev) 232 static int mx27_3ds_otg_init(struct platform_device *pdev)
228 { 233 {
229 return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); 234 return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
230 } 235 }
231 236
232 static struct mxc_usbh_platform_data otg_pdata __initdata = { 237 static struct mxc_usbh_platform_data otg_pdata __initdata = {
233 .init = mx27_3ds_otg_init, 238 .init = mx27_3ds_otg_init,
234 .portsc = MXC_EHCI_MODE_ULPI, 239 .portsc = MXC_EHCI_MODE_ULPI,
235 }; 240 };
236 241
237 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { 242 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
238 .operating_mode = FSL_USB2_DR_DEVICE, 243 .operating_mode = FSL_USB2_DR_DEVICE,
239 .phy_mode = FSL_USB2_PHY_ULPI, 244 .phy_mode = FSL_USB2_PHY_ULPI,
240 }; 245 };
241 246
242 static bool otg_mode_host __initdata; 247 static bool otg_mode_host __initdata;
243 248
244 static int __init mx27_3ds_otg_mode(char *options) 249 static int __init mx27_3ds_otg_mode(char *options)
245 { 250 {
246 if (!strcmp(options, "host")) 251 if (!strcmp(options, "host"))
247 otg_mode_host = true; 252 otg_mode_host = true;
248 else if (!strcmp(options, "device")) 253 else if (!strcmp(options, "device"))
249 otg_mode_host = false; 254 otg_mode_host = false;
250 else 255 else
251 pr_info("otg_mode neither \"host\" nor \"device\". " 256 pr_info("otg_mode neither \"host\" nor \"device\". "
252 "Defaulting to device\n"); 257 "Defaulting to device\n");
253 return 1; 258 return 1;
254 } 259 }
255 __setup("otg_mode=", mx27_3ds_otg_mode); 260 __setup("otg_mode=", mx27_3ds_otg_mode);
256 261
257 /* Regulators */ 262 /* Regulators */
258 static struct regulator_init_data gpo_init = { 263 static struct regulator_init_data gpo_init = {
259 .constraints = { 264 .constraints = {
260 .boot_on = 1, 265 .boot_on = 1,
261 .always_on = 1, 266 .always_on = 1,
262 } 267 }
263 }; 268 };
264 269
265 static struct regulator_consumer_supply vmmc1_consumers[] = { 270 static struct regulator_consumer_supply vmmc1_consumers[] = {
266 REGULATOR_SUPPLY("vcore", "spi0.0"), 271 REGULATOR_SUPPLY("vcore", "spi0.0"),
267 REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"), 272 REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"),
268 }; 273 };
269 274
270 static struct regulator_init_data vmmc1_init = { 275 static struct regulator_init_data vmmc1_init = {
271 .constraints = { 276 .constraints = {
272 .min_uV = 2800000, 277 .min_uV = 2800000,
273 .max_uV = 2800000, 278 .max_uV = 2800000,
274 .apply_uV = 1, 279 .apply_uV = 1,
275 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | 280 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
276 REGULATOR_CHANGE_STATUS, 281 REGULATOR_CHANGE_STATUS,
277 }, 282 },
278 .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers), 283 .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
279 .consumer_supplies = vmmc1_consumers, 284 .consumer_supplies = vmmc1_consumers,
280 }; 285 };
281 286
282 static struct regulator_consumer_supply vgen_consumers[] = { 287 static struct regulator_consumer_supply vgen_consumers[] = {
283 REGULATOR_SUPPLY("vdd", "spi0.0"), 288 REGULATOR_SUPPLY("vdd", "spi0.0"),
284 }; 289 };
285 290
286 static struct regulator_init_data vgen_init = { 291 static struct regulator_init_data vgen_init = {
287 .constraints = { 292 .constraints = {
288 .min_uV = 1800000, 293 .min_uV = 1800000,
289 .max_uV = 1800000, 294 .max_uV = 1800000,
290 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, 295 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
291 }, 296 },
292 .num_consumer_supplies = ARRAY_SIZE(vgen_consumers), 297 .num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
293 .consumer_supplies = vgen_consumers, 298 .consumer_supplies = vgen_consumers,
294 }; 299 };
295 300
296 static struct regulator_consumer_supply vvib_consumers[] = { 301 static struct regulator_consumer_supply vvib_consumers[] = {
297 REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"), 302 REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"),
298 }; 303 };
299 304
300 static struct regulator_init_data vvib_init = { 305 static struct regulator_init_data vvib_init = {
301 .constraints = { 306 .constraints = {
302 .min_uV = 1300000, 307 .min_uV = 1300000,
303 .max_uV = 1300000, 308 .max_uV = 1300000,
304 .apply_uV = 1, 309 .apply_uV = 1,
305 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | 310 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
306 REGULATOR_CHANGE_STATUS, 311 REGULATOR_CHANGE_STATUS,
307 }, 312 },
308 .num_consumer_supplies = ARRAY_SIZE(vvib_consumers), 313 .num_consumer_supplies = ARRAY_SIZE(vvib_consumers),
309 .consumer_supplies = vvib_consumers, 314 .consumer_supplies = vvib_consumers,
310 }; 315 };
311 316
312 static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = { 317 static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = {
313 { 318 {
314 .id = MC13783_REG_VMMC1, 319 .id = MC13783_REG_VMMC1,
315 .init_data = &vmmc1_init, 320 .init_data = &vmmc1_init,
316 }, { 321 }, {
317 .id = MC13783_REG_VGEN, 322 .id = MC13783_REG_VGEN,
318 .init_data = &vgen_init, 323 .init_data = &vgen_init,
319 }, { 324 }, {
320 .id = MC13783_REG_GPO1, /* Turn on 1.8V */ 325 .id = MC13783_REG_GPO1, /* Turn on 1.8V */
321 .init_data = &gpo_init, 326 .init_data = &gpo_init,
322 }, { 327 }, {
323 .id = MC13783_REG_GPO3, /* Turn on 3.3V */ 328 .id = MC13783_REG_GPO3, /* Turn on 3.3V */
324 .init_data = &gpo_init, 329 .init_data = &gpo_init,
325 }, { 330 }, {
326 .id = MC13783_REG_VVIB, /* Power OV2640 */ 331 .id = MC13783_REG_VVIB, /* Power OV2640 */
327 .init_data = &vvib_init, 332 .init_data = &vvib_init,
328 }, 333 },
329 }; 334 };
330 335
331 /* MC13783 */ 336 /* MC13783 */
337 static struct mc13xxx_codec_platform_data mx27_3ds_codec = {
338 .dac_ssi_port = MC13783_SSI1_PORT,
339 .adc_ssi_port = MC13783_SSI1_PORT,
340 };
341
332 static struct mc13xxx_platform_data mc13783_pdata = { 342 static struct mc13xxx_platform_data mc13783_pdata = {
333 .regulators = { 343 .regulators = {
334 .regulators = mx27_3ds_regulators, 344 .regulators = mx27_3ds_regulators,
335 .num_regulators = ARRAY_SIZE(mx27_3ds_regulators), 345 .num_regulators = ARRAY_SIZE(mx27_3ds_regulators),
336 346
337 }, 347 },
338 .flags = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC, 348 .flags = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC |
349 MC13XXX_USE_CODEC,
350 .codec = &mx27_3ds_codec,
339 }; 351 };
340 352
353 static struct imx_ssi_platform_data mx27_3ds_ssi_pdata = {
354 .flags = IMX_SSI_DMA | IMX_SSI_NET,
355 };
356
341 /* SPI */ 357 /* SPI */
342 static int spi1_chipselect[] = {SPI1_SS0}; 358 static int spi1_chipselect[] = {SPI1_SS0};
343 359
344 static const struct spi_imx_master spi1_pdata __initconst = { 360 static const struct spi_imx_master spi1_pdata __initconst = {
345 .chipselect = spi1_chipselect, 361 .chipselect = spi1_chipselect,
346 .num_chipselect = ARRAY_SIZE(spi1_chipselect), 362 .num_chipselect = ARRAY_SIZE(spi1_chipselect),
347 }; 363 };
348 364
349 static int spi2_chipselect[] = {SPI2_SS0}; 365 static int spi2_chipselect[] = {SPI2_SS0};
350 366
351 static const struct spi_imx_master spi2_pdata __initconst = { 367 static const struct spi_imx_master spi2_pdata __initconst = {
352 .chipselect = spi2_chipselect, 368 .chipselect = spi2_chipselect,
353 .num_chipselect = ARRAY_SIZE(spi2_chipselect), 369 .num_chipselect = ARRAY_SIZE(spi2_chipselect),
354 }; 370 };
355 371
356 static int mx27_3ds_camera_power(struct device *dev, int on) 372 static int mx27_3ds_camera_power(struct device *dev, int on)
357 { 373 {
358 /* enable or disable the camera */ 374 /* enable or disable the camera */
359 pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE"); 375 pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
360 gpio_set_value(CSI_PWRDWN, on ? 0 : 1); 376 gpio_set_value(CSI_PWRDWN, on ? 0 : 1);
361 377
362 if (!on) 378 if (!on)
363 goto out; 379 goto out;
364 380
365 /* If enabled, give a reset impulse */ 381 /* If enabled, give a reset impulse */
366 gpio_set_value(CSI_RESET, 0); 382 gpio_set_value(CSI_RESET, 0);
367 msleep(20); 383 msleep(20);
368 gpio_set_value(CSI_RESET, 1); 384 gpio_set_value(CSI_RESET, 1);
369 msleep(100); 385 msleep(100);
370 386
371 out: 387 out:
372 return 0; 388 return 0;
373 } 389 }
374 390
375 static struct i2c_board_info mx27_3ds_i2c_camera = { 391 static struct i2c_board_info mx27_3ds_i2c_camera = {
376 I2C_BOARD_INFO("ov2640", 0x30), 392 I2C_BOARD_INFO("ov2640", 0x30),
377 }; 393 };
378 394
379 static struct regulator_bulk_data mx27_3ds_camera_regs[] = { 395 static struct regulator_bulk_data mx27_3ds_camera_regs[] = {
380 { .supply = "cmos_vcore" }, 396 { .supply = "cmos_vcore" },
381 { .supply = "cmos_2v8" }, 397 { .supply = "cmos_2v8" },
382 }; 398 };
383 399
384 static struct soc_camera_link iclink_ov2640 = { 400 static struct soc_camera_link iclink_ov2640 = {
385 .bus_id = 0, 401 .bus_id = 0,
386 .board_info = &mx27_3ds_i2c_camera, 402 .board_info = &mx27_3ds_i2c_camera,
387 .i2c_adapter_id = 0, 403 .i2c_adapter_id = 0,
388 .power = mx27_3ds_camera_power, 404 .power = mx27_3ds_camera_power,
389 .regulators = mx27_3ds_camera_regs, 405 .regulators = mx27_3ds_camera_regs,
390 .num_regulators = ARRAY_SIZE(mx27_3ds_camera_regs), 406 .num_regulators = ARRAY_SIZE(mx27_3ds_camera_regs),
391 }; 407 };
392 408
393 static struct platform_device mx27_3ds_ov2640 = { 409 static struct platform_device mx27_3ds_ov2640 = {
394 .name = "soc-camera-pdrv", 410 .name = "soc-camera-pdrv",
395 .id = 0, 411 .id = 0,
396 .dev = { 412 .dev = {
397 .platform_data = &iclink_ov2640, 413 .platform_data = &iclink_ov2640,
398 }, 414 },
399 }; 415 };
400 416
401 static struct imx_fb_videomode mx27_3ds_modes[] = { 417 static struct imx_fb_videomode mx27_3ds_modes[] = {
402 { /* 480x640 @ 60 Hz */ 418 { /* 480x640 @ 60 Hz */
403 .mode = { 419 .mode = {
404 .name = "Epson-VGA", 420 .name = "Epson-VGA",
405 .refresh = 60, 421 .refresh = 60,
406 .xres = 480, 422 .xres = 480,
407 .yres = 640, 423 .yres = 640,
408 .pixclock = 41701, 424 .pixclock = 41701,
409 .left_margin = 20, 425 .left_margin = 20,
410 .right_margin = 41, 426 .right_margin = 41,
411 .upper_margin = 10, 427 .upper_margin = 10,
412 .lower_margin = 5, 428 .lower_margin = 5,
413 .hsync_len = 20, 429 .hsync_len = 20,
414 .vsync_len = 10, 430 .vsync_len = 10,
415 .sync = FB_SYNC_OE_ACT_HIGH | 431 .sync = FB_SYNC_OE_ACT_HIGH |
416 FB_SYNC_CLK_INVERT, 432 FB_SYNC_CLK_INVERT,
417 .vmode = FB_VMODE_NONINTERLACED, 433 .vmode = FB_VMODE_NONINTERLACED,
418 .flag = 0, 434 .flag = 0,
419 }, 435 },
420 .bpp = 16, 436 .bpp = 16,
421 .pcr = 0xFAC08B82, 437 .pcr = 0xFAC08B82,
422 }, 438 },
423 }; 439 };
424 440
425 static const struct imx_fb_platform_data mx27_3ds_fb_data __initconst = { 441 static const struct imx_fb_platform_data mx27_3ds_fb_data __initconst = {
426 .mode = mx27_3ds_modes, 442 .mode = mx27_3ds_modes,
427 .num_modes = ARRAY_SIZE(mx27_3ds_modes), 443 .num_modes = ARRAY_SIZE(mx27_3ds_modes),
428 .pwmr = 0x00A903FF, 444 .pwmr = 0x00A903FF,
429 .lscr1 = 0x00120300, 445 .lscr1 = 0x00120300,
430 .dmacr = 0x00020010, 446 .dmacr = 0x00020010,
431 }; 447 };
432 448
433 /* LCD */ 449 /* LCD */
434 static struct l4f00242t03_pdata mx27_3ds_lcd_pdata = { 450 static struct l4f00242t03_pdata mx27_3ds_lcd_pdata = {
435 .reset_gpio = LCD_RESET, 451 .reset_gpio = LCD_RESET,
436 .data_enable_gpio = LCD_ENABLE, 452 .data_enable_gpio = LCD_ENABLE,
437 }; 453 };
438 454
439 static struct spi_board_info mx27_3ds_spi_devs[] __initdata = { 455 static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
440 { 456 {
441 .modalias = "mc13783", 457 .modalias = "mc13783",
442 .max_speed_hz = 1000000, 458 .max_speed_hz = 1000000,
443 .bus_num = 1, 459 .bus_num = 1,
444 .chip_select = 0, /* SS0 */ 460 .chip_select = 0, /* SS0 */
445 .platform_data = &mc13783_pdata, 461 .platform_data = &mc13783_pdata,
446 /* irq number is run-time assigned */ 462 /* irq number is run-time assigned */
447 .mode = SPI_CS_HIGH, 463 .mode = SPI_CS_HIGH,
448 }, { 464 }, {
449 .modalias = "l4f00242t03", 465 .modalias = "l4f00242t03",
450 .max_speed_hz = 5000000, 466 .max_speed_hz = 5000000,
451 .bus_num = 0, 467 .bus_num = 0,
452 .chip_select = 0, /* SS0 */ 468 .chip_select = 0, /* SS0 */
453 .platform_data = &mx27_3ds_lcd_pdata, 469 .platform_data = &mx27_3ds_lcd_pdata,
454 }, 470 },
455 }; 471 };
456 472
457 static struct platform_device *devices[] __initdata = { 473 static struct platform_device *devices[] __initdata = {
458 &mx27_3ds_ov2640, 474 &mx27_3ds_ov2640,
459 }; 475 };
460 476
461 static const struct mx2_camera_platform_data mx27_3ds_cam_pdata __initconst = { 477 static const struct mx2_camera_platform_data mx27_3ds_cam_pdata __initconst = {
462 .clk = 26000000, 478 .clk = 26000000,
463 }; 479 };
464 480
465 static const struct imxi2c_platform_data mx27_3ds_i2c0_data __initconst = { 481 static const struct imxi2c_platform_data mx27_3ds_i2c0_data __initconst = {
466 .bitrate = 100000, 482 .bitrate = 100000,
467 }; 483 };
468 484
469 static void __init mx27pdk_init(void) 485 static void __init mx27pdk_init(void)
470 { 486 {
471 int ret; 487 int ret;
472 imx27_soc_init(); 488 imx27_soc_init();
473 489
474 mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins), 490 mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
475 "mx27pdk"); 491 "mx27pdk");
476 mx27_3ds_sdhc1_enable_level_translator(); 492 mx27_3ds_sdhc1_enable_level_translator();
477 imx27_add_imx_uart0(&uart_pdata); 493 imx27_add_imx_uart0(&uart_pdata);
478 imx27_add_fec(NULL); 494 imx27_add_fec(NULL);
479 imx27_add_imx_keypad(&mx27_3ds_keymap_data); 495 imx27_add_imx_keypad(&mx27_3ds_keymap_data);
480 imx27_add_mxc_mmc(0, &sdhc1_pdata); 496 imx27_add_mxc_mmc(0, &sdhc1_pdata);
481 imx27_add_imx2_wdt(); 497 imx27_add_imx2_wdt();
482 otg_phy_init(); 498 otg_phy_init();
483 499
484 if (otg_mode_host) { 500 if (otg_mode_host) {
485 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | 501 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
486 ULPI_OTG_DRVVBUS_EXT); 502 ULPI_OTG_DRVVBUS_EXT);
487 503
488 if (otg_pdata.otg) 504 if (otg_pdata.otg)
489 imx27_add_mxc_ehci_otg(&otg_pdata); 505 imx27_add_mxc_ehci_otg(&otg_pdata);
490 } 506 }
491 507
492 if (!otg_mode_host) 508 if (!otg_mode_host)
493 imx27_add_fsl_usb2_udc(&otg_device_pdata); 509 imx27_add_fsl_usb2_udc(&otg_device_pdata);
494 510
495 imx27_add_spi_imx1(&spi2_pdata); 511 imx27_add_spi_imx1(&spi2_pdata);
496 imx27_add_spi_imx0(&spi1_pdata); 512 imx27_add_spi_imx0(&spi1_pdata);
497 mx27_3ds_spi_devs[0].irq = gpio_to_irq(PMIC_INT); 513 mx27_3ds_spi_devs[0].irq = gpio_to_irq(PMIC_INT);
498 spi_register_board_info(mx27_3ds_spi_devs, 514 spi_register_board_info(mx27_3ds_spi_devs,
499 ARRAY_SIZE(mx27_3ds_spi_devs)); 515 ARRAY_SIZE(mx27_3ds_spi_devs));
500 516
501 if (mxc_expio_init(MX27_CS5_BASE_ADDR, IMX_GPIO_NR(3, 28))) 517 if (mxc_expio_init(MX27_CS5_BASE_ADDR, IMX_GPIO_NR(3, 28)))
502 pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n"); 518 pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n");
503 imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data); 519 imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data);
504 platform_add_devices(devices, ARRAY_SIZE(devices)); 520 platform_add_devices(devices, ARRAY_SIZE(devices));
505 imx27_add_imx_fb(&mx27_3ds_fb_data); 521 imx27_add_imx_fb(&mx27_3ds_fb_data);
506 522
507 ret = gpio_request_array(mx27_3ds_camera_gpios, 523 ret = gpio_request_array(mx27_3ds_camera_gpios,
508 ARRAY_SIZE(mx27_3ds_camera_gpios)); 524 ARRAY_SIZE(mx27_3ds_camera_gpios));
509 if (ret) { 525 if (ret) {
510 pr_err("Failed to request camera gpios"); 526 pr_err("Failed to request camera gpios");
511 iclink_ov2640.power = NULL; 527 iclink_ov2640.power = NULL;
512 } 528 }
513 529
514 imx27_add_mx2_camera(&mx27_3ds_cam_pdata); 530 imx27_add_mx2_camera(&mx27_3ds_cam_pdata);
531 imx27_add_imx_ssi(0, &mx27_3ds_ssi_pdata);
532
533 imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0);
515 } 534 }
516 535
517 static void __init mx27pdk_timer_init(void) 536 static void __init mx27pdk_timer_init(void)
518 { 537 {
519 mx27_clocks_init(26000000); 538 mx27_clocks_init(26000000);
520 } 539 }
521 540
522 static struct sys_timer mx27pdk_timer = { 541 static struct sys_timer mx27pdk_timer = {
523 .init = mx27pdk_timer_init, 542 .init = mx27pdk_timer_init,
524 }; 543 };
525 544
526 MACHINE_START(MX27_3DS, "Freescale MX27PDK") 545 MACHINE_START(MX27_3DS, "Freescale MX27PDK")
527 /* maintainer: Freescale Semiconductor, Inc. */ 546 /* maintainer: Freescale Semiconductor, Inc. */
528 .atag_offset = 0x100, 547 .atag_offset = 0x100,
529 .map_io = mx27_map_io, 548 .map_io = mx27_map_io,
530 .init_early = imx27_init_early, 549 .init_early = imx27_init_early,
531 .init_irq = mx27_init_irq, 550 .init_irq = mx27_init_irq,
532 .handle_irq = imx27_handle_irq, 551 .handle_irq = imx27_handle_irq,
533 .timer = &mx27pdk_timer, 552 .timer = &mx27pdk_timer,
534 .init_machine = mx27pdk_init, 553 .init_machine = mx27pdk_init,
535 .restart = mxc_restart, 554 .restart = mxc_restart,
536 MACHINE_END 555 MACHINE_END
537 556
arch/arm/mach-ks8695/Kconfig
Diff comments   View file @ 95360fd
1 if ARCH_KS8695 1 if ARCH_KS8695
2 2
3 menu "Kendin/Micrel KS8695 Implementations" 3 menu "Kendin/Micrel KS8695 Implementations"
4 4
5 config MACH_KS8695 5 config MACH_KS8695
6 bool "KS8695 development board" 6 bool "KS8695 development board"
7 select MIGHT_HAVE_PCI 7 select MIGHT_HAVE_PCI
8 help 8 help
9 Say 'Y' here if you want your kernel to run on the original 9 Say 'Y' here if you want your kernel to run on the original
10 Kendin-Micrel KS8695 development board. 10 Kendin-Micrel KS8695 development board.
11 11
12 config MACH_DSM320 12 config MACH_DSM320
13 bool "DSM-320 Wireless Media Player" 13 bool "DSM-320 Wireless Media Player"
14 help 14 help
15 Say 'Y' here if you want your kernel to run on the D-Link 15 Say 'Y' here if you want your kernel to run on the D-Link
16 DSM-320 Wireless Media Player. 16 DSM-320 Wireless Media Player.
17 17
18 config MACH_ACS5K 18 config MACH_ACS5K
19 bool "Brivo Systems LLC, ACS-5000 Master board" 19 bool "Brivo Systems LLC, ACS-5000 Master board"
20 help 20 help
21 say 'Y' here if you want your kernel to run on the Brivo 21 say 'Y' here if you want your kernel to run on the Brivo
22 Systems LLC, ACS-5000 Master board. 22 Systems LLC, ACS-5000 Master board.
23 23
24 config MACH_LITE300
25 bool "SecureComputing SG300"
26 help
27 Say 'Y' here if you want your kernel to support the
28 SecureComputing / SnapGear SG300 VPN Internet Router.
29 See http://www.securecomputing.com for more details.
30
31 config MACH_SG310
32 bool "McAfee SG310"
33 help
34 Say 'Y' here if you want your kernel to support the
35 McAfee / SnapGear SG310 VPN Internet Router.
36 See http://www.mcafee.com for more details.
37
38 config MACH_SE4200
39 bool "SecureComputing SE4200"
40 help
41 Say 'Y' here if you want your kernel to support the
42 SecureComputing / SnapGear SE4200 Secure Wireless VPN
43 Internet Router.
44 See http://www.securecomputing.com for more details.
45
46 config MACH_CM4002
47 bool "OpenGear CM4002"
48 help
49 Say 'Y' here if you want your kernel to support the OpenGear
50 CM4002 Secure Access Server. See http://www.opengear.com for
51 more details.
52
53 config MACH_CM4008
54 bool "OpenGear CM4008"
55 select MIGHT_HAVE_PCI
56 help
57 Say 'Y' here if you want your kernel to support the OpenGear
58 CM4008 Console Server. See http://www.opengear.com for more
59 details.
60
61 config MACH_CM41xx
62 bool "OpenGear CM41xx"
63 select MIGHT_HAVE_PCI
64 help
65 Say 'Y' here if you want your kernel to support the OpenGear
66 CM4016 or CM4048 Console Servers. See http://www.opengear.com for
67 more details.
68
69 config MACH_IM4004
70 bool "OpenGear IM4004"
71 select MIGHT_HAVE_PCI
72 help
73 Say 'Y' here if you want your kernel to support the OpenGear
74 IM4004 Secure Access Server. See http://www.opengear.com for
75 more details.
76
77 config MACH_IM42xx
78 bool "OpenGear IM42xx"
79 select MIGHT_HAVE_PCI
80 help
81 Say 'Y' here if you want your kernel to support the OpenGear
82 IM4216 or IM4248 Console Servers. See http://www.opengear.com for
83 more details.
84
24 endmenu 85 endmenu
25 86
26 endif 87 endif
27 88
arch/arm/mach-ks8695/Makefile
Diff comments   View file @ 95360fd
1 # arch/arm/mach-ks8695/Makefile 1 # arch/arm/mach-ks8695/Makefile
2 # 2 #
3 # Makefile for KS8695 architecture support 3 # Makefile for KS8695 architecture support
4 # 4 #
5 5
6 obj-y := cpu.o irq.o time.o devices.o 6 obj-y := cpu.o irq.o time.o devices.o
7 obj-m := 7 obj-m :=
8 obj-n := 8 obj-n :=
9 obj- := 9 obj- :=
10 10
11 # PCI support is optional 11 # PCI support is optional
12 obj-$(CONFIG_PCI) += pci.o 12 obj-$(CONFIG_PCI) += pci.o
13 13
14 # Board-specific support 14 # Board-specific support
15 obj-$(CONFIG_MACH_KS8695) += board-micrel.o 15 obj-$(CONFIG_MACH_KS8695) += board-micrel.o
16 obj-$(CONFIG_MACH_DSM320) += board-dsm320.o 16 obj-$(CONFIG_MACH_DSM320) += board-dsm320.o
17 obj-$(CONFIG_MACH_ACS5K) += board-acs5k.o 17 obj-$(CONFIG_MACH_ACS5K) += board-acs5k.o
18 obj-$(CONFIG_MACH_LITE300) += board-sg.o
19 obj-$(CONFIG_MACH_SG310) += board-sg.o
20 obj-$(CONFIG_MACH_SE4200) += board-sg.o
21 obj-$(CONFIG_MACH_CM4002) += board-og.o
22 obj-$(CONFIG_MACH_CM4008) += board-og.o
23 obj-$(CONFIG_MACH_CM41xx) += board-og.o
24 obj-$(CONFIG_MACH_IM4004) += board-og.o
25 obj-$(CONFIG_MACH_IM42xx) += board-og.o
18 26
arch/arm/mach-ks8695/board-og.c
Diff comments   View file @ 95360fd
File was created 1 /*
2 * board-og.c -- support for the OpenGear KS8695 based boards.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/types.h>
11 #include <linux/interrupt.h>
12 #include <linux/init.h>
13 #include <linux/delay.h>
14 #include <linux/platform_device.h>
15 #include <linux/serial_8250.h>
16 #include <linux/gpio.h>
17 #include <linux/irq.h>
18 #include <asm/mach-types.h>
19 #include <asm/mach/arch.h>
20 #include <asm/mach/map.h>
21 #include <mach/devices.h>
22 #include <mach/regs-gpio.h>
23 #include <mach/gpio-ks8695.h>
24 #include "generic.h"
25
26 static int og_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
27 {
28 if (machine_is_im4004() && (slot == 8))
29 return KS8695_IRQ_EXTERN1;
30 return KS8695_IRQ_EXTERN0;
31 }
32
33 static struct ks8695_pci_cfg __initdata og_pci = {
34 .mode = KS8695_MODE_PCI,
35 .map_irq = og_pci_map_irq,
36 };
37
38 static void __init og_register_pci(void)
39 {
40 /* Initialize the GPIO lines for interrupt mode */
41 ks8695_gpio_interrupt(KS8695_GPIO_0, IRQ_TYPE_LEVEL_LOW);
42
43 /* Cardbus Slot */
44 if (machine_is_im4004())
45 ks8695_gpio_interrupt(KS8695_GPIO_1, IRQ_TYPE_LEVEL_LOW);
46
47 ks8695_init_pci(&og_pci);
48 }
49
50 /*
51 * The PCI bus reset is driven by a dedicated GPIO line. Toggle it here
52 * and bring the PCI bus out of reset.
53 */
54 static void __init og_pci_bus_reset(void)
55 {
56 unsigned int rstline = 1;
57
58 /* Some boards use a different GPIO as the PCI reset line */
59 if (machine_is_im4004())
60 rstline = 2;
61 else if (machine_is_im42xx())
62 rstline = 0;
63
64 gpio_request(rstline, "PCI reset");
65 gpio_direction_output(rstline, 0);
66
67 /* Drive a reset on the PCI reset line */
68 gpio_set_value(rstline, 1);
69 gpio_set_value(rstline, 0);
70 mdelay(100);
71 gpio_set_value(rstline, 1);
72 mdelay(100);
73 }
74
75 /*
76 * Direct connect serial ports (non-PCI that is).
77 */
78 #define S8250_PHYS 0x03800000
79 #define S8250_VIRT 0xf4000000
80 #define S8250_SIZE 0x00100000
81
82 static struct __initdata map_desc og_io_desc[] = {
83 {
84 .virtual = S8250_VIRT,
85 .pfn = __phys_to_pfn(S8250_PHYS),
86 .length = S8250_SIZE,
87 .type = MT_DEVICE,
88 }
89 };
90
91 static struct resource og_uart_resources[] = {
92 {
93 .start = S8250_VIRT,
94 .end = S8250_VIRT + S8250_SIZE,
95 .flags = IORESOURCE_MEM
96 },
97 };
98
99 static struct plat_serial8250_port og_uart_data[] = {
100 {
101 .mapbase = S8250_VIRT,
102 .membase = (char *) S8250_VIRT,
103 .irq = 3,
104 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
105 .iotype = UPIO_MEM,
106 .regshift = 2,
107 .uartclk = 115200 * 16,
108 },
109 { },
110 };
111
112 static struct platform_device og_uart = {
113 .name = "serial8250",
114 .id = 0,
115 .dev.platform_data = og_uart_data,
116 .num_resources = 1,
117 .resource = og_uart_resources
118 };
119
120 static struct platform_device *og_devices[] __initdata = {
121 &og_uart
122 };
123
124 static void __init og_init(void)
125 {
126 ks8695_register_gpios();
127
128 if (machine_is_cm4002()) {
129 ks8695_gpio_interrupt(KS8695_GPIO_1, IRQ_TYPE_LEVEL_HIGH);
130 iotable_init(og_io_desc, ARRAY_SIZE(og_io_desc));
131 platform_add_devices(og_devices, ARRAY_SIZE(og_devices));
132 } else {
133 og_pci_bus_reset();
134 og_register_pci();
135 }
136
137 ks8695_add_device_lan();
138 ks8695_add_device_wan();
139 }
140
141 #ifdef CONFIG_MACH_CM4002
142 MACHINE_START(CM4002, "OpenGear/CM4002")
143 /* OpenGear Inc. */
144 .atag_offset = 0x100,
145 .map_io = ks8695_map_io,
146 .init_irq = ks8695_init_irq,
147 .init_machine = og_init,
148 .timer = &ks8695_timer,
149 .restart = ks8695_restart,
150 MACHINE_END
151 #endif
152
153 #ifdef CONFIG_MACH_CM4008
154 MACHINE_START(CM4008, "OpenGear/CM4008")
155 /* OpenGear Inc. */
156 .atag_offset = 0x100,
157 .map_io = ks8695_map_io,
158 .init_irq = ks8695_init_irq,
159 .init_machine = og_init,
160 .timer = &ks8695_timer,
161 .restart = ks8695_restart,
162 MACHINE_END
163 #endif
164
165 #ifdef CONFIG_MACH_CM41xx
166 MACHINE_START(CM41XX, "OpenGear/CM41xx")
167 /* OpenGear Inc. */
168 .atag_offset = 0x100,
169 .map_io = ks8695_map_io,
170 .init_irq = ks8695_init_irq,
171 .init_machine = og_init,
172 .timer = &ks8695_timer,
173 .restart = ks8695_restart,
174 MACHINE_END
175 #endif
176
177 #ifdef CONFIG_MACH_IM4004
178 MACHINE_START(IM4004, "OpenGear/IM4004")
179 /* OpenGear Inc. */
180 .atag_offset = 0x100,
181 .map_io = ks8695_map_io,
182 .init_irq = ks8695_init_irq,
183 .init_machine = og_init,
184 .timer = &ks8695_timer,
185 .restart = ks8695_restart,
186 MACHINE_END
187 #endif
188
189 #ifdef CONFIG_MACH_IM42xx
190 MACHINE_START(IM42XX, "OpenGear/IM42xx")
191 /* OpenGear Inc. */
192 .atag_offset = 0x100,
193 .map_io = ks8695_map_io,
194 .init_irq = ks8695_init_irq,
195 .init_machine = og_init,
196 .timer = &ks8695_timer,
197 .restart = ks8695_restart,
198 MACHINE_END
199 #endif
200
arch/arm/mach-ks8695/board-sg.c
Diff comments   View file @ 95360fd
File was created 1 /*
2 * board-sg.c -- support for the SnapGear KS8695 based boards
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/types.h>
11 #include <linux/init.h>
12 #include <linux/platform_device.h>
13 #include <linux/mtd/mtd.h>
14 #include <linux/mtd/map.h>
15 #include <linux/mtd/physmap.h>
16 #include <linux/mtd/partitions.h>
17 #include <asm/mach-types.h>
18 #include <asm/mach/arch.h>
19 #include <mach/devices.h>
20 #include "generic.h"
21
22 /*
23 * The SG310 machine type is fitted with a conventional 8MB Strataflash
24 * device. Define its partitioning.
25 */
26 #define FL_BASE 0x02000000
27 #define FL_SIZE SZ_8M
28
29 static struct mtd_partition sg_mtd_partitions[] = {
30 [0] = {
31 .name = "SnapGear Boot Loader",
32 .size = SZ_128K,
33 },
34 [1] = {
35 .name = "SnapGear non-volatile configuration",
36 .size = SZ_512K,
37 .offset = SZ_256K,
38 },
39 [2] = {
40 .name = "SnapGear image",
41 .offset = SZ_512K + SZ_256K,
42 },
43 [3] = {
44 .name = "SnapGear StrataFlash",
45 },
46 [4] = {
47 .name = "SnapGear Boot Tags",
48 .size = SZ_128K,
49 .offset = SZ_128K,
50 },
51 };
52
53 static struct physmap_flash_data sg_mtd_pdata = {
54 .width = 1,
55 .nr_parts = ARRAY_SIZE(sg_mtd_partitions),
56 .parts = sg_mtd_partitions,
57 };
58
59
60 static struct resource sg_mtd_resource[] = {
61 [0] = {
62 .start = FL_BASE,
63 .end = FL_BASE + FL_SIZE - 1,
64 .flags = IORESOURCE_MEM,
65 },
66 };
67
68 static struct platform_device sg_mtd_device = {
69 .name = "physmap-flash",
70 .id = 0,
71 .num_resources = ARRAY_SIZE(sg_mtd_resource),
72 .resource = sg_mtd_resource,
73 .dev = {
74 .platform_data = &sg_mtd_pdata,
75 },
76 };
77
78 static void __init sg_init(void)
79 {
80 ks8695_add_device_lan();
81 ks8695_add_device_wan();
82
83 if (machine_is_sg310())
84 platform_device_register(&sg_mtd_device);
85 }
86
87 #ifdef CONFIG_MACH_LITE300
88 MACHINE_START(LITE300, "SecureComputing/SG300")
89 /* SnapGear */
90 .atag_offset = 0x100,
91 .map_io = ks8695_map_io,
92 .init_irq = ks8695_init_irq,
93 .init_machine = sg_init,
94 .timer = &ks8695_timer,
95 .restart = ks8695_restart,
96 MACHINE_END
97 #endif
98
99 #ifdef CONFIG_MACH_SG310
100 MACHINE_START(SG310, "McAfee/SG310")
101 /* SnapGear */
102 .atag_offset = 0x100,
103 .map_io = ks8695_map_io,
104 .init_irq = ks8695_init_irq,
105 .init_machine = sg_init,
106 .timer = &ks8695_timer,
107 .restart = ks8695_restart,
108 MACHINE_END
109 #endif
110
111 #ifdef CONFIG_MACH_SE4200
112 MACHINE_START(SE4200, "SecureComputing/SE4200")
113 /* SnapGear */
114 .atag_offset = 0x100,
115 .map_io = ks8695_map_io,
116 .init_irq = ks8695_init_irq,
117 .init_machine = sg_init,
118 .timer = &ks8695_timer,
119 .restart = ks8695_restart,
120 MACHINE_END
121 #endif
122
arch/arm/mach-mmp/include/mach/debug-macro.S
Diff comments   View file @ 95360fd
1 /* arch/arm/mach-mmp/include/mach/debug-macro.S 1 /* arch/arm/mach-mmp/include/mach/debug-macro.S
2 * 2 *
3 * Debugging macro include header 3 * Debugging macro include header
4 * 4 *
5 * Copied from arch/arm/mach-pxa/include/mach/debug.S 5 * Copied from arch/arm/mach-pxa/include/mach/debug.S
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12 #if defined(CONFIG_DEBUG_MMP_UART2)
13 #define MMP_UART_OFFSET 0x00017000
14 #elif defined(CONFIG_DEBUG_MMP_UART3)
15 #define MMP_UART_OFFSET 0x00018000
16 #else
17 #error "Select uart for DEBUG_LL"
18 #endif
19
12 #include <mach/addr-map.h> 20 #include <mach/addr-map.h>
13 21
14 .macro addruart, rp, rv, tmp 22 .macro addruart, rp, rv, tmp
15 ldr \rp, =APB_PHYS_BASE @ physical 23 ldr \rp, =APB_PHYS_BASE @ physical
16 ldr \rv, =APB_VIRT_BASE @ virtual 24 ldr \rv, =APB_VIRT_BASE @ virtual
17 orr \rp, \rp, #0x00017000 25 orr \rp, \rp, #MMP_UART_OFFSET
18 orr \rv, \rv, #0x00017000 26 orr \rv, \rv, #MMP_UART_OFFSET
19 .endm 27 .endm
20 28
21 #define UART_SHIFT 2 29 #define UART_SHIFT 2
22 #include <asm/hardware/debug-8250.S> 30 #include <asm/hardware/debug-8250.S>
23 31
arch/arm/mach-mmp/ttc_dkb.c
Diff comments   View file @ 95360fd
1 /* 1 /*
2 * linux/arch/arm/mach-mmp/ttc_dkb.c 2 * linux/arch/arm/mach-mmp/ttc_dkb.c
3 * 3 *
4 * Support for the Marvell PXA910-based TTC_DKB Development Platform. 4 * Support for the Marvell PXA910-based TTC_DKB Development Platform.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * publishhed by the Free Software Foundation. 8 * publishhed by the Free Software Foundation.
9 */ 9 */
10 10
11 #include <linux/init.h> 11 #include <linux/init.h>
12 #include <linux/kernel.h> 12 #include <linux/kernel.h>
13 #include <linux/platform_device.h> 13 #include <linux/platform_device.h>
14 #include <linux/mtd/mtd.h> 14 #include <linux/mtd/mtd.h>
15 #include <linux/mtd/partitions.h> 15 #include <linux/mtd/partitions.h>
16 #include <linux/mtd/onenand.h> 16 #include <linux/mtd/onenand.h>
17 #include <linux/interrupt.h> 17 #include <linux/interrupt.h>
18 #include <linux/i2c/pca953x.h> 18 #include <linux/i2c/pca953x.h>
19 #include <linux/gpio.h> 19 #include <linux/gpio.h>
20 #include <linux/mfd/88pm860x.h> 20 #include <linux/mfd/88pm860x.h>
21 #include <linux/platform_data/mv_usb.h> 21 #include <linux/platform_data/mv_usb.h>
22 22
23 #include <asm/mach-types.h> 23 #include <asm/mach-types.h>
24 #include <asm/mach/arch.h> 24 #include <asm/mach/arch.h>
25 #include <asm/mach/flash.h> 25 #include <asm/mach/flash.h>
26 #include <mach/addr-map.h> 26 #include <mach/addr-map.h>
27 #include <mach/mfp-pxa910.h> 27 #include <mach/mfp-pxa910.h>
28 #include <mach/pxa910.h> 28 #include <mach/pxa910.h>
29 #include <mach/irqs.h> 29 #include <mach/irqs.h>
30 #include <mach/regs-usb.h> 30 #include <mach/regs-usb.h>
31 31
32 #include "common.h" 32 #include "common.h"
33 33
34 #define TTCDKB_GPIO_EXT0(x) (MMP_NR_BUILTIN_GPIO + ((x < 0) ? 0 : \ 34 #define TTCDKB_GPIO_EXT0(x) (MMP_NR_BUILTIN_GPIO + ((x < 0) ? 0 : \
35 ((x < 16) ? x : 15))) 35 ((x < 16) ? x : 15)))
36 #define TTCDKB_GPIO_EXT1(x) (MMP_NR_BUILTIN_GPIO + 16 + ((x < 0) ? 0 : \ 36 #define TTCDKB_GPIO_EXT1(x) (MMP_NR_BUILTIN_GPIO + 16 + ((x < 0) ? 0 : \
37 ((x < 16) ? x : 15))) 37 ((x < 16) ? x : 15)))
38 38
39 /* 39 /*
40 * 16 board interrupts -- MAX7312 GPIO expander 40 * 16 board interrupts -- MAX7312 GPIO expander
41 * 16 board interrupts -- PCA9575 GPIO expander 41 * 16 board interrupts -- PCA9575 GPIO expander
42 * 24 board interrupts -- 88PM860x PMIC 42 * 24 board interrupts -- 88PM860x PMIC
43 */ 43 */
44 #define TTCDKB_NR_IRQS (MMP_NR_IRQS + 16 + 16 + 24) 44 #define TTCDKB_NR_IRQS (MMP_NR_IRQS + 16 + 16 + 24)
45 45
46 static unsigned long ttc_dkb_pin_config[] __initdata = { 46 static unsigned long ttc_dkb_pin_config[] __initdata = {
47 /* UART2 */ 47 /* UART2 */
48 GPIO47_UART2_RXD, 48 GPIO47_UART2_RXD,
49 GPIO48_UART2_TXD, 49 GPIO48_UART2_TXD,
50 50
51 /* DFI */ 51 /* DFI */
52 DF_IO0_ND_IO0, 52 DF_IO0_ND_IO0,
53 DF_IO1_ND_IO1, 53 DF_IO1_ND_IO1,
54 DF_IO2_ND_IO2, 54 DF_IO2_ND_IO2,
55 DF_IO3_ND_IO3, 55 DF_IO3_ND_IO3,
56 DF_IO4_ND_IO4, 56 DF_IO4_ND_IO4,
57 DF_IO5_ND_IO5, 57 DF_IO5_ND_IO5,
58 DF_IO6_ND_IO6, 58 DF_IO6_ND_IO6,
59 DF_IO7_ND_IO7, 59 DF_IO7_ND_IO7,
60 DF_IO8_ND_IO8, 60 DF_IO8_ND_IO8,
61 DF_IO9_ND_IO9, 61 DF_IO9_ND_IO9,
62 DF_IO10_ND_IO10, 62 DF_IO10_ND_IO10,
63 DF_IO11_ND_IO11, 63 DF_IO11_ND_IO11,
64 DF_IO12_ND_IO12, 64 DF_IO12_ND_IO12,
65 DF_IO13_ND_IO13, 65 DF_IO13_ND_IO13,
66 DF_IO14_ND_IO14, 66 DF_IO14_ND_IO14,
67 DF_IO15_ND_IO15, 67 DF_IO15_ND_IO15,
68 DF_nCS0_SM_nCS2_nCS0, 68 DF_nCS0_SM_nCS2_nCS0,
69 DF_ALE_SM_WEn_ND_ALE, 69 DF_ALE_SM_WEn_ND_ALE,
70 DF_CLE_SM_OEn_ND_CLE, 70 DF_CLE_SM_OEn_ND_CLE,
71 DF_WEn_DF_WEn, 71 DF_WEn_DF_WEn,
72 DF_REn_DF_REn, 72 DF_REn_DF_REn,
73 DF_RDY0_DF_RDY0, 73 DF_RDY0_DF_RDY0,
74 }; 74 };
75 75
76 static struct mtd_partition ttc_dkb_onenand_partitions[] = { 76 static struct mtd_partition ttc_dkb_onenand_partitions[] = {
77 { 77 {
78 .name = "bootloader", 78 .name = "bootloader",
79 .offset = 0, 79 .offset = 0,
80 .size = SZ_1M, 80 .size = SZ_1M,
81 .mask_flags = MTD_WRITEABLE, 81 .mask_flags = MTD_WRITEABLE,
82 }, { 82 }, {
83 .name = "reserved", 83 .name = "reserved",
84 .offset = MTDPART_OFS_APPEND, 84 .offset = MTDPART_OFS_APPEND,
85 .size = SZ_128K, 85 .size = SZ_128K,
86 .mask_flags = MTD_WRITEABLE, 86 .mask_flags = MTD_WRITEABLE,
87 }, { 87 }, {
88 .name = "reserved", 88 .name = "reserved",
89 .offset = MTDPART_OFS_APPEND, 89 .offset = MTDPART_OFS_APPEND,
90 .size = SZ_8M, 90 .size = SZ_8M,
91 .mask_flags = MTD_WRITEABLE, 91 .mask_flags = MTD_WRITEABLE,
92 }, { 92 }, {
93 .name = "kernel", 93 .name = "kernel",
94 .offset = MTDPART_OFS_APPEND, 94 .offset = MTDPART_OFS_APPEND,
95 .size = (SZ_2M + SZ_1M), 95 .size = (SZ_2M + SZ_1M),
96 .mask_flags = 0, 96 .mask_flags = 0,
97 }, { 97 }, {
98 .name = "filesystem", 98 .name = "filesystem",
99 .offset = MTDPART_OFS_APPEND, 99 .offset = MTDPART_OFS_APPEND,
100 .size = SZ_32M + SZ_16M, 100 .size = SZ_32M + SZ_16M,
101 .mask_flags = 0, 101 .mask_flags = 0,
102 } 102 }
103 }; 103 };
104 104
105 static struct onenand_platform_data ttc_dkb_onenand_info = { 105 static struct onenand_platform_data ttc_dkb_onenand_info = {
106 .parts = ttc_dkb_onenand_partitions, 106 .parts = ttc_dkb_onenand_partitions,
107 .nr_parts = ARRAY_SIZE(ttc_dkb_onenand_partitions), 107 .nr_parts = ARRAY_SIZE(ttc_dkb_onenand_partitions),
108 }; 108 };
109 109
110 static struct resource ttc_dkb_resource_onenand[] = { 110 static struct resource ttc_dkb_resource_onenand[] = {
111 [0] = { 111 [0] = {
112 .start = SMC_CS0_PHYS_BASE, 112 .start = SMC_CS0_PHYS_BASE,
113 .end = SMC_CS0_PHYS_BASE + SZ_1M, 113 .end = SMC_CS0_PHYS_BASE + SZ_1M,
114 .flags = IORESOURCE_MEM, 114 .flags = IORESOURCE_MEM,
115 }, 115 },
116 }; 116 };
117 117
118 static struct platform_device ttc_dkb_device_onenand = { 118 static struct platform_device ttc_dkb_device_onenand = {
119 .name = "onenand-flash", 119 .name = "onenand-flash",
120 .id = -1, 120 .id = -1,
121 .resource = ttc_dkb_resource_onenand, 121 .resource = ttc_dkb_resource_onenand,
122 .num_resources = ARRAY_SIZE(ttc_dkb_resource_onenand), 122 .num_resources = ARRAY_SIZE(ttc_dkb_resource_onenand),
123 .dev = { 123 .dev = {
124 .platform_data = &ttc_dkb_onenand_info, 124 .platform_data = &ttc_dkb_onenand_info,
125 }, 125 },
126 }; 126 };
127 127
128 static struct platform_device *ttc_dkb_devices[] = { 128 static struct platform_device *ttc_dkb_devices[] = {
129 &pxa910_device_gpio, 129 &pxa910_device_gpio,
130 &pxa910_device_rtc, 130 &pxa910_device_rtc,
131 &ttc_dkb_device_onenand, 131 &ttc_dkb_device_onenand,
132 }; 132 };
133 133
134 static struct pca953x_platform_data max7312_data[] = { 134 static struct pca953x_platform_data max7312_data[] = {
135 { 135 {
136 .gpio_base = TTCDKB_GPIO_EXT0(0), 136 .gpio_base = TTCDKB_GPIO_EXT0(0),
137 .irq_base = MMP_NR_IRQS, 137 .irq_base = MMP_NR_IRQS,
138 }, 138 },
139 }; 139 };
140 140
141 static struct pm860x_platform_data ttc_dkb_pm8607_info = { 141 static struct pm860x_platform_data ttc_dkb_pm8607_info = {
142 .irq_base = IRQ_BOARD_START, 142 .irq_base = IRQ_BOARD_START,
143 }; 143 };
144 144
145 static struct i2c_board_info ttc_dkb_i2c_info[] = { 145 static struct i2c_board_info ttc_dkb_i2c_info[] = {
146 { 146 {
147 .type = "88PM860x", 147 .type = "88PM860x",
148 .addr = 0x34, 148 .addr = 0x34,
149 .platform_data = &ttc_dkb_pm8607_info, 149 .platform_data = &ttc_dkb_pm8607_info,
150 .irq = IRQ_PXA910_PMIC_INT, 150 .irq = IRQ_PXA910_PMIC_INT,
151 }, 151 },
152 { 152 {
153 .type = "max7312", 153 .type = "max7312",
154 .addr = 0x23, 154 .addr = 0x23,
155 .irq = MMP_GPIO_TO_IRQ(80), 155 .irq = MMP_GPIO_TO_IRQ(80),
156 .platform_data = &max7312_data, 156 .platform_data = &max7312_data,
157 }, 157 },
158 }; 158 };
159 159
160 #ifdef CONFIG_USB_SUPPORT 160 #ifdef CONFIG_USB_SUPPORT
161 #if defined(CONFIG_USB_MV_UDC) || defined(CONFIG_USB_EHCI_MV_U2O) 161 #if defined(CONFIG_USB_MV_UDC) || defined(CONFIG_USB_EHCI_MV_U2O)
162 162
163 static char *pxa910_usb_clock_name[] = { 163 static char *pxa910_usb_clock_name[] = {
164 [0] = "U2OCLK", 164 [0] = "U2OCLK",
165 }; 165 };
166 166
167 static struct mv_usb_platform_data ttc_usb_pdata = { 167 static struct mv_usb_platform_data ttc_usb_pdata = {
168 .clknum = 1, 168 .clknum = 1,
169 .clkname = pxa910_usb_clock_name, 169 .clkname = pxa910_usb_clock_name,
170 .vbus = NULL, 170 .vbus = NULL,
171 .mode = MV_USB_MODE_OTG, 171 .mode = MV_USB_MODE_OTG,
172 .otg_force_a_bus_req = 1, 172 .otg_force_a_bus_req = 1,
173 .phy_init = pxa_usb_phy_init, 173 .phy_init = pxa_usb_phy_init,
174 .phy_deinit = pxa_usb_phy_deinit, 174 .phy_deinit = pxa_usb_phy_deinit,
175 .set_vbus = NULL, 175 .set_vbus = NULL,
176 }; 176 };
177 #endif 177 #endif
178 #endif 178 #endif
179 179
180 #ifdef CONFIG_MTD_NAND_PXA3xx
181 static struct pxa3xx_nand_platform_data dkb_nand_info = {
182 .enable_arbiter = 1,
183 .num_cs = 1,
184 };
185 #endif
186
180 static void __init ttc_dkb_init(void) 187 static void __init ttc_dkb_init(void)
181 { 188 {
182 mfp_config(ARRAY_AND_SIZE(ttc_dkb_pin_config)); 189 mfp_config(ARRAY_AND_SIZE(ttc_dkb_pin_config));
183 190
184 /* on-chip devices */ 191 /* on-chip devices */
185 pxa910_add_uart(1); 192 pxa910_add_uart(1);
193 #ifdef CONFIG_MTD_NAND_PXA3xx
194 pxa910_add_nand(&dkb_nand_info);
195 #endif
186 196
187 /* off-chip devices */ 197 /* off-chip devices */
188 pxa910_add_twsi(0, NULL, ARRAY_AND_SIZE(ttc_dkb_i2c_info)); 198 pxa910_add_twsi(0, NULL, ARRAY_AND_SIZE(ttc_dkb_i2c_info));
189 platform_add_devices(ARRAY_AND_SIZE(ttc_dkb_devices)); 199 platform_add_devices(ARRAY_AND_SIZE(ttc_dkb_devices));
190 200
191 #ifdef CONFIG_USB_MV_UDC 201 #ifdef CONFIG_USB_MV_UDC
192 pxa168_device_u2o.dev.platform_data = &ttc_usb_pdata; 202 pxa168_device_u2o.dev.platform_data = &ttc_usb_pdata;
193 platform_device_register(&pxa168_device_u2o); 203 platform_device_register(&pxa168_device_u2o);
194 #endif 204 #endif
195 205
196 #ifdef CONFIG_USB_EHCI_MV_U2O 206 #ifdef CONFIG_USB_EHCI_MV_U2O
197 pxa168_device_u2oehci.dev.platform_data = &ttc_usb_pdata; 207 pxa168_device_u2oehci.dev.platform_data = &ttc_usb_pdata;
198 platform_device_register(&pxa168_device_u2oehci); 208 platform_device_register(&pxa168_device_u2oehci);
199 #endif 209 #endif
200 210
201 #ifdef CONFIG_USB_MV_OTG 211 #ifdef CONFIG_USB_MV_OTG
202 pxa168_device_u2ootg.dev.platform_data = &ttc_usb_pdata; 212 pxa168_device_u2ootg.dev.platform_data = &ttc_usb_pdata;
203 platform_device_register(&pxa168_device_u2ootg); 213 platform_device_register(&pxa168_device_u2ootg);
204 #endif 214 #endif
205 } 215 }
206 216
207 MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform") 217 MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform")
208 .map_io = mmp_map_io, 218 .map_io = mmp_map_io,
209 .nr_irqs = TTCDKB_NR_IRQS, 219 .nr_irqs = TTCDKB_NR_IRQS,
210 .init_irq = pxa910_init_irq, 220 .init_irq = pxa910_init_irq,
211 .timer = &pxa910_timer, 221 .timer = &pxa910_timer,
212 .init_machine = ttc_dkb_init, 222 .init_machine = ttc_dkb_init,
213 .restart = mmp_restart, 223 .restart = mmp_restart,
214 MACHINE_END 224 MACHINE_END
215 225
arch/arm/mach-msm/Kconfig
Diff comments   View file @ 95360fd
1 if ARCH_MSM 1 if ARCH_MSM
2 2
3 comment "Qualcomm MSM SoC Type"
4 depends on (ARCH_MSM8X60 || ARCH_MSM8960)
5
3 choice 6 choice
4 prompt "Qualcomm MSM SoC Type" 7 prompt "Qualcomm MSM SoC Type"
5 default ARCH_MSM7X00A 8 default ARCH_MSM7X00A
9 depends on !(ARCH_MSM8X60 || ARCH_MSM8960)
6 10
7 config ARCH_MSM7X00A 11 config ARCH_MSM7X00A
8 bool "MSM7x00A / MSM7x01A" 12 bool "MSM7x00A / MSM7x01A"
9 select MACH_TROUT if !MACH_HALIBUT 13 select MACH_TROUT if !MACH_HALIBUT
10 select ARCH_MSM_ARM11 14 select ARCH_MSM_ARM11
11 select MSM_SMD 15 select MSM_SMD
12 select MSM_SMD_PKG3 16 select MSM_SMD_PKG3
13 select CPU_V6 17 select CPU_V6
14 select GPIO_MSM_V1 18 select GPIO_MSM_V1
15 select MSM_PROC_COMM 19 select MSM_PROC_COMM
16 20
17 config ARCH_MSM7X30 21 config ARCH_MSM7X30
18 bool "MSM7x30" 22 bool "MSM7x30"
19 select MACH_MSM7X30_SURF # if ! 23 select MACH_MSM7X30_SURF # if !
20 select ARCH_MSM_SCORPION 24 select ARCH_MSM_SCORPION
21 select MSM_SMD 25 select MSM_SMD
22 select MSM_VIC 26 select MSM_VIC
23 select CPU_V7 27 select CPU_V7
24 select MSM_GPIOMUX 28 select MSM_GPIOMUX
25 select GPIO_MSM_V1 29 select GPIO_MSM_V1
26 select MSM_PROC_COMM 30 select MSM_PROC_COMM
27 31
28 config ARCH_QSD8X50 32 config ARCH_QSD8X50
29 bool "QSD8X50" 33 bool "QSD8X50"
30 select MACH_QSD8X50_SURF if !MACH_QSD8X50A_ST1_5 34 select MACH_QSD8X50_SURF if !MACH_QSD8X50A_ST1_5
31 select ARCH_MSM_SCORPION 35 select ARCH_MSM_SCORPION
32 select MSM_SMD 36 select MSM_SMD
33 select MSM_VIC 37 select MSM_VIC
34 select CPU_V7 38 select CPU_V7
35 select MSM_GPIOMUX 39 select MSM_GPIOMUX
36 select GPIO_MSM_V1 40 select GPIO_MSM_V1
37 select MSM_PROC_COMM 41 select MSM_PROC_COMM
38 42
43 endchoice
44
39 config ARCH_MSM8X60 45 config ARCH_MSM8X60
40 bool "MSM8X60" 46 bool "MSM8X60"
41 select ARCH_MSM_SCORPIONMP 47 select ARCH_MSM_SCORPIONMP
42 select ARM_GIC 48 select ARM_GIC
43 select CPU_V7 49 select CPU_V7
44 select MSM_V2_TLMM 50 select MSM_V2_TLMM
45 select GPIO_MSM_V2 51 select GPIO_MSM_V2
46 select MSM_GPIOMUX 52 select MSM_GPIOMUX
47 select MSM_SCM if SMP 53 select MSM_SCM if SMP
48 select USE_OF 54 select USE_OF
49 55
50 config ARCH_MSM8960 56 config ARCH_MSM8960
51 bool "MSM8960" 57 bool "MSM8960"
52 select ARCH_MSM_SCORPIONMP 58 select ARCH_MSM_SCORPIONMP
53 select ARM_GIC 59 select ARM_GIC
54 select CPU_V7 60 select CPU_V7
55 select MSM_V2_TLMM 61 select MSM_V2_TLMM
56 select MSM_GPIOMUX 62 select MSM_GPIOMUX
57 select MSM_SCM if SMP 63 select MSM_SCM if SMP
58 select USE_OF 64 select USE_OF
59
60 endchoice
61 65
62 config MSM_HAS_DEBUG_UART_HS 66 config MSM_HAS_DEBUG_UART_HS
63 bool 67 bool
64 68
65 config MSM_SOC_REV_A 69 config MSM_SOC_REV_A
66 bool 70 bool
67 config ARCH_MSM_SCORPIONMP 71 config ARCH_MSM_SCORPIONMP
68 bool 72 bool
69 select HAVE_SMP 73 select HAVE_SMP
70 74
71 config ARCH_MSM_ARM11 75 config ARCH_MSM_ARM11
72 bool 76 bool
73 config ARCH_MSM_SCORPION 77 config ARCH_MSM_SCORPION
74 bool 78 bool
75 79
76 config MSM_VIC 80 config MSM_VIC
77 bool 81 bool
78 82
79 menu "Qualcomm MSM Board Type" 83 menu "Qualcomm MSM Board Type"
80 84
81 config MACH_HALIBUT 85 config MACH_HALIBUT
82 depends on ARCH_MSM 86 depends on ARCH_MSM
83 depends on ARCH_MSM7X00A 87 depends on ARCH_MSM7X00A
84 bool "Halibut Board (QCT SURF7201A)" 88 bool "Halibut Board (QCT SURF7201A)"
85 help 89 help
86 Support for the Qualcomm SURF7201A eval board. 90 Support for the Qualcomm SURF7201A eval board.
87 91
88 config MACH_TROUT 92 config MACH_TROUT
89 depends on ARCH_MSM 93 depends on ARCH_MSM
90 depends on ARCH_MSM7X00A 94 depends on ARCH_MSM7X00A
91 bool "HTC Dream (aka trout)" 95 bool "HTC Dream (aka trout)"
92 help 96 help
93 Support for the HTC Dream, T-Mobile G1, Android ADP1 devices. 97 Support for the HTC Dream, T-Mobile G1, Android ADP1 devices.
94 98
95 config MACH_MSM7X30_SURF 99 config MACH_MSM7X30_SURF
96 depends on ARCH_MSM7X30 100 depends on ARCH_MSM7X30
97 bool "MSM7x30 SURF" 101 bool "MSM7x30 SURF"
98 help 102 help
99 Support for the Qualcomm MSM7x30 SURF eval board. 103 Support for the Qualcomm MSM7x30 SURF eval board.
100 104
101 config MACH_QSD8X50_SURF 105 config MACH_QSD8X50_SURF
102 depends on ARCH_QSD8X50 106 depends on ARCH_QSD8X50
103 bool "QSD8x50 SURF" 107 bool "QSD8x50 SURF"
104 help 108 help
105 Support for the Qualcomm QSD8x50 SURF eval board. 109 Support for the Qualcomm QSD8x50 SURF eval board.
106 110
107 config MACH_QSD8X50A_ST1_5 111 config MACH_QSD8X50A_ST1_5
108 depends on ARCH_QSD8X50 112 depends on ARCH_QSD8X50
109 select MSM_SOC_REV_A 113 select MSM_SOC_REV_A
110 bool "QSD8x50A ST1.5" 114 bool "QSD8x50A ST1.5"
111 help 115 help
112 Support for the Qualcomm ST1.5. 116 Support for the Qualcomm ST1.5.
113 117
114 endmenu 118 endmenu
115 119
116 config MSM_SMD_PKG3 120 config MSM_SMD_PKG3
117 bool 121 bool
118 122
119 config MSM_PROC_COMM 123 config MSM_PROC_COMM
120 bool 124 bool
121 125
122 config MSM_SMD 126 config MSM_SMD
123 bool 127 bool
124 128
125 config MSM_GPIOMUX 129 config MSM_GPIOMUX
126 bool 130 bool
127 131
128 config MSM_V2_TLMM 132 config MSM_V2_TLMM
129 bool 133 bool
130 134
131 config MSM_SCM 135 config MSM_SCM
132 bool 136 bool
arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
Diff comments   View file @ 95360fd
1 /* 1 /*
2 * Copyright (C) 2007 Google, Inc. 2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. 3 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com> 4 * Author: Brian Swetland <swetland@google.com>
5 * 5 *
6 * This software is licensed under the terms of the GNU General Public 6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and 7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms. 8 * may be copied, distributed, and modified under those terms.
9 * 9 *
10 * This program is distributed in the hope that it will be useful, 10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 * 14 *
15 * 15 *
16 * The MSM peripherals are spread all over across 768MB of physical 16 * The MSM peripherals are spread all over across 768MB of physical
17 * space, which makes just having a simple IO_ADDRESS macro to slide 17 * space, which makes just having a simple IO_ADDRESS macro to slide
18 * them into the right virtual location rough. Instead, we will 18 * them into the right virtual location rough. Instead, we will
19 * provide a master phys->virt mapping for peripherals here. 19 * provide a master phys->virt mapping for peripherals here.
20 * 20 *
21 */ 21 */
22 22
23 #ifndef __ASM_ARCH_MSM_IOMAP_8X60_H 23 #ifndef __ASM_ARCH_MSM_IOMAP_8X60_H
24 #define __ASM_ARCH_MSM_IOMAP_8X60_H 24 #define __ASM_ARCH_MSM_IOMAP_8X60_H
25 25
26 /* Physical base address and size of peripherals. 26 /* Physical base address and size of peripherals.
27 * Ordered by the virtual base addresses they will be mapped at. 27 * Ordered by the virtual base addresses they will be mapped at.
28 * 28 *
29 * MSM_VIC_BASE must be an value that can be loaded via a "mov" 29 * MSM_VIC_BASE must be an value that can be loaded via a "mov"
30 * instruction, otherwise entry-macro.S will not compile. 30 * instruction, otherwise entry-macro.S will not compile.
31 * 31 *
32 * If you add or remove entries here, you'll want to edit the 32 * If you add or remove entries here, you'll want to edit the
33 * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your 33 * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
34 * changes. 34 * changes.
35 * 35 *
36 */ 36 */
37 37
38 #define MSM8X60_QGIC_DIST_PHYS 0x02080000 38 #define MSM8X60_QGIC_DIST_PHYS 0x02080000
39 #define MSM8X60_QGIC_DIST_SIZE SZ_4K 39 #define MSM8X60_QGIC_DIST_SIZE SZ_4K
40 40
41 #define MSM8X60_QGIC_CPU_PHYS 0x02081000 41 #define MSM8X60_QGIC_CPU_PHYS 0x02081000
42 #define MSM8X60_QGIC_CPU_SIZE SZ_4K 42 #define MSM8X60_QGIC_CPU_SIZE SZ_4K
43 43
44 #define MSM_ACC_BASE IOMEM(0xF0002000)
45 #define MSM_ACC_PHYS 0x02001000
46 #define MSM_ACC_SIZE SZ_4K
47
48 #define MSM_GCC_BASE IOMEM(0xF0003000)
49 #define MSM_GCC_PHYS 0x02082000
50 #define MSM_GCC_SIZE SZ_4K
51
52 #define MSM_TLMM_BASE IOMEM(0xF0004000) 44 #define MSM_TLMM_BASE IOMEM(0xF0004000)
53 #define MSM_TLMM_PHYS 0x00800000 45 #define MSM_TLMM_PHYS 0x00800000
54 #define MSM_TLMM_SIZE SZ_16K 46 #define MSM_TLMM_SIZE SZ_16K
55
56 #define MSM_SHARED_RAM_BASE IOMEM(0xF0100000)
57 #define MSM_SHARED_RAM_SIZE SZ_1M
58 47
59 #define MSM8X60_TMR_PHYS 0x02000000 48 #define MSM8X60_TMR_PHYS 0x02000000
60 #define MSM8X60_TMR_SIZE SZ_4K 49 #define MSM8X60_TMR_SIZE SZ_4K
61 50
62 #define MSM8X60_TMR0_PHYS 0x02040000 51 #define MSM8X60_TMR0_PHYS 0x02040000
63 #define MSM8X60_TMR0_SIZE SZ_4K 52 #define MSM8X60_TMR0_SIZE SZ_4K
64 53
65 #ifdef CONFIG_DEBUG_MSM8660_UART 54 #ifdef CONFIG_DEBUG_MSM8660_UART
66 #define MSM_DEBUG_UART_BASE 0xF0040000 55 #define MSM_DEBUG_UART_BASE 0xF0040000
67 #define MSM_DEBUG_UART_PHYS 0x19C40000 56 #define MSM_DEBUG_UART_PHYS 0x19C40000
68 #endif 57 #endif
69 58
70 #endif 59 #endif
71 60
arch/arm/mach-msm/include/mach/msm_iomap.h
Diff comments   View file @ 95360fd
1 /* 1 /*
2 * Copyright (C) 2007 Google, Inc. 2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. 3 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com> 4 * Author: Brian Swetland <swetland@google.com>
5 * 5 *
6 * This software is licensed under the terms of the GNU General Public 6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and 7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms. 8 * may be copied, distributed, and modified under those terms.
9 * 9 *
10 * This program is distributed in the hope that it will be useful, 10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 * 14 *
15 * 15 *
16 * The MSM peripherals are spread all over across 768MB of physical 16 * The MSM peripherals are spread all over across 768MB of physical
17 * space, which makes just having a simple IO_ADDRESS macro to slide 17 * space, which makes just having a simple IO_ADDRESS macro to slide
18 * them into the right virtual location rough. Instead, we will 18 * them into the right virtual location rough. Instead, we will
19 * provide a master phys->virt mapping for peripherals here. 19 * provide a master phys->virt mapping for peripherals here.
20 * 20 *
21 */ 21 */
22 22
23 #ifndef __ASM_ARCH_MSM_IOMAP_H 23 #ifndef __ASM_ARCH_MSM_IOMAP_H
24 #define __ASM_ARCH_MSM_IOMAP_H 24 #define __ASM_ARCH_MSM_IOMAP_H
25 25
26 #include <asm/sizes.h> 26 #include <asm/sizes.h>
27 27
28 /* Physical base address and size of peripherals. 28 /* Physical base address and size of peripherals.
29 * Ordered by the virtual base addresses they will be mapped at. 29 * Ordered by the virtual base addresses they will be mapped at.
30 * 30 *
31 * MSM_VIC_BASE must be an value that can be loaded via a "mov" 31 * MSM_VIC_BASE must be an value that can be loaded via a "mov"
32 * instruction, otherwise entry-macro.S will not compile. 32 * instruction, otherwise entry-macro.S will not compile.
33 * 33 *
34 * If you add or remove entries here, you'll want to edit the 34 * If you add or remove entries here, you'll want to edit the
35 * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your 35 * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
36 * changes. 36 * changes.
37 * 37 *
38 */ 38 */
39 39
40 #if defined(CONFIG_ARCH_MSM7X30) 40 #if defined(CONFIG_ARCH_MSM7X30)
41 #include "msm_iomap-7x30.h" 41 #include "msm_iomap-7x30.h"
42 #elif defined(CONFIG_ARCH_QSD8X50) 42 #elif defined(CONFIG_ARCH_QSD8X50)
43 #include "msm_iomap-8x50.h" 43 #include "msm_iomap-8x50.h"
44 #elif defined(CONFIG_ARCH_MSM8X60)
45 #include "msm_iomap-8x60.h"
46 #else 44 #else
47 #include "msm_iomap-7x00.h" 45 #include "msm_iomap-7x00.h"
48 #endif 46 #endif
49 47
48 #include "msm_iomap-8x60.h"
50 #include "msm_iomap-8960.h" 49 #include "msm_iomap-8960.h"
51 50
52 #define MSM_DEBUG_UART_SIZE SZ_4K 51 #define MSM_DEBUG_UART_SIZE SZ_4K
53 #if defined(CONFIG_DEBUG_MSM_UART1) 52 #if defined(CONFIG_DEBUG_MSM_UART1)
54 #define MSM_DEBUG_UART_BASE 0xE1000000 53 #define MSM_DEBUG_UART_BASE 0xE1000000
55 #define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS 54 #define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS
56 #elif defined(CONFIG_DEBUG_MSM_UART2) 55 #elif defined(CONFIG_DEBUG_MSM_UART2)
57 #define MSM_DEBUG_UART_BASE 0xE1000000 56 #define MSM_DEBUG_UART_BASE 0xE1000000
58 #define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS 57 #define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS
59 #elif defined(CONFIG_DEBUG_MSM_UART3) 58 #elif defined(CONFIG_DEBUG_MSM_UART3)
60 #define MSM_DEBUG_UART_BASE 0xE1000000 59 #define MSM_DEBUG_UART_BASE 0xE1000000
61 #define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS 60 #define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS
62 #endif 61 #endif
63 62
64 /* Virtual addresses shared across all MSM targets. */ 63 /* Virtual addresses shared across all MSM targets. */
65 #define MSM_CSR_BASE IOMEM(0xE0001000) 64 #define MSM_CSR_BASE IOMEM(0xE0001000)
66 #define MSM_QGIC_DIST_BASE IOMEM(0xF0000000) 65 #define MSM_QGIC_DIST_BASE IOMEM(0xF0000000)
67 #define MSM_QGIC_CPU_BASE IOMEM(0xF0001000) 66 #define MSM_QGIC_CPU_BASE IOMEM(0xF0001000)
68 #define MSM_TMR_BASE IOMEM(0xF0200000) 67 #define MSM_TMR_BASE IOMEM(0xF0200000)
69 #define MSM_TMR0_BASE IOMEM(0xF0201000) 68 #define MSM_TMR0_BASE IOMEM(0xF0201000)
70 #define MSM_GPIO1_BASE IOMEM(0xE0003000) 69 #define MSM_GPIO1_BASE IOMEM(0xE0003000)
71 #define MSM_GPIO2_BASE IOMEM(0xE0004000) 70 #define MSM_GPIO2_BASE IOMEM(0xE0004000)
72 71
73 #endif 72 #endif
arch/arm/mach-msm/io.c
Diff comments   View file @ 95360fd
1 /* arch/arm/mach-msm/io.c 1 /* arch/arm/mach-msm/io.c
2 * 2 *
3 * MSM7K, QSD io support 3 * MSM7K, QSD io support
4 * 4 *
5 * Copyright (C) 2007 Google, Inc. 5 * Copyright (C) 2007 Google, Inc.
6 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. 6 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
7 * Author: Brian Swetland <swetland@google.com> 7 * Author: Brian Swetland <swetland@google.com>
8 * 8 *
9 * This software is licensed under the terms of the GNU General Public 9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and 10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms. 11 * may be copied, distributed, and modified under those terms.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 */ 18 */
19 19
20 #include <linux/kernel.h> 20 #include <linux/kernel.h>
21 #include <linux/init.h> 21 #include <linux/init.h>
22 #include <linux/io.h> 22 #include <linux/io.h>
23 #include <linux/export.h> 23 #include <linux/export.h>
24 24
25 #include <mach/hardware.h> 25 #include <mach/hardware.h>
26 #include <asm/page.h> 26 #include <asm/page.h>
27 #include <mach/msm_iomap.h> 27 #include <mach/msm_iomap.h>
28 #include <asm/mach/map.h> 28 #include <asm/mach/map.h>
29 29
30 #include <mach/board.h> 30 #include <mach/board.h>
31 31
32 #include "common.h" 32 #include "common.h"
33 33
34 #define MSM_CHIP_DEVICE_TYPE(name, chip, mem_type) { \ 34 #define MSM_CHIP_DEVICE_TYPE(name, chip, mem_type) { \
35 .virtual = (unsigned long) MSM_##name##_BASE, \ 35 .virtual = (unsigned long) MSM_##name##_BASE, \
36 .pfn = __phys_to_pfn(chip##_##name##_PHYS), \ 36 .pfn = __phys_to_pfn(chip##_##name##_PHYS), \
37 .length = chip##_##name##_SIZE, \ 37 .length = chip##_##name##_SIZE, \
38 .type = mem_type, \ 38 .type = mem_type, \
39 } 39 }
40 40
41 #define MSM_DEVICE_TYPE(name, mem_type) \ 41 #define MSM_DEVICE_TYPE(name, mem_type) \
42 MSM_CHIP_DEVICE_TYPE(name, MSM, mem_type) 42 MSM_CHIP_DEVICE_TYPE(name, MSM, mem_type)
43 #define MSM_CHIP_DEVICE(name, chip) \ 43 #define MSM_CHIP_DEVICE(name, chip) \
44 MSM_CHIP_DEVICE_TYPE(name, chip, MT_DEVICE) 44 MSM_CHIP_DEVICE_TYPE(name, chip, MT_DEVICE)
45 #define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM) 45 #define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM)
46 46
47 #if defined(CONFIG_ARCH_MSM7X00A) 47 #if defined(CONFIG_ARCH_MSM7X00A)
48 static struct map_desc msm_io_desc[] __initdata = { 48 static struct map_desc msm_io_desc[] __initdata = {
49 MSM_DEVICE_TYPE(VIC, MT_DEVICE_NONSHARED), 49 MSM_DEVICE_TYPE(VIC, MT_DEVICE_NONSHARED),
50 MSM_CHIP_DEVICE_TYPE(CSR, MSM7X00, MT_DEVICE_NONSHARED), 50 MSM_CHIP_DEVICE_TYPE(CSR, MSM7X00, MT_DEVICE_NONSHARED),
51 MSM_DEVICE_TYPE(DMOV, MT_DEVICE_NONSHARED), 51 MSM_DEVICE_TYPE(DMOV, MT_DEVICE_NONSHARED),
52 MSM_CHIP_DEVICE_TYPE(GPIO1, MSM7X00, MT_DEVICE_NONSHARED), 52 MSM_CHIP_DEVICE_TYPE(GPIO1, MSM7X00, MT_DEVICE_NONSHARED),
53 MSM_CHIP_DEVICE_TYPE(GPIO2, MSM7X00, MT_DEVICE_NONSHARED), 53 MSM_CHIP_DEVICE_TYPE(GPIO2, MSM7X00, MT_DEVICE_NONSHARED),
54 MSM_DEVICE_TYPE(CLK_CTL, MT_DEVICE_NONSHARED), 54 MSM_DEVICE_TYPE(CLK_CTL, MT_DEVICE_NONSHARED),
55 #if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \ 55 #if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
56 defined(CONFIG_DEBUG_MSM_UART3) 56 defined(CONFIG_DEBUG_MSM_UART3)
57 MSM_DEVICE_TYPE(DEBUG_UART, MT_DEVICE_NONSHARED), 57 MSM_DEVICE_TYPE(DEBUG_UART, MT_DEVICE_NONSHARED),
58 #endif 58 #endif
59 { 59 {
60 .virtual = (unsigned long) MSM_SHARED_RAM_BASE, 60 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
61 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS), 61 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
62 .length = MSM_SHARED_RAM_SIZE, 62 .length = MSM_SHARED_RAM_SIZE,
63 .type = MT_DEVICE, 63 .type = MT_DEVICE,
64 }, 64 },
65 }; 65 };
66 66
67 void __init msm_map_common_io(void) 67 void __init msm_map_common_io(void)
68 { 68 {
69 /* Make sure the peripheral register window is closed, since 69 /* Make sure the peripheral register window is closed, since
70 * we will use PTE flags (TEX[1]=1,B=0,C=1) to determine which 70 * we will use PTE flags (TEX[1]=1,B=0,C=1) to determine which
71 * pages are peripheral interface or not. 71 * pages are peripheral interface or not.
72 */ 72 */
73 asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0)); 73 asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0));
74 iotable_init(msm_io_desc, ARRAY_SIZE(msm_io_desc)); 74 iotable_init(msm_io_desc, ARRAY_SIZE(msm_io_desc));
75 } 75 }
76 #endif 76 #endif
77 77
78 #ifdef CONFIG_ARCH_QSD8X50 78 #ifdef CONFIG_ARCH_QSD8X50
79 static struct map_desc qsd8x50_io_desc[] __initdata = { 79 static struct map_desc qsd8x50_io_desc[] __initdata = {
80 MSM_DEVICE(VIC), 80 MSM_DEVICE(VIC),
81 MSM_CHIP_DEVICE(CSR, QSD8X50), 81 MSM_CHIP_DEVICE(CSR, QSD8X50),
82 MSM_DEVICE(DMOV), 82 MSM_DEVICE(DMOV),
83 MSM_CHIP_DEVICE(GPIO1, QSD8X50), 83 MSM_CHIP_DEVICE(GPIO1, QSD8X50),
84 MSM_CHIP_DEVICE(GPIO2, QSD8X50), 84 MSM_CHIP_DEVICE(GPIO2, QSD8X50),
85 MSM_DEVICE(CLK_CTL), 85 MSM_DEVICE(CLK_CTL),
86 MSM_DEVICE(SIRC), 86 MSM_DEVICE(SIRC),
87 MSM_DEVICE(SCPLL), 87 MSM_DEVICE(SCPLL),
88 MSM_DEVICE(AD5), 88 MSM_DEVICE(AD5),
89 MSM_DEVICE(MDC), 89 MSM_DEVICE(MDC),
90 #if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \ 90 #if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
91 defined(CONFIG_DEBUG_MSM_UART3) 91 defined(CONFIG_DEBUG_MSM_UART3)
92 MSM_DEVICE(DEBUG_UART), 92 MSM_DEVICE(DEBUG_UART),
93 #endif 93 #endif
94 { 94 {
95 .virtual = (unsigned long) MSM_SHARED_RAM_BASE, 95 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
96 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS), 96 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
97 .length = MSM_SHARED_RAM_SIZE, 97 .length = MSM_SHARED_RAM_SIZE,
98 .type = MT_DEVICE, 98 .type = MT_DEVICE,
99 }, 99 },
100 }; 100 };
101 101
102 void __init msm_map_qsd8x50_io(void) 102 void __init msm_map_qsd8x50_io(void)
103 { 103 {
104 iotable_init(qsd8x50_io_desc, ARRAY_SIZE(qsd8x50_io_desc)); 104 iotable_init(qsd8x50_io_desc, ARRAY_SIZE(qsd8x50_io_desc));
105 } 105 }
106 #endif /* CONFIG_ARCH_QSD8X50 */ 106 #endif /* CONFIG_ARCH_QSD8X50 */
107 107
108 #ifdef CONFIG_ARCH_MSM8X60 108 #ifdef CONFIG_ARCH_MSM8X60
109 static struct map_desc msm8x60_io_desc[] __initdata = { 109 static struct map_desc msm8x60_io_desc[] __initdata = {
110 MSM_CHIP_DEVICE(QGIC_DIST, MSM8X60), 110 MSM_CHIP_DEVICE(QGIC_DIST, MSM8X60),
111 MSM_CHIP_DEVICE(QGIC_CPU, MSM8X60), 111 MSM_CHIP_DEVICE(QGIC_CPU, MSM8X60),
112 MSM_CHIP_DEVICE(TMR, MSM8X60), 112 MSM_CHIP_DEVICE(TMR, MSM8X60),
113 MSM_CHIP_DEVICE(TMR0, MSM8X60), 113 MSM_CHIP_DEVICE(TMR0, MSM8X60),
114 MSM_DEVICE(ACC),
115 MSM_DEVICE(GCC),
116 #ifdef CONFIG_DEBUG_MSM8660_UART 114 #ifdef CONFIG_DEBUG_MSM8660_UART
117 MSM_DEVICE(DEBUG_UART), 115 MSM_DEVICE(DEBUG_UART),
118 #endif 116 #endif
119 }; 117 };
120 118
121 void __init msm_map_msm8x60_io(void) 119 void __init msm_map_msm8x60_io(void)
122 { 120 {
123 iotable_init(msm8x60_io_desc, ARRAY_SIZE(msm8x60_io_desc)); 121 iotable_init(msm8x60_io_desc, ARRAY_SIZE(msm8x60_io_desc));
124 } 122 }
125 #endif /* CONFIG_ARCH_MSM8X60 */ 123 #endif /* CONFIG_ARCH_MSM8X60 */
126 124
127 #ifdef CONFIG_ARCH_MSM8960 125 #ifdef CONFIG_ARCH_MSM8960
128 static struct map_desc msm8960_io_desc[] __initdata = { 126 static struct map_desc msm8960_io_desc[] __initdata = {
129 MSM_CHIP_DEVICE(QGIC_DIST, MSM8960), 127 MSM_CHIP_DEVICE(QGIC_DIST, MSM8960),
130 MSM_CHIP_DEVICE(QGIC_CPU, MSM8960), 128 MSM_CHIP_DEVICE(QGIC_CPU, MSM8960),
131 MSM_CHIP_DEVICE(TMR, MSM8960), 129 MSM_CHIP_DEVICE(TMR, MSM8960),
132 MSM_CHIP_DEVICE(TMR0, MSM8960), 130 MSM_CHIP_DEVICE(TMR0, MSM8960),
133 #ifdef CONFIG_DEBUG_MSM8960_UART 131 #ifdef CONFIG_DEBUG_MSM8960_UART
134 MSM_DEVICE(DEBUG_UART), 132 MSM_DEVICE(DEBUG_UART),
135 #endif 133 #endif
136 }; 134 };
137 135
138 void __init msm_map_msm8960_io(void) 136 void __init msm_map_msm8960_io(void)
139 { 137 {
140 iotable_init(msm8960_io_desc, ARRAY_SIZE(msm8960_io_desc)); 138 iotable_init(msm8960_io_desc, ARRAY_SIZE(msm8960_io_desc));
141 } 139 }
142 #endif /* CONFIG_ARCH_MSM8960 */ 140 #endif /* CONFIG_ARCH_MSM8960 */
143 141
144 #ifdef CONFIG_ARCH_MSM7X30 142 #ifdef CONFIG_ARCH_MSM7X30
145 static struct map_desc msm7x30_io_desc[] __initdata = { 143 static struct map_desc msm7x30_io_desc[] __initdata = {
146 MSM_DEVICE(VIC), 144 MSM_DEVICE(VIC),
147 MSM_CHIP_DEVICE(CSR, MSM7X30), 145 MSM_CHIP_DEVICE(CSR, MSM7X30),
148 MSM_DEVICE(DMOV), 146 MSM_DEVICE(DMOV),
149 MSM_CHIP_DEVICE(GPIO1, MSM7X30), 147 MSM_CHIP_DEVICE(GPIO1, MSM7X30),
150 MSM_CHIP_DEVICE(GPIO2, MSM7X30), 148 MSM_CHIP_DEVICE(GPIO2, MSM7X30),
151 MSM_DEVICE(CLK_CTL), 149 MSM_DEVICE(CLK_CTL),
152 MSM_DEVICE(CLK_CTL_SH2), 150 MSM_DEVICE(CLK_CTL_SH2),
153 MSM_DEVICE(AD5), 151 MSM_DEVICE(AD5),
154 MSM_DEVICE(MDC), 152 MSM_DEVICE(MDC),
155 MSM_DEVICE(ACC), 153 MSM_DEVICE(ACC),
156 MSM_DEVICE(SAW), 154 MSM_DEVICE(SAW),
157 MSM_DEVICE(GCC), 155 MSM_DEVICE(GCC),
158 MSM_DEVICE(TCSR), 156 MSM_DEVICE(TCSR),
159 #if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \ 157 #if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
160 defined(CONFIG_DEBUG_MSM_UART3) 158 defined(CONFIG_DEBUG_MSM_UART3)
161 MSM_DEVICE(DEBUG_UART), 159 MSM_DEVICE(DEBUG_UART),
162 #endif 160 #endif
163 { 161 {
164 .virtual = (unsigned long) MSM_SHARED_RAM_BASE, 162 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
165 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS), 163 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
166 .length = MSM_SHARED_RAM_SIZE, 164 .length = MSM_SHARED_RAM_SIZE,
167 .type = MT_DEVICE, 165 .type = MT_DEVICE,
168 }, 166 },
169 }; 167 };
170 168
171 void __init msm_map_msm7x30_io(void) 169 void __init msm_map_msm7x30_io(void)
172 { 170 {
173 iotable_init(msm7x30_io_desc, ARRAY_SIZE(msm7x30_io_desc)); 171 iotable_init(msm7x30_io_desc, ARRAY_SIZE(msm7x30_io_desc));
174 } 172 }
175 #endif /* CONFIG_ARCH_MSM7X30 */ 173 #endif /* CONFIG_ARCH_MSM7X30 */
176 174
177 void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size, 175 void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size,
178 unsigned int mtype, void *caller) 176 unsigned int mtype, void *caller)
179 { 177 {
180 if (mtype == MT_DEVICE) { 178 if (mtype == MT_DEVICE) {
181 /* The peripherals in the 88000000 - D0000000 range 179 /* The peripherals in the 88000000 - D0000000 range
182 * are only accessible by type MT_DEVICE_NONSHARED. 180 * are only accessible by type MT_DEVICE_NONSHARED.
183 * Adjust mtype as necessary to make this "just work." 181 * Adjust mtype as necessary to make this "just work."
184 */ 182 */
185 if ((phys_addr >= 0x88000000) && (phys_addr < 0xD0000000)) 183 if ((phys_addr >= 0x88000000) && (phys_addr < 0xD0000000))
186 mtype = MT_DEVICE_NONSHARED; 184 mtype = MT_DEVICE_NONSHARED;
187 } 185 }
188 186
189 return __arm_ioremap_caller(phys_addr, size, mtype, caller); 187 return __arm_ioremap_caller(phys_addr, size, mtype, caller);
190 } 188 }
191 189
arch/arm/mach-s3c64xx/mach-crag6410-module.c
Diff comments   View file @ 95360fd
1 /* Speyside modules for Cragganmore - board data probing 1 /* Speyside modules for Cragganmore - board data probing
2 * 2 *
3 * Copyright 2011 Wolfson Microelectronics plc 3 * Copyright 2011 Wolfson Microelectronics plc
4 * Mark Brown <broonie@opensource.wolfsonmicro.com> 4 * Mark Brown <broonie@opensource.wolfsonmicro.com>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11 #include <linux/export.h> 11 #include <linux/export.h>
12 #include <linux/interrupt.h> 12 #include <linux/interrupt.h>
13 #include <linux/i2c.h> 13 #include <linux/i2c.h>
14 #include <linux/spi/spi.h> 14 #include <linux/spi/spi.h>
15 15
16 #include <linux/mfd/wm831x/irq.h> 16 #include <linux/mfd/wm831x/irq.h>
17 #include <linux/mfd/wm831x/gpio.h> 17 #include <linux/mfd/wm831x/gpio.h>
18 #include <linux/mfd/wm8994/pdata.h> 18 #include <linux/mfd/wm8994/pdata.h>
19 #include <linux/mfd/arizona/pdata.h>
19 20
20 #include <linux/regulator/machine.h> 21 #include <linux/regulator/machine.h>
21 22
22 #include <sound/wm5100.h> 23 #include <sound/wm5100.h>
23 #include <sound/wm8996.h> 24 #include <sound/wm8996.h>
24 #include <sound/wm8962.h> 25 #include <sound/wm8962.h>
25 #include <sound/wm9081.h> 26 #include <sound/wm9081.h>
26 27
27 #include <plat/s3c64xx-spi.h> 28 #include <plat/s3c64xx-spi.h>
28 29
29 #include <mach/crag6410.h> 30 #include <mach/crag6410.h>
30 31
31 static struct s3c64xx_spi_csinfo wm0010_spi_csinfo = { 32 static struct s3c64xx_spi_csinfo wm0010_spi_csinfo = {
32 .line = S3C64XX_GPC(3), 33 .line = S3C64XX_GPC(3),
33 }; 34 };
34 35
35 static struct spi_board_info wm1253_devs[] = { 36 static struct spi_board_info wm1253_devs[] = {
36 [0] = { 37 [0] = {
37 .modalias = "wm0010", 38 .modalias = "wm0010",
38 .bus_num = 0, 39 .bus_num = 0,
39 .chip_select = 0, 40 .chip_select = 0,
40 .mode = SPI_MODE_0, 41 .mode = SPI_MODE_0,
41 .irq = S3C_EINT(5), 42 .irq = S3C_EINT(5),
42 .controller_data = &wm0010_spi_csinfo, 43 .controller_data = &wm0010_spi_csinfo,
43 }, 44 },
44 }; 45 };
45 46
46 static struct wm5100_pdata wm5100_pdata = { 47 static struct wm5100_pdata wm5100_pdata = {
47 .ldo_ena = S3C64XX_GPN(7), 48 .ldo_ena = S3C64XX_GPN(7),
48 .irq_flags = IRQF_TRIGGER_HIGH, 49 .irq_flags = IRQF_TRIGGER_HIGH,
49 .gpio_base = CODEC_GPIO_BASE, 50 .gpio_base = CODEC_GPIO_BASE,
50 51
51 .in_mode = { 52 .in_mode = {
52 WM5100_IN_DIFF, 53 WM5100_IN_DIFF,
53 WM5100_IN_DIFF, 54 WM5100_IN_DIFF,
54 WM5100_IN_DIFF, 55 WM5100_IN_DIFF,
55 WM5100_IN_SE, 56 WM5100_IN_SE,
56 }, 57 },
57 58
58 .hp_pol = CODEC_GPIO_BASE + 3, 59 .hp_pol = CODEC_GPIO_BASE + 3,
59 .jack_modes = { 60 .jack_modes = {
60 { WM5100_MICDET_MICBIAS3, 0, 0 }, 61 { WM5100_MICDET_MICBIAS3, 0, 0 },
61 { WM5100_MICDET_MICBIAS2, 1, 1 }, 62 { WM5100_MICDET_MICBIAS2, 1, 1 },
62 }, 63 },
63 64
64 .gpio_defaults = { 65 .gpio_defaults = {
65 0, 66 0,
66 0, 67 0,
67 0, 68 0,
68 0, 69 0,
69 0x2, /* IRQ: CMOS output */ 70 0x2, /* IRQ: CMOS output */
70 0x3, /* CLKOUT: CMOS output */ 71 0x3, /* CLKOUT: CMOS output */
71 }, 72 },
72 }; 73 };
73 74
74 static struct wm8996_retune_mobile_config wm8996_retune[] = { 75 static struct wm8996_retune_mobile_config wm8996_retune[] = {
75 { 76 {
76 .name = "Sub LPF", 77 .name = "Sub LPF",
77 .rate = 48000, 78 .rate = 48000,
78 .regs = { 79 .regs = {
79 0x6318, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000, 80 0x6318, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
80 0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000, 81 0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
81 0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000 82 0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
82 }, 83 },
83 }, 84 },
84 { 85 {
85 .name = "Sub HPF", 86 .name = "Sub HPF",
86 .rate = 48000, 87 .rate = 48000,
87 .regs = { 88 .regs = {
88 0x000A, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000, 89 0x000A, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
89 0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000, 90 0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
90 0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000 91 0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
91 }, 92 },
92 }, 93 },
93 }; 94 };
94 95
95 static struct wm8996_pdata wm8996_pdata __initdata = { 96 static struct wm8996_pdata wm8996_pdata __initdata = {
96 .ldo_ena = S3C64XX_GPN(7), 97 .ldo_ena = S3C64XX_GPN(7),
97 .gpio_base = CODEC_GPIO_BASE, 98 .gpio_base = CODEC_GPIO_BASE,
98 .micdet_def = 1, 99 .micdet_def = 1,
99 .inl_mode = WM8996_DIFFERRENTIAL_1, 100 .inl_mode = WM8996_DIFFERRENTIAL_1,
100 .inr_mode = WM8996_DIFFERRENTIAL_1, 101 .inr_mode = WM8996_DIFFERRENTIAL_1,
101 102
102 .irq_flags = IRQF_TRIGGER_RISING, 103 .irq_flags = IRQF_TRIGGER_RISING,
103 104
104 .gpio_default = { 105 .gpio_default = {
105 0x8001, /* GPIO1 == ADCLRCLK1 */ 106 0x8001, /* GPIO1 == ADCLRCLK1 */
106 0x8001, /* GPIO2 == ADCLRCLK2, input due to CPU */ 107 0x8001, /* GPIO2 == ADCLRCLK2, input due to CPU */
107 0x0141, /* GPIO3 == HP_SEL */ 108 0x0141, /* GPIO3 == HP_SEL */
108 0x0002, /* GPIO4 == IRQ */ 109 0x0002, /* GPIO4 == IRQ */
109 0x020e, /* GPIO5 == CLKOUT */ 110 0x020e, /* GPIO5 == CLKOUT */
110 }, 111 },
111 112
112 .retune_mobile_cfgs = wm8996_retune, 113 .retune_mobile_cfgs = wm8996_retune,
113 .num_retune_mobile_cfgs = ARRAY_SIZE(wm8996_retune), 114 .num_retune_mobile_cfgs = ARRAY_SIZE(wm8996_retune),
114 }; 115 };
115 116
116 static struct wm8962_pdata wm8962_pdata __initdata = { 117 static struct wm8962_pdata wm8962_pdata __initdata = {
117 .gpio_init = { 118 .gpio_init = {
118 0, 119 0,
119 WM8962_GPIO_FN_OPCLK, 120 WM8962_GPIO_FN_OPCLK,
120 WM8962_GPIO_FN_DMICCLK, 121 WM8962_GPIO_FN_DMICCLK,
121 0, 122 0,
122 0x8000 | WM8962_GPIO_FN_DMICDAT, 123 0x8000 | WM8962_GPIO_FN_DMICDAT,
123 WM8962_GPIO_FN_IRQ, /* Open drain mode */ 124 WM8962_GPIO_FN_IRQ, /* Open drain mode */
124 }, 125 },
125 .in4_dc_measure = true, 126 .in4_dc_measure = true,
126 }; 127 };
127 128
128 static struct wm9081_pdata wm9081_pdata __initdata = { 129 static struct wm9081_pdata wm9081_pdata __initdata = {
129 .irq_high = false, 130 .irq_high = false,
130 .irq_cmos = false, 131 .irq_cmos = false,
131 }; 132 };
132 133
133 static const struct i2c_board_info wm1254_devs[] = { 134 static const struct i2c_board_info wm1254_devs[] = {
134 { I2C_BOARD_INFO("wm8996", 0x1a), 135 { I2C_BOARD_INFO("wm8996", 0x1a),
135 .platform_data = &wm8996_pdata, 136 .platform_data = &wm8996_pdata,
136 .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2, 137 .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
137 }, 138 },
138 { I2C_BOARD_INFO("wm9081", 0x6c), 139 { I2C_BOARD_INFO("wm9081", 0x6c),
139 .platform_data = &wm9081_pdata, }, 140 .platform_data = &wm9081_pdata, },
140 }; 141 };
141 142
142 static const struct i2c_board_info wm1255_devs[] = { 143 static const struct i2c_board_info wm1255_devs[] = {
143 { I2C_BOARD_INFO("wm5100", 0x1a), 144 { I2C_BOARD_INFO("wm5100", 0x1a),
144 .platform_data = &wm5100_pdata, 145 .platform_data = &wm5100_pdata,
145 .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2, 146 .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
146 }, 147 },
147 { I2C_BOARD_INFO("wm9081", 0x6c), 148 { I2C_BOARD_INFO("wm9081", 0x6c),
148 .platform_data = &wm9081_pdata, }, 149 .platform_data = &wm9081_pdata, },
149 }; 150 };
150 151
151 static const struct i2c_board_info wm1259_devs[] = { 152 static const struct i2c_board_info wm1259_devs[] = {
152 { I2C_BOARD_INFO("wm8962", 0x1a), 153 { I2C_BOARD_INFO("wm8962", 0x1a),
153 .platform_data = &wm8962_pdata, 154 .platform_data = &wm8962_pdata,
154 .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2, 155 .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
155 }, 156 },
156 }; 157 };
157 158
158 static struct regulator_init_data wm8994_ldo1 = { 159 static struct regulator_init_data wm8994_ldo1 = {
159 .supply_regulator = "WALLVDD", 160 .supply_regulator = "WALLVDD",
160 }; 161 };
161 162
162 static struct regulator_init_data wm8994_ldo2 = { 163 static struct regulator_init_data wm8994_ldo2 = {
163 .supply_regulator = "WALLVDD", 164 .supply_regulator = "WALLVDD",
164 }; 165 };
165 166
166 static struct wm8994_pdata wm8994_pdata = { 167 static struct wm8994_pdata wm8994_pdata = {
167 .gpio_base = CODEC_GPIO_BASE, 168 .gpio_base = CODEC_GPIO_BASE,
168 .gpio_defaults = { 169 .gpio_defaults = {
169 0x3, /* IRQ out, active high, CMOS */ 170 0x3, /* IRQ out, active high, CMOS */
170 }, 171 },
171 .ldo = { 172 .ldo = {
172 { .init_data = &wm8994_ldo1, }, 173 { .init_data = &wm8994_ldo1, },
173 { .init_data = &wm8994_ldo2, }, 174 { .init_data = &wm8994_ldo2, },
174 }, 175 },
175 }; 176 };
176 177
177 static const struct i2c_board_info wm1277_devs[] = { 178 static const struct i2c_board_info wm1277_devs[] = {
178 { I2C_BOARD_INFO("wm8958", 0x1a), /* WM8958 is the superset */ 179 { I2C_BOARD_INFO("wm8958", 0x1a), /* WM8958 is the superset */
179 .platform_data = &wm8994_pdata, 180 .platform_data = &wm8994_pdata,
180 .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2, 181 .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
181 }, 182 },
182 }; 183 };
183 184
184 static const struct i2c_board_info wm5102_devs[] = { 185 static struct arizona_pdata wm5102_pdata = {
185 { I2C_BOARD_INFO("wm5102", 0x1a), 186 .ldoena = S3C64XX_GPN(7),
186 .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2, }, 187 .gpio_base = CODEC_GPIO_BASE,
188 .irq_active_high = true,
189 .micd_pol_gpio = CODEC_GPIO_BASE + 4,
190 .gpio_defaults = {
191 [2] = 0x10000, /* AIF3TXLRCLK */
192 [3] = 0x4, /* OPCLK */
193 },
187 }; 194 };
188 195
196 static struct s3c64xx_spi_csinfo wm5102_spi_csinfo = {
197 .line = S3C64XX_GPN(5),
198 };
199
200 static struct spi_board_info wm5102_spi_devs[] = {
201 [0] = {
202 .modalias = "wm5102",
203 .max_speed_hz = 10 * 1000 * 1000,
204 .bus_num = 0,
205 .chip_select = 0,
206 .mode = SPI_MODE_0,
207 .irq = GLENFARCLAS_PMIC_IRQ_BASE +
208 WM831X_IRQ_GPIO_2,
209 .controller_data = &wm5102_spi_csinfo,
210 .platform_data = &wm5102_pdata,
211 },
212 };
213
189 static const struct i2c_board_info wm6230_i2c_devs[] = { 214 static const struct i2c_board_info wm6230_i2c_devs[] = {
190 { I2C_BOARD_INFO("wm9081", 0x6c), 215 { I2C_BOARD_INFO("wm9081", 0x6c),
191 .platform_data = &wm9081_pdata, }, 216 .platform_data = &wm9081_pdata, },
192 }; 217 };
193 218
194 static __devinitdata const struct { 219 static __devinitdata const struct {
195 u8 id; 220 u8 id;
196 const char *name; 221 const char *name;
197 const struct i2c_board_info *i2c_devs; 222 const struct i2c_board_info *i2c_devs;
198 int num_i2c_devs; 223 int num_i2c_devs;
199 const struct spi_board_info *spi_devs; 224 const struct spi_board_info *spi_devs;
200 int num_spi_devs; 225 int num_spi_devs;
201 } gf_mods[] = { 226 } gf_mods[] = {
202 { .id = 0x01, .name = "1250-EV1 Springbank" }, 227 { .id = 0x01, .name = "1250-EV1 Springbank" },
203 { .id = 0x02, .name = "1251-EV1 Jura" }, 228 { .id = 0x02, .name = "1251-EV1 Jura" },
204 { .id = 0x03, .name = "1252-EV1 Glenlivet" }, 229 { .id = 0x03, .name = "1252-EV1 Glenlivet" },
205 { .id = 0x11, .name = "6249-EV2 Glenfarclas", }, 230 { .id = 0x11, .name = "6249-EV2 Glenfarclas", },
206 { .id = 0x14, .name = "6271-EV1 Lochnagar" }, 231 { .id = 0x14, .name = "6271-EV1 Lochnagar" },
207 { .id = 0x15, .name = "6320-EV1 Bells", 232 { .id = 0x15, .name = "6320-EV1 Bells",
208 .i2c_devs = wm6230_i2c_devs, 233 .i2c_devs = wm6230_i2c_devs,
209 .num_i2c_devs = ARRAY_SIZE(wm6230_i2c_devs) }, 234 .num_i2c_devs = ARRAY_SIZE(wm6230_i2c_devs) },
210 { .id = 0x21, .name = "1275-EV1 Mortlach" }, 235 { .id = 0x21, .name = "1275-EV1 Mortlach" },
211 { .id = 0x25, .name = "1274-EV1 Glencadam" }, 236 { .id = 0x25, .name = "1274-EV1 Glencadam" },
212 { .id = 0x31, .name = "1253-EV1 Tomatin", 237 { .id = 0x31, .name = "1253-EV1 Tomatin",
213 .spi_devs = wm1253_devs, .num_spi_devs = ARRAY_SIZE(wm1253_devs) }, 238 .spi_devs = wm1253_devs, .num_spi_devs = ARRAY_SIZE(wm1253_devs) },
214 { .id = 0x32, .name = "XXXX-EV1 Caol Illa" }, 239 { .id = 0x32, .name = "XXXX-EV1 Caol Illa" },
215 { .id = 0x33, .name = "XXXX-EV1 Oban" }, 240 { .id = 0x33, .name = "XXXX-EV1 Oban" },
216 { .id = 0x34, .name = "WM0010-6320-CS42 Balblair" }, 241 { .id = 0x34, .name = "WM0010-6320-CS42 Balblair" },
217 { .id = 0x39, .name = "1254-EV1 Dallas Dhu", 242 { .id = 0x39, .name = "1254-EV1 Dallas Dhu",
218 .i2c_devs = wm1254_devs, .num_i2c_devs = ARRAY_SIZE(wm1254_devs) }, 243 .i2c_devs = wm1254_devs, .num_i2c_devs = ARRAY_SIZE(wm1254_devs) },
219 { .id = 0x3a, .name = "1259-EV1 Tobermory", 244 { .id = 0x3a, .name = "1259-EV1 Tobermory",
220 .i2c_devs = wm1259_devs, .num_i2c_devs = ARRAY_SIZE(wm1259_devs) }, 245 .i2c_devs = wm1259_devs, .num_i2c_devs = ARRAY_SIZE(wm1259_devs) },
221 { .id = 0x3b, .name = "1255-EV1 Kilchoman", 246 { .id = 0x3b, .name = "1255-EV1 Kilchoman",
222 .i2c_devs = wm1255_devs, .num_i2c_devs = ARRAY_SIZE(wm1255_devs) }, 247 .i2c_devs = wm1255_devs, .num_i2c_devs = ARRAY_SIZE(wm1255_devs) },
223 { .id = 0x3c, .name = "1273-EV1 Longmorn" }, 248 { .id = 0x3c, .name = "1273-EV1 Longmorn" },
224 { .id = 0x3d, .name = "1277-EV1 Littlemill", 249 { .id = 0x3d, .name = "1277-EV1 Littlemill",
225 .i2c_devs = wm1277_devs, .num_i2c_devs = ARRAY_SIZE(wm1277_devs) }, 250 .i2c_devs = wm1277_devs, .num_i2c_devs = ARRAY_SIZE(wm1277_devs) },
226 { .id = 0x3e, .name = "WM5102-6271-EV1-CS127", 251 { .id = 0x3e, .name = "WM5102-6271-EV1-CS127 Amrut",
227 .i2c_devs = wm5102_devs, .num_i2c_devs = ARRAY_SIZE(wm5102_devs) }, 252 .spi_devs = wm5102_spi_devs,
253 .num_spi_devs = ARRAY_SIZE(wm5102_spi_devs) },
228 }; 254 };
229 255
230 static __devinit int wlf_gf_module_probe(struct i2c_client *i2c, 256 static __devinit int wlf_gf_module_probe(struct i2c_client *i2c,
231 const struct i2c_device_id *i2c_id) 257 const struct i2c_device_id *i2c_id)
232 { 258 {
233 int ret, i, j, id, rev; 259 int ret, i, j, id, rev;
234 260
235 ret = i2c_smbus_read_byte_data(i2c, 0); 261 ret = i2c_smbus_read_byte_data(i2c, 0);
236 if (ret < 0) { 262 if (ret < 0) {
237 dev_err(&i2c->dev, "Failed to read ID: %d\n", ret); 263 dev_err(&i2c->dev, "Failed to read ID: %d\n", ret);
238 return ret; 264 return ret;
239 } 265 }
240 266
241 id = (ret & 0xfe) >> 2; 267 id = (ret & 0xfe) >> 2;
242 rev = ret & 0x3; 268 rev = ret & 0x3;
243 for (i = 0; i < ARRAY_SIZE(gf_mods); i++) 269 for (i = 0; i < ARRAY_SIZE(gf_mods); i++)
244 if (id == gf_mods[i].id) 270 if (id == gf_mods[i].id)
245 break; 271 break;
246 272
247 if (i < ARRAY_SIZE(gf_mods)) { 273 if (i < ARRAY_SIZE(gf_mods)) {
248 dev_info(&i2c->dev, "%s revision %d\n", 274 dev_info(&i2c->dev, "%s revision %d\n",
249 gf_mods[i].name, rev + 1); 275 gf_mods[i].name, rev + 1);
250 276
251 for (j = 0; j < gf_mods[i].num_i2c_devs; j++) { 277 for (j = 0; j < gf_mods[i].num_i2c_devs; j++) {
252 if (!i2c_new_device(i2c->adapter, 278 if (!i2c_new_device(i2c->adapter,
253 &(gf_mods[i].i2c_devs[j]))) 279 &(gf_mods[i].i2c_devs[j])))
254 dev_err(&i2c->dev, 280 dev_err(&i2c->dev,
255 "Failed to register dev: %d\n", ret); 281 "Failed to register dev: %d\n", ret);
256 } 282 }
257 283
258 spi_register_board_info(gf_mods[i].spi_devs, 284 spi_register_board_info(gf_mods[i].spi_devs,
259 gf_mods[i].num_spi_devs); 285 gf_mods[i].num_spi_devs);
260 } else { 286 } else {
261 dev_warn(&i2c->dev, "Unknown module ID 0x%x revision %d\n", 287 dev_warn(&i2c->dev, "Unknown module ID 0x%x revision %d\n",
262 id, rev + 1); 288 id, rev + 1);
263 } 289 }
264 290
265 return 0; 291 return 0;
266 } 292 }
267 293
268 static const struct i2c_device_id wlf_gf_module_id[] = { 294 static const struct i2c_device_id wlf_gf_module_id[] = {
269 { "wlf-gf-module", 0 }, 295 { "wlf-gf-module", 0 },
270 { } 296 { }
271 }; 297 };
272 298
273 static struct i2c_driver wlf_gf_module_driver = { 299 static struct i2c_driver wlf_gf_module_driver = {
274 .driver = { 300 .driver = {
275 .name = "wlf-gf-module", 301 .name = "wlf-gf-module",
276 .owner = THIS_MODULE, 302 .owner = THIS_MODULE,
277 }, 303 },
278 .probe = wlf_gf_module_probe, 304 .probe = wlf_gf_module_probe,
279 .id_table = wlf_gf_module_id, 305 .id_table = wlf_gf_module_id,
280 }; 306 };
281 307
282 static int __init wlf_gf_module_register(void) 308 static int __init wlf_gf_module_register(void)
283 { 309 {
284 return i2c_add_driver(&wlf_gf_module_driver); 310 return i2c_add_driver(&wlf_gf_module_driver);
285 } 311 }
286 module_init(wlf_gf_module_register); 312 module_init(wlf_gf_module_register);
287 313
arch/arm/mach-s3c64xx/mach-crag6410.c
Diff comments   View file @ 95360fd
1 /* linux/arch/arm/mach-s3c64xx/mach-crag6410.c 1 /* linux/arch/arm/mach-s3c64xx/mach-crag6410.c
2 * 2 *
3 * Copyright 2011 Wolfson Microelectronics plc 3 * Copyright 2011 Wolfson Microelectronics plc
4 * Mark Brown <broonie@opensource.wolfsonmicro.com> 4 * Mark Brown <broonie@opensource.wolfsonmicro.com>
5 * 5 *
6 * Copyright 2011 Simtec Electronics 6 * Copyright 2011 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk> 7 * Ben Dooks <ben@simtec.co.uk>
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 */ 12 */
13 13
14 #include <linux/kernel.h> 14 #include <linux/kernel.h>
15 #include <linux/list.h> 15 #include <linux/list.h>
16 #include <linux/serial_core.h> 16 #include <linux/serial_core.h>
17 #include <linux/platform_device.h> 17 #include <linux/platform_device.h>
18 #include <linux/fb.h> 18 #include <linux/fb.h>
19 #include <linux/io.h> 19 #include <linux/io.h>
20 #include <linux/init.h> 20 #include <linux/init.h>
21 #include <linux/gpio.h> 21 #include <linux/gpio.h>
22 #include <linux/leds.h> 22 #include <linux/leds.h>
23 #include <linux/delay.h> 23 #include <linux/delay.h>
24 #include <linux/mmc/host.h> 24 #include <linux/mmc/host.h>
25 #include <linux/regulator/machine.h> 25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/fixed.h> 26 #include <linux/regulator/fixed.h>
27 #include <linux/pwm_backlight.h> 27 #include <linux/pwm_backlight.h>
28 #include <linux/dm9000.h> 28 #include <linux/dm9000.h>
29 #include <linux/gpio_keys.h> 29 #include <linux/gpio_keys.h>
30 #include <linux/basic_mmio_gpio.h> 30 #include <linux/basic_mmio_gpio.h>
31 #include <linux/spi/spi.h> 31 #include <linux/spi/spi.h>
32 32
33 #include <linux/i2c/pca953x.h> 33 #include <linux/i2c/pca953x.h>
34 #include <linux/platform_data/s3c-hsotg.h> 34 #include <linux/platform_data/s3c-hsotg.h>
35 35
36 #include <video/platform_lcd.h> 36 #include <video/platform_lcd.h>
37 37
38 #include <linux/mfd/wm831x/core.h> 38 #include <linux/mfd/wm831x/core.h>
39 #include <linux/mfd/wm831x/pdata.h> 39 #include <linux/mfd/wm831x/pdata.h>
40 #include <linux/mfd/wm831x/irq.h> 40 #include <linux/mfd/wm831x/irq.h>
41 #include <linux/mfd/wm831x/gpio.h> 41 #include <linux/mfd/wm831x/gpio.h>
42 42
43 #include <sound/wm1250-ev1.h> 43 #include <sound/wm1250-ev1.h>
44 44
45 #include <asm/hardware/vic.h> 45 #include <asm/hardware/vic.h>
46 #include <asm/mach/arch.h> 46 #include <asm/mach/arch.h>
47 #include <asm/mach-types.h> 47 #include <asm/mach-types.h>
48 48
49 #include <mach/hardware.h> 49 #include <mach/hardware.h>
50 #include <mach/map.h> 50 #include <mach/map.h>
51 51
52 #include <mach/regs-sys.h> 52 #include <mach/regs-sys.h>
53 #include <mach/regs-gpio.h> 53 #include <mach/regs-gpio.h>
54 #include <mach/regs-modem.h> 54 #include <mach/regs-modem.h>
55 #include <mach/crag6410.h> 55 #include <mach/crag6410.h>
56 56
57 #include <mach/regs-gpio-memport.h> 57 #include <mach/regs-gpio-memport.h>
58 58
59 #include <plat/regs-serial.h> 59 #include <plat/regs-serial.h>
60 #include <plat/regs-fb-v4.h> 60 #include <plat/regs-fb-v4.h>
61 #include <plat/fb.h> 61 #include <plat/fb.h>
62 #include <plat/sdhci.h> 62 #include <plat/sdhci.h>
63 #include <plat/gpio-cfg.h> 63 #include <plat/gpio-cfg.h>
64 #include <plat/s3c64xx-spi.h> 64 #include <plat/s3c64xx-spi.h>
65 65
66 #include <plat/keypad.h> 66 #include <plat/keypad.h>
67 #include <plat/clock.h> 67 #include <plat/clock.h>
68 #include <plat/devs.h> 68 #include <plat/devs.h>
69 #include <plat/cpu.h> 69 #include <plat/cpu.h>
70 #include <plat/adc.h> 70 #include <plat/adc.h>
71 #include <plat/iic.h> 71 #include <plat/iic.h>
72 #include <plat/pm.h> 72 #include <plat/pm.h>
73 73
74 #include "common.h" 74 #include "common.h"
75 75
76 /* serial port setup */ 76 /* serial port setup */
77 77
78 #define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK) 78 #define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
79 #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB) 79 #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
80 #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) 80 #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
81 81
82 static struct s3c2410_uartcfg crag6410_uartcfgs[] __initdata = { 82 static struct s3c2410_uartcfg crag6410_uartcfgs[] __initdata = {
83 [0] = { 83 [0] = {
84 .hwport = 0, 84 .hwport = 0,
85 .flags = 0, 85 .flags = 0,
86 .ucon = UCON, 86 .ucon = UCON,
87 .ulcon = ULCON, 87 .ulcon = ULCON,
88 .ufcon = UFCON, 88 .ufcon = UFCON,
89 }, 89 },
90 [1] = { 90 [1] = {
91 .hwport = 1, 91 .hwport = 1,
92 .flags = 0, 92 .flags = 0,
93 .ucon = UCON, 93 .ucon = UCON,
94 .ulcon = ULCON, 94 .ulcon = ULCON,
95 .ufcon = UFCON, 95 .ufcon = UFCON,
96 }, 96 },
97 [2] = { 97 [2] = {
98 .hwport = 2, 98 .hwport = 2,
99 .flags = 0, 99 .flags = 0,
100 .ucon = UCON, 100 .ucon = UCON,
101 .ulcon = ULCON, 101 .ulcon = ULCON,
102 .ufcon = UFCON, 102 .ufcon = UFCON,
103 }, 103 },
104 [3] = { 104 [3] = {
105 .hwport = 3, 105 .hwport = 3,
106 .flags = 0, 106 .flags = 0,
107 .ucon = UCON, 107 .ucon = UCON,
108 .ulcon = ULCON, 108 .ulcon = ULCON,
109 .ufcon = UFCON, 109 .ufcon = UFCON,
110 }, 110 },
111 }; 111 };
112 112
113 static struct platform_pwm_backlight_data crag6410_backlight_data = { 113 static struct platform_pwm_backlight_data crag6410_backlight_data = {
114 .pwm_id = 0, 114 .pwm_id = 0,
115 .max_brightness = 1000, 115 .max_brightness = 1000,
116 .dft_brightness = 600, 116 .dft_brightness = 600,
117 .pwm_period_ns = 100000, /* about 1kHz */ 117 .pwm_period_ns = 100000, /* about 1kHz */
118 }; 118 };
119 119
120 static struct platform_device crag6410_backlight_device = { 120 static struct platform_device crag6410_backlight_device = {
121 .name = "pwm-backlight", 121 .name = "pwm-backlight",
122 .id = -1, 122 .id = -1,
123 .dev = { 123 .dev = {
124 .parent = &s3c_device_timer[0].dev, 124 .parent = &s3c_device_timer[0].dev,
125 .platform_data = &crag6410_backlight_data, 125 .platform_data = &crag6410_backlight_data,
126 }, 126 },
127 }; 127 };
128 128
129 static void crag6410_lcd_power_set(struct plat_lcd_data *pd, unsigned int power) 129 static void crag6410_lcd_power_set(struct plat_lcd_data *pd, unsigned int power)
130 { 130 {
131 pr_debug("%s: setting power %d\n", __func__, power); 131 pr_debug("%s: setting power %d\n", __func__, power);
132 132
133 if (power) { 133 if (power) {
134 gpio_set_value(S3C64XX_GPB(0), 1); 134 gpio_set_value(S3C64XX_GPB(0), 1);
135 msleep(1); 135 msleep(1);
136 s3c_gpio_cfgpin(S3C64XX_GPF(14), S3C_GPIO_SFN(2)); 136 s3c_gpio_cfgpin(S3C64XX_GPF(14), S3C_GPIO_SFN(2));
137 } else { 137 } else {
138 gpio_direction_output(S3C64XX_GPF(14), 0); 138 gpio_direction_output(S3C64XX_GPF(14), 0);
139 gpio_set_value(S3C64XX_GPB(0), 0); 139 gpio_set_value(S3C64XX_GPB(0), 0);
140 } 140 }
141 } 141 }
142 142
143 static struct platform_device crag6410_lcd_powerdev = { 143 static struct platform_device crag6410_lcd_powerdev = {
144 .name = "platform-lcd", 144 .name = "platform-lcd",
145 .id = -1, 145 .id = -1,
146 .dev.parent = &s3c_device_fb.dev, 146 .dev.parent = &s3c_device_fb.dev,
147 .dev.platform_data = &(struct plat_lcd_data) { 147 .dev.platform_data = &(struct plat_lcd_data) {
148 .set_power = crag6410_lcd_power_set, 148 .set_power = crag6410_lcd_power_set,
149 }, 149 },
150 }; 150 };
151 151
152 /* 640x480 URT */ 152 /* 640x480 URT */
153 static struct s3c_fb_pd_win crag6410_fb_win0 = { 153 static struct s3c_fb_pd_win crag6410_fb_win0 = {
154 .max_bpp = 32, 154 .max_bpp = 32,
155 .default_bpp = 16, 155 .default_bpp = 16,
156 .xres = 640, 156 .xres = 640,
157 .yres = 480, 157 .yres = 480,
158 .virtual_y = 480 * 2, 158 .virtual_y = 480 * 2,
159 .virtual_x = 640, 159 .virtual_x = 640,
160 }; 160 };
161 161
162 static struct fb_videomode crag6410_lcd_timing = { 162 static struct fb_videomode crag6410_lcd_timing = {
163 .left_margin = 150, 163 .left_margin = 150,
164 .right_margin = 80, 164 .right_margin = 80,
165 .upper_margin = 40, 165 .upper_margin = 40,
166 .lower_margin = 5, 166 .lower_margin = 5,
167 .hsync_len = 40, 167 .hsync_len = 40,
168 .vsync_len = 5, 168 .vsync_len = 5,
169 .xres = 640, 169 .xres = 640,
170 .yres = 480, 170 .yres = 480,
171 }; 171 };
172 172
173 /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */ 173 /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
174 static struct s3c_fb_platdata crag6410_lcd_pdata __devinitdata = { 174 static struct s3c_fb_platdata crag6410_lcd_pdata __devinitdata = {
175 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp, 175 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
176 .vtiming = &crag6410_lcd_timing, 176 .vtiming = &crag6410_lcd_timing,
177 .win[0] = &crag6410_fb_win0, 177 .win[0] = &crag6410_fb_win0,
178 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, 178 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
179 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, 179 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
180 }; 180 };
181 181
182 /* 2x6 keypad */ 182 /* 2x6 keypad */
183 183
184 static uint32_t crag6410_keymap[] __devinitdata = { 184 static uint32_t crag6410_keymap[] __devinitdata = {
185 /* KEY(row, col, keycode) */ 185 /* KEY(row, col, keycode) */
186 KEY(0, 0, KEY_VOLUMEUP), 186 KEY(0, 0, KEY_VOLUMEUP),
187 KEY(0, 1, KEY_HOME), 187 KEY(0, 1, KEY_HOME),
188 KEY(0, 2, KEY_VOLUMEDOWN), 188 KEY(0, 2, KEY_VOLUMEDOWN),
189 KEY(0, 3, KEY_HELP), 189 KEY(0, 3, KEY_HELP),
190 KEY(0, 4, KEY_MENU), 190 KEY(0, 4, KEY_MENU),
191 KEY(0, 5, KEY_MEDIA), 191 KEY(0, 5, KEY_MEDIA),
192 KEY(1, 0, 232), 192 KEY(1, 0, 232),
193 KEY(1, 1, KEY_DOWN), 193 KEY(1, 1, KEY_DOWN),
194 KEY(1, 2, KEY_LEFT), 194 KEY(1, 2, KEY_LEFT),
195 KEY(1, 3, KEY_UP), 195 KEY(1, 3, KEY_UP),
196 KEY(1, 4, KEY_RIGHT), 196 KEY(1, 4, KEY_RIGHT),
197 KEY(1, 5, KEY_CAMERA), 197 KEY(1, 5, KEY_CAMERA),
198 }; 198 };
199 199
200 static struct matrix_keymap_data crag6410_keymap_data __devinitdata = { 200 static struct matrix_keymap_data crag6410_keymap_data __devinitdata = {
201 .keymap = crag6410_keymap, 201 .keymap = crag6410_keymap,
202 .keymap_size = ARRAY_SIZE(crag6410_keymap), 202 .keymap_size = ARRAY_SIZE(crag6410_keymap),
203 }; 203 };
204 204
205 static struct samsung_keypad_platdata crag6410_keypad_data __devinitdata = { 205 static struct samsung_keypad_platdata crag6410_keypad_data __devinitdata = {
206 .keymap_data = &crag6410_keymap_data, 206 .keymap_data = &crag6410_keymap_data,
207 .rows = 2, 207 .rows = 2,
208 .cols = 6, 208 .cols = 6,
209 }; 209 };
210 210
211 static struct gpio_keys_button crag6410_gpio_keys[] = { 211 static struct gpio_keys_button crag6410_gpio_keys[] = {
212 [0] = { 212 [0] = {
213 .code = KEY_SUSPEND, 213 .code = KEY_SUSPEND,
214 .gpio = S3C64XX_GPL(10), /* EINT 18 */ 214 .gpio = S3C64XX_GPL(10), /* EINT 18 */
215 .type = EV_KEY, 215 .type = EV_KEY,
216 .wakeup = 1, 216 .wakeup = 1,
217 .active_low = 1, 217 .active_low = 1,
218 }, 218 },
219 [1] = { 219 [1] = {
220 .code = SW_FRONT_PROXIMITY, 220 .code = SW_FRONT_PROXIMITY,
221 .gpio = S3C64XX_GPN(11), /* EINT 11 */ 221 .gpio = S3C64XX_GPN(11), /* EINT 11 */
222 .type = EV_SW, 222 .type = EV_SW,
223 }, 223 },
224 }; 224 };
225 225
226 static struct gpio_keys_platform_data crag6410_gpio_keydata = { 226 static struct gpio_keys_platform_data crag6410_gpio_keydata = {
227 .buttons = crag6410_gpio_keys, 227 .buttons = crag6410_gpio_keys,
228 .nbuttons = ARRAY_SIZE(crag6410_gpio_keys), 228 .nbuttons = ARRAY_SIZE(crag6410_gpio_keys),
229 }; 229 };
230 230
231 static struct platform_device crag6410_gpio_keydev = { 231 static struct platform_device crag6410_gpio_keydev = {
232 .name = "gpio-keys", 232 .name = "gpio-keys",
233 .id = 0, 233 .id = 0,
234 .dev.platform_data = &crag6410_gpio_keydata, 234 .dev.platform_data = &crag6410_gpio_keydata,
235 }; 235 };
236 236
237 static struct resource crag6410_dm9k_resource[] = { 237 static struct resource crag6410_dm9k_resource[] = {
238 [0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN5, 2), 238 [0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN5, 2),
239 [1] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN5 + (1 << 8), 2), 239 [1] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN5 + (1 << 8), 2),
240 [2] = DEFINE_RES_NAMED(S3C_EINT(17), 1, NULL, IORESOURCE_IRQ \ 240 [2] = DEFINE_RES_NAMED(S3C_EINT(17), 1, NULL, IORESOURCE_IRQ \
241 | IORESOURCE_IRQ_HIGHLEVEL), 241 | IORESOURCE_IRQ_HIGHLEVEL),
242 }; 242 };
243 243
244 static struct dm9000_plat_data mini6410_dm9k_pdata = { 244 static struct dm9000_plat_data mini6410_dm9k_pdata = {
245 .flags = DM9000_PLATF_16BITONLY, 245 .flags = DM9000_PLATF_16BITONLY,
246 }; 246 };
247 247
248 static struct platform_device crag6410_dm9k_device = { 248 static struct platform_device crag6410_dm9k_device = {
249 .name = "dm9000", 249 .name = "dm9000",
250 .id = -1, 250 .id = -1,
251 .num_resources = ARRAY_SIZE(crag6410_dm9k_resource), 251 .num_resources = ARRAY_SIZE(crag6410_dm9k_resource),
252 .resource = crag6410_dm9k_resource, 252 .resource = crag6410_dm9k_resource,
253 .dev.platform_data = &mini6410_dm9k_pdata, 253 .dev.platform_data = &mini6410_dm9k_pdata,
254 }; 254 };
255 255
256 static struct resource crag6410_mmgpio_resource[] = { 256 static struct resource crag6410_mmgpio_resource[] = {
257 [0] = DEFINE_RES_MEM_NAMED(S3C64XX_PA_XM0CSN4, 1, "dat"), 257 [0] = DEFINE_RES_MEM_NAMED(S3C64XX_PA_XM0CSN4, 1, "dat"),
258 }; 258 };
259 259
260 static struct platform_device crag6410_mmgpio = { 260 static struct platform_device crag6410_mmgpio = {
261 .name = "basic-mmio-gpio", 261 .name = "basic-mmio-gpio",
262 .id = -1, 262 .id = -1,
263 .resource = crag6410_mmgpio_resource, 263 .resource = crag6410_mmgpio_resource,
264 .num_resources = ARRAY_SIZE(crag6410_mmgpio_resource), 264 .num_resources = ARRAY_SIZE(crag6410_mmgpio_resource),
265 .dev.platform_data = &(struct bgpio_pdata) { 265 .dev.platform_data = &(struct bgpio_pdata) {
266 .base = MMGPIO_GPIO_BASE, 266 .base = MMGPIO_GPIO_BASE,
267 }, 267 },
268 }; 268 };
269 269
270 static struct platform_device speyside_device = { 270 static struct platform_device speyside_device = {
271 .name = "speyside", 271 .name = "speyside",
272 .id = -1, 272 .id = -1,
273 }; 273 };
274 274
275 static struct platform_device lowland_device = { 275 static struct platform_device lowland_device = {
276 .name = "lowland", 276 .name = "lowland",
277 .id = -1, 277 .id = -1,
278 }; 278 };
279 279
280 static struct platform_device tobermory_device = { 280 static struct platform_device tobermory_device = {
281 .name = "tobermory", 281 .name = "tobermory",
282 .id = -1, 282 .id = -1,
283 }; 283 };
284 284
285 static struct platform_device littlemill_device = { 285 static struct platform_device littlemill_device = {
286 .name = "littlemill", 286 .name = "littlemill",
287 .id = -1, 287 .id = -1,
288 }; 288 };
289 289
290 static struct platform_device bells_wm5102_device = {
291 .name = "bells",
292 .id = 0,
293 };
294
295 static struct platform_device bells_wm5110_device = {
296 .name = "bells",
297 .id = 1,
298 };
299
290 static struct regulator_consumer_supply wallvdd_consumers[] = { 300 static struct regulator_consumer_supply wallvdd_consumers[] = {
291 REGULATOR_SUPPLY("SPKVDD", "1-001a"), 301 REGULATOR_SUPPLY("SPKVDD", "1-001a"),
292 REGULATOR_SUPPLY("SPKVDD1", "1-001a"), 302 REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
293 REGULATOR_SUPPLY("SPKVDD2", "1-001a"), 303 REGULATOR_SUPPLY("SPKVDD2", "1-001a"),
294 REGULATOR_SUPPLY("SPKVDDL", "1-001a"), 304 REGULATOR_SUPPLY("SPKVDDL", "1-001a"),
295 REGULATOR_SUPPLY("SPKVDDR", "1-001a"), 305 REGULATOR_SUPPLY("SPKVDDR", "1-001a"),
296 306
297 REGULATOR_SUPPLY("DC1VDD", "0-0034"), 307 REGULATOR_SUPPLY("DC1VDD", "0-0034"),
298 REGULATOR_SUPPLY("DC2VDD", "0-0034"), 308 REGULATOR_SUPPLY("DC2VDD", "0-0034"),
299 REGULATOR_SUPPLY("DC3VDD", "0-0034"), 309 REGULATOR_SUPPLY("DC3VDD", "0-0034"),
300 REGULATOR_SUPPLY("LDO1VDD", "0-0034"), 310 REGULATOR_SUPPLY("LDO1VDD", "0-0034"),
301 REGULATOR_SUPPLY("LDO2VDD", "0-0034"), 311 REGULATOR_SUPPLY("LDO2VDD", "0-0034"),
302 REGULATOR_SUPPLY("LDO4VDD", "0-0034"), 312 REGULATOR_SUPPLY("LDO4VDD", "0-0034"),
303 REGULATOR_SUPPLY("LDO5VDD", "0-0034"), 313 REGULATOR_SUPPLY("LDO5VDD", "0-0034"),
304 REGULATOR_SUPPLY("LDO6VDD", "0-0034"), 314 REGULATOR_SUPPLY("LDO6VDD", "0-0034"),
305 REGULATOR_SUPPLY("LDO7VDD", "0-0034"), 315 REGULATOR_SUPPLY("LDO7VDD", "0-0034"),
306 REGULATOR_SUPPLY("LDO8VDD", "0-0034"), 316 REGULATOR_SUPPLY("LDO8VDD", "0-0034"),
307 REGULATOR_SUPPLY("LDO9VDD", "0-0034"), 317 REGULATOR_SUPPLY("LDO9VDD", "0-0034"),
308 REGULATOR_SUPPLY("LDO10VDD", "0-0034"), 318 REGULATOR_SUPPLY("LDO10VDD", "0-0034"),
309 REGULATOR_SUPPLY("LDO11VDD", "0-0034"), 319 REGULATOR_SUPPLY("LDO11VDD", "0-0034"),
310 320
311 REGULATOR_SUPPLY("DC1VDD", "1-0034"), 321 REGULATOR_SUPPLY("DC1VDD", "1-0034"),
312 REGULATOR_SUPPLY("DC2VDD", "1-0034"), 322 REGULATOR_SUPPLY("DC2VDD", "1-0034"),
313 REGULATOR_SUPPLY("DC3VDD", "1-0034"), 323 REGULATOR_SUPPLY("DC3VDD", "1-0034"),
314 }; 324 };
315 325
316 static struct regulator_init_data wallvdd_data = { 326 static struct regulator_init_data wallvdd_data = {
317 .constraints = { 327 .constraints = {
318 .always_on = 1, 328 .always_on = 1,
319 }, 329 },
320 .num_consumer_supplies = ARRAY_SIZE(wallvdd_consumers), 330 .num_consumer_supplies = ARRAY_SIZE(wallvdd_consumers),
321 .consumer_supplies = wallvdd_consumers, 331 .consumer_supplies = wallvdd_consumers,
322 }; 332 };
323 333
324 static struct fixed_voltage_config wallvdd_pdata = { 334 static struct fixed_voltage_config wallvdd_pdata = {
325 .supply_name = "WALLVDD", 335 .supply_name = "WALLVDD",
326 .microvolts = 5000000, 336 .microvolts = 5000000,
327 .init_data = &wallvdd_data, 337 .init_data = &wallvdd_data,
328 .gpio = -EINVAL, 338 .gpio = -EINVAL,
329 }; 339 };
330 340
331 static struct platform_device wallvdd_device = { 341 static struct platform_device wallvdd_device = {
332 .name = "reg-fixed-voltage", 342 .name = "reg-fixed-voltage",
333 .id = -1, 343 .id = -1,
334 .dev = { 344 .dev = {
335 .platform_data = &wallvdd_pdata, 345 .platform_data = &wallvdd_pdata,
336 }, 346 },
337 }; 347 };
338 348
339 static struct platform_device *crag6410_devices[] __initdata = { 349 static struct platform_device *crag6410_devices[] __initdata = {
340 &s3c_device_hsmmc0, 350 &s3c_device_hsmmc0,
341 &s3c_device_hsmmc2, 351 &s3c_device_hsmmc2,
342 &s3c_device_i2c0, 352 &s3c_device_i2c0,
343 &s3c_device_i2c1, 353 &s3c_device_i2c1,
344 &s3c_device_fb, 354 &s3c_device_fb,
345 &s3c_device_ohci, 355 &s3c_device_ohci,
346 &s3c_device_usb_hsotg, 356 &s3c_device_usb_hsotg,
347 &s3c_device_timer[0], 357 &s3c_device_timer[0],
348 &s3c64xx_device_iis0, 358 &s3c64xx_device_iis0,
349 &s3c64xx_device_iis1, 359 &s3c64xx_device_iis1,
350 &samsung_asoc_dma, 360 &samsung_asoc_dma,
351 &samsung_device_keypad, 361 &samsung_device_keypad,
352 &crag6410_gpio_keydev, 362 &crag6410_gpio_keydev,
353 &crag6410_dm9k_device, 363 &crag6410_dm9k_device,
354 &s3c64xx_device_spi0, 364 &s3c64xx_device_spi0,
355 &crag6410_mmgpio, 365 &crag6410_mmgpio,
356 &crag6410_lcd_powerdev, 366 &crag6410_lcd_powerdev,
357 &crag6410_backlight_device, 367 &crag6410_backlight_device,
358 &speyside_device, 368 &speyside_device,
359 &tobermory_device, 369 &tobermory_device,
360 &littlemill_device, 370 &littlemill_device,
361 &lowland_device, 371 &lowland_device,
372 &bells_wm5102_device,
373 &bells_wm5110_device,
362 &wallvdd_device, 374 &wallvdd_device,
363 }; 375 };
364 376
365 static struct pca953x_platform_data crag6410_pca_data = { 377 static struct pca953x_platform_data crag6410_pca_data = {
366 .gpio_base = PCA935X_GPIO_BASE, 378 .gpio_base = PCA935X_GPIO_BASE,
367 .irq_base = -1, 379 .irq_base = -1,
368 }; 380 };
369 381
370 /* VDDARM is controlled by DVS1 connected to GPK(0) */ 382 /* VDDARM is controlled by DVS1 connected to GPK(0) */
371 static struct wm831x_buckv_pdata vddarm_pdata = { 383 static struct wm831x_buckv_pdata vddarm_pdata = {
372 .dvs_control_src = 1, 384 .dvs_control_src = 1,
373 .dvs_gpio = S3C64XX_GPK(0), 385 .dvs_gpio = S3C64XX_GPK(0),
374 }; 386 };
375 387
376 static struct regulator_consumer_supply vddarm_consumers[] __devinitdata = { 388 static struct regulator_consumer_supply vddarm_consumers[] __devinitdata = {
377 REGULATOR_SUPPLY("vddarm", NULL), 389 REGULATOR_SUPPLY("vddarm", NULL),
378 }; 390 };
379 391
380 static struct regulator_init_data vddarm __devinitdata = { 392 static struct regulator_init_data vddarm __devinitdata = {
381 .constraints = { 393 .constraints = {
382 .name = "VDDARM", 394 .name = "VDDARM",
383 .min_uV = 1000000, 395 .min_uV = 1000000,
384 .max_uV = 1300000, 396 .max_uV = 1300000,
385 .always_on = 1, 397 .always_on = 1,
386 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, 398 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
387 }, 399 },
388 .num_consumer_supplies = ARRAY_SIZE(vddarm_consumers), 400 .num_consumer_supplies = ARRAY_SIZE(vddarm_consumers),
389 .consumer_supplies = vddarm_consumers, 401 .consumer_supplies = vddarm_consumers,
390 .supply_regulator = "WALLVDD", 402 .supply_regulator = "WALLVDD",
391 .driver_data = &vddarm_pdata, 403 .driver_data = &vddarm_pdata,
392 }; 404 };
393 405
394 static struct regulator_consumer_supply vddint_consumers[] __devinitdata = { 406 static struct regulator_consumer_supply vddint_consumers[] __devinitdata = {
395 REGULATOR_SUPPLY("vddint", NULL), 407 REGULATOR_SUPPLY("vddint", NULL),
396 }; 408 };
397 409
398 static struct regulator_init_data vddint __devinitdata = { 410 static struct regulator_init_data vddint __devinitdata = {
399 .constraints = { 411 .constraints = {
400 .name = "VDDINT", 412 .name = "VDDINT",
401 .min_uV = 1000000, 413 .min_uV = 1000000,
402 .max_uV = 1200000, 414 .max_uV = 1200000,
403 .always_on = 1, 415 .always_on = 1,
404 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, 416 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
405 }, 417 },
406 .num_consumer_supplies = ARRAY_SIZE(vddint_consumers), 418 .num_consumer_supplies = ARRAY_SIZE(vddint_consumers),
407 .consumer_supplies = vddint_consumers, 419 .consumer_supplies = vddint_consumers,
408 .supply_regulator = "WALLVDD", 420 .supply_regulator = "WALLVDD",
409 }; 421 };
410 422
411 static struct regulator_init_data vddmem __devinitdata = { 423 static struct regulator_init_data vddmem __devinitdata = {
412 .constraints = { 424 .constraints = {
413 .name = "VDDMEM", 425 .name = "VDDMEM",
414 .always_on = 1, 426 .always_on = 1,
415 }, 427 },
416 }; 428 };
417 429
418 static struct regulator_init_data vddsys __devinitdata = { 430 static struct regulator_init_data vddsys __devinitdata = {
419 .constraints = { 431 .constraints = {
420 .name = "VDDSYS,VDDEXT,VDDPCM,VDDSS", 432 .name = "VDDSYS,VDDEXT,VDDPCM,VDDSS",
421 .always_on = 1, 433 .always_on = 1,
422 }, 434 },
423 }; 435 };
424 436
425 static struct regulator_consumer_supply vddmmc_consumers[] __devinitdata = { 437 static struct regulator_consumer_supply vddmmc_consumers[] __devinitdata = {
426 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"), 438 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
427 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.1"), 439 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.1"),
428 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"), 440 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"),
429 }; 441 };
430 442
431 static struct regulator_init_data vddmmc __devinitdata = { 443 static struct regulator_init_data vddmmc __devinitdata = {
432 .constraints = { 444 .constraints = {
433 .name = "VDDMMC,UH", 445 .name = "VDDMMC,UH",
434 .always_on = 1, 446 .always_on = 1,
435 }, 447 },
436 .num_consumer_supplies = ARRAY_SIZE(vddmmc_consumers), 448 .num_consumer_supplies = ARRAY_SIZE(vddmmc_consumers),
437 .consumer_supplies = vddmmc_consumers, 449 .consumer_supplies = vddmmc_consumers,
438 .supply_regulator = "WALLVDD", 450 .supply_regulator = "WALLVDD",
439 }; 451 };
440 452
441 static struct regulator_init_data vddotgi __devinitdata = { 453 static struct regulator_init_data vddotgi __devinitdata = {
442 .constraints = { 454 .constraints = {
443 .name = "VDDOTGi", 455 .name = "VDDOTGi",
444 .always_on = 1, 456 .always_on = 1,
445 }, 457 },
446 .supply_regulator = "WALLVDD", 458 .supply_regulator = "WALLVDD",
447 }; 459 };
448 460
449 static struct regulator_init_data vddotg __devinitdata = { 461 static struct regulator_init_data vddotg __devinitdata = {
450 .constraints = { 462 .constraints = {
451 .name = "VDDOTG", 463 .name = "VDDOTG",
452 .always_on = 1, 464 .always_on = 1,
453 }, 465 },
454 .supply_regulator = "WALLVDD", 466 .supply_regulator = "WALLVDD",
455 }; 467 };
456 468
457 static struct regulator_init_data vddhi __devinitdata = { 469 static struct regulator_init_data vddhi __devinitdata = {
458 .constraints = { 470 .constraints = {
459 .name = "VDDHI", 471 .name = "VDDHI",
460 .always_on = 1, 472 .always_on = 1,
461 }, 473 },
462 .supply_regulator = "WALLVDD", 474 .supply_regulator = "WALLVDD",
463 }; 475 };
464 476
465 static struct regulator_init_data vddadc __devinitdata = { 477 static struct regulator_init_data vddadc __devinitdata = {
466 .constraints = { 478 .constraints = {
467 .name = "VDDADC,VDDDAC", 479 .name = "VDDADC,VDDDAC",
468 .always_on = 1, 480 .always_on = 1,
469 }, 481 },
470 .supply_regulator = "WALLVDD", 482 .supply_regulator = "WALLVDD",
471 }; 483 };
472 484
473 static struct regulator_init_data vddmem0 __devinitdata = { 485 static struct regulator_init_data vddmem0 __devinitdata = {
474 .constraints = { 486 .constraints = {
475 .name = "VDDMEM0", 487 .name = "VDDMEM0",
476 .always_on = 1, 488 .always_on = 1,
477 }, 489 },
478 .supply_regulator = "WALLVDD", 490 .supply_regulator = "WALLVDD",
479 }; 491 };
480 492
481 static struct regulator_init_data vddpll __devinitdata = { 493 static struct regulator_init_data vddpll __devinitdata = {
482 .constraints = { 494 .constraints = {
483 .name = "VDDPLL", 495 .name = "VDDPLL",
484 .always_on = 1, 496 .always_on = 1,
485 }, 497 },
486 .supply_regulator = "WALLVDD", 498 .supply_regulator = "WALLVDD",
487 }; 499 };
488 500
489 static struct regulator_init_data vddlcd __devinitdata = { 501 static struct regulator_init_data vddlcd __devinitdata = {
490 .constraints = { 502 .constraints = {
491 .name = "VDDLCD", 503 .name = "VDDLCD",
492 .always_on = 1, 504 .always_on = 1,
493 }, 505 },
494 .supply_regulator = "WALLVDD", 506 .supply_regulator = "WALLVDD",
495 }; 507 };
496 508
497 static struct regulator_init_data vddalive __devinitdata = { 509 static struct regulator_init_data vddalive __devinitdata = {
498 .constraints = { 510 .constraints = {
499 .name = "VDDALIVE", 511 .name = "VDDALIVE",
500 .always_on = 1, 512 .always_on = 1,
501 }, 513 },
502 .supply_regulator = "WALLVDD", 514 .supply_regulator = "WALLVDD",
503 }; 515 };
504 516
505 static struct wm831x_backup_pdata banff_backup_pdata __devinitdata = { 517 static struct wm831x_backup_pdata banff_backup_pdata __devinitdata = {
506 .charger_enable = 1, 518 .charger_enable = 1,
507 .vlim = 2500, /* mV */ 519 .vlim = 2500, /* mV */
508 .ilim = 200, /* uA */ 520 .ilim = 200, /* uA */
509 }; 521 };
510 522
511 static struct wm831x_status_pdata banff_red_led __devinitdata = { 523 static struct wm831x_status_pdata banff_red_led __devinitdata = {
512 .name = "banff:red:", 524 .name = "banff:red:",
513 .default_src = WM831X_STATUS_MANUAL, 525 .default_src = WM831X_STATUS_MANUAL,
514 }; 526 };
515 527
516 static struct wm831x_status_pdata banff_green_led __devinitdata = { 528 static struct wm831x_status_pdata banff_green_led __devinitdata = {
517 .name = "banff:green:", 529 .name = "banff:green:",
518 .default_src = WM831X_STATUS_MANUAL, 530 .default_src = WM831X_STATUS_MANUAL,
519 }; 531 };
520 532
521 static struct wm831x_touch_pdata touch_pdata __devinitdata = { 533 static struct wm831x_touch_pdata touch_pdata __devinitdata = {
522 .data_irq = S3C_EINT(26), 534 .data_irq = S3C_EINT(26),
523 .pd_irq = S3C_EINT(27), 535 .pd_irq = S3C_EINT(27),
524 }; 536 };
525 537
526 static struct wm831x_pdata crag_pmic_pdata __devinitdata = { 538 static struct wm831x_pdata crag_pmic_pdata __devinitdata = {
527 .wm831x_num = 1, 539 .wm831x_num = 1,
528 .gpio_base = BANFF_PMIC_GPIO_BASE, 540 .gpio_base = BANFF_PMIC_GPIO_BASE,
529 .soft_shutdown = true, 541 .soft_shutdown = true,
530 542
531 .backup = &banff_backup_pdata, 543 .backup = &banff_backup_pdata,
532 544
533 .gpio_defaults = { 545 .gpio_defaults = {
534 /* GPIO5: DVS1_REQ - CMOS, DBVDD, active high */ 546 /* GPIO5: DVS1_REQ - CMOS, DBVDD, active high */
535 [4] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA | 0x8, 547 [4] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA | 0x8,
536 /* GPIO11: Touchscreen data - CMOS, DBVDD, active high*/ 548 /* GPIO11: Touchscreen data - CMOS, DBVDD, active high*/
537 [10] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x6, 549 [10] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x6,
538 /* GPIO12: Touchscreen pen down - CMOS, DBVDD, active high*/ 550 /* GPIO12: Touchscreen pen down - CMOS, DBVDD, active high*/
539 [11] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x7, 551 [11] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x7,
540 }, 552 },
541 553
542 .dcdc = { 554 .dcdc = {
543 &vddarm, /* DCDC1 */ 555 &vddarm, /* DCDC1 */
544 &vddint, /* DCDC2 */ 556 &vddint, /* DCDC2 */
545 &vddmem, /* DCDC3 */ 557 &vddmem, /* DCDC3 */
546 }, 558 },
547 559
548 .ldo = { 560 .ldo = {
549 &vddsys, /* LDO1 */ 561 &vddsys, /* LDO1 */
550 &vddmmc, /* LDO2 */ 562 &vddmmc, /* LDO2 */
551 NULL, /* LDO3 */ 563 NULL, /* LDO3 */
552 &vddotgi, /* LDO4 */ 564 &vddotgi, /* LDO4 */
553 &vddotg, /* LDO5 */ 565 &vddotg, /* LDO5 */
554 &vddhi, /* LDO6 */ 566 &vddhi, /* LDO6 */
555 &vddadc, /* LDO7 */ 567 &vddadc, /* LDO7 */
556 &vddmem0, /* LDO8 */ 568 &vddmem0, /* LDO8 */
557 &vddpll, /* LDO9 */ 569 &vddpll, /* LDO9 */
558 &vddlcd, /* LDO10 */ 570 &vddlcd, /* LDO10 */
559 &vddalive, /* LDO11 */ 571 &vddalive, /* LDO11 */
560 }, 572 },
561 573
562 .status = { 574 .status = {
563 &banff_green_led, 575 &banff_green_led,
564 &banff_red_led, 576 &banff_red_led,
565 }, 577 },
566 578
567 .touch = &touch_pdata, 579 .touch = &touch_pdata,
568 }; 580 };
569 581
570 static struct i2c_board_info i2c_devs0[] __devinitdata = { 582 static struct i2c_board_info i2c_devs0[] __devinitdata = {
571 { I2C_BOARD_INFO("24c08", 0x50), }, 583 { I2C_BOARD_INFO("24c08", 0x50), },
572 { I2C_BOARD_INFO("tca6408", 0x20), 584 { I2C_BOARD_INFO("tca6408", 0x20),
573 .platform_data = &crag6410_pca_data, 585 .platform_data = &crag6410_pca_data,
574 }, 586 },
575 { I2C_BOARD_INFO("wm8312", 0x34), 587 { I2C_BOARD_INFO("wm8312", 0x34),
576 .platform_data = &crag_pmic_pdata, 588 .platform_data = &crag_pmic_pdata,
577 .irq = S3C_EINT(23), 589 .irq = S3C_EINT(23),
578 }, 590 },
579 }; 591 };
580 592
581 static struct s3c2410_platform_i2c i2c0_pdata = { 593 static struct s3c2410_platform_i2c i2c0_pdata = {
582 .frequency = 400000, 594 .frequency = 400000,
583 }; 595 };
584 596
585 static struct regulator_consumer_supply pvdd_1v2_consumers[] __devinitdata = { 597 static struct regulator_consumer_supply pvdd_1v2_consumers[] __devinitdata = {
586 REGULATOR_SUPPLY("DCVDD", "spi0.0"), 598 REGULATOR_SUPPLY("DCVDD", "spi0.0"),
587 REGULATOR_SUPPLY("AVDD", "spi0.0"), 599 REGULATOR_SUPPLY("AVDD", "spi0.0"),
588 }; 600 };
589 601
590 static struct regulator_init_data pvdd_1v2 __devinitdata = { 602 static struct regulator_init_data pvdd_1v2 __devinitdata = {
591 .constraints = { 603 .constraints = {
592 .name = "PVDD_1V2", 604 .name = "PVDD_1V2",
593 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 605 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
594 }, 606 },
595 607
596 .consumer_supplies = pvdd_1v2_consumers, 608 .consumer_supplies = pvdd_1v2_consumers,
597 .num_consumer_supplies = ARRAY_SIZE(pvdd_1v2_consumers), 609 .num_consumer_supplies = ARRAY_SIZE(pvdd_1v2_consumers),
598 }; 610 };
599 611
600 static struct regulator_consumer_supply pvdd_1v8_consumers[] __devinitdata = { 612 static struct regulator_consumer_supply pvdd_1v8_consumers[] __devinitdata = {
601 REGULATOR_SUPPLY("LDOVDD", "1-001a"), 613 REGULATOR_SUPPLY("LDOVDD", "1-001a"),
602 REGULATOR_SUPPLY("PLLVDD", "1-001a"), 614 REGULATOR_SUPPLY("PLLVDD", "1-001a"),
603 REGULATOR_SUPPLY("DBVDD", "1-001a"), 615 REGULATOR_SUPPLY("DBVDD", "1-001a"),
604 REGULATOR_SUPPLY("DBVDD1", "1-001a"), 616 REGULATOR_SUPPLY("DBVDD1", "1-001a"),
605 REGULATOR_SUPPLY("DBVDD2", "1-001a"), 617 REGULATOR_SUPPLY("DBVDD2", "1-001a"),
606 REGULATOR_SUPPLY("DBVDD3", "1-001a"), 618 REGULATOR_SUPPLY("DBVDD3", "1-001a"),
607 REGULATOR_SUPPLY("CPVDD", "1-001a"), 619 REGULATOR_SUPPLY("CPVDD", "1-001a"),
608 REGULATOR_SUPPLY("AVDD2", "1-001a"), 620 REGULATOR_SUPPLY("AVDD2", "1-001a"),
609 REGULATOR_SUPPLY("DCVDD", "1-001a"), 621 REGULATOR_SUPPLY("DCVDD", "1-001a"),
610 REGULATOR_SUPPLY("AVDD", "1-001a"), 622 REGULATOR_SUPPLY("AVDD", "1-001a"),
611 REGULATOR_SUPPLY("DBVDD", "spi0.0"), 623 REGULATOR_SUPPLY("DBVDD", "spi0.0"),
612 }; 624 };
613 625
614 static struct regulator_init_data pvdd_1v8 __devinitdata = { 626 static struct regulator_init_data pvdd_1v8 __devinitdata = {
615 .constraints = { 627 .constraints = {
616 .name = "PVDD_1V8", 628 .name = "PVDD_1V8",
617 .always_on = 1, 629 .always_on = 1,
618 }, 630 },
619 631
620 .consumer_supplies = pvdd_1v8_consumers, 632 .consumer_supplies = pvdd_1v8_consumers,
621 .num_consumer_supplies = ARRAY_SIZE(pvdd_1v8_consumers), 633 .num_consumer_supplies = ARRAY_SIZE(pvdd_1v8_consumers),
622 }; 634 };
623 635
624 static struct regulator_consumer_supply pvdd_3v3_consumers[] __devinitdata = { 636 static struct regulator_consumer_supply pvdd_3v3_consumers[] __devinitdata = {
625 REGULATOR_SUPPLY("MICVDD", "1-001a"), 637 REGULATOR_SUPPLY("MICVDD", "1-001a"),
626 REGULATOR_SUPPLY("AVDD1", "1-001a"), 638 REGULATOR_SUPPLY("AVDD1", "1-001a"),
627 }; 639 };
628 640
629 static struct regulator_init_data pvdd_3v3 __devinitdata = { 641 static struct regulator_init_data pvdd_3v3 __devinitdata = {
630 .constraints = { 642 .constraints = {
631 .name = "PVDD_3V3", 643 .name = "PVDD_3V3",
632 .always_on = 1, 644 .always_on = 1,
633 }, 645 },
634 646
635 .consumer_supplies = pvdd_3v3_consumers, 647 .consumer_supplies = pvdd_3v3_consumers,
636 .num_consumer_supplies = ARRAY_SIZE(pvdd_3v3_consumers), 648 .num_consumer_supplies = ARRAY_SIZE(pvdd_3v3_consumers),
637 }; 649 };
638 650
639 static struct wm831x_pdata glenfarclas_pmic_pdata __devinitdata = { 651 static struct wm831x_pdata glenfarclas_pmic_pdata __devinitdata = {
640 .wm831x_num = 2, 652 .wm831x_num = 2,
641 .irq_base = GLENFARCLAS_PMIC_IRQ_BASE, 653 .irq_base = GLENFARCLAS_PMIC_IRQ_BASE,
642 .gpio_base = GLENFARCLAS_PMIC_GPIO_BASE, 654 .gpio_base = GLENFARCLAS_PMIC_GPIO_BASE,
643 .soft_shutdown = true, 655 .soft_shutdown = true,
644 656
645 .gpio_defaults = { 657 .gpio_defaults = {
646 /* GPIO1-3: IRQ inputs, rising edge triggered, CMOS */ 658 /* GPIO1-3: IRQ inputs, rising edge triggered, CMOS */
647 [0] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA, 659 [0] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA,
648 [1] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA, 660 [1] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA,
649 [2] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA, 661 [2] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA,
650 }, 662 },
651 663
652 .dcdc = { 664 .dcdc = {
653 &pvdd_1v2, /* DCDC1 */ 665 &pvdd_1v2, /* DCDC1 */
654 &pvdd_1v8, /* DCDC2 */ 666 &pvdd_1v8, /* DCDC2 */
655 &pvdd_3v3, /* DCDC3 */ 667 &pvdd_3v3, /* DCDC3 */
656 }, 668 },
657 669
658 .disable_touch = true, 670 .disable_touch = true,
659 }; 671 };
660 672
661 static struct wm1250_ev1_pdata wm1250_ev1_pdata = { 673 static struct wm1250_ev1_pdata wm1250_ev1_pdata = {
662 .gpios = { 674 .gpios = {
663 [WM1250_EV1_GPIO_CLK_ENA] = S3C64XX_GPN(12), 675 [WM1250_EV1_GPIO_CLK_ENA] = S3C64XX_GPN(12),
664 [WM1250_EV1_GPIO_CLK_SEL0] = S3C64XX_GPL(12), 676 [WM1250_EV1_GPIO_CLK_SEL0] = S3C64XX_GPL(12),
665 [WM1250_EV1_GPIO_CLK_SEL1] = S3C64XX_GPL(13), 677 [WM1250_EV1_GPIO_CLK_SEL1] = S3C64XX_GPL(13),
666 [WM1250_EV1_GPIO_OSR] = S3C64XX_GPL(14), 678 [WM1250_EV1_GPIO_OSR] = S3C64XX_GPL(14),
667 [WM1250_EV1_GPIO_MASTER] = S3C64XX_GPL(8), 679 [WM1250_EV1_GPIO_MASTER] = S3C64XX_GPL(8),
668 }, 680 },
669 }; 681 };
670 682
671 static struct i2c_board_info i2c_devs1[] __devinitdata = { 683 static struct i2c_board_info i2c_devs1[] __devinitdata = {
672 { I2C_BOARD_INFO("wm8311", 0x34), 684 { I2C_BOARD_INFO("wm8311", 0x34),
673 .irq = S3C_EINT(0), 685 .irq = S3C_EINT(0),
674 .platform_data = &glenfarclas_pmic_pdata }, 686 .platform_data = &glenfarclas_pmic_pdata },
675 687
676 { I2C_BOARD_INFO("wlf-gf-module", 0x22) }, 688 { I2C_BOARD_INFO("wlf-gf-module", 0x22) },
677 { I2C_BOARD_INFO("wlf-gf-module", 0x24) }, 689 { I2C_BOARD_INFO("wlf-gf-module", 0x24) },
678 { I2C_BOARD_INFO("wlf-gf-module", 0x25) }, 690 { I2C_BOARD_INFO("wlf-gf-module", 0x25) },
679 { I2C_BOARD_INFO("wlf-gf-module", 0x26) }, 691 { I2C_BOARD_INFO("wlf-gf-module", 0x26) },
680 692
681 { I2C_BOARD_INFO("wm1250-ev1", 0x27), 693 { I2C_BOARD_INFO("wm1250-ev1", 0x27),
682 .platform_data = &wm1250_ev1_pdata }, 694 .platform_data = &wm1250_ev1_pdata },
683 }; 695 };
684 696
685 static struct s3c2410_platform_i2c i2c1_pdata = { 697 static struct s3c2410_platform_i2c i2c1_pdata = {
686 .frequency = 400000, 698 .frequency = 400000,
687 .bus_num = 1, 699 .bus_num = 1,
688 }; 700 };
689 701
690 static void __init crag6410_map_io(void) 702 static void __init crag6410_map_io(void)
691 { 703 {
692 s3c64xx_init_io(NULL, 0); 704 s3c64xx_init_io(NULL, 0);
693 s3c24xx_init_clocks(12000000); 705 s3c24xx_init_clocks(12000000);
694 s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs)); 706 s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs));
695 707
696 /* LCD type and Bypass set by bootloader */ 708 /* LCD type and Bypass set by bootloader */
697 } 709 }
698 710
699 static struct s3c_sdhci_platdata crag6410_hsmmc2_pdata = { 711 static struct s3c_sdhci_platdata crag6410_hsmmc2_pdata = {
700 .max_width = 4, 712 .max_width = 4,
701 .cd_type = S3C_SDHCI_CD_PERMANENT, 713 .cd_type = S3C_SDHCI_CD_PERMANENT,
702 .host_caps = MMC_CAP_POWER_OFF_CARD, 714 .host_caps = MMC_CAP_POWER_OFF_CARD,
703 }; 715 };
704 716
705 static void crag6410_cfg_sdhci0(struct platform_device *dev, int width) 717 static void crag6410_cfg_sdhci0(struct platform_device *dev, int width)
706 { 718 {
707 /* Set all the necessary GPG pins to special-function 2 */ 719 /* Set all the necessary GPG pins to special-function 2 */
708 s3c_gpio_cfgrange_nopull(S3C64XX_GPG(0), 2 + width, S3C_GPIO_SFN(2)); 720 s3c_gpio_cfgrange_nopull(S3C64XX_GPG(0), 2 + width, S3C_GPIO_SFN(2));
709 721
710 /* force card-detected for prototype 0 */ 722 /* force card-detected for prototype 0 */
711 s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_DOWN); 723 s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_DOWN);
712 } 724 }
713 725
714 static struct s3c_sdhci_platdata crag6410_hsmmc0_pdata = { 726 static struct s3c_sdhci_platdata crag6410_hsmmc0_pdata = {
715 .max_width = 4, 727 .max_width = 4,
716 .cd_type = S3C_SDHCI_CD_INTERNAL, 728 .cd_type = S3C_SDHCI_CD_INTERNAL,
717 .cfg_gpio = crag6410_cfg_sdhci0, 729 .cfg_gpio = crag6410_cfg_sdhci0,
718 .host_caps = MMC_CAP_POWER_OFF_CARD, 730 .host_caps = MMC_CAP_POWER_OFF_CARD,
719 }; 731 };
720 732
721 static const struct gpio_led gpio_leds[] = { 733 static const struct gpio_led gpio_leds[] = {
722 { 734 {
723 .name = "d13:green:", 735 .name = "d13:green:",
724 .gpio = MMGPIO_GPIO_BASE + 0, 736 .gpio = MMGPIO_GPIO_BASE + 0,
725 .default_state = LEDS_GPIO_DEFSTATE_ON, 737 .default_state = LEDS_GPIO_DEFSTATE_ON,
726 }, 738 },
727 { 739 {
728 .name = "d14:green:", 740 .name = "d14:green:",
729 .gpio = MMGPIO_GPIO_BASE + 1, 741 .gpio = MMGPIO_GPIO_BASE + 1,
730 .default_state = LEDS_GPIO_DEFSTATE_ON, 742 .default_state = LEDS_GPIO_DEFSTATE_ON,
731 }, 743 },
732 { 744 {
733 .name = "d15:green:", 745 .name = "d15:green:",
734 .gpio = MMGPIO_GPIO_BASE + 2, 746 .gpio = MMGPIO_GPIO_BASE + 2,
735 .default_state = LEDS_GPIO_DEFSTATE_ON, 747 .default_state = LEDS_GPIO_DEFSTATE_ON,
736 }, 748 },
737 { 749 {
738 .name = "d16:green:", 750 .name = "d16:green:",
739 .gpio = MMGPIO_GPIO_BASE + 3, 751 .gpio = MMGPIO_GPIO_BASE + 3,
740 .default_state = LEDS_GPIO_DEFSTATE_ON, 752 .default_state = LEDS_GPIO_DEFSTATE_ON,
741 }, 753 },
742 { 754 {
743 .name = "d17:green:", 755 .name = "d17:green:",
744 .gpio = MMGPIO_GPIO_BASE + 4, 756 .gpio = MMGPIO_GPIO_BASE + 4,
745 .default_state = LEDS_GPIO_DEFSTATE_ON, 757 .default_state = LEDS_GPIO_DEFSTATE_ON,
746 }, 758 },
747 { 759 {
748 .name = "d18:green:", 760 .name = "d18:green:",
749 .gpio = MMGPIO_GPIO_BASE + 5, 761 .gpio = MMGPIO_GPIO_BASE + 5,
750 .default_state = LEDS_GPIO_DEFSTATE_ON, 762 .default_state = LEDS_GPIO_DEFSTATE_ON,
751 }, 763 },
752 { 764 {
753 .name = "d19:green:", 765 .name = "d19:green:",
754 .gpio = MMGPIO_GPIO_BASE + 6, 766 .gpio = MMGPIO_GPIO_BASE + 6,
755 .default_state = LEDS_GPIO_DEFSTATE_ON, 767 .default_state = LEDS_GPIO_DEFSTATE_ON,
756 }, 768 },
757 { 769 {
758 .name = "d20:green:", 770 .name = "d20:green:",
759 .gpio = MMGPIO_GPIO_BASE + 7, 771 .gpio = MMGPIO_GPIO_BASE + 7,
760 .default_state = LEDS_GPIO_DEFSTATE_ON, 772 .default_state = LEDS_GPIO_DEFSTATE_ON,
761 }, 773 },
762 }; 774 };
763 775
764 static const struct gpio_led_platform_data gpio_leds_pdata = { 776 static const struct gpio_led_platform_data gpio_leds_pdata = {
765 .leds = gpio_leds, 777 .leds = gpio_leds,
766 .num_leds = ARRAY_SIZE(gpio_leds), 778 .num_leds = ARRAY_SIZE(gpio_leds),
767 }; 779 };
768 780
769 static struct s3c_hsotg_plat crag6410_hsotg_pdata; 781 static struct s3c_hsotg_plat crag6410_hsotg_pdata;
770 782
771 static void __init crag6410_machine_init(void) 783 static void __init crag6410_machine_init(void)
772 { 784 {
773 /* Open drain IRQs need pullups */ 785 /* Open drain IRQs need pullups */
774 s3c_gpio_setpull(S3C64XX_GPM(0), S3C_GPIO_PULL_UP); 786 s3c_gpio_setpull(S3C64XX_GPM(0), S3C_GPIO_PULL_UP);
775 s3c_gpio_setpull(S3C64XX_GPN(0), S3C_GPIO_PULL_UP); 787 s3c_gpio_setpull(S3C64XX_GPN(0), S3C_GPIO_PULL_UP);
776 788
777 gpio_request(S3C64XX_GPB(0), "LCD power"); 789 gpio_request(S3C64XX_GPB(0), "LCD power");
778 gpio_direction_output(S3C64XX_GPB(0), 0); 790 gpio_direction_output(S3C64XX_GPB(0), 0);
779 791
780 gpio_request(S3C64XX_GPF(14), "LCD PWM"); 792 gpio_request(S3C64XX_GPF(14), "LCD PWM");
781 gpio_direction_output(S3C64XX_GPF(14), 0); /* turn off */ 793 gpio_direction_output(S3C64XX_GPF(14), 0); /* turn off */
782 794
783 gpio_request(S3C64XX_GPB(1), "SD power"); 795 gpio_request(S3C64XX_GPB(1), "SD power");
784 gpio_direction_output(S3C64XX_GPB(1), 0); 796 gpio_direction_output(S3C64XX_GPB(1), 0);
785 797
786 gpio_request(S3C64XX_GPF(10), "nRESETSEL"); 798 gpio_request(S3C64XX_GPF(10), "nRESETSEL");
787 gpio_direction_output(S3C64XX_GPF(10), 1); 799 gpio_direction_output(S3C64XX_GPF(10), 1);
788 800
789 s3c_sdhci0_set_platdata(&crag6410_hsmmc0_pdata); 801 s3c_sdhci0_set_platdata(&crag6410_hsmmc0_pdata);
790 s3c_sdhci2_set_platdata(&crag6410_hsmmc2_pdata); 802 s3c_sdhci2_set_platdata(&crag6410_hsmmc2_pdata);
791 803
792 s3c_i2c0_set_platdata(&i2c0_pdata); 804 s3c_i2c0_set_platdata(&i2c0_pdata);
793 s3c_i2c1_set_platdata(&i2c1_pdata); 805 s3c_i2c1_set_platdata(&i2c1_pdata);
794 s3c_fb_set_platdata(&crag6410_lcd_pdata); 806 s3c_fb_set_platdata(&crag6410_lcd_pdata);
795 s3c_hsotg_set_platdata(&crag6410_hsotg_pdata); 807 s3c_hsotg_set_platdata(&crag6410_hsotg_pdata);
796 808
797 i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0)); 809 i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
798 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); 810 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
799 811
800 samsung_keypad_set_platdata(&crag6410_keypad_data); 812 samsung_keypad_set_platdata(&crag6410_keypad_data);
801 s3c64xx_spi0_set_platdata(NULL, 0, 1); 813 s3c64xx_spi0_set_platdata(NULL, 0, 1);
802 814
803 platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices)); 815 platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices));
804 816
805 gpio_led_register_device(-1, &gpio_leds_pdata); 817 gpio_led_register_device(-1, &gpio_leds_pdata);
806 818
807 regulator_has_full_constraints(); 819 regulator_has_full_constraints();
808 820
809 s3c64xx_pm_init(); 821 s3c64xx_pm_init();
810 } 822 }
811 823
812 MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410") 824 MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410")
813 /* Maintainer: Mark Brown <broonie@opensource.wolfsonmicro.com> */ 825 /* Maintainer: Mark Brown <broonie@opensource.wolfsonmicro.com> */
814 .atag_offset = 0x100, 826 .atag_offset = 0x100,
815 .init_irq = s3c6410_init_irq, 827 .init_irq = s3c6410_init_irq,
816 .handle_irq = vic_handle_irq, 828 .handle_irq = vic_handle_irq,
817 .map_io = crag6410_map_io, 829 .map_io = crag6410_map_io,
818 .init_machine = crag6410_machine_init, 830 .init_machine = crag6410_machine_init,
819 .init_late = s3c64xx_init_late, 831 .init_late = s3c64xx_init_late,
820 .timer = &s3c24xx_timer, 832 .timer = &s3c24xx_timer,
821 .restart = s3c64xx_restart, 833 .restart = s3c64xx_restart,
822 MACHINE_END 834 MACHINE_END
823 835
arch/arm/mach-shmobile/board-armadillo800eva.c
Diff comments   View file @ 95360fd
1 /* 1 /*
2 * armadillo 800 eva board support 2 * armadillo 800 eva board support
3 * 3 *
4 * Copyright (C) 2012 Renesas Solutions Corp. 4 * Copyright (C) 2012 Renesas Solutions Corp.
5 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 5 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License. 9 * the Free Software Foundation; version 2 of the License.
10 * 10 *
11 * This program is distributed in the hope that it will be useful, 11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 * 15 *
16 * You should have received a copy of the GNU General Public License 16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software 17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 * 19 *
20 */ 20 */
21 21
22 #include <linux/clk.h> 22 #include <linux/clk.h>
23 #include <linux/delay.h> 23 #include <linux/delay.h>
24 #include <linux/err.h> 24 #include <linux/err.h>
25 #include <linux/kernel.h> 25 #include <linux/kernel.h>
26 #include <linux/input.h> 26 #include <linux/input.h>
27 #include <linux/irq.h> 27 #include <linux/irq.h>
28 #include <linux/platform_device.h> 28 #include <linux/platform_device.h>
29 #include <linux/gpio.h> 29 #include <linux/gpio.h>
30 #include <linux/gpio_keys.h> 30 #include <linux/gpio_keys.h>
31 #include <linux/regulator/fixed.h> 31 #include <linux/regulator/fixed.h>
32 #include <linux/regulator/machine.h> 32 #include <linux/regulator/machine.h>
33 #include <linux/sh_eth.h> 33 #include <linux/sh_eth.h>
34 #include <linux/videodev2.h> 34 #include <linux/videodev2.h>
35 #include <linux/usb/renesas_usbhs.h> 35 #include <linux/usb/renesas_usbhs.h>
36 #include <linux/mfd/tmio.h> 36 #include <linux/mfd/tmio.h>
37 #include <linux/mmc/host.h> 37 #include <linux/mmc/host.h>
38 #include <linux/mmc/sh_mmcif.h> 38 #include <linux/mmc/sh_mmcif.h>
39 #include <linux/mmc/sh_mobile_sdhi.h> 39 #include <linux/mmc/sh_mobile_sdhi.h>
40 #include <linux/i2c-gpio.h>
40 #include <mach/common.h> 41 #include <mach/common.h>
41 #include <mach/irqs.h> 42 #include <mach/irqs.h>
42 #include <mach/r8a7740.h> 43 #include <mach/r8a7740.h>
43 #include <media/mt9t112.h> 44 #include <media/mt9t112.h>
44 #include <media/sh_mobile_ceu.h> 45 #include <media/sh_mobile_ceu.h>
45 #include <media/soc_camera.h> 46 #include <media/soc_camera.h>
46 #include <asm/page.h> 47 #include <asm/page.h>
47 #include <asm/mach-types.h> 48 #include <asm/mach-types.h>
48 #include <asm/mach/arch.h> 49 #include <asm/mach/arch.h>
49 #include <asm/mach/map.h> 50 #include <asm/mach/map.h>
50 #include <asm/mach/time.h> 51 #include <asm/mach/time.h>
51 #include <asm/hardware/cache-l2x0.h> 52 #include <asm/hardware/cache-l2x0.h>
52 #include <video/sh_mobile_lcdc.h> 53 #include <video/sh_mobile_lcdc.h>
53 #include <video/sh_mobile_hdmi.h> 54 #include <video/sh_mobile_hdmi.h>
54 #include <sound/sh_fsi.h> 55 #include <sound/sh_fsi.h>
55 #include <sound/simple_card.h> 56 #include <sound/simple_card.h>
56 57
57 /* 58 /*
58 * CON1 Camera Module 59 * CON1 Camera Module
59 * CON2 Extension Bus 60 * CON2 Extension Bus
60 * CON3 HDMI Output 61 * CON3 HDMI Output
61 * CON4 Composite Video Output 62 * CON4 Composite Video Output
62 * CON5 H-UDI JTAG 63 * CON5 H-UDI JTAG
63 * CON6 ARM JTAG 64 * CON6 ARM JTAG
64 * CON7 SD1 65 * CON7 SD1
65 * CON8 SD2 66 * CON8 SD2
66 * CON9 RTC BackUp 67 * CON9 RTC BackUp
67 * CON10 Monaural Mic Input 68 * CON10 Monaural Mic Input
68 * CON11 Stereo Headphone Output 69 * CON11 Stereo Headphone Output
69 * CON12 Audio Line Output(L) 70 * CON12 Audio Line Output(L)
70 * CON13 Audio Line Output(R) 71 * CON13 Audio Line Output(R)
71 * CON14 AWL13 Module 72 * CON14 AWL13 Module
72 * CON15 Extension 73 * CON15 Extension
73 * CON16 LCD1 74 * CON16 LCD1
74 * CON17 LCD2 75 * CON17 LCD2
75 * CON19 Power Input 76 * CON19 Power Input
76 * CON20 USB1 77 * CON20 USB1
77 * CON21 USB2 78 * CON21 USB2
78 * CON22 Serial 79 * CON22 Serial
79 * CON23 LAN 80 * CON23 LAN
80 * CON24 USB3 81 * CON24 USB3
81 * LED1 Camera LED(Yellow) 82 * LED1 Camera LED(Yellow)
82 * LED2 Power LED (Green) 83 * LED2 Power LED (Green)
83 * ED3-LED6 User LED(Yellow) 84 * ED3-LED6 User LED(Yellow)
84 * LED7 LAN link LED(Green) 85 * LED7 LAN link LED(Green)
85 * LED8 LAN activity LED(Yellow) 86 * LED8 LAN activity LED(Yellow)
86 */ 87 */
87 88
88 /* 89 /*
89 * DipSwitch 90 * DipSwitch
90 * 91 *
91 * SW1 92 * SW1
92 * 93 *
93 * -12345678-+---------------+---------------------------- 94 * -12345678-+---------------+----------------------------
94 * 1 | boot | hermit 95 * 1 | boot | hermit
95 * 0 | boot | OS auto boot 96 * 0 | boot | OS auto boot
96 * -12345678-+---------------+---------------------------- 97 * -12345678-+---------------+----------------------------
97 * 00 | boot device | eMMC 98 * 00 | boot device | eMMC
98 * 10 | boot device | SDHI0 (CON7) 99 * 10 | boot device | SDHI0 (CON7)
99 * 01 | boot device | - 100 * 01 | boot device | -
100 * 11 | boot device | Extension Buss (CS0) 101 * 11 | boot device | Extension Buss (CS0)
101 * -12345678-+---------------+---------------------------- 102 * -12345678-+---------------+----------------------------
102 * 0 | Extension Bus | D8-D15 disable, eMMC enable 103 * 0 | Extension Bus | D8-D15 disable, eMMC enable
103 * 1 | Extension Bus | D8-D15 enable, eMMC disable 104 * 1 | Extension Bus | D8-D15 enable, eMMC disable
104 * -12345678-+---------------+---------------------------- 105 * -12345678-+---------------+----------------------------
105 * 0 | SDHI1 | COM8 disable, COM14 enable 106 * 0 | SDHI1 | COM8 disable, COM14 enable
106 * 1 | SDHI1 | COM8 enable, COM14 disable 107 * 1 | SDHI1 | COM8 enable, COM14 disable
107 * -12345678-+---------------+---------------------------- 108 * -12345678-+---------------+----------------------------
108 * 0 | USB0 | COM20 enable, COM24 disable 109 * 0 | USB0 | COM20 enable, COM24 disable
109 * 1 | USB0 | COM20 disable, COM24 enable 110 * 1 | USB0 | COM20 disable, COM24 enable
110 * -12345678-+---------------+---------------------------- 111 * -12345678-+---------------+----------------------------
111 * 00 | JTAG | SH-X2 112 * 00 | JTAG | SH-X2
112 * 10 | JTAG | ARM 113 * 10 | JTAG | ARM
113 * 01 | JTAG | - 114 * 01 | JTAG | -
114 * 11 | JTAG | Boundary Scan 115 * 11 | JTAG | Boundary Scan
115 *-----------+---------------+---------------------------- 116 *-----------+---------------+----------------------------
116 */ 117 */
117 118
118 /* 119 /*
119 * FSI-WM8978 120 * FSI-WM8978
120 * 121 *
121 * this command is required when playback. 122 * this command is required when playback.
122 * 123 *
123 * # amixer set "Headphone" 50 124 * # amixer set "Headphone" 50
124 */ 125 */
125 126
126 /* 127 /*
127 * USB function 128 * USB function
128 * 129 *
129 * When you use USB Function, 130 * When you use USB Function,
130 * set SW1.6 ON, and connect cable to CN24. 131 * set SW1.6 ON, and connect cable to CN24.
131 * 132 *
132 * USBF needs workaround on R8A7740 chip. 133 * USBF needs workaround on R8A7740 chip.
133 * These are a little bit complex. 134 * These are a little bit complex.
134 * see 135 * see
135 * usbhsf_power_ctrl() 136 * usbhsf_power_ctrl()
136 */ 137 */
137 #define IRQ7 evt2irq(0x02e0) 138 #define IRQ7 evt2irq(0x02e0)
138 #define USBCR1 IOMEM(0xe605810a) 139 #define USBCR1 IOMEM(0xe605810a)
139 #define USBH 0xC6700000 140 #define USBH 0xC6700000
140 #define USBH_USBCTR 0x10834 141 #define USBH_USBCTR 0x10834
141 142
142 struct usbhsf_private { 143 struct usbhsf_private {
143 struct clk *phy; 144 struct clk *phy;
144 struct clk *usb24; 145 struct clk *usb24;
145 struct clk *pci; 146 struct clk *pci;
146 struct clk *func; 147 struct clk *func;
147 struct clk *host; 148 struct clk *host;
148 void __iomem *usbh_base; 149 void __iomem *usbh_base;
149 struct renesas_usbhs_platform_info info; 150 struct renesas_usbhs_platform_info info;
150 }; 151 };
151 152
152 #define usbhsf_get_priv(pdev) \ 153 #define usbhsf_get_priv(pdev) \
153 container_of(renesas_usbhs_get_info(pdev), \ 154 container_of(renesas_usbhs_get_info(pdev), \
154 struct usbhsf_private, info) 155 struct usbhsf_private, info)
155 156
156 static int usbhsf_get_id(struct platform_device *pdev) 157 static int usbhsf_get_id(struct platform_device *pdev)
157 { 158 {
158 return USBHS_GADGET; 159 return USBHS_GADGET;
159 } 160 }
160 161
161 static void usbhsf_power_ctrl(struct platform_device *pdev, 162 static void usbhsf_power_ctrl(struct platform_device *pdev,
162 void __iomem *base, int enable) 163 void __iomem *base, int enable)
163 { 164 {
164 struct usbhsf_private *priv = usbhsf_get_priv(pdev); 165 struct usbhsf_private *priv = usbhsf_get_priv(pdev);
165 166
166 /* 167 /*
167 * Work around for USB Function. 168 * Work around for USB Function.
168 * It needs USB host clock, and settings 169 * It needs USB host clock, and settings
169 */ 170 */
170 if (enable) { 171 if (enable) {
171 /* 172 /*
172 * enable all the related usb clocks 173 * enable all the related usb clocks
173 * for usb workaround 174 * for usb workaround
174 */ 175 */
175 clk_enable(priv->usb24); 176 clk_enable(priv->usb24);
176 clk_enable(priv->pci); 177 clk_enable(priv->pci);
177 clk_enable(priv->host); 178 clk_enable(priv->host);
178 clk_enable(priv->func); 179 clk_enable(priv->func);
179 clk_enable(priv->phy); 180 clk_enable(priv->phy);
180 181
181 /* 182 /*
182 * set USBCR1 183 * set USBCR1
183 * 184 *
184 * Port1 is driven by USB function, 185 * Port1 is driven by USB function,
185 * Port2 is driven by USB HOST 186 * Port2 is driven by USB HOST
186 * One HOST (Port1 or Port2 is HOST) 187 * One HOST (Port1 or Port2 is HOST)
187 * USB PLL input clock = 24MHz 188 * USB PLL input clock = 24MHz
188 */ 189 */
189 __raw_writew(0xd750, USBCR1); 190 __raw_writew(0xd750, USBCR1);
190 mdelay(1); 191 mdelay(1);
191 192
192 /* 193 /*
193 * start USB Host 194 * start USB Host
194 */ 195 */
195 __raw_writel(0x0000000c, priv->usbh_base + USBH_USBCTR); 196 __raw_writel(0x0000000c, priv->usbh_base + USBH_USBCTR);
196 __raw_writel(0x00000008, priv->usbh_base + USBH_USBCTR); 197 __raw_writel(0x00000008, priv->usbh_base + USBH_USBCTR);
197 mdelay(10); 198 mdelay(10);
198 199
199 /* 200 /*
200 * USB PHY Power ON 201 * USB PHY Power ON
201 */ 202 */
202 __raw_writew(0xd770, USBCR1); 203 __raw_writew(0xd770, USBCR1);
203 __raw_writew(0x4000, base + 0x102); /* USBF :: SUSPMODE */ 204 __raw_writew(0x4000, base + 0x102); /* USBF :: SUSPMODE */
204 205
205 } else { 206 } else {
206 __raw_writel(0x0000010f, priv->usbh_base + USBH_USBCTR); 207 __raw_writel(0x0000010f, priv->usbh_base + USBH_USBCTR);
207 __raw_writew(0xd7c0, USBCR1); /* GPIO */ 208 __raw_writew(0xd7c0, USBCR1); /* GPIO */
208 209
209 clk_disable(priv->phy); 210 clk_disable(priv->phy);
210 clk_disable(priv->func); /* usb work around */ 211 clk_disable(priv->func); /* usb work around */
211 clk_disable(priv->host); /* usb work around */ 212 clk_disable(priv->host); /* usb work around */
212 clk_disable(priv->pci); /* usb work around */ 213 clk_disable(priv->pci); /* usb work around */
213 clk_disable(priv->usb24); /* usb work around */ 214 clk_disable(priv->usb24); /* usb work around */
214 } 215 }
215 } 216 }
216 217
217 static int usbhsf_get_vbus(struct platform_device *pdev) 218 static int usbhsf_get_vbus(struct platform_device *pdev)
218 { 219 {
219 return gpio_get_value(GPIO_PORT209); 220 return gpio_get_value(GPIO_PORT209);
220 } 221 }
221 222
222 static irqreturn_t usbhsf_interrupt(int irq, void *data) 223 static irqreturn_t usbhsf_interrupt(int irq, void *data)
223 { 224 {
224 struct platform_device *pdev = data; 225 struct platform_device *pdev = data;
225 226
226 renesas_usbhs_call_notify_hotplug(pdev); 227 renesas_usbhs_call_notify_hotplug(pdev);
227 228
228 return IRQ_HANDLED; 229 return IRQ_HANDLED;
229 } 230 }
230 231
231 static void usbhsf_hardware_exit(struct platform_device *pdev) 232 static void usbhsf_hardware_exit(struct platform_device *pdev)
232 { 233 {
233 struct usbhsf_private *priv = usbhsf_get_priv(pdev); 234 struct usbhsf_private *priv = usbhsf_get_priv(pdev);
234 235
235 if (!IS_ERR(priv->phy)) 236 if (!IS_ERR(priv->phy))
236 clk_put(priv->phy); 237 clk_put(priv->phy);
237 if (!IS_ERR(priv->usb24)) 238 if (!IS_ERR(priv->usb24))
238 clk_put(priv->usb24); 239 clk_put(priv->usb24);
239 if (!IS_ERR(priv->pci)) 240 if (!IS_ERR(priv->pci))
240 clk_put(priv->pci); 241 clk_put(priv->pci);
241 if (!IS_ERR(priv->host)) 242 if (!IS_ERR(priv->host))
242 clk_put(priv->host); 243 clk_put(priv->host);
243 if (!IS_ERR(priv->func)) 244 if (!IS_ERR(priv->func))
244 clk_put(priv->func); 245 clk_put(priv->func);
245 if (priv->usbh_base) 246 if (priv->usbh_base)
246 iounmap(priv->usbh_base); 247 iounmap(priv->usbh_base);
247 248
248 priv->phy = NULL; 249 priv->phy = NULL;
249 priv->usb24 = NULL; 250 priv->usb24 = NULL;
250 priv->pci = NULL; 251 priv->pci = NULL;
251 priv->host = NULL; 252 priv->host = NULL;
252 priv->func = NULL; 253 priv->func = NULL;
253 priv->usbh_base = NULL; 254 priv->usbh_base = NULL;
254 255
255 free_irq(IRQ7, pdev); 256 free_irq(IRQ7, pdev);
256 } 257 }
257 258
258 static int usbhsf_hardware_init(struct platform_device *pdev) 259 static int usbhsf_hardware_init(struct platform_device *pdev)
259 { 260 {
260 struct usbhsf_private *priv = usbhsf_get_priv(pdev); 261 struct usbhsf_private *priv = usbhsf_get_priv(pdev);
261 int ret; 262 int ret;
262 263
263 priv->phy = clk_get(&pdev->dev, "phy"); 264 priv->phy = clk_get(&pdev->dev, "phy");
264 priv->usb24 = clk_get(&pdev->dev, "usb24"); 265 priv->usb24 = clk_get(&pdev->dev, "usb24");
265 priv->pci = clk_get(&pdev->dev, "pci"); 266 priv->pci = clk_get(&pdev->dev, "pci");
266 priv->func = clk_get(&pdev->dev, "func"); 267 priv->func = clk_get(&pdev->dev, "func");
267 priv->host = clk_get(&pdev->dev, "host"); 268 priv->host = clk_get(&pdev->dev, "host");
268 priv->usbh_base = ioremap_nocache(USBH, 0x20000); 269 priv->usbh_base = ioremap_nocache(USBH, 0x20000);
269 270
270 if (IS_ERR(priv->phy) || 271 if (IS_ERR(priv->phy) ||
271 IS_ERR(priv->usb24) || 272 IS_ERR(priv->usb24) ||
272 IS_ERR(priv->pci) || 273 IS_ERR(priv->pci) ||
273 IS_ERR(priv->host) || 274 IS_ERR(priv->host) ||
274 IS_ERR(priv->func) || 275 IS_ERR(priv->func) ||
275 !priv->usbh_base) { 276 !priv->usbh_base) {
276 dev_err(&pdev->dev, "USB clock setting failed\n"); 277 dev_err(&pdev->dev, "USB clock setting failed\n");
277 usbhsf_hardware_exit(pdev); 278 usbhsf_hardware_exit(pdev);
278 return -EIO; 279 return -EIO;
279 } 280 }
280 281
281 ret = request_irq(IRQ7, usbhsf_interrupt, IRQF_TRIGGER_NONE, 282 ret = request_irq(IRQ7, usbhsf_interrupt, IRQF_TRIGGER_NONE,
282 dev_name(&pdev->dev), pdev); 283 dev_name(&pdev->dev), pdev);
283 if (ret) { 284 if (ret) {
284 dev_err(&pdev->dev, "request_irq err\n"); 285 dev_err(&pdev->dev, "request_irq err\n");
285 return ret; 286 return ret;
286 } 287 }
287 irq_set_irq_type(IRQ7, IRQ_TYPE_EDGE_BOTH); 288 irq_set_irq_type(IRQ7, IRQ_TYPE_EDGE_BOTH);
288 289
289 /* usb24 use 1/1 of parent clock (= usb24s = 24MHz) */ 290 /* usb24 use 1/1 of parent clock (= usb24s = 24MHz) */
290 clk_set_rate(priv->usb24, 291 clk_set_rate(priv->usb24,
291 clk_get_rate(clk_get_parent(priv->usb24))); 292 clk_get_rate(clk_get_parent(priv->usb24)));
292 293
293 return 0; 294 return 0;
294 } 295 }
295 296
296 static struct usbhsf_private usbhsf_private = { 297 static struct usbhsf_private usbhsf_private = {
297 .info = { 298 .info = {
298 .platform_callback = { 299 .platform_callback = {
299 .get_id = usbhsf_get_id, 300 .get_id = usbhsf_get_id,
300 .get_vbus = usbhsf_get_vbus, 301 .get_vbus = usbhsf_get_vbus,
301 .hardware_init = usbhsf_hardware_init, 302 .hardware_init = usbhsf_hardware_init,
302 .hardware_exit = usbhsf_hardware_exit, 303 .hardware_exit = usbhsf_hardware_exit,
303 .power_ctrl = usbhsf_power_ctrl, 304 .power_ctrl = usbhsf_power_ctrl,
304 }, 305 },
305 .driver_param = { 306 .driver_param = {
306 .buswait_bwait = 5, 307 .buswait_bwait = 5,
307 .detection_delay = 5, 308 .detection_delay = 5,
308 .d0_rx_id = SHDMA_SLAVE_USBHS_RX, 309 .d0_rx_id = SHDMA_SLAVE_USBHS_RX,
309 .d1_tx_id = SHDMA_SLAVE_USBHS_TX, 310 .d1_tx_id = SHDMA_SLAVE_USBHS_TX,
310 }, 311 },
311 } 312 }
312 }; 313 };
313 314
314 static struct resource usbhsf_resources[] = { 315 static struct resource usbhsf_resources[] = {
315 { 316 {
316 .name = "USBHS", 317 .name = "USBHS",
317 .start = 0xe6890000, 318 .start = 0xe6890000,
318 .end = 0xe6890104 - 1, 319 .end = 0xe6890104 - 1,
319 .flags = IORESOURCE_MEM, 320 .flags = IORESOURCE_MEM,
320 }, 321 },
321 { 322 {
322 .start = evt2irq(0x0A20), 323 .start = evt2irq(0x0A20),
323 .flags = IORESOURCE_IRQ, 324 .flags = IORESOURCE_IRQ,
324 }, 325 },
325 }; 326 };
326 327
327 static struct platform_device usbhsf_device = { 328 static struct platform_device usbhsf_device = {
328 .name = "renesas_usbhs", 329 .name = "renesas_usbhs",
329 .dev = { 330 .dev = {
330 .platform_data = &usbhsf_private.info, 331 .platform_data = &usbhsf_private.info,
331 }, 332 },
332 .id = -1, 333 .id = -1,
333 .num_resources = ARRAY_SIZE(usbhsf_resources), 334 .num_resources = ARRAY_SIZE(usbhsf_resources),
334 .resource = usbhsf_resources, 335 .resource = usbhsf_resources,
335 }; 336 };
336 337
337 /* Ether */ 338 /* Ether */
338 static struct sh_eth_plat_data sh_eth_platdata = { 339 static struct sh_eth_plat_data sh_eth_platdata = {
339 .phy = 0x00, /* LAN8710A */ 340 .phy = 0x00, /* LAN8710A */
340 .edmac_endian = EDMAC_LITTLE_ENDIAN, 341 .edmac_endian = EDMAC_LITTLE_ENDIAN,
341 .register_type = SH_ETH_REG_GIGABIT, 342 .register_type = SH_ETH_REG_GIGABIT,
342 .phy_interface = PHY_INTERFACE_MODE_MII, 343 .phy_interface = PHY_INTERFACE_MODE_MII,
343 }; 344 };
344 345
345 static struct resource sh_eth_resources[] = { 346 static struct resource sh_eth_resources[] = {
346 { 347 {
347 .start = 0xe9a00000, 348 .start = 0xe9a00000,
348 .end = 0xe9a00800 - 1, 349 .end = 0xe9a00800 - 1,
349 .flags = IORESOURCE_MEM, 350 .flags = IORESOURCE_MEM,
350 }, { 351 }, {
351 .start = 0xe9a01800, 352 .start = 0xe9a01800,
352 .end = 0xe9a02000 - 1, 353 .end = 0xe9a02000 - 1,
353 .flags = IORESOURCE_MEM, 354 .flags = IORESOURCE_MEM,
354 }, { 355 }, {
355 .start = evt2irq(0x0500), 356 .start = evt2irq(0x0500),
356 .flags = IORESOURCE_IRQ, 357 .flags = IORESOURCE_IRQ,
357 }, 358 },
358 }; 359 };
359 360
360 static struct platform_device sh_eth_device = { 361 static struct platform_device sh_eth_device = {
361 .name = "sh-eth", 362 .name = "sh-eth",
362 .id = -1, 363 .id = -1,
363 .dev = { 364 .dev = {
364 .platform_data = &sh_eth_platdata, 365 .platform_data = &sh_eth_platdata,
365 }, 366 },
366 .resource = sh_eth_resources, 367 .resource = sh_eth_resources,
367 .num_resources = ARRAY_SIZE(sh_eth_resources), 368 .num_resources = ARRAY_SIZE(sh_eth_resources),
368 }; 369 };
369 370
370 /* LCDC */ 371 /* LCDC */
371 static struct fb_videomode lcdc0_mode = { 372 static struct fb_videomode lcdc0_mode = {
372 .name = "AMPIER/AM-800480", 373 .name = "AMPIER/AM-800480",
373 .xres = 800, 374 .xres = 800,
374 .yres = 480, 375 .yres = 480,
375 .left_margin = 88, 376 .left_margin = 88,
376 .right_margin = 40, 377 .right_margin = 40,
377 .hsync_len = 128, 378 .hsync_len = 128,
378 .upper_margin = 20, 379 .upper_margin = 20,
379 .lower_margin = 5, 380 .lower_margin = 5,
380 .vsync_len = 5, 381 .vsync_len = 5,
381 .sync = 0, 382 .sync = 0,
382 }; 383 };
383 384
384 static struct sh_mobile_lcdc_info lcdc0_info = { 385 static struct sh_mobile_lcdc_info lcdc0_info = {
385 .clock_source = LCDC_CLK_BUS, 386 .clock_source = LCDC_CLK_BUS,
386 .ch[0] = { 387 .ch[0] = {
387 .chan = LCDC_CHAN_MAINLCD, 388 .chan = LCDC_CHAN_MAINLCD,
388 .fourcc = V4L2_PIX_FMT_RGB565, 389 .fourcc = V4L2_PIX_FMT_RGB565,
389 .interface_type = RGB24, 390 .interface_type = RGB24,
390 .clock_divider = 5, 391 .clock_divider = 5,
391 .flags = 0, 392 .flags = 0,
392 .lcd_modes = &lcdc0_mode, 393 .lcd_modes = &lcdc0_mode,
393 .num_modes = 1, 394 .num_modes = 1,
394 .panel_cfg = { 395 .panel_cfg = {
395 .width = 111, 396 .width = 111,
396 .height = 68, 397 .height = 68,
397 }, 398 },
398 }, 399 },
399 }; 400 };
400 401
401 static struct resource lcdc0_resources[] = { 402 static struct resource lcdc0_resources[] = {
402 [0] = { 403 [0] = {
403 .name = "LCD0", 404 .name = "LCD0",
404 .start = 0xfe940000, 405 .start = 0xfe940000,
405 .end = 0xfe943fff, 406 .end = 0xfe943fff,
406 .flags = IORESOURCE_MEM, 407 .flags = IORESOURCE_MEM,
407 }, 408 },
408 [1] = { 409 [1] = {
409 .start = intcs_evt2irq(0x580), 410 .start = intcs_evt2irq(0x580),
410 .flags = IORESOURCE_IRQ, 411 .flags = IORESOURCE_IRQ,
411 }, 412 },
412 }; 413 };
413 414
414 static struct platform_device lcdc0_device = { 415 static struct platform_device lcdc0_device = {
415 .name = "sh_mobile_lcdc_fb", 416 .name = "sh_mobile_lcdc_fb",
416 .num_resources = ARRAY_SIZE(lcdc0_resources), 417 .num_resources = ARRAY_SIZE(lcdc0_resources),
417 .resource = lcdc0_resources, 418 .resource = lcdc0_resources,
418 .id = 0, 419 .id = 0,
419 .dev = { 420 .dev = {
420 .platform_data = &lcdc0_info, 421 .platform_data = &lcdc0_info,
421 .coherent_dma_mask = ~0, 422 .coherent_dma_mask = ~0,
422 }, 423 },
423 }; 424 };
424 425
425 /* 426 /*
426 * LCDC1/HDMI 427 * LCDC1/HDMI
427 */ 428 */
428 static struct sh_mobile_hdmi_info hdmi_info = { 429 static struct sh_mobile_hdmi_info hdmi_info = {
429 .flags = HDMI_OUTPUT_PUSH_PULL | 430 .flags = HDMI_OUTPUT_PUSH_PULL |
430 HDMI_OUTPUT_POLARITY_HI | 431 HDMI_OUTPUT_POLARITY_HI |
431 HDMI_32BIT_REG | 432 HDMI_32BIT_REG |
432 HDMI_HAS_HTOP1 | 433 HDMI_HAS_HTOP1 |
433 HDMI_SND_SRC_SPDIF, 434 HDMI_SND_SRC_SPDIF,
434 }; 435 };
435 436
436 static struct resource hdmi_resources[] = { 437 static struct resource hdmi_resources[] = {
437 [0] = { 438 [0] = {
438 .name = "HDMI", 439 .name = "HDMI",
439 .start = 0xe6be0000, 440 .start = 0xe6be0000,
440 .end = 0xe6be03ff, 441 .end = 0xe6be03ff,
441 .flags = IORESOURCE_MEM, 442 .flags = IORESOURCE_MEM,
442 }, 443 },
443 [1] = { 444 [1] = {
444 .start = evt2irq(0x1700), 445 .start = evt2irq(0x1700),
445 .flags = IORESOURCE_IRQ, 446 .flags = IORESOURCE_IRQ,
446 }, 447 },
447 [2] = { 448 [2] = {
448 .name = "HDMI emma3pf", 449 .name = "HDMI emma3pf",
449 .start = 0xe6be4000, 450 .start = 0xe6be4000,
450 .end = 0xe6be43ff, 451 .end = 0xe6be43ff,
451 .flags = IORESOURCE_MEM, 452 .flags = IORESOURCE_MEM,
452 }, 453 },
453 }; 454 };
454 455
455 static struct platform_device hdmi_device = { 456 static struct platform_device hdmi_device = {
456 .name = "sh-mobile-hdmi", 457 .name = "sh-mobile-hdmi",
457 .num_resources = ARRAY_SIZE(hdmi_resources), 458 .num_resources = ARRAY_SIZE(hdmi_resources),
458 .resource = hdmi_resources, 459 .resource = hdmi_resources,
459 .id = -1, 460 .id = -1,
460 .dev = { 461 .dev = {
461 .platform_data = &hdmi_info, 462 .platform_data = &hdmi_info,
462 }, 463 },
463 }; 464 };
464 465
465 static const struct fb_videomode lcdc1_mode = { 466 static const struct fb_videomode lcdc1_mode = {
466 .name = "HDMI 720p", 467 .name = "HDMI 720p",
467 .xres = 1280, 468 .xres = 1280,
468 .yres = 720, 469 .yres = 720,
469 .pixclock = 13468, 470 .pixclock = 13468,
470 .left_margin = 220, 471 .left_margin = 220,
471 .right_margin = 110, 472 .right_margin = 110,
472 .hsync_len = 40, 473 .hsync_len = 40,
473 .upper_margin = 20, 474 .upper_margin = 20,
474 .lower_margin = 5, 475 .lower_margin = 5,
475 .vsync_len = 5, 476 .vsync_len = 5,
476 .refresh = 60, 477 .refresh = 60,
477 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT, 478 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
478 }; 479 };
479 480
480 static struct sh_mobile_lcdc_info hdmi_lcdc_info = { 481 static struct sh_mobile_lcdc_info hdmi_lcdc_info = {
481 .clock_source = LCDC_CLK_PERIPHERAL, /* HDMI clock */ 482 .clock_source = LCDC_CLK_PERIPHERAL, /* HDMI clock */
482 .ch[0] = { 483 .ch[0] = {
483 .chan = LCDC_CHAN_MAINLCD, 484 .chan = LCDC_CHAN_MAINLCD,
484 .fourcc = V4L2_PIX_FMT_RGB565, 485 .fourcc = V4L2_PIX_FMT_RGB565,
485 .interface_type = RGB24, 486 .interface_type = RGB24,
486 .clock_divider = 1, 487 .clock_divider = 1,
487 .flags = LCDC_FLAGS_DWPOL, 488 .flags = LCDC_FLAGS_DWPOL,
488 .lcd_modes = &lcdc1_mode, 489 .lcd_modes = &lcdc1_mode,
489 .num_modes = 1, 490 .num_modes = 1,
490 .tx_dev = &hdmi_device, 491 .tx_dev = &hdmi_device,
491 .panel_cfg = { 492 .panel_cfg = {
492 .width = 1280, 493 .width = 1280,
493 .height = 720, 494 .height = 720,
494 }, 495 },
495 }, 496 },
496 }; 497 };
497 498
498 static struct resource hdmi_lcdc_resources[] = { 499 static struct resource hdmi_lcdc_resources[] = {
499 [0] = { 500 [0] = {
500 .name = "LCDC1", 501 .name = "LCDC1",
501 .start = 0xfe944000, 502 .start = 0xfe944000,
502 .end = 0xfe948000 - 1, 503 .end = 0xfe948000 - 1,
503 .flags = IORESOURCE_MEM, 504 .flags = IORESOURCE_MEM,
504 }, 505 },
505 [1] = { 506 [1] = {
506 .start = intcs_evt2irq(0x1780), 507 .start = intcs_evt2irq(0x1780),
507 .flags = IORESOURCE_IRQ, 508 .flags = IORESOURCE_IRQ,
508 }, 509 },
509 }; 510 };
510 511
511 static struct platform_device hdmi_lcdc_device = { 512 static struct platform_device hdmi_lcdc_device = {
512 .name = "sh_mobile_lcdc_fb", 513 .name = "sh_mobile_lcdc_fb",
513 .num_resources = ARRAY_SIZE(hdmi_lcdc_resources), 514 .num_resources = ARRAY_SIZE(hdmi_lcdc_resources),
514 .resource = hdmi_lcdc_resources, 515 .resource = hdmi_lcdc_resources,
515 .id = 1, 516 .id = 1,
516 .dev = { 517 .dev = {
517 .platform_data = &hdmi_lcdc_info, 518 .platform_data = &hdmi_lcdc_info,
518 .coherent_dma_mask = ~0, 519 .coherent_dma_mask = ~0,
519 }, 520 },
520 }; 521 };
521 522
522 /* GPIO KEY */ 523 /* GPIO KEY */
523 #define GPIO_KEY(c, g, d, ...) \ 524 #define GPIO_KEY(c, g, d, ...) \
524 { .code = c, .gpio = g, .desc = d, .active_low = 1, __VA_ARGS__ } 525 { .code = c, .gpio = g, .desc = d, .active_low = 1, __VA_ARGS__ }
525 526
526 static struct gpio_keys_button gpio_buttons[] = { 527 static struct gpio_keys_button gpio_buttons[] = {
527 GPIO_KEY(KEY_POWER, GPIO_PORT99, "SW3", .wakeup = 1), 528 GPIO_KEY(KEY_POWER, GPIO_PORT99, "SW3", .wakeup = 1),
528 GPIO_KEY(KEY_BACK, GPIO_PORT100, "SW4"), 529 GPIO_KEY(KEY_BACK, GPIO_PORT100, "SW4"),
529 GPIO_KEY(KEY_MENU, GPIO_PORT97, "SW5"), 530 GPIO_KEY(KEY_MENU, GPIO_PORT97, "SW5"),
530 GPIO_KEY(KEY_HOME, GPIO_PORT98, "SW6"), 531 GPIO_KEY(KEY_HOME, GPIO_PORT98, "SW6"),
531 }; 532 };
532 533
533 static struct gpio_keys_platform_data gpio_key_info = { 534 static struct gpio_keys_platform_data gpio_key_info = {
534 .buttons = gpio_buttons, 535 .buttons = gpio_buttons,
535 .nbuttons = ARRAY_SIZE(gpio_buttons), 536 .nbuttons = ARRAY_SIZE(gpio_buttons),
536 }; 537 };
537 538
538 static struct platform_device gpio_keys_device = { 539 static struct platform_device gpio_keys_device = {
539 .name = "gpio-keys", 540 .name = "gpio-keys",
540 .id = -1, 541 .id = -1,
541 .dev = { 542 .dev = {
542 .platform_data = &gpio_key_info, 543 .platform_data = &gpio_key_info,
543 }, 544 },
544 }; 545 };
545 546
546 /* Fixed 3.3V regulator to be used by SDHI0, SDHI1, MMCIF */ 547 /* Fixed 3.3V regulator to be used by SDHI0, SDHI1, MMCIF */
547 static struct regulator_consumer_supply fixed3v3_power_consumers[] = 548 static struct regulator_consumer_supply fixed3v3_power_consumers[] =
548 { 549 {
549 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), 550 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
550 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), 551 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
551 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"), 552 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
552 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"), 553 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
553 REGULATOR_SUPPLY("vmmc", "sh_mmcif"), 554 REGULATOR_SUPPLY("vmmc", "sh_mmcif"),
554 REGULATOR_SUPPLY("vqmmc", "sh_mmcif"), 555 REGULATOR_SUPPLY("vqmmc", "sh_mmcif"),
555 }; 556 };
556 557
557 /* SDHI0 */ 558 /* SDHI0 */
558 /* 559 /*
559 * FIXME 560 * FIXME
560 * 561 *
561 * It use polling mode here, since 562 * It use polling mode here, since
562 * CD (= Card Detect) pin is not connected to SDHI0_CD. 563 * CD (= Card Detect) pin is not connected to SDHI0_CD.
563 * We can use IRQ31 as card detect irq, 564 * We can use IRQ31 as card detect irq,
564 * but it needs chattering removal operation 565 * but it needs chattering removal operation
565 */ 566 */
566 #define IRQ31 evt2irq(0x33E0) 567 #define IRQ31 evt2irq(0x33E0)
567 static struct sh_mobile_sdhi_info sdhi0_info = { 568 static struct sh_mobile_sdhi_info sdhi0_info = {
568 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, 569 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
569 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, 570 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
570 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |\ 571 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |\
571 MMC_CAP_NEEDS_POLL, 572 MMC_CAP_NEEDS_POLL,
572 .tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, 573 .tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
573 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT, 574 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
574 }; 575 };
575 576
576 static struct resource sdhi0_resources[] = { 577 static struct resource sdhi0_resources[] = {
577 { 578 {
578 .name = "SDHI0", 579 .name = "SDHI0",
579 .start = 0xe6850000, 580 .start = 0xe6850000,
580 .end = 0xe6850100 - 1, 581 .end = 0xe6850100 - 1,
581 .flags = IORESOURCE_MEM, 582 .flags = IORESOURCE_MEM,
582 }, 583 },
583 /* 584 /*
584 * no SH_MOBILE_SDHI_IRQ_CARD_DETECT here 585 * no SH_MOBILE_SDHI_IRQ_CARD_DETECT here
585 */ 586 */
586 { 587 {
587 .name = SH_MOBILE_SDHI_IRQ_SDCARD, 588 .name = SH_MOBILE_SDHI_IRQ_SDCARD,
588 .start = evt2irq(0x0E20), 589 .start = evt2irq(0x0E20),
589 .flags = IORESOURCE_IRQ, 590 .flags = IORESOURCE_IRQ,
590 }, 591 },
591 { 592 {
592 .name = SH_MOBILE_SDHI_IRQ_SDIO, 593 .name = SH_MOBILE_SDHI_IRQ_SDIO,
593 .start = evt2irq(0x0E40), 594 .start = evt2irq(0x0E40),
594 .flags = IORESOURCE_IRQ, 595 .flags = IORESOURCE_IRQ,
595 }, 596 },
596 }; 597 };
597 598
598 static struct platform_device sdhi0_device = { 599 static struct platform_device sdhi0_device = {
599 .name = "sh_mobile_sdhi", 600 .name = "sh_mobile_sdhi",
600 .id = 0, 601 .id = 0,
601 .dev = { 602 .dev = {
602 .platform_data = &sdhi0_info, 603 .platform_data = &sdhi0_info,
603 }, 604 },
604 .num_resources = ARRAY_SIZE(sdhi0_resources), 605 .num_resources = ARRAY_SIZE(sdhi0_resources),
605 .resource = sdhi0_resources, 606 .resource = sdhi0_resources,
606 }; 607 };
607 608
608 /* SDHI1 */ 609 /* SDHI1 */
609 static struct sh_mobile_sdhi_info sdhi1_info = { 610 static struct sh_mobile_sdhi_info sdhi1_info = {
610 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, 611 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
611 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, 612 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
612 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, 613 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
613 .tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, 614 .tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
614 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT, 615 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
615 }; 616 };
616 617
617 static struct resource sdhi1_resources[] = { 618 static struct resource sdhi1_resources[] = {
618 [0] = { 619 [0] = {
619 .name = "SDHI1", 620 .name = "SDHI1",
620 .start = 0xe6860000, 621 .start = 0xe6860000,
621 .end = 0xe6860100 - 1, 622 .end = 0xe6860100 - 1,
622 .flags = IORESOURCE_MEM, 623 .flags = IORESOURCE_MEM,
623 }, 624 },
624 [1] = { 625 [1] = {
625 .start = evt2irq(0x0E80), 626 .start = evt2irq(0x0E80),
626 .flags = IORESOURCE_IRQ, 627 .flags = IORESOURCE_IRQ,
627 }, 628 },
628 [2] = { 629 [2] = {
629 .start = evt2irq(0x0EA0), 630 .start = evt2irq(0x0EA0),
630 .flags = IORESOURCE_IRQ, 631 .flags = IORESOURCE_IRQ,
631 }, 632 },
632 [3] = { 633 [3] = {
633 .start = evt2irq(0x0EC0), 634 .start = evt2irq(0x0EC0),
634 .flags = IORESOURCE_IRQ, 635 .flags = IORESOURCE_IRQ,
635 }, 636 },
636 }; 637 };
637 638
638 static struct platform_device sdhi1_device = { 639 static struct platform_device sdhi1_device = {
639 .name = "sh_mobile_sdhi", 640 .name = "sh_mobile_sdhi",
640 .id = 1, 641 .id = 1,
641 .dev = { 642 .dev = {
642 .platform_data = &sdhi1_info, 643 .platform_data = &sdhi1_info,
643 }, 644 },
644 .num_resources = ARRAY_SIZE(sdhi1_resources), 645 .num_resources = ARRAY_SIZE(sdhi1_resources),
645 .resource = sdhi1_resources, 646 .resource = sdhi1_resources,
646 }; 647 };
647 648
648 /* MMCIF */ 649 /* MMCIF */
649 static struct sh_mmcif_plat_data sh_mmcif_plat = { 650 static struct sh_mmcif_plat_data sh_mmcif_plat = {
650 .sup_pclk = 0, 651 .sup_pclk = 0,
651 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, 652 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
652 .caps = MMC_CAP_4_BIT_DATA | 653 .caps = MMC_CAP_4_BIT_DATA |
653 MMC_CAP_8_BIT_DATA | 654 MMC_CAP_8_BIT_DATA |
654 MMC_CAP_NONREMOVABLE, 655 MMC_CAP_NONREMOVABLE,
655 }; 656 };
656 657
657 static struct resource sh_mmcif_resources[] = { 658 static struct resource sh_mmcif_resources[] = {
658 [0] = { 659 [0] = {
659 .name = "MMCIF", 660 .name = "MMCIF",
660 .start = 0xe6bd0000, 661 .start = 0xe6bd0000,
661 .end = 0xe6bd0100 - 1, 662 .end = 0xe6bd0100 - 1,
662 .flags = IORESOURCE_MEM, 663 .flags = IORESOURCE_MEM,
663 }, 664 },
664 [1] = { 665 [1] = {
665 /* MMC ERR */ 666 /* MMC ERR */
666 .start = evt2irq(0x1AC0), 667 .start = evt2irq(0x1AC0),
667 .flags = IORESOURCE_IRQ, 668 .flags = IORESOURCE_IRQ,
668 }, 669 },
669 [2] = { 670 [2] = {
670 /* MMC NOR */ 671 /* MMC NOR */
671 .start = evt2irq(0x1AE0), 672 .start = evt2irq(0x1AE0),
672 .flags = IORESOURCE_IRQ, 673 .flags = IORESOURCE_IRQ,
673 }, 674 },
674 }; 675 };
675 676
676 static struct platform_device sh_mmcif_device = { 677 static struct platform_device sh_mmcif_device = {
677 .name = "sh_mmcif", 678 .name = "sh_mmcif",
678 .id = -1, 679 .id = -1,
679 .dev = { 680 .dev = {
680 .platform_data = &sh_mmcif_plat, 681 .platform_data = &sh_mmcif_plat,
681 }, 682 },
682 .num_resources = ARRAY_SIZE(sh_mmcif_resources), 683 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
683 .resource = sh_mmcif_resources, 684 .resource = sh_mmcif_resources,
684 }; 685 };
685 686
686 /* Camera */ 687 /* Camera */
687 static int mt9t111_power(struct device *dev, int mode) 688 static int mt9t111_power(struct device *dev, int mode)
688 { 689 {
689 struct clk *mclk = clk_get(NULL, "video1"); 690 struct clk *mclk = clk_get(NULL, "video1");
690 691
691 if (IS_ERR(mclk)) { 692 if (IS_ERR(mclk)) {
692 dev_err(dev, "can't get video1 clock\n"); 693 dev_err(dev, "can't get video1 clock\n");
693 return -EINVAL; 694 return -EINVAL;
694 } 695 }
695 696
696 if (mode) { 697 if (mode) {
697 /* video1 (= CON1 camera) expect 24MHz */ 698 /* video1 (= CON1 camera) expect 24MHz */
698 clk_set_rate(mclk, clk_round_rate(mclk, 24000000)); 699 clk_set_rate(mclk, clk_round_rate(mclk, 24000000));
699 clk_enable(mclk); 700 clk_enable(mclk);
700 gpio_direction_output(GPIO_PORT158, 1); 701 gpio_direction_output(GPIO_PORT158, 1);
701 } else { 702 } else {
702 gpio_direction_output(GPIO_PORT158, 0); 703 gpio_direction_output(GPIO_PORT158, 0);
703 clk_disable(mclk); 704 clk_disable(mclk);
704 } 705 }
705 706
706 clk_put(mclk); 707 clk_put(mclk);
707 708
708 return 0; 709 return 0;
709 } 710 }
710 711
711 static struct i2c_board_info i2c_camera_mt9t111 = { 712 static struct i2c_board_info i2c_camera_mt9t111 = {
712 I2C_BOARD_INFO("mt9t112", 0x3d), 713 I2C_BOARD_INFO("mt9t112", 0x3d),
713 }; 714 };
714 715
715 static struct mt9t112_camera_info mt9t111_info = { 716 static struct mt9t112_camera_info mt9t111_info = {
716 .divider = { 16, 0, 0, 7, 0, 10, 14, 7, 7 }, 717 .divider = { 16, 0, 0, 7, 0, 10, 14, 7, 7 },
717 }; 718 };
718 719
719 static struct soc_camera_link mt9t111_link = { 720 static struct soc_camera_link mt9t111_link = {
720 .i2c_adapter_id = 0, 721 .i2c_adapter_id = 0,
721 .bus_id = 0, 722 .bus_id = 0,
722 .board_info = &i2c_camera_mt9t111, 723 .board_info = &i2c_camera_mt9t111,
723 .power = mt9t111_power, 724 .power = mt9t111_power,
724 .priv = &mt9t111_info, 725 .priv = &mt9t111_info,
725 }; 726 };
726 727
727 static struct platform_device camera_device = { 728 static struct platform_device camera_device = {
728 .name = "soc-camera-pdrv", 729 .name = "soc-camera-pdrv",
729 .id = 0, 730 .id = 0,
730 .dev = { 731 .dev = {
731 .platform_data = &mt9t111_link, 732 .platform_data = &mt9t111_link,
732 }, 733 },
733 }; 734 };
734 735
735 /* CEU0 */ 736 /* CEU0 */
736 static struct sh_mobile_ceu_info sh_mobile_ceu0_info = { 737 static struct sh_mobile_ceu_info sh_mobile_ceu0_info = {
737 .flags = SH_CEU_FLAG_LOWER_8BIT, 738 .flags = SH_CEU_FLAG_LOWER_8BIT,
738 }; 739 };
739 740
740 static struct resource ceu0_resources[] = { 741 static struct resource ceu0_resources[] = {
741 [0] = { 742 [0] = {
742 .name = "CEU", 743 .name = "CEU",
743 .start = 0xfe910000, 744 .start = 0xfe910000,
744 .end = 0xfe91009f, 745 .end = 0xfe91009f,
745 .flags = IORESOURCE_MEM, 746 .flags = IORESOURCE_MEM,
746 }, 747 },
747 [1] = { 748 [1] = {
748 .start = intcs_evt2irq(0x0500), 749 .start = intcs_evt2irq(0x0500),
749 .flags = IORESOURCE_IRQ, 750 .flags = IORESOURCE_IRQ,
750 }, 751 },
751 [2] = { 752 [2] = {
752 /* place holder for contiguous memory */ 753 /* place holder for contiguous memory */
753 }, 754 },
754 }; 755 };
755 756
756 static struct platform_device ceu0_device = { 757 static struct platform_device ceu0_device = {
757 .name = "sh_mobile_ceu", 758 .name = "sh_mobile_ceu",
758 .id = 0, 759 .id = 0,
759 .num_resources = ARRAY_SIZE(ceu0_resources), 760 .num_resources = ARRAY_SIZE(ceu0_resources),
760 .resource = ceu0_resources, 761 .resource = ceu0_resources,
761 .dev = { 762 .dev = {
762 .platform_data = &sh_mobile_ceu0_info, 763 .platform_data = &sh_mobile_ceu0_info,
763 .coherent_dma_mask = 0xffffffff, 764 .coherent_dma_mask = 0xffffffff,
764 }, 765 },
765 }; 766 };
766 767
767 /* FSI */ 768 /* FSI */
768 static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable) 769 static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable)
769 { 770 {
770 struct clk *fsib; 771 struct clk *fsib;
771 int ret; 772 int ret;
772 773
773 /* it support 48KHz only */ 774 /* it support 48KHz only */
774 if (48000 != rate) 775 if (48000 != rate)
775 return -EINVAL; 776 return -EINVAL;
776 777
777 fsib = clk_get(dev, "ickb"); 778 fsib = clk_get(dev, "ickb");
778 if (IS_ERR(fsib)) 779 if (IS_ERR(fsib))
779 return -EINVAL; 780 return -EINVAL;
780 781
781 if (enable) { 782 if (enable) {
782 ret = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64; 783 ret = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
783 clk_enable(fsib); 784 clk_enable(fsib);
784 } else { 785 } else {
785 ret = 0; 786 ret = 0;
786 clk_disable(fsib); 787 clk_disable(fsib);
787 } 788 }
788 789
789 clk_put(fsib); 790 clk_put(fsib);
790 791
791 return ret; 792 return ret;
792 } 793 }
793 794
794 static struct sh_fsi_platform_info fsi_info = { 795 static struct sh_fsi_platform_info fsi_info = {
795 /* FSI-WM8978 */ 796 /* FSI-WM8978 */
796 .port_a = { 797 .port_a = {
797 .tx_id = SHDMA_SLAVE_FSIA_TX, 798 .tx_id = SHDMA_SLAVE_FSIA_TX,
798 }, 799 },
799 /* FSI-HDMI */ 800 /* FSI-HDMI */
800 .port_b = { 801 .port_b = {
801 .flags = SH_FSI_FMT_SPDIF | 802 .flags = SH_FSI_FMT_SPDIF |
802 SH_FSI_ENABLE_STREAM_MODE, 803 SH_FSI_ENABLE_STREAM_MODE,
803 .set_rate = fsi_hdmi_set_rate, 804 .set_rate = fsi_hdmi_set_rate,
804 .tx_id = SHDMA_SLAVE_FSIB_TX, 805 .tx_id = SHDMA_SLAVE_FSIB_TX,
805 } 806 }
806 }; 807 };
807 808
808 static struct resource fsi_resources[] = { 809 static struct resource fsi_resources[] = {
809 [0] = { 810 [0] = {
810 .name = "FSI", 811 .name = "FSI",
811 .start = 0xfe1f0000, 812 .start = 0xfe1f0000,
812 .end = 0xfe1f8400 - 1, 813 .end = 0xfe1f8400 - 1,
813 .flags = IORESOURCE_MEM, 814 .flags = IORESOURCE_MEM,
814 }, 815 },
815 [1] = { 816 [1] = {
816 .start = evt2irq(0x1840), 817 .start = evt2irq(0x1840),
817 .flags = IORESOURCE_IRQ, 818 .flags = IORESOURCE_IRQ,
818 }, 819 },
819 }; 820 };
820 821
821 static struct platform_device fsi_device = { 822 static struct platform_device fsi_device = {
822 .name = "sh_fsi2", 823 .name = "sh_fsi2",
823 .id = -1, 824 .id = -1,
824 .num_resources = ARRAY_SIZE(fsi_resources), 825 .num_resources = ARRAY_SIZE(fsi_resources),
825 .resource = fsi_resources, 826 .resource = fsi_resources,
826 .dev = { 827 .dev = {
827 .platform_data = &fsi_info, 828 .platform_data = &fsi_info,
828 }, 829 },
829 }; 830 };
830 831
831 /* FSI-WM8978 */ 832 /* FSI-WM8978 */
832 static struct asoc_simple_dai_init_info fsi_wm8978_init_info = { 833 static struct asoc_simple_dai_init_info fsi_wm8978_init_info = {
833 .fmt = SND_SOC_DAIFMT_I2S, 834 .fmt = SND_SOC_DAIFMT_I2S,
834 .codec_daifmt = SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_NB_NF, 835 .codec_daifmt = SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_NB_NF,
835 .cpu_daifmt = SND_SOC_DAIFMT_CBS_CFS, 836 .cpu_daifmt = SND_SOC_DAIFMT_CBS_CFS,
836 .sysclk = 12288000, 837 .sysclk = 12288000,
837 }; 838 };
838 839
839 static struct asoc_simple_card_info fsi_wm8978_info = { 840 static struct asoc_simple_card_info fsi_wm8978_info = {
840 .name = "wm8978", 841 .name = "wm8978",
841 .card = "FSI2A-WM8978", 842 .card = "FSI2A-WM8978",
842 .cpu_dai = "fsia-dai", 843 .cpu_dai = "fsia-dai",
843 .codec = "wm8978.0-001a", 844 .codec = "wm8978.0-001a",
844 .platform = "sh_fsi2", 845 .platform = "sh_fsi2",
845 .codec_dai = "wm8978-hifi", 846 .codec_dai = "wm8978-hifi",
846 .init = &fsi_wm8978_init_info, 847 .init = &fsi_wm8978_init_info,
847 }; 848 };
848 849
849 static struct platform_device fsi_wm8978_device = { 850 static struct platform_device fsi_wm8978_device = {
850 .name = "asoc-simple-card", 851 .name = "asoc-simple-card",
851 .id = 0, 852 .id = 0,
852 .dev = { 853 .dev = {
853 .platform_data = &fsi_wm8978_info, 854 .platform_data = &fsi_wm8978_info,
854 }, 855 },
855 }; 856 };
856 857
857 /* FSI-HDMI */ 858 /* FSI-HDMI */
858 static struct asoc_simple_dai_init_info fsi2_hdmi_init_info = { 859 static struct asoc_simple_dai_init_info fsi2_hdmi_init_info = {
859 .cpu_daifmt = SND_SOC_DAIFMT_CBM_CFM, 860 .cpu_daifmt = SND_SOC_DAIFMT_CBM_CFM,
860 }; 861 };
861 862
862 static struct asoc_simple_card_info fsi2_hdmi_info = { 863 static struct asoc_simple_card_info fsi2_hdmi_info = {
863 .name = "HDMI", 864 .name = "HDMI",
864 .card = "FSI2B-HDMI", 865 .card = "FSI2B-HDMI",
865 .cpu_dai = "fsib-dai", 866 .cpu_dai = "fsib-dai",
866 .codec = "sh-mobile-hdmi", 867 .codec = "sh-mobile-hdmi",
867 .platform = "sh_fsi2", 868 .platform = "sh_fsi2",
868 .codec_dai = "sh_mobile_hdmi-hifi", 869 .codec_dai = "sh_mobile_hdmi-hifi",
869 .init = &fsi2_hdmi_init_info, 870 .init = &fsi2_hdmi_init_info,
870 }; 871 };
871 872
872 static struct platform_device fsi_hdmi_device = { 873 static struct platform_device fsi_hdmi_device = {
873 .name = "asoc-simple-card", 874 .name = "asoc-simple-card",
874 .id = 1, 875 .id = 1,
875 .dev = { 876 .dev = {
876 .platform_data = &fsi2_hdmi_info, 877 .platform_data = &fsi2_hdmi_info,
877 }, 878 },
878 }; 879 };
879 880
881 /* RTC: RTC connects i2c-gpio. */
882 static struct i2c_gpio_platform_data i2c_gpio_data = {
883 .sda_pin = GPIO_PORT208,
884 .scl_pin = GPIO_PORT91,
885 .udelay = 5, /* 100 kHz */
886 };
887
888 static struct platform_device i2c_gpio_device = {
889 .name = "i2c-gpio",
890 .id = 2,
891 .dev = {
892 .platform_data = &i2c_gpio_data,
893 },
894 };
895
880 /* I2C */ 896 /* I2C */
881 static struct i2c_board_info i2c0_devices[] = { 897 static struct i2c_board_info i2c0_devices[] = {
882 { 898 {
883 I2C_BOARD_INFO("st1232-ts", 0x55), 899 I2C_BOARD_INFO("st1232-ts", 0x55),
884 .irq = evt2irq(0x0340), 900 .irq = evt2irq(0x0340),
885 }, 901 },
886 { 902 {
887 I2C_BOARD_INFO("wm8978", 0x1a), 903 I2C_BOARD_INFO("wm8978", 0x1a),
888 }, 904 },
889 }; 905 };
890 906
907 static struct i2c_board_info i2c2_devices[] = {
908 {
909 I2C_BOARD_INFO("s35390a", 0x30),
910 .type = "s35390a",
911 },
912 };
913
891 /* 914 /*
892 * board devices 915 * board devices
893 */ 916 */
894 static struct platform_device *eva_devices[] __initdata = { 917 static struct platform_device *eva_devices[] __initdata = {
895 &lcdc0_device, 918 &lcdc0_device,
896 &gpio_keys_device, 919 &gpio_keys_device,
897 &sh_eth_device, 920 &sh_eth_device,
898 &sdhi0_device, 921 &sdhi0_device,
899 &sh_mmcif_device, 922 &sh_mmcif_device,
900 &hdmi_device, 923 &hdmi_device,
901 &hdmi_lcdc_device, 924 &hdmi_lcdc_device,
902 &camera_device, 925 &camera_device,
903 &ceu0_device, 926 &ceu0_device,
904 &fsi_device, 927 &fsi_device,
905 &fsi_wm8978_device, 928 &fsi_wm8978_device,
906 &fsi_hdmi_device, 929 &fsi_hdmi_device,
930 &i2c_gpio_device,
907 }; 931 };
908 932
909 static void __init eva_clock_init(void) 933 static void __init eva_clock_init(void)
910 { 934 {
911 struct clk *system = clk_get(NULL, "system_clk"); 935 struct clk *system = clk_get(NULL, "system_clk");
912 struct clk *xtal1 = clk_get(NULL, "extal1"); 936 struct clk *xtal1 = clk_get(NULL, "extal1");
913 struct clk *usb24s = clk_get(NULL, "usb24s"); 937 struct clk *usb24s = clk_get(NULL, "usb24s");
914 struct clk *fsibck = clk_get(NULL, "fsibck"); 938 struct clk *fsibck = clk_get(NULL, "fsibck");
915 struct clk *fsib = clk_get(&fsi_device.dev, "ickb"); 939 struct clk *fsib = clk_get(&fsi_device.dev, "ickb");
916 940
917 if (IS_ERR(system) || 941 if (IS_ERR(system) ||
918 IS_ERR(xtal1) || 942 IS_ERR(xtal1) ||
919 IS_ERR(usb24s) || 943 IS_ERR(usb24s) ||
920 IS_ERR(fsibck) || 944 IS_ERR(fsibck) ||
921 IS_ERR(fsib)) { 945 IS_ERR(fsib)) {
922 pr_err("armadillo800eva board clock init failed\n"); 946 pr_err("armadillo800eva board clock init failed\n");
923 goto clock_error; 947 goto clock_error;
924 } 948 }
925 949
926 /* armadillo 800 eva extal1 is 24MHz */ 950 /* armadillo 800 eva extal1 is 24MHz */
927 clk_set_rate(xtal1, 24000000); 951 clk_set_rate(xtal1, 24000000);
928 952
929 /* usb24s use extal1 (= system) clock (= 24MHz) */ 953 /* usb24s use extal1 (= system) clock (= 24MHz) */
930 clk_set_parent(usb24s, system); 954 clk_set_parent(usb24s, system);
931 955
932 /* FSIBCK is 12.288MHz, and it is parent of FSI-B */ 956 /* FSIBCK is 12.288MHz, and it is parent of FSI-B */
933 clk_set_parent(fsib, fsibck); 957 clk_set_parent(fsib, fsibck);
934 clk_set_rate(fsibck, 12288000); 958 clk_set_rate(fsibck, 12288000);
935 clk_set_rate(fsib, 12288000); 959 clk_set_rate(fsib, 12288000);
936 960
937 clock_error: 961 clock_error:
938 if (!IS_ERR(system)) 962 if (!IS_ERR(system))
939 clk_put(system); 963 clk_put(system);
940 if (!IS_ERR(xtal1)) 964 if (!IS_ERR(xtal1))
941 clk_put(xtal1); 965 clk_put(xtal1);
942 if (!IS_ERR(usb24s)) 966 if (!IS_ERR(usb24s))
943 clk_put(usb24s); 967 clk_put(usb24s);
944 if (!IS_ERR(fsibck)) 968 if (!IS_ERR(fsibck))
945 clk_put(fsibck); 969 clk_put(fsibck);
946 if (!IS_ERR(fsib)) 970 if (!IS_ERR(fsib))
947 clk_put(fsib); 971 clk_put(fsib);
948 } 972 }
949 973
950 /* 974 /*
951 * board init 975 * board init
952 */ 976 */
953 #define GPIO_PORT7CR IOMEM(0xe6050007) 977 #define GPIO_PORT7CR IOMEM(0xe6050007)
954 #define GPIO_PORT8CR IOMEM(0xe6050008) 978 #define GPIO_PORT8CR IOMEM(0xe6050008)
955 static void __init eva_init(void) 979 static void __init eva_init(void)
956 { 980 {
957 struct platform_device *usb = NULL; 981 struct platform_device *usb = NULL;
958 982
959 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, 983 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
960 ARRAY_SIZE(fixed3v3_power_consumers), 3300000); 984 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
961 985
962 r8a7740_pinmux_init(); 986 r8a7740_pinmux_init();
963 r8a7740_meram_workaround(); 987 r8a7740_meram_workaround();
964 988
965 /* SCIFA1 */ 989 /* SCIFA1 */
966 gpio_request(GPIO_FN_SCIFA1_RXD, NULL); 990 gpio_request(GPIO_FN_SCIFA1_RXD, NULL);
967 gpio_request(GPIO_FN_SCIFA1_TXD, NULL); 991 gpio_request(GPIO_FN_SCIFA1_TXD, NULL);
968 992
969 /* LCDC0 */ 993 /* LCDC0 */
970 gpio_request(GPIO_FN_LCDC0_SELECT, NULL); 994 gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
971 gpio_request(GPIO_FN_LCD0_D0, NULL); 995 gpio_request(GPIO_FN_LCD0_D0, NULL);
972 gpio_request(GPIO_FN_LCD0_D1, NULL); 996 gpio_request(GPIO_FN_LCD0_D1, NULL);
973 gpio_request(GPIO_FN_LCD0_D2, NULL); 997 gpio_request(GPIO_FN_LCD0_D2, NULL);
974 gpio_request(GPIO_FN_LCD0_D3, NULL); 998 gpio_request(GPIO_FN_LCD0_D3, NULL);
975 gpio_request(GPIO_FN_LCD0_D4, NULL); 999 gpio_request(GPIO_FN_LCD0_D4, NULL);
976 gpio_request(GPIO_FN_LCD0_D5, NULL); 1000 gpio_request(GPIO_FN_LCD0_D5, NULL);
977 gpio_request(GPIO_FN_LCD0_D6, NULL); 1001 gpio_request(GPIO_FN_LCD0_D6, NULL);
978 gpio_request(GPIO_FN_LCD0_D7, NULL); 1002 gpio_request(GPIO_FN_LCD0_D7, NULL);
979 gpio_request(GPIO_FN_LCD0_D8, NULL); 1003 gpio_request(GPIO_FN_LCD0_D8, NULL);
980 gpio_request(GPIO_FN_LCD0_D9, NULL); 1004 gpio_request(GPIO_FN_LCD0_D9, NULL);
981 gpio_request(GPIO_FN_LCD0_D10, NULL); 1005 gpio_request(GPIO_FN_LCD0_D10, NULL);
982 gpio_request(GPIO_FN_LCD0_D11, NULL); 1006 gpio_request(GPIO_FN_LCD0_D11, NULL);
983 gpio_request(GPIO_FN_LCD0_D12, NULL); 1007 gpio_request(GPIO_FN_LCD0_D12, NULL);
984 gpio_request(GPIO_FN_LCD0_D13, NULL); 1008 gpio_request(GPIO_FN_LCD0_D13, NULL);
985 gpio_request(GPIO_FN_LCD0_D14, NULL); 1009 gpio_request(GPIO_FN_LCD0_D14, NULL);
986 gpio_request(GPIO_FN_LCD0_D15, NULL); 1010 gpio_request(GPIO_FN_LCD0_D15, NULL);
987 gpio_request(GPIO_FN_LCD0_D16, NULL); 1011 gpio_request(GPIO_FN_LCD0_D16, NULL);
988 gpio_request(GPIO_FN_LCD0_D17, NULL); 1012 gpio_request(GPIO_FN_LCD0_D17, NULL);
989 gpio_request(GPIO_FN_LCD0_D18_PORT40, NULL); 1013 gpio_request(GPIO_FN_LCD0_D18_PORT40, NULL);
990 gpio_request(GPIO_FN_LCD0_D19_PORT4, NULL); 1014 gpio_request(GPIO_FN_LCD0_D19_PORT4, NULL);
991 gpio_request(GPIO_FN_LCD0_D20_PORT3, NULL); 1015 gpio_request(GPIO_FN_LCD0_D20_PORT3, NULL);
992 gpio_request(GPIO_FN_LCD0_D21_PORT2, NULL); 1016 gpio_request(GPIO_FN_LCD0_D21_PORT2, NULL);
993 gpio_request(GPIO_FN_LCD0_D22_PORT0, NULL); 1017 gpio_request(GPIO_FN_LCD0_D22_PORT0, NULL);
994 gpio_request(GPIO_FN_LCD0_D23_PORT1, NULL); 1018 gpio_request(GPIO_FN_LCD0_D23_PORT1, NULL);
995 gpio_request(GPIO_FN_LCD0_DCK, NULL); 1019 gpio_request(GPIO_FN_LCD0_DCK, NULL);
996 gpio_request(GPIO_FN_LCD0_VSYN, NULL); 1020 gpio_request(GPIO_FN_LCD0_VSYN, NULL);
997 gpio_request(GPIO_FN_LCD0_HSYN, NULL); 1021 gpio_request(GPIO_FN_LCD0_HSYN, NULL);
998 gpio_request(GPIO_FN_LCD0_DISP, NULL); 1022 gpio_request(GPIO_FN_LCD0_DISP, NULL);
999 gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL); 1023 gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
1000 1024
1001 gpio_request(GPIO_PORT61, NULL); /* LCDDON */ 1025 gpio_request(GPIO_PORT61, NULL); /* LCDDON */
1002 gpio_direction_output(GPIO_PORT61, 1); 1026 gpio_direction_output(GPIO_PORT61, 1);
1003 1027
1004 gpio_request(GPIO_PORT202, NULL); /* LCD0_LED_CONT */ 1028 gpio_request(GPIO_PORT202, NULL); /* LCD0_LED_CONT */
1005 gpio_direction_output(GPIO_PORT202, 0); 1029 gpio_direction_output(GPIO_PORT202, 0);
1006 1030
1007 /* Touchscreen */ 1031 /* Touchscreen */
1008 gpio_request(GPIO_FN_IRQ10, NULL); /* TP_INT */ 1032 gpio_request(GPIO_FN_IRQ10, NULL); /* TP_INT */
1009 gpio_request(GPIO_PORT166, NULL); /* TP_RST_B */ 1033 gpio_request(GPIO_PORT166, NULL); /* TP_RST_B */
1010 gpio_direction_output(GPIO_PORT166, 1); 1034 gpio_direction_output(GPIO_PORT166, 1);
1011 1035
1012 /* GETHER */ 1036 /* GETHER */
1013 gpio_request(GPIO_FN_ET_CRS, NULL); 1037 gpio_request(GPIO_FN_ET_CRS, NULL);
1014 gpio_request(GPIO_FN_ET_MDC, NULL); 1038 gpio_request(GPIO_FN_ET_MDC, NULL);
1015 gpio_request(GPIO_FN_ET_MDIO, NULL); 1039 gpio_request(GPIO_FN_ET_MDIO, NULL);
1016 gpio_request(GPIO_FN_ET_TX_ER, NULL); 1040 gpio_request(GPIO_FN_ET_TX_ER, NULL);
1017 gpio_request(GPIO_FN_ET_RX_ER, NULL); 1041 gpio_request(GPIO_FN_ET_RX_ER, NULL);
1018 gpio_request(GPIO_FN_ET_ERXD0, NULL); 1042 gpio_request(GPIO_FN_ET_ERXD0, NULL);
1019 gpio_request(GPIO_FN_ET_ERXD1, NULL); 1043 gpio_request(GPIO_FN_ET_ERXD1, NULL);
1020 gpio_request(GPIO_FN_ET_ERXD2, NULL); 1044 gpio_request(GPIO_FN_ET_ERXD2, NULL);
1021 gpio_request(GPIO_FN_ET_ERXD3, NULL); 1045 gpio_request(GPIO_FN_ET_ERXD3, NULL);
1022 gpio_request(GPIO_FN_ET_TX_CLK, NULL); 1046 gpio_request(GPIO_FN_ET_TX_CLK, NULL);
1023 gpio_request(GPIO_FN_ET_TX_EN, NULL); 1047 gpio_request(GPIO_FN_ET_TX_EN, NULL);
1024 gpio_request(GPIO_FN_ET_ETXD0, NULL); 1048 gpio_request(GPIO_FN_ET_ETXD0, NULL);
1025 gpio_request(GPIO_FN_ET_ETXD1, NULL); 1049 gpio_request(GPIO_FN_ET_ETXD1, NULL);
1026 gpio_request(GPIO_FN_ET_ETXD2, NULL); 1050 gpio_request(GPIO_FN_ET_ETXD2, NULL);
1027 gpio_request(GPIO_FN_ET_ETXD3, NULL); 1051 gpio_request(GPIO_FN_ET_ETXD3, NULL);
1028 gpio_request(GPIO_FN_ET_PHY_INT, NULL); 1052 gpio_request(GPIO_FN_ET_PHY_INT, NULL);
1029 gpio_request(GPIO_FN_ET_COL, NULL); 1053 gpio_request(GPIO_FN_ET_COL, NULL);
1030 gpio_request(GPIO_FN_ET_RX_DV, NULL); 1054 gpio_request(GPIO_FN_ET_RX_DV, NULL);
1031 gpio_request(GPIO_FN_ET_RX_CLK, NULL); 1055 gpio_request(GPIO_FN_ET_RX_CLK, NULL);
1032 1056
1033 gpio_request(GPIO_PORT18, NULL); /* PHY_RST */ 1057 gpio_request(GPIO_PORT18, NULL); /* PHY_RST */
1034 gpio_direction_output(GPIO_PORT18, 1); 1058 gpio_direction_output(GPIO_PORT18, 1);
1035 1059
1036 /* USB */ 1060 /* USB */
1037 gpio_request(GPIO_PORT159, NULL); /* USB_DEVICE_MODE */ 1061 gpio_request(GPIO_PORT159, NULL); /* USB_DEVICE_MODE */
1038 gpio_direction_input(GPIO_PORT159); 1062 gpio_direction_input(GPIO_PORT159);
1039 1063
1040 if (gpio_get_value(GPIO_PORT159)) { 1064 if (gpio_get_value(GPIO_PORT159)) {
1041 /* USB Host */ 1065 /* USB Host */
1042 } else { 1066 } else {
1043 /* USB Func */ 1067 /* USB Func */
1044 /* 1068 /*
1045 * A1 chip has 2 IRQ7 pin and it was controled by MSEL register. 1069 * A1 chip has 2 IRQ7 pin and it was controled by MSEL register.
1046 * OTOH, usbhs interrupt needs its value (HI/LOW) to decide 1070 * OTOH, usbhs interrupt needs its value (HI/LOW) to decide
1047 * USB connection/disconnection (usbhsf_get_vbus()). 1071 * USB connection/disconnection (usbhsf_get_vbus()).
1048 * This means we needs to select GPIO_FN_IRQ7_PORT209 first, 1072 * This means we needs to select GPIO_FN_IRQ7_PORT209 first,
1049 * and select GPIO_PORT209 here 1073 * and select GPIO_PORT209 here
1050 */ 1074 */
1051 gpio_request(GPIO_FN_IRQ7_PORT209, NULL); 1075 gpio_request(GPIO_FN_IRQ7_PORT209, NULL);
1052 gpio_request(GPIO_PORT209, NULL); 1076 gpio_request(GPIO_PORT209, NULL);
1053 gpio_direction_input(GPIO_PORT209); 1077 gpio_direction_input(GPIO_PORT209);
1054 1078
1055 platform_device_register(&usbhsf_device); 1079 platform_device_register(&usbhsf_device);
1056 usb = &usbhsf_device; 1080 usb = &usbhsf_device;
1057 } 1081 }
1058 1082
1059 /* SDHI0 */ 1083 /* SDHI0 */
1060 gpio_request(GPIO_FN_SDHI0_CMD, NULL); 1084 gpio_request(GPIO_FN_SDHI0_CMD, NULL);
1061 gpio_request(GPIO_FN_SDHI0_CLK, NULL); 1085 gpio_request(GPIO_FN_SDHI0_CLK, NULL);
1062 gpio_request(GPIO_FN_SDHI0_D0, NULL); 1086 gpio_request(GPIO_FN_SDHI0_D0, NULL);
1063 gpio_request(GPIO_FN_SDHI0_D1, NULL); 1087 gpio_request(GPIO_FN_SDHI0_D1, NULL);
1064 gpio_request(GPIO_FN_SDHI0_D2, NULL); 1088 gpio_request(GPIO_FN_SDHI0_D2, NULL);
1065 gpio_request(GPIO_FN_SDHI0_D3, NULL); 1089 gpio_request(GPIO_FN_SDHI0_D3, NULL);
1066 gpio_request(GPIO_FN_SDHI0_WP, NULL); 1090 gpio_request(GPIO_FN_SDHI0_WP, NULL);
1067 1091
1068 gpio_request(GPIO_PORT17, NULL); /* SDHI0_18/33_B */ 1092 gpio_request(GPIO_PORT17, NULL); /* SDHI0_18/33_B */
1069 gpio_request(GPIO_PORT74, NULL); /* SDHI0_PON */ 1093 gpio_request(GPIO_PORT74, NULL); /* SDHI0_PON */
1070 gpio_request(GPIO_PORT75, NULL); /* SDSLOT1_PON */ 1094 gpio_request(GPIO_PORT75, NULL); /* SDSLOT1_PON */
1071 gpio_direction_output(GPIO_PORT17, 0); 1095 gpio_direction_output(GPIO_PORT17, 0);
1072 gpio_direction_output(GPIO_PORT74, 1); 1096 gpio_direction_output(GPIO_PORT74, 1);
1073 gpio_direction_output(GPIO_PORT75, 1); 1097 gpio_direction_output(GPIO_PORT75, 1);
1074 1098
1075 /* we can use GPIO_FN_IRQ31_PORT167 here for SDHI0 CD irq */ 1099 /* we can use GPIO_FN_IRQ31_PORT167 here for SDHI0 CD irq */
1076 1100
1077 /* 1101 /*
1078 * MMCIF 1102 * MMCIF
1079 * 1103 *
1080 * Here doesn't care SW1.4 status, 1104 * Here doesn't care SW1.4 status,
1081 * since CON2 is not mounted. 1105 * since CON2 is not mounted.
1082 */ 1106 */
1083 gpio_request(GPIO_FN_MMC1_CLK_PORT103, NULL); 1107 gpio_request(GPIO_FN_MMC1_CLK_PORT103, NULL);
1084 gpio_request(GPIO_FN_MMC1_CMD_PORT104, NULL); 1108 gpio_request(GPIO_FN_MMC1_CMD_PORT104, NULL);
1085 gpio_request(GPIO_FN_MMC1_D0_PORT149, NULL); 1109 gpio_request(GPIO_FN_MMC1_D0_PORT149, NULL);
1086 gpio_request(GPIO_FN_MMC1_D1_PORT148, NULL); 1110 gpio_request(GPIO_FN_MMC1_D1_PORT148, NULL);
1087 gpio_request(GPIO_FN_MMC1_D2_PORT147, NULL); 1111 gpio_request(GPIO_FN_MMC1_D2_PORT147, NULL);
1088 gpio_request(GPIO_FN_MMC1_D3_PORT146, NULL); 1112 gpio_request(GPIO_FN_MMC1_D3_PORT146, NULL);
1089 gpio_request(GPIO_FN_MMC1_D4_PORT145, NULL); 1113 gpio_request(GPIO_FN_MMC1_D4_PORT145, NULL);
1090 gpio_request(GPIO_FN_MMC1_D5_PORT144, NULL); 1114 gpio_request(GPIO_FN_MMC1_D5_PORT144, NULL);
1091 gpio_request(GPIO_FN_MMC1_D6_PORT143, NULL); 1115 gpio_request(GPIO_FN_MMC1_D6_PORT143, NULL);
1092 gpio_request(GPIO_FN_MMC1_D7_PORT142, NULL); 1116 gpio_request(GPIO_FN_MMC1_D7_PORT142, NULL);
1093 1117
1094 /* CEU0 */ 1118 /* CEU0 */
1095 gpio_request(GPIO_FN_VIO0_D7, NULL); 1119 gpio_request(GPIO_FN_VIO0_D7, NULL);
1096 gpio_request(GPIO_FN_VIO0_D6, NULL); 1120 gpio_request(GPIO_FN_VIO0_D6, NULL);
1097 gpio_request(GPIO_FN_VIO0_D5, NULL); 1121 gpio_request(GPIO_FN_VIO0_D5, NULL);
1098 gpio_request(GPIO_FN_VIO0_D4, NULL); 1122 gpio_request(GPIO_FN_VIO0_D4, NULL);
1099 gpio_request(GPIO_FN_VIO0_D3, NULL); 1123 gpio_request(GPIO_FN_VIO0_D3, NULL);
1100 gpio_request(GPIO_FN_VIO0_D2, NULL); 1124 gpio_request(GPIO_FN_VIO0_D2, NULL);
1101 gpio_request(GPIO_FN_VIO0_D1, NULL); 1125 gpio_request(GPIO_FN_VIO0_D1, NULL);
1102 gpio_request(GPIO_FN_VIO0_D0, NULL); 1126 gpio_request(GPIO_FN_VIO0_D0, NULL);
1103 gpio_request(GPIO_FN_VIO0_CLK, NULL); 1127 gpio_request(GPIO_FN_VIO0_CLK, NULL);
1104 gpio_request(GPIO_FN_VIO0_HD, NULL); 1128 gpio_request(GPIO_FN_VIO0_HD, NULL);
1105 gpio_request(GPIO_FN_VIO0_VD, NULL); 1129 gpio_request(GPIO_FN_VIO0_VD, NULL);
1106 gpio_request(GPIO_FN_VIO0_FIELD, NULL); 1130 gpio_request(GPIO_FN_VIO0_FIELD, NULL);
1107 gpio_request(GPIO_FN_VIO_CKO, NULL); 1131 gpio_request(GPIO_FN_VIO_CKO, NULL);
1108 1132
1109 /* CON1/CON15 Camera */ 1133 /* CON1/CON15 Camera */
1110 gpio_request(GPIO_PORT173, NULL); /* STANDBY */ 1134 gpio_request(GPIO_PORT173, NULL); /* STANDBY */
1111 gpio_request(GPIO_PORT172, NULL); /* RST */ 1135 gpio_request(GPIO_PORT172, NULL); /* RST */
1112 gpio_request(GPIO_PORT158, NULL); /* CAM_PON */ 1136 gpio_request(GPIO_PORT158, NULL); /* CAM_PON */
1113 gpio_direction_output(GPIO_PORT173, 0); 1137 gpio_direction_output(GPIO_PORT173, 0);
1114 gpio_direction_output(GPIO_PORT172, 1); 1138 gpio_direction_output(GPIO_PORT172, 1);
1115 gpio_direction_output(GPIO_PORT158, 0); /* see mt9t111_power() */ 1139 gpio_direction_output(GPIO_PORT158, 0); /* see mt9t111_power() */
1116 1140
1117 /* FSI-WM8978 */ 1141 /* FSI-WM8978 */
1118 gpio_request(GPIO_FN_FSIAIBT, NULL); 1142 gpio_request(GPIO_FN_FSIAIBT, NULL);
1119 gpio_request(GPIO_FN_FSIAILR, NULL); 1143 gpio_request(GPIO_FN_FSIAILR, NULL);
1120 gpio_request(GPIO_FN_FSIAOMC, NULL); 1144 gpio_request(GPIO_FN_FSIAOMC, NULL);
1121 gpio_request(GPIO_FN_FSIAOSLD, NULL); 1145 gpio_request(GPIO_FN_FSIAOSLD, NULL);
1122 gpio_request(GPIO_FN_FSIAISLD_PORT5, NULL); 1146 gpio_request(GPIO_FN_FSIAISLD_PORT5, NULL);
1123 1147
1124 gpio_request(GPIO_PORT7, NULL); 1148 gpio_request(GPIO_PORT7, NULL);
1125 gpio_request(GPIO_PORT8, NULL); 1149 gpio_request(GPIO_PORT8, NULL);
1126 gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */ 1150 gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */
1127 gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */ 1151 gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */
1128 1152
1129 /* FSI-HDMI */ 1153 /* FSI-HDMI */
1130 gpio_request(GPIO_FN_FSIBCK, NULL); 1154 gpio_request(GPIO_FN_FSIBCK, NULL);
1131 1155
1132 /* HDMI */ 1156 /* HDMI */
1133 gpio_request(GPIO_FN_HDMI_HPD, NULL); 1157 gpio_request(GPIO_FN_HDMI_HPD, NULL);
1134 gpio_request(GPIO_FN_HDMI_CEC, NULL); 1158 gpio_request(GPIO_FN_HDMI_CEC, NULL);
1135 1159
1136 /* 1160 /*
1137 * CAUTION 1161 * CAUTION
1138 * 1162 *
1139 * DBGMD/LCDC0/FSIA MUX 1163 * DBGMD/LCDC0/FSIA MUX
1140 * DBGMD_SELECT_B should be set after setting PFC Function. 1164 * DBGMD_SELECT_B should be set after setting PFC Function.
1141 */ 1165 */
1142 gpio_request(GPIO_PORT176, NULL); 1166 gpio_request(GPIO_PORT176, NULL);
1143 gpio_direction_output(GPIO_PORT176, 1); 1167 gpio_direction_output(GPIO_PORT176, 1);
1144 1168
1145 /* 1169 /*
1146 * We can switch CON8/CON14 by SW1.5, 1170 * We can switch CON8/CON14 by SW1.5,
1147 * but it needs after DBGMD_SELECT_B 1171 * but it needs after DBGMD_SELECT_B
1148 */ 1172 */
1149 gpio_request(GPIO_PORT6, NULL); 1173 gpio_request(GPIO_PORT6, NULL);
1150 gpio_direction_input(GPIO_PORT6); 1174 gpio_direction_input(GPIO_PORT6);
1151 if (gpio_get_value(GPIO_PORT6)) { 1175 if (gpio_get_value(GPIO_PORT6)) {
1152 /* CON14 enable */ 1176 /* CON14 enable */
1153 } else { 1177 } else {
1154 /* CON8 (SDHI1) enable */ 1178 /* CON8 (SDHI1) enable */
1155 gpio_request(GPIO_FN_SDHI1_CLK, NULL); 1179 gpio_request(GPIO_FN_SDHI1_CLK, NULL);
1156 gpio_request(GPIO_FN_SDHI1_CMD, NULL); 1180 gpio_request(GPIO_FN_SDHI1_CMD, NULL);
1157 gpio_request(GPIO_FN_SDHI1_D0, NULL); 1181 gpio_request(GPIO_FN_SDHI1_D0, NULL);
1158 gpio_request(GPIO_FN_SDHI1_D1, NULL); 1182 gpio_request(GPIO_FN_SDHI1_D1, NULL);
1159 gpio_request(GPIO_FN_SDHI1_D2, NULL); 1183 gpio_request(GPIO_FN_SDHI1_D2, NULL);
1160 gpio_request(GPIO_FN_SDHI1_D3, NULL); 1184 gpio_request(GPIO_FN_SDHI1_D3, NULL);
1161 gpio_request(GPIO_FN_SDHI1_CD, NULL); 1185 gpio_request(GPIO_FN_SDHI1_CD, NULL);
1162 gpio_request(GPIO_FN_SDHI1_WP, NULL); 1186 gpio_request(GPIO_FN_SDHI1_WP, NULL);
1163 1187
1164 gpio_request(GPIO_PORT16, NULL); /* SDSLOT2_PON */ 1188 gpio_request(GPIO_PORT16, NULL); /* SDSLOT2_PON */
1165 gpio_direction_output(GPIO_PORT16, 1); 1189 gpio_direction_output(GPIO_PORT16, 1);
1166 1190
1167 platform_device_register(&sdhi1_device); 1191 platform_device_register(&sdhi1_device);
1168 } 1192 }
1169 1193
1170 1194
1171 #ifdef CONFIG_CACHE_L2X0 1195 #ifdef CONFIG_CACHE_L2X0
1172 /* Early BRESP enable, Shared attribute override enable, 32K*8way */ 1196 /* Early BRESP enable, Shared attribute override enable, 32K*8way */
1173 l2x0_init(__io(0xf0002000), 0x40440000, 0x82000fff); 1197 l2x0_init(__io(0xf0002000), 0x40440000, 0x82000fff);
1174 #endif 1198 #endif
1175 1199
1176 i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices)); 1200 i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices));
1201 i2c_register_board_info(2, i2c2_devices, ARRAY_SIZE(i2c2_devices));
1177 1202
1178 r8a7740_add_standard_devices(); 1203 r8a7740_add_standard_devices();
1179 1204
1180 platform_add_devices(eva_devices, 1205 platform_add_devices(eva_devices,
1181 ARRAY_SIZE(eva_devices)); 1206 ARRAY_SIZE(eva_devices));
1182 1207
1183 eva_clock_init(); 1208 eva_clock_init();
1184 1209
1185 rmobile_add_device_to_domain(&r8a7740_pd_a4lc, &lcdc0_device); 1210 rmobile_add_device_to_domain(&r8a7740_pd_a4lc, &lcdc0_device);
1186 rmobile_add_device_to_domain(&r8a7740_pd_a4lc, &hdmi_lcdc_device); 1211 rmobile_add_device_to_domain(&r8a7740_pd_a4lc, &hdmi_lcdc_device);
1187 if (usb) 1212 if (usb)
1188 rmobile_add_device_to_domain(&r8a7740_pd_a3sp, usb); 1213 rmobile_add_device_to_domain(&r8a7740_pd_a3sp, usb);
1189 } 1214 }
1190 1215
1191 static void __init eva_earlytimer_init(void) 1216 static void __init eva_earlytimer_init(void)
1192 { 1217 {
1193 r8a7740_clock_init(MD_CK0 | MD_CK2); 1218 r8a7740_clock_init(MD_CK0 | MD_CK2);
1194 shmobile_earlytimer_init(); 1219 shmobile_earlytimer_init();
1195 } 1220 }
1196 1221
1197 static void __init eva_add_early_devices(void) 1222 static void __init eva_add_early_devices(void)
1198 { 1223 {
1199 r8a7740_add_early_devices(); 1224 r8a7740_add_early_devices();
1200 1225
1201 /* override timer setup with board-specific code */ 1226 /* override timer setup with board-specific code */
1202 shmobile_timer.init = eva_earlytimer_init; 1227 shmobile_timer.init = eva_earlytimer_init;
1203 } 1228 }
1204 1229
1205 static const char *eva_boards_compat_dt[] __initdata = { 1230 static const char *eva_boards_compat_dt[] __initdata = {
1206 "renesas,armadillo800eva", 1231 "renesas,armadillo800eva",
1207 NULL, 1232 NULL,
1208 }; 1233 };
1209 1234
1210 DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva") 1235 DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva")
1211 .map_io = r8a7740_map_io, 1236 .map_io = r8a7740_map_io,
1212 .init_early = eva_add_early_devices, 1237 .init_early = eva_add_early_devices,
1213 .init_irq = r8a7740_init_irq, 1238 .init_irq = r8a7740_init_irq,
1214 .handle_irq = shmobile_handle_irq_intc, 1239 .handle_irq = shmobile_handle_irq_intc,
1215 .init_machine = eva_init, 1240 .init_machine = eva_init,
1216 .init_late = shmobile_init_late, 1241 .init_late = shmobile_init_late,
1217 .timer = &shmobile_timer, 1242 .timer = &shmobile_timer,
1218 .dt_compat = eva_boards_compat_dt, 1243 .dt_compat = eva_boards_compat_dt,
1219 MACHINE_END 1244 MACHINE_END
1220 1245
arch/arm/mach-shmobile/board-marzen.c
Diff comments   View file @ 95360fd
1 /* 1 /*
2 * marzen board support 2 * marzen board support
3 * 3 *
4 * Copyright (C) 2011 Renesas Solutions Corp. 4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm 5 * Copyright (C) 2011 Magnus Damm
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License. 9 * the Free Software Foundation; version 2 of the License.
10 * 10 *
11 * This program is distributed in the hope that it will be useful, 11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 * 15 *
16 * You should have received a copy of the GNU General Public License 16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software 17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 19 */
20 20
21 #include <linux/kernel.h> 21 #include <linux/kernel.h>
22 #include <linux/init.h> 22 #include <linux/init.h>
23 #include <linux/interrupt.h> 23 #include <linux/interrupt.h>
24 #include <linux/irq.h> 24 #include <linux/irq.h>
25 #include <linux/platform_device.h> 25 #include <linux/platform_device.h>
26 #include <linux/delay.h> 26 #include <linux/delay.h>
27 #include <linux/io.h> 27 #include <linux/io.h>
28 #include <linux/gpio.h> 28 #include <linux/gpio.h>
29 #include <linux/dma-mapping.h> 29 #include <linux/dma-mapping.h>
30 #include <linux/regulator/fixed.h> 30 #include <linux/regulator/fixed.h>
31 #include <linux/regulator/machine.h> 31 #include <linux/regulator/machine.h>
32 #include <linux/smsc911x.h> 32 #include <linux/smsc911x.h>
33 #include <linux/mmc/sh_mobile_sdhi.h>
34 #include <linux/mfd/tmio.h>
33 #include <mach/hardware.h> 35 #include <mach/hardware.h>
34 #include <mach/r8a7779.h> 36 #include <mach/r8a7779.h>
35 #include <mach/common.h> 37 #include <mach/common.h>
36 #include <mach/irqs.h> 38 #include <mach/irqs.h>
37 #include <asm/mach-types.h> 39 #include <asm/mach-types.h>
38 #include <asm/mach/arch.h> 40 #include <asm/mach/arch.h>
39 #include <asm/hardware/gic.h> 41 #include <asm/hardware/gic.h>
40 #include <asm/traps.h> 42 #include <asm/traps.h>
41 43
44 /* Fixed 3.3V regulator to be used by SDHI0 */
45 static struct regulator_consumer_supply fixed3v3_power_consumers[] = {
46 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
47 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
48 };
49
42 /* Dummy supplies, where voltage doesn't matter */ 50 /* Dummy supplies, where voltage doesn't matter */
43 static struct regulator_consumer_supply dummy_supplies[] = { 51 static struct regulator_consumer_supply dummy_supplies[] = {
44 REGULATOR_SUPPLY("vddvario", "smsc911x"), 52 REGULATOR_SUPPLY("vddvario", "smsc911x"),
45 REGULATOR_SUPPLY("vdd33a", "smsc911x"), 53 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
46 }; 54 };
47 55
48 /* SMSC LAN89218 */ 56 /* SMSC LAN89218 */
49 static struct resource smsc911x_resources[] = { 57 static struct resource smsc911x_resources[] = {
50 [0] = { 58 [0] = {
51 .start = 0x18000000, /* ExCS0 */ 59 .start = 0x18000000, /* ExCS0 */
52 .end = 0x180000ff, /* A1->A7 */ 60 .end = 0x180000ff, /* A1->A7 */
53 .flags = IORESOURCE_MEM, 61 .flags = IORESOURCE_MEM,
54 }, 62 },
55 [1] = { 63 [1] = {
56 .start = gic_spi(28), /* IRQ 1 */ 64 .start = gic_spi(28), /* IRQ 1 */
57 .flags = IORESOURCE_IRQ, 65 .flags = IORESOURCE_IRQ,
58 }, 66 },
59 }; 67 };
60 68
61 static struct smsc911x_platform_config smsc911x_platdata = { 69 static struct smsc911x_platform_config smsc911x_platdata = {
62 .flags = SMSC911X_USE_32BIT, /* 32-bit SW on 16-bit HW bus */ 70 .flags = SMSC911X_USE_32BIT, /* 32-bit SW on 16-bit HW bus */
63 .phy_interface = PHY_INTERFACE_MODE_MII, 71 .phy_interface = PHY_INTERFACE_MODE_MII,
64 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, 72 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
65 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, 73 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
66 }; 74 };
67 75
68 static struct platform_device eth_device = { 76 static struct platform_device eth_device = {
69 .name = "smsc911x", 77 .name = "smsc911x",
70 .id = -1, 78 .id = -1,
71 .dev = { 79 .dev = {
72 .platform_data = &smsc911x_platdata, 80 .platform_data = &smsc911x_platdata,
73 }, 81 },
74 .resource = smsc911x_resources, 82 .resource = smsc911x_resources,
75 .num_resources = ARRAY_SIZE(smsc911x_resources), 83 .num_resources = ARRAY_SIZE(smsc911x_resources),
76 }; 84 };
77 85
86 static struct resource sdhi0_resources[] = {
87 [0] = {
88 .name = "sdhi0",
89 .start = 0xffe4c000,
90 .end = 0xffe4c0ff,
91 .flags = IORESOURCE_MEM,
92 },
93 [1] = {
94 .start = gic_spi(104),
95 .flags = IORESOURCE_IRQ,
96 },
97 };
98
99 static struct sh_mobile_sdhi_info sdhi0_platform_data = {
100 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT,
101 .tmio_caps = MMC_CAP_SD_HIGHSPEED,
102 };
103
104 static struct platform_device sdhi0_device = {
105 .name = "sh_mobile_sdhi",
106 .num_resources = ARRAY_SIZE(sdhi0_resources),
107 .resource = sdhi0_resources,
108 .id = 0,
109 .dev = {
110 .platform_data = &sdhi0_platform_data,
111 }
112 };
113
114 /* Thermal */
115 static struct resource thermal_resources[] = {
116 [0] = {
117 .start = 0xFFC48000,
118 .end = 0xFFC48038 - 1,
119 .flags = IORESOURCE_MEM,
120 },
121 };
122
123 static struct platform_device thermal_device = {
124 .name = "rcar_thermal",
125 .resource = thermal_resources,
126 .num_resources = ARRAY_SIZE(thermal_resources),
127 };
128
78 static struct platform_device *marzen_devices[] __initdata = { 129 static struct platform_device *marzen_devices[] __initdata = {
79 &eth_device, 130 &eth_device,
131 &sdhi0_device,
132 &thermal_device,
80 }; 133 };
81 134
82 static void __init marzen_init(void) 135 static void __init marzen_init(void)
83 { 136 {
84 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); 137 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
138 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
139 regulator_register_fixed(1, dummy_supplies,
140 ARRAY_SIZE(dummy_supplies));
85 141
86 r8a7779_pinmux_init(); 142 r8a7779_pinmux_init();
87 143
88 /* SCIF2 (CN18: DEBUG0) */ 144 /* SCIF2 (CN18: DEBUG0) */
89 gpio_request(GPIO_FN_TX2_C, NULL); 145 gpio_request(GPIO_FN_TX2_C, NULL);
90 gpio_request(GPIO_FN_RX2_C, NULL); 146 gpio_request(GPIO_FN_RX2_C, NULL);
91 147
92 /* SCIF4 (CN19: DEBUG1) */ 148 /* SCIF4 (CN19: DEBUG1) */
93 gpio_request(GPIO_FN_TX4, NULL); 149 gpio_request(GPIO_FN_TX4, NULL);
94 gpio_request(GPIO_FN_RX4, NULL); 150 gpio_request(GPIO_FN_RX4, NULL);
95 151
96 /* LAN89218 */ 152 /* LAN89218 */
97 gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */ 153 gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */
98 gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */ 154 gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */
155
156 /* SD0 (CN20) */
157 gpio_request(GPIO_FN_SD0_CLK, NULL);
158 gpio_request(GPIO_FN_SD0_CMD, NULL);
159 gpio_request(GPIO_FN_SD0_DAT0, NULL);
160 gpio_request(GPIO_FN_SD0_DAT1, NULL);
161 gpio_request(GPIO_FN_SD0_DAT2, NULL);
162 gpio_request(GPIO_FN_SD0_DAT3, NULL);
163 gpio_request(GPIO_FN_SD0_CD, NULL);
164 gpio_request(GPIO_FN_SD0_WP, NULL);
99 165
100 r8a7779_add_standard_devices(); 166 r8a7779_add_standard_devices();
101 platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices)); 167 platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
102 } 168 }
103 169
104 MACHINE_START(MARZEN, "marzen") 170 MACHINE_START(MARZEN, "marzen")
105 .map_io = r8a7779_map_io, 171 .map_io = r8a7779_map_io,
106 .init_early = r8a7779_add_early_devices, 172 .init_early = r8a7779_add_early_devices,
107 .nr_irqs = NR_IRQS_LEGACY, 173 .nr_irqs = NR_IRQS_LEGACY,
108 .init_irq = r8a7779_init_irq, 174 .init_irq = r8a7779_init_irq,
109 .handle_irq = gic_handle_irq, 175 .handle_irq = gic_handle_irq,
110 .init_machine = marzen_init, 176 .init_machine = marzen_init,
111 .init_late = shmobile_init_late, 177 .init_late = shmobile_init_late,
112 .timer = &shmobile_timer, 178 .timer = &shmobile_timer,
113 MACHINE_END 179 MACHINE_END
114 180