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Commit 966dc736b819999cd2d3a6408d47d33b579f7d56

Authored by Thomas Gleixner
1 parent af80b0fed6
Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch imx_3.14.28_1.0.0_ga

genirq: Generic chip: Cache per irq bit mask 

Cache the per irq bit mask instead of recalculating it over and over.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Russell King - ARM Linux <linux@arm.linux.org.uk>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Jean-Francois Moine <moinejf@free.fr>
Cc: devicetree-discuss@lists.ozlabs.org
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Gerlando Falauto <gerlando.falauto@keymile.com>
Cc: Rob Landley <rob@landley.net>
Acked-by: Grant Likely <grant.likely@linaro.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: http://lkml.kernel.org/r/20130506142539.227119865@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

Showing 2 changed files with 18 additions and 9 deletions Inline Diff

1 #ifndef _LINUX_IRQ_H 1 #ifndef _LINUX_IRQ_H
2 #define _LINUX_IRQ_H 2 #define _LINUX_IRQ_H
3 3
4 /* 4 /*
5 * Please do not include this file in generic code. There is currently 5 * Please do not include this file in generic code. There is currently
6 * no requirement for any architecture to implement anything held 6 * no requirement for any architecture to implement anything held
7 * within this file. 7 * within this file.
8 * 8 *
9 * Thanks. --rmk 9 * Thanks. --rmk
10 */ 10 */
11 11
12 #include <linux/smp.h> 12 #include <linux/smp.h>
13 #include <linux/linkage.h> 13 #include <linux/linkage.h>
14 #include <linux/cache.h> 14 #include <linux/cache.h>
15 #include <linux/spinlock.h> 15 #include <linux/spinlock.h>
16 #include <linux/cpumask.h> 16 #include <linux/cpumask.h>
17 #include <linux/gfp.h> 17 #include <linux/gfp.h>
18 #include <linux/irqreturn.h> 18 #include <linux/irqreturn.h>
19 #include <linux/irqnr.h> 19 #include <linux/irqnr.h>
20 #include <linux/errno.h> 20 #include <linux/errno.h>
21 #include <linux/topology.h> 21 #include <linux/topology.h>
22 #include <linux/wait.h> 22 #include <linux/wait.h>
23 23
24 #include <asm/irq.h> 24 #include <asm/irq.h>
25 #include <asm/ptrace.h> 25 #include <asm/ptrace.h>
26 #include <asm/irq_regs.h> 26 #include <asm/irq_regs.h>
27 27
28 struct seq_file; 28 struct seq_file;
29 struct module; 29 struct module;
30 struct irq_desc; 30 struct irq_desc;
31 struct irq_data; 31 struct irq_data;
32 typedef void (*irq_flow_handler_t)(unsigned int irq, 32 typedef void (*irq_flow_handler_t)(unsigned int irq,
33 struct irq_desc *desc); 33 struct irq_desc *desc);
34 typedef void (*irq_preflow_handler_t)(struct irq_data *data); 34 typedef void (*irq_preflow_handler_t)(struct irq_data *data);
35 35
36 /* 36 /*
37 * IRQ line status. 37 * IRQ line status.
38 * 38 *
39 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h 39 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
40 * 40 *
41 * IRQ_TYPE_NONE - default, unspecified type 41 * IRQ_TYPE_NONE - default, unspecified type
42 * IRQ_TYPE_EDGE_RISING - rising edge triggered 42 * IRQ_TYPE_EDGE_RISING - rising edge triggered
43 * IRQ_TYPE_EDGE_FALLING - falling edge triggered 43 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
44 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered 44 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
45 * IRQ_TYPE_LEVEL_HIGH - high level triggered 45 * IRQ_TYPE_LEVEL_HIGH - high level triggered
46 * IRQ_TYPE_LEVEL_LOW - low level triggered 46 * IRQ_TYPE_LEVEL_LOW - low level triggered
47 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits 47 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
48 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits 48 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
49 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type 49 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
50 * to setup the HW to a sane default (used 50 * to setup the HW to a sane default (used
51 * by irqdomain map() callbacks to synchronize 51 * by irqdomain map() callbacks to synchronize
52 * the HW state and SW flags for a newly 52 * the HW state and SW flags for a newly
53 * allocated descriptor). 53 * allocated descriptor).
54 * 54 *
55 * IRQ_TYPE_PROBE - Special flag for probing in progress 55 * IRQ_TYPE_PROBE - Special flag for probing in progress
56 * 56 *
57 * Bits which can be modified via irq_set/clear/modify_status_flags() 57 * Bits which can be modified via irq_set/clear/modify_status_flags()
58 * IRQ_LEVEL - Interrupt is level type. Will be also 58 * IRQ_LEVEL - Interrupt is level type. Will be also
59 * updated in the code when the above trigger 59 * updated in the code when the above trigger
60 * bits are modified via irq_set_irq_type() 60 * bits are modified via irq_set_irq_type()
61 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect 61 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
62 * it from affinity setting 62 * it from affinity setting
63 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing 63 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
64 * IRQ_NOREQUEST - Interrupt cannot be requested via 64 * IRQ_NOREQUEST - Interrupt cannot be requested via
65 * request_irq() 65 * request_irq()
66 * IRQ_NOTHREAD - Interrupt cannot be threaded 66 * IRQ_NOTHREAD - Interrupt cannot be threaded
67 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in 67 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
68 * request/setup_irq() 68 * request/setup_irq()
69 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) 69 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
70 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context 70 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
71 * IRQ_NESTED_TRHEAD - Interrupt nests into another thread 71 * IRQ_NESTED_TRHEAD - Interrupt nests into another thread
72 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable 72 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
73 */ 73 */
74 enum { 74 enum {
75 IRQ_TYPE_NONE = 0x00000000, 75 IRQ_TYPE_NONE = 0x00000000,
76 IRQ_TYPE_EDGE_RISING = 0x00000001, 76 IRQ_TYPE_EDGE_RISING = 0x00000001,
77 IRQ_TYPE_EDGE_FALLING = 0x00000002, 77 IRQ_TYPE_EDGE_FALLING = 0x00000002,
78 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), 78 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
79 IRQ_TYPE_LEVEL_HIGH = 0x00000004, 79 IRQ_TYPE_LEVEL_HIGH = 0x00000004,
80 IRQ_TYPE_LEVEL_LOW = 0x00000008, 80 IRQ_TYPE_LEVEL_LOW = 0x00000008,
81 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), 81 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
82 IRQ_TYPE_SENSE_MASK = 0x0000000f, 82 IRQ_TYPE_SENSE_MASK = 0x0000000f,
83 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK, 83 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK,
84 84
85 IRQ_TYPE_PROBE = 0x00000010, 85 IRQ_TYPE_PROBE = 0x00000010,
86 86
87 IRQ_LEVEL = (1 << 8), 87 IRQ_LEVEL = (1 << 8),
88 IRQ_PER_CPU = (1 << 9), 88 IRQ_PER_CPU = (1 << 9),
89 IRQ_NOPROBE = (1 << 10), 89 IRQ_NOPROBE = (1 << 10),
90 IRQ_NOREQUEST = (1 << 11), 90 IRQ_NOREQUEST = (1 << 11),
91 IRQ_NOAUTOEN = (1 << 12), 91 IRQ_NOAUTOEN = (1 << 12),
92 IRQ_NO_BALANCING = (1 << 13), 92 IRQ_NO_BALANCING = (1 << 13),
93 IRQ_MOVE_PCNTXT = (1 << 14), 93 IRQ_MOVE_PCNTXT = (1 << 14),
94 IRQ_NESTED_THREAD = (1 << 15), 94 IRQ_NESTED_THREAD = (1 << 15),
95 IRQ_NOTHREAD = (1 << 16), 95 IRQ_NOTHREAD = (1 << 16),
96 IRQ_PER_CPU_DEVID = (1 << 17), 96 IRQ_PER_CPU_DEVID = (1 << 17),
97 }; 97 };
98 98
99 #define IRQF_MODIFY_MASK \ 99 #define IRQF_MODIFY_MASK \
100 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ 100 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
101 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ 101 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
102 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID) 102 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID)
103 103
104 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) 104 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
105 105
106 /* 106 /*
107 * Return value for chip->irq_set_affinity() 107 * Return value for chip->irq_set_affinity()
108 * 108 *
109 * IRQ_SET_MASK_OK - OK, core updates irq_data.affinity 109 * IRQ_SET_MASK_OK - OK, core updates irq_data.affinity
110 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity 110 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity
111 */ 111 */
112 enum { 112 enum {
113 IRQ_SET_MASK_OK = 0, 113 IRQ_SET_MASK_OK = 0,
114 IRQ_SET_MASK_OK_NOCOPY, 114 IRQ_SET_MASK_OK_NOCOPY,
115 }; 115 };
116 116
117 struct msi_desc; 117 struct msi_desc;
118 struct irq_domain; 118 struct irq_domain;
119 119
120 /** 120 /**
121 * struct irq_data - per irq and irq chip data passed down to chip functions 121 * struct irq_data - per irq and irq chip data passed down to chip functions
122 * @mask: precomputed bitmask for accessing the chip registers
122 * @irq: interrupt number 123 * @irq: interrupt number
123 * @hwirq: hardware interrupt number, local to the interrupt domain 124 * @hwirq: hardware interrupt number, local to the interrupt domain
124 * @node: node index useful for balancing 125 * @node: node index useful for balancing
125 * @state_use_accessors: status information for irq chip functions. 126 * @state_use_accessors: status information for irq chip functions.
126 * Use accessor functions to deal with it 127 * Use accessor functions to deal with it
127 * @chip: low level interrupt hardware access 128 * @chip: low level interrupt hardware access
128 * @domain: Interrupt translation domain; responsible for mapping 129 * @domain: Interrupt translation domain; responsible for mapping
129 * between hwirq number and linux irq number. 130 * between hwirq number and linux irq number.
130 * @handler_data: per-IRQ data for the irq_chip methods 131 * @handler_data: per-IRQ data for the irq_chip methods
131 * @chip_data: platform-specific per-chip private data for the chip 132 * @chip_data: platform-specific per-chip private data for the chip
132 * methods, to allow shared chip implementations 133 * methods, to allow shared chip implementations
133 * @msi_desc: MSI descriptor 134 * @msi_desc: MSI descriptor
134 * @affinity: IRQ affinity on SMP 135 * @affinity: IRQ affinity on SMP
135 * 136 *
136 * The fields here need to overlay the ones in irq_desc until we 137 * The fields here need to overlay the ones in irq_desc until we
137 * cleaned up the direct references and switched everything over to 138 * cleaned up the direct references and switched everything over to
138 * irq_data. 139 * irq_data.
139 */ 140 */
140 struct irq_data { 141 struct irq_data {
142 u32 mask;
141 unsigned int irq; 143 unsigned int irq;
142 unsigned long hwirq; 144 unsigned long hwirq;
143 unsigned int node; 145 unsigned int node;
144 unsigned int state_use_accessors; 146 unsigned int state_use_accessors;
145 struct irq_chip *chip; 147 struct irq_chip *chip;
146 struct irq_domain *domain; 148 struct irq_domain *domain;
147 void *handler_data; 149 void *handler_data;
148 void *chip_data; 150 void *chip_data;
149 struct msi_desc *msi_desc; 151 struct msi_desc *msi_desc;
150 cpumask_var_t affinity; 152 cpumask_var_t affinity;
151 }; 153 };
152 154
153 /* 155 /*
154 * Bit masks for irq_data.state 156 * Bit masks for irq_data.state
155 * 157 *
156 * IRQD_TRIGGER_MASK - Mask for the trigger type bits 158 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
157 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending 159 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
158 * IRQD_NO_BALANCING - Balancing disabled for this IRQ 160 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
159 * IRQD_PER_CPU - Interrupt is per cpu 161 * IRQD_PER_CPU - Interrupt is per cpu
160 * IRQD_AFFINITY_SET - Interrupt affinity was set 162 * IRQD_AFFINITY_SET - Interrupt affinity was set
161 * IRQD_LEVEL - Interrupt is level triggered 163 * IRQD_LEVEL - Interrupt is level triggered
162 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup 164 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
163 * from suspend 165 * from suspend
164 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process 166 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process
165 * context 167 * context
166 * IRQD_IRQ_DISABLED - Disabled state of the interrupt 168 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
167 * IRQD_IRQ_MASKED - Masked state of the interrupt 169 * IRQD_IRQ_MASKED - Masked state of the interrupt
168 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt 170 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
169 */ 171 */
170 enum { 172 enum {
171 IRQD_TRIGGER_MASK = 0xf, 173 IRQD_TRIGGER_MASK = 0xf,
172 IRQD_SETAFFINITY_PENDING = (1 << 8), 174 IRQD_SETAFFINITY_PENDING = (1 << 8),
173 IRQD_NO_BALANCING = (1 << 10), 175 IRQD_NO_BALANCING = (1 << 10),
174 IRQD_PER_CPU = (1 << 11), 176 IRQD_PER_CPU = (1 << 11),
175 IRQD_AFFINITY_SET = (1 << 12), 177 IRQD_AFFINITY_SET = (1 << 12),
176 IRQD_LEVEL = (1 << 13), 178 IRQD_LEVEL = (1 << 13),
177 IRQD_WAKEUP_STATE = (1 << 14), 179 IRQD_WAKEUP_STATE = (1 << 14),
178 IRQD_MOVE_PCNTXT = (1 << 15), 180 IRQD_MOVE_PCNTXT = (1 << 15),
179 IRQD_IRQ_DISABLED = (1 << 16), 181 IRQD_IRQ_DISABLED = (1 << 16),
180 IRQD_IRQ_MASKED = (1 << 17), 182 IRQD_IRQ_MASKED = (1 << 17),
181 IRQD_IRQ_INPROGRESS = (1 << 18), 183 IRQD_IRQ_INPROGRESS = (1 << 18),
182 }; 184 };
183 185
184 static inline bool irqd_is_setaffinity_pending(struct irq_data *d) 186 static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
185 { 187 {
186 return d->state_use_accessors & IRQD_SETAFFINITY_PENDING; 188 return d->state_use_accessors & IRQD_SETAFFINITY_PENDING;
187 } 189 }
188 190
189 static inline bool irqd_is_per_cpu(struct irq_data *d) 191 static inline bool irqd_is_per_cpu(struct irq_data *d)
190 { 192 {
191 return d->state_use_accessors & IRQD_PER_CPU; 193 return d->state_use_accessors & IRQD_PER_CPU;
192 } 194 }
193 195
194 static inline bool irqd_can_balance(struct irq_data *d) 196 static inline bool irqd_can_balance(struct irq_data *d)
195 { 197 {
196 return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING)); 198 return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING));
197 } 199 }
198 200
199 static inline bool irqd_affinity_was_set(struct irq_data *d) 201 static inline bool irqd_affinity_was_set(struct irq_data *d)
200 { 202 {
201 return d->state_use_accessors & IRQD_AFFINITY_SET; 203 return d->state_use_accessors & IRQD_AFFINITY_SET;
202 } 204 }
203 205
204 static inline void irqd_mark_affinity_was_set(struct irq_data *d) 206 static inline void irqd_mark_affinity_was_set(struct irq_data *d)
205 { 207 {
206 d->state_use_accessors |= IRQD_AFFINITY_SET; 208 d->state_use_accessors |= IRQD_AFFINITY_SET;
207 } 209 }
208 210
209 static inline u32 irqd_get_trigger_type(struct irq_data *d) 211 static inline u32 irqd_get_trigger_type(struct irq_data *d)
210 { 212 {
211 return d->state_use_accessors & IRQD_TRIGGER_MASK; 213 return d->state_use_accessors & IRQD_TRIGGER_MASK;
212 } 214 }
213 215
214 /* 216 /*
215 * Must only be called inside irq_chip.irq_set_type() functions. 217 * Must only be called inside irq_chip.irq_set_type() functions.
216 */ 218 */
217 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) 219 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
218 { 220 {
219 d->state_use_accessors &= ~IRQD_TRIGGER_MASK; 221 d->state_use_accessors &= ~IRQD_TRIGGER_MASK;
220 d->state_use_accessors |= type & IRQD_TRIGGER_MASK; 222 d->state_use_accessors |= type & IRQD_TRIGGER_MASK;
221 } 223 }
222 224
223 static inline bool irqd_is_level_type(struct irq_data *d) 225 static inline bool irqd_is_level_type(struct irq_data *d)
224 { 226 {
225 return d->state_use_accessors & IRQD_LEVEL; 227 return d->state_use_accessors & IRQD_LEVEL;
226 } 228 }
227 229
228 static inline bool irqd_is_wakeup_set(struct irq_data *d) 230 static inline bool irqd_is_wakeup_set(struct irq_data *d)
229 { 231 {
230 return d->state_use_accessors & IRQD_WAKEUP_STATE; 232 return d->state_use_accessors & IRQD_WAKEUP_STATE;
231 } 233 }
232 234
233 static inline bool irqd_can_move_in_process_context(struct irq_data *d) 235 static inline bool irqd_can_move_in_process_context(struct irq_data *d)
234 { 236 {
235 return d->state_use_accessors & IRQD_MOVE_PCNTXT; 237 return d->state_use_accessors & IRQD_MOVE_PCNTXT;
236 } 238 }
237 239
238 static inline bool irqd_irq_disabled(struct irq_data *d) 240 static inline bool irqd_irq_disabled(struct irq_data *d)
239 { 241 {
240 return d->state_use_accessors & IRQD_IRQ_DISABLED; 242 return d->state_use_accessors & IRQD_IRQ_DISABLED;
241 } 243 }
242 244
243 static inline bool irqd_irq_masked(struct irq_data *d) 245 static inline bool irqd_irq_masked(struct irq_data *d)
244 { 246 {
245 return d->state_use_accessors & IRQD_IRQ_MASKED; 247 return d->state_use_accessors & IRQD_IRQ_MASKED;
246 } 248 }
247 249
248 static inline bool irqd_irq_inprogress(struct irq_data *d) 250 static inline bool irqd_irq_inprogress(struct irq_data *d)
249 { 251 {
250 return d->state_use_accessors & IRQD_IRQ_INPROGRESS; 252 return d->state_use_accessors & IRQD_IRQ_INPROGRESS;
251 } 253 }
252 254
253 /* 255 /*
254 * Functions for chained handlers which can be enabled/disabled by the 256 * Functions for chained handlers which can be enabled/disabled by the
255 * standard disable_irq/enable_irq calls. Must be called with 257 * standard disable_irq/enable_irq calls. Must be called with
256 * irq_desc->lock held. 258 * irq_desc->lock held.
257 */ 259 */
258 static inline void irqd_set_chained_irq_inprogress(struct irq_data *d) 260 static inline void irqd_set_chained_irq_inprogress(struct irq_data *d)
259 { 261 {
260 d->state_use_accessors |= IRQD_IRQ_INPROGRESS; 262 d->state_use_accessors |= IRQD_IRQ_INPROGRESS;
261 } 263 }
262 264
263 static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d) 265 static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d)
264 { 266 {
265 d->state_use_accessors &= ~IRQD_IRQ_INPROGRESS; 267 d->state_use_accessors &= ~IRQD_IRQ_INPROGRESS;
266 } 268 }
267 269
268 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) 270 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
269 { 271 {
270 return d->hwirq; 272 return d->hwirq;
271 } 273 }
272 274
273 /** 275 /**
274 * struct irq_chip - hardware interrupt chip descriptor 276 * struct irq_chip - hardware interrupt chip descriptor
275 * 277 *
276 * @name: name for /proc/interrupts 278 * @name: name for /proc/interrupts
277 * @irq_startup: start up the interrupt (defaults to ->enable if NULL) 279 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
278 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) 280 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
279 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) 281 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
280 * @irq_disable: disable the interrupt 282 * @irq_disable: disable the interrupt
281 * @irq_ack: start of a new interrupt 283 * @irq_ack: start of a new interrupt
282 * @irq_mask: mask an interrupt source 284 * @irq_mask: mask an interrupt source
283 * @irq_mask_ack: ack and mask an interrupt source 285 * @irq_mask_ack: ack and mask an interrupt source
284 * @irq_unmask: unmask an interrupt source 286 * @irq_unmask: unmask an interrupt source
285 * @irq_eoi: end of interrupt 287 * @irq_eoi: end of interrupt
286 * @irq_set_affinity: set the CPU affinity on SMP machines 288 * @irq_set_affinity: set the CPU affinity on SMP machines
287 * @irq_retrigger: resend an IRQ to the CPU 289 * @irq_retrigger: resend an IRQ to the CPU
288 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ 290 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
289 * @irq_set_wake: enable/disable power-management wake-on of an IRQ 291 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
290 * @irq_bus_lock: function to lock access to slow bus (i2c) chips 292 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
291 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips 293 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
292 * @irq_cpu_online: configure an interrupt source for a secondary CPU 294 * @irq_cpu_online: configure an interrupt source for a secondary CPU
293 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU 295 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
294 * @irq_suspend: function called from core code on suspend once per chip 296 * @irq_suspend: function called from core code on suspend once per chip
295 * @irq_resume: function called from core code on resume once per chip 297 * @irq_resume: function called from core code on resume once per chip
296 * @irq_pm_shutdown: function called from core code on shutdown once per chip 298 * @irq_pm_shutdown: function called from core code on shutdown once per chip
297 * @irq_print_chip: optional to print special chip info in show_interrupts 299 * @irq_print_chip: optional to print special chip info in show_interrupts
298 * @flags: chip specific flags 300 * @flags: chip specific flags
299 */ 301 */
300 struct irq_chip { 302 struct irq_chip {
301 const char *name; 303 const char *name;
302 unsigned int (*irq_startup)(struct irq_data *data); 304 unsigned int (*irq_startup)(struct irq_data *data);
303 void (*irq_shutdown)(struct irq_data *data); 305 void (*irq_shutdown)(struct irq_data *data);
304 void (*irq_enable)(struct irq_data *data); 306 void (*irq_enable)(struct irq_data *data);
305 void (*irq_disable)(struct irq_data *data); 307 void (*irq_disable)(struct irq_data *data);
306 308
307 void (*irq_ack)(struct irq_data *data); 309 void (*irq_ack)(struct irq_data *data);
308 void (*irq_mask)(struct irq_data *data); 310 void (*irq_mask)(struct irq_data *data);
309 void (*irq_mask_ack)(struct irq_data *data); 311 void (*irq_mask_ack)(struct irq_data *data);
310 void (*irq_unmask)(struct irq_data *data); 312 void (*irq_unmask)(struct irq_data *data);
311 void (*irq_eoi)(struct irq_data *data); 313 void (*irq_eoi)(struct irq_data *data);
312 314
313 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); 315 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
314 int (*irq_retrigger)(struct irq_data *data); 316 int (*irq_retrigger)(struct irq_data *data);
315 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); 317 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
316 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 318 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
317 319
318 void (*irq_bus_lock)(struct irq_data *data); 320 void (*irq_bus_lock)(struct irq_data *data);
319 void (*irq_bus_sync_unlock)(struct irq_data *data); 321 void (*irq_bus_sync_unlock)(struct irq_data *data);
320 322
321 void (*irq_cpu_online)(struct irq_data *data); 323 void (*irq_cpu_online)(struct irq_data *data);
322 void (*irq_cpu_offline)(struct irq_data *data); 324 void (*irq_cpu_offline)(struct irq_data *data);
323 325
324 void (*irq_suspend)(struct irq_data *data); 326 void (*irq_suspend)(struct irq_data *data);
325 void (*irq_resume)(struct irq_data *data); 327 void (*irq_resume)(struct irq_data *data);
326 void (*irq_pm_shutdown)(struct irq_data *data); 328 void (*irq_pm_shutdown)(struct irq_data *data);
327 329
328 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); 330 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
329 331
330 unsigned long flags; 332 unsigned long flags;
331 }; 333 };
332 334
333 /* 335 /*
334 * irq_chip specific flags 336 * irq_chip specific flags
335 * 337 *
336 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() 338 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
337 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled 339 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
338 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path 340 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
339 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks 341 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
340 * when irq enabled 342 * when irq enabled
341 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip 343 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
342 */ 344 */
343 enum { 345 enum {
344 IRQCHIP_SET_TYPE_MASKED = (1 << 0), 346 IRQCHIP_SET_TYPE_MASKED = (1 << 0),
345 IRQCHIP_EOI_IF_HANDLED = (1 << 1), 347 IRQCHIP_EOI_IF_HANDLED = (1 << 1),
346 IRQCHIP_MASK_ON_SUSPEND = (1 << 2), 348 IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
347 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), 349 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
348 IRQCHIP_SKIP_SET_WAKE = (1 << 4), 350 IRQCHIP_SKIP_SET_WAKE = (1 << 4),
349 IRQCHIP_ONESHOT_SAFE = (1 << 5), 351 IRQCHIP_ONESHOT_SAFE = (1 << 5),
350 }; 352 };
351 353
352 /* This include will go away once we isolated irq_desc usage to core code */ 354 /* This include will go away once we isolated irq_desc usage to core code */
353 #include <linux/irqdesc.h> 355 #include <linux/irqdesc.h>
354 356
355 /* 357 /*
356 * Pick up the arch-dependent methods: 358 * Pick up the arch-dependent methods:
357 */ 359 */
358 #include <asm/hw_irq.h> 360 #include <asm/hw_irq.h>
359 361
360 #ifndef NR_IRQS_LEGACY 362 #ifndef NR_IRQS_LEGACY
361 # define NR_IRQS_LEGACY 0 363 # define NR_IRQS_LEGACY 0
362 #endif 364 #endif
363 365
364 #ifndef ARCH_IRQ_INIT_FLAGS 366 #ifndef ARCH_IRQ_INIT_FLAGS
365 # define ARCH_IRQ_INIT_FLAGS 0 367 # define ARCH_IRQ_INIT_FLAGS 0
366 #endif 368 #endif
367 369
368 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS 370 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
369 371
370 struct irqaction; 372 struct irqaction;
371 extern int setup_irq(unsigned int irq, struct irqaction *new); 373 extern int setup_irq(unsigned int irq, struct irqaction *new);
372 extern void remove_irq(unsigned int irq, struct irqaction *act); 374 extern void remove_irq(unsigned int irq, struct irqaction *act);
373 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new); 375 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
374 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act); 376 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
375 377
376 extern void irq_cpu_online(void); 378 extern void irq_cpu_online(void);
377 extern void irq_cpu_offline(void); 379 extern void irq_cpu_offline(void);
378 extern int __irq_set_affinity_locked(struct irq_data *data, const struct cpumask *cpumask); 380 extern int __irq_set_affinity_locked(struct irq_data *data, const struct cpumask *cpumask);
379 381
380 #ifdef CONFIG_GENERIC_HARDIRQS 382 #ifdef CONFIG_GENERIC_HARDIRQS
381 383
382 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) 384 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
383 void irq_move_irq(struct irq_data *data); 385 void irq_move_irq(struct irq_data *data);
384 void irq_move_masked_irq(struct irq_data *data); 386 void irq_move_masked_irq(struct irq_data *data);
385 #else 387 #else
386 static inline void irq_move_irq(struct irq_data *data) { } 388 static inline void irq_move_irq(struct irq_data *data) { }
387 static inline void irq_move_masked_irq(struct irq_data *data) { } 389 static inline void irq_move_masked_irq(struct irq_data *data) { }
388 #endif 390 #endif
389 391
390 extern int no_irq_affinity; 392 extern int no_irq_affinity;
391 393
392 #ifdef CONFIG_HARDIRQS_SW_RESEND 394 #ifdef CONFIG_HARDIRQS_SW_RESEND
393 int irq_set_parent(int irq, int parent_irq); 395 int irq_set_parent(int irq, int parent_irq);
394 #else 396 #else
395 static inline int irq_set_parent(int irq, int parent_irq) 397 static inline int irq_set_parent(int irq, int parent_irq)
396 { 398 {
397 return 0; 399 return 0;
398 } 400 }
399 #endif 401 #endif
400 402
401 /* 403 /*
402 * Built-in IRQ handlers for various IRQ types, 404 * Built-in IRQ handlers for various IRQ types,
403 * callable via desc->handle_irq() 405 * callable via desc->handle_irq()
404 */ 406 */
405 extern void handle_level_irq(unsigned int irq, struct irq_desc *desc); 407 extern void handle_level_irq(unsigned int irq, struct irq_desc *desc);
406 extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc); 408 extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
407 extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc); 409 extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc);
408 extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc); 410 extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc);
409 extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc); 411 extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc);
410 extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc); 412 extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
411 extern void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc); 413 extern void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc);
412 extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc); 414 extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);
413 extern void handle_nested_irq(unsigned int irq); 415 extern void handle_nested_irq(unsigned int irq);
414 416
415 /* Handling of unhandled and spurious interrupts: */ 417 /* Handling of unhandled and spurious interrupts: */
416 extern void note_interrupt(unsigned int irq, struct irq_desc *desc, 418 extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
417 irqreturn_t action_ret); 419 irqreturn_t action_ret);
418 420
419 421
420 /* Enable/disable irq debugging output: */ 422 /* Enable/disable irq debugging output: */
421 extern int noirqdebug_setup(char *str); 423 extern int noirqdebug_setup(char *str);
422 424
423 /* Checks whether the interrupt can be requested by request_irq(): */ 425 /* Checks whether the interrupt can be requested by request_irq(): */
424 extern int can_request_irq(unsigned int irq, unsigned long irqflags); 426 extern int can_request_irq(unsigned int irq, unsigned long irqflags);
425 427
426 /* Dummy irq-chip implementations: */ 428 /* Dummy irq-chip implementations: */
427 extern struct irq_chip no_irq_chip; 429 extern struct irq_chip no_irq_chip;
428 extern struct irq_chip dummy_irq_chip; 430 extern struct irq_chip dummy_irq_chip;
429 431
430 extern void 432 extern void
431 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, 433 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
432 irq_flow_handler_t handle, const char *name); 434 irq_flow_handler_t handle, const char *name);
433 435
434 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, 436 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
435 irq_flow_handler_t handle) 437 irq_flow_handler_t handle)
436 { 438 {
437 irq_set_chip_and_handler_name(irq, chip, handle, NULL); 439 irq_set_chip_and_handler_name(irq, chip, handle, NULL);
438 } 440 }
439 441
440 extern int irq_set_percpu_devid(unsigned int irq); 442 extern int irq_set_percpu_devid(unsigned int irq);
441 443
442 extern void 444 extern void
443 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, 445 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
444 const char *name); 446 const char *name);
445 447
446 static inline void 448 static inline void
447 irq_set_handler(unsigned int irq, irq_flow_handler_t handle) 449 irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
448 { 450 {
449 __irq_set_handler(irq, handle, 0, NULL); 451 __irq_set_handler(irq, handle, 0, NULL);
450 } 452 }
451 453
452 /* 454 /*
453 * Set a highlevel chained flow handler for a given IRQ. 455 * Set a highlevel chained flow handler for a given IRQ.
454 * (a chained handler is automatically enabled and set to 456 * (a chained handler is automatically enabled and set to
455 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 457 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
456 */ 458 */
457 static inline void 459 static inline void
458 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) 460 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
459 { 461 {
460 __irq_set_handler(irq, handle, 1, NULL); 462 __irq_set_handler(irq, handle, 1, NULL);
461 } 463 }
462 464
463 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); 465 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
464 466
465 static inline void irq_set_status_flags(unsigned int irq, unsigned long set) 467 static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
466 { 468 {
467 irq_modify_status(irq, 0, set); 469 irq_modify_status(irq, 0, set);
468 } 470 }
469 471
470 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) 472 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
471 { 473 {
472 irq_modify_status(irq, clr, 0); 474 irq_modify_status(irq, clr, 0);
473 } 475 }
474 476
475 static inline void irq_set_noprobe(unsigned int irq) 477 static inline void irq_set_noprobe(unsigned int irq)
476 { 478 {
477 irq_modify_status(irq, 0, IRQ_NOPROBE); 479 irq_modify_status(irq, 0, IRQ_NOPROBE);
478 } 480 }
479 481
480 static inline void irq_set_probe(unsigned int irq) 482 static inline void irq_set_probe(unsigned int irq)
481 { 483 {
482 irq_modify_status(irq, IRQ_NOPROBE, 0); 484 irq_modify_status(irq, IRQ_NOPROBE, 0);
483 } 485 }
484 486
485 static inline void irq_set_nothread(unsigned int irq) 487 static inline void irq_set_nothread(unsigned int irq)
486 { 488 {
487 irq_modify_status(irq, 0, IRQ_NOTHREAD); 489 irq_modify_status(irq, 0, IRQ_NOTHREAD);
488 } 490 }
489 491
490 static inline void irq_set_thread(unsigned int irq) 492 static inline void irq_set_thread(unsigned int irq)
491 { 493 {
492 irq_modify_status(irq, IRQ_NOTHREAD, 0); 494 irq_modify_status(irq, IRQ_NOTHREAD, 0);
493 } 495 }
494 496
495 static inline void irq_set_nested_thread(unsigned int irq, bool nest) 497 static inline void irq_set_nested_thread(unsigned int irq, bool nest)
496 { 498 {
497 if (nest) 499 if (nest)
498 irq_set_status_flags(irq, IRQ_NESTED_THREAD); 500 irq_set_status_flags(irq, IRQ_NESTED_THREAD);
499 else 501 else
500 irq_clear_status_flags(irq, IRQ_NESTED_THREAD); 502 irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
501 } 503 }
502 504
503 static inline void irq_set_percpu_devid_flags(unsigned int irq) 505 static inline void irq_set_percpu_devid_flags(unsigned int irq)
504 { 506 {
505 irq_set_status_flags(irq, 507 irq_set_status_flags(irq,
506 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD | 508 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
507 IRQ_NOPROBE | IRQ_PER_CPU_DEVID); 509 IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
508 } 510 }
509 511
510 /* Handle dynamic irq creation and destruction */ 512 /* Handle dynamic irq creation and destruction */
511 extern unsigned int create_irq_nr(unsigned int irq_want, int node); 513 extern unsigned int create_irq_nr(unsigned int irq_want, int node);
512 extern unsigned int __create_irqs(unsigned int from, unsigned int count, 514 extern unsigned int __create_irqs(unsigned int from, unsigned int count,
513 int node); 515 int node);
514 extern int create_irq(void); 516 extern int create_irq(void);
515 extern void destroy_irq(unsigned int irq); 517 extern void destroy_irq(unsigned int irq);
516 extern void destroy_irqs(unsigned int irq, unsigned int count); 518 extern void destroy_irqs(unsigned int irq, unsigned int count);
517 519
518 /* 520 /*
519 * Dynamic irq helper functions. Obsolete. Use irq_alloc_desc* and 521 * Dynamic irq helper functions. Obsolete. Use irq_alloc_desc* and
520 * irq_free_desc instead. 522 * irq_free_desc instead.
521 */ 523 */
522 extern void dynamic_irq_cleanup(unsigned int irq); 524 extern void dynamic_irq_cleanup(unsigned int irq);
523 static inline void dynamic_irq_init(unsigned int irq) 525 static inline void dynamic_irq_init(unsigned int irq)
524 { 526 {
525 dynamic_irq_cleanup(irq); 527 dynamic_irq_cleanup(irq);
526 } 528 }
527 529
528 /* Set/get chip/data for an IRQ: */ 530 /* Set/get chip/data for an IRQ: */
529 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); 531 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
530 extern int irq_set_handler_data(unsigned int irq, void *data); 532 extern int irq_set_handler_data(unsigned int irq, void *data);
531 extern int irq_set_chip_data(unsigned int irq, void *data); 533 extern int irq_set_chip_data(unsigned int irq, void *data);
532 extern int irq_set_irq_type(unsigned int irq, unsigned int type); 534 extern int irq_set_irq_type(unsigned int irq, unsigned int type);
533 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); 535 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
534 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, 536 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
535 struct msi_desc *entry); 537 struct msi_desc *entry);
536 extern struct irq_data *irq_get_irq_data(unsigned int irq); 538 extern struct irq_data *irq_get_irq_data(unsigned int irq);
537 539
538 static inline struct irq_chip *irq_get_chip(unsigned int irq) 540 static inline struct irq_chip *irq_get_chip(unsigned int irq)
539 { 541 {
540 struct irq_data *d = irq_get_irq_data(irq); 542 struct irq_data *d = irq_get_irq_data(irq);
541 return d ? d->chip : NULL; 543 return d ? d->chip : NULL;
542 } 544 }
543 545
544 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) 546 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
545 { 547 {
546 return d->chip; 548 return d->chip;
547 } 549 }
548 550
549 static inline void *irq_get_chip_data(unsigned int irq) 551 static inline void *irq_get_chip_data(unsigned int irq)
550 { 552 {
551 struct irq_data *d = irq_get_irq_data(irq); 553 struct irq_data *d = irq_get_irq_data(irq);
552 return d ? d->chip_data : NULL; 554 return d ? d->chip_data : NULL;
553 } 555 }
554 556
555 static inline void *irq_data_get_irq_chip_data(struct irq_data *d) 557 static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
556 { 558 {
557 return d->chip_data; 559 return d->chip_data;
558 } 560 }
559 561
560 static inline void *irq_get_handler_data(unsigned int irq) 562 static inline void *irq_get_handler_data(unsigned int irq)
561 { 563 {
562 struct irq_data *d = irq_get_irq_data(irq); 564 struct irq_data *d = irq_get_irq_data(irq);
563 return d ? d->handler_data : NULL; 565 return d ? d->handler_data : NULL;
564 } 566 }
565 567
566 static inline void *irq_data_get_irq_handler_data(struct irq_data *d) 568 static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
567 { 569 {
568 return d->handler_data; 570 return d->handler_data;
569 } 571 }
570 572
571 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) 573 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
572 { 574 {
573 struct irq_data *d = irq_get_irq_data(irq); 575 struct irq_data *d = irq_get_irq_data(irq);
574 return d ? d->msi_desc : NULL; 576 return d ? d->msi_desc : NULL;
575 } 577 }
576 578
577 static inline struct msi_desc *irq_data_get_msi(struct irq_data *d) 579 static inline struct msi_desc *irq_data_get_msi(struct irq_data *d)
578 { 580 {
579 return d->msi_desc; 581 return d->msi_desc;
580 } 582 }
581 583
582 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, 584 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
583 struct module *owner); 585 struct module *owner);
584 586
585 /* use macros to avoid needing export.h for THIS_MODULE */ 587 /* use macros to avoid needing export.h for THIS_MODULE */
586 #define irq_alloc_descs(irq, from, cnt, node) \ 588 #define irq_alloc_descs(irq, from, cnt, node) \
587 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE) 589 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE)
588 590
589 #define irq_alloc_desc(node) \ 591 #define irq_alloc_desc(node) \
590 irq_alloc_descs(-1, 0, 1, node) 592 irq_alloc_descs(-1, 0, 1, node)
591 593
592 #define irq_alloc_desc_at(at, node) \ 594 #define irq_alloc_desc_at(at, node) \
593 irq_alloc_descs(at, at, 1, node) 595 irq_alloc_descs(at, at, 1, node)
594 596
595 #define irq_alloc_desc_from(from, node) \ 597 #define irq_alloc_desc_from(from, node) \
596 irq_alloc_descs(-1, from, 1, node) 598 irq_alloc_descs(-1, from, 1, node)
597 599
598 #define irq_alloc_descs_from(from, cnt, node) \ 600 #define irq_alloc_descs_from(from, cnt, node) \
599 irq_alloc_descs(-1, from, cnt, node) 601 irq_alloc_descs(-1, from, cnt, node)
600 602
601 void irq_free_descs(unsigned int irq, unsigned int cnt); 603 void irq_free_descs(unsigned int irq, unsigned int cnt);
602 int irq_reserve_irqs(unsigned int from, unsigned int cnt); 604 int irq_reserve_irqs(unsigned int from, unsigned int cnt);
603 605
604 static inline void irq_free_desc(unsigned int irq) 606 static inline void irq_free_desc(unsigned int irq)
605 { 607 {
606 irq_free_descs(irq, 1); 608 irq_free_descs(irq, 1);
607 } 609 }
608 610
609 static inline int irq_reserve_irq(unsigned int irq) 611 static inline int irq_reserve_irq(unsigned int irq)
610 { 612 {
611 return irq_reserve_irqs(irq, 1); 613 return irq_reserve_irqs(irq, 1);
612 } 614 }
613 615
614 #ifndef irq_reg_writel 616 #ifndef irq_reg_writel
615 # define irq_reg_writel(val, addr) writel(val, addr) 617 # define irq_reg_writel(val, addr) writel(val, addr)
616 #endif 618 #endif
617 #ifndef irq_reg_readl 619 #ifndef irq_reg_readl
618 # define irq_reg_readl(addr) readl(addr) 620 # define irq_reg_readl(addr) readl(addr)
619 #endif 621 #endif
620 622
621 /** 623 /**
622 * struct irq_chip_regs - register offsets for struct irq_gci 624 * struct irq_chip_regs - register offsets for struct irq_gci
623 * @enable: Enable register offset to reg_base 625 * @enable: Enable register offset to reg_base
624 * @disable: Disable register offset to reg_base 626 * @disable: Disable register offset to reg_base
625 * @mask: Mask register offset to reg_base 627 * @mask: Mask register offset to reg_base
626 * @ack: Ack register offset to reg_base 628 * @ack: Ack register offset to reg_base
627 * @eoi: Eoi register offset to reg_base 629 * @eoi: Eoi register offset to reg_base
628 * @type: Type configuration register offset to reg_base 630 * @type: Type configuration register offset to reg_base
629 * @polarity: Polarity configuration register offset to reg_base 631 * @polarity: Polarity configuration register offset to reg_base
630 */ 632 */
631 struct irq_chip_regs { 633 struct irq_chip_regs {
632 unsigned long enable; 634 unsigned long enable;
633 unsigned long disable; 635 unsigned long disable;
634 unsigned long mask; 636 unsigned long mask;
635 unsigned long ack; 637 unsigned long ack;
636 unsigned long eoi; 638 unsigned long eoi;
637 unsigned long type; 639 unsigned long type;
638 unsigned long polarity; 640 unsigned long polarity;
639 }; 641 };
640 642
641 /** 643 /**
642 * struct irq_chip_type - Generic interrupt chip instance for a flow type 644 * struct irq_chip_type - Generic interrupt chip instance for a flow type
643 * @chip: The real interrupt chip which provides the callbacks 645 * @chip: The real interrupt chip which provides the callbacks
644 * @regs: Register offsets for this chip 646 * @regs: Register offsets for this chip
645 * @handler: Flow handler associated with this chip 647 * @handler: Flow handler associated with this chip
646 * @type: Chip can handle these flow types 648 * @type: Chip can handle these flow types
647 * @mask_cache_priv: Cached mask register private to the chip type 649 * @mask_cache_priv: Cached mask register private to the chip type
648 * @mask_cache: Pointer to cached mask register 650 * @mask_cache: Pointer to cached mask register
649 * 651 *
650 * A irq_generic_chip can have several instances of irq_chip_type when 652 * A irq_generic_chip can have several instances of irq_chip_type when
651 * it requires different functions and register offsets for different 653 * it requires different functions and register offsets for different
652 * flow types. 654 * flow types.
653 */ 655 */
654 struct irq_chip_type { 656 struct irq_chip_type {
655 struct irq_chip chip; 657 struct irq_chip chip;
656 struct irq_chip_regs regs; 658 struct irq_chip_regs regs;
657 irq_flow_handler_t handler; 659 irq_flow_handler_t handler;
658 u32 type; 660 u32 type;
659 u32 mask_cache_priv; 661 u32 mask_cache_priv;
660 u32 *mask_cache; 662 u32 *mask_cache;
661 }; 663 };
662 664
663 /** 665 /**
664 * struct irq_chip_generic - Generic irq chip data structure 666 * struct irq_chip_generic - Generic irq chip data structure
665 * @lock: Lock to protect register and cache data access 667 * @lock: Lock to protect register and cache data access
666 * @reg_base: Register base address (virtual) 668 * @reg_base: Register base address (virtual)
667 * @irq_base: Interrupt base nr for this chip 669 * @irq_base: Interrupt base nr for this chip
668 * @irq_cnt: Number of interrupts handled by this chip 670 * @irq_cnt: Number of interrupts handled by this chip
669 * @mask_cache: Cached mask register shared between all chip types 671 * @mask_cache: Cached mask register shared between all chip types
670 * @type_cache: Cached type register 672 * @type_cache: Cached type register
671 * @polarity_cache: Cached polarity register 673 * @polarity_cache: Cached polarity register
672 * @wake_enabled: Interrupt can wakeup from suspend 674 * @wake_enabled: Interrupt can wakeup from suspend
673 * @wake_active: Interrupt is marked as an wakeup from suspend source 675 * @wake_active: Interrupt is marked as an wakeup from suspend source
674 * @num_ct: Number of available irq_chip_type instances (usually 1) 676 * @num_ct: Number of available irq_chip_type instances (usually 1)
675 * @private: Private data for non generic chip callbacks 677 * @private: Private data for non generic chip callbacks
676 * @list: List head for keeping track of instances 678 * @list: List head for keeping track of instances
677 * @chip_types: Array of interrupt irq_chip_types 679 * @chip_types: Array of interrupt irq_chip_types
678 * 680 *
679 * Note, that irq_chip_generic can have multiple irq_chip_type 681 * Note, that irq_chip_generic can have multiple irq_chip_type
680 * implementations which can be associated to a particular irq line of 682 * implementations which can be associated to a particular irq line of
681 * an irq_chip_generic instance. That allows to share and protect 683 * an irq_chip_generic instance. That allows to share and protect
682 * state in an irq_chip_generic instance when we need to implement 684 * state in an irq_chip_generic instance when we need to implement
683 * different flow mechanisms (level/edge) for it. 685 * different flow mechanisms (level/edge) for it.
684 */ 686 */
685 struct irq_chip_generic { 687 struct irq_chip_generic {
686 raw_spinlock_t lock; 688 raw_spinlock_t lock;
687 void __iomem *reg_base; 689 void __iomem *reg_base;
688 unsigned int irq_base; 690 unsigned int irq_base;
689 unsigned int irq_cnt; 691 unsigned int irq_cnt;
690 u32 mask_cache; 692 u32 mask_cache;
691 u32 type_cache; 693 u32 type_cache;
692 u32 polarity_cache; 694 u32 polarity_cache;
693 u32 wake_enabled; 695 u32 wake_enabled;
694 u32 wake_active; 696 u32 wake_active;
695 unsigned int num_ct; 697 unsigned int num_ct;
696 void *private; 698 void *private;
697 struct list_head list; 699 struct list_head list;
698 struct irq_chip_type chip_types[0]; 700 struct irq_chip_type chip_types[0];
699 }; 701 };
700 702
701 /** 703 /**
702 * enum irq_gc_flags - Initialization flags for generic irq chips 704 * enum irq_gc_flags - Initialization flags for generic irq chips
703 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg 705 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
704 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for 706 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
705 * irq chips which need to call irq_set_wake() on 707 * irq chips which need to call irq_set_wake() on
706 * the parent irq. Usually GPIO implementations 708 * the parent irq. Usually GPIO implementations
707 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private 709 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
710 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
708 */ 711 */
709 enum irq_gc_flags { 712 enum irq_gc_flags {
710 IRQ_GC_INIT_MASK_CACHE = 1 << 0, 713 IRQ_GC_INIT_MASK_CACHE = 1 << 0,
711 IRQ_GC_INIT_NESTED_LOCK = 1 << 1, 714 IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
712 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2, 715 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
716 IRQ_GC_NO_MASK = 1 << 3,
713 }; 717 };
714 718
715 /* Generic chip callback functions */ 719 /* Generic chip callback functions */
716 void irq_gc_noop(struct irq_data *d); 720 void irq_gc_noop(struct irq_data *d);
717 void irq_gc_mask_disable_reg(struct irq_data *d); 721 void irq_gc_mask_disable_reg(struct irq_data *d);
718 void irq_gc_mask_set_bit(struct irq_data *d); 722 void irq_gc_mask_set_bit(struct irq_data *d);
719 void irq_gc_mask_clr_bit(struct irq_data *d); 723 void irq_gc_mask_clr_bit(struct irq_data *d);
720 void irq_gc_unmask_enable_reg(struct irq_data *d); 724 void irq_gc_unmask_enable_reg(struct irq_data *d);
721 void irq_gc_ack_set_bit(struct irq_data *d); 725 void irq_gc_ack_set_bit(struct irq_data *d);
722 void irq_gc_ack_clr_bit(struct irq_data *d); 726 void irq_gc_ack_clr_bit(struct irq_data *d);
723 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d); 727 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d);
724 void irq_gc_eoi(struct irq_data *d); 728 void irq_gc_eoi(struct irq_data *d);
725 int irq_gc_set_wake(struct irq_data *d, unsigned int on); 729 int irq_gc_set_wake(struct irq_data *d, unsigned int on);
726 730
727 /* Setup functions for irq_chip_generic */ 731 /* Setup functions for irq_chip_generic */
728 struct irq_chip_generic * 732 struct irq_chip_generic *
729 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, 733 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
730 void __iomem *reg_base, irq_flow_handler_t handler); 734 void __iomem *reg_base, irq_flow_handler_t handler);
731 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, 735 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
732 enum irq_gc_flags flags, unsigned int clr, 736 enum irq_gc_flags flags, unsigned int clr,
733 unsigned int set); 737 unsigned int set);
734 int irq_setup_alt_chip(struct irq_data *d, unsigned int type); 738 int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
735 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, 739 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
736 unsigned int clr, unsigned int set); 740 unsigned int clr, unsigned int set);
737 741
738 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) 742 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
739 { 743 {
740 return container_of(d->chip, struct irq_chip_type, chip); 744 return container_of(d->chip, struct irq_chip_type, chip);
741 } 745 }
742 746
743 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) 747 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
744 748
745 #ifdef CONFIG_SMP 749 #ifdef CONFIG_SMP
746 static inline void irq_gc_lock(struct irq_chip_generic *gc) 750 static inline void irq_gc_lock(struct irq_chip_generic *gc)
747 { 751 {
748 raw_spin_lock(&gc->lock); 752 raw_spin_lock(&gc->lock);
749 } 753 }
750 754
751 static inline void irq_gc_unlock(struct irq_chip_generic *gc) 755 static inline void irq_gc_unlock(struct irq_chip_generic *gc)
752 { 756 {
753 raw_spin_unlock(&gc->lock); 757 raw_spin_unlock(&gc->lock);
754 } 758 }
755 #else 759 #else
756 static inline void irq_gc_lock(struct irq_chip_generic *gc) { } 760 static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
757 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } 761 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
758 #endif 762 #endif
759 763
760 #else /* !CONFIG_GENERIC_HARDIRQS */ 764 #else /* !CONFIG_GENERIC_HARDIRQS */
761 765
762 extern struct msi_desc *irq_get_msi_desc(unsigned int irq); 766 extern struct msi_desc *irq_get_msi_desc(unsigned int irq);
763 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); 767 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
764 768
765 #endif /* CONFIG_GENERIC_HARDIRQS */ 769 #endif /* CONFIG_GENERIC_HARDIRQS */
766 770
767 #endif /* _LINUX_IRQ_H */ 771 #endif /* _LINUX_IRQ_H */
768 772
kernel/irq/generic-chip.c
Diff comments   View file @ 966dc73
1 /* 1 /*
2 * Library implementing the most common irq chip callback functions 2 * Library implementing the most common irq chip callback functions
3 * 3 *
4 * Copyright (C) 2011, Thomas Gleixner 4 * Copyright (C) 2011, Thomas Gleixner
5 */ 5 */
6 #include <linux/io.h> 6 #include <linux/io.h>
7 #include <linux/irq.h> 7 #include <linux/irq.h>
8 #include <linux/slab.h> 8 #include <linux/slab.h>
9 #include <linux/export.h> 9 #include <linux/export.h>
10 #include <linux/interrupt.h> 10 #include <linux/interrupt.h>
11 #include <linux/kernel_stat.h> 11 #include <linux/kernel_stat.h>
12 #include <linux/syscore_ops.h> 12 #include <linux/syscore_ops.h>
13 13
14 #include "internals.h" 14 #include "internals.h"
15 15
16 static LIST_HEAD(gc_list); 16 static LIST_HEAD(gc_list);
17 static DEFINE_RAW_SPINLOCK(gc_lock); 17 static DEFINE_RAW_SPINLOCK(gc_lock);
18 18
19 /** 19 /**
20 * irq_gc_noop - NOOP function 20 * irq_gc_noop - NOOP function
21 * @d: irq_data 21 * @d: irq_data
22 */ 22 */
23 void irq_gc_noop(struct irq_data *d) 23 void irq_gc_noop(struct irq_data *d)
24 { 24 {
25 } 25 }
26 26
27 /** 27 /**
28 * irq_gc_mask_disable_reg - Mask chip via disable register 28 * irq_gc_mask_disable_reg - Mask chip via disable register
29 * @d: irq_data 29 * @d: irq_data
30 * 30 *
31 * Chip has separate enable/disable registers instead of a single mask 31 * Chip has separate enable/disable registers instead of a single mask
32 * register. 32 * register.
33 */ 33 */
34 void irq_gc_mask_disable_reg(struct irq_data *d) 34 void irq_gc_mask_disable_reg(struct irq_data *d)
35 { 35 {
36 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 36 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
37 struct irq_chip_type *ct = irq_data_get_chip_type(d); 37 struct irq_chip_type *ct = irq_data_get_chip_type(d);
38 u32 mask = 1 << (d->irq - gc->irq_base); 38 u32 mask = d->mask;
39 39
40 irq_gc_lock(gc); 40 irq_gc_lock(gc);
41 irq_reg_writel(mask, gc->reg_base + ct->regs.disable); 41 irq_reg_writel(mask, gc->reg_base + ct->regs.disable);
42 *ct->mask_cache &= ~mask; 42 *ct->mask_cache &= ~mask;
43 irq_gc_unlock(gc); 43 irq_gc_unlock(gc);
44 } 44 }
45 45
46 /** 46 /**
47 * irq_gc_mask_set_mask_bit - Mask chip via setting bit in mask register 47 * irq_gc_mask_set_mask_bit - Mask chip via setting bit in mask register
48 * @d: irq_data 48 * @d: irq_data
49 * 49 *
50 * Chip has a single mask register. Values of this register are cached 50 * Chip has a single mask register. Values of this register are cached
51 * and protected by gc->lock 51 * and protected by gc->lock
52 */ 52 */
53 void irq_gc_mask_set_bit(struct irq_data *d) 53 void irq_gc_mask_set_bit(struct irq_data *d)
54 { 54 {
55 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 55 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
56 struct irq_chip_type *ct = irq_data_get_chip_type(d); 56 struct irq_chip_type *ct = irq_data_get_chip_type(d);
57 u32 mask = 1 << (d->irq - gc->irq_base); 57 u32 mask = d->mask;
58 58
59 irq_gc_lock(gc); 59 irq_gc_lock(gc);
60 *ct->mask_cache |= mask; 60 *ct->mask_cache |= mask;
61 irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask); 61 irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask);
62 irq_gc_unlock(gc); 62 irq_gc_unlock(gc);
63 } 63 }
64 64
65 /** 65 /**
66 * irq_gc_mask_set_mask_bit - Mask chip via clearing bit in mask register 66 * irq_gc_mask_set_mask_bit - Mask chip via clearing bit in mask register
67 * @d: irq_data 67 * @d: irq_data
68 * 68 *
69 * Chip has a single mask register. Values of this register are cached 69 * Chip has a single mask register. Values of this register are cached
70 * and protected by gc->lock 70 * and protected by gc->lock
71 */ 71 */
72 void irq_gc_mask_clr_bit(struct irq_data *d) 72 void irq_gc_mask_clr_bit(struct irq_data *d)
73 { 73 {
74 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 74 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
75 struct irq_chip_type *ct = irq_data_get_chip_type(d); 75 struct irq_chip_type *ct = irq_data_get_chip_type(d);
76 u32 mask = 1 << (d->irq - gc->irq_base); 76 u32 mask = d->mask;
77 77
78 irq_gc_lock(gc); 78 irq_gc_lock(gc);
79 *ct->mask_cache &= ~mask; 79 *ct->mask_cache &= ~mask;
80 irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask); 80 irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask);
81 irq_gc_unlock(gc); 81 irq_gc_unlock(gc);
82 } 82 }
83 83
84 /** 84 /**
85 * irq_gc_unmask_enable_reg - Unmask chip via enable register 85 * irq_gc_unmask_enable_reg - Unmask chip via enable register
86 * @d: irq_data 86 * @d: irq_data
87 * 87 *
88 * Chip has separate enable/disable registers instead of a single mask 88 * Chip has separate enable/disable registers instead of a single mask
89 * register. 89 * register.
90 */ 90 */
91 void irq_gc_unmask_enable_reg(struct irq_data *d) 91 void irq_gc_unmask_enable_reg(struct irq_data *d)
92 { 92 {
93 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 93 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
94 struct irq_chip_type *ct = irq_data_get_chip_type(d); 94 struct irq_chip_type *ct = irq_data_get_chip_type(d);
95 u32 mask = 1 << (d->irq - gc->irq_base); 95 u32 mask = d->mask;
96 96
97 irq_gc_lock(gc); 97 irq_gc_lock(gc);
98 irq_reg_writel(mask, gc->reg_base + ct->regs.enable); 98 irq_reg_writel(mask, gc->reg_base + ct->regs.enable);
99 *ct->mask_cache |= mask; 99 *ct->mask_cache |= mask;
100 irq_gc_unlock(gc); 100 irq_gc_unlock(gc);
101 } 101 }
102 102
103 /** 103 /**
104 * irq_gc_ack_set_bit - Ack pending interrupt via setting bit 104 * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
105 * @d: irq_data 105 * @d: irq_data
106 */ 106 */
107 void irq_gc_ack_set_bit(struct irq_data *d) 107 void irq_gc_ack_set_bit(struct irq_data *d)
108 { 108 {
109 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 109 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
110 struct irq_chip_type *ct = irq_data_get_chip_type(d); 110 struct irq_chip_type *ct = irq_data_get_chip_type(d);
111 u32 mask = 1 << (d->irq - gc->irq_base); 111 u32 mask = d->mask;
112 112
113 irq_gc_lock(gc); 113 irq_gc_lock(gc);
114 irq_reg_writel(mask, gc->reg_base + ct->regs.ack); 114 irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
115 irq_gc_unlock(gc); 115 irq_gc_unlock(gc);
116 } 116 }
117 117
118 /** 118 /**
119 * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit 119 * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
120 * @d: irq_data 120 * @d: irq_data
121 */ 121 */
122 void irq_gc_ack_clr_bit(struct irq_data *d) 122 void irq_gc_ack_clr_bit(struct irq_data *d)
123 { 123 {
124 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 124 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
125 struct irq_chip_type *ct = irq_data_get_chip_type(d); 125 struct irq_chip_type *ct = irq_data_get_chip_type(d);
126 u32 mask = ~(1 << (d->irq - gc->irq_base)); 126 u32 mask = ~d->mask;
127 127
128 irq_gc_lock(gc); 128 irq_gc_lock(gc);
129 irq_reg_writel(mask, gc->reg_base + ct->regs.ack); 129 irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
130 irq_gc_unlock(gc); 130 irq_gc_unlock(gc);
131 } 131 }
132 132
133 /** 133 /**
134 * irq_gc_mask_disable_reg_and_ack- Mask and ack pending interrupt 134 * irq_gc_mask_disable_reg_and_ack- Mask and ack pending interrupt
135 * @d: irq_data 135 * @d: irq_data
136 */ 136 */
137 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d) 137 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)
138 { 138 {
139 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 139 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
140 struct irq_chip_type *ct = irq_data_get_chip_type(d); 140 struct irq_chip_type *ct = irq_data_get_chip_type(d);
141 u32 mask = 1 << (d->irq - gc->irq_base); 141 u32 mask = d->mask;
142 142
143 irq_gc_lock(gc); 143 irq_gc_lock(gc);
144 irq_reg_writel(mask, gc->reg_base + ct->regs.mask); 144 irq_reg_writel(mask, gc->reg_base + ct->regs.mask);
145 irq_reg_writel(mask, gc->reg_base + ct->regs.ack); 145 irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
146 irq_gc_unlock(gc); 146 irq_gc_unlock(gc);
147 } 147 }
148 148
149 /** 149 /**
150 * irq_gc_eoi - EOI interrupt 150 * irq_gc_eoi - EOI interrupt
151 * @d: irq_data 151 * @d: irq_data
152 */ 152 */
153 void irq_gc_eoi(struct irq_data *d) 153 void irq_gc_eoi(struct irq_data *d)
154 { 154 {
155 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 155 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
156 struct irq_chip_type *ct = irq_data_get_chip_type(d); 156 struct irq_chip_type *ct = irq_data_get_chip_type(d);
157 u32 mask = 1 << (d->irq - gc->irq_base); 157 u32 mask = d->mask;
158 158
159 irq_gc_lock(gc); 159 irq_gc_lock(gc);
160 irq_reg_writel(mask, gc->reg_base + ct->regs.eoi); 160 irq_reg_writel(mask, gc->reg_base + ct->regs.eoi);
161 irq_gc_unlock(gc); 161 irq_gc_unlock(gc);
162 } 162 }
163 163
164 /** 164 /**
165 * irq_gc_set_wake - Set/clr wake bit for an interrupt 165 * irq_gc_set_wake - Set/clr wake bit for an interrupt
166 * @d: irq_data 166 * @d: irq_data
167 * 167 *
168 * For chips where the wake from suspend functionality is not 168 * For chips where the wake from suspend functionality is not
169 * configured in a separate register and the wakeup active state is 169 * configured in a separate register and the wakeup active state is
170 * just stored in a bitmask. 170 * just stored in a bitmask.
171 */ 171 */
172 int irq_gc_set_wake(struct irq_data *d, unsigned int on) 172 int irq_gc_set_wake(struct irq_data *d, unsigned int on)
173 { 173 {
174 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 174 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
175 u32 mask = 1 << (d->irq - gc->irq_base); 175 u32 mask = d->mask;
176 176
177 if (!(mask & gc->wake_enabled)) 177 if (!(mask & gc->wake_enabled))
178 return -EINVAL; 178 return -EINVAL;
179 179
180 irq_gc_lock(gc); 180 irq_gc_lock(gc);
181 if (on) 181 if (on)
182 gc->wake_active |= mask; 182 gc->wake_active |= mask;
183 else 183 else
184 gc->wake_active &= ~mask; 184 gc->wake_active &= ~mask;
185 irq_gc_unlock(gc); 185 irq_gc_unlock(gc);
186 return 0; 186 return 0;
187 } 187 }
188 188
189 /** 189 /**
190 * irq_alloc_generic_chip - Allocate a generic chip and initialize it 190 * irq_alloc_generic_chip - Allocate a generic chip and initialize it
191 * @name: Name of the irq chip 191 * @name: Name of the irq chip
192 * @num_ct: Number of irq_chip_type instances associated with this 192 * @num_ct: Number of irq_chip_type instances associated with this
193 * @irq_base: Interrupt base nr for this chip 193 * @irq_base: Interrupt base nr for this chip
194 * @reg_base: Register base address (virtual) 194 * @reg_base: Register base address (virtual)
195 * @handler: Default flow handler associated with this chip 195 * @handler: Default flow handler associated with this chip
196 * 196 *
197 * Returns an initialized irq_chip_generic structure. The chip defaults 197 * Returns an initialized irq_chip_generic structure. The chip defaults
198 * to the primary (index 0) irq_chip_type and @handler 198 * to the primary (index 0) irq_chip_type and @handler
199 */ 199 */
200 struct irq_chip_generic * 200 struct irq_chip_generic *
201 irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base, 201 irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
202 void __iomem *reg_base, irq_flow_handler_t handler) 202 void __iomem *reg_base, irq_flow_handler_t handler)
203 { 203 {
204 struct irq_chip_generic *gc; 204 struct irq_chip_generic *gc;
205 unsigned long sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type); 205 unsigned long sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
206 206
207 gc = kzalloc(sz, GFP_KERNEL); 207 gc = kzalloc(sz, GFP_KERNEL);
208 if (gc) { 208 if (gc) {
209 raw_spin_lock_init(&gc->lock); 209 raw_spin_lock_init(&gc->lock);
210 gc->num_ct = num_ct; 210 gc->num_ct = num_ct;
211 gc->irq_base = irq_base; 211 gc->irq_base = irq_base;
212 gc->reg_base = reg_base; 212 gc->reg_base = reg_base;
213 gc->chip_types->chip.name = name; 213 gc->chip_types->chip.name = name;
214 gc->chip_types->handler = handler; 214 gc->chip_types->handler = handler;
215 } 215 }
216 return gc; 216 return gc;
217 } 217 }
218 EXPORT_SYMBOL_GPL(irq_alloc_generic_chip); 218 EXPORT_SYMBOL_GPL(irq_alloc_generic_chip);
219 219
220 /* 220 /*
221 * Separate lockdep class for interrupt chip which can nest irq_desc 221 * Separate lockdep class for interrupt chip which can nest irq_desc
222 * lock. 222 * lock.
223 */ 223 */
224 static struct lock_class_key irq_nested_lock_class; 224 static struct lock_class_key irq_nested_lock_class;
225 225
226 /** 226 /**
227 * irq_setup_generic_chip - Setup a range of interrupts with a generic chip 227 * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
228 * @gc: Generic irq chip holding all data 228 * @gc: Generic irq chip holding all data
229 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base 229 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
230 * @flags: Flags for initialization 230 * @flags: Flags for initialization
231 * @clr: IRQ_* bits to clear 231 * @clr: IRQ_* bits to clear
232 * @set: IRQ_* bits to set 232 * @set: IRQ_* bits to set
233 * 233 *
234 * Set up max. 32 interrupts starting from gc->irq_base. Note, this 234 * Set up max. 32 interrupts starting from gc->irq_base. Note, this
235 * initializes all interrupts to the primary irq_chip_type and its 235 * initializes all interrupts to the primary irq_chip_type and its
236 * associated handler. 236 * associated handler.
237 */ 237 */
238 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, 238 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
239 enum irq_gc_flags flags, unsigned int clr, 239 enum irq_gc_flags flags, unsigned int clr,
240 unsigned int set) 240 unsigned int set)
241 { 241 {
242 struct irq_chip_type *ct = gc->chip_types; 242 struct irq_chip_type *ct = gc->chip_types;
243 unsigned int i; 243 unsigned int i;
244 u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask; 244 u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
245 245
246 raw_spin_lock(&gc_lock); 246 raw_spin_lock(&gc_lock);
247 list_add_tail(&gc->list, &gc_list); 247 list_add_tail(&gc->list, &gc_list);
248 raw_spin_unlock(&gc_lock); 248 raw_spin_unlock(&gc_lock);
249 249
250 for (i = 0; i < gc->num_ct; i++) { 250 for (i = 0; i < gc->num_ct; i++) {
251 if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) { 251 if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) {
252 mskptr = &ct[i].mask_cache_priv; 252 mskptr = &ct[i].mask_cache_priv;
253 mskreg = ct[i].regs.mask; 253 mskreg = ct[i].regs.mask;
254 } 254 }
255 ct[i].mask_cache = mskptr; 255 ct[i].mask_cache = mskptr;
256 if (flags & IRQ_GC_INIT_MASK_CACHE) 256 if (flags & IRQ_GC_INIT_MASK_CACHE)
257 *mskptr = irq_reg_readl(gc->reg_base + mskreg); 257 *mskptr = irq_reg_readl(gc->reg_base + mskreg);
258 } 258 }
259 259
260 for (i = gc->irq_base; msk; msk >>= 1, i++) { 260 for (i = gc->irq_base; msk; msk >>= 1, i++) {
261 if (!(msk & 0x01)) 261 if (!(msk & 0x01))
262 continue; 262 continue;
263 263
264 if (flags & IRQ_GC_INIT_NESTED_LOCK) 264 if (flags & IRQ_GC_INIT_NESTED_LOCK)
265 irq_set_lockdep_class(i, &irq_nested_lock_class); 265 irq_set_lockdep_class(i, &irq_nested_lock_class);
266 266
267 if (!(flags & IRQ_GC_NO_MASK)) {
268 struct irq_data *d = irq_get_irq_data(i);
269
270 d->mask = 1 << (i - gc->irq_base);
271 }
267 irq_set_chip_and_handler(i, &ct->chip, ct->handler); 272 irq_set_chip_and_handler(i, &ct->chip, ct->handler);
268 irq_set_chip_data(i, gc); 273 irq_set_chip_data(i, gc);
269 irq_modify_status(i, clr, set); 274 irq_modify_status(i, clr, set);
270 } 275 }
271 gc->irq_cnt = i - gc->irq_base; 276 gc->irq_cnt = i - gc->irq_base;
272 } 277 }
273 EXPORT_SYMBOL_GPL(irq_setup_generic_chip); 278 EXPORT_SYMBOL_GPL(irq_setup_generic_chip);
274 279
275 /** 280 /**
276 * irq_setup_alt_chip - Switch to alternative chip 281 * irq_setup_alt_chip - Switch to alternative chip
277 * @d: irq_data for this interrupt 282 * @d: irq_data for this interrupt
278 * @type Flow type to be initialized 283 * @type Flow type to be initialized
279 * 284 *
280 * Only to be called from chip->irq_set_type() callbacks. 285 * Only to be called from chip->irq_set_type() callbacks.
281 */ 286 */
282 int irq_setup_alt_chip(struct irq_data *d, unsigned int type) 287 int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
283 { 288 {
284 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 289 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
285 struct irq_chip_type *ct = gc->chip_types; 290 struct irq_chip_type *ct = gc->chip_types;
286 unsigned int i; 291 unsigned int i;
287 292
288 for (i = 0; i < gc->num_ct; i++, ct++) { 293 for (i = 0; i < gc->num_ct; i++, ct++) {
289 if (ct->type & type) { 294 if (ct->type & type) {
290 d->chip = &ct->chip; 295 d->chip = &ct->chip;
291 irq_data_to_desc(d)->handle_irq = ct->handler; 296 irq_data_to_desc(d)->handle_irq = ct->handler;
292 return 0; 297 return 0;
293 } 298 }
294 } 299 }
295 return -EINVAL; 300 return -EINVAL;
296 } 301 }
297 EXPORT_SYMBOL_GPL(irq_setup_alt_chip); 302 EXPORT_SYMBOL_GPL(irq_setup_alt_chip);
298 303
299 /** 304 /**
300 * irq_remove_generic_chip - Remove a chip 305 * irq_remove_generic_chip - Remove a chip
301 * @gc: Generic irq chip holding all data 306 * @gc: Generic irq chip holding all data
302 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base 307 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
303 * @clr: IRQ_* bits to clear 308 * @clr: IRQ_* bits to clear
304 * @set: IRQ_* bits to set 309 * @set: IRQ_* bits to set
305 * 310 *
306 * Remove up to 32 interrupts starting from gc->irq_base. 311 * Remove up to 32 interrupts starting from gc->irq_base.
307 */ 312 */
308 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, 313 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
309 unsigned int clr, unsigned int set) 314 unsigned int clr, unsigned int set)
310 { 315 {
311 unsigned int i = gc->irq_base; 316 unsigned int i = gc->irq_base;
312 317
313 raw_spin_lock(&gc_lock); 318 raw_spin_lock(&gc_lock);
314 list_del(&gc->list); 319 list_del(&gc->list);
315 raw_spin_unlock(&gc_lock); 320 raw_spin_unlock(&gc_lock);
316 321
317 for (; msk; msk >>= 1, i++) { 322 for (; msk; msk >>= 1, i++) {
318 if (!(msk & 0x01)) 323 if (!(msk & 0x01))
319 continue; 324 continue;
320 325
321 /* Remove handler first. That will mask the irq line */ 326 /* Remove handler first. That will mask the irq line */
322 irq_set_handler(i, NULL); 327 irq_set_handler(i, NULL);
323 irq_set_chip(i, &no_irq_chip); 328 irq_set_chip(i, &no_irq_chip);
324 irq_set_chip_data(i, NULL); 329 irq_set_chip_data(i, NULL);
325 irq_modify_status(i, clr, set); 330 irq_modify_status(i, clr, set);
326 } 331 }
327 } 332 }
328 EXPORT_SYMBOL_GPL(irq_remove_generic_chip); 333 EXPORT_SYMBOL_GPL(irq_remove_generic_chip);
329 334
330 #ifdef CONFIG_PM 335 #ifdef CONFIG_PM
331 static int irq_gc_suspend(void) 336 static int irq_gc_suspend(void)
332 { 337 {
333 struct irq_chip_generic *gc; 338 struct irq_chip_generic *gc;
334 339
335 list_for_each_entry(gc, &gc_list, list) { 340 list_for_each_entry(gc, &gc_list, list) {
336 struct irq_chip_type *ct = gc->chip_types; 341 struct irq_chip_type *ct = gc->chip_types;
337 342
338 if (ct->chip.irq_suspend) 343 if (ct->chip.irq_suspend)
339 ct->chip.irq_suspend(irq_get_irq_data(gc->irq_base)); 344 ct->chip.irq_suspend(irq_get_irq_data(gc->irq_base));
340 } 345 }
341 return 0; 346 return 0;
342 } 347 }
343 348
344 static void irq_gc_resume(void) 349 static void irq_gc_resume(void)
345 { 350 {
346 struct irq_chip_generic *gc; 351 struct irq_chip_generic *gc;
347 352
348 list_for_each_entry(gc, &gc_list, list) { 353 list_for_each_entry(gc, &gc_list, list) {
349 struct irq_chip_type *ct = gc->chip_types; 354 struct irq_chip_type *ct = gc->chip_types;
350 355
351 if (ct->chip.irq_resume) 356 if (ct->chip.irq_resume)
352 ct->chip.irq_resume(irq_get_irq_data(gc->irq_base)); 357 ct->chip.irq_resume(irq_get_irq_data(gc->irq_base));
353 } 358 }
354 } 359 }
355 #else 360 #else
356 #define irq_gc_suspend NULL 361 #define irq_gc_suspend NULL
357 #define irq_gc_resume NULL 362 #define irq_gc_resume NULL
358 #endif 363 #endif
359 364
360 static void irq_gc_shutdown(void) 365 static void irq_gc_shutdown(void)
361 { 366 {
362 struct irq_chip_generic *gc; 367 struct irq_chip_generic *gc;
363 368
364 list_for_each_entry(gc, &gc_list, list) { 369 list_for_each_entry(gc, &gc_list, list) {
365 struct irq_chip_type *ct = gc->chip_types; 370 struct irq_chip_type *ct = gc->chip_types;
366 371
367 if (ct->chip.irq_pm_shutdown) 372 if (ct->chip.irq_pm_shutdown)
368 ct->chip.irq_pm_shutdown(irq_get_irq_data(gc->irq_base)); 373 ct->chip.irq_pm_shutdown(irq_get_irq_data(gc->irq_base));
369 } 374 }
370 } 375 }
371 376
372 static struct syscore_ops irq_gc_syscore_ops = { 377 static struct syscore_ops irq_gc_syscore_ops = {
373 .suspend = irq_gc_suspend, 378 .suspend = irq_gc_suspend,
374 .resume = irq_gc_resume, 379 .resume = irq_gc_resume,
375 .shutdown = irq_gc_shutdown, 380 .shutdown = irq_gc_shutdown,
376 }; 381 };
377 382
378 static int __init irq_gc_init_ops(void) 383 static int __init irq_gc_init_ops(void)
379 { 384 {
380 register_syscore_ops(&irq_gc_syscore_ops); 385 register_syscore_ops(&irq_gc_syscore_ops);
381 return 0; 386 return 0;
382 } 387 }
383 device_initcall(irq_gc_init_ops); 388 device_initcall(irq_gc_init_ops);
384 389